use work.trb_net_std.all;
--Entity decalaration for clock generator
-entity trb_net16_active_apimbuf is
-
- generic (INIT_DEPTH : integer := 1; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 1; -- or the replyibuf
- FIFO_TO_INT_DEPTH : integer := 1; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
+entity trb_net16_apimbuf is
+
+ generic (
+ API_TYPE : integer range 0 to 1 := 1;
+ INIT_DEPTH : integer range 0 to 7 := 0;
+ REPLY_DEPTH : integer range 0 to 7 := 2;
+ FIFO_TO_INT_DEPTH : integer range 0 to 7 := 2;
+ FIFO_TO_APL_DEPTH : integer range 0 to 7 := 2;
+ FIFO_TERM_BUFFER_DEPTH : integer := 0
+ MULT_WIDTH : integer range 1 to 5 := 3;
+ DAT_CHANNEL : integer range 0 to 2**(MULT_WIDTH-1) := 0;
+ DATA_WIDTH : integer range 16 to 16 := 16;
+ NUM_WIDTH : integer range 2 to 2 := 2
+ );
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
-- Media direction port
MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
);
end entity;
-architecture trb_net16_active_apimbuf_arch of trb_net16_active_apimbuf is
+architecture trb_net16_apimbuf_arch of trb_net16_apimbuf is
component trb_net16_iobuf is
);
end component;
-component trb_net16_active_api is
-
- generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
-
+component trb_net16_base_api is
+ generic (
+ API_TYPE : integer := 1;
+ FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
+ -- for the direction to
+ -- internal world
+ FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ );
port(
-- Misc
-- Internal direction port
-- This is just a clone from trb_net_iobuf
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_INIT_READ_IN: in std_logic;
+ INT_MASTER_DATAREADY_OUT: out std_logic;
+ INT_MASTER_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_MASTER_READ_IN: in std_logic;
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
+ INT_MASTER_DATAREADY_IN: in std_logic;
+ INT_MASTER_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_MASTER_READ_OUT: out std_logic;
- INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
+ INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the SLAVE path)
+ INT_SLAVE_DATAREADY_OUT: out std_logic;
+ INT_SLAVE_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_IN: in std_logic;
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
+ INT_SLAVE_DATAREADY_IN: in std_logic;
+ INT_SLAVE_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_OUT: out std_logic;
-- Status and control port
STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0);
signal MED_REPLY_READ_OUT : std_logic;
-signal m_DATAREADY_OUT : std_logic_vector (1 downto 0);
-signal m_DATA_OUT : std_logic_vector (31 downto 0);
-signal m_PACKET_NUM_OUT: std_logic_vector (3 downto 0);
-signal m_READ_IN : std_logic_vector (1 downto 0);
+signal m_DATAREADY_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATA_OUT : std_logic_vector (BUS_WIDTH*2**MULT_WIDTH-1 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
+signal m_READ_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
-signal m_DATAREADY_IN : std_logic_vector (1 downto 0);
-signal m_DATA_IN : std_logic_vector (31 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (3 downto 0);
-signal m_READ_OUT : std_logic_vector (1 downto 0);
+signal m_DATAREADY_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATA_IN : std_logic_vector (BUS_WIDTH**MULT_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
+signal m_READ_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
begin
- m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
- m_DATA_OUT(15 downto 0) <= MED_INIT_DATA_OUT;
- m_DATA_OUT(31 downto 16) <= MED_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(1 downto 0) <= MED_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(3 downto 2) <= MED_REPLY_PACKET_NUM_OUT;
- MED_INIT_READ_IN <= m_READ_IN(0);
- MED_REPLY_READ_IN <= m_READ_IN(1);
-
- MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
- MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
- MED_INIT_DATA_IN <= m_DATA_IN(15 downto 0);
- MED_REPLY_DATA_IN <= m_DATA_IN(31 downto 16);
- MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(1 downto 0);
- MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(3 downto 2);
- m_READ_OUT(0) <= MED_INIT_READ_OUT;
- m_READ_OUT(1) <= MED_REPLY_READ_OUT;
-
+ --Connections for data channel
+ m_DATAREADY_OUT(DAT_CHANNEL*2) <= MED_DAT_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(DAT_CHANNEL*2+1) <= MED_DAT_REPLY_DATAREADY_OUT;
+ m_DATA_OUT((DAT_CHANNEL*2+1)*BUS_WIDTH-1 downto DAT_CHANNEL*BUS_WIDTH*2) <= MED_DAT_INIT_DATA_OUT;
+ m_DATA_OUT((DAT_CHANNEL*2+2)*BUS_WIDTH-1 downto (DAT_CHANNEL*2+1)*BUS_WIDTH) <= MED_DAT_REPLY_DATA_OUT;
+ m_PACKET_NUM_OUT(DAT_CHANNEL*NUM_WIDTH*2+1 downto DAT_CHANNEL*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT;
+ m_PACKET_NUM_OUT(DAT_CHANNEL*NUM_WIDTH*3+1 downto DAT_CHANNEL*NUM_WIDTH*3) <= MED_DAT_REPLY_PACKET_NUM_OUT;
+ MED_DAT_INIT_READ_IN <= m_READ_IN(DAT_CHANNEL*2);
+ MED_DAT_REPLY_READ_IN <= m_READ_IN(DAT_CHANNEL*2+1);
+
+ MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(DAT_CHANNEL*2);
+ MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(DAT_CHANNEL*2+1);
+ MED_DAT_INIT_DATA_IN <= m_DATA_IN((DAT_CHANNEL*2+1)*BUS_WIDTH-1 downto DAT_CHANNEL*BUS_WIDTH*2);
+ MED_DAT_REPLY_DATA_IN <= m_DATA_IN((DAT_CHANNEL*2+2)*BUS_WIDTH-1 downto (DAT_CHANNEL*2+1)*BUS_WIDTH);
+ MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(DAT_CHANNEL*NUM_WIDTH*2+1 downto DAT_CHANNEL*NUM_WIDTH*2);
+ MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(DAT_CHANNEL*NUM_WIDTH*3+1 downto DAT_CHANNEL*NUM_WIDTH*3);
+ m_READ_OUT(DAT_CHANNEL*2) <= MED_DAT_INIT_READ_OUT;
+ m_READ_OUT(DAT_CHANNEL*2+1) <= MED_DAT_REPLY_READ_OUT;
- ACTIVE_API: trb_net16_active_api
-
- generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH)
-
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
-
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
-
- -- Internal direction port
- -- connect via private signals
-
- INT_INIT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
- INT_INIT_DATA_OUT => apl_to_buf_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM,
- INT_INIT_READ_IN => apl_to_buf_INIT_READ,
-
- INT_INIT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
- INT_INIT_DATA_IN => buf_to_apl_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => buf_to_apl_INIT_READ,
-
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => apl_to_buf_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => apl_to_buf_REPLY_READ,
-
- INT_REPLY_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => buf_to_apl_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => buf_to_apl_REPLY_READ,
-
- -- Status and control port
- STAT_FIFO_TO_INT => api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => api_stat_fifo_to_apl
- );
+ gen_actapi: if API_TYPE = 1 generate
+ DAT_ACTIVE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 1,
+ FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
+ INT_MASTER_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_INIT_PACKET_NUM,
+ INT_MASTER_READ_IN => apl_to_buf_DAT_INIT_READ,
+ INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
+ INT_MASTER_DATA_IN => buf_to_apl_DAT_INIT_DATA,
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_INIT_PACKET_NUM,
+ INT_MASTER_READ_OUT => buf_to_apl_DAT_INIT_READ,
+ INT_SLAVE_HEADER_IN => '0',
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
+ INT_SLAVE_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_REPLY_PACKET_NUM,
+ INT_SLAVE_READ_IN => apl_to_buf_DAT_REPLY_READ,
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
+ INT_SLAVE_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_REPLY_PACKET_NUM,
+ INT_SLAVE_READ_OUT => buf_to_apl_DAT_REPLY_READ,
+ -- Status and control port
+ STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
+ STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
+ );
+ end generate;
+
+ gen_pasapi: if API_TYPE = 0 generate
+ DAT_PASSIVE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 0,
+ FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => (others => '0'),
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
+ INT_MASTER_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_REPLY_PACKET_NUM,
+ INT_MASTER_READ_IN => apl_to_buf_DAT_REPLY_READ,
+ INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
+ INT_MASTER_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_REPLY_PACKET_NUM,
+ INT_MASTER_READ_OUT => buf_to_apl_DAT_REPLY_READ,
+ INT_SLAVE_HEADER_IN => '0',
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
+ INT_SLAVE_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_INIT_PACKET_NUM,
+ INT_SLAVE_READ_IN => apl_to_buf_DAT_INIT_READ,
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
+ INT_SLAVE_DATA_IN => buf_to_apl_DAT_INIT_DATA,
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_INIT_PACKET_NUM,
+ INT_SLAVE_READ_OUT => buf_to_apl_DAT_INIT_READ,
+ -- Status and control port
+ STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
+ STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
+ );
+ end generate;
STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
STAT_api_control_signals(3) <= APL_WRITE_IN;
IOBUF: trb_net16_iobuf
- generic map (INIT_DEPTH => INIT_DEPTH,
- REPLY_DEPTH => REPLY_DEPTH)
+ generic map (INIT_DEPTH => DAT_INIT_DEPTH,
+ REPLY_DEPTH => DAT_REPLY_DEPTH)
port map (
-- Misc
entity trb_net16_base_api is
- generic (API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
- --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
- FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium
- FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path
- -- if set to 0, no buffer is used
+ generic (
+ API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium
+ FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering master path
+ -- if set to 0, no buffer is used
+ SBUF_VERSION : integer range 0 to 1 := 0
+ );
port(
-- Misc
APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
APL_GOT_TRM: out std_logic;
- APL_HOLD_TRM: in std_logic;
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0) -- My own address (temporary solution!!!)
+ APL_RELEASE_TRM: in std_logic;
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0)
-- Status and control port
);
end component;
---------------------------------------
TrbNetTerm: trb_net16_term
+ generic map(
+ SECURE_MODE => 0
+ )
port map(
CLK => CLK,
RESET => RESET,
INT_DATA_IN => INT_MASTER_DATA_IN,
INT_PACKET_NUM_IN => INT_MASTER_PACKET_NUM_IN,
INT_READ_OUT => INT_MASTER_READ_OUT,
- APL_HOLD_TRM => '0',
- APL_DTYPE_IN => (others => '0'),
- APL_ERROR_PATTERN_IN => (others => '0'),
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN);
+ APL_RELEASE_TRM => '1',
+ APL_ERROR_PATTERN_IN => (others => '0')
+ );
---------------------------------------
-- fifo to internal
generic map (
DATA_WIDTH => 16,
NUM_WIDTH => 2,
- VERSION => 0)
+ VERSION => SBUF_VERSION)
port map (
CLK => CLK,
RESET => RESET,
when HDR => next_INT_MASTER_DATA_OUT <= current_combined_header;
when TRM => next_INT_MASTER_DATA_OUT <= current_registered_trailer;
when TRM_COMB => next_INT_MASTER_DATA_OUT <= current_combined_trailer;
- when DAT => next_INT_MASTER_DATA_OUT <= current_data;
- when others => next_INT_MASTER_DATA_OUT <= current_data;
+ when others => next_INT_MASTER_DATA_OUT <= current_data;
end case;
end process;
-------------------------------------------------------------------------------
if current_state = IDLE then
if APL_SEND_IN = '1' then
- if APL_SHORT_TRANSFER_IN = '1' and APL_WRITE_IN = '0' and fifo_to_int_empty = '1' then
+ if APL_SHORT_TRANSFER_IN = '1' then -- and APL_WRITE_IN = '0' and fifo_to_int_empty = '1'
next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN
update_registered_trailer <= '1'; -- moved from SEND_SHORT
else -- normal transfer, prepare the header
next_state <= SHUTDOWN;
if sbuf_free = '1' then
fifo_to_int_read <= '1';
- if fifo_to_int_empty = '0' then
- -- data words have to be prepared
- next_INT_MASTER_DATAREADY_OUT <= '1';
- else
- -- we are done
- --implicit: fill with padding words
- if master_counter = "00" then
- next_state <= SEND_TRAILER;
- out_select <= TRM;
- end if;
- next_INT_MASTER_DATAREADY_OUT <= '1';
+ next_INT_MASTER_DATAREADY_OUT <= '1';
+ -- we are done
+ --implicit: fill with padding words
+ if master_counter = "00" and fifo_to_int_empty = '1' then
+ next_state <= SEND_TRAILER;
+ out_select <= TRM;
end if;
end if;
-------------------------------------------------------------------------------
elsif current_state = WAITING then
next_state <= WAITING;
-- here we have to supply the receiver port
- -- part 1: connection to network
+ -- part 1: connection to network
if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then
next_INT_SLAVE_READ_OUT <= '1';
end if;
reg_APL_DATA_OUT <= (others => '0');
reg_APL_PACKET_NUM_OUT <= (others => '0');
reg_APL_TYP_OUT <= (others => '0');
- else
+ elsif CLK_EN = '1' then
reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
reg_APL_DATA_OUT <= next_APL_DATA_OUT;
reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT;
registered_trailer_F1 <= combined_trailer_F1;
registered_trailer_F2 <= combined_trailer_F2;
registered_trailer_F3 <= combined_trailer_F3;
- else
- registered_trailer_F1 <= registered_trailer_F1;
- registered_trailer_F2 <= registered_trailer_F2;
- registered_trailer_F3 <= registered_trailer_F3;
end if;
end if;
end process;
entity trb_net16_ibuf is
generic (
- DEPTH : integer := 1
+ DEPTH : integer range 0 to 7 := 1;
+ SBUF_VERSION : integer range 0 to 1 := 0
);
port(
-- Misc
signal tmp_INT_PACKET_NUM_OUT: std_logic_vector(1 downto 0);
signal current_last_header, next_last_header : std_logic_vector(47 downto 0);
--last_header does not contain the TYPE_HDR, only packets 1 to 3 are stored.
-
+ signal current_last_header_F1, current_last_header_F2, current_last_header_F3 : std_logic_vector(15 downto 0);
+ signal next_last_header_F1, next_last_header_F2, next_last_header_F3 : std_logic_vector(15 downto 0);
+ signal reading_header : std_logic;
+
type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_LOCKED_ERROR, GOT_UNDEFINED_ERROR);
signal current_error_state, next_error_state : ERROR_STATE;
signal next_rec_buffer_size_out, current_rec_buffer_size_out: std_logic_vector(3 downto 0);
SBUF: trb_net16_sbuf
- generic map (DATA_WIDTH => 16, NUM_WIDTH => 2, Version => 0)
+ generic map (DATA_WIDTH => 16, NUM_WIDTH => 2, Version => SBUF_VERSION)
port map (
CLK => CLK,
RESET => RESET,
-- this process controls what will be forwarded to the internal point
DATA_OUT : process (INT_HEADER_IN, fifo_data_out,
- current_last_header, INT_READ_IN,
release_locked, is_locked, sbuf_free, fifo_empty,
fifo_packet_num_out, current_fifo_packet_type)
begin
tmp_INT_DATAREADY_OUT <= '0';
got_eob_out <= '0';
got_locked <= is_locked;
- next_last_header <= current_last_header;
- if fifo_empty = '0' and (sbuf_free = '1' or current_fifo_packet_type = TYPE_EOB) then
- fifo_read <= '1';
- else
- fifo_read <= '0';
+ fifo_read <= sbuf_free and not fifo_empty;
+ if current_fifo_packet_type = TYPE_EOB and fifo_packet_num_out = "00" then
+ tmp_INT_DATA_OUT(2 downto 0) <= TYPE_DAT;
end if;
- if fifo_empty = '0' then
- if sbuf_free = '1' then
- tmp_INT_DATAREADY_OUT <= '1';
- if current_fifo_packet_type = TYPE_TRM then
- if fifo_packet_num_out = "11" then
- got_eob_out <= '1'; --exactly when buffer is killed
- end if;
- got_locked <= is_locked or not release_locked;
- end if;
- end if;
- if current_fifo_packet_type = TYPE_EOB then
- tmp_INT_DATAREADY_OUT <= '0';
- if fifo_packet_num_out = "11" then
- got_eob_out <= '1';
- end if;
+ if fifo_empty = '0' and sbuf_free = '1' then
+ tmp_INT_DATAREADY_OUT <= '1';
+ if (current_fifo_packet_type = TYPE_EOB or current_fifo_packet_type = TYPE_TRM)
+ and fifo_packet_num_out = "11" then
+ got_eob_out <= '1';
end if;
- if current_fifo_packet_type = TYPE_HDR then
- if fifo_packet_num_out = "01" then
- next_last_header(47 downto 32) <= fifo_data_out;
- elsif fifo_packet_num_out = "10" then
- next_last_header(31 downto 16) <= fifo_data_out;
- else
- next_last_header(15 downto 0) <= fifo_data_out;
- end if;
+ if current_fifo_packet_type = TYPE_TRM then
+ got_locked <= is_locked or not release_locked;
end if;
end if;
+
+
end process;
--BUGBUG HDR retransmit needed
if RESET = '1' then
is_locked <= '0';
reg_eob_out <= '0';
- current_last_header <= (others => '0');
elsif CLK_EN = '1' then
is_locked <= got_locked and not release_locked;
reg_eob_out <= got_eob_out;
- current_last_header <= next_last_header;
else
is_locked <= is_locked;
reg_eob_out <= reg_eob_out;
- current_last_header <= current_last_header;
end if;
end if;
end process;
+--saving last HDR
+ reading_header <= '1' when (current_fifo_packet_type = TYPE_HDR and fifo_empty = '0') else '0';
+ reg_hdr_f1: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '0' then
+ current_last_header_F1 <= (others => '0');
+ elsif reading_header = '1' and fifo_packet_num_out = "01" then
+ current_last_header_F1 <= fifo_data_out;
+ end if;
+ end if;
+ end process;
+ reg_hdr_f2: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '0' then
+ current_last_header_F2 <= (others => '0');
+ elsif reading_header = '1' and fifo_packet_num_out = "10" then
+ current_last_header_F2 <= fifo_data_out;
+ end if;
+ end if;
+ end process;
+ reg_hdr_f3: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '0' then
+ current_last_header_F3 <= (others => '0');
+ elsif reading_header = '1' and fifo_packet_num_out = "11" then
+ current_last_header_F3 <= fifo_data_out;
+ end if;
+ end if;
+ end process;
-- make STAT_BUFFER
entity trb_net16_io_multiplexer is
generic (BUS_WIDTH : integer := 16;
- MULT_WIDTH : integer range 1 to 5 := 1);
+ MULT_WIDTH : integer range 1 to 5 := 3);
port(
-- Misc
);
end component;
- component trb_net_sbuf is
- generic (DATA_WIDTH : integer := 18;
- VERSION: integer := 0);
+ component trb_net16_sbuf is
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ VERSION : integer := 0
+ );
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
-- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
+ COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word
COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ COMB_READ_IN : in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
-- Port to synchronous output.
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
+ SYN_DATAREADY_OUT : out STD_LOGIC;
+ SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
+ SYN_READ_IN : in STD_LOGIC;
-- Status and control port
- STAT_BUFFER: out STD_LOGIC
+ STAT_BUFFER : out STD_LOGIC
);
end component;
component trb_net_priority_arbiter is
- generic (WIDTH : integer := 16);
+ generic (WIDTH : integer := 2**MULT_WIDTH);
port(
-- Misc
CLK : in std_logic;
-- DEMUX
------------------------------------------------------------------------------
- demux_sbuf_data_in(BUS_WIDTH-1 downto 0) <= MED_DATA_IN (BUS_WIDTH-1 downto 0);
- demux_sbuf_data_in(BUS_WIDTH+1 downto BUS_WIDTH) <= MED_PACKET_NUM_IN;
-
G1: for i in 0 to 2**MULT_WIDTH-1 generate
- DEMUX_SBUF: trb_net_sbuf
+ DEMUX_SBUF: trb_net16_sbuf
generic map (DATA_WIDTH => BUS_WIDTH+2, VERSION => 0)
port map (
CLK => CLK,
COMB_DATAREADY_IN => next_demux_dr(i),
COMB_next_READ_OUT => demux_next_READ(i),
COMB_READ_IN => current_demux_READ(i),
- COMB_DATA_IN => demux_sbuf_data_in((BUS_WIDTH+2)-1 downto 0),
+ COMB_DATA_IN => MED_DATA_IN,
+ COMB_PACKET_NUM_IN => MED_PACKET_NUM_IN,
SYN_DATAREADY_OUT => INT_DATAREADY_OUT(i),
- SYN_DATA_OUT => demux_sbuf_data_out((BUS_WIDTH+2)*(i+1)-1 downto (BUS_WIDTH+2)*(i)),
+ SYN_DATA_OUT => INT_DATA_OUT ((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)),
+ SYN_PACKET_NUM_OUT => INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i),
SYN_READ_IN => INT_READ_IN(i)
);
- INT_DATA_OUT ((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i)) <= demux_sbuf_data_out((BUS_WIDTH+2)*(i+1)-3 downto (BUS_WIDTH+2)*i);
- INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= demux_sbuf_data_out((BUS_WIDTH+2)*(i+1)-1 downto (BUS_WIDTH+2)*(i+1)-2);
end generate;
MED_READ_OUT <= current_MED_READ_OUT;
end process;
- MUX_SBUF: trb_net_sbuf
+ MUX_SBUF: trb_net16_sbuf
generic map (DATA_WIDTH => BUS_WIDTH+2, VERSION => 0)
port map (
CLK => CLK,
COMB_DATAREADY_IN => mux_read,
COMB_next_READ_OUT => mux_next_READ,
COMB_READ_IN => '1',
- COMB_DATA_IN => current_mux_buffer,
+ COMB_DATA_IN => current_mux_buffer(BUS_WIDTH-1 downto 0),
+ COMB_PACKET_NUM_IN => current_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH),
SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
- SYN_DATA_OUT => MUX_SBUF_data_out,
+ SYN_DATA_OUT => MED_DATA_OUT,
+ SYN_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
SYN_READ_IN => MED_READ_IN
);
-
-MED_DATA_OUT <= MUX_SBUF_data_out(BUS_WIDTH-1 downto 0);
-MED_PACKET_NUM_OUT <= MUX_SBUF_data_out(BUS_WIDTH+1 downto BUS_WIDTH);
-
---this process is easier to implement without implicit priority -> use an OR of all possibilities
--- process (tmp_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN)
--- begin
--- current_mux_buffer <= (others => '0');
--- for i in 0 to 2**MULT_WIDTH-1 loop
--- if tmp_INT_READ_OUT(i) = '1' then
--- current_mux_buffer(BUS_WIDTH-1 downto 0)
--- <= INT_DATA_IN((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i));
--- current_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) <= INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i);
--- if INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i) = "00" then
--- current_mux_buffer(3+MULT_WIDTH-1 downto 3) <= conv_std_logic_vector(i, MULT_WIDTH);
--- end if;
--- end if;
--- end loop;
--- end process;
-
- process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN)
- variable var_mux_buffer : STD_LOGIC_VECTOR (BUS_WIDTH+2-1 downto 0);
- begin
- var_mux_buffer := (others => '0');
- for i in 0 to 2**MULT_WIDTH-1 loop
- if current_INT_READ_OUT(i) = '1' then
- var_mux_buffer(BUS_WIDTH-1 downto 0)
- := var_mux_buffer(BUS_WIDTH-1 downto 0) or INT_DATA_IN((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i));
- var_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH)
- := var_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) or INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i);
- if INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i) = "00" then
- var_mux_buffer(3+MULT_WIDTH-1 downto 3)
- := conv_std_logic_vector(i, MULT_WIDTH);
+ genmux : if MULT_WIDTH /= 3 generate
+ process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN)
+ variable var_mux_buffer : STD_LOGIC_VECTOR (BUS_WIDTH+2-1 downto 0);
+ begin
+ var_mux_buffer := (others => '0');
+ for i in 0 to 2**MULT_WIDTH-1 loop
+ if current_INT_READ_OUT(i) = '1' then
+ var_mux_buffer(BUS_WIDTH-1 downto 0)
+ := var_mux_buffer(BUS_WIDTH-1 downto 0) or INT_DATA_IN((BUS_WIDTH)*(i+1)-1 downto (BUS_WIDTH)*(i));
+ var_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH)
+ := var_mux_buffer(BUS_WIDTH+1 downto BUS_WIDTH) or INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i);
+ if INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i) = "00" then
+ var_mux_buffer(3+MULT_WIDTH-1 downto 3)
+ := conv_std_logic_vector(i, MULT_WIDTH);
+ end if;
end if;
- end if;
- end loop;
- current_mux_buffer <= var_mux_buffer;
- end process;
-
+ end loop;
+ current_mux_buffer <= var_mux_buffer;
+ end process;
+ end generate;
+ genmux3: if MULT_WIDTH = 3 generate
+ process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN)
+ variable var_mux_buffer : STD_LOGIC_VECTOR (BUS_WIDTH+2-1 downto 0);
+ begin
+ for i in 0 to BUS_WIDTH-1 loop
+ current_mux_buffer(i) <= (INT_DATA_IN((BUS_WIDTH)*(0)+i) and current_INT_READ_OUT(0)) or
+ (INT_DATA_IN((BUS_WIDTH)*(1)+i) and current_INT_READ_OUT(1)) or
+ (INT_DATA_IN((BUS_WIDTH)*(2)+i) and current_INT_READ_OUT(2)) or
+ (INT_DATA_IN((BUS_WIDTH)*(3)+i) and current_INT_READ_OUT(3)) or
+ (INT_DATA_IN((BUS_WIDTH)*(4)+i) and current_INT_READ_OUT(4)) or
+ (INT_DATA_IN((BUS_WIDTH)*(5)+i) and current_INT_READ_OUT(5)) or
+ (INT_DATA_IN((BUS_WIDTH)*(6)+i) and current_INT_READ_OUT(6)) or
+ (INT_DATA_IN((BUS_WIDTH)*(7)+i) and current_INT_READ_OUT(7));
+ end loop;
+ current_mux_buffer(BUS_WIDTH) <= (INT_PACKET_NUM_IN(0) and current_INT_READ_OUT(0)) or
+ (INT_PACKET_NUM_IN(2) and current_INT_READ_OUT(1)) or
+ (INT_PACKET_NUM_IN(4) and current_INT_READ_OUT(2)) or
+ (INT_PACKET_NUM_IN(6) and current_INT_READ_OUT(3)) or
+ (INT_PACKET_NUM_IN(8) and current_INT_READ_OUT(4)) or
+ (INT_PACKET_NUM_IN(10) and current_INT_READ_OUT(5)) or
+ (INT_PACKET_NUM_IN(12) and current_INT_READ_OUT(6)) or
+ (INT_PACKET_NUM_IN(14) and current_INT_READ_OUT(7));
+ current_mux_buffer(BUS_WIDTH+1) <= (INT_PACKET_NUM_IN(1) and current_INT_READ_OUT(0)) or
+ (INT_PACKET_NUM_IN(3) and current_INT_READ_OUT(1)) or
+ (INT_PACKET_NUM_IN(5) and current_INT_READ_OUT(2)) or
+ (INT_PACKET_NUM_IN(7) and current_INT_READ_OUT(3)) or
+ (INT_PACKET_NUM_IN(9) and current_INT_READ_OUT(4)) or
+ (INT_PACKET_NUM_IN(11) and current_INT_READ_OUT(5)) or
+ (INT_PACKET_NUM_IN(13) and current_INT_READ_OUT(6)) or
+ (INT_PACKET_NUM_IN(15) and current_INT_READ_OUT(7));
+
+ end process;
+ end generate;
+
mux_enable <= (mux_next_READ); -- or MED_READ_IN
mux_read <= or_all(current_INT_READ_OUT and INT_DATAREADY_IN);
signal next_INIT_IS_LOCKED, next_REPLY_IS_LOCKED: STD_LOGIC;
begin
- GEN_IBUF: if INIT_DEPTH>0 generate
+ GEN_INIT_IBUF: if INIT_DEPTH>0 generate
INITIBUF : trb_net16_ibuf
generic map (
DEPTH => INIT_DEPTH)
CTRL_LOCKED(15 downto 0) => INITIBUF_ctrl_locked,
STAT_BUFFER(31 downto 0) => INITIBUF_stat_buffer
);
+ end generate;
+
+ GEN_REPLY_IBUF : if REPLY_DEPTH > 0 generate
REPLYIBUF : trb_net16_ibuf
generic map (
DEPTH => REPLY_DEPTH)
);
end generate;
- GEN_TERM_IBUF: if INIT_DEPTH=0 generate
+ GEN_TERM_INIT_IBUF: if INIT_DEPTH=0 generate
INITIBUF : trb_net16_term_ibuf
port map (
CLK => CLK,
CTRL_LOCKED(15 downto 0) => INITIBUF_ctrl_locked,
STAT_BUFFER(31 downto 0) => INITIBUF_stat_buffer
);
+ end generate;
+
+ GEN_TERM_REPLY_IBUF: if REPLY_DEPTH=0 generate
REPLYIBUF : trb_net16_term_ibuf
port map (
CLK => CLK,
begin
current_NOP_word <= (others => '0');
current_ACK_word <= (others => '0');
- current_EOB_word <= (others => '0');
+ current_EOB_word <= INT_DATA_IN;
current_DATA_word <= INT_DATA_IN;
if transfer_counter = "10" then
current_ACK_word(3 downto 0) <= SEND_BUFFER_SIZE_IN;
if transfer_counter = "00" then
current_NOP_word(2 downto 0) <= TYPE_ILLEGAL;
current_ACK_word(2 downto 0) <= TYPE_ACK;
- current_EOB_word(2 downto 0) <= TYPE_EOB;
+ current_EOB_word(2 downto 0) <= TYPE_EOB or INT_DATA_IN(2 downto 0);
+ --this makes an EOB out of an DAT and keeps a TRM
end if;
end process;
next_INT_READ_OUT <= '1';
increase_TRANSMITTED_BUFFERS <= '0';
next_DATA_COUNT <= CURRENT_DATA_COUNT;
- next_SEND_ACK_IN <= send_ACK;
+ next_SEND_ACK_IN <= send_ACK; --BUGBUG: next_SEND_ACK_IN should be a counter (2 may arrive)
+ -- -> no real problem due to same speed of transmission
+
comb_dataready <= '0';
- if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
+ if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
--can only happen if idle or sending_data
- current_output_data_buffer <= current_DATA_word;
+ if send_EOB = '0' then
+ current_output_data_buffer <= current_DATA_word;
+ else
+ current_output_data_buffer <= current_EOB_word;
+ end if;
comb_dataready <= '1'; --I hope sbuf can store
if transfer_counter = "11" then
- if saved_packet_type = TYPE_TRM then --TRM means EOB
+ if saved_packet_type = TYPE_TRM or saved_packet_type = TYPE_EOB then --TRM means EOB
next_DATA_COUNT <= (others => '0');
increase_TRANSMITTED_BUFFERS <= '1';
else
next_DATA_COUNT <= CURRENT_DATA_COUNT +1;
end if;
- if (send_ACK = '1' or send_EOB = '1' ) then
+ if (send_ACK = '1') then
next_INT_READ_OUT <= '0';
end if;
end if;
- if send_ACK = '1' then --BUGBUG: next_SEND_ACK_IN should be a counter (2 may arrive)
- --no real problem due to same speed of transmission
- next_SEND_ACK_IN <= '1';
- end if;
elsif (send_ACK = '1') then
- next_INT_READ_OUT <= '0';
+ next_INT_READ_OUT <= '0';
current_output_data_buffer <= current_ACK_word;
if sbuf_free = '1' then
- comb_dataready <= '1';
+ comb_dataready <= '1';
if (transfer_counter = "11") then
- next_SEND_ACK_IN <= '0';
- end if;
- end if;
- elsif send_EOB = '1' then
- next_INT_READ_OUT <= '0';
- current_output_data_buffer <= current_EOB_word;
- if sbuf_free = '1' then
- comb_dataready <= '1';
- if (transfer_counter = "11") then
- next_DATA_COUNT <= (others => '0');
- increase_TRANSMITTED_BUFFERS <= '1';
+ next_SEND_ACK_IN <= '0';
end if;
end if;
end if;
- if --block reading if two buffers have been sent or current buffer runs full
- ((current_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = (max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0)))
- and reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1' and transfer_counter = "11")
- --long version of (next_count = max_count-1)
- or (next_TRANSMITTED_BUFFERS(1) = '1')
- or sbuf_free = '0' then
- next_INT_READ_OUT <= '0';
+ if next_TRANSMITTED_BUFFERS(1) = '1' or sbuf_free = '0' then
+ next_INT_READ_OUT <= '0';
end if;
+------------
+--old
+-- if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
+-- --can only happen if idle or sending_data
+-- current_output_data_buffer <= current_DATA_word;
+-- comb_dataready <= '1'; --I hope sbuf can store
+-- if transfer_counter = "11" then
+-- if saved_packet_type = TYPE_TRM then --TRM means EOB
+-- next_DATA_COUNT <= (others => '0');
+-- increase_TRANSMITTED_BUFFERS <= '1';
+-- else
+-- next_DATA_COUNT <= CURRENT_DATA_COUNT +1;
+-- end if;
+-- if (send_ACK = '1' or send_EOB = '1' ) then
+-- next_INT_READ_OUT <= '0';
+-- end if;
+-- end if;
+-- if send_ACK = '1' then --BUGBUG: next_SEND_ACK_IN should be a counter (2 may arrive)
+-- --no real problem due to same speed of transmission
+-- next_SEND_ACK_IN <= '1';
+-- end if;
+-- elsif (send_ACK = '1') then
+-- next_INT_READ_OUT <= '0';
+-- current_output_data_buffer <= current_ACK_word;
+-- if sbuf_free = '1' then
+-- comb_dataready <= '1';
+-- if (transfer_counter = "11") then
+-- next_SEND_ACK_IN <= '0';
+-- end if;
+-- end if;
+-- elsif send_EOB = '1' then
+-- next_INT_READ_OUT <= '0';
+-- current_output_data_buffer <= current_EOB_word;
+-- if sbuf_free = '1' then
+-- comb_dataready <= '1';
+-- if (transfer_counter = "11") then
+-- next_DATA_COUNT <= (others => '0');
+-- increase_TRANSMITTED_BUFFERS <= '1';
+-- end if;
+-- end if;
+-- end if;
+-- if --block reading if two buffers have been sent or current buffer runs full
+-- ((current_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = (max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0)))
+-- and reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1' and transfer_counter = "11")
+-- --long version of (next_count = max_count-1)
+-- or (next_TRANSMITTED_BUFFERS(1) = '1')
+-- or sbuf_free = '0' then
+-- next_INT_READ_OUT <= '0';
+-- end if;
+
+--end old
+----------
end process;
"11111" when REC_BUFFER_SIZE_IN="0100" else
"00001";
next_max_DATA_COUNT_minus_two(0) <= '0';
- next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 1)
- <= next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 1);
+-- next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 1)
+-- <= next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 1);
-- next_max_DATA_COUNT_minus_one <= "0000000000000011" when REC_BUFFER_SIZE_IN="0001" else
-- "0000000000000111" when REC_BUFFER_SIZE_IN="0010" else
if RESET = '1' then
max_DATA_COUNT_minus_one(0) <= '1';
max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 1) <= (others => '0');
- max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0) <= (others => '0');
+-- max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0) <= (others => '0');
else
max_DATA_COUNT_minus_one <= next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0);
- max_DATA_COUNT_minus_two <= next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0);
+-- max_DATA_COUNT_minus_two <= next_max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0);
end if;
end if;
end process;
+++ /dev/null
--- an passive api together with an iobuf
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net16_passive_apimbuf is
-
- generic (INIT_DEPTH : integer := 1; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 1; -- or the replyibuf
- FIFO_TO_INT_DEPTH : integer := 1; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_READ_IN: in std_logic; -- Media is reading
-
- MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
-
- -- APL Transmitter port
- APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in std_logic; --
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL_READ_IN: in std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- STAT_api_control_signals: out std_logic_vector(31 downto 0);
- STAT_MPLEX: out std_logic_vector(31 downto 0);
- CTRL_GEN: in std_logic_vector (31 downto 0);
- CTRL_LOCKED: in std_logic_vector (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
- MPLEX_CTRL: in std_logic_vector (31 downto 0);
- API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-end entity;
-
-architecture trb_net16_passive_apimbuf_arch of trb_net16_passive_apimbuf is
-
-component trb_net16_iobuf is
-
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
- -- the initibuf
- REPLY_DEPTH : integer := 3); -- or the replyibuf
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_INIT_READ_IN: in std_logic; -- Media is reading
-
- MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_REPLY_READ_IN: in std_logic; -- Media is reading
-
- MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
- INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- CTRL_GEN: in std_logic_vector (31 downto 0);
- CTRL_LOCKED: in std_logic_vector (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
- );
-end component;
-
-component trb_net16_passive_api is
-
- generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1),
- -- for the direction to
- -- internal world
- FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of
- -- the master path, if set to 0
- -- no buffer is used at all
-
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in std_logic; --
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL_READ_IN: in std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
-
- INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-end component;
-
-
-
-component trb_net16_io_multiplexer is
-
- generic (BUS_WIDTH : integer := 16;
- MULT_WIDTH : integer := 1);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (BUS_WIDTH-1 downto 0);
- -- highest bits are mult.
- MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_READ_OUT: out std_logic;
-
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (BUS_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_READ_IN: in std_logic;
-
- -- Internal direction port
- INT_DATAREADY_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
- INT_DATA_OUT: out std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
-
- INT_DATAREADY_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
- INT_DATA_IN: in std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
- INT_READ_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in std_logic_vector (31 downto 0);
- STAT: out std_logic_vector (31 downto 0)
- );
-end component;
-
-signal apl_to_buf_INIT_DATAREADY: std_logic;
-signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0);
-signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
-signal apl_to_buf_INIT_READ : std_logic;
-
-signal buf_to_apl_INIT_DATAREADY: std_logic;
-signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0);
-signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
-signal buf_to_apl_INIT_READ : std_logic;
-
-signal apl_to_buf_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0);
-signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
-signal apl_to_buf_REPLY_READ : std_logic;
-
-signal buf_to_apl_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0);
-signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
-signal buf_to_apl_REPLY_READ : std_logic;
-
--- for the connection to the multiplexer
-signal MED_INIT_DATAREADY_OUT : std_logic;
-signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0);
-signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
-signal MED_INIT_READ_IN : std_logic;
-
-signal MED_INIT_DATAREADY_IN : std_logic;
-signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0);
-signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0);
-signal MED_INIT_READ_OUT : std_logic;
-
-signal MED_REPLY_DATAREADY_OUT : std_logic;
-signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0);
-signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
-signal MED_REPLY_READ_IN : std_logic;
-
-signal MED_REPLY_DATAREADY_IN : std_logic;
-signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0);
-signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0);
-signal MED_REPLY_READ_OUT : std_logic;
-
-signal m_DATAREADY_OUT : std_logic_vector (1 downto 0);
-signal m_DATA_OUT : std_logic_vector (31 downto 0);
-signal m_PACKET_NUM_OUT: std_logic_vector (3 downto 0);
-signal m_READ_IN : std_logic_vector (1 downto 0);
-
-signal m_DATAREADY_IN : std_logic_vector (1 downto 0);
-signal m_DATA_IN : std_logic_vector (31 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (3 downto 0);
-signal m_READ_OUT : std_logic_vector (1 downto 0);
-
-begin
-
- m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
- m_DATA_OUT(15 downto 0) <= MED_INIT_DATA_OUT;
- m_DATA_OUT(31 downto 16) <= MED_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(1 downto 0) <= MED_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(3 downto 2) <= MED_REPLY_PACKET_NUM_OUT;
- MED_INIT_READ_IN <= m_READ_IN(0);
- MED_REPLY_READ_IN <= m_READ_IN(1);
-
- MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
- MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
- MED_INIT_DATA_IN <= m_DATA_IN(15 downto 0);
- MED_REPLY_DATA_IN <= m_DATA_IN(31 downto 16);
- MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(1 downto 0);
- MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(3 downto 2);
- m_READ_OUT(0) <= MED_INIT_READ_OUT;
- m_READ_OUT(1) <= MED_REPLY_READ_OUT;
-
-
- PASSIVE_API: trb_net16_passive_api
-
- generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
- FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH)
-
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
-
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
-
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
-
- -- Internal direction port
- -- connect via private signals
-
- INT_INIT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
- INT_INIT_DATA_OUT => apl_to_buf_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM,
- INT_INIT_READ_IN => apl_to_buf_INIT_READ,
-
- INT_INIT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
- INT_INIT_DATA_IN => buf_to_apl_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => buf_to_apl_INIT_READ,
-
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => apl_to_buf_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => apl_to_buf_REPLY_READ,
-
- INT_REPLY_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => buf_to_apl_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => buf_to_apl_REPLY_READ,
-
- -- Status and control port
- STAT_FIFO_TO_INT => api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => api_stat_fifo_to_apl
- );
-
-STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
-STAT_api_control_signals(3) <= APL_WRITE_IN;
-STAT_api_control_signals(4) <= APL_SEND_IN;
-STAT_api_control_signals(7 downto 5) <= (others => '0');
-STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0);
-STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY;
-STAT_api_control_signals(12) <= apl_to_buf_INIT_READ;
-STAT_api_control_signals(31 downto 13) <= (others => '0');
-
-
-
-IOBUF: trb_net16_iobuf
-
- generic map (INIT_DEPTH => INIT_DEPTH,
- REPLY_DEPTH => REPLY_DEPTH)
-
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_INIT_READ_IN,
-
- MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
-
- MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_REPLY_READ_IN,
-
- MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_INIT_READ,
-
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
-
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
-
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
-
- -- Status and control port
- STAT_GEN => STAT_GEN,
- STAT_LOCKED => STAT_LOCKED,
- STAT_INIT_BUFFER => STAT_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_REPLY_BUFFER,
- CTRL_GEN => CTRL_GEN,
- CTRL_LOCKED => CTRL_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER
- );
-
- MPLEX: trb_net16_io_multiplexer
- generic map (BUS_WIDTH => 16,
- MULT_WIDTH => 1)
- port map (
- CLK => CLK,
- RESET => RESET ,
- CLK_EN => CLK_EN,
-
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
-
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
-
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
- INT_READ_IN =>m_READ_OUT,
-
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
- INT_READ_OUT =>m_READ_IN,
-
- CTRL => MPLEX_CTRL
-
- );
-
-end architecture;
-
FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of
-- the master path, if set to 0
-- no buffer is used at all
- SECURE_MODE : integer range 0 to 1 := 1
+ SECURE_MODE : integer range 0 to 1 := 0
--if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these must be available when hold_trm goes low
+ --next trigger comes in. In secure mode these need to be available while relase_trg is high
);
port(
-- Misc
INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
INT_READ_OUT: out std_logic;
-
+
-- "mini" APL, just to see the triggers coming in
APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
APL_GOT_TRM: out std_logic;
- APL_HOLD_TRM: in std_logic;
- --the trigger is released as soon as HOLD_TRM is low -> keep high if idle
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0) -- My own address (temporary solution!!!)
+ APL_RELEASE_TRM: in std_logic;
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
-- Status and control port
);
end entity;
INT_READ_OUT <= not send_trm and not reg_APL_GOT_TRM;
process(RESET, reg_APL_DTYPE_OUT, reg_APL_SEQNR_OUT, reg_APL_GOT_TRM, current_packet_type,
- INT_PACKET_NUM_IN, INT_DATA_IN, APL_HOLD_TRM, send_trm,
+ INT_PACKET_NUM_IN, INT_DATA_IN, APL_RELEASE_TRM, send_trm,
transfer_counter, INT_READ_IN, saved_packet_type, buf_APL_ERROR_PATTERN_IN, buf_APL_DTYPE_IN)
begin
--next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT;
next_APL_SEQNR_OUT <= INT_DATA_IN(11 downto 4);
next_APL_GOT_TRM <= '1';
end if;
- end if;
- if (reg_APL_GOT_TRM = '1' and APL_HOLD_TRM = '0') or send_trm = '1' then
- next_APL_GOT_TRM <= '0';
+ end if;
+ if (reg_APL_GOT_TRM = '1' and APL_RELEASE_TRM = '1') or send_trm = '1' then
+ --next_transfer_counter is used for transmission!
if transfer_counter = "10" and INT_READ_IN = '1' then
next_send_trm <= '0';
else
elsif transfer_counter = "01" then
next_INT_DATA_OUT <= buf_APL_ERROR_PATTERN_IN(15 downto 0);
else
- next_INT_DATA_OUT(15 downto 12)<= (others => '0');
+ next_INT_DATA_OUT <= (others => '0');
next_INT_DATA_OUT(11 downto 4) <= reg_APL_SEQNR_OUT;
- next_INT_DATA_OUT(3 downto 0) <= buf_APL_DTYPE_IN;
+ end if;
+ if APL_RELEASE_TRM = '1' and reg_APL_GOT_TRM = '1' then
+ next_APL_GOT_TRM <= '0';
end if;
end process;
begin
if rising_edge(CLK) then
if RESET = '1' then
- buf_APL_DTYPE_IN <= (others => '0');
buf_APL_ERROR_PATTERN_IN <= (others => '0');
- elsif APL_HOLD_TRM = '0' and send_trm = '0' then
- buf_APL_DTYPE_IN <= APL_DTYPE_IN;
+ elsif APL_RELEASE_TRM = '1' then
buf_APL_ERROR_PATTERN_IN <= APL_ERROR_PATTERN_IN;
end if;
end if;
SECURE_GEN2: if SECURE_MODE = 0 generate
buf_APL_ERROR_PATTERN_IN <= APL_ERROR_PATTERN_IN;
- buf_APL_DTYPE_IN <= APL_DTYPE_IN;
end generate;
--count packets
if RESET = '1' then
buf_INT_DATA_OUT <= (others => '0');
buf_INT_DATAREADY_OUT <= '0';
- --transfer_counter <= "00";
else
buf_INT_DATA_OUT <= next_INT_DATA_OUT;
buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT;
- --transfer_counter <= next_transfer_counter;
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or (INT_PACKET_NUM_IN = "11" and INT_DATAREADY_IN = '1') then
+ if RESET = '1' then --or (INT_PACKET_NUM_IN = "11" and INT_DATAREADY_IN = '1')
saved_packet_type <= "111";
elsif INT_PACKET_NUM_IN = "00" then
saved_packet_type <= INT_DATA_IN(2 downto 0);
end if;
end process;
- --create comb. real packet type
--- current_packet_type <= INT_DATA_IN(2 downto 0) when (INT_PACKET_NUM_IN = "00")
--- else saved_packet_type;
-
+ CLK_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_APL_GOT_TRM <= '0';
+ reg_APL_DTYPE_OUT <= (others => '0');
+ reg_APL_SEQNR_OUT <= (others => '0');
+ send_trm <= '0';
+ else
+ reg_APL_GOT_TRM <= next_APL_GOT_TRM;
+ reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT;
+ reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT;
+ send_trm <= next_send_trm;
+ end if;
+ end if;
+ end process;
- CLK_REG: process(CLK)
- begin
+ ERROROUT1_REG: process(CLK)
+ begin
if rising_edge(CLK) then
if RESET = '1' then
- reg_APL_GOT_TRM <= '0';
- reg_APL_DTYPE_OUT <= (others => '0');
- --reg_APL_ERROR_PATTERN_OUT <= (others => '0');
- reg_APL_SEQNR_OUT <= (others => '0');
- send_trm <= '0';
- else
- reg_APL_GOT_TRM <= next_APL_GOT_TRM;
- reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT;
- --reg_APL_ERROR_PATTERN_OUT <= next_APL_ERROR_PATTERN_OUT;
- reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT;
- send_trm <= next_send_trm;
+ reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= (others => '0');
+ elsif INT_PACKET_NUM_IN = "01" then
+ reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= INT_DATA_IN;
end if;
end if;
end process;
-
- ERROROUT1_REG: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= (others => '0');
- elsif INT_PACKET_NUM_IN = "01" then
- reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= INT_DATA_IN;
- end if;
- end if;
- end process;
- ERROROUT2_REG: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= (others => '0');
- elsif INT_PACKET_NUM_IN = "10" then
- reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= INT_DATA_IN;
- end if;
+ ERROROUT2_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= (others => '0');
+ elsif INT_PACKET_NUM_IN = "10" then
+ reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= INT_DATA_IN;
end if;
- end process;
+ end if;
+ end process;
end architecture;
--- /dev/null
+-- this is an trigger receiver combined with a passive api
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+--Entity decalaration for clock generator
+entity trb_net16_trigger_receiver_apimbuf_endpoint is
+
+ generic (
+ --api type for data channel
+ API_TYPE : integer range 0 to 1 := 0;
+ --Fifo for data channel
+ DAT_INIT_DEPTH : integer range 0 to 7 := 2;
+ DAT_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here
+ DAT_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1;
+ DAT_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1;
+ DAT_FIFO_TERM_BUFFER_DEPTH : integer range 0 to 7 := 0;
+ --SBUF_DATA_VERSION : integer range 0 to 1 := 0;
+ --Fifo for TRG channel
+ TRG_INIT_DEPTH : integer range 0 to 7 := 0;
+ TRG_REPLY_DEPTH : integer range 0 to 7 := 0;
+ TRG_FIFO_TERM_BUFFER_DEPTH : integer range 0 to 7 := 0;
+ TRG_SECURE_MODE : integer range 0 to 1 := 0;
+ --SBUF_TRG_VERSION : integer range 0 to 1 := 0;
+ --Multiplexer
+ MULT_WIDTH : integer range 1 to 5 := 3;
+ TRG_CHANNEL : integer range 0 to 2**(MULT_WIDTH-1) := 0;
+ DAT_CHANNEL : integer range 0 to 2**(MULT_WIDTH-1) := 2;
+ --General
+ BUS_WIDTH : integer range 16 to 16 := 16;
+ NUM_WIDTH : integer range 2 to 2 := 2
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_READ_IN: in std_logic; -- Media is reading
+ MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ -- APL Transceiver port
+ APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN: in std_logic; --
+ APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN: in std_logic; -- Release sending of the data
+ APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN: in std_logic; -- Read data word
+ APL_RUN_OUT: out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+ APL_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0);
+
+ -- TRG Receiver port
+ TRG_GOT_TRIGGER_OUT : out std_logic;
+ TRG_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ TRG_DTYPE_OUT : out std_logic_vector(3 downto 0);
+ TRG_SEQNR_OUT : out std_logic_vector(7 downto 0);
+ TRG_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
+ TRG_RELEASE_IN : in std_logic;
+
+ -- Status and control port => for debugging
+ STAT_DAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_DAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_DAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_DAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ STAT_DAT_api_control_signals: out std_logic_vector(31 downto 0);
+ CTRL_DAT_GEN: in std_logic_vector (31 downto 0);
+ CTRL_DAT_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_DAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_DAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_TRG_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_TRG_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_TRG_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_TRG_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ STAT_TRG_api_control_signals: out std_logic_vector(31 downto 0);
+ CTRL_TRG_GEN: in std_logic_vector (31 downto 0);
+ CTRL_TRG_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_TRG_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_TRG_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_MPLEX: out std_logic_vector(31 downto 0);
+ MPLEX_CTRL: in std_logic_vector (31 downto 0);
+ DAT_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ DAT_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_trigger_receiver_apimbuf_endpoint_arch of trb_net16_trigger_receiver_apimbuf_endpoint is
+
+ component trb_net16_iobuf is
+
+ generic (
+ INIT_DEPTH : integer := 1;
+ REPLY_DEPTH : integer := 1
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic; -- Media is reading
+
+ MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic; -- Media is reading
+
+ MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT: out std_logic;
+ INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_INIT_READ_IN: in std_logic;
+
+ INT_INIT_DATAREADY_IN: in std_logic;
+ INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_INIT_READ_OUT: out std_logic;
+
+ INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT: out std_logic;
+ INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_REPLY_READ_IN: in std_logic;
+
+ INT_REPLY_DATAREADY_IN: in std_logic;
+ INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_REPLY_READ_OUT: out std_logic;
+
+ -- Status and control port
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
+ );
+ end component;
+
+ component trb_net16_base_api is
+ generic (API_TYPE : integer := API_TYPE; -- type of api: 0 passive, 1 active
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium
+ FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path
+ -- if set to 0, no buffer is used
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN : in std_logic; --
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN : in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN : in std_logic; -- Read data word
+ -- APL Control port
+ APL_RUN_OUT : out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+ -- Internal direction port
+ -- the ports with master or slave in their name are to be mapped by the active api
+ -- to the init respectivly the reply path and vice versa in the passive api.
+ -- lets define: the "master" path is the path that I send data on.
+ INT_MASTER_DATAREADY_OUT : out std_logic;
+ INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_MASTER_READ_IN : in std_logic;
+ INT_MASTER_DATAREADY_IN : in std_logic;
+ INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_MASTER_READ_OUT : out std_logic;
+ INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR
+ INT_SLAVE_DATAREADY_OUT : out std_logic;
+ INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_IN : in std_logic;
+ INT_SLAVE_DATAREADY_IN : in std_logic;
+ INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_OUT : out std_logic;
+ -- Status and control port
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component trb_net16_term is
+ generic (
+ FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ SECURE_MODE : integer range 0 to 1 := 0
+ --if secure_mode is not used, apl must provide error pattern and dtype until
+ --next trigger comes in. In secure mode these must be available when hold_trm goes low
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ INT_DATAREADY_OUT: out std_logic;
+ INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ INT_READ_IN: in std_logic;
+ INT_DATAREADY_IN: in std_logic;
+ INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_READ_OUT: out std_logic;
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+ APL_GOT_TRM: out std_logic;
+ APL_RELEASE_TRM: in std_logic;
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
+ -- Status and control port
+ );
+ end component;
+
+ component trb_net16_io_multiplexer is
+
+ generic (BUS_WIDTH : integer := 16;
+ MULT_WIDTH : integer := 3);
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in std_logic;
+ MED_DATA_IN: in std_logic_vector (BUS_WIDTH-1 downto 0);
+ -- highest bits are mult.
+ MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_READ_OUT: out std_logic;
+
+ MED_DATAREADY_OUT: out std_logic;
+ MED_DATA_OUT: out std_logic_vector (BUS_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_READ_IN: in std_logic;
+
+ -- Internal direction port
+ INT_DATAREADY_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
+ INT_DATA_OUT: out std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
+ INT_READ_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
+
+ INT_DATAREADY_IN: in std_logic_vector (2**MULT_WIDTH-1 downto 0);
+ INT_DATA_IN: in std_logic_vector ((BUS_WIDTH)*(2**MULT_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MULT_WIDTH)-1 downto 0);
+ INT_READ_OUT: out std_logic_vector (2**MULT_WIDTH-1 downto 0);
+
+ -- Status and control port
+ CTRL: in std_logic_vector (31 downto 0);
+ STAT: out std_logic_vector (31 downto 0)
+ );
+ end component;
+
+signal apl_to_buf_DAT_INIT_DATAREADY: std_logic;
+signal apl_to_buf_DAT_INIT_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_INIT_READ : std_logic;
+
+signal buf_to_apl_DAT_INIT_DATAREADY: std_logic;
+signal buf_to_apl_DAT_INIT_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_INIT_READ : std_logic;
+
+signal apl_to_buf_DAT_REPLY_DATAREADY: std_logic;
+signal apl_to_buf_DAT_REPLY_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal apl_to_buf_DAT_REPLY_READ : std_logic;
+
+signal buf_to_apl_DAT_REPLY_DATAREADY: std_logic;
+signal buf_to_apl_DAT_REPLY_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal buf_to_apl_DAT_REPLY_READ : std_logic;
+
+signal apl_to_buf_TRG_INIT_DATAREADY: std_logic;
+signal apl_to_buf_TRG_INIT_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_INIT_READ : std_logic;
+
+signal buf_to_apl_TRG_INIT_DATAREADY: std_logic;
+signal buf_to_apl_TRG_INIT_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_INIT_READ : std_logic;
+
+signal apl_to_buf_TRG_REPLY_DATAREADY: std_logic;
+signal apl_to_buf_TRG_REPLY_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal apl_to_buf_TRG_REPLY_READ : std_logic;
+
+signal buf_to_apl_TRG_REPLY_DATAREADY: std_logic;
+signal buf_to_apl_TRG_REPLY_DATA : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
+signal buf_to_apl_TRG_REPLY_READ : std_logic;
+
+-- for the connection to the multiplexer
+signal MED_DAT_INIT_DATAREADY_OUT : std_logic;
+signal MED_DAT_INIT_DATA_OUT : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_DAT_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_DAT_INIT_READ_IN : std_logic;
+
+signal MED_DAT_INIT_DATAREADY_IN : std_logic;
+signal MED_DAT_INIT_DATA_IN : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_DAT_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_DAT_INIT_READ_OUT : std_logic;
+
+signal MED_DAT_REPLY_DATAREADY_OUT : std_logic;
+signal MED_DAT_REPLY_DATA_OUT : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_READ_IN : std_logic;
+
+signal MED_DAT_REPLY_DATAREADY_IN : std_logic;
+signal MED_DAT_REPLY_DATA_IN : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_DAT_REPLY_READ_OUT : std_logic;
+
+signal MED_TRG_INIT_DATAREADY_OUT : std_logic;
+signal MED_TRG_INIT_DATA_OUT : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_TRG_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_TRG_INIT_READ_IN : std_logic;
+
+signal MED_TRG_INIT_DATAREADY_IN : std_logic;
+signal MED_TRG_INIT_DATA_IN : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_TRG_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_TRG_INIT_READ_OUT : std_logic;
+
+signal MED_TRG_REPLY_DATAREADY_OUT : std_logic;
+signal MED_TRG_REPLY_DATA_OUT : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_READ_IN : std_logic;
+
+signal MED_TRG_REPLY_DATAREADY_IN : std_logic;
+signal MED_TRG_REPLY_DATA_IN : std_logic_vector (BUS_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
+signal MED_TRG_REPLY_READ_OUT : std_logic;
+
+signal m_DATAREADY_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATA_OUT : std_logic_vector (BUS_WIDTH*2**MULT_WIDTH-1 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
+signal m_READ_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+
+signal m_DATAREADY_IN : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+signal m_DATA_IN : std_logic_vector (BUS_WIDTH**MULT_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MULT_WIDTH-1 downto 0);
+signal m_READ_OUT : std_logic_vector (2**MULT_WIDTH-1 downto 0);
+
+begin
+ --Connections for data channel
+ m_DATAREADY_OUT(DAT_CHANNEL*2) <= MED_DAT_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(DAT_CHANNEL*2+1) <= MED_DAT_REPLY_DATAREADY_OUT;
+ m_DATA_OUT((DAT_CHANNEL*2+1)*BUS_WIDTH-1 downto DAT_CHANNEL*BUS_WIDTH*2) <= MED_DAT_INIT_DATA_OUT;
+ m_DATA_OUT((DAT_CHANNEL*2+2)*BUS_WIDTH-1 downto (DAT_CHANNEL*2+1)*BUS_WIDTH) <= MED_DAT_REPLY_DATA_OUT;
+ m_PACKET_NUM_OUT(DAT_CHANNEL*4+1 downto DAT_CHANNEL*4) <= MED_DAT_INIT_PACKET_NUM_OUT;
+ m_PACKET_NUM_OUT(DAT_CHANNEL*4+3 downto DAT_CHANNEL*4+2) <= MED_DAT_REPLY_PACKET_NUM_OUT;
+ MED_DAT_INIT_READ_IN <= m_READ_IN(DAT_CHANNEL*2);
+ MED_DAT_REPLY_READ_IN <= m_READ_IN(DAT_CHANNEL*2+1);
+
+ MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(DAT_CHANNEL*2);
+ MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(DAT_CHANNEL*2+1);
+ MED_DAT_INIT_DATA_IN <= m_DATA_IN((DAT_CHANNEL*2+1)*BUS_WIDTH-1 downto DAT_CHANNEL*BUS_WIDTH*2);
+ MED_DAT_REPLY_DATA_IN <= m_DATA_IN((DAT_CHANNEL*2+2)*BUS_WIDTH-1 downto (DAT_CHANNEL*2+1)*BUS_WIDTH);
+ MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(DAT_CHANNEL*4+1 downto DAT_CHANNEL*4);
+ MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(DAT_CHANNEL*4+3 downto DAT_CHANNEL*4+2);
+ m_READ_OUT(DAT_CHANNEL*2) <= MED_DAT_INIT_READ_OUT;
+ m_READ_OUT(DAT_CHANNEL*2+1) <= MED_DAT_REPLY_READ_OUT;
+
+ --Connections for trigger channel
+ m_DATAREADY_OUT(TRG_CHANNEL*2) <= MED_TRG_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(TRG_CHANNEL*2+1) <= MED_TRG_REPLY_DATAREADY_OUT;
+ m_DATA_OUT((TRG_CHANNEL*2+1)*BUS_WIDTH-1 downto TRG_CHANNEL*BUS_WIDTH*2) <= MED_TRG_INIT_DATA_OUT;
+ m_DATA_OUT((TRG_CHANNEL*2+2)*BUS_WIDTH-1 downto (TRG_CHANNEL*2+1)*BUS_WIDTH) <= MED_TRG_REPLY_DATA_OUT;
+ m_PACKET_NUM_OUT(TRG_CHANNEL*4+1 downto TRG_CHANNEL*4) <= MED_TRG_INIT_PACKET_NUM_OUT;
+ m_PACKET_NUM_OUT(TRG_CHANNEL*4+3 downto TRG_CHANNEL*4+2) <= MED_TRG_REPLY_PACKET_NUM_OUT;
+ MED_TRG_INIT_READ_IN <= m_READ_IN(TRG_CHANNEL*2);
+ MED_TRG_REPLY_READ_IN <= m_READ_IN(TRG_CHANNEL*2+1);
+
+ MED_TRG_INIT_DATAREADY_IN <= m_DATAREADY_IN(TRG_CHANNEL*2);
+ MED_TRG_REPLY_DATAREADY_IN <= m_DATAREADY_IN(TRG_CHANNEL*2+1);
+ MED_TRG_INIT_DATA_IN <= m_DATA_IN((TRG_CHANNEL*2+1)*BUS_WIDTH-1 downto TRG_CHANNEL*BUS_WIDTH*2);
+ MED_TRG_REPLY_DATA_IN <= m_DATA_IN((TRG_CHANNEL*2+2)*BUS_WIDTH-1 downto (TRG_CHANNEL*2+1)*BUS_WIDTH);
+ MED_TRG_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(TRG_CHANNEL*4+1 downto TRG_CHANNEL*4);
+ MED_TRG_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(TRG_CHANNEL*4+3 downto TRG_CHANNEL*4+2);
+ m_READ_OUT(TRG_CHANNEL*2) <= MED_TRG_INIT_READ_OUT;
+ m_READ_OUT(TRG_CHANNEL*2+1) <= MED_TRG_REPLY_READ_OUT;
+
+ gen_actapi: if API_TYPE = 1 generate
+ DAT_ACTIVE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 1,
+ FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => DAT_FIFO_TERM_BUFFER_DEPTH
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
+ INT_MASTER_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_INIT_PACKET_NUM,
+ INT_MASTER_READ_IN => apl_to_buf_DAT_INIT_READ,
+ INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
+ INT_MASTER_DATA_IN => buf_to_apl_DAT_INIT_DATA,
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_INIT_PACKET_NUM,
+ INT_MASTER_READ_OUT => buf_to_apl_DAT_INIT_READ,
+ INT_SLAVE_HEADER_IN => '0',
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
+ INT_SLAVE_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_REPLY_PACKET_NUM,
+ INT_SLAVE_READ_IN => apl_to_buf_DAT_REPLY_READ,
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
+ INT_SLAVE_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_REPLY_PACKET_NUM,
+ INT_SLAVE_READ_OUT => buf_to_apl_DAT_REPLY_READ,
+ -- Status and control port
+ STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
+ STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
+ );
+ end generate;
+
+ gen_pasapi: if API_TYPE = 0 generate
+ DAT_PASSIVE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 0,
+ FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => DAT_FIFO_TERM_BUFFER_DEPTH
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => (others => '0'),
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
+ INT_MASTER_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_REPLY_PACKET_NUM,
+ INT_MASTER_READ_IN => apl_to_buf_DAT_REPLY_READ,
+ INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
+ INT_MASTER_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_REPLY_PACKET_NUM,
+ INT_MASTER_READ_OUT => buf_to_apl_DAT_REPLY_READ,
+ INT_SLAVE_HEADER_IN => '0',
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
+ INT_SLAVE_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_INIT_PACKET_NUM,
+ INT_SLAVE_READ_IN => apl_to_buf_DAT_INIT_READ,
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
+ INT_SLAVE_DATA_IN => buf_to_apl_DAT_INIT_DATA,
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_INIT_PACKET_NUM,
+ INT_SLAVE_READ_OUT => buf_to_apl_DAT_INIT_READ,
+ -- Status and control port
+ STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
+ STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
+ );
+ end generate;
+
+STAT_DAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
+STAT_DAT_api_control_signals(3) <= APL_WRITE_IN;
+STAT_DAT_api_control_signals(4) <= APL_SEND_IN;
+STAT_DAT_api_control_signals(7 downto 5) <= (others => '0');
+STAT_DAT_api_control_signals(10 downto 8) <= apl_to_buf_DAT_INIT_DATA(2 downto 0);
+STAT_DAT_api_control_signals(11) <= apl_to_buf_DAT_INIT_DATAREADY;
+STAT_DAT_api_control_signals(12) <= apl_to_buf_DAT_INIT_READ;
+STAT_DAT_api_control_signals(31 downto 13) <= (others => '0');
+
+
+
+DAT_IOBUF: trb_net16_iobuf
+ generic map(
+ INIT_DEPTH => DAT_INIT_DEPTH,
+ REPLY_DEPTH => DAT_REPLY_DEPTH
+ )
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_DAT_INIT_DATAREADY_OUT,
+ MED_INIT_DATA_OUT => MED_DAT_INIT_DATA_OUT,
+ MED_INIT_PACKET_NUM_OUT => MED_DAT_INIT_PACKET_NUM_OUT,
+ MED_INIT_READ_IN => MED_DAT_INIT_READ_IN,
+ MED_INIT_DATAREADY_IN => MED_DAT_INIT_DATAREADY_IN,
+ MED_INIT_DATA_IN => MED_DAT_INIT_DATA_IN,
+ MED_INIT_PACKET_NUM_IN => MED_DAT_INIT_PACKET_NUM_IN,
+ MED_INIT_READ_OUT => MED_DAT_INIT_READ_OUT,
+ MED_INIT_ERROR_IN => (others => '0'),
+ MED_REPLY_DATAREADY_OUT => MED_DAT_REPLY_DATAREADY_OUT,
+ MED_REPLY_DATA_OUT => MED_DAT_REPLY_DATA_OUT,
+ MED_REPLY_PACKET_NUM_OUT=> MED_DAT_REPLY_PACKET_NUM_OUT,
+ MED_REPLY_READ_IN => MED_DAT_REPLY_READ_IN,
+ MED_REPLY_DATAREADY_IN => MED_DAT_REPLY_DATAREADY_IN,
+ MED_REPLY_DATA_IN => MED_DAT_REPLY_DATA_IN,
+ MED_REPLY_PACKET_NUM_IN => MED_DAT_REPLY_PACKET_NUM_IN,
+ MED_REPLY_READ_OUT => MED_DAT_REPLY_READ_OUT,
+ MED_REPLY_ERROR_IN => (others => '0'),
+ -- Internal direction port
+ INT_INIT_DATAREADY_OUT => buf_to_apl_DAT_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => buf_to_apl_DAT_INIT_DATA,
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT_INIT_PACKET_NUM,
+ INT_INIT_READ_IN => buf_to_apl_DAT_INIT_READ,
+ INT_INIT_DATAREADY_IN => apl_to_buf_DAT_INIT_DATAREADY,
+ INT_INIT_DATA_IN => apl_to_buf_DAT_INIT_DATA,
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT_INIT_PACKET_NUM,
+ INT_INIT_READ_OUT => apl_to_buf_DAT_INIT_READ,
+ INT_REPLY_HEADER_IN => '0',
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => buf_to_apl_DAT_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT_REPLY_PACKET_NUM,
+ INT_REPLY_READ_IN => buf_to_apl_DAT_REPLY_READ,
+ INT_REPLY_DATAREADY_IN => apl_to_buf_DAT_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => apl_to_buf_DAT_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT_REPLY_PACKET_NUM,
+ INT_REPLY_READ_OUT => apl_to_buf_DAT_REPLY_READ,
+ -- Status and control port
+ STAT_GEN => STAT_DAT_GEN,
+ STAT_LOCKED => STAT_DAT_LOCKED,
+ STAT_INIT_BUFFER => STAT_DAT_INIT_BUFFER,
+ STAT_REPLY_BUFFER => STAT_DAT_REPLY_BUFFER,
+ CTRL_GEN => CTRL_DAT_GEN,
+ CTRL_LOCKED => CTRL_DAT_LOCKED,
+ STAT_CTRL_INIT_BUFFER => STAT_DAT_CTRL_INIT_BUFFER,
+ STAT_CTRL_REPLY_BUFFER => STAT_DAT_CTRL_REPLY_BUFFER
+ );
+
+ TRG_IOBUF: trb_net16_iobuf
+ generic map(
+ INIT_DEPTH => TRG_INIT_DEPTH,
+ REPLY_DEPTH => TRG_REPLY_DEPTH
+ )
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_TRG_INIT_DATAREADY_OUT,
+ MED_INIT_DATA_OUT => MED_TRG_INIT_DATA_OUT,
+ MED_INIT_PACKET_NUM_OUT => MED_TRG_INIT_PACKET_NUM_OUT,
+ MED_INIT_READ_IN => MED_TRG_INIT_READ_IN,
+ MED_INIT_DATAREADY_IN => MED_TRG_INIT_DATAREADY_IN,
+ MED_INIT_DATA_IN => MED_TRG_INIT_DATA_IN,
+ MED_INIT_PACKET_NUM_IN => MED_TRG_INIT_PACKET_NUM_IN,
+ MED_INIT_READ_OUT => MED_TRG_INIT_READ_OUT,
+ MED_INIT_ERROR_IN => (others => '0'),
+ MED_REPLY_DATAREADY_OUT => MED_TRG_REPLY_DATAREADY_OUT,
+ MED_REPLY_DATA_OUT => MED_TRG_REPLY_DATA_OUT,
+ MED_REPLY_PACKET_NUM_OUT=> MED_TRG_REPLY_PACKET_NUM_OUT,
+ MED_REPLY_READ_IN => MED_TRG_REPLY_READ_IN,
+ MED_REPLY_DATAREADY_IN => MED_TRG_REPLY_DATAREADY_IN,
+ MED_REPLY_DATA_IN => MED_TRG_REPLY_DATA_IN,
+ MED_REPLY_PACKET_NUM_IN => MED_TRG_REPLY_PACKET_NUM_IN,
+ MED_REPLY_READ_OUT => MED_TRG_REPLY_READ_OUT,
+ MED_REPLY_ERROR_IN => (others => '0'),
+ -- Internal direction port
+ INT_INIT_DATAREADY_OUT => buf_to_apl_TRG_INIT_DATAREADY,
+ INT_INIT_DATA_OUT => buf_to_apl_TRG_INIT_DATA,
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG_INIT_PACKET_NUM,
+ INT_INIT_READ_IN => buf_to_apl_TRG_INIT_READ,
+ INT_INIT_DATAREADY_IN => apl_to_buf_TRG_INIT_DATAREADY,
+ INT_INIT_DATA_IN => apl_to_buf_TRG_INIT_DATA,
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG_INIT_PACKET_NUM,
+ INT_INIT_READ_OUT => apl_to_buf_TRG_INIT_READ,
+ INT_REPLY_HEADER_IN => '0',
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG_REPLY_DATAREADY,
+ INT_REPLY_DATA_OUT => buf_to_apl_TRG_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG_REPLY_PACKET_NUM,
+ INT_REPLY_READ_IN => buf_to_apl_TRG_REPLY_READ,
+ INT_REPLY_DATAREADY_IN => apl_to_buf_TRG_REPLY_DATAREADY,
+ INT_REPLY_DATA_IN => apl_to_buf_TRG_REPLY_DATA,
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG_REPLY_PACKET_NUM,
+ INT_REPLY_READ_OUT => apl_to_buf_TRG_REPLY_READ,
+ -- Status and control port
+ STAT_GEN => STAT_TRG_GEN,
+ STAT_LOCKED => STAT_TRG_LOCKED,
+ STAT_INIT_BUFFER => STAT_TRG_INIT_BUFFER,
+ STAT_REPLY_BUFFER => STAT_TRG_REPLY_BUFFER,
+ CTRL_GEN => CTRL_TRG_GEN,
+ CTRL_LOCKED => CTRL_TRG_LOCKED,
+ STAT_CTRL_INIT_BUFFER => STAT_TRG_CTRL_INIT_BUFFER,
+ STAT_CTRL_REPLY_BUFFER => STAT_TRG_CTRL_REPLY_BUFFER
+ );
+
+ MPLEX: trb_net16_io_multiplexer
+
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT =>m_DATA_IN,
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
+ INT_READ_IN =>m_READ_OUT,
+ INT_DATAREADY_IN =>m_DATAREADY_OUT,
+ INT_DATA_IN =>m_DATA_OUT,
+ INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
+ INT_READ_OUT =>m_READ_IN,
+ CTRL => MPLEX_CTRL
+ );
+
+ TRG_INIT : trb_net16_term
+ generic map (
+ FIFO_TERM_BUFFER_DEPTH => TRG_FIFO_TERM_BUFFER_DEPTH,
+ SECURE_MODE => TRG_SECURE_MODE
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ INT_DATAREADY_OUT => apl_to_buf_TRG_REPLY_DATAREADY,
+ INT_DATA_OUT => apl_to_buf_TRG_REPLY_DATA,
+ INT_PACKET_NUM_OUT => apl_to_buf_TRG_REPLY_PACKET_NUM,
+ INT_READ_IN => apl_to_buf_TRG_REPLY_READ,
+ INT_DATAREADY_IN => buf_to_apl_TRG_INIT_DATAREADY,
+ INT_DATA_IN => buf_to_apl_TRG_INIT_DATA,
+ INT_PACKET_NUM_IN => buf_to_apl_TRG_INIT_PACKET_NUM,
+ INT_READ_OUT => buf_to_apl_TRG_INIT_READ,
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT => TRG_DTYPE_OUT,
+ APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT,
+ APL_SEQNR_OUT => TRG_SEQNR_OUT,
+ APL_GOT_TRM => TRG_GOT_TRIGGER_OUT,
+ APL_RELEASE_TRM => TRG_RELEASE_IN,
+ APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN
+ -- Status and control port
+ );
+
+
+ TRG_REPLY : trb_net16_term
+ generic map (
+ FIFO_TERM_BUFFER_DEPTH => TRG_FIFO_TERM_BUFFER_DEPTH,
+ SECURE_MODE => 0
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ INT_DATAREADY_OUT => apl_to_buf_TRG_INIT_DATAREADY,
+ INT_DATA_OUT => apl_to_buf_TRG_INIT_DATA,
+ INT_PACKET_NUM_OUT => apl_to_buf_TRG_INIT_PACKET_NUM,
+ INT_READ_IN => apl_to_buf_TRG_INIT_READ,
+ INT_DATAREADY_IN => buf_to_apl_TRG_REPLY_DATAREADY,
+ INT_DATA_IN => buf_to_apl_TRG_REPLY_DATA,
+ INT_PACKET_NUM_IN => buf_to_apl_TRG_REPLY_PACKET_NUM,
+ INT_READ_OUT => buf_to_apl_TRG_REPLY_READ,
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT => open,
+ APL_ERROR_PATTERN_OUT => open,
+ APL_SEQNR_OUT => open,
+ APL_GOT_TRM => open,
+ APL_RELEASE_TRM => '1',
+ APL_ERROR_PATTERN_IN => (others => '0')
+ -- Status and control port
+ );
+
+end architecture;
entity trb_net16_trigger_receiver_endpoint is
generic (
- INIT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), if
+ TRG_INIT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), if
-- the initibuf
- REPLY_DEPTH : integer := 1; -- or the replyibuf
- MULT_WIDTH : integer := 1;
+ TRG_REPLY_DEPTH : integer := 0; -- or the replyibuf
+ TRG_FIFO_TERM_BUFFER_DEPTH : integer range 0 to 7 := 0;
+ MULT_WIDTH : integer := 3;
+ TRG_CHANNEL : integer := 0;
BUS_WIDTH : integer := 16; --not to be changed
NUM_WIDTH : integer := 2; --not to be changed
- SECURE_MODE : integer := 0 -- if 0, error pattern and dtype must be valid until next
+ TRG_SECURE_MODE : integer := 0 -- if 0, error pattern and dtype must be valid until next
-- trigger comes in. if 1 these can be valid on falling edge of hold_trm only
);
MED_READ_OUT: out std_logic; -- buffer reads a word from media
MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
- APL_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- APL_GOT_TRIGGER_OUT : out std_logic;
- APL_DTYPE_OUT : out std_logic_vector(3 downto 0);
- APL_SEQNR_OUT : out std_logic_vector(7 downto 0);
- APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- APL_HOLD_IN : in std_logic;
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ TRG_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ TRG_GOT_TRIGGER_OUT : out std_logic;
+ TRG_DTYPE_OUT : out std_logic_vector(3 downto 0);
+ TRG_SEQNR_OUT : out std_logic_vector(7 downto 0);
+ TRG_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
+ TRG_RELEASE_IN : in std_logic;
-- Status and control port => just coming from the iobuf for debugging
STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
architecture trb_net16_trigger_receiver_endpoint_arch of trb_net16_trigger_receiver_endpoint is
component trb_net16_iobuf is
- generic (INIT_DEPTH : integer := INIT_DEPTH; -- Depth of the FIFO, 2^(n+1), if
+ generic (INIT_DEPTH : integer := TRG_INIT_DEPTH; -- Depth of the FIFO, 2^(n+1), if
-- the initibuf
- REPLY_DEPTH : integer := REPLY_DEPTH); -- or the replyibuf
+ REPLY_DEPTH : integer := TRG_REPLY_DEPTH); -- or the replyibuf
port(
-- Misc
CLK : in std_logic;
end component;
component trb_net16_term is
generic (
- FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of
+ FIFO_TERM_BUFFER_DEPTH : integer := TRG_FIFO_TERM_BUFFER_DEPTH; -- fifo for auto-answering of
-- the master path, if set to 0
-- no buffer is used at all
- SECURE_MODE : integer range 0 to 1 := SECURE_MODE
+ SECURE_MODE : integer range 0 to 1 := TRG_SECURE_MODE
--if secure_mode is not used, apl must provide error pattern and dtype until
--next trigger comes in. In secure mode these must be available when hold_trm goes low
);
APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
APL_GOT_TRM: out std_logic;
- APL_HOLD_TRM: in std_logic;
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0) -- My own address (temporary solution!!!)
+ APL_RELEASE_TRM: in std_logic;
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
-- Status and control port
);
end component;
-------------------------------------------------
--Connection between multiplexer and iobuf
-------------------------------------------------
- m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT;
- m_DATA_OUT(15 downto 0) <= MED_INIT_DATA_OUT;
- m_DATA_OUT(31 downto 16) <= MED_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(1 downto 0) <= MED_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(3 downto 2) <= MED_REPLY_PACKET_NUM_OUT;
- MED_INIT_READ_IN <= m_READ_IN(0);
- MED_REPLY_READ_IN <= m_READ_IN(1);
+ m_DATAREADY_OUT(TRG_CHANNEL*2) <= MED_INIT_DATAREADY_OUT;
+ m_DATAREADY_OUT(TRG_CHANNEL*2+1) <= MED_REPLY_DATAREADY_OUT;
+ m_DATA_OUT(BUS_WIDTH*(TRG_CHANNEL+1)-1 downto BUS_WIDTH*TRG_CHANNEL) <= MED_INIT_DATA_OUT;
+ m_DATA_OUT(BUS_WIDTH*(TRG_CHANNEL+2)-1 downto BUS_WIDTH*(TRG_CHANNEL+1)) <= MED_REPLY_DATA_OUT;
+ m_PACKET_NUM_OUT((TRG_CHANNEL+1)*2-1 downto TRG_CHANNEL*2) <= MED_INIT_PACKET_NUM_OUT;
+ m_PACKET_NUM_OUT((TRG_CHANNEL+2)*2-1 downto (TRG_CHANNEL+1)*2) <= MED_REPLY_PACKET_NUM_OUT;
+ MED_INIT_READ_IN <= m_READ_IN(TRG_CHANNEL*2);
+ MED_REPLY_READ_IN <= m_READ_IN(TRG_CHANNEL*2+1);
- MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0);
- MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1);
- MED_INIT_DATA_IN <= m_DATA_IN(15 downto 0);
- MED_REPLY_DATA_IN <= m_DATA_IN(31 downto 16);
- MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(1 downto 0);
- MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(3 downto 2);
- m_READ_OUT(0) <= MED_INIT_READ_OUT;
- m_READ_OUT(1) <= MED_REPLY_READ_OUT;
+ MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(TRG_CHANNEL*2);
+ MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(TRG_CHANNEL*2+1);
+ MED_INIT_DATA_IN <= m_DATA_IN(BUS_WIDTH*(TRG_CHANNEL+1)-1 downto BUS_WIDTH*TRG_CHANNEL);
+ MED_REPLY_DATA_IN <= m_DATA_IN(BUS_WIDTH*(TRG_CHANNEL+2)-1 downto BUS_WIDTH*(TRG_CHANNEL+1));
+ MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN((TRG_CHANNEL+1)*2-1 downto TRG_CHANNEL*2);
+ MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN((TRG_CHANNEL+2)*2-1 downto (TRG_CHANNEL+1)*2);
+ m_READ_OUT(TRG_CHANNEL*2) <= MED_INIT_READ_OUT;
+ m_READ_OUT(TRG_CHANNEL*2+1) <= MED_REPLY_READ_OUT;
IOBUF: trb_net16_iobuf
port map (
INT_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM,
INT_READ_OUT => buf_to_apl_INIT_READ,
-- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => APL_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
- APL_GOT_TRM => APL_GOT_TRIGGER_OUT,
- APL_HOLD_TRM => APL_HOLD_IN,
- APL_DTYPE_IN => "0000",
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN
+ APL_DTYPE_OUT => TRG_DTYPE_OUT,
+ APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT,
+ APL_SEQNR_OUT => TRG_SEQNR_OUT,
+ APL_GOT_TRM => TRG_GOT_TRIGGER_OUT,
+ APL_RELEASE_TRM => TRG_RELEASE_IN,
+ APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN
-- Status and control port
);
+ TRM_REPLY : trb_net16_term
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ INT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY,
+ INT_DATA_OUT => apl_to_buf_INIT_DATA,
+ INT_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM,
+ INT_READ_IN => apl_to_buf_INIT_READ,
+ INT_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY,
+ INT_DATA_IN => buf_to_apl_REPLY_DATA,
+ INT_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM,
+ INT_READ_OUT => buf_to_apl_REPLY_READ,
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT => open,
+ APL_ERROR_PATTERN_OUT => open,
+ APL_SEQNR_OUT => open,
+ APL_GOT_TRM => open,
+ APL_RELEASE_TRM => '1',
+ APL_ERROR_PATTERN_IN => (others => '0')
+ -- Status and control port
+ );
+
end architecture;
\ No newline at end of file
-- generic (BUS_WIDTH : integer := 56;
-- MULT_WIDTH : integer := 5);
- generic (BUS_WIDTH : integer := 52;
+ generic (BUS_WIDTH : integer := 16;
MULT_WIDTH : integer := 1);
port(
);
end component;
- component trb_net_sbuf is
-
- generic (DATA_WIDTH : integer := 56;
- VERSION: integer := 1);
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- -- the COMB_next_READ_OUT should be connected via comb. logic to a register
- -- to provide COMB_READ_IN (feedback path with 1 cycle delay)
- -- The "REAL" READ_OUT can be constructed in the comb via COMB_next_READ_
- -- OUT and the READ_IN: If one of these is ='1', no problem to read in next
- -- step.
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- -- Port to synchronous output.
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER: out STD_LOGIC
- );
+ component trb_net16_sbuf is
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ VERSION : integer := 0
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN : in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT : out STD_LOGIC;
+ SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
+ SYN_READ_IN : in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER : out STD_LOGIC
+ );
end component;
component trb_net_priority_arbiter is
-- the simpler part is the demux
G1: for i in 0 to 2**MULT_WIDTH-1 generate
- DEMUX_SBUF: trb_net_sbuf
+ DEMUX_SBUF: trb_net16_sbuf
generic map (DATA_WIDTH => BUS_WIDTH-MULT_WIDTH, VERSION => 0)
port map (
CLK => CLK,
return std_logic;
function xor_all (arg : std_logic_vector)
return std_logic;
-
- subtype TYPE_POSITION is integer range 50 downto 48;
+
+ subtype TYPE_POSITION is integer range 50 downto 48;
constant TYPE_DAT : std_logic_vector(2 downto 0) := "000";
constant TYPE_HDR : std_logic_vector(2 downto 0) := "001";
- constant TYPE_TRM : std_logic_vector(2 downto 0) := "010";
- constant TYPE_EOB : std_logic_vector(2 downto 0) := "011";
+ constant TYPE_EOB : std_logic_vector(2 downto 0) := "010";
+ constant TYPE_TRM : std_logic_vector(2 downto 0) := "011";
constant TYPE_ACK : std_logic_vector(2 downto 0) := "101";
constant TYPE_ILLEGAL : std_logic_vector(2 downto 0) := "111";
-
+
constant ERROR_OK : std_logic_vector(2 downto 0) := "000"; --transmission ok
constant ERROR_ENCOD : std_logic_vector(2 downto 0) := "001"; --transmission error by encoding
constant ERROR_RECOV : std_logic_vector(2 downto 0) := "010"; --transmission error, reconstructed
constant ERROR_FATAL : std_logic_vector(2 downto 0) := "011"; --transmission error, fatal
constant ERROR_NC : std_logic_vector(2 downto 0) := "101"; --media not connected
-
+
subtype F1_POSITION is integer range 47 downto 32;
subtype F2_POSITION is integer range 31 downto 16;
subtype F3_POSITION is integer range 15 downto 0;
subtype DTYPE_POSITION is integer range 3 downto 0;
subtype SEQNR_POSITION is integer range 11 downto 4;
subtype ERRORPATTERN_POSITION is integer range 47 downto 16;
-
+
subtype SOURCE_POSITION is integer range 47 downto 32;
subtype TARGET_POSITION is integer range 31 downto 16;
constant ILLEGAL_ADRESS : std_logic_vector(15 downto 0) := x"0000";
constant BROADCAST_ADRESS : std_logic_vector(15 downto 0) := x"ffff";
-
+
constant F1_CHECK_ACK : std_logic_vector(15 downto 0) := x"0000";
subtype BUFFER_SIZE_POSITION is integer range 19 downto 16;
INT_READ_OUT: STD_LOGIC;
INT_ERROR_IN: STD_LOGIC_VECTOR (2 downto 0); -- Status bits
end record;
-
-
+
+
end package trb_net_std;
package body trb_net_std is
jspc29 / trbnet.git / commitdiff