32 bit master debugged, IF

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index 7585f6d0933670bfaa049b2a5eb7f764c3e063a2..b8de49c040d64d5b4471575b76397388e6b410df 100644 (file)
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -4,9 +4,14 @@
 --\r
 -- Data in the user flash will be unpacked during boot, the data has the\r
 -- following format:\r
---   Version : 1 Byte (must be 0x01, otherwise the unpacking will be cancelled)\r
---   SPI address : 1 Byte\r
---   SPI data : 2 Bytes in big-endian\r
+--   Version : 1 Byte (must be 0x01 or 0x02, otherwise the unpacking will be cancelled)\r
+--   Version = 0x01 : 16 Bit version\r
+--     SPI address : 1 Byte\r
+--     SPI data : 2 Bytes in big-endian\r
+--   Version = 0x02 : 32 Bit version\r
+--     SPI address : 1 Byte\r
+--     SPI data : 4 Bytes in big-endian\r
+--     2 paddings bytes\r
 --\r
 -- SPI registers:\r
 --  0x4x : Mapped flash page (16 Bytes)\r
@@ -15,7 +20,10 @@
 --         Bits 12-0  : Flash page\r
 --  0x5C : control register\r
 --         Bit 0 : Enable cfg flash\r
---         Bit 1 : Master start (starts unpacking = booting)\r
+--         Bit 1 : Flash error (read-only)\r
+--         Bit 2 : Flash busy (read-only)\r
+--         Bit 4 : Master start (starts unpacking = booting)\r
+--         Bit 5 : Master running (read-only)\r
 --  0x5D : Bits 0/1: Flash memory read buswidth:\r
 --         00 : 8 Bit, 01 : 16 Bit, 11 : 32 Bit (if available)\r
 --         Bit 4: 0: Little Endian; 1: Big Endian\r
@@ -118,7 +126,8 @@ architecture arch of generic_flash_ctrl is
   signal out_delay : std_logic_vector(2 downto 0);\r
   \r
 \r
-  type state_type is (IDLE, EnableFLASH1, EnableFLASH2, EnableFLASH3, Start, ReadPage, WaitFlash1, WaitFlash2, ReadRAM, WaitRAM1, WaitRAM2, WaitRAM3, WaitRAM4, WaitRAM5, WriteSPI);\r
+  type state_type is (IDLE, EnableFLASH1, EnableFLASH2, EnableFLASH3, Start, ReadPage, WaitFlash1, WaitFlash2, ReadRAM, WaitRAM1, WaitRAM2, WaitRAM3, WaitRAM4,\r
+                      WaitRAM2_32, WaitRAM3_32, WaitRAM4_32, WaitRAM5_32, WaitRAM6_32, WriteSPI);\r
   signal state : state_type := IDLE;\r
   signal master_running       : std_logic;\r
   signal master_word_counter  : std_logic_vector(3 downto 0);\r
@@ -188,8 +197,11 @@ PROC_SELECTOR : process begin
   reg_LOC_ADDR_OUT  <= SPI_ADDR_IN;\r
   reg_LOC_WRITE_OUT <= SPI_WRITE_IN;\r
   reg_LOC_READ_OUT  <= SPI_READ_IN;\r
-  reg_SPI_DATA_OUT  <= LOC_DATA_IN;\r
-  reg_SPI_READY_OUT <= LOC_READY_IN;\r
+  if (out_delay = "000") then\r
+    reg_SPI_DATA_OUT  <= LOC_DATA_IN;\r
+    reg_SPI_READY_OUT <= LOC_READY_IN;\r
+  end if;\r
+  \r
   \r
   ram_write_i <= '0';\r
   ram_data_i <= x"00";\r
@@ -211,10 +223,13 @@ PROC_SELECTOR : process begin
     elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then\r
       reg_LOC_WRITE_OUT <= '0';\r
       enable_cfg_flash <= SPI_DATA_IN(0);\r
-      master_start_reg <= SPI_DATA_IN(1);\r
+      master_start_reg <= SPI_DATA_IN(4);\r
     elsif (SPI_ADDR_IN(7 downto 0) = x"5d") then\r
       reg_LOC_WRITE_OUT <= '0';\r
-      memreg <= SPI_DATA_IN; \r
+      memreg <= SPI_DATA_IN;\r
+    elsif (SPI_ADDR_IN(7 downto 0) = x"5f") then\r
+      reg_LOC_WRITE_OUT <= '0';\r
+      testreg <= SPI_DATA_IN;\r
     elsif (SPI_ADDR_IN(7 downto 0) = x"50") then\r
       reg_LOC_WRITE_OUT <= '0';\r
       spi_flash_command <= SPI_DATA_IN(15 downto 13);\r
@@ -223,7 +238,7 @@ PROC_SELECTOR : process begin
       else\r
         spi_flash_page <= "111" & SPI_DATA_IN(9 downto 0);\r
       end if;\r
-      spi_flash_go <= '1';      \r
+      spi_flash_go <= '1';\r
     end if;\r
   end if;\r
 \r
@@ -233,12 +248,9 @@ PROC_SELECTOR : process begin
     reg_LOC_DATA_OUT  <= master_DATA_OUT;\r
     reg_LOC_ADDR_OUT  <= master_ADDR_OUT;\r
   end if;\r
-  \r
-  if (DATA_BUS_WIDTH > 16) then\r
-    reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 16) <= (others => '0');\r
-  end if;\r
 \r
   if (out_delay = "001") then\r
+    reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');\r
     reg_LOC_READ_OUT  <= '0';\r
     reg_SPI_READY_OUT <= '0';\r
     if (memreg(0) = '1') then\r
@@ -316,6 +328,7 @@ PROC_SELECTOR : process begin
   \r
   if (SPI_READ_IN = '1') then    \r
     if (SPI_ADDR_IN(7 downto 4) = x"4" and burst_counter = "0000") then\r
+      reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');\r
       out_delay <= "001";\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '0';\r
@@ -324,22 +337,25 @@ PROC_SELECTOR : process begin
     elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
-      reg_SPI_DATA_OUT(15 downto 0) <= x"01" & "00000" & master_running & master_start_reg & enable_cfg_flash;\r
+      reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');\r
+      reg_SPI_DATA_OUT(15 downto 0) <= x"00" & "00" & master_running & master_start_reg & '0' & flash_busy & flash_err & enable_cfg_flash;\r
     elsif (SPI_ADDR_IN(7 downto 0) = x"5d") then\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
       reg_SPI_DATA_OUT  <= memreg;\r
+      reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');\r
       reg_SPI_DATA_OUT(11 downto 8) <= burst_counter;\r
       -- reg_SPI_DATA_OUT(15 downto 0) <= auto_dbg & "00" & master_flash_page;\r
     elsif (SPI_ADDR_IN(7 downto 0) = x"5e") then\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
+      reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');\r
       reg_SPI_DATA_OUT  <= master_DATA_OUT;\r
     elsif (SPI_ADDR_IN(7 downto 0) = x"5f") then\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
-      -- reg_SPI_DATA_OUT  <= testreg;\r
-      reg_SPI_DATA_OUT(15 downto 0)  <= x"000" & master_word_counter;\r
+      reg_SPI_DATA_OUT  <= testreg;\r
+      --reg_SPI_DATA_OUT(15 downto 0)  <= x"000" & master_word_counter;\r
     end if;\r
   end if;\r
   \r
@@ -411,10 +427,13 @@ begin
         state <= WaitRAM1;\r
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
       when WaitRAM1 =>\r
-        if (ram_data_o = x"01") then --Version OK\r
+        if (ram_data_o = x"01") then --Version: 16 Bit\r
           state <= WaitRAM2;\r
           master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
-        else\r
+        elsif (ram_data_o = x"02" and DATA_BUS_WIDTH > 24) then --Version: 32 Bit\r
+          state <= WaitRAM2_32;\r
+          master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
+        else -- break\r
           master_DATA_OUT(15 downto 0) <= x"ff" & ram_data_o;\r
           state <= IDLE;\r
         end if;\r
@@ -422,13 +441,34 @@ begin
         master_ADDR_OUT <= ram_data_o;\r
         state <= WaitRAM3;\r
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
+      when WaitRAM2_32 =>\r
+        master_ADDR_OUT <= ram_data_o;\r
+        state <= WaitRAM3_32;\r
+        master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
       when WaitRAM3 =>\r
         master_DATA_OUT(15 downto 0) <= ram_data_o & x"00";\r
         state <= WaitRAM4;\r
+      when WaitRAM3_32 =>\r
+        master_DATA_OUT(31 downto 0) <= ram_data_o & x"000000";\r
+        master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
+        state <= WaitRAM4_32;\r
       when WaitRAM4 =>\r
         master_DATA_OUT(15 downto 0) <= master_DATA_OUT(15 downto 8) & ram_data_o;\r
         state <= WriteSPI;\r
         master_WRITE_OUT <= '1';\r
+      when WaitRAM4_32 =>\r
+        master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 24) & ram_data_o & x"0000";\r
+        master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
+        state <= WaitRAM5_32;\r
+      when WaitRAM5_32 =>\r
+        master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 16) & ram_data_o & x"00";\r
+        master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 2);\r
+               -- padding bytes\r
+        state <= WaitRAM6_32;\r
+      when WaitRAM6_32 =>\r
+        master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 8) & ram_data_o;\r
+        state <= WriteSPI;\r
+        master_WRITE_OUT <= '1';\r
       when WriteSPI =>\r
         -- prepare for next cycle\r
         if (master_word_counter = x"F") then\r