Update CTS with TDC

diff --git a/cts/config.vhd b/cts/config.vhd
index 544db101d50191c71376892a52129833ad2a3da4..bde78a7041f945c5f96abab6d2875bff5b7b9b7e 100644 (file)
--- a/cts/config.vhd
+++ b/cts/config.vhd
@@ -13,7 +13,7 @@ package config is
 
 --design options: backplane or front SFP, with or without GBE
     constant USE_BACKPLANE : integer := c_NO;
-    constant USE_ADDON     : integer := c_NO;
+    constant USE_ADDON     : integer := c_YES;
     constant INCLUDE_GBE   : integer := c_YES;  --c_NO doesn't work
 
 --Runs with 120 MHz instead of 100 MHz     
@@ -169,7 +169,7 @@ package body config is
   constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
   constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
 
-  constant CFG_MODE : integer := USE_ADDON*2 + USE_BACKPLANE;
+  constant CFG_MODE : integer := USE_ADDON;--*2 + USE_BACKPLANE;
   
   constant INTERFACE_NUM        : integer := INTERFACE_NUM_ARR(CFG_MODE);
   constant IS_UPLINK            : hub_ct  := IS_UPLINK_ARR(CFG_MODE);
@@ -203,6 +203,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE
     t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
     t(26 downto 24) := std_logic_vector(to_unsigned(SFP_NUM_ARR(CFG_MODE),3)); --num SFPs with TrbNet
+    t(28 downto 28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1));
     t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));

diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf
index 15546caa9556d2b0b6a468b8e88d8b5c20c14fd5..4ec992ea611900c2cb2bc25a445c312f7a52d3f9 100644 (file)
--- a/cts/trb3sc_cts.lpf
+++ b/cts/trb3sc_cts.lpf
@@ -8,7 +8,8 @@ LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB";
 LOCATE COMP "gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC";
 LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
 
-
+BLOCK PATH FROM CELL THE_TDC/calibration_o*;
+BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*;
 
 REGION         "MEDIA_DOWN1" "R102C40D" 13 100;
 #LOCATE UGROUP  "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ; 

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 8f06f06321b9f67f151c16257cf9ee9b05876b22..4b5e3604482e0ac0f8c85054024e7e5b048f2880 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -279,13 +279,7 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
   end process;      
 
 
-  pll_calibration : entity work.pll_in125_out33
-    port map (
-      CLK   => CLK_SUPPL_PCLK,
-      CLKOP => clk_cal,
-      LOCK  => open);
-  
-  
+
 ---------------------------------------------------------------------------
 -- PCSA
 ---------------------------------------------------------------------------    
@@ -912,7 +906,7 @@ end generate;
       CLK_READOUT        => clk_sys,    -- Clock for the readout
       REFERENCE_TIME     => cts_trigger_out,  -- Reference time input
       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
+      HIT_CAL_IN         => CLK_SUPPL_PCLK,    -- Hits for calibrating the TDC
       -- Trigger signals from handler
       BUSRDO_RX          => cts_rdo_rx,
       BUSRDO_TX          => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR),