add automatic ADC reader to Trb5sc designs

diff --git a/gbe_standalone/config.vhd b/gbe_standalone/config.vhd
index c91c17889787a8a06a77a271b6ce448e0ec2ac60..381e7d9b0b8b0e444ceeb49fdf84648505adce0b 100644 (file)
--- a/gbe_standalone/config.vhd
+++ b/gbe_standalone/config.vhd
@@ -49,6 +49,7 @@ package config is
    
     constant INCLUDE_UART           : integer  := c_YES;  --300 slices
     constant INCLUDE_SPI            : integer  := c_YES; --300 slices
+    constant INCLUDE_ADC            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_NO;  --800 slices
     constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO; --300 slices
 

diff --git a/gbe_standalone/trb5sc_gbe_template.prj b/gbe_standalone/trb5sc_gbe_template.prj
index b88dd1c7dfe29c2b32c8a5608e8175e79b46b629..9cd3de699acf2085de29705090dea2c45b51a02e 100644 (file)
--- a/gbe_standalone/trb5sc_gbe_template.prj
+++ b/gbe_standalone/trb5sc_gbe_template.prj
@@ -116,6 +116,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/gbe_standalone/trb5sc_gbe_template.vhd b/gbe_standalone/trb5sc_gbe_template.vhd
index 0303ba80e5da458422e2733a2c3f6e797460dcb4..4ca55d37dc3d089a476b798ac8b00a6d9934ebaf 100644 (file)
--- a/gbe_standalone/trb5sc_gbe_template.vhd
+++ b/gbe_standalone/trb5sc_gbe_template.vhd
@@ -330,6 +330,13 @@ begin
 -- Control Tools
 -------------------------------------------------------------------------------
   THE_TOOLS : entity work.trb3sc_tools
+    generic map(
+      ADC_CMD_1        => x"2c3cb",
+      ADC_CMD_2        => x"1d5cb",
+      ADC_CMD_3        => x"1e3cb",
+      ADC_CMD_4        => x"2f5cb",
+      ADC_CMD_T        => x"1F393"  
+      )
     port map(
       CLK   => clk_sys,
       RESET => reset_i,

diff --git a/mimosis/config.vhd b/mimosis/config.vhd
index b2db4446f90045d0671b3d11f5f2f89c2bde8455..4b4a76ae833ea57ebb399a9707cfda45f17edc08 100644 (file)
--- a/mimosis/config.vhd
+++ b/mimosis/config.vhd
@@ -51,6 +51,7 @@ package config is
    
     constant INCLUDE_UART           : integer  := c_NO;  --300 slices
     constant INCLUDE_SPI            : integer  := c_NO; --300 slices
+    constant INCLUDE_ADC            : integer  := c_YES; 
     constant INCLUDE_LCD            : integer  := c_NO;  --800 slices
     constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO; --300 slices
 

diff --git a/mimosis/trb5sc_mimosis.prj b/mimosis/trb5sc_mimosis.prj
index 79f9de9a5c1946913f3716a554e99124060df0f3..da91664df1446c9043ca2702e797aa800b782af4 100644 (file)
--- a/mimosis/trb5sc_mimosis.prj
+++ b/mimosis/trb5sc_mimosis.prj
@@ -117,6 +117,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd
index c38e9795075697823a8c76c68eb53c8bccf32974..748735ea878244e0263b383841cc166bf630522f 100644 (file)
--- a/mimosis/trb5sc_mimosis.vhd
+++ b/mimosis/trb5sc_mimosis.vhd
@@ -346,6 +346,13 @@ RJ(0) <= clk_40;
 -- Control Tools\r
 ---------------------------------------------------------------------------\r
   THE_TOOLS : entity work.trb3sc_tools\r
+    generic map(\r
+      ADC_CMD_1        => x"2c3cb",\r
+      ADC_CMD_2        => x"1d5cb",\r
+      ADC_CMD_3        => x"1e3cb",\r
+      ADC_CMD_4        => x"2f5cb",\r
+      ADC_CMD_T        => x"1F393"  \r
+      )\r
     port map(\r
       CLK   => clk_sys,\r
       RESET => reset_i,\r

diff --git a/template/config.vhd b/template/config.vhd
index da29651cbc764dc6255069646554c55051b8ab04..1973faf5e08a368611b8ab35db97b2a2f3e9dd1a 100644 (file)
--- a/template/config.vhd
+++ b/template/config.vhd
@@ -49,6 +49,7 @@ package config is
    
     constant INCLUDE_UART           : integer  := c_YES;  --300 slices
     constant INCLUDE_SPI            : integer  := c_YES; --300 slices
+    constant INCLUDE_ADC            : integer  := c_YES;
     constant INCLUDE_LCD            : integer  := c_NO;  --800 slices
     constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO; --300 slices
 

diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj
index 1212a8547997b31b643e059323623205d271ef47..ab9a75ddcd08846ec1120c1b0512beb5876dba05 100644 (file)
--- a/template/trb5sc_template.prj
+++ b/template/trb5sc_template.prj
@@ -114,6 +114,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/template/trb5sc_template.vhd b/template/trb5sc_template.vhd
index 36132553a8e029eb8ac0eb9ed1ad18de325b28fc..4b0c911c48ccb243cb8f3a0fab2c93810225b64a 100644 (file)
--- a/template/trb5sc_template.vhd
+++ b/template/trb5sc_template.vhd
@@ -303,6 +303,13 @@ THE_CAL_PLL : entity work.pll_in125_out50
 -- Control Tools
 ---------------------------------------------------------------------------
   THE_TOOLS : entity work.trb3sc_tools
+    generic map(
+      ADC_CMD_1        => x"2c3cb",
+      ADC_CMD_2        => x"1d5cb",
+      ADC_CMD_3        => x"1e3cb",
+      ADC_CMD_4        => x"2f5cb",
+      ADC_CMD_T        => x"1F393"  
+      )
     port map(
       CLK   => clk_sys,
       RESET => reset_i,