CON : out std_logic_vector(16 downto 1);\r
INP : in std_logic_vector(16 downto 1);\r
PWM : out std_logic_vector(16 downto 1);\r
- SPARE_LINE : out std_logic_vector(5 downto 0);\r
+ SPARE_LINE : out std_logic_vector(3 downto 0);\r
+ SPARE_LVDS : out std_logic;\r
LED_GREEN : out std_logic;\r
LED_ORANGE : out std_logic;\r
LED_RED : out std_logic;\r
);\r
end component;\r
\r
+component PUR port(PUR : in std_logic); end component;\r
+component GSR port(GSR : in std_logic); end component;\r
+ \r
+\r
\r
attribute NOM_FREQ : string;\r
attribute NOM_FREQ of clk_source : label is "133.00";\r
signal ram_addr_i: std_logic_vector(3 downto 0);\r
signal temperature_i : std_logic_vector(11 downto 0);\r
\r
+type idram_t is array(0 to 7) of std_logic_vector(15 downto 0);\r
+signal idram : idram_t;\r
type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);\r
-signal idram : ram_t;\r
signal ram : ram_t;\r
\r
signal pwm_i : std_logic_vector(31 downto 0);\r
signal spi_operation_i : std_logic_vector(3 downto 0);\r
signal spi_channel_i : std_logic_vector(7 downto 0);\r
signal spi_write_i : std_logic_vector(15 downto 0);\r
+signal buf_SPI_OUT : std_logic;\r
+signal spi_debug_i : std_logic_vector(15 downto 0);\r
\r
signal pll_lock : std_logic;\r
-signal clk_33 : std_logic;\r
+signal clk_26 : std_logic;\r
signal clk_osc : std_logic;\r
\r
signal flashram_addr_i : std_logic_vector(3 downto 0);\r
signal flash_busy : std_logic;\r
signal flash_err : std_logic;\r
\r
+signal inp_select : integer range 0 to 15 := 0;\r
+signal input_enable : std_logic_vector(15 downto 0);\r
+signal inp_status : std_logic_vector(15 downto 0);\r
+signal led_status : std_logic_vector(4 downto 0);\r
+\r
+signal timer : unsigned(18 downto 0) := (others => '0');\r
+signal last_inp : std_logic_vector(3 downto 0) := (others => '0');\r
+signal leds : std_logic_vector(3 downto 0) := (others => '0');\r
+signal last_leds: std_logic_vector(3 downto 0) := (others => '0');\r
+signal onewire_monitor : std_logic;\r
+signal onewire_reset : std_logic;\r
+\r
begin\r
\r
-PROC_RESET : process begin\r
- wait until rising_edge(clk_i);\r
- reset_i <= not pll_lock;\r
- if reset_cnt /= x"F" then\r
- reset_cnt <= reset_cnt + 1;\r
- reset_i <= '1';\r
- end if;\r
-end process;\r
+-- PROC_RESET : process begin\r
+-- wait until rising_edge(clk_osc);\r
+-- reset_i <= not pll_lock;\r
+-- -- if reset_cnt /= x"F" then\r
+-- -- reset_cnt <= reset_cnt + 1;\r
+-- -- reset_i <= '1';\r
+-- -- end if;\r
+-- end process;\r
\r
\r
\r
THE_PLL : pll\r
port map(\r
CLKI => clk_osc,\r
- CLKOP => clk_33, --33\r
+ CLKOP => clk_26, --33\r
CLKOS => clk_i, --133\r
- LOCK => pll_lock\r
+ LOCK => pll_lock --no lock available!\r
);\r
\r
---------------------------------------------------------------------------\r
SPI_CLK => SPI_CLK,\r
SPI_CS => SPI_CS,\r
SPI_IN => SPI_IN,\r
- SPI_OUT => SPI_OUT,\r
+ SPI_OUT => buf_SPI_OUT,\r
DATA_OUT => spi_data_i,\r
REG00_IN => spi_reg00_i,\r
REG10_IN => spi_reg10_i,\r
OPERATION_OUT => spi_operation_i,\r
CHANNEL_OUT => spi_channel_i,\r
WRITE_OUT => spi_write_i,\r
- DEBUG_OUT => open\r
+ DEBUG_OUT => spi_debug_i\r
);\r
\r
- \r
+SPI_OUT <= buf_SPI_OUT; \r
---------------------------------------------------------------------------\r
-- RAM Interface\r
--------------------------------------------------------------------------- \r
AddressA => ram_addr_i,\r
AddressB => flashram_addr_i,\r
ClockA => clk_i, \r
- ClockB => clk_33,\r
+ ClockB => clk_26,\r
ClockEnA => '1',\r
ClockEnB => flashram_cen_i,\r
WrA => ram_write_i, \r
-- Flash Controller\r
--------------------------------------------------------------------------- \r
\r
-THE_FLASH : UFM_WB\r
- port map(\r
- clk_i => clk_33,\r
- rst_n => '1',\r
- cmd => flash_command,\r
- ufm_page => flash_page,\r
- GO => flash_go,\r
- BUSY => flash_busy,\r
- ERR => flash_err,\r
- mem_clk => open,\r
- mem_we => flashram_write_i,\r
- mem_ce => flashram_cen_i,\r
- mem_addr => flashram_addr_i,\r
- mem_wr_data => flashram_data_i,\r
- mem_rd_data => flashram_data_o\r
- );\r
+-- THE_FLASH : UFM_WB\r
+-- port map(\r
+-- clk_i => clk_26,\r
+-- rst_n => '1',\r
+-- cmd => flash_command,\r
+-- ufm_page => flash_page,\r
+-- GO => flash_go,\r
+-- BUSY => flash_busy,\r
+-- ERR => flash_err,\r
+-- mem_clk => open,\r
+-- mem_we => flashram_write_i,\r
+-- mem_ce => flashram_cen_i,\r
+-- mem_addr => flashram_addr_i,\r
+-- mem_wr_data => flashram_data_i,\r
+-- mem_rd_data => flashram_data_o\r
+-- );\r
\r
\r
+-- PUR_INST : PUR port map(PUR=>'1');\r
+-- GSR_INST : GSR port map(GSR=>'1');\r
---------------------------------------------------------------------------\r
-- PWM\r
--------------------------------------------------------------------------- \r
PWM => pwm_i\r
);\r
\r
+ PWM <= pwm_i(15 downto 0);\r
\r
-PWM_ODDR : oddr16\r
- port map(\r
- clk => clk_i,\r
- clkout => open,\r
- reset => '0',\r
- sclk => open,\r
- dataout => pwm_i,\r
- dout => PWM\r
- );\r
+-- PWM_ODDR : oddr16\r
+-- port map(\r
+-- clk => clk_i,\r
+-- clkout => open,\r
+-- reset => '0',\r
+-- sclk => open,\r
+-- dataout => pwm_i,\r
+-- dout => PWM\r
+-- );\r
\r
\r
\r
\r
THE_ONEWIRE : trb_net_onewire\r
generic map(\r
- CLK_PERIOD => 30\r
+ USE_TEMPERATURE_READOUT => 1,\r
+ PARASITIC_MODE => c_NO,\r
+ CLK_PERIOD => 40\r
)\r
port map(\r
- CLK => clk_33,\r
- RESET => reset_i,\r
+ CLK => clk_26,\r
+ RESET => onewire_reset,\r
READOUT_ENABLE_IN => '1',\r
ONEWIRE => TEMP_LINE,\r
- MONITOR_OUT => open,\r
+ MONITOR_OUT => onewire_monitor,\r
--connection to id ram, according to memory map in TrbNetRegIO\r
DATA_OUT => id_data_i,\r
ADDR_OUT => id_addr_i,\r
else\r
idram(4) <= "0000" & temperature_i;\r
end if;\r
- spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(3 downto 0))));\r
+ spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0))));\r
+ \r
+ if spi_write_i(1) = '1' then\r
+ onewire_reset <= spi_data_i(0);\r
+ end if;\r
+end process;\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- I/O Register 0x20\r
+--------------------------------------------------------------------------- \r
+THE_IO_REG_READ : process begin\r
+ wait until rising_edge(clk_i);\r
+ if spi_channel_i(4) = '0' then\r
+ case spi_channel_i(3 downto 0) is\r
+ when x"0" => spi_reg20_i <= input_enable;\r
+ when x"1" => spi_reg20_i <= inp_status;\r
+ when x"2" => spi_reg20_i <= x"00" & "000" & led_status(4) & leds;\r
+ when x"3" => spi_reg20_i <= x"000" & std_logic_vector(to_unsigned(inp_select,4));\r
+ when others => null;\r
+ end case;\r
+ else\r
+ case spi_channel_i(3 downto 0) is\r
+ when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
+ when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
+ when others => null;\r
+ end case;\r
+ end if;\r
+end process;\r
+\r
+THE_IO_REG_WRITE : process begin\r
+ wait until rising_edge(clk_i);\r
+ if spi_write_i(2) = '1' then\r
+ case spi_channel_i(3 downto 0) is\r
+ when x"0" => input_enable <= spi_data_i;\r
+ when x"1" => null;\r
+ when x"2" => led_status <= spi_data_i(4 downto 0);\r
+ when x"3" => inp_select <= to_integer(unsigned(spi_data_i(3 downto 0)));\r
+ when others => null;\r
+ end case;\r
+ end if;\r
end process;\r
- \r
+\r
+inp_status <= INP when rising_edge(clk_i);\r
+last_inp <= inp_status(3 downto 0) when rising_edge(clk_i);\r
+---------------------------------------------------------------------------\r
+-- LED blinking when activity on inputs\r
+---------------------------------------------------------------------------\r
+PROC_TIMER : process begin\r
+ wait until rising_edge(clk_i);\r
+ timer <= timer + 1;\r
+ leds <= (last_inp xor inp_status(3 downto 0)) or leds or last_leds;\r
+ if timer = 0 then\r
+ leds <= not inp_status(3 downto 0);\r
+ last_leds <= x"0";\r
+ end if;\r
+end process;\r
+\r
\r
---------------------------------------------------------------------------\r
-- Rest of the I/O\r
---------------------------------------------------------------------------\r
-CON <= INP;\r
+CON <= INP and not input_enable;\r
+\r
+SPARE_LINE(0) <= '0'; --clk_26;\r
+SPARE_LINE(1) <= '0'; --clk_i;\r
+SPARE_LINE(2) <= '0'; --timer(18);\r
+SPARE_LINE(3) <= '0';\r
\r
+SPARE_LVDS <= INP(inp_select+1);\r
\r
-SPARE_LINE <= (others => '0');\r
+-- TEST_LINE(0) <= '0';\r
+-- TEST_LINE(15 downto 1) <= (others => '0');\r
\r
-TEST_LINE(0) <= '0';\r
-TEST_LINE(15 downto 1) <= (others => '0');\r
+TEST_LINE(7 downto 0) <= spi_debug_i(7 downto 0);\r
+TEST_LINE(10 downto 8) <= id_addr_i(2 downto 0);\r
+TEST_LINE(11) <= onewire_monitor;\r
+TEST_LINE(12) <= id_write_i;\r
+TEST_LINE(15 downto 13) <= id_data_i(2 downto 0);\r
\r
-LED_GREEN <= '0';\r
-LED_ORANGE <= '0';\r
-LED_RED <= '0';\r
-LED_YELLOW <= '0';\r
+LED_GREEN <= not leds(0) when led_status(4) = '0' else not led_status(0);\r
+LED_ORANGE <= not leds(1) when led_status(4) = '0' else not led_status(1);\r
+LED_RED <= not leds(2) when led_status(4) = '0' else not led_status(2);\r
+LED_YELLOW <= not leds(3) when led_status(4) = '0' else not led_status(3);\r
\r
end architecture;\r
\r
+++ /dev/null
-
-# implementation: "workdir"
-impl -add workdir -type fpga
-
-# device options
-set_option -technology LATTICE-ECP3
-set_option -part LFE3_150EA
-set_option -package FN672C
-set_option -speed_grade -8
-set_option -part_companion ""
-
-# compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
-set_option -top_module "trb3_periph_wasa"
-set_option -resource_sharing true
-
-# map options
-set_option -frequency 200
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-#set_option -force_gsr
-set_option -force_gsr false
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-set_option -compiler_compatible true
-
-
-# simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 1
-
-# automatic place and route (vendor) options
-set_option -write_apr_constraint 0
-
-# set result format/file last
-project -result_format "edif"
-project -result_file "workdir/trb3_periph_wasa.edf"
-
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-impl -active "workdir"
-
-####################
-
-
-
-#add_file options
-
-add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib "work" "../base/trb3_components.vhd"
-
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
-
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
-
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
-add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
-
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
-
-add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-
-add_file -vhdl -lib "work" "trb3_periph_wasa.vhd"
-
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Adder_304.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/bit_sync.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Encoder_304_Bit.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/FIFO_32x32_OutReg.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/Reference_channel.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/ROM_encoder_3.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/ROM_FIFO.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/TDC.vhd"
-add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.3/up_counter.vhd"
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.version.all;
-
-
-
-entity trb3_periph_wasa is
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 6
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 4 <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Manager 3
- CLK_PCLK_RIGHT : in std_logic; --Clock Manager 1
- --CLK_PCLK_RIGHT is the only clock with external termination !?
- CLK_EXTERNAL : in std_logic; --Clock Manager 9
-
-
--- --Trigger
--- TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
--- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
-
- --Serdes
- CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used
- SERDES_TX : out std_logic_vector(1 downto 0);
- SERDES_RX : in std_logic_vector(1 downto 0);
- SFP_TXDIS : out std_logic;
- SFP_MOD : inout std_logic_vector(2 downto 0);
- SFP_LOS : in std_logic;
-
- --Connections
- SPARE_LINE : inout std_logic_vector( 2 downto 0); --LVDS, ext. termination, 1 used for trigger
- LVDS : inout std_logic_vector( 2 downto 1);
- INPUT : in std_logic_vector(64 downto 1);
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --DAC
- DAC_SDO : in std_logic;
- DAC_SDI : out std_logic;
- DAC_SCK : out std_logic;
- DAC_CS : out std_logic;
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- LED_CLK_GREEN : out std_logic;
- LED_CLK_RED : out std_logic;
- LED_SFP_GREEN : out std_logic;
- LED_SFP_RED : out std_logic;
-
- CLK_MNGR_USER : inout std_logic_vector(3 downto 0);
-
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
-
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of LED_CLK_GREEN : signal is false;
- attribute syn_useioff of LED_CLK_RED : signal is false;
- attribute syn_useioff of LED_SFP_RED : signal is false;
- attribute syn_useioff of LED_SFP_GREEN : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
-
- --important signals _with_ IO-FF
- attribute syn_useioff of DAC_SCK : signal is true;
- attribute syn_useioff of DAC_CS : signal is true;
- attribute syn_useioff of DAC_SDI : signal is true;
- attribute syn_useioff of DAC_SDO : signal is true;
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of TEST_LINE : signal is true;
- attribute syn_useioff of SPARE_LINE : signal is true;
- attribute syn_useioff of LVDS : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_wasa_arch of trb3_periph_wasa is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 5;
- constant REGIO_NUM_CTRL_REGS : integer := 3;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- --Clock / Reset
- signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
-
- --Media Interface
- signal med_stat_op : std_logic_vector (1*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
- signal med_data_out : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_out : std_logic;
- signal med_read_out : std_logic;
- signal med_data_in : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_in : std_logic;
- signal med_read_in : std_logic;
-
- --LVL1 channel
- signal timing_trg_received_i : std_logic;
- signal trg_data_valid_i : std_logic;
- signal trg_timing_valid_i : std_logic;
- signal trg_notiming_valid_i : std_logic;
- signal trg_invalid_i : std_logic;
- signal trg_type_i : std_logic_vector(3 downto 0);
- signal trg_number_i : std_logic_vector(15 downto 0);
- signal trg_code_i : std_logic_vector(7 downto 0);
- signal trg_information_i : std_logic_vector(23 downto 0);
- signal trg_int_number_i : std_logic_vector(15 downto 0);
- signal trg_multiple_trg_i : std_logic;
- signal trg_timeout_detected_i: std_logic;
- signal trg_spurious_trg_i : std_logic;
- signal trg_missing_tmg_trg_i : std_logic;
- signal trg_spike_detected_i : std_logic;
-
- --Data channel
- signal fee_trg_release_i : std_logic;
- signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
- signal fee_data_i : std_logic_vector(31 downto 0);
- signal fee_data_write_i : std_logic;
- signal fee_data_finished_i : std_logic;
- signal fee_almost_full_i : std_logic;
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spictrl_read_en : std_logic;
- signal spictrl_write_en : std_logic;
- signal spictrl_data_in : std_logic_vector(31 downto 0);
- signal spictrl_addr : std_logic;
- signal spictrl_data_out : std_logic_vector(31 downto 0);
- signal spictrl_ack : std_logic;
- signal spictrl_busy : std_logic;
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(5 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_ack : std_logic;
-
- signal dac_read_en : std_logic;
- signal dac_write_en : std_logic;
- signal dac_data_in : std_logic_vector(31 downto 0);
- signal dac_addr : std_logic_vector(4 downto 0);
- signal dac_data_out : std_logic_vector(31 downto 0);
- signal dac_ack : std_logic;
- signal dac_busy : std_logic;
-
- signal spi_bram_addr : std_logic_vector(7 downto 0);
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);
- signal spi_bram_we : std_logic;
-
-
- --FPGA Test
- signal time_counter : unsigned(31 downto 0);
-
- --TDC
- signal hit_in_i : std_logic_vector(64 downto 1);
-
- --TDC component
- component TDC
- generic (
- CHANNEL_NUMBER : integer range 1 to 65;
- STATUS_REG_NR : integer range 0 to 6;
- CONTROL_REG_NR : integer range 0 to 6);
- port (
- RESET : in std_logic;
- CLK_TDC : in std_logic;
- CLK_READOUT : in std_logic;
- REFERENCE_TIME : in std_logic;
- HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1);
- TRG_WIN_PRE : in std_logic_vector(10 downto 0);
- TRG_WIN_POST : in std_logic_vector(10 downto 0);
- TRG_DATA_VALID_IN : in std_logic;
- VALID_TIMING_TRG_IN : in std_logic;
- VALID_NOTIMING_TRG_IN : in std_logic;
- INVALID_TRG_IN : in std_logic;
- TMGTRG_TIMEOUT_IN : in std_logic;
- SPIKE_DETECTED_IN : in std_logic;
- MULTI_TMG_TRG_IN : in std_logic;
- SPURIOUS_TRG_IN : in std_logic;
- TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- TRG_CODE_IN : in std_logic_vector(7 downto 0);
- TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- TRG_TYPE_IN : in std_logic_vector(3 downto 0);
- TRG_RELEASE_OUT : out std_logic;
- TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0);
- DATA_OUT : out std_logic_vector(31 downto 0);
- DATA_WRITE_OUT : out std_logic;
- DATA_FINISHED_OUT : out std_logic;
- TDC_DEBUG : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0);
- LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0);
- CONTROL_REG_IN : in std_logic_vector(32*2**CONTROL_REG_NR-1 downto 0));
- end component;
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_i,
- CLKOK => clk_200_i,
- LOCK => pll_lock
- );
-
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => c_YES, --run on 200 MHz clock
- USE_CTC => c_YES --CTC required
- )
- port map(
- CLK => clk_200_i,
- SYSCLK => clk_100_i,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
- REFCLK2CORE_OUT => open,
- --SFP Connection
- SD_RXD_P_IN => SERDES_RX(0),
- SD_RXD_N_IN => SERDES_RX(1),
- SD_TXD_P_OUT => SERDES_TX(0),
- SD_TXD_N_OUT => SERDES_TX(1),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
- SD_PRSNT_N_IN => SFP_MOD(0),
- SD_LOS_IN => '0',
- SD_TXDIS_OUT => SFP_TXDIS,
- -- Status and control port
- STAT_OP => med_stat_op,
- CTRL_OP => med_ctrl_op,
- STAT_DEBUG => med_stat_debug,
- CTRL_DEBUG => (others => '0')
- );
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"50",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"92000000",
- REGIO_INIT_ADDRESS => x"f300",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => 100,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 13, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**13-800,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 2**9-16
- )
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out, -- open, --
- MED_DATA_OUT => med_data_out, -- open, --
- MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out, -- open, --
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
- LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
- LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
- LVL1_INVALID_TRG_OUT => trg_invalid_i,
-
- LVL1_TRG_TYPE_OUT => trg_type_i,
- LVL1_TRG_NUMBER_OUT => trg_number_i,
- LVL1_TRG_CODE_OUT => trg_code_i,
- LVL1_TRG_INFORMATION_OUT => trg_information_i,
- LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
- TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
- TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
- TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
- TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,
- FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,
- FEE_DATA_IN => fee_data_i,
- FEE_DATA_WRITE_IN(0) => fee_data_write_i,
- FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,
- FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-
----------------------------------------------------------------------------
--- I/O
----------------------------------------------------------------------------
-timing_trg_received_i <= SPARE_LINE(0);
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", others => x"0000"),
- PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, others => 0)
- )
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI CTRL)
- BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
- BUS_ADDR_OUT(0*16) => spictrl_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
- BUS_DATAREADY_IN(0) => spictrl_ack,
- BUS_WRITE_ACK_IN(0) => spictrl_ack,
- BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
- BUS_UNKNOWN_ADDR_IN(0) => '0',
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
- BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
- BUS_DATAREADY_IN(1) => spimem_ack,
- BUS_WRITE_ACK_IN(1) => spimem_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- --DAC
- BUS_READ_ENABLE_OUT(2) => dac_read_en,
- BUS_WRITE_ENABLE_OUT(2) => dac_write_en,
- BUS_DATA_OUT(2*32+31 downto 2*32) => dac_data_in,
- BUS_ADDR_OUT(2*16+4 downto 2*16) => dac_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATA_IN(2*32+31 downto 2*32) => dac_data_out,
- BUS_DATAREADY_IN(2) => dac_ack,
- BUS_WRITE_ACK_IN(2) => dac_ack,
- BUS_NO_MORE_DATA_IN(2) => dac_busy,
- BUS_UNKNOWN_ADDR_IN(2) => '0',
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
- THE_SPI_MASTER : spi_master
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_READ_IN => spictrl_read_en,
- BUS_WRITE_IN => spictrl_write_en,
- BUS_BUSY_OUT => spictrl_busy,
- BUS_ACK_OUT => spictrl_ack,
- BUS_ADDR_IN(0) => spictrl_addr,
- BUS_DATA_IN => spictrl_data_in,
- BUS_DATA_OUT => spictrl_data_out,
- -- SPI connections
- SPI_CS_OUT => FLASH_CS,
- SPI_SDI_IN => FLASH_DOUT,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SCK_OUT => FLASH_CLK,
- -- BRAM for read/write data
- BRAM_A_OUT => spi_bram_addr,
- BRAM_WR_D_IN => spi_bram_wr_d,
- BRAM_RD_D_OUT => spi_bram_rd_d,
- BRAM_WE_OUT => spi_bram_we,
- -- Status lines
- STAT => open
- );
-
--- data memory for SPI accesses
- THE_SPI_MEMORY : spi_databus_memory
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_ACK_OUT => spimem_ack,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
- -- state machine connections
- BRAM_ADDR_IN => spi_bram_addr,
- BRAM_WR_D_OUT => spi_bram_wr_d,
- BRAM_RD_D_IN => spi_bram_rd_d,
- BRAM_WE_IN => spi_bram_we,
- -- Status lines
- STAT => open
- );
-
----------------------------------------------------------------------------
--- DAC
----------------------------------------------------------------------------
- THE_DAC_SPI : spi_ltc2600
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_ADDR_IN => dac_addr,
- BUS_READ_IN => dac_read_en,
- BUS_WRITE_IN => dac_write_en,
- BUS_ACK_OUT => dac_ack,
- BUS_BUSY_OUT => dac_busy,
- BUS_DATA_IN => dac_data_in,
- BUS_DATA_OUT => dac_data_out,
- -- SPI connections
- SPI_CS_OUT(0) => DAC_CS,
- SPI_SDI_IN => DAC_SDO,
- SPI_SDO_OUT => DAC_SDI,
- SPI_SCK_OUT => DAC_SCK
- );
-
----------------------------------------------------------------------------
--- Reboot FPGA
----------------------------------------------------------------------------
- THE_FPGA_REBOOT : fpga_reboot
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
- DO_REBOOT => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN
- );
-
-
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_GREEN <= not time_counter(24);
- LED_ORANGE <= not time_counter(25);
- LED_RED <= not time_counter(26);
- LED_YELLOW <= not time_counter(27);
- LED_SFP_GREEN <= not med_stat_op(9);
- LED_SFP_RED <= not (med_stat_op(10) or med_stat_op(11));
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------
--- TEST_LINE(15 downto 0) <= (others => '0');
-
-
- LVDS <= INPUT(2 downto 1);
-
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- process
- begin
- wait until rising_edge(clk_100_i);
- time_counter <= time_counter + 1;
- end process;
-
--------------------------------------------------------------------------------
--- TDC
--------------------------------------------------------------------------------
- THE_TDC : TDC
- generic map (
- CHANNEL_NUMBER => 65, -- Number of TDC channels
- STATUS_REG_NR => REGIO_NUM_STAT_REGS,
- CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
- port map (
- RESET => reset_i,
- CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement
- CLK_READOUT => clk_100_i, -- Clock for the readout
- REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => hit_in_i(64 downto 1), -- Channel start signals
- TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width
- TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width
- --
- -- Trigger signals from handler
- TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet
- VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet
- VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet
- INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet
- TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet
- SPIKE_DETECTED_IN => trg_spike_detected_i,
- MULTI_TMG_TRG_IN => trg_multiple_trg_i,
- SPURIOUS_TRG_IN => trg_spurious_trg_i,
- --
- TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package
- TRG_CODE_IN => trg_code_i, --
- TRG_INFORMATION_IN => trg_information_i, --
- TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package
- --
- --Response to handler
- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
- TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc
- DATA_OUT => fee_data_i, -- tdc data
- DATA_WRITE_OUT => fee_data_write_i, -- data valid signal
- DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal
- --
- TDC_DEBUG => stat_reg,
- LOGIC_ANALYSER_OUT => TEST_LINE,
- CONTROL_REG_IN => ctrl_reg);
-
-
- hit_in_i <= INPUT;
-
- -- to detect rising & falling edges
- --hit_in_i(1) <= not timing_trg_received_i;
-
- --Gen_Hit_In_Signals : for i in 1 to 15 generate
- -- hit_in_i(i*2) <= INPUT(i-1);
- -- hit_in_i(i*2+1) <= not INPUT(i-1);
- --end generate Gen_Hit_In_Signals;
-
-end architecture;
jspc29 / trb3.git / commitdiff