first CTS recompilation with updated MI

diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj
index 08d4f6c8b08090c157b663aaf9b894091a9cb359..e2ffcc2d45959dc0e1a3c06b61036d51b616a9a9 100644 (file)
--- a/cts/trb3sc_cts.prj
+++ b/cts/trb3sc_cts.prj
@@ -137,6 +137,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vh
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_lsm_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_rsl.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
 
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd"

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 3cd69063310b0d10c5d72cc1369020e3ba595855..4440e8af24bce18504c960a8fac3e49dd9e1643c 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -232,12 +232,15 @@ architecture trb3sc_arch of trb3sc_cts is
   signal destroy_link_i              : std_logic;
   
   signal tx_pll_lol_qd_b_i           : std_logic;
-  signal rst_qd_c_i                  : std_logic;
-  signal tx_pcs_rst_ch_c_i           : std_logic;
+  signal tx_pll_lol_all_i            : std_logic;
+  signal tx_clk_avail_i              : std_logic;
   signal sync_tx_quad_i              : std_logic;
   signal link_tx_ready_i             : std_logic;
-  signal tx_reset_i                  : std_logic;
-
+  signal tx_pcs_rst_i                : std_logic;
+  signal rst_qd_c_i                  : std_logic;
+  
+  signal tx_reset_state    : std_logic_vector(3 downto 0);
+  
   signal debug_i                     : std_logic_vector(31 downto 0);
 
 begin
@@ -311,6 +314,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
 
   THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_RS
     generic map(
+      SERDES_NUM         => 3,
       SIM_MODE           => 0,
       IS_MODE            => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER),
       IS_WAP_ZERO        => 1
@@ -319,8 +323,10 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
       -- Clocks and reset
       CLK_REF_FULL       => clk_full_osc,
       SYSCLK             => clk_sys,
-      RESET              => reset_i,
-      CLEAR              => clear_i,
+      RESET              => reset_i, -- check
+      CLEAR              => reset_i, -- check      
+      
+      
       -- Media Interface TX/RX
       MEDIA_MED2INT(0)   => open, 
       MEDIA_MED2INT(1)   => open,
@@ -342,21 +348,23 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
       RX_RST_WORD_OUT    => open,
       TX_RST_IN          => '0',
       TX_RST_WORD_IN     => x"00",
+      -- sync operation
       WORD_SYNC_IN       => '1', -- CTS MASTER
       WORD_SYNC_OUT      => open,
       MASTER_CLK_IN      => clk_full_osc, -- CTS MASTER
       MASTER_CLK_OUT     => open,
-      MASTER_RESET_OUT   => open,
+      GLOBAL_RESET_IN    => '0', -- check
+      GLOBAL_RESET_OUT   => open,
+      TX_PLL_LOL_IN      => tx_pll_lol_all_i,
+      TX_PLL_LOL_OUT     => tx_pll_lol_qd_b_i,
+      TX_CLK_AVAIL_OUT   => tx_clk_avail_i,
+      TX_PCS_RST_IN      => tx_pcs_rst_i,
+      SYNC_TX_PLL_IN     => sync_tx_quad_i,
+      LINK_TX_READY_IN   => link_tx_ready_i,
       DESTROY_LINK_IN(0) => '0', 
       DESTROY_LINK_IN(1) => '0',
       DESTROY_LINK_IN(2) => '0',
       DESTROY_LINK_IN(3) => destroy_link_i,
-      LINK_TX_READY_IN   => link_tx_ready_i,
-      TX_PLL_LOL_OUT     => tx_pll_lol_qd_b_i,
-      TX_RESET_OUT       => tx_reset_i, -- BUG???
-      SYNC_TX_PLL_IN     => sync_tx_quad_i,
-      RST_QUAD_IN        => rst_qd_c_i,
-      RST_TX_PCS_IN      => tx_pcs_rst_ch_c_i,
       --SFP Connection
       SD_PRSNT_N_IN(0)   => '1',
       SD_LOS_IN(0)       => '1',
@@ -379,6 +387,25 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
       DEBUG_OUT          => debug_i
     );
 
+  THE_MAIN_TX_RST: main_tx_reset_RS
+  generic map(
+    SIM_MODE    => 0
+  )
+  port map (
+    CLEAR                => '0',
+    LOCALCLK             => clk_full_osc,
+    TX_PLL_LOL_QD_A_IN   => '0',
+    TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,
+    TX_PLL_LOL_QD_C_IN   => '0',
+    TX_PLL_LOL_QD_D_IN   => '0',
+    TX_PLL_LOL_OUT       => tx_pll_lol_all_i,
+    TX_CLOCK_AVAIL_IN    => tx_clk_avail_i,
+    TX_PCS_RST_CH_C_OUT  => tx_pcs_rst_i,
+    SYNC_TX_QUAD_OUT     => sync_tx_quad_i,
+    LINK_TX_READY_OUT    => link_tx_ready_i,
+    STATE_OUT            => tx_reset_state
+  );
+  
   PCSSW       <= "01001110"; --SFP2 on B3, AddOn on D1      
 
   THE_SYNC_PROC: process( clk_sys )
@@ -400,64 +427,12 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
   HDR_IO(2)    <= rx_dlm_i;
   HDR_IO(1)    <= tx_dlm_i;
 
-  TEST_LINE(0)  <= debug_i(16);
-  TEST_LINE(1)  <= debug_i(17);
-  TEST_LINE(2)  <= debug_i(18);
-  TEST_LINE(3)  <= debug_i(19);
-  TEST_LINE(4)  <= debug_i(20);
-  TEST_LINE(5)  <= debug_i(5);
-  TEST_LINE(6)  <= debug_i(6);
-  TEST_LINE(7)  <= debug_i(7);
-  TEST_LINE(8)  <= debug_i(8);
-  TEST_LINE(9)  <= debug_i(21);
-  TEST_LINE(10) <= debug_i(10);
-  TEST_LINE(11) <= debug_i(11);
-  TEST_LINE(12) <= tx_pll_lol_qd_b_i;
-  TEST_LINE(13) <= rst_qd_c_i;
-  TEST_LINE(14) <= tx_pcs_rst_ch_c_i;
-  TEST_LINE(15) <= sync_tx_quad_i;
-
---  DEBUG_OUT(5)           <= send_steady_idle_int;
---  DEBUG_OUT(4)           <= toggle_idle;
---  DEBUG_OUT(3 downto 0)  <= state_bits;
-  
---  DEBUG_OUT(0)            <= SFP_LOS_IN;
---  DEBUG_OUT(1)            <= RX_LOS_IN;
---  DEBUG_OUT(2)            <= RX_CDR_LOL_IN;
---  DEBUG_OUT(3)            <= rx_pcs_rst_i;
---  DEBUG_OUT(4)            <= rx_serdes_rst_i;
---  DEBUG_OUT(5)            <= link_rx_ready_i;
---  DEBUG_OUT(6)            <= link_half_done_i;
---  DEBUG_OUT(7)            <= link_full_done_i;
---  DEBUG_OUT(8)            <= LINK_TX_READY_IN;
---  DEBUG_OUT(9)            <= is_wap_zero_i;
---  DEBUG_OUT(10)           <= reset_rx_fsm_i;
---  DEBUG_OUT(11)           <= reset_i;
---  DEBUG_OUT(15 downto 12) <= rx_fsm_state;
+  TEST_LINE <= debug_i(15 downto 0);
   
   destroy_link_i <= common_ctrl_reg(88);
 
 end generate;
 
-  THE_MAIN_TX_RESET: main_tx_reset_RS
-  generic map(
-    SIM_MODE    => 0
-  )
-  port map(
-    CLEAR                => clear_i,
-    LOCALCLK             => clk_full_osc,
-    TX_PLL_LOL_QD_A_IN   => '0',
-    TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,
-    TX_PLL_LOL_QD_C_IN   => '0',
-    TX_PLL_LOL_QD_D_IN   => '0',
-    TX_CLOCK_AVAIL_IN    => '1', -- CTS MASTER
-    RST_QD_C_OUT         => rst_qd_c_i,
-    TX_PCS_RST_CH_C_OUT  => tx_pcs_rst_ch_c_i,
-    SYNC_TX_QUAD_OUT     => sync_tx_quad_i,
-    LINK_TX_READY_OUT    => link_tx_ready_i,
-    STATE_OUT            => open
-  );
-  
 ---------------------------------------------------------------------------
 -- PCSC   4 downlinks
 ---------------------------------------------------------------------------    

diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj
index fba56254e04d1b27680a383e69789a9101eaddd6..3bfb02981d53252d3303f62c79e1c76c407fd789 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.prj
+++ b/tdctemplate/trb3sc_tdctemplate.prj
@@ -184,7 +184,6 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
-#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_lsm_RS.vhd"