+
# implementation: "workdir"
impl -add workdir -type fpga
add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-
-
-add_file -vhdl -lib "work" "srcjan/trb3_periph.vhd"
-add_file -vhdl -lib "work" "srcjan/Adder_304.vhd"
-add_file -vhdl -lib "work" "srcjan/bit_sync.vhd"
-add_file -vhdl -lib "work" "srcjan/Channel.vhd"
-add_file -vhdl -lib "work" "srcjan/Channel_200.vhd"
-add_file -vhdl -lib "work" "srcjan/Encoder_304_Bit.vhd"
-add_file -vhdl -lib "work" "srcjan/FIFO_32x32_OutReg.vhd"
-add_file -vhdl -lib "work" "srcjan/Reference_channel.vhd"
-add_file -vhdl -lib "work" "srcjan/ROM_encoder_3.vhd"
-add_file -vhdl -lib "work" "srcjan/ROM_FIFO.vhd"
-add_file -vhdl -lib "work" "srcjan/TDC.vhd"
-add_file -vhdl -lib "work" "srcjan/up_counter.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/trb3_periph.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/Adder_304.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/bit_sync.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/Channel.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/Encoder_304_Bit.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/FIFO_32x32_OutReg.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/Reference_channel.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/ROM_encoder_3.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/ROM_FIFO.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/TDC.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/up_counter.vhd"
+
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/trb3_periph.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Adder_304.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/bit_sync.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Channel.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Encoder_304_Bit.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/FIFO_32x32_OutReg.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Reference_channel.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/ROM_encoder_3.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/ROM_FIFO.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/TDC.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/up_counter.vhd"
+
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/trb3_periph.vhd"
+##add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Adder_304.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/bit_sync.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Encoder_304_Bit.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/FIFO_32x32_OutReg.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Reference_channel.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_encoder_3.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_FIFO.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/TDC.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/up_counter.vhd"
+
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/trb3_periph.vhd"
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Adder_304.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/bit_sync.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel_200.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Encoder_304_Bit.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/FIFO_32x32_OutReg.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Reference_Channel.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_encoder_3.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_FIFO.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/TDC.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/up_counter.vhd"