phaserbox added

diff --git a/special/clockbox.vhd b/special/clockbox.vhd
index 596f1e4ab96df7812521aa577b5a708317c84158..326c6302aa4e490afc7352cdba1f6c2f10e9af2c 100644 (file)
--- a/special/clockbox.vhd
+++ b/special/clockbox.vhd
@@ -19,6 +19,14 @@ end entity clockbox;
 architecture clockbox_arch of clockbox is\r
 \r
 -- Components\r
+  component clockpoint is
+  port(
+    SAMPLE_CLK    : in  std_logic;
+    DATA_IN       : in  std_logic;
+    CLK_DATA      : in  std_logic;
+    DATA_OUT      : out std_logic
+  );
+  end component clockpoint;\r
 \r
 -- state machine signals\r
 \r
@@ -35,7 +43,7 @@ architecture clockbox_arch of clockbox is
   \r
 begin\r
 \r
-  THE_PING_POINT: entity clockpoint\r
+  THE_PING_POINT: clockpoint\r
   port map(\r
     SAMPLE_CLK    => SAMPLE_CLK,\r
     DATA_IN       => PING_IN,\r
@@ -43,7 +51,7 @@ begin
     DATA_OUT      => PING_OUT\r
   );\r
 \r
-  THE_PONG_POINT: entity clockpoint\r
+  THE_PONG_POINT: clockpoint\r
   port map(\r
     SAMPLE_CLK    => SAMPLE_CLK,\r
     DATA_IN       => PONG_IN,\r

diff --git a/special/ddmtd.vhd b/special/ddmtd.vhd
index 39dc808f22c29e5b5b0592a79fc4f2c89506ac8e..325e465bf00079cdcfd9e1ad66907158f8a73878 100644 (file)
--- a/special/ddmtd.vhd
+++ b/special/ddmtd.vhd
@@ -47,9 +47,12 @@ architecture ddmtd_arch of ddmtd is
   signal delay_ce_x    : std_logic;
   signal delay_rst     : std_logic;
   signal delay_ctr     : unsigned(10 downto 0);
+  signal delay_store_x : std_logic;
   signal delay_store   : std_logic;
   signal delay_valid   : std_logic;
   signal delay_data    : std_logic_vector(9 downto 0);
+  signal clr_done_i    : std_logic;\r
+  signal clr_done_q    : std_logic;\r
 
   attribute HGROUP : string;
 --  attribute BBOX   : string;
@@ -62,12 +65,14 @@ architecture ddmtd_arch of ddmtd is
 
 begin
 
-THE_SAMPLER_PROC: process( AUXCLK )
+THE_SYNC_PROC: process( AUXCLK )
 begin
-  if( rising_edge(AUXCLK) ) then
-               delay_valid   <= delay_store;
+  if( rising_edge(AUXCLK) ) then\r
+    delay_store   <= delay_store_x;
+    delay_valid   <= delay_store;\r
+    clr_done_q    <= clr_done_i;
   end if;
-end process THE_SAMPLER_PROC;
+end process THE_SYNC_PROC;
 
 -- PING deglitcher
 THE_PING_DEGLITCH: deglitch
@@ -101,9 +106,11 @@ begin
   end if;
 end process THE_DELAY_CTR_PROC;
 
-delay_rst   <= start_pong_i when FSM_ACTIVE_IN = '0' else FSM_RST_IN;
-delay_store <= start_pong_i when FSM_ACTIVE_IN = '0' else '1';
-delay_ce_x  <= delay_ce     when FSM_ACTIVE_IN = '0' else FSM_CE_IN;
+delay_rst     <= start_ping_i when FSM_ACTIVE_IN = '0' else FSM_RST_IN;
+delay_store_x <= start_pong_i when FSM_ACTIVE_IN = '0' else '1';
+delay_ce_x    <= delay_ce     when FSM_ACTIVE_IN = '0' else FSM_CE_IN;
+\r
+clr_done_i <= '1' when (delay_ctr = b"11_1111_1110") else '0';\r
 
 THE_DELAY_CE_PROC: process( AUXCLK, RESET )
 begin
@@ -146,6 +153,6 @@ START_PONG_OUT   <= start_pong_i;
 DELAY_VALUE_OUT  <= delay_data;
 DELAY_VALID_OUT  <= delay_valid;
 TOGGLE_OUT       <= toggle_q;
-FSM_CLR_DONE_OUT <= std_logic(delay_ctr(10));
+FSM_CLR_DONE_OUT <= clr_done_q;
 
 end architecture;

diff --git a/special/phaserbox.vhd b/special/phaserbox.vhd
new file mode 100644 (file)
index 0000000..80a4a76
--- /dev/null
+++ b/special/phaserbox.vhd
@@ -0,0 +1,195 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity phaserbox is\r
+port(\r
+  SAMPLE_CLK       : in  std_logic; -- auxiliary clock for sampling\r
+  RESET            : in  std_logic;\r
+  -- input signals\r
+  TX_SYNC_IN       : in  std_logic; -- outgoing sync signal\r
+  TX_CLK_IN        : in  std_logic; -- TX clock \r
+  RX_SYNC_IN       : in  std_logic; -- incoming sync signal\r
+  RX_CLK_IN        : in  std_logic; -- RX clock\r
+  START_DELAY_IN   : in  std_logic; -- outgoing DLM komma\r
+  STOP_DELAY_IN    : in  std_logic; -- incoming DLM komma\r
+  -- histogram\r
+  HISTO_CLK        : in  std_logic;\r
+  HISTO_START_IN   : in  std_logic;\r
+  HISTO_DONE_OUT   : out std_logic;\r
+  HISTO_ADDR_IN    : in  std_logic_vector(9 downto 0);\r
+  HISTO_DATA_OUT   : out std_logic_vector(17 downto 0);\r
+  -- \r
+  COARSE_DELAY_OUT : out std_logic_vector(31 downto 0);\r
+  --\r
+  DEBUG_OUT        : out std_logic_vector(15 downto 0)\r
+);\r
+end entity phaserbox;\r
+\r
+architecture phaserbox_arch of phaserbox is\r
+\r
+  -- Components\r
+  component clockbox is\r
+  port(\r
+    SAMPLE_CLK    : in  std_logic;\r
+    PING_IN       : in  std_logic;\r
+    CLK_PING      : in  std_logic;\r
+    PONG_IN       : in  std_logic;\r
+    CLK_PONG      : in  std_logic;\r
+    PING_OUT      : out std_logic;\r
+    PONG_OUT      : out std_logic\r
+  );\r
+  end component clockbox;\r
+\r
+  component ddmtd is\r
+  port(\r
+    AUXCLK           : in  std_logic; -- auxiliary clock for sampling\r
+    RESET            : in  std_logic;\r
+    -- input signals\r
+    PING_IN          : in  std_logic; -- TX_K signal\r
+    PONG_IN          : in  std_logic; -- RX_K signal\r
+    -- test signals\r
+    PING_OUT         : out std_logic; -- stretched TX_K signal\r
+    PONG_OUT         : out std_logic; -- stretched RX_K signal\r
+    START_PING_OUT   : out std_logic; -- rising edge of stretched TX_K signal\r
+    START_PONG_OUT   : out std_logic; -- rising edge of stretched RX_K signal\r
+    TOGGLE_OUT       : out std_logic; -- for checking by scope\r
+    -- result\r
+    DELAY_VALUE_OUT  : out std_logic_vector(9 downto 0); -- result of measurement\r
+    DELAY_VALID_OUT  : out std_logic; -- result of measurement is valid\r
+    -- remote control\r
+    FSM_ACTIVE_IN    : in  std_logic;\r
+    FSM_CE_IN        : in  std_logic;\r
+    FSM_RST_IN       : in  std_logic;\r
+    FSM_CLR_DONE_OUT : out std_logic\r
+  );\r
+  end component ddmtd;\r
+\r
+  component statistics is\r
+  port( \r
+    AUXCLK           : in  std_logic;\r
+    RESET            : in  std_logic;\r
+    DELAY_CLK        : in  std_logic;\r
+    DELAY_START_IN   : in  std_logic;\r
+    DELAY_STOP_IN    : in  std_logic;\r
+    DELAY_COARSE_OUT : out std_logic_vector(31 downto 0);\r
+    DELAY_VALUE_IN   : in  std_logic_vector(9 downto 0);\r
+    DELAY_VALID_IN   : in  std_logic;\r
+    FSM_START_IN     : in  std_logic;\r
+    FSM_CLR_DONE_IN  : in  std_logic;\r
+    FSM_ACTIVE_OUT   : out std_logic;\r
+    FSM_CE_OUT       : out std_logic;\r
+    FSM_RST_OUT      : out std_logic;\r
+    FSM_DONE_OUT     : out std_logic;\r
+    RD_CLK           : in  std_logic;\r
+    RD_ADDRESS_IN    : in  std_logic_vector(9 downto 0);\r
+    RD_DATA_OUT      : out std_logic_vector(17 downto 0)\r
+  );\r
+  end component statistics;\r
+\r
+  -- Signals\r
+  signal tx_sync_q            : std_logic;\r
+  signal rx_sync_q            : std_logic;\r
+  signal start_tx_sync_i      : std_logic;\r
+  signal start_rx_sync_i      : std_logic;\r
+  signal stretched_tx_sync_i  : std_logic; -- OBSELETE\r
+  signal stretched_rx_sync_i  : std_logic; -- OBSELETE\r
+  signal delay_value_i        : std_logic_vector(9 downto 0);\r
+  signal delay_valid_i        : std_logic;\r
+  signal fsm_active_i         : std_logic;\r
+  signal fsm_ce_i             : std_logic;\r
+  signal fsm_rst_i            : std_logic;\r
+  signal fsm_clr_done_i       : std_logic;\r
+  signal cal_phase_q          : std_logic; -- OBSELETE\r
+  signal toggle_q             : std_logic; -- OBSELETE\r
+  signal coarse_delay_i       : std_logic_vector(31 downto 0);\r
+  signal debug                : std_logic_vector(15 downto 0);\r
+\r
+  attribute HGROUP : string;\r
+--  attribute BBOX   : string;\r
+  attribute HGROUP of phaserbox_arch : architecture is "phaserbox_group";\r
+--  attribute BBOX   of ddmtd_arch : architecture is "2,2";\r
+  attribute syn_sharing : string;\r
+  attribute syn_sharing of phaserbox_arch : architecture is "off";\r
+  attribute syn_hier : string;\r
+  attribute syn_hier of phaserbox_arch : architecture is "hard";\r
+\r
+begin\r
+\r
+  --\r
+  cal_phase_q <= (TX_SYNC_IN xor RX_SYNC_IN) when rising_edge(TX_CLK_IN);\r
+\r
+  -- clock domain transfer with defined placement\r
+  THE_CLOCKBOX: clockbox\r
+  port map(\r
+    SAMPLE_CLK    => SAMPLE_CLK,\r
+    PING_IN       => TX_SYNC_IN,\r
+    CLK_PING      => TX_CLK_IN,\r
+    PONG_IN       => RX_SYNC_IN,\r
+    CLK_PONG      => RX_CLK_IN,\r
+    PING_OUT      => tx_sync_q,\r
+    PONG_OUT      => rx_sync_q\r
+  );\r
+\r
+  --\r
+  THE_DDMTD: ddmtd\r
+  port map(\r
+    AUXCLK           => SAMPLE_CLK,\r
+    RESET            => RESET,\r
+    -- input signals\r
+    PING_IN          => tx_sync_q,\r
+    PONG_IN          => rx_sync_q,\r
+    -- test signals\r
+    PING_OUT         => stretched_tx_sync_i, -- stretched TX_K signal\r
+    PONG_OUT         => stretched_rx_sync_i, -- stretched RX_K signal\r
+    START_PING_OUT   => start_tx_sync_i,\r
+    START_PONG_OUT   => start_rx_sync_i,\r
+    TOGGLE_OUT       => toggle_q, -- for checking by scope\r
+    -- result\r
+    DELAY_VALUE_OUT  => delay_value_i,\r
+    DELAY_VALID_OUT  => delay_valid_i,\r
+    -- remote control\r
+    FSM_ACTIVE_IN    => fsm_active_i,\r
+    FSM_CE_IN        => fsm_ce_i,\r
+    FSM_RST_IN       => fsm_rst_i,\r
+    FSM_CLR_DONE_OUT => fsm_clr_done_i\r
+  );\r
+\r
+  --\r
+  THE_STATISTICS: statistics\r
+  port map( \r
+    AUXCLK           => SAMPLE_CLK,\r
+    RESET            => RESET,\r
+    DELAY_CLK        => TX_CLK_IN,\r
+    DELAY_START_IN   => START_DELAY_IN,\r
+    DELAY_STOP_IN    => STOP_DELAY_IN,\r
+    DELAY_COARSE_OUT => coarse_delay_i,\r
+    DELAY_VALUE_IN   => delay_value_i,\r
+    DELAY_VALID_IN   => delay_valid_i,\r
+    FSM_START_IN     => HISTO_START_IN,\r
+    FSM_CLR_DONE_IN  => fsm_clr_done_i,\r
+    FSM_ACTIVE_OUT   => fsm_active_i,\r
+    FSM_CE_OUT       => fsm_ce_i,\r
+    FSM_RST_OUT      => fsm_rst_i,\r
+    FSM_DONE_OUT     => HISTO_DONE_OUT,\r
+    RD_CLK           => HISTO_CLK,\r
+    RD_ADDRESS_IN    => HISTO_ADDR_IN,\r
+    RD_DATA_OUT      => HISTO_DATA_OUT\r
+  );\r
+\r
+  -- DEBUG\r
+  debug(15 downto 6) <= (others => '0');\r
+  debug(5)  <= start_rx_sync_i;\r
+  debug(4)  <= start_tx_sync_i;\r
+  debug(3)  <= cal_phase_q;\r
+  debug(2)  <= toggle_q;\r
+  debug(1)  <= stretched_rx_sync_i;\r
+  debug(0)  <= stretched_tx_sync_i;\r
+\r
+  -- Outputs\r
+  COARSE_DELAY_OUT <= cal_phase_q & coarse_delay_i(30 downto 0);\r
+  DEBUG_OUT        <= debug;\r
+\r
+end architecture;\r

diff --git a/special/statistics.vhd b/special/statistics.vhd
index 24f88a019570bde530466300d1df8df57cf2b40d..93517f1cb4a5e06d626b80120fbc8fd1fc03c6af 100644 (file)
--- a/special/statistics.vhd
+++ b/special/statistics.vhd
@@ -179,13 +179,13 @@ DELAY_COARSE_OUT <= coarse_delay;
                       end if;
       when PCTR    => bsm <= x"4";
                       NEXT_STATE <= DLY1;
-                      fsm_act_x  <= '1';
+                      --fsm_act_x  <= '1';
       when DLY1    => bsm <= x"5";
                       if( DELAY_VALID_IN = '1' ) then
                         NEXT_STATE <= WFD;
                       else
                         NEXT_STATE <= DLY1;
-                        fsm_act_x  <= '1';
+                        --fsm_act_x  <= '1';
                       end if;
       when WFD    =>  bsm <= x"6";
                       if( DELAY_VALID_IN = '1' ) then
@@ -269,7 +269,7 @@ DELAY_COARSE_OUT <= coarse_delay;
   end process THE_SUM_CTR_PROC;
 
   sum_ctr_done <= std_logic(sum_ctr(18));
---  sum_ctr_done <= std_logic(sum_ctr(16));
+--  sum_ctr_done <= std_logic(sum_ctr(14));
 
 -- mean value
   mean_sum_x <= mean_sum_q + unsigned(DELAY_VALUE_IN);