<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_0" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 05 20 11:29:53.979" version="8.1" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="serdes_sync_0" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 08 12 15:03:13.880" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_0.lpc" type="lpc" modified="2015 05 20 11:29:52.000"/>
- <File name="serdes_sync_0.pp" type="pp" modified="2015 05 20 11:29:52.000"/>
- <File name="serdes_sync_0.sym" type="sym" modified="2015 05 20 11:29:52.000"/>
- <File name="serdes_sync_0.tft" type="tft" modified="2015 05 20 11:27:34.000"/>
- <File name="serdes_sync_0.txt" type="pcs_module" modified="2015 05 20 11:29:52.000"/>
- <File name="serdes_sync_0.vhd" type="top_level_vhdl" modified="2015 05 20 11:27:34.000"/>
+ <File name="serdes_sync_0.lpc" type="lpc" modified="2015 08 12 15:03:11.000"/>
+ <File name="serdes_sync_0.pp" type="pp" modified="2015 08 12 15:03:11.000"/>
+ <File name="serdes_sync_0.sym" type="sym" modified="2015 08 12 15:03:12.000"/>
+ <File name="serdes_sync_0.tft" type="tft" modified="2015 08 12 15:03:11.000"/>
+ <File name="serdes_sync_0.txt" type="pcs_module" modified="2015 08 12 15:03:11.000"/>
+ <File name="serdes_sync_0.vhd" type="top_level_vhdl" modified="2015 08 12 15:03:11.000"/>
</Package>
</DiamondModule>
CoreType=LPM
CoreStatus=Demo
CoreName=PCS
-CoreRevision=8.1
+CoreRevision=8.2
ModuleName=serdes_sync_0
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=05/20/2015
-Time=11:29:52
+Date=08/12/2015
+Time=15:03:11
[Parameters]
Verilog=0
_rx_data_width1=8
_rx_data_width2=8
_rx_data_width3=8
-_rx_fifo0=ENABLED
+_rx_fifo0=DISABLED
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
_rx_fifo3=ENABLED
CH0_TX_DATA_WIDTH "8"
CH0_RX_DATA_WIDTH "8"
CH0_TX_FIFO "DISABLED"
-CH0_RX_FIFO "ENABLED"
+CH0_RX_FIFO "DISABLED"
CH0_TDRV "0"
#CH0_TX_FICLK_RATE 200
#CH0_RXREFCLK_RATE "200"
hdinp_ch0, hdinn_ch0 : in std_logic;
hdoutp_ch0, hdoutn_ch0 : out std_logic;
sci_sel_ch0 : in std_logic;
- rxiclk_ch0 : in std_logic;
txiclk_ch0 : in std_logic;
rx_full_clk_ch0 : out std_logic;
rx_half_clk_ch0 : out std_logic;
PCIE_PHYSTATUS_0 => open,
SCISELCH0 => sci_sel_ch0,
SCIENCH0 => fpsc_vhi,
- FF_RXI_CLK_0 => rxiclk_ch0,
+ FF_RXI_CLK_0 => fpsc_vlo,
FF_TXI_CLK_0 => txiclk_ch0,
FF_EBRD_CLK_0 => fpsc_vlo,
FF_RX_F_CLK_0 => rx_full_clk_ch0,
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_4" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 07 16 10:47:34.916" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_4" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 10 15 14:55:32.927" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_4.lpc" type="lpc" modified="2015 07 16 10:47:32.000"/>
- <File name="serdes_sync_4.pp" type="pp" modified="2015 07 16 10:47:32.000"/>
- <File name="serdes_sync_4.sym" type="sym" modified="2015 07 16 10:47:33.000"/>
- <File name="serdes_sync_4.tft" type="tft" modified="2015 07 16 10:47:32.000"/>
- <File name="serdes_sync_4.txt" type="pcs_module" modified="2015 07 16 10:47:32.000"/>
- <File name="serdes_sync_4.vhd" type="top_level_vhdl" modified="2015 07 16 10:47:32.000"/>
+ <File name="serdes_sync_4.lpc" type="lpc" modified="2015 10 15 14:55:29.000"/>
+ <File name="serdes_sync_4.pp" type="pp" modified="2015 10 15 14:55:29.000"/>
+ <File name="serdes_sync_4.sym" type="sym" modified="2015 10 15 14:55:30.000"/>
+ <File name="serdes_sync_4.tft" type="tft" modified="2015 10 15 14:55:29.000"/>
+ <File name="serdes_sync_4.txt" type="pcs_module" modified="2015 10 15 14:55:29.000"/>
+ <File name="serdes_sync_4.vhd" type="top_level_vhdl" modified="2015 10 15 14:55:29.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_4
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=07/16/2015
-Time=10:47:32
+Date=10/15/2015
+Time=14:55:29
[Parameters]
Verilog=0
_rx_los_port3=Internal
_sci_ports=ENABLED
_sci_int_port=DISABLED
-_refck2core=ENABLED
+_refck2core=DISABLED
Regen=auto
PAR1=0
PARTrace1=0
CH2_PCSLBPORTS "DISABLED"
CH3_PCSLBPORTS "DISABLED"
INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
+QD_REFCK2CORE "DISABLED"
tx_pll_lol_qd_s : out std_logic;
tx_sync_qd_c : in std_logic;
rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
serdes_rst_qd_c : in std_logic);
end serdes_sync_4;
attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
attribute black_box_pad_pin: string;
attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
vlo_inst : VLO port map(Z => fpsc_vlo);
vhi_inst : VHI port map(Z => fpsc_vhi);
- refclk2fpga <= refclk2fpga_sig;
rx_los_low_ch0_s <= rx_los_low_ch0_sig;
rx_los_low_ch1_s <= rx_los_low_ch1_sig;
rx_los_low_ch2_s <= rx_los_low_ch2_sig;
IS_SYNC_SLAVE : integer := c_NO --select slave mode
);
port(
- CLK : in std_logic; -- *internal* 200 MHz reference clock
+ CLK_REF_FULL : in std_logic; -- 200 MHz reference clock
+ CLK_INTERNAL_FULL : in std_logic; -- internal 200 MHz, always on
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
--SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
+ SD_RXD_P_IN : in std_logic := '0';
+ SD_RXD_N_IN : in std_logic := '0';
+ SD_TXD_P_OUT : out std_logic := '0';
+ SD_TXD_N_OUT : out std_logic := '0';
SD_REFCLK_P_IN : in std_logic; --not used
SD_REFCLK_N_IN : in std_logic; --not used
SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
attribute syn_hier : string;
attribute syn_hier of med_ecp3_sfp_sync_arch : architecture is "hard";
-signal clk_200_i : std_logic;
-signal clk_200_internal : std_logic;
+-- signal clk_200_i : std_logic;
+signal clk_200_ref : std_logic;
signal clk_rx_full, clk_rx_half : std_logic;
signal clk_tx_full, clk_tx_half : std_logic;
signal debug_tx_control_i : std_logic_vector(31 downto 0);
signal stat_fsm_reset_i : std_logic_vector(31 downto 0);
+signal hdinp, hdinn, hdoutp, hdoutn : std_logic;
+attribute nopad : string;
+attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
+
begin
-clk_200_internal <= CLK;
+clk_200_ref <= CLK_REF_FULL;
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-- end generate;
--
-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
- clk_200_i <= clk_200_internal;
+-- clk_200_i <= clk_200_internal;
-- end generate;
-------------------------------------------------
-- Serdes
-------------------------------------------------
--- gen_pcs0 : if SERDES_NUM = 0 generate
--- THE_SERDES : entity work.serdes_sync_0
--- port map(
--- hdinp_ch0 => SD_RXD_P_IN,
--- hdinn_ch0 => SD_RXD_N_IN,
--- hdoutp_ch0 => SD_TXD_P_OUT,
--- hdoutn_ch0 => SD_TXD_N_OUT,
--- rxiclk_ch0 => clk_200_i,
--- txiclk_ch0 => clk_200_i,
--- rx_full_clk_ch0 => clk_rx_full,
--- rx_half_clk_ch0 => clk_rx_half,
--- tx_full_clk_ch0 => clk_tx_full,
--- tx_half_clk_ch0 => clk_tx_half,
--- fpga_rxrefclk_ch0 => clk_200_internal,
--- txdata_ch0 => tx_data,
--- tx_k_ch0 => tx_k,
--- tx_force_disp_ch0 => '0',
--- tx_disp_sel_ch0 => '0',
--- rxdata_ch0 => rx_data,
--- rx_k_ch0 => rx_k,
--- rx_disp_err_ch0 => open,
--- rx_cv_err_ch0 => rx_error,
--- rx_serdes_rst_ch0_c => rx_serdes_rst,
--- sb_felb_ch0_c => '0',
--- sb_felb_rst_ch0_c => '0',
--- tx_pcs_rst_ch0_c => tx_pcs_rst,
--- tx_pwrup_ch0_c => '1',
--- rx_pcs_rst_ch0_c => rx_pcs_rst,
--- rx_pwrup_ch0_c => '1',
--- rx_los_low_ch0_s => rx_los_low,
--- lsm_status_ch0_s => lsm_status,
--- rx_cdr_lol_ch0_s => rx_cdr_lol,
--- tx_div2_mode_ch0_c => '0',
--- rx_div2_mode_ch0_c => '0',
---
--- SCI_WRDATA => sci_data_in_i,
--- SCI_RDDATA => sci_data_out_i,
--- SCI_ADDR => sci_addr_i,
--- SCI_SEL_QUAD => sci_ch_i(4),
--- SCI_SEL_CH0 => sci_ch_i(0),
--- SCI_RD => sci_read_i,
--- SCI_WRN => sci_write_i,
---
--- fpga_txrefclk => clk_200_i,
--- tx_serdes_rst_c => '0',
--- tx_pll_lol_qd_s => tx_pll_lol,
--- rst_qd_c => rst_qd,
--- serdes_rst_qd_c => '0'
---
--- );
--- end generate;
+gen_pcs0 : if SERDES_NUM = 0 generate
+ THE_SERDES : entity work.serdes_sync_0
+ port map(
+ hdinp_ch0 => hdinp,
+ hdinn_ch0 => hdinn,
+ hdoutp_ch0 => hdoutp,
+ hdoutn_ch0 => hdoutn,
+ txiclk_ch0 => clk_200_ref,
+ rx_full_clk_ch0 => clk_rx_full,
+ rx_half_clk_ch0 => clk_rx_half,
+ tx_full_clk_ch0 => clk_tx_full,
+ tx_half_clk_ch0 => clk_tx_half,
+ fpga_rxrefclk_ch0 => CLK_INTERNAL_FULL,
+ txdata_ch0 => tx_data,
+ tx_k_ch0 => tx_k,
+ tx_force_disp_ch0 => '0',
+ tx_disp_sel_ch0 => '0',
+ rxdata_ch0 => rx_data,
+ rx_k_ch0 => rx_k,
+ rx_disp_err_ch0 => open,
+ rx_cv_err_ch0 => rx_error,
+ rx_serdes_rst_ch0_c => rx_serdes_rst,
+ sb_felb_ch0_c => '0',
+ sb_felb_rst_ch0_c => '0',
+ tx_pcs_rst_ch0_c => tx_pcs_rst,
+ tx_pwrup_ch0_c => '1',
+ rx_pcs_rst_ch0_c => rx_pcs_rst,
+ rx_pwrup_ch0_c => '1',
+ rx_los_low_ch0_s => rx_los_low,
+ lsm_status_ch0_s => lsm_status,
+ rx_cdr_lol_ch0_s => rx_cdr_lol,
+ tx_div2_mode_ch0_c => '0',
+ rx_div2_mode_ch0_c => '0',
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i,
+ SCI_SEL_QUAD => sci_ch_i(4),
+ SCI_SEL_CH0 => sci_ch_i(0),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+
+ fpga_txrefclk => clk_200_ref,
+ tx_serdes_rst_c => '0',
+ tx_pll_lol_qd_s => tx_pll_lol,
+ rst_qd_c => rst_qd,
+ serdes_rst_qd_c => '0'
+
+ );
+end generate;
gen_pcs3 : if SERDES_NUM = 3 generate
THE_SERDES : entity work.serdes_sync_3
port map(
- hdinp_ch3 => SD_RXD_P_IN,
- hdinn_ch3 => SD_RXD_N_IN,
- hdoutp_ch3 => SD_TXD_P_OUT,
- hdoutn_ch3 => SD_TXD_N_OUT,
--- rxiclk_ch3 => clk_rx_full, --JM06
- txiclk_ch3 => clk_rx_full, --clk_tx_full, --JM06 clk_tx_fullclk_200_i, JM150706
+ hdinp_ch3 => hdinp,
+ hdinn_ch3 => hdinn,
+ hdoutp_ch3 => hdoutp,
+ hdoutn_ch3 => hdoutn,
+ txiclk_ch3 => clk_200_ref, --clk_tx_full, --JM06 clk_tx_fullclk_200_i, JM150706
rx_full_clk_ch3 => clk_rx_full,
rx_half_clk_ch3 => clk_rx_half,
tx_full_clk_ch3 => clk_tx_full,
tx_half_clk_ch3 => clk_tx_half,
- fpga_rxrefclk_ch3 => clk_200_internal,
+ fpga_rxrefclk_ch3 => CLK_INTERNAL_FULL,
txdata_ch3 => tx_data,
tx_k_ch3 => tx_k,
tx_force_disp_ch3 => '0',
SCI_RDDATA => sci_data_out_i,
SCI_ADDR => sci_addr_i,
SCI_SEL_QUAD => sci_ch_i(4),
- SCI_SEL_CH3 => sci_ch_i(0),
+ SCI_SEL_CH3 => sci_ch_i(3),
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
- fpga_txrefclk => clk_rx_full,
+ fpga_txrefclk => clk_200_ref,
tx_serdes_rst_c => '0',
tx_pll_lol_qd_s => tx_pll_lol,
rst_qd_c => rst_qd,
tx_serdes_rst <= '0'; --no function
serdes_rst_qd <= '0'; --included in rst_qd
- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0
- else wa_position(15 downto 12) when SERDES_NUM = 3;
+ wa_position_sel <= x"0";
+-- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0
+-- else wa_position(15 downto 12) when SERDES_NUM = 3;
THE_MED_CONTROL : entity work.med_sync_control
generic map(
CLK_SYS => SYSCLK,
CLK_RXI => clk_rx_full, --clk_rx_full,
CLK_RXHALF => clk_rx_half,
- CLK_TXI => clk_rx_full, --clk_200_internal, --clk_tx_full, JM150706
- CLK_REF => clk_200_i,
+ CLK_TXI => clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706
+ CLK_REF => CLK_INTERNAL_FULL,
RESET => RESET,
CLEAR => CLEAR,
---Media interface for Lattice ECP3 using PCS at 2GHz
+--four links, all with receive buffers, as masters only.
+
LIBRARY IEEE;
IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES)
);
port(
- CLK : in std_logic; -- *internal* 200 MHz reference clock
+ CLK_REF_FULL : in std_logic; -- 200 MHz reference clock
+ CLK_INTERNAL_FULL : in std_logic; -- internal 200 MHz, always on
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
TX_DLM_WORD : in std_logic_vector(4*8-1 downto 0) := (others => '0');
--SFP Connection
- SD_RXD_P_IN : in std_logic_vector(3 downto 0);
- SD_RXD_N_IN : in std_logic_vector(3 downto 0);
- SD_TXD_P_OUT : out std_logic_vector(3 downto 0);
- SD_TXD_N_OUT : out std_logic_vector(3 downto 0);
SD_REFCLK_P_IN : in std_logic := '0'; --not used
SD_REFCLK_N_IN : in std_logic := '0'; --not used
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
attribute syn_hier of med_ecp3_sfp_sync_4_arch : architecture is "hard";
signal clk_200_i : std_logic;
-signal clk_200_internal : std_logic;
+signal clk_200_ref : std_logic;
signal clk_rx_full, clk_rx_half : std_logic_vector(3 downto 0);
signal clk_tx_full, clk_tx_half : std_logic_vector(3 downto 0);
signal debug_tx_control_i : std_logic_vector(4*32-1 downto 0);
signal stat_fsm_reset_i : std_logic_vector(4*32-1 downto 0);
+signal hdinp, hdinn, hdoutp, hdoutn : std_logic_vector(3 downto 0);
+attribute nopad : string;
+attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
begin
-clk_200_internal <= CLK;
+clk_200_ref <= CLK_REF_FULL;
SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
--- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
--- clk_200_i <= clk_rx_full;
--- end generate;
---
--- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
- clk_200_i <= clk_200_internal;
--- end generate;
-
-
-------------------------------------------------
-- Serdes
-------------------------------------------------
THE_SERDES : entity work.serdes_sync_4
port map(
- hdinp_ch0 => SD_RXD_P_IN(0),
- hdinn_ch0 => SD_RXD_N_IN(0),
- hdoutp_ch0 => SD_TXD_P_OUT(0),
- hdoutn_ch0 => SD_TXD_N_OUT(0),
- rxiclk_ch0 => clk_200_i,
- txiclk_ch0 => clk_tx_full(0),
+ hdinp_ch0 => hdinp (0),
+ hdinn_ch0 => hdinn (0),
+ hdoutp_ch0 => hdoutp(0),
+ hdoutn_ch0 => hdoutn(0),
+ txiclk_ch0 => clk_200_ref, --clk_tx_full(0),
+ rxiclk_ch0 => clk_200_ref,
rx_full_clk_ch0 => clk_rx_full(0),
rx_half_clk_ch0 => clk_rx_half(0),
tx_full_clk_ch0 => clk_tx_full(0),
tx_half_clk_ch0 => clk_tx_half(0),
- fpga_rxrefclk_ch0 => clk_200_internal,
+ fpga_rxrefclk_ch0 => CLK_INTERNAL_FULL,
txdata_ch0 => tx_data(0*8+7 downto 0*8),
tx_k_ch0 => tx_k(0),
tx_force_disp_ch0 => '0',
tx_div2_mode_ch0_c => '0',
rx_div2_mode_ch0_c => '0',
- hdinp_ch1 => SD_RXD_P_IN(1),
- hdinn_ch1 => SD_RXD_N_IN(1),
- hdoutp_ch1 => SD_TXD_P_OUT(1),
- hdoutn_ch1 => SD_TXD_N_OUT(1),
- rxiclk_ch1 => clk_200_i,
- txiclk_ch1 => clk_tx_full(1),
+ hdinp_ch1 => hdinp (1),
+ hdinn_ch1 => hdinn (1),
+ hdoutp_ch1 => hdoutp(1),
+ hdoutn_ch1 => hdoutn(1),
+ txiclk_ch1 => clk_200_ref, --clk_tx_full(1),
+ rxiclk_ch1 => clk_200_ref,
rx_full_clk_ch1 => clk_rx_full(1),
rx_half_clk_ch1 => clk_rx_half(1),
tx_full_clk_ch1 => clk_tx_full(1),
tx_half_clk_ch1 => clk_tx_half(1),
- fpga_rxrefclk_ch1 => clk_200_internal,
+ fpga_rxrefclk_ch1 => CLK_INTERNAL_FULL,
txdata_ch1 => tx_data(1*8+7 downto 1*8),
tx_k_ch1 => tx_k(1),
tx_force_disp_ch1 => '0',
tx_div2_mode_ch1_c => '0',
rx_div2_mode_ch1_c => '0',
- hdinp_ch2 => SD_RXD_P_IN(2),
- hdinn_ch2 => SD_RXD_N_IN(2),
- hdoutp_ch2 => SD_TXD_P_OUT(2),
- hdoutn_ch2 => SD_TXD_N_OUT(2),
- rxiclk_ch2 => clk_200_i,
- txiclk_ch2 => clk_tx_full(2),
+ hdinp_ch2 => hdinp (2),
+ hdinn_ch2 => hdinn (2),
+ hdoutp_ch2 => hdoutp(2),
+ hdoutn_ch2 => hdoutn(2),
+ txiclk_ch2 => clk_200_ref, --clk_tx_full(2),
+ rxiclk_ch2 => clk_200_ref,
rx_full_clk_ch2 => clk_rx_full(2),
rx_half_clk_ch2 => clk_rx_half(2),
tx_full_clk_ch2 => clk_tx_full(2),
tx_half_clk_ch2 => clk_tx_half(2),
- fpga_rxrefclk_ch2 => clk_200_internal,
+ fpga_rxrefclk_ch2 => CLK_INTERNAL_FULL,
txdata_ch2 => tx_data(2*8+7 downto 2*8),
tx_k_ch2 => tx_k(2),
tx_force_disp_ch2 => '0',
tx_div2_mode_ch2_c => '0',
rx_div2_mode_ch2_c => '0',
- hdinp_ch3 => SD_RXD_P_IN(3),
- hdinn_ch3 => SD_RXD_N_IN(3),
- hdoutp_ch3 => SD_TXD_P_OUT(3),
- hdoutn_ch3 => SD_TXD_N_OUT(3),
- rxiclk_ch3 => clk_200_i,
- txiclk_ch3 => clk_tx_full(3),
+ hdinp_ch3 => hdinp (3),
+ hdinn_ch3 => hdinn (3),
+ hdoutp_ch3 => hdoutp(3),
+ hdoutn_ch3 => hdoutn(3),
+ txiclk_ch3 => clk_200_ref, --clk_tx_full(3),
+ rxiclk_ch3 => clk_200_ref, --clk_tx_full(3),
rx_full_clk_ch3 => clk_rx_full(3),
rx_half_clk_ch3 => clk_rx_half(3),
tx_full_clk_ch3 => clk_tx_full(3),
tx_half_clk_ch3 => clk_tx_half(3),
- fpga_rxrefclk_ch3 => clk_200_internal,
+ fpga_rxrefclk_ch3 => CLK_INTERNAL_FULL,
txdata_ch3 => tx_data(3*8+7 downto 3*8),
tx_k_ch3 => tx_k(3),
tx_force_disp_ch3 => '0',
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
- fpga_txrefclk => clk_200_i,
+ fpga_txrefclk => clk_200_ref,
tx_serdes_rst_c => '0',
tx_pll_lol_qd_s => tx_pll_lol,
rst_qd_c => rst_qd(0),
)
port map(
CLK_SYS => SYSCLK,
- CLK_RXI => clk_200_i,
+ CLK_RXI => clk_200_ref,
CLK_RXHALF => clk_rx_half(i),
- CLK_TXI => clk_tx_full(i),
- CLK_REF => clk_200_internal,
+ CLK_TXI => clk_200_ref, --clk_tx_full(i),
+ CLK_REF => CLK_INTERNAL_FULL,
RESET => RESET,
CLEAR => CLEAR,
DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32),
STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32)
);
- end generate;
+ end generate;
+
gen_not_used : if IS_USED(i) = c_NO generate
MEDIA_MED2INT(i).dataready <= '0';
MEDIA_MED2INT(i).tx_read <= '1';
SCI_RD => sci_read_i,
SCI_WR => sci_write_i,
- WA_POS_OUT => wa_position,
+ WA_POS_OUT => open,
--Slowcontrol
BUS_RX => BUS_RX,
DEBUG_OUT => open
);
+wa_position <= (others => '0');
STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0);
STAT_DEBUG(15 downto 14) <= debug_tx_control_i(17 downto 16);
-
--- STAT_DEBUG(3 downto 0) <= debug_tx_control_i(3 downto 0);
--- STAT_DEBUG(5 downto 4) <= stat_fsm_reset_i(9 downto 8);
--- STAT_DEBUG(9 downto 6) <= debug_tx_control_i(19 downto 16);
--- STAT_DEBUG(12 downto 10) <= stat_fsm_reset_i(2 downto 0);
--- STAT_DEBUG(15 downto 13) <= stat_fsm_reset_i(6 downto 4);
-
+
end architecture;
signal rx_fsm_state : std_logic_vector(3 downto 0);
signal tx_fsm_state : std_logic_vector(3 downto 0);
signal wa_position_rx : std_logic_vector(3 downto 0);
-signal start_timer : unsigned(17 downto 0) := (others => '0');
+signal start_timer : unsigned(20 downto 0) := (others => '0');
signal request_retr_i : std_logic;
signal start_retr_i : std_logic;
gen_link_reset : if IS_SYNC_SLAVE = 1 generate
link_reset_pulse : pulse_sync port map(CLK_RXI,'0',make_link_reset_i,
CLK_SYS,'0',make_link_reset_real_i);
- link_reset_send : pulse_sync port map(CLK_RXI,'0',send_link_reset_i,
- CLK_SYS,'0',send_link_reset_real_i);
+ link_reset_send : signal_sync port map(RESET => '0',CLK0 => CLK_RXI,CLK1 => CLK_SYS,
+ D_IN(0) => send_link_reset_i,
+ D_OUT(0) => send_link_reset_real_i);
end generate;
-
-
sd_los_i <= SFP_LOS when rising_edge(CLK_SYS);
media_med2int_i.stat_op(15) <= send_link_reset_real_i when rising_edge(CLK_SYS);
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