-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-01-29">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-01-30">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2021302512" Name="trb3_periph_sodaclient_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2021452834" Name="trb3_periph_sodaclient_LA0" ID="0">
<Setting>
- <Clock SampleClk="the_sync_link/clk_rx_full" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="512"/>
+ <Clock SampleClk="soda_rx_clock_full" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_client_LA0_net"/>
</Bus>
</Trace>
<Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_hub/start_of_superburst_s,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="rxup_dlm_i,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="txup_dlm_i,"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_uplink/watchdog_trigger,"/>
- <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)rxdn_dlm_i[1:0],"/>
- <TU Serialbits="0" Type="0" ID="6" Sig="(BUS)txdn_dlm_i[1:0],"/>
- <TU Serialbits="0" Type="0" ID="7" Sig="a_soda_hub/start_calibration_s,"/>
+ <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_hub/start_of_calibration_s,"/>
+ <TU Serialbits="0" Type="0" ID="2" Sig="the_sync_uplink/watchdog_trigger,"/>
+ <TU Serialbits="0" Type="0" ID="3" Sig="(BUS)rxdn_dlm_i[1:0],"/>
+ <TU Serialbits="0" Type="0" ID="4" Sig="(BUS)txdn_dlm_i[1:0],"/>
+ <TU Serialbits="0" Type="0" ID="5" Sig="a_soda_hub/start_of_calibration_s,"/>
+ <TU Serialbits="0" Type="0" ID="6" Sig="(BUS)a_soda_hub/reply_valid_s[1:0],"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="7" Resource="0"/>
</Trigger>
</Dataset>
</Core>
MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ;
MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20.000000 ns ;
MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
+MULTICYCLE TO CELL "THE_SODA_SOURCE.packet_builder.soda_cmd_word_S*" 10.000000 ns ;
BLOCK JTAGPATHS ;
## IOBUF ALLPORTS ;
#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;\r
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-01-22">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-01-30">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_source"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2020398765" Name="trb3_periph_sodasource_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2021438704" Name="trb3_periph_sodasource_LA0" ID="0">
<Setting>
<Clock SampleClk="rx_clock_full" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="512"/>
<Sig Type="SIG" Name="the_sync_link/wa_position:14"/>
<Sig Type="SIG" Name="the_sync_link/wa_position:15"/>
</Bus>
+ <Sig Type="SIG" Name="the_soda_source/soda_cmd_strobe_s"/>
+ <Sig Type="SIG" Name="the_soda_source/soda_cmd_strobe_sodaclk_s"/>
+ <Sig Type="SIG" Name="the_soda_source/soda_cmd_pending_s"/>
+ <Sig Type="SIG" Name="the_soda_source/soda_send_cmd_s"/>
+ <Sig Type="SIG" Name="the_soda_source/soda_cmd_window_s"/>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="the_soda_source/store_rd,"/>
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
- -- \r
+ --
-- PCSA_REFCLKP : in std_logic; -- external refclock straight into serdes PL!
-- PCSA_REFCLKN : in std_logic; -- external refclock straight into serdes PL!
--Internal Connection TX
RX_DLM : out std_logic := '0';
RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";\r
- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!\r
- LINK_PHASE_OUT : out std_logic := '0'; --PL!
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
+ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!
+ link_PHASE_OUT : out std_logic := '0'; --PL!
--SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ SD_RXD_P_IN : in t_QUAD_BIT; -- well, there's 4 of them...
+ SD_RXD_N_IN : in t_QUAD_BIT;
+ SD_TXD_P_OUT : out t_QUAD_BIT;
+ SD_TXD_N_OUT : out t_QUAD_BIT;
+ SD_REFCLK_P_IN : in t_QUAD_BIT; --not used
+ SD_REFCLK_N_IN : in t_QUAD_BIT; --not used
+ SD_PRSNT_N_IN : in t_QUAD_BIT; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in t_QUAD_BIT; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out t_QUAD_BIT := (others => '0'); -- SFP disable
--Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
-- Status and control port
STAT_OP : out std_logic_vector (15 downto 0);
CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
attribute syn_sharing : string;
attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off";
-\r
+
component DCS
-- synthesis translate_off
--signal refclk_p_in_S : std_logic; --PL!
--signal refclk_n_in_S : std_logic; --PL!
---signal refclk2core_S : std_logic; --PL!\r
-
-signal clk_200_i : std_logic;
-signal clk_200_internal : std_logic;
-signal clk_rx_full : std_logic;
-signal clk_rx_half : std_logic;
-signal clk_tx_full : std_logic;
-signal clk_tx_half : std_logic;
-
-signal tx_data : std_logic_vector(7 downto 0);
-signal tx_k : std_logic;
-signal rx_data : std_logic_vector(7 downto 0);
-signal rx_k : std_logic;
-signal rx_error : std_logic;
-
-signal rst_n : std_logic;
-signal rst : std_logic; -- PL!
-signal rx_serdes_rst : std_logic;
-signal tx_serdes_rst : std_logic;
-signal tx_pcs_rst : std_logic;
-signal rx_pcs_rst : std_logic;
-signal rst_qd : std_logic;
-signal serdes_rst_qd : std_logic;
-signal sd_los_i : std_logic; --PL!
-
-signal rx_los_low : std_logic;
-signal lsm_status : std_logic;
-signal rx_cdr_lol : std_logic;
-signal tx_pll_lol : std_logic;
-
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
-signal sci_data_in_i : std_logic_vector(7 downto 0);
-signal sci_data_out_i : std_logic_vector(7 downto 0);
-signal sci_read_i : std_logic;
-signal sci_write_i : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
-signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow : std_logic;
-signal rx_allow : std_logic;
-signal tx_allow_q : std_logic;
-signal rx_allow_q : std_logic;
-signal link_phase_S : std_logic; --PL!
-signal request_retr_i : std_logic;
-signal start_retr_i : std_logic;
-signal request_retr_position_i : std_logic_vector(7 downto 0);
-signal start_retr_position_i : std_logic_vector(7 downto 0);
-signal send_link_reset_i : std_logic;
-signal make_link_reset_i : std_logic;
-signal got_link_ready_i : std_logic;
-signal internal_make_link_reset_out : std_logic;
-
-signal stat_rx_control_i : std_logic_vector(31 downto 0);
-signal stat_tx_control_i : std_logic_vector(31 downto 0);
-signal debug_rx_control_i : std_logic_vector(31 downto 0);
-signal debug_tx_control_i : std_logic_vector(31 downto 0);
-signal rx_fsm_state : std_logic_vector(3 downto 0);
-signal tx_fsm_state : std_logic_vector(3 downto 0);
-signal debug_reg : std_logic_vector(63 downto 0);
+--signal refclk2core_S : std_logic; --PL!
+
+signal clk_200_i : std_logic;
+signal clk_200_internal : std_logic;
+
+signal rst_n : std_logic;
+signal rst : std_logic; -- PL!
+
+---------------------------
+-- signals for downlinks --
+---------------------------
+signal clk_rx_full : t_QUAD_BIT;
+signal clk_rx_half : t_QUAD_BIT;
+signal clk_tx_full : t_QUAD_BIT;
+signal clk_tx_half : t_QUAD_BIT;
+
+signal tx_data : t_QUAD_BYTE;
+signal tx_k : t_QUAD_BIT;
+signal rx_data : t_QUAD_BYTE;
+signal rx_k : t_QUAD_BIT;
+signal rx_error : t_QUAD_BIT;
+
+signal rx_serdes_rst : t_QUAD_BIT;
+signal tx_serdes_rst : t_QUAD_BIT;
+signal tx_pcs_rst : t_QUAD_BIT;
+signal rx_pcs_rst : t_QUAD_BIT;
+signal rst_qd : t_QUAD_BIT;
+signal serdes_rst_qd : t_QUAD_BIT;
+signal sd_los_i : t_QUAD_BIT; --PL!
+
+signal rx_los_low : t_QUAD_BIT;
+signal lsm_status : t_QUAD_BIT;
+signal rx_cdr_lol : t_QUAD_BIT;
+signal tx_pll_lol : t_QUAD_BIT;
+
+signal wa_position : t_QUAD_WORD := (others => (others => '1'));
+signal wa_position_rx : t_QUAD_WORD := (others => (others => '1'));
+signal tx_allow : t_QUAD_BIT;
+signal rx_allow : t_QUAD_BIT;
+signal tx_allow_q : t_QUAD_BIT;
+signal rx_allow_q : t_QUAD_BIT;
+signal link_phase_S : t_QUAD_BIT; --PL!
+signal request_retr_i : t_QUAD_BIT;
+signal start_retr_i : t_QUAD_BIT;
+signal request_retr_position_i : t_QUAD_BYTE;
+signal start_retr_position_i : t_QUAD_BYTE;
+signal send_link_reset_i : t_QUAD_BIT;
+signal make_link_reset_i : t_QUAD_BIT;
+signal got_link_ready_i : t_QUAD_BIT;
+signal internal_make_link_reset_out : t_QUAD_BIT;
+
+signal stat_rx_control_i : t_QUAD_LWORD;
+signal stat_tx_control_i : t_QUAD_LWORD;
+signal debug_rx_control_i : t_QUAD_LWORD;
+signal debug_tx_control_i : t_QUAD_LWORD;
+signal rx_fsm_state : t_QUAD_NIBL;
+signal tx_fsm_state : t_QUAD_NIBL;
+
+
+signal sci_ch_i : std_logic_vector(3 downto 0);
+signal sci_qd_i : std_logic;
+signal sci_reg_i : std_logic;
+signal sci_addr_i : std_logic_vector(8 downto 0);
+signal sci_data_in_i : std_logic_vector(7 downto 0);
+signal sci_data_out_i : std_logic_vector(7 downto 0);
+signal sci_read_i : std_logic;
+signal sci_write_i : std_logic;
+signal sci_write_shift_i : std_logic_vector(2 downto 0);
+signal sci_read_shift_i : std_logic_vector(2 downto 0);
+
+signal debug_reg : std_logic_vector(63 downto 0);
type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state : sci_ctrl;
-signal sci_timer : unsigned(12 downto 0) := (others => '0');
-signal start_timer : unsigned(18 downto 0) := (others => '0');
-signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
-signal watchdog_trigger : std_logic :='0';
+signal sci_state : sci_ctrl;
+signal sci_timer : unsigned(12 downto 0) := (others => '0');
+signal start_timer : unsigned(18 downto 0) := (others => '0');
+signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
+signal watchdog_trigger : std_logic :='0';
begin
-clk_200_internal <= CLK; \r
+clk_200_internal <= CLK;
-CLK_RX_HALF_OUT <= clk_rx_half;
-CLK_RX_FULL_OUT <= clk_rx_full;
-CLK_TX_HALF_OUT <= clk_tx_half;
-CLK_TX_FULL_OUT <= clk_tx_full;
+CLK_RX_HALF_OUT <= clk_rx_half(0);
+CLK_RX_FULL_OUT <= clk_rx_full(0);
+CLK_TX_HALF_OUT <= clk_tx_half(0);
+CLK_TX_FULL_OUT <= clk_tx_full(0);
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
+SD_TXDIS_OUT <= (others => '0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
---rst_n <= not CLEAR; PL!\r
-rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+--rst_n <= not CLEAR; PL!
+--rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+--rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+rst_n <= 0 when (CLEAR='1') or (sd_los_i='1') or (internal_make_link_reset_out='1') or (watchdog_trigger='1') else '1';
+rst <= 1 when (CLEAR='1') or (sd_los_i='1') or (internal_make_link_reset_out='1') or (watchdog_trigger='1') else '0';
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
-- Serdes
-------------------------------------------------
THE_SERDES : entity work.serdes_sync_downstream
- port map(
--- refclkp => PCSA_REFCLKP, -- external refclock straight into serdes PL!\r
--- refclkn => PCSA_REFCLKN, -- external refclock straight into serdes PL!
- hdinp_ch0 => SD_RXD_P_IN,
- hdinn_ch0 => SD_RXD_N_IN,
- hdoutp_ch0 => SD_TXD_P_OUT,
- hdoutn_ch0 => SD_TXD_N_OUT,
--- rxiclk_ch0 => clk_200_i, -- read fifo is no longer present! PL!
- txiclk_ch0 => clk_200_i,
- rx_full_clk_ch0 => clk_rx_full,
- rx_half_clk_ch0 => clk_rx_half,
- tx_full_clk_ch0 => clk_tx_full,
- tx_half_clk_ch0 => clk_tx_half,
- fpga_rxrefclk_ch0 => clk_200_internal,
- txdata_ch0 => tx_data,
- tx_k_ch0 => tx_k,
- tx_force_disp_ch0 => '0',
- tx_disp_sel_ch0 => '0',
- rxdata_ch0 => rx_data,
- rx_k_ch0 => rx_k,
- rx_disp_err_ch0 => open,
- rx_cv_err_ch0 => rx_error,
- rx_serdes_rst_ch0_c => rx_serdes_rst,
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pcs_rst_ch0_c => tx_pcs_rst,
- tx_pwrup_ch0_c => '1',
- rx_pcs_rst_ch0_c => rx_pcs_rst,
- rx_pwrup_ch0_c => '1',
- rx_los_low_ch0_s => rx_los_low,
- lsm_status_ch0_s => lsm_status,
- rx_cdr_lol_ch0_s => rx_cdr_lol,
- tx_div2_mode_ch0_c => '0',
- rx_div2_mode_ch0_c => '0',\r
- refclk2fpga => open, --refclk2core_S,
-
- SCI_WRDATA => sci_data_in_i,
- SCI_RDDATA => sci_data_out_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_SEL_QUAD => sci_qd_i,
- SCI_SEL_CH0 => sci_ch_i(0),
- SCI_RD => sci_read_i,
- SCI_WRN => sci_write_i,
-
- fpga_txrefclk => clk_200_i,
- tx_serdes_rst_c => tx_serdes_rst,
- tx_pll_lol_qd_s => tx_pll_lol,
- rst_qd_c => rst_qd,
- serdes_rst_qd_c => serdes_rst_qd
+ port map(
+ --------------
+ -- CHANNEL0 --
+ --------------
+ hdinp_ch0 => SD_RXD_P_IN(0),
+ hdinn_ch0 => SD_RXD_N_IN(0),
+ hdoutp_ch0 => SD_TXD_P_OUT(0),
+ hdoutn_ch0 => SD_TXD_N_OUT(0),
+ -- rxiclk_ch0 => clk_200_i, -- read fifo is no longer present! PL!
+ txiclk_ch0 => clk_200_i,
+ rx_full_clk_ch0 => clk_rx_full(0),
+ rx_half_clk_ch0 => clk_rx_half(0),
+ tx_full_clk_ch0 => clk_tx_full(0),
+ tx_half_clk_ch0 => clk_tx_half(0),
+ fpga_rxrefclk_ch0 => clk_200_internal,
+ txdata_ch0 => tx_data(0),
+ tx_k_ch0 => tx_k(0),
+ tx_force_disp_ch0 => '0',
+ tx_disp_sel_ch0 => '0',
+ rxdata_ch0 => rx_data(0),
+ rx_k_ch0 => rx_k(0),
+ rx_disp_err_ch0 => open,
+ rx_cv_err_ch0 => rx_error(0),
+ rx_serdes_rst_ch0_c => rx_serdes_rst(0),
+ sb_felb_ch0_c => '0',
+ sb_felb_rst_ch0_c => '0',
+ tx_pcs_rst_ch0_c => tx_pcs_rst(0),
+ tx_pwrup_ch0_c => '1',
+ rx_pcs_rst_ch0_c => rx_pcs_rst(0),
+ rx_pwr_ch0_c => '1',
+ rx_los_low_ch0_s => rx_los_low(0),
+ lsm_status_ch0_s => lsm_status(0),
+ rx_cdr_lol_ch0_s => rx_cdr_lol(0),
+ tx_div2_mode_ch0_c => '0',
+ rx_div2_mode_ch0_c => '0',
+
+ --------------
+ -- CHANNEL1 --
+ --------------
+ hdinp_ch1 => SD_RXD_P_IN(1),
+ hdinn_ch1 => SD_RXD_N_IN(1),
+ hdoutp_ch1 => SD_TXD_P_OUT(1),
+ hdoutn_ch1 => SD_TXD_N_OUT(1),
+ -- rxiclk_ch1 => clk_200_i, -- read fifo is no longer present! PL!
+ txiclk_ch1 => clk_200_i,
+ rx_full_clk_ch1 => clk_rx_full(1),
+ rx_half_clk_ch1 => clk_rx_half(1),
+ tx_full_clk_ch1 => clk_tx_full(1),
+ tx_half_clk_ch1 => clk_tx_half(1),
+ fpga_rxrefclk_ch1 => clk_200_internal,
+ txdata_ch1 => tx_data(1),
+ tx_k_ch1 => tx_k(1),
+ tx_force_disp_ch1 => '0',
+ tx_disp_sel_ch1 => '0',
+ rxdata_ch1 => rx_data(1),
+ rx_k_ch1 => rx_k(1),
+ rx_disp_err_ch1 => open,
+ rx_cv_err_ch1 => rx_error(1),
+ rx_serdes_rst_ch1_c => rx_serdes_rst(1),
+ sb_felb_ch1_c => '0',
+ sb_felb_rst_ch1_c => '0',
+ tx_pcs_rst_ch1_c => tx_pcs_rst(1),
+ tx_pwrup_ch1_c => '1',
+ rx_pcs_rst_ch1_c => rx_pcs_rst(1),
+ rx_pwr_ch1_c => '1',
+ rx_los_low_ch1_s => rx_los_low(1),
+ lsm_status_ch1_s => lsm_status(1),
+ rx_cdr_lol_ch1_s => rx_cdr_lol(1),
+ tx_div2_mode_ch1_c => '0',
+ rx_div2_mode_ch1_c => '0',
+
+ --------------
+ -- CHANNEL2 --
+ --------------
+ hdinp_ch2 => SD_RXD_P_IN(2),
+ hdinn_ch2 => SD_RXD_N_IN(2),
+ hdoutp_ch2 => SD_TXD_P_OUT(2),
+ hdoutn_ch2 => SD_TXD_N_OUT(2),
+ -- rxiclk_ch2 => clk_200_i, -- read fifo is no longer present! PL!
+ txiclk_ch2 => clk_200_i,
+ rx_full_clk_ch2 => clk_rx_full(2),
+ rx_half_clk_ch2 => clk_rx_half(2),
+ tx_full_clk_ch2 => clk_tx_full(2),
+ tx_half_clk_ch2 => clk_tx_half(2),
+ fpga_rxrefclk_ch2 => clk_200_internal,
+ txdata_ch2 => tx_data(2),
+ tx_k_ch2 => tx_k(2),
+ tx_force_disp_ch2 => '0',
+ tx_disp_sel_ch2 => '0',
+ rxdata_ch2 => rx_data(2),
+ rx_k_ch2 => rx_k(2),
+ rx_disp_err_ch2 => open,
+ rx_cv_err_ch2 => rx_error(2),
+ rx_serdes_rst_ch2_c => rx_serdes_rst(2),
+ sb_felb_ch2_c => '0',
+ sb_felb_rst_ch2_c => '0',
+ tx_pcs_rst_ch2_c => tx_pcs_rst(2),
+ tx_pwrup_ch2_c => '1',
+ rx_pcs_rst_ch2_c => rx_pcs_rst(2),
+ rx_pwr_ch2_c => '1',
+ rx_los_low_ch2_s => rx_los_low(2),
+ lsm_status_ch2_s => lsm_status(2),
+ rx_cdr_lol_ch2_s => rx_cdr_lol(2),
+ tx_div2_mode_ch2_c => '0',
+ rx_div2_mode_ch2_c => '0',
+
+ --------------
+ -- CHANNEL3 --
+ --------------
+ hdinp_ch3 => SD_RXD_P_IN(3),
+ hdinn_ch3 => SD_RXD_N_IN(3),
+ hdoutp_ch3 => SD_TXD_P_OUT(3),
+ hdoutn_ch3 => SD_TXD_N_OUT(3),
+ -- rxiclk_ch3 => clk_200_i, -- read fifo is no longer present! PL!
+ txiclk_ch3 => clk_200_i,
+ rx_full_clk_ch3 => clk_rx_full(3),
+ rx_half_clk_ch3 => clk_rx_half(3),
+ tx_full_clk_ch3 => clk_tx_full(3),
+ tx_half_clk_ch3 => clk_tx_half(3),
+ fpga_rxrefclk_ch3 => clk_200_internal,
+ txdata_ch3 => tx_data(3),
+ tx_k_ch3 => tx_k(3),
+ tx_force_disp_ch3 => '0',
+ tx_disp_sel_ch3 => '0',
+ rxdata_ch3 => rx_data(3),
+ rx_k_ch3 => rx_k(3),
+ rx_disp_err_ch3 => open,
+ rx_cv_err_ch3 => rx_error(3),
+ rx_serdes_rst_ch3_c => rx_serdes_rst(3),
+ sb_felb_ch3_c => '0',
+ sb_felb_rst_ch3_c => '0',
+ tx_pcs_rst_ch3_c => tx_pcs_rst(3),
+ tx_pwrup_ch3_c => '1',
+ rx_pcs_rst_ch3_c => rx_pcs_rst(3),
+ rx_pwr_ch3_c => '1',
+ rx_los_low_ch3_s => rx_los_low(3),
+ lsm_status_ch3_s => lsm_status(3),
+ rx_cdr_lol_ch3_s => rx_cdr_lol(3),
+ tx_div2_mode_ch3_c => '0',
+ rx_div2_mode_ch3_c => '0',
+
+
+ refclk2fpga => open, --refclk2core_S,
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_qd_i,
+ SCI_SEL_CH0 => sci_ch_i(0),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+
+ fpga_txrefclk => clk_200_i,
+ tx_serdes_rst_c => tx_serdes_rst,
+ tx_pll_lol_qd_s => tx_pll_lol,
+ rst_qd_c => rst_qd,
+ serdes_rst_qd_c => serdes_rst_qd
- );
+);
--------------------------------------------------
--- Reset FSM & Link states
--------------------------------------------------
-THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n,
- RX_REFCLK => clk_200_i,
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RX_SERDES_RST_CH_C => rx_serdes_rst,
- RX_CDR_LOL_CH_S => rx_cdr_lol,
- RX_LOS_LOW_CH_S => rx_los_low,
- RX_PCS_RST_CH_C => rx_pcs_rst,
- WA_POSITION => wa_position_rx(3 downto 0),
- STATE_OUT => rx_fsm_state
- );
-
-THE_TX_FSM : tx_reset_fsm
- port map(
- RST_N => rst_n,
- TX_REFCLK => clk_200_internal,
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RST_QD_C => rst_qd,
- TX_PCS_RST_CH_C => tx_pcs_rst,
- STATE_OUT => tx_fsm_state
- );
+
+channel :for i in c_HUB_CHILDREN-1 downto 0 generate
+
+ -------------------------------------------------
+ -- Reset FSM & DOWN-link states
+ -------------------------------------------------
+ THE_RX_FSM : rx_reset_fsm
+ port map(
+ RST_N => rst_n,
+ RX_REFCLK => clk_200_i,
+ TX_PLL_LOL_QD_S => tx_pll_lol(i),
+ RX_SERDES_RST_CH_C => rx_serdes_rst(i),
+ RX_CDR_LOL_CH_S => rx_cdr_lol(i),
+ RX_LOS_LOW_CH_S => rx_los_low(i),
+ RX_PCS_RST_CH_C => rx_pcs_rst(i),
+ WA_POSITION => wa_position_rx(i)(3 downto 0),
+ STATE_OUT => rx_fsm_state(i)
+ );
+
+ THE_TX_FSM : tx_reset_fsm
+ port map(
+ RST_N => rst_n,
+ TX_REFCLK => clk_200_internal,
+ TX_PLL_LOL_QD_S => tx_pll_lol,
+ RST_QD_C => rst_qd,
+ TX_PCS_RST_CH_C => tx_pcs_rst,
+ STATE_OUT => tx_fsm_state
+ );
+end generate;
-- Master does not do bit-locking
wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
rx_allow_q <= rx_allow when rising_edge(SYSCLK);
tx_allow_q <= tx_allow when rising_edge(SYSCLK);
-
---PROC_START_TIMER : process begin
- --wait until rising_edge(clk_200_i);
- --if got_link_ready_i = '1' then
- --if start_timer(start_timer'left) = '0' then
- --start_timer <= start_timer + 1;
- --end if;
- --else
- --start_timer <= (others => '0');
- --end if;
---end process;
PROC_START_TIMER : process(clk_200_i)
begin
START_RETRANSMIT_IN => start_retr_i, --TODO
START_POSITION_IN => request_retr_position_i, --TODO
-\r
+
TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN,
SEND_DLM => TX_DLM,
SEND_DLM_WORD => TX_DLM_WORD,
- SEND_LINK_RESET_IN => CTRL_OP(15),
+ SEND_link_RESET_IN => CTRL_OP(15),
TX_ALLOW_IN => tx_allow,
- RX_ALLOW_IN => rx_allow,\r
- LINK_PHASE_OUT => link_phase_S, --PL!
+ RX_ALLOW_IN => rx_allow,
+ link_PHASE_OUT => link_phase_S, --PL!
DEBUG_OUT => debug_tx_control_i,
STAT_REG_OUT => stat_tx_control_i
);
-LINK_PHASE_OUT <= link_phase_S; --PL!
+link_PHASE_OUT <= link_phase_S; --PL!
-------------------------------------------------
-- RX Data
-------------------------------------------------
RX_DLM => RX_DLM,
RX_DLM_WORD => RX_DLM_WORD,
- SEND_LINK_RESET_OUT => send_link_reset_i,
+ SEND_link_RESET_OUT => send_link_reset_i,
MAKE_RESET_OUT => make_link_reset_i,
RX_ALLOW_IN => rx_allow,
- GOT_LINK_READY => got_link_ready_i,
+ GOT_link_READY => got_link_ready_i,
DEBUG_OUT => debug_rx_control_i,
STAT_REG_OUT => stat_rx_control_i
STAT_OP(5) <= request_retr_i;
STAT_OP(4) <= start_retr_i;
STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-end med_ecp3_sfp_sync_down_arch;
-
+end med_ecp3_sfp_sync_down_arch;
\ No newline at end of file
-------------------------------------------------
THE_SERDES : entity work.serdes_sync_upstream
port map(
- hdinp_ch0 => SD_RXD_P_IN,
- hdinn_ch0 => SD_RXD_N_IN,
- hdoutp_ch0 => SD_TXD_P_OUT,
- hdoutn_ch0 => SD_TXD_N_OUT,
--- rxiclk_ch0 => clk_200_i, -- no more RX-fifo
- txiclk_ch0 => clk_200_i,
- rx_full_clk_ch0 => clk_rx_full,
- rx_half_clk_ch0 => clk_rx_half,
- tx_full_clk_ch0 => clk_tx_full,
- tx_half_clk_ch0 => clk_tx_half,
- fpga_rxrefclk_ch0 => clk_200_internal,
- txdata_ch0 => tx_data,
- tx_k_ch0 => tx_k,
- tx_force_disp_ch0 => '0',
- tx_disp_sel_ch0 => '0',
- rxdata_ch0 => rx_data,
- rx_k_ch0 => rx_k,
- rx_disp_err_ch0 => open,
- rx_cv_err_ch0 => rx_error,
- rx_serdes_rst_ch0_c => rx_serdes_rst,
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pcs_rst_ch0_c => tx_pcs_rst,
- tx_pwrup_ch0_c => '1',
- rx_pcs_rst_ch0_c => rx_pcs_rst,
- rx_pwrup_ch0_c => '1',
- rx_los_low_ch0_s => rx_los_low,
- lsm_status_ch0_s => lsm_status,
- rx_cdr_lol_ch0_s => rx_cdr_lol,
- tx_div2_mode_ch0_c => '0',
- rx_div2_mode_ch0_c => '0',
+ hdinp_ch3 => SD_RXD_P_IN,
+ hdinn_ch3 => SD_RXD_N_IN,
+ hdoutp_ch3 => SD_TXD_P_OUT,
+ hdoutn_ch3 => SD_TXD_N_OUT,
+-- rxiclk_ch3 => clk_200_i, -- no more RX-fifo
+ txiclk_ch3 => clk_200_i,
+ rx_full_clk_ch3 => clk_rx_full,
+ rx_half_clk_ch3 => clk_rx_half,
+ tx_full_clk_ch3 => clk_tx_full,
+ tx_half_clk_ch3 => clk_tx_half,
+ fpga_rxrefclk_ch3 => clk_200_internal,
+ txdata_ch3 => tx_data,
+ tx_k_ch3 => tx_k,
+ tx_force_disp_ch3 => '0',
+ tx_disp_sel_ch3 => '0',
+ rxdata_ch3 => rx_data,
+ rx_k_ch3 => rx_k,
+ rx_disp_err_ch3 => open,
+ rx_cv_err_ch3 => rx_error,
+ rx_serdes_rst_ch3_c => rx_serdes_rst,
+ sb_felb_ch3_c => '0',
+ sb_felb_rst_ch3_c => '0',
+ tx_pcs_rst_ch3_c => tx_pcs_rst,
+ tx_pwrup_ch3_c => '1',
+ rx_pcs_rst_ch3_c => rx_pcs_rst,
+ rx_pwrup_ch3_c => '1',
+ rx_los_low_ch3_s => rx_los_low,
+ lsm_status_ch3_s => lsm_status,
+ rx_cdr_lol_ch3_s => rx_cdr_lol,
+ tx_div2_mode_ch3_c => '0',
+ rx_div2_mode_ch3_c => '0',
SCI_WRDATA => sci_data_in_i,
SCI_RDDATA => sci_data_out_i,
SCI_ADDR => sci_addr_i(5 downto 0),
SCI_SEL_QUAD => sci_qd_i,
- SCI_SEL_CH0 => sci_ch_i(0),
+ SCI_SEL_CH3 => sci_ch_i(0),
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 21 12:02:05.297" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 02 04 15:43:09.526" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 01 21 12:02:01.000"/>
- <File name="serdes_sync_downstream.pp" type="pp" modified="2014 01 21 12:02:01.000"/>
- <File name="serdes_sync_downstream.sym" type="sym" modified="2014 01 21 12:02:01.000"/>
- <File name="serdes_sync_downstream.tft" type="tft" modified="2014 01 21 12:02:01.000"/>
- <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 01 21 12:02:01.000"/>
- <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 01 21 12:02:01.000"/>
+ <File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 02 04 15:43:06.000"/>
+ <File name="serdes_sync_downstream.pp" type="pp" modified="2014 02 04 15:43:06.000"/>
+ <File name="serdes_sync_downstream.sym" type="sym" modified="2014 02 04 15:43:06.000"/>
+ <File name="serdes_sync_downstream.tft" type="tft" modified="2014 02 04 15:43:06.000"/>
+ <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 02 04 15:43:06.000"/>
+ <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 02 04 15:43:06.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=01/21/2014
-Time=12:02:01
+Date=02/04/2014
+Time=15:43:06
[Parameters]
Verilog=0
Order=Big Endian [MSB:LSB]
IO=0
_mode0=RXTX
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=DISABLED
+_mode1=RXTX
+_mode2=RXTX
+_mode3=RXTX
_protocol0=G8B10B
_protocol1=G8B10B
_protocol2=G8B10B
_refclk_mult=10X
_refclk_rate=200
_tx_protocol0=G8B10B
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
+_tx_protocol1=G8B10B
+_tx_protocol2=G8B10B
+_tx_protocol3=G8B10B
_tx_data_rate0=FULL
_tx_data_rate1=FULL
_tx_data_rate2=FULL
_tx_ficlk_rate2=200
_tx_ficlk_rate3=200
_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
+_pll_rxsrc1=INTERNAL
+_pll_rxsrc2=INTERNAL
+_pll_rxsrc3=INTERNAL
Multiplier0=
Multiplier1=
Multiplier2=
Multiplier3=
_rx_datarange0=2
-_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=2.5
+_rx_datarange1=2
+_rx_datarange2=2
+_rx_datarange3=2
_rx_protocol0=G8B10B
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
+_rx_protocol1=G8B10B
+_rx_protocol2=G8B10B
+_rx_protocol3=G8B10B
_rx_data_rate0=FULL
_rx_data_rate1=FULL
_rx_data_rate2=FULL
_rx_data_rate3=FULL
_rxrefclk_rate0=200
-_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=250.0
+_rxrefclk_rate1=200
+_rxrefclk_rate2=200
+_rxrefclk_rate3=200
_rx_data_width0=8
_rx_data_width1=8
_rx_data_width2=8
_rx_data_width3=8
_rx_fifo0=DISABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
+_rx_fifo1=DISABLED
+_rx_fifo2=DISABLED
+_rx_fifo3=DISABLED
_rx_ficlk_rate0=200
-_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=250.0
+_rx_ficlk_rate1=200
+_rx_ficlk_rate2=200
+_rx_ficlk_rate3=200
_tdrv_ch0=0
_tdrv_ch1=0
_tdrv_ch2=0
_rterm_rx2=50
_rterm_rx3=50
_rx_dcc0=DC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=AC
+_rx_dcc1=DC
+_rx_dcc2=DC
+_rx_dcc3=DC
_los_threshold_mode0=LOS_E
_los_threshold_mode1=LOS_E
_los_threshold_mode2=LOS_E
_cc_match_mode2=1
_cc_match_mode3=1
_k00=01
-_k01=00
-_k02=00
-_k03=00
+_k01=01
+_k02=01
+_k03=01
_k10=00
_k11=00
_k12=00
_k32=01
_k33=01
_byten00=00011100
-_byten01=00000000
-_byten02=00000000
-_byten03=00000000
+_byten01=00011100
+_byten02=00011100
+_byten03=00011100
_byten10=00000000
_byten11=00000000
_byten12=00000000
DEVICE_NAME "LFE3-150EA"
CH0_PROTOCOL "G8B10B"
+CH1_PROTOCOL "G8B10B"
+CH2_PROTOCOL "G8B10B"
+CH3_PROTOCOL "G8B10B"
CH0_MODE "RXTX"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
+CH1_MODE "RXTX"
+CH2_MODE "RXTX"
+CH3_MODE "RXTX"
CH0_CDR_SRC "REFCLK_CORE"
+CH1_CDR_SRC "REFCLK_CORE"
+CH2_CDR_SRC "REFCLK_CORE"
+CH3_CDR_SRC "REFCLK_CORE"
PLL_SRC "REFCLK_CORE"
TX_DATARATE_RANGE "MEDHIGH"
CH0_RX_DATARATE_RANGE "MEDHIGH"
+CH1_RX_DATARATE_RANGE "MEDHIGH"
+CH2_RX_DATARATE_RANGE "MEDHIGH"
+CH3_RX_DATARATE_RANGE "MEDHIGH"
REFCK_MULT "10X"
#REFCLK_RATE 200
CH0_RX_DATA_RATE "FULL"
+CH1_RX_DATA_RATE "FULL"
+CH2_RX_DATA_RATE "FULL"
+CH3_RX_DATA_RATE "FULL"
CH0_TX_DATA_RATE "FULL"
+CH1_TX_DATA_RATE "FULL"
+CH2_TX_DATA_RATE "FULL"
+CH3_TX_DATA_RATE "FULL"
CH0_TX_DATA_WIDTH "8"
+CH1_TX_DATA_WIDTH "8"
+CH2_TX_DATA_WIDTH "8"
+CH3_TX_DATA_WIDTH "8"
CH0_RX_DATA_WIDTH "8"
+CH1_RX_DATA_WIDTH "8"
+CH2_RX_DATA_WIDTH "8"
+CH3_RX_DATA_WIDTH "8"
CH0_TX_FIFO "DISABLED"
+CH1_TX_FIFO "ENABLED"
+CH2_TX_FIFO "ENABLED"
+CH3_TX_FIFO "ENABLED"
CH0_RX_FIFO "DISABLED"
+CH1_RX_FIFO "DISABLED"
+CH2_RX_FIFO "DISABLED"
+CH3_RX_FIFO "DISABLED"
CH0_TDRV "0"
+CH1_TDRV "0"
+CH2_TDRV "0"
+CH3_TDRV "0"
#CH0_TX_FICLK_RATE 200
+#CH1_TX_FICLK_RATE 200
+#CH2_TX_FICLK_RATE 200
+#CH3_TX_FICLK_RATE 200
#CH0_RXREFCLK_RATE "200"
+#CH1_RXREFCLK_RATE "200"
+#CH2_RXREFCLK_RATE "200"
+#CH3_RXREFCLK_RATE "200"
#CH0_RX_FICLK_RATE 200
+#CH1_RX_FICLK_RATE 200
+#CH2_RX_FICLK_RATE 200
+#CH3_RX_FICLK_RATE 200
CH0_TX_PRE "DISABLED"
+CH1_TX_PRE "DISABLED"
+CH2_TX_PRE "DISABLED"
+CH3_TX_PRE "DISABLED"
CH0_RTERM_TX "50"
+CH1_RTERM_TX "50"
+CH2_RTERM_TX "50"
+CH3_RTERM_TX "50"
CH0_RX_EQ "DISABLED"
+CH1_RX_EQ "DISABLED"
+CH2_RX_EQ "DISABLED"
+CH3_RX_EQ "DISABLED"
CH0_RTERM_RX "50"
+CH1_RTERM_RX "50"
+CH2_RTERM_RX "50"
+CH3_RTERM_RX "50"
CH0_RX_DCC "DC"
+CH1_RX_DCC "DC"
+CH2_RX_DCC "DC"
+CH3_RX_DCC "DC"
CH0_LOS_THRESHOLD_LO "2"
+CH1_LOS_THRESHOLD_LO "2"
+CH2_LOS_THRESHOLD_LO "2"
+CH3_LOS_THRESHOLD_LO "2"
PLL_TERM "50"
PLL_DCC "AC"
PLL_LOL_SET "0"
CH0_TX_SB "DISABLED"
+CH1_TX_SB "DISABLED"
+CH2_TX_SB "DISABLED"
+CH3_TX_SB "DISABLED"
CH0_RX_SB "DISABLED"
+CH1_RX_SB "DISABLED"
+CH2_RX_SB "DISABLED"
+CH3_RX_SB "DISABLED"
CH0_TX_8B10B "ENABLED"
+CH1_TX_8B10B "ENABLED"
+CH2_TX_8B10B "ENABLED"
+CH3_TX_8B10B "ENABLED"
CH0_RX_8B10B "ENABLED"
+CH1_RX_8B10B "ENABLED"
+CH2_RX_8B10B "ENABLED"
+CH3_RX_8B10B "ENABLED"
CH0_COMMA_A "1100000101"
+CH1_COMMA_A "1100000101"
+CH2_COMMA_A "1100000101"
+CH3_COMMA_A "1100000101"
CH0_COMMA_B "0011111010"
+CH1_COMMA_B "0011111010"
+CH2_COMMA_B "0011111010"
+CH3_COMMA_B "0011111010"
CH0_COMMA_M "1111111100"
+CH1_COMMA_M "1111111100"
+CH2_COMMA_M "1111111100"
+CH3_COMMA_M "1111111100"
CH0_RXWA "ENABLED"
+CH1_RXWA "ENABLED"
+CH2_RXWA "ENABLED"
+CH3_RXWA "ENABLED"
CH0_ILSM "ENABLED"
+CH1_ILSM "ENABLED"
+CH2_ILSM "ENABLED"
+CH3_ILSM "ENABLED"
CH0_CTC "DISABLED"
+CH1_CTC "DISABLED"
+CH2_CTC "DISABLED"
+CH3_CTC "DISABLED"
CH0_CC_MATCH4 "0100011100"
+CH1_CC_MATCH4 "0100011100"
+CH2_CC_MATCH4 "0100011100"
+CH3_CC_MATCH4 "0100011100"
CH0_CC_MATCH_MODE "1"
+CH1_CC_MATCH_MODE "1"
+CH2_CC_MATCH_MODE "1"
+CH3_CC_MATCH_MODE "1"
CH0_CC_MIN_IPG "3"
+CH1_CC_MIN_IPG "3"
+CH2_CC_MIN_IPG "3"
+CH3_CC_MIN_IPG "3"
CCHMARK "9"
CCLMARK "7"
CH0_SSLB "DISABLED"
+CH1_SSLB "DISABLED"
+CH2_SSLB "DISABLED"
+CH3_SSLB "DISABLED"
CH0_SPLBPORTS "DISABLED"
+CH1_SPLBPORTS "DISABLED"
+CH2_SPLBPORTS "DISABLED"
+CH3_SPLBPORTS "DISABLED"
CH0_PCSLBPORTS "DISABLED"
+CH1_PCSLBPORTS "DISABLED"
+CH2_PCSLBPORTS "DISABLED"
+CH3_PCSLBPORTS "DISABLED"
INT_ALL "DISABLED"
QD_REFCK2CORE "ENABLED"
-- CONFIG_FILE : String := "serdes_sync_downstream.txt";
-- QUAD_MODE : String := "SINGLE";
-- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
+-- CH1_CDR_SRC : String := "REFCLK_CORE";
+-- CH2_CDR_SRC : String := "REFCLK_CORE";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
-- PLL_SRC : String := "REFCLK_CORE"
);
port (
tx_pcs_rst_ch0_c : in std_logic;
tx_pwrup_ch0_c : in std_logic;
rx_pcs_rst_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
+ rx_pwr_ch0_c : in std_logic;
rx_los_low_ch0_s : out std_logic;
lsm_status_ch0_s : out std_logic;
rx_cdr_lol_ch0_s : out std_logic;
tx_div2_mode_ch0_c : in std_logic;
rx_div2_mode_ch0_c : in std_logic;
-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (7 downto 0);
+ tx_k_ch1 : in std_logic;
+ tx_force_disp_ch1 : in std_logic;
+ tx_disp_sel_ch1 : in std_logic;
+ rxdata_ch1 : out std_logic_vector (7 downto 0);
+ rx_k_ch1 : out std_logic;
+ rx_disp_err_ch1 : out std_logic;
+ rx_cv_err_ch1 : out std_logic;
+ rx_serdes_rst_ch1_c : in std_logic;
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pcs_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pcs_rst_ch1_c : in std_logic;
+ rx_pwr_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ sci_sel_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (7 downto 0);
+ tx_k_ch2 : in std_logic;
+ tx_force_disp_ch2 : in std_logic;
+ tx_disp_sel_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ rx_serdes_rst_ch2_c : in std_logic;
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pcs_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pcs_rst_ch2_c : in std_logic;
+ rx_pwr_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ tx_div2_mode_ch2_c : in std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (7 downto 0);
+ tx_k_ch3 : in std_logic;
+ tx_force_disp_ch3 : in std_logic;
+ tx_disp_sel_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ rx_serdes_rst_ch3_c : in std_logic;
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pcs_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pcs_rst_ch3_c : in std_logic;
+ rx_pwr_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
---- Miscillaneous ports
sci_wrdata : in std_logic_vector (7 downto 0);
sci_addr : in std_logic_vector (5 downto 0);
fpga_txrefclk : in std_logic;
tx_serdes_rst_c : in std_logic;
tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
rst_qd_c : in std_logic;
refclk2fpga : out std_logic;
serdes_rst_qd_c : in std_logic);
attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute CH0_CDR_SRC: string;
attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH1_CDR_SRC: string;
+ attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH2_CDR_SRC: string;
+ attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH3_CDR_SRC: string;
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
signal cin : std_logic_vector (11 downto 0) := "000000000000";
signal cout : std_logic_vector (19 downto 0);
signal tx_full_clk_ch0_sig : std_logic;
+signal tx_full_clk_ch1_sig : std_logic;
+signal tx_full_clk_ch2_sig : std_logic;
+signal tx_full_clk_ch3_sig : std_logic;
signal refclk2fpga_sig : std_logic;
signal tx_pll_lol_qd_sig : std_logic;
refclk2fpga <= refclk2fpga_sig;
rx_los_low_ch0_s <= rx_los_low_ch0_sig;
+ rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+ rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+ rx_los_low_ch3_s <= rx_los_low_ch3_sig;
rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+ rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+ rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
+ rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
+ tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
+ tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
+ tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-- pcs_quad instance
PCSD_INST : PCSD
generic map (CONFIG_FILE => USER_CONFIG_FILE,
QUAD_MODE => "SINGLE",
CH0_CDR_SRC => "REFCLK_CORE",
+ CH1_CDR_SRC => "REFCLK_CORE",
+ CH2_CDR_SRC => "REFCLK_CORE",
+ CH3_CDR_SRC => "REFCLK_CORE",
PLL_SRC => "REFCLK_CORE"
)
--synopsys translate_on
FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
- FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
+ FFC_RXPWDNB_0 => rx_pwr_ch0_c,
FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
FFS_RLOS_HI_0 => open,
FFS_PCIE_CON_0 => open,
FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
----- CH1 -----
- HDOUTP1 => open,
- HDOUTN1 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
+ HDOUTP1 => hdoutp_ch1,
+ HDOUTN1 => hdoutn_ch1,
+ HDINP1 => hdinp_ch1,
+ HDINN1 => hdinn_ch1,
PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
PCIE_RXPOLARITY_1 => fpsc_vlo,
PCIE_POWERDOWN_1_1 => fpsc_vlo,
PCIE_RXVALID_1 => open,
PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
+ SCISELCH1 => sci_sel_ch1,
+ SCIENCH1 => fpsc_vhi,
FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
+ FF_TXI_CLK_1 => txiclk_ch1,
FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_TX_F_CLK_1 => open,
- FF_TX_H_CLK_1 => open,
- FFC_CK_CORE_RX_1 => fpsc_vlo,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
+ FF_RX_F_CLK_1 => rx_full_clk_ch1,
+ FF_RX_H_CLK_1 => rx_half_clk_ch1,
+ FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
+ FF_TX_H_CLK_1 => tx_half_clk_ch1,
+ FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+ FF_TX_D_1_0 => txdata_ch1(0),
+ FF_TX_D_1_1 => txdata_ch1(1),
+ FF_TX_D_1_2 => txdata_ch1(2),
+ FF_TX_D_1_3 => txdata_ch1(3),
+ FF_TX_D_1_4 => txdata_ch1(4),
+ FF_TX_D_1_5 => txdata_ch1(5),
+ FF_TX_D_1_6 => txdata_ch1(6),
+ FF_TX_D_1_7 => txdata_ch1(7),
+ FF_TX_D_1_8 => tx_k_ch1,
+ FF_TX_D_1_9 => tx_force_disp_ch1,
+ FF_TX_D_1_10 => tx_disp_sel_ch1,
FF_TX_D_1_11 => fpsc_vlo,
FF_TX_D_1_12 => fpsc_vlo,
FF_TX_D_1_13 => fpsc_vlo,
FF_TX_D_1_21 => fpsc_vlo,
FF_TX_D_1_22 => fpsc_vlo,
FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
+ FF_RX_D_1_0 => rxdata_ch1(0),
+ FF_RX_D_1_1 => rxdata_ch1(1),
+ FF_RX_D_1_2 => rxdata_ch1(2),
+ FF_RX_D_1_3 => rxdata_ch1(3),
+ FF_RX_D_1_4 => rxdata_ch1(4),
+ FF_RX_D_1_5 => rxdata_ch1(5),
+ FF_RX_D_1_6 => rxdata_ch1(6),
+ FF_RX_D_1_7 => rxdata_ch1(7),
+ FF_RX_D_1_8 => rx_k_ch1,
+ FF_RX_D_1_9 => rx_disp_err_ch1,
+ FF_RX_D_1_10 => rx_cv_err_ch1,
FF_RX_D_1_11 => open,
FF_RX_D_1_12 => open,
FF_RX_D_1_13 => open,
FF_RX_D_1_22 => open,
FF_RX_D_1_23 => open,
- FFC_RRST_1 => fpsc_vlo,
+ FFC_RRST_1 => rx_serdes_rst_ch1_c,
FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
+ FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
FFC_SB_INV_RX_1 => fpsc_vlo,
FFC_PCIE_CT_1 => fpsc_vlo,
FFC_PCI_DET_EN_1 => fpsc_vlo,
FFC_FB_LOOPBACK_1 => fpsc_vlo,
FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
+ FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
+ FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
+ FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+ FFC_RXPWDNB_1 => rx_pwr_ch1_c,
+ FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
FFS_RLOS_HI_1 => open,
FFS_PCIE_CON_1 => open,
FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
+ FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
FFS_CC_OVERRUN_1 => open,
FFS_CC_UNDERRUN_1 => open,
FFS_SKP_ADDED_1 => open,
FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => open,
+ FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
FFS_RXFBFIFO_ERROR_1 => open,
FFS_TXFBFIFO_ERROR_1 => open,
LDR_CORE2TX_1 => fpsc_vlo,
LDR_RX2CORE_1 => open,
FFS_CDR_TRAIN_DONE_1 => open,
FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
----- CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
+ HDOUTP2 => hdoutp_ch2,
+ HDOUTN2 => hdoutn_ch2,
+ HDINP2 => hdinp_ch2,
+ HDINN2 => hdinn_ch2,
PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
PCIE_RXPOLARITY_2 => fpsc_vlo,
PCIE_POWERDOWN_2_1 => fpsc_vlo,
PCIE_RXVALID_2 => open,
PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
+ SCISELCH2 => sci_sel_ch2,
+ SCIENCH2 => fpsc_vhi,
FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
+ FF_TXI_CLK_2 => txiclk_ch2,
FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
+ FF_RX_F_CLK_2 => rx_full_clk_ch2,
+ FF_RX_H_CLK_2 => rx_half_clk_ch2,
+ FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
+ FF_TX_H_CLK_2 => tx_half_clk_ch2,
+ FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+ FF_TX_D_2_0 => txdata_ch2(0),
+ FF_TX_D_2_1 => txdata_ch2(1),
+ FF_TX_D_2_2 => txdata_ch2(2),
+ FF_TX_D_2_3 => txdata_ch2(3),
+ FF_TX_D_2_4 => txdata_ch2(4),
+ FF_TX_D_2_5 => txdata_ch2(5),
+ FF_TX_D_2_6 => txdata_ch2(6),
+ FF_TX_D_2_7 => txdata_ch2(7),
+ FF_TX_D_2_8 => tx_k_ch2,
+ FF_TX_D_2_9 => tx_force_disp_ch2,
+ FF_TX_D_2_10 => tx_disp_sel_ch2,
FF_TX_D_2_11 => fpsc_vlo,
FF_TX_D_2_12 => fpsc_vlo,
FF_TX_D_2_13 => fpsc_vlo,
FF_TX_D_2_21 => fpsc_vlo,
FF_TX_D_2_22 => fpsc_vlo,
FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
+ FF_RX_D_2_0 => rxdata_ch2(0),
+ FF_RX_D_2_1 => rxdata_ch2(1),
+ FF_RX_D_2_2 => rxdata_ch2(2),
+ FF_RX_D_2_3 => rxdata_ch2(3),
+ FF_RX_D_2_4 => rxdata_ch2(4),
+ FF_RX_D_2_5 => rxdata_ch2(5),
+ FF_RX_D_2_6 => rxdata_ch2(6),
+ FF_RX_D_2_7 => rxdata_ch2(7),
+ FF_RX_D_2_8 => rx_k_ch2,
+ FF_RX_D_2_9 => rx_disp_err_ch2,
+ FF_RX_D_2_10 => rx_cv_err_ch2,
FF_RX_D_2_11 => open,
FF_RX_D_2_12 => open,
FF_RX_D_2_13 => open,
FF_RX_D_2_22 => open,
FF_RX_D_2_23 => open,
- FFC_RRST_2 => fpsc_vlo,
+ FFC_RRST_2 => rx_serdes_rst_ch2_c,
FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
+ FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
FFC_SB_INV_RX_2 => fpsc_vlo,
FFC_PCIE_CT_2 => fpsc_vlo,
FFC_PCI_DET_EN_2 => fpsc_vlo,
FFC_FB_LOOPBACK_2 => fpsc_vlo,
FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
+ FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
+ FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
+ FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+ FFC_RXPWDNB_2 => rx_pwr_ch2_c,
+ FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
FFS_RLOS_HI_2 => open,
FFS_PCIE_CON_2 => open,
FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
+ FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
FFS_CC_OVERRUN_2 => open,
FFS_CC_UNDERRUN_2 => open,
FFS_SKP_ADDED_2 => open,
FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
+ FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
FFS_RXFBFIFO_ERROR_2 => open,
FFS_TXFBFIFO_ERROR_2 => open,
LDR_CORE2TX_2 => fpsc_vlo,
LDR_RX2CORE_2 => open,
FFS_CDR_TRAIN_DONE_2 => open,
FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
----- CH3 -----
- HDOUTP3 => open,
- HDOUTN3 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
+ HDOUTP3 => hdoutp_ch3,
+ HDOUTN3 => hdoutn_ch3,
+ HDINP3 => hdinp_ch3,
+ HDINN3 => hdinn_ch3,
PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
PCIE_RXPOLARITY_3 => fpsc_vlo,
PCIE_POWERDOWN_3_1 => fpsc_vlo,
PCIE_RXVALID_3 => open,
PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
+ SCISELCH3 => sci_sel_ch3,
+ SCIENCH3 => fpsc_vhi,
FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => txiclk_ch3,
FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_TX_F_CLK_3 => open,
- FF_TX_H_CLK_3 => open,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
+ FF_RX_F_CLK_3 => rx_full_clk_ch3,
+ FF_RX_H_CLK_3 => rx_half_clk_ch3,
+ FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+ FF_TX_H_CLK_3 => tx_half_clk_ch3,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+ FF_TX_D_3_0 => txdata_ch3(0),
+ FF_TX_D_3_1 => txdata_ch3(1),
+ FF_TX_D_3_2 => txdata_ch3(2),
+ FF_TX_D_3_3 => txdata_ch3(3),
+ FF_TX_D_3_4 => txdata_ch3(4),
+ FF_TX_D_3_5 => txdata_ch3(5),
+ FF_TX_D_3_6 => txdata_ch3(6),
+ FF_TX_D_3_7 => txdata_ch3(7),
+ FF_TX_D_3_8 => tx_k_ch3,
+ FF_TX_D_3_9 => tx_force_disp_ch3,
+ FF_TX_D_3_10 => tx_disp_sel_ch3,
FF_TX_D_3_11 => fpsc_vlo,
FF_TX_D_3_12 => fpsc_vlo,
FF_TX_D_3_13 => fpsc_vlo,
FF_TX_D_3_21 => fpsc_vlo,
FF_TX_D_3_22 => fpsc_vlo,
FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
+ FF_RX_D_3_0 => rxdata_ch3(0),
+ FF_RX_D_3_1 => rxdata_ch3(1),
+ FF_RX_D_3_2 => rxdata_ch3(2),
+ FF_RX_D_3_3 => rxdata_ch3(3),
+ FF_RX_D_3_4 => rxdata_ch3(4),
+ FF_RX_D_3_5 => rxdata_ch3(5),
+ FF_RX_D_3_6 => rxdata_ch3(6),
+ FF_RX_D_3_7 => rxdata_ch3(7),
+ FF_RX_D_3_8 => rx_k_ch3,
+ FF_RX_D_3_9 => rx_disp_err_ch3,
+ FF_RX_D_3_10 => rx_cv_err_ch3,
FF_RX_D_3_11 => open,
FF_RX_D_3_12 => open,
FF_RX_D_3_13 => open,
FF_RX_D_3_22 => open,
FF_RX_D_3_23 => open,
- FFC_RRST_3 => fpsc_vlo,
+ FFC_RRST_3 => rx_serdes_rst_ch3_c,
FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+ FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
FFC_SB_INV_RX_3 => fpsc_vlo,
FFC_PCIE_CT_3 => fpsc_vlo,
FFC_PCI_DET_EN_3 => fpsc_vlo,
FFC_FB_LOOPBACK_3 => fpsc_vlo,
FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
+ FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+ FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+ FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+ FFC_RXPWDNB_3 => rx_pwr_ch3_c,
+ FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
FFS_RLOS_HI_3 => open,
FFS_PCIE_CON_3 => open,
FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
+ FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
FFS_CC_OVERRUN_3 => open,
FFS_CC_UNDERRUN_3 => open,
FFS_SKP_ADDED_3 => open,
FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => open,
+ FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
FFS_RXFBFIFO_ERROR_3 => open,
FFS_TXFBFIFO_ERROR_3 => open,
LDR_CORE2TX_3 => fpsc_vlo,
LDR_RX2CORE_3 => open,
FFS_CDR_TRAIN_DONE_3 => open,
FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
----- Auxilliary ----
SCIWDATA7 => sci_wrdata(7),
FFC_QUAD_RST => rst_qd_c,
FFC_TRST => tx_serdes_rst_c,
FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
+ FFC_SYNC_TOGGLE => tx_sync_qd_c,
REFCK2CORE => refclk2fpga_sig,
CIN0 => fpsc_vlo,
CIN1 => fpsc_vlo,
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 16 15:35:13.845" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 02 05 09:13:24.083" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 01 16 15:35:12.000"/>
- <File name="serdes_sync_upstream.pp" type="pp" modified="2014 01 16 15:35:12.000"/>
- <File name="serdes_sync_upstream.sym" type="sym" modified="2014 01 16 15:35:12.000"/>
- <File name="serdes_sync_upstream.tft" type="tft" modified="2014 01 16 15:34:47.000"/>
- <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 01 16 15:35:12.000"/>
- <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 01 16 15:34:47.000"/>
+ <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 02 05 09:13:21.000"/>
+ <File name="serdes_sync_upstream.pp" type="pp" modified="2014 02 05 09:13:21.000"/>
+ <File name="serdes_sync_upstream.sym" type="sym" modified="2014 02 05 09:13:21.000"/>
+ <File name="serdes_sync_upstream.tft" type="tft" modified="2014 02 05 09:13:21.000"/>
+ <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 02 05 09:13:21.000"/>
+ <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 02 05 09:13:21.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_upstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=01/16/2014
-Time=15:35:12
+Date=02/05/2014
+Time=09:13:21
[Parameters]
Verilog=0
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
-_mode0=RXTX
+_mode0=DISABLED
_mode1=DISABLED
_mode2=DISABLED
-_mode3=DISABLED
+_mode3=RXTX
_protocol0=G8B10B
_protocol1=G8B10B
_protocol2=G8B10B
_pll_txsrc=INTERNAL
_refclk_mult=10X
_refclk_rate=200.0
-_tx_protocol0=G8B10B
+_tx_protocol0=DISABLED
_tx_protocol1=DISABLED
_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
+_tx_protocol3=G8B10B
_tx_data_rate0=FULL
_tx_data_rate1=FULL
_tx_data_rate2=FULL
_pll_rxsrc0=INTERNAL
_pll_rxsrc1=EXTERNAL
_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
+_pll_rxsrc3=INTERNAL
Multiplier0=
Multiplier1=
Multiplier2=
_rx_datarange0=2.0
_rx_datarange1=2.5
_rx_datarange2=2.5
-_rx_datarange3=2.5
-_rx_protocol0=G8B10B
+_rx_datarange3=2
+_rx_protocol0=DISABLED
_rx_protocol1=DISABLED
_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
+_rx_protocol3=G8B10B
_rx_data_rate0=FULL
_rx_data_rate1=FULL
_rx_data_rate2=FULL
_rxrefclk_rate0=200.0
_rxrefclk_rate1=250.0
_rxrefclk_rate2=250.0
-_rxrefclk_rate3=250.0
+_rxrefclk_rate3=200
_rx_data_width0=8
_rx_data_width1=8
_rx_data_width2=8
_rx_fifo0=DISABLED
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
+_rx_fifo3=DISABLED
_rx_ficlk_rate0=200.0
_rx_ficlk_rate1=250.0
_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=250.0
+_rx_ficlk_rate3=200
_tdrv_ch0=0
_tdrv_ch1=0
_tdrv_ch2=0
_rx_dcc0=AC
_rx_dcc1=AC
_rx_dcc2=AC
-_rx_dcc3=AC
+_rx_dcc3=DC
_los_threshold_mode0=LOS_E
_los_threshold_mode1=LOS_E
_los_threshold_mode2=LOS_E
_cc_match_mode3=1
_k00=01
_k01=00
-_k02=00
-_k03=00
+_k02=01
+_k03=01
_k10=00
_k11=00
_k12=00
_k33=01
_byten00=00011100
_byten01=00000000
-_byten02=00000000
-_byten03=00000000
+_byten02=00011100
+_byten03=00011100
_byten10=00000000
_byten11=00000000
_byten12=00000000
_sci_ports=ENABLED
_sci_int_port=ENABLED
_refck2core=DISABLED
-Regen=auto
+Regen=module
PAR1=0
PARTrace1=0
PAR3=0
# end user to adjust the PCSD quad to the final design requirements.
DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL "G8B10B"
-CH0_MODE "RXTX"
+CH3_PROTOCOL "G8B10B"
+CH0_MODE "DISABLED"
CH1_MODE "DISABLED"
CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH0_CDR_SRC "REFCLK_CORE"
+CH3_MODE "RXTX"
+CH3_CDR_SRC "REFCLK_CORE"
PLL_SRC "REFCLK_CORE"
TX_DATARATE_RANGE "MEDHIGH"
-CH0_RX_DATARATE_RANGE "MEDHIGH"
+CH3_RX_DATARATE_RANGE "MEDHIGH"
REFCK_MULT "10X"
#REFCLK_RATE 200.0
-CH0_RX_DATA_RATE "FULL"
-CH0_TX_DATA_RATE "FULL"
-CH0_TX_DATA_WIDTH "8"
-CH0_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "ENABLED"
-CH0_RX_FIFO "DISABLED"
-CH0_TDRV "0"
-#CH0_TX_FICLK_RATE 200.0
-#CH0_RXREFCLK_RATE "200.0"
-#CH0_RX_FICLK_RATE 200.0
-CH0_TX_PRE "DISABLED"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLED"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "AC"
-CH0_LOS_THRESHOLD_LO "2"
+CH3_RX_DATA_RATE "FULL"
+CH3_TX_DATA_RATE "FULL"
+CH3_TX_DATA_WIDTH "8"
+CH3_RX_DATA_WIDTH "8"
+CH3_TX_FIFO "ENABLED"
+CH3_RX_FIFO "DISABLED"
+CH3_TDRV "0"
+#CH3_TX_FICLK_RATE 200.0
+#CH3_RXREFCLK_RATE "200"
+#CH3_RX_FICLK_RATE 200
+CH3_TX_PRE "DISABLED"
+CH3_RTERM_TX "50"
+CH3_RX_EQ "DISABLED"
+CH3_RTERM_RX "50"
+CH3_RX_DCC "DC"
+CH3_LOS_THRESHOLD_LO "2"
PLL_TERM "50"
PLL_DCC "AC"
PLL_LOL_SET "0"
-CH0_TX_SB "DISABLED"
-CH0_RX_SB "DISABLED"
-CH0_TX_8B10B "ENABLED"
-CH0_RX_8B10B "ENABLED"
-CH0_COMMA_A "1100000101"
-CH0_COMMA_B "0011111010"
-CH0_COMMA_M "1111111100"
-CH0_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH0_CTC "DISABLED"
-CH0_CC_MATCH4 "0100011100"
-CH0_CC_MATCH_MODE "1"
-CH0_CC_MIN_IPG "3"
+CH3_TX_SB "DISABLED"
+CH3_RX_SB "DISABLED"
+CH3_TX_8B10B "ENABLED"
+CH3_RX_8B10B "ENABLED"
+CH3_COMMA_A "1100000101"
+CH3_COMMA_B "0011111010"
+CH3_COMMA_M "1111111100"
+CH3_RXWA "ENABLED"
+CH3_ILSM "ENABLED"
+CH3_CTC "DISABLED"
+CH3_CC_MATCH4 "0100011100"
+CH3_CC_MATCH_MODE "1"
+CH3_CC_MIN_IPG "3"
CCHMARK "9"
CCLMARK "7"
-CH0_SSLB "DISABLED"
-CH0_SPLBPORTS "DISABLED"
-CH0_PCSLBPORTS "DISABLED"
+CH3_SSLB "DISABLED"
+CH3_SPLBPORTS "DISABLED"
+CH3_PCSLBPORTS "DISABLED"
INT_ALL "ENABLED"
QD_REFCK2CORE "DISABLED"
-- CH0_CDR_SRC : String := "REFCLK_CORE";
-- CH1_CDR_SRC : String := "REFCLK_EXT";
-- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
-- PLL_SRC : String := "REFCLK_CORE"
);
port (
port (
------------------
-- CH0 --
- hdinp_ch0, hdinn_ch0 : in std_logic;
- hdoutp_ch0, hdoutn_ch0 : out std_logic;
- sci_sel_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- txdata_ch0 : in std_logic_vector (7 downto 0);
- tx_k_ch0 : in std_logic;
- tx_force_disp_ch0 : in std_logic;
- tx_disp_sel_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- rx_serdes_rst_ch0_c : in std_logic;
- sb_felb_ch0_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- tx_pcs_rst_ch0_c : in std_logic;
- tx_pwrup_ch0_c : in std_logic;
- rx_pcs_rst_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
- tx_div2_mode_ch0_c : in std_logic;
- rx_div2_mode_ch0_c : in std_logic;
-- CH1 --
-- CH2 --
-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (7 downto 0);
+ tx_k_ch3 : in std_logic;
+ tx_force_disp_ch3 : in std_logic;
+ tx_disp_sel_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ rx_serdes_rst_ch3_c : in std_logic;
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pcs_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pcs_rst_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
---- Miscillaneous ports
sci_wrdata : in std_logic_vector (7 downto 0);
sci_addr : in std_logic_vector (5 downto 0);
attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
attribute PLL_SRC: string;
attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH0_CDR_SRC: string;
- attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH3_CDR_SRC: string;
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200.000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
signal fpsc_vhi : std_logic := '1';
signal cin : std_logic_vector (11 downto 0) := "000000000000";
signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch0_sig : std_logic;
+signal tx_full_clk_ch3_sig : std_logic;
signal refclk2fpga_sig : std_logic;
signal tx_pll_lol_qd_sig : std_logic;
vlo_inst : VLO port map(Z => fpsc_vlo);
vhi_inst : VHI port map(Z => fpsc_vhi);
- rx_los_low_ch0_s <= rx_los_low_ch0_sig;
- rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+ rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+ rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
+ tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-- pcs_quad instance
PCSD_INST : PCSD
--synopsys translate_off
generic map (CONFIG_FILE => USER_CONFIG_FILE,
QUAD_MODE => "SINGLE",
- CH0_CDR_SRC => "REFCLK_CORE",
+ CH3_CDR_SRC => "REFCLK_CORE",
PLL_SRC => "REFCLK_CORE"
)
--synopsys translate_on
REFCLKN => fpsc_vlo,
----- CH0 -----
- HDOUTP0 => hdoutp_ch0,
- HDOUTN0 => hdoutn_ch0,
- HDINP0 => hdinp_ch0,
- HDINN0 => hdinn_ch0,
+ HDOUTP0 => open,
+ HDOUTN0 => open,
+ HDINP0 => fpsc_vlo,
+ HDINN0 => fpsc_vlo,
PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
PCIE_RXPOLARITY_0 => fpsc_vlo,
PCIE_POWERDOWN_0_1 => fpsc_vlo,
PCIE_RXVALID_0 => open,
PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => sci_sel_ch0,
- SCIENCH0 => fpsc_vhi,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
FF_RXI_CLK_0 => fpsc_vlo,
- FF_TXI_CLK_0 => txiclk_ch0,
+ FF_TXI_CLK_0 => fpsc_vlo,
FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => rx_full_clk_ch0,
- FF_RX_H_CLK_0 => rx_half_clk_ch0,
- FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
- FF_TX_H_CLK_0 => tx_half_clk_ch0,
- FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
- FF_TX_D_0_0 => txdata_ch0(0),
- FF_TX_D_0_1 => txdata_ch0(1),
- FF_TX_D_0_2 => txdata_ch0(2),
- FF_TX_D_0_3 => txdata_ch0(3),
- FF_TX_D_0_4 => txdata_ch0(4),
- FF_TX_D_0_5 => txdata_ch0(5),
- FF_TX_D_0_6 => txdata_ch0(6),
- FF_TX_D_0_7 => txdata_ch0(7),
- FF_TX_D_0_8 => tx_k_ch0,
- FF_TX_D_0_9 => tx_force_disp_ch0,
- FF_TX_D_0_10 => tx_disp_sel_ch0,
+ FF_RX_F_CLK_0 => open,
+ FF_RX_H_CLK_0 => open,
+ FF_TX_F_CLK_0 => open,
+ FF_TX_H_CLK_0 => open,
+ FFC_CK_CORE_RX_0 => fpsc_vlo,
+ FF_TX_D_0_0 => fpsc_vlo,
+ FF_TX_D_0_1 => fpsc_vlo,
+ FF_TX_D_0_2 => fpsc_vlo,
+ FF_TX_D_0_3 => fpsc_vlo,
+ FF_TX_D_0_4 => fpsc_vlo,
+ FF_TX_D_0_5 => fpsc_vlo,
+ FF_TX_D_0_6 => fpsc_vlo,
+ FF_TX_D_0_7 => fpsc_vlo,
+ FF_TX_D_0_8 => fpsc_vlo,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => fpsc_vlo,
FF_TX_D_0_11 => fpsc_vlo,
FF_TX_D_0_12 => fpsc_vlo,
FF_TX_D_0_13 => fpsc_vlo,
FF_TX_D_0_21 => fpsc_vlo,
FF_TX_D_0_22 => fpsc_vlo,
FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => rxdata_ch0(0),
- FF_RX_D_0_1 => rxdata_ch0(1),
- FF_RX_D_0_2 => rxdata_ch0(2),
- FF_RX_D_0_3 => rxdata_ch0(3),
- FF_RX_D_0_4 => rxdata_ch0(4),
- FF_RX_D_0_5 => rxdata_ch0(5),
- FF_RX_D_0_6 => rxdata_ch0(6),
- FF_RX_D_0_7 => rxdata_ch0(7),
- FF_RX_D_0_8 => rx_k_ch0,
- FF_RX_D_0_9 => rx_disp_err_ch0,
- FF_RX_D_0_10 => rx_cv_err_ch0,
+ FF_RX_D_0_0 => open,
+ FF_RX_D_0_1 => open,
+ FF_RX_D_0_2 => open,
+ FF_RX_D_0_3 => open,
+ FF_RX_D_0_4 => open,
+ FF_RX_D_0_5 => open,
+ FF_RX_D_0_6 => open,
+ FF_RX_D_0_7 => open,
+ FF_RX_D_0_8 => open,
+ FF_RX_D_0_9 => open,
+ FF_RX_D_0_10 => open,
FF_RX_D_0_11 => open,
FF_RX_D_0_12 => open,
FF_RX_D_0_13 => open,
FF_RX_D_0_22 => open,
FF_RX_D_0_23 => open,
- FFC_RRST_0 => rx_serdes_rst_ch0_c,
+ FFC_RRST_0 => fpsc_vlo,
FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
- FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
FFC_SB_INV_RX_0 => fpsc_vlo,
FFC_PCIE_CT_0 => fpsc_vlo,
FFC_PCI_DET_EN_0 => fpsc_vlo,
FFC_FB_LOOPBACK_0 => fpsc_vlo,
FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
- FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
- FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
- FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
- FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
+ FFC_LANE_TX_RST_0 => fpsc_vlo,
+ FFC_TXPWDNB_0 => fpsc_vlo,
+ FFC_LANE_RX_RST_0 => fpsc_vlo,
+ FFC_RXPWDNB_0 => fpsc_vlo,
+ FFS_RLOS_LO_0 => open,
FFS_RLOS_HI_0 => open,
FFS_PCIE_CON_0 => open,
FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
+ FFS_LS_SYNC_STATUS_0 => open,
FFS_CC_OVERRUN_0 => open,
FFS_CC_UNDERRUN_0 => open,
FFS_SKP_ADDED_0 => open,
FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
+ FFS_RLOL_0 => open,
FFS_RXFBFIFO_ERROR_0 => open,
FFS_TXFBFIFO_ERROR_0 => open,
LDR_CORE2TX_0 => fpsc_vlo,
LDR_RX2CORE_0 => open,
FFS_CDR_TRAIN_DONE_0 => open,
FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
+ FFC_RATE_MODE_TX_0 => fpsc_vlo,
FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
+ FFC_RATE_MODE_RX_0 => fpsc_vlo,
----- CH1 -----
HDOUTP1 => open,
FFC_RATE_MODE_RX_2 => fpsc_vlo,
----- CH3 -----
- HDOUTP3 => open,
- HDOUTN3 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
+ HDOUTP3 => hdoutp_ch3,
+ HDOUTN3 => hdoutn_ch3,
+ HDINP3 => hdinp_ch3,
+ HDINN3 => hdinn_ch3,
PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
PCIE_RXPOLARITY_3 => fpsc_vlo,
PCIE_POWERDOWN_3_1 => fpsc_vlo,
PCIE_RXVALID_3 => open,
PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
+ SCISELCH3 => sci_sel_ch3,
+ SCIENCH3 => fpsc_vhi,
FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => txiclk_ch3,
FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_TX_F_CLK_3 => open,
- FF_TX_H_CLK_3 => open,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
+ FF_RX_F_CLK_3 => rx_full_clk_ch3,
+ FF_RX_H_CLK_3 => rx_half_clk_ch3,
+ FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
+ FF_TX_H_CLK_3 => tx_half_clk_ch3,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+ FF_TX_D_3_0 => txdata_ch3(0),
+ FF_TX_D_3_1 => txdata_ch3(1),
+ FF_TX_D_3_2 => txdata_ch3(2),
+ FF_TX_D_3_3 => txdata_ch3(3),
+ FF_TX_D_3_4 => txdata_ch3(4),
+ FF_TX_D_3_5 => txdata_ch3(5),
+ FF_TX_D_3_6 => txdata_ch3(6),
+ FF_TX_D_3_7 => txdata_ch3(7),
+ FF_TX_D_3_8 => tx_k_ch3,
+ FF_TX_D_3_9 => tx_force_disp_ch3,
+ FF_TX_D_3_10 => tx_disp_sel_ch3,
FF_TX_D_3_11 => fpsc_vlo,
FF_TX_D_3_12 => fpsc_vlo,
FF_TX_D_3_13 => fpsc_vlo,
FF_TX_D_3_21 => fpsc_vlo,
FF_TX_D_3_22 => fpsc_vlo,
FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
+ FF_RX_D_3_0 => rxdata_ch3(0),
+ FF_RX_D_3_1 => rxdata_ch3(1),
+ FF_RX_D_3_2 => rxdata_ch3(2),
+ FF_RX_D_3_3 => rxdata_ch3(3),
+ FF_RX_D_3_4 => rxdata_ch3(4),
+ FF_RX_D_3_5 => rxdata_ch3(5),
+ FF_RX_D_3_6 => rxdata_ch3(6),
+ FF_RX_D_3_7 => rxdata_ch3(7),
+ FF_RX_D_3_8 => rx_k_ch3,
+ FF_RX_D_3_9 => rx_disp_err_ch3,
+ FF_RX_D_3_10 => rx_cv_err_ch3,
FF_RX_D_3_11 => open,
FF_RX_D_3_12 => open,
FF_RX_D_3_13 => open,
FF_RX_D_3_22 => open,
FF_RX_D_3_23 => open,
- FFC_RRST_3 => fpsc_vlo,
+ FFC_RRST_3 => rx_serdes_rst_ch3_c,
FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
+ FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
FFC_SB_INV_RX_3 => fpsc_vlo,
FFC_PCIE_CT_3 => fpsc_vlo,
FFC_PCI_DET_EN_3 => fpsc_vlo,
FFC_FB_LOOPBACK_3 => fpsc_vlo,
FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
+ FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
+ FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
+ FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+ FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+ FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
FFS_RLOS_HI_3 => open,
FFS_PCIE_CON_3 => open,
FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
+ FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
FFS_CC_OVERRUN_3 => open,
FFS_CC_UNDERRUN_3 => open,
FFS_SKP_ADDED_3 => open,
FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => open,
+ FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
FFS_RXFBFIFO_ERROR_3 => open,
FFS_TXFBFIFO_ERROR_3 => open,
LDR_CORE2TX_3 => fpsc_vlo,
LDR_RX2CORE_3 => open,
FFS_CDR_TRAIN_DONE_3 => open,
FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
----- Auxilliary ----
SCIWDATA7 => sci_wrdata(7),
architecture Behavioral of soda_cmd_window_generator is
- constant cWINDOW_delay : std_logic_vector(7 downto 0) := conv_std_logic_vector(28, 8); -- in clock-cycles
- constant cCLOCKS_PER_WINDOW : std_logic_vector(15 downto 0) := conv_std_logic_vector((COMMAND_WINDOS_SIZE / CLOCK_PERIOD) - 1, 16); -- in clock-cycles
signal window_delay_counter_S : std_logic_vector(7 downto 0) := (others => '0'); --
signal window_size_counter_S : std_logic_vector(15 downto 0) := (others => '0'); --
library ieee;
use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;\r
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
library work;
-use work.trb_net_std.all;\r
+use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; \r
+use work.trb_net16_hub_func.all;
package soda_components is
attribute syn_useioff : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
-\r
+
constant c_PHASE_L : std_logic := '0'; -- byt2word allignment of soda
constant c_PHASE_H : std_logic := '1'; -- byt2word allignment of soda
- constant c_HUB_CHILDREN : natural range 1 to 4 := 2; -- number of children per soda-hub\r
+ constant c_HUB_CHILDREN : natural range 1 to 4 := 2; -- number of children per soda-hub
constant cSODA_CLOCK_PERIOD : natural range 1 to 20 := 5; -- soda clock-period in ns
- constant cBURST_PERIOD : natural := 2400; -- particle-beam burst-period in ns\r
+ constant cBURST_PERIOD : natural := 2400; -- particle-beam burst-period in ns
constant cSODA_COMMAND_WINDOS_SIZE : natural range 1 to 65535 := 5000; -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns
+ constant cWINDOW_delay : std_logic_vector(7 downto 0) := conv_std_logic_vector(28, 8); -- in clock-cycles
+ constant cCLOCKS_PER_WINDOW : std_logic_vector(15 downto 0) := conv_std_logic_vector((cSODA_COMMAND_WINDOS_SIZE / cSODA_CLOCK_PERIOD) - 1, 16); -- in clock-cycles
+
- type t_HUB_DLM is array(c_HUB_CHILDREN-1 downto 0) of std_logic;\r
+ type t_HUB_DLM is array(c_HUB_CHILDREN-1 downto 0) of std_logic;
type t_HUB_DLM_BYTE is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0);
type t_HUB_DLM_WORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0);
type t_HUB_DLM_LWORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0);
type t_PACKET_TYPE_SENT is (c_NO_PACKET, c_CMD_PACKET, c_BST_PACKET);
type t_PACKET_TYPE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of t_PACKET_TYPE_SENT;
- type t_HUB_BIT_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic;\r
+ type t_HUB_BIT_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic;
type t_HUB_BYTE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0);
type t_HUB_WORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0);
type t_HUB_LWORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0);
-\r
+
+ type t_QUAD_BIT is array(3 downto 0) of std_logic;
+ type t_QUAD_NIBL is array(3 downto 0) of std_logic_vector(3 downto 0);
+ type t_QUAD_BYTE is array(3 downto 0) of std_logic_vector(7 downto 0);
+ type t_QUAD_9WORD is array(3 downto 0) of std_logic_vector(8 downto 0);
+ type t_QUAD_WORD is array(3 downto 0) of std_logic_vector(15 downto 0);
+ type t_QUAD_LWORD is array(3 downto 0) of std_logic_vector(31 downto 0);
component soda_superburst_generator
generic(
--Internal Connection
SODA_BURST_PULSE_IN : in std_logic := '0'; --
START_OF_SUPERBURST_OUT : out std_logic := '0';
- SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0')
+ SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CMD_WINDOW_OUT : out std_logic := '0'
);
end component;
--Internal Connection
START_OF_SUPERBURST_OUT : out std_logic := '0';
SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ START_OF_CALIBRATION_OUT : out std_logic := '0';
SODA_CMD_VALID_OUT : out std_logic := '0';
SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0');
--- EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
--- CRC_VALID_OUT : out std_logic := '0';\r
--- CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
RX_DLM_IN : in std_logic;
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0')
);
end component;
-\r
+
component soda_d8crc8 -- crc-calculator/checker
port(
CLOCK : in std_logic;
- RESET : in std_logic;
+ RESET : in std_logic;
SOC_IN : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_VALID_IN : in std_logic;
CRC_OUT : out std_logic_vector(7 downto 0);
CRC_VALID_OUT : out std_logic
);
- end component;\r
- \r
+ end component;
+
component soda_source -- box containing soda_source components
port(
SYSCLK : in std_logic; -- fabric clock
SODA_ACK_OUT : out std_logic := '0';
LEDS_OUT : out std_logic_vector(3 downto 0)
);
- end component;\r
-\r
+ end component;
+
component soda_hub
port(
SYSCLK : in std_logic; -- fabric clock
LEDS_OUT : out std_logic_vector(3 downto 0);
LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
);
- end component;\r
+ end component;
- component soda_reply_pkt_builder\r
- port(\r
- SODACLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
+ component soda_reply_pkt_builder
+ port(
+ SODACLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
LINK_PHASE_IN : in std_logic := '0'; --_vector(1 downto 0) := (others => '0');
- START_OF_SUPERBURST : in std_logic := '0';\r
- SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');\r
- SODA_CMD_STROBE_IN : in std_logic := '0'; -- \r
- SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit\r
+ START_OF_SUPERBURST : in std_logic := '0';
+ SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CMD_STROBE_IN : in std_logic := '0'; --
+ SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit
TX_DLM_PREVIEW_OUT : out std_logic := '0';
TX_DLM_OUT : out std_logic := '0'; --
- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')\r
- );\r
- end component;\r
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')
+ );
+ end component;
component soda_reply_handler
port(
);
end component;
- component soda_calibration_timer\r
- port(\r
- SODACLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic; \r
- --Internal Connection\r
- START_CALIBRATION : in std_logic := '0';\r
- END_CALIBRATION : in std_logic := '0';\r
+ component soda_calibration_timer
+ port(
+ SODACLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
+ START_CALIBRATION : in std_logic := '0';
+ END_CALIBRATION : in std_logic := '0';
CALIB_VALID_OUT : out std_logic := '0'; --
- CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0')\r
- );\r
- end component;\r
-\r
+ CALIB_TIME_OUT : out std_logic_vector(15 downto 0) := (others => '0')
+ );
+ end component;
+
component spi_flash_and_fpga_reload
port(
CLK_IN : in std_logic;
RX_DLM : out std_logic := '0';
RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";\r
- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!\r
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
+ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!
LINK_PHASE_OUT : out std_logic := '0'; --PL!
--SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ SD_RXD_P_IN : in t_QUAD_BIT;
+ SD_RXD_N_IN : in t_QUAD_BIT;
+ SD_TXD_P_OUT : out t_QUAD_BIT;
+ SD_TXD_N_OUT : out t_QUAD_BIT;
+ SD_REFCLK_P_IN : in t_QUAD_BIT; --not used
+ SD_REFCLK_N_IN : in t_QUAD_BIT; --not used
+ SD_PRSNT_N_IN : in t_QUAD_BIT; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in t_QUAD_BIT; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out t_QUAD_BIT := (others => '0'); -- SFP disable
--Control Interface
SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
end component;
-\r
+
component soda_tx_control
port(
CLK_200 : in std_logic;
DEBUG_OUT : out std_logic_vector(31 downto 0);
STAT_REG_OUT : out std_logic_vector(31 downto 0)
);
-end component;\r
-\r
+end component;
+
component soda_cmd_window_generator
generic( CLOCK_PERIOD : natural range 1 to 20 := cSODA_CLOCK_PERIOD; -- clock-period in ns
COMMAND_WINDOS_SIZE : natural range 1 to 65335 := cSODA_COMMAND_WINDOS_SIZE -- command window size in ns
SODA_CMD_WINDOW_OUT : out std_logic := '0'
);
end component;
-\r
-end package;
+
+end package;
\ No newline at end of file
type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
signal CURRENT_STATE, NEXT_STATE: STATES;
- signal last_packet_sent_S : t_PACKET_TYPE_SENT;
- signal expected_reply_S : std_logic_vector(7 downto 0);
- signal reply_valid_S : t_HUB_BIT_ARRAY;
- signal reply_OK_S : t_HUB_BIT_ARRAY;
- signal start_calibration_S : std_logic;
- signal calibration_valid_S : t_HUB_BIT_ARRAY;
- signal calibration_time_S : t_HUB_WORD_ARRAY;
- signal calib_register_s : t_HUB_LWORD_ARRAY;
+ signal last_packet_sent_S : t_PACKET_TYPE_SENT;
+ signal expected_reply_S : std_logic_vector(7 downto 0);
+ signal reply_valid_S : t_HUB_BIT_ARRAY;
+ signal reply_OK_S : t_HUB_BIT_ARRAY;
+ signal start_of_calibration_S : std_logic := '0';
+ signal start_calibration_S : t_HUB_BIT_ARRAY;
+ signal calibration_valid_S : t_HUB_BIT_ARRAY;
+ signal calibration_time_S : t_HUB_WORD_ARRAY;
+ signal calib_register_s : t_HUB_LWORD_ARRAY;
\r
- signal dead_channels_S : t_HUB_BIT_ARRAY;
- signal channel_status_S : t_HUB_BIT_ARRAY;\r
- signal status_register : std_logic_vector(31 downto 0) := (others => '0');
+ signal dead_channels_S : t_HUB_BIT_ARRAY;
+ signal channel_status_S : t_HUB_BIT_ARRAY;\r
+ signal status_register : std_logic_vector(31 downto 0) := (others => '0');
\r
-- slave bus signals
signal bus_ack_x : std_logic;
CLK_EN => '1',
--Internal Connection
START_OF_SUPERBURST_OUT => start_of_superburst_S,
+ START_OF_CALIBRATION_OUT => start_of_calibration_S,
SUPER_BURST_NR_OUT => super_burst_nr_S,
SODA_CMD_VALID_OUT => soda_cmd_valid_S,
SODA_CMD_WORD_OUT => soda_cmd_word_S,
RX_DLM_IN => RXUP_DLM_IN,
RX_DLM_WORD_IN => RXUP_DLM_WORD_IN
);
-
+\r
hub_reply_packet_builder : soda_reply_pkt_builder \r
port map(
SODACLK => SODACLK,
\r
channel :for i in c_HUB_CHILDREN-1 downto 0 generate
+ start_calibration_S(i) <= start_of_calibration_S;\r
+\r
packet_builder : soda_packet_builder
port map(
SODACLK => SODACLK,
SUPER_BURST_NR_IN => super_burst_nr_S,
SODA_CMD_WORD_IN => soda_cmd_word_S,
EXPECTED_REPLY_OUT => open,
- TIME_CAL_OUT => start_calibration_S,
+ TIME_CAL_OUT => open, --start_calibration_S(i),
TX_DLM_OUT => TXDN_DLM_OUT(i),
TX_DLM_WORD_OUT => TXDN_DLM_WORD_OUT(i)
);
CLEAR => '0',
CLK_EN => '1',
--Internal Connection
- START_CALIBRATION => start_calibration_S,
+ START_CALIBRATION => start_calibration_S(i),
END_CALIBRATION => reply_valid_S(i),
CALIB_VALID_OUT => calibration_valid_S(i),
CALIB_TIME_OUT => calibration_time_S(i)
--Internal Connection
START_OF_SUPERBURST_OUT : out std_logic := '0';
SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ START_OF_CALIBRATION_OUT : out std_logic := '0';
SODA_CMD_VALID_OUT : out std_logic := '0';
SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0');
--- EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- CRC_VALID_OUT : out std_logic := '0';\r
- CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
RX_DLM_IN : in std_logic;
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0')
);
c_SODA_PKT5, c_SODA_PKT6, c_SODA_PKT7, c_SODA_PKT8
);
signal packet_state_S : packet_state_type := c_IDLE;
--- crc-checker signals --
--- signal soc_S : std_logic;\r
--- signal eoc_S : std_logic;\r
--- signal crc_valid_in_s : std_logic;\r
--- signal crc_datain_S : std_logic_vector(7 downto 0) := (others => '0');\r
--- signal crc_tmp_S : std_logic_vector(7 downto 0) := (others => '0');\r
--- signal crc_out_S : std_logic_vector(7 downto 0) := (others => '0');\r
--- signal crc_valid_out_S : std_logic;\r
--- signal crc_check_ok_s : std_logic;\r
begin
end if;
end process;
- soda_packet_collector_proc : process(SODACLK, packet_state_S)
+ soda_packet_interpreter_proc : process(SODACLK, packet_state_S)
begin
if rising_edge(SODACLK) then
case packet_state_S is
when c_RST =>
START_OF_SUPERBURST_OUT <= '0';
+ START_OF_CALIBRATION_OUT <= '0';
SODA_CMD_VALID_OUT <= '0';
soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
when c_IDLE =>
START_OF_SUPERBURST_OUT <= '0';
+ START_OF_CALIBRATION_OUT <= '0';
SODA_CMD_VALID_OUT <= '0';
soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
when c_SODA_PKT1 =>
START_OF_SUPERBURST_OUT <= '0';
+ START_OF_CALIBRATION_OUT <= '0';
SODA_CMD_VALID_OUT <= '0';
- soda_pkt_word_S(31 downto 24) <= RX_DLM_WORD_IN;
+ soda_pkt_word_S(31 downto 24) <= RX_DLM_WORD_IN;\r
when c_SODA_PKT2 =>
-- do nothing -- disregard K28.7
when c_SODA_PKT3 =>
SUPER_BURST_NR_OUT <= soda_pkt_word_S(30 downto 0);
else
SODA_CMD_VALID_OUT <= '1';
- SODA_CMD_WORD_OUT <= soda_pkt_word_S(30 downto 0);
+ SODA_CMD_WORD_OUT <= soda_pkt_word_S(30 downto 0);\r
+ if soda_pkt_word_S(30)='1' then\r
+ START_OF_CALIBRATION_OUT <= '1';\r
+ end if;
end if;
when others =>
- START_OF_SUPERBURST_OUT <= '0';
+ START_OF_SUPERBURST_OUT <= '0';
+ START_OF_CALIBRATION_OUT <= '0';
soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
SODA_CMD_VALID_OUT <= '0';
end if;
end process;
- --crc_check_proc : process(SODACLK, packet_state_S)
- --begin
- --if rising_edge(SODACLK) then
- --case packet_state_S is
- --when c_RST=>
- --CRC_VALID_OUT <= '0';
- --CRC_DATA_OUT<= (others => '0');
- --soc_S <= '1';
- --eoc_S <= '0';
- --CRC_VALID_OUT <= '0';
- --when c_IDLE =>
- --CRC_VALID_OUT <= '0';
- --CRC_DATA_OUT<= (others => '0');
- --crc_valid_in_S<= '0';
- --crc_datain_S<= (others=>'0');
- --soc_S <= '1';
- --eoc_S <= '0';
- --when c_SODA_PKT1=>
- --crc_valid_in_S<= '1';
- --crc_datain_S<=RX_DLM_WORD_IN;
- --if (RX_DLM_WORD_IN(7)='0') then -- only calculate crc if it's a command packet
- --soc_S <= '0';
- --end if;
- --when c_SODA_PKT2=>
- --crc_valid_in_S<= '0';
- --crc_datain_S<= (others=>'0');
- --when c_SODA_PKT3=>
- --crc_valid_in_S<= '1';
- --crc_datain_S<= RX_DLM_WORD_IN;
- --when c_SODA_PKT4=>
- --crc_valid_in_S<= '0';
- --crc_datain_S<= (others=>'0');
- --when c_SODA_PKT5=>
- --crc_valid_in_S<= '1';
- --crc_datain_S<= RX_DLM_WORD_IN;
- --if (soc_S='0') then -- only terminate crc calculation if it is running
- --eoc_S <= '1';
- --end if;
- --when c_SODA_PKT6=>
- --crc_valid_in_S<= '0';
- --crc_datain_S<= (others=>'0');
- --eoc_S <= '0';
- --when c_SODA_PKT7=>
- --crc_valid_in_S<= '0';
- --crc_datain_S<= (others=>'0');
- --if ((crc_valid_out_S = '1') and (crc_out_S = RX_DLM_WORD_IN)) then
- --crc_check_ok_S<= '1';
- --else
- --crc_check_ok_S<= '0';
- --end if;
- --CRC_VALID_OUT <= '1';
- --when c_SODA_PKT8=>
- --CRC_VALID_OUT <= crc_valid_out_S;
- --CRC_DATA_OUT<= crc_out_S;
- --crc_valid_in_S<= '0';
- --crc_datain_S<= (others=>'0');
- --eoc_S <= '0';
- --crc_check_ok_S<= '0';
- --CRC_VALID_OUT <= '0';
- --when others =>
- --CRC_VALID_OUT <= '0';
- --CRC_DATA_OUT<= (others => '0');
- --crc_valid_in_S<= '0';
- --crc_datain_S<= (others=>'0');
- --soc_S <= '0';
- --eoc_S <= '0';
- --CRC_VALID_OUT <= '0';
- --end case;
- --end if;
- --end process;
end architecture;
\ No newline at end of file
);
signal packet_state_S : packet_state_type := c_IDLE;\r
\r
-signal soda_dlm_preview_S : std_logic;
+ signal soda_dlm_preview_S : std_logic;
\r
begin\r
end if;
end process;
\r
---reply_fsm_proc : process(SODACLK)
--- begin
--- if rising_edge(SODACLK) then\r
--- if (RESET='1') then
--- packet_state_S <= c_IDLE;
--- else
--- case packet_state_S is\r
--- when c_IDLE =>\r
--- if (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1') then\r
--- packet_state_S <= c_PKT1;\r
--- end if;
--- when c_PKT1 =>
--- packet_state_S <= c_PKT2;\r
--- when c_PKT2 =>
--- packet_state_S <= c_IDLE;\r
--- when others =>
--- packet_state_S <= c_IDLE;
--- end case;
--- end if;\r
--- end if;
--- end process;
-
--- collect_reply_proc : process(SODACLK)
--- begin
--- if rising_edge(SODACLK) then\r
--- if (RESET='1') then
--- TX_DLM_OUT <= '0';\r
--- TX_DLM_WORD_OUT <= (others=>'0');
--- elsif (START_OF_SUPERBURST='1') then\r
--- TX_DLM_OUT <= '1';\r
--- TX_DLM_WORD_OUT <= SUPER_BURST_NR_IN(7 downto 0);\r
--- elsif (SODA_CMD_STROBE_IN='1') then\r
--- TX_DLM_OUT <= '1';\r
--- TX_DLM_WORD_OUT <= SODA_CMD_WORD_IN(7 downto 0);
--- elsif (packet_state_S=c_PKT1) then
--- TX_DLM_OUT <= '0';\r
--- elsif (packet_state_S=c_PKT2) then
--- TX_DLM_WORD_OUT <= (others=>'0');
--- end if;\r
--- end if;
--- end process;
\r
\r
end architecture;
\ No newline at end of file
signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
signal soda_cmd_strobe_S : std_logic := '0';
signal soda_cmd_strobe_sodaclk_S : std_logic := '0';
+ signal soda_cmd_pending_S : std_logic := '0';
+ signal soda_send_cmd_S : std_logic := '0';
signal start_of_superburst_S : std_logic := '0';
signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
+ signal soda_cmd_window_S : std_logic := '0';
-- Signals
type t_STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
--Internal Connection
SODA_BURST_PULSE_IN => SODA_BURST_PULSE_IN,
START_OF_SUPERBURST_OUT => start_of_superburst_S,
- SUPER_BURST_NR_OUT => super_burst_nr_S
+ SUPER_BURST_NR_OUT => super_burst_nr_S,\r
+ SODA_CMD_WINDOW_OUT => soda_cmd_window_S
);
packet_builder : soda_packet_builder
RESET => RESET,
--Internal Connection
LINK_PHASE_IN => LINK_PHASE_IN, --link_phase_S, PL!
- SODA_CMD_STROBE_IN => soda_cmd_strobe_sodaclk_S,
+ SODA_CMD_STROBE_IN => soda_send_cmd_S,
START_OF_SUPERBURST => start_of_superburst_S,
SUPER_BURST_NR_IN => super_burst_nr_S,
SODA_CMD_WORD_IN => soda_cmd_word_S,
SIGNAL_IN => soda_cmd_strobe_S,
PULSE_OUT => soda_cmd_strobe_sodaclk_S
);
-
+\r
+ SODA_CMD_FLOWCTRL : process(SODACLK)\r
+ begin\r
+ if( rising_edge(SODACLK) ) then
+ if( RESET = '1' ) then\r
+ soda_cmd_pending_S <= '0';\r
+ soda_send_cmd_S <= '0';\r
+ elsif soda_cmd_strobe_sodaclk_S = '1' then\r
+ soda_cmd_pending_S <= '1';\r
+ elsif soda_cmd_window_S = '1' and soda_cmd_pending_S = '1' then\r
+ soda_send_cmd_S <= '1';
+ soda_cmd_pending_S <= '0';\r
+ else
+ soda_cmd_pending_S <= '0';
+ soda_send_cmd_S <= '0';
+ end if;\r
+ end if;
+ end process SODA_CMD_FLOWCTRL;
---------------------------------------------------------
-- data handling --
---------------------------------------------------------
entity soda_superburst_generator is
generic(
- BURST_COUNT : natural range 1 to 256 := 16 -- number of bursts to be counted between super-bursts
+ BURST_COUNT : natural range 4 to 256 := 16 -- number of bursts to be counted between super-bursts
);
port(
SODACLK : in std_logic; -- fabric clock
--Internal Connection
SODA_BURST_PULSE_IN : in std_logic := '0'; --
START_OF_SUPERBURST_OUT : out std_logic := '0';
- SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0')
+ SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CMD_WINDOW_OUT : out std_logic := '0'
);
end soda_superburst_generator;
end if;
end if;
end process;
+\r
+ soda_cmd_window_proc : process(SODACLK)
+ begin
+ if rising_edge(SODACLK) then
+ if (RESET='1') then
+ SODA_CMD_WINDOW_OUT <= '0';
+ elsif (burst_counter_S = (cBURST_COUNT - 1)) then\r
+ SODA_CMD_WINDOW_OUT <= '1';
+ elsif (burst_counter_S = 2) then
+ SODA_CMD_WINDOW_OUT <= '0';
+ end if;
+ end if;
+ end process;\r
end Behavioral;
jspc29 / soda.git / commitdiff