library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+USE IEEE.std_logic_UNSIGNED.ALL;
library work;
use work.trb_net_std.all;
THE_CALIB_CHECK_MACHINE : process--(calib_current_state, CRI_CAL_ACTIVE, CRI_APL_DATAREADY_IN)
+ variable cts_data_length : unsigned(9 downto 0) := (others => '0');
+ variable cts_TDC_pos : std_logic_vector(15 downto 0) := (others => '0');
begin
wait until rising_edge(CLK);
when DIRICH_LENGTH =>
rec_state <= x"6";
+ cts_TDC_pos := (others => '0');
+ cts_data_length := (others => '0');
+
if (cri_apl_caldrdy_in = '1') then
data_h <= cri_apl_caldata_in;
pack_num_h <= cri_apl_calpacknum_in;
pack_num_full <= pack_num_h & cri_apl_calpacknum_in;
cal_eod_full <= cal_eod_h & cri_apl_caleod_in;
data_rdy <= '1';
+
+ if (INCLUDE_TDC = c_YES) then
+ if ( dirich_length_i = dirich_length_input_i) then -- CTS Data header
+
+ cts_data_length := unsigned(data_h(3 downto 0))*2 -- Input Counter
+ + unsigned(data_h(8 downto 4))*2; -- TriggerChnlCntr
+ if data_h( 9) = '1' then cts_data_length := cts_data_length + 2; end if; -- inclLastIdle
+ if data_h(10) = '1' then cts_data_length := cts_data_length + 3; end if; -- inclTrigInfo
+ if data_h(11) = '1' then cts_data_length := cts_data_length + 1; end if; -- inclTS
+
+ -- ETM word length: for CBM RICH it should be 01. If not, we have a bug
+ if (data_h(13 downto 12) = b"01") then cts_data_length := cts_data_length + 1;
+ elsif (data_h(13 downto 12) = b"10") then cts_data_length := cts_data_length + 4;
+ end if;
+
+ if (( cts_data_length) >= unsigned(dirich_length_input_i)) then -- error; no calibration as this will be found in upacker as well!
+ cts_TDC_pos := ( others => '0');
+ else
+ cts_TDC_pos := std_logic_vector(unsigned(dirich_length_input_i) - cts_data_length);
+ end if;
+ end if;
+
+ if (dirich_length_i < cts_TDC_pos) then
+ dtype <= x"4";
+ end if;
+ end if;
+
if (dirich_length_i = x"0001") then
--if (combiner_length_i = x"0001")
calib_next_state <= DIRICH_LENGTH;
else
- if ((INCLUDE_TDC = c_YES) and
- (
- (dirich_length_i = dirich_length_input_i) or
- (dirich_length_i = std_logic_vector(unsigned(combiner_length_i) - 1))
- )
- ) then
- dtype <= x"4";
- end if;
calib_next_state <= CTS_H;
dirich_length_i <= std_logic_vector(unsigned(dirich_length_i) - 1);
combiner_length_i <= std_logic_vector(unsigned(combiner_length_i) - 1);