Important information is added for the data limit register

diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex
index aa6f237bc995989a111f93ddf00f6285eed1900a..6b1d94f7a15284f5e4e1fb902cf440abd3744d70 100644 (file)
--- a/trb3/TdcSlowControl.tex
+++ b/trb3/TdcSlowControl.tex
@@ -27,12 +27,21 @@ the control registers are given in Table \ref{tab:tdcControlReg}.
       \hline
       0xc803                   & Channel enable 2                      & 31-0  & Enable signals for the channels 33-64.\\
       \hline
-      \multirow{3}{*}{0xc804}  & \multirow{3}{*}{Data transfer limit}  & 7-0   & Defines \# of data words per channel to be read-out. Set it to 0x80 for full readout.\\
+      \multirow{8}{*}{0xc804}  & \multirow{8}{*}{Data transfer limit}  & 7-0
+      & Defines \# of data words per channel to be read-out. Set it to 0x80
+      for full readout. \textbf{ATTENTION! This conrol is implemented only for
+      debug readons. With this limit the earliest hit information is read 
+out. If you wish to get hits close to the trigger (latest hits) please use 
+the trigger window feature.}\\
                                 &                                       & 31-8  & reserved.\\
       \hline
+%      \multirow{3}{*}{0xc805} & \multirow{3}{*}{TDC channel trigger}  & 6-0   & The input signal on the defined channel is forwarded to the CTS for triggering.\\
+%                                &                                       & 31-7
+%                                & reserved.\\
+%      \hline
     \end{tabularx}
   \caption{The control registers of the TDC. Note that these registers
-  have been moved from 0xc0\ldots0xc4 at the beginning of 2013.}
+  have been moved from 0xc0\ldots0xc8 at the beginning of 2013.}
   \label{tab:tdcControlReg}
   \end{center}
 \end{table}