remove old files from master

diff --git a/ctdc_enc.v b/ctdc_enc.v
deleted file mode 100644 (file)
index c94be35..0000000
--- a/ctdc_enc.v
+++ /dev/null
@@ -1,129 +0,0 @@
-module ctdc_enc_neg(
-                                                                       clk,
-                                                                       in,\r
-                                                                       in_valid,
-                                                                       out,
-                                                                       out_valid
-                                                                       ) /* synthesis syn_preserve= 1*/;
-
-input wire clk;
-input wire [7:0]in;\r
-input wire in_valid;
-output reg [2:0]out /*synthesis syn_preserve=1*/;
-output reg out_valid /*synthesis syn_preserve=1*/;
-
-
-       always @ (posedge clk)begin\r
-               if(in_valid)begin
-               case (in)       
-                               8'b11111110 : begin
-                        out <= 3'b000;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11111100 : begin
-                        out <= 3'b001;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11111000 : begin
-                        out <= 3'b010;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11110000 : begin
-                        out <= 3'b011;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11100000 : begin
-                        out <= 3'b100;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11000000 : begin
-                        out <= 3'b101;
-                        out_valid <= 1'b1;
-                        end
-                               8'b10000000 : begin
-                        out <= 3'b110;
-                        out_valid <= 1'b1;
-                        end
-                               8'b00000000 : begin
-                        out <= 3'b111;
-                        out_valid <= 1'b1;
-                        end
-                       default   :  begin
-                                               out <=3'b000;
-                                               out_valid <= 1'b0;
-                                               end
-                       endcase
-               end else begin
-                       out <=3'b000;
-                       out_valid <= 1'b0;
-               end
-       end
-
-
-endmodule\r
-\r
-module ctdc_enc_pos(
-                                                                       clk,
-                                                                       in,
-                                                                       in_valid,
-                                                                       out,
-                                                                       out_valid
-                                                                       ) /* synthesis syn_preserve= 1*/;
-
-input wire clk;
-input wire [7:0]in;
-input wire in_valid;
-output reg [2:0]out /*synthesis syn_preserve=1*/;
-output reg out_valid /*synthesis syn_preserve=1*/;
-
-
-       always @ (posedge clk)begin
-               if(in_valid)begin
-               case (in)       
-                               //8'b11111110 : begin\r
-                               ~8'b11111110 : begin
-                        out <= 3'b000;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11111100 : begin
-                        out <= 3'b001;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11111000 : begin
-                        out <= 3'b010;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11110000 : begin
-                        out <= 3'b011;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11100000 : begin
-                        out <= 3'b100;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11000000 : begin
-                        out <= 3'b101;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b10000000 : begin
-                        out <= 3'b110;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b00000000 : begin
-                        out <= 3'b111;
-                        out_valid <= 1'b1;
-                        end
-                       default   :  begin
-                                               out <=3'b000;
-                                               out_valid <= 1'b0;
-                                               end
-                       endcase
-               end else begin
-                       out <=3'b000;
-                       out_valid <= 1'b0;
-               end
-       end
-
-
-endmodule
-

diff --git a/release.v b/release.v
deleted file mode 100644 (file)
index 79c7cff..0000000
--- a/release.v
+++ /dev/null
@@ -1,262 +0,0 @@
-/*\r
-COMPONENT ctdc_channel_raw_out is PORT
-                                                                               (
-                                                                               reset_in:       IN STD_LOGIC;   --active high
-                                                                               pll_clks_in: IN STD_LOGIC_VECTOR(3 downto 0);   -- 0, 45, 90, 135 phase shifted\r
-                                                                               xfer_clk_in:    IN STD_LOGIC;
-                                                                               coarse_reset_in:        IN STD_LOGIC;   --active rising edge 
-                                                                               signal_in:      IN STD_LOGIC;                           --idle low
-                                                                               data_out:       OUT STD_LOGIC_VECTOR(23 downto 0);      --output on rising edge of pll_clks_in[0] 
-                                                                               data_valid_out: OUT STD_LOGIC   --active high; using rising edge of pll_clks_in[0] \r
-                                                                               xfer_data_out:  OUT STD_LOGIC_VECTOR(23 downto 0);      --output on rising edge of xfer_clk
-                                                                               xfer_data_valid_out:    OUT STD_LOGIC   --active high; using rising edge of xfer_clk
-                                                                               pos_ready:      OUT STD_LOGIC;                          --debug; leave open
-                                                                               neg_ready:      OUT STD_LOGIC;                          --debug; leave open
-                                                                               coarse: OUT STD_LOGIC_VECTOR(8 downto 0);       --debug; leave open
-                                                                               buf_pos:        OUT STD_LOGIC_VECTOR(8 downto 0);       --debug; leave open
-                                                                               buf_neg:        OUT STD_LOGIC_VECTOR(8 downto 0);       --debug; leave open
-                                                                               );
-END COMPONENT; \r
-\r
-\r
-\r
-\r
-*/\r
-\r
-module ctdc_channel_raw_out (
-                                                                               reset_in, 
-                                                                               pll_clks_in, \r
-                                                                               xfer_clk_in,
-                                                                               coarse_reset_in, 
-                                                                               signal_in,
-                                                                               data_out,
-                                                                               data_valid_out,\r
-                                                                               xfer_data_out,\r
-                                                                               xfer_data_valid_out,\r
-                                                                               pos_ready,\r
-                                                                               neg_ready,\r
-                                                                               coarse,\r
-                                                                               buf_pos,
-                                                                               buf_neg
-                                                                               );
-                                                       
-       parameter COARSE_WIDTH = 9;
-       parameter TDC_WIDTH = 3;
-
-       input wire reset_in;
-       input wire [3:0]pll_clks_in;\r
-       input wire xfer_clk_in;
-       input wire signal_in;
-       input wire coarse_reset_in;\r
-       output wire pos_ready;\r
-       output wire neg_ready;
-       \r
-       output reg [COARSE_WIDTH-1:0]coarse;\r
-\r
-       reg coarse_reset_dl;\r
-       assign coarse_reset_rising = ~coarse_reset_dl & coarse_reset_in;\r
-
-       wire [7:0]tdc_single;\r
-       wire tdc_single_valid;
-       output reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]data_out;
-       output reg data_valid_out;\r
-       output reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]xfer_data_out;
-       output reg xfer_data_valid_out;
-       wire [1:0]raw_valid_vect;
-       
-       wire signal_gate /* synthesis syn_preserve= 1*/;
-       assign signal_gate = ~signal_in;
-       wire signal_gate_neg /* synthesis syn_preserve= 1*/;\r
-       \r
-       wire [2:0]enc_neg_out;
-       wire [2:0]enc_pos_out;\r
-       \r
-       output wire [8:0]buf_pos;\r
-       output wire [8:0]buf_neg;\r
-       
-        
-       ctdc_inv ctdc_inv_inst1(
-                                                       .in(signal_gate),
-                                                       .out(signal_gate_neg)
-       ) /* synthesis syn_black_box */;\r
-\r
-ctdc4ddr_dev ctdc_dev(
-                                               .trig(signal_gate_neg), 
-                                               .clks(pll_clks_in),
-                                               //.out_multi(tdc_multi),
-                                               //.out_half(tdc_half),
-                                               .out_single(tdc_single),
-                                               .out_single_valid(tdc_single_valid)
-                                                               ) /* synthesis syn_preserve= 1*/;
- ctdc_enc_neg ctdc_enc_neg_inst(
-                                                                       .clk(pll_clks_in[0]),
-                                                                       .in(tdc_single),
-                                                                       .in_valid(tdc_single_valid),
-                                                                       .out(enc_neg_out),
-                                                                       .out_valid(enc_neg_out_valid)
-                                                                       ) /* synthesis syn_preserve= 1*/;
-                                                                       
-ctdc_enc_pos ctdc_enc_pos_inst(
-                                                                       .clk(pll_clks_in[0]),
-                                                                       .in(tdc_single),
-                                                                       .in_valid(tdc_single_valid),
-                                                                       .out(enc_pos_out),
-                                                                       .out_valid(enc_pos_out_valid)
-                                                                       ) /* synthesis syn_preserve= 1*/;\r
-\r
-\r
-
-
-               
-        
-        reg [COARSE_WIDTH+TDC_WIDTH-1:0]buf_positive;
-        reg [COARSE_WIDTH+TDC_WIDTH-1:0]buf_negative;
-        reg buf_positive_ready;
-        reg buf_negative_ready;
-        //assign raw_valid_vect = {buf_positive_ready, buf_negative_ready};\r
-        \r
-       assign pos_ready = buf_positive_ready;
-       assign neg_ready = buf_negative_ready;
-
-       assign buf_pos = buf_positive[11:3];
-       assign buf_neg = buf_negative[11:3];\r
-        \r
-       always @(posedge pll_clks_in[0])begin\r
-               coarse_reset_dl <= coarse_reset_in;\r
-       end\r
-        \r
-        always @(posedge pll_clks_in[0])begin
-               if(reset_in | coarse_reset_rising)begin
-                       coarse <= 'b0;
-               end else begin\r
-                       coarse <= coarse +1;\r
-               end\r
-       end
-       
-       always @(posedge pll_clks_in[0])begin
-               if(reset_in)begin
-                       data_out <= 'b0;
-                       data_valid_out <= 'b0;
-               end else begin
-                       if(enc_pos_out_valid)begin
-                               buf_positive <= {coarse, enc_pos_out};
-                               buf_positive_ready <= 'b1;\r
-                               //data_out <= {'b00110010, coarse, enc_pos_out}; //temporary
-                       end else begin
-                               //
-                       end
-                       if(enc_neg_out_valid && buf_positive_ready)begin
-                               buf_negative <= {coarse, enc_neg_out};
-                               buf_negative_ready <= 'b1;
-                       end else begin
-                               //
-                       end
-                       if(buf_positive_ready && (buf_positive[COARSE_WIDTH-1 + TDC_WIDTH -: COARSE_WIDTH]) == coarse +'b1)begin
-                               buf_positive_ready <= 'b0;
-                       end
-                       if(buf_negative_ready && (buf_negative[COARSE_WIDTH-1 + TDC_WIDTH -: COARSE_WIDTH]) == coarse +'b1)begin
-                               buf_negative_ready <= 'b0;
-                       end
-                       if(buf_negative_ready & buf_positive_ready)begin
-                               buf_negative_ready <= 'b0;
-                               buf_positive_ready <= 'b0;
-                               data_out <= {buf_negative, buf_positive};
-                               data_valid_out <= 'b1;
-                       end else begin
-                               data_valid_out <= 'b0;
-                       end
-               end
-       end\r
-       \r
-       reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]slow_buf;\r
-       reg [3:0] slow_valid_dl;\r
-       wire slow_valid;\r
-       assign slow_valid = |slow_valid_dl[3:2];\r
-       \r
-       always @(posedge xfer_clk_in)begin\r
-               if(slow_valid)begin\r
-                       xfer_data_out <= slow_buf;\r
-                       xfer_data_valid_out <= 1'b1;\r
-               end else begin\r
-                       xfer_data_valid_out <= 1'b0;\r
-               end\r
-       end\r
-       
-       always @(posedge pll_clks_in[0])begin\r
-               if(data_valid_out & !(|slow_valid_dl))begin\r
-                       slow_buf <= data_out;\r
-                       slow_valid_dl[0] <= 1'b1;\r
-               end else begin\r
-                       slow_valid_dl[0] <= 1'b0;\r
-               end\r
-       end\r
-\r
-       always @(posedge pll_clks_in[0])begin\r
-               slow_valid_dl[3:1] <= slow_valid_dl[2:0];\r
-       end\r
-
-endmodule\r
-\r
-\r
-\r
-module ctdc4ddr_dev(trig, clks, out_multi, out_half, out_single, out_single_valid) /* synthesis syn_useioff=0*/; 
-       input wire trig;
-       input wire[3:0]clks;
-       output wire [7:0]out_single /*synthesis syn_preserve= 1*/;\r
-       output wire [7:0]out_half /*synthesis syn_preserve= 1*/;\r
-       output wire [7:0]out_multi /*synthesis syn_preserve= 1*/;
-       output wire out_single_valid;\r
-       reg [7:0]multi /*synthesis syn_preserve=1 synthesis syn_useioff=0*/;
-       reg [7:0]half_half /*synthesis syn_preserve=1 synthesis syn_useioff=0*/;\r
-       reg [7:0]single /*synthesis syn_preserve=1 synthesis syn_useioff=0*/;
-       \r
-       wire single_half_change; \r
-       assign out_single_valid = single[0] ^ half_half[0];\r
-       
-       assign out_half = half_half;\r
-       assign out_multi = multi;\r
-       assign out_single = single;\r
-\r
-       ctdc_inv ctdc_inv_inst1(
-                                                       .in(trig),
-                                                       .out(trigger)
-       ) /* synthesis syn_black_box */;
-       generate
-               genvar i;
-               for(i=0;i<4;i=i+1)begin
-
-                       always @(posedge clks[i])begin
-                               multi[i] <= trigger /*synthesis syn_preserve= 1*/;
-                       end
-                       always @(negedge clks[i])begin
-                               multi[4+i] <= trigger /*synthesis syn_preserve= 1*/;
-                       end\r
-                       always @(posedge clks[0])begin\r
-                               half_half[i] <= multi[i];\r
-                       end\r
-                       always @(negedge clks[0])begin\r
-                               half_half[4+i] <= multi[4+i];
-                       end\r
-                       always @(posedge clks[0])begin\r
-                               single[i] <= half_half[i];\r
-                               single[4+i] <= half_half[4+i];\r
-                       end
-                       
-               end
-       endgenerate
-endmodule\r
-\r
-\r
-
-
-
-
-module ctdc_inv(in,out) /* synthesis syn_preserve=1 */;
-input wire in /* synthesis syn_keep=1 */;
-output wire out /* synthesis syn_keep=1 */;
-
-assign out = ~ in /* synthesis syn_keep=1 */;
-
-endmodule\r
-\r
-\r