use work.trb_net_std.all;
use work.trb_net_components.all;
use work.med_sync_define.all;
+use work.soda_components.all;
entity med_ecp3_sfp_sync_up is
- generic(
- SERDES_NUM : integer range 0 to 3 := 0;
--- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO
- IS_SYNC_SLAVE : integer := c_YES --select slave mode
- );
- port(
- CLK : in std_logic; -- _internal_ 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- --Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
- --Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
- CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
-
- --Sync operation
- RX_DLM : out std_logic := '0';
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
- TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
-
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
+ generic( SERDES_NUM : integer range 0 to 3 := 0;
+ -- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO
+ IS_SYNC_SLAVE : integer := c_YES); --select slave mode
+ port(
+ CLK : in std_logic; -- _internal_ 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ --Internal Connection TX
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic := '0';
+ --Internal Connection RX
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ MED_DATAREADY_OUT : out std_logic := '0';
+ MED_READ_IN : in std_logic;
+ CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
+ CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
+
+ --Sync operation
+ RX_DLM : out std_logic := '0';
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
+ TX_DLM : in std_logic := '0';
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
+ TX_DLM_INIT : in std_logic := '0'; --PL!
+ LINK_PHASE_OUT : out std_logic := '0'; --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
end entity;
attribute syn_sharing : string;
attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off";
+\r
component DCS
-- synthesis translate_off
end component;
-
signal clk_200_i : std_logic;
signal clk_200_internal : std_logic;
signal clk_rx_full : std_logic;
signal rx_error : std_logic;
signal rst_n : std_logic;
+signal rst : std_logic; -- PL!
signal rx_serdes_rst : std_logic;
signal tx_serdes_rst : std_logic;
signal tx_pcs_rst : std_logic;
signal rx_pcs_rst : std_logic;
signal rst_qd : std_logic;
signal serdes_rst_qd : std_logic;
+signal sd_los_i : std_logic; --PL!
signal rx_los_low : std_logic;
signal lsm_status : std_logic;
signal rx_allow : std_logic;
signal tx_allow_q : std_logic;
signal rx_allow_q : std_logic;
+signal link_phase_S : std_logic; --PL!
signal request_retr_i : std_logic;
signal start_retr_i : std_logic;
signal request_retr_position_i : std_logic_vector(7 downto 0);
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-rst_n <= not CLEAR;
+--rst_n <= not CLEAR; PL!
+rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
+rst <= (CLEAR or sd_los_i or internal_make_link_reset_out);
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
THE_RX_FSM : rx_reset_fsm
port map(
RST_N => rst_n,
- RX_REFCLK => clk_200_internal,
+ RX_REFCLK => clk_200_internal, -- allways running PL!
TX_PLL_LOL_QD_S => tx_pll_lol,
RX_SERDES_RST_CH_C => rx_serdes_rst,
RX_CDR_LOL_CH_S => rx_cdr_lol,
THE_TX_FSM : tx_reset_fsm
port map(
RST_N => rst_n,
- TX_REFCLK => clk_200_internal,
+ TX_REFCLK => clk_200_internal, -- allways running PL!
TX_PLL_LOL_QD_S => tx_pll_lol,
RST_QD_C => rst_qd,
TX_PCS_RST_CH_C => tx_pcs_rst,
-------------------------------------------------
-- TX Data
-------------------------------------------------
-THE_TX : tx_control
- port map(
- CLK_200 => clk_200_i,
- CLK_100 => SYSCLK,
- RESET_IN => CLEAR,
+THE_TX : soda_tx_control
+ port map(
+ CLK_200 => clk_200_i,
+ CLK_100 => SYSCLK,
+ RESET_IN => rst, --CLEAR, PL!
- TX_DATA_IN => MED_DATA_IN,
- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,
- TX_WRITE_IN => MED_DATAREADY_IN,
- TX_READ_OUT => MED_READ_OUT,
+ TX_DATA_IN => MED_DATA_IN,
+ TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,
+ TX_WRITE_IN => MED_DATAREADY_IN,
+ TX_READ_OUT => MED_READ_OUT,
- TX_DATA_OUT => tx_data,
- TX_K_OUT => tx_k,
+ TX_DATA_OUT => tx_data,
+ TX_K_OUT => tx_k,
- REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
- REQUEST_POSITION_IN => request_retr_position_i, --TODO
+ REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
+ REQUEST_POSITION_IN => request_retr_position_i, --TODO
- START_RETRANSMIT_IN => start_retr_i, --TODO
- START_POSITION_IN => request_retr_position_i, --TODO
+ START_RETRANSMIT_IN => start_retr_i, --TODO
+ START_POSITION_IN => request_retr_position_i, --TODO
- SEND_DLM => TX_DLM,
- SEND_DLM_WORD => TX_DLM_WORD,
-
- SEND_LINK_RESET_IN => CTRL_OP(15),
- TX_ALLOW_IN => tx_allow,
- RX_ALLOW_IN => rx_allow,
+ TX_DLM_INIT => TX_DLM_INIT,
+ SEND_DLM => TX_DLM,
+ SEND_DLM_WORD => TX_DLM_WORD,
+
+ SEND_LINK_RESET_IN => CTRL_OP(15),
+ TX_ALLOW_IN => tx_allow,
+ RX_ALLOW_IN => rx_allow,
+ LINK_PHASE_OUT => link_phase_S, --PL!
- DEBUG_OUT => debug_tx_control_i,
- STAT_REG_OUT => stat_tx_control_i
- );
+ DEBUG_OUT => debug_tx_control_i,
+ STAT_REG_OUT => stat_tx_control_i
+);
+LINK_PHASE_OUT <= link_phase_S; --PL!
-------------------------------------------------
-- RX Data
port map(
CLK_200 => clk_200_i,
CLK_100 => SYSCLK,
- RESET_IN => CLEAR,
+ RESET_IN => rst, --CLEAR, PL!
RX_DATA_OUT => MED_DATA_OUT,
RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,
STAT_DEBUG <= debug_reg;
internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
+sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!
STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
jspc29 / soda.git / commitdiff