Update dirich with LED for PLL lock

diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd
index f22becd627988e25e8b8e70371c5dfd72abf295b..642e7e53fca6a1a42e5948979e5d8fbda1181595 100644 (file)
--- a/code/clock_reset_handler.vhd
+++ b/code/clock_reset_handler.vhd
@@ -32,7 +32,7 @@ architecture clock_reset_handler_arch of clock_reset_handler is
 
 attribute syn_keep     : boolean;
 attribute syn_preserve : boolean;
-signal clock_100, clock_120, clock_200, clock_240: std_logic;
+signal clock_100, clock_120, clock_200, clock_240, clock_200_raw: std_logic;
 signal sys_clk_i : std_logic;
 signal timer   : unsigned(16 downto 0) := (others => '0');
 signal clear_n_i : std_logic := '0';
@@ -52,9 +52,9 @@ GSR_OUT     <= not pll_lock or clear_n_i;
 THE_PLL : entity work.pll_240_100 --PLL with 200 MHz input!
   port map(
     CLKI   => CLOCK_IN,
-    CLKOP  => clock_200,
+    CLKOP  => clock_200_raw,
     CLKOS  => clock_100,
-    CLKOS2 => open, --clock_240,
+    CLKOS2 => clock_200, --clock_240,
     CLKOS3 => clock_120,
     LOCK   => pll_lock
     );  
@@ -93,7 +93,7 @@ THE_RESET_HANDLER : trb_net_reset_handler
   port map(
     CLEAR_IN        => '0',             -- reset input (high active, async)
     CLEAR_N_IN      => clear_n_i,       -- reset input (low active, async)
-    CLK_IN          => clock_200,        -- raw master clock, NOT from PLL/DLL!
+    CLK_IN          => clock_200_raw,        -- raw master clock, NOT from PLL/DLL!
     SYSCLK_IN       => sys_clk_i,       -- PLL/DLL remastered clock
     PLL_LOCKED_IN   => pll_lock,        -- master PLL lock signal (async)
     RESET_IN        => '0',             -- general reset signal (SYSCLK)

diff --git a/dirich/config.vhd b/dirich/config.vhd
index bca93e22a66b8a68c6c3ebd068aee24214320935..110aef8a1b43aa10730b43d6efffb459e078792c 100644 (file)
--- a/dirich/config.vhd
+++ b/dirich/config.vhd
@@ -42,7 +42,7 @@ package config is
    
     constant INCLUDE_UART           : integer  := c_NO;  --300 slices
     constant INCLUDE_SPI            : integer  := c_YES; --300 slices
-    constant INCLUDE_LCD            : integer  := c_YES;  --800 slices
+    constant INCLUDE_LCD            : integer  := c_NO;  --800 slices
     constant INCLUDE_DEBUG_INTERFACE: integer  := c_YES; --300 slices
 
     --input monitor and trigger generation logic

diff --git a/dirich/config_compile_frankfurt.pl b/dirich/config_compile_frankfurt.pl
index 9f01cff1cd052aee8b7574a250db406d33d0bc45..6d1188d1030df8a6a0140e9491504a2280fcec8c 100644 (file)
--- a/dirich/config_compile_frankfurt.pl
+++ b/dirich/config_compile_frankfurt.pl
@@ -5,11 +5,11 @@ Speedgrade  => '8',
 
 
 TOPNAME                      => "dirich",
-lm_license_file_for_synplify => "1702\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@jspc29",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.7_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/K-2015.09/',
-synplify_command             => "/d/jspc29/lattice/diamond/3.7_x64/bin/lin64/synpwrap -fg -options",
+# synplify_command             => "/d/jspc29/lattice/diamond/3.7_x64/bin/lin64/synpwrap -fg -options",
 # synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 # synplify_command             => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
 nodelist_file                => 'nodelist_frankfurt.txt',

diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf
index 5cae218a22a8e5c5f9653b46184488bdb368f93c..b14dff76125880d009a5e30af4ca0e550e6a94dc 100644 (file)
--- a/dirich/dirich.lpf
+++ b/dirich/dirich.lpf
@@ -28,6 +28,6 @@ MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
 MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
 MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
 
-GSR_NET NET "GSR_N"; 
+# GSR_NET NET "GSR_N"; 
 
-LOCATE COMP          "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;
+# LOCATE COMP          "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;

diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd
index f8513f4ee171712b8ba8cb99561ae4752309d490..2be182b74f2aa475e2d66813425519c2bbe96dab 100644 (file)
--- a/dirich/dirich.vhd
+++ b/dirich/dirich.vhd
@@ -100,6 +100,9 @@ architecture dirich_arch of dirich is
   signal hit_in_i         : std_logic_vector(32 downto 1);
   signal logic_analyser_i : std_logic_vector(16 downto 1);
 
+  signal led_los_lock : std_logic;
+  signal los_count : unsigned(23 downto 0);
+  
   attribute syn_keep of GSR_N     : signal is true;
   attribute syn_preserve of GSR_N : signal is true;  
 
@@ -138,7 +141,19 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     DEBUG_OUT       => debug_clock_reset
     );
 
-
+process begin
+  wait until rising_edge(CLOCK_CAL);
+  if debug_clock_reset(0) = '0' then
+    led_los_lock <= '0';
+    los_count <= (others => '0');
+  elsif los_count(23) = '0' then
+    los_count <= los_count + 1;
+  else
+    led_los_lock <= '1';
+  end if;
+end process;  
+    
+    
 ---------------------------------------------------------------------------
 -- TrbNet Uplink
 ---------------------------------------------------------------------------
@@ -354,9 +369,9 @@ PWM <= pwm_i;
 -- LED
 ---------------------------------------------------------------------------
   LED_GREEN            <= not med2int(0).stat_op(9) or led_off;   
-  LED_ORANGE           <= '1' or led_off;
+  LED_ORANGE           <= debug_clock_reset(0) or led_off;
   LED_RED              <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
-  LED_YELLOW           <= '1' or led_off;
+  LED_YELLOW           <= led_los_lock or led_off;
 
 
 ---------------------------------------------------------------------------