*** empty log message ***

diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd
index 743e9942c8d8ed9d9f7d31b87e85054f3ba8bd65..0f6c4cfb60077144d71fa8c9ca247e12c4d16a1e 100644 (file)
--- a/trb_net16_med_tlk.vhd
+++ b/trb_net16_med_tlk.vhd
@@ -76,7 +76,10 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is
   signal fifo_wr_en_m : std_logic;
   signal fifo_empty_m : std_logic;
   signal fifo_full_m  : std_logic;
-
+  signal fifo_almost_empty_m, fifo_almost_empty_a : std_logic;
+  signal fifo_valid_read_m, fifo_valid_read_a : std_logic;
+  signal fifo_underflow_a, fifo_underflow_m : std_logic;
+  
   signal fifo_reset    : std_logic;
   signal fifo_status_a : std_logic_vector(3 downto 0);
   signal fifo_status_m : std_logic_vector(3 downto 0);
@@ -108,10 +111,7 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is
   signal buf_MED_ERROR_OUT, next_MED_ERROR_OUT : std_logic_vector(2 downto 0);
   signal state_bits : std_logic_vector(2 downto 0);
   signal counter_reset : std_logic;
-  signal fifo_almost_empty_m, fifo_almost_empty_a : std_logic;
-  signal fifo_valid_read_m, fifo_valid_read_a : std_logic;
-  signal fifo_underflow_a, fifo_underflow_m : std_logic;
-  
+
 begin
 
   TLK_ENABLE  <= not RESET;
@@ -204,6 +204,7 @@ begin
   STAT(57) <= fifo_underflow_a;
   STAT(58) <= fifo_underflow_m;
   STAT(59) <= TLK_CLK_neg;
+  STAT(60) <= fifo_wr_en_m;
   --STAT(63 downto 57) <= (others => '0');
   
 
@@ -314,7 +315,7 @@ U1_BUFG: BUFG  port map (I => CLK_FB_Out, O => FB_CLK);
       end if;
     end process;
 
-  fifo_rd_en_m <= tx_allow and not fifo_almost_empty_m; -- and not fifo_empty_m;
+  fifo_rd_en_m <= tx_allow;  -- and not fifo_empty_m; and not fifo_almost_empty_m;
 
   process(TLK_CLK_neg)
     begin