--- /dev/null
+set_property DIFF_TERM TRUE [get_ports AD11A_N]
+set_property IOSTANDARD LVDS [get_ports AD11A_N]
+set_property DIFF_TERM TRUE [get_ports AD11A_P]
+set_property IOSTANDARD LVDS [get_ports AD11A_P]
+set_property PACKAGE_PIN AB8 [get_ports AD11A_P]
+set_property DIFF_TERM TRUE [get_ports AD21A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD21A_N]
+set_property DIFF_TERM TRUE [get_ports AD21A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD21A_P]
+set_property PACKAGE_PIN AA21 [get_ports AD21A_P]
+set_property DIFF_TERM TRUE [get_ports AD31A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD31A_N]
+set_property DIFF_TERM TRUE [get_ports AD31A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD31A_P]
+set_property PACKAGE_PIN P16 [get_ports AD31A_P]
+set_property DIFF_TERM TRUE [get_ports AD41A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD41A_N]
+set_property DIFF_TERM TRUE [get_ports AD41A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD41A_P]
+set_property PACKAGE_PIN B18 [get_ports AD41A_P]
+set_property DIFF_TERM TRUE [get_ports AD11B_N]
+set_property IOSTANDARD LVDS [get_ports AD11B_N]
+set_property DIFF_TERM TRUE [get_ports AD11B_P]
+set_property IOSTANDARD LVDS [get_ports AD11B_P]
+set_property PACKAGE_PIN AA6 [get_ports AD11B_P]
+set_property DIFF_TERM TRUE [get_ports AD21B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD21B_N]
+set_property DIFF_TERM TRUE [get_ports AD21B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD21B_P]
+set_property PACKAGE_PIN W17 [get_ports AD21B_P]
+set_property DIFF_TERM TRUE [get_ports AD31B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD31B_N]
+set_property DIFF_TERM TRUE [get_ports AD31B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD31B_P]
+set_property PACKAGE_PIN P21 [get_ports AD31B_P]
+set_property DIFF_TERM TRUE [get_ports AD41B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD41B_N]
+set_property DIFF_TERM TRUE [get_ports AD41B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD41B_P]
+set_property PACKAGE_PIN C19 [get_ports AD41B_P]
+set_property DIFF_TERM TRUE [get_ports AD12A_N]
+set_property IOSTANDARD LVDS [get_ports AD12A_N]
+set_property DIFF_TERM TRUE [get_ports AD12A_P]
+set_property IOSTANDARD LVDS [get_ports AD12A_P]
+set_property PACKAGE_PIN U7 [get_ports AD12A_P]
+set_property DIFF_TERM TRUE [get_ports AD22A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD22A_N]
+set_property DIFF_TERM TRUE [get_ports AD22A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD22A_P]
+set_property PACKAGE_PIN W16 [get_ports AD22A_P]
+set_property DIFF_TERM TRUE [get_ports AD32A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD32A_N]
+set_property DIFF_TERM TRUE [get_ports AD32A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD32A_P]
+set_property PACKAGE_PIN R18 [get_ports AD32A_P]
+set_property DIFF_TERM TRUE [get_ports AD42A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD42A_N]
+set_property DIFF_TERM TRUE [get_ports AD42A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD42A_P]
+set_property PACKAGE_PIN C22 [get_ports AD42A_P]
+set_property DIFF_TERM TRUE [get_ports AD12B_N]
+set_property IOSTANDARD LVDS [get_ports AD12B_N]
+set_property DIFF_TERM TRUE [get_ports AD12B_P]
+set_property IOSTANDARD LVDS [get_ports AD12B_P]
+set_property PACKAGE_PIN AA5 [get_ports AD12B_P]
+set_property DIFF_TERM TRUE [get_ports AD22B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD22B_N]
+set_property DIFF_TERM TRUE [get_ports AD22B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD22B_P]
+set_property PACKAGE_PIN AA16 [get_ports AD22B_P]
+set_property DIFF_TERM TRUE [get_ports AD32B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD32B_N]
+set_property DIFF_TERM TRUE [get_ports AD32B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD32B_P]
+set_property PACKAGE_PIN R21 [get_ports AD32B_P]
+set_property DIFF_TERM TRUE [get_ports AD42B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD42B_N]
+set_property DIFF_TERM TRUE [get_ports AD42B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD42B_P]
+set_property PACKAGE_PIN A20 [get_ports AD42B_P]
+set_property DIFF_TERM TRUE [get_ports AD13A_N]
+set_property IOSTANDARD LVDS [get_ports AD13A_N]
+set_property DIFF_TERM TRUE [get_ports AD13A_P]
+set_property IOSTANDARD LVDS [get_ports AD13A_P]
+set_property PACKAGE_PIN V7 [get_ports AD13A_P]
+set_property DIFF_TERM TRUE [get_ports AD23A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD23A_N]
+set_property DIFF_TERM TRUE [get_ports AD23A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD23A_P]
+set_property PACKAGE_PIN AB15 [get_ports AD23A_P]
+set_property DIFF_TERM TRUE [get_ports AD33A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD33A_N]
+set_property DIFF_TERM TRUE [get_ports AD33A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD33A_P]
+set_property PACKAGE_PIN R17 [get_ports AD33A_P]
+set_property DIFF_TERM TRUE [get_ports AD43A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD43A_N]
+set_property DIFF_TERM TRUE [get_ports AD43A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD43A_P]
+set_property PACKAGE_PIN B20 [get_ports AD43A_P]
+set_property DIFF_TERM TRUE [get_ports AD13B_N]
+set_property IOSTANDARD LVDS [get_ports AD13B_N]
+set_property DIFF_TERM TRUE [get_ports AD13B_P]
+set_property IOSTANDARD LVDS [get_ports AD13B_P]
+set_property PACKAGE_PIN AA9 [get_ports AD13B_P]
+set_property DIFF_TERM TRUE [get_ports AD23B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD23B_N]
+set_property DIFF_TERM TRUE [get_ports AD23B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD23B_P]
+set_property PACKAGE_PIN U17 [get_ports AD23B_P]
+set_property DIFF_TERM TRUE [get_ports AD33B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD33B_N]
+set_property DIFF_TERM TRUE [get_ports AD33B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD33B_P]
+set_property PACKAGE_PIN N22 [get_ports AD33B_P]
+set_property DIFF_TERM TRUE [get_ports AD43B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD43B_N]
+set_property DIFF_TERM TRUE [get_ports AD43B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD43B_P]
+set_property PACKAGE_PIN B17 [get_ports AD43B_P]
+set_property DIFF_TERM TRUE [get_ports AD14A_N]
+set_property IOSTANDARD LVDS [get_ports AD14A_N]
+set_property DIFF_TERM TRUE [get_ports AD14A_P]
+set_property IOSTANDARD LVDS [get_ports AD14A_P]
+set_property PACKAGE_PIN W6 [get_ports AD14A_P]
+set_property DIFF_TERM TRUE [get_ports AD24A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD24A_N]
+set_property DIFF_TERM TRUE [get_ports AD24A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD24A_P]
+set_property PACKAGE_PIN AA14 [get_ports AD24A_P]
+set_property DIFF_TERM TRUE [get_ports AD34A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD34A_N]
+set_property DIFF_TERM TRUE [get_ports AD34A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD34A_P]
+set_property PACKAGE_PIN P19 [get_ports AD34A_P]
+set_property DIFF_TERM TRUE [get_ports AD44A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD44A_N]
+set_property DIFF_TERM TRUE [get_ports AD44A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD44A_P]
+set_property PACKAGE_PIN D21 [get_ports AD44A_P]
+set_property DIFF_TERM TRUE [get_ports AD14B_N]
+set_property IOSTANDARD LVDS [get_ports AD14B_N]
+set_property DIFF_TERM TRUE [get_ports AD14B_P]
+set_property IOSTANDARD LVDS [get_ports AD14B_P]
+set_property PACKAGE_PIN U8 [get_ports AD14B_P]
+set_property DIFF_TERM TRUE [get_ports AD24B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD24B_N]
+set_property DIFF_TERM TRUE [get_ports AD24B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD24B_P]
+set_property PACKAGE_PIN AA20 [get_ports AD24B_P]
+set_property DIFF_TERM TRUE [get_ports AD34B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD34B_N]
+set_property DIFF_TERM TRUE [get_ports AD34B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD34B_P]
+set_property PACKAGE_PIN K21 [get_ports AD34B_P]
+set_property DIFF_TERM TRUE [get_ports AD44B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD44B_N]
+set_property DIFF_TERM TRUE [get_ports AD44B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD44B_P]
+set_property PACKAGE_PIN D19 [get_ports AD44B_P]
+set_property DIFF_TERM TRUE [get_ports AD15A_N]
+set_property IOSTANDARD LVDS [get_ports AD15A_N]
+set_property DIFF_TERM TRUE [get_ports AD15A_P]
+set_property IOSTANDARD LVDS [get_ports AD15A_P]
+set_property PACKAGE_PIN V10 [get_ports AD15A_P]
+set_property DIFF_TERM TRUE [get_ports AD25A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD25A_N]
+set_property DIFF_TERM TRUE [get_ports AD25A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD25A_P]
+set_property PACKAGE_PIN W21 [get_ports AD25A_P]
+set_property DIFF_TERM TRUE [get_ports AD35A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD35A_N]
+set_property DIFF_TERM TRUE [get_ports AD35A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD35A_P]
+set_property PACKAGE_PIN M20 [get_ports AD35A_P]
+set_property DIFF_TERM TRUE [get_ports AD45A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD45A_N]
+set_property DIFF_TERM TRUE [get_ports AD45A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD45A_P]
+set_property PACKAGE_PIN B15 [get_ports AD45A_P]
+set_property DIFF_TERM TRUE [get_ports AD15B_N]
+set_property IOSTANDARD LVDS [get_ports AD15B_N]
+set_property DIFF_TERM TRUE [get_ports AD15B_P]
+set_property IOSTANDARD LVDS [get_ports AD15B_P]
+set_property PACKAGE_PIN W11 [get_ports AD15B_P]
+set_property DIFF_TERM TRUE [get_ports AD25B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD25B_N]
+set_property DIFF_TERM TRUE [get_ports AD25B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD25B_P]
+set_property PACKAGE_PIN V20 [get_ports AD25B_P]
+set_property DIFF_TERM TRUE [get_ports AD35B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD35B_N]
+set_property DIFF_TERM TRUE [get_ports AD35B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD35B_P]
+set_property PACKAGE_PIN M17 [get_ports AD35B_P]
+set_property DIFF_TERM TRUE [get_ports AD45B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD45B_N]
+set_property DIFF_TERM TRUE [get_ports AD45B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD45B_P]
+set_property PACKAGE_PIN C14 [get_ports AD45B_P]
+set_property DIFF_TERM TRUE [get_ports AD16A_N]
+set_property IOSTANDARD LVDS [get_ports AD16A_N]
+set_property DIFF_TERM TRUE [get_ports AD16A_P]
+set_property IOSTANDARD LVDS [get_ports AD16A_P]
+set_property PACKAGE_PIN AA11 [get_ports AD16A_P]
+set_property DIFF_TERM TRUE [get_ports AD26A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD26A_N]
+set_property DIFF_TERM TRUE [get_ports AD26A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD26A_P]
+set_property PACKAGE_PIN Y21 [get_ports AD26A_P]
+set_property DIFF_TERM TRUE [get_ports AD36A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD36A_N]
+set_property DIFF_TERM TRUE [get_ports AD36A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD36A_P]
+set_property PACKAGE_PIN H22 [get_ports AD36A_P]
+set_property DIFF_TERM TRUE [get_ports AD46A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD46A_N]
+set_property DIFF_TERM TRUE [get_ports AD46A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD46A_P]
+set_property PACKAGE_PIN D15 [get_ports AD46A_P]
+set_property DIFF_TERM TRUE [get_ports AD16B_N]
+set_property IOSTANDARD LVDS [get_ports AD16B_N]
+set_property DIFF_TERM TRUE [get_ports AD16B_P]
+set_property IOSTANDARD LVDS [get_ports AD16B_P]
+set_property PACKAGE_PIN AB13 [get_ports AD16B_P]
+set_property DIFF_TERM TRUE [get_ports AD26B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD26B_N]
+set_property DIFF_TERM TRUE [get_ports AD26B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD26B_P]
+set_property PACKAGE_PIN U16 [get_ports AD26B_P]
+set_property DIFF_TERM TRUE [get_ports AD36B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD36B_N]
+set_property DIFF_TERM TRUE [get_ports AD36B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD36B_P]
+set_property PACKAGE_PIN J20 [get_ports AD36B_P]
+set_property DIFF_TERM TRUE [get_ports AD46B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD46B_N]
+set_property DIFF_TERM TRUE [get_ports AD46B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD46B_P]
+set_property PACKAGE_PIN F15 [get_ports AD46B_P]
+set_property DIFF_TERM TRUE [get_ports AD17A_N]
+set_property IOSTANDARD LVDS [get_ports AD17A_N]
+set_property DIFF_TERM TRUE [get_ports AD17A_P]
+set_property IOSTANDARD LVDS [get_ports AD17A_P]
+set_property PACKAGE_PIN V13 [get_ports AD17A_P]
+set_property DIFF_TERM TRUE [get_ports AD27A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD27A_N]
+set_property DIFF_TERM TRUE [get_ports AD27A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD27A_P]
+set_property PACKAGE_PIN T21 [get_ports AD27A_P]
+set_property DIFF_TERM TRUE [get_ports AD37A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD37A_N]
+set_property DIFF_TERM TRUE [get_ports AD37A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD37A_P]
+set_property PACKAGE_PIN G20 [get_ports AD37A_P]
+set_property DIFF_TERM TRUE [get_ports AD47A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD47A_N]
+set_property DIFF_TERM TRUE [get_ports AD47A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD47A_P]
+set_property PACKAGE_PIN C13 [get_ports AD47A_P]
+set_property DIFF_TERM TRUE [get_ports AD17B_N]
+set_property IOSTANDARD LVDS [get_ports AD17B_N]
+set_property DIFF_TERM TRUE [get_ports AD17B_P]
+set_property IOSTANDARD LVDS [get_ports AD17B_P]
+set_property PACKAGE_PIN T13 [get_ports AD17B_P]
+set_property DIFF_TERM TRUE [get_ports AD27B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD27B_N]
+set_property DIFF_TERM TRUE [get_ports AD27B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD27B_P]
+set_property PACKAGE_PIN T18 [get_ports AD27B_P]
+set_property DIFF_TERM TRUE [get_ports AD37B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD37B_N]
+set_property DIFF_TERM TRUE [get_ports AD37B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD37B_P]
+set_property PACKAGE_PIN G21 [get_ports AD37B_P]
+set_property DIFF_TERM TRUE [get_ports AD47B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD47B_N]
+set_property DIFF_TERM TRUE [get_ports AD47B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD47B_P]
+set_property PACKAGE_PIN C12 [get_ports AD47B_P]
+set_property DIFF_TERM TRUE [get_ports AD18A_N]
+set_property IOSTANDARD LVDS [get_ports AD18A_N]
+set_property DIFF_TERM TRUE [get_ports AD18A_P]
+set_property IOSTANDARD LVDS [get_ports AD18A_P]
+set_property PACKAGE_PIN W12 [get_ports AD18A_P]
+set_property DIFF_TERM TRUE [get_ports AD28A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD28A_N]
+set_property DIFF_TERM TRUE [get_ports AD28A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD28A_P]
+set_property PACKAGE_PIN U22 [get_ports AD28A_P]
+set_property DIFF_TERM TRUE [get_ports AD38A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD38A_N]
+set_property DIFF_TERM TRUE [get_ports AD38A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD38A_P]
+set_property PACKAGE_PIN L18 [get_ports AD38A_P]
+set_property DIFF_TERM TRUE [get_ports AD48A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD48A_N]
+set_property DIFF_TERM TRUE [get_ports AD48A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD48A_P]
+set_property PACKAGE_PIN A13 [get_ports AD48A_P]
+set_property DIFF_TERM TRUE [get_ports AD18B_N]
+set_property IOSTANDARD LVDS [get_ports AD18B_N]
+set_property DIFF_TERM TRUE [get_ports AD18B_P]
+set_property IOSTANDARD LVDS [get_ports AD18B_P]
+set_property PACKAGE_PIN Y13 [get_ports AD18B_P]
+set_property DIFF_TERM TRUE [get_ports AD28B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD28B_N]
+set_property DIFF_TERM TRUE [get_ports AD28B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD28B_P]
+set_property PACKAGE_PIN T20 [get_ports AD28B_P]
+set_property DIFF_TERM TRUE [get_ports AD38B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD38B_N]
+set_property DIFF_TERM TRUE [get_ports AD38B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD38B_P]
+set_property PACKAGE_PIN E21 [get_ports AD38B_P]
+set_property DIFF_TERM TRUE [get_ports AD48B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD48B_N]
+set_property DIFF_TERM TRUE [get_ports AD48B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD48B_P]
+set_property PACKAGE_PIN E14 [get_ports AD48B_P]
+set_property DIFF_TERM TRUE [get_ports DCOA1_N]
+set_property IOSTANDARD LVDS [get_ports DCOA1_N]
+set_property DIFF_TERM TRUE [get_ports DCOA1_P]
+set_property IOSTANDARD LVDS [get_ports DCOA1_P]
+set_property LOC ILOGIC_X1Y74 [get_cells FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X1Y5 [get_cells FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X1Y74 [get_cells FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN W9 [get_ports DCOA1_P]
+set_property DIFF_TERM TRUE [get_ports DCOB1_N]
+set_property IOSTANDARD LVDS [get_ports DCOB1_N]
+set_property DIFF_TERM TRUE [get_ports DCOB1_P]
+set_property IOSTANDARD LVDS [get_ports DCOB1_P]
+set_property LOC ILOGIC_X1Y76 [get_cells FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X1Y6 [get_cells FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X1Y76 [get_cells FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN Y8 [get_ports DCOB1_P]
+set_property DIFF_TERM TRUE [get_ports FRA1_N]
+set_property IOSTANDARD LVDS [get_ports FRA1_N]
+set_property DIFF_TERM TRUE [get_ports FRA1_P]
+set_property IOSTANDARD LVDS [get_ports FRA1_P]
+set_property PACKAGE_PIN U10 [get_ports FRA1_P]
+set_property DIFF_TERM TRUE [get_ports FRB1_N]
+set_property IOSTANDARD LVDS [get_ports FRB1_N]
+set_property DIFF_TERM TRUE [get_ports FRB1_P]
+set_property IOSTANDARD LVDS [get_ports FRB1_P]
+set_property PACKAGE_PIN AA10 [get_ports FRB1_P]
+set_property DIFF_TERM TRUE [get_ports DCOA2_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA2_N]
+set_property DIFF_TERM TRUE [get_ports DCOA2_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA2_P]
+set_property LOC ILOGIC_X0Y76 [get_cells FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y6 [get_cells FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y76 [get_cells FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN V19 [get_ports DCOA2_P]
+set_property DIFF_TERM TRUE [get_ports DCOB2_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB2_N]
+set_property DIFF_TERM TRUE [get_ports DCOB2_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB2_P]
+set_property LOC ILOGIC_X0Y74 [get_cells FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y5 [get_cells FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y74 [get_cells FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN Y18 [get_ports DCOB2_P]
+set_property DIFF_TERM TRUE [get_ports FRA2_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRA2_N]
+set_property DIFF_TERM TRUE [get_ports FRA2_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRA2_P]
+set_property PACKAGE_PIN AA18 [get_ports FRA2_P]
+set_property DIFF_TERM TRUE [get_ports FRB2_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRB2_N]
+set_property DIFF_TERM TRUE [get_ports FRB2_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRB2_P]
+set_property PACKAGE_PIN AA19 [get_ports FRB2_P]
+set_property DIFF_TERM TRUE [get_ports DCOA3_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA3_N]
+set_property DIFF_TERM TRUE [get_ports DCOA3_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA3_P]
+set_property LOC ILOGIC_X0Y126 [get_cells FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y10 [get_cells FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y126 [get_cells FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN L19 [get_ports DCOA3_P]
+set_property DIFF_TERM TRUE [get_ports DCOB3_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB3_N]
+set_property DIFF_TERM TRUE [get_ports DCOB3_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB3_P]
+set_property LOC ILOGIC_X0Y124 [get_cells FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y9 [get_cells FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y124 [get_cells FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN N18 [get_ports DCOB3_P]
+set_property DIFF_TERM TRUE [get_ports FRA3_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRA3_N]
+set_property DIFF_TERM TRUE [get_ports FRA3_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRA3_P]
+set_property PACKAGE_PIN N20 [get_ports FRA3_P]
+set_property DIFF_TERM TRUE [get_ports FRB3_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRB3_N]
+set_property DIFF_TERM TRUE [get_ports FRB3_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRB3_P]
+set_property PACKAGE_PIN J21 [get_ports FRB3_P]
+set_property DIFF_TERM TRUE [get_ports DCOA4_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA4_N]
+set_property DIFF_TERM TRUE [get_ports DCOA4_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA4_P]
+set_property LOC ILOGIC_X0Y176 [get_cells FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y14 [get_cells FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y176 [get_cells FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN C17 [get_ports DCOA4_P]
+set_property DIFF_TERM TRUE [get_ports DCOB4_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB4_N]
+set_property DIFF_TERM TRUE [get_ports DCOB4_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB4_P]
+set_property LOC ILOGIC_X0Y174 [get_cells FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y13 [get_cells FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y174 [get_cells FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN E17 [get_ports DCOB4_P]
+set_property DIFF_TERM TRUE [get_ports FRA4_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRA4_N]
+set_property DIFF_TERM TRUE [get_ports FRA4_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRA4_P]
+set_property PACKAGE_PIN B16 [get_ports FRA4_P]
+set_property DIFF_TERM TRUE [get_ports FRB4_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRB4_N]
+set_property DIFF_TERM TRUE [get_ports FRB4_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRB4_P]
+set_property PACKAGE_PIN E16 [get_ports FRB4_P]
+
+set_property PACKAGE_PIN W15 [get_ports {CSA[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSA[1]}]
+set_property PACKAGE_PIN V15 [get_ports {CSB[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSB[1]}]
+set_property PACKAGE_PIN U12 [get_ports SCK]
+set_property IOSTANDARD LVCMOS18 [get_ports SCK]
+set_property PACKAGE_PIN U11 [get_ports SDI]
+set_property IOSTANDARD LVCMOS18 [get_ports SDI]
+set_property PACKAGE_PIN W14 [get_ports {SDOA[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[1]}]
+set_property PACKAGE_PIN Y14 [get_ports {SDOB[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[1]}]
+set_property PACKAGE_PIN T16 [get_ports {CSA[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSA[2]}]
+set_property PACKAGE_PIN R16 [get_ports {CSB[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSB[2]}]
+set_property PACKAGE_PIN T15 [get_ports {SDOA[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[2]}]
+set_property PACKAGE_PIN U15 [get_ports {SDOB[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[2]}]
+set_property PACKAGE_PIN H17 [get_ports {CSA[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSA[3]}]
+set_property PACKAGE_PIN G17 [get_ports {CSB[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSB[3]}]
+set_property PACKAGE_PIN J16 [get_ports {SDOA[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[3]}]
+set_property PACKAGE_PIN J17 [get_ports {SDOB[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[3]}]
+set_property PACKAGE_PIN F18 [get_ports {CSA[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSA[4]}]
+set_property PACKAGE_PIN E19 [get_ports {CSB[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSB[4]}]
+set_property PACKAGE_PIN G15 [get_ports {SDOA[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[4]}]
+set_property PACKAGE_PIN G16 [get_ports {SDOB[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[4]}]
+
+set_property PACKAGE_PIN K17 [get_ports GEO]
+set_property IOSTANDARD LVCMOS25 [get_ports GEO]
+set_property SLEW SLOW [get_ports GEO]
+set_property PULLUP true [get_ports GEO]
+
+#Bank 16 = 2.5V
+set_property PACKAGE_PIN H12 [get_ports SYS_CLK]
+set_property IOSTANDARD LVCMOS25 [get_ports SYS_CLK]
+
+set_property PACKAGE_PIN D11 [get_ports INTCOMC1_N]
+set_property PACKAGE_PIN E11 [get_ports INTCOMC1_P]
+set_property PACKAGE_PIN G10 [get_ports INTCOMC2_N]
+set_property PACKAGE_PIN G11 [get_ports INTCOMC2_P]
+set_property PACKAGE_PIN E9 [get_ports INTCOM0_N]
+set_property PACKAGE_PIN F9 [get_ports INTCOM0_P]
+set_property PACKAGE_PIN H8 [get_ports INTCOM1_N]
+set_property PACKAGE_PIN H9 [get_ports INTCOM1_P]
+set_property PACKAGE_PIN F8 [get_ports INTCOM2_N]
+set_property PACKAGE_PIN G8 [get_ports INTCOM2_P]
+set_property PACKAGE_PIN C9 [get_ports INTCOM3_N]
+set_property PACKAGE_PIN D9 [get_ports INTCOM3_P]
+set_property PACKAGE_PIN B10 [get_ports INTCOM4_N]
+set_property PACKAGE_PIN B11 [get_ports INTCOM4_P]
+set_property PACKAGE_PIN A8 [get_ports INTCOM5_N]
+set_property PACKAGE_PIN A9 [get_ports INTCOM5_P]
+set_property PACKAGE_PIN B8 [get_ports INTCOM6_N]
+set_property PACKAGE_PIN C8 [get_ports INTCOM6_P]
+set_property PACKAGE_PIN A10 [get_ports INTCOM7_N]
+set_property PACKAGE_PIN A11 [get_ports INTCOM7_P]
+
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC1_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC1_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC2_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC2_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM0_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM0_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM1_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM1_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM2_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM2_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM3_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM3_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM4_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM4_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM5_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM5_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM6_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM6_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM7_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM7_P]
+
+set_property PACKAGE_PIN F10 [get_ports RCV_CLK_N]
+set_property DIFF_TERM TRUE [get_ports RCV_CLK_N]
+set_property IOSTANDARD LVDS_25 [get_ports RCV_CLK_N]
+set_property PACKAGE_PIN F11 [get_ports RCV_CLK_P]
+set_property DIFF_TERM TRUE [get_ports RCV_CLK_P]
+set_property IOSTANDARD LVDS_25 [get_ports RCV_CLK_P]
+
+set_property PACKAGE_PIN E12 [get_ports S_CTRL]
+set_property IOSTANDARD LVCMOS25 [get_ports S_CTRL]
+set_property PACKAGE_PIN E13 [get_ports T_CTRL]
+set_property IOSTANDARD LVCMOS25 [get_ports T_CTRL]
+
+#bank 34: 3.3V
+set_property PACKAGE_PIN W5 [get_ports SYNC]
+set_property IOSTANDARD LVCMOS18 [get_ports SYNC]
+set_property PACKAGE_PIN AA4 [get_ports CLKu]
+set_property IOSTANDARD LVCMOS18 [get_ports CLKu]
+set_property PACKAGE_PIN AA3 [get_ports DATAu]
+set_property IOSTANDARD LVCMOS18 [get_ports DATAu]
+set_property PACKAGE_PIN Y4 [get_ports LEu]
+set_property IOSTANDARD LVCMOS18 [get_ports LEu]
+set_property PACKAGE_PIN AB3 [get_ports RDu]
+set_property IOSTANDARD LVCMOS18 [get_ports RDu]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets RDu]
+
+set_property IOSTANDARD LVCMOS18 [get_ports ST_CLK_N]
+set_property PACKAGE_PIN T4 [get_ports ST_CLK_P]
+set_property PACKAGE_PIN U3 [get_ports ST_CLK_N]
+set_property IOSTANDARD LVCMOS18 [get_ports ST_CLK_P]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ST_CLK_N]
+
+set_property PACKAGE_PIN R3 [get_ports GCLK_P]
+set_property PACKAGE_PIN T3 [get_ports GCLK_N]
+set_property IOSTANDARD LVDS [get_ports GCLK_P]
+set_property IOSTANDARD LVDS [get_ports GCLK_N]
+#//set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets GCLK_N]
+
+set_property PACKAGE_PIN D6 [get_ports MGTREFCLK_P]
+set_property PACKAGE_PIN D5 [get_ports MGTREFCLK_N]
+
+set_property PACKAGE_PIN G3 [get_ports RX_N]
+set_property PACKAGE_PIN G4 [get_ports RX_P]
+set_property PACKAGE_PIN F1 [get_ports TX_N]
+set_property PACKAGE_PIN F2 [get_ports TX_P]
+set_property PACKAGE_PIN K1 [get_ports LOS]
+set_property IOSTANDARD LVCMOS18 [get_ports LOS]
+set_property PACKAGE_PIN L1 [get_ports TX_DIS]
+set_property IOSTANDARD LVCMOS18 [get_ports TX_DIS]
+
+set_property PACKAGE_PIN M2 [get_ports {MOD_DEF[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MOD_DEF[0]}]
+set_property PACKAGE_PIN M1 [get_ports {MOD_DEF[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MOD_DEF[1]}]
+set_property PACKAGE_PIN K3 [get_ports {MOD_DEF[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MOD_DEF[2]}]
+
+set_property PACKAGE_PIN T10 [get_ports TEMP_OUT]
+set_property IOSTANDARD LVCMOS18 [get_ports TEMP_OUT]
+set_property PACKAGE_PIN T11 [get_ports TEMP_IN]
+set_property IOSTANDARD LVCMOS18 [get_ports TEMP_IN]
+
+set_property PACKAGE_PIN Y1 [get_ports MON1_N]
+set_property IOSTANDARD LVCMOS18 [get_ports MON1_N]
+#set_property IOSTANDARD LVDS [get_ports MON1_N]
+set_property PACKAGE_PIN W1 [get_ports MON1_P]
+#set_property IOSTANDARD LVCMOS18 [get_ports MON1_P]
+set_property IOSTANDARD LVDS [get_ports MON1_P]
+
+set_property PACKAGE_PIN Y2 [get_ports MON2_N]
+#set_property IOSTANDARD LVCMOS18 [get_ports MON2_N]
+set_property IOSTANDARD LVDS [get_ports MON2_N]
+set_property PACKAGE_PIN Y3 [get_ports MON2_P]
+#set_property IOSTANDARD LVCMOS18 [get_ports MON2_P]
+set_property IOSTANDARD LVDS [get_ports MON2_P]
+
+set_property PACKAGE_PIN G13 [get_ports JTAG_OUT1_TCK_F]
+set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TCK_F]
+set_property PACKAGE_PIN H14 [get_ports JTAG_OUT1_TDI_F]
+set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TDI_F]
+set_property PACKAGE_PIN H13 [get_ports JTAG_OUT1_TDO_F]
+set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TDO_F]
+set_property PACKAGE_PIN F13 [get_ports JTAG_OUT1_TMS_F]
+set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TMS_F]
+
+set_property PACKAGE_PIN D1 [get_ports GT_A2B_0_N]
+set_property PACKAGE_PIN D2 [get_ports GT_A2B_0_P]
+set_property PACKAGE_PIN B1 [get_ports GT_A2B_1_N]
+set_property PACKAGE_PIN B2 [get_ports GT_A2B_1_P]
+set_property PACKAGE_PIN E3 [get_ports GT_B2A_0_N]
+set_property PACKAGE_PIN E4 [get_ports GT_B2A_0_P]
+set_property PACKAGE_PIN C3 [get_ports GT_B2A_1_N]
+set_property PACKAGE_PIN C4 [get_ports GT_B2A_1_P]
+
+#NET "DONE_P1" LOC = P6;
+#NET "CF_D0_I1" LOC = H18;
+#NET "CF_D1_I1" LOC = H19;
+#NET "CF_D2_I1" LOC = G18;
+#NET "CF_D3_I1" LOC = F19;
+#NET "CF_EMCL_I1" LOC = H12;
+#NET "CF_EMCL_I1" LOC = J19;
+#NET "CF_FCS_I1" LOC = L16;
+#NET "CF_PUDC_I1" LOC = K18;
+#NET "CCLK1_P1" LOC = G7;
+#NET "JTAG_IN1_TCK" LOC = K7;
+#NET "JTAG_IN1_TDI" LOC = K6;
+#NET "JTAG_IN1_TDO" LOC = J6;
+#NET "JTAG_IN1_TMS" LOC = L6;
+
+
+##########################################################################################
+# done inside clockmodule100Mto80M # create_clock -period 10.000 -name SYS_CLK [get_ports SYS_CLK]
+create_clock -period 6.430 -name ST_CLK_N [get_ports ST_CLK_N]
+
+
+
+
+
+create_pblock pblock_adc_1
+add_cells_to_pblock [get_pblocks pblock_adc_1] [get_cells {FEE_ADCinput_module1/AdcToplevel2356_1/* FEE_ADCinput_module1/AdcToplevel1458_1/*}]
+add_cells_to_pblock [get_pblocks pblock_adc_1] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_1 FEE_ADCinput_module1/AdcToplevel2356_1}]
+resize_pblock [get_pblocks pblock_adc_1] -add {SLICE_X106Y50:SLICE_X109Y99}
+#add_cells_to_pblock [get_pblocks pblock_adc_1] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel2356_1 FEE_ADCinput_module1/AdcToplevel1458_1]]
+create_pblock pblock_adc_2
+add_cells_to_pblock [get_pblocks pblock_adc_2] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_2/* FEE_ADCinput_module1/AdcToplevel2356_2/*}]
+add_cells_to_pblock [get_pblocks pblock_adc_2] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_2 FEE_ADCinput_module1/AdcToplevel2356_2}]
+resize_pblock [get_pblocks pblock_adc_2] -add {SLICE_X0Y50:SLICE_X3Y99}
+#add_cells_to_pblock [get_pblocks pblock_adc_2] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel1458_2 FEE_ADCinput_module1/AdcToplevel2356_2]]
+create_pblock pblock_adc_3
+add_cells_to_pblock [get_pblocks pblock_adc_3] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_3/* FEE_ADCinput_module1/AdcToplevel2356_3/*}]
+add_cells_to_pblock [get_pblocks pblock_adc_3] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_3 FEE_ADCinput_module1/AdcToplevel2356_3}]
+resize_pblock [get_pblocks pblock_adc_3] -add {SLICE_X0Y100:SLICE_X3Y149}
+#add_cells_to_pblock [get_pblocks pblock_adc_3] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel1458_3 FEE_ADCinput_module1/AdcToplevel2356_3]]
+create_pblock pblock_adc_4
+add_cells_to_pblock [get_pblocks pblock_adc_4] [get_cells {FEE_ADCinput_module1/AdcToplevel2356_4/* FEE_ADCinput_module1/AdcToplevel1458_4/*}]
+add_cells_to_pblock [get_pblocks pblock_adc_4] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_4 FEE_ADCinput_module1/AdcToplevel2356_4}]
+resize_pblock [get_pblocks pblock_adc_4] -add {SLICE_X0Y151:SLICE_X3Y199}
+#add_cells_to_pblock [get_pblocks pblock_adc_4] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel2356_4 FEE_ADCinput_module1/AdcToplevel1458_4]]
+
+#############################################################################################
+# Timing constraints
+#############################################################################################
+# The DCLK input clock, bit clock from the ADC, doesn't need a timespec.
+# This clock passes from the IOB through the BUFIO and to the .CLK input of all used ISERDES.
+# This path is made from dedicated routing.
+# From the IOB to theBUFIO.I is a dedicated connection only availabel with Clock Capable_IO.
+# This connection takes for all IO-banks in a FPGA and from all FPGAs of the familly an
+# average value of 220 ps.
+# The connection from the BUFIO.O to all ISERDES.CLK is also a dedicated connection, it
+# takes on average 330 ps.
+# The BUFIO average delay is: 869 ps and an LVDS IOB is average: 1094 ps.
+# A MAXSKEW constraint is used to detect the skew on the CLK net.
+
+#
+# The connection from the BUFR.O to the ISERDES.CLKDIV inputs runs over normal clock nets.
+# Oposite to the BUFIO.O - ISERDES.CLK routing, the BUFR.O net not only connects to the
+# ISERDES.CLKDIV pins of the I/O SERDES in the IO-bank the BUFR is located in but to all
+# clocked elements (FFs, BRAM, DSP, ..) in that clock area.
+# It also connects to the adjacent upper and lower clock areas.
+# Therefore it is necessary to put timing constraints on this clock.
+# A MAXSKEW constraint to keep the skew as low as possible. makes sure the ISERDES are clocked
+# at the same time so that early-late data cannot appear at the outputs of the ISERDES.
+
+
+set_false_path -through [get_nets GEO]
+set_false_path -through [get_ports GEO]
+set_false_path -from [get_ports GEO]
+set_false_path -from [get_ports S_CTRL]
+set_false_path -to [get_ports T_CTRL]
+
+create_clock -period 12.500 -name ADC_clk_S [get_pins FEE_ADCinput_module1/ADCclkbuf/O]
+
+#//create_generated_clock -name clock40MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clock40MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clock_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT1]
+#//create_generated_clock -name clock100MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT2]
+create_generated_clock -name clock200MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT3]
+create_generated_clock -name async_clock_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT4]
+#create_generated_clock -name rxSodaClk80_S [get_pins clockmodule40Mto80M1/inst/mmcm_adv_inst/CLKOUT1]
+#create_generated_clock -name rxSodaClk40_S [get_pins FEE_gtxModule1/FEE_SODAfrequencydiv51/clockdiv5buf/O]
+#create_generated_clock -name rxSodaClk_S [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/FEE_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT1]
+#create_generated_clock -name RXOUTCLK [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/gtx_i/gtxKintex7FEE80_init_i/U0/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i/RXOUTCLK]
+
+create_clock -name aurora_clock -period 10.000 [get_pins gen_combine.aurora_dual_module1/aurora_module_i/clock_module_i/user_clk_buf_i/I]
+#create_generated_clock -name aurora_clock [get_pins gen_combine.aurora_dual_module1/aurora_module_i/aurora_dual_i/U0/gt_wrapper_i/aurora_dual_multi_gt_i/gt0_aurora_dual_i/gtxe2_i/TXOUTCLK
+
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
+
+
+
+################################# GTX #####################
+#NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P";
+#TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 8 ns HIGH 50 %;
+#NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N";
+#TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 8 ns HIGH 50 %;
+create_clock -period 12.500 -name GCLK_P [get_ports GCLK_P]
+#create_clock -period 12.500 -name GCLK_N [get_ports GCLK_N]
+create_clock -period 12.500 [get_ports MGTREFCLK_P]
+#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
+#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
+#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}]
+##---------- Set placement for gt0_gtx_wrapper_i/GTXE2_CHANNEL ------
+#set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells gtxKintex7FEE80_support_i/gtxKintex7FEE80_init_i/inst/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i]
+
+#create_generated_clock -name rxSodaClk [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/FEE_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT1]
+create_clock -period 5.0 -name rxSodaClk [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/FEE_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT1]
+create_clock -period 12.5 [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*TXOUTCLK}]
+#create_clock -period 10.0 [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*RXOUTCLK}]
+create_clock -period 10.0 -name RXOUTCLK [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/gtx_i/gtxKintex7FEE80_init_i/U0/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i/RXOUTCLK]
+
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clockmodule40Mto80M1/inst/clk_out2]
+
+
+create_clock -period 3.125 -name BitClk_0 [get_pins FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_1 [get_pins FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_2 [get_pins FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_3 [get_pins FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_4 [get_pins FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_5 [get_pins FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_6 [get_pins FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_7 [get_pins FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+
+create_clock -period 3.125 -name DCOA1_P -waveform {0.000 1.563} [get_ports DCOA1_P]
+create_clock -period 3.125 -name DCOA2_P -waveform {0.000 1.563} [get_ports DCOA2_P]
+create_clock -period 3.125 -name DCOA3_P -waveform {0.000 1.563} [get_ports DCOA3_P]
+create_clock -period 3.125 -name DCOA4_P -waveform {0.000 1.563} [get_ports DCOA4_P]
+create_clock -period 3.125 -name DCOB1_P -waveform {0.000 1.563} [get_ports DCOB1_P]
+create_clock -period 3.125 -name DCOB2_P -waveform {0.000 1.563} [get_ports DCOB2_P]
+create_clock -period 3.125 -name DCOB3_P -waveform {0.000 1.563} [get_ports DCOB3_P]
+create_clock -period 3.125 -name DCOB4_P -waveform {0.000 1.563} [get_ports DCOB4_P]
+#create_clock -period 1000.000 -name GEO -waveform {0.000 500.000} [get_ports GEO]
+
+#create_clock -period 12.500 -name clock_S -waveform {0.000 6.250} [get_nets clock_S]
+#create_clock -period 10.000 -name clock100MHz_S -waveform {0.000 5.000} [get_nets clock100MHz_S]
+#create_clock -period 5.000 -name clock200MHz_S -waveform {0.000 2.500} [get_nets clock200MHz_S]
+#create_clock -period 15.833 -name async_clock_S [get_nets async_clock_S]
+
+#create_clock -period 12.500 -name adcclockA0 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_1/IntClkDiv]
+#create_clock -period 12.500 -name adcclockA1 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_2/IntClkDiv]
+#create_clock -period 12.500 -name adcclockA2 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_3/IntClkDiv]
+#create_clock -period 12.500 -name adcclockA3 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_4/IntClkDiv]
+#create_clock -period 12.500 -name adcclockB0 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_1/IntClkDiv]
+#create_clock -period 12.500 -name adcclockB1 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_2/IntClkDiv]
+#create_clock -period 12.500 -name adcclockB2 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_3/IntClkDiv]
+#create_clock -period 12.500 -name adcclockB3 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_4/IntClkDiv]
+
+create_clock -period 12.500 -name adcclockA0 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockA1 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockA2 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockA3 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockB0 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockB1 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockB2 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockB3 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+
+
+set_false_path -from [get_clocks SYS_CLK] -to [get_clocks {ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks ST_CLK_N] -to [get_clocks {SYS_CLK GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks GCLK_P] -to [get_clocks {SYS_CLK ST_CLK_N ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks ADC_clk_S] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_0] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_1] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_2] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_3] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_4] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_5] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_6] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_7}]
+set_false_path -from [get_clocks BitClk_7] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6}]
+
+#//set_false_path -from [get_clocks clock_S] -to [get_clocks -include_generated_clocks {clock100MHz_S clock200MHz_S ADC_clk_S }]
+set_false_path -from [get_clocks clock_S] -to [get_clocks -include_generated_clocks {clock200MHz_S ADC_clk_S RXOUTCLK rxSodaClk aurora_clock}]
+#//set_false_path -from [get_clocks clock100MHz_S] -to [get_clocks -include_generated_clocks {clock_S ADC_clk_S}]
+set_false_path -from [get_clocks clock200MHz_S] -to [get_clocks -include_generated_clocks {clock_S ADC_clk_S aurora_clock}]
+#//set_false_path -from [get_clocks ADC_clk_S] -to [get_clocks -include_generated_clocks {clock_S clock100MHz_S clock200MHz_S}]
+set_false_path -from [get_clocks ADC_clk_S] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S aurora_clock}]
+set_false_path -from [get_clocks RXOUTCLK] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S aurora_clock}]
+set_false_path -from [get_clocks rxSodaClk] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S aurora_clock}]
+set_false_path -from [get_clocks aurora_clock] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S ADC_clk_S RXOUTCLK rxSodaClk}]
+
+set_false_path -from [get_clocks adcclockA0] -to [get_clocks BitClk_0]
+set_false_path -from [get_clocks adcclockB0] -to [get_clocks BitClk_1]
+set_false_path -from [get_clocks adcclockA1] -to [get_clocks BitClk_2]
+set_false_path -from [get_clocks adcclockB1] -to [get_clocks BitClk_3]
+set_false_path -from [get_clocks adcclockA2] -to [get_clocks BitClk_4]
+set_false_path -from [get_clocks adcclockB2] -to [get_clocks BitClk_5]
+set_false_path -from [get_clocks adcclockA3] -to [get_clocks BitClk_6]
+set_false_path -from [get_clocks adcclockB3] -to [get_clocks BitClk_7]
+
+set_false_path -from [get_clocks adcclockA0] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockB0] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockA1] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockB1] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockA2] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockB2] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockA3] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockB3] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+
+set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks {adcclockA0 adcclockB0 adcclockA1 adcclockB1 adcclockA2 adcclockB2 adcclockA3 adcclockB3}]
+
+#//set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock40MHz_S]
+set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock_S]
+#//set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock100MHz_S]
+set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock200MHz_S]
+#//set_false_path -from [get_clocks -include_generated_clocks clock40MHz_S] -to [get_clocks -include_generated_clocks async_clock_S]
+
+#//set_false_path -from [get_clocks -include_generated_clocks clock40MHz_S] -to [get_clocks -include_generated_clocks async_clock_S]
+set_false_path -from [get_clocks -include_generated_clocks clock_S] -to [get_clocks -include_generated_clocks async_clock_S]
+#//set_false_path -from [get_clocks -include_generated_clocks clock100MHz_S] -to [get_clocks -include_generated_clocks async_clock_S]
+set_false_path -from [get_clocks -include_generated_clocks clock200MHz_S] -to [get_clocks -include_generated_clocks async_clock_S]
+
+set_max_delay -from [get_clocks rxSodaClk] -to [get_clocks -include_generated_clocks {ADC_clk_S}] 3.0
+
+################################################################################
+# Timespec between groups
+################################################################################
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcFrame/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000
+
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000
+
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000
+
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000
+
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000
+
+set_max_delay -from [get_clocks BitClk_0] 1.000
+set_max_delay -from [get_clocks BitClk_1] 1.000
+set_max_delay -from [get_clocks BitClk_2] 1.000
+set_max_delay -from [get_clocks BitClk_3] 1.000
+set_max_delay -from [get_clocks BitClk_4] 1.000
+set_max_delay -from [get_clocks BitClk_5] 1.000
+set_max_delay -from [get_clocks BitClk_6] 1.000
+set_max_delay -from [get_clocks BitClk_7] 1.000
+set_max_delay -from [get_clocks adcclockA0] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockA1] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockA2] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockA3] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockB0] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockB1] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockB2] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockB3] -to [get_clocks ADC_clk_S] 2.600
+#--//set_max_delay -from [get_clocks ADC_clk_S] 3.000
+
+
+#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -min -add_delay 0.000 [get_ports AD11A_N]
+#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -max -add_delay 1.000 [get_ports AD11A_N]
+#set_input_delay -clock [get_clocks BitClk_0] -min -add_delay 0.000 [get_ports AD11A_N]
+#set_input_delay -clock [get_clocks BitClk_0] -max -add_delay 1.000 [get_ports AD11A_N]
+#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -min -add_delay 0.000 [get_ports AD11A_P]
+#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -max -add_delay 1.000 [get_ports AD11A_P]
+#set_input_delay -clock [get_clocks BitClk_0] -min -add_delay 0.000 [get_ports AD11A_P]
+#set_input_delay -clock [get_clocks BitClk_0] -max -add_delay 1.000 [get_ports AD11A_P]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clockmodule40Mto80M1/inst/clk_out2]
+
+# TXOUTCLK Constraint: Value is selected based on the line rate (4.0 Gbps) and lane width (4-Byte)
+#create_clock -period 10.000 [get_pins -hier -filter {name=~*gt_wrapper_i*aurora_dual_multi_gt_i*gt0_aurora_dual_i*gtxe2_i*TXOUTCLK}]
+#### CDC Path #####
+set_false_path -to [get_pins -hier *cdc_to*]
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *ack_sync_reg1}]
+############################### GT LOC (For use in top level design) ###################################
+set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells gen_combine.aurora_dual_module1/aurora_module_i/aurora_dual_i/U0/gt_wrapper_i/aurora_dual_multi_gt_i/gt0_aurora_dual_i/gtxe2_i]
+set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells gen_combine.aurora_dual_module1/aurora_module_i/aurora_dual_i/U0/gt_wrapper_i/aurora_dual_multi_gt_i/gt1_aurora_dual_i/gtxe2_i]
+
+#//set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
+#//set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
+#//set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}]
+#//set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells gtxconn1_module1/gtxconn1_support_i/gtxconn1_init_i/U0/gtxconn1_i/gt0_gtxconn1_i/gtxe2_i]
+#//set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells gtxconn2_module1/gtxconn2_support_i/gtxconn2_init_i/U0/gtxconn2_i/gt0_gtxconn2_i/gtxe2_i]
+
+
+# Configuration options
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
--- /dev/null
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+--library Adc_Interface;
+-- use Adc_Interface.all;
+library work;
+USE work.panda_package.all;
+use work.soda_components.all;
+
+entity FEE_Kintex_ADCboard is
+ Port (
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+ SYS_CLK : in std_logic; -- 100MHz
+ GCLK_P : in std_logic;
+ GCLK_N : in std_logic;
+ ST_CLK_P : in std_logic;
+ ST_CLK_N : in std_logic;
+
+----ADC1---------------------------------------------
+ AD11A_P : in std_logic;
+ AD11A_N : in std_logic;
+ AD11B_P : in std_logic;
+ AD11B_N : in std_logic;
+ AD12A_P : in std_logic;
+ AD12A_N : in std_logic;
+ AD12B_P : in std_logic;
+ AD12B_N : in std_logic;
+ AD13A_P : in std_logic;
+ AD13A_N : in std_logic;
+ AD13B_P : in std_logic;
+ AD13B_N : in std_logic;
+ AD14A_P : in std_logic;
+ AD14A_N : in std_logic;
+ AD14B_P : in std_logic;
+ AD14B_N : in std_logic;
+ AD15A_P : in std_logic;
+ AD15A_N : in std_logic;
+ AD15B_P : in std_logic;
+ AD15B_N : in std_logic;
+ AD16A_P : in std_logic;
+ AD16A_N : in std_logic;
+ AD16B_P : in std_logic;
+ AD16B_N : in std_logic;
+ AD17A_P : in std_logic;
+ AD17A_N : in std_logic;
+ AD17B_P : in std_logic;
+ AD17B_N : in std_logic;
+ AD18A_P : in std_logic;
+ AD18A_N : in std_logic;
+ AD18B_P : in std_logic;
+ AD18B_N : in std_logic;
+
+ DCOA1_P : in std_logic;
+ DCOA1_N : in std_logic;
+ DCOB1_P : in std_logic;
+ DCOB1_N : in std_logic;
+
+ FRA1_P : in std_logic;
+ FRA1_N : in std_logic;
+ FRB1_P : in std_logic;
+ FRB1_N : in std_logic;
+
+
+----ADC2---------------------------------------------
+ AD21A_P : in std_logic;
+ AD21A_N : in std_logic;
+ AD21B_P : in std_logic;
+ AD21B_N : in std_logic;
+ AD22A_P : in std_logic;
+ AD22A_N : in std_logic;
+ AD22B_P : in std_logic;
+ AD22B_N : in std_logic;
+ AD23A_P : in std_logic;
+ AD23A_N : in std_logic;
+ AD23B_P : in std_logic;
+ AD23B_N : in std_logic;
+ AD24A_P : in std_logic;
+ AD24A_N : in std_logic;
+ AD24B_P : in std_logic;
+ AD24B_N : in std_logic;
+ AD25A_P : in std_logic;
+ AD25A_N : in std_logic;
+ AD25B_P : in std_logic;
+ AD25B_N : in std_logic;
+ AD26A_P : in std_logic;
+ AD26A_N : in std_logic;
+ AD26B_P : in std_logic;
+ AD26B_N : in std_logic;
+ AD27A_P : in std_logic;
+ AD27A_N : in std_logic;
+ AD27B_P : in std_logic;
+ AD27B_N : in std_logic;
+ AD28A_P : in std_logic;
+ AD28A_N : in std_logic;
+ AD28B_P : in std_logic;
+ AD28B_N : in std_logic;
+
+ DCOA2_P : in std_logic;
+ DCOA2_N : in std_logic;
+ DCOB2_P : in std_logic;
+ DCOB2_N : in std_logic;
+
+ FRA2_P : in std_logic;
+ FRA2_N : in std_logic;
+ FRB2_P : in std_logic;
+ FRB2_N : in std_logic;
+
+----ADC3---------------------------------------------
+ AD31A_P : in std_logic;
+ AD31A_N : in std_logic;
+ AD31B_P : in std_logic;
+ AD31B_N : in std_logic;
+ AD32A_P : in std_logic;
+ AD32A_N : in std_logic;
+ AD32B_P : in std_logic;
+ AD32B_N : in std_logic;
+ AD33A_P : in std_logic;
+ AD33A_N : in std_logic;
+ AD33B_P : in std_logic;
+ AD33B_N : in std_logic;
+ AD34A_P : in std_logic;
+ AD34A_N : in std_logic;
+ AD34B_P : in std_logic;
+ AD34B_N : in std_logic;
+ AD35A_P : in std_logic;
+ AD35A_N : in std_logic;
+ AD35B_P : in std_logic;
+ AD35B_N : in std_logic;
+ AD36A_P : in std_logic;
+ AD36A_N : in std_logic;
+ AD36B_P : in std_logic;
+ AD36B_N : in std_logic;
+ AD37A_P : in std_logic;
+ AD37A_N : in std_logic;
+ AD37B_P : in std_logic;
+ AD37B_N : in std_logic;
+ AD38A_P : in std_logic;
+ AD38A_N : in std_logic;
+ AD38B_P : in std_logic;
+ AD38B_N : in std_logic;
+
+ DCOA3_P : in std_logic;
+ DCOA3_N : in std_logic;
+ DCOB3_P : in std_logic;
+ DCOB3_N : in std_logic;
+
+ FRA3_P : in std_logic;
+ FRA3_N : in std_logic;
+ FRB3_P : in std_logic;
+ FRB3_N : in std_logic;
+
+----ADC4---------------------------------------------
+ AD41A_P : in std_logic;
+ AD41A_N : in std_logic;
+ AD41B_P : in std_logic;
+ AD41B_N : in std_logic;
+ AD42A_P : in std_logic;
+ AD42A_N : in std_logic;
+ AD42B_P : in std_logic;
+ AD42B_N : in std_logic;
+ AD43A_P : in std_logic;
+ AD43A_N : in std_logic;
+ AD43B_P : in std_logic;
+ AD43B_N : in std_logic;
+ AD44A_P : in std_logic;
+ AD44A_N : in std_logic;
+ AD44B_P : in std_logic;
+ AD44B_N : in std_logic;
+ AD45A_P : in std_logic;
+ AD45A_N : in std_logic;
+ AD45B_P : in std_logic;
+ AD45B_N : in std_logic;
+ AD46A_P : in std_logic;
+ AD46A_N : in std_logic;
+ AD46B_P : in std_logic;
+ AD46B_N : in std_logic;
+ AD47A_P : in std_logic;
+ AD47A_N : in std_logic;
+ AD47B_P : in std_logic;
+ AD47B_N : in std_logic;
+ AD48A_P : in std_logic;
+ AD48A_N : in std_logic;
+ AD48B_P : in std_logic;
+ AD48B_N : in std_logic;
+
+ DCOA4_P : in std_logic;
+ DCOA4_N : in std_logic;
+ DCOB4_P : in std_logic;
+ DCOB4_N : in std_logic;
+
+ FRA4_P : in std_logic;
+ FRA4_N : in std_logic;
+ FRB4_P : in std_logic;
+ FRB4_N : in std_logic;
+
+----ADCconfiguration---------------------------------------------
+ SCK : out std_logic;
+ SDI : out std_logic;
+ CSA : out std_logic_vector(1 to 4);
+ CSB : out std_logic_vector(1 to 4);
+ SDOA : in std_logic_vector(1 to 4); -- out for parallel init
+ SDOB : in std_logic_vector(1 to 4); -- out for parallel init
+
+----GTX---------------------------------------------
+ MOD_DEF : in std_logic_vector(2 downto 0);
+ LOS : in std_logic;
+ TX_DIS : out std_logic;
+ MGTREFCLK_P : in std_logic;
+ MGTREFCLK_N : in std_logic;
+
+ RX_P : in std_logic;
+ RX_N : in std_logic;
+ TX_P : out std_logic;
+ TX_N : out std_logic;
+
+----PLL---------------------------------------------
+ S_CTRL : in std_logic; -- 1 : FPGA1 controls PLL&JTAG, 0 : FPGA2 controls PLL&JTAG
+ T_CTRL : out std_logic; -- T_CTRL from FPGA1<>T_CTRL from FPGA2 : FPGA2 controls PLL&JTAG
+ RDu : in std_logic;
+ CLKu : inout std_logic;
+ DATAu : inout std_logic;
+ LEu : inout std_logic;
+ SYNC : out std_logic;
+ RCV_CLK_P : out std_logic; -- ref clock for PLL LMK04806
+ RCV_CLK_N : out std_logic;
+
+----interconnection---------------------------------------------
+ INTCOMC1_P : inout std_logic;
+ INTCOMC1_N : inout std_logic;
+ INTCOMC2_P : inout std_logic;
+ INTCOMC2_N : inout std_logic;
+
+ INTCOM0_P : inout std_logic;
+ INTCOM0_N : inout std_logic;
+ INTCOM1_P : inout std_logic;
+ INTCOM1_N : inout std_logic;
+ INTCOM2_P : inout std_logic;
+ INTCOM2_N : inout std_logic;
+ INTCOM3_P : inout std_logic;
+ INTCOM3_N : inout std_logic;
+ INTCOM4_P : inout std_logic;
+ INTCOM4_N : inout std_logic;
+ INTCOM5_P : inout std_logic;
+ INTCOM5_N : inout std_logic;
+ INTCOM6_P : inout std_logic;
+ INTCOM6_N : inout std_logic;
+ INTCOM7_P : inout std_logic;
+ INTCOM7_N : inout std_logic;
+
+----Temperature-------------------------------------
+ TEMP_IN : out std_logic;
+ TEMP_OUT : in std_logic;
+
+----Interconnection-------------------------------------
+ GT_A2B_0_P : out std_logic;
+ GT_A2B_0_N : out std_logic;
+ GT_A2B_1_P : out std_logic;
+ GT_A2B_1_N : out std_logic;
+ GT_B2A_0_P : in std_logic;
+ GT_B2A_0_N : in std_logic;
+ GT_B2A_1_P : in std_logic;
+ GT_B2A_1_N : in std_logic;
+
+----JTAG out-------------------------------------
+ JTAG_OUT1_TCK_F : inout std_logic;
+ JTAG_OUT1_TDI_F : inout std_logic;
+ JTAG_OUT1_TDO_F : inout std_logic;
+ JTAG_OUT1_TMS_F : inout std_logic;
+
+----Test,Monitor-------------------------------------
+ MON1_P : out std_logic;
+ MON1_N : out std_logic; -- in
+ MON2_P : out std_logic;
+ MON2_N : out std_logic
+ );
+end FEE_Kintex_ADCboard;
+
+
+
+architecture Behavioral of FEE_Kintex_ADCboard is
+constant FPGA_IN_CONTROL : std_logic := '0';
+constant ADC_PARALLELINIT : boolean := true;
+constant SWAPFPGAS : boolean := false;
+constant SECOND_FE_MODULE : boolean := true;
+constant MWD_DOUBLEFILTER : boolean := true;
+constant MWD_PU_DOUBLEFILTER : boolean := true;
+constant MWD_WIDTHBITS : natural := 4;
+constant MWD_SCALEBITS : natural := 12;
+constant MWD2_WIDTHBITS : natural := 1;
+constant MWD2_SCALEBITS : natural := 8;
+constant BASELINE_BWBITS : natural := 10;
+constant WAVEFORMBUFFERSIZE : natural := 9;
+constant CF_DELAYBITS : natural := 3;
+constant MAXPILEUPHITS : natural := 3;
+constant IDIVMAXBITS : natural := 6;
+constant INTEGRALRATIOBITS : natural := 3;
+
+
+component clockmodule100to80M
+port(
+ CLK_IN1 : in std_logic;
+ CLK_OUT1 : out std_logic;
+ CLK_OUT2 : out std_logic;
+ CLK_OUT3 : out std_logic;
+ CLK_OUT4 : out std_logic;
+ CLK_OUT5 : out std_logic;
+ CLK_OUT6 : out std_logic;
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+component clockmodule40Mto80M
+port(
+ CLK_IN1 : in std_logic;
+ CLK_OUT1 : out std_logic;
+ CLK_OUT2 : out std_logic;
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+component LMK04806 is
+ generic(
+ CLK_DIV : integer := 2 -- slow down transfer : mayb 1
+ );
+ port(
+ clock : in std_logic; --Master clock
+ reset : in std_logic; --reset
+ CLKu : out std_logic; --Clk to LMK
+ DATAu : out std_logic; --Data to LMK
+ LEu : out std_logic; --Data Latch to LMK
+ RDu : in std_logic; --Read back
+ SYNC : out std_logic; --Sync CLK outputs LMK
+ boot_PLL : in std_logic; --Start booting when set high
+ booting : out std_logic --busy signal
+ );
+end component;
+
+component FEE_startup is
+ port(
+ clock : in std_logic;
+ ADCclock : in std_logic;
+ clock_from_PLL : in std_logic;
+ reset : in std_logic;
+ GEO : in std_logic;
+ IcontrolPLL : in std_logic;
+ ADCchip_init : out std_logic;
+ PLL_init : out std_logic;
+ PLL_booting : in std_logic;
+ GTX_reset : out std_logic;
+ GTX_LOS : in std_logic;
+ GTX_rxLocked : in std_logic;
+ GTX_txLocked : in std_logic;
+ GTX_error : in std_logic;
+ PLLuseGTXclock : out std_logic;
+ PLL_locked : in std_logic;
+ ADCs_reset : out std_logic;
+ ADCs_ready : in std_logic;
+ FEE_reset : out std_logic;
+ startupready : out std_logic
+ );
+end component;
+
+component FEE_ADCinput_module is
+ port (
+ clock200MHz : in std_logic;
+ clock80MHz : in std_logic;
+ clockAsync : in std_logic;
+ reset : in std_logic;
+ ADCs_enable : in std_logic;
+----ADC1---------------------------------------------
+ AD11A_P : in std_logic;
+ AD11A_N : in std_logic;
+ AD11B_P : in std_logic;
+ AD11B_N : in std_logic;
+ AD12A_P : in std_logic;
+ AD12A_N : in std_logic;
+ AD12B_P : in std_logic;
+ AD12B_N : in std_logic;
+ AD13A_P : in std_logic;
+ AD13A_N : in std_logic;
+ AD13B_P : in std_logic;
+ AD13B_N : in std_logic;
+ AD14A_P : in std_logic;
+ AD14A_N : in std_logic;
+ AD14B_P : in std_logic;
+ AD14B_N : in std_logic;
+ AD15A_P : in std_logic;
+ AD15A_N : in std_logic;
+ AD15B_P : in std_logic;
+ AD15B_N : in std_logic;
+ AD16A_P : in std_logic;
+ AD16A_N : in std_logic;
+ AD16B_P : in std_logic;
+ AD16B_N : in std_logic;
+ AD17A_P : in std_logic;
+ AD17A_N : in std_logic;
+ AD17B_P : in std_logic;
+ AD17B_N : in std_logic;
+ AD18A_P : in std_logic;
+ AD18A_N : in std_logic;
+ AD18B_P : in std_logic;
+ AD18B_N : in std_logic;
+
+ DCOA1_P : in std_logic;
+ DCOA1_N : in std_logic;
+ DCOB1_P : in std_logic;
+ DCOB1_N : in std_logic;
+
+ FRA1_P : in std_logic;
+ FRA1_N : in std_logic;
+ FRB1_P : in std_logic;
+ FRB1_N : in std_logic;
+
+----ADC2---------------------------------------------
+ AD21A_P : in std_logic;
+ AD21A_N : in std_logic;
+ AD21B_P : in std_logic;
+ AD21B_N : in std_logic;
+ AD22A_P : in std_logic;
+ AD22A_N : in std_logic;
+ AD22B_P : in std_logic;
+ AD22B_N : in std_logic;
+ AD23A_P : in std_logic;
+ AD23A_N : in std_logic;
+ AD23B_P : in std_logic;
+ AD23B_N : in std_logic;
+ AD24A_P : in std_logic;
+ AD24A_N : in std_logic;
+ AD24B_P : in std_logic;
+ AD24B_N : in std_logic;
+ AD25A_P : in std_logic;
+ AD25A_N : in std_logic;
+ AD25B_P : in std_logic;
+ AD25B_N : in std_logic;
+ AD26A_P : in std_logic;
+ AD26A_N : in std_logic;
+ AD26B_P : in std_logic;
+ AD26B_N : in std_logic;
+ AD27A_P : in std_logic;
+ AD27A_N : in std_logic;
+ AD27B_P : in std_logic;
+ AD27B_N : in std_logic;
+ AD28A_P : in std_logic;
+ AD28A_N : in std_logic;
+ AD28B_P : in std_logic;
+ AD28B_N : in std_logic;
+
+ DCOA2_P : in std_logic;
+ DCOA2_N : in std_logic;
+ DCOB2_P : in std_logic;
+ DCOB2_N : in std_logic;
+
+ FRA2_P : in std_logic;
+ FRA2_N : in std_logic;
+ FRB2_P : in std_logic;
+ FRB2_N : in std_logic;
+
+----ADC3---------------------------------------------
+ AD31A_P : in std_logic;
+ AD31A_N : in std_logic;
+ AD31B_P : in std_logic;
+ AD31B_N : in std_logic;
+ AD32A_P : in std_logic;
+ AD32A_N : in std_logic;
+ AD32B_P : in std_logic;
+ AD32B_N : in std_logic;
+ AD33A_P : in std_logic;
+ AD33A_N : in std_logic;
+ AD33B_P : in std_logic;
+ AD33B_N : in std_logic;
+ AD34A_P : in std_logic;
+ AD34A_N : in std_logic;
+ AD34B_P : in std_logic;
+ AD34B_N : in std_logic;
+ AD35A_P : in std_logic;
+ AD35A_N : in std_logic;
+ AD35B_P : in std_logic;
+ AD35B_N : in std_logic;
+ AD36A_P : in std_logic;
+ AD36A_N : in std_logic;
+ AD36B_P : in std_logic;
+ AD36B_N : in std_logic;
+ AD37A_P : in std_logic;
+ AD37A_N : in std_logic;
+ AD37B_P : in std_logic;
+ AD37B_N : in std_logic;
+ AD38A_P : in std_logic;
+ AD38A_N : in std_logic;
+ AD38B_P : in std_logic;
+ AD38B_N : in std_logic;
+
+ DCOA3_P : in std_logic;
+ DCOA3_N : in std_logic;
+ DCOB3_P : in std_logic;
+ DCOB3_N : in std_logic;
+
+ FRA3_P : in std_logic;
+ FRA3_N : in std_logic;
+ FRB3_P : in std_logic;
+ FRB3_N : in std_logic;
+
+----ADC4---------------------------------------------
+ AD41A_P : in std_logic;
+ AD41A_N : in std_logic;
+ AD41B_P : in std_logic;
+ AD41B_N : in std_logic;
+ AD42A_P : in std_logic;
+ AD42A_N : in std_logic;
+ AD42B_P : in std_logic;
+ AD42B_N : in std_logic;
+ AD43A_P : in std_logic;
+ AD43A_N : in std_logic;
+ AD43B_P : in std_logic;
+ AD43B_N : in std_logic;
+ AD44A_P : in std_logic;
+ AD44A_N : in std_logic;
+ AD44B_P : in std_logic;
+ AD44B_N : in std_logic;
+ AD45A_P : in std_logic;
+ AD45A_N : in std_logic;
+ AD45B_P : in std_logic;
+ AD45B_N : in std_logic;
+ AD46A_P : in std_logic;
+ AD46A_N : in std_logic;
+ AD46B_P : in std_logic;
+ AD46B_N : in std_logic;
+ AD47A_P : in std_logic;
+ AD47A_N : in std_logic;
+ AD47B_P : in std_logic;
+ AD47B_N : in std_logic;
+ AD48A_P : in std_logic;
+ AD48A_N : in std_logic;
+ AD48B_P : in std_logic;
+ AD48B_N : in std_logic;
+
+ DCOA4_P : in std_logic;
+ DCOA4_N : in std_logic;
+ DCOB4_P : in std_logic;
+ DCOB4_N : in std_logic;
+
+ FRA4_P : in std_logic;
+ FRA4_N : in std_logic;
+ FRB4_P : in std_logic;
+ FRB4_N : in std_logic;
+ ADC_clk : out std_logic;
+ ADCs_ready : out std_logic;
+ adcdata : out array_adc_type
+ );
+end component;
+
+component AdcSerialProg is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ init : in std_logic;
+ clock_out : out std_logic;
+ dataA_in : in std_logic_vector(3 downto 0);
+ dataB_in : in std_logic_vector(3 downto 0);
+ data_out : out std_logic;
+ chipnselectA : out std_logic_vector(3 downto 0);
+ chipnselectB : out std_logic_vector(3 downto 0);
+ selREGS : in std_logic_vector(2 downto 0)
+ );
+end component;
+
+component FEE_gtxModule is
+ Port (
+ gtpClk_P : in std_logic;
+ gtpClk_N : in std_logic;
+ refclk_out : out std_logic;
+ sysClk : in std_logic;
+ asyncclk : in std_logic;
+ reset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+
+ txAsyncClk : in std_logic;
+ txAsyncData : in std_logic_vector(31 downto 0);
+ txAsyncDataWrite : in std_logic;
+ txAsyncFirstData : in std_logic;
+ txAsyncLastData : in std_logic;
+ txAsyncFifoFull : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxAsyncClk : in std_logic;
+ rxAsyncData : out std_logic_vector(31 downto 0);
+ rxAsyncFirstData : out std_logic;
+ rxAsyncLastData : out std_logic;
+ rxAsyncDataRead : in std_logic;
+ rxError : out std_logic;
+ rxAsyncDataOverflow : out std_logic;
+ rxAsyncDataPresent : out std_logic;
+ rxUsrClkdiv2 : out std_logic;
+ rxSodaClk : out std_logic;
+ rxSodaClk40 : out std_logic;
+ rxLocked : out std_logic;
+
+ gtpTxP0 : out std_logic;
+ gtpTxN0 : out std_logic;
+ gtpRxP0 : in std_logic;
+ gtpRxN0 : in std_logic;
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+ );
+end component;
+
+component gtx_common is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
+ SIM_QPLLREFCLK_SEL : bit_vector := "001"
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK1_IN : in std_logic;
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+);
+
+end component;
+
+component FEE_adc32_module is
+ generic (
+ NROFADCS : natural := NROFFEEADCS;
+ ADCBITS : natural := ADCBITS;
+ MWD_WIDTHBITS : natural := MWD_WIDTHBITS;
+ MWD2_WIDTHBITS : natural := MWD2_WIDTHBITS;
+ MWD_SCALEBITS : natural := MWD_SCALEBITS;
+ MWD2_SCALEBITS : natural := MWD2_SCALEBITS;
+ MWD_DOUBLEFILTER : boolean := MWD_DOUBLEFILTER;
+ MWD_PU_DOUBLEFILTER : boolean := MWD_PU_DOUBLEFILTER;
+ BASELINE_BWBITS : natural := BASELINE_BWBITS;
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
+ ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY;
+ CF_DELAYBITS : natural := CF_DELAYBITS;
+ MAXPILEUPHITS : natural := MAXPILEUPHITS;
+ IDIVMAXBITS : natural := IDIVMAXBITS;
+ INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS;
+ SECOND_FE_MODULE : boolean := SECOND_FE_MODULE
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable_data : in std_logic;
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+ ADCdata : in array_adc_type;
+ superburst_start : in std_logic;
+ superburst_received : in std_logic_vector(30 downto 0);
+ force_hit : in std_logic;
+ onesecondpulse : in std_logic;
+ rxNotInTable : in std_logic;
+ startupready : in std_logic;
+ request_init : in std_logic;
+ packet_in_data : in std_logic_vector (31 downto 0);
+ packet_in_present : in std_logic;
+ packet_in_read : out std_logic;
+ packet_out_data : out std_logic_vector(31 downto 0);
+ packet_out_first : out std_logic;
+ packet_out_last : out std_logic;
+ packet_out_write : out std_logic;
+ packet_out_inpipe : out std_logic;
+ packet_out_fifofull : in std_logic;
+ errorbyte_out : out std_logic_vector(7 downto 0);
+ errorbyte_in : in std_logic_vector(7 downto 0);
+ smaart_in : in std_logic;
+ smaart_out : out std_logic;
+ sysmon_data : in std_logic_vector(15 downto 0);
+ sysmon_reset : out std_logic;
+ sysmon_address : out std_logic_vector(6 downto 0);
+ sysmon_read : out std_logic;
+ second_module_zero : in std_logic;
+ enable_waveform : out std_logic;
+ compare_error : out std_logic
+ );
+end component;
+
+component FEE_receive_split is
+ port (
+ clock_in : in std_logic;
+ clock_local : in std_logic;
+ clock_remote : in std_logic;
+ reset : in std_logic;
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+ data_in : in std_logic_vector (31 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_present : in std_logic;
+ data_in_fifofull : out std_logic;
+ data_in_read : out std_logic;
+ data_local : out std_logic_vector(31 downto 0);
+ data_local_first : out std_logic;
+ data_local_last : out std_logic;
+ data_local_present : out std_logic;
+ data_local_read : in std_logic;
+ data_remote : out std_logic_vector(31 downto 0);
+ data_remote_first : out std_logic;
+ data_remote_last : out std_logic;
+ data_remote_present : out std_logic;
+ data_remote_read : in std_logic;
+ error : out std_logic
+ );
+end component;
+
+component FEE_transmit_combine is
+ port (
+ clock_local : in std_logic;
+ clock_remote : in std_logic;
+ clock_out : in std_logic;
+ reset : in std_logic;
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+ enable_waveform : in std_logic;
+ data_local : in std_logic_vector (31 downto 0);
+ data_local_first : in std_logic;
+ data_local_last : in std_logic;
+ data_local_write : in std_logic;
+ data_local_inpipe : in std_logic;
+ data_local_fifofull : out std_logic;
+ data_remote : in std_logic_vector(31 downto 0);
+ data_remote_first : in std_logic;
+ data_remote_last : in std_logic;
+ data_remote_write : in std_logic;
+ data_remote_inpipe : in std_logic;
+ data_remote_fifofull : out std_logic;
+ data_remote_almostfull : out std_logic;
+ data_out : out std_logic_vector(31 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_fifofull : in std_logic;
+ error : out std_logic
+ );
+end component;
+
+component FEE_soda_client is
+ port(
+ SYSCLK : in std_logic; -- fabric clock
+ SODACLK : in std_logic; -- recovered clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+
+ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0);
+ RX_DLM_IN : in std_logic;
+ TX_DLM_OUT : out std_logic;
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0);
+ TX_DLM_PREVIEW_OUT : out std_logic := '0';
+ LINK_PHASE_IN : in std_logic;
+
+ START_OF_SUPERBURST : out std_logic; -- PS
+ SUPER_BURST_NR : out std_logic_vector(30 downto 0); -- PS
+ SODA_CMD_VALID : out std_logic; -- PS
+ SODA_CMD_WORD : out std_logic_vector(30 downto 0); -- PS
+
+ SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
+ SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
+ SODA_READ_IN : in std_logic := '0';
+ SODA_WRITE_IN : in std_logic := '0';
+ SODA_ACK_OUT : out std_logic := '0';
+ LEDS_OUT : out std_logic_vector(3 downto 0);
+ LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
+ );
+end component;
+
+component SystemMonitorModule is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ address : in std_logic_vector(6 downto 0);
+ data_write : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ data_read : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ alarms : out std_logic_vector(7 downto 0)
+ );
+end component;
+
+component reboot is
+ port (
+ TRIGGER : in std_logic;
+ SYSCLK : in std_logic
+ );
+end component;
+
+component sem_module is
+ port (
+ clk : in std_logic;
+ status_heartbeat : out std_logic;
+ status_initialization : out std_logic;
+ status_observation : out std_logic;
+ status_correction : out std_logic;
+ status_classification : out std_logic;
+ status_injection : out std_logic;
+ status_essential : out std_logic;
+ status_uncorrectable : out std_logic
+ );
+end component;
+
+component aurora_dual_module is
+ port (
+ stable_clock : in std_logic; -- 80MHz
+ reset : in std_logic;
+ user_clock : out std_logic;
+ tx_data : in std_logic_vector(31 downto 0);
+ tx_first : in std_logic;
+ tx_last : in std_logic;
+ tx_write : in std_logic;
+ tx_allowed : out std_logic;
+ tx_inpipe : in std_logic;
+ rx_data : out std_logic_vector(31 downto 0);
+ rx_first : out std_logic;
+ rx_last : out std_logic;
+ rx_write : out std_logic;
+ rx_almostfull : in std_logic;
+ rx_inpipe : out std_logic;
+ locked : out std_logic;
+ error : out std_logic;
+ RXP : in std_logic_vector(0 to 1);
+ RXN : in std_logic_vector(0 to 1);
+ TXP : out std_logic_vector(0 to 1);
+ TXN : out std_logic_vector(0 to 1);
+ GTXQ0_P : in std_logic;
+ GTXQ0_N : in std_logic;
+ gt0_refclk_in : in std_logic;
+ gt0_qplllock_in : in std_logic;
+ gt0_qpllrefclklost_in : in std_logic;
+ gt0_qpllreset_out : out std_logic;
+ GT_QPLLOUTCLK_IN : in std_logic;
+ GT_QPLLOUTREFCLK_IN : in std_logic
+ );
+end component;
+
+component FEE_fiforead2write is
+ generic(
+ BITS : integer := 32
+ );
+ port(
+ clock : in std_logic;
+ data_in : in std_logic_vector(BITS-1 downto 0);
+ data_in_empty : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(BITS-1 downto 0);
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic
+ );
+end component;
+
+component posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in :in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+component vio_debug is
+ Port (
+ clk : in STD_LOGIC;
+ probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
+ probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
+ probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 )
+ );
+end component;
+
+component vio36
+ Port (
+ clk : IN STD_LOGIC;
+ probe_out0 : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
+ );
+end component;
+
+type adcdata_type is array(0 to 7) of std_logic_vector(15 downto 0);
+type AdcDataOut_type is array(0 to 3) of std_logic_vector((32*((4/2)*2))-1 downto 0);
+type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0);
+
+-- clocking
+signal clock_S : std_logic; -- main clock, frequency equal to ADC clock, PLL reference during boot
+signal clock40MHz_S : std_logic;
+signal clock100MHz_S : std_logic;
+signal clock160MHz_S : std_logic;
+signal clock200MHz_S : std_logic;
+signal gclk_S : std_logic;
+signal ST_CLK_S : std_logic;
+signal async_clock_S : std_logic;
+signal RCV_CLK_S : std_logic;
+signal ADC_clk_S : std_logic;
+signal onesecondpulse_S : std_logic;
+
+-- resetting
+signal IcontrolPLL_S : std_logic := '0';
+signal IcontrolPLLnot_S : std_logic := '1';
+signal clockmodule_locked_S : std_logic;
+signal reset_S : std_logic := '0';
+signal reset_FEE_S : std_logic;
+signal reset_FEE_ADCclk_S : std_logic := '0';
+signal reset_rxSodaClk_S : std_logic;
+signal startupready_S : std_logic;
+signal request_init_S : std_logic := '0';
+signal GEO_S : std_logic := '0';
+signal GEObuf_S : std_logic := '0';
+signal T_CTRL_S : std_logic := '0';
+signal S_CTRL_S : std_logic := '0';
+signal enable_waveform_S : std_logic;
+
+-- PLL
+signal CLKu_S : std_logic;
+signal DATAu_S : std_logic;
+signal LEu_S : std_logic;
+signal RDu_S : std_logic;
+signal SYNC_S : std_logic;
+signal pll_boot_s : std_logic;
+signal pll_boot1_s : std_logic;
+signal PLL_booting_busy_S : std_logic;
+
+signal PLLuseGTXclock_S : std_logic;
+signal PLLuseGTXclock0_S : std_logic;
+signal PLLuseGTXclock1_S : std_logic;
+signal clockswitch_locked_S : std_logic;
+signal clockswitch_reset_S : std_logic;
+
+
+-- system monitor
+signal sysmon_data_S : std_logic_vector(15 downto 0);
+signal sysmon_reset_S : std_logic;
+signal sysmon_address_S : std_logic_vector(6 downto 0);
+signal sysmon_read_S : std_logic;
+
+signal TEMP_OUT_S : std_logic := '0';
+signal TEMP_IN_S : std_logic := '0';
+
+-- SODA
+signal EnableDataTaking_S : std_logic := '0';
+signal DisableDataTaking_S : std_logic := '0';
+signal enable_data_S : std_logic := '0';
+signal DataTaking_enabled_out_S : std_logic := '0';
+signal DataTaking_enabled_in_S : std_logic := '0';
+signal SODA_cmd_valid_S : std_logic := '0';
+signal SODA_cmd_word_S : std_logic_vector(30 downto 0);
+signal superburst_out0_S : std_logic_vector(30 downto 0);
+signal superburst_out_S : std_logic_vector(15 downto 0);
+signal superburst_startout0_S : std_logic;
+signal superburst_startout_S : std_logic;
+signal superburst0_in_S : std_logic_vector(15 downto 0);
+signal superburst_in_S : std_logic_vector(30 downto 0);
+signal superburst_start_S : std_logic;
+signal superburst_startin0_S : std_logic;
+signal superburst_startin0sync_S : std_logic;
+signal clear_superburst_startin_S : std_logic;
+signal superburst_startin1_S : std_logic;
+signal superburst_startin2_S : std_logic;
+signal superburst_startin3_S : std_logic;
+
+signal force_hit_S : std_logic;
+signal force_hit_out0_S : std_logic;
+signal force_hit_out_S : std_logic;
+
+-- ADCs
+signal SCK_S : std_logic;
+signal SDI_S : std_logic;
+signal CSA_S : std_logic_vector(1 to 4);
+signal CSB_S : std_logic_vector(1 to 4);
+signal SDOA_S : std_logic_vector(1 to 4);
+signal SDOB_S : std_logic_vector(1 to 4);
+signal ADCchip_init_S : std_logic;
+signal ADCchip_init1_S : std_logic;
+signal reset_ADCs_S : std_logic;
+signal reset_ADCs0_S : std_logic;
+signal reset_ADCs1_S : std_logic;
+signal adcdata_S : array_adc_type;
+signal ADCs_enable_S : std_logic;
+signal ADCs_ready_S : std_logic;
+
+-- gtx
+signal GTX_reset_S : std_logic;
+signal LOS_S : std_logic;
+signal LOS_GEO_S : std_logic;
+signal rxUsrClkdiv2_S : std_logic;
+signal rxSodaClk_S : std_logic;
+signal rxSodaClk40_S : std_logic;
+signal rxSodaClk80_S : std_logic;
+signal TX_DLM_S : std_logic;
+signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);
+signal RX_DLM_S : std_logic;
+signal RX_DLM_WORD_S : std_logic_vector(7 downto 0);
+signal disable_GTX_reset_S : std_logic := '0';
+signal GTX_txLocked_S : std_logic;
+signal GTX_txLocked_GEO_S : std_logic;
+signal GTX_rxLocked_S : std_logic;
+signal GTX_rxLocked_GEO_S : std_logic;
+signal GTX_rxclockLocked_S : std_logic;
+signal GTX_Error_S : std_logic;
+signal GTX_Error_GEO_S : std_logic;
+
+-- gtx common
+signal refclk_S : std_logic;
+signal gt0_qplllock_S : std_logic;
+signal gt0_qplloutclk_S : std_logic;
+signal gt0_qplloutrefclk_S : std_logic;
+signal gt0_qpllrefclklost_S : std_logic;
+signal gt0_qpllreset_S : std_logic;
+
+-- FE output data
+signal FE_in_data_S : std_logic_vector(31 downto 0);
+signal FE_out_data_S : std_logic_vector(31 downto 0);
+signal FE_in_present_S : std_logic;
+signal FE_in_read_S : std_logic;
+signal FE_out_first_S : std_logic;
+signal FE_out_last_S : std_logic;
+signal FE_out_write_S : std_logic;
+signal FE_out_inpipe_S : std_logic;
+signal FE_out_fifofull_S : std_logic;
+
+-- fiber data
+signal packet_out_clock_S : std_logic;
+signal packet_in_data_S : std_logic_vector(31 downto 0);
+signal packet_out_data_S : std_logic_vector(31 downto 0);
+signal packet_in_present_S : std_logic;
+signal packet_in_read_S : std_logic;
+signal packet_in_first_S : std_logic;
+signal packet_in_last_S : std_logic;
+signal packet_out_first_S : std_logic;
+signal packet_out_last_S : std_logic;
+signal packet_out_write_S : std_logic;
+signal packet_out_fifofull_S : std_logic;
+signal rxNotInTable_S : std_logic;
+signal errorbyte_S : std_logic_vector(7 downto 0) := (others => '0');
+
+-- SEM
+signal doreboot_S : std_logic := '0';
+signal status_heartbeat_S : std_logic;
+signal status_initialization_S : std_logic;
+signal status_observation_S : std_logic;
+signal status_correction_S : std_logic;
+signal status_classification_S : std_logic;
+signal status_injection_S : std_logic;
+signal status_essential_S : std_logic;
+signal status_uncorrectable_S : std_logic;
+
+-- interconnection
+signal aurora_clock_S : std_logic;
+signal aurora_tx_data_S : std_logic_vector(31 downto 0);
+signal aurora_tx_allowed_S : std_logic;
+signal aurora_tx_first_S : std_logic;
+signal aurora_tx_last_S : std_logic;
+signal aurora_tx_write_S : std_logic;
+signal aurora_tx_inpipe_S : std_logic;
+signal aurora_rx_data_S : std_logic_vector(31 downto 0);
+signal aurora_rx_first_S : std_logic;
+signal aurora_rx_last_S : std_logic;
+signal aurora_rx_write_S : std_logic;
+signal aurora_rx_almostfull_S : std_logic;
+signal aurora_rx_inpipe_S : std_logic;
+signal aurora_locked_S : std_logic;
+signal aurora_error_S : std_logic;
+
+-- split received data
+signal split_in_S : std_logic_vector(31 downto 0);
+signal split_in_first_S : std_logic;
+signal split_in_last_S : std_logic;
+signal split_in_present_S : std_logic;
+signal split_in_fifofull_S : std_logic;
+signal split_in_read_S : std_logic;
+signal split_local_S : std_logic_vector(31 downto 0);
+signal split_local_first_S : std_logic;
+signal split_local_last_S : std_logic;
+signal split_local_present_S : std_logic;
+signal split_local_read_S : std_logic;
+signal split_remote_S : std_logic_vector(31 downto 0);
+signal split_remote_first_S : std_logic;
+signal split_remote_last_S : std_logic;
+signal split_remote_present_S : std_logic;
+signal split_remote_read_S : std_logic;
+signal split_error_S : std_logic;
+
+-- combine FE data
+signal comb_local_S : std_logic_vector(31 downto 0);
+signal comb_local_first_S : std_logic;
+signal comb_local_last_S : std_logic;
+signal comb_local_write_S : std_logic;
+signal comb_local_inpipe_S : std_logic;
+signal comb_local_fifofull_S : std_logic;
+signal comb_remote_S : std_logic_vector(31 downto 0);
+signal comb_remote_first_S : std_logic;
+signal comb_remote_last_S : std_logic;
+signal comb_remote_write_S : std_logic;
+signal comb_remote_inpipe_S : std_logic;
+signal comb_remote_fifofull_S : std_logic;
+signal comb_remote_almostfull_S : std_logic;
+signal comb_out_S : std_logic_vector(31 downto 0);
+signal comb_out_first_S : std_logic;
+signal comb_out_last_S : std_logic;
+signal comb_out_write_S : std_logic;
+signal comb_out_inpipe_S : std_logic;
+signal comb_out_fifofull_S : std_logic;
+signal comb_error_S : std_logic;
+
+signal split_remote_wr_S : std_logic_vector(31 downto 0);
+signal split_remote_wr_first_S : std_logic;
+signal split_remote_wr_last_S : std_logic;
+signal split_remote_wr_write_S : std_logic;
+signal split_remote_wr_allowed_S : std_logic;
+signal split_remote_fifoempty_S : std_logic;
+
+signal gt0_qpllreset1_S : std_logic;
+signal gt0_qpllreset2_S : std_logic;
+
+-- test compare feature extraction results
+signal vioword_S : std_logic_vector(35 downto 0) := (others => '0');
+signal compare_error_S : std_logic;
+signal compare_error1_S : std_logic;
+
+attribute keep : string;
+attribute keep of clock_S : signal is "TRUE";
+attribute keep of ADC_clk_S : signal is "TRUE";
+--attribute keep of clock100MHz_S : signal is "TRUE";
+attribute keep of clock200MHz_S : signal is "TRUE";
+attribute keep of async_clock_S : signal is "TRUE";
+
+-- test
+
+-- signal aurora1_txclock_Sdiv10_S : std_logic;
+-- signal aurora1_rxclock_Sdiv10_S : std_logic;
+-- signal aurora2_txclock_Sdiv10_S : std_logic;
+-- signal aurora2_rxclock_Sdiv10_S : std_logic;
+
+--signal vio_LMK04806_wr0_S : std_logic;
+--signal vio_LMK04806_wr_S : std_logic;
+signal debug_reset_S : std_logic := '0';
+
+signal debug_packet_out_data_S : std_logic_vector(31 downto 0);
+signal debug_packet_out_first_S : std_logic;
+signal debug_packet_out_last_S : std_logic;
+
+attribute mark_debug : string;
+-- attribute mark_debug of GEO_S : signal is "true";
+-- attribute mark_debug of T_CTRL_S : signal is "true";
+-- attribute mark_debug of S_CTRL_S : signal is "true";
+-- attribute mark_debug of reset_S : signal is "true";
+-- attribute mark_debug of clockmodule_locked_S : signal is "true";
+-- attribute mark_debug of IcontrolPLL_S : signal is "true";
+-- attribute mark_debug of ADCchip_init_S : signal is "true";
+-- attribute mark_debug of PLL_boot_S : signal is "true";
+-- attribute mark_debug of PLL_booting_busy_S : signal is "true";
+-- attribute mark_debug of GTX_reset_S : signal is "true";
+-- attribute mark_debug of LOS_GEO_S : signal is "true";
+-- attribute mark_debug of GTX_rxclockLocked_S : signal is "true";
+-- attribute mark_debug of GTX_txLocked_GEO_S : signal is "true";
+-- attribute mark_debug of GTX_Error_GEO_S : signal is "true";
+-- attribute mark_debug of PLLuseGTXclock_S : signal is "true";
+-- attribute mark_debug of PLLuseGTXclock0_S : signal is "true";
+-- attribute mark_debug of reset_ADCs_S : signal is "true";
+-- attribute mark_debug of ADCs_ready_S : signal is "true";
+-- attribute mark_debug of reset_FEE_S : signal is "true";
+-- attribute mark_debug of startupready_S : signal is "true";
+-- attribute mark_debug of reset_rxSodaClk_S : signal is "true";
+
+-- attribute mark_debug of status_heartbeat_S : signal is "true";
+-- attribute mark_debug of status_initialization_S : signal is "true";
+-- attribute mark_debug of status_observation_S : signal is "true";
+-- attribute mark_debug of status_correction_S : signal is "true";
+-- attribute mark_debug of status_classification_S : signal is "true";
+-- attribute mark_debug of status_injection_S : signal is "true";
+-- attribute mark_debug of status_essential_S : signal is "true";
+-- attribute mark_debug of status_uncorrectable_S : signal is "true";
+-- attribute mark_debug of doreboot_S : signal is "true";
+
+-- attribute mark_debug of LOS : signal is "true";
+-- attribute mark_debug of INTCOMC1_P : signal is "true";
+-- attribute mark_debug of INTCOMC1_N : signal is "true";
+-- attribute mark_debug of INTCOMC2_P : signal is "true";
+-- attribute mark_debug of INTCOMC2_N : signal is "true";
+
+
+-- attribute mark_debug of FE_in_data_S : signal is "true";
+-- attribute mark_debug of FE_in_present_S : signal is "true";
+-- attribute mark_debug of FE_in_read_S : signal is "true";
+-- attribute mark_debug of FE_out_data_S : signal is "true";
+-- attribute mark_debug of FE_out_first_S : signal is "true";
+-- attribute mark_debug of FE_out_last_S : signal is "true";
+-- attribute mark_debug of FE_out_write_S : signal is "true";
+-- attribute mark_debug of FE_out_inpipe_S : signal is "true";
+-- attribute mark_debug of FE_out_fifofull_S : signal is "true";
+
+-- attribute mark_debug of aurora_tx_data_S : signal is "true";
+-- attribute mark_debug of aurora_tx_write_S : signal is "true";
+-- attribute mark_debug of aurora_tx_allowed_S : signal is "true";
+-- attribute mark_debug of aurora_rx_data_S : signal is "true";
+-- attribute mark_debug of aurora_rx_write_S : signal is "true";
+-- attribute mark_debug of aurora_locked_S : signal is "true";
+-- attribute mark_debug of aurora_error_S : signal is "true";
+
+-- attribute mark_debug of packet_in_data_S : signal is "true";
+-- attribute mark_debug of packet_in_first_S : signal is "true";
+-- attribute mark_debug of packet_in_last_S : signal is "true";
+-- attribute mark_debug of packet_in_read_S : signal is "true";
+-- attribute mark_debug of packet_in_present_S : signal is "true";
+-- attribute mark_debug of packet_out_data_S : signal is "true";
+-- attribute mark_debug of packet_out_write_S : signal is "true";
+-- attribute mark_debug of packet_out_first_S : signal is "true";
+-- attribute mark_debug of packet_out_last_S : signal is "true";
+-- attribute mark_debug of packet_out_fifofull_S : signal is "true";
+
+--attribute mark_debug of debug_packet_out_data_S : signal is "true";
+--attribute mark_debug of debug_packet_out_first_S : signal is "true";
+--attribute mark_debug of debug_packet_out_last_S : signal is "true";
+-- attribute mark_debug of superburst_out_S : signal is "true";
+-- attribute mark_debug of superburst_startout0_S : signal is "true";
+-- attribute mark_debug of superburst_startout_S : signal is "true";
+-- attribute mark_debug of superburst0_in_S : signal is "true";
+-- attribute mark_debug of superburst_in_S : signal is "true";
+-- attribute mark_debug of superburst_start_S : signal is "true";
+-- attribute mark_debug of superburst_startin0_S : signal is "true";
+-- attribute mark_debug of superburst_startin0sync_S : signal is "true";
+-- attribute mark_debug of clear_superburst_startin_S : signal is "true";
+-- attribute mark_debug of superburst_startin1_S : signal is "true";
+-- attribute mark_debug of superburst_startin2_S : signal is "true";
+-- attribute mark_debug of superburst_startin3_S : signal is "true";
+
+begin
+
+-- IO buffers ------------------------------------------------
+T_CTRL_inst : OBUF port map(O => T_CTRL,I => T_CTRL_S);
+S_CTRL_inst : IBUF port map (O => S_CTRL_S, I => S_CTRL);
+GEO_inst : IBUF port map (O => GEObuf_S, I => GEO);
+RDu_inst : IBUF port map (O => RDu_S, I => RDu);
+
+GEO_S <= GEObuf_S when SWAPFPGAS=false else not GEObuf_S;
+
+
+--IOBUF1 : IOBUF port map (O => PLLuseGTXclock0_S, IO => INTCOMC1_P, I => PLLuseGTXclock_S, T => IcontrolPLLnot_S);
+--IOBUF2 : IOBUF port map (O => superburst_start0_S, IO => INTCOMC1_N, I => superburst_startout_S, T => IcontrolPLLnot_S);
+--IOBUF3 : IOBUF port map (O => DataTaking_enabled_in_S, IO => INTCOMC2_N, I => DataTaking_enabled_out_S, T => IcontrolPLLnot_S);
+--IOBUF4 : IOBUF port map (O => open, IO => CLKu, I => CLKu_S, T => IcontrolPLLnot_S);
+--IOBUF5 : IOBUF port map (O => open, IO => DATAu, I => DATAu_S, T => IcontrolPLLnot_S);
+--IOBUF6 : IOBUF port map (O => open, IO => LEu, I => LEu_S, T => IcontrolPLLnot_S);
+
+INTCOMC1_P <= PLLuseGTXclock_S when IcontrolPLLnot_S='0' else 'Z';
+PLLuseGTXclock0_S <= INTCOMC1_P;
+
+INTCOMC1_N <= superburst_startout_S when IcontrolPLLnot_S='0' else 'Z';
+superburst_startin0_S <= INTCOMC1_N;
+
+INTCOMC2_N <= DataTaking_enabled_out_S when IcontrolPLLnot_S='0' else 'Z';
+DataTaking_enabled_in_S <= INTCOMC2_N;
+
+INTCOMC2_P <= force_hit_out_S when IcontrolPLLnot_S='0' else 'Z';
+force_hit_S <= INTCOMC2_P;
+
+CLKu <= CLKu_S when IcontrolPLLnot_S='0' else 'Z';
+DATAu <= DATAu_S when IcontrolPLLnot_S='0' else 'Z';
+LEu <= LEu_S when IcontrolPLLnot_S='0' else 'Z';
+SYNC <= SYNC_S when IcontrolPLLnot_S='0' else 'Z';
+
+JTAG_IOBUF1 : IOBUF port map (
+ O => open,
+ IO => JTAG_OUT1_TCK_F,
+ I => '0',
+ T => '1'
+ );
+JTAG_IOBUF2 : IOBUF port map (
+ O => open,
+ IO => JTAG_OUT1_TDI_F,
+ I => '0',
+ T => '1'
+ );
+JTAG_IOBUF3 : IOBUF port map (
+ O => open,
+ IO => JTAG_OUT1_TDO_F,
+ I => '0',
+ T => '1'
+ );
+JTAG_IOBUF4 : IOBUF port map (
+ O => open,
+ IO => JTAG_OUT1_TMS_F,
+ I => '0',
+ T => '1'
+ );
+
+TEMP_OUT_S <= TEMP_OUT;
+TEMP_IN <= TEMP_IN_S;
+
+
+--SCK <= SCK_S;
+--SDI <= SDI_S;
+--CSA <= CSA_S;
+--CSB <= CSB_S;
+SDOA_S <= SDOA;
+SDOB_S <= SDOB;
+
+SCK_inst : OBUF port map(O => SCK,I => SCK_S);
+SDI_inst : OBUF port map(O => SDI,I => SDI_S);
+CSA1_inst : OBUF port map(O => CSA(1),I => CSA_S(1));
+CSA2_inst : OBUF port map(O => CSA(2),I => CSA_S(2));
+CSA3_inst : OBUF port map(O => CSA(3),I => CSA_S(3));
+CSA4_inst : OBUF port map(O => CSA(4),I => CSA_S(4));
+CSB1_inst : OBUF port map(O => CSB(1),I => CSB_S(1));
+CSB2_inst : OBUF port map(O => CSB(2),I => CSB_S(2));
+CSB3_inst : OBUF port map(O => CSB(3),I => CSB_S(3));
+CSB4_inst : OBUF port map(O => CSB(4),I => CSB_S(4));
+--
+--GEN_SDO_parallel: if ADC_PARALLELINIT=true generate
+-- SDOA1_inst : OBUF port map (O => SDOA(1), I => SDOA_S(1));
+-- SDOA2_inst : OBUF port map (O => SDOA(2), I => SDOA_S(2));
+-- SDOA3_inst : OBUF port map (O => SDOA(3), I => SDOA_S(3));
+-- SDOA4_inst : OBUF port map (O => SDOA(4), I => SDOA_S(4));
+-- SDOB1_inst : OBUF port map (O => SDOB(1), I => SDOB_S(1));
+-- SDOB2_inst : OBUF port map (O => SDOB(2), I => SDOB_S(2));
+-- SDOB3_inst : OBUF port map (O => SDOB(3), I => SDOB_S(3));
+-- SDOB4_inst : OBUF port map (O => SDOB(4), I => SDOB_S(4));
+--end generate;
+--GEN_SDO_serial: if ADC_PARALLELINIT=false generate
+-- SDOA1_inst : IBUF port map (O => SDOA_S(1), I => SDOA(1));
+-- SDOA2_inst : IBUF port map (O => SDOA_S(2), I => SDOA(2));
+-- SDOA3_inst : IBUF port map (O => SDOA_S(3), I => SDOA(3));
+-- SDOA4_inst : IBUF port map (O => SDOA_S(4), I => SDOA(4));
+-- SDOB1_inst : IBUF port map (O => SDOB_S(1), I => SDOB(1));
+-- SDOB2_inst : IBUF port map (O => SDOB_S(2), I => SDOB(2));
+-- SDOB3_inst : IBUF port map (O => SDOB_S(3), I => SDOB(3));
+-- SDOB4_inst : IBUF port map (O => SDOB_S(4), I => SDOB(4));
+--end generate;
+
+
+--GEN_SDO_parallel: if ADC_PARALLELINIT=true generate
+-- SDOA1_inst : IOBUF port map (O => open, IO => SDOA(1), I => SDOA_S(1), T => '0');
+-- SDOA2_inst : IOBUF port map (O => open, IO => SDOA(2), I => SDOA_S(2), T => '0');
+-- SDOA3_inst : IOBUF port map (O => open, IO => SDOA(3), I => SDOA_S(3), T => '0');
+-- SDOA4_inst : IOBUF port map (O => open, IO => SDOA(4), I => SDOA_S(4), T => '0');
+-- SDOB1_inst : IOBUF port map (O => open, IO => SDOB(1), I => SDOB_S(1), T => '0');
+-- SDOB2_inst : IOBUF port map (O => open, IO => SDOB(2), I => SDOB_S(2), T => '0');
+-- SDOB3_inst : IOBUF port map (O => open, IO => SDOB(3), I => SDOB_S(3), T => '0');
+-- SDOB4_inst : IOBUF port map (O => open, IO => SDOB(4), I => SDOB_S(4), T => '0');
+--end generate;
+--GEN_SDO_serial: if ADC_PARALLELINIT=false generate
+-- SDOA1_inst : IOBUF port map (O => SDOA_S(1), IO => SDOA(1), I => '0', T => '1');
+-- SDOA2_inst : IOBUF port map (O => SDOA_S(2), IO => SDOA(2), I => '0', T => '1');
+-- SDOA3_inst : IOBUF port map (O => SDOA_S(3), IO => SDOA(3), I => '0', T => '1');
+-- SDOA4_inst : IOBUF port map (O => SDOA_S(4), IO => SDOA(4), I => '0', T => '1');
+-- SDOB1_inst : IOBUF port map (O => SDOB_S(1), IO => SDOB(1), I => '0', T => '1');
+-- SDOB2_inst : IOBUF port map (O => SDOB_S(2), IO => SDOB(2), I => '0', T => '1');
+-- SDOB3_inst : IOBUF port map (O => SDOB_S(3), IO => SDOB(3), I => '0', T => '1');
+-- SDOB4_inst : IOBUF port map (O => SDOB_S(4), IO => SDOB(4), I => '0', T => '1');
+--end generate;
+
+
+-- process(clock_S,clockmodule_locked_S,GEO_S)
+-- variable T_CTRL_count_V : integer range 0 to 3 := 0;
+-- begin
+ -- if (clockmodule_locked_S='0') then
+ -- T_CTRL_S <= GEO_S;
+ -- elsif (rising_edge(clock_S)) then
+ -- if GEO_S='0' then
+ -- if (FPGA_IN_CONTROL='0') then
+ -- if (S_CTRL_S='0') and (T_CTRL_count_V=3) then -- wrong value
+ -- T_CTRL_S <= not T_CTRL_S;
+ -- T_CTRL_count_V := 0;
+ -- elsif T_CTRL_count_V/=3 then
+ -- T_CTRL_count_V := T_CTRL_count_V+1;
+ -- end if;
+ -- else
+ -- T_CTRL_S <= GEO_S;
+ -- end if;
+ -- else
+ -- if (FPGA_IN_CONTROL='1') then
+ -- if (S_CTRL_S='1') and (T_CTRL_count_V=3) then -- wrong value
+ -- T_CTRL_S <= not T_CTRL_S;
+ -- T_CTRL_count_V := 0;
+ -- elsif T_CTRL_count_V/=3 then
+ -- T_CTRL_count_V := T_CTRL_count_V+1;
+ -- end if;
+ -- else
+ -- T_CTRL_S <= GEO_S;
+ -- end if;
+ -- end if;
+ -- end if;
+-- end process;
+T_CTRL_S <= '0';
+
+--IcontrolPLL_S <= '1' when (GEO='0') and (S_CTRL='1') else '0';
+--IcontrolPLL_S <= '1' when ((GEO_S='0') and (S_CTRL_S='1')) or ((GEO_S='1') and (S_CTRL_S='0')) else '0';
+
+IcontrolPLL_S <= '1' when (GEO_S='0') else '0';
+IcontrolPLLnot_S <= '0' when (GEO_S='0') else '1';
+
+-- process(clock_S,clockmodule_locked_S)
+-- begin
+ -- if clockmodule_locked_S='0' then
+ -- IcontrolPLLnot_S <= '1';
+ -- elsif (rising_edge(clock_S)) then
+ -- IcontrolPLLnot_S <= not IcontrolPLL_S;
+ -- end if;
+-- end process;
+
+-- main reset -----------------------------------------------
+process(clock_S,clockmodule_locked_S,debug_reset_S)
+variable S_CTRL_V : std_logic := '0';
+variable count_V : std_logic_vector(5 downto 0) := (others => '0');
+begin
+ if (clockmodule_locked_S='0') or (debug_reset_S='1') then
+ reset_S <= '1';
+ count_V := (others => '0');
+ elsif (rising_edge(clock_S)) then
+ if S_CTRL_V/=S_CTRL_S then
+ reset_S <= '1';
+ count_V := (others => '0');
+ else
+ if (count_V(count_V'left)='1') then
+ reset_S <= '0';
+ else
+ count_V := count_V+1;
+ reset_S <= '1';
+ end if;
+ end if;
+ S_CTRL_V := S_CTRL_S;
+ end if;
+end process;
+
+
+-- main clock -----------------------------------------------
+
+clockmodule100Mto80Ma: clockmodule100to80M port map(
+ CLK_IN1 => SYS_CLK,
+ CLK_OUT1 => clock40MHz_S,
+ CLK_OUT2 => clock_S, -- 80MHz
+ CLK_OUT3 => clock100MHz_S,
+ CLK_OUT4 => clock200MHz_S,
+ CLK_OUT5 => async_clock_S,
+ CLK_OUT6 => clock160MHz_S,
+ RESET => '0',
+ LOCKED => clockmodule_locked_S);
+
+sysclk_buf : IBUFGDS
+ generic map(
+ IOSTANDARD => "LVDS"
+ )
+ port map (
+ I => GCLK_P,
+ IB => GCLK_N,
+ O => gclk_S
+ );
+
+--gclk_S <= GCLK_P; -- when GEO_S='0' else clock_S; --// assign fixed clock to gclk due to hardware error?
+
+
+
+-- clock to external PLL LMK04806 -------------------------------------
+
+
+select_RCV_CLK : BUFGMUX
+ generic map (
+ CLK_SEL_TYPE => "ASYNC" --//ASYNC
+ )
+ port map( --
+ O => RCV_CLK_S,
+ I0 => clock_S, -- clock40MHz_S, -- clock_S,
+ I1 => rxSodaClk80_S, --clock40MHz_S, -- clock_S, -- rxSodaClk40_S,
+ S => PLLuseGTXclock1_S);
+PLLuseGTXclock1_S <= PLLuseGTXclock_S when IcontrolPLLnot_S='0' else '0';
+
+clockmodule40Mto80M1: clockmodule40Mto80M port map(
+ CLK_IN1 => rxSodaClk40_S,
+ CLK_OUT1 => open,
+ CLK_OUT2 => rxSodaClk80_S, -- RCV_CLK_S,
+ RESET => IcontrolPLLnot_S,
+ LOCKED => clockswitch_locked_S);
+
+process(clock_S,reset_S)
+variable GTX_rxLocked_V : std_logic;
+variable timer_V : std_logic_vector(3 downto 0);
+begin
+ if reset_S='1' then
+ GTX_rxclockLocked_S <= '0';
+ timer_V := (others => '0');
+ elsif (rising_edge(clock_S)) then
+ if ((GTX_rxLocked_GEO_S='1') and (GTX_rxLocked_V='0')) then
+ timer_V := (others => '0');
+ GTX_rxclockLocked_S <= '0';
+ else
+ if timer_V(timer_V'left)='0' then
+ timer_V := timer_V+1;
+ GTX_rxclockLocked_S <= '0';
+ else
+ if (GTX_rxLocked_GEO_S='1') and ((clockswitch_locked_S='1') or (IcontrolPLLnot_S='1')) then
+ GTX_rxclockLocked_S <= '1';
+ else
+ GTX_rxclockLocked_S <= '0';
+ end if;
+ end if;
+ end if;
+ GTX_rxLocked_V := GTX_rxLocked_GEO_S;
+ end if;
+end process;
+
+--sends clock to PLL
+OBUFDS_inst : OBUFDS
+ generic map(
+ IOSTANDARD => "LVDS_25")
+ port map(
+ O => RCV_CLK_P,
+ OB => RCV_CLK_N,
+ I => RCV_CLK_S);
+
+
+-- external PLL LMK04806 -------------------------------------
+LMK04806_1: LMK04806 port map(
+ clock => clock_S,
+ reset => reset_S,
+ CLKu => CLKu_S,
+ DATAu => DATAu_S,
+ LEu => LEu_S,
+ RDu => RDu_S,
+ SYNC => SYNC_S,
+ boot_PLL => PLL_boot_S,
+ booting => PLL_booting_busy_S);
+PLL_boot1_S <= '1' when (PLL_boot_S='1') else '0';
+
+SystemMonitorModule1: SystemMonitorModule port map(
+ clock => ADC_clk_S,
+ reset => sysmon_reset_S,
+ address => sysmon_address_S,
+ data_write => '0',
+ data_in => (others => '0'),
+ data_read => sysmon_read_S,
+ data_out => sysmon_data_S,
+ alarms => open);
+
+-- startup ----------------------------------------------------
+FEE_startup1: FEE_startup port map(
+ clock => clock_S,
+ ADCclock => ADC_clk_S,
+ clock_from_PLL => gclk_S,
+ reset => reset_S,
+ GEO => GEO_S,
+ IcontrolPLL => IcontrolPLL_S,
+ ADCchip_init => ADCchip_init_S,
+ PLL_init => PLL_boot_S,
+ PLL_booting => PLL_booting_busy_S,
+ GTX_reset => GTX_reset_S,
+ GTX_LOS => LOS_GEO_S,
+ GTX_rxLocked => GTX_rxclockLocked_S, --GTX_rxLocked_S,
+ GTX_txLocked => GTX_txLocked_GEO_S,
+ GTX_error => GTX_Error_GEO_S,
+ PLLuseGTXclock => PLLuseGTXclock_S,
+ PLL_locked => PLLuseGTXclock0_S,
+ ADCs_reset => reset_ADCs_S,
+ ADCs_ready => ADCs_ready_S,
+ FEE_reset => reset_FEE_S,
+ startupready => startupready_S
+ );
+
+-- ADC configuration (PARALLEL or SERIAL)--------------------------------------------------------------
+
+gen_adcparallelprog: if ADC_PARALLELINIT=true generate
+ SCK_S <= '0'; -- 2-lane 16-bits serialization
+ SDI_S <= '0'; -- normal mode (not sleeping)
+ CSA_S <= (others => '0'); -- 2-lane 16-bits serialization
+ CSB_S <= (others => '0'); -- 2-lane 16-bits serialization
+ SDOA_S <= (others => '0'); -- no internal termination
+ SDOB_S <= (others => '0'); -- no internal termination
+end generate;
+
+gen_adcserialprog: if ADC_PARALLELINIT=false generate
+AdcSerialProg1: AdcSerialProg port map(
+ clock => clock_S,
+ reset => reset_S,
+ init => ADCchip_init1_S,
+ clock_out => SCK_S,
+ dataA_in(0) => SDOA_S(1),
+ dataA_in(1) => SDOA_S(2),
+ dataA_in(2) => SDOA_S(3),
+ dataA_in(3) => SDOA_S(4),
+ dataB_in(0) => SDOB_S(1),
+ dataB_in(1) => SDOB_S(2),
+ dataB_in(2) => SDOB_S(3),
+ dataB_in(3) => SDOB_S(4),
+ data_out => SDI_S,
+ chipnselectA(0) => CSA_S(1),
+ chipnselectA(1) => CSA_S(2),
+ chipnselectA(2) => CSA_S(3),
+ chipnselectA(3) => CSA_S(4),
+ chipnselectB(0) => CSB_S(1),
+ chipnselectB(1) => CSB_S(2),
+ chipnselectB(2) => CSB_S(3),
+ chipnselectB(3) => CSB_S(4),
+ selREGS => (others => '0')
+ );
+ADCchip_init1_S <= '1' when (ADCchip_init_S='1') else '0';
+end generate;
+
+-- ADC inputs ----------------------------------------------------------------------
+reset_ADCs1_S <= '1' when (reset_ADCs_S='1') else '0';
+
+FEE_ADCinput_module1: FEE_ADCinput_module port map(
+ clock200MHz => clock200MHz_S,
+ clock80MHz => clock_S,
+ clockAsync => async_clock_S,
+ reset => reset_ADCs1_S,
+ ADCs_enable => ADCs_enable_S,
+----ADC1---------------------------------------------
+ AD11A_P => AD11A_P,
+ AD11A_N => AD11A_N,
+ AD11B_P => AD11B_P,
+ AD11B_N => AD11B_N,
+ AD12A_P => AD12A_P,
+ AD12A_N => AD12A_N,
+ AD12B_P => AD12B_P,
+ AD12B_N => AD12B_N,
+ AD13A_P => AD13A_P,
+ AD13A_N => AD13A_N,
+ AD13B_P => AD13B_P,
+ AD13B_N => AD13B_N,
+ AD14A_P => AD14A_P,
+ AD14A_N => AD14A_N,
+ AD14B_P => AD14B_P,
+ AD14B_N => AD14B_N,
+ AD15A_P => AD15A_P,
+ AD15A_N => AD15A_N,
+ AD15B_P => AD15B_P,
+ AD15B_N => AD15B_N,
+ AD16A_P => AD16A_P,
+ AD16A_N => AD16A_N,
+ AD16B_P => AD16B_P,
+ AD16B_N => AD16B_N,
+ AD17A_P => AD17A_P,
+ AD17A_N => AD17A_N,
+ AD17B_P => AD17B_P,
+ AD17B_N => AD17B_N,
+ AD18A_P => AD18A_P,
+ AD18A_N => AD18A_N,
+ AD18B_P => AD18B_P,
+ AD18B_N => AD18B_N,
+
+ DCOA1_P => DCOA1_P,
+ DCOA1_N => DCOA1_N,
+ DCOB1_P => DCOB1_P,
+ DCOB1_N => DCOB1_N,
+
+ FRA1_P => FRA1_P ,
+ FRA1_N => FRA1_N ,
+ FRB1_P => FRB1_P ,
+ FRB1_N => FRB1_N ,
+
+ ----ADC2---------------------------------------------
+ AD21A_P => AD21A_P,
+ AD21A_N => AD21A_N,
+ AD21B_P => AD21B_P,
+ AD21B_N => AD21B_N,
+ AD22A_P => AD22A_P,
+ AD22A_N => AD22A_N,
+ AD22B_P => AD22B_P,
+ AD22B_N => AD22B_N,
+ AD23A_P => AD23A_P,
+ AD23A_N => AD23A_N,
+ AD23B_P => AD23B_P,
+ AD23B_N => AD23B_N,
+ AD24A_P => AD24A_P,
+ AD24A_N => AD24A_N,
+ AD24B_P => AD24B_P,
+ AD24B_N => AD24B_N,
+ AD25A_P => AD25A_P,
+ AD25A_N => AD25A_N,
+ AD25B_P => AD25B_P,
+ AD25B_N => AD25B_N,
+ AD26A_P => AD26A_P,
+ AD26A_N => AD26A_N,
+ AD26B_P => AD26B_P,
+ AD26B_N => AD26B_N,
+ AD27A_P => AD27A_P,
+ AD27A_N => AD27A_N,
+ AD27B_P => AD27B_P,
+ AD27B_N => AD27B_N,
+ AD28A_P => AD28A_P,
+ AD28A_N => AD28A_N,
+ AD28B_P => AD28B_P,
+ AD28B_N => AD28B_N,
+
+ DCOA2_P => DCOA2_P,
+ DCOA2_N => DCOA2_N,
+ DCOB2_P => DCOB2_P,
+ DCOB2_N => DCOB2_N,
+
+ FRA2_P => FRA2_P ,
+ FRA2_N => FRA2_N ,
+ FRB2_P => FRB2_P ,
+ FRB2_N => FRB2_N ,
+
+ ----ADC3---------------------------------------------
+ AD31A_P => AD31A_P,
+ AD31A_N => AD31A_N,
+ AD31B_P => AD31B_P,
+ AD31B_N => AD31B_N,
+ AD32A_P => AD32A_P,
+ AD32A_N => AD32A_N,
+ AD32B_P => AD32B_P,
+ AD32B_N => AD32B_N,
+ AD33A_P => AD33A_P,
+ AD33A_N => AD33A_N,
+ AD33B_P => AD33B_P,
+ AD33B_N => AD33B_N,
+ AD34A_P => AD34A_P,
+ AD34A_N => AD34A_N,
+ AD34B_P => AD34B_P,
+ AD34B_N => AD34B_N,
+ AD35A_P => AD35A_P,
+ AD35A_N => AD35A_N,
+ AD35B_P => AD35B_P,
+ AD35B_N => AD35B_N,
+ AD36A_P => AD36A_P,
+ AD36A_N => AD36A_N,
+ AD36B_P => AD36B_P,
+ AD36B_N => AD36B_N,
+ AD37A_P => AD37A_P,
+ AD37A_N => AD37A_N,
+ AD37B_P => AD37B_P,
+ AD37B_N => AD37B_N,
+ AD38A_P => AD38A_P,
+ AD38A_N => AD38A_N,
+ AD38B_P => AD38B_P,
+ AD38B_N => AD38B_N,
+
+ DCOA3_P => DCOA3_P,
+ DCOA3_N => DCOA3_N,
+ DCOB3_P => DCOB3_P,
+ DCOB3_N => DCOB3_N,
+
+ FRA3_P => FRA3_P ,
+ FRA3_N => FRA3_N ,
+ FRB3_P => FRB3_P ,
+ FRB3_N => FRB3_N ,
+
+ ----ADC4---------------------------------------------
+ AD41A_P => AD41A_P,
+ AD41A_N => AD41A_N,
+ AD41B_P => AD41B_P,
+ AD41B_N => AD41B_N,
+ AD42A_P => AD42A_P,
+ AD42A_N => AD42A_N,
+ AD42B_P => AD42B_P,
+ AD42B_N => AD42B_N,
+ AD43A_P => AD43A_P,
+ AD43A_N => AD43A_N,
+ AD43B_P => AD43B_P,
+ AD43B_N => AD43B_N,
+ AD44A_P => AD44A_P,
+ AD44A_N => AD44A_N,
+ AD44B_P => AD44B_P,
+ AD44B_N => AD44B_N,
+ AD45A_P => AD45A_P,
+ AD45A_N => AD45A_N,
+ AD45B_P => AD45B_P,
+ AD45B_N => AD45B_N,
+ AD46A_P => AD46A_P,
+ AD46A_N => AD46A_N,
+ AD46B_P => AD46B_P,
+ AD46B_N => AD46B_N,
+ AD47A_P => AD47A_P,
+ AD47A_N => AD47A_N,
+ AD47B_P => AD47B_P,
+ AD47B_N => AD47B_N,
+ AD48A_P => AD48A_P,
+ AD48A_N => AD48A_N,
+ AD48B_P => AD48B_P,
+ AD48B_N => AD48B_N,
+
+ DCOA4_P => DCOA4_P,
+ DCOA4_N => DCOA4_N,
+ DCOB4_P => DCOB4_P,
+ DCOB4_N => DCOB4_N,
+
+ FRA4_P => FRA4_P ,
+ FRA4_N => FRA4_N ,
+ FRB4_P => FRB4_P ,
+ FRB4_N => FRB4_N ,
+
+ ADC_clk => ADC_clk_S,
+ ADCs_ready => ADCs_ready_S,
+ adcdata => adcdata_S
+ );
+ADCs_enable_S <= '1';
+
+-- Superburst --------------------------------------------------------------
+
+--IOBUF_superburst00: IOBUF port map (O => superburst_in_S(0), IO => INTCOM0_P, I => superburst_out_S(0), T => IcontrolPLLnot_S);
+--IOBUF_superburst01: IOBUF port map (O => superburst_in_S(1), IO => INTCOM0_N, I => superburst_out_S(1), T => IcontrolPLLnot_S);
+--IOBUF_superburst02: IOBUF port map (O => superburst_in_S(2), IO => INTCOM1_P, I => superburst_out_S(2), T => IcontrolPLLnot_S);
+--IOBUF_superburst03: IOBUF port map (O => superburst_in_S(3), IO => INTCOM1_N, I => superburst_out_S(3), T => IcontrolPLLnot_S);
+--IOBUF_superburst04: IOBUF port map (O => superburst_in_S(4), IO => INTCOM2_P, I => superburst_out_S(4), T => IcontrolPLLnot_S);
+--IOBUF_superburst05: IOBUF port map (O => superburst_in_S(5), IO => INTCOM2_N, I => superburst_out_S(5), T => IcontrolPLLnot_S);
+--IOBUF_superburst06: IOBUF port map (O => superburst_in_S(6), IO => INTCOM3_P, I => superburst_out_S(6), T => IcontrolPLLnot_S);
+--IOBUF_superburst07: IOBUF port map (O => superburst_in_S(7), IO => INTCOM3_N, I => superburst_out_S(7), T => IcontrolPLLnot_S);
+--IOBUF_superburst08: IOBUF port map (O => superburst_in_S(8), IO => INTCOM4_P, I => superburst_out_S(8), T => IcontrolPLLnot_S);
+--IOBUF_superburst09: IOBUF port map (O => superburst_in_S(9), IO => INTCOM4_N, I => superburst_out_S(9), T => IcontrolPLLnot_S);
+--IOBUF_superburst10: IOBUF port map (O => superburst_in_S(10), IO => INTCOM5_P, I => superburst_out_S(10), T => IcontrolPLLnot_S);
+--IOBUF_superburst11: IOBUF port map (O => superburst_in_S(11), IO => INTCOM5_N, I => superburst_out_S(11), T => IcontrolPLLnot_S);
+--IOBUF_superburst12: IOBUF port map (O => superburst_in_S(12), IO => INTCOM6_P, I => superburst_out_S(12), T => IcontrolPLLnot_S);
+--IOBUF_superburst13: IOBUF port map (O => superburst_in_S(13), IO => INTCOM6_N, I => superburst_out_S(13), T => IcontrolPLLnot_S);
+--IOBUF_superburst14: IOBUF port map (O => superburst_in_S(14), IO => INTCOM7_P, I => superburst_out_S(14), T => IcontrolPLLnot_S);
+--IOBUF_superburst15: IOBUF port map (O => superburst_in_S(15), IO => INTCOM7_N, I => superburst_out_S(15), T => IcontrolPLLnot_S);
+
+INTCOM0_P <= superburst_out_S(0) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM0_N <= superburst_out_S(1) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM1_P <= superburst_out_S(2) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM1_N <= superburst_out_S(3) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM2_P <= superburst_out_S(4) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM2_N <= superburst_out_S(5) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM3_P <= superburst_out_S(6) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM3_N <= superburst_out_S(7) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM4_P <= superburst_out_S(8) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM4_N <= superburst_out_S(9) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM5_P <= superburst_out_S(10) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM5_N <= superburst_out_S(11) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM6_P <= superburst_out_S(12) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM6_N <= superburst_out_S(13) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM7_P <= superburst_out_S(14) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM7_N <= superburst_out_S(15) when IcontrolPLLnot_S='0' else 'Z';
+
+
+superburst_out_S(15 downto 0) <= superburst_out0_S(15 downto 0) when superburst_startout_S='1' else '0' & superburst_out0_S(30 downto 16);
+
+process(rxSodaClk_S)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+ if (rising_edge(rxSodaClk_S)) then
+ if (superburst_startout0_S='1') then
+ superburst_startout_S <= '1';
+ count_V := (others => '0');
+ elsif count_V="011" then
+ superburst_startout_S <= '0';
+ elsif count_V/="111" then
+ count_V := count_V+1;
+ end if;
+ end if;
+end process;
+
+superburst0_in_S(0) <= INTCOM0_P;
+superburst0_in_S(1) <= INTCOM0_N;
+superburst0_in_S(2) <= INTCOM1_P;
+superburst0_in_S(3) <= INTCOM1_N;
+superburst0_in_S(4) <= INTCOM2_P;
+superburst0_in_S(5) <= INTCOM2_N;
+superburst0_in_S(6) <= INTCOM3_P;
+superburst0_in_S(7) <= INTCOM3_N;
+superburst0_in_S(8) <= INTCOM4_P;
+superburst0_in_S(9) <= INTCOM4_N;
+superburst0_in_S(10) <= INTCOM5_P;
+superburst0_in_S(11) <= INTCOM5_N;
+superburst0_in_S(12) <= INTCOM6_P;
+superburst0_in_S(13) <= INTCOM6_N;
+superburst0_in_S(14) <= INTCOM7_P;
+superburst0_in_S(15) <= INTCOM7_N;
+
+process(superburst_startin0_S,clear_superburst_startin_S)
+begin
+ if clear_superburst_startin_S='1' then
+ superburst_startin1_S <= '0';
+ elsif (rising_edge(superburst_startin0_S)) then
+ superburst_startin1_S <= '1';
+ end if;
+end process;
+process(ADC_clk_S)
+variable done_V : std_logic:= '0';
+begin
+ if (rising_edge(ADC_clk_S)) then
+ clear_superburst_startin_S <= '0';
+ superburst_start_S <= '0';
+ superburst_startin2_S <= superburst_startin1_S;
+ superburst_startin3_S <= superburst_startin2_S;
+ superburst_startin0sync_S <= superburst_startin0_S;
+ if (superburst_startin3_S='0') and (superburst_startin2_S='1') then
+ superburst_in_S(15 downto 0) <= superburst0_in_S(15 downto 0);
+ done_V := '0';
+ elsif (superburst_startin2_S='1') and (superburst_startin0sync_S='0') and (done_V='0') then
+ superburst_in_S(30 downto 16) <= superburst0_in_S(14 downto 0);
+ clear_superburst_startin_S <= '1';
+ superburst_start_S <= '1';
+ done_V := '1';
+ elsif (done_V='1') and (superburst_startin3_S='1') and (superburst_startin2_S='1') and (superburst_startin0sync_S='0') then
+ clear_superburst_startin_S <= '1';
+ end if;
+ end if;
+end process;
+
+-- GTX ----------------------------------------------------
+
+LOS_S <= '1' when (LOS='1') or (MOD_DEF(0)='1') else '0';
+TX_DIS <= '0'; -- SFP always enabled
+
+
+FEE_gtxModule1: FEE_gtxModule port map(
+ gtpClk_P => MGTREFCLK_P,
+ gtpClk_N => MGTREFCLK_N,
+ refclk_out => refclk_S,
+ sysClk => clock_S,
+ asyncclk => async_clock_S,
+ reset => GTX_reset_S,
+ disable_GTX_reset => disable_GTX_reset_S,
+
+ TX_DLM => TX_DLM_S,
+ TX_DLM_WORD => TX_DLM_WORD_S,
+ RX_DLM => RX_DLM_S,
+ RX_DLM_WORD => RX_DLM_WORD_S,
+
+ txAsyncClk => packet_out_clock_S,
+ txAsyncData => packet_out_data_S,
+ txAsyncDataWrite => packet_out_write_S,
+ txAsyncFirstData => packet_out_first_S,
+ txAsyncLastData => packet_out_last_S,
+ txAsyncFifoFull => packet_out_fifofull_S,
+ txUsrClk => open,
+ txLocked => GTX_txLocked_S,
+
+ rxAsyncClk => packet_out_clock_S,
+ rxAsyncData => packet_in_data_S,
+ rxAsyncFirstData => packet_in_first_S,
+ rxAsyncLastData => packet_in_last_S,
+ rxAsyncDataRead => packet_in_read_S,
+ rxError => GTX_Error_S,
+ rxAsyncDataOverflow => open,
+ rxAsyncDataPresent => packet_in_present_S,
+ rxUsrClkdiv2 => rxUsrClkdiv2_S,
+ rxSodaClk => rxSodaClk_S,
+ rxSodaClk40 => rxSodaClk40_S,
+ rxLocked => GTX_rxLocked_S,
+
+ gtpTxP0 => TX_P,
+ gtpTxN0 => TX_N,
+ gtpRxP0 => RX_P,
+ gtpRxN0 => RX_N,
+ GT0_QPLLOUTCLK_IN => '0', -- gt0_qplloutclk_S,
+ GT0_QPLLOUTREFCLK_IN => '0' -- gt0_qplloutrefclk_S,
+ );
+
+
+
+process(rxSodaClk_S)
+begin
+ if (rising_edge(rxSodaClk_S)) then
+ reset_rxSodaClk_S <= not startupready_S;
+ end if;
+end process;
+
+gtx_common1: gtx_common port map(
+ QPLLREFCLKSEL_IN => "001",
+ GTREFCLK0_IN => refclk_S,
+ GTREFCLK1_IN => '0',
+ QPLLLOCK_OUT => gt0_qplllock_S,
+ QPLLLOCKDETCLK_IN => clock_S,
+ QPLLOUTCLK_OUT => gt0_qplloutclk_S,
+ QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_S,
+ QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_S,
+ QPLLRESET_IN => gt0_qpllreset_S
+ );
+
+posedge_to_pulse_notintable: posedge_to_pulse port map(
+ clock_in => rxSodaClk_S,
+ clock_out => ADC_clk_S,
+ en_clk => '1',
+ signal_in => GTX_Error_GEO_S,
+ pulse => rxNotInTable_S);
+
+
+-- SODA ----------------------------------------------------
+FEE_soda_client1: FEE_soda_client port map(
+ SYSCLK => clock_S,
+ SODACLK => rxSodaClk_S,
+ RESET => reset_rxSodaClk_S,
+ CLEAR => '0',
+ CLK_EN => '1',
+ RX_DLM_WORD_IN => RX_DLM_WORD_S,
+ RX_DLM_IN => RX_DLM_S,
+ TX_DLM_OUT => TX_DLM_S,
+ TX_DLM_WORD_OUT => TX_DLM_WORD_S,
+ TX_DLM_PREVIEW_OUT => open,
+ LINK_PHASE_IN => c_PHASE_H,
+
+ START_OF_SUPERBURST => superburst_startout0_S,
+ SUPER_BURST_NR => superburst_out0_S,
+ SODA_CMD_VALID => SODA_cmd_valid_S,
+ SODA_CMD_WORD => SODA_cmd_word_S,
+
+ SODA_DATA_IN => (others => '0'),
+ SODA_DATA_OUT => open,
+ SODA_ADDR_IN => (others => '0'),
+ SODA_READ_IN => '0',
+ SODA_WRITE_IN => '0',
+ SODA_ACK_OUT => open,
+ LEDS_OUT => open,
+ LINK_DEBUG_IN => (others => '0'));
+
+posedge_to_pulse_force_hit_out_S: posedge_to_pulse port map(
+ clock_in => rxSodaClk_S,
+ clock_out => ADC_clk_S,
+ en_clk => '1',
+ signal_in => force_hit_out0_S,
+ pulse => force_hit_out_S);
+
+
+process(rxSodaClk_S)
+begin
+ if (rising_edge(rxSodaClk_S)) then
+ reset_rxSodaClk_S <= not startupready_S;
+ end if;
+end process;
+
+EnableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(29)='1') else '0';
+DisableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(28)='1') else '0';
+force_hit_out0_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(26)='1') else '0';
+
+datatakingprocess: process(rxSodaClk_S)
+begin
+ if (rising_edge(rxSodaClk_S)) then
+ if DisableDataTaking_S='1' then
+ DataTaking_enabled_out_S <= '0';
+ elsif EnableDataTaking_S='1' then
+ DataTaking_enabled_out_S <= '1';
+ end if;
+ end if;
+end process;
+
+process(ADC_clk_S,startupready_S)
+variable enable_data_V : std_logic := '0';
+variable DataTaking_enabled_V : std_logic := '0';
+begin
+ if (startupready_S='0') then
+ enable_data_V := '0';
+ enable_data_S <= '0';
+ elsif (rising_edge(ADC_clk_S)) then
+ enable_data_S <= DataTaking_enabled_V;
+ DataTaking_enabled_V := DataTaking_enabled_in_S;
+ end if;
+end process;
+
+process(ADC_clk_S)
+variable counter : integer range 0 to ADCCLOCKFREQUENCY-1 := 0;
+begin
+ if (rising_edge(ADC_clk_S)) then
+ if counter/=0 then
+ counter := counter-1;
+ onesecondpulse_S <= '0';
+ else
+ counter := ADCCLOCKFREQUENCY-1;
+ onesecondpulse_S <= '1';
+ end if;
+ end if;
+end process;
+
+-- Feature extraction module ----------------------------------------------------
+process(ADC_clk_S) -- synchronise to 1 clock
+begin
+ if (rising_edge(ADC_clk_S)) then
+ reset_FEE_ADCclk_S <= reset_FEE_S;
+ end if;
+end process;
+
+FEE_module1: FEE_adc32_module port map(
+ clock => ADC_clk_S,
+ reset => reset_FEE_ADCclk_S,
+ enable_data => enable_data_S,
+ GEO => GEO_S,
+ ADCdata => adcdata_S,
+ superburst_start => superburst_start_S,
+ superburst_received => superburst_in_S,
+ force_hit => force_hit_S,
+ onesecondpulse => onesecondpulse_S,
+ rxNotInTable => rxNotInTable_S,
+ startupready => startupready_S,
+ request_init => request_init_S,
+ packet_in_data => FE_in_data_S,
+ packet_in_present => FE_in_present_S,
+ packet_in_read => FE_in_read_S,
+ packet_out_data => FE_out_data_S,
+ packet_out_first => FE_out_first_S,
+ packet_out_last => FE_out_last_S,
+ packet_out_write => FE_out_write_S,
+ packet_out_inpipe => FE_out_inpipe_S,
+ packet_out_fifofull => FE_out_fifofull_S,
+ errorbyte_out => errorbyte_S,
+ errorbyte_in => errorbyte_S,
+ smaart_in => TEMP_OUT_S,
+ smaart_out => TEMP_IN_S,
+ sysmon_data => sysmon_data_S,
+ sysmon_reset => sysmon_reset_S,
+ sysmon_address => sysmon_address_S,
+ sysmon_read => sysmon_read_S,
+ second_module_zero => vioword_S(9),
+ enable_waveform => enable_waveform_S,
+ compare_error => compare_error_S
+ );
+
+
+gen_nocombine: if NROFFEEFPGAS=1 generate
+
+ GTX_txLocked_GEO_S <= GTX_txLocked_S;
+ GTX_Error_GEO_S <= GTX_Error_S;
+ GTX_rxLocked_GEO_S <= GTX_rxLocked_S;
+ LOS_GEO_S <= LOS_S;
+
+ packet_out_clock_S <= ADC_clk_S;
+ FE_in_data_S <= packet_in_data_S;
+ FE_in_present_S <= packet_in_present_S;
+ packet_in_read_S <= FE_in_read_S;
+-- FE_in_first_S <= packet_in_first_S;
+-- FE_in_last_S <= packet_in_last_S;
+ packet_out_data_S <= FE_out_data_S;
+ packet_out_first_S <= FE_out_first_S;
+ packet_out_last_S <= FE_out_last_S;
+ packet_out_write_S <= FE_out_write_S;
+ FE_out_fifofull_S <= packet_out_fifofull_S;
+
+end generate;
+
+gen_combine: if NROFFEEFPGAS=2 generate
+
+ packet_out_clock_S <= aurora_clock_S;
+ GTX_txLocked_GEO_S <= GTX_txLocked_S when GEO_S='0' else '1';
+ GTX_rxLocked_GEO_S <= GTX_rxLocked_S when GEO_S='0' else '1';
+ GTX_Error_GEO_S <= GTX_Error_S when GEO_S='0' else '0';
+ LOS_GEO_S <= LOS_S when GEO_S='0' else '0';
+
+ FE_in_data_S <= split_local_S;
+-- FE_in_first_S <= split_local_first_S;
+-- FE_in_last_S <= split_local_last_S;
+ FE_in_present_S <= split_local_present_S;
+ split_local_read_S <= FE_in_read_S;
+
+ split_in_S <= packet_in_data_S when GEO_S='0' else aurora_rx_data_S;
+ split_in_first_S <= packet_in_first_S when GEO_S='0' else aurora_rx_first_S;
+ split_in_last_S <= packet_in_last_S when GEO_S='0' else aurora_rx_last_S;
+ split_in_present_S <= packet_in_present_S when GEO_S='0' else aurora_rx_write_S;
+ packet_in_read_S <= split_in_read_S when GEO_S='0' else '1';
+
+ aurora_tx_data_S <= split_remote_wr_S when GEO_S='0' else comb_out_S;
+ aurora_tx_first_S <= split_remote_wr_first_S when GEO_S='0' else comb_out_first_S;
+ aurora_tx_last_S <= split_remote_wr_last_S when GEO_S='0' else comb_out_last_S;
+ aurora_tx_inpipe_S <= '0' when GEO_S='0' else comb_out_inpipe_S;
+ aurora_tx_write_S <= split_remote_wr_write_S when GEO_S='0' else comb_out_write_S;
+ FEE_fiforead2write1: FEE_fiforead2write
+ generic map(
+ BITS => 34)
+ port map(
+ clock => aurora_clock_S,
+ data_in(31 downto 0) => split_remote_S,
+ data_in(32) => split_remote_first_S,
+ data_in(33) => split_remote_last_S,
+ data_in_empty => split_remote_fifoempty_S,
+ data_in_read => split_remote_read_S,
+ data_out(31 downto 0) => split_remote_wr_S,
+ data_out(32) => split_remote_wr_first_S,
+ data_out(33) => split_remote_wr_last_S,
+ data_out_write => split_remote_wr_write_S,
+ data_out_allowed => split_remote_wr_allowed_S);
+ split_remote_fifoempty_S <= '1' when split_remote_present_S='0' else '0';
+ split_remote_wr_allowed_S <= aurora_tx_allowed_S when GEO_S='0' else '1';
+
+ packet_out_data_S <= comb_out_S;
+ packet_out_write_S <= comb_out_write_S;
+ packet_out_first_S <= comb_out_first_S;
+ packet_out_last_S <= comb_out_last_S;
+ comb_out_fifofull_S <= packet_out_fifofull_S when GEO_S='0' else not aurora_tx_allowed_S;
+
+ comb_local_S <= FE_out_data_S;
+ comb_local_first_S <= FE_out_first_S;
+ comb_local_last_S <= FE_out_last_S;
+ comb_local_write_S <= FE_out_write_S;
+ comb_local_inpipe_S <= FE_out_inpipe_S;
+ FE_out_fifofull_S <= comb_local_fifofull_S;
+
+ comb_remote_S <= aurora_rx_data_S;
+ comb_remote_first_S <= aurora_rx_first_S;
+ comb_remote_last_S <= aurora_rx_last_S;
+ comb_remote_write_S <= aurora_rx_write_S when GEO_S='0' else '0';
+ comb_remote_inpipe_S <= aurora_rx_inpipe_S when GEO_S='0' else '0';
+ aurora_rx_almostfull_S <= comb_remote_almostfull_S when GEO_S='0' else '0';
+ -- error <= '1' when aurora_rx_write_S='1' and comb_remote_fifofull_S='1' else '0';
+
+ aurora_dual_module1: aurora_dual_module port map(
+ stable_clock => clock_S,
+ reset => reset_FEE_S,
+ user_clock => aurora_clock_S,
+ tx_data => aurora_tx_data_S,
+ tx_first => aurora_tx_first_S,
+ tx_last => aurora_tx_last_S,
+ tx_write => aurora_tx_write_S,
+ tx_allowed => aurora_tx_allowed_S,
+ tx_inpipe => aurora_tx_inpipe_S,
+ rx_data => aurora_rx_data_S,
+ rx_first => aurora_rx_first_S,
+ rx_last => aurora_rx_last_S,
+ rx_write => aurora_rx_write_S,
+ rx_almostfull => aurora_rx_almostfull_S,
+ rx_inpipe => aurora_rx_inpipe_S,
+ locked => aurora_locked_S,
+ error => aurora_error_S,
+ RXP(0) => GT_B2A_0_P,
+ RXP(1) => GT_B2A_1_P,
+ RXN(0) => GT_B2A_0_N,
+ RXN(1) => GT_B2A_1_N,
+ TXP(0) => GT_A2B_0_P,
+ TXP(1) => GT_A2B_1_P,
+ TXN(0) => GT_A2B_0_N,
+ TXN(1) => GT_A2B_1_N,
+ GTXQ0_P => MGTREFCLK_P,
+ GTXQ0_N => MGTREFCLK_N,
+ gt0_refclk_in => refclk_S,
+ gt0_qplllock_in => gt0_qplllock_S,
+ gt0_qpllrefclklost_in => gt0_qpllrefclklost_S,
+ gt0_qpllreset_out => gt0_qpllreset_S,
+ GT_QPLLOUTCLK_IN => gt0_qplloutclk_S,
+ GT_QPLLOUTREFCLK_IN => gt0_qplloutrefclk_S
+ );
+
+ FEE_receive_split1: FEE_receive_split port map(
+ clock_in => aurora_clock_S,
+ clock_local => ADC_clk_S,
+ clock_remote => aurora_clock_S,
+ reset => reset_FEE_S,
+ GEO => GEO_S,
+ data_in => split_in_S,
+ data_in_first => split_in_first_S,
+ data_in_last => split_in_last_S,
+ data_in_present => split_in_present_S,
+ data_in_fifofull => split_in_fifofull_S,
+ data_in_read => split_in_read_S,
+ data_local => split_local_S,
+ data_local_first => split_local_first_S,
+ data_local_last => split_local_last_S,
+ data_local_present => split_local_present_S,
+ data_local_read => split_local_read_S,
+ data_remote => split_remote_S,
+ data_remote_first => split_remote_first_S,
+ data_remote_last => split_remote_last_S,
+ data_remote_present => split_remote_present_S,
+ data_remote_read => split_remote_read_S,
+ error => split_error_S);
+
+ FEE_transmit_combine1: FEE_transmit_combine port map(
+ clock_local => ADC_clk_S,
+ clock_remote => aurora_clock_S,
+ clock_out => aurora_clock_S,
+ reset => reset_FEE_S,
+ GEO => GEO_S,
+ enable_waveform => enable_waveform_S,
+ data_local => comb_local_S,
+ data_local_first => comb_local_first_S,
+ data_local_last => comb_local_last_S,
+ data_local_write => comb_local_write_S,
+ data_local_inpipe => comb_local_inpipe_S,
+ data_local_fifofull => comb_local_fifofull_S,
+ data_remote => comb_remote_S,
+ data_remote_first => comb_remote_first_S,
+ data_remote_last => comb_remote_last_S,
+ data_remote_write => comb_remote_write_S,
+ data_remote_inpipe => comb_remote_inpipe_S,
+ data_remote_fifofull => comb_remote_fifofull_S,
+ data_remote_almostfull => comb_remote_almostfull_S,
+ data_out => comb_out_S,
+ data_out_first => comb_out_first_S,
+ data_out_last => comb_out_last_S,
+ data_out_write => comb_out_write_S,
+ data_out_inpipe => comb_out_inpipe_S,
+ data_out_fifofull => comb_out_fifofull_S,
+ error => comb_error_S);
+
+end generate;
+
+reboot1: reboot port map(
+ TRIGGER => doreboot_S,
+ SYSCLK => clock40MHz_S);
+
+pulse_wr: posedge_to_pulse port map(
+ clock_in => ADC_clk_S,
+ clock_out => clock_S,
+ en_clk => '1',
+ signal_in => compare_error_S,
+ pulse => compare_error1_S);
+
+
+sem_module1: sem_module port map(
+ clk => clock40MHz_S,
+ status_heartbeat => status_heartbeat_S,
+ status_initialization => status_initialization_S,
+ status_observation => status_observation_S,
+ status_correction => status_correction_S,
+ status_classification => status_classification_S,
+ status_injection => status_injection_S,
+ status_essential => status_essential_S,
+ status_uncorrectable => status_uncorrectable_S);
+
+process(clock40MHz_S)
+variable prev_status_correction_V : std_logic := '1';
+begin
+ if (rising_edge(clock40MHz_S)) then
+ doreboot_S <= '0';
+ if (status_correction_S='0') and (prev_status_correction_V/='1') then
+ if status_uncorrectable_S='1' then
+ doreboot_S <= '1';
+ end if;
+ end if;
+ if (compare_error1_S='1') and (startupready_S='1') then
+--// doreboot_S <= '1';
+ end if;
+ prev_status_correction_V := status_correction_S;
+ end if;
+end process;
+
+superburst_lvds_out1 : OBUFDS
+ generic map(
+ IOSTANDARD => "LVDS")
+ port map(
+ O => MON2_P,
+ OB => MON2_N,
+ I => superburst_startout0_S);
+superburst_lvds_out2 : OBUFDS
+ generic map(
+ IOSTANDARD => "LVDS")
+ port map(
+ O => MON1_P,
+ OB => MON1_N,
+ I => superburst_startout_S);
+
+
+
+-- pulse_wr: posedge_to_pulse port map(
+ -- clock_in => clock_S,
+ -- clock_out => clock_S,
+ -- en_clk => '1',
+ -- signal_in => vio_LMK04806_wr0_S,
+ -- pulse => vio_LMK04806_wr_S);
+
+
+-- vio_debug1: vio_debug port map(
+ -- clk => clock_S,
+ -- probe_in0(0) => RDu_S,
+ -- probe_in1(0) => PLL_booting_busy_S,
+ -- probe_in2(0) => GTX_rxLocked_S,
+ -- probe_in3(0) => startupready_S,
+ -- probe_out0(0) => debug_reset_S,
+ -- probe_out1(0) => vio_LMK04806_wr0_S,
+ -- probe_out2 => vio_LMK04806_dta_S);
+
+vio36_1: vio36 port map(
+ clk => ADC_clk_S,
+ probe_out0 => vioword_S);
+
+
+process(packet_out_clock_S)
+begin
+ if (rising_edge(packet_out_clock_S)) then
+ if packet_out_write_S='1' then
+ debug_packet_out_data_S <= packet_out_data_S;
+ debug_packet_out_first_S <= packet_out_first_S;
+ debug_packet_out_last_S <= packet_out_last_S;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2015.3 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="10" Path="D:/Xilinx_proj/Panda/Xilinx/FrontEndElectronics/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard_Vivado.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="1b37de9fde294ec199fac2bb789ffffa"/>
+ <Option Name="Part" Val="xc7k160tfbg484-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PPRDIR/FEE_Kintex_ADCboard_Vivado.ip_user_files"/>
+ <Option Name="IPStaticSourceDir" Val="$PPRDIR/FEE_Kintex_ADCboard_Vivado.ip_user_files/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ </Configuration>
+ <FileSets Version="1" Minor="31">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_sync_block.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_gt.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_cpll_railing.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/blockmem.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_tx_startup_fsm.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_rx_startup_fsm.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_multi_gt.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_auto_phase_align.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/shift_register_small.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/iirfilter_1order_selectBW.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_MWDfilter_unsigned.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_init.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/gtxkintex7fee80_clock_module.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_eventdetector.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../SODA/trb_net_std.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/Panda_package.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/gtxkintex7fee80_gt_usrclk_source.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/gtxkintex7fee80_common_reset.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_wavemux_readfifo.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_wavemux2to1.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_waveform_to_36bits.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_pulse_detect.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_pulsewaveform_buffer.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_pileup_check.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_mux2to1.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_extract_pulse.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_baselinefollower_eventdetector.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_cdc_sync_exdes.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../SODA/trb_net_components.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../SODA/trb_net16_hub_func.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_collect_pileup_pulses.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/ip_vivado/gtxkintex7fee80_support.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_sorting_wavemux.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_sorting_mux.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_rxBitLock.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_dual_pulse_waveform.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/FEE_data8to16.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/FEE_data16to8.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/crc8_add_check32.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_support_reset_logic.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_clock_module.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/adc/AdcFrame.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/adc/AdcData.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/adc/AdcClock.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../SODA/soda_components.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/sensors/TMP104module.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../SODA/soda_reply_pkt_builder.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../SODA/soda_packet_handler.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/FEE_SODAfrequencydiv5.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_slowcontrol_packet_receiver.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_pulse_and_pileup_waveforms.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_measure_frequency.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/FEE_gtxWrapper_Kintex7.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_fifo8to32_SODA.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_fifo32to8_SODA.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_combine_data.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_board_slowcontrol.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_support.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_ll_to_axi_exdes.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_axi_to_ll_exdes.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_aurora_pkg.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/adc/AdcToplevel.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/ip/sem_support/sem_sem_cfg.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/posedge_to_pulse.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/sensors/SystemMonitorModule.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/reboot.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/LMK04806.vhd">
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+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/gtx_common.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_transmit_combine.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/FEE_startup.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../SODA/FEE_soda_client.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_receive_split.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/gtx/FEE_gtxModule.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_fiforead2write.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/adc/FEE_ADCinput_module.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/FEE_adc32_module.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_module.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/adc/AdcSerialProg.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/sources/sem_module.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/FEE_Kintex_ADCboard.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../FEE_modules/shift_register.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
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+</Project>
--- /dev/null
+---------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 27-10-2014
+-- Module Name: FEE_startup
+-- Description: Startup FEE : reset, PLL, ADCs, GTX ...
+-- Modifications:
+-- 30-03-2015 GTX_LOS signal added
+-- 09-09-2015 GTX_LOS synchronized and longer waiting times
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_startup
+--
+--
+-- Library:
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : stable main clock, frequency equal to ADC clock
+-- ADCclock : clock for ADC data, stable after GTX lock / ADCs init
+-- clock_from_PLL : clock from external PLL, frequency equal to ADC clock
+-- reset : reset all
+-- GEO : first ('0') or second ('1') FPGA
+-- IcontrolPLL : this FPGA controls the PLL/jtag
+-- PLL_booting : PLL initializing busy
+-- GTX_LOS : Los Off Signal from SFP module
+-- GTX_rxLocked : GTX receiver is locked to SODA frequency
+-- GTX_txLocked : GTX transmitter is locked
+-- GTX_error : error in GTX
+-- PLL_locked : external PLL is locked
+-- ADCs_ready : frame start signals from ADCs, LVDS negative
+--
+-- Outputs:
+-- ADCchip_init : start initialize ADC chip with serial interface
+-- PLL_init : initialize the PLL
+-- GTX_reset : reset the GTX
+-- PLLuseGTXclock : use the GTX recovered clock as reference for the external PLL
+-- ADCs_reset : reset the ADCs
+-- FEE_reset : reset the FEE module (feature extraction / slow control / ...)
+-- startupready : startup procedure is done
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_startup is
+ port (
+ clock : in std_logic;
+ ADCclock : in std_logic;
+ clock_from_PLL : in std_logic;
+ reset : in std_logic;
+ GEO : in std_logic;
+ IcontrolPLL : in std_logic;
+ ADCchip_init : out std_logic;
+ PLL_init : out std_logic;
+ PLL_booting : in std_logic;
+ GTX_LOS : in std_logic;
+ GTX_reset : out std_logic;
+ GTX_rxLocked : in std_logic;
+ GTX_txLocked : in std_logic;
+ GTX_error : in std_logic;
+ PLLuseGTXclock : out std_logic;
+ PLL_locked : in std_logic;
+ ADCs_reset : out std_logic;
+ ADCs_ready : in std_logic;
+ FEE_reset : out std_logic;
+ startupready : out std_logic
+ );
+end FEE_startup;
+
+architecture Behavioral of FEE_startup is
+
+type stage_type is (resetting,initPLL,waitPLLready,waitPLLlocked,resetGTX,waitGTXlocked,switchPLLclock,enableADCs,waitADCsready,enableFEE,readystate);
+signal stage_S : stage_type := resetting;
+
+signal PLLclockdiv255_S : std_logic;
+signal PLLclockdiv255sync0_S : std_logic;
+signal PLLclockdiv255sync1_S : std_logic;
+signal PLLclockdiv255_prev_S : std_logic;
+signal PLLfrequencyERROR_S : std_logic;
+signal PLLfrequcounter_V : integer range 0 to 255 := 0;
+
+signal IcontrolPLL_S : std_logic;
+signal IcontrolPLL1_S : std_logic;
+signal PLL_init_S : std_logic := '0';
+signal ADCchip_init_S : std_logic;
+signal GTX_LOS_S : std_logic;
+signal GTX_LOS0_S : std_logic;
+signal GTX_reset_S : std_logic := '1';
+signal PLLuseGTXclock_S : std_logic := '0';
+signal PLL_booting_S : std_logic;
+signal PLL_locked_S : std_logic;
+signal GTX_rxLocked0_S : std_logic;
+signal GTX_rxLocked_S : std_logic;
+signal GTX_txLocked0_S : std_logic;
+signal GTX_txLocked_S : std_logic;
+signal GTX_error0_S : std_logic;
+signal GTX_error_S : std_logic;
+signal ADCs_ready0_S : std_logic;
+signal ADCs_ready_S : std_logic;
+signal ADCs_reset_S : std_logic := '1';
+signal FEE_reset_S : std_logic := '1';
+signal FEE_reset0_S : std_logic := '1';
+signal startupready_S : std_logic := '0';
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of IcontrolPLL_S : signal is "true";
+-- attribute mark_debug of PLL_init_S : signal is "true";
+-- attribute mark_debug of ADCchip_init_S : signal is "true";
+-- attribute mark_debug of GTX_LOS_S : signal is "true";
+-- attribute mark_debug of GTX_reset_S : signal is "true";
+-- attribute mark_debug of PLLuseGTXclock_S : signal is "true";
+-- attribute mark_debug of PLL_booting_S : signal is "true";
+-- attribute mark_debug of PLL_locked_S : signal is "true";
+-- attribute mark_debug of GTX_rxLocked_S : signal is "true";
+-- attribute mark_debug of GTX_txLocked_S : signal is "true";
+-- attribute mark_debug of GTX_error_S : signal is "true";
+-- attribute mark_debug of ADCs_ready_S : signal is "true";
+-- attribute mark_debug of ADCs_reset_S : signal is "true";
+-- attribute mark_debug of FEE_reset_S : signal is "true";
+-- attribute mark_debug of startupready_S : signal is "true";
+-- attribute mark_debug of stage_S : signal is "true";
+
+begin
+
+
+-- FPGA1:
+-- reset , PLL unlocked
+-- initialize external PLL
+-- wait for external PLL ready
+-- wait for fiber locked
+-- switch PLL reference to reconstructed clock
+-- enable ADCs & enable FPGA2
+-- wait for ADCs ready
+-- enable FEE module
+
+-- FPGA2 with fiber:
+-- reset , PLL unlocked
+-- wait for fiber locked
+-- wait for enable ADCs
+-- enable ADCs
+-- wait for ADCs ready
+-- enable FEE module
+
+-- FPGA2 without fiber:
+-- reset , PLL unlocked
+-- wait for aurora locked
+-- wait for enable ADCs
+-- enable ADCs
+-- wait for ADCs ready
+-- enable FEE module
+
+-- synchronize to the right clock, if necessary -----------------
+PLL_init <= PLL_init_S;
+PLL_booting_S <= PLL_booting;
+ADCchip_init <= ADCchip_init_S;
+GTX_reset <= GTX_reset_S;
+PLLuseGTXclock <= PLLuseGTXclock_S;
+ADCs_reset <= ADCs_reset_S;
+startupready <= startupready_S;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ IcontrolPLL_S <= IcontrolPLL;
+ GTX_LOS_S <= GTX_LOS0_S;
+ GTX_LOS0_S <= GTX_LOS;
+ PLL_locked_S <= PLL_locked;
+ GTX_rxLocked0_S <= GTX_rxLocked;
+ GTX_rxLocked_S <= GTX_rxLocked0_S;
+ GTX_txLocked0_S <= GTX_txLocked;
+ GTX_txLocked_S <= GTX_txLocked0_S;
+ GTX_error0_S <= GTX_error;
+ GTX_error_S <= GTX_error0_S;
+ ADCs_ready0_S <= ADCs_ready;
+ ADCs_ready_S <= ADCs_ready0_S;
+ end if;
+end process;
+
+process(ADCclock,reset)
+begin
+ if reset='1' then
+ FEE_reset0_S <= '1';
+ FEE_reset <= '1';
+ elsif (rising_edge(ADCclock)) then
+
+ FEE_reset0_S <= FEE_reset_S;
+ FEE_reset <= FEE_reset0_S;
+ end if;
+end process;
+--------------------------------------------------------------------------
+
+-- check PLL frequency ---------------------------------------------------
+process(clock_from_PLL)
+variable counter_V : std_logic_vector(7 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock_from_PLL)) then
+ PLLclockdiv255_S <= counter_V(7);
+ counter_V := counter_V+1;
+ end if;
+end process;
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ PLLfrequencyERROR_S <= '0';
+ PLLclockdiv255sync0_S <= PLLclockdiv255_S;
+ PLLclockdiv255sync1_S <= PLLclockdiv255sync0_S;
+ PLLclockdiv255_prev_S <= PLLclockdiv255sync1_S;
+ if PLLclockdiv255_prev_S/=PLLclockdiv255sync1_S then
+ if (PLLfrequcounter_V<125) or (PLLfrequcounter_V>129) then
+ PLLfrequencyERROR_S <= '1';
+ end if;
+ PLLfrequcounter_V <= 0;
+ elsif PLLfrequcounter_V<255 then
+ PLLfrequcounter_V <= PLLfrequcounter_V+1;
+ end if;
+ end if;
+end process;
+--------------------------------------------------------------------------
+
+process(clock,reset,IcontrolPLL)
+variable wait_V : std_logic_vector(17 downto 0);
+variable waitADC_V : std_logic_vector(8 downto 0);
+begin
+ if reset='1' then
+ stage_S <= resetting;
+ ADCchip_init_S <= '0';
+ PLL_init_S <= '0';
+ GTX_reset_S <= '1';
+ PLLuseGTXclock_S <= '0';
+ ADCs_reset_S <= '1';
+ FEE_reset_S <= '1';
+ startupready_S <= '0';
+ IcontrolPLL1_S <= IcontrolPLL;
+ elsif (rising_edge(clock)) then
+ startupready_S <= '0';
+ case stage_S is
+ when resetting =>
+ wait_V := (others => '0');
+ ADCchip_init_S <= '1';
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '1';
+ PLLuseGTXclock_S <= '0';
+ ADCs_reset_S <= '1';
+ FEE_reset_S <= '1';
+ if IcontrolPLL_S='1' then
+ stage_S <= initPLL;
+ else
+ stage_S <= waitPLLlocked;
+ end if;
+ when initPLL =>
+ ADCchip_init_S <= '0';
+ PLL_init_S <= '1';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '1';
+ PLLuseGTXclock_S <= '0';
+ ADCs_reset_S <= '1';
+ FEE_reset_S <= '1';
+ if PLL_booting_S='1' then
+ wait_V := (others => '0');
+ stage_S <= waitPLLready;
+ else
+ if wait_V(17)='0' then
+ wait_V := wait_V+1;
+ else
+ stage_S <= resetting;
+ end if;
+ end if;
+ when waitPLLready =>
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '1';
+ PLLuseGTXclock_S <= '0';
+ ADCs_reset_S <= '1';
+ FEE_reset_S <= '1';
+ if PLL_booting_S='0' then
+ wait_V := (others => '0');
+ stage_S <= resetGTX;
+ else
+ if wait_V(16)='0' then
+ wait_V := wait_V+1;
+ else
+ stage_S <= resetting;
+ end if;
+ end if;
+ when waitPLLlocked =>
+ ADCchip_init_S <= '0';
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '1';
+ PLLuseGTXclock_S <= '0';
+ ADCs_reset_S <= '1';
+ FEE_reset_S <= '1';
+ if ((IcontrolPLL_S='1') or (PLL_locked_S='1')) and (GTX_LOS_S='0') then
+ stage_S <= resetGTX;
+ end if;
+ when resetGTX =>
+ ADCchip_init_S <= '0';
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '1';
+ PLLuseGTXclock_S <= '0';
+ ADCs_reset_S <= '1';
+ FEE_reset_S <= '1';
+ if wait_V(3)='0' then
+ wait_V := wait_V+1;
+ else
+ wait_V := (others => '0');
+ stage_S <= waitGTXlocked;
+ end if;
+ if GTX_LOS_S='1' then
+ stage_S <= waitPLLlocked;
+ end if;
+ when waitGTXlocked =>
+ ADCchip_init_S <= '0';
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '0';
+ PLLuseGTXclock_S <= '0';
+ ADCs_reset_S <= '1';
+ FEE_reset_S <= '1';
+ if (GTX_rxLocked_S='1') and (GTX_txLocked_S='1') and (GTX_LOS_S='0') then
+ stage_S <= switchPLLclock;
+ else
+ if wait_V(13)='1' then
+ wait_V := wait_V+1;
+ else
+ if (PLLfrequencyERROR_S='1') or (GTX_LOS_S='1') then
+ stage_S <= resetting;
+ end if;
+ end if;
+ end if;
+ when switchPLLclock => -- not necessary if IcontrolPLL_S='0', but does not harm
+ ADCchip_init_S <= '0';
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '0';
+ PLLuseGTXclock_S <= '1';
+ ADCs_reset_S <= '1';
+ FEE_reset_S <= '1';
+ stage_S <= enableADCs;
+ when enableADCs =>
+ ADCchip_init_S <= '0';
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '0';
+ PLLuseGTXclock_S <= '1';
+ ADCs_reset_S <= '0';
+ FEE_reset_S <= '1';
+ wait_V := (others => '0');
+ waitADC_V := (others => '0');
+ stage_S <= waitADCsready;
+ when waitADCsready =>
+ ADCchip_init_S <= '0';
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '0';
+ PLLuseGTXclock_S <= '1';
+ ADCs_reset_S <= '0';
+ FEE_reset_S <= '1';
+ if PLLfrequencyERROR_S='1' then
+ stage_S <= resetting;
+ elsif (ADCs_ready_S='1') then
+ if waitADC_V(8)='1' then
+ stage_S <= enableFEE;
+ else
+ waitADC_V := waitADC_V+1;
+ end if;
+ elsif wait_V(17)='0' then
+ wait_V := wait_V+1;
+ waitADC_V := (others => '0');
+ else
+ stage_S <= resetting;
+ end if;
+ when enableFEE =>
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '0';
+ PLLuseGTXclock_S <= '1';
+ ADCs_reset_S <= '0';
+ stage_S <= readystate;
+ when readystate =>
+ PLL_init_S <= '0';
+ FEE_reset_S <= '0';
+ GTX_reset_S <= '0';
+ PLLuseGTXclock_S <= '1';
+ ADCs_reset_S <= '0';
+ if PLLfrequencyERROR_S='1' then
+ stage_S <= resetting;
+ elsif (GTX_rxLocked_S='0') or (GTX_txLocked_S='0') or (GTX_LOS_S='1') then
+ stage_S <= waitPLLlocked;
+stage_S <= resetting;
+ elsif ADCs_ready_S='0' then
+ ADCs_reset_S <= '1';
+ ADCchip_init_S <= '0';
+ stage_S <= enableADCs;
+ else
+ startupready_S <= '1';
+ end if;
+ when others =>
+ PLL_init_S <= '0';
+ FEE_reset_S <= '1';
+ GTX_reset_S <= '1';
+ PLLuseGTXclock_S <= '0';
+ ADCs_reset_S <= '1';
+ FEE_reset_S <= '1';
+ startupready_S <= '0';
+ stage_S <= resetting;
+ end case;
+ if IcontrolPLL1_S/=IcontrolPLL_S then -- check if the same FPGA controls PLL
+ stage_S <= resetting;
+ end if;
+ IcontrolPLL1_S <= IcontrolPLL_S;
+ end if;
+end process;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+--use work.util_pack.ALL;
+
+entity LMK04806 is
+ generic(
+ CLK_DIV : integer := 2 -- slow down transfer
+ );
+ PORT(
+ clock : in std_logic; --Master clock
+ reset : in std_logic; --reset
+ CLKu : out std_logic; --Clk to LMK
+ DATAu : out std_logic; --Data to LMK
+ LEu : out std_logic; --Data Latch to LMK
+ RDu : in std_logic; --Read back
+ SYNC : out std_logic; --Sync CLK outputs LMK
+ boot_PLL : in std_logic; --Start booting when set high
+ booting : out std_logic --busy signal
+ );
+end LMK04806;
+
+architecture Behavioral of LMK04806 is
+constant NROFREGS : integer := 27;
+type RomType is array (0 to NROFREGS-1) of std_logic_vector(31 downto 0);
+type RomType32 is array (0 to 31) of std_logic_vector(31 downto 0);
+-- parameters based on 'Clock design tool' from National Semiconductor
+--CONSTANT TAB62M5 : RomType := -- 62.5MHz
+-- (
+-- x"00020000", -- R0 (Reset=1)
+-- x"00000500", -- R0 (Reset=0)
+-- X"00000500", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 62.5MHz)
+-- X"00000501", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 62.5MHz)
+-- X"00000502", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 125MHz) GTX & gclk
+-- X"00000503", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 125MHz) GTX & gclk
+-- X"00000504", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 62.5MHz)
+-- X"00000505", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 62.5MHz)
+-- x"11110006", -- R6 (OUT 3,2,1,0:LVDS, no delay)
+-- x"11110007", -- R7 (OUT 7,6,5,4:LVDS, no delay)
+-- x"11110008", -- R8 (OUT 11,10,9,8:LVDS, no delay)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"0000806A", -- R10 (OSCout1=LVPECL-700mV, OSCout0=disabled, OSCout1,0=disabled, OSC0,1=bypass_divider, OSCoutDIV=8, VCOdiv=1, FEEDbackMUX=CLKout6)
+-- x"4402800B", -- R11 (mode=singlePLL, 0delay, SYNC=enabled, active=high, SYNC_QUAL=1?, auto_sync=1, sSYNC=input, externalXTAL=disabled)
+-- x"030C00aC", -- R12 (LD=0, no force SYNC, no DAC tracking, no HOLDOVER)
+-- x"3B00800D", -- R13 (HOLDOVER pin=uwire, status pins=0, no DLD1DET, status CLKin=0, CLKin not used)
+-- x"0000000E", -- R14 (LOS after 1200ns, CLKin not used, no DAC trip)
+-- x"8000800F", -- R15 (MAN_DAC=512, disabled, HOLDOVER count=512, disabled)
+-- x"01550410", -- R16 (xtal=1.65V, fixed pattern)
+-- x"000000D8", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm, delay=0ps, window=40ns) -- DD0000D8
+-- x"010100D9", -- R25 (DAC clkdiv=4, PLL2 DLD cont=1024)
+-- x"83A8001A", -- R26 (PLL2 window=3.7ns, no 2*frequ, neg slope, chargepump=100u, PLL2 DLD count=8192???, CPout2=active)
+-- x"0008003B", -- R27 (PLL1 not used: neg slope, div=1, PLL1 DLD count=8192, CPout1=tristate)
+-- x"0010005C", -- R28 (PLL2 R_divider=1, PLL1 N_divider=1)
+-- x"0000015D", -- R29 (OSCin=0..63MHz, <100MHz, PLL2 N_CALdivider=10)
+-- x"0400015E", -- R30 (N_prescaler=4, N_divider=10)
+---- X"00000500", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 62.5MHz) ???
+-- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+-- );
+-- CONSTANT TAB80 : RomType := -- 80MHz
+ -- (
+ -- x"00020000", -- R0 (Reset=1)
+ -- x"00000400", -- R0 (Reset=0)
+ -- X"00000400", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz)
+ -- X"00000401", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+ -- X"00000402", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+ -- X"00000403", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+ -- X"00000404", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+ -- X"00000405", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 80MHz)
+ -- x"11110006", -- R6 (OUT 3,2,1,0:LVDS, no delay)
+ -- x"11110007", -- R7 (OUT 7,6,5,4:LVDS, no delay)
+ -- x"11110008", -- R8 (OUT 11,10,9,8:LVDS, no delay)
+ -- x"55555549", -- R9 (fixed pattern)
+ -- x"0000806A", -- R10 (OSCout1=LVPECL-700mV, OSCout0=disabled, OSCout1,0=disabled, OSC0,1=bypass_divider, OSCoutDIV=8, VCOdiv=1, FEEDbackMUX=CLKout6)
+ -- x"4400800B", -- R11 (mode=singlePLL, 0delay, SYNC=enabled, active=high, SYNC_QUAL=0?, auto_sync=1, sSYNC=input, externalXTAL=disabled)
+ -- x"030000aC", -- R12 (LD[31..27]=0, LD_type[26..24]=3, SYNC_PLLX_DLD[23..22]=0, EN_TRACK[8]=disable, force_SYNC, no DAC tracking, no HOLDOVER)
+ -- x"6B00800D", --3B... R13 (HOLDOVER pin=uwire, status pins=0, no DLD1DET, status CLKin=0, CLKin not used)
+ -- x"0000000E", -- R14 (LOS after 1200ns, CLKin not used, no DAC trip)
+ -- x"8000800F", -- R15 (MAN_DAC=512, disabled, HOLDOVER count=512, disabled)
+ -- x"01550410", -- R16 (xtal=1.65V, fixed pattern)
+ -- x"000000D8", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm, delay=0ps, window=40ns) -- DD0000D8
+ -- x"010100D9", -- R25 (DAC clkdiv=4, PLL2 DLD cont=1024)
+ -- x"83A8001A", -- R26 (PLL2 window=3.7ns, no 2*frequ, neg slope, chargepump=100u, PLL2 DLD count=8192???, CPout2=active)
+ -- x"0008003B", -- R27 (PLL1 not used: neg slope, div=1, PLL1 DLD count=8192, CPout1=tristate)
+ -- x"0010005C", -- R28 (PLL2 R_divider=1, PLL1 N_divider=1)
+ -- x"0100015D", -- R29 (OSCin=63..127MHz, <100MHz, PLL2 N_CALdivider=10)
+ -- x"0400015E", -- R30 (N_prescaler=4, N_divider=10)
+--//-- X"00000400", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz) ???
+ -- x"000b001F" -- R31 (ReadbackReg=11 Regs:unlocked) 001F001F
+ -- );
+
+
+-- CONSTANT TAB_orig : RomType := -- test
+ -- (
+ -- x"00020000", -- R0 (Reset=1)
+ -- x"00000400", -- R0 (Reset=0)
+ -- X"00000400", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=32 OUT0,1 80MHz)
+ -- X"00000401", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+ -- X"00000402", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+ -- X"00000403", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+ -- X"00000404", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+ -- X"00000405", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+ -- x"11110006", -- R6 (OUT 3,2,1,0:LVDS, no delay)
+ -- x"11110007", -- R7 (OUT 7,6,5,4:LVDS, no delay) x"61160007", for cmos_out
+ -- x"11110008", -- R8 (OUT 11,10,9,8:LVDS, no delay)
+ -- x"55555549", -- R9 (fixed pattern)
+ -- x"1000480A", -- R10 (OSCout1[31..30]=700mV, OSCout0[27..24]=disabled, OSCout1,0[23..22]=disabled, OSC0,1[21..20]=bypass_divider, PD_OSCin[19]=0(powered), OSCoutDIV[18..16]=8, VCOdiv[12]=select, EN_FEEDBACK_MUX[11]=1, VCOdiv[10..8]=8 FEEDbackMUX[7..5]=3=CLKout6)
+ -- x"4402800B", -- R11 (mode[31..27]=singlePLL+0delay, SYNC[26]=enabled, NO_SYNC_CLKoutX_Y[25..20]=0, SYNC_mux[19..18]=0, SYNC_QUAL[17]=1, sync[16]=0=high, auto_sync[15]=1, sSYNC[14..12]=input, externalXTAL[5]=disabled)
+ -- x"0300006C", -- R12 (LD[31..27]=0, LD_type[26..24]=3, SYNC_PLLX_DLD[23..22]=0, EN_TRACK[8]=disable, HOLDOVER[7..6]=disable)
+ -- x"9300000D", --..3B R13 (HOLDOVER_pin[31..27]=uwire, output[26..25]=pushpull, CLK1_mux[22..20]=0, CLK0_mux[18..16]=0, DLD1DET[15]=0,CLKin[14..12]=0, CLKin_mode[11..9]=0, CLKin[8]=high, EN_CLKinX[6..5]=0
+ -- x"0000000E", -- R14 (LOS[31..30] after 1200ns, LOS[28]=disabled, CLKin[26..24], CLKinX_BUF_TYPE[21..20]=0, DAC_trip[19..14][11..6]=0, EN_VTUNE_RAIL_DET[5]=0)
+ -- x"0000004F", -- R15 (MAN_DAC [31:22]=0 (sets dac value when in manual DAC mode, set to 0), EN_MAN_DAC[20]=0 (enables manual DAC), HOLDOVER DLD+CNT[19:6]=1 (how many clocks of PLL1 PDF before HOLDOVER mode is exited. 1, I guess, if we're not using holdover mode), FORCE_HOLDOVER[5]=0,(diabled))
+ -- x"01550410", -- R16 (xtal=1.65V, fixed pattern)
+ -- x"00000018", -- R24 (PLL2_C4_LF[31:28]=0(10pF), PLL2_C3_LF[27:23]=0(10pF), PLL2_R4_LF[22:20]=0(200 Ohm), PLL2_R3_LF[18:16]=0(200 Ohm), PLL1_N_DLY[14:12]=0 (PLL1, doesn't matter and setting to 0 delay), PLL1_R_DLY[10:8]=0(same), PLL1_WIND_SIZE[7:6]=0 (setting 0)
+ -- x"00400059", -- R25 (DAC_CLK_DIV[31:22]=1 (PLL1 relevant, setting to 1), PLL1_DLD_CNT[19:6]=1,
+ -- x"8fA0801A", -- R26 (PLL2 window[31:30]=3.7ns, PLL2_doublefreq[29]=0, slope[28]=neg, chargepump[27..26]=max?100u, PLL2 DLD count19..6]=1024, CPout2[5]=active)
+ -- x"0008003B", -- R27 (PLL1 not used: slope[28]=neg, div=1, PLL1 DLD count=8192, CPout1=tristate)
+ -- x"0018001C", -- R28 (PLL2 R_divider[31..20]=1, PLL1 N_divider[19..6]=maxbit)
+ -- x"0100009D", -- R29 (OSCin[26..24]=63..127MHz, phasedet[23]<100MHz, PLL2 N_CALdivider[22..5]=DIVX*PLL2_N/PLL2_P=32*1/8=4)
+ -- x"0000003E", -- R30 (N_prescaler=PLL2_P[26:24]=8, not used, PLL1_N_divider[22..5]=1)
+-- x"00000f00", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz) ???
+ -- x"002b001F" -- R31 (LE must be high ReadbackReg=2 Regs:unlocked) 001F001F
+ -- );
+
+constant TAB : RomType :=
+ (
+ x"00020000", -- R0 (Reset=1)
+ x"00000400", -- R0 (Reset=0)
+ X"00000400", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=32 OUT0,1 80MHz)
+ X"00000401", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+ X"00000402", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+ X"00000403", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+ X"00000404", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+ X"00000405", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+ x"11110006", -- R6 (OUT 3,2,1,0:LVDS, no delay)
+ x"11110007", -- R7 (OUT 7,6,5,4:LVDS, no delay) x"61160007", for cmos_out
+ x"11110008", -- R8 (OUT 11,10,9,8:LVDS, no delay)
+ x"55555549", -- R9 (fixed pattern)
+ x"1000486A", -- R10 (OSCout1[31..30]=700mV, OSCout0[27..24]=disabled, OSCout1,0[23..22]=disabled, OSC0,1[21..20]=bypass_divider, PD_OSCin[19]=0(powered), OSCoutDIV[18..16]=8, VCOdiv[12]=select, EN_FEEDBACK_MUX[11]=1, VCOdiv[10..8]=8 FEEDbackMUX[7..5]=3=CLKout6)
+ x"4402a00B", -- R11 (mode[31..27]=singlePLL+0delay, SYNC[26]=enabled, NO_SYNC_CLKoutX_Y[25..20]=0, SYNC_mux[19..18]=0, SYNC_QUAL[17]=1, sync[16]=0=high, auto_sync[15]=1, sSYNC[14..12]=input, externalXTAL[5]=disabled)
+ x"030C006C", -- R12 (LD[31..27]=0, LD_type[26..24]=3, SYNC_PLLX_DLD[23..22]=0, EN_TRACK[8]=disable, HOLDOVER[7..6]=disable)
+ x"2300000D", --..3B R13 (HOLDOVER_pin[31..27]=status, output[26..25]=pushpull, CLK1_mux[22..20]=0, CLK0_mux[18..16]=0, DLD1DET[15]=0,CLKin[14..12]=0, CLKin_mode[11..9]=0, CLKin[8]=high, EN_CLKinX[6..5]=0
+ x"0000000E", -- R14 (LOS[31..30] after 1200ns, LOS[28]=disabled, CLKin[26..24], CLKinX_BUF_TYPE[21..20]=0, DAC_trip[19..14][11..6]=0, EN_VTUNE_RAIL_DET[5]=0)
+ x"0000004F", -- R15 (MAN_DAC [31:22]=0 (sets dac value when in manual DAC mode, set to 0), EN_MAN_DAC[20]=0 (enables manual DAC), HOLDOVER DLD+CNT[19:6]=1 (how many clocks of PLL1 PDF before HOLDOVER mode is exited. 1, I guess, if we're not using holdover mode), FORCE_HOLDOVER[5]=0,(diabled))
+ x"01550410", -- R16 (xtal=1.65V, fixed pattern)
+ x"88110018", -- R24 (PLL2_C4_LF[31:28]=8(29pF), PLL2_C3_LF[27:23]=0(29pF), PLL2_R4_LF[22:20]=1(1k), PLL2_R3_LF[18:16]=1(1k), PLL1_N_DLY[14:12]=0 (PLL1, doesn't matter and setting to 0 delay), PLL1_R_DLY[10:8]=0(same), PLL1_WIND_SIZE[7:6]=0 (setting 0)
+ x"00400059", -- R25 (DAC_CLK_DIV[31:22]=1 (PLL1 relevant, setting to 1), PLL1_DLD_CNT[19:6]=1,
+ x"87A0801A", -- R26 (PLL2 window[31:30]=3.7ns, PLL2_doublefreq[29]=0, slope[28]=neg, chargepump[27..26]=11=3200,01=400,00=100u, PLL2 DLD count19..6]=1024, CPout2[5]=active)
+ x"0008003B", -- R27 (PLL1 not used: slope[28]=neg, div=1, PLL1 DLD count=8192, CPout1=tristate)
+ x"0018001C", -- R28 (PLL2 R_divider[31..20]=1, PLL1 N_divider[19..6]=maxbit)
+ x"0100009D", -- R29 (OSCin[26..24]=63..127MHz, phasedet[23]<100MHz, PLL2 N_CALdivider[22..5]=DIVX*PLL2_N/PLL2_P=32*1/8=4)
+ x"0000003E", -- R30 (N_prescaler=PLL2_P[26:24]=8, not used, PLL1_N_divider[22..5]=1)
+-- x"00000f00", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz) ???
+ x"002b001F" -- R31 (LE must be high ReadbackReg=2 Regs:unlocked) 001F001F
+ );
+
+--CONSTANT TAB_Pawel : RomType := -- |Pawel
+-- (
+-- x"80020140", --R0 (CLKout_1_PD = 1, RESET=1, CLKout0_1_DIV=10)
+-- x"000003C0", --R0 (CLKout0_1_DIV=30)
+-- x"000003C0", --R0 (CLKout0_1_DIV=30)
+-- x"000003C0", --R0 (CLKout0_1_DIV=30)
+-- x"000003C1", --R1 (CLKout2_3_DIV=30)
+-- x"00000602", --R2 (CLKout4_5_DIV=48) --35
+-- --00000000000000000000010110100010
+-- x"00000603", --R3 (CLKout6_7_DIV=48)
+-- x"000003C4", --R4 (CLKout8_9_DIV=30)
+-- x"000003C5", --R5 (CLKout10_11_DIV=30)
+-- x"11110006", --R6 (CLKout3_TYPE=1, CLKout2_TYPE=1, CLKout1_TYPE=1, CLKout0_TYPE=1)
+-- x"11110007", --R7 (CLKout7_TYPE=1, CLKout6_TYPE=1, CLKout5_TYPE=1, CLKout4_TYPE=1)
+-- x"11110008", --R8 (CLKout11_TYPE=1, CLKout10_TYPE=1, CLKout9_TYPE=1, CLKout8_TYPE=1)
+-- x"55555549", --R9 (fixed pattern)
+-- x"910141CA", --R10 (OSCout1_LVPECL_AMP=3(-1600mV), OSCout0_TYPE=1(LVDS), EN_OSCout1[23]=0 (disabled), EN_OSCout0[22]=0 (disabled), OSCout1_MUX[21]=0 (bypass MUX), OSC_out1_MUX[20]=0(bypass MUX), PD_OSCin[19]=0(powered), OSCout_DIV[18:16]=2(divide by 2), VCO_MUX[12]=0(select VCO), EN_FEEDBACK_MUX[11]=0 (feedback mux powered down), VCO_DIV[10:8]=2(divide by 2), FEEDBACK_MUX[7:5]=3(guess it doens't matter. taking FBCLKin)
+-- x"2400800D", --R11
+-- x"130C006C", --R12 (LD_MUX[31:27]=2 (PLL2 DLD (digital lock detect)), LD_TYPE[26:24]=3 (output push-pull), SYNC_PLL2_DLD[23]=0? (sync not forced), SYNC_PLL1_DLD[22]=0? (sync not forced), EN_TRACK[8]=0 (tracks the PLL1` which we're not using, set to 0), HOLDOVER_MODE[7:6]=1 (disabled))
+-- x"0301880D", --R13 (holdover_mux[31:27]=0 (logic low), holdover_type[26:24]=3(output (push-pull)), status_clkin1_mux[22:20]=0(logic low), status_clkin0_Type[18:16]=1 (they're both disconnected as far as I can tell, thus we want pull-up), disable_dld1_det[15]=1(disables, because we won't use PLL1), status+clkin0_mux[14:12]=0(logic low), clkin_select_mode[11:9]=4(I think this is the case, take auto, because I don't think it will be used), clk_in_select_inv[7]=0 (not inversed), en_clkin1[6]=0 (disable), en_clkin0[5]=0 (diable)
+-- x"013FC00E", --R14 !!!see above!!!
+-- x"0000004F", --R15 (MAN_DAC [31:22]=0 (sets dac value when in manual DAC mode, set to 0), EN_MAN_DAC[20]=0 (enables manual DAC), HOLDOVER DLD+CNT[19:6]=1 (how many clocks of PLL1 PDF before HOLDOVER mode is exited. 1, I guess, if we're not using holdover mode), FORCE_HOLDOVER[5]=0,(diabled))
+-- x"01550410", --R16 (XTAL_LVL[31:30]=0 (sets the peak amplitude on the tunable crystal. --assuming 0, the lowest))
+-- x"00000018", --R24 (PLL2_C4_LF[31:28]=0(10pF), PLL2_C3_LF[27:23]=0(10pF), PLL2_R4_LF[22:20]=0(200 Ohm), PLL2_R3_LF[18:16]=0(200 Ohm), PLL1_N_DLY[14:12]=0 (PLL1, doesn't matter and setting to 0 delay), PLL1_R_DLY[10:8]=0(same), PLL1_WIND_SIZE[7:6]=0 (setting 0)
+-- x"00400059", --R25 (DAC_CLK_DIV[31:22]=1 (PLL1 relevant, setting to 1), PLL1_DLD_CNT[19:6]=1,
+-- x"4FA8001A", --R26 (PLL2_WIND_SIZE[31:30]=2 (has to be =2 according to documentation), EN_PLL2_REF_2X[29]=0 (according to schematics), PLL2_CP_POL[28]=0 (must be negative to use internal VCO), PLL2_CP_GAIN[27:26]=3 (according to LMK03806), PLL2_DLD_CNT[19:6]=2000 (leftmost bit =1 according to LMK03806), PLL2_CP_TRI=0 (according to LMK03806)
+-- x"0000005B", --R27 (PLL1_CP_POL[28]=0, PLL1_CP_GAIN[27:26]=0, CLKin1_PreR_DIV[23:22]=0, CLKin0_PreR_DIV[21:20]=0, PLL1_R[19:6]=1, PLL1_CP_TRI=0(because PLL1_CP_GAIN is not equal to XXXX)
+-- x"0010005C", --R28 (PLL2_R[31:20]=1, PLL1_N[19:6]=1(not used))
+-- --!!! 0000 0000 0XXX XXXX XXXX XXXX XX11 1101 --R29
+-- --x"0000003D", --R29 !!!see above!!!
+-- x"0100021D", --R29
+-- x"0200021E", --R30 (PLL2_P[26:24]=2, PLL2_N[22:5]=16)
+-- x"001F001F" --R31 (READBACK_LE[21] (guessing low)=0, READBACK_ADDRESS[20:16]=31 (from LMK03806), uWire_LOCK[5]=0 (from LMK03806)n
+-- );
+
+type stage_type is (waiting,starting,DATAu_set,CLKu_high,CLKu_low,LEu_wait,
+ LEu_high,LEu_high0,LEu_high1,LEu_high2,LEu_high3,LEu_high4,LEu_high5,LEu_low,reading0,reading1,lockdelay);
+signal stage_S : stage_type := waiting;
+
+signal cnt_dly : std_logic_vector(3 downto 0) := (others => '0');
+signal regcount_S : integer range 0 to NROFREGS-1 := 0;
+signal bitcount_S : integer range 0 to 31 := 31;
+signal lockcount_S : std_logic_vector(11 downto 0) := (others => '0');
+
+signal boot_PLL_S : std_logic := '0';
+signal CLKu_S : std_logic;
+signal DATAu_S : std_logic;
+signal LEu_S : std_logic;
+signal SYNC_S : std_logic;
+
+
+--------------------------------------------------------------------
+BEGIN
+
+
+booting <= '0' when (stage_S=waiting) else '1';
+SYNC_S <= '0';
+SYNC <= SYNC_S;
+CLKu <= CLKu_S;
+DATAu <= DATAu_S;
+LEu <= LEu_S;
+SYNC <= SYNC_S;
+
+--******************************************************************
+-- PLL BOOT STATEMACHINE
+--******************************************************************
+
+process(clock,reset)
+begin
+ if reset = '1' then
+ stage_S <= waiting;
+ CLKu_S <= '0';
+ DATAu_S <= '0';
+ LEu_S <= '0';
+ elsif rising_edge(clock) then
+--// boot_PLL_S <= boot_PLL;
+ case stage_S is
+ when waiting =>
+ CLKu_S <= '0';
+ DATAu_S <= '0';
+ LEu_S <= '0';
+ bitcount_S <= 31;
+ regcount_S <= 0;
+--// if (boot_PLL='1') then --and (boot_PLL_S='0') then
+ if (boot_PLL='1') or (boot_PLL_S='1') then --and (boot_PLL_S='0') then
+ stage_S <= starting;
+ end if;
+ cnt_dly <= (others => '0');
+ lockcount_S <= (others => '0');
+ when starting =>
+ CLKu_S <= '0';
+ DATAu_S <= '0';
+ LEu_S <= '0';
+ stage_S <= DATAu_set;
+ when DATAu_set =>
+ CLKu_S <= '0';
+ DATAu_S <= TAB(regcount_S)(bitcount_S);
+ LEu_S <= '0';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= CLKu_high;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when CLKu_high =>
+ CLKu_S <= '1';
+ LEu_S <= '0';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= CLKu_low;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when CLKu_low =>
+ CLKu_S <= '0';
+ LEu_S <= '0';
+ cnt_dly <= (others => '0');
+ if bitcount_S>0 then
+ bitcount_S <= bitcount_S-1;
+ stage_S <= DATAu_set;
+ else
+ stage_S <= LEu_wait;
+ end if;
+ when LEu_wait =>
+ CLKu_S <= '0';
+ LEu_S <= '0';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= LEu_high;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when LEu_high =>
+ CLKu_S <= '0';
+ LEu_S <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ if conv_integer(unsigned(TAB(regcount_S)(4 downto 0)))<6 then
+ stage_S <= LEu_high0;
+ else
+ stage_S <= LEu_low;
+ end if;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when LEu_high0 =>
+ CLKu_S <= '1';
+ LEu_S <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= LEu_high1;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when LEu_high1 =>
+ CLKu_S <= '0';
+ LEu_S <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= LEu_high2;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when LEu_high2 =>
+ CLKu_S <= '1';
+ LEu_S <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= LEu_high3;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when LEu_high3 =>
+ CLKu_S <= '0';
+ LEu_S <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= LEu_high4;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when LEu_high4 =>
+ CLKu_S <= '1';
+ LEu_S <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= LEu_high5;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when LEu_high5 =>
+ CLKu_S <= '0';
+ LEu_S <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= LEu_low;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when LEu_low =>
+ CLKu_S <= '0';
+-- LEu_S <= '0';
+ if regcount_S<NROFREGS-1 then
+ bitcount_S <= 31;
+ LEu_S <= '0';
+ regcount_S <= regcount_S+1;
+ stage_S <= DATAu_set;
+ else
+ bitcount_S <= 26;
+ LEu_S <= '1';
+ stage_S <= reading0;
+ end if;
+ when reading0 =>
+ CLKu_S <= '0';
+ LEu_S <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ stage_S <= reading1;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when reading1 =>
+ CLKu_S <= '1';
+ LEu_S <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ if bitcount_S>0 then
+ bitcount_S <= bitcount_S-1;
+ stage_S <= reading0;
+ else
+ bitcount_S <= 31;
+ stage_S <= lockdelay;
+ end if;
+ else
+ cnt_dly <= cnt_dly + 1;
+ end if;
+ when lockdelay =>
+ if lockcount_S(lockcount_S'left)='0' then
+ lockcount_S <= lockcount_S+1;
+ else
+ stage_S <= waiting;
+ end if;
+ when others =>
+ stage_S <= waiting;
+ end case;
+ end if;
+end process;
+
+
+
+END Behavioral;
+
+
--- /dev/null
+-----------------------------------------------------------
+-- LTM9009 SLOW CONTROL UNIT --
+-----------------------------------------------------------
+-- Device: xc7vlx160t-1ffG484 --
+--
+-- created by P. Marciniewski --
+-- Uppsala University, Dept of Physics and Astronomy --
+-----------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.panda_pkg.all;
+use work.util_pack.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+
+entity LTM9009_SLOW_CONTROL is
+ PORT(
+ CLK75 : in std_logic;
+ RES : in std_logic;
+ SCK : out std_logic;
+ SDI : in std_logic_vector(7 downto 0);
+ SDO : out std_logic;
+ CS : out std_logic_vector(7 downto 0)
+ );
+end LTM9009_SLOW_CONTROL;
+
+----------------------------------------------------------------
+
+architecture Behavioral of LTM9009_SLOW_CONTROL is
+
+ signal clk_cnt : std_logic_vector(6 downto 0);
+ signal sck_i : std_logic;
+ signal sdo_sh : std_logic_vector(15 downto 0);
+ signal vio_vector : std_logic_vector(19 downto 0);
+ signal bit_cnt : std_logic_vector(3 downto 0);
+ signal sequencer_stm : std_logic_vector(1 downto 0);
+ signal adc_adr : std_logic_vector(2 downto 0);
+ signal adc_rd : std_logic;
+ signal sdi_sh : std_logic_vector(7 downto 0);
+ signal adc_ctrl_ila_vector : std_logic_vector(31 downto 0);
+ signal adc_ctrl_vio_vector : std_logic_vector(19 downto 0);
+
+
+BEGIN
+
+-- vio_vector <= "00010000000101101001";
+ adc_rd <= vio_vector(15);
+ adc_adr <= vio_vector(18 downto 16);
+
+----------------------------------------------------------------------------------------------
+-- CLOCK DIVIDER
+----------------------------------------------------------------------------------------------
+
+ process(RES,CLK75)
+ begin
+ if RES = '1' then
+ clk_cnt <= "0000000";
+ elsif rising_edge(CLK75) then
+ clk_cnt <= clk_cnt + 1;
+ end if;
+ end process;
+
+ sc_clk_bufg: BUFG
+ PORT MAP (
+-- I => clk_cnt(1),
+ I => clk_cnt(6),
+ O => sck_i
+ );
+
+----------------------------------------------------------------------------------------------
+-- SEQUENCER STATE MACHINE
+----------------------------------------------------------------------------------------------
+
+ process(RES,sck_i)
+ begin
+ if RES = '1' then
+ sdo_sh <= x"0000";
+ bit_cnt <= x"0";
+ sequencer_stm <= "00";
+
+ elsif rising_edge(sck_i) then
+
+ vio_vector <= adc_ctrl_vio_vector;
+
+ case sequencer_stm is
+ when "00" =>
+ sdo_sh <= vio_vector(15 downto 0);
+ bit_cnt <= x"0";
+ if vio_vector(19) = '1' then
+ sequencer_stm <= "01";
+ end if;
+ when "01" =>
+ sdo_sh <= sdo_sh(14 downto 0) & '0';
+ if bit_cnt = 15 then
+ sequencer_stm <= "10";
+ else
+ bit_cnt <= bit_cnt + 1;
+ end if;
+ when "10" =>
+ if vio_vector(19) = '0' then
+ sequencer_stm <= "00";
+ end if;
+ when others =>
+ sequencer_stm <= "00";
+ end case;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------------------
+-- INPUT MULTIPLEXER
+----------------------------------------------------------------------------------------------
+
+ process(RES,sck_i)
+ begin
+ if RES = '1' then
+ sdi_sh <= x"00";
+ elsif falling_edge(sck_i) then
+ if sequencer_stm = "01" then
+ if (adc_rd = '1' and bit_cnt > 7) then
+ sdi_sh(0) <= SDI(slv2int(adc_adr));
+ sdi_sh(7 downto 1) <= sdi_sh(6 downto 0);
+ end if;
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------------------
+-- OUTPUT BUFFERS
+----------------------------------------------------------------------------------------------
+
+ SCK <= not clk_cnt(1) when sequencer_stm = "01" else '1';
+ SDO <= sdo_sh(15) when sequencer_stm = "01" else '1';
+ CS_DEMUX: for i in 0 to 7 generate
+ process(sequencer_stm, adc_adr)
+ begin
+ if sequencer_stm = "01" then
+ if (int2slv(i,4) = '0' & adc_adr) then
+ CS(i) <= '0';
+ else
+ CS(i) <= '1';
+ end if;
+ else
+ CS(i) <= '1';
+ end if;
+ end process;
+ end generate;
+-- adc_ctrl_vio_vector <= "00000000000000000000";
+
+END Behavioral;
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--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx\r
--- \ \ \/ Version: \r
--- \ \ Filename: AdcClock.vhd\r
--- / / Date Last Modified: 16 Jun 09\r
--- /___/ /\ Date Created: 08/06/06\r
--- \ \ / \\r
--- \___\/\___\\r
--- \r
--- Device: Virtex-6\r
--- Author: Marc Defossez\r
--- Entity Name: AdcClock\r
--- Purpose: High-speed local clock control for an interface between a FPGA and a\r
--- Texas Instruments ADC.\r
--- Tools: ISE - XST\r
--- Limitations: none\r
---\r
--- Revision History:\r
--- Rev. \r
---\r
------------------------------------------------------------------------------------------------\r
--- Naming Conventions:\r
--- active low signals: "*_n"\r
--- clock signals: "clk", "clk_div#", "clk_#x"\r
--- reset signals: "rst", "rst_n"\r
--- generics: "C_*"\r
--- user defined types: "*_TYPE"\r
--- state machine next state: "*_ns"\r
--- state machine current state: "*_cs"\r
--- combinatorial signals: "*_com"\r
--- pipelined or register delay signals: "*_d#"\r
--- counter signals: "*cnt*"\r
--- clock enable signals: "*_ce"\r
--- internal version of output port: "*_i"\r
--- device pins: "*_pin"\r
--- ports: "- Names begin with Uppercase"\r
--- processes: "*_PROCESS"\r
--- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
------------------------------------------------------------------------------------------------\r
---\r
-library IEEE;\r
- use IEEE.std_logic_1164.all;\r
- use IEEE.std_logic_UNSIGNED.all;\r
- use IEEE.std_logic_arith.all;\r
-library UNISIM;\r
- use UNISIM.VCOMPONENTS.all;\r
------------------------------------------------------------------------------------------------\r
--- Entity pin description\r
------------------------------------------------------------------------------------------------\r
------------------------------------------------------------------------------------------------\r
-entity AdcClock is\r
- generic (\r
- C_BufioLoc : string := "BUFIODQS_X0Y12";\r
- C_BufrLoc : string := "BUFR_X0Y6";\r
- C_AdcBits : integer := 16;\r
- C_StatTaps : integer := 16\r
- );\r
- port (\r
- BitClk : in std_logic;\r
- BitClkRst : in std_logic;\r
- BitClkEna : in std_logic;\r
- BitClkReSync : in std_logic;\r
- BitClkDivReset : in std_logic;\r
- BitClk_MonClkOut : out std_logic; -- CLK output\r
- BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input\r
- BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output\r
- BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input\r
- BitClkAlignWarn : out std_logic;\r
- BitClkInvrtd : out std_logic;\r
- BitClkDone : out std_logic\r
- );\r
-end AdcClock;\r
------------------------------------------------------------------------------------------------\r
--- Arcitecture section\r
------------------------------------------------------------------------------------------------\r
-architecture AdcClock_struct of AdcClock is\r
------------------------------------------------------------------------------------------------\r
--- Component Instantiation\r
------------------------------------------------------------------------------------------------\r
--- Components are instantiated by means / through the use of library references.\r
------------------------------------------------------------------------------------------------\r
--- Constants, Signals and Attributes Declarations\r
------------------------------------------------------------------------------------------------\r
--- Constants\r
-constant Low : std_logic := '0';\r
-constant LowNibble : std_logic_vector(4 downto 0) := "00000";\r
-constant High : std_logic := '1';\r
--- Signals\r
-signal IntBitClkRst : std_logic;\r
----------- ISRDS signals ------------------\r
-signal IntClkCtrlDlyCe : std_logic;\r
-signal IntClkCtrlDlyInc : std_logic;\r
-signal IntClkCtrlDlyRst : std_logic;\r
-\r
-signal IntBitClk_Ddly : std_logic;\r
-signal IntBitClk : std_logic;\r
-signal IntClkCtrlIsrdsMtoS1 : std_logic;\r
-signal IntClkCtrlIsrdsMtoS2 : std_logic;\r
-signal IntClkCtrlOut : std_logic_vector(7 downto 0);\r
----------- Controller signals -------------\r
-signal IntCal : std_logic;\r
-signal IntVal : std_logic;\r
-signal IntCalVal : std_logic_vector (1 downto 0);\r
-signal IntProceedCnt : std_logic_vector (2 downto 0);\r
-signal IntproceedCntTc : std_logic;\r
-signal IntproceedCntTc_d : std_logic;\r
-signal IntProceed : std_logic;\r
-signal IntProceedDone : std_logic;\r
-\r
-type StateType is (Idle, A, B, C, D, E, F, G, G1, H, K, K1, K2, IdlyIncDec, Done);\r
-signal State : StateType;\r
-signal ReturnState : StateType;\r
-\r
-signal PassedSubState : std_logic;\r
-signal IntNumIncDecIdly : std_logic_vector (3 downto 0);\r
-signal IntAction : std_logic_vector (1 downto 0);\r
-signal IntClkCtrlDone : std_logic;\r
-signal IntClkCtrlAlgnWrn : std_logic;\r
-signal IntClkCtrlInvrtd : std_logic;\r
-signal IntTurnAroundBit : std_logic;\r
-signal IntCalValReg : std_logic_vector (1 downto 0);\r
-signal IntTimeOutCnt : std_logic_vector (3 downto 0);\r
-signal IntStepCnt : std_logic_vector (3 downto 0);\r
--- Attributes\r
-attribute LOC : string;\r
- attribute LOC of AdcClock_I_Bufio : label is C_BufioLoc;\r
--- The BUFR is generated through a generate statement and therefore the LOC attribute\r
--- must be place into the generate statement.\r
--- See the BUFR generation down in the source code.\r
------------------------------------------------------------------------------------------------\r
-signal reset_clockdiv_S : std_logic;\r
- \r
- \r
-begin\r
------------------------------------------------------------------------------------------------\r
--- Bit clock capture ISERDES Master-Slave combination\r
------------------------------------------------------------------------------------------------\r
---\r
-AdcClock_I_Iodly : IODELAYE1\r
- generic map (\r
- SIGNAL_PATTERN => "CLOCK",\r
- REFCLK_FREQUENCY => 200.0, \r
- HIGH_PERFORMANCE_MODE => TRUE,\r
- DELAY_SRC => "I",\r
- CINVCTRL_SEL => FALSE,\r
- IDELAY_TYPE => "VARIABLE",\r
- IDELAY_VALUE => C_StatTaps,\r
- ODELAY_TYPE => "FIXED",\r
- ODELAY_VALUE => 0\r
- )\r
- port map (\r
- DATAIN => Low, -- in input from FPGA fabric\r
- IDATAIN => BitClk, -- in input from IOB\r
- ODATAIN => Low, -- in input from I/O SERDES\r
- CLKIN => Low, -- in input from BUFIO. BUFG, or BUFR\r
- CE => IntClkCtrlDlyCe, -- in\r
- INC => IntClkCtrlDlyInc, -- in\r
- C => BitClk_RefClkIn, -- in\r
- RST => IntClkCtrlDlyRst, -- in \r
- T => Low, -- in\r
- DATAOUT => IntBitClk_Ddly, -- out Delayed data\r
- CINVCTRL => Low, -- in\r
- CNTVALUEIN => LowNibble, -- in [4:0]\r
- CNTVALUEOUT => open -- out [4:0]\r
- );\r
-IntClkCtrlDlyRst <= BitClkRst;\r
---\r
-AdcClock_I_Isrds_Master : ISERDESE1\r
- generic map (\r
- SERDES_MODE => "MASTER", -- \r
- INTERFACE_TYPE => "NETWORKING",-- \r
- IOBDELAY => "IBUF", -- \r
- DATA_RATE => "SDR", -- \r
- DATA_WIDTH => 8, --\r
- DYN_CLKDIV_INV_EN => FALSE, -- \r
- DYN_CLK_INV_EN => FALSE, -- \r
- NUM_CE => 1, -- \r
- OFB_USED => FALSE -- \r
- )\r
- port map (\r
- D => BitClk, -- in Clock from clock input IBUFDS\r
- DDLY => IntBitClk_Ddly, -- in\r
- DYNCLKDIVSEL => Low, -- in\r
- DYNCLKSEL => Low, -- in\r
- OFB => Low, -- in\r
- BITSLIP => Low, -- in !!!!!\r
- CE1 => BitClkEna, -- in\r
- CE2 => Low, -- in\r
- RST => IntBitClkRst, -- in\r
- CLK => BitClk_MonClkIn, -- in Clock from BUFIO.O = BitClk\r
- CLKB => Low, -- in\r
- CLKDIV => BitClk_RefClkIn, -- in Clock from BUFR.O = BitClkDiv\r
- OCLK => Low, -- in\r
- SHIFTOUT1 => IntClkCtrlIsrdsMtoS1,-- out\r
- SHIFTOUT2 => IntClkCtrlIsrdsMtoS2,-- out\r
- O => IntBitClk, -- out Clock to BUFIO.I\r
- Q1 => IntClkCtrlOut(0), -- out\r
- Q2 => IntClkCtrlOut(1), -- out\r
- Q3 => IntClkCtrlOut(2), -- out\r
- Q4 => IntClkCtrlOut(3), -- out\r
- Q5 => IntClkCtrlOut(4), -- out\r
- Q6 => IntClkCtrlOut(5), -- out\r
- SHIFTIN1 => Low, -- in\r
- SHIFTIN2 => Low -- in\r
- );\r
---\r
-AdcClock_I_Isrds_Slave : ISERDESE1\r
- generic map (\r
- SERDES_MODE => "SLAVE", -- \r
- INTERFACE_TYPE => "NETWORKING",-- \r
- IOBDELAY => "NONE", -- \r
- DATA_RATE => "SDR", -- \r
- DATA_WIDTH => 8, --\r
- DYN_CLKDIV_INV_EN => FALSE, -- \r
- DYN_CLK_INV_EN => FALSE, -- \r
- NUM_CE => 1, -- \r
- OFB_USED => FALSE -- \r
- )\r
- port map (\r
- D => Low, -- in\r
- DDLY => Low, -- in\r
- DYNCLKDIVSEL => Low, -- in\r
- DYNCLKSEL => Low, -- in\r
- OFB => Low, -- in\r
- BITSLIP => Low, -- in !!!!!\r
- CE1 => BitClkEna, -- in\r
- CE2 => Low, -- in\r
- RST => IntBitClkRst, -- in\r
- CLK => BitClk_MonClkIn, -- in\r
- CLKB => Low, -- in\r
- CLKDIV => BitClk_RefClkIn, -- in\r
- OCLK => Low, -- in\r
- SHIFTOUT1 => open, -- out\r
- SHIFTOUT2 => open, -- out\r
- O => open, -- out\r
- Q1 => open, -- out\r
- Q2 => open, -- out\r
- Q3 => IntClkCtrlOut(6), -- out\r
- Q4 => IntClkCtrlOut(7), -- out\r
- Q5 => open, -- out\r
- Q6 => open, -- out\r
- SHIFTIN1 => IntClkCtrlIsrdsMtoS1,-- in\r
- SHIFTIN2 => IntClkCtrlIsrdsMtoS2 -- in\r
- );\r
--- Input from ISERDES.O -- Output and CLK for all ISERDES\r
-AdcClock_I_Bufio : BUFIO\r
- port map (I => IntBitClk, O => BitClk_MonClkOut);\r
---\r
-Gen_Bufr_Div_3 : if (C_AdcBits = 12) generate\r
- attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;\r
-begin\r
- AdcClock_I_Bufr : BUFR\r
- generic map (BUFR_DIVIDE => "3", SIM_DEVICE => "VIRTEX6") -- 12-bit = DIV by 3\r
--- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.\r
- port map (I => IntBitClk, O => BitClk_RefClkOut,\r
- CE => High, CLR => BitClkDivReset);\r
-end generate;\r
---\r
-Gen_Bufr_Div_4 : if (C_AdcBits /= 12) generate\r
- attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;\r
-begin\r
- AdcClock_I_Bufr : BUFR\r
- generic map (BUFR_DIVIDE => "4", SIM_DEVICE => "VIRTEX6") -- 14- and 16-bit = DIV by 4\r
--- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.\r
- port map (I => IntBitClk, O => BitClk_RefClkOut,\r
- CE => High, CLR => BitClkDivReset);\r
-end generate;\r
-\r
-\r
------------------------------------------------------------------------------------------------\r
--- Bit clock re-synchronizer\r
------------------------------------------------------------------------------------------------\r
-IntBitClkRst <= BitClkRst or BitClkReSync;\r
------------------------------------------------------------------------------------------------\r
--- Bit clock controller for clock alignment input.\r
------------------------------------------------------------------------------------------------\r
--- This input section makes sure 64 bits are captured before action is taken to pass to\r
--- the statemachine for evaluation.\r
--- 8 samples of the Bit Clock are taken by the ISERDES and then transferred to the parallel\r
--- FPGA world. The Proceed counter needs 8 reference clock rising edges before terminal count.\r
--- The Proceed counter terminal count then loads the 2 control bits (made from sampled clock)\r
--- into an intermediate register (IntCalVal).\r
---\r
--- IntCal = '1' when all outputs of the ISERDES are '1 else it's '0'.\r
--- IntVal = '1' when all outputs are '0' or '1'.\r
---\r
-IntCal <= IntClkCtrlOut(7) and IntClkCtrlOut(6) and IntClkCtrlOut(5) and\r
- IntClkCtrlOut(4) and IntClkCtrlOut(3) and IntClkCtrlOut(2) and\r
- IntClkCtrlOut(1) and IntClkCtrlOut(0);\r
-IntVal <= '1' when (IntClkCtrlOut = "11111111" or IntClkCtrlOut = "00000000") else '0';\r
---\r
-AdcClock_Proceed_PROCESS : process (BitClkEna, IntBitClkRst, BitClk_RefClkIn, IntProceedDone, IntClkCtrlDone)\r
-begin\r
- if (IntBitClkRst = '1') then\r
- IntProceedCnt <= (others => '0');\r
- IntProceedCntTc_d <= '0';\r
- IntCalVal <= (others => '0');\r
- IntProceed <= '0';\r
- elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then\r
- if (BitClkEna = '1' and IntClkCtrlDone = '0') then\r
- IntProceedCnt <= IntProceedCnt + 1;\r
- IntProceedCntTc_d <= IntProceedCntTc;\r
- if (IntProceedCntTc_d = '1') then\r
- IntCalVal <= IntCal & IntVal;\r
- end if;\r
- if (IntProceedCntTc_d = '1') then\r
- IntProceed <= '1';\r
- elsif (IntProceedDone = '1') then\r
- IntProceed <= '0';\r
- end if;\r
- end if;\r
- end if;\r
-end process;\r
-IntProceedCntTc <= '1' when (IntProceedCnt = "110") else '0';\r
------------------------------------------------------------------------------------------------\r
--- Bit clock controller for clock alignment state machine.\r
------------------------------------------------------------------------------------------------\r
-BitClkAlignWarn <= IntClkCtrlAlgnWrn;\r
-BitClkInvrtd <= IntClkCtrlInvrtd;\r
-BitClkDone <= IntClkCtrlDone;\r
-\r
-AdcClock_State_PROCESS : process (BitClk_RefClkIn, IntBitClkRst, BitClkEna, IntProceed, IntCalVal)\r
-subtype ActCalVal is std_logic_vector (4 downto 0);\r
-begin\r
- if (IntBitClkRst = '1') then\r
- State <= Idle;\r
- ReturnState <= Idle;\r
- PassedSubState <= '0';\r
- --\r
- IntNumIncDecIdly <= "0000"; -- Max. 16\r
- IntAction <= "00"; \r
- IntClkCtrlDlyInc <= '1';\r
- IntClkCtrlDlyCe <= '0';\r
- IntClkCtrlDone <= '0';\r
- IntClkCtrlAlgnWrn <= '0';\r
- IntClkCtrlInvrtd <= '0';\r
- IntTurnAroundBit <= '0';\r
- IntProceedDone <= '0';\r
- IntClkCtrlDone <= '0';\r
- IntCalValReg <= (others => '0'); -- 2-bit\r
- IntTimeOutCnt <= (others => '0'); -- 4-bit\r
- IntStepCnt <= (others => '0'); -- 4-bit (16)\r
- elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then\r
- if (BitClkEna = '1' and IntClkCtrlDone = '0') then\r
- case State is \r
- when Idle =>\r
- IntProceedDone <= '0';\r
- PassedSubState <= '0';\r
- case ActCalVal'(IntAction(1 downto 0) & IntCalVal (1 downto 0) & IntProceed) is\r
- when "00001" => State <= A;\r
- when "01001" => State <= B;\r
- when "10001" => State <= B;\r
- when "11001" => State <= B;\r
- when "01111" => State <= C;\r
- when "01101" => State <= D;\r
- when "01011" => State <= D;\r
- when "00011" => State <= E;\r
- when "00101" => State <= E;\r
- when "00111" => State <= E;\r
- when "10011" => State <= F;\r
- when "11011" => State <= F;\r
- when "10101" => State <= F;\r
- when "11101" => State <= F;\r
- when "10111" => State <= F;\r
- when "11111" => State <= F;\r
- when others => State <= Idle;\r
- end case;\r
- when A => -- First time and sampling in jitter or cross area.\r
- IntAction <= "01"; -- Set the action bits and go to next step.\r
- State <= B;\r
- when B => -- Input is samples in jitter or clock cross area.\r
- if (PassedSubState = '1') then\r
- PassedSubState <= '0'; -- Clear the pass through the substate bit.\r
- IntProceedDone <= '1'; -- Reset the proceed bit.\r
- State <= Idle; -- Return for a new sample of the input.\r
- elsif (IntTimeOutCnt = "1111") then -- When arriving here something is wrong.\r
- IntTimeOutCnt <= "0000"; -- Reset the counter.\r
- IntAction <= "00"; -- reset the action bits.\r
- IntClkCtrlAlgnWrn <= '1'; -- Raise a FLAG.\r
- IntProceedDone <= '1'; -- Reset the proceed bit.\r
- State <= Idle; -- Retry, return for new sample of input.\r
- else\r
- IntTimeOutCnt <= IntTimeOutCnt + 1;\r
- IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.\r
- ReturnState <= State; -- This state is the state to return too.\r
- IntProceedDone <= '1'; -- Reset the proceed bit.\r
- IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
- State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.\r
- end if;\r
- when C => -- After first sample, jitter or cross, is now high.\r
- IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.\r
- ReturnState <= Done; -- This state is the state to return too.\r
- IntClkCtrlDlyInc <= '0'; -- Set for decrement.\r
- State <= IdlyIncDec;\r
- when D => -- Same as C but with indication of 180-deg shift.\r
- IntClkCtrlInvrtd <= '1';\r
- State <= C;\r
- when E => -- First saple with valid data.\r
- IntCalValReg <= IntCalVal; -- Register the sampled value\r
- IntAction <= "10";\r
- IntProceedDone <= '1'; -- Reset the proceed bit.\r
- IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.\r
- ReturnState <= Idle; -- When increment is done return sampling.\r
- IntClkCtrlDlyInc <= '1'; -- Set for increment\r
- State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.\r
- when F => -- Next samples with valid data.\r
- if (IntCalVal /= IntCalValReg) then\r
- State <= G; -- The new CalVal value is different from the first.\r
- else\r
- if (IntStepCnt = "1111") then -- Step counter at the end, 15\r
- if (IntTurnAroundBit = '0') then \r
- State <= H; -- No edge found and first time here.\r
- elsif (IntCalValReg = "11") then\r
- State <= K; -- A turnaround already happend.\r
- else -- No edge is found (large 1/2 period).\r
- State <= K1; -- Move the clock edge to near the correct\r
- end if; -- edge.\r
- else\r
- IntStepCnt <= IntStepCnt + 1;\r
- IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.\r
- IntProceedDone <= '1'; -- Reset the proceed bit.\r
- ReturnState <= Idle; -- When increment is done return sampling.\r
- IntClkCtrlDlyInc <= '1'; -- Set for increment\r
- State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.\r
- end if;\r
- end if;\r
- when G =>\r
- if (IntCalValReg /= "01") then\r
- IntClkCtrlInvrtd <= '1';\r
- State <= G1;\r
- else\r
- State <= G1;\r
- end if;\r
- when G1 =>\r
- if (IntTimeOutCnt = "00") then\r
- State <= Done;\r
- else\r
- IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.\r
- ReturnState <= Done; -- After decrement it's finished.\r
- IntClkCtrlDlyInc <= '0'; -- Set for decrement\r
- State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
- end if;\r
- when H =>\r
- IntTurnAroundBit <= '1'; -- Indicate that the Idelay jumps to 0.\r
- IntStepCnt <= IntStepCnt + 1; -- Set all registers to zero.\r
- IntAction <= "00"; -- Take one step, let the counter flow over \r
- IntCalValReg <= "00"; -- The idelay turn over to 0.\r
- IntTimeOutCnt <= "0000"; -- Start sampling from scratch.\r
- IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.\r
- IntProceedDone <= '1'; -- Reset the proceed bit.\r
- ReturnState <= Idle; -- After increment go sampling for new.\r
- IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
- State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
- when K =>\r
- IntNumIncDecIdly <= "1111"; -- Number increments or decrements to do.\r
- ReturnState <= K2; -- After increment it is done.\r
- IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
- State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
- when K1 =>\r
- IntNumIncDecIdly <= "1110"; -- Number increments or decrements to do.\r
- ReturnState <= K2; -- After increment it is done.\r
- IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
- State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
- when K2 =>\r
- IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.\r
- ReturnState <= Done; -- After increment it is done.\r
- IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
- State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
- --\r
- when IdlyIncDec => -- Increment or decrement by enable.\r
- if (IntNumIncDecIdly /= "0000") then -- Check number of tap jumps\r
- IntNumIncDecIdly <= IntNumIncDecIdly - 1; -- If not 0 jump and decrement.\r
- IntClkCtrlDlyCe <= '1'; -- Do the jump. enable it.\r
- else\r
- IntClkCtrlDlyCe <= '0'; -- when it is enabled, disbale it\r
- PassedSubState <= '1'; -- Set a check bit "I've been here and passed".\r
- State <= ReturnState; -- Return to origin.\r
- end if;\r
- when Done => -- Alignment done.\r
- IntClkCtrlDone <= '1'; -- Alignment is done.\r
- end case;\r
- end if;\r
- end if;\r
-end process;\r
---\r
-------------------------------------------------------------------------------------------------\r
+-----------------------------------------------------------------------------------------------
+-- © Copyright 2012, Xilinx, Inc. All rights reserved.
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is
+-- protected under U.S. and international copyright and other intellectual property laws.
+-----------------------------------------------------------------------------------------------
+--
+-- Disclaimer:
+-- This disclaimer is not a license and does not grant any rights to the materials
+-- distributed herewith. Except as otherwise provided in a valid license issued to you
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
+-- negligence, or under any other theory of liability) for any loss or damage of any
+-- kind or nature related to, arising under or in connection with these materials,
+-- including for any direct, or any indirect, special, incidental, or consequential
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or
+-- damage suffered as a result of any action brought by a third party) even if such
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any
+-- application requiring fail-safe performance, such as life-support or safety devices
+-- or systems, Class III medical devices, nuclear facilities, applications related to
+-- the deployment of airbags, or any other applications that could lead to death,
+-- personal injury, or severe property or environmental damage (individually and
+-- collectively, "Critical Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical Applications, subject only to
+-- applicable laws and regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version: V0,03
+-- \ \ Filename: AdcClock.vhd
+-- / / Date Last Modified: 24 Jul 12
+-- /___/ /\ Date Created: 08 Jun 09
+-- \ \ / \
+-- \___\/\___\
+--
+-- Device: 7-series
+-- Author: Marc Defossez
+-- Entity Name: AdcClock
+-- Purpose: Clock control for an ADC interface.
+-- Tools: ISE_14.1
+-- Limitations: none
+--
+-- Revision History:
+-- Rev.
+--
+-----------------------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>"
+-----------------------------------------------------------------------------------------------
+--
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+ use IEEE.std_logic_arith.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+-----------------------------------------------------------------------------------------------
+-- Entity pin description
+-----------------------------------------------------------------------------------------------
+entity AdcClock is
+ generic (
+ C_BufioLoc : string := "BUFIO_X0Y17"; -- IO-bank 16
+ C_BufrLoc : string := "BUFR_X0Y17";
+ C_IserdesLoc: string := "BUFR_X0Y17";
+ C_StatTaps : integer := 16
+ );
+ port (
+ BitClk : in std_logic;
+ BitClkRst : in std_logic;
+ BitClkEna : in std_logic;
+ BitClkReSync : in std_logic;
+ BitClk_MonClkOut : out std_logic; -- CLK output
+ BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input
+ BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output
+ BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input
+ BitClkAlignWarn : out std_logic;
+ BitClkInvrtd : out std_logic;
+ BitClkDone : out std_logic
+ );
+end AdcClock;
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcClock_struct of AdcClock is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+-- Components are instantiated by means / through the use of library references.
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+-- Constants
+constant Low : std_logic := '0';
+constant LowNibble : std_logic_vector(4 downto 0) := "00000";
+constant High : std_logic := '1';
+-- Signals
+signal IntBitClkRst : std_logic;
+---------- ISRDS signals ------------------
+signal IntClkCtrlDlyCe : std_logic;
+signal IntClkCtrlDlyInc : std_logic;
+signal IntClkCtrlDlyRst : std_logic;
+
+signal IntBitClk_Ddly : std_logic;
+signal IntBitClk : std_logic;
+signal BitClk_inv : std_logic;
+
+signal IntClkCtrlIsrdsMtoS1 : std_logic;
+signal IntClkCtrlIsrdsMtoS2 : std_logic;
+signal IntClkCtrlOut : std_logic_vector(7 downto 0);
+---------- Controller signals -------------
+signal IntCal : std_logic;
+signal IntVal : std_logic;
+signal IntCalVal : std_logic_vector (1 downto 0);
+signal IntProceedCnt : std_logic_vector (2 downto 0);
+signal IntproceedCntTc : std_logic;
+signal IntproceedCntTc_d : std_logic;
+signal IntProceed : std_logic;
+signal IntProceedDone : std_logic;
+
+type StateType is (Idle, A, B, C, D, E, F, G, G1, H, K, K1, K2, IdlyIncDec, Done);
+signal State : StateType;
+signal ReturnState : StateType;
+
+signal PassedSubState : std_logic;
+signal IntNumIncDecIdly : std_logic_vector (3 downto 0);
+signal IntAction : std_logic_vector (1 downto 0);
+signal IntClkCtrlDone : std_logic;
+signal IntClkCtrlAlgnWrn : std_logic;
+signal IntClkCtrlInvrtd : std_logic;
+signal IntTurnAroundBit : std_logic;
+signal IntCalValReg : std_logic_vector (1 downto 0);
+signal IntTimeOutCnt : std_logic_vector (3 downto 0);
+signal IntStepCnt : std_logic_vector (4 downto 0); --//
+-- Attributes
+attribute KEEP_HIERARCHY : string;
+ attribute KEEP_HIERARCHY of AdcClock_struct : architecture is "YES";
+attribute LOC : string;
+ attribute LOC of AdcClock_I_Bufio : label is C_BufioLoc;
+ attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;
+ attribute LOC of AdcClock_I_Isrds_Master : label is C_IserdesLoc;
+--attribute keep : string;
+--attribute keep of BitClk_inv : signal is "TRUE";
+
+-----------------------------------------------------------------------------------------------
+begin
+-----------------------------------------------------------------------------------------------
+-- Bit clock capture ISERDES Master-Slave combination
+-----------------------------------------------------------------------------------------------
+--
+BitClk_inv <= not BitClk; -- peterS: invert clock for better optimal delay point
+AdcClock_I_Iodly : IDELAYE2 --_FINEDELAY
+ generic map (
+ SIGNAL_PATTERN => "CLOCK",
+ REFCLK_FREQUENCY => 200.0,
+ HIGH_PERFORMANCE_MODE => "TRUE",
+ --FINEDELAY => "BYPASS",
+ DELAY_SRC => "IDATAIN",
+ CINVCTRL_SEL => "FALSE",
+ IDELAY_TYPE => "VARIABLE",
+ IDELAY_VALUE => C_StatTaps,
+ PIPE_SEL => "FALSE"
+ )
+ port map (
+ DATAIN => Low, -- in
+ IDATAIN => BitClk_inv, -- in
+ CE => IntClkCtrlDlyCe, -- in
+ INC => IntClkCtrlDlyInc, -- in
+ C => BitClk_RefClkIn, -- in
+ LD => IntClkCtrlDlyRst, -- in
+ LDPIPEEN => Low, -- in
+ REGRST => '0', --//IntClkCtrlDlyRst, -- in
+ DATAOUT => IntBitClk_Ddly, -- out
+ CINVCTRL => Low, -- in
+ CNTVALUEOUT => open, -- out [4:0]
+ CNTVALUEIN => LowNibble -- in [4:0]
+ );
+IntClkCtrlDlyRst <= BitClkRst;
+
+AdcClock_I_Isrds_Master : ISERDESE2
+ generic map (
+ SERDES_MODE => "MASTER",
+ INTERFACE_TYPE => "NETWORKING",
+ IOBDELAY => "IBUF",
+ DATA_RATE => "SDR",
+ DATA_WIDTH => 8,
+ DYN_CLKDIV_INV_EN => "FALSE",
+ DYN_CLK_INV_EN => "FALSE",
+ NUM_CE => 1,
+ OFB_USED => "FALSE",
+ INIT_Q1 => '0',
+ INIT_Q2 => '0',
+ INIT_Q3 => '0',
+ INIT_Q4 => '0',
+ SRVAL_Q1 => '0',
+ SRVAL_Q2 => '0',
+ SRVAL_Q3 => '0',
+ SRVAL_Q4 => '0'
+ )
+ port map (
+ D => BitClk_inv, -- in Clock from clock input IBUFDS
+ DDLY => IntBitClk_Ddly, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => Low, -- in
+ CE1 => BitClkEna, -- in
+ CE2 => Low, -- in
+ RST => IntBitClkRst, -- in
+ CLK => BitClk_MonClkIn, -- in
+ CLKB => Low, -- in
+ CLKDIV => BitClk_RefClkIn, -- in
+ CLKDIVP => Low, -- in
+ OCLK => Low, -- in
+ OCLKB => Low, -- in
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low, -- in
+ O => IntBitClk, -- out
+ Q1 => IntClkCtrlOut(0), -- out
+ Q2 => IntClkCtrlOut(1), -- out
+ Q3 => IntClkCtrlOut(2), -- out
+ Q4 => IntClkCtrlOut(3), -- out
+ Q5 => IntClkCtrlOut(4), -- out
+ Q6 => IntClkCtrlOut(5), -- out
+ Q7 => IntClkCtrlOut(6), -- out
+ Q8 => IntClkCtrlOut(7), -- out
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open -- out
+ );
+-- Input from ISERDES.O -- Output and CLK for all ISERDES
+AdcClock_I_Bufio : BUFIO
+ port map (I => IntBitClk, O => BitClk_MonClkOut);
+
+AdcClock_I_Bufr : BUFR
+ generic map (BUFR_DIVIDE => "4", SIM_DEVICE => "7SERIES") -- 14- and 16-bit = DIV by 4
+-- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.
+ port map (I => IntBitClk, O => BitClk_RefClkOut,
+ CE => High, CLR => BitClkReSync); --// ); --//peter low
+
+
+-----------------------------------------------------------------------------------------------
+-- Bit clock re-synchronizer
+-----------------------------------------------------------------------------------------------
+IntBitClkRst <= BitClkRst; --// or BitClkReSync;
+-----------------------------------------------------------------------------------------------
+-- Bit clock controller for clock alignment input.
+-----------------------------------------------------------------------------------------------
+-- This input section makes sure 64 bits are captured before action is taken to pass to
+-- the statemachine for evaluation.
+-- 8 samples of the Bit Clock are taken by the ISERDES and then transferred to the parallel
+-- FPGA world. The Proceed counter needs 8 reference clock rising edges before terminal count.
+-- The Proceed counter terminal count then loads the 2 control bits (made from sampled clock)
+-- into an intermediate register (IntCalVal).
+--
+-- IntCal = '1' when all outputs of the ISERDES are '1 else it's '0'.
+-- IntVal = '1' when all outputs are '0' or '1'.
+--
+IntCal <= IntClkCtrlOut(7) and IntClkCtrlOut(6) and IntClkCtrlOut(5) and
+ IntClkCtrlOut(4) and IntClkCtrlOut(3) and IntClkCtrlOut(2) and
+ IntClkCtrlOut(1) and IntClkCtrlOut(0);
+IntVal <= '1' when (IntClkCtrlOut = "11111111" or IntClkCtrlOut = "00000000") else '0';
+--
+AdcClock_Proceed_PROCESS : process (BitClkEna, IntBitClkRst, BitClk_RefClkIn, IntProceedDone, IntClkCtrlDone)
+begin
+ if (IntBitClkRst = '1') then
+ IntProceedCnt <= (others => '0');
+ IntProceedCntTc_d <= '0';
+ IntCalVal <= (others => '0');
+ IntProceed <= '0';
+ elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then
+ if (BitClkEna = '1' and IntClkCtrlDone = '0') then
+ IntProceedCnt <= IntProceedCnt + 1;
+ IntProceedCntTc_d <= IntProceedCntTc;
+ if (IntProceedCntTc_d = '1') then
+ IntCalVal <= IntCal & IntVal;
+ end if;
+ if (IntProceedCntTc_d = '1') then
+ IntProceed <= '1';
+ elsif (IntProceedDone = '1') then
+ IntProceed <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+IntProceedCntTc <= '1' when (IntProceedCnt = "110") else '0';
+-----------------------------------------------------------------------------------------------
+-- Bit clock controller for clock alignment state machine.
+-----------------------------------------------------------------------------------------------
+BitClkAlignWarn <= IntClkCtrlAlgnWrn;
+BitClkInvrtd <= IntClkCtrlInvrtd;
+BitClkDone <= IntClkCtrlDone;
+
+AdcClock_State_PROCESS : process (BitClk_RefClkIn, IntBitClkRst, BitClkEna, IntProceed, IntCalVal)
+subtype ActCalVal is std_logic_vector (4 downto 0);
+begin
+ if (IntBitClkRst = '1') then
+ State <= Idle;
+ ReturnState <= Idle;
+ PassedSubState <= '0';
+ --
+ IntNumIncDecIdly <= "0000"; -- Max. 16
+ IntAction <= "00";
+ IntClkCtrlDlyInc <= '1';
+ IntClkCtrlDlyCe <= '0';
+ IntClkCtrlDone <= '0';
+ IntClkCtrlAlgnWrn <= '0';
+ IntClkCtrlInvrtd <= '0';
+ IntTurnAroundBit <= '0';
+ IntProceedDone <= '0';
+ IntClkCtrlDone <= '0';
+ IntCalValReg <= (others => '0'); -- 2-bit
+ IntTimeOutCnt <= (others => '0'); -- 4-bit
+ IntStepCnt <= (others => '0'); -- 4-bit (16)
+ elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then
+ if (BitClkEna = '1' and IntClkCtrlDone = '0') then
+ case State is
+ when Idle =>
+ IntProceedDone <= '0';
+ PassedSubState <= '0';
+ case ActCalVal'(IntAction(1 downto 0) & IntCalVal (1 downto 0) & IntProceed) is
+ when "00001" => State <= A;
+ when "01001" => State <= B;
+ when "10001" => State <= B;
+ when "11001" => State <= B;
+ when "01111" => State <= C;
+ when "01101" => State <= D;
+ when "01011" => State <= D;
+ when "00011" => State <= E;
+ when "00101" => State <= E;
+ when "00111" => State <= E;
+ when "10011" => State <= F;
+ when "11011" => State <= F;
+ when "10101" => State <= F;
+ when "11101" => State <= F;
+ when "10111" => State <= F;
+ when "11111" => State <= F;
+ when others => State <= Idle;
+ end case;
+ when A => -- First time and sampling in jitter or cross area.
+ IntAction <= "01"; -- Set the action bits and go to next step.
+ State <= B;
+ when B => -- Input is samples in jitter or clock cross area.
+ if (PassedSubState = '1') then
+ PassedSubState <= '0'; -- Clear the pass through the substate bit.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ State <= Idle; -- Return for a new sample of the input.
+ elsif (IntTimeOutCnt = "1111") then -- When arriving here something is wrong.
+ IntTimeOutCnt <= "0000"; -- Reset the counter.
+ IntAction <= "00"; -- reset the action bits.
+ IntClkCtrlAlgnWrn <= '1'; -- Raise a FLAG.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ State <= Idle; -- Retry, return for new sample of input.
+ else
+ IntTimeOutCnt <= IntTimeOutCnt + 1;
+ IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.
+ ReturnState <= State; -- This state is the state to return too.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.
+ end if;
+ when C => -- After first sample, jitter or cross, is now high.
+ IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.
+ ReturnState <= Done; -- This state is the state to return too.
+ IntClkCtrlDlyInc <= '0'; -- Set for decrement.
+ State <= IdlyIncDec;
+ when D => -- Same as C but with indication of 180-deg shift.
+ IntClkCtrlInvrtd <= '1';
+ State <= C;
+ when E => -- First sample with valid data.
+ IntCalValReg <= IntCalVal; -- Register the sampled value
+ IntAction <= "10";
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.
+ ReturnState <= Idle; -- When increment is done return sampling.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment
+ State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.
+ when F => -- Next samples with valid data.
+ if (IntCalVal /= IntCalValReg) then
+ State <= G; -- The new CalVal value is different from the first.
+ else
+ if (IntStepCnt = "11111") then -- Step counter at the end, 15 --//
+ if (IntTurnAroundBit = '0') then
+ State <= H; -- No edge found and first time here.
+ elsif (IntCalValReg = "11") then
+ State <= K; -- A turnaround already happend.
+ else -- No edge is found (large 1/2 period).
+ State <= K1; -- Move the clock edge to near the correct
+ end if; -- edge.
+ else
+ IntStepCnt <= IntStepCnt + 1;
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ ReturnState <= Idle; -- When increment is done return sampling.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment
+ State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.
+ end if;
+ end if;
+ when G =>
+ if (IntCalValReg /= "01") then
+ IntClkCtrlInvrtd <= '1';
+ State <= G1;
+ else
+ State <= G1;
+ end if;
+ when G1 =>
+ if (IntTimeOutCnt = "00") then
+ State <= Done;
+ else
+ IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.
+ ReturnState <= Done; -- After decrement it's finished.
+ IntClkCtrlDlyInc <= '0'; -- Set for decrement
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ end if;
+ when H =>
+ IntTurnAroundBit <= '1'; -- Indicate that the Idelay jumps to 0.
+ IntStepCnt <= IntStepCnt + 1; -- Set all registers to zero.
+ IntAction <= "00"; -- Take one step, let the counter flow over
+ IntCalValReg <= "00"; -- The idelay turn over to 0.
+ IntTimeOutCnt <= "0000"; -- Start sampling from scratch.
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.
+ IntProceedDone <= '1'; -- Reset the proceed bit.
+ ReturnState <= Idle; -- After increment go sampling for new.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ when K =>
+ IntNumIncDecIdly <= "1111"; -- Number increments or decrements to do.
+ ReturnState <= K2; -- After increment it is done.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ when K1 =>
+ IntNumIncDecIdly <= "1110"; -- Number increments or decrements to do.
+ ReturnState <= K2; -- After increment it is done.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ when K2 =>
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.
+ ReturnState <= Done; -- After increment it is done.
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.
+ --
+ when IdlyIncDec => -- Increment or decrement by enable.
+ if (IntNumIncDecIdly /= "0000") then -- Check number of tap jumps
+ IntNumIncDecIdly <= IntNumIncDecIdly - 1; -- If not 0 jump and decrement.
+ IntClkCtrlDlyCe <= '1'; -- Do the jump. enable it.
+ else
+ IntClkCtrlDlyCe <= '0'; -- when it is enabled, disbale it
+ PassedSubState <= '1'; -- Set a check bit "I've been here and passed".
+ State <= ReturnState; -- Return to origin.
+ end if;
+ when Done => -- Alignment done.
+ IntClkCtrlDone <= '1'; -- Alignment is done.
+ end case;
+ end if;
+ end if;
+end process;
+--
+------------------------------------------------------------------------------------------------
+
+
+
end AdcClock_struct;
\ No newline at end of file
--- /dev/null
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+
+entity AdcData is
+ port (
+ DatD0_n : in std_logic;
+ DatD0_p : in std_logic;
+ DatD1_n : in std_logic;
+ DatD1_p : in std_logic;
+ DatClk : in std_logic;
+ DatClkDiv : in std_logic;
+ DatRst : in std_logic;
+ DatEna : in std_logic;
+ DatDone : in std_logic;
+ DatOut : out std_logic_vector(31 downto 0)
+ );
+end AdcData;
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcData_struct of AdcData is
+signal IntDatClk : std_logic;
+signal IntDatClk_n : std_logic;
+--
+signal IntDatSrds0Out : std_logic_vector(7 downto 0);
+signal IntDatSrds1Out : std_logic_vector(7 downto 0);
+signal IntDatSrds0 : std_logic_vector(7 downto 0);
+signal IntDatSrds1 : std_logic_vector(7 downto 0);
+signal IntDat0 : std_logic_vector(7 downto 0);
+signal IntDat1 : std_logic_vector(7 downto 0);
+signal IntDat0Mux : std_logic_vector(7 downto 0);
+signal IntDat1Mux : std_logic_vector(7 downto 0);
+signal IntDat0Swp : std_logic_vector(7 downto 0);
+signal IntDat1Swp : std_logic_vector(7 downto 0);
+signal IntDatSwpBus : std_logic_vector(31 downto 0);
+signal IntDatDone : std_logic;
+signal IntDatEna : std_logic;
+-- Attributes
+attribute KEEP_HIERARCHY : string;
+attribute KEEP_HIERARCHY of AdcData_struct : architecture is "YES";
+-----------------------------------------------------------------------------------------------
+
+begin
+--
+-- DatRst and DatEna are synchronised to DatClkDiv on the level were this component "AdcData"
+-- is used. This higher level is "AdcToplevel".
+AdcData_Done_PROCESS : process (DatClkDiv, DatRst)
+begin
+ if (DatRst = '1') then
+ IntDatDone <= '0';
+ elsif (DatClkDiv'event and DatClkDiv = '1') then
+ IntDatDone <= DatDone;
+ end if;
+end process;
+--
+IntDatEna <= '1' when (IntDatDone = '1' and DatEna = '1') else '0';
+-----------------------------------------------------------------------------------------------
+IntDatClk <= DatClk; -- CLOCK FOR P-side ISERDES
+IntDatClk_n <= not DatClk; -- CLOCK FOR N_side ISERDES
+-----------------------------------------------------------------------------------------------
+-- ISERDES for channel ZERO
+-----------------------------------------------------------------------------------------------
+AdcData_I_Isrds_D0_p : ISERDESE2
+ generic map (
+ SERDES_MODE => "MASTER", -- string
+ INTERFACE_TYPE => "NETWORKING", -- string
+ IOBDELAY => "NONE", -- string
+ DATA_RATE => "SDR", -- string
+ DATA_WIDTH => 4, -- integer <-- Number of bits
+ DYN_CLKDIV_INV_EN => "FALSE", -- string
+ DYN_CLK_INV_EN => "FALSE", -- string
+ NUM_CE => 1, -- integer
+ OFB_USED => "FALSE", -- string
+ INIT_Q1 => '0', -- bit;
+ INIT_Q2 => '0', -- bit;
+ INIT_Q3 => '0', -- bit;
+ INIT_Q4 => '0', -- bit;
+ SRVAL_Q1 => '0', -- bit;
+ SRVAL_Q2 => '0', -- bit;
+ SRVAL_Q3 => '0', -- bit;
+ SRVAL_Q4 => '0' -- bit
+ )
+ port map (
+ D => DatD0_p, -- in
+ DDLY => '0', -- in
+ OFB => '0', -- in
+ BITSLIP => '0',-- in
+ CE1 => IntDatDone, -- in
+ CE2 => '0', -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk, -- in
+ CLKB => '0', -- in
+ CLKDIV => DatClkDiv, -- in
+ CLKDIVP => '0', -- in
+ OCLK => '0', -- in
+ OCLKB => '0', -- in
+ DYNCLKDIVSEL => '0', -- in
+ DYNCLKSEL => '0', -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds0Out(6), -- out (0)
+ Q2 => IntDatSrds0Out(4), -- out (2)
+ Q3 => IntDatSrds0Out(2), -- out (4)
+ Q4 => IntDatSrds0Out(0), -- out (6)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ Q7 => open, -- out
+ Q8 => open, -- out
+ SHIFTIN1 => '0', -- in
+ SHIFTIN2 => '0' -- in
+ );
+AdcData_I_Isrds_D0_n : ISERDESE2
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => 4, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => "FALSE", --
+ DYN_CLK_INV_EN => "FALSE", --
+ NUM_CE => 1, --
+ OFB_USED => "FALSE", --
+ INIT_Q1 => '0', -- bit;
+ INIT_Q2 => '0', -- bit;
+ INIT_Q3 => '0', -- bit;
+ INIT_Q4 => '0', -- bit;
+ SRVAL_Q1 => '0', -- bit;
+ SRVAL_Q2 => '0', -- bit;
+ SRVAL_Q3 => '0', -- bit;
+ SRVAL_Q4 => '0' -- bit
+ )
+ port map (
+ D => DatD0_n, -- in
+ DDLY => '0', -- in
+ OFB => '0', -- in
+ BITSLIP => '0',-- in
+ CE1 => IntDatDone, -- in
+ CE2 => '0', -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk_n, -- in
+ CLKB => '0', -- in
+ CLKDIV => DatClkDiv, -- in
+ CLKDIVP => '0', -- in
+ OCLK => '0', -- in
+ OCLKB => '0', -- in
+ DYNCLKDIVSEL => '0', -- in
+ DYNCLKSEL => '0', -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds0Out(7), -- out (1)
+ Q2 => IntDatSrds0Out(5), -- out (3)
+ Q3 => IntDatSrds0Out(3), -- out (5)
+ Q4 => IntDatSrds0Out(1), -- out (7)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ Q7 => open, -- out
+ Q8 => open, -- out
+ SHIFTIN1 => '0', -- in
+ SHIFTIN2 => '0' -- in
+ );
+-----------------------------------------------------------------------------------------------
+-- ISERDES for channel ONE
+-----------------------------------------------------------------------------------------------
+AdcData_I_Isrds_D1_p : ISERDESE2
+ generic map (
+ SERDES_MODE => "MASTER", -- string
+ INTERFACE_TYPE => "NETWORKING", -- string
+ IOBDELAY => "NONE", -- string
+ DATA_RATE => "SDR", -- string
+ DATA_WIDTH => 4, -- integer <-- Number of bits
+ DYN_CLKDIV_INV_EN => "FALSE", -- string
+ DYN_CLK_INV_EN => "FALSE", -- string
+ NUM_CE => 1, -- integer
+ OFB_USED => "FALSE", -- string
+ INIT_Q1 => '0', -- bit;
+ INIT_Q2 => '0', -- bit;
+ INIT_Q3 => '0', -- bit;
+ INIT_Q4 => '0', -- bit;
+ SRVAL_Q1 => '0', -- bit;
+ SRVAL_Q2 => '0', -- bit;
+ SRVAL_Q3 => '0', -- bit;
+ SRVAL_Q4 => '0' -- bit
+ )
+ port map (
+ D => DatD1_p, -- in
+ DDLY => '0', -- in
+ OFB => '0', -- in
+ BITSLIP => '0',-- in
+ CE1 => IntDatDone, -- in
+ CE2 => '0', -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk, -- in
+ CLKB => '0', -- in
+ CLKDIV => DatClkDiv, -- in
+ CLKDIVP => '0', -- in
+ OCLK => '0', -- in
+ OCLKB => '0', -- in
+ DYNCLKDIVSEL => '0', -- in
+ DYNCLKSEL => '0', -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds1Out(6), -- out (0)
+ Q2 => IntDatSrds1Out(4), -- out (2)
+ Q3 => IntDatSrds1Out(2), -- out (4)
+ Q4 => IntDatSrds1Out(0), -- out (6)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ Q7 => open, -- out
+ Q8 => open, -- out
+ SHIFTIN1 => '0', -- in
+ SHIFTIN2 => '0' -- in
+ );
+AdcData_I_Isrds_D1_n : ISERDESE2
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => 4, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => "FALSE", --
+ DYN_CLK_INV_EN => "FALSE", --
+ NUM_CE => 1, --
+ OFB_USED => "FALSE", --
+ INIT_Q1 => '0', -- bit;
+ INIT_Q2 => '0', -- bit;
+ INIT_Q3 => '0', -- bit;
+ INIT_Q4 => '0', -- bit;
+ SRVAL_Q1 => '0', -- bit;
+ SRVAL_Q2 => '0', -- bit;
+ SRVAL_Q3 => '0', -- bit;
+ SRVAL_Q4 => '0' -- bit
+ )
+ port map (
+ D => DatD1_n, -- in
+ DDLY => '0', -- in
+ OFB => '0', -- in
+ BITSLIP => '0',-- in
+ CE1 => IntDatDone, -- in
+ CE2 => '0', -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk_n, -- in
+ CLKB => '0', -- in
+ CLKDIV => DatClkDiv, -- in
+ CLKDIVP => '0', -- in
+ OCLK => '0', -- in
+ OCLKB => '0', -- in
+ DYNCLKDIVSEL => '0', -- in
+ DYNCLKSEL => '0', -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds1Out(7), -- out (1)
+ Q2 => IntDatSrds1Out(5), -- out (3)
+ Q3 => IntDatSrds1Out(3), -- out (5)
+ Q4 => IntDatSrds1Out(1), -- out (7)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ Q7 => open, -- out
+ Q8 => open, -- out
+ SHIFTIN1 => '0', -- in
+ SHIFTIN2 => '0' -- in
+ );
+-----------------------------------------------------------------------------------------------
+
+
+ IntDatSrds0 <= not IntDatSrds0Out(7) & IntDatSrds0Out(6) &
+ not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
+ not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
+ not IntDatSrds0Out(1) & IntDatSrds0Out(0);
+ IntDatSrds1 <= not IntDatSrds1Out(7) & IntDatSrds1Out(6) &
+ not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
+ not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
+ not IntDatSrds1Out(1) & IntDatSrds1Out(0);
+
+-----------------------------------------------------------------------------------------------
+-- DATA REGISTER
+-----------------------------------------------------------------------------------------------
+Gen_1_DatReg : for n in 7 downto 0 generate
+ AdcData_I_Fdce_Reg0 : FDCE
+ generic map (INIT => '0') -- bit
+--// port map (D => IntDatSrds0(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst,
+ port map (D => IntDatSrds0(n), C => DatClkDiv, CE => '1', CLR => '0',
+ Q => IntDat0(n));
+ AdcData_I_Fdce_Reg1 : FDCE
+ generic map (INIT => '0') -- bit
+--// port map (D => IntDatSrds1(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst,
+ port map (D => IntDatSrds1(n), C => DatClkDiv, CE => '1', CLR => '0',
+ Q => IntDat1(n));
+end generate Gen_1_DatReg;
+
+
+IntDat0Mux <= IntDat0;
+IntDat1Mux <= IntDat1;
+
+Gen_3_DatReg : for n in 7 downto 0 generate
+ AdcData_I_Fdce_Reg2 : FDCE
+ generic map (INIT => '0') -- bit
+--// port map (D => IntDat0Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst,
+ port map (D => IntDat0Mux(n), C => DatClkDiv, CE => '1', CLR => '0',
+ Q => IntDat0Swp(n));
+ AdcData_I_Fdce_Reg3 : FDCE
+ generic map (INIT => '0') -- bit
+--// port map (D => IntDat1Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst,
+ port map (D => IntDat1Mux(n), C => DatClkDiv, CE => '1', CLR => '0',
+ Q => IntDat1Swp(n));
+end generate Gen_3_DatReg;
+
+
+
+-----------------------------------------------------------------------------------------------
+-- 2-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
+-- Only one of these options can be chosen at a time.
+-- 2-wire, Msb-Bit or Msb-Byte
+-- 2-wire, Lsb-Bit or Lsb-Byte
+-----------------------------------------------------------------------------------------------
+
+-- Bit mode, MSB First, 14-bits (16-bits)
+-- Bit : 7, 6, 5, 4, 3, 2, 1, 0
+-- Channel 0 : 0/(D14), D12, D10, D8, D6, D4, D2, D0
+-- Channel 1 : 0/(D15), D13, D11, D9, D7, D5, D3, D1
+IntDatSwpBus <= IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
+ & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2);
+Gen_1_H : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => '1', C => DatClkDiv,
+--// CLR => DatRst, Q => DatOut(n+16));
+ CLR => '0', Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => '1', C => DatClkDiv,
+--// CLR => DatRst, Q => DatOut(n));
+ CLR => '0', Q => DatOut(n));
+end generate Gen_1_H;
+-----------------------------------------------------------------------------------------------
+
+
+end AdcData_struct;
\ No newline at end of file
--- /dev/null
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+ use IEEE.std_logic_textio.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+
+entity AdcFrame is
+ port (
+ FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT
+ FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT
+ FrmClkRst : in std_logic;
+ FrmClkEna : in std_logic;
+ FrmClk : in std_logic;
+ FrmClkDiv : in std_logic;
+ FrmClkDone : in std_logic; -- Input from clock syncronisation.
+ Frame_out : out std_logic;
+ Frame_OK : out std_logic
+ );
+end AdcFrame;
+-----------------------------------------------------------------------------------------------
+-- Architecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcFrame_struct of AdcFrame is
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+--
+-- Constants
+
+-- Signals
+signal IntFrmClk : std_logic := '0';
+signal IntFrmClk_n : std_logic := '0';
+signal IntFrmSrdsOut : std_logic_vector (7 downto 0);
+signal IntFrmEna : std_logic := '0';
+signal Frame_out_S : std_Logic := '0';
+signal Frame_OK_S : std_Logic := '0';
+-- Attributes
+attribute keep : string;
+attribute KEEP_HIERARCHY : string;
+attribute KEEP_HIERARCHY of AdcFrame_struct : architecture is "YES";
+attribute keep of Frame_out_S : signal is "TRUE";
+-----------------------------------------------------------------------------------------------
+attribute mark_debug : string;
+-- attribute mark_debug of FrmClkRst : signal is "true";
+-- attribute mark_debug of IntFrmSrdsOut : signal is "true";
+-- attribute mark_debug of IntFrmEna : signal is "true";
+
+begin
+
+AdcFrame_I_Fdce_Done : FDCE
+ generic map (INIT => '0') -- bit
+ port map(D => FrmClkDone, CE => FrmClkEna, C => FrmClkDiv, CLR => FrmClkRst,
+ Q => IntFrmEna);
+
+-----------------------------------------------------------------------------------------------
+-- ISERDES FOR FRAME CAPTURE
+-----------------------------------------------------------------------------------------------
+IntFrmClk <= FrmClk;
+IntFrmClk_n <= not FrmClk;
+--
+AdcFrame_I_Isrds_p : ISERDESE2
+ generic map (
+ SERDES_MODE => "MASTER", -- string
+ INTERFACE_TYPE => "NETWORKING", -- string
+ IOBDELAY => "NONE", -- string
+ DATA_RATE => "SDR", -- string
+ DATA_WIDTH => 4, -- integer <-- Number of bits
+ DYN_CLKDIV_INV_EN => "FALSE", -- string
+ DYN_CLK_INV_EN => "FALSE", -- string
+ NUM_CE => 1, -- integer
+ OFB_USED => "FALSE", -- string
+ INIT_Q1 => '0', -- bit;
+ INIT_Q2 => '0', -- bit;
+ INIT_Q3 => '0', -- bit;
+ INIT_Q4 => '0', -- bit;
+ SRVAL_Q1 => '0', -- bit;
+ SRVAL_Q2 => '0', -- bit;
+ SRVAL_Q3 => '0', -- bit;
+ SRVAL_Q4 => '0' -- bit
+ )
+ port map (
+ D => FrmClk_p, -- in
+ DDLY => '0', -- in
+ OFB => '0', -- in
+ BITSLIP => '0', -- in
+ CE1 => IntFrmEna, -- in
+ CE2 => '0', -- in
+ RST => FrmClkRst, -- in
+ CLK => IntFrmClk, -- in
+ CLKB => '0', -- in
+ CLKDIV => FrmClkDiv, -- in
+ CLKDIVP => '0', -- in
+ OCLK => '0', -- in
+ OCLKB => '0', -- in
+ DYNCLKDIVSEL => '0', -- in
+ DYNCLKSEL => '0', -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => Frame_out_S, -- open, -- out
+ Q1 => IntFrmSrdsOut(6), -- out (0)
+ Q2 => IntFrmSrdsOut(4), -- out (2)
+ Q3 => IntFrmSrdsOut(2), -- out (4)
+ Q4 => IntFrmSrdsOut(0), -- out (6)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ Q7 => open, -- out
+ Q8 => open, -- out
+ SHIFTIN1 => '0', -- in
+ SHIFTIN2 => '0' -- in
+ );
+Frame_out <= Frame_out_S;
+--
+AdcFrame_I_Isrds_n : ISERDESE2
+ generic map (
+ SERDES_MODE => "MASTER", -- string
+ INTERFACE_TYPE => "NETWORKING", -- string
+ IOBDELAY => "NONE", -- string
+ DATA_RATE => "SDR", -- string
+ DATA_WIDTH => 4, -- integer 12-bit = 3 and 14/16 b its = 4
+ DYN_CLKDIV_INV_EN => "FALSE", -- string
+ DYN_CLK_INV_EN => "FALSE", -- string
+ NUM_CE => 1, -- integer
+ OFB_USED => "FALSE", -- string
+ INIT_Q1 => '0', -- bit;
+ INIT_Q2 => '0', -- bit;
+ INIT_Q3 => '0', -- bit;
+ INIT_Q4 => '0', -- bit;
+ SRVAL_Q1 => '0', -- bit;
+ SRVAL_Q2 => '0', -- bit;
+ SRVAL_Q3 => '0', -- bit;
+ SRVAL_Q4 => '0' -- bit
+ )
+ port map (
+ D => FrmClk_n, -- in
+ DDLY => '0', -- in
+ OFB => '0', -- in
+ BITSLIP => '0', -- in
+ CE1 => IntFrmEna, -- in
+ CE2 => '0', -- in
+ RST => FrmClkRst, -- in
+ CLK => IntFrmClk_n, -- in
+ CLKB => '0', -- in
+ CLKDIV => FrmClkDiv, -- in
+ CLKDIVP => '0', -- in
+ OCLK => '0', -- in
+ OCLKB => '0', -- in
+ DYNCLKDIVSEL => '0', -- in
+ DYNCLKSEL => '0', -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntFrmSrdsOut(7), -- out (1)
+ Q2 => IntFrmSrdsOut(5), -- out (3)
+ Q3 => IntFrmSrdsOut(3), -- out (5)
+ Q4 => IntFrmSrdsOut(1), -- out (7)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ Q7 => open, -- out
+ Q8 => open, -- out
+ SHIFTIN1 => '0', -- in
+ SHIFTIN2 => '0' -- in
+ );
+
+-----------------------------------------------------------------------------------------------
+-- FRAME PATTERN COMPARATOR
+-----------------------------------------------------------------------------------------------
+process(FrmClkDiv,FrmClkRst)
+begin
+ if FrmClkRst='1' then
+ Frame_OK_S <= '0';
+ elsif rising_edge(FrmClkDiv) then
+ if IntFrmSrdsOut=x"a5" then
+ Frame_OK_S <= '1';
+ else
+ Frame_OK_S <= '0';
+ end if;
+ end if;
+end process;
+Frame_OK <= Frame_OK_S;
+
+end AdcFrame_struct;
--- /dev/null
+---------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 06-11-2014
+-- Module Name: AdcSerialProg
+-- Description: Serial programming of LTM9009
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- AdcSerialProg
+-- Module to convert serial data from ADCs (LTM9009-14) to parallel
+-- Based on Xilinx serial ADC reference design
+--
+--
+-- Library:
+--
+-- Generics:
+--
+-- Inputs:
+-- clock200MHz : 200MHz clock input for IODELAYCTRL
+-- reset : reset ADCs
+-- ADCs_enable : enable signal for ADCs
+-- AD*_P : serial data links from ADCs, LVDS positive
+-- AD*_N : serial data links from ADCs, LVDS negative
+-- DCO*_P : data clock from ADCs, LVDS positive
+-- DCO*_N : data clock from ADCs, LVDS negative
+-- FRA*_P : frame start signals from ADCs, LVDS positive
+-- FRA*_N : frame start signals from ADCs, LVDS negative
+--
+-- Outputs:
+-- ADC_clk : clock for parallel ADC data
+-- adcdata : parallel ADC data
+--
+-- Components:
+-- AdcToplevel : top-level module from Xilinx serial ADC reference design
+--
+----------------------------------------------------------------------------------
+
+entity AdcSerialProg is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ init : in std_logic;
+ clock_out : out std_logic;
+ dataA_in : in std_logic_vector(3 downto 0);
+ dataB_in : in std_logic_vector(3 downto 0);
+ data_out : out std_logic;
+ chipnselectA : out std_logic_vector(3 downto 0);
+ chipnselectB : out std_logic_vector(3 downto 0);
+ selREGS : in std_logic_vector(2 downto 0)
+ );
+end AdcSerialProg;
+
+architecture Behavioral of AdcSerialProg is
+
+constant NROFREGS : integer := 10;
+type RomType is array (0 to 8*16-1) of std_logic_vector(16 downto 0); -- highest bit : csa/csb
+--type RomType is array (0 to NROFREGS-1) of std_logic_vector(15 downto 0);
+--CONSTANT REGS : RomType := -- bit15:0=CSA,1=CSB
+-- (
+-- "0000000010000000", -- A0 (bit7=Reset)
+-- "1000000010000000", -- A0 (bit7=Reset)
+-- "0000000100000000", -- A1 (clock stabilize no random binary normal)
+-- "1000000100000000", -- A1 (clock stabilize no random binary normal)
+-- "0000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+-- "1000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+-- "0000001100000000", -- A3 (no test pattern)
+-- "1000001100000000", -- A3 (no test pattern)
+-- "0000010000000000", -- A4 (test pattern)
+-- "1000010000000000" -- A4 (test pattern)
+-- );
+CONSTANT REGS : RomType := -- bit15:0=CSA,1=CSB
+ (
+ "00000000010000000", -- A0 (bit7=Reset)
+ "10000000010000000", -- A0 (bit7=Reset)
+ "00000000100000000", -- A1 (clock stabilize no random binary normal)
+ "10000000100000000", -- A1 (clock stabilize no random binary normal)
+ "00000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+ "10000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+ "00000001100000000", -- A3 (no test pattern)
+ "10000001100000000", -- A3 (no test pattern)
+ "00000010000000000", -- A4 (test pattern)
+ "10000010000000000", -- A4 (test pattern)
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+
+ "00000000010000000", -- A0 (bit7=Reset)
+ "10000000010000000", -- A0 (bit7=Reset)
+ "00000000100000000", -- A1 (clock stabilize no random binary normal)
+ "10000000100000000", -- A1 (clock stabilize no random binary normal)
+ "00000001000000001", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+ "10000001000000001", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+-- "00000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+-- "10000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+ "00000001100000000", -- A3 (no test pattern)
+ "10000001100000000", -- A3 (no test pattern)
+ "00000010000000000", -- A4 (test pattern)
+ "10000010000000000", -- A4 (test pattern)
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+
+ "00000000010000000", -- A0 (bit7=Reset)
+ "10000000010000000", -- A0 (bit7=Reset)
+ "00000000100000000", -- A1 (clock stabilize no random binary normal)
+ "10000000100000000", -- A1 (clock stabilize no random binary normal)
+ "00000001000100111", -- A2 (4mA LVDS no termination enabled 2lanes 16bits)
+ "10000001000100111", -- A2 (4mA LVDS no termination enabled 2lanes 16bits)
+-- "00000001000100000", -- A2 (4mA LVDS no termination enabled 2lanes 16bits)
+-- "10000001000100000", -- A2 (4mA LVDS no termination enabled 2lanes 16bits)
+ "00000001100000000", -- A3 (no test pattern)
+ "10000001100000000", -- A3 (no test pattern)
+ "00000010000000000", -- A4 (test pattern)
+ "10000010000000000", -- A4 (test pattern)
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+
+ "00000000010000000", -- A0 (bit7=Reset)
+ "10000000010000000", -- A0 (bit7=Reset)
+ "00000000100000000", -- A1 (clock stabilize no random binary normal)
+ "10000000100000000", -- A1 (clock stabilize no random binary normal)
+ "00000001001000000", -- A2 (4.5mA LVDS no termination enabled 2lanes 16bits)
+ "10000001001000000", -- A2 (4.5mA LVDS no termination enabled 2lanes 16bits)
+ "00000001100000000", -- A3 (no test pattern)
+ "10000001100000000", -- A3 (no test pattern)
+ "00000010000000000", -- A4 (test pattern)
+ "10000010000000000", -- A4 (test pattern)
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+
+ "00000000010000000", -- A0 (bit7=Reset)
+ "10000000010000000", -- A0 (bit7=Reset)
+ "00000000100000000", -- A1 (clock stabilize no random binary normal)
+ "10000000100000000", -- A1 (clock stabilize no random binary normal)
+ "00000001010100000", -- A2 (2.5mA LVDS +termination enabled 2lanes 16bits)
+ "10000001010100000", -- A2 (2.5mA LVDS +termination enabled 2lanes 16bits)
+ "00000001100000000", -- A3 (no test pattern)
+ "10000001100000000", -- A3 (no test pattern)
+ "00000010000000000", -- A4 (test pattern)
+ "10000010000000000", -- A4 (test pattern)
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+
+ "00000000010000000", -- A0 (bit7=Reset)
+ "10000000010000000", -- A0 (bit7=Reset)
+ "00000000100000000", -- A1 (clock stabilize no random binary normal)
+ "10000000100000000", -- A1 (clock stabilize no random binary normal)
+ "00000001011000000", -- A2 (2.1mA LVDS +termination enabled 2lanes 16bits)
+ "10000001011000000", -- A2 (2.1mA LVDS +termination enabled 2lanes 16bits)
+ "00000001100000000", -- A3 (no test pattern)
+ "10000001100000000", -- A3 (no test pattern)
+ "00000010000000000", -- A4 (test pattern)
+ "10000010000000000", -- A4 (test pattern)
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+
+ "00000000010000000", -- A0 (bit7=Reset)
+ "10000000010000000", -- A0 (bit7=Reset)
+ "00000000100000000", -- A1 (clock stabilize no random binary normal)
+ "10000000100000000", -- A1 (clock stabilize no random binary normal)
+ "00000001011100000", -- A2 (1.75mA LVDS +termination enabled 2lanes 16bits)
+ "10000001011100000", -- A2 (1.75mA LVDS +termination enabled 2lanes 16bits)
+ "00000001100000000", -- A3 (no test pattern)
+ "10000001100000000", -- A3 (no test pattern)
+ "00000010000000000", -- A4 (test pattern)
+ "10000010000000000", -- A4 (test pattern)
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+
+ "00000000010000000", -- A0 (bit7=Reset)
+ "10000000010000000", -- A0 (bit7=Reset)
+ "00000000100000000", -- A1 (clock stabilize no random binary normal)
+ "10000000100000000", -- A1 (clock stabilize no random binary normal)
+ "00000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+ "10000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)
+ "00000001100000000", -- A3 (no test pattern)
+ "10000001100000000", -- A3 (no test pattern)
+ "00000010000000000", -- A4 (test pattern)
+ "10000010000000000", -- A4 (test pattern)
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000", -- dummy
+ "00000000000000000" -- dummy
+
+ );
+
+
+type stage_type is (waiting,cs_high,cs_low,sdo_set,clk_rise,clk_high,clk_fall);
+signal stage_S : stage_type := waiting;
+
+--type adcdata_type is array(0 to 31) of std_logic_vector(13 downto 0);
+type AdcDataOut_type is array(0 to 3) of std_logic_vector(127 downto 0);
+type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0);
+signal bitcount_S : integer range 0 to 15;
+signal regcount_S : integer range 0 to NROFREGS-1;
+signal clock_out_S : std_logic;
+signal data_out_S : std_logic;
+signal chipnselectA_S : std_logic;
+signal chipnselectB_S : std_logic;
+signal REGS_out_S : std_logic_vector(16 downto 0);
+
+begin
+
+process (clock)
+begin
+ if (clock'event and clock = '1') then
+ REGS_out_S <= REGS(conv_integer(selREGS)*16+regcount_S);
+ end if;
+end process;
+
+
+
+clock_out <= clock_out_S;
+data_out <= data_out_S;
+chipnselectA <= chipnselectA_S & chipnselectA_S & chipnselectA_S & chipnselectA_S;
+chipnselectB <= chipnselectB_S & chipnselectB_S & chipnselectB_S & chipnselectB_S;
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ chipnselectA_S <= '1';
+ chipnselectB_S <= '1';
+ clock_out_S <= '0';
+ stage_S <= waiting;
+ else
+ case stage_S is
+ when waiting =>
+ bitcount_S <= 15;
+ regcount_S <= 0;
+ chipnselectA_S <= '1';
+ chipnselectB_S <= '1';
+ clock_out_S <= '0';
+ if init='1' then
+ stage_S <= cs_high;
+ end if;
+ when cs_high =>
+ clock_out_S <= '0';
+ chipnselectA_S <= '1';
+ chipnselectB_S <= '1';
+ stage_S <= cs_low;
+ when cs_low =>
+ clock_out_S <= '0';
+ chipnselectA_S <= REGS_out_S(16);
+ chipnselectB_S <= not REGS_out_S(16);
+ stage_S <= sdo_set;
+ when sdo_set =>
+ data_out_S <= REGS_out_S(bitcount_S);
+ clock_out_S <= '0';
+ stage_S <= clk_rise;
+ when clk_rise =>
+ clock_out_S <= '1';
+ stage_S <= clk_high;
+ when clk_high =>
+ clock_out_S <= '1';
+ stage_S <= clk_fall;
+ when clk_fall =>
+ clock_out_S <= '0';
+ if bitcount_S=0 then
+ bitcount_S <= 15;
+ if regcount_S=NROFREGS-1 then
+ regcount_S <= 0;
+ stage_S <= waiting;
+ else
+ regcount_S <= regcount_S+1;
+ stage_S <= cs_high;
+ end if;
+ else
+ bitcount_S <= bitcount_S-1;
+ stage_S <= sdo_set;
+ end if;
+ when others =>
+ chipnselectA_S <= '1';
+ chipnselectB_S <= '1';
+ clock_out_S <= '0';
+ stage_S <= waiting;
+ end case;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
--- /dev/null
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.STD_LOGIC_ARITH.ALL;
+ use IEEE.std_logic_UNSIGNED.all;
+ use IEEE.std_logic_textio.all;
+ use std.textio.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+
+
+entity AdcToplevel is
+ generic (
+ C_BufioLoc : string := "BUFIO_X0Y6";
+ C_BufrLoc : string := "BUFR_X0Y6";
+ C_IserdesLoc : string := "BUFR_X0Y17";
+ C_StatTaps : integer := 16;
+ C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y1"
+ );
+ port (
+ DCLK_p : in std_logic;
+ DCLK_n : in std_logic; -- Not used.
+ FCLK_p : in std_logic;
+ FCLK_n : in std_logic;
+ DATA_p : in std_logic_vector(7 downto 0);
+ DATA_n : in std_logic_vector(7 downto 0);
+ SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application
+ clockAsync : in std_logic;
+ AdcIntrfcRst : in std_logic;
+ AdcIntrfcEna : in std_logic;
+ AdcBitClkDone : out std_logic;
+ AdcIdlyCtrlRdy : out std_logic;
+ AdcClkDiv : out std_logic;
+ AdcDataClk : in std_logic;
+ AdcDataOut : out std_logic_vector(127 downto 0);
+ ADCs_ready : out std_logic
+ );
+end AdcToplevel;
+
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcToplevel_struct of AdcToplevel is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+component AdcFrame is
+ port (
+ FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT
+ FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT
+ FrmClkRst : in std_logic;
+ FrmClkEna : in std_logic;
+ FrmClk : in std_logic;
+ FrmClkDiv : in std_logic;
+ FrmClkDone : in std_logic; -- Input from clock syncronisation.
+ Frame_out : out std_logic;
+ Frame_OK : out std_logic
+ );
+end component;
+component AdcClock is
+ generic (
+ C_BufioLoc : string := C_BufioLoc;
+ C_BufrLoc : string := C_BufrLoc;
+ C_IserdesLoc : string := C_IserdesLoc;
+ C_StatTaps : integer := C_StatTaps
+ );
+ port (
+ BitClk : in std_logic;
+ BitClkRst : in std_logic;
+ BitClkEna : in std_logic;
+ BitClkReSync : in std_logic;
+ BitClk_MonClkOut : out std_logic; -- CLK output
+ BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input
+ BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output
+ BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input
+ BitClkAlignWarn : out std_logic;
+ BitClkInvrtd : out std_logic;
+ BitClkDone : out std_logic
+ );
+end component;
+component AdcData is
+ port (
+ DatD0_n : in std_logic;
+ DatD0_p : in std_logic;
+ DatD1_n : in std_logic;
+ DatD1_p : in std_logic;
+ DatClk : in std_logic;
+ DatClkDiv : in std_logic;
+ DatRst : in std_logic;
+ DatEna : in std_logic;
+ DatDone : in std_logic;
+ DatOut : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+
+-- Signals
+signal IntRst : std_logic;
+signal IntEna_d : std_logic;
+signal IntEna : std_logic;
+--
+signal IntBitClkDone : std_logic;
+signal IntClk : std_logic;
+signal IntClkDiv : std_logic;
+signal IntDataOut : std_logic_vector(127 downto 0);
+-----------------------------------------------------------------------------------------------
+--
+
+signal AdcBitClkAlgnWrn_S : std_logic := '0';
+signal AdcBitClkInvrtd_S : std_logic := '0';
+signal AdcIdlyCtrlRdy_S : std_logic := '0';
+signal Frame_OK_S : std_logic := '0';
+signal ADCs_ready_S : std_logic := '0';
+signal IntBitClkDone_S : std_logic := '0';
+signal IntBitClkDone0_S : std_logic := '0';
+
+signal slipcounter_S : integer range 0 to 63 := 0;
+signal ClockResync_S : std_logic := '0';
+signal ClockResync0_S : std_logic := '0';
+signal ClockResync1_S : std_logic := '0';
+signal ClockResync2_S : std_logic := '0';
+signal ClockReset_S : std_logic := '0';
+
+signal IntEna_S : std_logic := '0';
+signal IntRst_S : std_logic := '0';
+signal IntEna0_S : std_logic := '0';
+signal IntRst0_S : std_logic := '0';
+signal frame_S : std_logic := '0';
+signal reset_S : std_logic := '0';
+
+
+signal AdcData_negedge : std_logic_vector(127 downto 0);
+signal AdcDataOut_S : std_logic_vector(127 downto 0);
+
+signal AdcIntrfcRst_IdlyCtrl_S : std_logic := '1';
+signal AdcIntrfcRst_IntClkDiv_S : std_logic := '1';
+signal AdcIntrfcRst_clockAsync_S : std_logic := '1';
+
+-- Attributes
+attribute keep : string;
+attribute LOC : string;
+attribute KEEP_HIERARCHY : string;
+attribute keep of IntClk : signal is "TRUE";
+attribute keep of IntClkDiv : signal is "TRUE";
+attribute keep of IntRst_S : signal is "TRUE";
+attribute keep of IntEna_S : signal is "TRUE";
+attribute keep of IntBitClkDone_S : signal is "TRUE";
+
+attribute mark_debug : string;
+-- attribute mark_debug of IntDataOut : signal is "true";
+-- attribute mark_debug of AdcBitClkAlgnWrn_S : signal is "true";
+-- attribute mark_debug of AdcBitClkInvrtd_S : signal is "true";
+-- attribute mark_debug of IntBitClkDone : signal is "true";
+-- attribute mark_debug of ClockReset_S : signal is "true";
+-- attribute mark_debug of ClockResync_S : signal is "true";
+-- attribute mark_debug of IntEna_S : signal is "true";
+-- attribute mark_debug of IntRst_S : signal is "true";
+-- attribute mark_debug of IntBitClkDone_S : signal is "true";
+-- attribute mark_debug of AdcIdlyCtrlRdy_S : signal is "true";
+-- attribute mark_debug of Frame_OK_S : signal is "true";
+-- attribute mark_debug of ADCs_ready_S : signal is "true";
+-- attribute mark_debug of AdcIntrfcRst : signal is "true";
+
+
+
+attribute KEEP_HIERARCHY of AdcToplevel_struct : architecture is "YES";
+-----------------------------------------------------------------------------------------------
+--
+begin
+
+
+AdcClkDiv <= IntClkDiv;
+ADCs_ready <= ADCs_ready_S;
+AdcBitClkDone <= IntBitClkDone_S;
+
+process(IntClkDiv)
+begin
+ if falling_edge(IntClkDiv) then -- falling_edge
+ AdcData_negedge <= IntDataOut;
+ end if;
+end process;
+
+process(AdcDataClk)
+begin
+ if rising_edge(AdcDataClk) then
+ AdcDataOut <= AdcData_negedge;
+ end if;
+end process;
+--AdcDataOut <= IntDataOut;
+
+-----------------------------------------------------------------------------------------------
+-- IDELAYCTRL
+-- An IDELAYCTRL component must be used per IO-bank. Normally a ADC port fits a whole
+-- IO-Bank. The number of IDELAYCTRL components should thus fit with the number of ADC port.
+-- In case of this test design, two ADC ports fit into one IO-Bank, thus only one IDLEAYCTRL
+-- component is needed.
+-- Don not forget to hook the outputs of the IDELAYCTRL components correctly to the reset and
+-- enable for each ADC block.
+-- Don not forget to LOC the IDELAYCTRL components down.
+-----------------------------------------------------------------------------------------------
+Gen_0 : if C_AdcUseIdlyCtrl = 0 generate
+ AdcIdlyCtrlRdy_S <= '1';
+end generate Gen_0;
+Gen_1 : if C_AdcUseIdlyCtrl = 1 generate
+ attribute LOC of AdcToplevel_I_IdlyCtrl_0 : label is C_AdcIdlyCtrlLoc;
+begin
+ AdcToplevel_I_IdlyCtrl_0 : IDELAYCTRL
+--// port map (REFCLK => SysRefClk, RST => ClockResync_S, RDY => AdcIdlyCtrlRdy); --AdcIntrfcRst
+ port map (REFCLK => SysRefClk, RST => AdcIntrfcRst_IdlyCtrl_S, RDY => AdcIdlyCtrlRdy_S); --
+end generate Gen_1;
+AdcIdlyCtrlRdy <= AdcIdlyCtrlRdy_S;
+
+process(SysRefClk)
+begin
+ if (rising_edge(SysRefClk)) then
+ AdcIntrfcRst_IdlyCtrl_S <= AdcIntrfcRst;
+ end if;
+end process;
+process(IntClkDiv,AdcIntrfcRst)
+begin
+ if AdcIntrfcRst='1' then
+ AdcIntrfcRst_IntClkDiv_S <= '1';
+ elsif (rising_edge(IntClkDiv)) then
+ AdcIntrfcRst_IntClkDiv_S <= AdcIntrfcRst;
+ end if;
+end process;
+process(clockAsync,AdcIntrfcRst)
+begin
+ if AdcIntrfcRst='1' then
+ AdcIntrfcRst_clockAsync_S <= '1';
+ elsif (rising_edge(clockAsync)) then
+ AdcIntrfcRst_clockAsync_S <= AdcIntrfcRst;
+ end if;
+end process;
+
+
+-- IntRst and IntEna are the reset and enable signals to be used in the interafce.
+-- they are generated from the incomming system enable and reset.
+AdcToplevel_I_Fdpe_Rst : FDPE
+ generic map (INIT => '1')
+ port map (C => IntClkDiv, CE => '1', PRE => AdcIntrfcRst_IntClkDiv_S, D => '0', Q => IntRst); --AdcIntrfcRst
+AdcToplevel_I_Fdce_Ena_0 : FDCE
+ generic map (INIT => '0')
+ port map (C => IntClkDiv, CE => AdcIntrfcEna, CLR => IntRst, D => '1', Q => IntEna_d);
+AdcToplevel_I_Fdce_Ena_1 : FDCE
+ generic map (INIT => '0')
+ port map (C => IntClkDiv, CE => '1', CLR => IntRst, D => IntEna_d, Q => IntEna);
+
+-----------------------------------------------------------------------------------------------
+-- BIT CLOCK
+-- IntClk and IntClkDiv are the clock to be used in the interface.
+-----------------------------------------------------------------------------------------------
+-- There is no IBUFGDS used on this level of the design.
+-- The IBUFGDS can be found in the AdcIo level.
+-- That is this the reason why the DCLK_n is not used here.
+-- At the AdcIo level the DCLK_n output is connected to GND.
+AdcToplevel_I_AdcClock : AdcClock
+generic map (
+ C_BufioLoc => C_BufioLoc, -- string
+ C_BufrLoc => C_BufrLoc, -- string
+ C_StatTaps => C_StatTaps -- integer
+ )
+port map (
+ BitClk => DCLK_p, -- in
+ BitClkRst => IntRst, -- ClockReset_S, --//IntRst, -- IntRst, -- in
+ BitClkEna => IntEna, -- in
+ BitClkReSync => ClockResync_S, -- AdcReSync, -- in
+ BitClk_MonClkOut => IntClk, -- out -->--|---->----
+ BitClk_MonClkIn => IntClk, -- in --<--|
+ BitClk_RefClkOut => IntClkDiv, -- out -->----|-->----
+ BitClk_RefClkIn => IntClkDiv, -- in --<----|
+ BitClkAlignWarn => AdcBitClkAlgnWrn_S,-- out
+ BitClkInvrtd => AdcBitClkInvrtd_S, -- out
+ BitClkDone => IntBitClkDone -- out Enables the AdcFrame block.
+);
+
+
+AdcToplevel_I_AdcFrame : AdcFrame
+port map (
+ FrmClk_n => FCLK_n, -- in input n from IBUFDS_DIFF_OUT
+ FrmClk_p => FCLK_p, -- in input p from IBUFDS_DIFF_OUT
+ FrmClkRst => IntRst_S, -- in
+ FrmClkEna => IntEna_S, -- in
+ FrmClk => IntClk, -- in
+ FrmClkDiv => IntClkDiv, -- in
+ FrmClkDone => IntBitClkDone_S, -- in From AdcClock done.
+ Frame_out => frame_S,
+ Frame_OK => Frame_OK_S
+);
+
+-----------------------------------------------------------------------------------------------
+-- DATA INPUTS
+-- Default the interface is set in BYTE and MSB first mode.
+-- This is coded in the AdcData level and can be mnodified if wanted.
+-- Enable the generics and all selection possibilities are available.
+-----------------------------------------------------------------------------------------------
+Gen_2 : for cw in 3 downto 0 generate
+ AdcToplevel_I_AdcData : AdcData
+ port map (
+ DatD0_n => DATA_n(cw*2), -- in
+ DatD0_p => DATA_p(cw*2), -- in
+ DatD1_n => DATA_n((cw*2)+1), -- in
+ DatD1_p => DATA_p((cw*2)+1), -- in
+ DatClk => IntClk, -- in
+ DatClkDiv => IntClkDiv, -- in
+ DatRst => IntRst_S, -- in
+ DatEna => IntEna_S, -- in
+ DatDone => IntBitClkDone_S, -- in
+ DatOut => IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-32)
+ );
+end generate Gen_2;
+
+--process(SysRefClk)
+--begin
+-- if (rising_edge(SysRefClk)) then
+-- if (AdcIntrfcRst='1') then -- or (ClockResync0_S='1') then
+-- reset_clockdiv0_S <= '1';
+-- elsif frame_S='1' then
+-- reset_clockdiv0_S <= '0';
+-- end if;
+-- end if;
+--end process;
+
+--process(IntClkDiv,reset_clockdiv0_S)
+--variable counter_V : integer range 0 to 3 := 0;
+--begin
+-- if reset_clockdiv0_S='1' then
+-- ClockResync_S <= '0';
+-- counter_V := 0;
+-- elsif (rising_edge(IntClkDiv)) then
+-- if counter_V<3 then
+-- counter_V := counter_V+1;
+-- ClockResync_S <= '1';
+-- else
+-- ClockResync_S <= '0';
+-- end if;
+-- end if;
+--end process;
+--ClockResync_S <= ClockResync0_S;
+--posedge_to_pulse1: posedge_to_pulse port map(
+-- clock_in => IntClkDiv,
+-- clock_out => clockAsync,
+-- en_clk => '1',
+-- signal_in => ClockResync1_S,
+-- pulse => ClockResync_S
+-- );
+
+--process(clockAsync,AdcIntrfcRst)
+--variable count_V : integer range 0 to 127 := 0;
+--variable countsync_V : integer range 0 to 127 := 7;
+--begin
+-- if (AdcIntrfcRst='1') then
+-- reset_S <= '1';
+-- ClockResync_S <= '1';
+-- count_V := 0;
+-- elsif (rising_edge(clockAsync)) then
+-- if count_V=0 then
+-- if countsync_V>25 then
+-- countsync_V := 7;
+-- else
+-- countsync_V := countsync_V+1;
+-- end if;
+-- end if;
+-- ClockResync1_S <= ClockResync0_S;
+-- ClockResync2_S <= ClockResync1_S;
+-- if (ClockResync2_S='0') and (ClockResync1_S='1') then
+-- reset_S <= '1';
+-- ClockResync_S <= '1';
+-- count_V := 0;
+-- elsif (count_V<countsync_V) then
+-- reset_S <= '1';
+-- ClockResync_S <= '1';
+-- count_V := count_V+1;
+-- elsif (count_V<127) then
+-- reset_S <= '1';
+-- ClockResync_S <= '0';
+-- count_V := count_V+1;
+-- else
+-- ClockResync_S <= '0';
+-- reset_S <= '0';
+-- end if;
+-- end if;
+--end process;
+
+process(clockAsync,AdcIntrfcRst_clockAsync_S)
+variable count_V : integer range 0 to 7 := 0;
+begin
+ if (AdcIntrfcRst_clockAsync_S='1') then
+ reset_S <= '1';
+ ClockResync_S <= '1';
+ count_V := 0;
+ elsif (rising_edge(clockAsync)) then
+ ClockResync1_S <= ClockResync0_S;
+ ClockResync2_S <= ClockResync1_S;
+ if (ClockResync2_S='0') and (ClockResync1_S='1') then
+ ClockResync_S <= '1';
+ ClockReset_S <= '1';
+ reset_S <= '1';
+ count_V := 0;
+ elsif (count_V<2) then
+ ClockResync_S <= '1';
+ ClockReset_S <= '1';
+ reset_S <= '1';
+ count_V := count_V+1;
+ elsif (count_V<7) then
+ ClockResync_S <= '0';
+ ClockReset_S <= '1';
+ reset_S <= '1';
+ count_V := count_V+1;
+ else
+ ClockResync_S <= '0';
+ ClockReset_S <= '0';
+ reset_S <= '0';
+ end if;
+ end if;
+end process;
+
+
+process(IntClkDiv,AdcIntrfcRst_IntClkDiv_S,AdcIdlyCtrlRdy_S)
+begin
+ if (AdcIntrfcRst_IntClkDiv_S='1') or (AdcIdlyCtrlRdy_S='0') then
+ slipcounter_S <= 0;
+ ClockResync0_S <= '0';
+ IntEna0_S <= '0';
+ IntRst0_S <= '1';
+ ADCs_ready_S <= '0';
+ IntBitClkDone0_S <= '0';
+ elsif (rising_edge(IntClkDiv)) then
+ if (IntBitClkDone='0') or (ClockResync0_S='1') then
+ slipcounter_S <= 0;
+ ClockResync0_S <= '0';
+ IntEna0_S <= '0';
+ IntRst0_S <= '1';
+ ADCs_ready_S <= '0';
+ IntBitClkDone0_S <= '0';
+ elsif slipcounter_S<8 then
+ slipcounter_S <= slipcounter_S+1;
+ ClockResync0_S <= '0';
+ IntEna0_S <= '0';
+ IntRst0_S <= '1';
+ IntBitClkDone0_S <= '0';
+ elsif IntBitClkDone='0' then
+ elsif (AdcBitClkAlgnWrn_S='1') or (AdcBitClkInvrtd_S='1') then
+ ClockResync0_S <= '1';
+ elsif slipcounter_S<24 then
+ slipcounter_S <= slipcounter_S+1;
+ ClockResync0_S <= '0';
+ IntEna0_S <= '1';
+ IntRst0_S <= '0';
+ elsif slipcounter_S<28 then
+ slipcounter_S <= slipcounter_S+1;
+ IntBitClkDone0_S <= '1';
+ IntEna0_S <= '1';
+ IntRst0_S <= '0';
+ elsif slipcounter_S<63 then
+ slipcounter_S <= slipcounter_S+1;
+ else
+ if (Frame_OK_S='0') then
+ ClockResync0_S <= '1';
+ else
+ ADCs_ready_S <= '1';
+ end if;
+ end if;
+ end if;
+end process;
+
+sync_IntRst : FDPE
+ generic map (INIT => '0')
+ port map (C => IntClkDiv, CE => '1', PRE => IntRst, D => IntRst0_S, Q => IntRst_S);
+sync_IntEna : FDCE
+ generic map (INIT => '0')
+ port map (C => IntClkDiv, CE => '1', CLR => IntRst, D => IntEna0_S, Q => IntEna_S);
+sync_IntBitClkDone : FDCE
+ generic map (INIT => '0')
+ port map (C => IntClkDiv, CE => '1', CLR => '0', D => IntBitClkDone0_S, Q => IntBitClkDone_S);
+
+
+end AdcToplevel_struct;
\ No newline at end of file
--
-- Inputs:
-- clock200MHz : 200MHz clock input for IODELAYCTRL
--- reset : reset ADCs\r
+-- reset : reset ADCs
-- ADCs_enable : enable signal for ADCs
-- AD*_P : serial data links from ADCs, LVDS positive
-- AD*_N : serial data links from ADCs, LVDS negative
entity FEE_ADCinput_module is
port (
clock200MHz : in std_logic;
+ clock80MHz : in std_logic;
+ clockAsync : in std_logic;
reset : in std_logic;
ADCs_enable : in std_logic;
----ADC1---------------------------------------------
FRB4_P : in std_logic;
FRB4_N : in std_logic;
ADC_clk : out std_logic;
- ADCs_ready : out std_logic;\r
+ ADCs_ready : out std_logic;
adcdata : out array_adc_type
);
end FEE_ADCinput_module;
architecture Behavioral of FEE_ADCinput_module is
-
-
+constant C_StatTaps : integer := 10;-- 10 = midden van 20 steps voor 80MHz/2 DDR
component AdcToplevel is
generic (
- C_AdcChnls : integer := 4; -- Number of ADC in a package
- C_AdcWireInt : integer := 2; -- 2 = 2-wire, 1 = 1-wire interface
- C_BufioLoc : string := "BUFIODQS_X1Y15";
- C_BufrLoc : string := "BUFR_X0Y6";
- C_AdcBits : integer := 16;
- C_StatTaps : integer := 16;
- C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes
- C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y3";
- C_FrmPattern : string := "0000000000001111" -- "0000000011110000" -- Read above text!
+ C_BufioLoc : string := "BUFIO_X0Y6";
+ C_BufrLoc : string := "BUFR_X0Y6";
+ C_IserdesLoc : string := "BUFR_X0Y17";
+ C_StatTaps : integer := C_StatTaps;
+ C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y1"
);
port (
- DCLK_p : in std_logic;
- DCLK_n : in std_logic; -- Not used.
- FCLK_p : in std_logic;
- FCLK_n : in std_logic;
- DATA_p : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
- DATA_n : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
- -- application connections
- SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application
- AdcIntrfcRst : in std_logic;
- AdcIntrfcEna : in std_logic;
- AdcReSync : in std_logic;
- AdcFrmSyncWrn : out std_logic;
- AdcBitClkAlgnWrn : out std_logic;
- AdcBitClkInvrtd : out std_logic;
- AdcBitClkDone : out std_logic;
- AdcIdlyCtrlRdy : out std_logic;
-
- AdcClkDiv : out std_logic;
- AdcDataClk : in std_logic;
- AdcDataClkNot : in std_logic;
- AdcDataOut : out std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
- ADCs_ready : out std_logic;\r
- testOK : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)
+ DCLK_p : in std_logic;
+ DCLK_n : in std_logic; -- Not used.
+ FCLK_p : in std_logic;
+ FCLK_n : in std_logic;
+ DATA_p : in std_logic_vector(7 downto 0);
+ DATA_n : in std_logic_vector(7 downto 0);
+ SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application
+ clockAsync : in std_logic;
+ AdcIntrfcRst : in std_logic;
+ AdcIntrfcEna : in std_logic;
+ AdcBitClkDone : out std_logic;
+ AdcIdlyCtrlRdy : out std_logic;
+ AdcClkDiv : out std_logic;
+ AdcDataClk : in std_logic;
+ AdcDataOut : out std_logic_vector(127 downto 0);
+ ADCs_ready : out std_logic
);
-end component;\r
-
-component FEE_clockbuf80MHz\r
- port(\r
- CLK_IN1 : in std_logic;\r
- CLK_OUT1 : out std_logic;\r
- CLK_OUT2 : out std_logic\r
- );\r
-end component;\r
-\r
-function TermOrNot (Term : integer) return boolean is
-begin
- if (Term = 0) then
- return FALSE;
- else
- return TRUE;
- end if;
-end TermOrNot;
-\r
-constant C_OnChipLvdsTerm : integer := 1;\r
+end component;
+
+component FEE_clockbuf80MHz
+ port(
+ CLK_IN1 : in std_logic;
+ CLK_OUT1 : out std_logic;
+ CLK_OUT2 : out std_logic
+ );
+end component;
+
+--COMPONENT async_fifo_512x128
+-- PORT (
+-- rst : IN STD_LOGIC;
+-- wr_clk : IN STD_LOGIC;
+-- rd_clk : IN STD_LOGIC;
+-- din : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+-- wr_en : IN STD_LOGIC;
+-- rd_en : IN STD_LOGIC;
+-- dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
+-- full : OUT STD_LOGIC;
+-- empty : OUT STD_LOGIC
+-- );
+--END COMPONENT;
+
+constant C_OnChipLvdsTerm : boolean := true;
--type adcdata_type is array(0 to 31) of std_logic_vector(13 downto 0);
-type AdcDataOut_type is array(0 to 3) of std_logic_vector((32*((4/2)*2))-1 downto 0);
+type AdcDataOut_type is array(0 to 3) of std_logic_vector(127 downto 0);
type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0);
signal adcdata1458_P : adcdataserial_type;
signal AdcBitClkInvrtdB_S : std_logic_vector(0 to 3);
signal adcclockB_S : std_logic_vector(0 to 3);
signal AdcDataOutB_S : AdcDataOut_type;
-\r
+
+signal ADCs_ready0_S : std_logic_vector(0 to 7);
+signal ADCs_ready1_S : std_logic_vector(0 to 7);
signal ADCs_ready_S : std_logic_vector(0 to 7);
signal adcdata0_S : array_adc_type;
signal adcdata1_S : array_adc_type;
-signal ADC_clk_S : std_logic;\r
-signal ADC_clknot_S : std_logic;\r
+signal ADC_clk_S : std_logic;
+
+attribute keep : string;
+attribute DONT_TOUCH : string;
+attribute keep of ADC_clk_S : signal is "TRUE";
+attribute DONT_TOUCH of ADC_clk_S : signal is "TRUE";
+
+signal sync_AdcDataOutA_S : AdcDataOut_type;
+signal sync_AdcDataOutB_S : AdcDataOut_type;
-attribute keep : string;\r
-attribute keep of ADC_clk_S : signal is "TRUE";\r
-attribute keep of ADC_clknot_S: signal is "TRUE";\r
+attribute mark_debug : string;
+--attribute mark_debug of ADCs_ready1_S : signal is "true";
begin
ADC_clk <= ADC_clk_S;
-ADCs_ready <= '1' when (ADCs_ready_S=x"ff") and (reset='0') else '0';\r
-\r
+ADCs_ready <= '1' when (ADCs_ready1_S=x"ff") and (reset='0') else '0';
+
+process(clock80MHz) -- synchronise to 1 clock
+begin
+ if (rising_edge(clock80MHz)) then
+ ADCs_ready0_S <= ADCs_ready_S;
+ ADCs_ready1_S <= ADCs_ready0_S;
+ end if;
+end process;
-- ADC inputs ----------------------------------------------------------------------
---- B and A swopped !!!
adcdata1458_0B0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD11B_P, IB => AD11B_N, O => adcdata1458_P(0)(0), OB => adcdata1458_N(0)(0));
adcdata1458_0A0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD11A_P, IB => AD11A_N, O => adcdata1458_P(0)(1), OB => adcdata1458_N(0)(1));
adcdata1458_0B1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD14B_P, IB => AD14B_N, O => adcdata1458_P(0)(2), OB => adcdata1458_N(0)(2));
adcdata1458_0A1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD14A_P, IB => AD14A_N, O => adcdata1458_P(0)(3), OB => adcdata1458_N(0)(3));
adcdata1458_0B2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD15B_P, IB => AD15B_N, O => adcdata1458_P(0)(4), OB => adcdata1458_N(0)(4));
adcdata1458_0A2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD15A_P, IB => AD15A_N, O => adcdata1458_P(0)(5), OB => adcdata1458_N(0)(5));
adcdata1458_0B3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD18B_P, IB => AD18B_N, O => adcdata1458_P(0)(6), OB => adcdata1458_N(0)(6));
adcdata1458_0A3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD18A_P, IB => AD18A_N, O => adcdata1458_P(0)(7), OB => adcdata1458_N(0)(7));
adcdata2367_0B0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD12B_P, IB => AD12B_N, O => adcdata2367_P(0)(0), OB => adcdata2367_N(0)(0));
adcdata2367_0A0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD12A_P, IB => AD12A_N, O => adcdata2367_P(0)(1), OB => adcdata2367_N(0)(1));
adcdata2367_0B1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD13B_P, IB => AD13B_N, O => adcdata2367_P(0)(2), OB => adcdata2367_N(0)(2));
adcdata2367_0A1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD13A_P, IB => AD13A_N, O => adcdata2367_P(0)(3), OB => adcdata2367_N(0)(3));
adcdata2367_0B2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD16B_P, IB => AD16B_N, O => adcdata2367_P(0)(4), OB => adcdata2367_N(0)(4));
adcdata2367_0A2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD16A_P, IB => AD16A_N, O => adcdata2367_P(0)(5), OB => adcdata2367_N(0)(5));
adcdata2367_0B3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD17B_P, IB => AD17B_N, O => adcdata2367_P(0)(6), OB => adcdata2367_N(0)(6));
adcdata2367_0A3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD17A_P, IB => AD17A_N, O => adcdata2367_P(0)(7), OB => adcdata2367_N(0)(7));
adcdata1458_1B0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD21B_P, IB => AD21B_N, O => adcdata1458_P(1)(0), OB => adcdata1458_N(1)(0));
adcdata1458_1A0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD21A_P, IB => AD21A_N, O => adcdata1458_P(1)(1), OB => adcdata1458_N(1)(1));
adcdata1458_1B1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD24B_P, IB => AD24B_N, O => adcdata1458_P(1)(2), OB => adcdata1458_N(1)(2));
adcdata1458_1A1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD24A_P, IB => AD24A_N, O => adcdata1458_P(1)(3), OB => adcdata1458_N(1)(3));
adcdata1458_1B2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD25B_P, IB => AD25B_N, O => adcdata1458_P(1)(4), OB => adcdata1458_N(1)(4));
adcdata1458_1A2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD25A_P, IB => AD25A_N, O => adcdata1458_P(1)(5), OB => adcdata1458_N(1)(5));
adcdata1458_1B3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD28B_P, IB => AD28B_N, O => adcdata1458_P(1)(6), OB => adcdata1458_N(1)(6));
adcdata1458_1A3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD28A_P, IB => AD28A_N, O => adcdata1458_P(1)(7), OB => adcdata1458_N(1)(7));
adcdata2367_1B0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD22B_P, IB => AD22B_N, O => adcdata2367_P(1)(0), OB => adcdata2367_N(1)(0));
adcdata2367_1A0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD22A_P, IB => AD22A_N, O => adcdata2367_P(1)(1), OB => adcdata2367_N(1)(1));
adcdata2367_1B1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD23B_P, IB => AD23B_N, O => adcdata2367_P(1)(2), OB => adcdata2367_N(1)(2));
adcdata2367_1A1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD23A_P, IB => AD23A_N, O => adcdata2367_P(1)(3), OB => adcdata2367_N(1)(3));
adcdata2367_1B2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD26B_P, IB => AD26B_N, O => adcdata2367_P(1)(4), OB => adcdata2367_N(1)(4));
adcdata2367_1A2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD26A_P, IB => AD26A_N, O => adcdata2367_P(1)(5), OB => adcdata2367_N(1)(5));
adcdata2367_1B3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD27B_P, IB => AD27B_N, O => adcdata2367_P(1)(6), OB => adcdata2367_N(1)(6));
adcdata2367_1A3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD27A_P, IB => AD27A_N, O => adcdata2367_P(1)(7), OB => adcdata2367_N(1)(7));
adcdata1458_2B0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD31B_P, IB => AD31B_N, O => adcdata1458_P(2)(0), OB => adcdata1458_N(2)(0));
adcdata1458_2A0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD31A_P, IB => AD31A_N, O => adcdata1458_P(2)(1), OB => adcdata1458_N(2)(1));
adcdata1458_2B1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD34B_P, IB => AD34B_N, O => adcdata1458_P(2)(2), OB => adcdata1458_N(2)(2));
adcdata1458_2A1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD34A_P, IB => AD34A_N, O => adcdata1458_P(2)(3), OB => adcdata1458_N(2)(3));
adcdata1458_2B2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD35B_P, IB => AD35B_N, O => adcdata1458_P(2)(4), OB => adcdata1458_N(2)(4));
adcdata1458_2A2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD35A_P, IB => AD35A_N, O => adcdata1458_P(2)(5), OB => adcdata1458_N(2)(5));
adcdata1458_2B3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD38B_P, IB => AD38B_N, O => adcdata1458_P(2)(6), OB => adcdata1458_N(2)(6));
adcdata1458_2A3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD38A_P, IB => AD38A_N, O => adcdata1458_P(2)(7), OB => adcdata1458_N(2)(7));
adcdata2367_2B0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD32B_P, IB => AD32B_N, O => adcdata2367_P(2)(0), OB => adcdata2367_N(2)(0));
adcdata2367_2A0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD32A_P, IB => AD32A_N, O => adcdata2367_P(2)(1), OB => adcdata2367_N(2)(1));
adcdata2367_2B1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD33B_P, IB => AD33B_N, O => adcdata2367_P(2)(2), OB => adcdata2367_N(2)(2));
adcdata2367_2A1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD33A_P, IB => AD33A_N, O => adcdata2367_P(2)(3), OB => adcdata2367_N(2)(3));
adcdata2367_2B2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD36B_P, IB => AD36B_N, O => adcdata2367_P(2)(4), OB => adcdata2367_N(2)(4));
adcdata2367_2A2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD36A_P, IB => AD36A_N, O => adcdata2367_P(2)(5), OB => adcdata2367_N(2)(5));
adcdata2367_2B3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD37B_P, IB => AD37B_N, O => adcdata2367_P(2)(6), OB => adcdata2367_N(2)(6));
adcdata2367_2A3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD37A_P, IB => AD37A_N, O => adcdata2367_P(2)(7), OB => adcdata2367_N(2)(7));
adcdata1458_3B0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD41B_P, IB => AD41B_N, O => adcdata1458_P(3)(0), OB => adcdata1458_N(3)(0));
adcdata1458_3A0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD41A_P, IB => AD41A_N, O => adcdata1458_P(3)(1), OB => adcdata1458_N(3)(1));
adcdata1458_3B1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD44B_P, IB => AD44B_N, O => adcdata1458_P(3)(2), OB => adcdata1458_N(3)(2));
adcdata1458_3A1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD44A_P, IB => AD44A_N, O => adcdata1458_P(3)(3), OB => adcdata1458_N(3)(3));
adcdata1458_3B2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD45B_P, IB => AD45B_N, O => adcdata1458_P(3)(4), OB => adcdata1458_N(3)(4));
adcdata1458_3A2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD45A_P, IB => AD45A_N, O => adcdata1458_P(3)(5), OB => adcdata1458_N(3)(5));
adcdata1458_3B3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD48B_P, IB => AD48B_N, O => adcdata1458_P(3)(6), OB => adcdata1458_N(3)(6));
adcdata1458_3A3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD48A_P, IB => AD48A_N, O => adcdata1458_P(3)(7), OB => adcdata1458_N(3)(7));
adcdata2367_3B0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD42B_P, IB => AD42B_N, O => adcdata2367_P(3)(0), OB => adcdata2367_N(3)(0));
adcdata2367_3A0 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD42A_P, IB => AD42A_N, O => adcdata2367_P(3)(1), OB => adcdata2367_N(3)(1));
adcdata2367_3B1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD43B_P, IB => AD43B_N, O => adcdata2367_P(3)(2), OB => adcdata2367_N(3)(2));
adcdata2367_3A1 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD43A_P, IB => AD43A_N, O => adcdata2367_P(3)(3), OB => adcdata2367_N(3)(3));
adcdata2367_3B2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD46B_P, IB => AD46B_N, O => adcdata2367_P(3)(4), OB => adcdata2367_N(3)(4));
adcdata2367_3A2 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD46A_P, IB => AD46A_N, O => adcdata2367_P(3)(5), OB => adcdata2367_N(3)(5));
adcdata2367_3B3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD47B_P, IB => AD47B_N, O => adcdata2367_P(3)(6), OB => adcdata2367_N(3)(6));
adcdata2367_3A3 : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => AD47A_P, IB => AD47A_N, O => adcdata2367_P(3)(7), OB => adcdata2367_N(3)(7));
+
+
DCOA1_buf : IBUFGDS
- generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => DCOA1_P, IB => DCOA1_N, O => DCOA1_P_S);
DCOA1_N_S <= '0';
DCOA2_buf : IBUFGDS
- generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => DCOA2_P, IB => DCOA2_N, O => DCOA2_P_S);
DCOA2_N_S <= '0';
DCOA3_buf : IBUFGDS
- generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => DCOA3_P, IB => DCOA3_N, O => DCOA3_P_S);
DCOA3_N_S <= '0';
DCOA4_buf : IBUFGDS
- generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => DCOA4_P, IB => DCOA4_N, O => DCOA4_P_S);
DCOA4_N_S <= '0';
DCOB1_buf : IBUFGDS
- generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => DCOB1_P, IB => DCOB1_N, O => DCOB1_P_S);
DCOB1_N_S <= '0';
DCOB2_buf : IBUFGDS
- generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => DCOB2_P, IB => DCOB2_N, O => DCOB2_P_S);
DCOB2_N_S <= '0';
DCOB3_buf : IBUFGDS
- generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => DCOB3_P, IB => DCOB3_N, O => DCOB3_P_S);
DCOB3_N_S <= '0';
DCOB4_buf : IBUFGDS
- generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => DCOB4_P, IB => DCOB4_N, O => DCOB4_P_S);
DCOB4_N_S <= '0';
FRA1_buf : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => FRA1_P, IB => FRA1_N, O => FRA1_P_S, OB => FRA1_N_S);
FRA2_buf : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => FRA2_P, IB => FRA2_N, O => FRA2_P_S, OB => FRA2_N_S);
FRA3_buf : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => FRA3_P, IB => FRA3_N, O => FRA3_P_S, OB => FRA3_N_S);
FRA4_buf : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => FRA4_P, IB => FRA4_N, O => FRA4_P_S, OB => FRA4_N_S);
-
FRB1_buf : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => FRB1_P, IB => FRB1_N, O => FRB1_P_S, OB => FRB1_N_S);
FRB2_buf : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => FRB2_P, IB => FRB2_N, O => FRB2_P_S, OB => FRB2_N_S);
FRB3_buf : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => FRB3_P, IB => FRB3_N, O => FRB3_P_S, OB => FRB3_N_S);
FRB4_buf : IBUFDS_DIFF_OUT
- generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm)
port map (I => FRB4_P, IB => FRB4_N, O => FRB4_P_S, OB => FRB4_N_S);
AdcToplevel1458_1: AdcToplevel
generic map(
- C_AdcChnls => 4,
- C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
- C_BufioLoc => "BUFIODQS_X1Y14",
- C_BufrLoc => "BUFR_X1Y7",
- C_AdcBits => 16,
--- C_StatTaps => 16,
+ C_BufioLoc => "BUFIO_X1Y5",
+ C_BufrLoc => "BUFR_X1Y4",
+ C_IserdesLoc => "ILOGIC_X1Y74",
+ C_StatTaps => C_StatTaps, -- 8
C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
- C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3" --IDELAYCTRL_X2Y3
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y1"
)
port map(
DCLK_p => DCOA1_P_S,
DATA_n => adcdata1458_n(0),
-- application connections
SysRefClk => clock200MHz,
+ clockAsync => clockAsync,
AdcIntrfcRst => reset,
AdcIntrfcEna => ADCs_enable,
- AdcReSync => '0',
- AdcFrmSyncWrn => AdcFrmSyncWrnA_S(0),
- AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(0),
- AdcBitClkInvrtd => AdcBitClkInvrtdA_S(0),
AdcBitClkDone => AdcBitClkDoneA_S(0),
AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(0),
AdcClkDiv => adcclockA_S(0),
- adcdataclk => ADC_clk_S,
- adcdataclknot => ADC_clknot_S,
+ AdcDataClk => ADC_clk_S,
AdcDataOut => AdcDataOutA_S(0),
- ADCs_ready => ADCs_ready_S(0),\r
- testOK => open,
- testword0 => open);
+ ADCs_ready => ADCs_ready_S(0)
+ );
AdcToplevel2356_1: AdcToplevel
generic map(
- C_AdcChnls => 4,
- C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
- C_BufioLoc => "BUFIODQS_X1Y13",
- C_BufrLoc => "BUFR_X1Y6",
- C_AdcBits => 16,
--- C_StatTaps => 16,
+ C_BufioLoc => "BUFIO_X1Y6",
+ C_BufrLoc => "BUFR_X1Y7",
+ C_IserdesLoc => "ILOGIC_X1Y76",
+ C_StatTaps => C_StatTaps, -- 8
C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
- C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3"
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y1"
)
port map(
DCLK_p => DCOB1_P_S,
DATA_n => adcdata2367_N(0),
-- application connections
SysRefClk => clock200MHz,
+ clockAsync => clockAsync,
AdcIntrfcRst => reset,
AdcIntrfcEna => ADCs_enable,
- AdcReSync => '0',
- AdcFrmSyncWrn => AdcFrmSyncWrnB_S(0),
- AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(0),
- AdcBitClkInvrtd => AdcBitClkInvrtdB_S(0),
AdcBitClkDone => AdcBitClkDoneB_S(0),
AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(0),
AdcClkDiv => adcclockB_S(0),
- adcdataclk => ADC_clk_S,
- adcdataclknot => ADC_clknot_S,
+ AdcDataClk => ADC_clk_S,
AdcDataOut => AdcDataOutB_S(0),
- ADCs_ready => ADCs_ready_S(1),\r
- testOK => open,
- testword0 => open);
+ ADCs_ready => ADCs_ready_S(1)
+ );
AdcToplevel1458_2: AdcToplevel
generic map(
- C_AdcChnls => 4,
- C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
- C_BufioLoc => "BUFIODQS_X0Y13",
- C_BufrLoc => "BUFR_X0Y6",
- C_AdcBits => 16,
--- C_StatTaps => 16,
+ C_BufioLoc => "BUFIO_X0Y6",
+ C_BufrLoc => "BUFR_X0Y7",
+ C_IserdesLoc => "ILOGIC_X0Y76",
+ C_StatTaps => C_StatTaps, -- 8
C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
- C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3" --IDELAYCTRL_X2Y3
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y1"
)
port map(
DCLK_p => DCOA2_P_S,
DATA_n => adcdata1458_n(1),
-- application connections
SysRefClk => clock200MHz,
+ clockAsync => clockAsync,
AdcIntrfcRst => reset,
AdcIntrfcEna => ADCs_enable,
- AdcReSync => '0',
- AdcFrmSyncWrn => AdcFrmSyncWrnA_S(1),
- AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(1),
- AdcBitClkInvrtd => AdcBitClkInvrtdA_S(1),
AdcBitClkDone => AdcBitClkDoneA_S(1),
AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(1),
AdcClkDiv => adcclockA_S(1),
- adcdataclk => ADC_clk_S,
- adcdataclknot => ADC_clknot_S,
+ AdcDataClk => ADC_clk_S,
AdcDataOut => AdcDataOutA_S(1),
- ADCs_ready => ADCs_ready_S(2),\r
- testOK => open,
- testword0 => open);
+ ADCs_ready => ADCs_ready_S(2)
+ );
AdcToplevel2356_2: AdcToplevel
generic map(
- C_AdcChnls => 4,
- C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
- C_BufioLoc => "BUFIODQS_X0Y14",
- C_BufrLoc => "BUFR_X0Y7",
- C_AdcBits => 16,
--- C_StatTaps => 16,
+ C_BufioLoc => "BUFIO_X0Y5",
+ C_BufrLoc => "BUFR_X0Y4",
+ C_IserdesLoc => "ILOGIC_X0Y74",
+ C_StatTaps => C_StatTaps, -- 8
C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
- C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3"
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y1"
)
port map(
DCLK_p => DCOB2_P_S,
DATA_n => adcdata2367_N(1),
-- application connections
SysRefClk => clock200MHz,
+ clockAsync => clockAsync,
AdcIntrfcRst => reset,
AdcIntrfcEna => ADCs_enable,
- AdcReSync => '0',
- AdcFrmSyncWrn => AdcFrmSyncWrnB_S(1),
- AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(1),
- AdcBitClkInvrtd => AdcBitClkInvrtdB_S(1),
AdcBitClkDone => AdcBitClkDoneB_S(1),
AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(1),
AdcClkDiv => adcclockB_S(1),
- adcdataclk => ADC_clk_S,
- adcdataclknot => ADC_clknot_S,
+ AdcDataClk => ADC_clk_S,
AdcDataOut => AdcDataOutB_S(1),
- ADCs_ready => ADCs_ready_S(3),\r
- testOK => open,
- testword0 => open);
+ ADCs_ready => ADCs_ready_S(3)
+ );
AdcToplevel1458_3: AdcToplevel
generic map(
- C_AdcChnls => 4,
- C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
- C_BufioLoc => "BUFIODQS_X0Y10",
- C_BufrLoc => "BUFR_X0Y5",
- C_AdcBits => 16,
--- C_StatTaps => 16,
+ C_BufioLoc => "BUFIO_X0Y10",
+ C_BufrLoc => "BUFR_X0Y11",
+ C_IserdesLoc => "ILOGIC_X0Y126",
+ C_StatTaps => C_StatTaps, -- 8
C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
- C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2" --IDELAYCTRL_X2Y3
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2"
)
port map(
DCLK_p => DCOA3_P_S,
DATA_n => adcdata1458_n(2),
-- application connections
SysRefClk => clock200MHz,
+ clockAsync => clockAsync,
AdcIntrfcRst => reset,
AdcIntrfcEna => ADCs_enable,
- AdcReSync => '0',
- AdcFrmSyncWrn => AdcFrmSyncWrnA_S(2),
- AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(2),
- AdcBitClkInvrtd => AdcBitClkInvrtdA_S(2),
AdcBitClkDone => AdcBitClkDoneA_S(2),
AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(2),
AdcClkDiv => adcclockA_S(2),
- adcdataclk => ADC_clk_S,
- adcdataclknot => ADC_clknot_S,
+ AdcDataClk => ADC_clk_S,
AdcDataOut => AdcDataOutA_S(2),
- ADCs_ready => ADCs_ready_S(4),\r
- testOK => open,
- testword0 => open);
+ ADCs_ready => ADCs_ready_S(4)
+ );
AdcToplevel2356_3: AdcToplevel
generic map(
- C_AdcChnls => 4,
- C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
- C_BufioLoc => "BUFIODQS_X0Y9",
- C_BufrLoc => "BUFR_X0Y4",
- C_AdcBits => 16,
--- C_StatTaps => 16,
+ C_BufioLoc => "BUFIO_X0Y9",
+ C_BufrLoc => "BUFR_X0Y8",
+ C_IserdesLoc => "ILOGIC_X0Y124",
+ C_StatTaps => C_StatTaps, -- 8
C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2"
)
DATA_n => adcdata2367_N(2),
-- application connections
SysRefClk => clock200MHz,
+ clockAsync => clockAsync,
AdcIntrfcRst => reset,
AdcIntrfcEna => ADCs_enable,
- AdcReSync => '0',
- AdcFrmSyncWrn => AdcFrmSyncWrnB_S(2),
- AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(2),
- AdcBitClkInvrtd => AdcBitClkInvrtdB_S(2),
AdcBitClkDone => AdcBitClkDoneB_S(2),
AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(2),
AdcClkDiv => adcclockB_S(2),
- adcdataclk => ADC_clk_S,
- adcdataclknot => ADC_clknot_S,
+ AdcDataClk => ADC_clk_S,
AdcDataOut => AdcDataOutB_S(2),
- ADCs_ready => ADCs_ready_S(5),\r
- testOK => open,
- testword0 => open);
+ ADCs_ready => ADCs_ready_S(5)
+ );
AdcToplevel1458_4: AdcToplevel
generic map(
- C_AdcChnls => 4,
- C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
- C_BufioLoc => "BUFIODQS_X2Y9",
- C_BufrLoc => "BUFR_X2Y4",
- C_AdcBits => 16,
--- C_StatTaps => 16,
+ C_BufioLoc => "BUFIO_X0Y14",
+ C_BufrLoc => "BUFR_X0Y15",
+ C_IserdesLoc => "ILOGIC_X0Y176",
+ C_StatTaps => C_StatTaps, -- 8
C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
- C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2" --IDELAYCTRL_X2Y3
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3"
)
port map(
DCLK_p => DCOA4_P_S,
DATA_n => adcdata1458_n(3),
-- application connections
SysRefClk => clock200MHz,
+ clockAsync => clockAsync,
AdcIntrfcRst => reset,
AdcIntrfcEna => ADCs_enable,
- AdcReSync => '0',
- AdcFrmSyncWrn => AdcFrmSyncWrnA_S(3),
- AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(3),
- AdcBitClkInvrtd => AdcBitClkInvrtdA_S(3),
AdcBitClkDone => AdcBitClkDoneA_S(3),
AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(3),
AdcClkDiv => adcclockA_S(3),
- adcdataclk => ADC_clk_S,
- adcdataclknot => ADC_clknot_S,
+ AdcDataClk => ADC_clk_S,
AdcDataOut => AdcDataOutA_S(3),
- ADCs_ready => ADCs_ready_S(6),\r
- testOK => open,
- testword0 => open);
+ ADCs_ready => ADCs_ready_S(6)
+ );
AdcToplevel2356_4: AdcToplevel
generic map(
- C_AdcChnls => 4,
- C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
- C_BufioLoc => "BUFIODQS_X2Y10",
- C_BufrLoc => "BUFR_X2Y5",
- C_AdcBits => 16,
--- C_StatTaps => 16,
+ C_BufioLoc => "BUFIO_X0Y13",
+ C_BufrLoc => "BUFR_X0Y12",
+ C_IserdesLoc => "ILOGIC_X0Y174",
+ C_StatTaps => C_StatTaps, -- 8
C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
- C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2"
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3"
)
port map(
DCLK_p => DCOB4_P_S,
DATA_n => adcdata2367_N(3),
-- application connections
SysRefClk => clock200MHz,
+ clockAsync => clockAsync,
AdcIntrfcRst => reset,
AdcIntrfcEna => ADCs_enable,
- AdcReSync => '0',
- AdcFrmSyncWrn => AdcFrmSyncWrnB_S(3),
- AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(3),
- AdcBitClkInvrtd => AdcBitClkInvrtdB_S(3),
AdcBitClkDone => AdcBitClkDoneB_S(3),
AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(3),
AdcClkDiv => adcclockB_S(3),
- adcdataclk => ADC_clk_S,
- adcdataclknot => ADC_clknot_S,
+ AdcDataClk => ADC_clk_S,
AdcDataOut => AdcDataOutB_S(3),
- ADCs_ready => ADCs_ready_S(7),\r
- testOK => open,
- testword0 => open);
-
---ADCclkbuf : BUFG port map (
--- O => ADC_clk_S,
--- I => adcclockB_S(0));\r
- \r
-FEE_clockbuf80MHz1: FEE_clockbuf80MHz port map(\r
- CLK_IN1 => adcclockA_S(0),\r
- CLK_OUT1 => ADC_clk_S,\r
- CLK_OUT2 => ADC_clknot_S);\r
-
-gen_adcpar1: for chipnr in 0 to 3 generate\r
+ ADCs_ready => ADCs_ready_S(7)
+ );
+
+
-adcdata0_S((3-chipnr)*8+1) <= AdcDataOutA_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutA_S(chipnr)(0*32+15 downto 0*32+10);
-adcdata0_S((3-chipnr)*8+2) <= not (AdcDataOutA_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutA_S(chipnr)(1*32+15 downto 1*32+10));
-adcdata0_S((3-chipnr)*8+5) <= AdcDataOutA_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutA_S(chipnr)(2*32+15 downto 2*32+10);
-adcdata0_S((3-chipnr)*8+6) <= not (AdcDataOutA_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutA_S(chipnr)(3*32+15 downto 3*32+10));
+ADCclkbuf : BUFG port map (
+ O => ADC_clk_S,
+ I => adcclockA_S(0));
-adcdata0_S((3-chipnr)*8+0) <= not (AdcDataOutB_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutB_S(chipnr)(0*32+15 downto 0*32+10));
-adcdata0_S((3-chipnr)*8+3) <= AdcDataOutB_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutB_S(chipnr)(1*32+15 downto 1*32+10);
-adcdata0_S((3-chipnr)*8+4) <= not (AdcDataOutB_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutB_S(chipnr)(2*32+15 downto 2*32+10));
-adcdata0_S((3-chipnr)*8+7) <= AdcDataOutB_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutB_S(chipnr)(3*32+15 downto 3*32+10);
+gen_adcpar1: for chipnr in 0 to 3 generate
+
+--process(ADC_clk_S) -- synchronise to 1 clock
+--begin
+-- if (rising_edge(ADC_clk_S)) then
+adcdata0_S((chipnr)*8+1) <= (sync_AdcDataOutA_S(chipnr)(0*32+7 downto 0*32+0) & sync_AdcDataOutA_S(chipnr)(0*32+15 downto 0*32+10));
+adcdata0_S((chipnr)*8+2) <= (sync_AdcDataOutA_S(chipnr)(1*32+7 downto 1*32+0) & sync_AdcDataOutA_S(chipnr)(1*32+15 downto 1*32+10));
+adcdata0_S((chipnr)*8+5) <= (sync_AdcDataOutA_S(chipnr)(2*32+7 downto 2*32+0) & sync_AdcDataOutA_S(chipnr)(2*32+15 downto 2*32+10));
+adcdata0_S((chipnr)*8+6) <= (sync_AdcDataOutA_S(chipnr)(3*32+7 downto 3*32+0) & sync_AdcDataOutA_S(chipnr)(3*32+15 downto 3*32+10));
+
+adcdata0_S((chipnr)*8+0) <= (sync_AdcDataOutB_S(chipnr)(0*32+7 downto 0*32+0) & sync_AdcDataOutB_S(chipnr)(0*32+15 downto 0*32+10));
+adcdata0_S((chipnr)*8+3) <= (sync_AdcDataOutB_S(chipnr)(1*32+7 downto 1*32+0) & sync_AdcDataOutB_S(chipnr)(1*32+15 downto 1*32+10));
+adcdata0_S((chipnr)*8+4) <= (sync_AdcDataOutB_S(chipnr)(2*32+7 downto 2*32+0) & sync_AdcDataOutB_S(chipnr)(2*32+15 downto 2*32+10));
+adcdata0_S((chipnr)*8+7) <= (sync_AdcDataOutB_S(chipnr)(3*32+7 downto 3*32+0) & sync_AdcDataOutB_S(chipnr)(3*32+15 downto 3*32+10));
+-- end if;
+--end process;
end generate;
-process(ADC_clk_S) -- synchronise to 1 clock
-begin
- if (rising_edge(ADC_clk_S)) then
- adcdata1_S <= adcdata0_S;
- adcdata <= adcdata1_S;
- end if;
-end process;
+adcdata <= adcdata0_S;
+
+sync_AdcDataOutA_S <= AdcDataOutA_S;
+sync_AdcDataOutB_S <= AdcDataOutB_S;
+
+--0 <- B0 =1
+--1 <- A0 =0
+--2 <- A1 =2
+--3 <- B1 =3
+--4 <- B2 =5
+--5 <- A2 =4
+--6 <- A3 =6
+--7 <- B3 =7
+
end Behavioral;
--- /dev/null
+NET "AD11A_N" DIFF_TERM = "TRUE";
+NET "AD11A_N" IOSTANDARD = LVDS;
+NET "AD11A_N" LOC = AB7;
+NET "AD11A_P" DIFF_TERM = "TRUE";
+NET "AD11A_P" IOSTANDARD = LVDS;
+NET "AD11A_P" LOC = AB8;
+NET "AD21A_N" DIFF_TERM = "TRUE";
+NET "AD21A_N" IOSTANDARD = LVDS_25;
+NET "AD21A_N" LOC = AB22;
+NET "AD21A_P" DIFF_TERM = "TRUE";
+NET "AD21A_P" IOSTANDARD = LVDS_25;
+NET "AD21A_P" LOC = AA21;
+NET "AD31A_N" DIFF_TERM = "TRUE";
+NET "AD31A_N" IOSTANDARD = LVDS_25;
+NET "AD31A_N" LOC = N17;
+NET "AD31A_P" DIFF_TERM = "TRUE";
+NET "AD31A_P" IOSTANDARD = LVDS_25;
+NET "AD31A_P" LOC = P16;
+NET "AD41A_N" DIFF_TERM = "TRUE";
+NET "AD41A_N" IOSTANDARD = LVDS_25;
+NET "AD41A_N" LOC = A19;
+NET "AD41A_P" DIFF_TERM = "TRUE";
+NET "AD41A_P" IOSTANDARD = LVDS_25;
+NET "AD41A_P" LOC = B18;
+NET "AD11B_N" DIFF_TERM = "TRUE";
+NET "AD11B_N" IOSTANDARD = LVDS;
+NET "AD11B_N" LOC = AB6;
+NET "AD11B_P" DIFF_TERM = "TRUE";
+NET "AD11B_P" IOSTANDARD = LVDS;
+NET "AD11B_P" LOC = AA6;
+NET "AD21B_N" DIFF_TERM = "TRUE";
+NET "AD21B_N" IOSTANDARD = LVDS_25;
+NET "AD21B_N" LOC = Y17;
+NET "AD21B_P" DIFF_TERM = "TRUE";
+NET "AD21B_P" IOSTANDARD = LVDS_25;
+NET "AD21B_P" LOC = W17;
+NET "AD31B_N" DIFF_TERM = "TRUE";
+NET "AD31B_N" IOSTANDARD = LVDS_25;
+NET "AD31B_N" LOC = P22;
+NET "AD31B_P" DIFF_TERM = "TRUE";
+NET "AD31B_P" IOSTANDARD = LVDS_25;
+NET "AD31B_P" LOC = P21;
+NET "AD41B_N" DIFF_TERM = "TRUE";
+NET "AD41B_N" IOSTANDARD = LVDS_25;
+NET "AD41B_N" LOC = C20;
+NET "AD41B_P" DIFF_TERM = "TRUE";
+NET "AD41B_P" IOSTANDARD = LVDS_25;
+NET "AD41B_P" LOC = C19;
+NET "AD12A_N" DIFF_TERM = "TRUE";
+NET "AD12A_N" IOSTANDARD = LVDS;
+NET "AD12A_N" LOC = U6;
+NET "AD12A_P" DIFF_TERM = "TRUE";
+NET "AD12A_P" IOSTANDARD = LVDS;
+NET "AD12A_P" LOC = U7;
+NET "AD22A_N" DIFF_TERM = "TRUE";
+NET "AD22A_N" IOSTANDARD = LVDS_25;
+NET "AD22A_N" LOC = Y16;
+NET "AD22A_P" DIFF_TERM = "TRUE";
+NET "AD22A_P" IOSTANDARD = LVDS_25;
+NET "AD22A_P" LOC = W16;
+NET "AD32A_N" DIFF_TERM = "TRUE";
+NET "AD32A_N" IOSTANDARD = LVDS_25;
+NET "AD32A_N" LOC = R19;
+NET "AD32A_P" DIFF_TERM = "TRUE";
+NET "AD32A_P" IOSTANDARD = LVDS_25;
+NET "AD32A_P" LOC = R18;
+NET "AD42A_N" DIFF_TERM = "TRUE";
+NET "AD42A_N" IOSTANDARD = LVDS_25;
+NET "AD42A_N" LOC = B22;
+NET "AD42A_P" DIFF_TERM = "TRUE";
+NET "AD42A_P" IOSTANDARD = LVDS_25;
+NET "AD42A_P" LOC = C22;
+NET "AD12B_N" DIFF_TERM = "TRUE";
+NET "AD12B_N" IOSTANDARD = LVDS;
+NET "AD12B_N" LOC = AB5;
+NET "AD12B_P" DIFF_TERM = "TRUE";
+NET "AD12B_P" IOSTANDARD = LVDS;
+NET "AD12B_P" LOC = AA5;
+NET "AD22B_N" DIFF_TERM = "TRUE";
+NET "AD22B_N" IOSTANDARD = LVDS_25;
+NET "AD22B_N" LOC = AB17;
+NET "AD22B_P" DIFF_TERM = "TRUE";
+NET "AD22B_P" IOSTANDARD = LVDS_25;
+NET "AD22B_P" LOC = AA16;
+NET "AD32B_N" DIFF_TERM = "TRUE";
+NET "AD32B_N" IOSTANDARD = LVDS_25;
+NET "AD32B_N" LOC = R22;
+NET "AD32B_P" DIFF_TERM = "TRUE";
+NET "AD32B_P" IOSTANDARD = LVDS_25;
+NET "AD32B_P" LOC = R21;
+NET "AD42B_N" DIFF_TERM = "TRUE";
+NET "AD42B_N" IOSTANDARD = LVDS_25;
+NET "AD42B_N" LOC = A21;
+NET "AD42B_P" DIFF_TERM = "TRUE";
+NET "AD42B_P" IOSTANDARD = LVDS_25;
+NET "AD42B_P" LOC = A20;
+NET "AD13A_N" DIFF_TERM = "TRUE";
+NET "AD13A_N" IOSTANDARD = LVDS;
+NET "AD13A_N" LOC = W7;
+NET "AD13A_P" DIFF_TERM = "TRUE";
+NET "AD13A_P" IOSTANDARD = LVDS;
+NET "AD13A_P" LOC = V7;
+NET "AD23A_N" DIFF_TERM = "TRUE";
+NET "AD23A_N" IOSTANDARD = LVDS_25;
+NET "AD23A_N" LOC = AB16;
+NET "AD23A_P" DIFF_TERM = "TRUE";
+NET "AD23A_P" IOSTANDARD = LVDS_25;
+NET "AD23A_P" LOC = AB15;
+NET "AD33A_N" DIFF_TERM = "TRUE";
+NET "AD33A_N" IOSTANDARD = LVDS_25;
+NET "AD33A_N" LOC = P17;
+NET "AD33A_P" DIFF_TERM = "TRUE";
+NET "AD33A_P" IOSTANDARD = LVDS_25;
+NET "AD33A_P" LOC = R17;
+NET "AD43A_N" DIFF_TERM = "TRUE";
+NET "AD43A_N" IOSTANDARD = LVDS_25;
+NET "AD43A_N" LOC = B21;
+NET "AD43A_P" DIFF_TERM = "TRUE";
+NET "AD43A_P" IOSTANDARD = LVDS_25;
+NET "AD43A_P" LOC = B20;
+NET "AD13B_N" DIFF_TERM = "TRUE";
+NET "AD13B_N" IOSTANDARD = LVDS;
+NET "AD13B_N" LOC = AA8;
+NET "AD13B_P" DIFF_TERM = "TRUE";
+NET "AD13B_P" IOSTANDARD = LVDS;
+NET "AD13B_P" LOC = AA9;
+NET "AD23B_N" DIFF_TERM = "TRUE";
+NET "AD23B_N" IOSTANDARD = LVDS_25;
+NET "AD23B_N" LOC = V18;
+NET "AD23B_P" DIFF_TERM = "TRUE";
+NET "AD23B_P" IOSTANDARD = LVDS_25;
+NET "AD23B_P" LOC = U17;
+NET "AD33B_N" DIFF_TERM = "TRUE";
+NET "AD33B_N" IOSTANDARD = LVDS_25;
+NET "AD33B_N" LOC = M22;
+NET "AD33B_P" DIFF_TERM = "TRUE";
+NET "AD33B_P" IOSTANDARD = LVDS_25;
+NET "AD33B_P" LOC = N22;
+NET "AD43B_N" DIFF_TERM = "TRUE";
+NET "AD43B_N" IOSTANDARD = LVDS_25;
+NET "AD43B_N" LOC = A18;
+NET "AD43B_P" DIFF_TERM = "TRUE";
+NET "AD43B_P" IOSTANDARD = LVDS_25;
+NET "AD43B_P" LOC = B17;
+NET "AD14A_N" DIFF_TERM = "TRUE";
+NET "AD14A_N" IOSTANDARD = LVDS;
+NET "AD14A_N" LOC = Y6;
+NET "AD14A_P" DIFF_TERM = "TRUE";
+NET "AD14A_P" IOSTANDARD = LVDS;
+NET "AD14A_P" LOC = W6;
+NET "AD24A_N" DIFF_TERM = "TRUE";
+NET "AD24A_N" IOSTANDARD = LVDS_25;
+NET "AD24A_N" LOC = AA15;
+NET "AD24A_P" DIFF_TERM = "TRUE";
+NET "AD24A_P" IOSTANDARD = LVDS_25;
+NET "AD24A_P" LOC = AA14;
+NET "AD34A_N" DIFF_TERM = "TRUE";
+NET "AD34A_N" IOSTANDARD = LVDS_25;
+NET "AD34A_N" LOC = P20;
+NET "AD34A_P" DIFF_TERM = "TRUE";
+NET "AD34A_P" IOSTANDARD = LVDS_25;
+NET "AD34A_P" LOC = P19;
+NET "AD44A_N" DIFF_TERM = "TRUE";
+NET "AD44A_N" IOSTANDARD = LVDS_25;
+NET "AD44A_N" LOC = D22;
+NET "AD44A_P" DIFF_TERM = "TRUE";
+NET "AD44A_P" IOSTANDARD = LVDS_25;
+NET "AD44A_P" LOC = D21;
+NET "AD14B_N" DIFF_TERM = "TRUE";
+NET "AD14B_N" IOSTANDARD = LVDS;
+NET "AD14B_N" LOC = V8;
+NET "AD14B_P" DIFF_TERM = "TRUE";
+NET "AD14B_P" IOSTANDARD = LVDS;
+NET "AD14B_P" LOC = U8;
+NET "AD24B_N" DIFF_TERM = "TRUE";
+NET "AD24B_N" IOSTANDARD = LVDS_25;
+NET "AD24B_N" LOC = AB21;
+NET "AD24B_P" DIFF_TERM = "TRUE";
+NET "AD24B_P" IOSTANDARD = LVDS_25;
+NET "AD24B_P" LOC = AA20;
+NET "AD34B_N" DIFF_TERM = "TRUE";
+NET "AD34B_N" IOSTANDARD = LVDS_25;
+NET "AD34B_N" LOC = K22;
+NET "AD34B_P" DIFF_TERM = "TRUE";
+NET "AD34B_P" IOSTANDARD = LVDS_25;
+NET "AD34B_P" LOC = K21;
+NET "AD44B_N" DIFF_TERM = "TRUE";
+NET "AD44B_N" IOSTANDARD = LVDS_25;
+NET "AD44B_N" LOC = D20;
+NET "AD44B_P" DIFF_TERM = "TRUE";
+NET "AD44B_P" IOSTANDARD = LVDS_25;
+NET "AD44B_P" LOC = D19;
+NET "AD15A_N" DIFF_TERM = "TRUE";
+NET "AD15A_N" IOSTANDARD = LVDS;
+NET "AD15A_N" LOC = W10;
+NET "AD15A_P" DIFF_TERM = "TRUE";
+NET "AD15A_P" IOSTANDARD = LVDS;
+NET "AD15A_P" LOC = V10;
+NET "AD25A_N" DIFF_TERM = "TRUE";
+NET "AD25A_N" IOSTANDARD = LVDS_25;
+NET "AD25A_N" LOC = W22;
+NET "AD25A_P" DIFF_TERM = "TRUE";
+NET "AD25A_P" IOSTANDARD = LVDS_25;
+NET "AD25A_P" LOC = W21;
+NET "AD35A_N" DIFF_TERM = "TRUE";
+NET "AD35A_N" IOSTANDARD = LVDS_25;
+NET "AD35A_N" LOC = L21;
+NET "AD35A_P" DIFF_TERM = "TRUE";
+NET "AD35A_P" IOSTANDARD = LVDS_25;
+NET "AD35A_P" LOC = M20;
+NET "AD45A_N" DIFF_TERM = "TRUE";
+NET "AD45A_N" IOSTANDARD = LVDS_25;
+NET "AD45A_N" LOC = A15;
+NET "AD45A_P" DIFF_TERM = "TRUE";
+NET "AD45A_P" IOSTANDARD = LVDS_25;
+NET "AD45A_P" LOC = B15;
+NET "AD15B_N" DIFF_TERM = "TRUE";
+NET "AD15B_N" IOSTANDARD = LVDS;
+NET "AD15B_N" LOC = Y11;
+NET "AD15B_P" DIFF_TERM = "TRUE";
+NET "AD15B_P" IOSTANDARD = LVDS;
+NET "AD15B_P" LOC = W11;
+NET "AD25B_N" DIFF_TERM = "TRUE";
+NET "AD25B_N" IOSTANDARD = LVDS_25;
+NET "AD25B_N" LOC = W20;
+NET "AD25B_P" DIFF_TERM = "TRUE";
+NET "AD25B_P" IOSTANDARD = LVDS_25;
+NET "AD25B_P" LOC = V20;
+NET "AD35B_N" DIFF_TERM = "TRUE";
+NET "AD35B_N" IOSTANDARD = LVDS_25;
+NET "AD35B_N" LOC = M18;
+NET "AD35B_P" DIFF_TERM = "TRUE";
+NET "AD35B_P" IOSTANDARD = LVDS_25;
+NET "AD35B_P" LOC = M17;
+NET "AD45B_N" DIFF_TERM = "TRUE";
+NET "AD45B_N" IOSTANDARD = LVDS_25;
+NET "AD45B_N" LOC = C15;
+NET "AD45B_P" DIFF_TERM = "TRUE";
+NET "AD45B_P" IOSTANDARD = LVDS_25;
+NET "AD45B_P" LOC = C14;
+NET "AD16A_N" DIFF_TERM = "TRUE";
+NET "AD16A_N" IOSTANDARD = LVDS;
+NET "AD16A_N" LOC = AB11;
+NET "AD16A_P" DIFF_TERM = "TRUE";
+NET "AD16A_P" IOSTANDARD = LVDS;
+NET "AD16A_P" LOC = AA11;
+NET "AD26A_N" DIFF_TERM = "TRUE";
+NET "AD26A_N" IOSTANDARD = LVDS_25;
+NET "AD26A_N" LOC = Y22;
+NET "AD26A_P" DIFF_TERM = "TRUE";
+NET "AD26A_P" IOSTANDARD = LVDS_25;
+NET "AD26A_P" LOC = Y21;
+NET "AD36A_N" DIFF_TERM = "TRUE";
+NET "AD36A_N" IOSTANDARD = LVDS_25;
+NET "AD36A_N" LOC = G22;
+NET "AD36A_P" DIFF_TERM = "TRUE";
+NET "AD36A_P" IOSTANDARD = LVDS_25;
+NET "AD36A_P" LOC = H22;
+NET "AD46A_N" DIFF_TERM = "TRUE";
+NET "AD46A_N" IOSTANDARD = LVDS_25;
+NET "AD46A_N" LOC = D16;
+NET "AD46A_P" DIFF_TERM = "TRUE";
+NET "AD46A_P" IOSTANDARD = LVDS_25;
+NET "AD46A_P" LOC = D15;
+NET "AD16B_N" DIFF_TERM = "TRUE";
+NET "AD16B_N" IOSTANDARD = LVDS;
+NET "AD16B_N" LOC = AB12;
+NET "AD16B_P" DIFF_TERM = "TRUE";
+NET "AD16B_P" IOSTANDARD = LVDS;
+NET "AD16B_P" LOC = AB13;
+NET "AD26B_N" DIFF_TERM = "TRUE";
+NET "AD26B_N" IOSTANDARD = LVDS_25;
+NET "AD26B_N" LOC = V17;
+NET "AD26B_P" DIFF_TERM = "TRUE";
+NET "AD26B_P" IOSTANDARD = LVDS_25;
+NET "AD26B_P" LOC = U16;
+NET "AD36B_N" DIFF_TERM = "TRUE";
+NET "AD36B_N" IOSTANDARD = LVDS_25;
+NET "AD36B_N" LOC = H20;
+NET "AD36B_P" DIFF_TERM = "TRUE";
+NET "AD36B_P" IOSTANDARD = LVDS_25;
+NET "AD36B_P" LOC = J20;
+NET "AD46B_N" DIFF_TERM = "TRUE";
+NET "AD46B_N" IOSTANDARD = LVDS_25;
+NET "AD46B_N" LOC = F16;
+NET "AD46B_P" DIFF_TERM = "TRUE";
+NET "AD46B_P" IOSTANDARD = LVDS_25;
+NET "AD46B_P" LOC = F15;
+NET "AD17A_N" DIFF_TERM = "TRUE";
+NET "AD17A_N" IOSTANDARD = LVDS;
+NET "AD17A_N" LOC = V12;
+NET "AD17A_P" DIFF_TERM = "TRUE";
+NET "AD17A_P" IOSTANDARD = LVDS;
+NET "AD17A_P" LOC = V13;
+NET "AD27A_N" DIFF_TERM = "TRUE";
+NET "AD27A_N" IOSTANDARD = LVDS_25;
+NET "AD27A_N" LOC = U21;
+NET "AD27A_P" DIFF_TERM = "TRUE";
+NET "AD27A_P" IOSTANDARD = LVDS_25;
+NET "AD27A_P" LOC = T21;
+NET "AD37A_N" DIFF_TERM = "TRUE";
+NET "AD37A_N" IOSTANDARD = LVDS_25;
+NET "AD37A_N" LOC = F20;
+NET "AD37A_P" DIFF_TERM = "TRUE";
+NET "AD37A_P" IOSTANDARD = LVDS_25;
+NET "AD37A_P" LOC = G20;
+NET "AD47A_N" DIFF_TERM = "TRUE";
+NET "AD47A_N" IOSTANDARD = LVDS_25;
+NET "AD47A_N" LOC = B13;
+NET "AD47A_P" DIFF_TERM = "TRUE";
+NET "AD47A_P" IOSTANDARD = LVDS_25;
+NET "AD47A_P" LOC = C13;
+NET "AD17B_N" DIFF_TERM = "TRUE";
+NET "AD17B_N" IOSTANDARD = LVDS;
+NET "AD17B_N" LOC = U13;
+NET "AD17B_P" DIFF_TERM = "TRUE";
+NET "AD17B_P" IOSTANDARD = LVDS;
+NET "AD17B_P" LOC = T13;
+NET "AD27B_N" DIFF_TERM = "TRUE";
+NET "AD27B_N" IOSTANDARD = LVDS_25;
+NET "AD27B_N" LOC = U18;
+NET "AD27B_P" DIFF_TERM = "TRUE";
+NET "AD27B_P" IOSTANDARD = LVDS_25;
+NET "AD27B_P" LOC = T18;
+NET "AD37B_N" DIFF_TERM = "TRUE";
+NET "AD37B_N" IOSTANDARD = LVDS_25;
+NET "AD37B_N" LOC = F21;
+NET "AD37B_P" DIFF_TERM = "TRUE";
+NET "AD37B_P" IOSTANDARD = LVDS_25;
+NET "AD37B_P" LOC = G21;
+NET "AD47B_N" DIFF_TERM = "TRUE";
+NET "AD47B_N" IOSTANDARD = LVDS_25;
+NET "AD47B_N" LOC = B12;
+NET "AD47B_P" DIFF_TERM = "TRUE";
+NET "AD47B_P" IOSTANDARD = LVDS_25;
+NET "AD47B_P" LOC = C12;
+NET "AD18A_N" DIFF_TERM = "TRUE";
+NET "AD18A_N" IOSTANDARD = LVDS;
+NET "AD18A_N" LOC = Y12;
+NET "AD18A_P" DIFF_TERM = "TRUE";
+NET "AD18A_P" IOSTANDARD = LVDS;
+NET "AD18A_P" LOC = W12;
+NET "AD28A_N" DIFF_TERM = "TRUE";
+NET "AD28A_N" IOSTANDARD = LVDS_25;
+NET "AD28A_N" LOC = V22;
+NET "AD28A_P" DIFF_TERM = "TRUE";
+NET "AD28A_P" IOSTANDARD = LVDS_25;
+NET "AD28A_P" LOC = U22;
+NET "AD38A_N" DIFF_TERM = "TRUE";
+NET "AD38A_N" IOSTANDARD = LVDS_25;
+NET "AD38A_N" LOC = K19;
+NET "AD38A_P" DIFF_TERM = "TRUE";
+NET "AD38A_P" IOSTANDARD = LVDS_25;
+NET "AD38A_P" LOC = L18;
+NET "AD48A_N" DIFF_TERM = "TRUE";
+NET "AD48A_N" IOSTANDARD = LVDS_25;
+NET "AD48A_N" LOC = A14;
+NET "AD48A_P" DIFF_TERM = "TRUE";
+NET "AD48A_P" IOSTANDARD = LVDS_25;
+NET "AD48A_P" LOC = A13;
+NET "AD18B_N" DIFF_TERM = "TRUE";
+NET "AD18B_N" IOSTANDARD = LVDS;
+NET "AD18B_N" LOC = AA13;
+NET "AD18B_P" DIFF_TERM = "TRUE";
+NET "AD18B_P" IOSTANDARD = LVDS;
+NET "AD18B_P" LOC = Y13;
+NET "AD28B_N" DIFF_TERM = "TRUE";
+NET "AD28B_N" IOSTANDARD = LVDS_25;
+NET "AD28B_N" LOC = U20;
+NET "AD28B_P" DIFF_TERM = "TRUE";
+NET "AD28B_P" IOSTANDARD = LVDS_25;
+NET "AD28B_P" LOC = T20;
+NET "AD38B_N" DIFF_TERM = "TRUE";
+NET "AD38B_N" IOSTANDARD = LVDS_25;
+NET "AD38B_N" LOC = E22;
+NET "AD38B_P" DIFF_TERM = "TRUE";
+NET "AD38B_P" IOSTANDARD = LVDS_25;
+NET "AD38B_P" LOC = E21;
+NET "AD48B_N" DIFF_TERM = "TRUE";
+NET "AD48B_N" IOSTANDARD = LVDS_25;
+NET "AD48B_N" LOC = D14;
+NET "AD48B_P" DIFF_TERM = "TRUE";
+NET "AD48B_P" IOSTANDARD = LVDS_25;
+NET "AD48B_P" LOC = E14;
+NET "DCOA1_N" DIFF_TERM = "TRUE";
+NET "DCOA1_N" IOSTANDARD = LVDS;
+NET "DCOA1_N" LOC = Y9;
+NET "DCOA1_P" DIFF_TERM = "TRUE";
+NET "DCOA1_P" IOSTANDARD = LVDS;
+NET "DCOA1_P" LOC = W9;
+NET "DCOB1_N" DIFF_TERM = "TRUE";
+NET "DCOB1_N" IOSTANDARD = LVDS;
+NET "DCOB1_N" LOC = Y7;
+NET "DCOB1_P" DIFF_TERM = "TRUE";
+NET "DCOB1_P" IOSTANDARD = LVDS;
+NET "DCOB1_P" LOC = Y8;
+NET "FRA1_N" DIFF_TERM = "TRUE";
+NET "FRA1_N" IOSTANDARD = LVDS;
+NET "FRA1_N" LOC = V9;
+NET "FRA1_P" DIFF_TERM = "TRUE";
+NET "FRA1_P" IOSTANDARD = LVDS;
+NET "FRA1_P" LOC = U10;
+NET "FRB1_N" DIFF_TERM = "TRUE";
+NET "FRB1_N" IOSTANDARD = LVDS;
+NET "FRB1_N" LOC = AB10;
+NET "FRB1_P" DIFF_TERM = "TRUE";
+NET "FRB1_P" IOSTANDARD = LVDS;
+NET "FRB1_P" LOC = AA10;
+NET "DCOA2_N" DIFF_TERM = "TRUE";
+NET "DCOA2_N" IOSTANDARD = LVDS_25;
+NET "DCOA2_N" LOC = W19;
+NET "DCOA2_P" DIFF_TERM = "TRUE";
+NET "DCOA2_P" IOSTANDARD = LVDS_25;
+NET "DCOA2_P" LOC = V19;
+NET "DCOB2_N" DIFF_TERM = "TRUE";
+NET "DCOB2_N" IOSTANDARD = LVDS_25;
+NET "DCOB2_N" LOC = Y19;
+NET "DCOB2_P" DIFF_TERM = "TRUE";
+NET "DCOB2_P" IOSTANDARD = LVDS_25;
+NET "DCOB2_P" LOC = Y18;
+NET "FRA2_N" DIFF_TERM = "TRUE";
+NET "FRA2_N" IOSTANDARD = LVDS_25;
+NET "FRA2_N" LOC = AB18;
+NET "FRA2_P" DIFF_TERM = "TRUE";
+NET "FRA2_P" IOSTANDARD = LVDS_25;
+NET "FRA2_P" LOC = AA18;
+NET "FRB2_N" DIFF_TERM = "TRUE";
+NET "FRB2_N" IOSTANDARD = LVDS_25;
+NET "FRB2_N" LOC = AB20;
+NET "FRB2_P" DIFF_TERM = "TRUE";
+NET "FRB2_P" IOSTANDARD = LVDS_25;
+NET "FRB2_P" LOC = AA19;
+NET "DCOA3_N" DIFF_TERM = "TRUE";
+NET "DCOA3_N" IOSTANDARD = LVDS_25;
+NET "DCOA3_N" LOC = L20;
+NET "DCOA3_P" DIFF_TERM = "TRUE";
+NET "DCOA3_P" IOSTANDARD = LVDS_25;
+NET "DCOA3_P" LOC = L19;
+NET "DCOB3_N" DIFF_TERM = "TRUE";
+NET "DCOB3_N" IOSTANDARD = LVDS_25;
+NET "DCOB3_N" LOC = N19;
+NET "DCOB3_P" DIFF_TERM = "TRUE";
+NET "DCOB3_P" IOSTANDARD = LVDS_25;
+NET "DCOB3_P" LOC = N18;
+NET "FRA3_N" DIFF_TERM = "TRUE";
+NET "FRA3_N" IOSTANDARD = LVDS_25;
+NET "FRA3_N" LOC = M21;
+NET "FRA3_P" DIFF_TERM = "TRUE";
+NET "FRA3_P" IOSTANDARD = LVDS_25;
+NET "FRA3_P" LOC = N20;
+NET "FRB3_N" DIFF_TERM = "TRUE";
+NET "FRB3_N" IOSTANDARD = LVDS_25;
+NET "FRB3_N" LOC = J22;
+NET "FRB3_P" DIFF_TERM = "TRUE";
+NET "FRB3_P" IOSTANDARD = LVDS_25;
+NET "FRB3_P" LOC = J21;
+NET "DCOA4_N" DIFF_TERM = "TRUE";
+NET "DCOA4_N" IOSTANDARD = LVDS_25;
+NET "DCOA4_N" LOC = C18;
+NET "DCOA4_P" DIFF_TERM = "TRUE";
+NET "DCOA4_P" IOSTANDARD = LVDS_25;
+NET "DCOA4_P" LOC = C17;
+NET "DCOB4_N" DIFF_TERM = "TRUE";
+NET "DCOB4_N" IOSTANDARD = LVDS_25;
+NET "DCOB4_N" LOC = E18;
+NET "DCOB4_P" DIFF_TERM = "TRUE";
+NET "DCOB4_P" IOSTANDARD = LVDS_25;
+NET "DCOB4_P" LOC = E17;
+NET "FRA4_N" DIFF_TERM = "TRUE";
+NET "FRA4_N" IOSTANDARD = LVDS_25;
+NET "FRA4_N" LOC = A16;
+NET "FRA4_P" DIFF_TERM = "TRUE";
+NET "FRA4_P" IOSTANDARD = LVDS_25;
+NET "FRA4_P" LOC = B16;
+NET "FRB4_N" DIFF_TERM = "TRUE";
+NET "FRB4_N" IOSTANDARD = LVDS_25;
+NET "FRB4_N" LOC = D17;
+NET "FRB4_P" DIFF_TERM = "TRUE";
+NET "FRB4_P" IOSTANDARD = LVDS_25;
+NET "FRB4_P" LOC = E16;
+
+NET "CSA[1]" LOC = W15;
+NET "CSA[1]" IOSTANDARD = LVCMOS25;
+NET "CSB[1]" LOC = V15;
+NET "CSB[1]" IOSTANDARD = LVCMOS25;
+NET "SCK" LOC = U12;
+NET "SCK" IOSTANDARD = LVCMOS18;
+NET "SDI" LOC = U11;
+NET "SDI" IOSTANDARD = LVCMOS18;
+NET "SDOA[1]" LOC = W14;
+NET "SDOA[1]" IOSTANDARD = LVCMOS25;
+NET "SDOB[1]" LOC = Y14;
+NET "SDOB[1]" IOSTANDARD = LVCMOS25;
+NET "CSA[2]" LOC = T16;
+NET "CSA[2]" IOSTANDARD = LVCMOS25;
+NET "CSB[2]" LOC = R16;
+NET "CSB[2]" IOSTANDARD = LVCMOS25;
+NET "SDOA[2]" LOC = T15;
+NET "SDOA[2]" IOSTANDARD = LVCMOS25;
+NET "SDOB[2]" LOC = U15;
+NET "SDOB[2]" IOSTANDARD = LVCMOS25;
+NET "CSA[3]" LOC = H17;
+NET "CSA[3]" IOSTANDARD = LVCMOS25;
+NET "CSB[3]" LOC = G17;
+NET "CSB[3]" IOSTANDARD = LVCMOS25;
+NET "SDOA[3]" LOC = J16;
+NET "SDOA[3]" IOSTANDARD = LVCMOS25;
+NET "SDOB[3]" LOC = J17;
+NET "SDOB[3]" IOSTANDARD = LVCMOS25;
+NET "CSA[4]" LOC = F18;
+NET "CSA[4]" IOSTANDARD = LVCMOS25;
+NET "CSB[4]" LOC = E19;
+NET "CSB[4]" IOSTANDARD = LVCMOS25;
+NET "SDOA[4]" LOC = G15;
+NET "SDOA[4]" IOSTANDARD = LVCMOS25;
+NET "SDOB[4]" LOC = G16;
+NET "SDOB[4]" IOSTANDARD = LVCMOS25;
+
+NET "GCLK_N" DIFF_TERM = "TRUE";
+NET "GCLK_N" IOSTANDARD = LVDS;
+NET "GCLK_N" LOC = T3;
+NET "GCLK_P" DIFF_TERM = "TRUE";
+NET "GCLK_P" IOSTANDARD = LVDS;
+NET "GCLK_P" LOC = R3;
+#NET "GCLK_P" IOSTANDARD = LVCMOS18;
+#NET "GCLK_N" IOSTANDARD = LVCMOS18;
+#NET "GCLK_N" CLOCK_DEDICATED_ROUTE = FALSE;
+
+
+NET "GEO" LOC = K17;
+NET "GEO" IOSTANDARD = LVCMOS25;
+NET "GEO" SLEW = SLOW;
+NET "GEO" PULLUP;
+NET "GEO" TIG;
+
+#Bank 16 = 2.5V
+NET "SYS_CLK" LOC = H12;
+NET "SYS_CLK" IOSTANDARD = LVCMOS25;
+
+NET "INTCOMC1_N" LOC = D11;
+NET "INTCOMC1_P" LOC = E11;
+NET "INTCOMC2_N" LOC = G10;
+NET "INTCOMC2_P" LOC = G11;
+NET "INTCOM0_N" LOC = E9;
+NET "INTCOM0_P" LOC = F9;
+NET "INTCOM1_N" LOC = H8;
+NET "INTCOM1_P" LOC = H9;
+NET "INTCOM2_N" LOC = F8;
+NET "INTCOM2_P" LOC = G8;
+NET "INTCOM3_N" LOC = C9;
+NET "INTCOM3_P" LOC = D9;
+NET "INTCOM4_N" LOC = B10;
+NET "INTCOM4_P" LOC = B11;
+NET "INTCOM5_N" LOC = A8;
+NET "INTCOM5_P" LOC = A9;
+NET "INTCOM6_N" LOC = B8;
+NET "INTCOM6_P" LOC = C8;
+NET "INTCOM7_N" LOC = A10;
+NET "INTCOM7_P" LOC = A11;
+
+NET "INTCOMC1_N" IOSTANDARD = LVCMOS25;
+NET "INTCOMC1_P" IOSTANDARD = LVCMOS25;
+NET "INTCOMC2_N" IOSTANDARD = LVCMOS25;
+NET "INTCOMC2_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM0_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM0_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM1_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM1_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM2_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM2_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM3_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM3_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM4_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM4_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM5_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM5_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM6_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM6_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM7_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM7_P" IOSTANDARD = LVCMOS25;
+
+
+NET "INTCOMC1_P" SLEW = FAST;
+NET "INTCOMC1_N" SLEW = FAST;
+NET "INTCOMC2_P" SLEW = FAST;
+NET "INTCOMC2_N" SLEW = FAST;
+NET "INTCOM0_P" SLEW = FAST;
+NET "INTCOM0_N" SLEW = FAST;
+NET "INTCOM1_P" SLEW = FAST;
+NET "INTCOM1_N" SLEW = FAST;
+NET "INTCOM2_P" SLEW = FAST;
+NET "INTCOM2_N" SLEW = FAST;
+NET "INTCOM3_P" SLEW = FAST;
+NET "INTCOM3_N" SLEW = FAST;
+NET "INTCOM4_P" SLEW = FAST;
+NET "INTCOM4_N" SLEW = FAST;
+NET "INTCOM5_P" SLEW = FAST;
+NET "INTCOM5_N" SLEW = FAST;
+NET "INTCOM6_P" SLEW = FAST;
+NET "INTCOM6_N" SLEW = FAST;
+NET "INTCOM7_P" SLEW = FAST;
+NET "INTCOM7_N" SLEW = FAST;
+
+
+NET "INTCOMC1_P" DRIVE = 4;
+NET "INTCOMC1_N" DRIVE = 4;
+NET "INTCOMC2_P" DRIVE = 4;
+NET "INTCOMC2_N" DRIVE = 4;
+NET "INTCOM0_P" DRIVE = 4;
+NET "INTCOM0_N" DRIVE = 4;
+NET "INTCOM1_P" DRIVE = 4;
+NET "INTCOM1_N" DRIVE = 4;
+NET "INTCOM2_P" DRIVE = 4;
+NET "INTCOM2_N" DRIVE = 4;
+NET "INTCOM3_P" DRIVE = 4;
+NET "INTCOM3_N" DRIVE = 4;
+NET "INTCOM4_P" DRIVE = 4;
+NET "INTCOM4_N" DRIVE = 4;
+NET "INTCOM5_P" DRIVE = 4;
+NET "INTCOM5_N" DRIVE = 4;
+NET "INTCOM6_P" DRIVE = 4;
+NET "INTCOM6_N" DRIVE = 4;
+NET "INTCOM7_P" DRIVE = 4;
+NET "INTCOM7_N" DRIVE = 4;
+
+
+
+NET "RCV_CLK_N" LOC = F10;
+NET "RCV_CLK_N" DIFF_TERM = "TRUE";
+NET "RCV_CLK_N" IOSTANDARD = LVDS_25;
+NET "RCV_CLK_P" LOC = F11;
+NET "RCV_CLK_P" DIFF_TERM = "TRUE";
+NET "RCV_CLK_P" IOSTANDARD = LVDS_25;
+
+NET "S_CTRL" LOC = E12;
+NET "S_CTRL" IOSTANDARD = LVCMOS25;
+NET "T_CTRL" LOC = E13;
+NET "T_CTRL" IOSTANDARD = LVCMOS25;
+
+#bank 34: 3.3V
+NET "SYNC" LOC = W5;
+NET "SYNC" IOSTANDARD = LVCMOS18;
+NET "CLKu" LOC = AA4;
+NET "CLKu" IOSTANDARD = LVCMOS18;
+NET "DATAu" LOC = AA3;
+NET "DATAu" IOSTANDARD = LVCMOS18;
+NET "LEu" LOC = Y4;
+NET "LEu" IOSTANDARD = LVCMOS18;
+NET "RDu" LOC = AB3;
+NET "RDu" IOSTANDARD = LVCMOS18;
+NET "RDu" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "ST_CLK_N" LOC = U3;
+#NET "ST_CLK_N" DIFF_TERM = "TRUE";
+#NET "ST_CLK_N" IOSTANDARD = LVDS;
+NET "ST_CLK_N" IOSTANDARD = LVCMOS18;
+
+NET "ST_CLK_P" LOC = T4;
+#NET "ST_CLK_P" DIFF_TERM = "TRUE";
+#NET "ST_CLK_P" IOSTANDARD = LVDS;
+NET "ST_CLK_P" IOSTANDARD = LVCMOS18;
+#NET "ST_CLK_N" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "MGTREFCLK_N" LOC = D5;
+NET "MGTREFCLK_N" DIFF_TERM = "TRUE";
+NET "MGTREFCLK_N" IOSTANDARD = LVDS;
+NET "MGTREFCLK_P" LOC = D6;
+NET "MGTREFCLK_P" DIFF_TERM = "TRUE";
+NET "MGTREFCLK_P" IOSTANDARD = LVDS;
+NET "RX_N" LOC = G3;
+NET "RX_N" DIFF_TERM = "TRUE";
+NET "RX_N" IOSTANDARD = LVDS;
+NET "RX_P" LOC = G4;
+NET "RX_P" DIFF_TERM = "TRUE";
+NET "RX_P" IOSTANDARD = LVDS;
+NET "TX_N" LOC = F1;
+NET "TX_N" DIFF_TERM = "TRUE";
+NET "TX_N" IOSTANDARD = LVDS;
+NET "TX_P" LOC = F2;
+NET "TX_P" DIFF_TERM = "TRUE";
+NET "TX_P" IOSTANDARD = LVDS;
+NET "LOS" LOC = K1;
+NET "LOS" IOSTANDARD = LVCMOS18;
+NET "TX_DIS" LOC = L1;
+NET "TX_DIS" IOSTANDARD = LVCMOS18;
+NET "MOD_DEF[0]" LOC = M2;
+NET "MOD_DEF[0]" IOSTANDARD = LVCMOS18;
+NET "MOD_DEF[1]" LOC = M1;
+NET "MOD_DEF[1]" IOSTANDARD = LVCMOS18;
+NET "MOD_DEF[2]" LOC = K3;
+NET "MOD_DEF[2]" IOSTANDARD = LVCMOS18;
+
+NET "MON1_N" LOC = Y1;
+NET "MON1_N" IOSTANDARD = LVCMOS18;
+NET "MON1_P" LOC = W1;
+NET "MON1_P" IOSTANDARD = LVCMOS18;
+NET "MON2_N" LOC = Y2;
+NET "MON2_N" IOSTANDARD = LVCMOS18;
+NET "MON2_P" LOC = Y3;
+NET "MON2_P" IOSTANDARD = LVCMOS18;
+
+NET "TEMP_OUT" LOC = T10;
+NET "TEMP_OUT" IOSTANDARD = LVCMOS18;
+NET "TEMP_IN" LOC = T11;
+NET "TEMP_IN" IOSTANDARD = LVCMOS18;
+
+#NET "GT_A2B_0_N" LOC = D1;
+#NET "GT_A2B_0_P" LOC = D2;
+#NET "GT_A2B_1_N" LOC = B1;
+#NET "GT_A2B_1_P" LOC = B2;
+#NET "GT_B2A_0_N" LOC = E3;
+#NET "GT_B2A_0_P" LOC = E4;
+#NET "GT_B2A_1_N" LOC = C3;
+#NET "GT_B2A_1_P" LOC = C4;
+#NET "DONE_P1" LOC = P6;
+#NET "CF_D0_I1" LOC = H18;
+#NET "CF_D1_I1" LOC = H19;
+#NET "CF_D2_I1" LOC = G18;
+#NET "CF_D3_I1" LOC = F19;
+#NET "CF_EMCL_I1" LOC = H12;
+#NET "CF_EMCL_I1" LOC = J19;
+#NET "CF_FCS_I1" LOC = L16;
+#NET "CF_PUDC_I1" LOC = K18;
+#NET "CCLK1_P1" LOC = G7;
+#NET "JTAG_IN1_TCK" LOC = K7;
+#NET "JTAG_IN1_TDI" LOC = K6;
+#NET "JTAG_IN1_TDO" LOC = J6;
+#NET "JTAG_IN1_TMS" LOC = L6;
+NET "JTAG_OUT1_TCK_F" LOC = G13;
+NET "JTAG_OUT1_TCK_F" IOSTANDARD = LVCMOS25;
+NET "JTAG_OUT1_TDI_F" LOC = H14;
+NET "JTAG_OUT1_TDI_F" IOSTANDARD = LVCMOS25;
+NET "JTAG_OUT1_TDO_F" LOC = H13;
+NET "JTAG_OUT1_TDO_F" IOSTANDARD = LVCMOS25;
+NET "JTAG_OUT1_TMS_F" LOC = F13;
+NET "JTAG_OUT1_TMS_F" IOSTANDARD = LVCMOS25;
+
+
+##########################################################################################
+# timing clock inputs:
+NET "SYS_CLK" TNM_NET = "SYS_CLK";
+TIMESPEC TS_SYS_CLK = PERIOD "SYS_CLK" 10 ns HIGH 50 %;
+
+NET "ST_CLK_P" TNM_NET = "ST_CLK_P";
+TIMESPEC TS_ST_CLK_P = PERIOD "ST_CLK_P" 6.43 ns HIGH 50 %;
+NET "ST_CLK_N" TNM_NET = "ST_CLK_N";
+TIMESPEC TS_ST_CLK_N = PERIOD "ST_CLK_N" 6.43 ns HIGH 50 %;
+
+NET "GCLK_P" TNM_NET = "GCLK_P";
+TIMESPEC TS_GCLK_P = PERIOD "GCLK_P" 12.5 ns HIGH 50 %;
+NET "GCLK_N" TNM_NET = "GCLK_N";
+TIMESPEC TS_GCLK_N = PERIOD "GCLK_N" 12.5 ns HIGH 50 %;
+
+##########################################################################################
+# derived clocks
+NET "async_clock_S" TNM_NET = "async_clock_S";
+TIMESPEC TS_async_clock_S = PERIOD "async_clock_S" 15.8333 ns HIGH 50 %;
+
+NET "clock100MHz_S" TNM_NET = "clock100MHz_S";
+TIMESPEC TS_clock100MHz_S = PERIOD "clock100MHz_S" 10 ns HIGH 50 %;
+
+NET "clock_S" TNM_NET = "clock_S";
+TIMESPEC TS_clock_S = PERIOD "clock_S" 12.5 ns HIGH 50 %;
+
+#NET "ST_CLK_S" TNM_NET = "ST_CLK_S";
+#TIMESPEC TS_ST_CLK_S = PERIOD "ST_CLK_S" 6.43 ns HIGH 50 %;
+
+NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S";
+TIMESPEC TS_rxSodaClk_S = PERIOD "rxSodaClk_S" 5 ns HIGH 50 %;
+
+##########################################################################################
+# between clocks
+TIMESPEC TS_asyn_to_clock = FROM "async_clock_S" TO "clock_S" TIG ;
+TIMESPEC TS_clock_to_async = FROM "clock_S" TO "async_clock_S" TIG ;
+
+#TIMESPEC TS_G_to_ST = FROM "GCLK_P" TO "ST_CLK_S" TIG;
+#TIMESPEC TS_SODA_to_ST = FROM "rxSodaClk_S" TO "ST_CLK_S_net" TIG;
+TIMESPEC TS_SODA_to_G = FROM "rxSodaClk_S" TO "GCLK_P" TIG ;
+
+
+################################################################################################################################
+# GTX
+#NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P";
+#TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 12.5 ns HIGH 50 %;
+#NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N";
+#TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 12.5 ns HIGH 50 %;
+
+NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/rxRecClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/rxRecClk_S";
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_rxRecClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/rxRecClk_S" 10 ns HIGH 50 %;
+NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txOutClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txOutClk_S";
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_txOutClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txOutClk_S" 12.5 ns HIGH 50 %;
+
+
+### ???????????????? :
+NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S";
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_txUsrClk_buf_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" 10 ns HIGH 50 %;
+
+NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S";
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_txUsrClkx2_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" 5 ns HIGH 50 %;
+
+
+TIMESPEC TS_FEE_gtxModule1_tx = FROM "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" 2 ns;
+TIMESPEC TS_FEE_gtxModule1_tx = FROM "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" 2 ns;
+
+INST "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/gtx_i/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i" LOC = GTXE2_CHANNEL_X0Y0;
+
+################################################################################################################################
+# ADC
+NET "ADC_clk_S" TNM_NET = "ADC_clk_S";
+TIMESPEC TS_ADC_clk_S = PERIOD "ADC_clk_S" 12.5 ns HIGH 50 %;
+NET "ADC_clk_S" MAXDELAY = 3 ns;
+NET "ADC_clk_S" MAXSKEW = 1 ns;
+
+
+################################################################################################################################
+# ADC placement
+INST "FEE_ADCinput_module1/AdcToplevel1458_1" AREA_GROUP = "pblock_adc_1";
+INST "FEE_ADCinput_module1/AdcToplevel2356_1" AREA_GROUP = "pblock_adc_1";
+AREA_GROUP "pblock_adc_1" RANGE=SLICE_X106Y50:SLICE_X109Y99;
+#AREA_GROUP "pblock_adc_1" RANGE=SLICE_X104Y99:SLICE_X108Y50;
+INST "FEE_ADCinput_module1/AdcToplevel1458_2" AREA_GROUP = "pblock_adc_2";
+INST "FEE_ADCinput_module1/AdcToplevel2356_2" AREA_GROUP = "pblock_adc_2";
+AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y50:SLICE_X3Y99;
+#AREA_GROUP "pblock_adc_2" RANGE=SLICE_X1Y99:SLICE_X2Y50;
+#AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y99:SLICE_X2Y50;
+INST "FEE_ADCinput_module1/AdcToplevel1458_3" AREA_GROUP = "pblock_adc_3";
+INST "FEE_ADCinput_module1/AdcToplevel2356_3" AREA_GROUP = "pblock_adc_3";
+AREA_GROUP "pblock_adc_3" RANGE=SLICE_X0Y100:SLICE_X3Y149;
+#AREA_GROUP "pblock_adc_3" RANGE=SLICE_X1Y149:SLICE_X2Y100;
+INST "FEE_ADCinput_module1/AdcToplevel1458_4" AREA_GROUP = "pblock_adc_4";
+INST "FEE_ADCinput_module1/AdcToplevel2356_4" AREA_GROUP = "pblock_adc_4";
+AREA_GROUP "pblock_adc_4" RANGE=SLICE_X0Y151:SLICE_X3Y199;
+
+
+#############################################################################################
+# Timing constraints
+#############################################################################################
+# The DCLK input clock, bit clock from the ADC, doesn't need a timespec.
+# This clock passes from the IOB through the BUFIO and to the .CLK input of all used ISERDES.
+# This path is made from dedicated routing.
+# From the IOB to the BUFIO.I is a dedicated connection only availabel with Clock Capable_IO.
+# This connection takes for all IO-banks in a FPGA and from all FPGAs of the familly an
+# average value of 220 ps.
+# The connection from the BUFIO.O to all ISERDES.CLK is also a dedicated connection, it
+# takes on average 330 ps.
+# The BUFIO average delay is: 869 ps and an LVDS IOB is average: 1094 ps.
+# A MAXSKEW constraint is used to detect the skew on the CLK net.
+#-->NET "*AdcClock/BitClk_MonClkOut" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntClk" MAXSKEW = 100 ps;
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntClk" MAXDELAY = 400 ps;
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+
+#
+# The connection from the BUFR.O to the ISERDES.CLKDIV inputs runs over normal clock nets.
+# Oposite to the BUFIO.O - ISERDES.CLK routing, the BUFR.O net not only connects to the
+# ISERDES.CLKDIV pins of the I/O SERDES in the IO-bank the BUFR is located in but to all
+# clocked elements (FFs, BRAM, DSP, ..) in that clock area.
+# It also connects to the adjacent upper and lower clock areas.
+# Therefore it is necessary to put timing constraints on this clock.
+# A MAXSKEW constraint to keep the skew as low as possible. makes sure the ISERDES are clocked
+# at the same time so that early-late data cannot appear at the outputs of the ISERDES.
+#-->NET "*AdcClock/BitClk_RefClkOut" MAXSKEW = 300 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntClkDiv" MAXSKEW = 400 ps;
+
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntRst_S" MAXDELAY = 1.5 ns;
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntEna_S" MAXDELAY = 1.5 ns;
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+
+# A period constraint at the BUFR will make sure the correct timing is applied on clock net.
+#-->NET "*AdcClock/BitClk_RefClkOut" TNM_NET = "BitClkRefClk";
+#-->TIMESPEC TS_ClkDiv = PERIOD "BitClkRefClk" 3.4 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk";
+TIMESPEC TS_AdcToplevel1458_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk";
+TIMESPEC TS_AdcToplevel2356_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" 3 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk";
+TIMESPEC TS_AdcToplevel1458_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk";
+TIMESPEC TS_AdcToplevel2356_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" 3 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk";
+TIMESPEC TS_AdcToplevel1458_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk";
+TIMESPEC TS_AdcToplevel2356_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" 3 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk";
+TIMESPEC TS_AdcToplevel1458_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk";
+TIMESPEC TS_AdcToplevel2356_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" 3 ns HIGH 50 %;
+
+
+
+
+
+
+
+################################################################################
+# Grouping of components.
+################################################################################
+# The logic of the interface is timing constraint with FROM-TO constraints.
+# The logic is first grouped per functionality and the constraints are applied.
+#-->INST "*AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds4B";
+#-->INST "*AdcClock/*" TNM = FFS "AdcClk_Ffs";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs4B";
+
+#-->INST "*AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrm_Isrds";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds4B";
+#-->INST "*AdcFrame/*" TNM = FFS "AdcFrm_Ffs";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs4B";
+
+#-->INST "*AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4B";
+
+#-->INST "*AdcData/*" TNM = FFS "AdcData_Ffs";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4B";
+
+################################################################################
+# Timespec between groups
+################################################################################
+#-->TIMESPEC TS_ClkIsrds_ClkFfs = FROM "AdcClk_Isrds" TO "AdcClk_Ffs" 3 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs1A = FROM "AdcClk_Isrds1A" TO "AdcClk_Ffs1A" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs1B = FROM "AdcClk_Isrds1B" TO "AdcClk_Ffs1B" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs2A = FROM "AdcClk_Isrds2A" TO "AdcClk_Ffs2A" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs2B = FROM "AdcClk_Isrds2B" TO "AdcClk_Ffs2B" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs3A = FROM "AdcClk_Isrds3A" TO "AdcClk_Ffs3A" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs3B = FROM "AdcClk_Isrds3B" TO "AdcClk_Ffs3B" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs4A = FROM "AdcClk_Isrds4A" TO "AdcClk_Ffs4A" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs4B = FROM "AdcClk_Isrds4B" TO "AdcClk_Ffs4B" 2.2 ns;
+#-->TIMESPEC TS_FrmIsrds_FrmFfs = FROM "AdcFrm_Isrds" TO "AdcFrm_Ffs" 3 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs1A = FROM "AdcFrame_Isrds1A" TO "AdcFrame_Ffs1A" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs1B = FROM "AdcFrame_Isrds1B" TO "AdcFrame_Ffs1B" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs2A = FROM "AdcFrame_Isrds2A" TO "AdcFrame_Ffs2A" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs2B = FROM "AdcFrame_Isrds2B" TO "AdcFrame_Ffs2B" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs3A = FROM "AdcFrame_Isrds3A" TO "AdcFrame_Ffs3A" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs3B = FROM "AdcFrame_Isrds3B" TO "AdcFrame_Ffs3B" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs4A = FROM "AdcFrame_Isrds4A" TO "AdcFrame_Ffs4A" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs4B = FROM "AdcFrame_Isrds4B" TO "AdcFrame_Ffs4B" 2.2 ns;
+#-->TIMESPEC TS_DatIsrds_DatFfs = FROM "AdcDat_Isrds" TO "AdcDat_Ffs" 3 ns;
+TIMESPEC TS_DataIsrds_DataFfs1A = FROM "AdcData_Isrds1A" TO "AdcData_Ffs1A" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs1B = FROM "AdcData_Isrds1B" TO "AdcData_Ffs1B" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs2A = FROM "AdcData_Isrds2A" TO "AdcData_Ffs2A" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs2B = FROM "AdcData_Isrds2B" TO "AdcData_Ffs2B" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs3A = FROM "AdcData_Isrds3A" TO "AdcData_Ffs3A" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs3B = FROM "AdcData_Isrds3B" TO "AdcData_Ffs3B" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs4A = FROM "AdcData_Isrds4A" TO "AdcData_Ffs4A" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs4B = FROM "AdcData_Isrds4B" TO "AdcData_Ffs4B" 2.2 ns;
+
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv2";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv3";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv4";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv5";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv6";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv7";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv8";
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "IntClk1";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "IntClk2";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "IntClk3";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "IntClk4";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "IntClk5";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "IntClk6";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "IntClk7";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "IntClk8";
+
+
+TIMESPEC TS_IntClkDiv_IntClk1 = FROM "IntClkDiv1" TO "IntClk1" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk2 = FROM "IntClkDiv2" TO "IntClk2" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk3 = FROM "IntClkDiv3" TO "IntClk3" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk4 = FROM "IntClkDiv4" TO "IntClk4" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk5 = FROM "IntClkDiv5" TO "IntClk5" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk6 = FROM "IntClkDiv6" TO "IntClk6" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk7 = FROM "IntClkDiv7" TO "IntClk7" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk8 = FROM "IntClkDiv8" TO "IntClk8" 2 ns;
+
+#TIMESPEC TS_IntClk_IntClkDiv1 = FROM "IntClk1" TO "IntClkDiv1" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv2 = FROM "IntClk2" TO "IntClkDiv2" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv3 = FROM "IntClk3" TO "IntClkDiv3" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv4 = FROM "IntClk4" TO "IntClkDiv4" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv5 = FROM "IntClk5" TO "IntClkDiv5" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv6 = FROM "IntClk6" TO "IntClkDiv6" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv7 = FROM "IntClk7" TO "IntClkDiv7" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv8 = FROM "IntClk8" TO "IntClkDiv8" 2 ns;
+
+
+###############################################################################################
+
+#TIMESPEC TS_Data_ADCclk1A = FROM "AdcData_Ffs1A" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk2A = FROM "AdcData_Ffs2A" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk2B = FROM "AdcData_Ffs2B" TO "ADC_clk_S 1 ns;
+#TIMESPEC TS_Data_ADCclk3A = FROM "AdcData_Ffs3A" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk3B = FROM "AdcData_Ffs3B" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk4A = FROM "AdcData_Ffs4A" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk4B = FROM "AdcData_Ffs4B" TO "ADC_clk_S" 1 ns;
+
+
+# sys_clk not
+NET "SYS_CLK" CLOCK_DEDICATED_ROUTE = BACKBONE;
+PIN "clockmodule100Mto80Ma/mmcm_adv_inst.CLKIN1" CLOCK_DEDICATED_ROUTE = BACKBONE;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 18-11-2014
+-- Module Name: FEE_SODAfrequencydiv5
+-- Description: Converts 200MHz from GTX to 40 MHz SODA
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_SODAfrequencydiv5
+-- Measures the number of pulses in one second
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : recovered clock
+-- data : data from GTX
+-- kchar : k-character signal from GTX
+--
+-- Outputs:
+-- clockdiv5 : input clock divided by 5 and synchronous to SODA
+-- error : error in incoming data or phase
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_SODAfrequencydiv5 is
+ port (
+ clock : in std_logic;
+ data : in std_logic_vector(7 downto 0);
+ kchar : in std_logic;
+ clockdiv5 : out std_logic;
+ error : out std_logic
+ );
+end FEE_SODAfrequencydiv5;
+
+architecture Behavioral of FEE_SODAfrequencydiv5 is
+constant KCHARSODA : std_logic_vector(7 downto 0) := x"DC";
+
+signal clockdiv5_S : std_logic;
+signal div5count0_S : std_logic;
+signal clock5div2_S : std_logic := '0';
+signal prev_clock5div2_S : std_logic := '0';
+signal clockdiv5_reset_S : std_logic;
+signal SODA_kchar_S : std_logic;
+signal disable_SODAcheck_S : std_logic := '0';
+signal disable_clock5check_S : std_logic := '0';
+signal SODA40_signal_S : std_logic;
+signal div5count_S : std_logic_vector(2 downto 0) := (others => '0');
+signal SODA_count_S : std_logic_vector(3 downto 0) := (others => '0');
+signal SODAerror_S : std_logic;
+signal clockdiv5error_S : std_logic;
+signal clockbiterror_S : std_logic;
+
+begin
+
+error <= '1' when (SODAerror_S='1') or (clockdiv5error_S='1') or (clockbiterror_S='1') else '0';
+--clockdiv5 <= clockdiv5_S;
+clockdiv5buf : BUFG
+ port map (
+ I => clockdiv5_S,
+ O => clockdiv5);
+
+rxrecclk_bufrdiv5_i : BUFR
+ generic map ( BUFR_DIVIDE => "5" )
+ port map (
+ CE => '1',
+ CLR => clockdiv5_reset_S,
+ I => clock,
+ O => clockdiv5_S);
+
+process_checkSODA: process(clock)
+variable disable_count_V : std_logic_vector(1 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ div5count0_S <= '0';
+ clockbiterror_S <= '0';
+ if div5count_S/="100" then
+ if (disable_SODAcheck_S='0') and (SODA40_signal_S='1') then -- wrong phase
+ div5count_S <= "000";
+ disable_SODAcheck_S <= '1';
+ disable_count_V := (others => '0');
+ clockbiterror_S <= '1';
+ else
+ div5count_S <= div5count_S+1;
+ end if;
+ else
+ div5count_S <= "000";
+ div5count0_S <= '1';
+ if disable_count_V(disable_count_V'left)='0' then
+ disable_count_V := disable_count_V+1;
+ else
+ disable_SODAcheck_S <= '0';
+ end if;
+ end if;
+ prev_clock5div2_S <= clock5div2_S;
+ end if;
+end process;
+
+
+
+process_checkdiv5: process(clock)
+variable disable_count_V : std_logic_vector(3 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ clockdiv5_reset_S <= '0';
+ clockdiv5error_S <= '0';
+ if (disable_SODAcheck_S='0') and (disable_clock5check_S='0') then
+ if (clock5div2_S/=prev_clock5div2_S) and div5count0_S='0' then -- div5 clock wrong phase : reset
+ clockdiv5_reset_S <= '1';
+ disable_clock5check_S <= '1';
+ disable_count_V := (others => '0');
+ clockdiv5error_S <= '1';
+ end if;
+ else
+ if disable_count_V(disable_count_V'left)='0' then
+ disable_count_V := disable_count_V+1;
+ else
+ disable_clock5check_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+process_SODAchar: process(clock)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ if (kchar='1') and (data=KCHARSODA) then
+ SODA_kchar_S <= '1';
+ else
+ SODA_kchar_S <= '0';
+ end if;
+ end if;
+end process;
+
+process_SODAstart: process(clock)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ SODA40_signal_S <= '0';
+ SODAerror_S <= '0';
+ if (SODA_count_S="0000") and (SODA_kchar_S='1') then
+ SODA40_signal_S <= '1';
+ SODA_count_S <= SODA_count_S+1;
+ elsif SODA_count_S(0)='1' then -- SODA data
+ if SODA_kchar_S='1' then -- error
+ SODA_count_S <= "0000";
+ SODAerror_S <= '1';
+ else
+ SODA_count_S <= SODA_count_S+1;
+ end if;
+ elsif (SODA_count_S(2 downto 1)/="00") then -- SODA k-char
+ if SODA_kchar_S='0' then -- error
+ SODA_count_S <= "0000";
+ SODAerror_S <= '1';
+ else
+ SODA_count_S <= SODA_count_S+1;
+ end if;
+ elsif (SODA_count_S(3)='1') then -- end SODA packet
+ SODA_count_S <= "0000";
+ if SODA_kchar_S='1' then -- error
+ SODAerror_S <= '1';
+ end if;
+ end if;
+ end if;
+end process;
+
+process_clock5div2: process(clockdiv5_S)
+begin
+ if (rising_edge(clockdiv5_S)) then
+ clock5div2_S <= not clock5div2_S;
+ end if;
+end process;
+
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 04-02-2015
+-- Module Name: FEE_data16to8
+-- Description: Converts 16 bits data at 100MHz to 8 bits data at 200MHz
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_data16to8
+-- Converts 16 bits data at 100MHz to 8 bits data at 200MHz
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock_in : input clock at single
+-- data_in : 16 bits input data
+-- kchar_in : corresponding k-character (one for each input byte)
+--
+-- Outputs:
+-- clock_out : output clock at double speed
+-- data_out : 8 bits output data at double speed
+-- kchar_out : corresponding k-character
+--
+-- Components:
+-- clock100to200 : clock doubler : 100MHz -> 200MHz
+--
+----------------------------------------------------------------------------------
+
+entity FEE_data16to8 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ kchar_in : in std_logic_vector(1 downto 0);
+ notintable_in : in std_logic_vector(1 downto 0);
+ clock_out : out std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ kchar_out : out std_logic;
+ notintable_out : out std_logic
+ );
+end FEE_data16to8;
+
+architecture Behavioral of FEE_data16to8 is
+
+component clock100to200 is
+ port
+ (
+ clk_in1 : in std_logic;
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic
+ );
+end component;
+
+signal clock_out_S : std_logic;
+signal phase_S : std_logic;
+signal kchar_in_S : std_logic_vector(1 downto 0);
+
+begin
+
+clock100to200_1: clock100to200 port map(
+ clk_in1 => clock_in,
+ clk_out1 => open,
+ clk_out2 => clock_out_S);
+clock_out <= clock_out_S;
+
+process(clock_out_S)
+begin
+ if (rising_edge(clock_out_S)) then
+ kchar_in_S <= kchar_in;
+ end if;
+end process;
+
+process(clock_out_S)
+begin
+ if (rising_edge(clock_out_S)) then
+ if kchar_in_S/=kchar_in then
+ phase_S <= '0';
+ else
+ phase_S <= not phase_S;
+ end if;
+ end if;
+end process;
+
+process(clock_out_S)
+begin
+ if (rising_edge(clock_out_S)) then
+ if phase_S='1' then
+ data_out <= data_in(7 downto 0);
+ kchar_out <= kchar_in(0);
+ notintable_out <= notintable_in(0);
+ else
+ data_out <= data_in(15 downto 8);
+ kchar_out <= kchar_in(1);
+ notintable_out <= notintable_in(1);
+ end if;
+ end if;
+end process;
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 06-02-2015
+-- Module Name: FEE_data8to16
+-- Description: Converts 8 bits data at 200MHz to 16 bits data at 100MHz
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_data8to16
+-- Converts 8 bits data at 200MHz to 16 bits data at 100MHz
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock_in : input clock
+-- data_in : 8 bits input data
+-- kchar_in : corresponding k-character
+--
+-- Outputs:
+-- clock_out : output clock at half speed
+-- data_out : 16 bits output data at half speed
+-- kchar_out : corresponding k-character (one for each byte)
+--
+-- Components:
+-- clock100to200 : clock doubler : 100MHz -> 200MHz
+--
+----------------------------------------------------------------------------------
+
+entity FEE_data8to16 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ kchar_in : in std_logic;
+ clock_out : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ kchar_out : out std_logic_vector(1 downto 0)
+ );
+end FEE_data8to16;
+
+architecture Behavioral of FEE_data8to16 is
+
+component clock100to200 is
+ port
+ (
+ clk_in1 : in std_logic;
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic
+ );
+end component;
+
+signal clock_in_S : std_logic;
+signal data_in0_S : std_logic_vector(7 downto 0);
+signal kchar_in0_S : std_logic;
+signal data_in1_S : std_logic_vector(7 downto 0);
+signal kchar_in1_S : std_logic;
+signal data_out_S : std_logic_vector(15 downto 0);
+signal kchar_out_S : std_logic_vector(1 downto 0);
+
+begin
+
+--clock100to200_1: clock100to200 port map(
+-- clk_in1 => clock_out,
+-- clk_out1 => open,
+-- clk_out2 => clock_in_S);
+--clock_in <= clock_in_S;
+clock_in_S <= clock_in;
+
+
+process(clock_in_S)
+begin
+ if (rising_edge(clock_in_S)) then
+ data_in0_S <= data_in;
+ kchar_in0_S <= kchar_in;
+ data_in1_S <= data_in0_S;
+ kchar_in1_S <= kchar_in0_S;
+ end if;
+end process;
+
+process(clock_out)
+begin
+ if (rising_edge(clock_out)) then
+ data_out_S <= data_in0_S & data_in1_S;
+ kchar_out_S <= kchar_in0_S & kchar_in1_S;
+ data_out <= data_out_S;
+ kchar_out <= kchar_out_S;
+ end if;
+end process;
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 26-08-2013
+-- Module Name: FEE_gtxModule
+-- Description: GTP/GTX/serdes tranceiver for PANDA Front End Electronics with clock synchronization
+-- Modifications:
+-- 19-11-2014 Name changed from gtpBufLayerFee to FEE_gtxModule
+-- 07-02-2015 Version for Kintex7
+-- 25-01-2017 First/last signals added
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+library work;
+use work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_gtxModule
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization:
+--
+-- Receiver generates synchronous clock on incomming serial data (SODA) and detects synchronous
+-- data packages (SODA-commands) with fixed delay.
+-- Receives also asynchronous data from fibre and outputs it as 32 bits.
+-- SODA packages use the DLM i/o. Data is send along with K27.7 character (0xFB)
+-- Idle's consists of K28.1 & K28.5 characters (0x3c,0xBC)
+-- All other valid (non K) characters is treated as data and combined to 32-bits
+--
+-- Transmitter sends data (asynchronous to SODA). The data is organised as 32-bits words.
+-- If no data is available then idle's are sent (0x3CBC)
+--
+-- Only one channel of the dual GTP or GTX is used.
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+--
+-- Inputs:
+-- gtpClk_P,gtpClk_N : Reference clock for GTP/GTX, frequency must match expected SODA frequency (finally probably 155.52 MHz)
+-- sysClk : stable clock (80MHz)
+-- asyncclk : stable clock at different clock speed (not used)
+-- reset : reset GTP/GTX
+-- disable_GTX_reset : disable reset of GTX (during clock switching)
+-- TX_DLM : transmit SODA character
+-- TX_DLM_WORD : SODA character to be transmitted
+-- rxAsyncClk : Clock for the asynchronous (32-bits) data (used for slow-control in FEE)
+-- txAsyncData : asynchronous 32-bits data to be transmitted
+-- txAsyncDataWrite : write signal for asynchronous 32-bits data to be transmitted
+-- txAsyncFirstData : First asynchronous 32-bits word of the data packet to be transmitted
+-- txAsyncLastData : Last asynchronous 32-bits word of the data packet to be transmitted, used for separating packets on the fiber
+-- txAsyncClk : clock for the asynchronous 32-bits data to be transmitted
+-- rxAsyncDataRead : read signal for the asynchronous data fifo
+-- gtpRxP0,gtpRxN0 : differential GTP/GTX inputs
+--
+-- Outputs:
+-- RX_DLM : SODA character received
+-- RX_DLM_WORD : SODA character
+-- txAsyncFifoFull : fifo for 32-bits transmit data is full
+-- txLocked : Transmitter PLL locked
+-- rxAsyncData : asynchronous 32 bits data from the receiver fifo
+-- rxError : invalid character or other receiver error
+-- rxAsyncDataOverflow : overflow bit of the receiver asynchronous data fifo
+-- rxAsyncDataPresent : Indicates if asynchronous data is available in the receiver fifo
+-- rxSodaClk : Reconstructed clock, synchronous with original SODA clock but different frequency (200MHz)
+-- rxSodaClk40 : Reconstructed SODA clock : 40MHz
+-- rxLocked : Receiver locked
+-- gtpTxP0,gtpTxN0 : differential transmit outputs of the GTP/GTX (not used at the moment)
+--
+-- Components:
+-- FEE_gtxWrapper_Kintex7 : module with the GTP/GTX interface
+-- FEE_SODAfrequencydiv5 : make divide by 5 clock from recovered clock
+-- FEE_fifo32to8_SODA : fifo for data to be transmitted, converts data from 32-bits to 16-bits
+-- FEE_fifo8to32_SODA : fifo for received asynchronous data, converts data from 16-bits to 32-bits
+-- sync_to_different_phase : synchronize to clock with same frequency but different phase
+--
+----------------------------------------------------------------------------------
+
+entity FEE_gtxModule is
+ Port (
+ gtpClk_P : in std_logic;
+ gtpClk_N : in std_logic;
+ refclk_out : out std_logic;
+ sysClk : in std_logic;
+ asyncclk : in std_logic;
+ reset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+
+ txAsyncClk : in std_logic;
+ txAsyncData : in std_logic_vector(31 downto 0);
+ txAsyncDataWrite : in std_logic;
+ txAsyncFirstData : in std_logic;
+ txAsyncLastData : in std_logic;
+ txAsyncFifoFull : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxAsyncClk : in std_logic;
+ rxAsyncData : out std_logic_vector(31 downto 0);
+ rxAsyncFirstData : out std_logic;
+ rxAsyncLastData : out std_logic;
+ rxAsyncDataRead : in std_logic;
+ rxError : out std_logic;
+ rxAsyncDataOverflow : out std_logic;
+ rxAsyncDataPresent : out std_logic;
+ rxUsrClkdiv2 : out std_logic;
+ rxSodaClk : out std_logic;
+ rxSodaClk40 : out std_logic;
+ rxLocked : out std_logic;
+
+ gtpTxP0 : out std_logic;
+ gtpTxN0 : out std_logic;
+ gtpRxP0 : in std_logic;
+ gtpRxN0 : in std_logic;
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+ );
+end FEE_gtxModule;
+
+
+architecture Behavioral of FEE_gtxModule is
+
+component FEE_gtxWrapper_Kintex7 is
+ port (
+ gtpClk_P : in std_logic;
+ gtpClk_N : in std_logic;
+ refclk_out : out std_logic;
+ sysClk : in std_logic;
+ gtpReset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ txData : in std_logic_vector (7 downto 0);
+ txCharIsK : in std_logic;
+ txP : out std_logic;
+ txN : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxData : out std_logic_vector (7 downto 0);
+ rxCharIsK : out std_logic;
+ rxNotInTable : out std_logic;
+ rxP : in std_logic;
+ rxN : in std_logic;
+ rxUsrClk : out std_logic;
+ rxUsrClkdiv2 : out std_logic;
+ rxLocked : out std_logic;
+
+ resetDone : out std_logic;
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+ );
+end component;
+
+component FEE_SODAfrequencydiv5 is
+ port (
+ clock : in std_logic;
+ data : in std_logic_vector(7 downto 0);
+ kchar : in std_logic;
+ clockdiv5 : out std_logic;
+ error : out std_logic
+ );
+end component;
+
+component FEE_fifo32to8_SODA is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 downto 0);
+ data_write : in std_logic;
+ full : out std_logic;
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ char_is_k : out std_logic
+ );
+end component;
+
+component FEE_fifo8to32_SODA is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ char_is_k : in std_logic;
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(31 downto 0);
+ data_read : in std_logic;
+ data_available : out std_logic;
+ overflow : out std_logic;
+ error : out std_logic
+ );
+end component;
+
+component sync_to_different_phase is
+ generic (
+ WIDTH : natural := 18
+ );
+ port (
+ clock1 : in std_logic;
+ clock2 : in std_logic;
+ data_in : in std_logic_vector(WIDTH-1 downto 0);
+ data_out : out std_logic_vector(WIDTH-1 downto 0)
+ );
+end component;
+
+component async_fifo_16x9
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(8 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(8 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+component asyncfifo is
+ generic (
+ DATA_WIDTH : natural := 9;
+ ADDR_WIDTH : natural := 2
+ );
+ port (
+ reset : in std_logic;
+ read_clock : in std_logic;
+ read_request : in std_logic;
+ data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+ write_clock : in std_logic;
+ write_request : in std_logic;
+ data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ valid : out std_logic
+ );
+end component;
+
+signal rxSodaClk40_S : std_logic := '0';
+signal rxNotInTable_S : std_logic := '0';
+signal rxLocked_S : std_logic := '0';
+signal txLocked_S : std_logic := '0';
+signal txreset_S : std_logic := '0';
+signal txCharIsK_S : std_logic := '0';
+signal txUsrClk_S : std_logic;
+signal txData_S : std_logic_vector(7 downto 0);
+signal rxCharIsK_S : std_logic;
+
+signal rxUsrClk_S : std_logic;
+signal rxData_S : std_logic_vector(7 downto 0);
+signal rxerror_s : std_logic;
+
+signal TX_DLM_S : std_logic;
+signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);
+signal RX_DLM_S : std_logic;
+signal RX_DLM_WORD_S : std_logic_vector(7 downto 0);
+
+signal fifo_dout_S : std_logic_vector(8 downto 0) := (others => '0');
+signal fifosync_write_S : std_logic;
+signal fifosync_read_S : std_logic;
+signal fifosync_empty_S : std_logic;
+signal fifosync_full_S : std_logic;
+signal fifosync_valid_S : std_logic;
+signal rxphase_S : std_logic;
+signal rxphaseError_S : std_logic;
+signal rxAsyncData_S : std_logic_vector(31 downto 0);
+signal rxAsyncDataRead_aftr1clk_S : std_logic;
+
+begin
+
+txUsrClk <= txUsrClk_S;
+rxSodaClk <= rxUsrClk_S;
+rxSodaClk40 <= rxSodaClk40_S;
+
+FEE_gtxWrapper_Kintex7_1 : FEE_gtxWrapper_Kintex7
+ port map (
+ gtpClk_P => gtpClk_P,
+ gtpClk_N => gtpClk_N,
+ refclk_out => refclk_out,
+ sysClk => sysClk,
+ gtpReset => reset,
+ disable_GTX_reset => disable_GTX_reset,
+ txData => txData_S,
+ txCharIsK => txCharIsK_S,
+ txP => gtpTxP0,
+ txN => gtpTxN0,
+ txUsrClk => txUsrClk_S,
+ txLocked => txLocked_S,
+ rxData => rxData_S,
+ rxCharIsK => rxCharIsK_S,
+ rxNotInTable => rxNotInTable_S,
+ rxP => gtpRxP0,
+ rxN => gtpRxN0,
+ rxUsrClk => rxUsrClk_S,
+ rxUsrClkdiv2 => rxUsrClkdiv2,
+ rxLocked => rxLocked_S,
+ resetDone => open,
+ GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
+ GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN
+ );
+
+FEE_SODAfrequencydiv51: FEE_SODAfrequencydiv5 port map(
+ clock => rxUsrClk_S,
+ data => rxData_S,
+ kchar => rxCharIsK_S,
+ clockdiv5 => rxSodaClk40_S,
+ error => open
+ );
+
+-- synchronise SODA signals to txUsrClk_S. same frequency, differe4nt phase -----------------
+txreset_S <= '1' when (txLocked_S='0') or (reset='1') or (rxLocked_S='0') else '0';
+fifosync: async_fifo_16x9 port map(
+ rst => txreset_S,
+ wr_clk => rxUsrClk_S,
+ rd_clk => txUsrClk_S,
+ din(7 downto 0) => TX_DLM_WORD,
+ din(8) => TX_DLM,
+ wr_en => fifosync_write_S,
+ rd_en => fifosync_read_S,
+ dout => fifo_dout_S,
+ full => fifosync_full_S,
+ empty => fifosync_empty_S);
+--fifosync: asyncfifo
+-- generic map(
+-- DATA_WIDTH => 9,
+-- ADDR_WIDTH => 2
+-- )
+-- port map(
+-- reset => txreset_S,
+-- read_clock => txUsrClk_S,
+-- read_request => fifosync_read_S,
+-- data_in(7 downto 0) => TX_DLM_WORD,
+-- data_in(8) => TX_DLM,
+-- write_clock => rxUsrClk_S,
+-- write_request => fifosync_write_S,
+-- data_out => fifo_dout_S,
+-- empty => fifosync_empty_S,
+-- full => fifosync_full_S,
+-- valid => fifosync_valid_S);
+fifosync_read_S <= '1'; -- when fifosync_empty_S='0' else '0';
+fifosync_write_S <= '1' when fifosync_full_S='0' else '0';
+
+TX_DLM_WORD_S <= fifo_dout_S(7 downto 0);
+TX_DLM_S <= fifo_dout_S(8); -- when fifosync_valid_S='1' else '0';
+
+FEE_fifo32to8_SODA1: FEE_fifo32to8_SODA port map(
+ write_clock => txAsyncClk,
+ read_clock => txUsrClk_S,
+ reset => '0', -- reset,
+ data_in => txAsyncData,
+ data_write => txAsyncDataWrite,
+ full => txAsyncFifoFull,
+ TX_DLM => TX_DLM_S,
+ TX_DLM_WORD => TX_DLM_WORD_S,
+ data_out => txData_S,
+ char_is_k => txCharIsK_S
+ );
+
+FEE_fifo8to32_SODA1: FEE_fifo8to32_SODA port map(
+ write_clock => rxUsrClk_S,
+ read_clock => rxAsyncClk,
+ reset => '0', -- reset,
+ data_in => rxData_S,
+ char_is_k => rxCharIsK_S,
+ RX_DLM => RX_DLM_S,
+ RX_DLM_WORD => RX_DLM_WORD_S,
+ data_out => rxAsyncData_S,
+ data_read => rxAsyncDataRead,
+ data_available => rxAsyncDataPresent,
+ overflow => rxAsyncDataOverflow,
+ error => rxerror_S);
+rxAsyncData <= rxAsyncData_S;
+rxAsyncFirstData <= '1' when (rxAsyncDataRead_aftr1clk_S='1') and (rxphase_S='0') else '0';
+rxAsyncLastData <= '1' when (rxAsyncDataRead_aftr1clk_S='1') and (rxphase_S='1') else '0';
+process(rxAsyncClk)
+begin
+ if (rising_edge(rxAsyncClk)) then
+ rxphaseError_S <= '0';
+ if (rxAsyncDataRead_aftr1clk_S='1') then
+ if rxphase_S='0' then
+ if rxAsyncData_S(31 downto 24)=x"5C" then
+ rxphase_S <= '1';
+ else
+ rxphaseError_S <= '1';
+ end if;
+ else
+ rxphase_S <= '0';
+ end if;
+ end if;
+ rxAsyncDataRead_aftr1clk_S <= rxAsyncDataRead;
+ end if;
+end process;
+
+RX_DLM <= RX_DLM_S;
+RX_DLM_WORD <= RX_DLM_WORD_S;
+
+txLocked <= txLocked_S; -- 1 => OK
+rxLocked <= rxLocked_S; -- 1 => OK
+rxError <= rxNotInTable_S or rxerror_S or rxphaseError_S; -- '1' => error
+
+
+end Behavioral;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 05-02-2015
+-- Module Name: FEE_gtxWrapper_Kintex7
+-- Description: GTP/GTX tranceiver for PANDA Front End Electronics on Kintex7 with clock synchronization
+-- Modifications:
+-- 05-02-2015 Originally FEE_gtxWrapper_Virtex6
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library work;
+use work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_gtxWrapper_Kintex7
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization on a Virtex5.
+--
+-- Receiver makes recovered synchronous clock on incomming serial data (SODA).
+-- Data is 16-bits, synchronous to recovered clock.
+-- Transmitter sends 16-bits data.
+--
+-- Only one channel of the dual GTP or GTX is used.
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+--
+-- Inputs:
+-- gtpClk_P,gtpClk_N : Reference clock for GTP/GTX, frequency must match expected SODA frequency
+-- sysClk : stable clock (80MHz)
+-- gtpReset : reset GTP/GTX
+-- disable_GTX_reset : disable ressetting temporarely
+-- txData : 16-bits input data to transmit
+-- txCharIsK : data to transmit are K-characters
+-- rxP,rxN : differential transmit inputs from the GTP/GTX
+--
+-- Outputs:
+-- txP,txN : differential transmit outputs of the GTP/GTX
+-- txUsrClk : clock for transmit data
+-- txLocked : transmitter locked
+-- rxData : 16-bits received data
+-- rxCharIsK : received 16-bits data (2 bytes) are K-characters
+-- rxNotInTable : receiver data not valid
+-- rxUsrClk : Recovered synchronous clock
+-- rxLocked : receiver locked to incomming data
+-- resetDone : resetting ready
+--
+-- Components:
+-- GTXVIRTEX5FEE : Xilinx module for GTP or GTX, generated with the IP core generator with a few adjustments
+-- FEE_rxBitLock : Module for checking and resetting the GTP/GTX to lock the receiver clock at the right phase
+-- Clock_62M5_doubler : Clock doubler with PLL
+--
+----------------------------------------------------------------------------------
+
+entity FEE_gtxWrapper_Kintex7 is
+ port (
+ gtpClk_P : in std_logic;
+ gtpClk_N : in std_logic;
+ refclk_out : out std_logic;
+ sysClk : in std_logic;
+ gtpReset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ txData : in std_logic_vector (7 downto 0);
+ txCharIsK : in std_logic;
+ txP : out std_logic;
+ txN : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxData : out std_logic_vector (7 downto 0);
+ rxCharIsK : out std_logic;
+ rxNotInTable : out std_logic;
+ rxP : in std_logic;
+ rxN : in std_logic;
+ rxUsrClk : out std_logic;
+ rxUsrClkdiv2 : out std_logic;
+ rxLocked : out std_logic;
+
+ resetDone : out std_logic;
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+ );
+end FEE_gtxWrapper_Kintex7;
+
+architecture Behavioral of FEE_gtxWrapper_Kintex7 is
+
+component gtxKintex7FEE80_support is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 12
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_OUT : out std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic;
+ sysclk_in : in std_logic;
+ refclk_out : out std_logic --// Modified
+
+);
+
+end component;
+
+component FEE_rxBitLock is
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ resetDone : in std_logic;
+ lossOfSync : in std_logic;
+ rxPllLocked : in std_logic;
+ rxReset : out std_logic;
+ fsmStatus : out std_logic_vector (1 downto 0)
+ );
+end component;
+
+component FEE_data8to16 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ kchar_in : in std_logic;
+ clock_out : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ kchar_out : out std_logic_vector(1 downto 0)
+ );
+end component;
+
+component FEE_data16to8 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ kchar_in : in std_logic_vector(1 downto 0);
+ notintable_in : in std_logic_vector(1 downto 0);
+ clock_out : out std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ kchar_out : out std_logic;
+ notintable_out : out std_logic
+ );
+end component;
+
+component posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+
+signal gtpReset_S : std_logic;
+signal txResetdone_S : std_logic;
+signal pllLkDet_S : std_logic :='0';
+signal rxResetDone_S : std_logic :='0';
+signal rxResetDone_sysclk_S: std_logic;
+signal ff_txfullclk : std_logic; -- tx clock at double tx speed
+signal ff_rxhalfclk : std_logic;
+signal ff_txhalfclk : std_logic;
+
+signal txData16_S : std_logic_vector(15 downto 0);
+signal txCharIsK16_S : std_logic_vector(1 downto 0);
+
+signal rxReset_S : std_logic :='0';
+signal rxData_S : std_logic_vector(7 downto 0);
+signal rxCharIsK_S : std_logic;
+signal rxNotInTable_S : std_logic;
+signal rxData16_S : std_logic_vector(15 downto 0);
+signal rxCharIsK16_S : std_logic_vector(1 downto 0);
+signal rxNotInTable16_S : std_logic_vector(1 downto 0);
+signal rxDispError16_S : std_logic_vector(1 downto 0);
+signal rxLocked0_S : std_logic;
+signal rxLocked1_S : std_logic;
+signal rxLocked2_S : std_logic;
+signal rxLossOfSync1_S : std_logic;
+signal rxResetBitLock_S : std_logic :='0';
+signal sync_rxResetBitLock_S : std_logic :='0';
+signal prev_rxResetBitLock_S : std_logic :='0';
+signal fsmStatus_S : std_logic_vector(1 downto 0);
+signal rxPLLwrapper_reset_S : std_logic :='0';
+signal rxResetBitLock_pulse_S : std_logic :='0';
+
+
+signal rxCDRlock_S : std_logic :='0';
+signal CDR_reset_S : std_logic :='0';
+
+signal drpaddr_in_S : std_logic_vector(8 downto 0);
+signal drpdi_in_S : std_logic_vector(15 downto 0);
+signal drpdo_out_S : std_logic_vector(15 downto 0);
+signal drpen_in_S : std_logic;
+signal drprdy_out_S : std_logic;
+signal drpwe_in_S : std_logic;
+
+signal comma_align_latency_S : std_logic_vector(6 downto 0);
+signal comma_align_latency_valid_S : std_logic;
+
+
+type drp_state_type is (initting, running, reading);
+signal drp_state_S : drp_state_type := initting;
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of rxData16_S : signal is "true";
+-- attribute mark_debug of rxCharIsK16_S : signal is "true";
+-- attribute mark_debug of rxNotInTable16_S : signal is "true";
+-- attribute mark_debug of rxDispError16_S : signal is "true";
+-- attribute mark_debug of txData : signal is "true";
+-- attribute mark_debug of txCharIsK : signal is "true";
+
+-- attribute mark_debug of gtpReset_S : signal is "true";
+-- attribute mark_debug of txResetdone_S : signal is "true";
+-- attribute mark_debug of rxResetDone_S : signal is "true";
+-- attribute mark_debug of pllLkDet_S : signal is "true";
+-- attribute mark_debug of rxReset_S : signal is "true";
+-- attribute mark_debug of rxLocked0_S : signal is "true";
+-- attribute mark_debug of rxLossOfSync1_S : signal is "true";
+-- attribute mark_debug of rxResetBitLock_S : signal is "true";
+-- attribute mark_debug of fsmStatus_S : signal is "true";
+-- attribute mark_debug of rxPLLwrapper_reset_S : signal is "true";
+-- attribute mark_debug of rxResetBitLock_pulse_S : signal is "true";
+-- attribute mark_debug of rxCDRlock_S : signal is "true";
+-- attribute mark_debug of CDR_reset_S : signal is "true";
+-- attribute mark_debug of disable_GTX_reset : signal is "true";
+
+
+begin
+ resetDone <= rxResetDone_sysclk_S;
+ rxLocked <= rxLocked2_S;
+ txLocked <= rxResetDone_sysclk_S;
+ rxUsrClkdiv2 <= ff_rxhalfclk;
+ txUsrClk <= ff_txfullclk;
+
+process(sysClk)
+variable resetDone_V : std_logic;
+begin
+ if rising_edge(sysClk) then
+ rxResetDone_sysclk_S <= resetDone_V;
+ resetDone_V := rxResetDone_S;
+ end if;
+end process;
+
+FEE_data8to16_1: FEE_data8to16
+ port map(
+ clock_in => ff_txfullclk,
+ data_in => txData,
+ kchar_in => txCharIsK,
+ clock_out => ff_txhalfclk,
+ data_out => txData16_S,
+ kchar_out => txCharIsK16_S
+ );
+
+FEE_data16to8_1: FEE_data16to8
+ port map(
+ clock_in => ff_rxhalfclk,
+ data_in => rxData16_S,
+ kchar_in => rxCharIsK16_S,
+ notintable_in => rxNotInTable16_S,
+ clock_out => rxUsrClk,
+ data_out => rxData_S,
+ kchar_out => rxCharIsK_S,
+ notintable_out => rxNotInTable_S
+ );
+rxData <= rxData_S;
+rxCharIsK <= rxCharIsK_S;
+rxNotInTable <= rxNotInTable_S;
+
+gtx_i : gtxKintex7FEE80_support
+ port map(
+ SOFT_RESET_TX_IN => gtpReset_S,
+ SOFT_RESET_RX_IN => gtpReset_S,
+ DONT_RESET_ON_DATA_ERROR_IN => '1',
+ Q0_CLK0_GTREFCLK_PAD_N_IN => gtpClk_N,
+ Q0_CLK0_GTREFCLK_PAD_P_IN => gtpClk_P,
+
+ GT0_TX_FSM_RESET_DONE_OUT => open,
+ GT0_RX_FSM_RESET_DONE_OUT => open,
+ GT0_DATA_VALID_IN => '1',
+ GT0_TX_MMCM_LOCK_OUT => open,
+
+ GT0_TXUSRCLK_OUT => open,
+ GT0_TXUSRCLK2_OUT => ff_txhalfclk, -- clock for tx_data (100MHz)
+ GT0_TXUSRCLKX2_OUT => ff_txfullclk, -- clock for 8 bits data (200MHz)
+ GT0_RXUSRCLK_OUT => open,
+ GT0_RXUSRCLK2_OUT => ff_rxhalfclk, -- clock for rx_data (100MHz)
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => open,
+ gt0_cplllock_out => pllLkDet_S,
+ gt0_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => drpaddr_in_S,
+ gt0_drpdi_in => drpdi_in_S,
+ gt0_drpdo_out => drpdo_out_S,
+ gt0_drpen_in => drpen_in_S,
+ gt0_drprdy_out => drprdy_out_S,
+ gt0_drpwe_in => drpwe_in_S,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => '0',
+ gt0_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => open,
+ gt0_eyescantrigger_in => '0',
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => CDR_reset_S,
+ GT0_RXCDRLOCK_OUT => rxCDRlock_S,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => rxData16_S,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => rxDispError16_S,
+ gt0_rxnotintable_out => rxNotInTable16_S,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => rxP,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => rxN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => open,
+ gt0_rxphslipmonitor_out => open,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => '0',
+ gt0_rxmonitorout_out => open,
+ gt0_rxmonitorsel_in => "00",
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => rxReset_S,
+ gt0_rxpmareset_in => rxReset_S,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => rxCharIsK16_S,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => rxResetDone_S,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => '0',
+ gt0_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => txData16_S,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => txN,
+ gt0_gtxtxp_out => txP,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out => open,
+ gt0_txoutclkpcs_out => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => txCharIsK16_S,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => txResetdone_S,
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
+ GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
+ sysclk_in => sysClk,
+ refclk_out => refclk_out --// Modified
+ );
+
+
+rxLossOfSync1_S <= '0' when (rxNotInTable16_S="00") or (disable_GTX_reset='1') else '1';
+FEE_rxBitLock1 : FEE_rxBitLock port map (
+ clk => ff_rxhalfclk,
+ reset => gtpReset_S,
+ resetDone => rxResetDone_S,
+ lossOfSync => rxLossOfSync1_S,
+ rxPllLocked => PllLkDet_S,
+ rxReset => rxResetBitLock_S,
+ fsmStatus => fsmStatus_S
+ );
+
+
+process(sysClk,gtpReset)
+variable counter_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+ if gtpReset='1' then
+ gtpReset_S <= '1';
+ counter_V := (others => '0');
+ elsif rising_edge(sysClk) then
+ gtpReset_S <= '0';
+ if counter_V(counter_V'left)='1' then
+ if rxResetDone_S='0' then
+ counter_V := (others => '0');
+ gtpReset_S <= '1';
+ end if;
+ else
+ counter_V := counter_V+1;
+ end if;
+ end if;
+end process;
+
+---- rxReset_S <= gtpReset;
+rxReset_S <= '1' when ((rxPLLwrapper_reset_S='1') or (gtpReset_S='1') or (rxResetBitLock_pulse_S='1')) and (disable_GTX_reset='0') else '0';
+rxLocked0_S <= '1' when (rxResetDone_S='1') and (fsmStatus_S = "10") else '0';
+
+
+process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ if (sync_rxResetBitLock_S='1') and (prev_rxResetBitLock_S='0') then
+ rxResetBitLock_pulse_S <= '1';
+ else
+ rxResetBitLock_pulse_S <= '0';
+ end if;
+ sync_rxResetBitLock_S <= rxResetBitLock_S;
+ prev_rxResetBitLock_S <= sync_rxResetBitLock_S;
+ end if;
+end process;
+
+process(sysClk)
+variable counter_V : std_logic_vector(5 downto 0) := (others => '0');
+variable timoutcounter_V : std_logic_vector(7 downto 0) := (others => '0');
+begin
+ if rising_edge(sysClk) then
+ rxPLLwrapper_reset_S <= '0';
+ CDR_reset_S <= '0';
+ comma_align_latency_valid_S <= '0';
+ drpen_in_S <= '0';
+ drpwe_in_S <= '0';
+ drpdi_in_S <= (others => '0');
+ case drp_state_S is
+ when initting =>
+ rxLocked2_S <= '0';
+ counter_V := (others => '0');
+ if rxResetDone_S='1' then
+ drp_state_S <= running;
+ end if;
+ when running =>
+ if rxLocked1_S='0' then
+ drp_state_S <= initting;
+ else
+ if counter_V(counter_V'left) = '1' then
+ counter_V := (others => '0');
+ timoutcounter_V := (others => '0');
+ drpen_in_S <= '1';
+ drpaddr_in_S <= "101001110"; -- x"14E";
+ drp_state_S <= reading;
+ else
+ counter_V := counter_V+1;
+ end if;
+ end if;
+ when reading =>
+ if drprdy_out_S='1' then
+ comma_align_latency_S <= drpdo_out_S(6 downto 0); -- COMMA_ALIGN_LATENCY
+ comma_align_latency_valid_S <= '1';
+ if drpdo_out_S(6 downto 0)/="0000000" then
+ CDR_reset_S <= '1'; --// rxPLLwrapper_reset_S <= '1';
+ rxLocked2_S <= '0';
+ else
+ rxLocked2_S <= '1';
+ end if;
+ drp_state_S <= running;
+ elsif timoutcounter_V(timoutcounter_V'left)='1' then
+ drp_state_S <= initting;
+ else
+ timoutcounter_V := timoutcounter_V+1;
+ end if;
+ when others =>
+ drp_state_S <= initting;
+ end case;
+ rxLocked1_S <= rxLocked0_S;
+ end if;
+end process;
+
+
+end Behavioral;
--- /dev/null
+---------------------------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_common.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_common
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+
+
+--***************************** Entity Declaration ****************************
+entity gtx_common is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
+ SIM_QPLLREFCLK_SEL : bit_vector := "001"
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK1_IN : in std_logic;
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+);
+
+end gtx_common;
+
+architecture RTL of gtx_common is
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "gtx_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_TOP : integer := 40;
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
+
+begin
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+
+ gtxe2_common_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
+ SIM_VERSION => "4.0",
+
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (1)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GTREFCLK0_IN,
+ GTREFCLK1 => GTREFCLK1_IN,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports -----------------------
+ QPLLDMONITOR => open,
+ ----------------------- Common Block - Clocking Ports ----------------------
+ QPLLOUTCLK => QPLLOUTCLK_OUT,
+ QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
+ REFCLKOUTMONITOR => open,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => QPLLLOCK_OUT,
+ QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_vcc_i,
+ QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
+ QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
+ QPLLRESET => QPLLRESET_IN,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ --------------------------------- QPLL Ports -------------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "11111",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+end RTL;
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 2.6
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80 (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity gtxKintex7FEE80 is
+generic
+(
+ QPLL_FBDIV_TOP : integer := 16;
+
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
+ RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
+ PMA_RSV_IN : bit_vector := x"00018480"
+
+);
+port
+(
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X0Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ GT0_CPLLFBCLKLOST_OUT : out std_logic;
+ GT0_CPLLLOCK_OUT : out std_logic;
+ GT0_CPLLLOCKDETCLK_IN : in std_logic;
+ GT0_CPLLREFCLKLOST_OUT : out std_logic;
+ GT0_CPLLRESET_IN : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ GT0_GTREFCLK0_IN : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
+ GT0_DRPCLK_IN : in std_logic;
+ GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
+ GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
+ GT0_DRPEN_IN : in std_logic;
+ GT0_DRPRDY_OUT : out std_logic;
+ GT0_DRPWE_IN : in std_logic;
+ --------------------- RX Initialization and Reset Ports --------------------
+ GT0_RXUSERRDY_IN : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ GT0_EYESCANDATAERROR_OUT : out std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic;
+ GT0_RXCDRLOCK_OUT : out std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ GT0_RXUSRCLK_IN : in std_logic;
+ GT0_RXUSRCLK2_IN : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
+ GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GT0_GTXRXP_IN : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GT0_GTXRXN_IN : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ GT0_RXDLYEN_IN : in std_logic;
+ GT0_RXDLYSRESET_IN : in std_logic;
+ GT0_RXDLYSRESETDONE_OUT : out std_logic;
+ GT0_RXPHALIGN_IN : in std_logic;
+ GT0_RXPHALIGNDONE_OUT : out std_logic;
+ GT0_RXPHALIGNEN_IN : in std_logic;
+ GT0_RXPHDLYRESET_IN : in std_logic;
+ GT0_RXPHMONITOR_OUT : out std_logic_vector(4 downto 0);
+ GT0_RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ GT0_RXLPMHFHOLD_IN : in std_logic;
+ GT0_RXLPMLFHOLD_IN : in std_logic;
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ GT0_RXOUTCLK_OUT : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GT0_GTRXRESET_IN : in std_logic;
+ GT0_RXPCSRESET_IN : in std_logic;
+ GT0_RXPMARESET_IN : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ GT0_RXRESETDONE_OUT : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ GT0_GTTXRESET_IN : in std_logic;
+ GT0_TXUSERRDY_IN : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ GT0_TXUSRCLK_IN : in std_logic;
+ GT0_TXUSRCLK2_IN : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ GT0_TXDLYEN_IN : in std_logic;
+ GT0_TXDLYSRESET_IN : in std_logic;
+ GT0_TXDLYSRESETDONE_OUT : out std_logic;
+ GT0_TXPHALIGN_IN : in std_logic;
+ GT0_TXPHALIGNDONE_OUT : out std_logic;
+ GT0_TXPHALIGNEN_IN : in std_logic;
+ GT0_TXPHDLYRESET_IN : in std_logic;
+ GT0_TXPHINIT_IN : in std_logic;
+ GT0_TXPHINITDONE_OUT : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GT0_GTXTXN_OUT : out std_logic;
+ GT0_GTXTXP_OUT : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ GT0_TXOUTCLK_OUT : out std_logic;
+ GT0_TXOUTCLKFABRIC_OUT : out std_logic;
+ GT0_TXOUTCLKPCS_OUT : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ GT0_TXRESETDONE_OUT : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GT0_GTREFCLK0_COMMON_IN : in std_logic;
+ ------------------------- Common Block - QPLL Ports ------------------------
+ GT0_QPLLLOCK_OUT : out std_logic;
+ GT0_QPLLLOCKDETCLK_IN : in std_logic;
+ GT0_QPLLREFCLKLOST_OUT : out std_logic;
+ GT0_QPLLRESET_IN : in std_logic
+
+
+);
+
+
+end gtxKintex7FEE80;
+
+architecture RTL of gtxKintex7FEE80 is
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80,gtwizard_v2_6,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+
+ signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
+ signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
+
+
+ signal gt0_qpllclk_i : std_logic;
+ signal gt0_qpllrefclk_i : std_logic;
+
+
+--*************************** Component Declarations **************************
+component gtxKintex7FEE80_GT
+generic
+(
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
+ RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
+ PMA_RSV_IN : bit_vector := X"00000000";
+ PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
+);
+port
+(
+ --------------------------------- CPLL Ports -------------------------------
+ CPLLFBCLKLOST_OUT : out std_logic;
+ CPLLLOCK_OUT : out std_logic;
+ CPLLLOCKDETCLK_IN : in std_logic;
+ CPLLREFCLKLOST_OUT : out std_logic;
+ CPLLRESET_IN : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ GTREFCLK0_IN : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ DRPADDR_IN : in std_logic_vector(8 downto 0);
+ DRPCLK_IN : in std_logic;
+ DRPDI_IN : in std_logic_vector(15 downto 0);
+ DRPDO_OUT : out std_logic_vector(15 downto 0);
+ DRPEN_IN : in std_logic;
+ DRPRDY_OUT : out std_logic;
+ DRPWE_IN : in std_logic;
+ ------------------------------- Clocking Ports -----------------------------
+ QPLLCLK_IN : in std_logic;
+ QPLLREFCLK_IN : in std_logic;
+ --------------------- RX Initialization and Reset Ports --------------------
+ RXUSERRDY_IN : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ EYESCANDATAERROR_OUT : out std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN : in std_logic;
+ RXCDRLOCK_OUT : out std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ RXUSRCLK_IN : in std_logic;
+ RXUSRCLK2_IN : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ RXDATA_OUT : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ RXDISPERR_OUT : out std_logic_vector(1 downto 0);
+ RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GTXRXP_IN : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GTXRXN_IN : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ RXDLYEN_IN : in std_logic;
+ RXDLYSRESET_IN : in std_logic;
+ RXDLYSRESETDONE_OUT : out std_logic;
+ RXPHALIGN_IN : in std_logic;
+ RXPHALIGNDONE_OUT : out std_logic;
+ RXPHALIGNEN_IN : in std_logic;
+ RXPHDLYRESET_IN : in std_logic;
+ RXPHMONITOR_OUT : out std_logic_vector(4 downto 0);
+ RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ RXLPMHFHOLD_IN : in std_logic;
+ RXLPMLFHOLD_IN : in std_logic;
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ RXOUTCLK_OUT : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GTRXRESET_IN : in std_logic;
+ RXPCSRESET_IN : in std_logic;
+ RXPMARESET_IN : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ RXCHARISK_OUT : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ RXRESETDONE_OUT : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ GTTXRESET_IN : in std_logic;
+ TXUSERRDY_IN : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ TXUSRCLK_IN : in std_logic;
+ TXUSRCLK2_IN : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ TXDLYEN_IN : in std_logic;
+ TXDLYSRESET_IN : in std_logic;
+ TXDLYSRESETDONE_OUT : out std_logic;
+ TXPHALIGN_IN : in std_logic;
+ TXPHALIGNDONE_OUT : out std_logic;
+ TXPHALIGNEN_IN : in std_logic;
+ TXPHDLYRESET_IN : in std_logic;
+ TXPHINIT_IN : in std_logic;
+ TXPHINITDONE_OUT : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA_IN : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTXTXN_OUT : out std_logic;
+ GTXTXP_OUT : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ TXOUTCLK_OUT : out std_logic;
+ TXOUTCLKFABRIC_OUT : out std_logic;
+ TXOUTCLKPCS_OUT : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ TXCHARISK_IN : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ TXRESETDONE_OUT : out std_logic
+
+
+);
+end component;
+
+
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+--********************************* Main Body of Code**************************
+
+begin
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ gt0_qpllclk_i <= gt0_qplloutclk_i;
+ gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
+
+
+
+ --------------------------- GT Instances -------------------------------
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X0Y0)
+
+ gt0_gtxKintex7FEE80_i : gtxKintex7FEE80_GT
+ generic map
+ (
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
+ PMA_RSV_IN => PMA_RSV_IN,
+ PCS_RSVD_ATTR_IN => X"000000000006"
+ )
+ port map
+ (
+ --------------------------------- CPLL Ports -------------------------------
+ CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT,
+ CPLLLOCK_OUT => GT0_CPLLLOCK_OUT,
+ CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN,
+ CPLLREFCLKLOST_OUT => GT0_CPLLREFCLKLOST_OUT,
+ CPLLRESET_IN => GT0_CPLLRESET_IN,
+ -------------------------- Channel - Clocking Ports ------------------------
+ GTREFCLK0_IN => GT0_GTREFCLK0_IN,
+ ---------------------------- Channel - DRP Ports --------------------------
+ DRPADDR_IN => GT0_DRPADDR_IN,
+ DRPCLK_IN => GT0_DRPCLK_IN,
+ DRPDI_IN => GT0_DRPDI_IN,
+ DRPDO_OUT => GT0_DRPDO_OUT,
+ DRPEN_IN => GT0_DRPEN_IN,
+ DRPRDY_OUT => GT0_DRPRDY_OUT,
+ DRPWE_IN => GT0_DRPWE_IN,
+ ------------------------------- Clocking Ports -----------------------------
+ QPLLCLK_IN => gt0_qpllclk_i,
+ QPLLREFCLK_IN => gt0_qpllrefclk_i,
+ --------------------- RX Initialization and Reset Ports --------------------
+ RXUSERRDY_IN => GT0_RXUSERRDY_IN,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN => GT0_RXCDRRESET_IN,
+ RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ RXUSRCLK_IN => GT0_RXUSRCLK_IN,
+ RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ RXDATA_OUT => GT0_RXDATA_OUT,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ RXDISPERR_OUT => GT0_RXDISPERR_OUT,
+ RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GTXRXP_IN => GT0_GTXRXP_IN,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GTXRXN_IN => GT0_GTXRXN_IN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ RXDLYEN_IN => GT0_RXDLYEN_IN,
+ RXDLYSRESET_IN => GT0_RXDLYSRESET_IN,
+ RXDLYSRESETDONE_OUT => GT0_RXDLYSRESETDONE_OUT,
+ RXPHALIGN_IN => GT0_RXPHALIGN_IN,
+ RXPHALIGNDONE_OUT => GT0_RXPHALIGNDONE_OUT,
+ RXPHALIGNEN_IN => GT0_RXPHALIGNEN_IN,
+ RXPHDLYRESET_IN => GT0_RXPHDLYRESET_IN,
+ RXPHMONITOR_OUT => GT0_RXPHMONITOR_OUT,
+ RXPHSLIPMONITOR_OUT => GT0_RXPHSLIPMONITOR_OUT,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ RXLPMHFHOLD_IN => GT0_RXLPMHFHOLD_IN,
+ RXLPMLFHOLD_IN => GT0_RXLPMLFHOLD_IN,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GTRXRESET_IN => GT0_GTRXRESET_IN,
+ RXPCSRESET_IN => GT0_RXPCSRESET_IN,
+ RXPMARESET_IN => GT0_RXPMARESET_IN,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ RXCHARISK_OUT => GT0_RXCHARISK_OUT,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ RXRESETDONE_OUT => GT0_RXRESETDONE_OUT,
+ --------------------- TX Initialization and Reset Ports --------------------
+ GTTXRESET_IN => GT0_GTTXRESET_IN,
+ TXUSERRDY_IN => GT0_TXUSERRDY_IN,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ TXUSRCLK_IN => GT0_TXUSRCLK_IN,
+ TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ TXDLYEN_IN => GT0_TXDLYEN_IN,
+ TXDLYSRESET_IN => GT0_TXDLYSRESET_IN,
+ TXDLYSRESETDONE_OUT => GT0_TXDLYSRESETDONE_OUT,
+ TXPHALIGN_IN => GT0_TXPHALIGN_IN,
+ TXPHALIGNDONE_OUT => GT0_TXPHALIGNDONE_OUT,
+ TXPHALIGNEN_IN => GT0_TXPHALIGNEN_IN,
+ TXPHDLYRESET_IN => GT0_TXPHDLYRESET_IN,
+ TXPHINIT_IN => GT0_TXPHINIT_IN,
+ TXPHINITDONE_OUT => GT0_TXPHINITDONE_OUT,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA_IN => GT0_TXDATA_IN,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTXTXN_OUT => GT0_GTXTXN_OUT,
+ GTXTXP_OUT => GT0_GTXTXP_OUT,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
+ TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT,
+ TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ TXCHARISK_IN => GT0_TXCHARISK_IN,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ TXRESETDONE_OUT => GT0_TXRESETDONE_OUT
+
+ );
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+
+ gtxe2_common_0_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => ("001"),
+ SIM_VERSION => "4.0",
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (1)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN,
+ GTREFCLK1 => tied_to_ground_i,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports -----------------------
+ QPLLDMONITOR => open,
+ ----------------------- Common Block - Clocking Ports ----------------------
+ QPLLOUTCLK => gt0_qplloutclk_i,
+ QPLLOUTREFCLK => gt0_qplloutrefclk_i,
+ REFCLKOUTMONITOR => open,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => GT0_QPLLLOCK_OUT,
+ QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_ground_i,
+ QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT,
+ QPLLREFCLKSEL => "001",
+ QPLLRESET => GT0_QPLLRESET_IN,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ --------------------------------- QPLL Ports -------------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "00000",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+
+
+end RTL;
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2.6
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtxkintex7fee80_auto_phase_align.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+-- Description : The logic below implements the procedure to do automatic phase-alignment
+-- on the 7-series GTX as described in ug476pdf, version 1.3,
+-- Chapters "Using the TX Phase Alignment to Bypass the TX Buffer"
+-- and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer"
+-- Should the logic below differ from what is described in a later version
+-- of the user-guide, you are using an auto-alignment block, which is
+-- out of date and needs to be updated for safe operation.
+--
+--
+--
+-- Module gtxKintex7FEE80_AUTO_PHASE_ALIGN
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_AUTO_PHASE_ALIGN is
+ Generic(
+ GT_TYPE : string := "GTX"
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Auto phase-alignment performed sucessfully
+ PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the
+ DLYSRESET : out STD_LOGIC; -- |transceiver.
+ DLYSRESETDONE : in STD_LOGIC; --/
+ RECCLKSTABLE : in STD_LOGIC --/on the RX-side.
+
+ );
+end gtxKintex7FEE80_AUTO_PHASE_ALIGN;
+
+architecture RTL of gtxKintex7FEE80_AUTO_PHASE_ALIGN is
+
+ component gtxKintex7FEE80_sync_block
+ generic (
+ INITIALISE : bit_vector(1 downto 0) := "00"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ type phase_align_auto_fsm is(
+ INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE
+ );
+
+ signal phalign_state : phase_align_auto_fsm := INIT;
+ signal phaligndone_prev : std_logic := '0';
+ signal phaligndone_ris_edge : std_logic;
+
+ signal count_phalign_edges : integer range 0 to 3:= 0;
+ signal phaligndone_sync : std_logic := '0';
+ signal dlysresetdone_sync : std_logic := '0';
+
+begin
+
+ sync_PHALIGNDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => PHALIGNDONE,
+ data_out => phaligndone_sync
+ );
+
+ sync_DLYSRESETDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => DLYSRESETDONE,
+ data_out => dlysresetdone_sync
+ );
+
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ phaligndone_prev <= phaligndone_sync;
+ end if;
+ end process;
+ phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0';
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then
+ DLYSRESET <= '0';
+ count_phalign_edges <= 0;
+ PHASE_ALIGNMENT_DONE <= '0';
+ phalign_state <= INIT;
+ else
+ if phaligndone_ris_edge = '1' then
+ if count_phalign_edges < 3 then
+ count_phalign_edges <= count_phalign_edges + 1;
+ end if;
+ end if;
+
+ DLYSRESET <= '0';
+
+ case phalign_state is
+ when INIT =>
+ PHASE_ALIGNMENT_DONE <= '0';
+ if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then
+ --DLYSRESET is toggled to '1'
+ DLYSRESET <= '1';
+ phalign_state <= WAIT_PHRST_DONE;
+ end if;
+
+ when WAIT_PHRST_DONE =>
+ if dlysresetdone_sync = '1' then
+ phalign_state <= COUNT_PHALIGN_DONE;
+ end if;
+ --No timeout-check here as that is done in the main FSM
+
+ when COUNT_PHALIGN_DONE =>
+ if ((GT_TYPE = "GTX" and count_phalign_edges = 2) or ((GT_TYPE = "GTH" or GT_TYPE = "GTP") and phaligndone_ris_edge = '1')) then
+ --For GTX: Only on the second edge of the PHALIGNDONE-signal the
+ -- phase-alignment is completed
+ --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment
+
+ phalign_state <= PHALIGN_DONE;
+ end if;
+
+ when PHALIGN_DONE =>
+ PHASE_ALIGNMENT_DONE <= '1';
+
+ when OTHERS =>
+ phalign_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
+
--- file: clockmodule80to80M.vhd\r
--- \r
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
--- \r
-------------------------------------------------------------------------------\r
--- User entered comments\r
-------------------------------------------------------------------------------\r
--- None\r
---\r
-------------------------------------------------------------------------------\r
--- "Output Output Phase Duty Pk-to-Pk Phase"\r
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
-------------------------------------------------------------------------------\r
--- CLK_OUT1____40.000______0.000______50.0______174.629____114.212\r
--- CLK_OUT2____80.000______0.000______50.0______151.652____114.212\r
--- CLK_OUT3___100.000______0.000______50.0______144.719____114.212\r
--- CLK_OUT4___200.000______0.000______50.0______126.455____114.212\r
---\r
-------------------------------------------------------------------------------\r
--- "Input Clock Freq (MHz) Input Jitter (UI)"\r
-------------------------------------------------------------------------------\r
--- __primary_____________100____________0.010\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.numeric_std.all;\r
-\r
-library unisim;\r
-use unisim.vcomponents.all;\r
-\r
-entity clockmodule80to80M is\r
-port\r
- (-- Clock in ports\r
- CLK_IN1 : in std_logic;\r
- -- Clock out ports\r
- CLK_OUT1 : out std_logic;\r
- CLK_OUT2 : out std_logic;\r
- CLK_OUT3 : out std_logic;\r
- CLK_OUT4 : out std_logic;\r
- -- Status and control signals\r
- RESET : in std_logic;\r
- LOCKED : out std_logic\r
- );\r
-end clockmodule80to80M;\r
-\r
-architecture xilinx of clockmodule80to80M is\r
- attribute CORE_GENERATION_INFO : string;\r
- attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule80to80M,clk_wiz_v3_6,{component_name=clockmodule80to80M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";\r
- -- Input clock buffering / unused connectors\r
- signal clkin1 : std_logic;\r
- -- Output clock buffering / unused connectors\r
- signal clkfbout : std_logic;\r
- signal clkfbout_buf : std_logic;\r
- signal clkfboutb_unused : std_logic;\r
- signal clkout0 : std_logic;\r
- signal clkout0b_unused : std_logic;\r
- signal clkout1 : std_logic;\r
- signal clkout1b_unused : std_logic;\r
- signal clkout2 : std_logic;\r
- signal clkout2b_unused : std_logic;\r
- signal clkout3 : std_logic;\r
- signal clkout3b_unused : std_logic;\r
- signal clkout4_unused : std_logic;\r
- signal clkout5_unused : std_logic;\r
- signal clkout6_unused : std_logic;\r
- -- Dynamic programming unused signals\r
- signal do_unused : std_logic_vector(15 downto 0);\r
- signal drdy_unused : std_logic;\r
- -- Dynamic phase shift unused signals\r
- signal psdone_unused : std_logic;\r
- -- Unused status signals\r
- signal clkfbstopped_unused : std_logic;\r
- signal clkinstopped_unused : std_logic;\r
-begin\r
-\r
-\r
- -- Input buffering\r
- --------------------------------------\r
- clkin1 <= CLK_IN1;\r
-\r
-\r
- -- Clocking primitive\r
- --------------------------------------\r
- -- Instantiation of the MMCM primitive\r
- -- * Unused inputs are tied off\r
- -- * Unused outputs are labeled unused\r
- mmcm_adv_inst : MMCM_ADV\r
- generic map\r
- (BANDWIDTH => "OPTIMIZED",\r
- CLKOUT4_CASCADE => FALSE,\r
- CLOCK_HOLD => FALSE,\r
- COMPENSATION => "ZHOLD",\r
- STARTUP_WAIT => FALSE,\r
- DIVCLK_DIVIDE => 1,\r
- CLKFBOUT_MULT_F => 8.000,\r
- CLKFBOUT_PHASE => 0.000,\r
- CLKFBOUT_USE_FINE_PS => FALSE,\r
- CLKOUT0_DIVIDE_F => 20.000,\r
- CLKOUT0_PHASE => 0.000,\r
- CLKOUT0_DUTY_CYCLE => 0.500,\r
- CLKOUT0_USE_FINE_PS => FALSE,\r
- CLKOUT1_DIVIDE => 10,\r
- CLKOUT1_PHASE => 0.000,\r
- CLKOUT1_DUTY_CYCLE => 0.500,\r
- CLKOUT1_USE_FINE_PS => FALSE,\r
- CLKOUT2_DIVIDE => 8,\r
- CLKOUT2_PHASE => 0.000,\r
- CLKOUT2_DUTY_CYCLE => 0.500,\r
- CLKOUT2_USE_FINE_PS => FALSE,\r
- CLKOUT3_DIVIDE => 4,\r
- CLKOUT3_PHASE => 0.000,\r
- CLKOUT3_DUTY_CYCLE => 0.500,\r
- CLKOUT3_USE_FINE_PS => FALSE,\r
- CLKIN1_PERIOD => 10.000,\r
- REF_JITTER1 => 0.010)\r
- port map\r
- -- Output clocks\r
- (CLKFBOUT => clkfbout,\r
- CLKFBOUTB => clkfboutb_unused,\r
- CLKOUT0 => clkout0,\r
- CLKOUT0B => clkout0b_unused,\r
- CLKOUT1 => clkout1,\r
- CLKOUT1B => clkout1b_unused,\r
- CLKOUT2 => clkout2,\r
- CLKOUT2B => clkout2b_unused,\r
- CLKOUT3 => clkout3,\r
- CLKOUT3B => clkout3b_unused,\r
- CLKOUT4 => clkout4_unused,\r
- CLKOUT5 => clkout5_unused,\r
- CLKOUT6 => clkout6_unused,\r
- -- Input clock control\r
- CLKFBIN => clkfbout_buf,\r
- CLKIN1 => clkin1,\r
- CLKIN2 => '0',\r
- -- Tied to always select the primary input clock\r
- CLKINSEL => '1',\r
- -- Ports for dynamic reconfiguration\r
- DADDR => (others => '0'),\r
- DCLK => '0',\r
- DEN => '0',\r
- DI => (others => '0'),\r
- DO => do_unused,\r
- DRDY => drdy_unused,\r
- DWE => '0',\r
- -- Ports for dynamic phase shift\r
- PSCLK => '0',\r
- PSEN => '0',\r
- PSINCDEC => '0',\r
- PSDONE => psdone_unused,\r
- -- Other control and status signals\r
- LOCKED => LOCKED,\r
- CLKINSTOPPED => clkinstopped_unused,\r
- CLKFBSTOPPED => clkfbstopped_unused,\r
- PWRDWN => '0',\r
- RST => RESET);\r
-\r
- -- Output buffering\r
- -------------------------------------\r
- clkf_buf : BUFG\r
- port map\r
- (O => clkfbout_buf,\r
- I => clkfbout);\r
-\r
-\r
- clkout1_buf : BUFG\r
- port map\r
- (O => CLK_OUT1,\r
- I => clkout0);\r
-\r
-\r
-\r
- clkout2_buf : BUFG\r
- port map\r
- (O => CLK_OUT2,\r
- I => clkout1);\r
-\r
- clkout3_buf : BUFG\r
- port map\r
- (O => CLK_OUT3,\r
- I => clkout2);\r
-\r
- clkout4_buf : BUFG\r
- port map\r
- (O => CLK_OUT4,\r
- I => clkout3);\r
-\r
-end xilinx;\r
+-- file: clk_wiz_v2_1.vhd
+--
+-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1 100.000 0.000 50.000 130.958 98.575
+-- CLK_OUT2 200.000 0.000 50.000 114.829 98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock Input Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary 100.000 0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTXKINTEX7FEE80_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end GTXKINTEX7FEE80_CLOCK_MODULE;
+
+architecture xilinx of GTXKINTEX7FEE80_CLOCK_MODULE is
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+ -- Input clock buffering / unused connectors
+ signal clkin1 : std_logic;
+ -- Output clock buffering / unused connectors
+ signal clkfbout : std_logic;
+ signal clkfbout_buf : std_logic;
+ signal clkfboutb_unused : std_logic;
+ signal clkout0 : std_logic;
+ signal clkout0b_unused : std_logic;
+ signal clkout1 : std_logic;
+ signal clkout1b_unused : std_logic;
+ signal clkout2 : std_logic;
+ signal clkout2b_unused : std_logic;
+ signal clkout3 : std_logic;
+ signal clkout3b_unused : std_logic;
+ signal clkout4_unused : std_logic;
+ signal clkout5_unused : std_logic;
+ signal clkout6_unused : std_logic;
+ -- Dynamic programming unused signals
+ signal do_unused : std_logic_vector(15 downto 0);
+ signal drdy_unused : std_logic;
+ -- Dynamic phase shift unused signals
+ signal psdone_unused : std_logic;
+ -- Unused status signals
+ signal clkfbstopped_unused : std_logic;
+ signal clkinstopped_unused : std_logic;
+begin
+
+
+ -- Input buffering
+ --------------------------------------
+ clkin1_buf : BUFG
+ port map
+ (O => clkin1,
+ I => CLK_IN);
+
+ -- Clocking primitive
+ --------------------------------------
+ -- Instantiation of the MMCM primitive
+ -- * Unused inputs are tied off
+ -- * Unused outputs are labeled unused
+
+ mmcm_adv_inst : MMCME2_ADV
+ generic map
+ (BANDWIDTH => "OPTIMIZED",
+ CLKOUT4_CASCADE => FALSE,
+ COMPENSATION => "ZHOLD",
+ STARTUP_WAIT => FALSE,
+ DIVCLK_DIVIDE => DIVIDE,
+ CLKFBOUT_MULT_F => MULT,
+ CLKFBOUT_PHASE => 0.000,
+ CLKFBOUT_USE_FINE_PS => FALSE,
+ CLKOUT0_DIVIDE_F => OUT0_DIVIDE,
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKOUT0_USE_FINE_PS => FALSE,
+ CLKIN1_PERIOD => CLK_PERIOD,
+ CLKOUT1_DIVIDE => OUT1_DIVIDE,
+ CLKOUT1_PHASE => 0.000,
+ CLKOUT1_DUTY_CYCLE => 0.500,
+ CLKOUT1_USE_FINE_PS => FALSE,
+ CLKOUT2_DIVIDE => OUT2_DIVIDE,
+ CLKOUT2_PHASE => 0.000,
+ CLKOUT2_DUTY_CYCLE => 0.500,
+ CLKOUT2_USE_FINE_PS => FALSE,
+ CLKOUT3_DIVIDE => OUT3_DIVIDE,
+ CLKOUT3_PHASE => 0.000,
+ CLKOUT3_DUTY_CYCLE => 0.500,
+ CLKOUT3_USE_FINE_PS => FALSE,
+ REF_JITTER1 => 0.010)
+ port map
+ -- Output clocks
+ (CLKFBOUT => clkfbout,
+ CLKFBOUTB => clkfboutb_unused,
+ CLKOUT0 => clkout0,
+ CLKOUT0B => clkout0b_unused,
+ CLKOUT1 => clkout1,
+ CLKOUT1B => clkout1b_unused,
+ CLKOUT2 => clkout2,
+ CLKOUT2B => clkout2b_unused,
+ CLKOUT3 => clkout3,
+ CLKOUT3B => clkout3b_unused,
+ CLKOUT4 => clkout4_unused,
+ CLKOUT5 => clkout5_unused,
+ CLKOUT6 => clkout6_unused,
+ -- Input clock control
+ CLKFBIN => clkfbout,
+ CLKIN1 => clkin1,
+ CLKIN2 => '0',
+ -- Tied to always select the primary input clock
+ CLKINSEL => '1',
+ -- Ports for dynamic reconfiguration
+ DADDR => (others => '0'),
+ DCLK => '0',
+ DEN => '0',
+ DI => (others => '0'),
+ DO => do_unused,
+ DRDY => drdy_unused,
+ DWE => '0',
+ -- Ports for dynamic phase shift
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ PSDONE => psdone_unused,
+ -- Other control and status signals
+ LOCKED => MMCM_LOCKED_OUT,
+ CLKINSTOPPED => clkinstopped_unused,
+ CLKFBSTOPPED => clkfbstopped_unused,
+ PWRDWN => '0',
+ RST => MMCM_RESET_IN);
+
+ -- Output buffering
+ -------------------------------------
+ --clkf_buf : BUFG
+ --port map
+ -- (O => clkfbout_buf,
+ -- I => clkfbout);
+
+
+ clkout0_buf : BUFG
+ port map
+ (O => CLK0_OUT,
+ I => clkout0);
+
+ clkout1_buf : BUFG
+ port map
+ (O => CLK1_OUT,
+ I => clkout1);
+
+ clkout2_buf : BUFG
+ port map
+ (O => CLK2_OUT,
+ I => clkout2);
+
+ clkout3_buf : BUFG
+ port map
+ (O => CLK3_OUT,
+ I => clkout3);
+
+end xilinx;
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 2.6
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_gt.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity gtxKintex7FEE80_GT is
+generic
+(
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
+ RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
+ PMA_RSV_IN : bit_vector := x"00018480";
+ PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
+);
+port
+(
+ --------------------------------- CPLL Ports -------------------------------
+ CPLLFBCLKLOST_OUT : out std_logic;
+ CPLLLOCK_OUT : out std_logic;
+ CPLLLOCKDETCLK_IN : in std_logic;
+ CPLLREFCLKLOST_OUT : out std_logic;
+ CPLLRESET_IN : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ GTREFCLK0_IN : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ DRPADDR_IN : in std_logic_vector(8 downto 0);
+ DRPCLK_IN : in std_logic;
+ DRPDI_IN : in std_logic_vector(15 downto 0);
+ DRPDO_OUT : out std_logic_vector(15 downto 0);
+ DRPEN_IN : in std_logic;
+ DRPRDY_OUT : out std_logic;
+ DRPWE_IN : in std_logic;
+ ------------------------------- Clocking Ports -----------------------------
+ QPLLCLK_IN : in std_logic;
+ QPLLREFCLK_IN : in std_logic;
+ --------------------- RX Initialization and Reset Ports --------------------
+ RXUSERRDY_IN : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ EYESCANDATAERROR_OUT : out std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN : in std_logic;
+ RXCDRLOCK_OUT : out std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ RXUSRCLK_IN : in std_logic;
+ RXUSRCLK2_IN : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ RXDATA_OUT : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ RXDISPERR_OUT : out std_logic_vector(1 downto 0);
+ RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GTXRXP_IN : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GTXRXN_IN : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ RXDLYEN_IN : in std_logic;
+ RXDLYSRESET_IN : in std_logic;
+ RXDLYSRESETDONE_OUT : out std_logic;
+ RXPHALIGN_IN : in std_logic;
+ RXPHALIGNDONE_OUT : out std_logic;
+ RXPHALIGNEN_IN : in std_logic;
+ RXPHDLYRESET_IN : in std_logic;
+ RXPHMONITOR_OUT : out std_logic_vector(4 downto 0);
+ RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ RXLPMHFHOLD_IN : in std_logic;
+ RXLPMLFHOLD_IN : in std_logic;
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ RXOUTCLK_OUT : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GTRXRESET_IN : in std_logic;
+ RXPCSRESET_IN : in std_logic;
+ RXPMARESET_IN : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ RXCHARISK_OUT : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ RXRESETDONE_OUT : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ GTTXRESET_IN : in std_logic;
+ TXUSERRDY_IN : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ TXUSRCLK_IN : in std_logic;
+ TXUSRCLK2_IN : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ TXDLYEN_IN : in std_logic;
+ TXDLYSRESET_IN : in std_logic;
+ TXDLYSRESETDONE_OUT : out std_logic;
+ TXPHALIGN_IN : in std_logic;
+ TXPHALIGNDONE_OUT : out std_logic;
+ TXPHALIGNEN_IN : in std_logic;
+ TXPHDLYRESET_IN : in std_logic;
+ TXPHINIT_IN : in std_logic;
+ TXPHINITDONE_OUT : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA_IN : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTXTXN_OUT : out std_logic;
+ GTXTXP_OUT : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ TXOUTCLK_OUT : out std_logic;
+ TXOUTCLKFABRIC_OUT : out std_logic;
+ TXOUTCLKPCS_OUT : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ TXCHARISK_IN : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ TXRESETDONE_OUT : out std_logic
+
+
+);
+
+
+end gtxKintex7FEE80_GT;
+
+architecture RTL of gtxKintex7FEE80_GT is
+
+--**************************** Signal Declarations ****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+
+
+
+ -- RX Datapath signals
+ signal rxdata_i : std_logic_vector(63 downto 0);
+ signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
+ signal rxcharisk_float_i : std_logic_vector(5 downto 0);
+ signal rxdisperr_float_i : std_logic_vector(5 downto 0);
+ signal rxnotintable_float_i : std_logic_vector(5 downto 0);
+ signal rxrundisp_float_i : std_logic_vector(5 downto 0);
+
+
+
+ -- TX Datapath signals
+ signal txdata_i : std_logic_vector(63 downto 0);
+ signal txkerr_float_i : std_logic_vector(5 downto 0);
+ signal txrundisp_float_i : std_logic_vector(5 downto 0);
+ signal rxstartofseq_float_i : std_logic;
+
+--******************************** Main Body of Code***************************
+
+begin
+
+ --------------------------- Static signal Assignments ---------------------
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+
+ ------------------- GT Datapath byte mapping -----------------
+
+ RXDATA_OUT <= rxdata_i(15 downto 0);
+
+ txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+ ----------------------------- GTXE2 Instance --------------------------
+
+ gtxe2_i :GTXE2_CHANNEL
+ generic map
+ (
+
+ --_______________________ Simulation-Only Attributes ___________________
+
+ SIM_RECEIVER_DETECT_PASS => ("TRUE"),
+ SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
+ SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
+ SIM_CPLLREFCLK_SEL => ("001"),
+ SIM_VERSION => ("4.0"),
+
+
+ ------------------RX Byte and Word Alignment Attributes---------------
+ ALIGN_COMMA_DOUBLE => ("FALSE"),
+ ALIGN_COMMA_ENABLE => ("1111111111"),
+ ALIGN_COMMA_WORD => (1),
+ ALIGN_MCOMMA_DET => ("TRUE"),
+ ALIGN_MCOMMA_VALUE => ("1010000011"),
+ ALIGN_PCOMMA_DET => ("TRUE"),
+ ALIGN_PCOMMA_VALUE => ("0101111100"),
+ SHOW_REALIGN_COMMA => ("FALSE"), --//("TRUE"),
+ RXSLIDE_AUTO_WAIT => (7),
+ RXSLIDE_MODE => ("AUTO"),--//("PCS"),
+ RX_SIG_VALID_DLY => (10),
+
+ ------------------RX 8B/10B Decoder Attributes---------------
+ RX_DISPERR_SEQ_MATCH => ("TRUE"),
+ DEC_MCOMMA_DETECT => ("TRUE"),
+ DEC_PCOMMA_DETECT => ("TRUE"),
+ DEC_VALID_COMMA_ONLY => ("FALSE"),
+
+ ------------------------RX Clock Correction Attributes----------------------
+ CBCC_DATA_SOURCE_SEL => ("DECODED"),
+ CLK_COR_SEQ_2_USE => ("FALSE"),
+ CLK_COR_KEEP_IDLE => ("FALSE"),
+ CLK_COR_MAX_LAT => (9),
+ CLK_COR_MIN_LAT => (7),
+ CLK_COR_PRECEDENCE => ("TRUE"),
+ CLK_COR_REPEAT_WAIT => (0),
+ CLK_COR_SEQ_LEN => (1),
+ CLK_COR_SEQ_1_ENABLE => ("1111"),
+ CLK_COR_SEQ_1_1 => ("0100000000"),
+ CLK_COR_SEQ_1_2 => ("0000000000"),
+ CLK_COR_SEQ_1_3 => ("0000000000"),
+ CLK_COR_SEQ_1_4 => ("0000000000"),
+ CLK_CORRECT_USE => ("FALSE"),
+ CLK_COR_SEQ_2_ENABLE => ("1111"),
+ CLK_COR_SEQ_2_1 => ("0100000000"),
+ CLK_COR_SEQ_2_2 => ("0000000000"),
+ CLK_COR_SEQ_2_3 => ("0000000000"),
+ CLK_COR_SEQ_2_4 => ("0000000000"),
+
+ ------------------------RX Channel Bonding Attributes----------------------
+ CHAN_BOND_KEEP_ALIGN => ("FALSE"),
+ CHAN_BOND_MAX_SKEW => (1),
+ CHAN_BOND_SEQ_LEN => (1),
+ CHAN_BOND_SEQ_1_1 => ("0000000000"),
+ CHAN_BOND_SEQ_1_2 => ("0000000000"),
+ CHAN_BOND_SEQ_1_3 => ("0000000000"),
+ CHAN_BOND_SEQ_1_4 => ("0000000000"),
+ CHAN_BOND_SEQ_1_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_1 => ("0000000000"),
+ CHAN_BOND_SEQ_2_2 => ("0000000000"),
+ CHAN_BOND_SEQ_2_3 => ("0000000000"),
+ CHAN_BOND_SEQ_2_4 => ("0000000000"),
+ CHAN_BOND_SEQ_2_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_USE => ("FALSE"),
+ FTS_DESKEW_SEQ_ENABLE => ("1111"),
+ FTS_LANE_DESKEW_CFG => ("1111"),
+ FTS_LANE_DESKEW_EN => ("FALSE"),
+
+ ---------------------------RX Margin Analysis Attributes----------------------------
+ ES_CONTROL => ("000000"),
+ ES_ERRDET_EN => ("FALSE"),
+ ES_EYE_SCAN_EN => ("TRUE"),
+ ES_HORZ_OFFSET => (x"000"),
+ ES_PMA_CFG => ("0000000000"),
+ ES_PRESCALE => ("00000"),
+ ES_QUALIFIER => (x"00000000000000000000"),
+ ES_QUAL_MASK => (x"00000000000000000000"),
+ ES_SDATA_MASK => (x"00000000000000000000"),
+ ES_VERT_OFFSET => ("000000000"),
+
+ -------------------------FPGA RX Interface Attributes-------------------------
+ RX_DATA_WIDTH => (20),
+
+ ---------------------------PMA Attributes----------------------------
+ OUTREFCLK_SEL_INV => ("11"),
+ PMA_RSV => (PMA_RSV_IN),
+ PMA_RSV2 => (x"2040"),
+ PMA_RSV3 => ("00"),
+ PMA_RSV4 => (x"00000000"),
+ RX_BIAS_CFG => ("000000000100"),
+ DMONITOR_CFG => (x"000A00"),
+ RX_CM_SEL => ("00"),
+ RX_CM_TRIM => ("000"),
+ RX_DEBUG_CFG => ("000000000000"),
+ RX_OS_CFG => ("0000010000000"),
+ TERM_RCAL_CFG => ("10000"),
+ TERM_RCAL_OVRD => ('0'),
+ TST_RSV => (x"00000000"),
+ RX_CLK25_DIV => (4),
+ TX_CLK25_DIV => (4),
+ UCODEER_CLR => ('0'),
+
+ ---------------------------PCI Express Attributes----------------------------
+ PCS_PCIE_EN => ("FALSE"),
+
+ ---------------------------PCS Attributes----------------------------
+ PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
+
+ -------------RX Buffer Attributes------------
+ RXBUF_ADDR_MODE => ("FAST"),
+ RXBUF_EIDLE_HI_CNT => ("1000"),
+ RXBUF_EIDLE_LO_CNT => ("0000"),
+ RXBUF_EN => ("FALSE"),
+ RX_BUFFER_CFG => ("000000"),
+ RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
+ RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
+ RXBUF_RESET_ON_EIDLE => ("FALSE"),
+ RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
+ RXBUFRESET_TIME => ("00001"),
+ RXBUF_THRESH_OVFLW => (61),
+ RXBUF_THRESH_OVRD => ("FALSE"),
+ RXBUF_THRESH_UNDFLW => (4),
+ RXDLY_CFG => (x"001F"),
+ RXDLY_LCFG => (x"030"),
+ RXDLY_TAP_CFG => (x"0000"),
+ RXPH_CFG => (x"000000"),
+ RXPHDLY_CFG => (x"084020"),
+ RXPH_MONITOR_SEL => ("00000"),
+ RX_XCLK_SEL => ("RXUSR"),
+ RX_DDI_SEL => ("000000"),
+ RX_DEFER_RESET_BUF_EN => ("TRUE"),
+
+ -----------------------CDR Attributes-------------------------
+
+ --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+ --For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h038C008bff20200010
+ RXCDR_CFG => (x"03000023ff10200020"),
+
+ RXCDR_FR_RESET_ON_EIDLE => ('0'),
+ RXCDR_HOLD_DURING_EIDLE => ('0'),
+ RXCDR_PH_RESET_ON_EIDLE => ('0'),
+ RXCDR_LOCK_CFG => ("010101"),
+
+ -------------------RX Initialization and Reset Attributes-------------------
+ RXCDRFREQRESET_TIME => ("00001"),
+ RXCDRPHRESET_TIME => ("00001"),
+ RXISCANRESET_TIME => ("00001"),
+ RXPCSRESET_TIME => ("00001"),
+ RXPMARESET_TIME => ("00011"),
+
+ -------------------RX OOB Signaling Attributes-------------------
+ RXOOB_CFG => ("0000110"),
+
+ -------------------------RX Gearbox Attributes---------------------------
+ RXGEARBOX_EN => ("FALSE"),
+ GEARBOX_MODE => ("000"),
+
+ -------------------------PRBS Detection Attribute-----------------------
+ RXPRBS_ERR_LOOPBACK => ('0'),
+
+ -------------Power-Down Attributes----------
+ PD_TRANS_TIME_FROM_P2 => (x"03c"),
+ PD_TRANS_TIME_NONE_P2 => (x"3c"),
+ PD_TRANS_TIME_TO_P2 => (x"64"),
+
+ -------------RX OOB Signaling Attributes----------
+ SAS_MAX_COM => (64),
+ SAS_MIN_COM => (36),
+ SATA_BURST_SEQ_LEN => ("1111"),
+ SATA_BURST_VAL => ("100"),
+ SATA_EIDLE_VAL => ("100"),
+ SATA_MAX_BURST => (8),
+ SATA_MAX_INIT => (21),
+ SATA_MAX_WAKE => (7),
+ SATA_MIN_BURST => (4),
+ SATA_MIN_INIT => (12),
+ SATA_MIN_WAKE => (4),
+
+ -------------RX Fabric Clock Output Control Attributes----------
+ TRANS_TIME_RATE => (x"0E"),
+
+ --------------TX Buffer Attributes----------------
+ TXBUF_EN => ("FALSE"),
+ TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
+ TXDLY_CFG => (x"001F"),
+ TXDLY_LCFG => (x"030"),
+ TXDLY_TAP_CFG => (x"0000"),
+ TXPH_CFG => (x"0780"),
+ TXPHDLY_CFG => (x"084020"),
+ TXPH_MONITOR_SEL => ("00000"),
+ TX_XCLK_SEL => ("TXUSR"),
+
+ -------------------------FPGA TX Interface Attributes-------------------------
+ TX_DATA_WIDTH => (20),
+
+ -------------------------TX Configurable Driver Attributes-------------------------
+ TX_DEEMPH0 => ("00000"),
+ TX_DEEMPH1 => ("00000"),
+ TX_EIDLE_ASSERT_DELAY => ("110"),
+ TX_EIDLE_DEASSERT_DELAY => ("100"),
+ TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
+ TX_MAINCURSOR_SEL => ('0'),
+ TX_DRIVE_MODE => ("DIRECT"),
+ TX_MARGIN_FULL_0 => ("1001110"),
+ TX_MARGIN_FULL_1 => ("1001001"),
+ TX_MARGIN_FULL_2 => ("1000101"),
+ TX_MARGIN_FULL_3 => ("1000010"),
+ TX_MARGIN_FULL_4 => ("1000000"),
+ TX_MARGIN_LOW_0 => ("1000110"),
+ TX_MARGIN_LOW_1 => ("1000100"),
+ TX_MARGIN_LOW_2 => ("1000010"),
+ TX_MARGIN_LOW_3 => ("1000000"),
+ TX_MARGIN_LOW_4 => ("1000000"),
+
+ -------------------------TX Gearbox Attributes--------------------------
+ TXGEARBOX_EN => ("FALSE"),
+
+ -------------------------TX Initialization and Reset Attributes--------------------------
+ TXPCSRESET_TIME => ("00001"),
+ TXPMARESET_TIME => ("00001"),
+
+ -------------------------TX Receiver Detection Attributes--------------------------
+ TX_RXDETECT_CFG => (x"1832"),
+ TX_RXDETECT_REF => ("100"),
+
+ ----------------------------CPLL Attributes----------------------------
+ CPLL_CFG => (x"BC07DC"),
+ CPLL_FBDIV => (5),
+ CPLL_FBDIV_45 => (5),
+ CPLL_INIT_CFG => (x"00001E"),
+ CPLL_LOCK_CFG => (x"01E8"),
+ CPLL_REFCLK_DIV => (1),
+ RXOUT_DIV => (2),
+ TXOUT_DIV => (2),
+ SATA_CPLL_CFG => ("VCO_3000MHZ"),
+
+ --------------RX Initialization and Reset Attributes-------------
+ RXDFELPMRESET_TIME => ("0001111"),
+
+ --------------RX Equalizer Attributes-------------
+ RXLPM_HF_CFG => ("00000011110000"),
+ RXLPM_LF_CFG => ("00000011110000"),
+ RX_DFE_GAIN_CFG => (x"020FEA"),
+ RX_DFE_H2_CFG => ("000000000000"),
+ RX_DFE_H3_CFG => ("000001000000"),
+ RX_DFE_H4_CFG => ("00011110000"),
+ RX_DFE_H5_CFG => ("00011100000"),
+ RX_DFE_KL_CFG => ("0000011111110"),
+ RX_DFE_LPM_CFG => (x"0904"),
+ RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
+ RX_DFE_UT_CFG => ("10001111000000000"),
+ RX_DFE_VP_CFG => ("00011111100000011"),
+
+ -------------------------Power-Down Attributes-------------------------
+ RX_CLKMUX_PD => ('1'),
+ TX_CLKMUX_PD => ('1'),
+
+ -------------------------FPGA RX Interface Attribute-------------------------
+ RX_INT_DATAWIDTH => (0),
+
+ -------------------------FPGA TX Interface Attribute-------------------------
+ TX_INT_DATAWIDTH => (0),
+
+ ------------------TX Configurable Driver Attributes---------------
+ TX_QPI_STATUS_EN => ('0'),
+
+ -------------------------RX Equalizer Attributes--------------------------
+ RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
+ RX_DFE_XYD_CFG => ("0000000000000"),
+
+ -------------------------TX Configurable Driver Attributes--------------------------
+ TX_PREDRIVER_MODE => ('0')
+
+
+ )
+ port map
+ (
+ --------------------------------- CPLL Ports -------------------------------
+ CPLLFBCLKLOST => CPLLFBCLKLOST_OUT,
+ CPLLLOCK => CPLLLOCK_OUT,
+ CPLLLOCKDETCLK => CPLLLOCKDETCLK_IN,
+ CPLLLOCKEN => tied_to_vcc_i,
+ CPLLPD => tied_to_ground_i,
+ CPLLREFCLKLOST => CPLLREFCLKLOST_OUT,
+ CPLLREFCLKSEL => "001",
+ CPLLRESET => CPLLRESET_IN,
+ GTRSVD => "0000000000000000",
+ PCSRSVDIN => "0000000000000000",
+ PCSRSVDIN2 => "00000",
+ PMARSVDIN => "00000",
+ PMARSVDIN2 => "00000",
+ TSTIN => "11111111111111111111",
+ TSTOUT => open,
+ ---------------------------------- Channel ---------------------------------
+ CLKRSVD => "0000",
+ -------------------------- Channel - Clocking Ports ------------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GTREFCLK0_IN,
+ GTREFCLK1 => tied_to_ground_i,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ DRPADDR => DRPADDR_IN,
+ DRPCLK => DRPCLK_IN,
+ DRPDI => DRPDI_IN,
+ DRPDO => DRPDO_OUT,
+ DRPEN => DRPEN_IN,
+ DRPRDY => DRPRDY_OUT,
+ DRPWE => DRPWE_IN,
+ ------------------------------- Clocking Ports -----------------------------
+ GTREFCLKMONITOR => open,
+ QPLLCLK => QPLLCLK_IN,
+ QPLLREFCLK => QPLLREFCLK_IN,
+ RXSYSCLKSEL => "00",
+ TXSYSCLKSEL => "00",
+ --------------------------- Digital Monitor Ports --------------------------
+ DMONITOROUT => open,
+ ----------------- FPGA TX Interface Datapath Configuration ----------------
+ TX8B10BEN => tied_to_vcc_i,
+ ------------------------------- Loopback Ports -----------------------------
+ LOOPBACK => tied_to_ground_vec_i(2 downto 0),
+ ----------------------------- PCI Express Ports ----------------------------
+ PHYSTATUS => open,
+ RXRATE => tied_to_ground_vec_i(2 downto 0),
+ RXVALID => open,
+ ------------------------------ Power-Down Ports ----------------------------
+ RXPD => "00",
+ TXPD => "00",
+ -------------------------- RX 8B/10B Decoder Ports -------------------------
+ SETERRSTATUS => tied_to_ground_i,
+ --------------------- RX Initialization and Reset Ports --------------------
+ EYESCANRESET => tied_to_ground_i,
+ RXUSERRDY => RXUSERRDY_IN,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ EYESCANDATAERROR => EYESCANDATAERROR_OUT,
+ EYESCANMODE => tied_to_ground_i,
+ EYESCANTRIGGER => tied_to_ground_i,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRFREQRESET => tied_to_ground_i,
+ RXCDRHOLD => tied_to_ground_i,
+ RXCDRLOCK => RXCDRLOCK_OUT,
+ RXCDROVRDEN => tied_to_ground_i,
+ RXCDRRESET => RXCDRRESET_IN, --// tied_to_ground_i,
+ RXCDRRESETRSV => tied_to_ground_i,
+ ------------------- Receive Ports - Clock Correction Ports -----------------
+ RXCLKCORCNT => open,
+ ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+ RX8B10BEN => tied_to_vcc_i,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ RXUSRCLK => RXUSRCLK_IN,
+ RXUSRCLK2 => RXUSRCLK2_IN,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ RXDATA => rxdata_i,
+ ------------------- Receive Ports - Pattern Checker Ports ------------------
+ RXPRBSERR => open,
+ RXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
+ ------------------- Receive Ports - Pattern Checker ports ------------------
+ RXPRBSCNTRESET => tied_to_ground_i,
+ -------------------- Receive Ports - RX Equalizer Ports -------------------
+ RXDFEXYDEN => tied_to_ground_i,
+ RXDFEXYDHOLD => tied_to_ground_i,
+ RXDFEXYDOVRDEN => tied_to_ground_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ RXDISPERR(7 downto 2) => rxdisperr_float_i,
+ RXDISPERR(1 downto 0) => RXDISPERR_OUT,
+ RXNOTINTABLE(7 downto 2) => rxnotintable_float_i,
+ RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GTXRXP => GTXRXP_IN,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GTXRXN => GTXRXN_IN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ RXBUFRESET => tied_to_ground_i,
+ RXBUFSTATUS => open,
+ RXDDIEN => tied_to_vcc_i,
+ RXDLYBYPASS => tied_to_ground_i,
+ RXDLYEN => RXDLYEN_IN,
+ RXDLYOVRDEN => tied_to_ground_i,
+ RXDLYSRESET => RXDLYSRESET_IN,
+ RXDLYSRESETDONE => RXDLYSRESETDONE_OUT,
+ RXPHALIGN => RXPHALIGN_IN,
+ RXPHALIGNDONE => RXPHALIGNDONE_OUT,
+ RXPHALIGNEN => RXPHALIGNEN_IN,
+ RXPHDLYPD => tied_to_ground_i,
+ RXPHDLYRESET => RXPHDLYRESET_IN,
+ RXPHMONITOR => RXPHMONITOR_OUT,
+ RXPHOVRDEN => tied_to_ground_i,
+ RXPHSLIPMONITOR => RXPHSLIPMONITOR_OUT,
+ RXSTATUS => open,
+ -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+ RXBYTEISALIGNED => open,
+ RXBYTEREALIGN => open,
+ RXCOMMADET => open,
+ RXCOMMADETEN => tied_to_vcc_i,
+ RXMCOMMAALIGNEN => tied_to_vcc_i,
+ RXPCOMMAALIGNEN => tied_to_vcc_i,
+ ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+ RXCHANBONDSEQ => open,
+ RXCHBONDEN => tied_to_ground_i,
+ RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
+ RXCHBONDMASTER => tied_to_ground_i,
+ RXCHBONDO => open,
+ RXCHBONDSLAVE => tied_to_ground_i,
+ ----------------- Receive Ports - RX Channel Bonding Ports ----------------
+ RXCHANISALIGNED => open,
+ RXCHANREALIGN => open,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ RXLPMHFHOLD => RXLPMHFHOLD_IN,
+ RXLPMHFOVRDEN => tied_to_ground_i,
+ RXLPMLFHOLD => RXLPMLFHOLD_IN,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ RXDFEAGCHOLD => tied_to_ground_i,
+ RXDFEAGCOVRDEN => tied_to_ground_i,
+ RXDFECM1EN => tied_to_ground_i,
+ RXDFELFHOLD => tied_to_ground_i,
+ RXDFELFOVRDEN => tied_to_ground_i,
+ RXDFELPMRESET => tied_to_ground_i,
+ RXDFETAP2HOLD => tied_to_ground_i,
+ RXDFETAP2OVRDEN => tied_to_ground_i,
+ RXDFETAP3HOLD => tied_to_ground_i,
+ RXDFETAP3OVRDEN => tied_to_ground_i,
+ RXDFETAP4HOLD => tied_to_ground_i,
+ RXDFETAP4OVRDEN => tied_to_ground_i,
+ RXDFETAP5HOLD => tied_to_ground_i,
+ RXDFETAP5OVRDEN => tied_to_ground_i,
+ RXDFEUTHOLD => tied_to_ground_i,
+ RXDFEUTOVRDEN => tied_to_ground_i,
+ RXDFEVPHOLD => tied_to_ground_i,
+ RXDFEVPOVRDEN => tied_to_ground_i,
+ RXDFEVSEN => tied_to_ground_i,
+ RXLPMLFKLOVRDEN => tied_to_ground_i,
+ RXMONITOROUT => open,
+ RXMONITORSEL => "00",
+ RXOSHOLD => tied_to_ground_i,
+ RXOSOVRDEN => tied_to_ground_i,
+ ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+ RXRATEDONE => open,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ RXOUTCLK => RXOUTCLK_OUT,
+ RXOUTCLKFABRIC => open,
+ RXOUTCLKPCS => open,
+ RXOUTCLKSEL => "010",
+ ---------------------- Receive Ports - RX Gearbox Ports --------------------
+ RXDATAVALID => open,
+ RXHEADER => open,
+ RXHEADERVALID => open,
+ RXSTARTOFSEQ => open,
+ --------------------- Receive Ports - RX Gearbox Ports --------------------
+ RXGEARBOXSLIP => tied_to_ground_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GTRXRESET => GTRXRESET_IN,
+ RXOOBRESET => tied_to_ground_i,
+ RXPCSRESET => RXPCSRESET_IN,
+ RXPMARESET => RXPMARESET_IN,
+ ------------------ Receive Ports - RX Margin Analysis ports ----------------
+ RXLPMEN => tied_to_vcc_i,
+ ------------------- Receive Ports - RX OOB Signaling ports -----------------
+ RXCOMSASDET => open,
+ RXCOMWAKEDET => open,
+ ------------------ Receive Ports - RX OOB Signaling ports -----------------
+ RXCOMINITDET => open,
+ ------------------ Receive Ports - RX OOB signalling Ports -----------------
+ RXELECIDLE => open,
+ RXELECIDLEMODE => "11",
+ ----------------- Receive Ports - RX Polarity Control Ports ----------------
+ RXPOLARITY => tied_to_ground_i,
+ ---------------------- Receive Ports - RX gearbox ports --------------------
+ RXSLIDE => tied_to_ground_i,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ RXCHARISCOMMA => open,
+ RXCHARISK(7 downto 2) => rxcharisk_float_i,
+ RXCHARISK(1 downto 0) => RXCHARISK_OUT,
+ ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+ RXCHBONDI => "00000",
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ RXRESETDONE => RXRESETDONE_OUT,
+ -------------------------------- Rx AFE Ports ------------------------------
+ RXQPIEN => tied_to_ground_i,
+ RXQPISENN => open,
+ RXQPISENP => open,
+ --------------------------- TX Buffer Bypass Ports -------------------------
+ TXPHDLYTSTCLK => tied_to_ground_i,
+ ------------------------ TX Configurable Driver Ports ----------------------
+ TXPOSTCURSOR => "00000",
+ TXPOSTCURSORINV => tied_to_ground_i,
+ TXPRECURSOR => tied_to_ground_vec_i(4 downto 0),
+ TXPRECURSORINV => tied_to_ground_i,
+ TXQPIBIASEN => tied_to_ground_i,
+ TXQPISTRONGPDOWN => tied_to_ground_i,
+ TXQPIWEAKPUP => tied_to_ground_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ CFGRESET => tied_to_ground_i,
+ GTTXRESET => GTTXRESET_IN,
+ PCSRSVDOUT => open,
+ TXUSERRDY => TXUSERRDY_IN,
+ ---------------------- Transceiver Reset Mode Operation --------------------
+ GTRESETSEL => tied_to_ground_i,
+ RESETOVRD => tied_to_ground_i,
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ TXCHARDISPMODE => tied_to_ground_vec_i(7 downto 0),
+ TXCHARDISPVAL => tied_to_ground_vec_i(7 downto 0),
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ TXUSRCLK => TXUSRCLK_IN,
+ TXUSRCLK2 => TXUSRCLK2_IN,
+ --------------------- Transmit Ports - PCI Express Ports -------------------
+ TXELECIDLE => tied_to_ground_i,
+ TXMARGIN => tied_to_ground_vec_i(2 downto 0),
+ TXRATE => tied_to_ground_vec_i(2 downto 0),
+ TXSWING => tied_to_ground_i,
+ ------------------ Transmit Ports - Pattern Generator Ports ----------------
+ TXPRBSFORCEERR => tied_to_ground_i,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ TXDLYBYPASS => tied_to_ground_i,
+ TXDLYEN => TXDLYEN_IN,
+ TXDLYHOLD => tied_to_ground_i,
+ TXDLYOVRDEN => tied_to_ground_i,
+ TXDLYSRESET => TXDLYSRESET_IN,
+ TXDLYSRESETDONE => TXDLYSRESETDONE_OUT,
+ TXDLYUPDOWN => tied_to_ground_i,
+ TXPHALIGN => TXPHALIGN_IN,
+ TXPHALIGNDONE => TXPHALIGNDONE_OUT,
+ TXPHALIGNEN => TXPHALIGNEN_IN,
+ TXPHDLYPD => tied_to_ground_i,
+ TXPHDLYRESET => TXPHDLYRESET_IN,
+ TXPHINIT => TXPHINIT_IN,
+ TXPHINITDONE => TXPHINITDONE_OUT,
+ TXPHOVRDEN => tied_to_ground_i,
+ ---------------------- Transmit Ports - TX Buffer Ports --------------------
+ TXBUFSTATUS => open,
+ --------------- Transmit Ports - TX Configurable Driver Ports --------------
+ TXBUFDIFFCTRL => "100",
+ TXDEEMPH => tied_to_ground_i,
+ TXDIFFCTRL => "1000",
+ TXDIFFPD => tied_to_ground_i,
+ TXINHIBIT => tied_to_ground_i,
+ TXMAINCURSOR => "0000000",
+ TXPISOPD => tied_to_ground_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA => txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTXTXN => GTXTXN_OUT,
+ GTXTXP => GTXTXP_OUT,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ TXOUTCLK => TXOUTCLK_OUT,
+ TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT,
+ TXOUTCLKPCS => TXOUTCLKPCS_OUT,
+ TXOUTCLKSEL => "011",
+ TXRATEDONE => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ TXCHARISK(7 downto 2) => tied_to_ground_vec_i(5 downto 0),
+ TXCHARISK(1 downto 0) => TXCHARISK_IN,
+ TXGEARBOXREADY => open,
+ TXHEADER => tied_to_ground_vec_i(2 downto 0),
+ TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
+ TXSTARTSEQ => tied_to_ground_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ TXPCSRESET => tied_to_ground_i,
+ TXPMARESET => tied_to_ground_i,
+ TXRESETDONE => TXRESETDONE_OUT,
+ ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+ TXCOMFINISH => open,
+ TXCOMINIT => tied_to_ground_i,
+ TXCOMSAS => tied_to_ground_i,
+ TXCOMWAKE => tied_to_ground_i,
+ TXPDELECIDLEMODE => tied_to_ground_i,
+ ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+ TXPOLARITY => tied_to_ground_i,
+ --------------- Transmit Ports - TX Receiver Detection Ports --------------
+ TXDETECTRX => tied_to_ground_i,
+ ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+ TX8B10BBYPASS => tied_to_ground_vec_i(7 downto 0),
+ ------------------ Transmit Ports - pattern Generator Ports ----------------
+ TXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
+ ----------------------- Tx Configurable Driver Ports ----------------------
+ TXQPISENN => open,
+ TXQPISENP => open
+
+ );
+
+ end RTL;
+
+
+
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2.6
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtxkintex7fee80_rx_manual_phase_align.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+-- Description : This module performs RX Buffer Phase Alignment in Manual Mode.
+--
+--
+--
+-- Module gtxKintex7FEE80_rx_manual_phase_align
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN is
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ RXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN;
+
+architecture RTL of gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN is
+
+ component gtxKintex7FEE80_sync_block
+ generic (
+ INITIALISE : bit_vector(1 downto 0) := "00"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ constant VCC_VEC : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '1');
+ constant GND_VEC : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+
+ type rx_phase_align_manual_fsm is(
+ INIT, WAIT_DLYRST_DONE, M_PHALIGN, M_DLYEN,
+ S_PHALIGN, M_DLYEN2, PHALIGN_DONE
+ );
+ signal rx_phalign_manual_state : rx_phase_align_manual_fsm := INIT;
+ signal rxphaligndone_prev : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal rxphaligndone_ris_edge : std_logic_vector(NUMBER_OF_LANES-1 downto 0);
+
+ signal rxdlysresetdone_store : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal rxphaligndone_store : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal rxdone_clear : std_logic := '0';
+
+ signal rxphaligndone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal rxdlysresetdone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+
+
+begin
+
+ cdc: for i in 0 to NUMBER_OF_LANES-1 generate
+ sync_RXPHALIGNDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => RXPHALIGNDONE(i),
+ data_out => rxphaligndone_sync(i)
+ );
+
+ sync_RXDLYSRESETDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => RXDLYSRESETDONE(i),
+ data_out => rxdlysresetdone_sync(i)
+ );
+
+ end generate;
+
+
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ rxphaligndone_prev <= rxphaligndone_sync;
+ end if;
+ end process;
+
+ edge_detect: for i in 0 to NUMBER_OF_LANES-1 generate
+ rxphaligndone_ris_edge(i) <= '1' when (rxphaligndone_prev(i) = '0') and (rxphaligndone_sync(i) = '1') else '0';
+ end generate;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if rxdone_clear = '1' then
+ rxdlysresetdone_store <= (others=>'0');
+ rxphaligndone_store <= (others=>'0');
+ else
+ for i in 0 to NUMBER_OF_LANES-1 loop
+ if rxdlysresetdone_sync(i) = '1' then
+ rxdlysresetdone_store(i) <= '1';
+ end if;
+ if rxphaligndone_ris_edge(i) = '1' then
+ rxphaligndone_store(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end process;
+
+
+
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if RESET_PHALIGNMENT = '1' then
+ PHASE_ALIGNMENT_DONE <= '0';
+ RXDLYSRESET <= (others => '0');
+ RXPHALIGN <= (others => '0');
+ RXDLYEN <= (others => '0');
+ rx_phalign_manual_state <= INIT;
+ rxdone_clear <= '1';
+ else
+ case rx_phalign_manual_state is
+ when INIT =>
+ PHASE_ALIGNMENT_DONE <= '0';
+ rxdone_clear <= '1';
+
+ if RUN_PHALIGNMENT = '1' then
+ --Assert RXDLYSRESET for all lanes.
+ rxdone_clear <= '0';
+ RXDLYSRESET <= (others => '1');
+ rx_phalign_manual_state <= WAIT_DLYRST_DONE;
+ end if;
+
+ when WAIT_DLYRST_DONE =>
+ for i in 0 to NUMBER_OF_LANES - 1 loop
+ --if RXDLYSRESETDONE(i) = '1' then
+ if rxdlysresetdone_store(i) = '1' then
+ --Hold RXDLYSRESET High until RXDLYSRESETDONE of the
+ --respective lane is asserted.
+ --Deassert RXDLYSRESET for the lane in which the
+ --RXDLYSRESETDONE is asserted.
+ RXDLYSRESET(i) <= '0';
+ end if;
+ end loop;
+ if rxdlysresetdone_store = VCC_VEC then
+ rx_phalign_manual_state <= M_PHALIGN;
+ end if;
+
+ when M_PHALIGN =>
+ --When RXDLYSRESET of all lanes are deasserted, assert
+ --RXPHALIGN for the master lane.
+ RXPHALIGN(MASTER_LANE_ID) <= '1';
+ if rxphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+ --Hold this signal High until a rising edge on RXPHALIGNDONE
+ --of the master lane is detected, then deassert RXPHALIGN for
+ --the master lane.
+ RXPHALIGN(MASTER_LANE_ID) <= '0';
+ rx_phalign_manual_state <= M_DLYEN;
+ end if;
+
+ when M_DLYEN =>
+ --Assert RXDLYEN for the master lane. This causes RXPHALIGNDONE
+ --to be deasserted.
+ RXDLYEN(MASTER_LANE_ID) <= '1';
+ if rxphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+ --Hold RXDLYEN for the master lane High until a rising edge on
+ --RXPHALIGNDONE of the master lane is detected, then deassert
+ --RXDLYEN for the master lane.
+ RXDLYEN(MASTER_LANE_ID) <= '0';
+ rx_phalign_manual_state <= S_PHALIGN;
+ end if;
+
+ when S_PHALIGN =>
+ --Assert RXPHALIGN for all slave lane(s). Hold this signal High until
+ --a rising edge on RXPHALIGNDONE of the respective slave lane is detected.
+ RXPHALIGN <= (others=>'1');--\Assert only the PHALIGN signal of
+ RXPHALIGN(MASTER_LANE_ID) <= '0'; --/the slaves.
+ for i in 0 to NUMBER_OF_LANES - 1 loop
+ if rxphaligndone_store(i) = '1' then
+ --When a rising edge on the respective lane is detected, RXPHALIGN
+ --of that lane is deasserted.
+ RXPHALIGN(i) <= '0';
+ end if;
+ end loop;
+ --The reason for checking of the occurance of at least one rising edge
+ --is to avoid the potential direct move where RXPHALIGNDONE might not
+ --be going low fast enough.
+ --if rxphaligndone_store = VCC_VEC and rxphaligndone_ris_edge /= GND_VEC then
+ if rxphaligndone_store = VCC_VEC then
+ rx_phalign_manual_state <= M_DLYEN2;
+ end if;
+
+ when M_DLYEN2 =>
+ --When RXPHALIGN for all slave lane(s) are deasserted, assert RXDLYEN
+ --for the master lane. This causes RXPHALIGNDONE of the master lane
+ --to be deasserted.
+ RXDLYEN(MASTER_LANE_ID) <= '1';
+ if rxphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+ --Wait until RXPHALIGNDONE of the master lane reasserts. Phase and
+ --delay alignment for the multilane interface is complete.
+ rx_phalign_manual_state <= PHALIGN_DONE;
+ end if;
+
+ when PHALIGN_DONE =>
+ --Continue to hold RXDLYEN for the master lane High to adjust RXUSRCLK
+ --to compensate for temperature and voltage variations.
+ RXDLYEN(MASTER_LANE_ID) <= '1';
+ PHASE_ALIGNMENT_DONE <= '1';
+
+ when OTHERS =>
+ rx_phalign_manual_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
+
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2.6
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtxkintex7fee80_rx_startup_fsm.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+-- Description : This module performs RX reset and initialization.
+--
+--
+--
+-- Module gtxKintex7FEE80_rx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_RX_STARTUP_FSM is
+ Generic( EXAMPLE_SIMULATION : integer := 0;
+ GT_TYPE : string := "GTX";
+ EQ_MODE : string := "DFE"; --RX Equalisation Mode; set to DFE or LPM
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ RXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ RECCLK_STABLE : in STD_LOGIC;
+ RECCLK_MONITOR_RESTART : in STD_LOGIC:='0';
+ DATA_VALID : in STD_LOGIC;
+ TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
+ DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; --Used to control the Auto-Reset of FSM when Data Error is detected
+ GTRXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='1';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
+ RX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
+ RXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC;
+ PHALIGNMENT_DONE : in STD_LOGIC;
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ RXDFEAGCHOLD : out STD_LOGIC;
+ RXDFELFHOLD : out STD_LOGIC;
+ RXLPMLFHOLD : out STD_LOGIC;
+ RXLPMHFHOLD : out STD_LOGIC;
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end gtxKintex7FEE80_RX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+-- are calculated at design-time based on the Generics
+--
+-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
+-- => signal which PLL has been reset
+-- *
+
+
+
+architecture RTL of gtxKintex7FEE80_RX_STARTUP_FSM is
+
+ component gtxKintex7FEE80_sync_block
+ generic (
+ INITIALISE : bit_vector(1 downto 0) := "00"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+
+ type rx_rst_fsm_type is(
+ INIT, ASSERT_ALL_RESETS, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
+ RELEASE_MMCM_RESET, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+ MONITOR_DATA_VALID, FSM_DONE);
+
+ signal rx_state : rx_rst_fsm_type := INIT;
+
+ constant MMCM_LOCK_CNT_MAX : integer := 1024;
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+ constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
+ constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--500 us time-out
+ constant WAIT_TIMEOUT_1us : integer := 1000 / STABLE_CLOCK_PERIOD; --1 us time-out
+ constant WAIT_TIMEOUT_100us : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
+ constant WAIT_TIME_ADAPT : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD;
+
+ signal init_wait_count : integer range 0 to WAIT_MAX:=0;
+ signal init_wait_done : std_logic := '0';
+ signal pll_reset_asserted : std_logic := '0';
+ signal rx_fsm_reset_done_int : std_logic := '0';
+ signal rx_fsm_reset_done_int_s2 : std_logic := '0';
+ signal rx_fsm_reset_done_int_s3 : std_logic := '0';
+
+ signal rxresetdone_s2 : std_logic := '0';
+ signal rxresetdone_s3 : std_logic := '0';
+
+ constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
+ signal retry_counter_int : integer range 0 to MAX_RETRIES := 0;
+ signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+ signal recclk_mon_restart_count : integer range 0 to 3:= 0;
+ signal recclk_mon_count_reset : std_logic := '0';
+
+ signal reset_time_out : std_logic := '0';
+ signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
+ signal time_tlock_max : std_logic := '0';--|have been reached.
+ signal time_out_500us : std_logic := '0';--|
+ signal time_out_1us : std_logic := '0';--/
+ signal time_out_100us : std_logic := '0';--/
+ signal check_tlock_max : std_logic := '0';
+
+ signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+ signal mmcm_lock_int : std_logic := '0';
+ signal mmcm_lock_reclocked : std_logic := '0';
+
+ signal run_phase_alignment_int: std_logic := '0';
+ signal run_phase_alignment_int_s2 : std_logic := '0';
+ signal run_phase_alignment_int_s3 : std_logic := '0';
+
+ constant MAX_WAIT_BYPASS : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
+ signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
+ signal time_out_wait_bypass : std_logic := '0';
+ signal time_out_wait_bypass_s2 : std_logic := '0';
+ signal time_out_wait_bypass_s3 : std_logic := '0';
+
+ signal refclk_lost : std_logic;
+
+ signal time_out_adapt : std_logic := '0';
+ signal adapt_count_reset : std_logic := '0';
+ signal adapt_count : integer range 0 to WAIT_TIME_ADAPT-1;
+
+ signal data_valid_sync: std_logic := '0';
+
+ signal cplllock_sync: std_logic := '0';
+ signal qplllock_sync: std_logic := '0';
+ signal cplllock_prev: std_logic := '0';
+ signal qplllock_prev: std_logic := '0';
+ signal cplllock_ris_edge: std_logic := '0';
+ signal qplllock_ris_edge: std_logic := '0';
+
+begin
+ --Alias section, signals used within this module mapped to output ports:
+ RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+ RUN_PHALIGNMENT <= run_phase_alignment_int;
+ RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+
+ adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
+ time_out_adapt <= '1';
+ end generate;
+
+ adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(adapt_count_reset = '1') then
+ adapt_count <= 0;
+ time_out_adapt <= '0';
+ elsif(adapt_count = WAIT_TIME_ADAPT -1) then
+ time_out_adapt <= '1';
+ else
+ adapt_count <= adapt_count + 1;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ retries_recclk_monitor:process(STABLE_CLOCK)
+ begin
+ --This counter monitors, how many retries the RECCLK monitor
+ --runs. If during startup too many retries are necessary, the whole
+ --initialisation-process of the transceivers gets restarted.
+ if rising_edge(STABLE_CLOCK) then
+ if recclk_mon_count_reset = '1' then
+ recclk_mon_restart_count <= 0;
+ elsif RECCLK_MONITOR_RESTART = '1' then
+ if recclk_mon_restart_count = 3 then
+ recclk_mon_restart_count <= 0;
+ else
+ recclk_mon_restart_count <= recclk_mon_restart_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ timeouts:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- One common large counter for generating three time-out signals.
+ -- Intermediate time-outs are derived from calculated values, based
+ -- on the period of the provided clock.
+ if reset_time_out = '1' then
+ time_out_counter <= 0;
+ time_out_2ms <= '0';
+ time_tlock_max <= '0';
+ time_out_500us <= '0';
+ time_out_1us <= '0';
+ time_out_100us <= '0';
+ else
+ if time_out_counter = WAIT_TIMEOUT_2ms then
+ time_out_2ms <= '1';
+ else
+ time_out_counter <= time_out_counter + 1;
+ end if;
+
+ if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
+ time_tlock_max <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_500us then
+ time_out_500us <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_1us then
+ time_out_1us <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_100us then
+ time_out_100us <= '1';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+
+ mmcm_lock_wait:process(RXUSERCLK)
+ begin
+ --The lock-signal from the MMCM is not immediately used but
+ --enabling a counter. Only when the counter hits its maximum,
+ --the MMCM is considered as "really" locked.
+ --The counter avoids that the FSM already starts on only a
+ --coarse lock of the MMCM (=toggling of the LOCK-signal).
+ if rising_edge(RXUSERCLK) then
+ if MMCM_LOCK = '0' then
+ mmcm_lock_count <= 0;
+ mmcm_lock_int <= '0';
+ else
+ if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+ mmcm_lock_count <= mmcm_lock_count + 1;
+ else
+ mmcm_lock_int <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ -- Clock Domain Crossing
+
+ sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => RXUSERCLK,
+ data_in => run_phase_alignment_int,
+ data_out => run_phase_alignment_int_s2
+ );
+
+ sync_rx_fsm_reset_done_int : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => RXUSERCLK,
+ data_in => rx_fsm_reset_done_int,
+ data_out => rx_fsm_reset_done_int_s2
+ );
+
+ process(RXUSERCLK)
+ begin
+ if rising_edge(RXUSERCLK) then
+ run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
+
+ rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2;
+ end if;
+ end process;
+
+ sync_RXRESETDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => RXRESETDONE,
+ data_out => rxresetdone_s2
+ );
+
+ sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => time_out_wait_bypass,
+ data_out => time_out_wait_bypass_s2
+ );
+
+ sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => mmcm_lock_int,
+ data_out => mmcm_lock_reclocked
+ );
+
+ sync_data_valid : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => DATA_VALID,
+ data_out => data_valid_sync
+ );
+
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ rxresetdone_s3 <= rxresetdone_s2;
+
+ time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
+ cplllock_prev <= cplllock_sync;
+ qplllock_prev <= qplllock_sync;
+ end if;
+ end process;
+
+ sync_CPLLLOCK : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => CPLLLOCK,
+ data_out => cplllock_sync
+ );
+
+ sync_QPLLLOCK : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => QPLLLOCK,
+ data_out => qplllock_sync
+ );
+
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ cplllock_ris_edge <= '0';
+ elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+ cplllock_ris_edge <= '1';
+ elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+ cplllock_ris_edge <= cplllock_ris_edge;
+ else
+ cplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ qplllock_ris_edge <= '0';
+ elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+ qplllock_ris_edge <= '1';
+ elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+ qplllock_ris_edge <= qplllock_ris_edge;
+ else
+ qplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+
+
+ timeout_buffer_bypass:process(RXUSERCLK)
+ begin
+ if rising_edge(RXUSERCLK) then
+ if run_phase_alignment_int_s3 = '0' then
+ wait_bypass_count <= 0;
+ time_out_wait_bypass <= '0';
+ elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
+ if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+ time_out_wait_bypass <= '1';
+ else
+ wait_bypass_count <= wait_bypass_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+
+ --FSM for resetting the GTX/GTH/GTP in the 7-series.
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ --
+ -- Following steps are performed:
+ -- 1) After configuration wait for approximately 500 ns as specified in
+ -- answer-record 43482
+ -- 2) Assert all resets on the GT and on an MMCM potentially connected.
+ -- After that wait until a reference-clock has been detected.
+ -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+ -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+ -- Also get info from the TX-side which PLL has been reset.
+ -- 5) Wait for the RESET_DONE-signal from the GT.
+ -- 6) Signal to start the phase-alignment procedure and wait for it to
+ -- finish.
+ -- 7) Reset-sequence has successfully run through. Signal this to the
+ -- rest of the design by asserting RX_FSM_RESET_DONE.
+
+ reset_fsm:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+ rx_state <= INIT;
+ RXUSERRDY <= '0';
+ GTRXRESET <= '0';
+ MMCM_RESET <= '1';
+ rx_fsm_reset_done_int <= '0';
+ QPLL_RESET <= '0';
+ CPLL_RESET <= '0';
+ pll_reset_asserted <= '0';
+ reset_time_out <= '1';
+ retry_counter_int <= 0;
+ run_phase_alignment_int <= '0';
+ check_tlock_max <= '0';
+ RESET_PHALIGNMENT <= '1';
+ recclk_mon_count_reset <= '1';
+ adapt_count_reset <= '1';
+ RXDFEAGCHOLD <= '0';
+ RXDFELFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ RXLPMHFHOLD <= '0';
+
+ else
+
+ case rx_state is
+ when INIT =>
+ --Initial state after configuration. This state will be left after
+ --approx. 500 ns and not be re-entered.
+ if init_wait_done = '1' then
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when ASSERT_ALL_RESETS =>
+ --This is the state into which the FSM will always jump back if any
+ --time-outs will occur.
+ --The number of retries is reported on the output RETRY_COUNTER. In
+ --case the transceiver never comes up for some reason, this machine
+ --will still continue its best and rerun until the FPGA is turned off
+ --or the transceivers come up correctly.
+ if RX_QPLL_USED and not TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ QPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ QPLL_RESET <= '0';
+ end if;
+ elsif not RX_QPLL_USED and TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ CPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ CPLL_RESET <= '0';
+ end if;
+ end if;
+
+ RXUSERRDY <= '0';
+ GTRXRESET <= '1';
+ MMCM_RESET <= '1';
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+ check_tlock_max <= '0';
+ recclk_mon_count_reset <= '1';
+ adapt_count_reset <= '1';
+
+
+ if (RX_QPLL_USED and not TX_QPLL_USED and (QPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or
+ (not RX_QPLL_USED and TX_QPLL_USED and (CPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or
+ (not RX_QPLL_USED and not TX_QPLL_USED and (CPLLREFCLKLOST = '0') ) or
+ (RX_QPLL_USED and TX_QPLL_USED and (QPLLREFCLKLOST = '0') ) then
+ rx_state <= RELEASE_PLL_RESET;
+ reset_time_out <= '1';
+ end if;
+
+ when RELEASE_PLL_RESET =>
+ --PLL-Reset of the GTX gets released and the time-out counter
+ --starts running.
+ pll_reset_asserted <= '0';
+ reset_time_out <= '0';
+
+
+ if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_ris_edge = '1')) or
+ (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_ris_edge = '1')) then
+ rx_state <= VERIFY_RECCLK_STABLE;
+ reset_time_out <= '1';
+ recclk_mon_count_reset <= '0';
+ adapt_count_reset <= '0';
+
+ elsif (RX_QPLL_USED and (qplllock_sync = '1')) or
+ (not RX_QPLL_USED and (cplllock_sync = '1')) then
+ rx_state <= VERIFY_RECCLK_STABLE;
+ reset_time_out <= '1';
+ recclk_mon_count_reset <= '0';
+ adapt_count_reset <= '0';
+ end if;
+
+ if time_out_2ms = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when VERIFY_RECCLK_STABLE =>
+ --reset_time_out <= '0';
+ --Time-out counter is not released in this state as here the FSM
+ --does not wait for a certain period of time but checks on the number
+ --of retries in the RECCLK monitor
+ GTRXRESET <= '0';
+ if RECCLK_STABLE = '1' then
+ rx_state <= RELEASE_MMCM_RESET;
+ reset_time_out <= '1';
+
+ end if;
+
+ if recclk_mon_restart_count = 2 then
+ --If two retries are performed in the RECCLK monitor
+ --the whole initialisation-sequence gets restarted.
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when RELEASE_MMCM_RESET =>
+ --Release of the MMCM-reset. Waiting for the MMCM to lock.
+ reset_time_out <= '0';
+ check_tlock_max <= '1';
+
+ MMCM_RESET <= '0';
+ if mmcm_lock_reclocked = '1' then
+ rx_state <= WAIT_RESET_DONE;
+ reset_time_out <= '1';
+ end if;
+
+ if time_tlock_max = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_RESET_DONE =>
+ --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
+ --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
+ if TXUSERRDY = '1' then
+ RXUSERRDY <= '1';
+ end if;
+ reset_time_out <= '0';
+ if rxresetdone_s3 = '1' then
+ rx_state <= DO_PHASE_ALIGNMENT;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_2ms = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when DO_PHASE_ALIGNMENT =>
+ --The direct handling of the signals for the Phase Alignment is done outside
+ --this state-machine.
+ RESET_PHALIGNMENT <= '0';
+ run_phase_alignment_int <= '1';
+ reset_time_out <= '0';
+
+ if PHALIGNMENT_DONE = '1' then
+ rx_state <= MONITOR_DATA_VALID;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_wait_bypass_s3 = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when MONITOR_DATA_VALID =>
+ reset_time_out <= '0';
+
+ if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0') then
+ rx_state <= ASSERT_ALL_RESETS;
+ rx_fsm_reset_done_int <= '0';
+ elsif (data_valid_sync = '1') then
+ rx_state <= FSM_DONE;
+ rx_fsm_reset_done_int <= '0';
+ reset_time_out <= '1';
+ end if;
+
+ when FSM_DONE =>
+ reset_time_out <= '0';
+ if data_valid_sync = '0' then
+ rx_fsm_reset_done_int <= '0';
+ reset_time_out <= '1';
+ rx_state <= MONITOR_DATA_VALID;
+ elsif(time_out_1us = '1') then
+ rx_fsm_reset_done_int <= '1';
+ end if;
+
+ if(time_out_adapt = '1') then
+ if((GT_TYPE = "GTX" ) and EQ_MODE = "DFE") then
+ RXDFEAGCHOLD <= '1';
+ RXDFELFHOLD <= '1';
+ else
+ RXDFEAGCHOLD <= '0';
+ RXDFELFHOLD <= '0';
+ RXLPMHFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ end if;
+ end if;
+
+ when OTHERS =>
+ rx_state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
+
+
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2.6
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename :gtxkintex7fee80_sync_block.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+--
+-- Description: Used on signals crossing from one clock domain to
+-- another, this is a flip-flop pair, with both flops
+-- placed together with RLOCs into the same slice. Thus
+-- the routing delay between the two is minimum to safe-
+-- guard against metastability issues.
+--
+--
+-- Module gtxKintex7FEE80_sync_block
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity gtxkintex7fee80_sync_block is
+ generic (
+ INITIALISE : bit_vector(1 downto 0) := "00"
+ );
+ port (
+ clk : in std_logic; -- clock to be sync'ed to
+ data_in : in std_logic; -- Data to be 'synced'
+ data_out : out std_logic -- synced data
+ );
+
+end gtxkintex7fee80_sync_block;
+
+
+architecture structural of gtxkintex7fee80_sync_block is
+
+
+ -- Internal Signals
+ signal data_sync1 : std_logic;
+
+ -- These attributes will stop Vivado translating the desired flip-flops into an
+ -- SRL based shift register.
+ attribute ASYNC_REG : string;
+ attribute ASYNC_REG of data_sync : label is "TRUE";
+ attribute ASYNC_REG of data_sync_reg : label is "TRUE";
+
+ -- These attributes will stop timing errors being reported on the target flip-flop during back annotated SDF simulation.
+ attribute MSGON : string;
+ attribute MSGON of data_sync : label is "FALSE";
+ attribute MSGON of data_sync_reg : label is "FALSE";
+
+ -- These attributes will stop XST translating the desired flip-flops into an
+ -- SRL based shift register.
+ attribute shreg_extract : string;
+ attribute shreg_extract of data_sync : label is "no";
+ attribute shreg_extract of data_sync_reg : label is "no";
+
+
+begin
+
+ data_sync : FD
+ generic map (
+ INIT => INITIALISE(0)
+ )
+ port map (
+ C => clk,
+ D => data_in,
+ Q => data_sync1
+ );
+
+
+ data_sync_reg : FD
+ generic map (
+ INIT => INITIALISE(1)
+ )
+ port map (
+ C => clk,
+ D => data_sync1,
+ Q => data_out
+ );
+
+
+end structural;
+
+
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2.6
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename :gtxkintex7fee80_sync_pulse.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+--
+-- Description: Used on signals crossing from faster clock domain
+--
+--
+-- Module gtxKintex7FEE80_sync_pulse
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxkintex7fee80_sync_pulse is
+ Generic(
+ C_NUM_SRETCH_REGS : integer := 3;
+ C_NUM_SYNC_REGS : integer := 3
+ );
+
+ Port (
+ -- Clock and Reset
+ CLK : in STD_LOGIC;
+ -- User Interface
+ USER_DONE : out STD_LOGIC := '0';
+ -- GT Interface
+ GT_DONE : in STD_LOGIC
+
+ );
+end gtxkintex7fee80_sync_pulse;
+
+architecture RTL of gtxkintex7fee80_sync_pulse is
+
+-- ---------------------------------------------------------------------------
+-- Wire and Register Declaration
+-- ---------------------------------------------------------------------------
+signal stretch_r : std_logic_vector (C_NUM_SRETCH_REGS-1 downto 0):= (others=>'0');
+signal sync1_r : std_logic_vector (C_NUM_SYNC_REGS-1 downto 0):= (others=>'0');
+signal sync2_r : std_logic_vector (C_NUM_SYNC_REGS-1 downto 0):= (others=>'0');
+
+ -- These attributes will stop Vivado translating the desired flip-flops into an
+ -- SRL based shift register.
+ attribute ASYNC_REG : string;
+ attribute ASYNC_REG of sync1_r : signal is "TRUE";
+ attribute ASYNC_REG of sync2_r : signal is "TRUE";
+
+ -- These attributes will stop XST translating the desired flip-flops into an
+ -- SRL based shift register.
+ attribute shreg_extract : string;
+ attribute shreg_extract of sync1_r : signal is "no";
+ attribute shreg_extract of sync2_r : signal is "no";
+
+
+begin
+------------------------------------------------------------------------------
+-- Stretch GT_DONE Signal
+------------------------------------------------------------------------------
+ process (CLK,GT_DONE)
+ begin
+ if (GT_DONE = '0') then
+ stretch_r <= (others=>'0');
+ elsif (CLK'event and CLK = '1') then
+ stretch_r <= ('1' & stretch_r(C_NUM_SRETCH_REGS-1 downto 1));
+ end if;
+ end process;
+
+------------------------------------------------------------------------------
+-- Synchronizers
+------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if (CLK'event and CLK = '1') then
+ sync1_r <= (stretch_r(0) & sync1_r(C_NUM_SYNC_REGS-1 downto 1));
+ end if;
+ end process;
+
+ process (CLK)
+ begin
+ if (CLK'event and CLK = '1') then
+ sync2_r <= (GT_DONE & sync2_r(C_NUM_SYNC_REGS-1 downto 1));
+ end if;
+ end process;
+
+------------------------------------------------------------------------------
+-- Final Flop Stage with AND of both synchronizers - keeps USER_DONE low
+-- when input is low for many cycles...
+------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if (CLK'event and CLK = '1') then
+ USER_DONE <= sync1_r(0) and sync2_r(0);
+ end if;
+ end process;
+
+end RTL;
+
+
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 2.6
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_init.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module gtxKintex7FEE80_init
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity gtxKintex7FEE80_top is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
+ STABLE_CLOCK_PERIOD : integer := 12; --Period of the stable clock driving this state-machine, unit is [ns]
+ EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ GT0_CPLLFBCLKLOST_OUT : out std_logic;
+ GT0_CPLLLOCK_OUT : out std_logic;
+ GT0_CPLLLOCKDETCLK_IN : in std_logic;
+ GT0_CPLLRESET_IN : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ GT0_GTREFCLK0_IN : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
+ GT0_DRPCLK_IN : in std_logic;
+ GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
+ GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
+ GT0_DRPEN_IN : in std_logic;
+ GT0_DRPRDY_OUT : out std_logic;
+ GT0_DRPWE_IN : in std_logic;
+ --------------------- RX Initialization and Reset Ports --------------------
+ GT0_RXUSERRDY_IN : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ GT0_EYESCANDATAERROR_OUT : out std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic;
+ GT0_RXCDRLOCK_OUT : out std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ GT0_RXUSRCLK_IN : in std_logic;
+ GT0_RXUSRCLK2_IN : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
+ GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GT0_GTXRXP_IN : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GT0_GTXRXN_IN : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ GT0_RXPHMONITOR_OUT : out std_logic_vector(4 downto 0);
+ GT0_RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ GT0_RXOUTCLK_OUT : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GT0_GTRXRESET_IN : in std_logic;
+ GT0_RXPMARESET_IN : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ GT0_RXRESETDONE_OUT : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ GT0_GTTXRESET_IN : in std_logic;
+ GT0_TXUSERRDY_IN : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ GT0_TXUSRCLK_IN : in std_logic;
+ GT0_TXUSRCLK2_IN : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GT0_GTXTXN_OUT : out std_logic;
+ GT0_GTXTXP_OUT : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ GT0_TXOUTCLK_OUT : out std_logic;
+ GT0_TXOUTCLKFABRIC_OUT : out std_logic;
+ GT0_TXOUTCLKPCS_OUT : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ GT0_TXRESETDONE_OUT : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GT0_GTREFCLK0_COMMON_IN : in std_logic;
+ ------------------------- Common Block - QPLL Ports ------------------------
+ GT0_QPLLLOCK_OUT : out std_logic;
+ GT0_QPLLLOCKDETCLK_IN : in std_logic;
+ GT0_QPLLRESET_IN : in std_logic;
+ testword0 : out std_logic_vector(35 downto 0) := (others => '0')
+
+
+);
+
+end gtxKintex7FEE80_top;
+
+architecture RTL of gtxKintex7FEE80_top is
+
+--**************************Component Declarations*****************************
+
+
+component gtxKintex7FEE80
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to 1 to speed up sim reset
+
+);
+port
+(
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ GT0_CPLLFBCLKLOST_OUT : out std_logic;
+ GT0_CPLLLOCK_OUT : out std_logic;
+ GT0_CPLLLOCKDETCLK_IN : in std_logic;
+ GT0_CPLLREFCLKLOST_OUT : out std_logic;
+ GT0_CPLLRESET_IN : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ GT0_GTREFCLK0_IN : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
+ GT0_DRPCLK_IN : in std_logic;
+ GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
+ GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
+ GT0_DRPEN_IN : in std_logic;
+ GT0_DRPRDY_OUT : out std_logic;
+ GT0_DRPWE_IN : in std_logic;
+ --------------------- RX Initialization and Reset Ports --------------------
+ GT0_RXUSERRDY_IN : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ GT0_EYESCANDATAERROR_OUT : out std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic;
+ GT0_RXCDRLOCK_OUT : out std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ GT0_RXUSRCLK_IN : in std_logic;
+ GT0_RXUSRCLK2_IN : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
+ GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GT0_GTXRXP_IN : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GT0_GTXRXN_IN : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ GT0_RXDLYEN_IN : in std_logic;
+ GT0_RXDLYSRESET_IN : in std_logic;
+ GT0_RXDLYSRESETDONE_OUT : out std_logic;
+ GT0_RXPHALIGN_IN : in std_logic;
+ GT0_RXPHALIGNDONE_OUT : out std_logic;
+ GT0_RXPHALIGNEN_IN : in std_logic;
+ GT0_RXPHDLYRESET_IN : in std_logic;
+ GT0_RXPHMONITOR_OUT : out std_logic_vector(4 downto 0);
+ GT0_RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ GT0_RXLPMHFHOLD_IN : in std_logic;
+ GT0_RXLPMLFHOLD_IN : in std_logic;
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ GT0_RXOUTCLK_OUT : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GT0_GTRXRESET_IN : in std_logic;
+ GT0_RXPCSRESET_IN : in std_logic;
+ GT0_RXPMARESET_IN : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ GT0_RXRESETDONE_OUT : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ GT0_GTTXRESET_IN : in std_logic;
+ GT0_TXUSERRDY_IN : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ GT0_TXUSRCLK_IN : in std_logic;
+ GT0_TXUSRCLK2_IN : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ GT0_TXDLYEN_IN : in std_logic;
+ GT0_TXDLYSRESET_IN : in std_logic;
+ GT0_TXDLYSRESETDONE_OUT : out std_logic;
+ GT0_TXPHALIGN_IN : in std_logic;
+ GT0_TXPHALIGNDONE_OUT : out std_logic;
+ GT0_TXPHALIGNEN_IN : in std_logic;
+ GT0_TXPHDLYRESET_IN : in std_logic;
+ GT0_TXPHINIT_IN : in std_logic;
+ GT0_TXPHINITDONE_OUT : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GT0_GTXTXN_OUT : out std_logic;
+ GT0_GTXTXP_OUT : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ GT0_TXOUTCLK_OUT : out std_logic;
+ GT0_TXOUTCLKFABRIC_OUT : out std_logic;
+ GT0_TXOUTCLKPCS_OUT : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ GT0_TXRESETDONE_OUT : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GT0_GTREFCLK0_COMMON_IN : in std_logic;
+ ------------------------- Common Block - QPLL Ports ------------------------
+ GT0_QPLLLOCK_OUT : out std_logic;
+ GT0_QPLLLOCKDETCLK_IN : in std_logic;
+ GT0_QPLLREFCLKLOST_OUT : out std_logic;
+ GT0_QPLLRESET_IN : in std_logic
+
+);
+end component;
+
+component gtxKintex7FEE80_TX_STARTUP_FSM
+ Generic(
+ GT_TYPE : string := "GTX";
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ TXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ GTTXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='0';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
+ TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
+ TXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC:='0';
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ PHALIGNMENT_DONE : in STD_LOGIC;
+
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end component;
+
+component gtxKintex7FEE80_RX_STARTUP_FSM
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ EQ_MODE : string := "DFE";
+ GT_TYPE : string := "GTX";
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ RXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ RECCLK_STABLE : in STD_LOGIC;
+ RECCLK_MONITOR_RESTART : in STD_LOGIC;
+ DATA_VALID : in STD_LOGIC;
+ TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
+ DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
+ GTRXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='0';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
+ RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
+ RXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC;
+ PHALIGNMENT_DONE : in STD_LOGIC;
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ RXDFEAGCHOLD : out STD_LOGIC;
+ RXDFELFHOLD : out STD_LOGIC;
+ RXLPMLFHOLD : out STD_LOGIC;
+ RXLPMHFHOLD : out STD_LOGIC;
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end component;
+
+
+
+
+component gtxKintex7FEE80_AUTO_PHASE_ALIGN
+ Generic(
+ GT_TYPE : string := "GTX"
+ );
+ port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC; -- Auto phase-alignment performed sucessfully
+ PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the
+ DLYSRESET : out STD_LOGIC; -- |transceiver.
+ DLYSRESETDONE : in STD_LOGIC; --/
+ RECCLKSTABLE : in STD_LOGIC --/on the RX-side.
+
+ );
+end component;
+
+
+component gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ TXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHINIT : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHINITDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end component;
+
+component gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ RXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end component;
+
+ function get_cdrlock_time(is_sim : in integer) return integer is
+ variable lock_time: integer;
+ begin
+ if (is_sim = 1) then
+ lock_time := 1000;
+ else
+ lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183
+ end if;
+ return lock_time;
+ end function;
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+ constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
+ constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
+
+ -------------------------- GT Wrapper Wires ------------------------------
+ signal gt0_cpllreset_i : std_logic;
+ signal gt0_cpllreset_t : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_txresetdone_i : std_logic;
+ signal gt0_rxresetdone_i : std_logic;
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_gttxreset_t : std_logic;
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_gtrxreset_t : std_logic;
+ signal gt0_rxpcsreset_i : std_logic;
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ signal gt0_txuserrdy_t : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ signal gt0_rxuserrdy_t : std_logic;
+
+ signal gt0_rxdfeagchold_i : std_logic;
+ signal gt0_rxdfelfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ signal gt0_rxlpmhfhold_i : std_logic;
+
+
+
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qplllock_i : std_logic;
+
+
+ ------------------------------- Global Signals -----------------------------
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ signal gt0_run_tx_phalignment_i : std_logic;
+ signal gt0_rst_tx_phalignment_i : std_logic;
+ signal gt0_tx_phalignment_done_i : std_logic;
+
+ signal gt0_rxoutclk_i : std_logic;
+ signal gt0_recclk_stable_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_run_rx_phalignment_i : std_logic;
+ signal gt0_rst_rx_phalignment_i : std_logic;
+ signal gt0_rx_phalignment_done_i : std_logic;
+
+
+
+ --------------------------- TX Buffer Bypass Signals --------------------
+ signal mstr0_txsyncallin_i : std_logic;
+ signal U0_TXDLYEN : std_logic_vector(0 downto 0);
+ signal U0_TXDLYSRESET : std_logic_vector(0 downto 0);
+ signal U0_TXDLYSRESETDONE : std_logic_vector(0 downto 0);
+ signal U0_TXPHINIT : std_logic_vector(0 downto 0);
+ signal U0_TXPHINITDONE : std_logic_vector(0 downto 0);
+ signal U0_TXPHALIGN : std_logic_vector(0 downto 0);
+ signal U0_TXPHALIGNDONE : std_logic_vector(0 downto 0);
+ signal U0_run_tx_phalignment_i : std_logic;
+ signal U0_rst_tx_phalignment_i : std_logic;
+
+
+ --------------------------- RX Buffer Bypass Signals --------------------
+ signal rxmstr0_rxsyncallin_i : std_logic;
+
+
+ signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
+ signal rx_cdrlocked : std_logic;
+
+
+ signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');
+
+
+
+--**************************** Main Body of Code *******************************
+begin
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+
+ ----------------------------- The GT Wrapper -----------------------------
+
+ -- Use the instantiation template in the example directory to add the GT wrapper to your design.
+ -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
+ -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
+ -- enabled, bonding should occur after alignment.
+
+
+ gtxKintex7FEE80_i : gtxKintex7FEE80
+ generic map
+ (
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
+ )
+ port map
+ (
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y0)
+
+ --------------------------------- CPLL Ports -------------------------------
+ GT0_CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT,
+ GT0_CPLLLOCK_OUT => gt0_cplllock_i,
+ GT0_CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN,
+ GT0_CPLLREFCLKLOST_OUT => gt0_cpllrefclklost_i,
+ GT0_CPLLRESET_IN => gt0_cpllreset_i,
+ -------------------------- Channel - Clocking Ports ------------------------
+ GT0_GTREFCLK0_IN => GT0_GTREFCLK0_IN,
+ ---------------------------- Channel - DRP Ports --------------------------
+ GT0_DRPADDR_IN => GT0_DRPADDR_IN,
+ GT0_DRPCLK_IN => GT0_DRPCLK_IN,
+ GT0_DRPDI_IN => GT0_DRPDI_IN,
+ GT0_DRPDO_OUT => GT0_DRPDO_OUT,
+ GT0_DRPEN_IN => GT0_DRPEN_IN,
+ GT0_DRPRDY_OUT => GT0_DRPRDY_OUT,
+ GT0_DRPWE_IN => GT0_DRPWE_IN,
+ --------------------- RX Initialization and Reset Ports --------------------
+ GT0_RXUSERRDY_IN => gt0_rxuserrdy_i,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN,
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN,
+ GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ GT0_RXDATA_OUT => GT0_RXDATA_OUT,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ GT0_RXDISPERR_OUT => GT0_RXDISPERR_OUT,
+ GT0_RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GT0_GTXRXP_IN => GT0_GTXRXP_IN,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GT0_GTXRXN_IN => GT0_GTXRXN_IN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ GT0_RXDLYEN_IN => '0', -- gt0_rxdlyen_i,
+ GT0_RXDLYSRESET_IN => '1', -- gt0_rxdlysreset_i,
+ GT0_RXDLYSRESETDONE_OUT => gt0_rxdlysresetdone_i,
+ GT0_RXPHALIGN_IN => '0', -- gt0_rxphalign_i,
+ GT0_RXPHALIGNDONE_OUT => gt0_rxphaligndone_i,
+ GT0_RXPHALIGNEN_IN => '1', -- gt0_rxphalignen_i,
+ GT0_RXPHDLYRESET_IN => '1', -- gt0_rxphdlyreset_i,
+ GT0_RXPHMONITOR_OUT => GT0_RXPHMONITOR_OUT,
+ GT0_RXPHSLIPMONITOR_OUT => GT0_RXPHSLIPMONITOR_OUT,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ GT0_RXLPMHFHOLD_IN => gt0_rxlpmhfhold_i,
+ GT0_RXLPMLFHOLD_IN => gt0_rxlpmlfhold_i,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ GT0_RXOUTCLK_OUT => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GT0_GTRXRESET_IN => gt0_gtrxreset_i,
+ GT0_RXPCSRESET_IN => gt0_rxpcsreset_i,
+ GT0_RXPMARESET_IN => GT0_RXPMARESET_IN,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ GT0_RXCHARISK_OUT => GT0_RXCHARISK_OUT,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ GT0_GTTXRESET_IN => gt0_gttxreset_i,
+ GT0_TXUSERRDY_IN => gt0_txuserrdy_i,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN,
+ GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ GT0_TXDLYEN_IN => gt0_txdlyen_i,
+ GT0_TXDLYSRESET_IN => gt0_txdlysreset_i,
+ GT0_TXDLYSRESETDONE_OUT => gt0_txdlysresetdone_i,
+ GT0_TXPHALIGN_IN => gt0_txphalign_i,
+ GT0_TXPHALIGNDONE_OUT => gt0_txphaligndone_i,
+ GT0_TXPHALIGNEN_IN => gt0_txphalignen_i,
+ GT0_TXPHDLYRESET_IN => gt0_txphdlyreset_i,
+ GT0_TXPHINIT_IN => gt0_txphinit_i,
+ GT0_TXPHINITDONE_OUT => gt0_txphinitdone_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GT0_TXDATA_IN => GT0_TXDATA_IN,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GT0_GTXTXN_OUT => GT0_GTXTXN_OUT,
+ GT0_GTXTXP_OUT => GT0_GTXTXP_OUT,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
+ GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT,
+ GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ GT0_TXCHARISK_IN => GT0_TXCHARISK_IN,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
+
+
+
+
+ --____________________________COMMON PORTS________________________________
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ GT0_QPLLLOCK_OUT => gt0_qplllock_i,
+ GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN,
+ GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ GT0_QPLLRESET_IN => gt0_qpllreset_i
+
+ );
+
+ gt0_rxpcsreset_i <= tied_to_ground_i;
+
+ gt0_rxdfelpmreset_i <= tied_to_ground_i;
+
+
+
+
+ GT0_CPLLLOCK_OUT <= gt0_cplllock_i;
+ GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
+ GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
+ GT0_RXOUTCLK_OUT <= gt0_rxoutclk_i;
+ GT0_QPLLLOCK_OUT <= gt0_qplllock_i;
+
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
+ gt0_cpllreset_i <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
+ gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
+ gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
+ gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
+ gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
+ gt0_qpllreset_i <= GT0_QPLLRESET_IN or gt0_qpllreset_t;
+end generate chipscope;
+
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
+ gt0_cpllreset_i <= gt0_cpllreset_t;
+ gt0_gttxreset_i <= gt0_gttxreset_t;
+ gt0_gtrxreset_i <= gt0_gtrxreset_t;
+ gt0_txuserrdy_i <= gt0_txuserrdy_t;
+ gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
+ gt0_qpllreset_i <= gt0_qpllreset_t;
+end generate no_chipscope;
+
+
+gt0_txresetfsm_i: gtxKintex7FEE80_TX_STARTUP_FSM
+
+ generic map(
+ GT_TYPE => "GTX", --GTX or GTH or GTP
+ STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH => 8,
+ TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
+ RX_QPLL_USED => FALSE, -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL => TRUE -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ )
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ TXUSERCLK => GT0_TXUSRCLK_IN,
+ SOFT_RESET => SOFT_RESET_IN,
+ QPLLREFCLKLOST => tied_to_ground_i,
+ CPLLREFCLKLOST => gt0_cpllrefclklost_i,
+ QPLLLOCK => tied_to_vcc_i,
+ CPLLLOCK => gt0_cplllock_i,
+ TXRESETDONE => gt0_txresetdone_i,
+ MMCM_LOCK => GT0_TX_MMCM_LOCK_IN,
+ GTTXRESET => gt0_gttxreset_t,
+ MMCM_RESET => GT0_TX_MMCM_RESET_OUT,
+ QPLL_RESET => open,
+ CPLL_RESET => gt0_cpllreset_t,
+ TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT,
+ TXUSERRDY => gt0_txuserrdy_t,
+ RUN_PHALIGNMENT => gt0_run_tx_phalignment_i,
+ RESET_PHALIGNMENT => gt0_rst_tx_phalignment_i,
+ PHALIGNMENT_DONE => gt0_tx_phalignment_done_i,
+ RETRY_COUNTER => open
+ );
+
+
+
+
+
+
+gt0_rxresetfsm_i: gtxKintex7FEE80_RX_STARTUP_FSM
+
+ generic map(
+ EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
+ GT_TYPE => "GTX", --GTX or GTH or GTP
+ EQ_MODE => "LPM", --Rx Equalization Mode - Set to DFE or LPM
+ STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH => 8,
+ TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
+ RX_QPLL_USED => FALSE, -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL => TRUE -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ )
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ RXUSERCLK => GT0_RXUSRCLK_IN,
+ SOFT_RESET => SOFT_RESET_IN,
+ DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
+ QPLLREFCLKLOST => tied_to_ground_i,
+ CPLLREFCLKLOST => gt0_cpllrefclklost_i,
+ QPLLLOCK => tied_to_vcc_i,
+ CPLLLOCK => gt0_cplllock_i,
+ RXRESETDONE => gt0_rxresetdone_i,
+ MMCM_LOCK => tied_to_vcc_i,
+ RECCLK_STABLE => gt0_recclk_stable_i,
+ RECCLK_MONITOR_RESTART => tied_to_ground_i,
+ DATA_VALID => GT0_DATA_VALID_IN,
+ TXUSERRDY => tied_to_vcc_i,
+ GTRXRESET => gt0_gtrxreset_t,
+ MMCM_RESET => open,
+ QPLL_RESET => open,
+ CPLL_RESET => open,
+ RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT,
+ RXUSERRDY => gt0_rxuserrdy_t,
+ RUN_PHALIGNMENT => gt0_run_rx_phalignment_i,
+ RESET_PHALIGNMENT => gt0_rst_rx_phalignment_i,
+ PHALIGNMENT_DONE => gt0_rx_phalignment_done_i,
+ RXDFEAGCHOLD => gt0_rxdfeagchold_i,
+ RXDFELFHOLD => gt0_rxdfelfhold_i,
+ RXLPMLFHOLD => gt0_rxlpmlfhold_i,
+ RXLPMHFHOLD => gt0_rxlpmhfhold_i,
+ RETRY_COUNTER => open
+ );
+
+
+
+ cdrlock_timeout:process(SYSCLK_IN)
+ begin
+ if rising_edge(SYSCLK_IN) then
+ if(gt0_gtrxreset_i = '1') then
+ rx_cdrlocked <= '0';
+ rx_cdrlock_counter <= 0 after DLY;
+ elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
+ rx_cdrlocked <= '1';
+ rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
+ else
+ rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
+ end if;
+ end if;
+ end process;
+
+gt0_recclk_stable_i <= rx_cdrlocked;
+
+
+
+ --------------------------- TX Buffer Bypass Logic --------------------
+ -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer.
+ -- Include the TX SYNC module in your own design if TX Buffer is bypassed.
+
+--Manual
+ gt0_tx_manual_phase_i : gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN
+ generic map
+ ( NUMBER_OF_LANES => 1,
+ MASTER_LANE_ID => 0
+ )
+ port map
+ (
+ STABLE_CLOCK => SYSCLK_IN,
+ RESET_PHALIGNMENT => U0_rst_tx_phalignment_i, --TODO
+ RUN_PHALIGNMENT => U0_run_tx_phalignment_i, --TODO
+ PHASE_ALIGNMENT_DONE => gt0_tx_phalignment_done_i,
+ TXDLYSRESET => U0_TXDLYSRESET,
+ TXDLYSRESETDONE => U0_TXDLYSRESETDONE,
+ TXPHINIT => U0_TXPHINIT,
+ TXPHINITDONE => U0_TXPHINITDONE,
+ TXPHALIGN => U0_TXPHALIGN,
+ TXPHALIGNDONE => U0_TXPHALIGNDONE,
+ TXDLYEN => U0_TXDLYEN
+ );
+
+ gt0_txphdlyreset_i <= tied_to_ground_i;
+ gt0_txphalignen_i <= tied_to_vcc_i;
+ gt0_txdlysreset_i <= U0_TXDLYSRESET(0);
+ gt0_txphinit_i <= U0_TXPHINIT(0);
+ gt0_txphalign_i <= U0_TXPHALIGN(0);
+ gt0_txdlyen_i <= U0_TXDLYEN(0);
+ U0_TXDLYSRESETDONE(0) <= gt0_txdlysresetdone_i;
+ U0_TXPHINITDONE(0) <= gt0_txphinitdone_i;
+ U0_TXPHALIGNDONE(0) <= gt0_txphaligndone_i;
+
+
+
+ U0_run_tx_phalignment_i <= gt0_run_tx_phalignment_i
+ ;
+
+ U0_rst_tx_phalignment_i <= gt0_rst_tx_phalignment_i
+ ;
+
+
+
+ --------------------------- RX Buffer Bypass Logic --------------------
+-- The RX SYNC Module drives the ports needed to Bypass the RX Buffer.
+-- Include the RX SYNC module in your own design if RX Buffer is bypassed.
+
+
+--Auto
+
+gt0_rxphdlyreset_i <= tied_to_ground_i; --// '1'; --//
+gt0_rxphalignen_i <= tied_to_ground_i; --//'1'; --//
+gt0_rxdlyen_i <= tied_to_ground_i;
+gt0_rxphalign_i <= tied_to_ground_i;
+
+gt0_rx_phalignment_done_i <= '1';
+gt0_rxdlysreset_i <= '1'; --//
+
+
+
+--gt0_rx_auto_phase_align_i : gtxKintex7FEE80_AUTO_PHASE_ALIGN
+-- generic map(
+-- GT_TYPE => "GTX" --GTX or GTH or GTP
+-- )
+-- port map (
+-- STABLE_CLOCK => SYSCLK_IN,
+-- RUN_PHALIGNMENT => gt0_run_rx_phalignment_i,
+-- PHASE_ALIGNMENT_DONE => gt0_rx_phalignment_done_i,
+-- PHALIGNDONE => gt0_rxphaligndone_i,
+-- DLYSRESET => gt0_rxdlysreset_i,
+-- DLYSRESETDONE => gt0_rxdlysresetdone_i,
+-- RECCLKSTABLE => gt0_recclk_stable_i
+-- );
+
+
+
+
+
+--testword0(22) <= gt0_cplllock_i;
+--testword0(23) <= gt0_cpllrefclklost_i;
+--testword0(24) <= gt0_cpllreset_i;
+
+
+--testword0(35 downto 22) <= testword0_S(35 downto 22);
+
+--testword0(22) <= SOFT_RESET_IN;
+--testword0(23) <= gt0_cplllock_i;
+--testword0(24) <= gt0_recclk_stable_i;
+--
+--testword0(25) <= gt0_rxuserrdy_i;
+--testword0(26) <= gt0_rxdlysreset_i;
+--testword0(27) <= gt0_rxdlysresetdone_i;
+--testword0(28) <= gt0_rxphaligndone_i;
+--testword0(29) <= gt0_rxphdlyreset_i;
+--testword0(30) <= gt0_gtrxreset_i;
+--
+--testword0(31) <= gt0_rxpcsreset_i;
+--testword0(32) <= gt0_rxresetdone_i;
+--
+--
+--testword0(33) <= gt0_run_rx_phalignment_i;
+--testword0(34) <= gt0_rst_rx_phalignment_i;
+--testword0(35) <= gt0_rx_phalignment_done_i;
+
+--testword0(33) <= gt0_txresetdone_i;
+--testword0(34) <= gt0_qpllrefclklost_i;
+--testword0(35) <= gt0_qpllreset_i;
+
+--gt0_gttxreset_i
+--gt0_txuserrdy_i
+--gt0_txphaligndone_i
+--gt0_txphdlyreset_i
+
+
+
+
+end RTL;
+
+
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2.6
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtxkintex7fee80_tx_manual_phase_align.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+-- Description : This module performs TX Buffer Phase Alignment in Manual Mode.
+--
+--
+--
+-- Module gtxKintex7FEE80_tx_manual_phase_align
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN is
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ TXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHINIT : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHINITDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN;
+
+architecture RTL of gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN is
+
+ component gtxKintex7FEE80_sync_block
+ generic (
+ INITIALISE : bit_vector(1 downto 0) := "00"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ component gtxkintex7fee80_sync_pulse
+ generic(
+ C_NUM_SRETCH_REGS : integer := 3;
+ C_NUM_SYNC_REGS : integer := 3
+ );
+
+ port (
+ CLK : in STD_LOGIC;
+ USER_DONE : out STD_LOGIC := '0';
+ GT_DONE : in STD_LOGIC
+
+ );
+end component;
+
+ constant VCC_VEC : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '1');
+ constant GND_VEC : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+
+ signal txphaligndone_prev : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal txphaligndone_ris_edge : std_logic_vector(NUMBER_OF_LANES-1 downto 0);
+ signal txphinitdone_prev : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal txphinitdone_ris_edge : std_logic_vector(NUMBER_OF_LANES-1 downto 0);
+ signal txphinitdone_store_edge : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal txphinitdone_clear_slave : std_logic:='0';
+ signal txdlysresetdone_store : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal txphaligndone_store : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal txdone_clear : std_logic:='0';
+
+
+ signal count_phalign_edges : integer range 0 to 3:= 0;
+
+
+ signal txphaligndone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal txphinitdone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+ signal txdlysresetdone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+
+ type tx_phase_align_manual_fsm is(
+ INIT, WAIT_PHRST_DONE, M_PHINIT, M_PHALIGN, M_DLYEN,
+ S_PHINIT, S_PHALIGN, M_DLYEN2, PHALIGN_DONE
+ );
+ signal tx_phalign_manual_state : tx_phase_align_manual_fsm := INIT;
+
+begin
+
+ cdc: for i in 0 to NUMBER_OF_LANES-1 generate
+ sync_TXPHALIGNDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => TXPHALIGNDONE(i),
+ data_out => txphaligndone_sync(i)
+ );
+
+ sync_TXDLYSRESETDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => TXDLYSRESETDONE(i),
+ data_out => txdlysresetdone_sync(i)
+ );
+
+ sync_TXPHINITDONE : gtxKintex7FEE80_sync_pulse
+ port map
+ (
+ CLK => STABLE_CLOCK,
+ GT_DONE => TXPHINITDONE(i),
+ USER_DONE => txphinitdone_sync(i)
+ );
+ end generate;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ txphaligndone_prev <= txphaligndone_sync;
+ txphinitdone_prev <= txphinitdone_sync;
+ end if;
+ end process;
+
+
+ rising_edge_detect: for i in 0 to NUMBER_OF_LANES-1 generate
+ txphaligndone_ris_edge(i) <= '1' when (txphaligndone_prev(i) = '0') and (txphaligndone_sync(i) = '1') else '0';
+ txphinitdone_ris_edge(i) <= '1' when (txphinitdone_prev(i) = '0') and (txphinitdone_sync(i) = '1') else '0';
+ end generate;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if txdone_clear = '1' then
+ txdlysresetdone_store <= (others=>'0');
+ txphaligndone_store <= (others=>'0');
+ else
+ for i in 0 to NUMBER_OF_LANES-1 loop
+ if txdlysresetdone_sync(i) = '1' then
+ txdlysresetdone_store(i) <= '1';
+ end if;
+ if txphaligndone_ris_edge(i) = '1' then
+ txphaligndone_store(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end process;
+
+
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if txphinitdone_clear_slave = '1' then
+ --Only clear the TXPHINITDONE-storage from the slaves.
+ txphinitdone_store_edge <= (others=>'0');
+ --The information stored on the MASTER_LANE_ID is used differently. The way txphinitdone_store_edge
+ --is coded, it will be optimised away afterwards. It is only for simplicity of the code on the checks
+ --that the master-lane is "recorded" too.
+ txphinitdone_store_edge(MASTER_LANE_ID) <= '1';
+ else
+ for i in 0 to NUMBER_OF_LANES-1 loop
+ if txphinitdone_ris_edge(i) = '1' then
+ txphinitdone_store_edge(i) <= '1';
+ end if;
+ end loop;
+ end if;
+ end if;
+ end process;
+
+
+
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if RESET_PHALIGNMENT = '1' then
+ PHASE_ALIGNMENT_DONE <= '0';
+ TXDLYSRESET <= (others=> '0');
+ TXPHINIT <= (others=> '0');
+ TXPHALIGN <= (others=> '0');
+ TXDLYEN <= (others=> '0');
+ tx_phalign_manual_state <= INIT;
+ txphinitdone_clear_slave <= '1';
+ txdone_clear <= '1';
+ else
+ case tx_phalign_manual_state is
+ when INIT =>
+ PHASE_ALIGNMENT_DONE <= '0';
+ txphinitdone_clear_slave <= '1';
+ txdone_clear <= '1';
+ if RUN_PHALIGNMENT = '1' then
+ --TXDLYSRESET is toggled to '1'
+ TXDLYSRESET <= (others=> '1');
+ txphinitdone_clear_slave <= '0';
+ txdone_clear <= '0';
+ tx_phalign_manual_state <= WAIT_PHRST_DONE;
+ end if;
+
+ when WAIT_PHRST_DONE =>
+ --Assert TXDLYSRESET for all lanes, hold high until
+ --TXDLYSRESETDONE of the respective lane is asserted.
+ for i in 0 to NUMBER_OF_LANES - 1 loop
+ if txdlysresetdone_store(i) = '1' then
+ --Deassert TXDLYSRESET for the lane in which
+ --the TXDLYSRESETDONE is asserted:
+ TXDLYSRESET(i) <= '0';
+ end if;
+ end loop;
+ if txdlysresetdone_store = VCC_VEC then
+ --When all TXDLYSRESETDONE-signals are asserted, move
+ --to the next state.
+ tx_phalign_manual_state <= M_PHINIT;
+ end if;
+
+ when M_PHINIT =>
+ --Assert TXPHINIT on the master and hold high until a
+ --rising edge on TXPHINITDONE is detected:
+ TXPHINIT(MASTER_LANE_ID) <= '1';
+ if txphinitdone_ris_edge(MASTER_LANE_ID) = '1' then
+ --Then deassert TXPHINIT and move to the next state.
+ TXPHINIT(MASTER_LANE_ID) <= '0';
+ tx_phalign_manual_state <= M_PHALIGN;
+ end if;
+
+ when M_PHALIGN =>
+ --Assert TXPHALIGN on the master and hold high until a
+ --rising edge on TXPHALIGNDONE is detected:
+ TXPHALIGN(MASTER_LANE_ID) <= '1';
+ if txphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+ --Then dassert TXPHALIGN and move to the next state.
+ TXPHALIGN(MASTER_LANE_ID) <= '0';
+ tx_phalign_manual_state <= M_DLYEN;
+ end if;
+
+ when M_DLYEN =>
+ --Assert TXDLYEN on the master and hold high until a
+ --rising edge on TXPHALIGNDONE is detected.
+ TXDLYEN(MASTER_LANE_ID) <= '1';
+ if txphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+ --Then deassert TXDLYEN and move to the next state.
+ if(NUMBER_OF_LANES > 1) then
+ TXDLYEN(MASTER_LANE_ID) <= '0';
+ tx_phalign_manual_state <= S_PHINIT;
+ else
+ tx_phalign_manual_state <= PHALIGN_DONE;
+ end if;
+ end if;
+ when S_PHINIT =>
+ --Assert TXPHINIT for all slave lane(s). Hold this
+ --signal High until TXPHINITDONE of the respective
+ --slave lane is asserted.
+ TXPHINIT <= (others=>'1');--\Assert only the PHINIT-signal of
+ TXPHINIT(MASTER_LANE_ID) <= '0'; --/the slaves.
+
+ for i in 0 to NUMBER_OF_LANES - 1 loop
+ if txphinitdone_store_edge(i) = '1' then
+ --Deassert TXPHINIT for the slave lane in which
+ --the TXPHINITDONE is asserted.
+ TXPHINIT(i) <= '0';
+ end if;
+ end loop;
+ --if txphinitdone_store_edge = VCC_VEC and txphinitdone_ris_edge /= GND_VEC then
+ if txphinitdone_store_edge = VCC_VEC then
+ --When all TXPHINITDONE-signals are high and at least one rising edge
+ --has been detected, move to the next state.
+ --The reason for checking of the occurance of at least one rising edge
+ --is to avoid the potential direct move where TXPHINITDONE might not
+ --be going low fast enough.
+ tx_phalign_manual_state <= S_PHALIGN;
+ end if;
+
+ when S_PHALIGN =>
+ --Assert TXPHALIGN for all slave lane(s). Hold this signal High
+ --until TXPHALIGNDONE of the respective slave lane is asserted.
+ TXPHALIGN <= (others=>'1');--again only assertion for slave
+ TXPHALIGN(MASTER_LANE_ID) <= '0'; --but not for master
+
+ for i in 0 to NUMBER_OF_LANES - 1 loop
+ --if txphaligndone_ris_edge(i) = '1' then
+ if txphaligndone_store(i) = '1' then
+ --Deassert TXPHALIGN for the slave lane in which the
+ --TXPHALIGNDONE is asserted.
+ TXPHALIGN(i) <= '0';
+ end if;
+ end loop;
+ --if txphaligndone_store = VCC_VEC and txphaligndone_ris_edge /= GND_VEC then
+ if txphaligndone_store = VCC_VEC then
+ --When all TXPHALIGNDONE-signals are asserted high, move to the next
+ --state.
+ tx_phalign_manual_state <= M_DLYEN2;
+ end if;
+
+ when M_DLYEN2 =>
+ --Assert TXDLYEN for the master lane. This causes TXPHALIGNDONE of
+ --the master lane to be deasserted.
+ TXDLYEN(MASTER_LANE_ID) <= '1';
+ if txphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+ --Wait until TXPHALIGNDONE of the master lane reasserts. Phase
+ --and delay alignment for the multilane interface is complete.
+ tx_phalign_manual_state <= PHALIGN_DONE;
+ end if;
+
+ when PHALIGN_DONE =>
+ --Continue to hold TXDLYEN for the master lane High to adjust
+ --TXUSRCLK to compensate for temperature and voltage variations.
+ TXDLYEN(MASTER_LANE_ID) <= '1';
+ PHASE_ALIGNMENT_DONE <= '1';
+
+ when OTHERS =>
+ tx_phalign_manual_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end RTL;
+
+
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 2.6
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename :gtxkintex7fee80_tx_startup_fsm.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module gtxKintex7FEE80_tx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_TX_STARTUP_FSM is
+ Generic( GT_TYPE : string := "GTX";
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ TXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ GTTXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='1';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
+ TX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
+ TXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC:='0';
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ PHALIGNMENT_DONE : in STD_LOGIC;
+
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end gtxKintex7FEE80_TX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+-- are calculated at design-time based on the Generics
+--
+-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
+-- => signal which PLL has been reset
+-- *
+
+
+
+architecture RTL of gtxKintex7FEE80_TX_STARTUP_FSM is
+
+ component gtxKintex7FEE80_sync_block
+ generic (
+ INITIALISE : bit_vector(1 downto 0) := "00"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ type tx_rst_fsm_type is(
+ INIT, ASSERT_ALL_RESETS, RELEASE_PLL_RESET,
+ RELEASE_MMCM_RESET, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+ RESET_FSM_DONE);
+
+ signal tx_state : tx_rst_fsm_type := INIT;
+
+ constant MMCM_LOCK_CNT_MAX : integer := 1024;
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+ constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
+ constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--100 us time-out
+
+ signal init_wait_count : integer range 0 to WAIT_MAX:=0;
+ signal init_wait_done : std_logic := '0';
+ signal pll_reset_asserted : std_logic := '0';
+
+ signal tx_fsm_reset_done_int : std_logic := '0';
+ signal tx_fsm_reset_done_int_s2 : std_logic := '0';
+ signal tx_fsm_reset_done_int_s3 : std_logic := '0';
+
+ signal txresetdone_s2 : std_logic := '0';
+ signal txresetdone_s3 : std_logic := '0';
+
+ constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
+ signal retry_counter_int : integer range 0 to MAX_RETRIES;
+ signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+
+ signal reset_time_out : std_logic := '0';
+ signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
+ signal time_tlock_max : std_logic := '0';--|have been reached.
+ signal time_out_500us : std_logic := '0';--/
+
+ signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+ signal mmcm_lock_int : std_logic := '0';
+ signal mmcm_lock_reclocked : std_logic := '0';
+
+ signal run_phase_alignment_int : std_logic := '0';
+ signal run_phase_alignment_int_s2 : std_logic := '0';
+ signal run_phase_alignment_int_s3 : std_logic := '0';
+
+ constant MAX_WAIT_BYPASS : integer := 110000; --110000 TXUSRCLK cycles is the max time for Multi lane designs
+ signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
+ signal time_out_wait_bypass : std_logic := '0';
+ signal time_out_wait_bypass_s2 : std_logic := '0';
+ signal time_out_wait_bypass_s3 : std_logic := '0';
+ signal refclk_lost : std_logic;
+
+ signal cplllock_sync: std_logic := '0';
+ signal qplllock_sync: std_logic := '0';
+ signal cplllock_prev: std_logic := '0';
+ signal qplllock_prev: std_logic := '0';
+ signal cplllock_ris_edge: std_logic := '0';
+ signal qplllock_ris_edge: std_logic := '0';
+
+begin
+ --Alias section, signals used within this module mapped to output ports:
+ RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+ RUN_PHALIGNMENT <= run_phase_alignment_int;
+ TX_FSM_RESET_DONE <= tx_fsm_reset_done_int;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+
+ timeouts:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- One common large counter for generating three time-out signals.
+ -- Intermediate time-outs are derived from calculated values, based
+ -- on the period of the provided clock.
+ if reset_time_out = '1' then
+ time_out_counter <= 0;
+ time_out_2ms <= '0';
+ time_tlock_max <= '0';
+ time_out_500us <= '0';
+ else
+ if time_out_counter = WAIT_TIMEOUT_2ms then
+ time_out_2ms <= '1';
+ else
+ time_out_counter <= time_out_counter + 1;
+ end if;
+
+ if time_out_counter = WAIT_TLOCK_MAX then
+ time_tlock_max <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_500us then
+ time_out_500us <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ mmcm_lock_wait:process(TXUSERCLK)
+ begin
+ if rising_edge(TXUSERCLK) then
+ if MMCM_LOCK = '0' then
+ mmcm_lock_count <= 0;
+ mmcm_lock_int <= '0';
+ else
+ if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+ mmcm_lock_count <= mmcm_lock_count + 1;
+ else
+ mmcm_lock_int <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+
+ -- Clock Domain Crossing
+
+ sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => TXUSERCLK,
+ data_in => run_phase_alignment_int,
+ data_out => run_phase_alignment_int_s2
+ );
+
+ sync_tx_fsm_reset_done_int : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => TXUSERCLK,
+ data_in => tx_fsm_reset_done_int,
+ data_out => tx_fsm_reset_done_int_s2
+ );
+
+ process(TXUSERCLK)
+ begin
+ if rising_edge(TXUSERCLK) then
+ run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
+
+ tx_fsm_reset_done_int_s3 <= tx_fsm_reset_done_int_s2;
+ end if;
+ end process;
+
+ sync_TXRESETDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => TXRESETDONE,
+ data_out => txresetdone_s2
+ );
+
+ sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => time_out_wait_bypass,
+ data_out => time_out_wait_bypass_s2
+ );
+
+ sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => mmcm_lock_int,
+ data_out => mmcm_lock_reclocked
+ );
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ txresetdone_s3 <= txresetdone_s2;
+
+ time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
+ cplllock_prev <= cplllock_sync;
+ qplllock_prev <= qplllock_sync;
+ end if;
+ end process;
+
+ sync_CPLLLOCK : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => CPLLLOCK,
+ data_out => cplllock_sync
+ );
+
+ sync_QPLLLOCK : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => QPLLLOCK,
+ data_out => qplllock_sync
+ );
+
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ cplllock_ris_edge <= '0';
+ elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+ cplllock_ris_edge <= '1';
+ elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+ cplllock_ris_edge <= cplllock_ris_edge;
+ else
+ cplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ qplllock_ris_edge <= '0';
+ elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+ qplllock_ris_edge <= '1';
+ elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+ qplllock_ris_edge <= qplllock_ris_edge;
+ else
+ qplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ timeout_buffer_bypass:process(TXUSERCLK)
+ begin
+ if rising_edge(TXUSERCLK) then
+ if run_phase_alignment_int_s3 = '0' then
+ wait_bypass_count <= 0;
+ time_out_wait_bypass <= '0';
+ elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0') then
+ if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+ time_out_wait_bypass <= '1';
+ else
+ wait_bypass_count <= wait_bypass_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+ --FSM for resetting the GTX/GTH/GTP in the 7-series.
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ --
+ -- Following steps are performed:
+ -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in
+ -- answer-record 43482
+ -- 2) Assert all resets on the GT and on an MMCM potentially connected.
+ -- After that wait until a reference-clock has been detected.
+ -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+ -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+ -- Also signal to the RX-side which PLL has been reset.
+ -- 5) Wait for the RESET_DONE-signal from the GT.
+ -- 6) Signal to start the phase-alignment procedure and wait for it to
+ -- finish.
+ -- 7) Reset-sequence has successfully run through. Signal this to the
+ -- rest of the design by asserting TX_FSM_RESET_DONE.
+
+ reset_fsm:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+ tx_state <= INIT;
+ TXUSERRDY <= '0';
+ GTTXRESET <= '0';
+ MMCM_RESET <= '1';
+ tx_fsm_reset_done_int <= '0';
+ QPLL_RESET <= '0';
+ CPLL_RESET <= '0';
+ pll_reset_asserted <= '0';
+ reset_time_out <= '0';
+ retry_counter_int <= 0;
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+ else
+
+ case tx_state is
+ when INIT =>
+ --Initial state after configuration. This state will be left after
+ --approx. 500 ns and not be re-entered.
+ if init_wait_done = '1' then
+ tx_state <= ASSERT_ALL_RESETS;
+ reset_time_out <= '1';
+ end if;
+
+ when ASSERT_ALL_RESETS =>
+ --This is the state into which the FSM will always jump back if any
+ --time-outs will occur.
+ --The number of retries is reported on the output RETRY_COUNTER. In
+ --case the transceiver never comes up for some reason, this machine
+ --will still continue its best and rerun until the FPGA is turned off
+ --or the transceivers come up correctly.
+ if TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ QPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ QPLL_RESET <= '0';
+ end if;
+ else
+ if pll_reset_asserted = '0' then
+ CPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ CPLL_RESET <= '0';
+ end if;
+ end if;
+ TXUSERRDY <= '0';
+ GTTXRESET <= '1';
+ MMCM_RESET <= '1';
+ reset_time_out <= '0';
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+
+ if (TX_QPLL_USED and (QPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or
+ (not TX_QPLL_USED and (CPLLREFCLKLOST = '0') and pll_reset_asserted = '1') then
+ tx_state <= RELEASE_PLL_RESET;
+ end if;
+
+ when RELEASE_PLL_RESET =>
+ --PLL-Reset of the GTX gets released and the time-out counter
+ --starts running.
+ pll_reset_asserted <= '0';
+
+ if (TX_QPLL_USED and (qplllock_ris_edge = '1')) or
+ (not TX_QPLL_USED and (cplllock_ris_edge = '1')) then
+ tx_state <= RELEASE_MMCM_RESET;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_2ms = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when RELEASE_MMCM_RESET =>
+ GTTXRESET <= '0';
+ reset_time_out <= '0';
+ --Release of the MMCM-reset. Waiting for the MMCM to lock.
+ MMCM_RESET <= '0';
+ if mmcm_lock_reclocked = '1' then
+ tx_state <= WAIT_RESET_DONE;
+ reset_time_out <= '1';
+ end if;
+
+ if time_tlock_max = '1' and mmcm_lock_reclocked = '0' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_RESET_DONE =>
+ TXUSERRDY <= '1';
+ reset_time_out <= '0';
+ if txresetdone_s3 = '1' then
+ tx_state <= DO_PHASE_ALIGNMENT;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_500us = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when DO_PHASE_ALIGNMENT =>
+ --The direct handling of the signals for the Phase Alignment is done outside
+ --this state-machine.
+ RESET_PHALIGNMENT <= '0';
+ run_phase_alignment_int <= '1';
+ reset_time_out <= '0';
+
+ if PHALIGNMENT_DONE = '1' then
+ tx_state <= RESET_FSM_DONE;
+ end if;
+
+ if time_out_wait_bypass_s3 = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when RESET_FSM_DONE =>
+ reset_time_out <= '1';
+ tx_fsm_reset_done_int <= '1';
+
+ when OTHERS =>
+ tx_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80 (a Core Top)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity gtxKintex7FEE80 is
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end gtxKintex7FEE80;
+
+architecture RTL of gtxKintex7FEE80 is
+ attribute DowngradeIPIdentifiedWarnings: string;
+ attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of RTL : architecture is "gtxKintex7FEE80,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+--**************************Component Declarations*****************************
+
+component gtxKintex7FEE80_init
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+
+ STABLE_CLOCK_PERIOD : integer := 12;
+ -- Set to 1 for simulation
+ EXAMPLE_USE_CHIPSCOPE : integer := 1 --// Modified -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end component;
+
+--**************************** Main Body of Code *******************************
+begin
+ U0 : gtxKintex7FEE80_init
+ generic map
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP => "TRUE",
+ EXAMPLE_SIMULATION => 0,
+
+ USE_BUFG => 0,
+
+ STABLE_CLOCK_PERIOD => 12,
+ EXAMPLE_USE_CHIPSCOPE => 1 --// Modified
+)
+port map
+(
+ SYSCLK_IN => SYSCLK_IN,
+ SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
+ SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
+ DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
+ GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
+ GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
+ GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
+ GT0_TX_MMCM_LOCK_IN => GT0_TX_MMCM_LOCK_IN,
+ GT0_TX_MMCM_RESET_OUT => GT0_TX_MMCM_RESET_OUT,
+
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => gt0_cplllockdetclk_in,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => gt0_gtrefclk0_in,
+ gt0_gtrefclk1_in => gt0_gtrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => gt0_drpclk_in,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_in,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_out,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_in,
+ gt0_txusrclk2_in => gt0_txusrclk2_in,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_out,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
+ GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN
+
+);
+
+end RTL;
+
--- /dev/null
+--//////////////////////////////////////////////////////////////////////////////
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_auto_phase_align.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : The logic below implements the procedure to do automatic phase-alignment
+-- on the 7-series GTX as described in ug476pdf, version 1.3,
+-- Chapters "Using the TX Phase Alignment to Bypass the TX Buffer"
+-- and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer"
+-- Should the logic below differ from what is described in a later version
+-- of the user-guide, you are using an auto-alignment block, which is
+-- out of date and needs to be updated for safe operation.
+--
+--
+--
+-- Module gtxKintex7FEE80_AUTO_PHASE_ALIGN
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_AUTO_PHASE_ALIGN is
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Auto phase-alignment performed sucessfully
+ PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the
+ DLYSRESET : out STD_LOGIC; -- |transceiver.
+ DLYSRESETDONE : in STD_LOGIC; --/
+ RECCLKSTABLE : in STD_LOGIC --/on the RX-side.
+
+ );
+end gtxKintex7FEE80_AUTO_PHASE_ALIGN;
+
+architecture RTL of gtxKintex7FEE80_AUTO_PHASE_ALIGN is
+
+ component gtxKintex7FEE80_sync_block
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ type phase_align_auto_fsm is(
+ INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE
+ );
+
+ signal phalign_state : phase_align_auto_fsm := INIT;
+ signal phaligndone_prev : std_logic := '0';
+ signal phaligndone_ris_edge : std_logic;
+
+ signal count_phalign_edges : integer range 0 to 3:= 0;
+ signal phaligndone_sync : std_logic := '0';
+ signal dlysresetdone_sync : std_logic := '0';
+
+begin
+
+ sync_PHALIGNDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => PHALIGNDONE,
+ data_out => phaligndone_sync
+ );
+
+ sync_DLYSRESETDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => DLYSRESETDONE,
+ data_out => dlysresetdone_sync
+ );
+
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ phaligndone_prev <= phaligndone_sync;
+ end if;
+ end process;
+ phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0';
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then
+ DLYSRESET <= '0';
+ count_phalign_edges <= 0;
+ PHASE_ALIGNMENT_DONE <= '0';
+ phalign_state <= INIT;
+ else
+ if phaligndone_ris_edge = '1' then
+ if count_phalign_edges < 3 then
+ count_phalign_edges <= count_phalign_edges + 1;
+ end if;
+ end if;
+
+ DLYSRESET <= '0';
+
+ case phalign_state is
+ when INIT =>
+ PHASE_ALIGNMENT_DONE <= '0';
+ if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then
+ --DLYSRESET is toggled to '1'
+ DLYSRESET <= '1';
+ phalign_state <= WAIT_PHRST_DONE;
+ end if;
+
+ when WAIT_PHRST_DONE =>
+ if dlysresetdone_sync = '1' then
+ phalign_state <= COUNT_PHALIGN_DONE;
+ end if;
+ --No timeout-check here as that is done in the main FSM
+
+ when COUNT_PHALIGN_DONE =>
+ if (count_phalign_edges = 2) then
+
+ --For GTX: Only on the second edge of the PHALIGNDONE-signal the
+ -- phase-alignment is completed
+ --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment
+
+ phalign_state <= PHALIGN_DONE;
+ end if;
+
+ when PHALIGN_DONE =>
+ PHASE_ALIGNMENT_DONE <= '1';
+
+ when OTHERS =>
+ phalign_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_cpll_railing.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module gtxKintex7FEE80_cpll_railing
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity gtxKintex7FEE80_cpll_railing is
+generic( USE_BUFG : integer := 0
+ );
+ port (
+ cpll_reset_out : out std_logic;
+ cpll_pd_out : out std_logic;
+ refclk_out : out std_logic;
+
+ refclk_in : in std_logic
+ );
+ end gtxKintex7FEE80_cpll_railing;
+
+
+architecture RTL of gtxKintex7FEE80_cpll_railing is
+
+--**************************** Signal Declarations ****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+
+attribute equivalent_register_removal: string;
+signal cpllpd_wait : std_logic_vector(95 downto 0) := x"FFFFFFFFFFFFFFFFFFFFFFFF";
+signal cpllreset_wait : std_logic_vector(127 downto 0) := x"000000000000000000000000000000FF";
+attribute equivalent_register_removal of cpllpd_wait : signal is "no";
+attribute equivalent_register_removal of cpllreset_wait : signal is "no";
+signal gtrefclk0_i :std_logic ;
+--******************************** Main Body of Code***************************
+
+begin
+
+ --------------------------- Static signal Assignments ---------------------
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+
+ use_bufg_cpll:if(USE_BUFG = 1) generate
+ refclk_buf : BUFG
+ port map
+ (O => gtrefclk0_i,
+ I => refclk_in);
+
+ end generate;
+
+ use_bufr_cpll:if(USE_BUFG = 0) generate
+ refclk_buf : BUFR
+ port map
+ (O => gtrefclk0_i,
+ CE => tied_to_vcc_i,
+ CLR => tied_to_ground_i,
+ I => refclk_in);
+
+ end generate;
+
+ process( gtrefclk0_i )
+ begin
+ if(gtrefclk0_i'event and gtrefclk0_i = '1') then
+ cpllpd_wait <= cpllpd_wait(94 downto 0) & '0';
+ cpllreset_wait <= cpllreset_wait(126 downto 0) & '0';
+ end if;
+ end process;
+
+cpll_pd_out <= cpllpd_wait(95);
+cpll_reset_out <= cpllreset_wait(127);
+refclk_out <= gtrefclk0_i;
+
+
+ end RTL;
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_gt.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity gtxKintex7FEE80_GT is
+generic
+(
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
+ RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
+ SIM_CPLLREFCLK_SEL : bit_vector := "001";
+ PMA_RSV_IN : bit_vector := x"00018480";
+ PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
+);
+port
+(
+ cpllpd_in : in std_logic;
+ cpllrefclksel_in : in std_logic_vector(2 downto 0);
+ --------------------------------- CPLL Ports -------------------------------
+ cpllfbclklost_out : out std_logic;
+ cplllock_out : out std_logic;
+ cplllockdetclk_in : in std_logic;
+ cpllrefclklost_out : out std_logic;
+ cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gtrefclk0_in : in std_logic;
+ gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ drpaddr_in : in std_logic_vector(8 downto 0);
+ drpclk_in : in std_logic;
+ drpdi_in : in std_logic_vector(15 downto 0);
+ drpdo_out : out std_logic_vector(15 downto 0);
+ drpen_in : in std_logic;
+ drprdy_out : out std_logic;
+ drpwe_in : in std_logic;
+ ------------------------------- Clocking Ports -----------------------------
+ qpllclk_in : in std_logic;
+ qpllrefclk_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ eyescanreset_in : in std_logic;
+ rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ eyescandataerror_out : out std_logic;
+ eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN : in std_logic; --// Modified
+ RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ rxusrclk_in : in std_logic;
+ rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ rxdisperr_out : out std_logic_vector(1 downto 0);
+ rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ rxdlyen_in : in std_logic;
+ rxdlysreset_in : in std_logic;
+ rxdlysresetdone_out : out std_logic;
+ rxphalign_in : in std_logic;
+ rxphaligndone_out : out std_logic;
+ rxphalignen_in : in std_logic;
+ rxphdlyreset_in : in std_logic;
+ rxphmonitor_out : out std_logic_vector(4 downto 0);
+ rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ rxlpmhfhold_in : in std_logic;
+ rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ rxdfelpmreset_in : in std_logic;
+ rxmonitorout_out : out std_logic_vector(6 downto 0);
+ rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gtrxreset_in : in std_logic;
+ rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gttxreset_in : in std_logic;
+ txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ txusrclk_in : in std_logic;
+ txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ txdlyen_in : in std_logic;
+ txdlysreset_in : in std_logic;
+ txdlysresetdone_out : out std_logic;
+ txphalign_in : in std_logic;
+ txphaligndone_out : out std_logic;
+ txphalignen_in : in std_logic;
+ txphdlyreset_in : in std_logic;
+ txphinit_in : in std_logic;
+ txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gtxtxn_out : out std_logic;
+ gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ txoutclk_out : out std_logic;
+ txoutclkfabric_out : out std_logic;
+ txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ txresetdone_out : out std_logic
+
+
+);
+
+
+end gtxKintex7FEE80_GT;
+
+architecture RTL of gtxKintex7FEE80_GT is
+
+--**************************** Signal Declarations ****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+
+
+
+ -- RX Datapath signals
+ signal rxdata_i : std_logic_vector(63 downto 0);
+ signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
+ signal rxcharisk_float_i : std_logic_vector(5 downto 0);
+ signal rxdisperr_float_i : std_logic_vector(5 downto 0);
+ signal rxnotintable_float_i : std_logic_vector(5 downto 0);
+ signal rxrundisp_float_i : std_logic_vector(5 downto 0);
+
+
+ -- TX Datapath signals
+ signal txdata_i : std_logic_vector(63 downto 0);
+ signal txkerr_float_i : std_logic_vector(5 downto 0);
+ signal txrundisp_float_i : std_logic_vector(5 downto 0);
+ signal rxstartofseq_float_i : std_logic;
+--******************************** Main Body of Code***************************
+
+begin
+
+ --------------------------- Static signal Assignments ---------------------
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+
+ ------------------- GT Datapath byte mapping -----------------
+ RXDATA_OUT <= rxdata_i(15 downto 0);
+
+ txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+ ----------------------------- GTXE2 Instance --------------------------
+
+ gtxe2_i :GTXE2_CHANNEL
+ generic map
+ (
+
+ --_______________________ Simulation-Only Attributes ___________________
+
+ SIM_RECEIVER_DETECT_PASS => ("TRUE"),
+ SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
+ SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
+ SIM_CPLLREFCLK_SEL => (SIM_CPLLREFCLK_SEL),
+ SIM_VERSION => ("4.0"),
+
+
+ ------------------RX Byte and Word Alignment Attributes---------------
+ ALIGN_COMMA_DOUBLE => ("FALSE"),
+ ALIGN_COMMA_ENABLE => ("1111111111"),
+ ALIGN_COMMA_WORD => (1),
+ ALIGN_MCOMMA_DET => ("TRUE"),
+ ALIGN_MCOMMA_VALUE => ("1010000011"),
+ ALIGN_PCOMMA_DET => ("TRUE"),
+ ALIGN_PCOMMA_VALUE => ("0101111100"),
+ SHOW_REALIGN_COMMA => ("FALSE"),
+ RXSLIDE_AUTO_WAIT => (7),
+ RXSLIDE_MODE => ("AUTO"), --// ("PCS"), Modified
+ RX_SIG_VALID_DLY => (10),
+
+ ------------------RX 8B/10B Decoder Attributes---------------
+ RX_DISPERR_SEQ_MATCH => ("TRUE"),
+ DEC_MCOMMA_DETECT => ("TRUE"),
+ DEC_PCOMMA_DETECT => ("TRUE"),
+ DEC_VALID_COMMA_ONLY => ("FALSE"),
+
+ ------------------------RX Clock Correction Attributes----------------------
+ CBCC_DATA_SOURCE_SEL => ("DECODED"),
+ CLK_COR_SEQ_2_USE => ("FALSE"),
+ CLK_COR_KEEP_IDLE => ("FALSE"),
+ CLK_COR_MAX_LAT => (9),
+ CLK_COR_MIN_LAT => (7),
+ CLK_COR_PRECEDENCE => ("TRUE"),
+ CLK_COR_REPEAT_WAIT => (0),
+ CLK_COR_SEQ_LEN => (1),
+ CLK_COR_SEQ_1_ENABLE => ("1111"),
+ CLK_COR_SEQ_1_1 => ("0100000000"),
+ CLK_COR_SEQ_1_2 => ("0000000000"),
+ CLK_COR_SEQ_1_3 => ("0000000000"),
+ CLK_COR_SEQ_1_4 => ("0000000000"),
+ CLK_CORRECT_USE => ("FALSE"),
+ CLK_COR_SEQ_2_ENABLE => ("1111"),
+ CLK_COR_SEQ_2_1 => ("0100000000"),
+ CLK_COR_SEQ_2_2 => ("0000000000"),
+ CLK_COR_SEQ_2_3 => ("0000000000"),
+ CLK_COR_SEQ_2_4 => ("0000000000"),
+
+ ------------------------RX Channel Bonding Attributes----------------------
+ CHAN_BOND_KEEP_ALIGN => ("FALSE"),
+ CHAN_BOND_MAX_SKEW => (1),
+ CHAN_BOND_SEQ_LEN => (1),
+ CHAN_BOND_SEQ_1_1 => ("0000000000"),
+ CHAN_BOND_SEQ_1_2 => ("0000000000"),
+ CHAN_BOND_SEQ_1_3 => ("0000000000"),
+ CHAN_BOND_SEQ_1_4 => ("0000000000"),
+ CHAN_BOND_SEQ_1_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_1 => ("0000000000"),
+ CHAN_BOND_SEQ_2_2 => ("0000000000"),
+ CHAN_BOND_SEQ_2_3 => ("0000000000"),
+ CHAN_BOND_SEQ_2_4 => ("0000000000"),
+ CHAN_BOND_SEQ_2_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_USE => ("FALSE"),
+ FTS_DESKEW_SEQ_ENABLE => ("1111"),
+ FTS_LANE_DESKEW_CFG => ("1111"),
+ FTS_LANE_DESKEW_EN => ("FALSE"),
+
+ ---------------------------RX Margin Analysis Attributes----------------------------
+ ES_CONTROL => ("000000"),
+ ES_ERRDET_EN => ("FALSE"),
+ ES_EYE_SCAN_EN => ("TRUE"),
+ ES_HORZ_OFFSET => (x"000"),
+ ES_PMA_CFG => ("0000000000"),
+ ES_PRESCALE => ("00000"),
+ ES_QUALIFIER => (x"00000000000000000000"),
+ ES_QUAL_MASK => (x"00000000000000000000"),
+ ES_SDATA_MASK => (x"00000000000000000000"),
+ ES_VERT_OFFSET => ("000000000"),
+
+ -------------------------FPGA RX Interface Attributes-------------------------
+ RX_DATA_WIDTH => (20),
+
+ ---------------------------PMA Attributes----------------------------
+ OUTREFCLK_SEL_INV => ("11"),
+ PMA_RSV => (PMA_RSV_IN),
+ PMA_RSV2 => (x"2040"), --// was 2050
+ PMA_RSV3 => ("00"),
+ PMA_RSV4 => (x"00000000"),
+ RX_BIAS_CFG => ("000000000100"),
+ DMONITOR_CFG => (x"000A00"),
+ RX_CM_SEL => ("00"),
+ RX_CM_TRIM => ("000"), --// was 010
+ RX_DEBUG_CFG => ("000000000000"),
+ RX_OS_CFG => ("0000010000000"),
+ TERM_RCAL_CFG => ("10000"),
+ TERM_RCAL_OVRD => ('0'),
+ TST_RSV => (x"00000000"),
+ RX_CLK25_DIV => (4),
+ TX_CLK25_DIV => (4),
+ UCODEER_CLR => ('0'),
+
+ ---------------------------PCI Express Attributes----------------------------
+ PCS_PCIE_EN => ("FALSE"),
+
+ ---------------------------PCS Attributes----------------------------
+ PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
+
+ -------------RX Buffer Attributes------------
+ RXBUF_ADDR_MODE => ("FAST"),
+ RXBUF_EIDLE_HI_CNT => ("1000"),
+ RXBUF_EIDLE_LO_CNT => ("0000"),
+ RXBUF_EN => ("FALSE"),
+ RX_BUFFER_CFG => ("000000"),
+ RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
+ RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
+ RXBUF_RESET_ON_EIDLE => ("FALSE"),
+ RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
+ RXBUFRESET_TIME => ("00001"),
+ RXBUF_THRESH_OVFLW => (61),
+ RXBUF_THRESH_OVRD => ("FALSE"),
+ RXBUF_THRESH_UNDFLW => (4),
+ RXDLY_CFG => (x"001F"),
+ RXDLY_LCFG => (x"030"),
+ RXDLY_TAP_CFG => (x"0000"),
+ RXPH_CFG => (x"000000"),
+ RXPHDLY_CFG => (x"084020"),
+ RXPH_MONITOR_SEL => ("00000"),
+ RX_XCLK_SEL => ("RXUSR"),
+ RX_DDI_SEL => ("000000"),
+ RX_DEFER_RESET_BUF_EN => ("TRUE"),
+
+ -----------------------CDR Attributes-------------------------
+
+ --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+ --For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010
+
+ --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
+
+ --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
+
+ --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
+
+ --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
+
+ --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
+
+ --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
+ RXCDR_CFG => (x"03000023ff10200020"),
+ RXCDR_FR_RESET_ON_EIDLE => ('0'),
+ RXCDR_HOLD_DURING_EIDLE => ('0'),
+ RXCDR_PH_RESET_ON_EIDLE => ('0'),
+ RXCDR_LOCK_CFG => ("010101"),
+
+ -------------------RX Initialization and Reset Attributes-------------------
+ RXCDRFREQRESET_TIME => ("00001"),
+ RXCDRPHRESET_TIME => ("00001"),
+ RXISCANRESET_TIME => ("00001"),
+ RXPCSRESET_TIME => ("00001"),
+ RXPMARESET_TIME => ("00011"),
+
+ -------------------RX OOB Signaling Attributes-------------------
+ RXOOB_CFG => ("0000110"),
+
+ -------------------------RX Gearbox Attributes---------------------------
+ RXGEARBOX_EN => ("FALSE"),
+ GEARBOX_MODE => ("000"),
+
+ -------------------------PRBS Detection Attribute-----------------------
+ RXPRBS_ERR_LOOPBACK => ('0'),
+
+ -------------Power-Down Attributes----------
+ PD_TRANS_TIME_FROM_P2 => (x"03c"),
+ PD_TRANS_TIME_NONE_P2 => (x"3c"),
+ PD_TRANS_TIME_TO_P2 => (x"64"),
+
+ -------------RX OOB Signaling Attributes----------
+ SAS_MAX_COM => (64),
+ SAS_MIN_COM => (36),
+ SATA_BURST_SEQ_LEN => ("0101"),
+ SATA_BURST_VAL => ("100"),
+ SATA_EIDLE_VAL => ("100"),
+ SATA_MAX_BURST => (8),
+ SATA_MAX_INIT => (21),
+ SATA_MAX_WAKE => (7),
+ SATA_MIN_BURST => (4),
+ SATA_MIN_INIT => (12),
+ SATA_MIN_WAKE => (4),
+
+ -------------RX Fabric Clock Output Control Attributes----------
+ TRANS_TIME_RATE => (x"0E"),
+
+ --------------TX Buffer Attributes----------------
+ TXBUF_EN => ("FALSE"),
+ TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
+ TXDLY_CFG => (x"001F"),
+ TXDLY_LCFG => (x"030"),
+ TXDLY_TAP_CFG => (x"0000"),
+ TXPH_CFG => (x"0780"),
+ TXPHDLY_CFG => (x"084020"),
+ TXPH_MONITOR_SEL => ("00000"),
+ TX_XCLK_SEL => ("TXUSR"),
+
+ -------------------------FPGA TX Interface Attributes-------------------------
+ TX_DATA_WIDTH => (20),
+
+ -------------------------TX Configurable Driver Attributes-------------------------
+ TX_DEEMPH0 => ("00000"),
+ TX_DEEMPH1 => ("00000"),
+ TX_EIDLE_ASSERT_DELAY => ("110"),
+ TX_EIDLE_DEASSERT_DELAY => ("100"),
+ TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
+ TX_MAINCURSOR_SEL => ('0'),
+ TX_DRIVE_MODE => ("DIRECT"),
+ TX_MARGIN_FULL_0 => ("1001110"),
+ TX_MARGIN_FULL_1 => ("1001001"),
+ TX_MARGIN_FULL_2 => ("1000101"),
+ TX_MARGIN_FULL_3 => ("1000010"),
+ TX_MARGIN_FULL_4 => ("1000000"),
+ TX_MARGIN_LOW_0 => ("1000110"),
+ TX_MARGIN_LOW_1 => ("1000100"),
+ TX_MARGIN_LOW_2 => ("1000010"),
+ TX_MARGIN_LOW_3 => ("1000000"),
+ TX_MARGIN_LOW_4 => ("1000000"),
+
+ -------------------------TX Gearbox Attributes--------------------------
+ TXGEARBOX_EN => ("FALSE"),
+
+ -------------------------TX Initialization and Reset Attributes--------------------------
+ TXPCSRESET_TIME => ("00001"),
+ TXPMARESET_TIME => ("00001"),
+
+ -------------------------TX Receiver Detection Attributes--------------------------
+ TX_RXDETECT_CFG => (x"1832"),
+ TX_RXDETECT_REF => ("100"),
+
+ ----------------------------CPLL Attributes----------------------------
+ CPLL_CFG => (x"BC07DC"),
+ CPLL_FBDIV => (5),
+ CPLL_FBDIV_45 => (5),
+ CPLL_INIT_CFG => (x"00001E"),
+ CPLL_LOCK_CFG => (x"01E8"),
+ CPLL_REFCLK_DIV => (1),
+ RXOUT_DIV => (2),
+ TXOUT_DIV => (2),
+ SATA_CPLL_CFG => ("VCO_3000MHZ"),
+
+ --------------RX Initialization and Reset Attributes-------------
+ RXDFELPMRESET_TIME => ("0001111"),
+
+ --------------RX Equalizer Attributes-------------
+ RXLPM_HF_CFG => ("00000011110000"),
+ RXLPM_LF_CFG => ("00000011110000"),
+ RX_DFE_GAIN_CFG => (x"020FEA"),
+ RX_DFE_H2_CFG => ("000000000000"),
+ RX_DFE_H3_CFG => ("000001000000"),
+ RX_DFE_H4_CFG => ("00011110000"),
+ RX_DFE_H5_CFG => ("00011100000"),
+ RX_DFE_KL_CFG => ("0000011111110"),
+ RX_DFE_LPM_CFG => (x"0904"),
+ RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
+ RX_DFE_UT_CFG => ("10001111000000000"),
+ RX_DFE_VP_CFG => ("00011111100000011"),
+
+ -------------------------Power-Down Attributes-------------------------
+ RX_CLKMUX_PD => ('1'),
+ TX_CLKMUX_PD => ('1'),
+
+ -------------------------FPGA RX Interface Attribute-------------------------
+ RX_INT_DATAWIDTH => (0),
+
+ -------------------------FPGA TX Interface Attribute-------------------------
+ TX_INT_DATAWIDTH => (0),
+
+ ------------------TX Configurable Driver Attributes---------------
+ TX_QPI_STATUS_EN => ('0'),
+
+ -------------------------RX Equalizer Attributes--------------------------
+ RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
+ RX_DFE_XYD_CFG => ("0000000000000"),
+
+ -------------------------TX Configurable Driver Attributes--------------------------
+ TX_PREDRIVER_MODE => ('0')
+
+
+ )
+ port map
+ (
+ --------------------------------- CPLL Ports -------------------------------
+ CPLLFBCLKLOST => cpllfbclklost_out,
+ CPLLLOCK => cplllock_out,
+ CPLLLOCKDETCLK => cplllockdetclk_in,
+ CPLLLOCKEN => tied_to_vcc_i,
+ CPLLPD => cpllpd_in,
+ CPLLREFCLKLOST => cpllrefclklost_out,
+ CPLLREFCLKSEL => cpllrefclksel_in,
+ CPLLRESET => cpllreset_in,
+ GTRSVD => "0000000000000000",
+ PCSRSVDIN => "0000000000000000",
+ PCSRSVDIN2 => "00000",
+ PMARSVDIN => "00000",
+ PMARSVDIN2 => "00000",
+ TSTIN => "11111111111111111111",
+ TSTOUT => open,
+ ---------------------------------- Channel ---------------------------------
+ CLKRSVD => tied_to_ground_vec_i(3 downto 0),
+ -------------------------- Channel - Clocking Ports ------------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => gtrefclk0_in,
+ GTREFCLK1 => gtrefclk1_in,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ DRPADDR => drpaddr_in,
+ DRPCLK => drpclk_in,
+ DRPDI => drpdi_in,
+ DRPDO => drpdo_out,
+ DRPEN => drpen_in,
+ DRPRDY => drprdy_out,
+ DRPWE => drpwe_in,
+ ------------------------------- Clocking Ports -----------------------------
+ GTREFCLKMONITOR => open,
+ QPLLCLK => qpllclk_in,
+ QPLLREFCLK => qpllrefclk_in,
+ RXSYSCLKSEL => "00",
+ TXSYSCLKSEL => "00",
+ --------------------------- Digital Monitor Ports --------------------------
+ DMONITOROUT => dmonitorout_out,
+ ----------------- FPGA TX Interface Datapath Configuration ----------------
+ TX8B10BEN => tied_to_vcc_i,
+ ------------------------------- Loopback Ports -----------------------------
+ LOOPBACK => tied_to_ground_vec_i(2 downto 0),
+ ----------------------------- PCI Express Ports ----------------------------
+ PHYSTATUS => open,
+ RXRATE => tied_to_ground_vec_i(2 downto 0),
+ RXVALID => open,
+ ------------------------------ Power-Down Ports ----------------------------
+ RXPD => "00",
+ TXPD => "00",
+ -------------------------- RX 8B/10B Decoder Ports -------------------------
+ SETERRSTATUS => tied_to_ground_i,
+ --------------------- RX Initialization and Reset Ports --------------------
+ EYESCANRESET => eyescanreset_in,
+ RXUSERRDY => rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ EYESCANDATAERROR => eyescandataerror_out,
+ EYESCANMODE => tied_to_ground_i,
+ EYESCANTRIGGER => eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRFREQRESET => tied_to_ground_i,
+ RXCDRHOLD => tied_to_ground_i,
+ RXCDRLOCK => RXCDRLOCK_OUT, --// Modified
+ RXCDROVRDEN => tied_to_ground_i,
+ RXCDRRESET => RXCDRRESET_IN, --// Modified tied_to_ground_i,
+ RXCDRRESETRSV => tied_to_ground_i,
+ ------------------- Receive Ports - Clock Correction Ports -----------------
+ RXCLKCORCNT => open,
+ ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+ RX8B10BEN => tied_to_vcc_i,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ RXUSRCLK => rxusrclk_in,
+ RXUSRCLK2 => rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ RXDATA => rxdata_i,
+ ------------------- Receive Ports - Pattern Checker Ports ------------------
+ RXPRBSERR => open,
+ RXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
+ ------------------- Receive Ports - Pattern Checker ports ------------------
+ RXPRBSCNTRESET => tied_to_ground_i,
+ -------------------- Receive Ports - RX Equalizer Ports -------------------
+ RXDFEXYDEN => tied_to_vcc_i,
+ RXDFEXYDHOLD => tied_to_ground_i,
+ RXDFEXYDOVRDEN => tied_to_ground_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ RXDISPERR(7 downto 2) => rxdisperr_float_i,
+ RXDISPERR(1 downto 0) => rxdisperr_out,
+ RXNOTINTABLE(7 downto 2) => rxnotintable_float_i,
+ RXNOTINTABLE(1 downto 0) => rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GTXRXP => gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GTXRXN => gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ RXBUFRESET => tied_to_ground_i,
+ RXBUFSTATUS => open,
+ RXDDIEN => tied_to_vcc_i,
+ RXDLYBYPASS => tied_to_ground_i,
+ RXDLYEN => rxdlyen_in,
+ RXDLYOVRDEN => tied_to_ground_i,
+ RXDLYSRESET => rxdlysreset_in,
+ RXDLYSRESETDONE => rxdlysresetdone_out,
+ RXPHALIGN => rxphalign_in,
+ RXPHALIGNDONE => rxphaligndone_out,
+ RXPHALIGNEN => rxphalignen_in,
+ RXPHDLYPD => tied_to_ground_i,
+ RXPHDLYRESET => rxphdlyreset_in,
+ RXPHMONITOR => rxphmonitor_out,
+ RXPHOVRDEN => tied_to_ground_i,
+ RXPHSLIPMONITOR => rxphslipmonitor_out,
+ RXSTATUS => open,
+ -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+ RXBYTEISALIGNED => open,
+ RXBYTEREALIGN => open,
+ RXCOMMADET => open,
+ RXCOMMADETEN => tied_to_vcc_i,
+ RXMCOMMAALIGNEN => tied_to_vcc_i,
+ RXPCOMMAALIGNEN => tied_to_vcc_i,
+ ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+ RXCHANBONDSEQ => open,
+ RXCHBONDEN => tied_to_ground_i,
+ RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
+ RXCHBONDMASTER => tied_to_ground_i,
+ RXCHBONDO => open,
+ RXCHBONDSLAVE => tied_to_ground_i,
+ ----------------- Receive Ports - RX Channel Bonding Ports ----------------
+ RXCHANISALIGNED => open,
+ RXCHANREALIGN => open,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ RXLPMHFHOLD => rxlpmhfhold_in,
+ RXLPMHFOVRDEN => tied_to_ground_i,
+ RXLPMLFHOLD => rxlpmlfhold_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ RXDFEAGCHOLD => tied_to_ground_i,
+ RXDFEAGCOVRDEN => tied_to_ground_i,
+ RXDFECM1EN => tied_to_ground_i,
+ RXDFELFHOLD => tied_to_ground_i,
+ RXDFELFOVRDEN => tied_to_ground_i,
+ RXDFELPMRESET => rxdfelpmreset_in,
+ RXDFETAP2HOLD => tied_to_ground_i,
+ RXDFETAP2OVRDEN => tied_to_ground_i,
+ RXDFETAP3HOLD => tied_to_ground_i,
+ RXDFETAP3OVRDEN => tied_to_ground_i,
+ RXDFETAP4HOLD => tied_to_ground_i,
+ RXDFETAP4OVRDEN => tied_to_ground_i,
+ RXDFETAP5HOLD => tied_to_ground_i,
+ RXDFETAP5OVRDEN => tied_to_ground_i,
+ RXDFEUTHOLD => tied_to_ground_i,
+ RXDFEUTOVRDEN => tied_to_ground_i,
+ RXDFEVPHOLD => tied_to_ground_i,
+ RXDFEVPOVRDEN => tied_to_ground_i,
+ RXDFEVSEN => tied_to_ground_i,
+ RXLPMLFKLOVRDEN => tied_to_ground_i,
+ RXMONITOROUT => rxmonitorout_out,
+ RXMONITORSEL => rxmonitorsel_in,
+ RXOSHOLD => tied_to_ground_i,
+ RXOSOVRDEN => tied_to_ground_i,
+ ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+ RXRATEDONE => open,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ RXOUTCLK => rxoutclk_out,
+ RXOUTCLKFABRIC => open,
+ RXOUTCLKPCS => open,
+ RXOUTCLKSEL => "010",
+ ---------------------- Receive Ports - RX Gearbox Ports --------------------
+ RXDATAVALID => open,
+ RXHEADER => open,
+ RXHEADERVALID => open,
+ RXSTARTOFSEQ => open,
+ --------------------- Receive Ports - RX Gearbox Ports --------------------
+ RXGEARBOXSLIP => tied_to_ground_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GTRXRESET => gtrxreset_in,
+ RXOOBRESET => tied_to_ground_i,
+ RXPCSRESET => tied_to_ground_i,
+ RXPMARESET => rxpmareset_in,
+ ------------------ Receive Ports - RX Margin Analysis ports ----------------
+ RXLPMEN => tied_to_vcc_i,
+ ------------------- Receive Ports - RX OOB Signaling ports -----------------
+ RXCOMSASDET => open,
+ RXCOMWAKEDET => open,
+ ------------------ Receive Ports - RX OOB Signaling ports -----------------
+ RXCOMINITDET => open,
+ ------------------ Receive Ports - RX OOB signalling Ports -----------------
+ RXELECIDLE => open,
+ RXELECIDLEMODE => "11",
+ ----------------- Receive Ports - RX Polarity Control Ports ----------------
+ RXPOLARITY => tied_to_ground_i,
+ ---------------------- Receive Ports - RX gearbox ports --------------------
+ RXSLIDE => tied_to_ground_i,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ RXCHARISCOMMA => open,
+ RXCHARISK(7 downto 2) => rxcharisk_float_i,
+ RXCHARISK(1 downto 0) => rxcharisk_out,
+ ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+ RXCHBONDI => "00000",
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ RXRESETDONE => rxresetdone_out,
+ -------------------------------- Rx AFE Ports ------------------------------
+ RXQPIEN => tied_to_ground_i,
+ RXQPISENN => open,
+ RXQPISENP => open,
+ --------------------------- TX Buffer Bypass Ports -------------------------
+ TXPHDLYTSTCLK => tied_to_ground_i,
+ ------------------------ TX Configurable Driver Ports ----------------------
+ TXPOSTCURSOR => "00000",
+ TXPOSTCURSORINV => tied_to_ground_i,
+ TXPRECURSOR => tied_to_ground_vec_i(4 downto 0),
+ TXPRECURSORINV => tied_to_ground_i,
+ TXQPIBIASEN => tied_to_ground_i,
+ TXQPISTRONGPDOWN => tied_to_ground_i,
+ TXQPIWEAKPUP => tied_to_ground_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ CFGRESET => tied_to_ground_i,
+ GTTXRESET => gttxreset_in,
+ PCSRSVDOUT => open,
+ TXUSERRDY => txuserrdy_in,
+ ---------------------- Transceiver Reset Mode Operation --------------------
+ GTRESETSEL => tied_to_ground_i,
+ RESETOVRD => tied_to_ground_i,
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ TXCHARDISPMODE => tied_to_ground_vec_i(7 downto 0),
+ TXCHARDISPVAL => tied_to_ground_vec_i(7 downto 0),
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ TXUSRCLK => txusrclk_in,
+ TXUSRCLK2 => txusrclk2_in,
+ --------------------- Transmit Ports - PCI Express Ports -------------------
+ TXELECIDLE => tied_to_ground_i,
+ TXMARGIN => tied_to_ground_vec_i(2 downto 0),
+ TXRATE => tied_to_ground_vec_i(2 downto 0),
+ TXSWING => tied_to_ground_i,
+ ------------------ Transmit Ports - Pattern Generator Ports ----------------
+ TXPRBSFORCEERR => tied_to_ground_i,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ TXDLYBYPASS => tied_to_ground_i,
+ TXDLYEN => txdlyen_in,
+ TXDLYHOLD => tied_to_ground_i,
+ TXDLYOVRDEN => tied_to_ground_i,
+ TXDLYSRESET => txdlysreset_in,
+ TXDLYSRESETDONE => txdlysresetdone_out,
+ TXDLYUPDOWN => tied_to_ground_i,
+ TXPHALIGN => txphalign_in,
+ TXPHALIGNDONE => txphaligndone_out,
+ TXPHALIGNEN => txphalignen_in,
+ TXPHDLYPD => tied_to_ground_i,
+ TXPHDLYRESET => txphdlyreset_in,
+ TXPHINIT => txphinit_in,
+ TXPHINITDONE => txphinitdone_out,
+ TXPHOVRDEN => tied_to_ground_i,
+ ---------------------- Transmit Ports - TX Buffer Ports --------------------
+ TXBUFSTATUS => open,
+ --------------- Transmit Ports - TX Configurable Driver Ports --------------
+ TXBUFDIFFCTRL => "100",
+ TXDEEMPH => tied_to_ground_i,
+ TXDIFFCTRL => "1000",
+ TXDIFFPD => tied_to_ground_i,
+ TXINHIBIT => tied_to_ground_i,
+ TXMAINCURSOR => "0000000",
+ TXPISOPD => tied_to_ground_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA => txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTXTXN => gtxtxn_out,
+ GTXTXP => gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ TXOUTCLK => txoutclk_out,
+ TXOUTCLKFABRIC => txoutclkfabric_out,
+ TXOUTCLKPCS => txoutclkpcs_out,
+ TXOUTCLKSEL => "011",
+ TXRATEDONE => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ TXCHARISK(7 downto 2) => tied_to_ground_vec_i(5 downto 0),
+ TXCHARISK(1 downto 0) => txcharisk_in,
+ TXGEARBOXREADY => open,
+ TXHEADER => tied_to_ground_vec_i(2 downto 0),
+ TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
+ TXSTARTSEQ => tied_to_ground_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ TXPCSRESET => tied_to_ground_i,
+ TXPMARESET => tied_to_ground_i,
+ TXRESETDONE => txresetdone_out,
+ ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+ TXCOMFINISH => open,
+ TXCOMINIT => tied_to_ground_i,
+ TXCOMSAS => tied_to_ground_i,
+ TXCOMWAKE => tied_to_ground_i,
+ TXPDELECIDLEMODE => tied_to_ground_i,
+ ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+ TXPOLARITY => tied_to_ground_i,
+ --------------- Transmit Ports - TX Receiver Detection Ports --------------
+ TXDETECTRX => tied_to_ground_i,
+ ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+ TX8B10BBYPASS => tied_to_ground_vec_i(7 downto 0),
+ ------------------ Transmit Ports - pattern Generator Ports ----------------
+ TXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
+ ----------------------- Tx Configurable Driver Ports ----------------------
+ TXQPISENN => open,
+ TXQPISENP => open
+
+ );
+
+
+ end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_init.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module gtxKintex7FEE80_init
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity gtxKintex7FEE80_init is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+
+ STABLE_CLOCK_PERIOD : integer := 12;
+ -- Set to 1 for simulation
+ EXAMPLE_USE_CHIPSCOPE : integer := 1 --// Modified -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end gtxKintex7FEE80_init;
+
+architecture RTL of gtxKintex7FEE80_init is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+
+component gtxKintex7FEE80_multi_gt
+generic
+(
+ -- Simulation attributes
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
+
+);
+port
+(
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllrefclklost_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxdlyen_in : in std_logic;
+ gt0_rxdlysreset_in : in std_logic;
+ gt0_rxdlysresetdone_out : out std_logic;
+ gt0_rxphalign_in : in std_logic;
+ gt0_rxphaligndone_out : out std_logic;
+ gt0_rxphalignen_in : in std_logic;
+ gt0_rxphdlyreset_in : in std_logic;
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ gt0_rxlpmhfhold_in : in std_logic;
+ gt0_rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ gt0_txdlyen_in : in std_logic;
+ gt0_txdlysreset_in : in std_logic;
+ gt0_txdlysresetdone_out : out std_logic;
+ gt0_txphalign_in : in std_logic;
+ gt0_txphaligndone_out : out std_logic;
+ gt0_txphalignen_in : in std_logic;
+ gt0_txphdlyreset_in : in std_logic;
+ gt0_txphinit_in : in std_logic;
+ gt0_txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end component;
+
+component gtxKintex7FEE80_TX_STARTUP_FSM
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ TXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ GTTXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='0';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
+ TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
+ TXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC:='0';
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ PHALIGNMENT_DONE : in STD_LOGIC;
+
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end component;
+
+component gtxKintex7FEE80_RX_STARTUP_FSM
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ EQ_MODE : string := "DFE";
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ RXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ RECCLK_STABLE : in STD_LOGIC;
+ RECCLK_MONITOR_RESTART : in STD_LOGIC;
+ DATA_VALID : in STD_LOGIC;
+ TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
+ DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
+ GTRXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='0';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
+ RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
+ RXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC;
+ PHALIGNMENT_DONE : in STD_LOGIC;
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ RXDFEAGCHOLD : out STD_LOGIC;
+ RXDFELFHOLD : out STD_LOGIC;
+ RXLPMLFHOLD : out STD_LOGIC;
+ RXLPMHFHOLD : out STD_LOGIC;
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end component;
+
+
+
+
+component gtxKintex7FEE80_AUTO_PHASE_ALIGN
+ port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC; -- Auto phase-alignment performed sucessfully
+ PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the
+ DLYSRESET : out STD_LOGIC; -- |transceiver.
+ DLYSRESETDONE : in STD_LOGIC; --/
+ RECCLKSTABLE : in STD_LOGIC --/on the RX-side.
+
+ );
+end component;
+
+
+component gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ TXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHINIT : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHINITDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end component;
+
+component gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ RXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end component;
+
+ function get_cdrlock_time(is_sim : in integer) return integer is
+ variable lock_time: integer;
+ begin
+ if (is_sim = 1) then
+ lock_time := 1000;
+ else
+ lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183
+ end if;
+ return lock_time;
+ end function;
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+ constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
+ constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
+
+
+
+ -------------------------- GT Wrapper Wires ------------------------------
+ signal gt0_txpmaresetdone_i : std_logic;
+ signal gt0_rxpmaresetdone_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ signal gt0_cpllreset_t : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_txresetdone_i : std_logic;
+ signal gt0_rxresetdone_i : std_logic;
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_gttxreset_t : std_logic;
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_gtrxreset_t : std_logic;
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ signal gt0_txuserrdy_t : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ signal gt0_rxuserrdy_t : std_logic;
+
+ signal gt0_rxdfeagchold_i : std_logic;
+ signal gt0_rxdfelfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ signal gt0_rxlpmhfhold_i : std_logic;
+
+
+
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qplllock_i : std_logic;
+
+
+ ------------------------------- Global Signals -----------------------------
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ signal gt0_run_tx_phalignment_i : std_logic;
+ signal gt0_rst_tx_phalignment_i : std_logic;
+ signal gt0_tx_phalignment_done_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+ signal gt0_rxoutclk_i2 : std_logic;
+ signal gt0_txoutclk_i2 : std_logic;
+ signal gt0_recclk_stable_i : std_logic;
+ signal gt0_rx_cdrlocked : std_logic;
+ signal gt0_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_run_rx_phalignment_i : std_logic;
+ signal gt0_rst_rx_phalignment_i : std_logic;
+ signal gt0_rx_phalignment_done_i : std_logic;
+
+
+
+ --------------------------- TX Buffer Bypass Signals --------------------
+ signal mstr0_txsyncallin_i : std_logic;
+ signal U0_TXDLYEN : std_logic_vector(0 downto 0);
+ signal U0_TXDLYSRESET : std_logic_vector(0 downto 0);
+ signal U0_TXDLYSRESETDONE : std_logic_vector(0 downto 0);
+ signal U0_TXPHINIT : std_logic_vector(0 downto 0);
+ signal U0_TXPHINITDONE : std_logic_vector(0 downto 0);
+ signal U0_TXPHALIGN : std_logic_vector(0 downto 0);
+ signal U0_TXPHALIGNDONE : std_logic_vector(0 downto 0);
+ signal U0_run_tx_phalignment_i : std_logic;
+ signal U0_rst_tx_phalignment_i : std_logic;
+
+
+ --------------------------- RX Buffer Bypass Signals --------------------
+ signal rxmstr0_rxsyncallin_i : std_logic;
+ signal U0_RXDLYEN : std_logic_vector(0 downto 0);
+ signal U0_RXDLYSRESET : std_logic_vector(0 downto 0);
+ signal U0_RXDLYSRESETDONE : std_logic_vector(0 downto 0);
+ signal U0_RXPHALIGN : std_logic_vector(0 downto 0);
+ signal U0_RXPHALIGNDONE : std_logic_vector(0 downto 0);
+ signal U0_run_rx_phalignment_i : std_logic;
+ signal U0_rst_rx_phalignment_i : std_logic;
+
+
+
+ signal rx_cdrlocked : std_logic;
+
+
+
+
+
+--**************************** Main Body of Code *******************************
+begin
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+
+ ----------------------------- The GT Wrapper -----------------------------
+
+ -- Use the instantiation template in the example directory to add the GT wrapper to your design.
+ -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
+ -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
+ -- enabled, bonding should occur after alignment.
+
+
+ gtxKintex7FEE80_i : gtxKintex7FEE80_multi_gt
+ generic map
+ (
+ USE_BUFG => USE_BUFG,
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
+ )
+ port map
+ (
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y0)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_i,
+ gt0_cplllockdetclk_in => gt0_cplllockdetclk_in,
+ gt0_cpllrefclklost_out => gt0_cpllrefclklost_i,
+ gt0_cpllreset_in => gt0_cpllreset_i,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => gt0_gtrefclk0_in,
+ gt0_gtrefclk1_in => gt0_gtrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => gt0_drpclk_in,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_i,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_in,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxdlyen_in => gt0_rxdlyen_i,
+ gt0_rxdlysreset_in => gt0_rxdlysreset_i,
+ gt0_rxdlysresetdone_out => gt0_rxdlysresetdone_i,
+ gt0_rxphalign_in => gt0_rxphalign_i,
+ gt0_rxphaligndone_out => gt0_rxphaligndone_i,
+ gt0_rxphalignen_in => gt0_rxphalignen_i,
+ gt0_rxphdlyreset_in => gt0_rxphdlyreset_i,
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ gt0_rxlpmhfhold_in => gt0_rxlpmhfhold_i,
+ gt0_rxlpmlfhold_in => gt0_rxlpmlfhold_i,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_i,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_i,
+ gt0_txuserrdy_in => gt0_txuserrdy_i,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_in,
+ gt0_txusrclk2_in => gt0_txusrclk2_in,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ gt0_txdlyen_in => gt0_txdlyen_i,
+ gt0_txdlysreset_in => gt0_txdlysreset_i,
+ gt0_txdlysresetdone_out => gt0_txdlysresetdone_i,
+ gt0_txphalign_in => gt0_txphalign_i,
+ gt0_txphaligndone_out => gt0_txphaligndone_i,
+ gt0_txphalignen_in => gt0_txphalignen_i,
+ gt0_txphdlyreset_in => gt0_txphdlyreset_i,
+ gt0_txphinit_in => gt0_txphinit_i,
+ gt0_txphinitdone_out => gt0_txphinitdone_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_i,
+
+
+
+
+ --____________________________COMMON PORTS________________________________
+ gt0_qplloutclk_in => gt0_qplloutclk_in,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_in
+ );
+
+
+gt0_rxdfelpmreset_i <= tied_to_ground_i;
+
+
+GT0_CPLLLOCK_OUT <= gt0_cplllock_i;
+GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
+GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
+GT0_RXOUTCLK_OUT <= gt0_rxoutclk_i;
+GT0_TXOUTCLK_OUT <= gt0_txoutclk_i;
+
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
+gt0_cpllreset_i <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
+ gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
+ gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
+ gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
+ gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
+end generate chipscope;
+
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
+gt0_cpllreset_i <= gt0_cpllreset_t;
+gt0_gttxreset_i <= gt0_gttxreset_t;
+gt0_gtrxreset_i <= gt0_gtrxreset_t;
+gt0_txuserrdy_i <= gt0_txuserrdy_t;
+gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
+end generate no_chipscope;
+
+
+gt0_txresetfsm_i: gtxKintex7FEE80_TX_STARTUP_FSM
+
+ generic map(
+ EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
+ STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH => 8,
+ TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
+ RX_QPLL_USED => FALSE, -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL => TRUE -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ )
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ TXUSERCLK => GT0_TXUSRCLK_IN,
+ SOFT_RESET => SOFT_RESET_TX_IN,
+ QPLLREFCLKLOST => tied_to_ground_i,
+ CPLLREFCLKLOST => gt0_cpllrefclklost_i,
+ QPLLLOCK => tied_to_vcc_i,
+ CPLLLOCK => gt0_cplllock_i,
+ TXRESETDONE => gt0_txresetdone_i,
+ MMCM_LOCK => GT0_TX_MMCM_LOCK_IN,
+ GTTXRESET => gt0_gttxreset_t,
+ MMCM_RESET => GT0_TX_MMCM_RESET_OUT,
+ QPLL_RESET => open,
+ CPLL_RESET => gt0_cpllreset_t,
+ TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT,
+ TXUSERRDY => gt0_txuserrdy_t,
+ RUN_PHALIGNMENT => gt0_run_tx_phalignment_i,
+ RESET_PHALIGNMENT => gt0_rst_tx_phalignment_i,
+ PHALIGNMENT_DONE => gt0_tx_phalignment_done_i,
+ RETRY_COUNTER => open
+ );
+
+
+
+
+
+
+
+
+gt0_rxresetfsm_i: gtxKintex7FEE80_RX_STARTUP_FSM
+
+ generic map(
+ EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
+ EQ_MODE => "LPM", --Rx Equalization Mode - Set to DFE or LPM
+ STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH => 8,
+ TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
+ RX_QPLL_USED => FALSE, -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ )
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ RXUSERCLK => GT0_RXUSRCLK_IN,
+ SOFT_RESET => SOFT_RESET_RX_IN,
+ DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
+ QPLLREFCLKLOST => tied_to_ground_i,
+ CPLLREFCLKLOST => gt0_cpllrefclklost_i,
+ QPLLLOCK => tied_to_vcc_i,
+ CPLLLOCK => gt0_cplllock_i,
+ RXRESETDONE => gt0_rxresetdone_i,
+ MMCM_LOCK => tied_to_vcc_i,
+ RECCLK_STABLE => gt0_recclk_stable_i,
+ RECCLK_MONITOR_RESTART => tied_to_ground_i,
+ DATA_VALID => GT0_DATA_VALID_IN,
+ TXUSERRDY => tied_to_vcc_i,
+ GTRXRESET => gt0_gtrxreset_t,
+ MMCM_RESET => open,
+ QPLL_RESET => open,
+ CPLL_RESET => open,
+ RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT,
+ RXUSERRDY => gt0_rxuserrdy_t,
+ RUN_PHALIGNMENT => gt0_run_rx_phalignment_i,
+ RESET_PHALIGNMENT => gt0_rst_rx_phalignment_i,
+ PHALIGNMENT_DONE => gt0_rx_phalignment_done_i,
+ RXDFEAGCHOLD => gt0_rxdfeagchold_i,
+ RXDFELFHOLD => gt0_rxdfelfhold_i,
+ RXLPMLFHOLD => gt0_rxlpmlfhold_i,
+ RXLPMHFHOLD => gt0_rxlpmhfhold_i,
+ RETRY_COUNTER => open
+ );
+
+
+
+ gt0_cdrlock_timeout:process(SYSCLK_IN)
+ begin
+ if rising_edge(SYSCLK_IN) then
+ if(gt0_gtrxreset_i = '1') then
+ gt0_rx_cdrlocked <= '0';
+ gt0_rx_cdrlock_counter <= 0 after DLY;
+ elsif (gt0_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
+ gt0_rx_cdrlocked <= '1';
+ gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter after DLY;
+ else
+ gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter + 1 after DLY;
+ end if;
+ end if;
+ end process;
+
+gt0_recclk_stable_i <= gt0_rx_cdrlocked;
+
+
+
+ --------------------------- TX Buffer Bypass Logic --------------------
+ -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer.
+ -- Include the TX SYNC module in your own design if TX Buffer is bypassed.
+
+
+--Auto
+gt0_txphdlyreset_i <= tied_to_ground_i;
+gt0_txphalignen_i <= tied_to_ground_i;
+gt0_txdlyen_i <= tied_to_ground_i;
+gt0_txphalign_i <= tied_to_ground_i;
+gt0_txphinit_i <= tied_to_ground_i;
+
+gt0_tx_auto_phase_align_i : gtxKintex7FEE80_AUTO_PHASE_ALIGN
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ RUN_PHALIGNMENT => gt0_run_tx_phalignment_i,
+ PHASE_ALIGNMENT_DONE => gt0_tx_phalignment_done_i,
+ PHALIGNDONE => gt0_txphaligndone_i,
+ DLYSRESET => gt0_txdlysreset_i,
+ DLYSRESETDONE => gt0_txdlysresetdone_i,
+ RECCLKSTABLE => tied_to_vcc_i
+ );
+
+
+
+
+ --------------------------- RX Buffer Bypass Logic --------------------
+-- The RX SYNC Module drives the ports needed to Bypass the RX Buffer.
+-- Include the RX SYNC module in your own design if RX Buffer is bypassed.
+
+
+--Auto
+gt0_rxphdlyreset_i <= '1'; --// Modified??????? tied_to_ground_i;
+gt0_rxphalignen_i <= '1'; --// Modified??????? tied_to_ground_i;
+gt0_rxdlyen_i <= tied_to_ground_i;
+gt0_rxphalign_i <= tied_to_ground_i;
+
+
+gt0_rx_phalignment_done_i <= '1'; --// Modified
+gt0_rxdlysreset_i <= '1'; --// Modified
+-- gt0_rx_auto_phase_align_i : gtxKintex7FEE80_AUTO_PHASE_ALIGN
+ -- port map (
+ -- STABLE_CLOCK => SYSCLK_IN,
+ -- RUN_PHALIGNMENT => gt0_run_rx_phalignment_i,
+ -- PHASE_ALIGNMENT_DONE => gt0_rx_phalignment_done_i,
+ -- PHALIGNDONE => gt0_rxphaligndone_i,
+ -- DLYSRESET => gt0_rxdlysreset_i,
+ -- DLYSRESETDONE => gt0_rxdlysresetdone_i,
+ -- RECCLKSTABLE => gt0_recclk_stable_i
+ -- );
+
+
+
+end RTL;
+
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_multi_gt.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_multi_gt (a Multi GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity gtxKintex7FEE80_multi_gt is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
+ RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+
+ PMA_RSV_IN : bit_vector := x"00018480"
+);
+port
+(
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X0Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllrefclklost_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxdlyen_in : in std_logic;
+ gt0_rxdlysreset_in : in std_logic;
+ gt0_rxdlysresetdone_out : out std_logic;
+ gt0_rxphalign_in : in std_logic;
+ gt0_rxphaligndone_out : out std_logic;
+ gt0_rxphalignen_in : in std_logic;
+ gt0_rxphdlyreset_in : in std_logic;
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ gt0_rxlpmhfhold_in : in std_logic;
+ gt0_rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ gt0_txdlyen_in : in std_logic;
+ gt0_txdlysreset_in : in std_logic;
+ gt0_txdlysresetdone_out : out std_logic;
+ gt0_txphalign_in : in std_logic;
+ gt0_txphaligndone_out : out std_logic;
+ gt0_txphalignen_in : in std_logic;
+ gt0_txphdlyreset_in : in std_logic;
+ gt0_txphinit_in : in std_logic;
+ gt0_txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+
+end gtxKintex7FEE80_multi_gt;
+
+architecture RTL of gtxKintex7FEE80_multi_gt is
+ attribute DowngradeIPIdentifiedWarnings: string;
+ attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80_multi_gt,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
+ signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
+
+ signal gt0_qpllclk_i : std_logic;
+ signal gt0_qpllrefclk_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ signal gt0_cpllpd_i : std_logic;
+ signal cpll_reset0_i : std_logic;
+ signal cpll_pd0_i : std_logic;
+
+--*************************** Component Declarations **************************
+component gtxKintex7FEE80_GT
+generic
+(
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
+ RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
+ PMA_RSV_IN : bit_vector := X"00000000";
+ SIM_CPLLREFCLK_SEL : bit_vector := "001";
+ PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
+);
+port
+(
+ cpllpd_in : in std_logic;
+ cpllrefclksel_in : in std_logic_vector (2 downto 0);
+ --------------------------------- CPLL Ports -------------------------------
+ cpllfbclklost_out : out std_logic;
+ cplllock_out : out std_logic;
+ cplllockdetclk_in : in std_logic;
+ cpllrefclklost_out : out std_logic;
+ cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gtrefclk0_in : in std_logic;
+ gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ drpaddr_in : in std_logic_vector(8 downto 0);
+ drpclk_in : in std_logic;
+ drpdi_in : in std_logic_vector(15 downto 0);
+ drpdo_out : out std_logic_vector(15 downto 0);
+ drpen_in : in std_logic;
+ drprdy_out : out std_logic;
+ drpwe_in : in std_logic;
+ ------------------------------- Clocking Ports -----------------------------
+ qpllclk_in : in std_logic;
+ qpllrefclk_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ eyescanreset_in : in std_logic;
+ rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ eyescandataerror_out : out std_logic;
+ eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN : in std_logic; --// Modified
+ RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ rxusrclk_in : in std_logic;
+ rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ rxdisperr_out : out std_logic_vector(1 downto 0);
+ rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ rxdlyen_in : in std_logic;
+ rxdlysreset_in : in std_logic;
+ rxdlysresetdone_out : out std_logic;
+ rxphalign_in : in std_logic;
+ rxphaligndone_out : out std_logic;
+ rxphalignen_in : in std_logic;
+ rxphdlyreset_in : in std_logic;
+ rxphmonitor_out : out std_logic_vector(4 downto 0);
+ rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ rxlpmhfhold_in : in std_logic;
+ rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ rxdfelpmreset_in : in std_logic;
+ rxmonitorout_out : out std_logic_vector(6 downto 0);
+ rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gtrxreset_in : in std_logic;
+ rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gttxreset_in : in std_logic;
+ txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ txusrclk_in : in std_logic;
+ txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ txdlyen_in : in std_logic;
+ txdlysreset_in : in std_logic;
+ txdlysresetdone_out : out std_logic;
+ txphalign_in : in std_logic;
+ txphaligndone_out : out std_logic;
+ txphalignen_in : in std_logic;
+ txphdlyreset_in : in std_logic;
+ txphinit_in : in std_logic;
+ txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gtxtxn_out : out std_logic;
+ gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ txoutclk_out : out std_logic;
+ txoutclkfabric_out : out std_logic;
+ txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ txresetdone_out : out std_logic
+
+
+);
+end component;
+component gtxKintex7FEE80_cpll_railing
+ Generic(
+ USE_BUFG : integer := 0
+);
+port
+(
+ cpll_reset_out : out std_logic;
+ cpll_pd_out : out std_logic;
+ refclk_out : out std_logic;
+
+ refclk_in : in std_logic
+
+);
+end component;
+
+
+
+--********************************* Main Body of Code**************************
+
+begin
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ gt0_qpllclk_i <= GT0_QPLLOUTCLK_IN;
+ gt0_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN;
+
+
+
+ --------------------------- GT Instances -------------------------------
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X0Y0)
+
+gt0_gtxKintex7FEE80_i : gtxKintex7FEE80_GT
+ generic map
+ (
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
+ SIM_CPLLREFCLK_SEL => "001",
+ PMA_RSV_IN => PMA_RSV_IN,
+ PCS_RSVD_ATTR_IN => X"000000000000"
+ )
+ port map
+ (
+ cpllpd_in => gt0_cpllpd_i,
+ cpllrefclksel_in => "001",
+ --------------------------------- CPLL Ports -------------------------------
+ cpllfbclklost_out => gt0_cpllfbclklost_out,
+ cplllock_out => gt0_cplllock_out,
+ cplllockdetclk_in => gt0_cplllockdetclk_in,
+ cpllrefclklost_out => gt0_cpllrefclklost_out,
+ cpllreset_in => gt0_cpllreset_i,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gtrefclk0_in => gt0_gtrefclk0_in,
+ gtrefclk1_in => gt0_gtrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ drpaddr_in => gt0_drpaddr_in,
+ drpclk_in => gt0_drpclk_in,
+ drpdi_in => gt0_drpdi_in,
+ drpdo_out => gt0_drpdo_out,
+ drpen_in => gt0_drpen_in,
+ drprdy_out => gt0_drprdy_out,
+ drpwe_in => gt0_drpwe_in,
+ ------------------------------- Clocking Ports -----------------------------
+ qpllclk_in => gt0_qpllclk_i,
+ qpllrefclk_in => gt0_qpllrefclk_i,
+ --------------------------- Digital Monitor Ports --------------------------
+ dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ eyescanreset_in => gt0_eyescanreset_in,
+ rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ eyescandataerror_out => gt0_eyescandataerror_out,
+ eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ rxusrclk_in => gt0_rxusrclk_in,
+ rxusrclk2_in => gt0_rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ rxdisperr_out => gt0_rxdisperr_out,
+ rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ rxdlyen_in => gt0_rxdlyen_in,
+ rxdlysreset_in => gt0_rxdlysreset_in,
+ rxdlysresetdone_out => gt0_rxdlysresetdone_out,
+ rxphalign_in => gt0_rxphalign_in,
+ rxphaligndone_out => gt0_rxphaligndone_out,
+ rxphalignen_in => gt0_rxphalignen_in,
+ rxphdlyreset_in => gt0_rxphdlyreset_in,
+ rxphmonitor_out => gt0_rxphmonitor_out,
+ rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ rxlpmhfhold_in => gt0_rxlpmhfhold_in,
+ rxlpmlfhold_in => gt0_rxlpmlfhold_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ rxmonitorout_out => gt0_rxmonitorout_out,
+ rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ rxoutclk_out => gt0_rxoutclk_out,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gtrxreset_in => gt0_gtrxreset_in,
+ rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gttxreset_in => gt0_gttxreset_in,
+ txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ txusrclk_in => gt0_txusrclk_in,
+ txusrclk2_in => gt0_txusrclk2_in,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ txdlyen_in => gt0_txdlyen_in,
+ txdlysreset_in => gt0_txdlysreset_in,
+ txdlysresetdone_out => gt0_txdlysresetdone_out,
+ txphalign_in => gt0_txphalign_in,
+ txphaligndone_out => gt0_txphaligndone_out,
+ txphalignen_in => gt0_txphalignen_in,
+ txphdlyreset_in => gt0_txphdlyreset_in,
+ txphinit_in => gt0_txphinit_in,
+ txphinitdone_out => gt0_txphinitdone_out,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gtxtxn_out => gt0_gtxtxn_out,
+ gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ txoutclk_out => gt0_txoutclk_out,
+ txoutclkfabric_out => gt0_txoutclkfabric_out,
+ txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ txresetdone_out => gt0_txresetdone_out
+
+ );
+
+
+ cpll_railing0_i : gtxKintex7FEE80_cpll_railing
+ generic map(
+ USE_BUFG => USE_BUFG
+ )
+ port map
+ (
+ cpll_reset_out => cpll_reset0_i,
+ cpll_pd_out => cpll_pd0_i,
+ refclk_out => open,
+ refclk_in => gt0_gtrefclk0_in
+);
+
+
+gt0_cpllreset_i <= cpll_reset0_i or gt0_cpllreset_in;
+gt0_cpllpd_i <= cpll_pd0_i ;
+end RTL;
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 3.5
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtxkintex7fee80_rx_startup_fsm.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+-- Description : This module performs RX reset and initialization.
+--
+--
+--
+-- Module gtxKintex7FEE80_rx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library unisim;
+use unisim.vcomponents.all;
+
+entity gtxKintex7FEE80_RX_STARTUP_FSM is
+ Generic( EXAMPLE_SIMULATION : integer := 0;
+ EQ_MODE : string := "DFE"; --RX Equalisation Mode; set to DFE or LPM
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ RXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ RECCLK_STABLE : in STD_LOGIC;
+ RECCLK_MONITOR_RESTART : in STD_LOGIC:='0';
+ DATA_VALID : in STD_LOGIC;
+ TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
+ DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; --Used to control the Auto-Reset of FSM when Data Error is detected
+ GTRXRESET : out STD_LOGIC;
+ MMCM_RESET : out STD_LOGIC;
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
+ RX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
+ RXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC;
+ PHALIGNMENT_DONE : in STD_LOGIC;
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ RXDFEAGCHOLD : out STD_LOGIC;
+ RXDFELFHOLD : out STD_LOGIC;
+ RXLPMLFHOLD : out STD_LOGIC;
+ RXLPMHFHOLD : out STD_LOGIC;
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end gtxKintex7FEE80_RX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+-- are calculated at design-time based on the Generics
+--
+-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
+-- => signal which PLL has been reset
+-- *
+
+
+
+architecture RTL of gtxKintex7FEE80_RX_STARTUP_FSM is
+
+ component gtxKintex7FEE80_sync_block
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+ type rx_rst_fsm_type is(
+ INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
+ RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+ MONITOR_DATA_VALID, FSM_DONE);
+
+ signal rx_state : rx_rst_fsm_type := INIT;
+
+ constant MMCM_LOCK_CNT_MAX : integer := 256;
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+ constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
+ constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--500 us time-out
+ constant WAIT_TIMEOUT_1us : integer := 1000 / STABLE_CLOCK_PERIOD; --1 us time-out
+ constant WAIT_TIMEOUT_100us : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
+ constant WAIT_TIME_ADAPT : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD;
+ constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
+
+ signal init_wait_count : integer range 0 to WAIT_MAX:=0;
+ signal init_wait_done : std_logic := '0';
+ signal pll_reset_asserted : std_logic := '0';
+ signal rx_fsm_reset_done_int : std_logic := '0';
+ signal rx_fsm_reset_done_int_s2 : std_logic := '0';
+ signal rx_fsm_reset_done_int_s3 : std_logic := '0';
+
+ signal rxresetdone_s2 : std_logic := '0';
+ signal rxresetdone_s3 : std_logic := '0';
+
+ constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
+ signal retry_counter_int : integer range 0 to MAX_RETRIES := 0;
+ signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+ signal recclk_mon_restart_count : integer range 0 to 3:= 0;
+ signal recclk_mon_count_reset : std_logic := '0';
+
+ signal reset_time_out : std_logic := '0';
+ signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
+ signal time_tlock_max : std_logic := '0';--|have been reached.
+ signal time_out_500us : std_logic := '0';--|
+ signal time_out_1us : std_logic := '0';--/
+ signal time_out_100us : std_logic := '0';--/
+ signal check_tlock_max : std_logic := '0';
+
+ signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+ signal mmcm_lock_int : std_logic := '0';
+ signal mmcm_lock_i : std_logic := '0';
+ signal mmcm_lock_reclocked : std_logic := '0';
+ signal gtrxreset_i : std_logic := '0';
+ signal mmcm_reset_i : std_logic := '1';
+ signal rxpmaresetdone_i : std_logic := '0';
+ signal txpmaresetdone_i : std_logic := '0';
+ signal rxpmaresetdone_ss : std_logic := '0';
+ signal rxpmaresetdone_sync : std_logic ;
+ signal txpmaresetdone_sync : std_logic ;
+ signal rxpmaresetdone_s : std_logic ;
+ signal rxpmaresetdone_rx_s : std_logic ;
+ signal pmaresetdone_fallingedge_detect : std_logic ;
+ signal pmaresetdone_fallingedge_detect_s : std_logic ;
+
+ signal run_phase_alignment_int: std_logic := '0';
+ signal run_phase_alignment_int_s2 : std_logic := '0';
+ signal run_phase_alignment_int_s3 : std_logic := '0';
+
+ constant MAX_WAIT_BYPASS : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
+ signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
+ signal time_out_wait_bypass : std_logic := '0';
+ signal time_out_wait_bypass_s2 : std_logic := '0';
+ signal time_out_wait_bypass_s3 : std_logic := '0';
+
+ signal refclk_lost : std_logic;
+
+ signal time_out_adapt : std_logic := '0';
+ signal adapt_count_reset : std_logic := '0';
+ signal adapt_count : integer range 0 to WAIT_TIME_ADAPT-1;
+ signal data_valid_sync: std_logic := '0';
+ signal cplllock_sync: std_logic := '0';
+ signal qplllock_sync: std_logic := '0';
+ signal cplllock_prev: std_logic := '0';
+ signal qplllock_prev: std_logic := '0';
+ signal cplllock_ris_edge: std_logic := '0';
+ signal qplllock_ris_edge: std_logic := '0';
+ signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+ signal wait_time_done : std_logic;
+
+
+ attribute shreg_extract : string;
+ attribute ASYNC_REG : string;
+
+ signal reset_sync_reg1_tx : std_logic;
+ signal reset_sync_reg1 : std_logic;
+ signal gtrxreset_s : std_logic;
+ signal gtrxreset_tx_s : std_logic;
+ signal txpmaresetdone_s : std_logic;
+begin
+ --Alias section, signals used within this module mapped to output ports:
+ RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+ RUN_PHALIGNMENT <= run_phase_alignment_int;
+ RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
+ GTRXRESET <= gtrxreset_i;
+ MMCM_RESET <= mmcm_reset_i;
+ process(STABLE_CLOCK,SOFT_RESET)
+ begin
+ if (SOFT_RESET = '1') then
+ init_wait_done <= '0';
+ init_wait_count <= 0 ;
+ elsif rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+
+ adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
+ time_out_adapt <= '1';
+ end generate;
+
+ adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(adapt_count_reset = '1') then
+ adapt_count <= 0;
+ time_out_adapt <= '0';
+ elsif(adapt_count = WAIT_TIME_ADAPT -1) then
+ time_out_adapt <= '1';
+ else
+ adapt_count <= adapt_count + 1;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ retries_recclk_monitor:process(STABLE_CLOCK)
+ begin
+ --This counter monitors, how many retries the RECCLK monitor
+ --runs. If during startup too many retries are necessary, the whole
+ --initialisation-process of the transceivers gets restarted.
+ if rising_edge(STABLE_CLOCK) then
+ if recclk_mon_count_reset = '1' then
+ recclk_mon_restart_count <= 0;
+ elsif RECCLK_MONITOR_RESTART = '1' then
+ if recclk_mon_restart_count = 3 then
+ recclk_mon_restart_count <= 0;
+ else
+ recclk_mon_restart_count <= recclk_mon_restart_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ timeouts:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- One common large counter for generating three time-out signals.
+ -- Intermediate time-outs are derived from calculated values, based
+ -- on the period of the provided clock.
+ if reset_time_out = '1' then
+ time_out_counter <= 0;
+ time_out_2ms <= '0';
+ time_tlock_max <= '0';
+ time_out_500us <= '0';
+ time_out_1us <= '0';
+ time_out_100us <= '0';
+ else
+ if time_out_counter = WAIT_TIMEOUT_2ms then
+ time_out_2ms <= '1';
+ else
+ time_out_counter <= time_out_counter + 1;
+ end if;
+
+ if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
+ time_tlock_max <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_500us then
+ time_out_500us <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_1us then
+ time_out_1us <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_100us then
+ time_out_100us <= '1';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+
+
+ mmcm_lock_wait:process(STABLE_CLOCK)
+ begin
+ --The lock-signal from the MMCM is not immediately used but
+ --enabling a counter. Only when the counter hits its maximum,
+ --the MMCM is considered as "really" locked.
+ --The counter avoids that the FSM already starts on only a
+ --coarse lock of the MMCM (=toggling of the LOCK-signal).
+ if rising_edge(STABLE_CLOCK) then
+ if mmcm_lock_i = '0' then
+ mmcm_lock_count <= 0;
+ mmcm_lock_reclocked <= '0';
+ else
+ if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+ mmcm_lock_count <= mmcm_lock_count + 1;
+ else
+ mmcm_lock_reclocked <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ -- Clock Domain Crossing
+
+ sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => RXUSERCLK,
+ data_in => run_phase_alignment_int,
+ data_out => run_phase_alignment_int_s2
+ );
+
+ sync_rx_fsm_reset_done_int : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => RXUSERCLK,
+ data_in => rx_fsm_reset_done_int,
+ data_out => rx_fsm_reset_done_int_s2
+ );
+
+ process(RXUSERCLK)
+ begin
+ if rising_edge(RXUSERCLK) then
+ run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
+
+ rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2;
+ end if;
+ end process;
+
+ sync_RXRESETDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => RXRESETDONE,
+ data_out => rxresetdone_s2
+ );
+
+ sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => time_out_wait_bypass,
+ data_out => time_out_wait_bypass_s2
+ );
+
+ sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => MMCM_LOCK,
+ data_out => mmcm_lock_i
+ );
+
+ sync_data_valid : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => DATA_VALID,
+ data_out => data_valid_sync
+ );
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ rxresetdone_s3 <= rxresetdone_s2;
+
+ time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
+
+ cplllock_prev <= cplllock_sync;
+ qplllock_prev <= qplllock_sync;
+ end if;
+ end process;
+
+ sync_CPLLLOCK : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => CPLLLOCK,
+ data_out => cplllock_sync
+ );
+
+ sync_QPLLLOCK : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => QPLLLOCK,
+ data_out => qplllock_sync
+ );
+
+
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ cplllock_ris_edge <= '0';
+ elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+ cplllock_ris_edge <= '1';
+ elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+ cplllock_ris_edge <= cplllock_ris_edge;
+ else
+ cplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ qplllock_ris_edge <= '0';
+ elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+ qplllock_ris_edge <= '1';
+ elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+ qplllock_ris_edge <= qplllock_ris_edge;
+ else
+ qplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ timeout_buffer_bypass:process(RXUSERCLK)
+ begin
+ if rising_edge(RXUSERCLK) then
+ if run_phase_alignment_int_s3 = '0' then
+ wait_bypass_count <= 0;
+ time_out_wait_bypass <= '0';
+ elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
+ if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+ time_out_wait_bypass <= '1';
+ else
+ wait_bypass_count <= wait_bypass_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+
+ timeout_max:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if((rx_state = ASSERT_ALL_RESETS) or
+ (rx_state = RELEASE_MMCM_RESET)) then
+ wait_time_cnt <= WAIT_TIME_MAX;
+ elsif (wait_time_cnt > 0 ) then
+ wait_time_cnt <= wait_time_cnt - 1;
+ end if;
+ end if;
+ end process;
+
+ wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+
+ --FSM for resetting the GTX/GTH/GTP in the 7-series.
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ --
+ -- Following steps are performed:
+ -- 1) After configuration wait for approximately 500 ns as specified in
+ -- answer-record 43482
+ -- 2) Assert all resets on the GT and on an MMCM potentially connected.
+ -- After that wait until a reference-clock has been detected.
+ -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+ -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+ -- Also get info from the TX-side which PLL has been reset.
+ -- 5) Wait for the RESET_DONE-signal from the GT.
+ -- 6) Signal to start the phase-alignment procedure and wait for it to
+ -- finish.
+ -- 7) Reset-sequence has successfully run through. Signal this to the
+ -- rest of the design by asserting RX_FSM_RESET_DONE.
+
+ reset_fsm:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if (SOFT_RESET = '1' ) then
+ --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+ rx_state <= INIT;
+ RXUSERRDY <= '0';
+ gtrxreset_i <= '0';
+ mmcm_reset_i <= '0';
+ rx_fsm_reset_done_int <= '0';
+ QPLL_RESET <= '0';
+ CPLL_RESET <= '0';
+ pll_reset_asserted <= '0';
+ reset_time_out <= '1';
+ retry_counter_int <= 0;
+ run_phase_alignment_int <= '0';
+ check_tlock_max <= '0';
+ RESET_PHALIGNMENT <= '1';
+ recclk_mon_count_reset <= '1';
+ adapt_count_reset <= '1';
+ RXDFEAGCHOLD <= '0';
+ RXDFELFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ RXLPMHFHOLD <= '0';
+
+ else
+
+ case rx_state is
+ when INIT =>
+ --Initial state after configuration. This state will be left after
+ --approx. 500 ns and not be re-entered.
+ if init_wait_done = '1' then
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when ASSERT_ALL_RESETS =>
+ --This is the state into which the FSM will always jump back if any
+ --time-outs will occur.
+ --The number of retries is reported on the output RETRY_COUNTER. In
+ --case the transceiver never comes up for some reason, this machine
+ --will still continue its best and rerun until the FPGA is turned off
+ --or the transceivers come up correctly.
+ if RX_QPLL_USED and not TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ QPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ QPLL_RESET <= '0';
+ end if;
+ elsif not RX_QPLL_USED and TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ CPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ CPLL_RESET <= '0';
+ end if;
+ end if;
+
+ RXUSERRDY <= '0';
+ gtrxreset_i <= '1';
+ mmcm_reset_i <= '1';
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+ check_tlock_max <= '0';
+ recclk_mon_count_reset <= '1';
+ adapt_count_reset <= '1';
+
+ if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+ (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '0') and pll_reset_asserted = '1') or
+ (not RX_QPLL_USED and not TX_QPLL_USED ) or
+ (RX_QPLL_USED and TX_QPLL_USED ) then
+ rx_state <= WAIT_FOR_PLL_LOCK;
+ reset_time_out <= '1';
+ end if;
+
+ when WAIT_FOR_PLL_LOCK =>
+ if(wait_time_done = '1') then
+ rx_state <= RELEASE_PLL_RESET;
+ end if;
+
+ when RELEASE_PLL_RESET =>
+ --PLL-Reset of the GTX gets released and the time-out counter
+ --starts running.
+ pll_reset_asserted <= '0';
+ reset_time_out <= '0';
+
+ if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '1')) or
+ (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '1')) then
+ rx_state <= VERIFY_RECCLK_STABLE;
+ reset_time_out <= '1';
+ recclk_mon_count_reset <= '0';
+ adapt_count_reset <= '0';
+ elsif (RX_QPLL_USED and (qplllock_sync = '1')) or
+ (not RX_QPLL_USED and (cplllock_sync = '1')) then
+ rx_state <= VERIFY_RECCLK_STABLE;
+ reset_time_out <= '1';
+ recclk_mon_count_reset <= '0';
+ adapt_count_reset <= '0';
+ end if;
+
+ if time_out_2ms = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when VERIFY_RECCLK_STABLE =>
+ --reset_time_out <= '0';
+ --Time-out counter is not released in this state as here the FSM
+ --does not wait for a certain period of time but checks on the number
+ --of retries in the RECCLK monitor
+ gtrxreset_i <= '0';
+ if RECCLK_STABLE = '1' then
+ rx_state <= RELEASE_MMCM_RESET;
+ reset_time_out <= '1';
+
+ end if;
+
+ if recclk_mon_restart_count = 2 then
+ --If two retries are performed in the RECCLK monitor
+ --the whole initialisation-sequence gets restarted.
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when RELEASE_MMCM_RESET =>
+ --Release of the MMCM-reset. Waiting for the MMCM to lock.
+ check_tlock_max <= '1';
+
+ mmcm_reset_i <= '0';
+ reset_time_out <= '0';
+
+ if mmcm_lock_reclocked = '1' then
+ rx_state <= WAIT_FOR_RXUSRCLK;
+ reset_time_out <= '1';
+ end if;
+
+ if (time_tlock_max = '1' and reset_time_out = '0' )then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_FOR_RXUSRCLK =>
+ if wait_time_done = '1' then
+ rx_state <= WAIT_RESET_DONE;
+ end if;
+
+ when WAIT_RESET_DONE =>
+ --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
+ --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
+ if TXUSERRDY = '1' then
+ RXUSERRDY <= '1';
+ end if;
+ reset_time_out <= '0';
+ if rxresetdone_s3 = '1' then
+ rx_state <= DO_PHASE_ALIGNMENT;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_2ms = '1' and reset_time_out = '0' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when DO_PHASE_ALIGNMENT =>
+ --The direct handling of the signals for the Phase Alignment is done outside
+ --this state-machine.
+ RESET_PHALIGNMENT <= '0';
+ run_phase_alignment_int <= '1';
+ reset_time_out <= '0';
+
+ if PHALIGNMENT_DONE = '1' then
+ rx_state <= MONITOR_DATA_VALID;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_wait_bypass_s3 = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when MONITOR_DATA_VALID =>
+ reset_time_out <= '0';
+
+ if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0') then
+ rx_state <= ASSERT_ALL_RESETS;
+ rx_fsm_reset_done_int <= '0';
+ elsif (data_valid_sync = '1') then
+ rx_state <= FSM_DONE;
+ rx_fsm_reset_done_int <= '0';
+ reset_time_out <= '1';
+ end if;
+
+ when FSM_DONE =>
+ reset_time_out <= '0';
+ if data_valid_sync = '0' then
+ rx_fsm_reset_done_int <= '0';
+ reset_time_out <= '1';
+ rx_state <= MONITOR_DATA_VALID;
+
+ elsif(time_out_1us = '1' and reset_time_out = '0') then
+ rx_fsm_reset_done_int <= '1';
+ end if;
+
+ if(time_out_adapt = '1') then
+ if(EQ_MODE = "DFE") then
+ RXDFEAGCHOLD <= '1';
+ RXDFELFHOLD <= '1';
+ RXLPMHFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ else
+ RXDFEAGCHOLD <= '0';
+ RXDFELFHOLD <= '0';
+ RXLPMHFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ end if;
+ end if;
+ when OTHERS =>
+ rx_state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
+
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 3.5
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtxkintex7fee80_sync_block.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+--
+-- Description: Used on signals crossing from one clock domain to
+-- another, this is a flip-flop pair, with both flops
+-- placed together with RLOCs into the same slice. Thus
+-- the routing delay between the two is minimum to safe-
+-- guard against metastability issues.
+--
+--
+-- Module gtxKintex7FEE80_sync_block
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity gtxKintex7FEE80_sync_block is
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic; -- clock to be sync'ed to
+ data_in : in std_logic; -- Data to be 'synced'
+ data_out : out std_logic -- synced data
+ );
+
+-- attribute dont_touch : string;
+-- attribute dont_touch of gtxKintex7FEE80_sync_block : entity is "yes";
+
+end gtxKintex7FEE80_sync_block;
+
+
+architecture structural of gtxKintex7FEE80_sync_block is
+
+
+ -- Internal Signals
+ signal data_sync1 : std_logic;
+ signal data_sync2 : std_logic;
+ signal data_sync3 : std_logic;
+ signal data_sync4 : std_logic;
+ signal data_sync5 : std_logic;
+
+ -- These attributes will stop timing errors being reported in back annotated
+ -- SDF simulation.
+ attribute ASYNC_REG : string;
+ attribute ASYNC_REG of data_sync_reg1 : label is "true";
+ attribute ASYNC_REG of data_sync_reg2 : label is "true";
+ attribute ASYNC_REG of data_sync_reg3 : label is "true";
+ attribute ASYNC_REG of data_sync_reg4 : label is "true";
+ attribute ASYNC_REG of data_sync_reg5 : label is "true";
+ attribute ASYNC_REG of data_sync_reg6 : label is "true";
+
+ -- These attributes will stop XST translating the desired flip-flops into an
+ -- SRL based shift register.
+ attribute shreg_extract : string;
+ attribute shreg_extract of data_sync_reg1 : label is "no";
+ attribute shreg_extract of data_sync_reg2 : label is "no";
+ attribute shreg_extract of data_sync_reg3 : label is "no";
+ attribute shreg_extract of data_sync_reg4 : label is "no";
+ attribute shreg_extract of data_sync_reg5 : label is "no";
+ attribute shreg_extract of data_sync_reg6 : label is "no";
+
+
+begin
+
+ data_sync_reg1 : FD
+ generic map (
+ INIT => INITIALISE(0)
+ )
+ port map (
+ C => clk,
+ D => data_in,
+ Q => data_sync1
+ );
+
+ data_sync_reg2 : FD
+ generic map (
+ INIT => INITIALISE(1)
+ )
+ port map (
+ C => clk,
+ D => data_sync1,
+ Q => data_sync2
+ );
+
+ data_sync_reg3 : FD
+ generic map (
+ INIT => INITIALISE(2)
+ )
+ port map (
+ C => clk,
+ D => data_sync2,
+ Q => data_sync3
+ );
+
+ data_sync_reg4 : FD
+ generic map (
+ INIT => INITIALISE(3)
+ )
+ port map (
+ C => clk,
+ D => data_sync3,
+ Q => data_sync4
+ );
+
+ data_sync_reg5 : FD
+ generic map (
+ INIT => INITIALISE(4)
+ )
+ port map (
+ C => clk,
+ D => data_sync4,
+ Q => data_sync5
+ );
+
+ data_sync_reg6 : FD
+ generic map (
+ INIT => INITIALISE(5)
+ )
+ port map (
+ C => clk,
+ D => data_sync5,
+ Q => data_out
+ );
+
+
+
+end structural;
+
+
--- /dev/null
+--//////////////////////////////////////////////////////////////////////////////
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename :gtxkintex7fee80_tx_startup_fsm.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module gtxKintex7FEE80_tx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_TX_STARTUP_FSM is
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ TXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ GTTXRESET : out STD_LOGIC;
+ MMCM_RESET : out STD_LOGIC:='1';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
+ TX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
+ TXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC:='0';
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ PHALIGNMENT_DONE : in STD_LOGIC;
+
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end gtxKintex7FEE80_TX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+-- are calculated at design-time based on the Generics
+--
+-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
+-- => signal which PLL has been reset
+-- *
+
+
+
+architecture RTL of gtxKintex7FEE80_TX_STARTUP_FSM is
+
+ component gtxKintex7FEE80_sync_block
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ type tx_rst_fsm_type is(
+ INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET,
+ WAIT_FOR_TXOUTCLK, RELEASE_MMCM_RESET, WAIT_FOR_TXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+ RESET_FSM_DONE);
+
+ signal tx_state : tx_rst_fsm_type := INIT;
+
+ constant MMCM_LOCK_CNT_MAX : integer := 256;
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+ constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
+ constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_1us_cycles : integer := 1000 / STABLE_CLOCK_PERIOD;--1 us time-out
+ constant WAIT_1us : integer := WAIT_1us_cycles+ 10; -- 1us plus some additional margin
+
+ signal init_wait_count : integer range 0 to WAIT_MAX:=0;
+ signal init_wait_done : std_logic := '0';
+ signal pll_reset_asserted : std_logic := '0';
+
+ signal tx_fsm_reset_done_int : std_logic := '0';
+ signal tx_fsm_reset_done_int_s2 : std_logic := '0';
+ signal tx_fsm_reset_done_int_s3 : std_logic := '0';
+
+ signal txresetdone_s2 : std_logic := '0';
+ signal txresetdone_s3 : std_logic := '0';
+
+ constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
+ signal retry_counter_int : integer range 0 to MAX_RETRIES;
+ signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+
+ signal reset_time_out : std_logic := '0';
+ signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
+ signal time_tlock_max : std_logic := '0';--|have been reached.
+ signal time_out_500us : std_logic := '0';--/
+
+ signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+ signal mmcm_lock_int : std_logic := '0';
+ signal mmcm_lock_i : std_logic := '0';
+ signal mmcm_lock_reclocked : std_logic := '0';
+
+ signal run_phase_alignment_int : std_logic := '0';
+ signal run_phase_alignment_int_s2 : std_logic := '0';
+ signal run_phase_alignment_int_s3 : std_logic := '0';
+ constant MAX_WAIT_BYPASS : integer := 45824; --110000 TXUSRCLK cycles is the max time for Multi lane designs
+
+ constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
+
+ signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
+ signal time_out_wait_bypass : std_logic := '0';
+ signal time_out_wait_bypass_s2 : std_logic := '0';
+ signal time_out_wait_bypass_s3 : std_logic := '0';
+ signal txuserrdy_i : std_logic := '0';
+ signal refclk_lost : std_logic;
+ signal gttxreset_i : std_logic := '0';
+ signal txpmaresetdone_i : std_logic := '0';
+ signal txpmaresetdone_sync : std_logic ;
+
+ signal cplllock_sync: std_logic := '0';
+ signal qplllock_sync: std_logic := '0';
+ signal cplllock_prev: std_logic := '0';
+ signal qplllock_prev: std_logic := '0';
+ signal cplllock_ris_edge: std_logic := '0';
+ signal qplllock_ris_edge: std_logic := '0';
+ signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+ signal wait_time_done :std_logic;
+
+begin
+ --Alias section, signals used within this module mapped to output ports:
+ RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+ RUN_PHALIGNMENT <= run_phase_alignment_int;
+ TX_FSM_RESET_DONE <= tx_fsm_reset_done_int;
+ GTTXRESET <= gttxreset_i;
+
+ process(STABLE_CLOCK,SOFT_RESET)
+ begin
+ if (SOFT_RESET = '1') then
+ init_wait_done <= '0';
+ init_wait_count <= 0 ;
+ elsif rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ timeouts:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- One common large counter for generating three time-out signals.
+ -- Intermediate time-outs are derived from calculated values, based
+ -- on the period of the provided clock.
+ if reset_time_out = '1' then
+ time_out_counter <= 0;
+ time_out_2ms <= '0';
+ time_tlock_max <= '0';
+ time_out_500us <= '0';
+ else
+ if time_out_counter = WAIT_TIMEOUT_2ms then
+ time_out_2ms <= '1';
+ else
+ time_out_counter <= time_out_counter + 1;
+ end if;
+
+ if time_out_counter = WAIT_TLOCK_MAX then
+ time_tlock_max <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_500us then
+ time_out_500us <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ mmcm_lock_wait:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if mmcm_lock_i = '0' then
+ mmcm_lock_count <= 0;
+ mmcm_lock_reclocked <= '0';
+ else
+ if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+ mmcm_lock_count <= mmcm_lock_count + 1;
+ else
+ mmcm_lock_reclocked <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+
+ -- Clock Domain Crossing
+
+ sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => TXUSERCLK,
+ data_in => run_phase_alignment_int,
+ data_out => run_phase_alignment_int_s2
+ );
+
+ sync_tx_fsm_reset_done_int : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => TXUSERCLK,
+ data_in => tx_fsm_reset_done_int,
+ data_out => tx_fsm_reset_done_int_s2
+ );
+
+ process(TXUSERCLK)
+ begin
+ if rising_edge(TXUSERCLK) then
+ run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
+
+ tx_fsm_reset_done_int_s3 <= tx_fsm_reset_done_int_s2;
+ end if;
+ end process;
+
+ sync_TXRESETDONE : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => TXRESETDONE,
+ data_out => txresetdone_s2
+ );
+
+ sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => time_out_wait_bypass,
+ data_out => time_out_wait_bypass_s2
+ );
+
+ sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => MMCM_LOCK,
+ data_out => mmcm_lock_i
+ );
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ txresetdone_s3 <= txresetdone_s2;
+
+ time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
+
+ cplllock_prev <= cplllock_sync;
+ qplllock_prev <= qplllock_sync;
+ end if;
+ end process;
+
+ sync_CPLLLOCK : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => CPLLLOCK,
+ data_out => cplllock_sync
+ );
+
+ sync_QPLLLOCK : gtxKintex7FEE80_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => QPLLLOCK,
+ data_out => qplllock_sync
+ );
+
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ cplllock_ris_edge <= '0';
+ elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+ cplllock_ris_edge <= '1';
+ elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+ cplllock_ris_edge <= cplllock_ris_edge;
+ else
+ cplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ qplllock_ris_edge <= '0';
+ elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+ qplllock_ris_edge <= '1';
+ elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+ qplllock_ris_edge <= qplllock_ris_edge;
+ else
+ qplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+
+
+ timeout_buffer_bypass:process(TXUSERCLK)
+ begin
+ if rising_edge(TXUSERCLK) then
+ if run_phase_alignment_int_s3 = '0' then
+ wait_bypass_count <= 0;
+ time_out_wait_bypass <= '0';
+ elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0') then
+ if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+ time_out_wait_bypass <= '1';
+ else
+ wait_bypass_count <= wait_bypass_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+ timeout_max:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if((tx_state = ASSERT_ALL_RESETS) or
+ (tx_state = RELEASE_PLL_RESET) or
+ (tx_state = RELEASE_MMCM_RESET)) then
+ wait_time_cnt <= WAIT_TIME_MAX;
+ elsif (wait_time_cnt > 0 ) then
+ wait_time_cnt <= wait_time_cnt - 1;
+ end if;
+ end if;
+ end process;
+
+ wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+
+ --FSM for resetting the GTX/GTH/GTP in the 7-series.
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ --
+ -- Following steps are performed:
+ -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in
+ -- answer-record 43482
+ -- 2) Assert all resets on the GT and on an MMCM potentially connected.
+ -- After that wait until a reference-clock has been detected.
+ -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+ -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+ -- Also signal to the RX-side which PLL has been reset.
+ -- 5) Wait for the RESET_DONE-signal from the GT.
+ -- 6) Signal to start the phase-alignment procedure and wait for it to
+ -- finish.
+ -- 7) Reset-sequence has successfully run through. Signal this to the
+ -- rest of the design by asserting TX_FSM_RESET_DONE.
+
+ reset_fsm:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ --if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+ tx_state <= INIT;
+ TXUSERRDY <= '0';
+ gttxreset_i <= '0';
+ MMCM_RESET <= '0';
+ tx_fsm_reset_done_int <= '0';
+ QPLL_RESET <= '0';
+ CPLL_RESET <= '0';
+ pll_reset_asserted <= '0';
+ reset_time_out <= '0';
+ retry_counter_int <= 0;
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+ else
+
+ case tx_state is
+ when INIT =>
+ --Initial state after configuration. This state will be left after
+ --approx. 500 ns and not be re-entered.
+ if init_wait_done = '1' then
+ tx_state <= ASSERT_ALL_RESETS;
+ reset_time_out <= '1';
+ end if;
+
+ when ASSERT_ALL_RESETS =>
+ --This is the state into which the FSM will always jump back if any
+ --time-outs will occur.
+ --The number of retries is reported on the output RETRY_COUNTER. In
+ --case the transceiver never comes up for some reason, this machine
+ --will still continue its best and rerun until the FPGA is turned off
+ --or the transceivers come up correctly.
+ if TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ QPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ QPLL_RESET <= '0';
+ end if;
+ else
+ if pll_reset_asserted = '0' then
+ CPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ CPLL_RESET <= '0';
+ end if;
+ end if;
+ TXUSERRDY <= '0';
+ gttxreset_i <= '1';
+ MMCM_RESET <= '1';
+ reset_time_out <= '1';
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+
+ if (TX_QPLL_USED and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+ (not TX_QPLL_USED and (cplllock_sync = '0') and pll_reset_asserted = '1') then
+ tx_state <= WAIT_FOR_PLL_LOCK;
+ end if;
+
+ when WAIT_FOR_PLL_LOCK =>
+ if(wait_time_done = '1') then
+ tx_state <= RELEASE_PLL_RESET;
+ end if;
+
+ when RELEASE_PLL_RESET =>
+ --PLL-Reset of the GTX gets released and the time-out counter
+ --starts running.
+ pll_reset_asserted <= '0';
+
+ if (TX_QPLL_USED and (qplllock_sync = '1')) or
+ (not TX_QPLL_USED and (cplllock_sync = '1')) then
+ tx_state <= WAIT_FOR_TXOUTCLK;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_2ms = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_FOR_TXOUTCLK =>
+ gttxreset_i <= '0';
+ if(wait_time_done = '1') then
+ tx_state <= RELEASE_MMCM_RESET;
+ end if;
+
+ when RELEASE_MMCM_RESET =>
+ --Release of the MMCM-reset. Waiting for the MMCM to lock.
+ MMCM_RESET <= '0';
+ reset_time_out <= '0';
+ if mmcm_lock_reclocked = '1' then
+ tx_state <= WAIT_FOR_TXUSRCLK;
+ reset_time_out <= '1';
+ end if;
+
+ if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0') then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_FOR_TXUSRCLK =>
+ if(wait_time_done = '1') then
+ tx_state <= WAIT_RESET_DONE;
+ end if;
+
+ when WAIT_RESET_DONE =>
+ TXUSERRDY <= '1';
+ reset_time_out <= '0';
+ if txresetdone_s3 = '1' then
+ tx_state <= DO_PHASE_ALIGNMENT;
+ reset_time_out <= '1';
+ end if;
+
+ if (time_out_500us = '1' and reset_time_out = '0') then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when DO_PHASE_ALIGNMENT =>
+ --The direct handling of the signals for the Phase Alignment is done outside
+ --this state-machine.
+ RESET_PHALIGNMENT <= '0';
+ run_phase_alignment_int <= '1';
+ reset_time_out <= '0';
+
+ if PHALIGNMENT_DONE = '1' then
+ tx_state <= RESET_FSM_DONE;
+ end if;
+
+ if time_out_wait_bypass_s3 = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when RESET_FSM_DONE =>
+ reset_time_out <= '1';
+ tx_fsm_reset_done_int <= '1';
+
+ when OTHERS =>
+ tx_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">gtxKintex7FEE80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK0_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK0_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
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+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
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+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : gtxVirtex6FEE80_top.ucf\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\\r
-##\r
-##\r
-## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## Device: xc6vlx130t\r
-## Package: ff484\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-################################## Clock Constraints ##########################\r
-\r
-NET "q3_clk0_refclk_i" TNM_NET = "q3_clk0_refclk_i";\r
-TIMESPEC "TS_q3_clk0_refclk_i" = PERIOD "q3_clk0_refclk_i" 12.5;\r
-\r
-\r
-\r
-# User Clock Constraints\r
-NET "gtx0_txusrclk2_i" TNM_NET = "gtx0_txusrclk2_i";
-TIMESPEC "TS_gtx0_txusrclk2_i" = PERIOD "gtx0_txusrclk2_i" 5.0;
-
-NET "gtx0_rxusrclk2_i" TNM_NET = "gtx0_rxusrclk2_i";
-TIMESPEC "TS_gtx0_rxusrclk2_i" = PERIOD "gtx0_rxusrclk2_i" 5.0;
-
-\r
-\r
-#################### locs for top level ports (ML623 Board) ###################\r
-\r
-\r
-\r
-####################### GTX reference clock constraints #######################\r
-NET Q3_CLK0_MGTREFCLK_PAD_N_IN LOC=L3;\r
-NET Q3_CLK0_MGTREFCLK_PAD_P_IN LOC=L4;\r
-\r
-\r
-################################# mgt wrapper constraints #####################\r
-\r
-##---------- Set placement for gtx0_gtx_wrapper_i/GTX_DUAL ------\r
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i LOC=GTXE1_X0Y12;\r
-\r
-\r
-\r
+################################################################################
+## ____ ____
+## / /\/ /
+## /___/ \ / Vendor: Xilinx
+## \ \ \/ Version : 3.5
+## \ \ Application : 7 Series FPGAs Transceivers Wizard
+## / / Filename : gtxKintex7FEE80_exdes.xdc
+## /___/ /\
+## \ \ / \
+## \___\/\___\
+##
+##
+## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
+## Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+##
+## Device: xc7k160t
+## Package: fbg484
+##
+## (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+
+
+################################## Clock Constraints ##########################
+
+
+####################### GT reference clock constraints #########################
+
+
+ create_clock -period 12.5 [get_ports Q0_CLK0_GTREFCLK_PAD_P_IN]
+
+
+
+
+
+create_clock -name drpclk_in_i -period 12.5 [get_ports DRP_CLK_IN_P]
+
+
+# User Clock Constraints
+
+
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}]
+################################# RefClk Location constraints #####################
+set_property LOC D5 [get_ports Q0_CLK0_GTREFCLK_PAD_N_IN ]
+set_property LOC D6 [get_ports Q0_CLK0_GTREFCLK_PAD_P_IN ]
+
+## LOC constrain for DRP_CLK_P/N
+## set_property LOC C25 [get_ports DRP_CLK_IN_P]
+## set_property LOC B25 [get_ports DRP_CLK_IN_N]
+
+################################# mgt wrapper constraints #####################
+
+##---------- Set placement for gt0_gtx_wrapper_i/GTXE2_CHANNEL ------
+set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells gtxKintex7FEE80_support_i/gtxKintex7FEE80_init_i/U0/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i]
+
+##---------- Set ASYNC_REG for flop which have async input ----------
+##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_gen*system_reset_r_reg}]
+##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_check*system_reset_r_reg}]
+
+##---------- Set False Path from one clock to other ----------
--- file: clockmodule80M.vhd\r
--- \r
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
--- \r
-------------------------------------------------------------------------------\r
--- User entered comments\r
-------------------------------------------------------------------------------\r
--- None\r
---\r
-------------------------------------------------------------------------------\r
--- "Output Output Phase Duty Pk-to-Pk Phase"\r
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
-------------------------------------------------------------------------------\r
--- CLK_OUT1____99.999______0.000______50.0______144.151____174.045\r
---\r
-------------------------------------------------------------------------------\r
--- "Input Clock Freq (MHz) Input Jitter (UI)"\r
-------------------------------------------------------------------------------\r
--- __primary__________155.52____________0.010\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.numeric_std.all;\r
-\r
-library unisim;\r
-use unisim.vcomponents.all;\r
-\r
-entity clockmodule80M is\r
-port\r
- (-- Clock in ports\r
- CLK_IN1 : in std_logic;\r
- -- Clock out ports\r
- CLK_OUT1 : out std_logic;\r
- -- Status and control signals\r
- LOCKED : out std_logic\r
- );\r
-end clockmodule80M;\r
-\r
-architecture xilinx of clockmodule80M is\r
- attribute CORE_GENERATION_INFO : string;\r
- attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule80M,clk_wiz_v3_6,{component_name=clockmodule80M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=6.430,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";\r
- -- Input clock buffering / unused connectors\r
- signal clkin1 : std_logic;\r
- -- Output clock buffering / unused connectors\r
- signal clkfbout : std_logic;\r
- signal clkfbout_buf : std_logic;\r
- signal clkfboutb_unused : std_logic;\r
- signal clkout0 : std_logic;\r
- signal clkout0b_unused : std_logic;\r
- signal clkout1_unused : std_logic;\r
- signal clkout1b_unused : std_logic;\r
- signal clkout2_unused : std_logic;\r
- signal clkout2b_unused : std_logic;\r
- signal clkout3_unused : std_logic;\r
- signal clkout3b_unused : std_logic;\r
- signal clkout4_unused : std_logic;\r
- signal clkout5_unused : std_logic;\r
- signal clkout6_unused : std_logic;\r
- -- Dynamic programming unused signals\r
- signal do_unused : std_logic_vector(15 downto 0);\r
- signal drdy_unused : std_logic;\r
- -- Dynamic phase shift unused signals\r
- signal psdone_unused : std_logic;\r
- -- Unused status signals\r
- signal clkfbstopped_unused : std_logic;\r
- signal clkinstopped_unused : std_logic;\r
-begin\r
-\r
-\r
- -- Input buffering\r
- --------------------------------------\r
- clkin1 <= CLK_IN1;\r
-\r
-\r
- -- Clocking primitive\r
- --------------------------------------\r
- -- Instantiation of the MMCM primitive\r
- -- * Unused inputs are tied off\r
- -- * Unused outputs are labeled unused\r
- mmcm_adv_inst : MMCM_ADV\r
- generic map\r
- (BANDWIDTH => "OPTIMIZED",\r
- CLKOUT4_CASCADE => FALSE,\r
- CLOCK_HOLD => FALSE,\r
- COMPENSATION => "ZHOLD",\r
- STARTUP_WAIT => FALSE,\r
- DIVCLK_DIVIDE => 5,\r
- CLKFBOUT_MULT_F => 43.000,\r
- CLKFBOUT_PHASE => 0.000,\r
- CLKFBOUT_USE_FINE_PS => FALSE,\r
- CLKOUT0_DIVIDE_F => 13.375,\r
- CLKOUT0_PHASE => 0.000,\r
- CLKOUT0_DUTY_CYCLE => 0.500,\r
- CLKOUT0_USE_FINE_PS => FALSE,\r
- CLKIN1_PERIOD => 6.430,\r
- REF_JITTER1 => 0.010)\r
- port map\r
- -- Output clocks\r
- (CLKFBOUT => clkfbout,\r
- CLKFBOUTB => clkfboutb_unused,\r
- CLKOUT0 => clkout0,\r
- CLKOUT0B => clkout0b_unused,\r
- CLKOUT1 => clkout1_unused,\r
- CLKOUT1B => clkout1b_unused,\r
- CLKOUT2 => clkout2_unused,\r
- CLKOUT2B => clkout2b_unused,\r
- CLKOUT3 => clkout3_unused,\r
- CLKOUT3B => clkout3b_unused,\r
- CLKOUT4 => clkout4_unused,\r
- CLKOUT5 => clkout5_unused,\r
- CLKOUT6 => clkout6_unused,\r
- -- Input clock control\r
- CLKFBIN => clkfbout_buf,\r
- CLKIN1 => clkin1,\r
- CLKIN2 => '0',\r
- -- Tied to always select the primary input clock\r
- CLKINSEL => '1',\r
- -- Ports for dynamic reconfiguration\r
- DADDR => (others => '0'),\r
- DCLK => '0',\r
- DEN => '0',\r
- DI => (others => '0'),\r
- DO => do_unused,\r
- DRDY => drdy_unused,\r
- DWE => '0',\r
- -- Ports for dynamic phase shift\r
- PSCLK => '0',\r
- PSEN => '0',\r
- PSINCDEC => '0',\r
- PSDONE => psdone_unused,\r
- -- Other control and status signals\r
- LOCKED => LOCKED,\r
- CLKINSTOPPED => clkinstopped_unused,\r
- CLKFBSTOPPED => clkfbstopped_unused,\r
- PWRDWN => '0',\r
- RST => '0');\r
-\r
- -- Output buffering\r
- -------------------------------------\r
- clkf_buf : BUFG\r
- port map\r
- (O => clkfbout_buf,\r
- I => clkfbout);\r
-\r
-\r
- clkout1_buf : BUFG\r
- port map\r
- (O => CLK_OUT1,\r
- I => clkout0);\r
-\r
-\r
-\r
-end xilinx;\r
+-- file: clk_wiz_v2_1.vhd
+--
+-- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1 100.000 0.000 50.000 130.958 98.575
+-- CLK_OUT2 200.000 0.000 50.000 114.829 98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock Input Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary 100.000 0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity gtxKintex7FEE80_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end gtxKintex7FEE80_CLOCK_MODULE;
+
+architecture xilinx of gtxKintex7FEE80_CLOCK_MODULE is
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of xilinx : architecture is "gtxKintex7FEE80,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+ -- Input clock buffering / unused connectors
+ signal clkin1 : std_logic;
+ -- Output clock buffering / unused connectors
+ signal clkfbout : std_logic;
+ signal clkfbout_buf : std_logic;
+ signal clkfboutb_unused : std_logic;
+ signal clkout0 : std_logic;
+ signal clkout0b_unused : std_logic;
+ signal clkout1 : std_logic;
+ signal clkout1b_unused : std_logic;
+ signal clkout2 : std_logic;
+ signal clkout2b_unused : std_logic;
+ signal clkout3 : std_logic;
+ signal clkout3b_unused : std_logic;
+ signal clkout4_unused : std_logic;
+ signal clkout5_unused : std_logic;
+ signal clkout6_unused : std_logic;
+ -- Dynamic programming unused signals
+ signal do_unused : std_logic_vector(15 downto 0);
+ signal drdy_unused : std_logic;
+ -- Dynamic phase shift unused signals
+ signal psdone_unused : std_logic;
+ -- Unused status signals
+ signal clkfbstopped_unused : std_logic;
+ signal clkinstopped_unused : std_logic;
+begin
+
+
+ -- Input buffering
+ --------------------------------------
+ clkin1_buf : BUFG
+ port map
+ (O => clkin1,
+ I => CLK_IN);
+
+ -- Clocking primitive
+ --------------------------------------
+ -- Instantiation of the MMCM primitive
+ -- * Unused inputs are tied off
+ -- * Unused outputs are labeled unused
+
+ mmcm_adv_inst : MMCME2_ADV
+ generic map
+ (BANDWIDTH => "OPTIMIZED",
+ CLKOUT4_CASCADE => FALSE,
+ COMPENSATION => "ZHOLD",
+ STARTUP_WAIT => FALSE,
+ DIVCLK_DIVIDE => DIVIDE,
+ CLKFBOUT_MULT_F => MULT,
+ CLKFBOUT_PHASE => 0.000,
+ CLKFBOUT_USE_FINE_PS => FALSE,
+ CLKOUT0_DIVIDE_F => OUT0_DIVIDE,
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKOUT0_USE_FINE_PS => FALSE,
+ CLKIN1_PERIOD => CLK_PERIOD,
+ CLKOUT1_DIVIDE => OUT1_DIVIDE,
+ CLKOUT1_PHASE => 0.000,
+ CLKOUT1_DUTY_CYCLE => 0.500,
+ CLKOUT1_USE_FINE_PS => FALSE,
+ CLKOUT2_DIVIDE => OUT2_DIVIDE,
+ CLKOUT2_PHASE => 0.000,
+ CLKOUT2_DUTY_CYCLE => 0.500,
+ CLKOUT2_USE_FINE_PS => FALSE,
+ CLKOUT3_DIVIDE => OUT3_DIVIDE,
+ CLKOUT3_PHASE => 0.000,
+ CLKOUT3_DUTY_CYCLE => 0.500,
+ CLKOUT3_USE_FINE_PS => FALSE,
+ REF_JITTER1 => 0.010)
+ port map
+ -- Output clocks
+ (CLKFBOUT => clkfbout,
+ CLKFBOUTB => clkfboutb_unused,
+ CLKOUT0 => clkout0,
+ CLKOUT0B => clkout0b_unused,
+ CLKOUT1 => clkout1,
+ CLKOUT1B => clkout1b_unused,
+ CLKOUT2 => clkout2,
+ CLKOUT2B => clkout2b_unused,
+ CLKOUT3 => clkout3,
+ CLKOUT3B => clkout3b_unused,
+ CLKOUT4 => clkout4_unused,
+ CLKOUT5 => clkout5_unused,
+ CLKOUT6 => clkout6_unused,
+ -- Input clock control
+ CLKFBIN => clkfbout,
+ CLKIN1 => clkin1,
+ CLKIN2 => '0',
+ -- Tied to always select the primary input clock
+ CLKINSEL => '1',
+ -- Ports for dynamic reconfiguration
+ DADDR => (others => '0'),
+ DCLK => '0',
+ DEN => '0',
+ DI => (others => '0'),
+ DO => do_unused,
+ DRDY => drdy_unused,
+ DWE => '0',
+ -- Ports for dynamic phase shift
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ PSDONE => psdone_unused,
+ -- Other control and status signals
+ LOCKED => MMCM_LOCKED_OUT,
+ CLKINSTOPPED => clkinstopped_unused,
+ CLKFBSTOPPED => clkfbstopped_unused,
+ PWRDWN => '0',
+ RST => MMCM_RESET_IN);
+
+ -- Output buffering
+ -------------------------------------
+ --clkf_buf : BUFG
+ --port map
+ -- (O => clkfbout_buf,
+ -- I => clkfbout);
+
+
+ clkout0_buf : BUFG
+ port map
+ (O => CLK0_OUT,
+ I => clkout0);
+
+ clkout1_buf : BUFG
+ port map
+ (O => CLK1_OUT,
+ I => clkout1);
+
+-- clkout2_buf : BUFG
+-- port map
+-- (O => CLK2_OUT,
+-- I => clkout2);
+--
+-- clkout3_buf : BUFG
+-- port map
+-- (O => CLK3_OUT,
+-- I => clkout3);
+
+CLK2_OUT <= '0';
+CLK3_OUT <= '0';
+end xilinx;
--- /dev/null
+---------------------------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_common.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_common
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity gtxKintex7FEE80_common is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
+ SIM_QPLLREFCLK_SEL : bit_vector := "001"
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK1_IN : in std_logic;
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+);
+
+end gtxKintex7FEE80_common;
+
+architecture RTL of gtxKintex7FEE80_common is
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_TOP : integer := 16;
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
+
+begin
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+
+ gtxe2_common_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
+ SIM_VERSION => "4.0",
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (1)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GTREFCLK0_IN,
+ GTREFCLK1 => GTREFCLK1_IN,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports -----------------------
+ QPLLDMONITOR => open,
+ ----------------------- Common Block - Clocking Ports ----------------------
+ QPLLOUTCLK => QPLLOUTCLK_OUT,
+ QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
+ REFCLKOUTMONITOR => open,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => QPLLLOCK_OUT,
+ QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_vcc_i,
+ QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
+ QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
+ QPLLRESET => QPLLRESET_IN,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ --------------------------------- QPLL Ports -------------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "11111",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+end RTL;
--- /dev/null
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_common_reset.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module gtxKintex7FEE80_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity gtxKintex7FEE80_common_reset is
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic:= '0' --Reset QPLL
+ );
+end gtxKintex7FEE80_common_reset;
+
+architecture RTL of gtxKintex7FEE80_common_reset is
+
+
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+
+ signal init_wait_count : std_logic_vector(7 downto 0) :=(others => '0');
+ signal init_wait_done : std_logic :='0';
+ signal common_reset_asserted : std_logic :='0';
+ signal common_reset_i : std_logic ;
+
+ type rst_type is(
+ INIT, ASSERT_COMMON_RESET);
+
+ signal state : rst_type := INIT;
+
+begin
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ state <= INIT;
+ common_reset_asserted <= '0';
+ COMMON_RESET <= '0';
+ else
+
+ case state is
+ when INIT =>
+ if init_wait_done = '1' then
+ state <= ASSERT_COMMON_RESET;
+ end if;
+
+ when ASSERT_COMMON_RESET =>
+ if common_reset_asserted = '0' then
+ COMMON_RESET <= '1';
+ common_reset_asserted <= '1';
+ else
+ COMMON_RESET <= '0';
+ end if;
+ when OTHERS =>
+ state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_gt_usrclk_source.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity gtxKintex7FEE80_GT_USRCLK_SOURCE is
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_TXCLK_LOCK_OUT : out std_logic;
+ GT0_TX_MMCM_RESET_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_OUT : out std_logic
+);
+
+
+end gtxKintex7FEE80_GT_USRCLK_SOURCE;
+
+architecture RTL of gtxKintex7FEE80_GT_USRCLK_SOURCE is
+
+component GTXKINTEX7FEE80_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+
+ attribute syn_noclockbuf : boolean;
+ signal q0_clk0_gtrefclk : std_logic;
+ attribute syn_noclockbuf of q0_clk0_gtrefclk : signal is true;
+
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal txoutclk_mmcm0_locked_i : std_logic;
+ signal txoutclk_mmcm0_reset_i : std_logic;
+ signal gt0_txoutclk_to_mmcm_i : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+ gt0_txoutclk_i <= GT0_TXOUTCLK_IN;
+ gt0_rxoutclk_i <= GT0_RXOUTCLK_IN;
+
+ Q0_CLK0_GTREFCLK_OUT <= q0_clk0_gtrefclk;
+
+ --IBUFDS_GTE2
+ ibufds_instq0_clk0 : IBUFDS_GTE2
+ port map
+ (
+ O => q0_clk0_gtrefclk,
+ ODIV2 => open,
+ CEB => tied_to_ground_i,
+ I => Q0_CLK0_GTREFCLK_PAD_P_IN,
+ IB => Q0_CLK0_GTREFCLK_PAD_N_IN
+ );
+
+
+
+ -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+ -- for improved jitter performance, and to avoid consuming an additional BUFG
+ txoutclk_mmcm0_reset_i <= GT0_TX_MMCM_RESET_IN;
+ txoutclk_mmcm0_i : gtxKintex7FEE80_CLOCK_MODULE
+ generic map
+ (
+ MULT => 40.0, --// 35.0, Modified
+ DIVIDE => 4,
+ CLK_PERIOD => 12.5,
+ OUT0_DIVIDE => 8.0, --// 7.0 Modified
+ OUT1_DIVIDE => 4, --// 1 Modified
+ OUT2_DIVIDE => 1,
+ OUT3_DIVIDE => 1
+ )
+ port map
+ (
+ CLK0_OUT => gt0_txusrclk_i,
+ CLK1_OUT => GT0_TXUSRCLKX2_OUT, --// Modified
+ CLK2_OUT => open,
+ CLK3_OUT => open,
+ CLK_IN => gt0_txoutclk_i,
+ MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
+ MMCM_RESET_IN => txoutclk_mmcm0_reset_i
+ );
+
+
+ rxoutclk_bufg1_i : BUFG
+ port map
+ (
+ I => gt0_rxoutclk_i,
+ O => gt0_rxusrclk_i
+ );
+
+
+
+
+GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT0_TXCLK_LOCK_OUT <= txoutclk_mmcm0_locked_i;
+GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtxkintex7fee80_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module gtxKintex7FEE80_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity gtxKintex7FEE80_support is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 12
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_OUT : out std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic; --// Modified
+ GT0_QPLLOUTREFCLK_IN : in std_logic; --// Modified
+ sysclk_in : in std_logic;
+ refclk_out : out std_logic --// Modified
+
+);
+
+end gtxKintex7FEE80_support;
+
+architecture RTL of gtxKintex7FEE80_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component gtxKintex7FEE80
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y0)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component gtxKintex7FEE80_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component gtxKintex7FEE80_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component gtxKintex7FEE80_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_TXCLK_LOCK_OUT : out std_logic;
+ GT0_TX_MMCM_RESET_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q0_CLK0_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y0)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt0_txmmcm_lock_i : std_logic;
+ signal gt0_txmmcm_reset_i : std_logic;
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q0_clk0_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+ GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+ gt0_qplloutclk_i <= gt0_qplloutclk_in; --// Modified
+ gt0_qplloutrefclk_i <= gt0_qplloutrefclk_in; --// Modified
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+
+
+ gt_usrclk_source : gtxKintex7FEE80_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXUSRCLKX2_OUT => GT0_TXUSRCLKX2_OUT, --// Modified
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_TXCLK_LOCK_OUT => gt0_txmmcm_lock_i,
+ GT0_TX_MMCM_RESET_IN => gt0_txmmcm_reset_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
+ Q0_CLK0_GTREFCLK_PAD_N_IN => Q0_CLK0_GTREFCLK_PAD_N_IN,
+ Q0_CLK0_GTREFCLK_PAD_P_IN => Q0_CLK0_GTREFCLK_PAD_P_IN,
+ Q0_CLK0_GTREFCLK_OUT => q0_clk0_refclk_i
+
+ );
+refclk_out <= q0_clk0_refclk_i; --// Modified
+sysclk_in_i <= sysclk_in;
+
+--// Modified
+ -- common0_i:gtxKintex7FEE80_common
+ -- generic map
+ -- (
+ -- WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ -- SIM_QPLLREFCLK_SEL => "001"
+ -- )
+ -- port map
+ -- (
+ -- QPLLREFCLKSEL_IN => "001",
+ -- GTREFCLK0_IN => q0_clk0_refclk_i,
+ -- GTREFCLK1_IN => tied_to_ground_i,
+ -- QPLLLOCK_OUT => gt0_qplllock_i,
+ -- QPLLLOCKDETCLK_IN => sysclk_in_i,
+ -- QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ -- QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ -- QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ -- QPLLRESET_IN => gt0_qpllreset_t
+
+-- );
+
+ common_reset_i:gtxKintex7FEE80_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ gtxKintex7FEE80_init_i : gtxKintex7FEE80
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_mmcm_lock_in => gt0_txmmcm_lock_i,
+ gt0_tx_mmcm_reset_out => gt0_txmmcm_reset_i,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y0)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => q0_clk0_refclk_i,
+ gt0_gtrefclk1_in => tied_to_ground_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP5_VAUXN5">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP6_VAUXN6">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP7_VAUXN7">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP8_VAUXN8">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP9_VAUXN9">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VP_VN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_AVERAGING">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_CALIBRATION">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_TEMPERATURE">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP12_VAUXN12">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP3_VAUXN3">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP4_VAUXN4">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP7_VAUXN7">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VBRAM">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VCCPINT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VP_VN">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VREFN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VREFP">false</spirit:configurableElementValue>
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+ <xilinx:configElementInfos>
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+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_16x9</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
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+</spirit:design>
--- /dev/null
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--- /dev/null
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--- /dev/null
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+</spirit:design>
--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_39">X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_4">X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_40">X</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_47">X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_48">X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_5">X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_6">X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_7">X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_8">X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_9">X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INIT_CLK">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LANE_WIDTH">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LINE_RATE">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK_FREQUENCY">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK_SOURCE">none</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ROW_USED">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_START_LANE">X0Y0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_START_QUAD">X0Y0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UCOLUMN_USED">right</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_BYTESWAP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_CHIPSCOPE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_CRC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_SCRAMBLER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_active_transceiverquads">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">aurora_dual</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRP_FREQ">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dataflow_Config">Duplex</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Mode">Framing</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLEEND_GTREFCLK">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLEEND_INITCLK">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AURORA_LANES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GT_CLOCK_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GT_LOC_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GT_LOC_2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GT_LOC_3" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INIT_CLK" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LANE_WIDTH" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LINE_RATE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_REFCLK_FREQUENCY" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DRP_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Flow_Mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Interface_Mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SINGLEEND_INITCLK" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SupportLevel" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
---------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : sim_reset_mgt_model.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\ \r
---\r
---\r
--- Module SIM_RESET_MGT_MODEL\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---\r
--- The Reset On Configuration(ROC) module is part of the UNISIM library\r
--- and is required for emulating the GSR pulse at the beginning of functional\r
--- simulation in order to correctly reset the VHDL MGT smart model.This module\r
--- is required for simulation only.\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
+-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
+--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
---
+--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
---
+--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
---
+--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***************************** Entity Declaration *****************************\r
-\r
-entity SIM_RESET_MGT_MODEL is\r
-port \r
-(\r
- GSR_IN : in std_logic\r
-);\r
-end SIM_RESET_MGT_MODEL;\r
-\r
-architecture BEHAVIORAL of SIM_RESET_MGT_MODEL is\r
- \r
- \r
---********************************* Main Body of Code****************************\r
- \r
-begin \r
- GSR <= GSR_IN; \r
- ------------------------------ ROCBUF Instantiation ----------------------- \r
- -- This component is required for correctly resetting the VHDL GTX component on configuration\r
- -- It is for simulation alone and will be ripped out during synthesis.\r
- U1 : ROCBUF \r
- port map \r
- (\r
- I => GSR,\r
- O => open\r
- ); \r
-\r
-\r
-end BEHAVIORAL;\r
-\r
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+
+--
+-- AURORA
+--
+--
+-- Description: Aurora Package Definition
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use STD.TEXTIO.all;
+
+package AURORA_PKG is
+
+ function std_bool (EXP_IN : in boolean) return std_logic;
+
+end;
+
+package body AURORA_PKG is
+
+ function std_bool (EXP_IN : in boolean) return std_logic is
+
+ begin
+
+ if (EXP_IN) then
+
+ return('1');
+
+ else
+
+ return('0');
+
+ end if;
+
+ end std_bool;
+
+end;
--- /dev/null
+------------------------------------------------------------------------------
+-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+------------------------------------------------------------------------------
+--
+-- AXI_TO_LL_EXDES
+--
+--
+-- Description: This light wrapper/shim convertes Legacy LocalLink interface
+-- signals from AXI-4 Stream protocol signals
+--
+--
+------------------------------------------------------------------------------/
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_MISC.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity aurora_dual_AXI_TO_LL_EXDES is
+generic
+(
+ DATA_WIDTH : integer := 16; -- DATA bus width
+ STRB_WIDTH : integer := 2; -- STROBE bus width
+ REM_WIDTH : integer := 1; -- REM bus width
+ USE_UFC_REM : integer := 0 -- UFC REM bus width identifier
+);
+
+port
+(
+
+ ---------------------- AXI4-S Interface -------------------------------
+
+ AXI4_S_IP_TX_TDATA : in std_logic_vector (0 to DATA_WIDTH-1);
+ AXI4_S_IP_TX_TKEEP : in std_logic_vector (0 to STRB_WIDTH-1);
+ AXI4_S_IP_TX_TVALID : in std_logic;
+ AXI4_S_IP_TX_TLAST : in std_logic;
+ AXI4_S_OP_TX_TREADY : out std_logic;
+
+ ---------------------- LocalLink Interface ----------------------------
+ LL_OP_DATA : out std_logic_vector (0 to DATA_WIDTH-1);
+ LL_OP_REM : out std_logic_vector (0 to REM_WIDTH -1);
+ LL_OP_SRC_RDY_N : out std_logic;
+ LL_OP_SOF_N : out std_logic;
+ LL_OP_EOF_N : out std_logic;
+ LL_IP_DST_RDY_N : in std_logic;
+
+ ---------------------- System Interface ----------------------------
+ USER_CLK : in std_logic;
+ RESET : in std_logic;
+ CHANNEL_UP : in std_logic
+
+);
+
+end aurora_dual_AXI_TO_LL_EXDES;
+
+architecture BEHAVIORAL of aurora_dual_AXI_TO_LL_EXDES is
+ attribute core_generation_info : string;
+attribute core_generation_info of BEHAVIORAL : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+--***********************************Parameter Declarations***************************
+
+ constant DLY : time := 1 ns;
+
+ signal new_pkt_r : std_logic;
+ signal new_pkt : std_logic;
+ signal temp_cond : std_logic;
+ signal ll_op_sof : std_logic;
+ signal ll_ip_dst_rdy : std_logic;
+ signal AXI4_S_IP_TX_TKEEP_i : std_logic_vector(0 to STRB_WIDTH-1);
+
+begin
+
+--*********************************Main Body of Code**********************************
+
+
+
+ ll_ip_dst_rdy <= not LL_IP_DST_RDY_N;
+
+
+ process(USER_CLK)
+ begin
+ if(USER_CLK'event and USER_CLK='1') then
+ LL_OP_DATA <= AXI4_S_IP_TX_TDATA;
+ end if;
+ end process;
+
+
+ AXI4_S_IP_TX_TKEEP_i <= AXI4_S_IP_TX_TKEEP;
+
+
+
+
+ process(USER_CLK)
+ begin
+ if(USER_CLK'event and USER_CLK='1') then
+ LL_OP_SRC_RDY_N <= not AXI4_S_IP_TX_TVALID;
+ LL_OP_EOF_N <= not AXI4_S_IP_TX_TLAST;
+ end if;
+ end process;
+ process(USER_CLK)
+ begin
+ if(USER_CLK'event and USER_CLK='1') then
+ LL_OP_REM <= ("0" & AXI4_S_IP_TX_TKEEP_i(0)) + ("0" & AXI4_S_IP_TX_TKEEP_i(1)) + ("0" & AXI4_S_IP_TX_TKEEP_i(2)) + ("0" & AXI4_S_IP_TX_TKEEP_i(3)) - '1';
+ end if;
+ end process;
+ new_pkt <= '0' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
+ '1' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND not AXI4_S_IP_TX_TLAST) = '1') else
+ new_pkt_r;
+
+ temp_cond <= '0' when (new_pkt_r = '1') else
+ '1';
+ ll_op_sof <= temp_cond when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
+ (new_pkt and (not new_pkt_r));
+
+ process(USER_CLK)
+ begin
+ if(USER_CLK'event and USER_CLK='1') then
+ LL_OP_SOF_N <= not ll_op_sof;
+ end if;
+ end process;
+
+ process(USER_CLK)
+ begin
+ if(USER_CLK'event and USER_CLK='1') then
+ if(RESET = '1') then
+ new_pkt_r <= '0' after DLY;
+ elsif(CHANNEL_UP = '1') then
+ new_pkt_r <= new_pkt after DLY;
+ else
+ new_pkt_r <= '0' after DLY;
+ end if;
+ end if;
+ end process;
+
+ -- Assign output from temp signal
+ AXI4_S_OP_TX_TREADY <= ll_ip_dst_rdy;
+
+end BEHAVIORAL;
--- /dev/null
+------------------------------------------------------------------------------/
+-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+--------------------------------------------------------------------------------
+
+--Generic Help
+--C_CDC_TYPE : Defines the type of CDC needed
+-- 0 means pulse synchronizer. Used to transfer one clock pulse
+-- from prmry domain to scndry domain.
+-- 1 means level synchronizer. Used to transfer level signal.
+-- 2 means level synchronizer with ack. Used to transfer level
+-- signal. Input signal should change only when prmry_ack is detected
+--
+--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
+-- Set to 0 when incoming signal is purely floped signal.
+--
+--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
+-- it might be needed.
+-- 0 means reset not needed for sync flops
+-- 1 means reset needed for sync flops. i
+-- In this case prmry_resetn should be in prmry clock,
+-- while scndry_reset should be in scndry clock.
+--
+--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
+-- However, based on design buses can also be CDC'ed.
+-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
+-- Output is on scndry_vect_out.
+-- 1 means it is a single bit. In this case input be connected to prmry_in.
+-- Output is on scndry_out.
+--
+--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
+--
+--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
+-- Value of 0, 1 is allowed only for level CDC.
+-- Min value for Pulse CDC is 2
+--
+--Whenever this file is used following XDC constraint has to be added
+
+-- set_false_path -to [get_pins -hier *cdc_to*]
+
+
+--IO Ports
+--
+-- prmry_aclk : clock of originating domain (source domain)
+-- prmry_resetn : sync reset of originating clock domain (source domain)
+-- prmry_in : input signal bit. This should be a pure flop output without
+-- any combi logic. This is source.
+-- prmry_vect_in : bus signal. From Source domain.
+-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
+-- Used only when C_CDC_TYPE = 2
+-- scndry_aclk : destination clock.
+-- scndry_resetn : sync reset of destination domain
+-- scndry_out : sync'ed output in destination domain. Single bit.
+-- scndry_vect_out : sync'ed output in destination domain. bus.
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_misc.all;
+
+
+
+entity aurora_dual_cdc_sync_exdes is
+ generic (
+ C_CDC_TYPE : integer range 0 to 2 := 1 ;
+ -- 0 is pulse synch
+ -- 1 is level synch
+ -- 2 is ack based level sync
+ C_RESET_STATE : integer range 0 to 1 := 0 ;
+ -- 0 is reset not needed
+ -- 1 is reset needed
+ C_SINGLE_BIT : integer range 0 to 1 := 1 ;
+ -- 0 is bus input
+ -- 1 is single bit input
+ C_FLOP_INPUT : integer range 0 to 1 := 0 ;
+ C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
+ C_MTBF_STAGES : integer range 0 to 6 := 2
+ -- Vector Data witdth
+ );
+
+ port (
+ prmry_aclk : in std_logic ; --
+ prmry_resetn : in std_logic ; --
+ prmry_in : in std_logic ; --
+ prmry_vect_in : in std_logic_vector --
+ (C_VECTOR_WIDTH - 1 downto 0) ; --
+ prmry_ack : out std_logic ;
+ --
+ scndry_aclk : in std_logic ; --
+ scndry_resetn : in std_logic ; --
+ --
+ -- Primary to Secondary Clock Crossing --
+ scndry_out : out std_logic ; --
+ --
+ scndry_vect_out : out std_logic_vector --
+ (C_VECTOR_WIDTH - 1 downto 0) --
+
+ );
+
+end aurora_dual_cdc_sync_exdes;
+
+-------------------------------------------------------------------------------
+-- Architecture
+-------------------------------------------------------------------------------
+architecture implementation of aurora_dual_cdc_sync_exdes is
+ attribute DowngradeIPIdentifiedWarnings: string;
+ attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
+
+-------------------------------------------------------------------------------
+-- Functions
+-------------------------------------------------------------------------------
+
+-- No Functions Declared
+
+-------------------------------------------------------------------------------
+-- Constants Declarations
+-------------------------------------------------------------------------------
+
+-- No Constants Declared
+
+-------------------------------------------------------------------------------
+-- Begin architecture logic
+-------------------------------------------------------------------------------
+begin
+-- Generate PULSE clock domain crossing
+GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
+
+-- Primary to Secondary
+signal s_out_d1_cdc_to : std_logic := '0';
+signal s_out_d2 : std_logic := '0';
+signal s_out_d3 : std_logic := '0';
+signal s_out_d4 : std_logic := '0';
+signal s_out_d5 : std_logic := '0';
+signal s_out_d6 : std_logic := '0';
+signal s_out_d7 : std_logic := '0';
+signal s_out_re : std_logic := '0';
+signal prmry_in_xored : std_logic := '0';
+signal p_in_d1_cdc_from : std_logic := '0';
+
+
+
+ -----------------------------------------------------------------------------
+ -- ATTRIBUTE Declarations
+ -----------------------------------------------------------------------------
+ -- Prevent x-propagation on clock-domain crossing register
+ ATTRIBUTE async_reg : STRING;
+ ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_out_d5 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_out_d6 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_out_d7 : SIGNAL IS "true";
+
+ ATTRIBUTE shift_extract : STRING;
+ ATTRIBUTE shift_extract OF s_out_d1_cdc_to : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_out_d2 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_out_d3 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_out_d4 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_out_d5 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_out_d6 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_out_d7 : SIGNAL IS "no";
+
+begin
+
+ --*****************************************************************************
+ --** Asynchronous Pulse Clock Crossing **
+ --** PRIMARY TO SECONDARY OPEN-ENDED **
+ --*****************************************************************************
+
+prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
+
+ REG_P_IN : process(prmry_aclk)
+ begin
+ if(prmry_aclk'EVENT and prmry_aclk ='1')then
+ if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+ p_in_d1_cdc_from <= '0';
+ else
+ p_in_d1_cdc_from <= prmry_in_xored;
+ end if;
+ end if;
+ end process REG_P_IN;
+
+
+ P_IN_CROSS2SCNDRY : process(scndry_aclk)
+ begin
+ if(scndry_aclk'EVENT and scndry_aclk ='1')then
+ if(scndry_resetn = '0' and C_RESET_STATE = 1)then
+ s_out_d1_cdc_to <= '0';
+ s_out_d2 <= '0';
+ s_out_d3 <= '0';
+ s_out_d4 <= '0';
+ s_out_d5 <= '0';
+ s_out_d6 <= '0';
+ s_out_d7 <= '0';
+ scndry_out <= '0';
+ else
+ s_out_d1_cdc_to <= p_in_d1_cdc_from;
+ s_out_d2 <= s_out_d1_cdc_to;
+ s_out_d3 <= s_out_d2;
+ s_out_d4 <= s_out_d3;
+ s_out_d5 <= s_out_d4;
+ s_out_d6 <= s_out_d5;
+ s_out_d7 <= s_out_d6;
+ scndry_out <= s_out_re;
+ end if;
+ end if;
+ end process P_IN_CROSS2SCNDRY;
+
+MTBF_2 : if C_MTBF_STAGES = 2 generate
+begin
+ s_out_re <= s_out_d2 xor s_out_d3;
+
+end generate MTBF_2;
+
+MTBF_3 : if C_MTBF_STAGES = 3 generate
+begin
+ s_out_re <= s_out_d3 xor s_out_d4;
+
+end generate MTBF_3;
+
+MTBF_4 : if C_MTBF_STAGES = 4 generate
+begin
+ s_out_re <= s_out_d4 xor s_out_d5;
+
+end generate MTBF_4;
+
+MTBF_5 : if C_MTBF_STAGES = 5 generate
+begin
+ s_out_re <= s_out_d5 xor s_out_d6;
+
+end generate MTBF_5;
+
+MTBF_6 : if C_MTBF_STAGES = 6 generate
+begin
+ s_out_re <= s_out_d6 xor s_out_d7;
+
+end generate MTBF_6;
+
+ -- Feed secondary pulse out
+
+end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
+
+
+-- Generate LEVEL clock domain crossing with reset state = 0
+GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
+begin
+-- Primary to Secondary
+
+SINGLE_BIT : if C_SINGLE_BIT = 1 generate
+
+signal p_level_in_d1_cdc_from : std_logic := '0';
+signal p_level_in_int : std_logic := '0';
+signal s_level_out_d1_cdc_to : std_logic := '0';
+signal s_level_out_d2 : std_logic := '0';
+signal s_level_out_d3 : std_logic := '0';
+signal s_level_out_d4 : std_logic := '0';
+signal s_level_out_d5 : std_logic := '0';
+signal s_level_out_d6 : std_logic := '0';
+ -----------------------------------------------------------------------------
+ -- ATTRIBUTE Declarations
+ -----------------------------------------------------------------------------
+ -- Prevent x-propagation on clock-domain crossing register
+ ATTRIBUTE async_reg : STRING;
+ ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
+
+ ATTRIBUTE shift_extract : STRING;
+ ATTRIBUTE shift_extract OF s_level_out_d1_cdc_to : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_d2 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_d3 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_d4 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_d5 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_d6 : SIGNAL IS "no";
+
+ ATTRIBUTE keep : STRING;
+ ATTRIBUTE keep OF p_level_in_d1_cdc_from : SIGNAL IS "true";
+begin
+
+ --*****************************************************************************
+ --** Asynchronous Level Clock Crossing **
+ --** PRIMARY TO SECONDARY **
+ --*****************************************************************************
+ -- register is scndry to provide clean ff output to clock crossing logic
+
+INPUT_FLOP : if C_FLOP_INPUT = 1 generate
+begin
+
+ REG_PLEVEL_IN : process(prmry_aclk)
+ begin
+ if(prmry_aclk'EVENT and prmry_aclk ='1')then
+ if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+ p_level_in_d1_cdc_from <= '0';
+ else
+ p_level_in_d1_cdc_from <= prmry_in;
+ end if;
+ end if;
+ end process REG_PLEVEL_IN;
+
+ p_level_in_int <= p_level_in_d1_cdc_from;
+
+end generate INPUT_FLOP;
+
+
+NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
+begin
+
+ p_level_in_int <= prmry_in;
+
+end generate NO_INPUT_FLOP;
+
+ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
+ begin
+ if(scndry_aclk'EVENT and scndry_aclk ='1')then
+ if(scndry_resetn = '0' and C_RESET_STATE = 1)then
+ s_level_out_d1_cdc_to <= '0';
+ s_level_out_d2 <= '0';
+ s_level_out_d3 <= '0';
+ s_level_out_d4 <= '0';
+ s_level_out_d5 <= '0';
+ s_level_out_d6 <= '0';
+ else
+ s_level_out_d1_cdc_to <= p_level_in_int;
+ s_level_out_d2 <= s_level_out_d1_cdc_to;
+ s_level_out_d3 <= s_level_out_d2;
+ s_level_out_d4 <= s_level_out_d3;
+ s_level_out_d5 <= s_level_out_d4;
+ s_level_out_d6 <= s_level_out_d5;
+ end if;
+ end if;
+ end process CROSS_PLEVEL_IN2SCNDRY;
+
+
+
+
+MTBF_L1 : if C_MTBF_STAGES = 1 generate
+begin
+ scndry_out <= s_level_out_d1_cdc_to;
+
+
+end generate MTBF_L1;
+
+MTBF_L2 : if C_MTBF_STAGES = 2 generate
+begin
+
+ scndry_out <= s_level_out_d2;
+
+
+end generate MTBF_L2;
+
+MTBF_L3 : if C_MTBF_STAGES = 3 generate
+begin
+
+ scndry_out <= s_level_out_d3;
+
+
+
+end generate MTBF_L3;
+
+MTBF_L4 : if C_MTBF_STAGES = 4 generate
+begin
+ scndry_out <= s_level_out_d4;
+
+
+
+end generate MTBF_L4;
+
+MTBF_L5 : if C_MTBF_STAGES = 5 generate
+begin
+
+ scndry_out <= s_level_out_d5;
+
+
+end generate MTBF_L5;
+
+MTBF_L6 : if C_MTBF_STAGES = 6 generate
+begin
+
+ scndry_out <= s_level_out_d6;
+
+
+end generate MTBF_L6;
+
+end generate SINGLE_BIT;
+
+
+
+MULTI_BIT : if C_SINGLE_BIT = 0 generate
+
+signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+ -----------------------------------------------------------------------------
+ -- ATTRIBUTE Declarations
+ -----------------------------------------------------------------------------
+ -- Prevent x-propagation on clock-domain crossing register
+ ATTRIBUTE async_reg : STRING;
+ ATTRIBUTE async_reg OF s_level_out_bus_d1_cdc_to : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
+
+ ATTRIBUTE shift_extract : STRING;
+ ATTRIBUTE shift_extract OF s_level_out_bus_d1_cdc_to : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_bus_d2 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_bus_d3 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_bus_d4 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_bus_d5 : SIGNAL IS "no";
+ ATTRIBUTE shift_extract OF s_level_out_bus_d6 : SIGNAL IS "no";
+
+begin
+
+ --*****************************************************************************
+ --** Asynchronous Level Clock Crossing **
+ --** PRIMARY TO SECONDARY **
+ --*****************************************************************************
+ -- register is scndry to provide clean ff output to clock crossing logic
+-- REG_PLEVEL_IN : process(prmry_aclk)
+-- begin
+-- if(prmry_aclk'EVENT and prmry_aclk ='1')then
+-- if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+-- p_level_in_bus_d1_cdc_from <= (others => '0');
+-- else
+-- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
+-- end if;
+-- end if;
+-- end process REG_PLEVEL_IN;
+
+ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
+ begin
+ if(scndry_aclk'EVENT and scndry_aclk ='1')then
+ if(scndry_resetn = '0' and C_RESET_STATE = 1)then
+ s_level_out_bus_d1_cdc_to <= (others => '0');
+ s_level_out_bus_d2 <= (others => '0');
+ s_level_out_bus_d3 <= (others => '0');
+ s_level_out_bus_d4 <= (others => '0');
+ s_level_out_bus_d5 <= (others => '0');
+ s_level_out_bus_d6 <= (others => '0');
+ else
+ s_level_out_bus_d1_cdc_to <= prmry_vect_in;
+ s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
+ s_level_out_bus_d3 <= s_level_out_bus_d2;
+ s_level_out_bus_d4 <= s_level_out_bus_d3;
+ s_level_out_bus_d5 <= s_level_out_bus_d4;
+ s_level_out_bus_d6 <= s_level_out_bus_d5;
+ end if;
+ end if;
+ end process CROSS_PLEVEL_IN2SCNDRY;
+
+
+
+MTBF_L1 : if C_MTBF_STAGES = 1 generate
+begin
+
+ scndry_vect_out <= s_level_out_bus_d1_cdc_to;
+
+
+end generate MTBF_L1;
+
+MTBF_L2 : if C_MTBF_STAGES = 2 generate
+begin
+
+ scndry_vect_out <= s_level_out_bus_d2;
+
+
+end generate MTBF_L2;
+
+MTBF_L3 : if C_MTBF_STAGES = 3 generate
+begin
+
+ scndry_vect_out <= s_level_out_bus_d3;
+
+
+
+end generate MTBF_L3;
+
+MTBF_L4 : if C_MTBF_STAGES = 4 generate
+begin
+ scndry_vect_out <= s_level_out_bus_d4;
+
+
+
+end generate MTBF_L4;
+
+MTBF_L5 : if C_MTBF_STAGES = 5 generate
+begin
+
+ scndry_vect_out <= s_level_out_bus_d5;
+
+
+end generate MTBF_L5;
+
+MTBF_L6 : if C_MTBF_STAGES = 6 generate
+begin
+
+ scndry_vect_out <= s_level_out_bus_d6;
+
+
+end generate MTBF_L6;
+
+end generate MULTI_BIT;
+
+
+end generate GENERATE_LEVEL_P_S_CDC;
+
+
+GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
+-- Primary to Secondary
+
+
+signal p_level_in_d1_cdc_from : std_logic := '0';
+signal p_level_in_int : std_logic := '0';
+signal s_level_out_d1_cdc_to : std_logic := '0';
+signal s_level_out_d2 : std_logic := '0';
+signal s_level_out_d3 : std_logic := '0';
+signal s_level_out_d4 : std_logic := '0';
+signal s_level_out_d5 : std_logic := '0';
+signal s_level_out_d6 : std_logic := '0';
+signal p_level_out_d1_cdc_to : std_logic := '0';
+signal p_level_out_d2 : std_logic := '0';
+signal p_level_out_d3 : std_logic := '0';
+signal p_level_out_d4 : std_logic := '0';
+signal p_level_out_d5 : std_logic := '0';
+signal p_level_out_d6 : std_logic := '0';
+signal p_level_out_d7 : std_logic := '0';
+signal scndry_out_int : std_logic := '0';
+signal prmry_pulse_ack : std_logic := '0';
+ -----------------------------------------------------------------------------
+ -- ATTRIBUTE Declarations
+ -----------------------------------------------------------------------------
+ -- Prevent x-propagation on clock-domain crossing register
+ ATTRIBUTE async_reg : STRING;
+ ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
+
+ ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF p_level_out_d3 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF p_level_out_d4 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF p_level_out_d5 : SIGNAL IS "true";
+ ATTRIBUTE async_reg OF p_level_out_d6 : SIGNAL IS "true";
+
+begin
+
+ --*****************************************************************************
+ --** Asynchronous Level Clock Crossing **
+ --** PRIMARY TO SECONDARY **
+ --*****************************************************************************
+ -- register is scndry to provide clean ff output to clock crossing logic
+INPUT_FLOP : if C_FLOP_INPUT = 1 generate
+begin
+
+ REG_PLEVEL_IN : process(prmry_aclk)
+ begin
+ if(prmry_aclk'EVENT and prmry_aclk ='1')then
+ if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+ p_level_in_d1_cdc_from <= '0';
+ else
+ p_level_in_d1_cdc_from <= prmry_in;
+ end if;
+ end if;
+ end process REG_PLEVEL_IN;
+
+ p_level_in_int <= p_level_in_d1_cdc_from;
+
+end generate INPUT_FLOP;
+
+
+NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
+begin
+
+ p_level_in_int <= prmry_in;
+
+end generate NO_INPUT_FLOP;
+
+ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
+ begin
+ if(scndry_aclk'EVENT and scndry_aclk ='1')then
+ if(scndry_resetn = '0' and C_RESET_STATE = 1)then
+ s_level_out_d1_cdc_to <= '0';
+ s_level_out_d2 <= '0';
+ s_level_out_d3 <= '0';
+ s_level_out_d4 <= '0';
+ s_level_out_d5 <= '0';
+ s_level_out_d6 <= '0';
+ else
+ s_level_out_d1_cdc_to <= p_level_in_int;
+ s_level_out_d2 <= s_level_out_d1_cdc_to;
+ s_level_out_d3 <= s_level_out_d2;
+ s_level_out_d4 <= s_level_out_d3;
+ s_level_out_d5 <= s_level_out_d4;
+ s_level_out_d6 <= s_level_out_d5;
+ end if;
+ end if;
+ end process CROSS_PLEVEL_IN2SCNDRY;
+
+
+ CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
+ begin
+ if(prmry_aclk'EVENT and prmry_aclk ='1')then
+ if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+ p_level_out_d1_cdc_to <= '0';
+ p_level_out_d2 <= '0';
+ p_level_out_d3 <= '0';
+ p_level_out_d4 <= '0';
+ p_level_out_d5 <= '0';
+ p_level_out_d6 <= '0';
+ p_level_out_d7 <= '0';
+ prmry_ack <= '0';
+ else
+ p_level_out_d1_cdc_to <= scndry_out_int;
+ p_level_out_d2 <= p_level_out_d1_cdc_to;
+ p_level_out_d3 <= p_level_out_d2;
+ p_level_out_d4 <= p_level_out_d3;
+ p_level_out_d5 <= p_level_out_d4;
+ p_level_out_d6 <= p_level_out_d5;
+ p_level_out_d7 <= p_level_out_d6;
+ prmry_ack <= prmry_pulse_ack;
+ end if;
+ end if;
+ end process CROSS_PLEVEL_SCNDRY2PRMRY;
+
+
+
+
+MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
+begin
+
+ scndry_out_int <= s_level_out_d2;
+ prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
+
+
+end generate MTBF_L2;
+
+MTBF_L3 : if C_MTBF_STAGES = 3 generate
+begin
+
+ scndry_out_int <= s_level_out_d3;
+ prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
+
+
+
+end generate MTBF_L3;
+
+MTBF_L4 : if C_MTBF_STAGES = 4 generate
+begin
+ scndry_out_int <= s_level_out_d4;
+ prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
+
+
+
+end generate MTBF_L4;
+
+MTBF_L5 : if C_MTBF_STAGES = 5 generate
+begin
+
+ scndry_out_int <= s_level_out_d5;
+ prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
+
+
+end generate MTBF_L5;
+
+MTBF_L6 : if C_MTBF_STAGES = 6 generate
+begin
+
+ scndry_out_int <= s_level_out_d6;
+ prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
+
+
+end generate MTBF_L6;
+
+ scndry_out <= scndry_out_int;
+
+
+end generate GENERATE_LEVEL_ACK_P_S_CDC;
+
+
+end implementation;
--- /dev/null
+-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+
+--
+-- CLOCK_MODULE
+--
+--
+--
+-- Description: A module provided as a convenience for desingners using 4-byte
+-- lane Aurora Modules. This module takes the V5 reference clock as
+-- input, and produces a fabric clock on a global clock net suitable
+-- for driving application logic connected to the Aurora User Interface.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+-- synthesis translate_off
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- synthesis translate_on
+
+entity aurora_dual_CLOCK_MODULE is
+
+ port (
+ INIT_CLK_P : in std_logic;
+ INIT_CLK_N : in std_logic;
+ INIT_CLK_O : out std_logic;
+ GT_CLK : in std_logic;
+ GT_CLK_LOCKED : in std_logic;
+ USER_CLK : out std_logic;
+ SYNC_CLK : out std_logic;
+ PLL_NOT_LOCKED : out std_logic
+
+ );
+
+end aurora_dual_CLOCK_MODULE;
+
+architecture MAPPED of aurora_dual_CLOCK_MODULE is
+ attribute core_generation_info : string;
+ attribute core_generation_info of MAPPED : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+ component IBUFDS
+ port (
+
+ O : out std_ulogic;
+ I : in std_ulogic;
+ IB : in std_ulogic);
+
+ end component;
+
+
+-- External Register Declarations --
+
+
+ component BUFG
+
+ port (
+
+ O : out std_ulogic;
+ I : in std_ulogic
+
+ );
+
+ end component;
+
+ signal user_clk_i : std_logic;
+ signal INIT_CLK_I : std_logic;
+
+begin
+
+
+
+ USER_CLK <= user_clk_i;
+ SYNC_CLK <= user_clk_i;
+ PLL_NOT_LOCKED <= not GT_CLK_LOCKED;
+
+ -- The User Clock is distributed on a global clock net.
+ user_clk_buf_i : BUFG
+
+ port map (
+
+ I => GT_CLK,
+ O => user_clk_i
+
+ );
+ -- init_clk_ibufg_i : IBUFDS --// Modified
+ -- port map (
+ -- I => INIT_CLK_P,
+ -- IB => INIT_CLK_N,
+ -- O => INIT_CLK_I
+ -- );
+
+ -- init_clk_buf_i : BUFG
+ -- port map
+ -- (
+ -- I => INIT_CLK_I,
+ -- O => INIT_CLK_O
+ -- );
+INIT_CLK_O <= '0'; --// Modified
+
+end MAPPED;
--- /dev/null
+------------------------------------------------------------------------------/
+-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+--------------------------------------------------------------------------------
+library IEEE;
+ use IEEE.numeric_std.all;
+ use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_misc.all;
+ use ieee.std_logic_1164.all;
+
+library UNISIM;
+ use UNISIM.Vcomponents.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity aurora_dual_gt_common_wrapper is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
+);
+port
+(
+--____________________________COMMON PORTS ,_______________________________{
+ gt_qpllclk_quad1_i : out std_logic;
+ gt_qpllrefclk_quad1_i : out std_logic;
+--____________________________COMMON PORTS ,_______________________________}
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ gt0_gtrefclk0_common_in : in std_logic;
+ ------------------------- Common Block - QPLL Ports ------------------------
+ gt0_qplllock_out : out std_logic;
+ gt0_qplllockdetclk_in : in std_logic;
+ gt0_qpllrefclklost_out : out std_logic;
+ gt0_qpllreset_in : in std_logic
+);
+
+end aurora_dual_gt_common_wrapper;
+
+architecture STRUCTURE of aurora_dual_gt_common_wrapper is
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_TOP : integer := 40;
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+
+--********************************* Main Body of Code**************************
+
+begin
+
+--********************************* Main Body of Code**************************
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+gtxe2_common_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => ("001"),
+ SIM_VERSION => ("4.0"),
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (1)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => gt0_gtrefclk0_common_in,
+ GTREFCLK1 => tied_to_ground_i,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLDMONITOR => open,
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => gt0_qplllock_out,
+ QPLLLOCKDETCLK => gt0_qplllockdetclk_in,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTCLK => gt_qpllclk_quad1_i,
+ QPLLOUTREFCLK => gt_qpllrefclk_quad1_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_vcc_i,
+ QPLLREFCLKLOST => gt0_qpllrefclklost_out,
+ QPLLREFCLKSEL => "001",
+ QPLLRESET => gt0_qpllreset_in,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ REFCLKOUTMONITOR => open,
+ ----------------------------- Common Block Ports ---------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "11111",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+end STRUCTURE;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+------------------------------------------------------------------------------
+--
+-- LL_TO_AXI_EXDES
+--
+--
+-- Description: This light wrapper/shim convertes Legacy LocalLink interface
+-- signals from AXI-4 Stream protocol signals
+--
+--
+------------------------------------------------------------------------------/
+library IEEE;
+use IEEE.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_misc.all;
+use ieee.std_logic_1164.all;
+
+entity aurora_dual_LL_TO_AXI_EXDES is
+generic
+(
+ DATA_WIDTH : integer := 16; -- DATA bus width
+ STRB_WIDTH : integer := 2; -- STROBE bus width
+ USE_UFC_REM : integer := 0; -- UFC REM bus width identifier
+ USE_4_NFC : integer := 0; -- 0 => PDU, 1 => NFC, 2 => UFC
+ REM_WIDTH : integer := 1 -- REM bus width
+);
+
+port
+(
+
+ ---------------------- AXI4-S Interface -------------------------------
+ AXI4_S_OP_TDATA : out std_logic_vector (0 to DATA_WIDTH-1);
+ AXI4_S_OP_TKEEP : out std_logic_vector (0 to STRB_WIDTH-1);
+ AXI4_S_OP_TVALID : out std_logic;
+ AXI4_S_OP_TLAST : out std_logic;
+ AXI4_S_IP_TREADY : in std_logic;
+
+ ---------------------- LocalLink Interface ----------------------------
+ LL_IP_DATA : in std_logic_vector (0 to DATA_WIDTH-1);
+ LL_IP_REM : in std_logic_vector (0 to REM_WIDTH-1);
+ LL_IP_SRC_RDY_N : in std_logic;
+ LL_IP_SOF_N : in std_logic;
+ LL_IP_EOF_N : in std_logic;
+ LL_OP_DST_RDY_N : out std_logic
+
+);
+
+end aurora_dual_LL_TO_AXI_EXDES;
+
+architecture BEHAVIORAL of aurora_dual_LL_TO_AXI_EXDES is
+ attribute core_generation_info : string;
+attribute core_generation_info of BEHAVIORAL : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+--***********************************Parameter Declarations***************************
+
+ constant DLY : time := 1 ns;
+ signal ll_ip_rem_inc_shift : std_logic_vector(0 to STRB_WIDTH-1);
+ signal rem_int : integer range 0 to 4;
+ signal ufc_rem_int : integer range 0 to 16;
+signal AXI4_S_OP_TKEEP_i : std_logic_vector(0 to STRB_WIDTH-1);
+begin
+
+--*********************************Main Body of Code**********************************
+
+
+ AXI4_S_OP_TDATA <= LL_IP_DATA;
+
+
+ AXI4_S_OP_TKEEP <= AXI4_S_OP_TKEEP_i ;
+
+
+
+
+
+pdu_rem : if USE_UFC_REM = 0 generate
+ rem_int <= TO_INTEGER(unsigned (LL_IP_REM + '1'));
+ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl rem_int);
+AXI4_S_OP_TKEEP_i <= "1111" when (LL_IP_REM = "11") else
+ (not ll_ip_rem_inc_shift);
+end generate pdu_rem;
+
+ufc_rem : if USE_UFC_REM = 1 generate
+ ufc_rem_int <= TO_INTEGER(unsigned (LL_IP_REM + '1'));
+ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl ufc_rem_int);
+AXI4_S_OP_TKEEP_i <= "1111" when (LL_IP_REM = "11") else
+ (not ll_ip_rem_inc_shift);
+end generate ufc_rem;
+
+ AXI4_S_OP_TVALID <= not LL_IP_SRC_RDY_N;
+ AXI4_S_OP_TLAST <= not LL_IP_EOF_N;
+ LL_OP_DST_RDY_N <= not AXI4_S_IP_TREADY;
+
+end BEHAVIORAL;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_MISC.all;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+use WORK.AURORA_PKG.all;
+
+-- synthesis translate_off
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- synthesis translate_on
+
+entity aurora_dual_module is
+ port (
+ stable_clock : in std_logic; -- 80MHz
+ reset : in std_logic;
+ user_clock : out std_logic;
+ tx_data : in std_logic_vector(31 downto 0);
+ tx_first : in std_logic;
+ tx_last : in std_logic;
+ tx_write : in std_logic;
+ tx_allowed : out std_logic;
+ tx_inpipe : in std_logic;
+ rx_data : out std_logic_vector(31 downto 0);
+ rx_first : out std_logic;
+ rx_last : out std_logic;
+ rx_write : out std_logic;
+ rx_almostfull : in std_logic;
+ rx_inpipe : out std_logic;
+ locked : out std_logic;
+ error : out std_logic;
+ RXP : in std_logic_vector(0 to 1);
+ RXN : in std_logic_vector(0 to 1);
+ TXP : out std_logic_vector(0 to 1);
+ TXN : out std_logic_vector(0 to 1);
+ GTXQ0_P : in std_logic;
+ GTXQ0_N : in std_logic;
+ gt0_refclk_in : in std_logic;
+ gt0_qplllock_in : in std_logic;
+ gt0_qpllrefclklost_in : in std_logic;
+ gt0_qpllreset_out : out std_logic;
+ GT_QPLLOUTCLK_IN : in std_logic;
+ GT_QPLLOUTREFCLK_IN : in std_logic
+ );
+end aurora_dual_module;
+
+architecture MAPPED of aurora_dual_module is
+ attribute DowngradeIPIdentifiedWarnings: string;
+ attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
+ attribute core_generation_info : string;
+ attribute core_generation_info of MAPPED : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=40000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=true,c_ufc=false,flow_mode=None,interface_mode=Streaming,dataflow_config=Duplex}";
+
+-- Parameter Declarations --
+
+ constant DLY : time := 1 ns;
+
+-- External Register Declarations --
+
+ signal HARD_ERR_Buffer : std_logic;
+ signal SOFT_ERR_Buffer : std_logic;
+signal LANE_UP_Buffer : std_logic_vector(0 to 1);
+ signal CHANNEL_UP_Buffer : std_logic;
+signal TXP_Buffer : std_logic_vector(0 to 1);
+signal TXN_Buffer : std_logic_vector(0 to 1);
+
+-- Internal Register Declarations --
+
+ signal gt_reset_i : std_logic;
+ signal system_reset_i : std_logic;
+ signal sysreset_vio_i : std_logic;
+ signal sysreset_i : std_logic;
+ signal gtreset_vio_i : std_logic;
+ signal gtreset_vio_o : std_logic;
+ signal loopback_vio_i : std_logic_vector(2 downto 0);
+ signal loopback_vio_o : std_logic_vector(2 downto 0);
+
+-- Wire Declarations --
+
+ -- Stream TX Interface
+
+signal tx_d_i : std_logic_vector(0 to 31);
+signal tx_rem_i : std_logic_vector(0 to 1);
+ signal tx_src_rdy_n_i : std_logic;
+ signal tx_sof_n_i : std_logic;
+ signal tx_eof_n_i : std_logic;
+
+ signal tx_dst_rdy_n_i : std_logic;
+
+ -- LocalLink RX Interface
+
+signal rx_d_i : std_logic_vector(0 to 31);
+signal rx_rem_i : std_logic_vector(0 to 1) := (others => '1');
+ signal rx_src_rdy_n_i : std_logic;
+ signal rx_sof_n_i : std_logic;
+ signal rx_eof_n_i : std_logic;
+
+
+ -- Native Flow Control TX Interface
+
+ signal nfc_req_n_i : std_logic;
+ signal nfc_nb_i : std_logic_vector(0 to 3);
+ signal nfc_ack_n_i : std_logic;
+
+ -- Native Flow Control RX Interface
+ signal rx_snf_i : std_logic;
+ signal rx_fc_nb_i : std_logic_vector(0 to 3);
+ signal rx_fc_nb_int : std_logic_vector(0 to 3);
+
+ -- User Flow Control TX Interface
+
+ signal ufc_tx_req_n_i : std_logic;
+ signal ufc_tx_ms_i : std_logic_vector(0 to 2);
+ signal ufc_tx_ack_n_i : std_logic;
+
+ -- User Flow Control RX Inteface
+
+signal ufc_rx_data_i : std_logic_vector(0 to 31);
+signal ufc_rx_rem_i : std_logic_vector(0 to 1);
+ signal ufc_rx_src_rdy_n_i : std_logic;
+ signal ufc_rx_sof_n_i : std_logic;
+ signal ufc_rx_eof_n_i : std_logic;
+
+
+ -- Error Detection Interface
+
+ signal hard_err_i : std_logic;
+ signal soft_err_i : std_logic;
+ signal frame_err_i : std_logic;
+ -- Status
+
+ signal channel_up_i : std_logic;
+ signal channel_up_r : std_logic;
+ signal channel_up_r_vio : std_logic;
+signal lane_up_i : std_logic_vector(0 to 1);
+
+ -- Clock Compensation Control Interface
+
+ signal warn_cc_i : std_logic;
+
+ -- System Interface
+
+ signal pll_not_locked_i : std_logic;
+ signal pll_not_locked_ila : std_logic;
+ signal user_clk_i : std_logic;
+ signal reset_i : std_logic;
+ signal power_down_i : std_logic;
+ signal loopback_i : std_logic_vector(2 downto 0);
+ signal tx_lock_i : std_logic;
+ signal link_reset_i : std_logic := '0';
+ signal link_reset_ila : std_logic := '0';
+ signal rx_resetdone_i : std_logic;
+ signal tx_resetdone_i : std_logic;
+ signal tx_resetdone_ila : std_logic;
+ attribute keep : string;
+ signal init_clk_i : std_logic;
+ attribute keep of init_clk_i : signal is "true";
+signal daddr_in_i : std_logic_vector(8 downto 0);
+signal dclk_in_i : std_logic;
+signal den_in_i : std_logic;
+signal di_in_i : std_logic_vector(15 downto 0);
+signal drdy_out_unused_i : std_logic;
+signal drpdo_out_unused_i : std_logic_vector(15 downto 0);
+signal dwe_in_i : std_logic;
+signal daddr_in_LANE1_i : std_logic_vector(8 downto 0);
+signal dclk_in_LANE1_i : std_logic;
+signal den_in_LANE1_i : std_logic;
+signal di_in_LANE1_i : std_logic_vector(15 downto 0);
+signal drdy_out_LANE1_unused_i : std_logic;
+signal drpdo_out_LANE1_unused_i : std_logic_vector(15 downto 0);
+signal dwe_in_LANE1_i : std_logic;
+ --Frame check signals
+signal tied_to_ground_i : std_logic;
+signal tied_to_gnd_vec_i : std_logic_vector(0 to 31);
+
+ -- TX AXI PDU I/F signals
+signal tx_data_i : std_logic_vector(0 to 31);
+ signal tx_tvalid_i : std_logic;
+ signal tx_tready_i : std_logic;
+
+signal tx_tkeep_i : std_logic_vector(0 to 3);
+ signal tx_tlast_i : std_logic;
+ -- RX AXI PDU I/F signals
+signal rx_data_i : std_logic_vector(0 to 31);
+ signal rx_tvalid_i : std_logic;
+signal rx_tkeep_i : std_logic_vector(0 to 3);
+ signal rx_tlast_i : std_logic;
+
+ -- TX AXI UFC I/F signals
+signal axi_ufc_tx_ms_i : std_logic_vector(0 to 2);
+ signal axi_ufc_tx_req_n_i : std_logic;
+ signal axi_ufc_tx_ack_n_i : std_logic;
+
+ -- RX AXI UFC I/F signals
+signal axi_ufc_rx_data_i : std_logic_vector(0 to 31);
+signal axi_ufc_rx_rem_i : std_logic_vector(0 to 3);
+ signal axi_ufc_rx_src_rdy_n_i : std_logic;
+ signal axi_ufc_rx_eof_n_i : std_logic;
+
+ -- TX AXI NFC I/F signals
+ signal axi_nfc_nb_i : std_logic_vector(0 to 3);
+ signal axi_nfc_req_n_i : std_logic;
+ signal axi_nfc_ack_n_i : std_logic;
+
+
+
+
+
+ --SLACK Registers
+ signal lane_up_r : std_logic_vector(0 to 1);
+ signal lane_up_r2 : std_logic_vector(0 to 1);
+ signal drpclk_i : std_logic;
+
+-- Component Declarations --
+
+ component BUFG is
+ port (
+
+ O : out std_ulogic;
+ I : in std_ulogic
+
+ );
+ end component;
+
+
+ -- AXI Shim modules
+ component aurora_dual_LL_TO_AXI_EXDES is
+ generic
+ (
+ DATA_WIDTH : integer := 16; -- DATA bus width
+ USE_UFC_REM : integer := 0; -- UFC REM bus width identifier
+ STRB_WIDTH : integer := 2; -- STROBE bus width
+ USE_4_NFC : integer := 0; -- 0 => PDU, 1 => NFC, 2 => UFC
+ REM_WIDTH : integer := 1 -- REM bus width
+ );
+
+ port
+ (
+
+ ---------------------- AXI4-S Interface -------------------------------
+ AXI4_S_OP_TDATA : out std_logic_vector (0 to DATA_WIDTH-1);
+ AXI4_S_OP_TKEEP : out std_logic_vector (0 to STRB_WIDTH-1);
+ AXI4_S_OP_TVALID : out std_logic;
+ AXI4_S_OP_TLAST : out std_logic;
+ AXI4_S_IP_TREADY : in std_logic;
+
+ ---------------------- LocalLink Interface ----------------------------
+ LL_IP_DATA : in std_logic_vector (0 to DATA_WIDTH-1);
+ LL_IP_REM : in std_logic_vector (0 to REM_WIDTH-1);
+ LL_IP_SRC_RDY_N : in std_logic;
+ LL_IP_SOF_N : in std_logic;
+ LL_IP_EOF_N : in std_logic;
+ LL_OP_DST_RDY_N : out std_logic
+
+ );
+ end component;
+
+ component aurora_dual_AXI_TO_LL_EXDES is
+ generic
+ (
+ DATA_WIDTH : integer := 16; -- DATA bus width
+ STRB_WIDTH : integer := 2; -- STROBE bus width
+ REM_WIDTH : integer := 1; -- REM bus width
+ USE_UFC_REM : integer := 0 -- UFC REM bus width identifier
+ );
+
+ port
+ (
+
+ ---------------------- AXI4-S Interface -------------------------------
+ AXI4_S_IP_TX_TDATA : in std_logic_vector (0 to DATA_WIDTH-1);
+ AXI4_S_IP_TX_TKEEP : in std_logic_vector (0 to STRB_WIDTH-1);
+ AXI4_S_IP_TX_TVALID : in std_logic;
+ AXI4_S_IP_TX_TLAST : in std_logic;
+ AXI4_S_OP_TX_TREADY : out std_logic;
+
+ ---------------------- LocalLink Interface ----------------------------
+ LL_OP_DATA : out std_logic_vector (0 to DATA_WIDTH-1);
+ LL_OP_REM : out std_logic_vector (0 to REM_WIDTH -1);
+ LL_OP_SRC_RDY_N : out std_logic;
+ LL_OP_SOF_N : out std_logic;
+ LL_OP_EOF_N : out std_logic;
+ LL_IP_DST_RDY_N : in std_logic;
+
+ ---------------------- System Interface ----------------------------
+ USER_CLK : in std_logic;
+ RESET : in std_logic;
+ CHANNEL_UP : in std_logic
+
+ );
+ end component;
+
+
+
+
+ component aurora_dual_support
+ port (
+ -- TX Stream Interface
+s_axi_tx_tdata : in std_logic_vector(0 to 31);
+ s_axi_tx_tvalid : in std_logic;
+ s_axi_tx_tready : out std_logic;
+s_axi_tx_tkeep : in std_logic_vector(0 to 3);
+ s_axi_tx_tlast : in std_logic;
+
+ -- RX Stream Interface
+m_axi_rx_tdata : out std_logic_vector(0 to 31);
+m_axi_rx_tkeep : out std_logic_vector(0 to 3);
+ m_axi_rx_tvalid : out std_logic;
+ m_axi_rx_tlast : out std_logic;
+ -- Native Flow Control TX Interface
+ s_axi_nfc_req : in std_logic;
+ s_axi_nfc_nb : in std_logic_vector(0 to 3);
+ s_axi_nfc_ack : out std_logic;
+
+ -- Native Flow Control RX Interface
+ m_axi_rx_snf : out std_logic;
+ m_axi_rx_fc_nb : out std_logic_vector(0 to 3);
+ -- User Flow Control TX Interface
+ s_axi_ufc_tx_req : in std_logic;
+ s_axi_ufc_tx_ms : in std_logic_vector(0 to 2);
+ s_axi_ufc_tx_ack : out std_logic;
+ -- User Flow Control RX Inteface
+
+m_axi_ufc_rx_tdata : out std_logic_vector(0 to 31);
+m_axi_ufc_rx_tkeep : out std_logic_vector(0 to 3);
+ m_axi_ufc_rx_tvalid : out std_logic;
+ m_axi_ufc_rx_tlast : out std_logic;
+ -- GT Serial I/O
+
+ rxp : in std_logic_vector(0 to 1);
+ rxn : in std_logic_vector(0 to 1);
+
+ txp : out std_logic_vector(0 to 1);
+ txn : out std_logic_vector(0 to 1);
+
+ -- GT Reference Clock Interface
+ gt_refclk1_p : in std_logic;
+ gt_refclk1_n : in std_logic;
+ -- Error Detection Interface
+
+ hard_err : out std_logic;
+ soft_err : out std_logic;
+
+ frame_err : out std_logic;
+
+
+ -- Status
+
+ channel_up : out std_logic;
+ lane_up : out std_logic_vector(0 to 1);
+ -- System Interface
+
+ user_clk_out : out std_logic;
+ sys_reset_out : out std_logic;
+ gt_reset : in std_logic;
+ reset : in std_logic;
+ power_down : in std_logic;
+ loopback : in std_logic_vector(2 downto 0);
+ init_clk_p : in std_logic;
+ init_clk_n : in std_logic;
+ init_clk_out : out std_logic;
+ pll_not_locked_out : out std_logic;
+ tx_resetdone_out : out std_logic;
+ rx_resetdone_out : out std_logic;
+ link_reset_out : out std_logic;
+
+drpclk_in : in std_logic;
+drpaddr_in : in std_logic_vector(8 downto 0);
+drpdi_in : in std_logic_vector(15 downto 0);
+drpdo_out : out std_logic_vector(15 downto 0);
+drpen_in : in std_logic;
+drprdy_out : out std_logic;
+drpwe_in : in std_logic;
+drpaddr_in_lane1 : in std_logic_vector(8 downto 0);
+drpdi_in_lane1 : in std_logic_vector(15 downto 0);
+drpdo_out_lane1 : out std_logic_vector(15 downto 0);
+drpen_in_lane1 : in std_logic;
+drprdy_out_lane1 : out std_logic;
+drpwe_in_lane1 : in std_logic;
+
+
+ tx_lock : out std_logic;
+ sysclk_in : in std_logic; --// Modified
+ gt0_refclk_in : in std_logic; --// Modified
+ gt0_qplllock_in : in std_logic; --// Modified
+ gt0_qpllrefclklost_in : in std_logic; --// Modified
+ gt0_qpllreset_out : out std_logic; --// Modified
+ GT_QPLLOUTCLK_IN : in std_logic; --// Modified
+ GT_QPLLOUTREFCLK_IN : in std_logic --// Modified
+ );
+
+ end component;
+
+
+
+
+
+signal tx_allowed_S : std_logic;
+signal tx_data_S : std_logic_vector(31 downto 0);
+signal insertUFC_word_S : std_logic_vector(31 downto 0);
+signal insertUFC_S : std_logic;
+
+attribute mark_debug : string;
+
+-- attribute mark_debug of pll_not_locked_i : signal is "true";
+-- attribute mark_debug of power_down_i : signal is "true";
+-- attribute mark_debug of tx_lock_i : signal is "true";
+-- attribute mark_debug of rx_resetdone_i : signal is "true";
+-- attribute mark_debug of tx_resetdone_i : signal is "true";
+-- attribute mark_debug of lane_up_r2 : signal is "true";
+-- attribute mark_debug of hard_err_i : signal is "true";
+-- attribute mark_debug of soft_err_i : signal is "true";
+-- attribute mark_debug of frame_err_i : signal is "true";
+attribute mark_debug of lane_up_i : signal is "true";
+attribute mark_debug of locked : signal is "true";
+-- attribute mark_debug of channel_up_i : signal is "true";
+-- attribute mark_debug of gt0_qplllock_in : signal is "true";
+-- attribute mark_debug of gt0_qpllrefclklost_in : signal is "true";
+-- attribute mark_debug of gt0_qpllreset_out : signal is "true";
+-- attribute mark_debug of system_reset_i : signal is "true";
+-- attribute mark_debug of reset_i : signal is "true";
+-- attribute mark_debug of gtreset_vio_o : signal is "true";
+
+attribute mark_debug of tx_allowed_S : signal is "true";
+attribute mark_debug of tx_data_S : signal is "true";
+attribute mark_debug of nfc_req_n_i : signal is "true";
+attribute mark_debug of nfc_ack_n_i : signal is "true";
+attribute mark_debug of nfc_nb_i : signal is "true";
+
+attribute mark_debug of tx_write : signal is "true";
+attribute mark_debug of tx_data : signal is "true";
+attribute mark_debug of tx_first : signal is "true";
+attribute mark_debug of tx_last : signal is "true";
+attribute mark_debug of tx_allowed : signal is "true";
+attribute mark_debug of rx_data : signal is "true";
+attribute mark_debug of rx_write : signal is "true";
+attribute mark_debug of rx_first : signal is "true";
+attribute mark_debug of rx_last : signal is "true";
+attribute mark_debug of rx_almostfull : signal is "true";
+attribute mark_debug of rx_rem_i : signal is "true";
+
+attribute mark_debug of tx_inpipe : signal is "true";
+attribute mark_debug of rx_inpipe : signal is "true";
+attribute mark_debug of insertUFC_S : signal is "true";
+attribute mark_debug of ufc_tx_req_n_i : signal is "true";
+attribute mark_debug of ufc_tx_ack_n_i : signal is "true";
+attribute mark_debug of ufc_rx_src_rdy_n_i : signal is "true";
+attribute mark_debug of ufc_rx_sof_n_i : signal is "true";
+attribute mark_debug of ufc_rx_eof_n_i : signal is "true";
+attribute mark_debug of ufc_rx_data_i : signal is "true";
+
+
+
+begin
+
+tx_allowed <= tx_allowed_S;
+tx_allowed_S <= '1' when tx_dst_rdy_n_i='0' else '0';
+tx_src_rdy_n_i <= '0' when tx_write='1' else '1';
+reset_i <= reset;
+gtreset_vio_o <= reset;
+user_clock <= user_clk_i;
+rx_write <= '1' when rx_src_rdy_n_i='0' else '0';
+rx_first <= '1' when rx_sof_n_i='0' else '0';
+rx_last <= '1' when rx_eof_n_i='0' else '0';
+loopback_vio_o <= "000"; --// Modified 000
+tx_data_S <= insertUFC_word_S when insertUFC_S='1' else tx_data;
+gendata: for i in 0 to 31 generate
+tx_d_i(i) <= tx_data_S(i);
+rx_data(i) <= rx_d_i(i);
+end generate;
+tx_rem_i <= (others => '1');
+tx_sof_n_i<= '0' when tx_first='1' else '1';
+tx_eof_n_i<= '0' when tx_last='1' else '1';
+error <= '1' when (HARD_ERR_Buffer='1') or (SOFT_ERR_Buffer='1') else '0';
+locked <= '1' when (LANE_UP_Buffer="11") and (CHANNEL_UP_Buffer='1') else '0';
+
+TXP <= TXP_Buffer;
+TXN <= TXN_Buffer;
+init_clk_i <= stable_clock;
+drpclk_i <= stable_clock;
+-- drpclk_bufg : BUFG
+-- port map
+ -- (
+ -- I => stable_clock,
+ -- O => drpclk_i
+ -- );
+
+process (user_clk_i)
+variable retrycount_V : std_logic_vector(11 downto 0);
+begin
+ if (user_clk_i 'event and user_clk_i = '1') then
+ if nfc_req_n_i='0' then
+ retrycount_V := (others => '0');
+ if nfc_ack_n_i='0' then
+ nfc_req_n_i <= '1';
+ end if;
+ elsif (rx_almostfull='1') then
+ nfc_nb_i <= (others => '1');
+ if retrycount_V(retrycount_V'left)='1' then
+ nfc_req_n_i <= '0';
+ else
+ retrycount_V := retrycount_V+1;
+ end if;
+ else
+ nfc_nb_i <= (others => '0');
+ if rx_src_rdy_n_i='0' then
+ retrycount_V := (others => '0');
+ end if;
+ if retrycount_V(retrycount_V'left)='1' then
+ nfc_req_n_i <= '0';
+ else
+ retrycount_V := retrycount_V+1;
+ end if;
+ end if;
+ end if;
+end process;
+
+ufc_tx_ms_i <= "001";
+process (user_clk_i)
+variable retrycount_V : std_logic_vector(12 downto 0);
+variable busy_V : std_logic := '0';
+variable tx_insert_inpipe0_V : std_logic := '0';
+begin
+ if (user_clk_i 'event and user_clk_i = '1') then
+ insertUFC_S <= '0';
+ if (tx_write='1') and (tx_allowed_S='1') and (tx_first='1') then
+ busy_V := '1';
+ elsif (tx_write='1') and (tx_allowed_S='1') and (tx_last='1') then
+ busy_V := '0';
+ end if;
+ if ufc_tx_req_n_i='0' then
+ if ufc_tx_ack_n_i='0' then
+ ufc_tx_req_n_i <= '1';
+ insertUFC_S <= '1';
+ end if;
+ elsif tx_inpipe='0' then
+ insertUFC_word_S <= x"00000000";
+ if (busy_V='0') and (tx_write='0') and (tx_allowed_S='1') then
+ if tx_insert_inpipe0_V='0' then
+ retrycount_V := (others => '0');
+ ufc_tx_req_n_i <= '0';
+ tx_insert_inpipe0_V := '1';
+ elsif retrycount_V(retrycount_V'left)='1' then
+ retrycount_V := (others => '0');
+ ufc_tx_req_n_i <= '0';
+ tx_insert_inpipe0_V := '1';
+ else
+ retrycount_V := retrycount_V+1;
+ end if;
+ end if;
+ else
+ insertUFC_word_S <= x"00000001";
+ if tx_insert_inpipe0_V='1' then
+ tx_insert_inpipe0_V := '0';
+ retrycount_V := (others => '0');
+ ufc_tx_req_n_i <= '0';
+ tx_insert_inpipe0_V := '0';
+ else
+ if retrycount_V(retrycount_V'left)='1' then
+ retrycount_V := (others => '0');
+ ufc_tx_req_n_i <= '0';
+ tx_insert_inpipe0_V := '0';
+ else
+ retrycount_V := retrycount_V+1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+process (user_clk_i)
+begin
+ if (user_clk_i 'event and user_clk_i = '1') then
+ if (ufc_rx_src_rdy_n_i='0') and (ufc_rx_sof_n_i='0') and (ufc_rx_eof_n_i='0') then
+ rx_inpipe <= ufc_rx_data_i(0);
+ end if;
+ end if;
+end process;
+
+ tied_to_ground_i <= '0';
+
+ process (user_clk_i)
+ begin
+ if (user_clk_i 'event and user_clk_i = '1') then
+ lane_up_r <= lane_up_i;
+ lane_up_r2 <= lane_up_r;
+ end if;
+ end process;
+
+
+
+
+
+ -- Register User I/O --
+
+ -- Register User Outputs from core.
+
+ process (user_clk_i)
+
+ begin
+
+ if (user_clk_i 'event and user_clk_i = '1') then
+
+ HARD_ERR_Buffer <= hard_err_i;
+ SOFT_ERR_Buffer <= soft_err_i;
+ LANE_UP_Buffer <= lane_up_i;
+ CHANNEL_UP_Buffer <= channel_up_i;
+
+ end if;
+
+ end process;
+
+ -- System Interface
+
+ power_down_i <= '0';
+
+ process (user_clk_i)
+ begin
+ if (user_clk_i 'event and user_clk_i = '1') then
+ channel_up_r <= channel_up_i;
+ end if;
+ end process;
+
+
+daddr_in_i <= (others=>'0');
+dclk_in_i <= '0';
+den_in_i <= '0';
+di_in_i <= (others=>'0');
+dwe_in_i <= '0';
+daddr_in_LANE1_i <= (others=>'0');
+dclk_in_LANE1_i <= '0';
+den_in_LANE1_i <= '0';
+di_in_LANE1_i <= (others=>'0');
+dwe_in_LANE1_i <= '0';
+ -- _______________________________ Module Instantiations ________________________--
+
+
+ --_____________________________ RX AXI SHIM _______________________________
+ frame_chk_axi_to_ll_pdu_i : aurora_dual_AXI_TO_LL_EXDES
+ generic map
+ (
+ DATA_WIDTH => 32,
+ STRB_WIDTH => 4,
+ REM_WIDTH => 2,
+ USE_UFC_REM => 0
+ )
+ port map
+ (
+ -- AXI4-S input signals
+ AXI4_S_IP_TX_TVALID => rx_tvalid_i,
+ AXI4_S_OP_TX_TREADY => OPEN,
+ AXI4_S_IP_TX_TDATA => rx_data_i,
+ AXI4_S_IP_TX_TKEEP => rx_tkeep_i,
+ AXI4_S_IP_TX_TLAST => rx_tlast_i,
+
+ -- LocalLink output Interface
+ LL_OP_DATA => rx_d_i,
+ LL_OP_SOF_N => rx_sof_n_i,
+ LL_OP_EOF_N => rx_eof_n_i,
+ LL_OP_REM => rx_rem_i,
+ LL_OP_SRC_RDY_N => rx_src_rdy_n_i,
+ LL_IP_DST_RDY_N => tied_to_ground_i,
+
+ -- System Interface
+ USER_CLK => user_clk_i,
+ RESET => system_reset_i,
+ CHANNEL_UP => channel_up_r
+ );
+
+
+ frame_chk_axi_to_ll_ufc_i : aurora_dual_AXI_TO_LL_EXDES
+ generic map
+ (
+ DATA_WIDTH => 32,
+ STRB_WIDTH => 4,
+ REM_WIDTH => 2,
+ USE_UFC_REM => 1
+ )
+ port map
+ (
+ -- AXI4-S input signals
+ AXI4_S_IP_TX_TVALID => axi_ufc_rx_src_rdy_n_i,
+ AXI4_S_OP_TX_TREADY => OPEN,
+ AXI4_S_IP_TX_TDATA => axi_ufc_rx_data_i,
+ AXI4_S_IP_TX_TKEEP => axi_ufc_rx_rem_i,
+ AXI4_S_IP_TX_TLAST => axi_ufc_rx_eof_n_i,
+
+ -- LocalLink output Interface
+ LL_OP_DATA => ufc_rx_data_i,
+ LL_OP_SOF_N => ufc_rx_sof_n_i,
+ LL_OP_EOF_N => ufc_rx_eof_n_i,
+ LL_OP_REM => ufc_rx_rem_i,
+ LL_OP_SRC_RDY_N => ufc_rx_src_rdy_n_i,
+ LL_IP_DST_RDY_N => tied_to_ground_i,
+
+ -- System Interface
+ USER_CLK => user_clk_i,
+ RESET => system_reset_i,
+ CHANNEL_UP => channel_up_r
+ );
+
+ --_____________________________ TX AXI SHIM _______________________________
+ frame_gen_ll_to_axi_pdu_i : aurora_dual_LL_TO_AXI_EXDES
+ generic map
+ (
+ DATA_WIDTH => 32,
+ STRB_WIDTH => 4,
+ USE_4_NFC => 0,
+ REM_WIDTH => 2
+ )
+
+ port map
+ (
+ LL_IP_DATA => tx_d_i,
+ LL_IP_SOF_N => tx_sof_n_i,
+ LL_IP_EOF_N => tx_eof_n_i,
+ LL_IP_REM => tx_rem_i,
+ LL_IP_SRC_RDY_N => tx_src_rdy_n_i,
+ LL_OP_DST_RDY_N => tx_dst_rdy_n_i,
+
+ AXI4_S_OP_TVALID => tx_tvalid_i,
+ AXI4_S_OP_TDATA => tx_data_i,
+ AXI4_S_OP_TKEEP => tx_tkeep_i,
+ AXI4_S_OP_TLAST => tx_tlast_i,
+ AXI4_S_IP_TREADY => tx_tready_i
+
+ );
+
+ frame_gen_ll_to_axi_ufc_i : aurora_dual_LL_TO_AXI_EXDES
+ generic map
+ (
+ DATA_WIDTH => 3,
+ USE_UFC_REM => 1,
+ STRB_WIDTH => 4,
+ USE_4_NFC => 2,
+ REM_WIDTH => 2
+ )
+
+ port map
+ (
+ LL_IP_DATA => ufc_tx_ms_i,
+ LL_IP_SOF_N => tied_to_ground_i,
+ LL_IP_EOF_N => tied_to_ground_i,
+LL_IP_REM => "00",
+ LL_IP_SRC_RDY_N => ufc_tx_req_n_i,
+ LL_OP_DST_RDY_N => ufc_tx_ack_n_i,
+
+ -- AXI4-S output signals
+ AXI4_S_OP_TVALID => axi_ufc_tx_req_n_i,
+ AXI4_S_OP_TDATA => axi_ufc_tx_ms_i,
+ AXI4_S_OP_TKEEP => OPEN,
+ AXI4_S_OP_TLAST => OPEN,
+ AXI4_S_IP_TREADY => axi_ufc_tx_ack_n_i
+ );
+
+ frame_gen_ll_to_axi_nfc_i : aurora_dual_LL_TO_AXI_EXDES
+ generic map
+ (
+ DATA_WIDTH => 4,
+ STRB_WIDTH => 4,
+ USE_4_NFC => 1,
+ REM_WIDTH => 2
+ )
+
+ port map
+ (
+ LL_IP_DATA => nfc_nb_i,
+ LL_IP_SOF_N => tied_to_ground_i,
+ LL_IP_EOF_N => tied_to_ground_i,
+LL_IP_REM => "00",
+ LL_IP_SRC_RDY_N => nfc_req_n_i,
+ LL_OP_DST_RDY_N => nfc_ack_n_i,
+
+ -- AXI4-S output signals
+ AXI4_S_OP_TVALID => axi_nfc_req_n_i,
+ AXI4_S_OP_TDATA => axi_nfc_nb_i,
+ AXI4_S_OP_TKEEP => OPEN,
+ AXI4_S_OP_TLAST => OPEN,
+ AXI4_S_IP_TREADY => axi_nfc_ack_n_i
+
+ );
+
+ -- Module Instantiations --
+ aurora_module_i : aurora_dual_support
+ port map (
+ -- AXI TX Interface
+ s_axi_tx_tdata => tx_data_i,
+ s_axi_tx_tkeep => tx_tkeep_i,
+ s_axi_tx_tvalid => tx_tvalid_i,
+ s_axi_tx_tlast => tx_tlast_i,
+ s_axi_tx_tready => tx_tready_i,
+
+ -- AXI RX Interface
+ m_axi_rx_tdata => rx_data_i,
+ m_axi_rx_tkeep => rx_tkeep_i,
+ m_axi_rx_tvalid => rx_tvalid_i,
+ m_axi_rx_tlast => rx_tlast_i,
+
+ -- Native Flow Control TX Interface
+ s_axi_nfc_req => axi_nfc_req_n_i,
+ s_axi_nfc_nb => axi_nfc_nb_i,
+ s_axi_nfc_ack => axi_nfc_ack_n_i,
+
+ -- Native Flow Control RX Interface
+ m_axi_rx_snf => rx_snf_i,
+ m_axi_rx_fc_nb => rx_fc_nb_int,
+ -- User Flow Control TX Interface
+ s_axi_ufc_tx_req => axi_ufc_tx_req_n_i,
+ s_axi_ufc_tx_ms => axi_ufc_tx_ms_i,
+ s_axi_ufc_tx_ack => axi_ufc_tx_ack_n_i,
+ -- User Flow Control RX Inteface
+ m_axi_ufc_rx_tdata => axi_ufc_rx_data_i,
+ m_axi_ufc_rx_tkeep => axi_ufc_rx_rem_i,
+ m_axi_ufc_rx_tvalid => axi_ufc_rx_src_rdy_n_i,
+ m_axi_ufc_rx_tlast => axi_ufc_rx_eof_n_i,
+ -- GT Serial I/O
+ rxp => RXP,
+ rxn => RXN,
+ txp => TXP_Buffer,
+ txn => TXN_Buffer,
+
+ -- GT Reference Clock Interface
+ gt_refclk1_p => GTXQ0_P,
+ gt_refclk1_n => GTXQ0_N,
+
+
+ -- Error Detection Interface
+
+ hard_err => hard_err_i,
+ soft_err => soft_err_i,
+ frame_err => frame_err_i,
+
+ -- Status
+
+ channel_up => channel_up_i,
+ lane_up => lane_up_i,
+
+ -- System Interface
+
+ user_clk_out => user_clk_i,
+ sys_reset_out => system_reset_i,
+ reset => reset_i,
+ power_down => power_down_i,
+ loopback => loopback_vio_o,
+ gt_reset => gtreset_vio_o,
+ init_clk_p => '1',
+ init_clk_n => '0',
+ init_clk_out => open,
+ pll_not_locked_out => pll_not_locked_i,
+ tx_resetdone_out => tx_resetdone_i,
+ rx_resetdone_out => rx_resetdone_i,
+ link_reset_out => link_reset_i,
+
+
+drpclk_in => drpclk_i,
+drpaddr_in => daddr_in_i,
+drpen_in => den_in_i,
+drpdi_in => di_in_i,
+drprdy_out => drdy_out_unused_i,
+drpdo_out => drpdo_out_unused_i,
+drpwe_in => dwe_in_i,
+drpaddr_in_lane1 => daddr_in_lane1_i,
+drpen_in_lane1 => den_in_lane1_i,
+drpdi_in_lane1 => di_in_lane1_i,
+drprdy_out_lane1 => drdy_out_lane1_unused_i,
+drpdo_out_lane1 => drpdo_out_lane1_unused_i,
+drpwe_in_lane1 => dwe_in_lane1_i,
+ tx_lock => tx_lock_i,
+ sysclk_in => stable_clock,
+ gt0_refclk_in => gt0_refclk_in, --// Modified
+ gt0_qplllock_in => gt0_qplllock_in, --// Modified
+ gt0_qpllrefclklost_in => gt0_qpllrefclklost_in, --// Modified
+ gt0_qpllreset_out => gt0_qpllreset_out, --// Modified
+ GT_QPLLOUTCLK_IN => GT_QPLLOUTCLK_IN, --// Modified
+ GT_QPLLOUTREFCLK_IN => GT_QPLLOUTREFCLK_IN --// Modified
+ );
+
+end MAPPED;
--- /dev/null
+------------------------------------------------------------------------------/
+-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------/
+ library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_misc.all;
+ use IEEE.numeric_std.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
+
+-- synthesis translate_off
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- synthesis translate_on
+
+entity aurora_dual_support is
+port (
+ -- AXI TX Interface
+ s_axi_tx_tdata : in std_logic_vector(0 to 31);
+ s_axi_tx_tkeep : in std_logic_vector(0 to 3);
+ s_axi_tx_tvalid : in std_logic;
+ s_axi_tx_tready : out std_logic;
+ s_axi_tx_tlast : in std_logic;
+
+
+ -- AXI RX Interface
+ m_axi_rx_tdata : out std_logic_vector(0 to 31);
+ m_axi_rx_tkeep : out std_logic_vector(0 to 3);
+ m_axi_rx_tvalid : out std_logic;
+ m_axi_rx_tlast : out std_logic;
+
+ -- Native Flow Control TX Interface
+ s_axi_nfc_req : in std_logic;
+
+ s_axi_nfc_nb : in std_logic_vector(0 to 3);
+ s_axi_nfc_ack : out std_logic;
+
+ -- Native Flow Control RX Interface
+ m_axi_rx_snf : out std_logic;
+
+ m_axi_rx_fc_nb : out std_logic_vector(0 to 3);
+
+ -- User Flow Control TX Interface
+ s_axi_ufc_tx_req : in std_logic;
+
+ s_axi_ufc_tx_ms : in std_logic_vector(0 to 2);
+ s_axi_ufc_tx_ack : out std_logic;
+
+
+ -- User Flow Control RX Inteface
+
+ m_axi_ufc_rx_tdata : out std_logic_vector(0 to 31);
+ m_axi_ufc_rx_tkeep : out std_logic_vector(0 to 3);
+ m_axi_ufc_rx_tvalid : out std_logic;
+ m_axi_ufc_rx_tlast : out std_logic;
+
+
+
+ -- GT Serial I/O
+ rxp : in std_logic_vector(0 to 1);
+ rxn : in std_logic_vector(0 to 1);
+
+ txp : out std_logic_vector(0 to 1);
+ txn : out std_logic_vector(0 to 1);
+
+ -- GT Reference Clock Interface
+ gt_refclk1_p : in std_logic;
+ gt_refclk1_n : in std_logic;
+
+ -- Error Detection Interface
+
+ frame_err : out std_logic;
+ hard_err : out std_logic;
+ soft_err : out std_logic;
+ channel_up : out std_logic;
+ lane_up : out std_logic_vector(0 to 1);
+
+
+
+
+ -- System Interface
+ user_clk_out : out std_logic;
+ reset : in std_logic;
+ gt_reset : in std_logic;
+ sys_reset_out : out std_logic;
+
+ power_down : in std_logic;
+ loopback : in std_logic_vector(2 downto 0);
+ tx_lock : out std_logic;
+ init_clk_p : in std_logic;
+ init_clk_n : in std_logic;
+ init_clk_out : out std_logic;
+ tx_resetdone_out : out std_logic;
+ rx_resetdone_out : out std_logic;
+ link_reset_out : out std_logic;
+
+
+ --DRP Ports
+ drpclk_in : in std_logic;
+ drpaddr_in : in std_logic_vector(8 downto 0);
+ drpdi_in : in std_logic_vector(15 downto 0);
+ drpdo_out : out std_logic_vector(15 downto 0);
+ drpen_in : in std_logic;
+ drprdy_out : out std_logic;
+ drpwe_in : in std_logic;
+ drpaddr_in_lane1 : in std_logic_vector(8 downto 0);
+ drpdi_in_lane1 : in std_logic_vector(15 downto 0);
+ drpdo_out_lane1 : out std_logic_vector(15 downto 0);
+ drpen_in_lane1 : in std_logic;
+ drprdy_out_lane1 : out std_logic;
+ drpwe_in_lane1 : in std_logic;
+
+
+ pll_not_locked_out : out std_logic;
+ sysclk_in : in std_logic; --// Modified
+ gt0_refclk_in : in std_logic; --// Modified
+ gt0_qplllock_in : in std_logic; --// Modified
+ gt0_qpllrefclklost_in : in std_logic; --// Modified
+ gt0_qpllreset_out : out std_logic; --// Modified
+ GT_QPLLOUTCLK_IN : in std_logic; --// Modified
+ GT_QPLLOUTREFCLK_IN : in std_logic --// Modified
+ );
+
+end aurora_dual_support;
+
+
+architecture STRUCTURE of aurora_dual_support is
+ attribute core_generation_info : string;
+ attribute core_generation_info of STRUCTURE : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+ component aurora_dual
+ port (
+ -- TX Stream Interface
+ S_AXI_TX_TDATA : in std_logic_vector(0 to 31);
+ S_AXI_TX_TKEEP : in std_logic_vector(0 to 3);
+ S_AXI_TX_TVALID : in std_logic;
+ S_AXI_TX_TREADY : out std_logic;
+ S_AXI_TX_TLAST : in std_logic;
+
+ -- RX Stream Interface
+ M_AXI_RX_TDATA : out std_logic_vector(0 to 31);
+ M_AXI_RX_TKEEP : out std_logic_vector(0 to 3);
+ M_AXI_RX_TVALID : out std_logic;
+ M_AXI_RX_TLAST : out std_logic;
+ -- Native Flow Control TX Interface
+ S_AXI_NFC_TX_TVALID : in std_logic;
+ S_AXI_NFC_TX_TDATA : in std_logic_vector(0 to 3);
+ S_AXI_NFC_TX_TREADY : out std_logic;
+
+ -- Native Flow Control RX Interface
+ M_AXI_NFC_RX_TVALID : out std_logic;
+ M_AXI_NFC_RX_TDATA : out std_logic_vector(0 to 3);
+ -- User Flow Control TX Interface
+
+ S_AXI_UFC_TX_TVALID : in std_logic;
+ S_AXI_UFC_TX_TDATA : in std_logic_vector(0 to 2);
+ S_AXI_UFC_TX_TREADY : out std_logic;
+
+ -- User Flow Control RX Inteface
+ M_AXI_UFC_RX_TDATA : out std_logic_vector(0 to 31);
+ M_AXI_UFC_RX_TKEEP : out std_logic_vector(0 to 3);
+ M_AXI_UFC_RX_TVALID : out std_logic;
+ M_AXI_UFC_RX_TLAST : out std_logic;
+
+ -- GT Serial I/O
+ RXP : in std_logic_vector(0 to 1);
+ RXN : in std_logic_vector(0 to 1);
+ TXP : out std_logic_vector(0 to 1);
+ TXN : out std_logic_vector(0 to 1);
+
+ -- GT Reference Clock Interface
+ gt_refclk1 : in std_logic;
+
+ -- Error Detection Interface
+ HARD_ERR : out std_logic;
+ SOFT_ERR : out std_logic;
+
+ -- Status
+ CHANNEL_UP : out std_logic;
+ LANE_UP : out std_logic_vector(0 to 1);
+
+
+ FRAME_ERR : out std_logic;
+
+
+
+
+ -- System Interface
+
+ USER_CLK : in std_logic;
+ SYNC_CLK : in std_logic;
+ GT_RESET : in std_logic;
+ RESET : in std_logic;
+ sys_reset_out : out std_logic;
+ POWER_DOWN : in std_logic;
+ LOOPBACK : in std_logic_vector(2 downto 0);
+ TX_OUT_CLK : out std_logic;
+ INIT_CLK_IN : in std_logic;
+ PLL_NOT_LOCKED : in std_logic;
+ TX_RESETDONE_OUT : out std_logic;
+ RX_RESETDONE_OUT : out std_logic;
+ LINK_RESET_OUT : out std_logic;
+
+ drpclk_in : in std_logic;
+ drpaddr_in : in std_logic_vector(8 downto 0);
+ drpdi_in : in std_logic_vector(15 downto 0);
+ drpdo_out : out std_logic_vector(15 downto 0);
+ drpen_in : in std_logic;
+ drprdy_out : out std_logic;
+ drpwe_in : in std_logic;
+ drpaddr_in_lane1 : in std_logic_vector(8 downto 0);
+ drpdi_in_lane1 : in std_logic_vector(15 downto 0);
+ drpdo_out_lane1 : out std_logic_vector(15 downto 0);
+ drpen_in_lane1 : in std_logic;
+ drprdy_out_lane1 : out std_logic;
+ drpwe_in_lane1 : in std_logic;
+
+--------------------{
+--__________COMMON PORTS _______________________________{
+ ------------------------- Common Block - QPLL Ports ------------------------
+ gt0_qplllock_in : in std_logic;
+ gt0_qpllrefclklost_in : in std_logic;
+ gt0_qpllreset_out : out std_logic;
+ gt_qpllclk_quad1_in : in std_logic;
+ gt_qpllrefclk_quad1_in : in std_logic;
+--____________________________COMMON PORTS _______________________________}
+ TX_LOCK : out std_logic
+ );
+
+ end component;
+
+
+component aurora_dual_gt_common_wrapper
+port
+(
+--____________________________COMMON PORTS ,_______________________________{
+ gt_qpllclk_quad1_i : out std_logic;
+ gt_qpllrefclk_quad1_i : out std_logic;
+--____________________________COMMON PORTS ,_______________________________}
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ gt0_gtrefclk0_common_in : in std_logic;
+ ------------------------- Common Block - QPLL Ports ------------------------
+ gt0_qplllock_out : out std_logic;
+ gt0_qplllockdetclk_in : in std_logic;
+ gt0_qpllrefclklost_out : out std_logic;
+ gt0_qpllreset_in : in std_logic
+
+);
+end component;
+
+
+ component IBUFDS_GTE2
+ port (
+ O : out std_ulogic;
+ ODIV2 : out std_ulogic;
+ CEB : in std_ulogic;
+ I : in std_ulogic;
+ IB : in std_ulogic
+ );
+ end component;
+
+ component BUFG
+
+ port (
+
+ O : out std_ulogic;
+ I : in std_ulogic
+
+ );
+
+ end component;
+
+ component aurora_dual_CLOCK_MODULE
+ port (
+ INIT_CLK_P : in std_logic;
+ INIT_CLK_N : in std_logic;
+ INIT_CLK_O : out std_logic;
+ GT_CLK : in std_logic;
+ GT_CLK_LOCKED : in std_logic;
+ USER_CLK : out std_logic;
+ SYNC_CLK : out std_logic;
+ PLL_NOT_LOCKED : out std_logic
+ );
+ end component;
+
+ component aurora_dual_SUPPORT_RESET_LOGIC
+ port (
+ RESET : in std_logic;
+ USER_CLK : in std_logic;
+ INIT_CLK_IN : in std_logic;
+ GT_RESET_IN : in std_logic;
+ SYSTEM_RESET : out std_logic;
+ GT_RESET_OUT : out std_logic
+ );
+ end component;
+
+ component aurora_dual_cdc_sync is
+ generic (
+ C_CDC_TYPE : integer range 0 to 2 := 1 ;
+ -- 0 is pulse synch
+ -- 1 is level synch
+ -- 2 is ack based level sync
+ C_RESET_STATE : integer range 0 to 1 := 0 ;
+ -- 0 is reset not needed
+ -- 1 is reset needed
+ C_SINGLE_BIT : integer range 0 to 1 := 1 ;
+ -- 0 is bus input
+ -- 1 is single bit input
+ C_FLOP_INPUT : integer range 0 to 1 := 0 ;
+ C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
+ C_MTBF_STAGES : integer range 0 to 6 := 2
+ -- Vector Data witdth
+ );
+
+ port (
+ prmry_aclk : in std_logic ; --
+ prmry_resetn : in std_logic ; --
+ prmry_in : in std_logic ; --
+ prmry_vect_in : in std_logic_vector --
+ (C_VECTOR_WIDTH - 1 downto 0) ; --
+ prmry_ack : out std_logic ;
+ --
+ scndry_aclk : in std_logic ; --
+ scndry_resetn : in std_logic ; --
+ --
+ -- Primary to Secondary Clock Crossing --
+ scndry_out : out std_logic ; --
+ --
+ scndry_vect_out : out std_logic_vector --
+ (C_VECTOR_WIDTH - 1 downto 0) --
+
+ );
+ end component;
+
+------------ Wire declarations
+--------------------{
+ ------------------------- Common Block - QPLL Ports ------------------------
+signal gt0_qplllock_i : std_logic;
+signal gt0_qpllrefclklost_i : std_logic;
+signal gt0_qpllreset_i : std_logic;
+signal gt_qpllclk_quad1_i : std_logic;
+signal gt_qpllrefclk_quad1_i : std_logic;
+--------------------}
+signal gt_refclk1_i : std_logic;
+
+signal tx_out_clk_i : std_logic;
+signal user_clk_i : std_logic;
+signal sync_clk_i : std_logic;
+signal pll_not_locked_i : std_logic;
+signal tx_lock_i : std_logic;
+
+signal init_clk_i : std_logic;
+signal tx_resetdone_i : std_logic;
+signal rx_resetdone_i : std_logic;
+signal link_reset_i : std_logic;
+signal system_reset_i : std_logic;
+signal gt_reset_i : std_logic;
+signal drpclk_i : std_logic;
+signal reset_sync_user_clk : std_logic;
+signal gt_reset_sync_init_clk : std_logic;
+begin
+
+ --*********************************Main Body of Code**********************************
+
+ --// Modified
+ -- IBUFDS_GTE2_CLK1 : IBUFDS_GTE2
+ -- port map (
+ -- I => gt_refclk1_p,
+ -- IB => gt_refclk1_n,
+ -- CEB => '0',
+ -- O => gt_refclk1_i,
+ -- ODIV2 => OPEN);
+
+
+ drpclk_i <= drpclk_in;
+
+ -- Instantiate a clock module for clock division
+
+ clock_module_i : aurora_dual_CLOCK_MODULE
+ port map (
+ INIT_CLK_P => init_clk_p,
+ INIT_CLK_N => init_clk_n,
+ INIT_CLK_O => open, --// Modified init_clk_i,
+ GT_CLK => tx_out_clk_i,
+ GT_CLK_LOCKED => tx_lock_i,
+ USER_CLK => user_clk_i,
+ SYNC_CLK => sync_clk_i,
+ PLL_NOT_LOCKED => pll_not_locked_i
+ );
+
+ -- outputs
+ init_clk_out <= init_clk_i;
+ user_clk_out <= user_clk_i;
+ pll_not_locked_out <= pll_not_locked_i;
+ tx_lock <= tx_lock_i;
+ tx_resetdone_out <= tx_resetdone_i;
+ rx_resetdone_out <= rx_resetdone_i;
+ link_reset_out <= link_reset_i;
+
+
+ reset_sync_user_clk <= reset;
+ gt_reset_sync_init_clk <= gt_reset;
+
+ support_reset_logic_i : aurora_dual_SUPPORT_RESET_LOGIC
+ port map (
+ RESET => reset_sync_user_clk,
+ USER_CLK => user_clk_i,
+ INIT_CLK_IN => init_clk_i,
+ GT_RESET_IN => gt_reset_sync_init_clk,
+ SYSTEM_RESET => system_reset_i,
+ GT_RESET_OUT => gt_reset_i
+ );
+
+ --// Modified
+-- -------- instance of _gt_common_wrapper ---{
+-- gt_common_support : aurora_dual_gt_common_wrapper
+
+-- port map
+-- (
+-- --____________________________COMMON PORTS ,_______________________________{
+ -- gt_qpllclk_quad1_i => gt_qpllclk_quad1_i ,
+ -- gt_qpllrefclk_quad1_i => gt_qpllrefclk_quad1_i ,
+ -- ---------------------- Common Block - Ref Clock Ports ---------------------
+ -- gt0_gtrefclk0_common_in => gt_refclk1_i,
+
+ -- ------------------------- Common Block - QPLL Ports ------------------------
+ -- gt0_qplllock_out => gt0_qplllock_i,
+ -- gt0_qplllockdetclk_in => init_clk_i,
+ -- gt0_qpllrefclklost_out => gt0_qpllrefclklost_i ,
+ -- gt0_qpllreset_in => gt0_qpllreset_i
+-- --____________________________COMMON PORTS ,_______________________________}
+-- );
+init_clk_i <= sysclk_in; --// Modified
+gt_qpllclk_quad1_i <= GT_QPLLOUTCLK_IN; --// Modified
+gt_qpllrefclk_quad1_i <= GT_QPLLOUTREFCLK_IN; --// Modified
+gt_refclk1_i <= gt0_refclk_in; --// Modified
+gt0_qplllock_i <= gt0_qplllock_in; --// Modified
+gt0_qpllrefclklost_i <= gt0_qpllrefclklost_in; --// Modified
+gt0_qpllreset_out <= gt0_qpllreset_i; --// Modified
+-------- instance of _gt_common_wrapper ---}
+
+ aurora_dual_i : aurora_dual
+ port map (
+ -- AXI TX Interface
+ s_axi_tx_tdata => s_axi_tx_tdata,
+ s_axi_tx_tkeep => s_axi_tx_tkeep,
+ s_axi_tx_tvalid => s_axi_tx_tvalid,
+ s_axi_tx_tlast => s_axi_tx_tlast,
+ s_axi_tx_tready => s_axi_tx_tready,
+
+ -- AXI RX Interface
+ m_axi_rx_tdata => m_axi_rx_tdata,
+ m_axi_rx_tkeep => m_axi_rx_tkeep,
+ m_axi_rx_tvalid => m_axi_rx_tvalid,
+ m_axi_rx_tlast => m_axi_rx_tlast,
+ -- Native Flow Control TX Interface
+ s_axi_nfc_tx_tvalid => s_axi_nfc_req,
+ s_axi_nfc_tx_tdata => s_axi_nfc_nb,
+ s_axi_nfc_tx_tready => s_axi_nfc_ack,
+
+ -- Native Flow Control RX Interface
+ m_axi_nfc_rx_tvalid => m_axi_rx_snf,
+ m_axi_nfc_rx_tdata => m_axi_rx_fc_nb,
+
+
+ -- User Flow Control TX Interface
+ s_axi_ufc_tx_tvalid => s_axi_ufc_tx_req,
+ s_axi_ufc_tx_tdata => s_axi_ufc_tx_ms,
+ s_axi_ufc_tx_tready => s_axi_ufc_tx_ack,
+
+ -- User Flow Control RX Inteface
+ m_axi_ufc_rx_tdata => m_axi_ufc_rx_tdata,
+ m_axi_ufc_rx_tkeep => m_axi_ufc_rx_tkeep,
+ m_axi_ufc_rx_tvalid => m_axi_ufc_rx_tvalid,
+ m_axi_ufc_rx_tlast => m_axi_ufc_rx_tlast,
+
+ -- GT Serial I/O
+ rxp => rxp,
+ rxn => rxn,
+ txp => txp,
+ txn => txn,
+
+ -- GT Reference Clock Interface
+ gt_refclk1 => gt_refclk1_i,
+ -- Error Detection Interface
+ frame_err => frame_err,
+
+ -- Error Detection Interface
+ hard_err => hard_err,
+ soft_err => soft_err,
+
+ -- Status
+ channel_up => channel_up,
+ lane_up => lane_up,
+
+
+
+
+ -- System Interface
+ user_clk => user_clk_i,
+ sync_clk => sync_clk_i,
+ reset => system_reset_i,
+ sys_reset_out => sys_reset_out,
+ power_down => power_down,
+ loopback => loopback,
+ gt_reset => gt_reset_i,
+ tx_lock => tx_lock_i,
+ init_clk_in => init_clk_i,
+ pll_not_locked => pll_not_locked_i,
+ tx_resetdone_out => tx_resetdone_i,
+ rx_resetdone_out => rx_resetdone_i,
+ link_reset_out => link_reset_i,
+
+
+ drpclk_in => drpclk_i,
+ drpaddr_in => drpaddr_in,
+ drpen_in => drpen_in,
+ drpdi_in => drpdi_in,
+ drprdy_out => drprdy_out,
+ drpdo_out => drpdo_out,
+ drpwe_in => drpwe_in,
+ drpaddr_in_lane1 => drpaddr_in_lane1,
+ drpen_in_lane1 => drpen_in_lane1,
+ drpdi_in_lane1 => drpdi_in_lane1,
+ drprdy_out_lane1 => drprdy_out_lane1,
+ drpdo_out_lane1 => drpdo_out_lane1,
+ drpwe_in_lane1 => drpwe_in_lane1,
+--------------------{
+--__________COMMON PORTS _______________________________{
+ ------------------------- Common Block - QPLL Ports ------------------------
+ gt0_qplllock_in => gt0_qplllock_i,
+ gt0_qpllrefclklost_in => gt0_qpllrefclklost_i,
+ gt0_qpllreset_out => gt0_qpllreset_i,
+ gt_qpllclk_quad1_in => gt_qpllclk_quad1_i ,
+ gt_qpllrefclk_quad1_in => gt_qpllrefclk_quad1_i ,
+--____________________________COMMON PORTS ,_______________________________}
+--------------------}
+ tx_out_clk => tx_out_clk_i
+
+ );
+
+ end STRUCTURE;
--- /dev/null
+
+-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+---------------------------------------------------------------------------------------------
+-- AURORA RESET LOGIC
+--
+--
+-- Description: RESET logic using Debouncer
+--
+--
+
+library IEEE;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_misc.all;
+use ieee.std_logic_1164.all;
+
+-- synthesis translate_off
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- synthesis translate_on
+
+entity aurora_dual_SUPPORT_RESET_LOGIC is
+ port (
+
+ RESET : in std_logic;
+ USER_CLK : in std_logic;
+ INIT_CLK_IN : in std_logic;
+ GT_RESET_IN : in std_logic;
+ SYSTEM_RESET : out std_logic;
+ GT_RESET_OUT : out std_logic
+ );
+
+end aurora_dual_SUPPORT_RESET_LOGIC;
+
+architecture MAPPED of aurora_dual_SUPPORT_RESET_LOGIC is
+ attribute DowngradeIPIdentifiedWarnings: string;
+ attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
+ attribute core_generation_info : string;
+attribute core_generation_info of MAPPED : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+-- Parameter Declarations --
+
+ constant DLY : time := 1 ns;
+
+-- Internal Register Declarations --
+
+ signal reset_debounce_r : std_logic_vector(0 to 3);
+ signal debounce_gt_rst_r : std_logic_vector(0 to 3) := "0000";
+ signal reset_debounce_r2 : std_logic;
+ signal gt_rst_r : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal gt_rst_sync : std_logic;
+
+ attribute ASYNC_REG : string;
+ attribute SHIFT_EXTRACT : string;
+
+ attribute ASYNC_REG of debounce_gt_rst_r: signal is "true";
+ attribute SHIFT_EXTRACT of debounce_gt_rst_r: signal is "no";
+
+-- Component Declarations --
+
+ component aurora_dual_cdc_sync_exdes is
+ generic (
+ C_CDC_TYPE : integer range 0 to 2 := 1 ;
+ -- 0 is pulse synch
+ -- 1 is level synch
+ -- 2 is ack based level sync
+ C_RESET_STATE : integer range 0 to 1 := 0 ;
+ -- 0 is reset not needed
+ -- 1 is reset needed
+ C_SINGLE_BIT : integer range 0 to 1 := 1 ;
+ -- 0 is bus input
+ -- 1 is single bit input
+ C_FLOP_INPUT : integer range 0 to 1 := 0 ;
+ C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
+ C_MTBF_STAGES : integer range 0 to 6 := 2
+ -- Vector Data witdth
+ );
+
+ port (
+ prmry_aclk : in std_logic ; --
+ prmry_resetn : in std_logic ; --
+ prmry_in : in std_logic ; --
+ prmry_vect_in : in std_logic_vector --
+ (C_VECTOR_WIDTH - 1 downto 0) ; --
+ prmry_ack : out std_logic ;
+ --
+ scndry_aclk : in std_logic ; --
+ scndry_resetn : in std_logic ; --
+ --
+ -- Primary to Secondary Clock Crossing --
+ scndry_out : out std_logic ; --
+ --
+ scndry_vect_out : out std_logic_vector --
+ (C_VECTOR_WIDTH - 1 downto 0) --
+
+ );
+
+ end component;
+
+begin
+
+ -- Tie off top level constants.
+ tied_to_ground_i <= '0';
+
+ -- ___________________________Debouncing circuit for GT_RESET_IN________________________
+-- Reset sync from INIT_CLK to USER_CLK
+
+ gt_rst_r_cdc_sync : aurora_dual_cdc_sync_exdes
+ generic map
+ (
+ c_cdc_type => 1 ,
+ c_flop_input => 1 ,
+ c_reset_state => 0 ,
+ c_single_bit => 1 ,
+ c_vector_width => 2 ,
+ c_mtbf_stages => 4
+ )
+ port map
+ (
+ prmry_aclk => INIT_CLK_IN ,
+ prmry_resetn => '1' ,
+ prmry_in => gt_rst_r ,
+ prmry_vect_in => "00" ,
+ scndry_aclk => USER_CLK ,
+ scndry_resetn => '1' ,
+ prmry_ack => open ,
+ scndry_out => gt_rst_sync ,
+ scndry_vect_out => open
+ );
+
+
+ -- Debounce the GT_RESET_IN signal using the INIT_CLK
+ process(INIT_CLK_IN)
+ begin
+ if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
+ debounce_gt_rst_r <= GT_RESET_IN & debounce_gt_rst_r(0 to 2);
+ gt_rst_r <= debounce_gt_rst_r(0) and
+ debounce_gt_rst_r(1) and
+ debounce_gt_rst_r(2) and
+ debounce_gt_rst_r(3);
+ end if;
+ end process;
+
+
+ GT_RESET_OUT <= gt_rst_r;
+
+ -- _______________________Debounce the Reset signal________________________ --
+
+ -- Simple Debouncer for Reset button. The debouncer has an
+ -- asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
+ -- that unknown values are not driven into the reset line
+ process (USER_CLK, gt_rst_sync)
+ begin
+ if (gt_rst_sync = '1') then
+ reset_debounce_r <= "1111";
+ elsif (USER_CLK 'event and USER_CLK = '1') then
+ reset_debounce_r <= RESET & reset_debounce_r(0 to 2);
+ end if;
+ end process;
+
+ process(USER_CLK)
+ begin
+ if(USER_CLK'event and USER_CLK='1') then
+ reset_debounce_r2 <= (reset_debounce_r(0) and
+ reset_debounce_r(1) and
+ reset_debounce_r(2) and
+ reset_debounce_r(3));
+ end if;
+ end process;
+
+ SYSTEM_RESET <= reset_debounce_r2;
+
+end MAPPED;
--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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+</spirit:design>
--- /dev/null
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+</spirit:design>
--- /dev/null
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+</spirit:design>
--- /dev/null
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+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
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+</spirit:design>
--- /dev/null
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+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___100.000______0.000______50.0______130.958_____98.575</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2___200.000______0.000______50.0______114.829_____98.575</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clock100to200</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">130.958</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">98.575</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">114.829</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">98.575</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clock100to200</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_LOCKED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_RESET" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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+ <spirit:componentInstances>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1____40.000______0.000______50.0______174.629____114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2____80.000______0.000______50.0______151.652____114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3___100.000______0.000______50.0______144.719____114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">CLK_OUT4___200.000______0.000______50.0______126.455____114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">CLK_OUT5____66.667______0.000______50.0______157.646____114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">CLK_OUT6___160.000______0.000______50.0______131.841____114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clockmodule100to80M</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">174.629</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.00</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">151.652</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">144.719</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">126.455</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">157.646</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">65</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">131.841</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">114.212</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
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--- /dev/null
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+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>clockmodule40Mto80M</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">250.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">40.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary______________40____________0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">24.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">25.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">24.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1____40.000______0.000______50.0______247.096____196.976</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2____80.000______0.000______50.0______200.412____196.976</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">40</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clockmodule40Mto80M</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">250.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">247.096</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">196.976</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">200.412</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">196.976</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clockmodule40Mto80M</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">24.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">25.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">24.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">40</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_RESET" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>gtxKintex7FEE80_clockmodule</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.1"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">gtxKintex7FEE80_clockmodule</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">125.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">12.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">12.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">136.213</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">100.585</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">119.661</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">100.585</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">gtxKintex7FEE80_clockmodule</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary______________80____________0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___100.000______0.000______50.0______136.213____100.585</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2___200.000______0.000______50.0______119.661____100.585</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">12.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/ Core: sem
+-- \ \ Entity: sem_sem_cfg
+-- / / Filename: sem_sem_cfg.vhd
+-- /___/ /\ Purpose: Wrapper file for configuration logic.
+-- \ \ / \
+-- \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity is a wrapper to encapsulate the FRAME_ECC and ICAP primitives.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- icap_clk input The controller clock, used to clock
+-- the configuration logic as well.
+--
+-- icap_o[31:0] output ICAP data output. Synchronous to
+-- icap_clk.
+--
+-- icap_csib input ICAP chip select, active low. Used
+-- to enable the ICAP for read or write.
+-- Synchronous to icap_clk.
+--
+-- icap_rdwrb input ICAP write select, active low. Used
+-- to select between read or write.
+-- Synchronous to icap_clk.
+--
+-- icap_i[31:0] input ICAP data input. Synchronous to
+-- icap_clk.
+--
+-- fecc_crcerr output FRAME_ECC status indicating a device
+-- CRC check at end of readback cycle
+-- has failed. Synchronous to icap_clk.
+--
+-- fecc_eccerr output FRAME_ECC status indicating a frame
+-- ECC check at end of frame readback
+-- has failed. Synchronous to icap_clk.
+--
+-- fecc_eccerrsingle output FRAME_ECC status indicating syndrome
+-- appears to be for a single bit error.
+-- Synchronous to icap_clk.
+--
+-- fecc_syndromevalid output FRAME_ECC status indicating syndrome
+-- is valid in this cycle. Synchronous
+-- to icap_clk.
+--
+-- fecc_syndrome[12:0] output FRAME_ECC syndrome. Synchronous to
+-- icap_clk.
+--
+-- fecc_far[25:0] output FRAME_ECC status showing FAR or EFAR.
+-- Synchronous to icap_clk.
+--
+-- fecc_synbit[4:0] output FRAME_ECC status indicating location
+-- of error in a word. Synchronous to
+-- icap_clk.
+--
+-- fecc_synword[6:0] output FRAME_ECC status indicating location
+-- of error word in a frame. Synchronous
+-- to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- TCQ int Sets the clock-to-out for behavioral
+-- descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_cfg
+-- |
+-- +- ICAPE2 (unisim)
+-- |
+-- \- FRAME_ECCE2 (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_cfg is
+port (
+ icap_clk : in std_logic;
+ icap_o : out std_logic_vector(31 downto 0);
+ icap_csib : in std_logic;
+ icap_rdwrb : in std_logic;
+ icap_i : in std_logic_vector(31 downto 0);
+ fecc_crcerr : out std_logic;
+ fecc_eccerr : out std_logic;
+ fecc_eccerrsingle : out std_logic;
+ fecc_syndromevalid : out std_logic;
+ fecc_syndrome : out std_logic_vector(12 downto 0);
+ fecc_far : out std_logic_vector(25 downto 0);
+ fecc_synbit : out std_logic_vector(4 downto 0);
+ fecc_synword : out std_logic_vector(6 downto 0)
+ );
+end entity sem_sem_cfg;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_cfg is
+
+ ---------------------------------------------------------------------------
+ -- Define local constants.
+ ---------------------------------------------------------------------------
+
+ constant TCQ : time := 1 ps;
+
+ ---------------------------------------------------------------------------
+ -- Declare non-library components.
+ ---------------------------------------------------------------------------
+
+ -- None
+
+ ---------------------------------------------------------------------------
+ -- Declare signals.
+ ---------------------------------------------------------------------------
+
+ -- None
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+ begin
+
+ ---------------------------------------------------------------------------
+ -- Instantiate the FRAME_ECC primitive.
+ ---------------------------------------------------------------------------
+
+ example_frame_ecc : FRAME_ECCE2
+ generic map (
+ FRAME_RBT_IN_FILENAME => "NONE",
+ FARSRC => "EFAR"
+ )
+ port map (
+ CRCERROR => fecc_crcerr,
+ ECCERROR => fecc_eccerr,
+ ECCERRORSINGLE => fecc_eccerrsingle,
+ FAR => fecc_far,
+ SYNBIT => fecc_synbit,
+ SYNDROME => fecc_syndrome,
+ SYNDROMEVALID => fecc_syndromevalid,
+ SYNWORD => fecc_synword
+ );
+
+ ---------------------------------------------------------------------------
+ -- Instantiate the ICAP primitive.
+ ---------------------------------------------------------------------------
+
+ example_icap : ICAPE2
+ generic map (
+ SIM_CFG_FILE_NAME => "NONE",
+ DEVICE_ID => X"FFFFFFFF",
+ ICAP_WIDTH => "X32"
+ )
+ port map (
+ O => icap_o,
+ CLK => icap_clk,
+ CSIB => icap_csib,
+ I => icap_i,
+ RDWRB => icap_rdwrb
+ );
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
--- /dev/null
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/ Core: sem
+-- \ \ Entity: sem_sem_example
+-- / / Filename: sem_sem_example.vhd
+-- /___/ /\ Purpose: System level design example.
+-- \ \ / \
+-- \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity is the system level design example, the top level of what is
+-- intended for physical implementation. This entity is essentially an HDL
+-- netlist of sub-entities used to construct the solution. The system level
+-- design example is customized by the Vivado IP Catalog.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- clk input System clock; the entire system is
+-- synchronized to this signal, which
+-- is distributed on a global clock
+-- buffer and referred to as icap_clk.
+--
+-- status_heartbeat output Heartbeat signal for external watch
+-- dog timer implementation; pulses
+-- when readback runs. Synchronous to
+-- icap_clk.
+--
+-- status_initialization output Indicates initialization is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_observation output Indicates observation is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_correction output Indicates correction is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_classification output Indicates classification is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_injection output Indicates injection is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_essential output Indicates essential error condition.
+-- Qualified by de-assertion of the
+-- status_classification signal, and
+-- is synchronous to icap_clk.
+--
+-- status_uncorrectable output Indicates uncorrectable error
+-- condition. Qualified by de-assertion
+-- of the status_correction signal, and
+-- is synchronous to icap_clk.
+--
+-- monitor_tx output Serial status output. Synchronous
+-- to icap_clk, but received externally
+-- by another device as an asynchronous
+-- signal, perceived as lower bitrate.
+-- Uses 8N1 protocol.
+--
+-- monitor_rx input Serial command input. Asynchronous
+-- signal provided by another device at
+-- a lower bitrate, synchronized to the
+-- icap_clk and oversampled. Uses 8N1
+-- protocol.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- TCQ int Sets the clock-to-out for behavioral
+-- descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_example
+-- |
+-- +- sem (sem_controller)
+-- |
+-- +- sem_sem_cfg
+-- |
+-- +- sem_sem_mon
+-- |
+-- +- sem_sem_hid
+-- |
+-- +- IBUF (unisim)
+-- |
+-- \- BUFGCE (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_example is
+port (
+ clk : in std_logic;
+ status_heartbeat : out std_logic;
+ status_initialization : out std_logic;
+ status_observation : out std_logic;
+ status_correction : out std_logic;
+ status_classification : out std_logic;
+ status_injection : out std_logic;
+ status_essential : out std_logic;
+ status_uncorrectable : out std_logic;
+ monitor_tx : out std_logic;
+ monitor_rx : in std_logic;
+ disable_all : out std_logic;
+ ADC_selREGS : out std_logic_vector(2 downto 0);
+ disable_tests : out std_logic_vector(3 downto 0);
+ insert_data : in std_logic_vector(7 downto 0);
+ insert_data_available : in std_logic;
+ insert_data_read : out std_logic
+ );
+end entity sem_sem_example;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_example is
+
+ ---------------------------------------------------------------------------
+ -- Define local constants.
+ ---------------------------------------------------------------------------
+
+ constant TCQ : time := 1 ps;
+
+ ---------------------------------------------------------------------------
+ -- Declare non-library components.
+ ---------------------------------------------------------------------------
+
+ component sem
+ port (
+ status_heartbeat : out std_logic;
+ status_initialization : out std_logic;
+ status_observation : out std_logic;
+ status_correction : out std_logic;
+ status_classification : out std_logic;
+ status_injection : out std_logic;
+ status_essential : out std_logic;
+ status_uncorrectable : out std_logic;
+ monitor_txdata : out std_logic_vector(7 downto 0);
+ monitor_txwrite : out std_logic;
+ monitor_txfull : in std_logic;
+ monitor_rxdata : in std_logic_vector(7 downto 0);
+ monitor_rxread : out std_logic;
+ monitor_rxempty : in std_logic;
+ inject_strobe : in std_logic;
+ inject_address : in std_logic_vector(39 downto 0);
+ fecc_crcerr : in std_logic;
+ fecc_eccerr : in std_logic;
+ fecc_eccerrsingle : in std_logic;
+ fecc_syndromevalid : in std_logic;
+ fecc_syndrome : in std_logic_vector(12 downto 0);
+ fecc_far : in std_logic_vector(25 downto 0);
+ fecc_synbit : in std_logic_vector(4 downto 0);
+ fecc_synword : in std_logic_vector(6 downto 0);
+ icap_o : in std_logic_vector(31 downto 0);
+ icap_i : out std_logic_vector(31 downto 0);
+ icap_csib : out std_logic;
+ icap_rdwrb : out std_logic;
+ icap_clk : in std_logic;
+ icap_request : out std_logic;
+ icap_grant : in std_logic
+ );
+ end component;
+
+ component sem_sem_cfg
+ port (
+ fecc_crcerr : out std_logic;
+ fecc_eccerr : out std_logic;
+ fecc_eccerrsingle : out std_logic;
+ fecc_syndromevalid : out std_logic;
+ fecc_syndrome : out std_logic_vector(12 downto 0);
+ fecc_far : out std_logic_vector(25 downto 0);
+ fecc_synbit : out std_logic_vector(4 downto 0);
+ fecc_synword : out std_logic_vector(6 downto 0);
+ icap_o : out std_logic_vector(31 downto 0);
+ icap_i : in std_logic_vector(31 downto 0);
+ icap_clk : in std_logic;
+ icap_csib : in std_logic;
+ icap_rdwrb : in std_logic
+ );
+ end component;
+
+ component sem_sem_mon
+ port (
+ icap_clk : in std_logic;
+ monitor_tx : out std_logic;
+ monitor_rx : in std_logic;
+ monitor_txdata : in std_logic_vector(7 downto 0);
+ monitor_txwrite : in std_logic;
+ monitor_txfull : out std_logic;
+ monitor_rxdata : out std_logic_vector(7 downto 0);
+ monitor_rxread : in std_logic;
+ monitor_rxempty : out std_logic
+ );
+ end component;
+
+ component sem_sem_hid
+ port (
+ icap_clk : in std_logic;
+ status_heartbeat : in std_logic;
+ status_initialization : in std_logic;
+ status_observation : in std_logic;
+ status_correction : in std_logic;
+ status_classification : in std_logic;
+ status_injection : in std_logic;
+ status_essential : in std_logic;
+ status_uncorrectable : in std_logic;
+ inject_strobe : out std_logic;
+ inject_address : out std_logic_vector(39 downto 0);
+ disable_all : out std_logic;
+ ADC_selREGS : out std_logic_vector(2 downto 0);
+ disable_tests : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ ---------------------------------------------------------------------------
+ -- Declare signals.
+ ---------------------------------------------------------------------------
+
+ signal status_heartbeat_internal : std_logic;
+ signal status_initialization_internal : std_logic;
+ signal status_observation_internal : std_logic;
+ signal status_correction_internal : std_logic;
+ signal status_classification_internal : std_logic;
+ signal status_injection_internal : std_logic;
+ signal status_essential_internal : std_logic;
+ signal status_uncorrectable_internal : std_logic;
+
+ signal monitor_txdata : std_logic_vector(7 downto 0);
+ signal monitor_txwrite : std_logic;
+ signal monitor_txfull : std_logic;
+ signal monitor_rxdata : std_logic_vector(7 downto 0);
+ signal monitor_rxread : std_logic;
+ signal monitor_rxempty : std_logic;
+ signal inject_strobe : std_logic;
+ signal inject_address : std_logic_vector(39 downto 0);
+ signal fecc_crcerr : std_logic;
+ signal fecc_eccerr : std_logic;
+ signal fecc_eccerrsingle : std_logic;
+ signal fecc_syndromevalid : std_logic;
+ signal fecc_syndrome : std_logic_vector(12 downto 0);
+ signal fecc_far : std_logic_vector(25 downto 0);
+ signal fecc_synbit : std_logic_vector(4 downto 0);
+ signal fecc_synword : std_logic_vector(6 downto 0);
+ signal icap_o : std_logic_vector(31 downto 0);
+ signal icap_i : std_logic_vector(31 downto 0);
+ signal icap_csib : std_logic;
+ signal icap_rdwrb : std_logic;
+ signal icap_unused : std_logic;
+ signal icap_grant : std_logic;
+ signal icap_clk : std_logic;
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+ constant V_ENABLETIME : integer := 21; -- FOR 115200 259; FOR 9600
+ signal monitor_rxdata_S : std_logic_vector(7 downto 0);
+ signal monitor_rxread_S : std_logic;
+ signal monitor_rxempty_S : std_logic;
+ signal insert_rxdata_S : std_logic_vector(7 downto 0);
+ signal insert_rxempty_S : std_logic := '0';
+ signal insertingcmd_S : std_logic := '0';
+ signal insert_S : std_logic := '0';
+
+ signal monitor_tx_S : std_logic;
+ signal monitor_txdata_S : std_logic_vector(7 downto 0);
+ signal monitor_txwrite_S : std_logic;
+ signal monitor_txfull_S : std_logic := '0';
+ signal insert_data_read_S : std_logic := '0';
+ signal insert_txdata_S : std_logic_vector(7 downto 0);
+ signal insert_txwrite_S : std_logic := '0';
+ signal insertingstat_S : std_logic := '0';
+ signal insert_writecr_S : std_logic := '0';
+
+
+
+attribute mark_debug : string;
+-- attribute mark_debug of monitor_rx : signal is "true";
+-- attribute mark_debug of monitor_rxdata_S : signal is "true";
+-- attribute mark_debug of monitor_rxread_S : signal is "true";
+-- attribute mark_debug of monitor_rxempty_S : signal is "true";
+
+-- attribute mark_debug of insertingcmd_S : signal is "true";
+-- attribute mark_debug of insert_rxempty_S : signal is "true";
+-- attribute mark_debug of insert_S : signal is "true";
+-- attribute mark_debug of monitor_txdata_S : signal is "true";
+-- attribute mark_debug of monitor_txwrite_S : signal is "true";
+-- attribute mark_debug of monitor_txfull_S : signal is "true";
+-- attribute mark_debug of insert_data_read_S : signal is "true";
+-- attribute mark_debug of insert_txdata_S : signal is "true";
+-- attribute mark_debug of insert_txwrite_S : signal is "true";
+-- attribute mark_debug of insertingstat_S : signal is "true";
+-- attribute mark_debug of insert_writecr_S : signal is "true";
+-- attribute mark_debug of monitor_tx_S : signal is "true";
+
+ begin
+
+ ---------------------------------------------------------------------------
+ -- This design (the example, including the controller itself) is fully
+ -- synchronous; the global clock buffer is instantiated here to drive
+ -- the icap_clk signal.
+ ---------------------------------------------------------------------------
+
+ example_bufg : BUFGCE
+ port map (
+ I => clk,
+ O => icap_clk,
+ CE => '1'
+ );
+
+ ---------------------------------------------------------------------------
+ -- The controller sub-entity is the kernel of the soft error mitigation
+ -- solution. The port list is dynamic based on the IP core options.
+ ---------------------------------------------------------------------------
+
+ example_controller : sem
+ port map (
+ status_heartbeat => status_heartbeat_internal,
+ status_initialization => status_initialization_internal,
+ status_observation => status_observation_internal,
+ status_correction => status_correction_internal,
+ status_classification => status_classification_internal,
+ status_injection => status_injection_internal,
+ status_essential => status_essential_internal,
+ status_uncorrectable => status_uncorrectable_internal,
+ monitor_txdata => monitor_txdata,
+ monitor_txwrite => monitor_txwrite,
+ monitor_txfull => monitor_txfull,
+ monitor_rxdata => monitor_rxdata,
+ monitor_rxread => monitor_rxread,
+ monitor_rxempty => monitor_rxempty,
+ inject_strobe => inject_strobe,
+ inject_address => inject_address,
+ fecc_crcerr => fecc_crcerr,
+ fecc_eccerr => fecc_eccerr,
+ fecc_eccerrsingle => fecc_eccerrsingle,
+ fecc_syndromevalid => fecc_syndromevalid,
+ fecc_syndrome => fecc_syndrome,
+ fecc_far => fecc_far,
+ fecc_synbit => fecc_synbit,
+ fecc_synword => fecc_synword,
+ icap_o => icap_o,
+ icap_i => icap_i,
+ icap_csib => icap_csib,
+ icap_rdwrb => icap_rdwrb,
+ icap_clk => icap_clk,
+ icap_request => icap_unused,
+ icap_grant => icap_grant
+ );
+
+ icap_grant <= '1';
+ status_heartbeat <= status_heartbeat_internal;
+ status_initialization <= status_initialization_internal;
+ status_observation <= status_observation_internal;
+ status_correction <= status_correction_internal;
+ status_classification <= status_classification_internal;
+ status_injection <= status_injection_internal;
+ status_essential <= status_essential_internal;
+ status_uncorrectable <= status_uncorrectable_internal;
+
+ ---------------------------------------------------------------------------
+ -- The cfg sub-entity contains the device specific primitives to access
+ -- the internal configuration port and the frame crc/ecc status signals.
+ ---------------------------------------------------------------------------
+
+ example_cfg : sem_sem_cfg
+ port map (
+ fecc_crcerr => fecc_crcerr,
+ fecc_eccerr => fecc_eccerr,
+ fecc_eccerrsingle => fecc_eccerrsingle,
+ fecc_syndromevalid => fecc_syndromevalid,
+ fecc_syndrome => fecc_syndrome,
+ fecc_far => fecc_far,
+ fecc_synbit => fecc_synbit,
+ fecc_synword => fecc_synword,
+ icap_o => icap_o,
+ icap_i => icap_i,
+ icap_csib => icap_csib,
+ icap_rdwrb => icap_rdwrb,
+ icap_clk => icap_clk
+ );
+
+ ---------------------------------------------------------------------------
+ -- The mon sub-entity contains a UART for communication purposes.
+ ---------------------------------------------------------------------------
+
+ example_mon : sem_sem_mon
+ port map (
+ icap_clk => icap_clk,
+ monitor_tx => monitor_tx_S,
+ monitor_rx => monitor_rx,
+ monitor_txdata => monitor_txdata_S,
+ monitor_txwrite => monitor_txwrite_S,
+ monitor_txfull => monitor_txfull_S,
+ monitor_rxdata => monitor_rxdata_S,
+ monitor_rxread => monitor_rxread_S,
+ monitor_rxempty => monitor_rxempty_S
+ );
+monitor_tx <= monitor_tx_S;
+monitor_txdata_S <= monitor_txdata when insertingstat_S='0' else insert_txdata_S;
+monitor_txwrite_S <= monitor_txwrite when insertingstat_S='0' else insert_txwrite_S;
+monitor_txfull <= monitor_txfull_S when insertingstat_S='0' else '1';
+monitor_rxdata <= monitor_rxdata_S when insertingcmd_S='0' else insert_rxdata_S;
+monitor_rxread_S <= monitor_rxread when insertingcmd_S='0' else '0';
+monitor_rxempty <= monitor_rxempty_S when insertingcmd_S='0' else insert_rxempty_S;
+
+process(icap_clk)
+variable rxcount_V : integer range 0 to 16*V_ENABLETIME*12 := 0;
+variable delaycount_V : integer range 0 to 16*V_ENABLETIME*115200 := 0;
+begin
+ if rising_edge(icap_clk) then
+ if delaycount_V<16*V_ENABLETIME*115200-1 then
+ delaycount_V := delaycount_V+1;
+ else
+ delaycount_V := 0;
+ insert_S <= '1';
+ end if;
+ if insertingcmd_S='0' then
+ if monitor_rx='1' then
+ if rxcount_V<16*V_ENABLETIME*12-1 then
+ rxcount_V := rxcount_V+1;
+ else
+ if (monitor_rxempty_S='1') and (monitor_rxread='0') and (insert_S='1') then
+ insertingcmd_S <= '1';
+ insert_rxempty_S <= '0';
+ insert_rxdata_S <= x"53";
+ end if;
+ end if;
+ else
+ rxcount_V := 0;
+ end if;
+ else
+ insert_S <= '0';
+ if insert_rxempty_S='1' then
+ insertingcmd_S <= '0';
+ else
+ if monitor_rxread='1' then
+ insert_rxempty_S <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(icap_clk)
+variable rxcount_V : integer range 0 to 16*V_ENABLETIME*12 := 0;
+begin
+ if rising_edge(icap_clk) then
+ insert_data_read_S <= '0';
+ insert_txwrite_S <= '0';
+ if insertingstat_S='0' then
+ if (monitor_tx_S='1') and (monitor_txwrite_S='0') then
+ if rxcount_V<16*V_ENABLETIME*12-1 then
+ rxcount_V := rxcount_V+1;
+ else
+ if (insert_data_available='1') then
+ insert_data_read_S <= '1';
+ insertingstat_S <= '1';
+ insert_writecr_S <= '0';
+ end if;
+ end if;
+ else
+ rxcount_V := 0;
+ end if;
+ else
+ if insert_writecr_S='0' then
+ if insert_data_read_S='1' then
+ insert_txdata_S <= insert_data;
+ if monitor_txfull_S='0' then
+ insert_txwrite_S <= '1';
+ end if;
+ else
+ if insert_txwrite_S='0' then
+ if monitor_txfull_S='0' then
+ insert_txwrite_S <= '1';
+ end if;
+ else
+ insert_writecr_S <= '1';
+ end if;
+ end if;
+ else
+ insert_txdata_S <= x"0d";
+ if insert_txwrite_S='1' then
+ insertingstat_S <= '0';
+ else
+ if monitor_txfull_S='0' then
+ insert_txwrite_S <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+insert_data_read <= insert_data_read_S;
+
+
+ ---------------------------------------------------------------------------
+ -- The hid sub-entity contains a Vivado Lab Tools VIO for interfacing.
+ ---------------------------------------------------------------------------
+
+ example_hid : sem_sem_hid
+ port map (
+ icap_clk => icap_clk,
+ status_heartbeat => status_heartbeat_internal,
+ status_initialization => status_initialization_internal,
+ status_observation => status_observation_internal,
+ status_correction => status_correction_internal,
+ status_classification => status_classification_internal,
+ status_injection => status_injection_internal,
+ status_essential => status_essential_internal,
+ status_uncorrectable => status_uncorrectable_internal,
+ inject_strobe => inject_strobe,
+ inject_address => inject_address,
+ disable_all => disable_all,
+ ADC_selREGS => ADC_selREGS,
+ disable_tests => disable_tests
+ );
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
--- /dev/null
+
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/ Core: sem
+-- \ \ Entity: sem_sem_hid
+-- / / Filename: sem_sem_hid.vhd
+-- /___/ /\ Purpose: HID Shim using Vivado Lab Tools components.
+-- \ \ / \
+-- \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity contains instances of Virtual Input/Output (VIO) cores to enable
+-- interactive injection of errors and observation of status.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- icap_clk input The system clock signal.
+--
+-- status_heartbeat input Heartbeat signal for external watch
+-- dog timer implementation; pulses
+-- when readback runs. Synchronous to
+-- icap_clk.
+--
+-- status_initialization input Indicates initialization is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_observation input Indicates observation is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_correction input Indicates correction is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_classification input Indicates classification is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_injection input Indicates injection is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_essential input Indicates essential error condition.
+-- Qualified by de-assertion of the
+-- status_classification signal, and
+-- is synchronous to icap_clk.
+--
+-- status_uncorrectable input Indicates uncorrectable error
+-- condition. Qualified by de-assertion
+-- of the status_correction signal, and
+-- is synchronous to icap_clk.
+--
+-- inject_strobe output Error injection port strobe used
+-- by the controller to enable capture
+-- of the error injection address.
+-- Synchronous to icap_clk.
+--
+-- inject_address[39:0] output Error injection port address used
+-- to specify the location of a bit
+-- to be corrupted. Synchronous to
+-- icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- TCQ int Sets the clock-to-out for behavioral
+-- descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_hid
+-- |
+-- \- sem_sem_vio
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_hid is
+port (
+ icap_clk : in std_logic;
+ status_heartbeat : in std_logic;
+ status_initialization : in std_logic;
+ status_observation : in std_logic;
+ status_correction : in std_logic;
+ status_classification : in std_logic;
+ status_injection : in std_logic;
+ status_essential : in std_logic;
+ status_uncorrectable : in std_logic;
+ inject_strobe : out std_logic;
+ inject_address : out std_logic_vector(39 downto 0);
+ disable_all : out std_logic;
+ ADC_selREGS : out std_logic_vector(2 downto 0);
+ disable_tests : out std_logic_vector(3 downto 0)
+ );
+end entity sem_sem_hid;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_hid is
+
+ ---------------------------------------------------------------------------
+ -- Define local constants.
+ ---------------------------------------------------------------------------
+
+ constant TCQ : time := 1 ps;
+ constant MAXOFFSET : integer := 16383;
+ constant MAXCOUNT : integer := 4095;
+
+ ---------------------------------------------------------------------------
+ -- Define local output wires.
+ ---------------------------------------------------------------------------
+
+ signal inject_strobe_internal : std_logic;
+ signal inject_address_internal : std_logic_vector(39 downto 0);
+ signal previous_inject_strobe_internal : std_logic:= '0';
+
+
+type testmode_type is (NORMAL,IDLE,INJECT,OBSERV,RESET,AUTO,TIMED,NONE);
+signal testmode_S : testmode_type := NORMAL;
+signal testmode : std_logic_vector(2 downto 0);
+signal prev_testmode_S : testmode_type := NORMAL;
+signal count_S : integer range 0 to MAXCOUNT := 0;
+signal offset_S : integer range 0 to MAXOFFSET := 0;
+signal inject_address_S : std_logic_vector(39 downto 0);
+signal prev_inject_address_S : std_logic_vector(39 downto 0);
+
+ attribute mark_debug : string;
+ attribute mark_debug of status_heartbeat : signal is "true";
+ attribute mark_debug of status_initialization : signal is "true";
+ attribute mark_debug of status_observation : signal is "true";
+ attribute mark_debug of status_correction : signal is "true";
+ attribute mark_debug of status_classification : signal is "true";
+ attribute mark_debug of status_injection : signal is "true";
+ attribute mark_debug of status_essential : signal is "true";
+ attribute mark_debug of status_uncorrectable : signal is "true";
+ attribute mark_debug of inject_address_internal : signal is "true";
+ attribute mark_debug of disable_all : signal is "true";
+ attribute mark_debug of ADC_selREGS : signal is "true";
+ attribute mark_debug of disable_tests : signal is "true";
+
+ ---------------------------------------------------------------------------
+ -- Component Declaration
+ ---------------------------------------------------------------------------
+
+ component sem_sem_vio
+ port (
+ clk : in std_logic;
+ probe_in0 : in std_logic_vector(0 downto 0);
+ probe_in1 : in std_logic_vector(0 downto 0);
+ probe_in2 : in std_logic_vector(0 downto 0);
+ probe_in3 : in std_logic_vector(0 downto 0);
+ probe_in4 : in std_logic_vector(0 downto 0);
+ probe_in5 : in std_logic_vector(0 downto 0);
+ probe_in6 : in std_logic_vector(0 downto 0);
+ probe_in7 : in std_logic_vector(0 downto 0);
+ probe_out0 : out std_logic_vector(0 downto 0);
+ probe_out1 : out std_logic_vector(39 downto 0);
+ probe_out2 : out std_logic_vector(2 downto 0);
+ probe_out3 : out std_logic_vector(0 downto 0);
+ probe_out4 : out std_logic_vector(2 downto 0);
+ probe_out5 : out std_logic_vector(3 downto 0);
+ probe_out6 : out std_logic_vector(0 downto 0);
+ probe_out7 : out std_logic_vector(0 downto 0)
+ );
+ end component;
+
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+ begin
+
+ ---------------------------------------------------------------------------
+ -- Create a 1-cycle pulse from the VIO inject_strobe output to ensure a
+ -- single error injection command is issued to the SEM controller.
+ ---------------------------------------------------------------------------
+
+ process(icap_clk)
+ begin
+ if rising_edge(icap_clk) then
+ previous_inject_strobe_internal <= inject_strobe_internal after TCQ;
+ end if;
+ end process;
+
+ -- inject_strobe <= (not previous_inject_strobe_internal) and
+ -- inject_strobe_internal;
+ -- inject_address <= inject_address_internal;
+
+ ---------------------------------------------------------------------------
+ -- Instantiate the SEM VIO core.
+ ---------------------------------------------------------------------------
+
+ example_vio : sem_sem_vio
+ port map (
+ clk => icap_clk,
+ probe_in0(0) => status_heartbeat,
+ probe_in1(0) => status_uncorrectable,
+ probe_in2(0) => status_essential,
+ probe_in3(0) => status_injection,
+ probe_in4(0) => status_classification,
+ probe_in5(0) => status_correction,
+ probe_in6(0) => status_observation,
+ probe_in7(0) => status_initialization,
+ probe_out0(0) => inject_strobe_internal,
+ probe_out1(39 downto 0) => inject_address_internal,
+ probe_out2(2 downto 0) => testmode,
+ probe_out3(0) => disable_all,
+ probe_out4(2 downto 0) => ADC_selREGS,
+ probe_out5(3 downto 0) => disable_tests,
+ probe_out6(0) => open,
+ probe_out7(0) => open
+ );
+testmode_S <= NORMAL when testmode="000" else
+ IDLE when testmode="001" else
+ INJECT when testmode="010" else
+ OBSERV when testmode="011" else
+ RESET when testmode="100" else
+ AUTO when testmode="101" else
+ TIMED when testmode="110" else
+ NONE when testmode="111" else
+ IDLE when testmode="000" else
+ NORMAL;
+
+inject_address <= inject_address_S;
+
+ process(icap_clk)
+ begin
+ if rising_edge(icap_clk) then
+ inject_strobe <= '0';
+ case testmode_S is
+ when NORMAL =>
+ inject_address_S <= inject_address_internal;
+ if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+ inject_strobe <= '1';
+ end if;
+ when IDLE =>
+ inject_address_S(39 downto 36) <= "1110";
+ inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+ if (prev_testmode_S/=testmode_S) then
+ inject_strobe <= '1';
+ end if;
+ if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+ inject_strobe <= '1';
+ end if;
+ when INJECT =>
+ inject_address_S(39 downto 36) <= "1100";
+ inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+ if (prev_testmode_S/=testmode_S) then
+ inject_strobe <= '1';
+ end if;
+ if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+ inject_strobe <= '1';
+ end if;
+ when OBSERV =>
+ inject_address_S(39 downto 36) <= "1010";
+ inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+ if (prev_testmode_S/=testmode_S) then
+ inject_strobe <= '1';
+ end if;
+ if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+ inject_strobe <= '1';
+ end if;
+ when RESET =>
+ inject_address_S(39 downto 36) <= "1011";
+ inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+ if (prev_testmode_S/=testmode_S) then
+ inject_strobe <= '1';
+ end if;
+ if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+ inject_strobe <= '1';
+ end if;
+ when AUTO =>
+ inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+ if (prev_inject_address_S(35 downto 0)/=inject_address_internal(35 downto 0))
+ or (prev_testmode_S/=testmode_S)
+ or ((inject_strobe_internal='1') and (previous_inject_strobe_internal='0')) then
+ inject_strobe <= '1';
+ inject_address_S(39 downto 36) <= "1110";
+ count_S <= 0;
+ else
+ if count_S=1000 then
+ inject_address_S(39 downto 36) <= "1100";
+ inject_strobe <= '1';
+ elsif count_S=2000 then
+ inject_address_S(39 downto 36) <= "1010";
+ inject_strobe <= '1';
+ end if;
+ if count_S<4095 then
+ count_S <= count_S+1;
+ end if;
+ end if;
+ when TIMED =>
+ if (prev_inject_address_S(35 downto 0)/=inject_address_internal(35 downto 0))
+ or (prev_testmode_S/=testmode_S)
+ or ((inject_strobe_internal='1') and (previous_inject_strobe_internal='0')) then
+ inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+ offset_S <= 0;
+ count_S <= 0;
+ else
+ if offset_S<MAXOFFSET then
+ if count_S=0 then
+ inject_strobe <= '1';
+ inject_address_S(39 downto 36) <= "1110";
+ inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0) + conv_std_logic_vector(offset_S,36);
+ elsif count_S=100 then
+ inject_address_S(39 downto 36) <= "1100";
+ inject_strobe <= '1';
+ elsif count_S=200 then
+ inject_address_S(39 downto 36) <= "1010";
+ inject_strobe <= '1';
+ end if;
+ if count_S<MAXCOUNT then
+ count_S <= count_S+1;
+ else
+ count_S <= 0;
+ offset_S <= offset_S+1;
+ end if;
+ end if;
+ end if;
+ when NONE =>
+ when OTHERS =>
+ end case;
+ prev_testmode_S <= testmode_S;
+ prev_inject_address_S <= inject_address_internal;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
+
--- /dev/null
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/ Core: sem
+-- \ \ Entity: sem_sem_mon
+-- / / Filename: sem_sem_mon.vhd
+-- /___/ /\ Purpose: MON Shim for RS232 Port.
+-- \ \ / \
+-- \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity is a MON Shim implementation for communication with external
+-- RS232 devices. Examples of external devices include a desktop or laptop
+-- computer, or an embedded processor system. This shim may be replaced with
+-- a custom user-supplied design to enable communication with other devices.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- icap_clk input The system clock signal.
+--
+-- monitor_tx output Serial status output. Synchronous
+-- to icap_clk, but received externally
+-- by another device as an asynchronous
+-- signal, perceived as lower bitrate.
+-- Uses 8N1 protocol.
+--
+-- monitor_rx input Serial command input. Asynchronous
+-- signal provided by another device at
+-- a lower bitrate, synchronized to the
+-- icap_clk and oversampled. Uses 8N1
+-- protocol.
+--
+-- monitor_txdata[7:0] input Output data from controller,
+-- qualified by monitor_txwrite.
+-- Synchronous to icap_clk.
+--
+-- monitor_txwrite input Write strobe, used by peripheral
+-- to capture data. Synchronous to
+-- icap_clk.
+--
+-- monitor_txfull output Flow control signal indicating the
+-- peripheral is not ready to receive
+-- additional data writes. Synchronous
+-- to icap_clk.
+--
+-- monitor_rxdata[7:0] output Input data to controller qualified
+-- by monitor_rxread. Synchronous to
+-- icap_clk.
+--
+-- monitor_rxread input Read strobe, used by peripheral
+-- to change state. Synchronous to
+-- icap_clk.
+--
+-- monitor_rxempty output Flow control signal indicating the
+-- peripheral is not ready to service
+-- additional data reads. Synchronous
+-- to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- TCQ int Sets the clock-to-out for behavioral
+-- descriptions of sequential logic.
+--
+-- V_ENABLETIME int This sets communication baud rate;
+-- see user guide for additional detail.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_mon
+-- |
+-- +- sem_sem_mon_fifo
+-- |
+-- +- sem_sem_mon_piso
+-- |
+-- \- sem_sem_mon_sipo
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_mon is
+port (
+ icap_clk : in std_logic;
+ monitor_tx : out std_logic;
+ monitor_rx : in std_logic;
+ monitor_txdata : in std_logic_vector(7 downto 0);
+ monitor_txwrite : in std_logic;
+ monitor_txfull : out std_logic;
+ monitor_rxdata : out std_logic_vector(7 downto 0);
+ monitor_rxread : in std_logic;
+ monitor_rxempty : out std_logic
+ );
+end entity sem_sem_mon;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_mon is
+
+ ---------------------------------------------------------------------------
+ -- Define local constants.
+ ---------------------------------------------------------------------------
+
+ constant TCQ : time := 1 ps;
+ constant V_ENABLETIME : integer := 21; -- FOR 115200 259; FOR 9600
+
+ ---------------------------------------------------------------------------
+ -- Declare non-library components.
+ ---------------------------------------------------------------------------
+
+ component sem_sem_mon_fifo
+ port (
+ icap_clk : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ write : in std_logic;
+ read : in std_logic;
+ full : out std_logic;
+ data_present : out std_logic
+ );
+ end component;
+
+ component sem_sem_mon_sipo
+ port (
+ icap_clk : in std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ serial_in : in std_logic;
+ en_16_x_baud : in std_logic;
+ data_strobe : out std_logic
+ );
+ end component;
+
+ component sem_sem_mon_piso
+ port (
+ icap_clk : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ send_character : in std_logic;
+ en_16_x_baud : in std_logic;
+ serial_out : out std_logic;
+ tx_complete : out std_logic
+ );
+ end component;
+
+ ---------------------------------------------------------------------------
+ -- Declare signals.
+ ---------------------------------------------------------------------------
+
+ signal en_16_x_counter : std_logic_vector(11 downto 0) := X"000";
+ signal en_16_x_baud : std_logic;
+ signal fifo_read : std_logic;
+ signal fifo_data_present : std_logic;
+ signal fifo_data_out : std_logic_vector(7 downto 0);
+ signal txfull_p : std_logic;
+ signal fifo_write : std_logic;
+ signal fifo_data_in : std_logic_vector(7 downto 0);
+ signal fifo_unused : std_logic;
+ signal rxempty_n : std_logic;
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+ begin
+
+ ---------------------------------------------------------------------------
+ -- Create the 16x enable signal for baud rate generation. This has an
+ -- initial value, but no functional reset; it runs continuously.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ if (en_16_x_baud = '1') then
+ en_16_x_counter <= X"000" after TCQ;
+ else
+ en_16_x_counter <= en_16_x_counter + X"001" after TCQ;
+ end if;
+ end if;
+ end process;
+
+ en_16_x_baud <= '1' when (en_16_x_counter = conv_std_logic_vector(V_ENABLETIME,12)) else '0';
+
+ ---------------------------------------------------------------------------
+ -- Implement the transmit channel with a FIFO and PISO.
+ ---------------------------------------------------------------------------
+
+ example_mon_fifo_tx : sem_sem_mon_fifo
+ port map (
+ data_in => monitor_txdata,
+ data_out => fifo_data_out,
+ write => monitor_txwrite,
+ read => fifo_read,
+ full => txfull_p,
+ data_present => fifo_data_present,
+ icap_clk => icap_clk
+ );
+
+ example_mon_piso : sem_sem_mon_piso
+ port map (
+ data_in => fifo_data_out,
+ send_character => fifo_data_present,
+ en_16_x_baud => en_16_x_baud,
+ serial_out => monitor_tx,
+ tx_complete => fifo_read,
+ icap_clk => icap_clk
+ );
+
+ monitor_txfull <= txfull_p;
+
+ ---------------------------------------------------------------------------
+ -- Implement the receive channel with a SIPO and FIFO.
+ ---------------------------------------------------------------------------
+
+ example_mon_sipo : sem_sem_mon_sipo
+ port map (
+ serial_in => monitor_rx,
+ data_out => fifo_data_in,
+ data_strobe => fifo_write,
+ en_16_x_baud => en_16_x_baud,
+ icap_clk => icap_clk
+ );
+
+ example_mon_fifo_rx : sem_sem_mon_fifo
+ port map (
+ data_in => fifo_data_in,
+ data_out => monitor_rxdata,
+ write => fifo_write,
+ read => monitor_rxread,
+ full => fifo_unused,
+ data_present => rxempty_n,
+ icap_clk => icap_clk
+ );
+
+ monitor_rxempty <= not (rxempty_n);
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
--- /dev/null
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/ Core: sem
+-- \ \ Entity: sem_sem_mon_fifo
+-- / / Filename: sem_sem_mon_fifo.vhd
+-- /___/ /\ Purpose: MON Shim 32x8 FIFO.
+-- \ \ / \
+-- \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity contains a 32x8 synchronous FIFO implementation.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- icap_clk input The system clock signal.
+--
+-- data_in[7:0] input Input to the FIFO. Synchronous
+-- to icap_clk.
+--
+-- data_out[7:0] output Output from the FIFO. Synchronous
+-- to icap_clk.
+--
+-- write input Write strobe, used to enable data
+-- capture. Synchronous to icap_clk.
+--
+-- read input Read strobe, used to advance data
+-- output to next value. Synchronous
+-- to icap_clk.
+--
+-- full output Indicates when the FIFO is full.
+-- Synchronous to icap_clk.
+--
+-- data_present output Indicates when the FIFO has data
+-- (not empty). Synchronous to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- TCQ int Sets the clock-to-out for behavioral
+-- descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_mon_fifo
+-- |
+-- \- SRLC32E (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_mon_fifo is
+port (
+ icap_clk : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ write : in std_logic;
+ read : in std_logic;
+ full : out std_logic;
+ data_present : out std_logic
+ );
+end entity sem_sem_mon_fifo;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_mon_fifo is
+
+ ---------------------------------------------------------------------------
+ -- Define local constants.
+ ---------------------------------------------------------------------------
+
+ constant TCQ : time := 1 ps;
+
+ ---------------------------------------------------------------------------
+ -- Declare non-library components.
+ ---------------------------------------------------------------------------
+
+ -- None
+
+ ---------------------------------------------------------------------------
+ -- Declare signals.
+ ---------------------------------------------------------------------------
+
+ signal augend : std_logic_vector(5 downto 0) := "011111";
+ signal addend : std_logic_vector(5 downto 0);
+ signal addsel : std_logic_vector(1 downto 0);
+ signal valid_write : std_logic;
+ signal valid_read : std_logic;
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+ begin
+
+ ---------------------------------------------------------------------------
+ -- Data storage.
+ ---------------------------------------------------------------------------
+
+ data_srl_0 : SRLC32E
+ port map (
+ D => data_in(0),
+ CE => write,
+ CLK => icap_clk,
+ A => augend(4 downto 0),
+ Q => data_out(0),
+ Q31 => open
+ );
+
+ data_srl_1 : SRLC32E
+ port map (
+ D => data_in(1),
+ CE => write,
+ CLK => icap_clk,
+ A => augend(4 downto 0),
+ Q => data_out(1),
+ Q31 => open
+ );
+
+ data_srl_2 : SRLC32E
+ port map (
+ D => data_in(2),
+ CE => write,
+ CLK => icap_clk,
+ A => augend(4 downto 0),
+ Q => data_out(2),
+ Q31 => open
+ );
+
+ data_srl_3 : SRLC32E
+ port map (
+ D => data_in(3),
+ CE => write,
+ CLK => icap_clk,
+ A => augend(4 downto 0),
+ Q => data_out(3),
+ Q31 => open
+ );
+
+ data_srl_4 : SRLC32E
+ port map (
+ D => data_in(4),
+ CE => write,
+ CLK => icap_clk,
+ A => augend(4 downto 0),
+ Q => data_out(4),
+ Q31 => open
+ );
+
+ data_srl_5 : SRLC32E
+ port map (
+ D => data_in(5),
+ CE => write,
+ CLK => icap_clk,
+ A => augend(4 downto 0),
+ Q => data_out(5),
+ Q31 => open
+ );
+
+ data_srl_6 : SRLC32E
+ port map (
+ D => data_in(6),
+ CE => write,
+ CLK => icap_clk,
+ A => augend(4 downto 0),
+ Q => data_out(6),
+ Q31 => open
+ );
+
+ data_srl_7 : SRLC32E
+ port map (
+ D => data_in(7),
+ CE => write,
+ CLK => icap_clk,
+ A => augend(4 downto 0),
+ Q => data_out(7),
+ Q31 => open
+ );
+
+ ---------------------------------------------------------------------------
+ -- Buffer management.
+ ---------------------------------------------------------------------------
+
+ valid_write <= write when (augend /= "111111") else '0';
+ valid_read <= read and augend(5);
+ addsel <= valid_read & valid_write;
+
+ process (addsel)
+ begin
+ case addsel is
+ when "01" => addend <= "000001";
+ when "10" => addend <= "111111";
+ when others => addend <= "000000";
+ end case;
+ end process;
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ augend <= (augend + addend) after TCQ;
+ end if;
+ end process;
+
+ data_present <= augend(5);
+ full <= '1' when (augend = "111111") else '0';
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
--- /dev/null
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/ Core: sem
+-- \ \ Entity: sem_sem_mon_piso
+-- / / Filename: sem_sem_mon_piso.vhd
+-- /___/ /\ Purpose: MON Shim 8N1 PISO.
+-- \ \ / \
+-- \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity contains an 8N1 PISO implementation.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- icap_clk input The system clock signal.
+--
+-- data_in[7:0] input Input to the PISO. Synchronous
+-- to icap_clk.
+--
+-- send_character input Qualifies availability of valid
+-- data on data_in port. Synchronous
+-- to icap_clk.
+--
+-- en_16_x_baud input Enable signal with periodic single
+-- cycle pulses at 16 times baud rate.
+-- Synchronous to icap_clk.
+--
+-- serial_out output Serialized output. Synchronous
+-- to icap_clk.
+--
+-- tx_complete output Indicates transmission complete.
+-- Synchronous to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- TCQ int Sets the clock-to-out for behavioral
+-- descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_mon_piso
+-- |
+-- \- FD (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_mon_piso is
+port (
+ icap_clk : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ send_character : in std_logic;
+ en_16_x_baud : in std_logic;
+ serial_out : out std_logic;
+ tx_complete : out std_logic
+ );
+end entity sem_sem_mon_piso;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_mon_piso is
+
+ ---------------------------------------------------------------------------
+ -- Define local constants.
+ ---------------------------------------------------------------------------
+
+ constant TCQ : time := 1 ps;
+
+ ---------------------------------------------------------------------------
+ -- Declare non-library components.
+ ---------------------------------------------------------------------------
+
+ -- None
+
+ ---------------------------------------------------------------------------
+ -- Declare signals.
+ ---------------------------------------------------------------------------
+
+ signal hot_delay : std_logic_vector(15 downto 0) := X"0000";
+ signal bit_select : std_logic_vector(2 downto 0) := "000";
+ signal piso_out : std_logic := '1';
+ signal all_done : std_logic := '0';
+ signal tx_start : std_logic := '0';
+ signal tx_stop : std_logic := '0';
+ signal tx_run : std_logic := '0';
+ signal tx_bit : std_logic;
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+ begin
+
+ ---------------------------------------------------------------------------
+ -- Convert parallel data to serial data with provision for stop and start.
+ -- Follow this by a flip-flop instance specifically for packing to pin.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ if (tx_start = '1') then
+ piso_out <= '0' after TCQ;
+ elsif (tx_stop = '1') then
+ piso_out <= '1' after TCQ;
+ elsif (tx_run = '1') then
+ piso_out <= data_in(conv_integer(bit_select)) after TCQ;
+ else
+ piso_out <= '1' after TCQ;
+ end if;
+ end if;
+ end process;
+
+ pipeline_serial : FD
+ generic map (INIT => '1')
+ port map (
+ D => piso_out,
+ Q => serial_out,
+ C => icap_clk
+ );
+
+ ---------------------------------------------------------------------------
+ -- Transmit bit counter.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ if (tx_start = '1') then
+ bit_select <= "000" after TCQ;
+ elsif ((en_16_x_baud = '1') and (tx_run = '1') and (tx_bit = '1')) then
+ bit_select <= bit_select + "001" after TCQ;
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------
+ -- Start bit enable.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ if (en_16_x_baud = '1') then
+ tx_start <= (
+ (not tx_start and (send_character and not tx_start and not tx_run) and not tx_stop and not tx_bit) or
+ (not tx_start and (send_character and not tx_start and not tx_run) and tx_stop and tx_bit) or
+ ( tx_start and not (send_character and not tx_start and not tx_run) and not tx_stop and not tx_bit) )
+ after TCQ;
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------
+ -- Stop bit enable.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ if (en_16_x_baud = '1') then
+ tx_stop <= (
+ (not tx_stop and (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0))) and tx_run and tx_bit) or
+ ( tx_stop and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0))) and not tx_run and not tx_bit) )
+ after TCQ;
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------
+ -- Run bit enable.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ if (en_16_x_baud = '1') then
+ tx_run <= (
+ (not tx_run and tx_start and tx_bit and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) or
+ ( tx_run and not tx_start and not tx_bit and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) or
+ ( tx_run and not tx_start and tx_bit and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) or
+ ( tx_run and tx_start and not tx_bit and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) )
+ after TCQ;
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------
+ -- Bit rate enable.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ if (en_16_x_baud = '1') then
+ hot_delay(0) <= (
+ (not tx_stop and not (send_character and not tx_start and not tx_run) and tx_bit) or
+ ( tx_stop and (send_character and not tx_start and not tx_run) and tx_bit) or
+ (not tx_stop and (send_character and not tx_start and not tx_run) and not tx_bit) )
+ after TCQ;
+ hot_delay(15 downto 1) <= hot_delay(14 downto 0) after TCQ;
+ end if;
+ end if;
+ end process;
+
+ tx_bit <= hot_delay(15);
+
+ ---------------------------------------------------------------------------
+ -- Transmit complete strobe.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ all_done <= (en_16_x_baud and (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) after TCQ;
+ end if;
+ end process;
+
+ tx_complete <= all_done;
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
--- /dev/null
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/ Core: sem
+-- \ \ Entity: sem_sem_mon_sipo
+-- / / Filename: sem_sem_mon_sipo.vhd
+-- /___/ /\ Purpose: MON Shim 8N1 SIPO.
+-- \ \ / \
+-- \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity contains an 8N1 SIPO implementation.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- icap_clk input The system clock signal.
+--
+-- data_out[7:0] output Output from the SIPO. Synchronous
+-- to icap_clk.
+--
+-- serial_in output Asynchronous serial input.
+--
+-- en_16_x_baud input Enable signal with periodic single
+-- cycle pulses at 16 times baud rate.
+-- Synchronous to icap_clk.
+--
+-- data_strobe output Indicates reception complete.
+-- Synchronous to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- TCQ int Sets the clock-to-out for behavioral
+-- descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_mon_sipo
+-- |
+-- \- FD (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_mon_sipo is
+port (
+ icap_clk : in std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ serial_in : in std_logic;
+ en_16_x_baud : in std_logic;
+ data_strobe : out std_logic
+ );
+end entity sem_sem_mon_sipo;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_mon_sipo is
+
+ ---------------------------------------------------------------------------
+ -- Define local constants.
+ ---------------------------------------------------------------------------
+
+ constant TCQ : time := 1 ps;
+
+ attribute ASYNC_REG : string;
+ attribute ASYNC_REG of sync_reg_a : label is "TRUE";
+ attribute ASYNC_REG of sync_reg_b : label is "TRUE";
+ attribute ASYNC_REG of sync_reg_c : label is "TRUE";
+ attribute ASYNC_REG of sync_reg_d : label is "TRUE";
+
+ ---------------------------------------------------------------------------
+ -- Declare non-library components.
+ ---------------------------------------------------------------------------
+
+ -- None
+
+ ---------------------------------------------------------------------------
+ -- Declare signals.
+ ---------------------------------------------------------------------------
+
+ signal sync_serial_a : std_logic;
+ signal sync_serial_b : std_logic;
+ signal sync_serial_c : std_logic;
+ signal stop_bit : std_logic;
+ signal edge_delay : std_logic;
+ signal start_edge : std_logic;
+ signal delay_line : std_logic_vector(150 downto 0) := (others => '0');
+ signal valid_delay : std_logic_vector(151 downto 0) := (others => '0');
+ signal data_strobe_int : std_logic := '0';
+ signal valid_char : std_logic := '0';
+ signal purge : std_logic := '0';
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+ begin
+
+ ---------------------------------------------------------------------------
+ -- Synchronize serial input.
+ ---------------------------------------------------------------------------
+
+ sync_reg_a : FD
+ port map (D => serial_in, Q => sync_serial_a, C => icap_clk);
+ sync_reg_b : FD
+ port map (D => sync_serial_a, Q => sync_serial_b, C => icap_clk);
+ sync_reg_c : FD
+ port map (D => sync_serial_b, Q => sync_serial_c, C => icap_clk);
+ sync_reg_d : FD
+ port map (D => sync_serial_c, Q => stop_bit, C => icap_clk);
+
+ ---------------------------------------------------------------------------
+ -- Create a delay line to pick out various bits of the serial signal by
+ -- capturing the incoming signal at 16 times the baud rate. This block
+ -- also delays the valid_char pulse, the length of time equivalent to
+ -- purge the data shift register. This is used to generate purge signal
+ -- which locks out additional strobes that might otherwise occur while
+ -- the most recent captured data makes it way out of the shift register.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ if (en_16_x_baud = '1') then
+ delay_line <= (delay_line(149 downto 0) & stop_bit) after TCQ;
+ valid_char <= (not edge_delay and start_edge and stop_bit and not purge) after TCQ;
+ valid_delay <= (valid_delay(150 downto 0) & valid_char) after TCQ;
+ purge <= ((purge or valid_char) and not valid_delay(151)) after TCQ;
+ end if;
+ end if;
+ end process;
+
+ data_out <= (delay_line( 15) &
+ delay_line( 31) &
+ delay_line( 47) &
+ delay_line( 63) &
+ delay_line( 79) &
+ delay_line( 95) &
+ delay_line(111) &
+ delay_line(127));
+ edge_delay <= delay_line(149);
+ start_edge <= delay_line(150);
+
+ ---------------------------------------------------------------------------
+ -- Generate a single-cycle output data strobe when the character is valid.
+ ---------------------------------------------------------------------------
+
+ process (icap_clk)
+ begin
+ if rising_edge (icap_clk) then
+ data_strobe_int <= (valid_char and en_16_x_baud) after TCQ;
+ end if;
+ end process;
+
+ data_strobe <= data_strobe_int;
+
+ ---------------------------------------------------------------------------
+ --
+ ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
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--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_512x41</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
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--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_FWFT_512x36</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">510</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
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--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
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--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
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+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
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+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
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--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
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--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_WIDTH">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_WIDTH">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_INIT_VAL">0x0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_INIT_VAL">0x0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio36</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_PROBE_IN" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_OUT0_WIDTH" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity reboot is
+ port (
+ TRIGGER : in std_logic;
+ SYSCLK : in std_logic
+ );
+end reboot;
+
+architecture Behavioral of reboot is
+
+
+ type FSM_STATE is (STATE_00, STATE_01, STATE_02, STATE_03, STATE_04, STATE_05,
+ STATE_06, STATE_07, STATE_08, STATE_09, STATE_10, STATE_11);
+ signal NEXT_STATE : FSM_STATE := STATE_00;
+ signal CE : std_logic := '1';
+ signal I : std_logic_vector(31 downto 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+ signal ICAP_WRITE : std_logic := '1';
+begin
+
+ ICAPE2_inst : ICAPE2
+ generic map (
+ ICAP_WIDTH => "X32",
+ SIM_CFG_FILE_NAME => "NONE"
+ )
+ port map (
+ O => open, -- 32-bit output (not used)
+ CLK => SYSCLK, -- 1-bit Clock Input
+ CSIB => CE, -- 1-bit Active-Low ICAP Enable
+ I => I, -- 32-bit iConfiguration data input bus
+ RDWRB => ICAP_WRITE -- 1-bit input: Read/Write Select input
+ );
+
+ process(SYSCLK)
+ begin
+ if (falling_edge(SYSCLK)) then
+ if (TRIGGER = '0') then
+ case NEXT_STATE is
+ when STATE_00 =>
+ ICAP_WRITE <= '1';
+ CE <= '1';
+ I <= x"00000000";
+ NEXT_STATE <= STATE_01;
+ when STATE_01 =>
+ ICAP_WRITE <= '0';
+ CE <= '1';
+ I <= x"00000000";
+ NEXT_STATE <= STATE_02;
+ when STATE_02 =>
+ ICAP_WRITE <= '0';
+ CE <= '0';
+ I <= x"00000000";
+ NEXT_STATE <= STATE_03;
+ when STATE_03 =>
+ ICAP_WRITE <= '0';
+ CE <= '0';
+ I <= x"FFFFFFFF"; -- dummy word
+ NEXT_STATE <= STATE_04;
+ when STATE_04 =>
+ ICAP_WRITE <= '0';
+ CE <= '0';
+ I <= x"5599AA66"; -- sync word
+ NEXT_STATE <= STATE_05;
+ when STATE_05 =>
+ ICAP_WRITE <= '0';
+ CE <= '0';
+ I <= x"04000000"; -- Type 1 NO OP
+ NEXT_STATE <= STATE_06;
+ when STATE_06 =>
+ ICAP_WRITE <= '0';
+ CE <= '0';
+ I <= x"0C400080"; -- Type 1 Write 1 word to WBSTAR
+ NEXT_STATE <= STATE_07;
+ when STATE_07 =>
+ ICAP_WRITE <= '0';
+ CE <= '0';
+ I <= x"00000000"; -- x"00800000" Warm boot start address
+ NEXT_STATE <= STATE_08;
+ when STATE_08 =>
+ ICAP_WRITE <= '0';
+ CE <= '0';
+ I <= x"0C000180"; -- Type 1 write 1 word to CMD
+ NEXT_STATE <= STATE_09;
+ when STATE_09 =>
+ ICAP_WRITE <= '0';
+ CE <= '0';
+ I <= x"000000F0"; -- IPROG command
+ NEXT_STATE <= STATE_10;
+ when STATE_10 =>
+ ICAP_WRITE <= '0';
+ CE <= '0';
+ I <= x"04000000"; -- Type 1 NO OP
+ NEXT_STATE <= STATE_11;
+ when STATE_11 =>
+ ICAP_WRITE <= '0';
+ CE <= '1'; -- deassert CE
+ I <= x"04000000";
+ NEXT_STATE <= STATE_11;
+ when others =>
+ ICAP_WRITE <= '1';
+ CE <= '1';
+ I <= x"AAAAAAAA";
+ NEXT_STATE <= STATE_00;
+ end case;
+ else
+ ICAP_WRITE <= '1';
+ CE <= '1';
+ I <= x"AAAABBBB";
+ NEXT_STATE <= STATE_00;
+ end if;
+ end if;
+ end process;
+
+end Behavioral;
--- /dev/null
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ /
+-- \ \ \/ Core: sem
+-- \ \ Entity: sem_sem_example
+-- / / Filename: sem_sem_example.vhd
+-- /___/ /\ Purpose: System level design example.
+-- \ \ / \
+-- \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity is the system level design example, the top level of what is
+-- intended for physical implementation. This entity is essentially an HDL
+-- netlist of sub-entities used to construct the solution. The system level
+-- design example is customized by the Vivado IP Catalog.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- clk input System clock; the entire system is
+-- synchronized to this signal, which
+-- is distributed on a global clock
+-- buffer and referred to as icap_clk.
+--
+-- status_heartbeat output Heartbeat signal for external watch
+-- dog timer implementation; pulses
+-- when readback runs. Synchronous to
+-- icap_clk.
+--
+-- status_initialization output Indicates initialization is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_observation output Indicates observation is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_correction output Indicates correction is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_classification output Indicates classification is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_injection output Indicates injection is taking
+-- place. Synchronous to icap_clk.
+--
+-- status_essential output Indicates essential error condition.
+-- Qualified by de-assertion of the
+-- status_classification signal, and
+-- is synchronous to icap_clk.
+--
+-- status_uncorrectable output Indicates uncorrectable error
+-- condition. Qualified by de-assertion
+-- of the status_correction signal, and
+-- is synchronous to icap_clk.
+--
+-- monitor_tx output Serial status output. Synchronous
+-- to icap_clk, but received externally
+-- by another device as an asynchronous
+-- signal, perceived as lower bitrate.
+-- Uses 8N1 protocol.
+--
+-- monitor_rx input Serial command input. Asynchronous
+-- signal provided by another device at
+-- a lower bitrate, synchronized to the
+-- icap_clk and oversampled. Uses 8N1
+-- protocol.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name Type Description
+-- ============================= ====== ====================================
+-- TCQ int Sets the clock-to-out for behavioral
+-- descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_example
+-- |
+-- +- sem (sem_controller)
+-- |
+-- +- sem_sem_cfg
+-- |
+-- +- sem_sem_mon
+-- |
+-- +- sem_sem_hid
+-- |
+-- +- IBUF (unisim)
+-- |
+-- \- BUFGCE (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_module is
+port (
+ clk : in std_logic;
+ status_heartbeat : out std_logic;
+ status_initialization : out std_logic;
+ status_observation : out std_logic;
+ status_correction : out std_logic;
+ status_classification : out std_logic;
+ status_injection : out std_logic;
+ status_essential : out std_logic;
+ status_uncorrectable : out std_logic
+ );
+end sem_module;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_module is
+
+ ---------------------------------------------------------------------------
+ -- Define local constants.
+ ---------------------------------------------------------------------------
+
+ constant TCQ : time := 1 ps;
+
+ ---------------------------------------------------------------------------
+ -- Declare non-library components.
+ ---------------------------------------------------------------------------
+
+ component sem
+ port (
+ status_heartbeat : out std_logic;
+ status_initialization : out std_logic;
+ status_observation : out std_logic;
+ status_correction : out std_logic;
+ status_classification : out std_logic;
+ status_injection : out std_logic;
+ status_essential : out std_logic;
+ status_uncorrectable : out std_logic;
+ monitor_txdata : out std_logic_vector(7 downto 0);
+ monitor_txwrite : out std_logic;
+ monitor_txfull : in std_logic;
+ monitor_rxdata : in std_logic_vector(7 downto 0);
+ monitor_rxread : out std_logic;
+ monitor_rxempty : in std_logic;
+ inject_strobe : in std_logic;
+ inject_address : in std_logic_vector(39 downto 0);
+ fecc_crcerr : in std_logic;
+ fecc_eccerr : in std_logic;
+ fecc_eccerrsingle : in std_logic;
+ fecc_syndromevalid : in std_logic;
+ fecc_syndrome : in std_logic_vector(12 downto 0);
+ fecc_far : in std_logic_vector(25 downto 0);
+ fecc_synbit : in std_logic_vector(4 downto 0);
+ fecc_synword : in std_logic_vector(6 downto 0);
+ icap_o : in std_logic_vector(31 downto 0);
+ icap_i : out std_logic_vector(31 downto 0);
+ icap_csib : out std_logic;
+ icap_rdwrb : out std_logic;
+ icap_clk : in std_logic;
+ icap_request : out std_logic;
+ icap_grant : in std_logic
+ );
+ end component;
+
+ component sem_sem_cfg
+ port (
+ fecc_crcerr : out std_logic;
+ fecc_eccerr : out std_logic;
+ fecc_eccerrsingle : out std_logic;
+ fecc_syndromevalid : out std_logic;
+ fecc_syndrome : out std_logic_vector(12 downto 0);
+ fecc_far : out std_logic_vector(25 downto 0);
+ fecc_synbit : out std_logic_vector(4 downto 0);
+ fecc_synword : out std_logic_vector(6 downto 0);
+ icap_o : out std_logic_vector(31 downto 0);
+ icap_i : in std_logic_vector(31 downto 0);
+ icap_clk : in std_logic;
+ icap_csib : in std_logic;
+ icap_rdwrb : in std_logic
+ );
+ end component;
+
+
+ ---------------------------------------------------------------------------
+ -- Declare signals.
+ ---------------------------------------------------------------------------
+ signal fecc_crcerr : std_logic;
+ signal fecc_eccerr : std_logic;
+ signal fecc_eccerrsingle : std_logic;
+ signal fecc_syndromevalid : std_logic;
+ signal fecc_syndrome : std_logic_vector(12 downto 0);
+ signal fecc_far : std_logic_vector(25 downto 0);
+ signal fecc_synbit : std_logic_vector(4 downto 0);
+ signal fecc_synword : std_logic_vector(6 downto 0);
+ signal icap_o : std_logic_vector(31 downto 0);
+ signal icap_i : std_logic_vector(31 downto 0);
+ signal icap_csib : std_logic;
+ signal icap_rdwrb : std_logic;
+ signal icap_unused : std_logic;
+ signal icap_grant : std_logic;
+ signal icap_clk : std_logic;
+
+attribute mark_debug : string;
+-- attribute mark_debug of monitor_rx : signal is "true";
+
+
+ begin
+
+ ---------------------------------------------------------------------------
+ -- This design (the example, including the controller itself) is fully
+ -- synchronous; the global clock buffer is instantiated here to drive
+ -- the icap_clk signal.
+ ---------------------------------------------------------------------------
+
+ example_bufg : BUFGCE
+ port map (
+ I => clk,
+ O => icap_clk,
+ CE => '1'
+ );
+
+ ---------------------------------------------------------------------------
+ -- The controller sub-entity is the kernel of the soft error mitigation
+ -- solution. The port list is dynamic based on the IP core options.
+ ---------------------------------------------------------------------------
+
+ sem_controller : sem
+ port map (
+ status_heartbeat => status_heartbeat,
+ status_initialization => status_initialization,
+ status_observation => status_observation,
+ status_correction => status_correction,
+ status_classification => status_classification,
+ status_injection => status_injection,
+ status_essential => status_essential,
+ status_uncorrectable => status_uncorrectable,
+ monitor_txdata => open,
+ monitor_txwrite => open,
+ monitor_txfull => '0',
+ monitor_rxdata => (others => '0'),
+ monitor_rxread => open,
+ monitor_rxempty => '1',
+ inject_strobe => '0',
+ inject_address => (others => '0'),
+ fecc_crcerr => fecc_crcerr,
+ fecc_eccerr => fecc_eccerr,
+ fecc_eccerrsingle => fecc_eccerrsingle,
+ fecc_syndromevalid => fecc_syndromevalid,
+ fecc_syndrome => fecc_syndrome,
+ fecc_far => fecc_far,
+ fecc_synbit => fecc_synbit,
+ fecc_synword => fecc_synword,
+ icap_o => icap_o,
+ icap_i => icap_i,
+ icap_csib => icap_csib,
+ icap_rdwrb => icap_rdwrb,
+ icap_clk => icap_clk,
+ icap_request => icap_unused,
+ icap_grant => icap_grant
+ );
+
+ icap_grant <= '1';
+
+ ---------------------------------------------------------------------------
+ -- The cfg sub-entity contains the device specific primitives to access
+ -- the internal configuration port and the frame crc/ecc status signals.
+ ---------------------------------------------------------------------------
+
+ sem_cfg : sem_sem_cfg
+ port map (
+ fecc_crcerr => fecc_crcerr,
+ fecc_eccerr => fecc_eccerr,
+ fecc_eccerrsingle => fecc_eccerrsingle,
+ fecc_syndromevalid => fecc_syndromevalid,
+ fecc_syndrome => fecc_syndrome,
+ fecc_far => fecc_far,
+ fecc_synbit => fecc_synbit,
+ fecc_synword => fecc_synword,
+ icap_o => icap_o,
+ icap_i => icap_i,
+ icap_csib => icap_csib,
+ icap_rdwrb => icap_rdwrb,
+ icap_clk => icap_clk
+ );
+
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
USE ieee.std_logic_arith.all;
----------------------------------------------------------------------------------
--- SystemMonitorModule\r
+-- SystemMonitorModule
-- Reads FPGA system parameters: temperature and voltages
--- The Xilinx System Monitor measures several FPGA physical operating parameters.\r
+-- The Xilinx System Monitor measures several FPGA physical operating parameters.
-- For further information see Xilinx documentation
-- The settings and parameters are accessable with a 16-bits data bus and 7 bits address bus.
-- This module initializes the System Monitor so that the main parameters are continuously measured.
--- This behaviour can bechanged because all settings are accessable.\r
---\r
---\r
--- The main settings addresses and their initialize value are:\r
+-- This behaviour can be changed because all settings are accessable.
+--
+--
+-- The main settings addresses and their initialize value are:
-- 0x40 : 1000 -- average 16
-- 0x41 : 2000 -- enable sequence & alarms, no calibration
-- 0x42 : 1400 -- clock division = 20 : 50MHz/2.5MHz
-- 0x48 : 3700 -- select temp,VCCint,VCCaux,VrefP,VrefN
-- 0x49 : 0000 -- not Vaux
-- 0x4a : 3700 -- enable averaging
--- 0x4b : 0000 -- disable averaging Vau\r
--- 0x4c : 0000 -- unipolar inputs\r
--- 0x4d : 0000 -- unipolar inputs\r
--- 0x4e : 0000 -- default Acquisition Time\r
--- 0x4f : 0000 -- default Acquisition Time\r
---\r
---\r
--- The system parameters are measured with an 10 bits ADC:\r
---\r
--- For die Temperature (address 0) :\r
--- Temperature(degreeC) = (ADCcode * 503.975)/1024 - 273.15\r
---\r
--- For VCCint (1V, address=1), VCCaux (2.5V, address=2), VrefP(2.5V, address=4) : \r
--- Supply Voltage (Volts) = (ADCcode / 1024) x 3V\r
---\r
--- For VrefN(0.0V, address=5) :\r
--- Voltage (Volts) = ADCcode(2-complement) * 977uV\r
---\r
+-- 0x4b : 0000 -- disable averaging Vau
+-- 0x4c : 0000 -- unipolar inputs
+-- 0x4d : 0000 -- unipolar inputs
+-- 0x4e : 0000 -- default Acquisition Time
+-- 0x4f : 0000 -- default Acquisition Time
+--
+--
+-- The system parameters are measured with an 10 bits ADC:
+--
+-- For die Temperature (address 0) :
+-- Temperature(degreeC) = (ADCcode * 503.975)/1024 - 273.15
+--
+-- For VCCint (1V, address=1), VCCaux (2.5V, address=2), VrefP(2.5V, address=4) :
+-- Supply Voltage (Volts) = (ADCcode / 1024) x 3V
+--
+-- For VrefN(0.0V, address=5) :
+-- Voltage (Volts) = ADCcode(2-complement) * 977uV
+--
--
--
-- Library:
--
-- Generics:
---\r
+--
-- Inputs:
-- clock : clock for the system monitor (must not exceed 100MHz)
-- reset : reset
Port (
clock : in std_logic;
reset : in std_logic;
- address : in std_logic_vector(6 downto 0);\r
+ address : in std_logic_vector(6 downto 0);
data_write : in std_logic;
- data_in : in std_logic_vector(15 downto 0);\r
- data_read : in std_logic;\r
- data_out : out std_logic_vector(15 downto 0);\r
- alarms : out std_logic_vector(7 downto 0);
- testword0 : out std_logic_vector(35 downto 0));
+ data_in : in std_logic_vector(15 downto 0);
+ data_read : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ alarms : out std_logic_vector(7 downto 0));
end SystemMonitorModule;
architecture Behavioral of SystemMonitorModule is
-component SystemMonitorVirtex\r
- port (\r
- DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port\r
- DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port\r
- DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port\r
- DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port\r
- DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port\r
- RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic\r
- BUSY_OUT : out STD_LOGIC; -- ADC Busy signal\r
- CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs\r
- DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port\r
- DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port\r
- EOC_OUT : out STD_LOGIC; -- End of Conversion Signal\r
- EOS_OUT : out STD_LOGIC; -- End of Sequence Signal\r
- JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal\r
- JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG\r
- JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred\r
- OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output\r
- VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output\r
- VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output\r
- USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output\r
- VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair\r
- VN_IN : in STD_LOGIC\r
-);\r
+component SystemMonitorKintex
+ port (
+ DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port
+ DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
+ DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port
+ DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
+ DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
+ RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic
+ BUSY_OUT : out STD_LOGIC; -- ADC Busy signal
+ CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
+ DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
+ DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
+ EOC_OUT : out STD_LOGIC; -- End of Conversion Signal
+ EOS_OUT : out STD_LOGIC; -- End of Sequence Signal
+ JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal
+ JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG
+ JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred
+ OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output
+ VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output
+ VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output
+ USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output
+ ALARM_OUT : out STD_LOGIC; -- OR'ed output of all the Alarms
+ VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair
+ VN_IN : in STD_LOGIC
+);
end component;
-constant NROFREGISTERS : natural :=11;\r
+
+
+constant NROFREGISTERS : natural :=11;
type registerarray_type is array (0 to NROFREGISTERS-1)
of std_logic_vector (23 downto 0);
-\r
-constant REGISTERARRAY : registerarray_type := (\r
-x"401000", -- average 16\r
+
+constant REGISTERARRAY : registerarray_type := (
+x"401000", -- average 16
x"412000", -- enable sequence & alarms, no calibration
x"421400", -- clock division = 20 : 50MHz/2.5MHz
x"483700", -- select temp,VCCint,VCCaux,VrefP,VrefN
x"490000", -- not Vaux
x"4a3700", -- enable averaging
-x"4b0000", -- disable averaging Vau\r
-x"4c0000", -- unipolar inputs\r
-x"4d0000", -- unipolar inputs\r
-x"4e0000", -- default Acquisition Time\r
-x"4f0000"); -- default Acquisition Time\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
- \r
+x"4b0000", -- disable averaging Vau
+x"4c0000", -- unipolar inputs
+x"4d0000", -- unipolar inputs
+x"4e0000", -- default Acquisition Time
+x"4f0000"); -- default Acquisition Time
+
+
--0x40 : 1000 -- average 16
--0x41 : 2000 -- enable sequence & alarms, no calibration
--0x42 : 1400 -- clock division = 20 : 50MHz/2.5MHz
--0x48 : 3700 -- select temp,VCCint,VCCaux,VrefP,VrefN
--0x49 : 0000 -- not Vaux
--0x4a : 3700 -- enable averaging
---0x4b : 0000 -- disable averaging Vau\r
---0x4c : 0000 -- unipolar inputs\r
---0x4d : 0000 -- unipolar inputs\r
---0x4e : 0000 -- default Acquisition Time\r
---0x4f : 0000 -- default Acquisition Time\r
-\r
-\r
+--0x4b : 0000 -- disable averaging Vau
+--0x4c : 0000 -- unipolar inputs
+--0x4d : 0000 -- unipolar inputs
+--0x4e : 0000 -- default Acquisition Time
+--0x4f : 0000 -- default Acquisition Time
+
+
signal registerindex_S : integer range 0 to NROFREGISTERS;
signal accesscounter_S : integer range 0 to 7;
signal delaycounter_S : std_logic_vector(11 downto 0);
signal DR_address_S : std_logic_vector(6 downto 0);
signal DR_address_init_S : std_logic_vector(6 downto 0);
signal DR_enable_S : std_logic := '0';
-signal DR_data_in_S : std_logic_vector(15 downto 0);\r
-signal DR_data_init_S : std_logic_vector(15 downto 0);\r
+signal DR_data_in_S : std_logic_vector(15 downto 0);
+signal DR_data_init_S : std_logic_vector(15 downto 0);
signal DR_write_S : std_logic := '0';
signal DR_write_init_S : std_logic := '0';
signal VCCaux_alarm_S : std_logic := '0';
signal VCCint_alarm_S : std_logic := '0';
signal USERtemp_alarm_S : std_logic := '0';
-\r
-\r
-
-begin\r
-\r
-\r
-SystemMonitorVirtex1: SystemMonitorVirtex port map ( \r
- DADDR_IN => DR_address_S,\r
- DCLK_IN => clock,\r
- DEN_IN => DR_enable_S,\r
- DI_IN => DR_data_in_S,\r
- DWE_IN => DR_write_S,\r
- RESET_IN => reset,\r
- BUSY_OUT => ADC_busy_S,\r
- CHANNEL_OUT => channel_S,\r
- DO_OUT => DR_data_out_S,\r
- DRDY_OUT => DR_ready_S,\r
- EOC_OUT => EndofConversion_S,\r
- EOS_OUT => EndofSequence_S,\r
- JTAGBUSY_OUT => open,\r
- JTAGLOCKED_OUT => open,\r
- JTAGMODIFIED_OUT => open,\r
- OT_OUT => OverTemperatur_alarm_S,\r
- VCCAUX_ALARM_OUT => VCCaux_alarm_S,\r
- VCCINT_ALARM_OUT => VCCint_alarm_S,\r
- USER_TEMP_ALARM_OUT => USERtemp_alarm_S,\r
- VP_IN => '0',\r
- VN_IN => '0'\r
- );\r
-\r
-alarms(3 downto 0) <= OverTemperatur_alarm_S & VCCaux_alarm_S & VCCint_alarm_S & USERtemp_alarm_S;\r
-alarms(7 downto 4) <= (others => '0');\r
-\r
-DR_address_S <= DR_address_init_S when sysmon_active_S='0' else address;\r
-DR_enable_S <= '1' when ((data_read='1') and (sysmon_active_S='1')) or (DR_write_S='1') else '0';\r
-data_out <= DR_data_out_S;\r
-\r
-DR_write_S <= '1' when ((data_write='1') and (sysmon_active_S='1')) or (DR_write_init_S='1') else '0';\r
-DR_data_in_S <= data_in when (sysmon_active_S='1') else DR_data_init_S;\r
-\r
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of DR_data_out_S : signal is "true";
+-- attribute mark_debug of DR_address_S : signal is "true";
+-- attribute mark_debug of sysmon_active_S : signal is "true";
+-- attribute mark_debug of DR_enable_S : signal is "true";
+-- attribute mark_debug of ADC_busy_S : signal is "true";
+-- attribute mark_debug of DR_ready_S : signal is "true";
+-- attribute mark_debug of EndofConversion_S : signal is "true";
+-- attribute mark_debug of EndofSequence_S : signal is "true";
+-- attribute mark_debug of channel_S : signal is "true";
+
+begin
+
+
+SystemMonitorKintex1: SystemMonitorKintex port map (
+ DADDR_IN => DR_address_S,
+ DCLK_IN => clock,
+ DEN_IN => DR_enable_S,
+ DI_IN => DR_data_in_S,
+ DWE_IN => DR_write_S,
+ RESET_IN => reset,
+ BUSY_OUT => ADC_busy_S,
+ CHANNEL_OUT => channel_S,
+ DO_OUT => DR_data_out_S,
+ DRDY_OUT => DR_ready_S,
+ EOC_OUT => EndofConversion_S,
+ EOS_OUT => EndofSequence_S,
+ JTAGBUSY_OUT => open,
+ JTAGLOCKED_OUT => open,
+ JTAGMODIFIED_OUT => open,
+ OT_OUT => OverTemperatur_alarm_S,
+ VCCAUX_ALARM_OUT => VCCaux_alarm_S,
+ VCCINT_ALARM_OUT => VCCint_alarm_S,
+ ALARM_OUT => open,
+ USER_TEMP_ALARM_OUT => USERtemp_alarm_S,
+ VP_IN => '0',
+ VN_IN => '0'
+ );
+
+alarms(3 downto 0) <= OverTemperatur_alarm_S & VCCaux_alarm_S & VCCint_alarm_S & USERtemp_alarm_S;
+alarms(7 downto 4) <= (others => '0');
+
+DR_address_S <= DR_address_init_S when sysmon_active_S='0' else address;
+DR_enable_S <= '1' when ((data_read='1') and (sysmon_active_S='1')) or (DR_write_S='1') else '0';
+data_out <= DR_data_out_S;
+
+DR_write_S <= '1' when ((data_write='1') and (sysmon_active_S='1')) or (DR_write_init_S='1') else '0';
+DR_data_in_S <= data_in when (sysmon_active_S='1') else DR_data_init_S;
+
process(clock)
begin
if (rising_edge(clock)) then
- if (reset = '1') and (sysmon_active_S='1') then \r
- DR_write_init_S <= '0';\r
- sysmon_active_S <= '0';\r
- registerindex_S <= 0;\r
- accesscounter_S <= 0;\r
+ if (reset = '1') and (sysmon_active_S='1') then
+ DR_write_init_S <= '0';
+ sysmon_active_S <= '0';
+ registerindex_S <= 0;
+ accesscounter_S <= 0;
delaycounter_S <= (others => '0');
- else\r
- if sysmon_active_S='0' then\r
- if delaycounter_S(delaycounter_S'left)='0' then \r
- delaycounter_S <= delaycounter_S+1;\r
- DR_write_init_S <= '0';\r
- registerindex_S <= 0;\r
- accesscounter_S <= 0;\r
- DR_address_init_S <= (others => '0');\r
- else\r
- if accesscounter_S<7 then\r
- if accesscounter_S=0 then\r
- DR_address_init_S <= REGISTERARRAY(registerindex_S)(22 downto 16);\r
- DR_data_init_S <= REGISTERARRAY(registerindex_S)(15 downto 0);\r
- DR_write_init_S <= '1';\r
- else\r
- DR_write_init_S <= '0';\r
- end if;\r
- accesscounter_S <= accesscounter_S+1;\r
- else\r
- accesscounter_S <= 0;\r
- DR_write_init_S <= '0';\r
- if registerindex_S<NROFREGISTERS then\r
- registerindex_S <= registerindex_S+1;\r
- else\r
- DR_address_init_S <= (others => '0');\r
- DR_data_init_S <= (others => '0');\r
- registerindex_S <= 0;\r
- sysmon_active_S <= '1';\r
- end if;\r
- end if;\r
- end if;\r
- else\r
- accesscounter_S <= 0;\r
- DR_write_init_S <= '0';\r
- end if;\r
+ DR_address_init_S <= (others => '0');
+ DR_data_init_S <= (others => '0');
+ else
+ if sysmon_active_S='0' then
+ if delaycounter_S(delaycounter_S'left)='0' then
+ delaycounter_S <= delaycounter_S+1;
+ DR_write_init_S <= '0';
+ registerindex_S <= 0;
+ accesscounter_S <= 0;
+ DR_address_init_S <= (others => '0');
+ else
+ if accesscounter_S<7 then
+ if accesscounter_S=0 then
+ DR_address_init_S <= REGISTERARRAY(registerindex_S)(22 downto 16);
+ DR_data_init_S <= REGISTERARRAY(registerindex_S)(15 downto 0);
+ DR_write_init_S <= '1';
+ else
+ DR_write_init_S <= '0';
+ end if;
+ accesscounter_S <= accesscounter_S+1;
+ else
+ accesscounter_S <= 0;
+ DR_write_init_S <= '0';
+ if registerindex_S<NROFREGISTERS then
+ registerindex_S <= registerindex_S+1;
+ else
+ DR_address_init_S <= (others => '0');
+ DR_data_init_S <= (others => '0');
+ registerindex_S <= 0;
+ sysmon_active_S <= '1';
+ end if;
+ end if;
+ end if;
+ else
+ accesscounter_S <= 0;
+ DR_write_init_S <= '0';
+ end if;
end if;
end if;
end process;
-testword0(15 downto 0) <= DR_data_out_S;
-testword0(22 downto 16) <= DR_address_S;
-testword0(23) <= sysmon_active_S;
-testword0(24) <= '0';
-testword0(25) <= DR_enable_S;
-testword0(26) <= ADC_busy_S;
-testword0(27) <= DR_ready_S;
-testword0(28) <= EndofConversion_S;
-testword0(29) <= EndofSequence_S;
-testword0(30) <= '1' when OverTemperatur_alarm_S='1' or VCCaux_alarm_S='1' or VCCint_alarm_S='1' or USERtemp_alarm_S='1' else '0';
-testword0(35 downto 31) <= channel_S;
-
end Behavioral;
--- /dev/null
+---------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 9-10-2012
+-- Module Name: TMP104module
+-- Description: Module to access TMP104 temperature sensor
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- TMP104module
+-- Module to access TMP104 temperature sensor with smaart interface:
+-- Serial connection with baudrate from 4.8 to 114 kbps
+-- startbit=0, stopbit=1
+-- first byte : calibrate = 0x55
+-- second byte : command
+-- third byte (after 1 wait cycle) : data, receive or send
+--
+-- sequence:
+-- startbit=0 1 0 1 0 1 0 1 0 stopbit=1 startbit=0 p0 p1 p2 p3 p4 p5 p6 p7 stopbit=1
+-- wait=1 startbit=0 d0 d1 d2 d3 d4 d5 d6 d7 stopbit=1
+--
+-- TMP104:
+-- d<7..0> : data (receive or send)
+-- p0 = R/W
+-- p2,p1 = 00=read temp, 01=configuration, 10=low temperature, 11= high temperature
+-- p6..p3 = in/id : 0000
+-- p7 = GLB : global command
+--
+--
+-- Library:
+--
+-- Generics:
+-- TMP104CLOCKDIVIDER : number of clockcycles for 1 smaart bit (defines baudrate)
+-- TMP104INTERVAL : number of smaart clock cycles between temperature measurements
+--
+-- Inputs:
+-- clock : clock input
+-- reset : synchronous reset
+-- smaart_in : smaart serial data from TMP01
+--
+-- Outputs:
+-- smaart_out : smaart serial data to TMP01
+-- temperature : measured temperature in binary twos complement format, range -55 to +127 degree C
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity TMP104module is
+ generic (
+ TMP104CLOCKDIVIDER : natural := 1628;
+ TMP104INTERVAL : natural := 50
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ smaart_in : in std_logic;
+ smaart_out : out std_logic;
+ temperature : out std_logic_vector (7 downto 0)
+ );
+end TMP104module;
+
+architecture Behavioral of TMP104module is
+
+
+constant BYTE_CALIBRATE : std_logic_vector(7 downto 0) := "01010101";
+constant CMD_INITIALIZE : std_logic_vector(7 downto 0) := "10001100";
+constant CMD_ASSIGN : std_logic_vector(7 downto 0) := "10010000";
+constant CMD_CLEARINTERRUPT : std_logic_vector(7 downto 0) := "10101001";
+constant CMD_RESET : std_logic_vector(7 downto 0) := "10110100";
+constant CMD_READTEMPERATURE : std_logic_vector(7 downto 0) := "00000001";
+
+
+type command_state_type is (RST,INIT,WAITREADY,ASSIGN,GETTEMPERATURE);
+signal command_state_S : command_state_type := INIT;
+signal return_state_S : command_state_type := INIT;
+
+type smaart_state_type is (WAIT0,START0,CALIBRATE,STOP0,START1,COMMAND,STOP1,WAIT1,START2,DATA,STOP2);
+signal smaart_state_S : smaart_state_type := WAIT0;
+
+signal clockdivcounter_S : integer range 0 to TMP104CLOCKDIVIDER := 0;
+signal clockdiv_full_S : std_logic := '0';
+signal clockdiv_half_S : std_logic := '0';
+signal clockdivphase_S : std_logic := '0';
+
+signal command_counter_S : integer range 0 to TMP104INTERVAL := 0;
+signal bitcounter_S : integer range 0 to 7 := 0;
+signal command_S : std_logic_vector (7 downto 0) := x"00";
+signal senddata_S : std_logic_vector (7 downto 0) := x"02";
+signal receivedata_S : std_logic_vector (7 downto 0) := x"00";
+signal start_smaart_s : std_logic := '0';
+signal smaart_out_S : std_logic := '1';
+constant TMP104CLOCKDIVIDERdiv2 : integer range 0 to TMP104CLOCKDIVIDER := TMP104CLOCKDIVIDER/2;
+begin
+
+smaart_out <= smaart_out_S;
+
+clockdiv_process: process(clock)
+begin
+ if (rising_edge(clock)) then
+ if clockdivcounter_S<TMP104CLOCKDIVIDERdiv2-1 then
+ clockdivcounter_S <= clockdivcounter_S+1;
+ clockdiv_full_S <= '0';
+ clockdiv_half_S <= '0';
+ else
+ clockdivcounter_S <= 0;
+ if clockdivphase_S='0' then
+ clockdiv_full_S <= '1';
+ clockdiv_half_S <= '0';
+ clockdivphase_S <= '1';
+ else
+ clockdiv_full_S <= '0';
+ clockdiv_half_S <= '1';
+ clockdivphase_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+command_process: process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ command_counter_S <= 0;
+ start_smaart_S <= '0';
+ command_state_S <= INIT;
+ else
+ if clockdiv_full_S='1' then
+ case command_state_S is
+ when RST =>
+ if command_counter_S<TMP104INTERVAL-1 then
+ start_smaart_S <= '0';
+ command_counter_S <= command_counter_S+1;
+ else
+ start_smaart_S <= '1';
+ command_counter_S <= 0;
+ command_S <= CMD_RESET;
+ command_state_S <= WAITREADY;
+ return_state_S <= INIT;
+ end if;
+ when INIT =>
+ if command_counter_S<TMP104INTERVAL-1 then
+ start_smaart_S <= '0';
+ command_counter_S <= command_counter_S+1;
+ else
+ start_smaart_S <= '1';
+ command_counter_S <= 0;
+ command_S <= CMD_INITIALIZE;
+ command_state_S <= WAITREADY;
+ return_state_S <= ASSIGN;
+ end if;
+ when ASSIGN =>
+ if command_counter_S<TMP104INTERVAL-1 then
+ start_smaart_S <= '0';
+ command_counter_S <= command_counter_S+1;
+ else
+ start_smaart_S <= '1';
+ command_counter_S <= 0;
+ command_S <= CMD_ASSIGN;
+ command_state_S <= WAITREADY;
+ return_state_S <= GETTEMPERATURE;
+ end if;
+ when WAITREADY =>
+ start_smaart_S <= '0';
+ command_counter_S <= 0;
+ if smaart_state_S=WAIT0 then
+ command_state_S <= return_state_S;
+ end if;
+ when GETTEMPERATURE =>
+ if command_counter_S=0 then
+ temperature <= receivedata_S;
+ end if;
+ if command_counter_S<TMP104INTERVAL-1 then
+ start_smaart_S <= '0';
+ command_counter_S <= command_counter_S+1;
+ else
+ start_smaart_S <= '1';
+ command_counter_S <= 0;
+ command_S <= CMD_READTEMPERATURE;
+ command_state_S <= WAITREADY;
+ return_state_S <= GETTEMPERATURE;
+ end if;
+ when others =>
+ start_smaart_S <= '0';
+ command_counter_S <= 0;
+ command_state_S <= INIT;
+ end case;
+ else
+ start_smaart_S <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+smaart_process: process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ smaart_out_S <= '1';
+ bitcounter_S <= 0;
+ smaart_state_S <= WAIT0;
+ else
+ if (clockdiv_full_S='1') and ((smaart_state_S=DATA) or (smaart_state_S=STOP2)) then
+ if (smaart_state_S=STOP2) then
+ receivedata_S(7) <= smaart_in;
+ elsif (bitcounter_S>0) then
+ receivedata_S(bitcounter_S-1) <= smaart_in;
+ end if;
+ end if;
+ if start_smaart_S='1' then
+ smaart_out_S <= '1';
+ bitcounter_S <= 0;
+ smaart_state_S <= START0;
+ elsif clockdiv_full_S='1' then
+ case smaart_state_S is
+ when WAIT0 =>
+ smaart_out_S <= '1';
+ bitcounter_S <= 0;
+ smaart_state_S <= WAIT0;
+ when START0 =>
+ smaart_out_S <= '0';
+ bitcounter_S <= 0;
+ smaart_state_S <= CALIBRATE;
+ when CALIBRATE =>
+ smaart_out_S <= BYTE_CALIBRATE(bitcounter_S);
+ if bitcounter_S<7 then
+ bitcounter_S <= bitcounter_S+1;
+ else
+ bitcounter_S <= 0;
+ smaart_state_S <= STOP0;
+ end if;
+ when STOP0 =>
+ smaart_out_S <= '1';
+ bitcounter_S <= 0;
+ smaart_state_S <= START1;
+ when START1 =>
+ smaart_out_S <= '0';
+ bitcounter_S <= 0;
+ smaart_state_S <= COMMAND;
+ when COMMAND =>
+ smaart_out_S <= command_S(bitcounter_S);
+ if bitcounter_S<7 then
+ bitcounter_S <= bitcounter_S+1;
+ else
+ bitcounter_S <= 0;
+ smaart_state_S <= STOP1;
+ end if;
+ when STOP1 =>
+ smaart_out_S <= '1';
+ bitcounter_S <= 0;
+ smaart_state_S <= WAIT1;
+ when WAIT1 =>
+ smaart_out_S <= '1';
+ bitcounter_S <= 0;
+ smaart_state_S <= START2;
+ when START2 =>
+ if (command_S(0)='1') or (command_S(7)='1') then -- init or read
+ smaart_out_S <= '1';
+ else
+ smaart_out_S <= '0';
+ end if;
+ bitcounter_S <= 0;
+ smaart_state_S <= DATA;
+ when DATA =>
+ if (command_S(0)='1') or (command_S(7)='1') then -- init or read
+ smaart_out_S <= '1';
+ else
+ smaart_out_S <= senddata_S(bitcounter_S);
+ end if;
+ if bitcounter_S<7 then
+ bitcounter_S <= bitcounter_S+1;
+ else
+ bitcounter_S <= 0;
+ smaart_state_S <= STOP2;
+ end if;
+ when STOP2 =>
+ smaart_out_S <= '1';
+ bitcounter_S <= 0;
+ smaart_state_S <= WAIT0;
+ when others =>
+ smaart_out_S <= '1';
+ bitcounter_S <= 0;
+ smaart_state_S <= WAIT0;
+ end case;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI-cart/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 2008, 22-04-2015
+-- Module Name: FEE_MWDfilter_unsigned
+-- Description: Moving Window Deconvolution filter for unsigned signals
+-- Modifications:
+-- 23-04-2015 offset added
+-- 24-04-2015 signed output added
+-- 30-04-2015 unsigned output added
+-- 28-02-2017 decrease output bits
+-- 08-03-2017 width of the MWD input changed to width+1 for less resources
+-- 05-04-2017 rewritten in std_logic_vector instead of integers
+----------------------------------------------------------------------------------
+
+------------------------------------------------------------------------------------------------------
+-- FEE_MWDfilter_unsigned
+-- Moving Window Deconvolution filter for unsigned signals.
+-- Formula:
+-- N(k) = A(k) - A(k-w) + 1/T * sum(A(k-1)..A(k-w))
+-- k : index in ADC data stream
+-- N(k) : Output value
+-- A(k) : new ADC value
+-- A(k-w) : old ADC value (w samples before)
+-- w : Width of window
+-- T : Tau = exponential decay time constant to compensate for
+-- sum(A(k-1)..A(k-w)) : summation of w ADC values
+--
+-- generics
+-- MWD_DATABITS : number of ADC bits
+-- MWD_WIDTHBITS : number of bits for the width
+-- MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data_in : ADC sampling data, signed
+-- MWD_width : width plus 1 of the MWD filter
+-- MWD_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq)
+--
+-- outputs
+-- data_out_signed : signed MWD data output, width depends on MWD_WIDTHBITS
+-- data_out_unsigned : unsigned MWD data output (half of the range is added), width depends on MWD_WIDTHBITS
+--
+-- components
+-- shift_register : shift register for std_logic_vector
+--
+------------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_SIGNED.ALL;
+
+entity FEE_MWDfilter_unsigned is
+ generic (
+ MWD_DATABITS : natural := 14;
+ MWD_WIDTHBITS : natural := 8;
+ MWD_SCALEBITS : natural := 15
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector((MWD_DATABITS-1) downto 0);
+ MWD_width : in std_logic_vector((MWD_WIDTHBITS-1) downto 0);
+ MWD_tau_factor : in std_logic_vector((MWD_SCALEBITS-1) downto 0);
+ data_out_signed : out std_logic_vector(MWD_DATABITS downto 0);
+ data_out_unsigned : out std_logic_vector(MWD_DATABITS downto 0));
+end FEE_MWDfilter_unsigned;
+
+architecture Behavioral of FEE_MWDfilter_unsigned is
+
+component shift_register_small is
+ generic (
+ width : natural := MWD_DATABITS;
+ depthbits : natural := MWD_WIDTHBITS
+ );
+ port (
+ clock : in std_logic;
+ data_in : in std_logic_vector((width-1) downto 0);
+ depth : in std_logic_vector((depthbits-1) downto 0);
+ data_out : out std_logic_vector((width-1) downto 0));
+end component;
+
+constant ZEROS : std_logic_vector(63 downto 0) := (others => '0');
+constant ONES : std_logic_vector(63 downto 0) := (others => '1');
+
+signal initializing_S : std_logic := '1';
+signal MWD_disable_S : std_logic := '1';
+
+signal resetcounter_S : std_logic_vector(MWD_WIDTHBITS+2 downto 0);
+signal MWD_width_S : std_logic_vector(MWD_WIDTHBITS-1 downto 0);
+signal data_in_signed_S : std_logic_vector(MWD_DATABITS downto 0);
+signal shiftregin_S : std_logic_vector(MWD_DATABITS-1 downto 0);
+signal data_in_delayed_S : std_logic_vector(MWD_DATABITS-1 downto 0);
+signal data_in_delayed0_S : std_logic_vector(MWD_DATABITS-1 downto 0);
+signal MWD_tau_factor_S : std_logic_vector(MWD_SCALEBITS downto 0);
+signal summated_samples_S : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+
+signal data_out_S : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0) := (others => '0'); -- signed
+signal data_out_scaled_S : std_logic_vector(MWD_DATABITS downto 0) := (others => '0'); -- signed
+
+signal mult_S : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0) := (others => '0'); -- signed
+signal add_S : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0) := (others => '0'); -- signed
+signal data_in_signed1_S : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+
+attribute mark_debug : string;
+attribute mark_debug of reset : signal is "true";
+attribute mark_debug of MWD_disable_S : signal is "true";
+attribute mark_debug of initializing_S : signal is "true";
+--attribute mark_debug of resetcounter_S : signal is "true";
+--attribute mark_debug of shiftregin_S : signal is "true";
+--attribute mark_debug of data_in_delayed_S : signal is "true";
+--attribute mark_debug of summated_samples_S : signal is "true";
+--attribute mark_debug of data_out_S : signal is "true";
+
+begin
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if (reset='1') or (MWD_width_S/=MWD_width) or (MWD_width_S=ZEROS(MWD_WIDTHBITS-1 downto 0)) then
+ MWD_disable_S <= '1';
+ else
+ MWD_disable_S <= '0';
+ end if;
+ MWD_width_S <= MWD_width;
+ end if;
+end process;
+
+data_in_signed_S <= ('0' & data_in)-conv_std_logic_vector(2**(MWD_DATABITS-1),MWD_DATABITS+1);
+shiftregin_S <= (others => '0') when (initializing_S='1') or (MWD_disable_S='1') else data_in_signed_S(MWD_DATABITS-1 downto 0);
+gen_shiftreg2: if MWD_WIDTHBITS>1 generate
+shift_register_MWD: shift_register_small
+ generic map(
+ width => MWD_DATABITS,
+ depthbits => MWD_WIDTHBITS)
+ port map(
+ clock => clock,
+ data_in => shiftregin_S,
+ depth => MWD_width_S,
+ data_out => data_in_delayed_S);
+end generate;
+gen_noshiftreg2: if MWD_WIDTHBITS<=1 generate
+-- shift_register_MWD: shift_register_small
+ -- generic map(
+ -- width => MWD_DATABITS,
+ -- depthbits => 2)
+ -- port map(
+ -- clock => clock,
+ -- data_in => shiftregin_S,
+ -- depth => "01",
+ -- data_out => data_in_delayed_S);
+ process(clock)
+ begin
+ if rising_edge(clock) then
+ data_in_delayed_S <= data_in_delayed0_S;
+ data_in_delayed0_S <= shiftregin_S;
+ end if;
+ end process;
+end generate;
+
+data_out_signed <= data_out_scaled_S;
+data_out_scaled_S <=
+ (MWD_DATABITS => '1', others => '0') when conv_integer(signed(data_out_S))<-2**MWD_DATABITS else
+ (MWD_DATABITS => '0', others => '1') when conv_integer(signed(data_out_S))>=2**MWD_DATABITS else
+ data_out_S(MWD_DATABITS downto 0);
+
+--data_out_unsigned <= conv_std_logic_vector(conv_integer(signed(data_out_S))+2**(MWD_DATABITS+MWD_WIDTHBITS),MWD_DATABITS+MWD_WIDTHBITS+2)(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+data_out_unsigned <= conv_std_logic_vector(conv_integer(signed(data_out_scaled_S))+2**MWD_DATABITS,MWD_DATABITS+2)(MWD_DATABITS downto 0);
+
+-- process(clock)
+-- variable shiftregin_V : integer range -2**(MWD_DATABITS-1) to 2**(MWD_DATABITS-1)-1;
+-- variable data_in_delayed_V : integer range -2**(MWD_DATABITS-1) to 2**(MWD_DATABITS-1)-1;
+-- variable bdiff_V : integer range -2**MWD_DATABITS to 2**MWD_DATABITS-1;
+-- variable multiplied_V : std_logic_vector(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS-1 downto 0); -- signed
+-- variable multiplied_scaledback_V : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS-1 downto 0); -- signed
+-- begin
+ -- if rising_edge(clock) then
+ -- shiftregin_V := conv_integer(signed(shiftregin_S));
+ -- data_in_delayed_V := conv_integer(signed(data_in_delayed_S));
+ -- bdiff_V := shiftregin_V - data_in_delayed_V;
+ -- multiplied_V := conv_std_logic_vector(conv_integer(signed('0' & MWD_tau_factor_S)) * summated_samples_S,MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS); -- signed multiply : MWD_SCALEBITS + MWD_WIDTHBITS + MWD_WIDTHBITS
+ -- multiplied_scaledback_V := multiplied_V(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS-1 downto MWD_SCALEBITS);
+
+ -- if MWD_disable_S='1' then
+ -- data_out_S <= conv_std_logic_vector(conv_integer(signed(data_in_signed_S)),MWD_DATABITS+MWD_WIDTHBITS+1);
+ -- resetcounter_S <= (others => '0');
+ -- initializing_S <= '1';
+ -- summated_samples_S <= 0;
+ -- elsif initializing_S='1' then
+ -- if resetcounter_S(resetcounter_S'left-1)='0' then
+ -- resetcounter_S <= resetcounter_S+1;
+ -- else
+ -- initializing_S <= '0';
+ -- end if;
+ -- summated_samples_S <= 0;
+ -- else
+ -- if resetcounter_S(resetcounter_S'left)='0' then
+ -- resetcounter_S <= resetcounter_S+1;
+ -- else
+ -- data_out_S <= conv_std_logic_vector(bdiff_V + conv_integer(signed(multiplied_scaledback_V)),MWD_DATABITS+MWD_WIDTHBITS+1); -- signed
+ -- end if;
+ -- summated_samples_S <= (summated_samples_S+shiftregin_V)-data_in_delayed_V;
+ -- end if;
+ -- end if;
+-- end process;
+MWD_tau_factor_S <= '0' & MWD_tau_factor;
+
+
+-- process(clock)
+-- begin
+ -- if rising_edge(clock) then
+ -- if (MWD_disable_S='1') or (reset='1') then
+ -- data_out_S <= conv_std_logic_vector(conv_integer(signed(data_in_signed_S)),MWD_DATABITS+MWD_WIDTHBITS+1);
+ -- resetcounter_S <= (others => '0');
+ -- initializing_S <= '1';
+ -- summated_samples_S <= 0;
+ -- elsif initializing_S='1' then
+ -- if resetcounter_S(resetcounter_S'left-1)='0' then
+ -- resetcounter_S <= resetcounter_S+1;
+ -- else
+ -- initializing_S <= '0';
+ -- end if;
+ -- summated_samples_S <= 0;
+ -- else
+ -- if resetcounter_S(resetcounter_S'left)='0' then
+ -- resetcounter_S <= resetcounter_S+1;
+ -- else
+ -- data_out_S <= conv_std_logic_vector((conv_integer(signed(shiftregin_S)) - conv_integer(signed(data_in_delayed_S))) +
+ -- conv_integer(signed(conv_std_logic_vector(conv_integer(signed('0' & MWD_tau_factor_S)) * summated_samples_S,MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS)(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS-1 downto MWD_SCALEBITS))),MWD_DATABITS+MWD_WIDTHBITS+1); -- signed
+ -- end if;
+ -- summated_samples_S <= (summated_samples_S+conv_integer(signed(shiftregin_S)))-conv_integer(signed(data_in_delayed_S));
+ -- end if;
+ -- end if;
+-- end process;
+
+data_out_S <= add_S + mult_S when initializing_S='0' else data_in_signed1_S;
+
+data_in_signed1_S(MWD_DATABITS+MWD_WIDTHBITS downto MWD_DATABITS) <= (others => data_in_signed_S(MWD_DATABITS-1));
+data_in_signed1_S(MWD_DATABITS-1 downto 0) <= data_in_signed_S(MWD_DATABITS-1 downto 0);
+
+
+process(clock)
+variable mult_V : std_logic_vector(MWD_SCALEBITS+1+MWD_DATABITS+MWD_WIDTHBITS+1-1 downto 0);
+variable shiftregin_V : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+variable data_in_delayed_V : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+begin
+ if rising_edge(clock) then
+ if (MWD_disable_S='1') or (reset='1') then
+-- data_out_S <= (others => '0');
+-- data_out_S(MWD_DATABITS-1 downto 0) <= data_in_signed_S(MWD_DATABITS-1 downto 0);
+ resetcounter_S <= (others => '0');
+ initializing_S <= '1';
+ summated_samples_S <= (others => '0');
+ elsif initializing_S='1' then
+ if resetcounter_S(resetcounter_S'left-1)='0' then
+ resetcounter_S <= resetcounter_S+1;
+ else
+ initializing_S <= '0';
+ end if;
+ summated_samples_S <= (others => '0');
+ else
+ if resetcounter_S(resetcounter_S'left)='0' then
+ resetcounter_S <= resetcounter_S+1;
+ else
+ mult_V := MWD_tau_factor_S * summated_samples_S;
+ mult_S <= mult_V(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS downto MWD_SCALEBITS);
+ shiftregin_V(MWD_DATABITS+MWD_WIDTHBITS downto MWD_DATABITS) := (others => shiftregin_S(MWD_DATABITS-1));
+ shiftregin_V(MWD_DATABITS-1 downto 0) := shiftregin_S;
+ data_in_delayed_V(MWD_DATABITS+MWD_WIDTHBITS downto MWD_DATABITS) := (others => data_in_delayed_S(MWD_DATABITS-1));
+ data_in_delayed_V(MWD_DATABITS-1 downto 0) := data_in_delayed_S;
+ add_S <= shiftregin_V - data_in_delayed_V;
+-- data_out_S <= (shiftregin_S + mult_V(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS downto MWD_SCALEBITS)) - data_in_delayed_S;
+ end if;
+ summated_samples_S <= (summated_samples_S+shiftregin_S)-data_in_delayed_S;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
clockdiv5 <= clockdiv5_S;
rxrecclk_bufrdiv5_i : BUFR
- generic map ( BUFR_DIVIDE => "5" )
+ generic map ( \r
+ BUFR_DIVIDE => "5",\r
+ SIM_DEVICE => "VIRTEX6")
port map (
CE => '1',
CLR => clockdiv5_reset_S,
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 15-02-2012
-- Module Name: FEE_adc32_module
-- 02-10-2014 onesecondpulse, errorbyte
-- 10-10-2014 Integral as measurement for the energy instead of maximum
-- 16-10-2014 inpipe signals
+-- 24-04-2015 Moving Window Deconvolution added
+-- 19-08-2015 Force_hit added: force waveform acquisition with SODA command
+-- 06-10-2015 Invert ADCs bit added
+-- 05-11-2015 Data errorbit added
+-- 28-10-2016 Enable_waveform to FEE_pulse_and_pileup_waveforms
+-- 23-02-2017 Parallel data from Feature Extraction instead of 36-bits, MWD registers in FE
+-- 05-04-2017 Second Feature Extraction module for detecting errors due to radiation
----------------------------------------------------------------------------------
library IEEE;
----------------------------------------------------------------------------------
-- FEE_adc32_module\r
-- Module for Front End Electronics: fiber connection, adc waveform reading & multiplexers & feature extraction.\r
--- ADC data is analysed or put in waveforms if regarded as pileup. \r
+-- ADC data is analysed or put in waveforms. \r
--
-- The data is sent to the GTP/GTX transceiver in packets\r
-- Slow control processes slow-control packets on the fiber to/from the multiplexer board.\r
-- bit3: enable waveforms
-- bit 17..16 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read
-- bit 18 = reset/initializes FPGA System monitor
--- board_register B: read\r
+-- board_register B: \r
+-- read\r
-- bit1 : Data Taken enabled (enable and disabled is done with SODA packets)
-- bit 5..4 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare
-- bit 15..6 = ADC value from FPGA System monitor
-- bit20 : error : transmit data error, multiplexer error
-- bit21 : error : receive data buffer overrun
-- bit22 : error : adc data buffer overrun
--- bit23 : error : data taken disabled
+-- bit23 : error : data taken disabled\r
-- board_register C: automatically sent
-- data not important; this slowcontrol command indicates buffer full
-- board_register D: read
--\r
-- Each ADC has its own set of registers. See module FEE_pulse_and_pileup_waveforms for addresses.\r
--
+-- The resulting output data packets : 4 32-bit words, with CRC8 in last word
+-- 0xDA ADCnumber(7..0) superburstnumber(15..0)
+-- timestamp(15..0) energy(15..0)
+-- CF_before(15..0) CF_after(15..0)
+-- 0000 statusbyte(7..0) CRC8(7..0)
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+-- 0x5C address(7..0) replybit 0000000 data(31..24)
+-- data(23..0) CRC8(7..0)
+--
+-- The waveform packets : 32-bit words, with CRC8 in last word
+-- 0xAF ADCnumber(7..0) superburstnumber(15..0)
+-- timestamp(15..0) 0x00 statusbyte(7..0)
+-- 0 adc0(14..0) 0 adc1(14..0) : 2 adc-samples 15 bits signed
+-- 0 adc2(14..0) 0 adc3(14..0) : next 2 adc-samples 15 bits signed
+-- .........
+-- 1 adcn(14..0) 1 00 CRC8(7..0) : last 32-bit word: last adc-sample 15 bits signed
+-- or
+-- 0 0000 1 00 CRC8(7..0) : last 32-bit word: no sample--
--
--
-- Library
-- work.panda_package : for type declarations and constants
--
-- Generics:
--- NROFADCS : number of the adc's, probably 16
--- ADCBITS : number of ADC-bits
--- BASELINE_BWBITS : number of bits for the baseline IIR filter bandwidth
--- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size\r
--- ADCCLOCKFREQUENCY : Frequency of the ADCclock in Hz
--- CF_DELAYBITS : number of bits for the constant fraction delay
--- CF_FRACTIONBIT : number of bits for the calculated fraction of the precise timestamp
--- IDIVMAXBITS : number of bits for maximum to integral ratio check
--- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+-- NROFADCS : number of the adc's, probably 16
+-- ADCBITS : number of ADC-bits
+-- MWD_WIDTHBITS : number of bits for the width
+-- MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations
+-- MWD2_WIDTHBITS : number of bits for the width of second MWD
+-- MWD2_SCALEBITS : number of bits for tau factor for second MWD, also scaling for calculations
+-- MWD_DOUBLEFILTER : two MWD filters in series for single pulses
+-- MWD_PU_DOUBLEFILTER : two MWD filters in series for pileup
+-- BASELINE_BWBITS : number of bits for the baseline IIR filter bandwidth
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size\r
+-- ADCCLOCKFREQUENCY : Frequency of the ADCclock in Hz
+-- CF_DELAYBITS : number of bits for the constant fraction delay
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+-- MAXPILEUPHITS : maximum number of hits in one pileup waveform
+-- SECOND_FE_MODULE : Second Feature Extraction module for detecting errors due to radiation
--
-- Inputs:
--- clock : clock for everything
--- reset : reset all\r
--- enable_data : enable data, controlled by SODA\r
--- ADCdata : parallel sampling adc data
--- rxNotInTable : error in received fiber data, used for status\r
--- superburst_start : Signal to indicate start of new superburst, received (back) from pin\r
--- superburst_received : superburstnumber
--- startupready : startup procedure is finished: ready to send data
--- request_init : send a request to the DC to initialize all registers
--- packet_in_data : 32 bits data input from fiber module\r
--- packet_in_present : data available from fiber module\r
--- packet_out_fifofull : connected fifo for packet data is full
--- errorbyte_in : errors occurred for slow control reply\r
--- smaart_in : serial input from external TMP104 sensor
--- sysmon_data : data from the FPGA system monitor module\r
+-- clock : clock for everything
+-- reset : reset all\r
+-- enable_data : enable data, controlled by SODA\r
+-- GEO : FPGA identification: 0:this is FPGA1, 1:this is FPGA2
+-- ADCdata : parallel sampling adc data
+-- superburst_start : Signal to indicate start of new superburst, received (back) from pin\r
+-- superburst_received : superburstnumber\r
+-- force_hit : force hit at input
+-- onesecondpulse : pulse per second for frequency measurement
+-- rxNotInTable : error in received fiber data, used for status\r
+-- startupready : startup procedure is finished: ready to send data
+-- request_init : send a request to the DC to initialize all registers
+-- packet_in_data : 32 bits data input from fiber module\r
+-- packet_in_present : data available from fiber module\r
+-- packet_out_fifofull : connected fifo for packet data is full
+-- errorbyte_in : errors occurred for slow control reply\r
+-- smaart_in : serial input from external TMP104 sensor
+-- sysmon_data : data from the FPGA system monitor module
+-- second_module_zero : signal to prevent second module optimized from the design
-- \r
-- Outputs:
--- packet_in_read : read signal to fiber module to read next data\r
--- packet_out_data : packet data to fiber module
--- packet_out_first : first 32-bit data word of a packet
--- packet_out_last : last 32-bit data word of a packet
--- packet_out_write : write signal for packet data
--- errorbyte_out : errors occurred: adjust with other FE instances for comparison\r
--- smaart_out : serial output to external TMP104 sensor
--- sysmon_reset : reset signal to the FPGA system monitor module\r
--- sysmon_address : selection address for the FPGA system monitor module\r
--- sysmon_read : read signal to the FPGA system monitor module\r
+-- packet_in_read : read signal to fiber module to read next data\r
+-- packet_out_data : packet data to fiber module
+-- packet_out_first : first 32-bit data word of a packet
+-- packet_out_last : last 32-bit data word of a packet
+-- packet_out_write : write signal for packet data
+-- packet_out_inpipe : more data to come soon
+-- errorbyte_out : errors occurred: adjust with other FE instances for comparison\r
+-- smaart_out : serial output to external TMP104 sensor
+-- sysmon_reset : reset signal to the FPGA system monitor module\r
+-- sysmon_address : selection address for the FPGA system monitor module\r
+-- sysmon_read : read signal to the FPGA system monitor module
+-- enable_waveform : produce waveforms and not Feature Extraction data
+-- compare_error : error comparing the output of two modules
--
-- Components:
--- FEE_board_slowcontrol : slowcontrol unit to translate fiber packets to slowcontrol commands
--- FEE_slowcontrol_packet_receiver : Read and interprets data (=slowcontrol commands) from fiber from Multiplexer board
--- FEE_pulse_and_pileup_waveforms : measure waveforms for pulses and pileup and multiplex to one stream\r
--- FEE_combine_data : combine slow-control, pileup waveforms and feature extraction data to one stream to GTP/GTX\r
--- FEE_measure_frequency : measure frequency of hits\r
--- TMP104module : module to access external temperature sensor TMP104
+-- FEE_board_slowcontrol : slowcontrol unit to translate fiber packets to slowcontrol commands
+-- FEE_slowcontrol_packet_receiver : Read and interprets data (=slowcontrol commands) from fiber from Multiplexer board
+-- FEE_pulse_and_pileup_waveforms : measure waveforms for pulses and pileup and multiplex to one stream\r
+-- FEE_combine_data : combine slow-control, pileup waveforms and feature extraction data to one stream to GTP/GTX\r
+-- FEE_measure_frequency : measure frequency of hits\r
+-- TMP104module : module to access external temperature sensor TMP104
--
----------------------------------------------------------------------------------
generic (
NROFADCS : natural := 32;
ADCBITS : natural := 14;
+ MWD_WIDTHBITS : natural := 5;
+ MWD_SCALEBITS : natural := 16;
+ MWD2_WIDTHBITS : natural := 2;
+ MWD2_SCALEBITS : natural := 16;
+ MWD_DOUBLEFILTER : boolean := false;
+ MWD_PU_DOUBLEFILTER : boolean := false;
BASELINE_BWBITS : natural := 10;
WAVEFORMBUFFERSIZE : natural := 10;
ADCCLOCKFREQUENCY : natural := 80000000;
CF_DELAYBITS : natural := 4;
- CF_FRACTIONBIT : natural := 11;
IDIVMAXBITS : natural := 6;
- INTEGRALRATIOBITS : natural := 3
+ INTEGRALRATIOBITS : natural := 3;
+ MAXPILEUPHITS : natural := 3;
+ SECOND_FE_MODULE : boolean := false
);
port (
clock : in std_logic;
reset : in std_logic;\r
enable_data : in std_logic;
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
ADCdata : in array_adc_type;\r
superburst_start : in std_logic;
- superburst_received : in std_logic_vector(30 downto 0);
+ superburst_received : in std_logic_vector(30 downto 0);\r
+ force_hit : in std_logic;
onesecondpulse : in std_logic;
rxNotInTable : in std_logic;
startupready : in std_logic;
packet_out_first : out std_logic;
packet_out_last : out std_logic;
packet_out_write : out std_logic;
+ packet_out_inpipe : out std_logic;
packet_out_fifofull : in std_logic;\r
errorbyte_out : out std_logic_vector(7 downto 0);\r
errorbyte_in : in std_logic_vector(7 downto 0);\r
sysmon_data : in std_logic_vector(15 downto 0);\r
sysmon_reset : out std_logic;\r
sysmon_address : out std_logic_vector(6 downto 0);\r
- sysmon_read : out std_logic;\r
- testindex : in integer range 0 to NROFADCS/2-1;\r
- testword0 : out std_logic_vector(35 downto 0);
- testword1 : out std_logic_vector(35 downto 0);\r
- testword2 : out std_logic_vector(35 downto 0)\r
+ sysmon_read : out std_logic;
+ second_module_zero : in std_logic;\r
+ enable_waveform : out std_logic;
+ compare_error : out std_logic
);
end FEE_adc32_module;
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
overflow_in : in std_logic;
request_init : in std_logic;
byte_data : in std_logic_vector(7 downto 0);
generic (
NROFADCS : natural := NROFADCS;
ADCBITS : natural := ADCBITS;
- BWBITS : natural := BASELINE_BWBITS;
+ MWD_WIDTHBITS : natural := MWD_WIDTHBITS;
+ MWD_SCALEBITS : natural := MWD_SCALEBITS;
+ MWD2_WIDTHBITS : natural := MWD2_WIDTHBITS;
+ MWD2_SCALEBITS : natural := MWD2_SCALEBITS;
+ BASELINE_BWBITS : natural := BASELINE_BWBITS;
+ MWD_DOUBLEFILTER : boolean := MWD_DOUBLEFILTER;
+ MWD_PU_DOUBLEFILTER : boolean := MWD_PU_DOUBLEFILTER;
WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
IDIVMAXBITS : natural := IDIVMAXBITS;
INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS;
- CF_DELAYBITS : natural := CF_DELAYBITS
+ CF_DELAYBITS : natural := CF_DELAYBITS;
+ MAXPILEUPHITS : natural := MAXPILEUPHITS;
+ NOWAVEFORMS : boolean := false
);
Port (\r
clock : in std_logic;
reset : in std_logic;
- superburstnumber : in std_logic_vector(30 downto 0); \r
- timestampcounter : in std_logic_vector(15 downto 0); \r
+ superburstnumber : in std_logic_vector(30 downto 0);
+ superburstupdate : in std_logic;
ADCdata : in array_adc_type;
enable_data : in std_logic;
+ enable_waveform : in std_logic;
+ force_hit : in std_logic;
slowcontrol_byte_data : in std_logic_vector (7 downto 0);
slowcontrol_byte_write : in std_logic;
slowcontrol_byte_request: in std_logic;
- pulsedata_out : out std_logic_vector(35 downto 0);
+ pulsedata_channel : out std_logic_vector(7 downto 0);
+ pulsedata_status : out std_logic_vector(7 downto 0);
+ pulsedata_superburst : out std_logic_vector(30 downto 0);
+ pulsedata_timestamp : out std_logic_vector(15 downto 0);
+ pulsedata_energy : out std_logic_vector(15 downto 0);
+ pulsedata_CFvalbefore : out std_logic_vector(15 downto 0);
+ pulsedata_CFvalafter : out std_logic_vector(15 downto 0);
pulsedata_read : in std_logic;
pulsedata_available : out std_logic;
pulsedata_inpipe : out std_logic;
- pileupdata_out : out std_logic_vector(35 downto 0);
- pileupdata_read : in std_logic;
- pileupdata_available : out std_logic;\r
- pileupdata_inpipe : out std_logic;
+ wavedata_out : out std_logic_vector(35 downto 0);
+ wavedata_read : in std_logic;
+ wavedata_available : out std_logic;
+ wavedata_inpipe : out std_logic;
pulsedetect : out std_logic_vector(0 to NROFADCS-1);
- overflow : out std_logic;\r
- testindex : in integer range 0 to NROFADCS/2-1;\r
- testword0 : out std_logic_vector(35 downto 0);\r
- testword1 : out std_logic_vector(35 downto 0);\r
- testword2 : out std_logic_vector(35 downto 0)\r
+ overflow : out std_logic;
+ error : out std_logic
);\r
end component;\r
\r
port (
clock : in std_logic;
reset : in std_logic;
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+ enable_waveform : in std_logic;
-- signals to/from data fifo :
- pulse_data : in std_logic_vector(35 downto 0);
+ pulse_channel : in std_logic_vector(7 downto 0);
+ pulse_status : in std_logic_vector(7 downto 0);
+ pulse_superburst : in std_logic_vector(30 downto 0);
+ pulse_timestamp : in std_logic_vector(15 downto 0);
+ pulse_energy : in std_logic_vector(15 downto 0);
+ pulse_CFvalbefore : in std_logic_vector(15 downto 0);
+ pulse_CFvalafter : in std_logic_vector(15 downto 0);
pulse_notpresent : in std_logic; -- empty signal from fifo
pulse_inpipe : in std_logic;
pulse_read : out std_logic; -- read from FWFT fifo
packet_firstword : out std_logic;
packet_lastword : out std_logic;
packet_datawrite : out std_logic;
+ packet_inpipe : out std_logic;
packet_fifofull : in std_logic;
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)\r
+ error : out std_logic\r
);
end component;\r
signal error_occurred_S : std_logic_vector (7 downto 0) := (others => '0');
signal enable_data_S : std_logic := '0';\r
signal startupready_S : std_logic := '0';\r
-
-signal rxAsyncDataRead_S : std_logic := '0';
-signal rxAsyncData_S : std_logic_vector (31 downto 0) := (others => '0');
-\r
+signal ADCdata_S : array_adc_type;
signal packet_in_read_S : std_logic;
-\r
-signal superburstnumber_s : std_logic_vector(30 downto 0);\r
-
-signal SODA_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
-signal SODA_cmd_valid_S : std_logic := '0';\r
+signal reset1_S : std_logic;
+signal soft_reset_S : std_logic;
-signal slowcontrol_error1_S : std_logic := '0';
+signal slowcontrol_error1_S : std_logic;
+signal invertADCs_S : std_logic;
+signal clear_errors_S : std_logic;
-signal clear_errors_S : std_logic := '0';
-
-signal pulsedata_out_S : std_logic_vector(35 downto 0);
+signal pulsedata_channel_S : std_logic_vector(7 downto 0);
+signal pulsedata_status_S : std_logic_vector(7 downto 0);
+signal pulsedata_superburst_S : std_logic_vector(30 downto 0);
+signal pulsedata_timestamp_S : std_logic_vector(15 downto 0);
+signal pulsedata_energy_S : std_logic_vector(15 downto 0);
+signal pulsedata_CFvalbefore_S : std_logic_vector(15 downto 0);
+signal pulsedata_CFvalafter_S : std_logic_vector(15 downto 0);
signal pulsedata_read_S : std_logic;
signal pulsedata_available_S : std_logic;\r
signal pulsedata_inpipe_S : std_logic;\r
-signal pileupdata_out_S : std_logic_vector(35 downto 0);
-signal pileupdata_read_S : std_logic;
-signal pileupdata_available_S : std_logic;
+signal wavedata_out_S : std_logic_vector(35 downto 0);
+signal wavedata_read_S : std_logic;
+signal wavedata_available_S : std_logic;
signal pulse_notpresent_S : std_logic;
-signal pileupdata_inpipe_s : std_logic;
+signal wavedata_inpipe_S : std_logic;
+signal wave_inpipe_S : std_logic;
signal overflow_S : std_logic;
+signal dataerror_S : std_logic;
+signal request_init_S : std_logic;
signal slowcontrol_data_S : std_logic_vector(31 downto 0);
signal slowcontrol_address_S : std_logic_vector(7 downto 0);
signal board_control_C_S : std_logic_vector(31 downto 0);
signal board_control_D_S : std_logic_vector(31 downto 0);
\r
-
-signal timestampcounter_s : std_logic_vector(15 downto 0) := (others => '0');
-signal start_of_superburst_S : std_logic := '0';\r
-\r
signal MUX_error_S : std_logic := '0';\r
\r
signal enable_waveform_S : std_logic := '0';\r
+signal enable_waveform_aftr1clk_S : std_logic;
signal wave_notpresent_S : std_logic := '0';\r
signal wave_read_S : std_logic := '0';\r
\r
signal sysmon_address_S : std_logic_vector(6 downto 0);
signal sysmon_address_saved_S : std_logic_vector(6 downto 0);
signal temperature_S : std_logic_vector (7 downto 0) := (others => '0');\r
-signal testword0_S : std_logic_vector(35 downto 0);
-signal testword1_S : std_logic_vector(35 downto 0);\r
-constant DEBUG : std_logic := '0';
-begin
-\r
- \r
-timestampcounter: process(clock)
+
+signal adcdata2_S : array_adc_type;
+signal pulsedata2_channel_S : std_logic_vector(7 downto 0);
+signal pulsedata2_status_S : std_logic_vector(7 downto 0);
+signal pulsedata2_superburst_S : std_logic_vector(30 downto 0);
+signal pulsedata2_timestamp_S : std_logic_vector(15 downto 0);
+signal pulsedata2_energy_S : std_logic_vector(15 downto 0);
+signal pulsedata2_CFvalbefore_S : std_logic_vector(15 downto 0);
+signal pulsedata2_CFvalafter_S : std_logic_vector(15 downto 0);
+signal pulsedata2_available_S : std_logic;
+signal pulsedata2_inpipe_S : std_logic;
+signal pulsedetect2_S : std_logic_vector(0 to NROFADCS-1);
+signal overflow2_S : std_logic;
+signal dataerror2_S : std_logic;
+signal reset2a_S : std_logic;
+signal reset2_S : std_logic;
+signal request_init2_S : std_logic := '0';
+signal unequal_counter_S : std_logic_vector(23 downto 0) := (others => '0');
+signal unequal_time_S : std_logic_vector(23 downto 0) := (others => '0');
+signal unequal_S : std_logic := '0';
+signal reboot_S : std_logic := '0';
+signal superburst2_start_S : std_logic;
+signal slowcontrol2_byte_write_S : std_logic;
+
+attribute mark_debug : string;
+attribute mark_debug of pulsedata2_available_S : signal is "true";
+attribute mark_debug of pulsedata2_inpipe_S : signal is "true";
+attribute mark_debug of overflow2_S : signal is "true";
+attribute mark_debug of dataerror2_S : signal is "true";
+attribute mark_debug of reset2a_S : signal is "true";
+attribute mark_debug of reset2_S : signal is "true";
+attribute mark_debug of request_init2_S : signal is "true";
+attribute mark_debug of unequal_counter_S : signal is "true";
+attribute mark_debug of unequal_time_S : signal is "true";
+attribute mark_debug of unequal_S : signal is "true";
+attribute mark_debug of reboot_S : signal is "true";
+
begin
- if (rising_edge(clock)) then
- if superburst_start='1' then\r
- timestampcounter_S <= (others => '0');\r
- superburstnumber_S <= superburst_received;\r
- else\r
- timestampcounter_S <= timestampcounter_S+1;\r
- end if;\r
- end if;
-end process;\r
- \r
- \r
-gendebug2: if DEBUG='0' generate\r
+compare_error <= reboot_S;\r
+enable_waveform <= enable_waveform_S;
FEE_slowcontrol_packet_receiver1: FEE_slowcontrol_packet_receiver port map(
clock => clock,
overflow => receive_overflow_S);
packet_in_read <= packet_in_read_S;\r
+request_init_S <= '1' when (request_init='1') or (request_init2_S='1') else '0';
FEE_board_slowcontrol1: FEE_board_slowcontrol port map(
clock => clock,
reset => reset,
enable => startupready,
+ GEO => GEO,
overflow_in => receive_overflow_S,
- request_init => request_init,
+ request_init => request_init_S,
byte_data => slowcontrol_byte_data_S,
byte_write => slowcontrol_byte_write_S,
byte_request => slowcontrol_byte_request_S,
if (slowcontrol_overflow_S='1') then
error_occurred_S(2) <= '1';
end if;\r
--- if cf_error_S='1' then
--- error_occurred_S(3) <= '1';
--- end if;\r
if MUX_error_S='1' then
error_occurred_S(4) <= '1';
end if;\r
--- if (rxAsyncDataOverflow_S='1') then
--- error_occurred_S(5) <= '1';
--- end if;
+ if (dataerror_S='1') then
+ error_occurred_S(5) <= '1';
+ end if;
if overflow_S='1' then
error_occurred_S(6) <= '1';
end if;
end process;
\r
\r
-
-
+soft_reset_S <= board_control_A_S(0);
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ invertADCs_S <= board_control_A_S(1);\r
+ end if;
+end process;
clear_errors_S <= board_control_A_S(2);\r
enable_waveform_S <= board_control_A_S(3);\r
pulsedetectmux_S <= pulsedetect_S(conv_integer(unsigned(board_control_A_S(20 downto 16))));\r
board_status_D_S(31 downto 0) <= pulsefrequency_S;\r
\r
+gen_invert: for i in 0 to NROFADCS-1 generate\r
+ ADCdata_S(i) <= not ADCdata(i) when invertADCs_S='1' else ADCdata(i);\r
+end generate; \r
\r
-FEE_pulse_and_pileup_waveforms1: FEE_pulse_and_pileup_waveforms port map(
+FEE_pulse_and_pileup_waveforms1: FEE_pulse_and_pileup_waveforms
+ generic map(
+ NROFADCS => NROFADCS,
+ ADCBITS => ADCBITS,
+ MWD_WIDTHBITS => MWD_WIDTHBITS,
+ MWD_SCALEBITS => MWD_SCALEBITS,
+ MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+ MWD2_SCALEBITS => MWD2_SCALEBITS,
+ BASELINE_BWBITS => BASELINE_BWBITS,
+ MWD_DOUBLEFILTER => MWD_DOUBLEFILTER,
+ MWD_PU_DOUBLEFILTER => MWD_PU_DOUBLEFILTER,
+ WAVEFORMBUFFERSIZE => WAVEFORMBUFFERSIZE,
+ IDIVMAXBITS => IDIVMAXBITS,
+ INTEGRALRATIOBITS => INTEGRALRATIOBITS,
+ CF_DELAYBITS => CF_DELAYBITS,
+ MAXPILEUPHITS => MAXPILEUPHITS,
+ NOWAVEFORMS => false
+ )
+ port map(
clock => clock,
- reset => reset,
- superburstnumber => superburstnumber_S,
- timestampcounter => timestampcounter_S,
- ADCdata => ADCdata,
+ reset => reset1_S,
+ superburstnumber => superburst_received,
+ superburstupdate => superburst_start,
+ ADCdata => ADCdata_S,
enable_data => enable_data,
+ enable_waveform => enable_waveform_S,
+ force_hit => force_hit,
slowcontrol_byte_data => slowcontrol_byte_data_S,
slowcontrol_byte_write => slowcontrol_byte_write_S,
slowcontrol_byte_request => slowcontrol_byte_request_S,
- pulsedata_out => pulsedata_out_S,
+ pulsedata_channel => pulsedata_channel_S,
+ pulsedata_status => pulsedata_status_S,
+ pulsedata_superburst => pulsedata_superburst_S,
+ pulsedata_timestamp => pulsedata_timestamp_S,
+ pulsedata_energy => pulsedata_energy_S,
+ pulsedata_CFvalbefore => pulsedata_CFvalbefore_S,
+ pulsedata_CFvalafter => pulsedata_CFvalafter_S,
pulsedata_read => pulsedata_read_S,
pulsedata_available => pulsedata_available_S,
pulsedata_inpipe => pulsedata_inpipe_S,
- pileupdata_out => pileupdata_out_S,
- pileupdata_read => pileupdata_read_S,
- pileupdata_available => pileupdata_available_S,
- pileupdata_inpipe => pileupdata_inpipe_S,
+ wavedata_out => wavedata_out_S,
+ wavedata_read => wavedata_read_S,
+ wavedata_available => wavedata_available_S,
+ wavedata_inpipe => wavedata_inpipe_S,
pulsedetect => pulsedetect_S,
overflow => overflow_S,
- testindex => testindex,\r
- testword0 => testword0,
- testword1 => testword1,
- testword2 => testword2
+ error => dataerror_S
);
- \r
+reset1_S <= '1' when (reset='1') or (reset2a_S='1') or (soft_reset_S='1') else '0';
+
+gen_second_FE_module: if SECOND_FE_MODULE=TRUE generate
+
+FEE_pulse_and_pileup_waveforms2: FEE_pulse_and_pileup_waveforms
+ generic map(
+ NROFADCS => NROFADCS,
+ ADCBITS => ADCBITS,
+ MWD_WIDTHBITS => MWD_WIDTHBITS,
+ MWD_SCALEBITS => MWD_SCALEBITS,
+ MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+ MWD2_SCALEBITS => MWD2_SCALEBITS,
+ BASELINE_BWBITS => BASELINE_BWBITS,
+ MWD_DOUBLEFILTER => MWD_DOUBLEFILTER,
+ MWD_PU_DOUBLEFILTER => MWD_PU_DOUBLEFILTER,
+ WAVEFORMBUFFERSIZE => WAVEFORMBUFFERSIZE,
+ IDIVMAXBITS => IDIVMAXBITS,
+ INTEGRALRATIOBITS => INTEGRALRATIOBITS,
+ CF_DELAYBITS => CF_DELAYBITS,
+ MAXPILEUPHITS => MAXPILEUPHITS,
+ NOWAVEFORMS => true
+ )
+ port map(
+ clock => clock,
+ reset => reset2_S,
+ superburstnumber => superburst_received,
+ superburstupdate => superburst2_start_S,
+ ADCdata => adcdata2_S,
+ enable_data => enable_data,
+ enable_waveform => '0',
+ force_hit => force_hit,
+ slowcontrol_byte_data => slowcontrol_byte_data_S,
+ slowcontrol_byte_write => slowcontrol_byte_write_S,
+ slowcontrol_byte_request => slowcontrol_byte_request_S,
+ pulsedata_channel => pulsedata2_channel_S,
+ pulsedata_status => pulsedata2_status_S,
+ pulsedata_superburst => pulsedata2_superburst_S,
+ pulsedata_timestamp => pulsedata2_timestamp_S,
+ pulsedata_energy => pulsedata2_energy_S,
+ pulsedata_CFvalbefore => pulsedata2_CFvalbefore_S,
+ pulsedata_CFvalafter => pulsedata2_CFvalafter_S,
+ pulsedata_read => pulsedata_read_S,
+ pulsedata_available => pulsedata2_available_S,
+ pulsedata_inpipe => pulsedata2_inpipe_S,
+ wavedata_out => open,
+ wavedata_read => wavedata_read_S,
+ wavedata_available => open,
+ wavedata_inpipe => open,
+ pulsedetect => pulsedetect2_S,
+ overflow => overflow2_S,
+ error => dataerror2_S
+ );
+ superburst2_start_S <= superburst_start when second_module_zero='0' else '0';
+ slowcontrol2_byte_write_S <= slowcontrol_byte_write_S when second_module_zero='0' else '0';
+ adcdata2_S <= adcdata_S when second_module_zero='0' else (others => (others => '0'));
+
+ reset2_S <= '1' when (reset='1') or (reset2a_S='1') or (soft_reset_S='1') else '0';
+
+ process(clock)
+ variable request_init_done_V : std_logic := '1';
+ begin
+ if (rising_edge(clock)) then
+ unequal_S <= '0';
+ reboot_S <= '0';
+ reset2a_S <= '0';
+ request_init2_S <= '0';
+ if (second_module_zero='1') or (reset='1') or (enable_waveform_aftr1clk_S/=enable_waveform_S) then
+ unequal_counter_S <= (others => '0');
+ reset2a_S <= '1';
+ unequal_time_S <= (others => '0');
+ request_init_done_V := '0';
+ else
+ if (unequal_counter_S(8)='1') and (request_init_done_V='0') then
+ request_init2_S <= '1';
+ request_init_done_V := '1';
+ end if;
+ if (enable_waveform_S='0') then
+ if ((pulsedata2_channel_S/=pulsedata_channel_S) or
+ (pulsedata2_status_S/=pulsedata_status_S) or
+ (pulsedata2_superburst_S/=pulsedata_superburst_S) or
+ (pulsedata2_timestamp_S/=pulsedata_timestamp_S) or
+ (pulsedata2_energy_S/=pulsedata_energy_S) or
+ (pulsedata2_CFvalbefore_S/=pulsedata_CFvalbefore_S) or
+ (pulsedata2_CFvalafter_S/=pulsedata_CFvalafter_S) or
+ (pulsedata2_available_S/=pulsedata_available_S) or
+ (pulsedata2_inpipe_S/=pulsedata_inpipe_S) or
+ (pulsedetect2_S/=pulsedetect_S) or
+ (overflow2_S/=overflow_S) or
+ (dataerror2_S/=dataerror_S)) then
+ unequal_time_S <= unequal_counter_S;
+ unequal_S <= '1';
+ if (unequal_counter_S(unequal_counter_S'left)='1') then
+ reboot_S <= '1';
+ end if;
+ end if;
+ end if;
+ if unequal_counter_S(unequal_counter_S'left)='0' then
+ unequal_counter_S <= unequal_counter_S+1;
+ end if;
+ end if;
+ enable_waveform_aftr1clk_S <= enable_waveform_S;
+ end if;
+ end process;
+
+end generate;
+ \r
pulse_notpresent_S <= not pulsedata_available_S;
FEE_combine_data1: FEE_combine_data port map(
clock => clock,
reset => reset,
+ GEO => GEO,
+ enable_waveform => enable_waveform_S,
-- signals to/from data fifo :
- pulse_data => pulsedata_out_S,
+ pulse_channel => pulsedata_channel_S,
+ pulse_status => pulsedata_status_S,
+ pulse_superburst => pulsedata_superburst_S,
+ pulse_timestamp => pulsedata_timestamp_S,
+ pulse_energy => pulsedata_energy_S,
+ pulse_CFvalbefore => pulsedata_CFvalbefore_S,
+ pulse_CFvalafter => pulsedata_CFvalafter_S,
pulse_notpresent => pulse_notpresent_S,
pulse_inpipe => pulsedata_inpipe_S,
pulse_read => pulsedata_read_S,\r
slowcontrol_notpresent => slowcontrol_notpresent_S,
slowcontrol_read => slowcontrol_read_S,
-- signals to/from waveform fifo
- wave_data => pileupdata_out_S,
+ wave_data => wavedata_out_S,
wave_notpresent => wave_notpresent_S,
- wave_inpipe => pileupdata_inpipe_S,
+ wave_inpipe => wave_inpipe_S,
wave_read => wave_read_S,
-- signals to/from fiber module
packet_data_out => packet_out_data,
packet_firstword => packet_out_first,
packet_lastword => packet_out_last,
packet_datawrite => packet_out_write,
+ packet_inpipe => packet_out_inpipe,
packet_fifofull => packet_out_fifofull,
- error => MUX_error_S,
- testword0 => open);
+ error => MUX_error_S);
\r
-wave_notpresent_S <= '1' when (pileupdata_available_S='0') or (enable_waveform_S='0') else '0';\r
-pileupdata_read_S <= '1' when (enable_waveform_S='0') and (pileupdata_available_S='1') else wave_read_S;\r
+wave_notpresent_S <= '1' when (wavedata_available_S='0') or (enable_waveform_S='0') else '0';\r
+wavedata_read_S <= '1' when (enable_waveform_S='0') and (wavedata_available_S='1') else wave_read_S;\r
+wave_inpipe_S <= '1' when (wavedata_inpipe_S='1') and (enable_waveform_S='1') else '0';\r
---gtpClk_I : IBUFDS port map(
--- O => gtpClk_S,
--- I => gtpClkP0,
--- IB => gtpClkN0);\r
-
---GTX_refclock: IBUFDS_GTXE1 port map(
--- O => gtpClk_S,
--- ODIV2 => open,
--- CEB => '0',
--- I => MGTREFCLK_P,
--- IB => MGTREFCLK_N);\r
-end generate; --debug\r
-
-gendebug3: if DEBUG='0' generate\r
FEE_measure_frequency1: FEE_measure_frequency port map(\r
clock => clock,
pulse => pulsedetectmux_S,\r
onesecondpulse => onesecondpulse,
frequency => pulsefrequency_S);\r
-end generate; -- debug\r
---TMP104module1: TMP104module port map(
--- clock => clock,
--- reset => reset,\r
--- smaart_in => smaart_in,
--- smaart_out => smaart_out,
--- temperature => temperature_S);\r
---testword0(34 downto 0) <= testword0_S(34 downto 0);\r
---testword0(35) <= enable_waveform_S;\r
-
---testword1(15 downto 0) <= packet_in_data(31 downto 16); \r
---testword1(16) <= packet_in_present; \r
---testword1(17) <= packet_in_read_S; \r
---testword1(18) <= slowcontrol_byte_write_S; \r
---testword1(19) <= slowcontrol_byte_request_S; \r
---testword1(27 downto 20) <= slowcontrol_byte_data_S; \r
---testword1(28) <= slowcontrol_error1_S; \r
---testword1(29) <= receive_overflow_S; \r
---testword1(34 downto 30) <= testword1_S(4 downto 0); \r
---testword1(35) <= '1' when testword1_S(23 downto 0)=x"000000" else '0';\r
-\r
+TMP104module1: TMP104module port map(
+ clock => clock,
+ reset => reset,\r
+ smaart_in => smaart_in,
+ smaart_out => smaart_out,
+ temperature => temperature_S
+ );\r
\r
end Behavioral;
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 27-01-2012
-- Module Name: FEE_baselinefollower_eventdetector
-- Description: Baseline reconstruction, pulse detection
-- Modifications:
-- 16-09-2014 name changed from baselinefollower_eventdetector to FEE_baselinefollower_eventdetector
+-- 24-04-2015 Moving Window Deconvolution added
+-- 03-03-2016 Output delayed with 1 clock
+-- 23-02-2017 Added one additional Moving Window Deconvolution with short width
----------------------------------------------------------------------------------\r
\r
library IEEE;
-- Baseline reconstruction, pulse detection
--
-- generics
--- ADCBITS : number of ADC bits
--- BWBITS : number of bits for the IIR filter bandwidth
+-- ADCBITS : number of ADC bits
+-- BASELINE_BWBITS : number of bits for the IIR filter bandwidth
+-- MWD_WIDTHBITS : number of bits for the width
+-- MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations
+-- MWD2_WIDTHBITS : number of bits for the width of second MWD
+-- MWD2_SCALEBITS : number of bits for tau factor for second MWD, also scaling for calculations
+-- MWD_DOUBLEFILTER : two MWD filters in series
--
-- inputs
--- clock : ADC sampling clock
--- reset : synchrounous reset\r
--- enable : enable detection of pulses
+-- clock : ADC sampling clock
+-- reset : synchrounous reset\r
+-- enable : enable detection of pulses
-- ADCdata : ADC sampling data
--- threshold : threshold above baseline for start of pulse
--- IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
--- maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline
+-- MWD1_width : width of the first MWD filter
+-- MWD1_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for first single pulse MWD
+-- MWD2_width : width of the second MWD filter
+-- MWD2_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for second single pulse MWD
+-- threshold : threshold above baseline for start of pulse
+-- IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BASELINE_BWBITS)/samplefrequency)
+-- maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline
--
-- outputs
--- baseline : resulting corrected baseline\r
--- ADC_delayed : ADC data delayed with 1 clock
--- ADC_minus_baseline : ADC values delayed minus baseline
--- baseline_inhibit : signal to indicate a pulse is valid and baseline filtering/stdev is inhibit
--- pulse_active : the ADC-signal exceeds the trigger-level\r
--- pulse_rising : the pulse has not yet reached its maximum\r
--- max_data : maximum value of waveform\r
+-- ADC_minus_baseline : ADC values delayed minus baseline
+-- baseline_inhibit : signal to indicate a pulse is valid and baseline filtering/stdev is inhibit
+-- pulse_active : the ADC-signal exceeds the trigger-level\r
+-- pulse_rising : the pulse has not yet reached its maximum\r
+-- max_data : maximum value of waveform\r
--
--- components
--- IIRfilter_1order : IIR filter for the baseline
--- FEE_eventdetector : detection of pulse
+-- components\r
+-- FEE_MWDfilter_unsigned : Moving Window deconvolution
+-- iirfilter_1order_selectBW : IIR filter for the baseline
+-- FEE_eventdetector : detection of pulse
--
----------------------------------------------------------------------------------
entity FEE_baselinefollower_eventdetector is
generic (
ADCBITS : natural := 16;
- BWBITS : natural := 10
+ BASELINE_BWBITS : natural := 10;
+ MWD_WIDTHBITS : natural := 8;
+ MWD_SCALEBITS : natural := 16;
+ MWD2_WIDTHBITS : natural := 2;
+ MWD2_SCALEBITS : natural := 16;
+ MWD_DOUBLEFILTER : boolean := false
);
port (
- clock : in std_logic;
- reset : in std_logic;\r
- enable : in std_logic;\r
- ADCdata : in std_logic_vector((ADCBITS-1) downto 0);
- threshold : in std_logic_vector((ADCBITS-1) downto 0);
+ clock : in std_logic;
+ reset : in std_logic;\r
+ enable : in std_logic;\r
+ ADCdata : in std_logic_vector(ADCBITS-1 downto 0);
+ MWD1_width : in std_logic_vector((MWD_WIDTHBITS-1) downto 0);
+ MWD1_tau_factor : in std_logic_vector((MWD_SCALEBITS-1) downto 0);
+ MWD2_width : in std_logic_vector(MWD2_WIDTHBITS-1 downto 0);
+ MWD2_tau_factor : in std_logic_vector((MWD2_SCALEBITS-1) downto 0);
+ threshold : in std_logic_vector(ADCBITS-1 downto 0);
IIRfilterBW : in std_logic_vector(2 downto 0);
maxabovebaseline : in std_logic_vector(3 downto 0);
- baseline : out std_logic_vector((ADCBITS-1) downto 0);
- ADC_delayed : out std_logic_vector(ADCBITS-1 downto 0);
ADC_minus_baseline : out std_logic_vector(ADCBITS downto 0);
baseline_inhibit : out std_logic;
pulse_active : out std_logic;\r
pulse_rising : out std_logic;\r
- max_data : out std_logic_vector(ADCBITS-1 downto 0)\r
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)
);
end FEE_baselinefollower_eventdetector;
architecture Behavioral of FEE_baselinefollower_eventdetector is
+component FEE_MWDfilter_unsigned is
+ generic (
+ MWD_DATABITS : natural := ADCBITS;
+ MWD_WIDTHBITS : natural := MWD_WIDTHBITS;
+ MWD_SCALEBITS : natural := MWD_SCALEBITS
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector((MWD_DATABITS-1) downto 0);
+ MWD_width : in std_logic_vector((MWD_WIDTHBITS-1) downto 0);
+ MWD_tau_factor : in std_logic_vector((MWD_SCALEBITS-1) downto 0);
+ data_out_signed : out std_logic_vector(MWD_DATABITS downto 0);
+ data_out_unsigned : out std_logic_vector(MWD_DATABITS downto 0));
+end component; \r
+\r
component iirfilter_1order_selectBW is
generic (
- ADCBITS : natural := ADCBITS;
- BWBITS : natural := BWBITS
+ ADCBITS : natural := ADCBITS+MWD_WIDTHBITS+4;
+ BWBITS : natural := BASELINE_BWBITS
);
port (
- clock : in std_logic;
- reset : in std_logic;
- data_in : in std_logic_vector ((ADCBITS-1) downto 0);
- BWidx : in std_logic_vector (2 downto 0);
- inhibit : in std_logic;
- data_out : out std_logic_vector ((ADCBITS-1) downto 0));
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector (ADCBITS-1 downto 0);
+ BWidx : in std_logic_vector (2 downto 0);
+ inhibit : in std_logic;
+ data_out : out std_logic_vector (ADCBITS-1 downto 0));
end component;
component FEE_eventdetector is\r
max_data : out std_logic_vector(ADCBITS-1 downto 0)\r
);\r
end component;
+\r
+constant ZEROS : std_logic_vector(63 downto 0) := (others => '0');
+\r
+signal MWD1data_unsigned_S : std_logic_vector(ADCBITS downto 0);
+signal MWDdata_unsigned_S : std_logic_vector(ADCBITS+1 downto 0);
-signal ADC_delayed_S : std_logic_vector((ADCBITS-1) downto 0) := (others => '0');
-signal baseline_S : std_logic_vector((ADCBITS-1) downto 0) := (others => '0');
-signal ADC_minusbaseline_S : std_logic_vector(ADCBITS downto 0) := (others => '0');\r
+signal ADC_delayed_S : std_logic_vector(ADCBITS+1 downto 0);
+signal baseline_S : std_logic_vector(ADCBITS+1 downto 0);
+signal ADC_minusbaselinei_S : integer range -2**(ADCBITS+2) to 2**(ADCBITS+2)-1;\r
+signal ADC_minusbaseline_S : std_logic_vector(ADCBITS downto 0);\r
signal baseline_inhibit_S : std_logic := '0';\r
-signal pulse_active_S : std_logic := '0';\r
+signal pulse_active_S : std_logic := '0';
+signal pulse_rising_S : std_logic := '0';
signal enable_S : std_logic := '0';\r
-\r
+attribute mark_debug : string;
+-- attribute mark_debug of ADC_delayed_S : signal is "true";
+-- attribute mark_debug of MWD1data_unsigned_S : signal is "true";
+-- attribute mark_debug of MWDdata_unsigned_S : signal is "true";
+-- attribute mark_debug of baseline_S : signal is "true";
+-- attribute mark_debug of ADC_minusbaselinei_S : signal is "true";
+-- attribute mark_debug of ADC_minusbaseline_S : signal is "true";
+-- attribute mark_debug of baseline_inhibit_S : signal is "true";
+attribute mark_debug of pulse_active_S : signal is "true";
begin
-
+FEE_MWDfilter_unsigned1: FEE_MWDfilter_unsigned
+ generic map(
+ MWD_DATABITS => ADCBITS,
+ MWD_WIDTHBITS => MWD_WIDTHBITS,
+ MWD_SCALEBITS => MWD_SCALEBITS)
+ port map(
+ clock => clock,
+ reset => reset,
+ data_in => ADCdata,
+ MWD_width => MWD1_width,
+ MWD_tau_factor => MWD1_tau_factor,
+ data_out_unsigned => MWD1data_unsigned_S,
+ data_out_signed => open);
-baselinefilter: iirfilter_1order_selectBW port map(
- clock => clock,
- reset => reset,
- data_in => ADC_delayed_S,
- BWidx => IIRfilterBW(2 downto 0),
- inhibit => baseline_inhibit_S,
- data_out => baseline_S);
+gen_second_MWD: if MWD_DOUBLEFILTER=true generate
+ FEE_MWDfilter_unsigned2: FEE_MWDfilter_unsigned
+ generic map(
+ MWD_DATABITS => ADCBITS+1,
+ MWD_WIDTHBITS => MWD2_WIDTHBITS,
+ MWD_SCALEBITS => MWD2_SCALEBITS)
+ port map(
+ clock => clock,
+ reset => reset,
+ data_in => MWD1data_unsigned_S,
+ MWD_width => MWD2_width,
+ MWD_tau_factor => MWD2_tau_factor,
+ data_out_unsigned => MWDdata_unsigned_S,
+ data_out_signed => open);
+end generate;
-ADC_minusbaseline_S <= conv_std_logic_vector(conv_integer(signed('0' & ADCdata)) - conv_integer(signed('0' & baseline_S)),(ADCBITS+1));
+gen_no_second_MWD: if MWD_DOUBLEFILTER=false generate
+ MWDdata_unsigned_S <= '0' & MWD1data_unsigned_S;
+end generate;
+
+baselinefilter: iirfilter_1order_selectBW
+ generic map(
+ ADCBITS => ADCBITS+2,
+ BWBITS => BASELINE_BWBITS)
+ port map(
+ clock => clock,
+ reset => reset,
+ data_in => ADC_delayed_S,
+ BWidx => IIRfilterBW(2 downto 0),
+ inhibit => baseline_inhibit_S,
+ data_out => baseline_S);
+
+ADC_minusbaselinei_S <= conv_integer(signed('0' & MWDdata_unsigned_S)) - conv_integer(signed('0' & baseline_S));\r
+ADC_minusbaseline_S <=\r
+ (0 => '0', others => '1') when ADC_minusbaselinei_S>2**ADCBITS-1 else -- clip positive\r
+ (0 => '1', others => '0') when ADC_minusbaselinei_S<-2**ADCBITS else -- clip negative\r
+ conv_std_logic_vector(ADC_minusbaselinei_S,ADCBITS+1); -- in range\r
FEE_eventdetector1: FEE_eventdetector port map(\r
clock => clock,
maxabovebaseline => maxabovebaseline,\r
baseline_freeze => baseline_inhibit_S,\r
pulse_active => pulse_active_S,\r
- pulse_rising => pulse_rising,\r
+ pulse_rising => pulse_rising_S,\r
max_data => max_data);\r
-pulse_active <= pulse_active_S when enable_S='1' else '0';\r
\r
process(clock)
begin
if rising_edge(clock) then
- ADC_delayed_S <= ADCdata;\r
+ ADC_delayed_S <= MWDdata_unsigned_S;\r
if pulse_active_S='0' then\r
enable_S <= enable;\r
end if;
end if;
end process;\r
-baseline <= baseline_S;
-baseline_inhibit <= baseline_inhibit_S;\r
-ADC_delayed <= ADC_delayed_S;
-ADC_minus_baseline <= ADC_minusbaseline_S;\r
+process(clock)
+begin
+ if rising_edge(clock) then
+ pulse_rising <= pulse_rising_S;
+ if enable_S='1' then
+ pulse_active <= pulse_active_S;
+ else
+ pulse_active <= '0';
+ end if;
+ baseline_inhibit <= baseline_inhibit_S;
+ ADC_minus_baseline <= ADC_minusbaseline_S;
+ end if;
+end process;
+
end Behavioral;
clock : in std_logic;\r
reset : in std_logic;\r
enable : in std_logic;\r
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2\r
overflow_in : in std_logic;\r
request_init : in std_logic;\r
byte_data : in std_logic_vector(7 downto 0);\r
\r
component sync_fifo_512x41\r
port (\r
- rst : in std_logic;\r
- clk : in std_logic;\r
+ srst : in std_logic;\r
+ clk : in std_logic;\r
din : in std_logic_vector(40 downto 0);\r
wr_en : in std_logic;\r
rd_en : in std_logic;\r
signal slowcontrol_write_S : std_logic;\r
signal slowcontrol_fifofull_S : std_logic;\r
\r
-signal board_control_A_S : std_logic_vector (31 downto 0) := x"00000000";\r
+signal board_control_A_S : std_logic_vector (31 downto 0) := x"00000008";\r
signal board_control_B_S : std_logic_vector (31 downto 0) := x"00000000";\r
signal board_control_C_S : std_logic_vector (31 downto 0) := x"00000000";\r
signal board_control_D_S : std_logic_vector (31 downto 0) := x"00000000";\r
end if;\r
if byte_idx_S=0 then\r
if (byte_write='1') then\r
- if (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then\r
+ if (NROFFEEFPGAS=1) and (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then\r
selected_S <= '1';\r
selected_reg_S <= byte_data(1 downto 0);\r
+ elsif (NROFFEEFPGAS=2) and (byte_data(7 downto 3)=ADDRESS_FEE_CONTROL(7 downto 3)) and (byte_data(0)=GEO) then\r
+ selected_S <= '1';\r
+ selected_reg_S <= byte_data(2 downto 1);\r
else\r
selected_S <= '0';\r
end if;\r
byte_idx_S <= 1;\r
elsif byte_request='1' then\r
- if (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then\r
+ if (NROFFEEFPGAS=1) and (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then\r
case byte_data(1 downto 0) is\r
when "00" => slowcontrol_data_S <= board_status_A;\r
when "01" => slowcontrol_data_S <= board_status_B;\r
if slowcontrol_fifofull_S='1' then\r
overflow2_S <= '1';\r
end if;\r
+ elsif (NROFFEEFPGAS=2) and (byte_data(7 downto 3)=ADDRESS_FEE_CONTROL(7 downto 3)) and (byte_data(0)=GEO) then\r
+ case byte_data(2 downto 1) is\r
+ when "00" => slowcontrol_data_S <= board_status_A;\r
+ when "01" => slowcontrol_data_S <= board_status_B;\r
+ when "10" => slowcontrol_data_S <= board_status_C;\r
+ when "11" => slowcontrol_data_S <= board_status_D;\r
+ when others => \r
+ end case;\r
+ slowcontrol_address_S <= byte_data;\r
+ slowcontrol_reply_S <= '1';\r
+ slowcontrol_write_S <= '1';\r
+ if slowcontrol_fifofull_S='1' then\r
+ overflow2_S <= '1';\r
+ end if;\r
end if; \r
selected_S <= '0';\r
byte_idx_S <= 0;\r
overflow2_S <= '0';\r
slowcontrol_data_S <= (others => '0');\r
slowcontrol_address_S <= ADDRESS_FEE_SLOWCONTROLERROR;\r
- slowcontrol_reply_S <= '1'; -- ??\r
+ slowcontrol_reply_S <= '0'; -- ??\r
slowcontrol_write_S <= '1';\r
end if;\r
end if;\r
\r
fifo_in_S <= slowcontrol_reply_S & slowcontrol_address_S & slowcontrol_data_S;\r
fifo1: sync_fifo_512x41 port map(\r
- rst => reset,\r
+ srst => reset,\r
clk => clock,\r
din => fifo_in_S,\r
wr_en => slowcontrol_write_S,\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI-cart/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 04-04-2017
+-- Module Name: FEE_collect_pileup_pulses
+-- Description: Collect results of Feature Extraction for pileup pulses
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+USE work.panda_package.all;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_collect_pileup_pulses
+-- Collect results of Feature Extraction for pileup pulses
+-- Hits in pileup waveform are stored in memory and if the waveform is regarded as valid pileup then the hits are written to the output.
+--
+--
+-- generics
+-- MAXPILEUPHITS : maximum number of hits in one pileup waveform
+--
+-- inputs
+-- clock : clock
+-- reset : synchrounous reset
+-- pulse_active : pulse is active: above thresshold
+-- pileup_valid : pileup waveform is valid
+-- detect_singlepulse : single hit detected
+-- detect_pileuppulse : hit detected in pileup waveform
+-- detect_clearpulse : clear pileup waveform
+-- detect_purge : clear detected hits in pileup waveform
+-- data_in_write : write signal for input data
+-- data_in_superburst : superburstnumber
+-- data_in_timestamp : time within superburst
+-- data_in_energy : energy of the hit
+-- data_in_CF1 : Constant Fraction result: sample before zero-crossing
+-- data_in_CF2 : Constant Fraction result: sample after zero-crossing
+--
+-- outputs
+-- data_out_write : write signal for input data
+-- data_out_superburst : superburstnumber
+-- data_out_timestamp : time within superburst
+-- data_out_energy : energy of the hit
+-- data_out_CF1 : Constant Fraction result: sample before zero-crossing
+-- data_out_CF2 : Constant Fraction result: sample after zero-crossing
+-- data_out_skipped : Previous data was skipped
+--
+-- Components:
+-- blockmem : memory for pileup data
+-- blockmem1x96_xilinx, blockmem2x96_xilinx, blockmem3x96_xilinx : Xilinx block memory IP cores
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_collect_pileup_pulses is
+ generic (
+ MAXPILEUPHITS : natural := 3
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ pulse_active : in std_logic;
+ pileup_valid : in std_logic;
+ detect_singlepulse : in std_logic;
+ detect_pileuppulse : in std_logic;
+ detect_clearpulse : in std_logic;
+ detect_purge : in std_logic;
+ data_in_write : in std_logic;
+ data_in_superburst : in std_logic_vector(30 downto 0);
+ data_in_timestamp : in std_logic_vector(15 downto 0);
+ data_in_energy : in std_logic_vector(15 downto 0);
+ data_in_CF1 : in std_logic_vector(15 downto 0);
+ data_in_CF2 : in std_logic_vector(15 downto 0);
+ data_out_write : out std_logic;
+ data_out_superburst : out std_logic_vector(30 downto 0);
+ data_out_timestamp : out std_logic_vector(15 downto 0);
+ data_out_energy : out std_logic_vector(15 downto 0);
+ data_out_CF1 : out std_logic_vector(15 downto 0);
+ data_out_CF2 : out std_logic_vector(15 downto 0);
+ data_out_skipped : out std_logic
+ );
+end FEE_collect_pileup_pulses;
+
+architecture Behavioral of FEE_collect_pileup_pulses is
+
+component blockmem is
+ generic (
+ ADDRESS_BITS : natural := twologarray(MAXPILEUPHITS);
+ DATA_BITS : natural := 96
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)
+ );
+end component;
+
+COMPONENT blockmem1x96_xilinx
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+ );
+END COMPONENT;
+
+COMPONENT blockmem2x96_xilinx
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+ );
+END COMPONENT;
+
+COMPONENT blockmem3x96_xilinx
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+ );
+END COMPONENT;
+
+constant ZEROS : std_logic_vector(63 downto 0) := (others => '0');
+constant ONES : std_logic_vector(63 downto 0) := (others => '1');
+type pileupbuffer_superburst_type is array(0 to MAXPILEUPHITS-1) of std_logic_vector(30 downto 0);
+type pileupbuffer_16bits_type is array(0 to MAXPILEUPHITS-1) of std_logic_vector(15 downto 0);
+
+
+signal mem_writeaddress_S : std_logic_vector(twologarray(MAXPILEUPHITS)-1 downto 0);
+signal mem_readaddress_S : std_logic_vector(twologarray(MAXPILEUPHITS)-1 downto 0);
+
+signal data_out_write_S : std_logic := '0';
+signal hitcount_S : integer range 0 to MAXPILEUPHITS;
+signal resultcount_S : integer range 0 to MAXPILEUPHITS;
+signal readcount_S : integer range 0 to MAXPILEUPHITS;
+signal pileupbuffer_skipped_S : std_logic;
+
+attribute mark_debug : string;
+-- attribute mark_debug of clipping_S : signal is "true";
+
+begin
+
+data_out_write <= data_out_write_S;
+mem_writeaddress_S <= conv_std_logic_vector(hitcount_S,twologarray(MAXPILEUPHITS));
+mem_readaddress_S <= conv_std_logic_vector(readcount_S,twologarray(MAXPILEUPHITS));
+
+gen_otherbitsmemblock: if twologarray(MAXPILEUPHITS)>3 generate
+ blockmem1: blockmem port map(
+ clock => clock,
+ write_enable => data_in_write,
+ write_address => mem_writeaddress_S,
+ data_in(15 downto 0) => data_in_CF2,
+ data_in(31 downto 16) => data_in_CF1,
+ data_in(47 downto 32) => data_in_energy,
+ data_in(63 downto 48) => data_in_timestamp,
+ data_in(94 downto 64) => data_in_superburst,
+ data_in(95) => pileupbuffer_skipped_S,
+ read_address => mem_readaddress_S,
+ data_out(15 downto 0) => data_out_CF2,
+ data_out(31 downto 16) => data_out_CF1,
+ data_out(47 downto 32) => data_out_energy,
+ data_out(63 downto 48) => data_out_timestamp,
+ data_out(94 downto 64) => data_out_superburst,
+ data_out(95) => data_out_skipped
+ );
+end generate;
+
+gen_1bitsmemblock: if twologarray(MAXPILEUPHITS)=1 generate
+blockmem1x96_xilinx1: blockmem1x96_xilinx port map(
+ clka => clock,
+ wea(0) => data_in_write,
+ addra => mem_writeaddress_S,
+ dina(15 downto 0) => data_in_CF2,
+ dina(31 downto 16) => data_in_CF1,
+ dina(47 downto 32) => data_in_energy,
+ dina(63 downto 48) => data_in_timestamp,
+ dina(94 downto 64) => data_in_superburst,
+ dina(95) => pileupbuffer_skipped_S,
+ clkb => clock,
+ addrb => mem_readaddress_S,
+ doutb(15 downto 0) => data_out_CF2,
+ doutb(31 downto 16) => data_out_CF1,
+ doutb(47 downto 32) => data_out_energy,
+ doutb(63 downto 48) => data_out_timestamp,
+ doutb(94 downto 64) => data_out_superburst,
+ doutb(95) => data_out_skipped);
+end generate;
+gen_2bitsmemblock: if twologarray(MAXPILEUPHITS)=2 generate
+blockmem2x96_xilinx1: blockmem2x96_xilinx port map(
+ clka => clock,
+ wea(0) => data_in_write,
+ addra => mem_writeaddress_S,
+ dina(15 downto 0) => data_in_CF2,
+ dina(31 downto 16) => data_in_CF1,
+ dina(47 downto 32) => data_in_energy,
+ dina(63 downto 48) => data_in_timestamp,
+ dina(94 downto 64) => data_in_superburst,
+ dina(95) => pileupbuffer_skipped_S,
+ clkb => clock,
+ addrb => mem_readaddress_S,
+ doutb(15 downto 0) => data_out_CF2,
+ doutb(31 downto 16) => data_out_CF1,
+ doutb(47 downto 32) => data_out_energy,
+ doutb(63 downto 48) => data_out_timestamp,
+ doutb(94 downto 64) => data_out_superburst,
+ doutb(95) => data_out_skipped);
+end generate;
+gen_3bitsmemblock: if twologarray(MAXPILEUPHITS)=3 generate
+blockmem1x96_xilinx1: blockmem3x96_xilinx port map(
+ clka => clock,
+ wea(0) => data_in_write,
+ addra => mem_writeaddress_S,
+ dina(15 downto 0) => data_in_CF2,
+ dina(31 downto 16) => data_in_CF1,
+ dina(47 downto 32) => data_in_energy,
+ dina(63 downto 48) => data_in_timestamp,
+ dina(94 downto 64) => data_in_superburst,
+ dina(95) => pileupbuffer_skipped_S,
+ clkb => clock,
+ addrb => mem_readaddress_S,
+ doutb(15 downto 0) => data_out_CF2,
+ doutb(31 downto 16) => data_out_CF1,
+ doutb(47 downto 32) => data_out_energy,
+ doutb(63 downto 48) => data_out_timestamp,
+ doutb(94 downto 64) => data_out_superburst,
+ doutb(95) => data_out_skipped);
+end generate;
+
+process(clock)
+variable detect_pileupvalidpulse_V : std_logic;
+variable pileuppulse_detected_V : std_logic := '0';
+begin
+ if rising_edge(clock) then
+ data_out_write_S <= '0';
+ detect_pileupvalidpulse_V := '0';
+ if detect_pileuppulse='1' then
+ if pulse_active='1' then
+ pileuppulse_detected_V := '1';
+ else
+ pileuppulse_detected_V := '0';
+ detect_pileupvalidpulse_V := '1';
+ end if;
+ elsif pileuppulse_detected_V='1' then
+ if pulse_active='0' then
+ pileuppulse_detected_V := '0';
+ detect_pileupvalidpulse_V := '1';
+ end if;
+ end if;
+ if (data_in_write='1') then
+ if hitcount_S<MAXPILEUPHITS then
+ hitcount_S <= hitcount_S+1;
+ else
+ pileupbuffer_skipped_S <= '1';
+ end if;
+ end if;
+ if detect_pileupvalidpulse_V='1' then
+ if (hitcount_S=0) and (data_in_write='0') then
+ pileupbuffer_skipped_S <= '1';
+ elsif (hitcount_S=0) and (data_in_write='1') then
+ resultcount_S <= 1;
+ readcount_S <= 0;
+ else
+ pileupbuffer_skipped_S <= '0';
+ if (data_in_write='1') and (hitcount_S<MAXPILEUPHITS) then
+ resultcount_S <= hitcount_S+1;
+ else
+ resultcount_S <= hitcount_S;
+ end if;
+ hitcount_S <= 0;
+ readcount_S <= 0;
+ end if;
+ else
+ if readcount_S<resultcount_S then
+ data_out_write_S <= '1';
+ readcount_S <= readcount_S+1;
+ end if;
+ end if;
+ if (reset='1') or (detect_singlepulse='1') or (detect_clearpulse='1') or (detect_purge='1') then
+ hitcount_S <= 0;
+ readcount_S <= 0;
+ resultcount_S <= 0;
+ end if;
+ if (pileup_valid='0') and (pulse_active='0') and (data_in_write='0') then
+ hitcount_S <= 0;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
+
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 28-02-2012
-- Module Name: FEE_combine_data
-- 09-09-2014 New data formats without hamming code
-- 10-10-2014 Integral as measurement for the energy instead of maximum
-- 16-10-2014 Inpipe signals, better sorting between waveforms and single pulse packets
+-- 23-02-2017 Parallel data from Feature Extraction instead of 36-bits
----------------------------------------------------------------------------------
library IEEE;
-- Module in the Front End Electronics that builds packets from Pulse data, waveforms and
-- Slow-control data to send to the fiber module.
--
--- The pulse data consists of three successive 36-bits words with bits 35..34 the index:
--- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
--- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
--- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- The pulse data from the feature extraction contains values that determine time and energy.
+-- The parameters are received in parallel.
--
-- The Slow-control commands consists of address and data plus a bit to indicate reply.
--- If an error occurs then a slowcontrol packet with address ADDRESS_FEE_SLOWCONTROLERROR is sent
+-- If an error occurs then a slowcontrol packet with address ADDRESS_FEE_SLOWCONTROLERROR is sent.
--
-- The waveform data consists of 36-bits data with variable length :
-- bits(35..32)="0000" : bits(31..16)=superburstnumber, bits(31..0)=timestamp inside superburst
--
-- The resulting data packets : 4 32-bit words, with CRC8 in last word
-- 0xDA ADCnumber(7..0) superburstnumber(15..0)
--- 0000 energy(15..0)
+-- timestamp(15..0) energy(15..0)
-- CF_before(15..0) CF_after(15..0)
--- timestamp(15..0) statusbyte(7..0) CRC8(7..0)
+-- 0000 statusbyte(7..0) CRC8(7..0)
--
-- The slow control packets : 2 32-bit words, with CRC8 in last word
-- 0x5C address(7..0) replybit 0000000 data(31..24)
-- Inputs:
-- clock : clock input
-- reset : synchronous reset
--- pulse_data : data with results from Feature Extraction
+-- GEO : FPGA identification: 0:this is FPGA1, 1:this is FPGA2
+-- pulse_channel : results from Feature Extraction: ADC channel number
+-- pulse_status : results from Feature Extraction: status byte
+-- pulse_superburst : results from Feature Extraction: superburst number
+-- pulse_timestamp : results from Feature Extraction: timestamp within superburst
+-- pulse_energy : results from Feature Extraction: energy
+-- pulse_CFvalbefore : results from Feature Extraction: ADC sample before zero-crossing Constant Fraction method
+-- pulse_CFvalafter : results from Feature Extraction: ADC sample after zero-crossing Constant Fraction method
-- pulse_notpresent : pulse data not available (empty signal from connected fifo)
-- pulse_inpipe : more single pulse data on its way
--- slowcontrol_data : slow-control command :
--- first address-word with bit31=reply, bit30..28=101 and bit23..0=address then data-word
+-- slowcontrol_data : data slow-control command
+-- slowcontrol_address : address slow-control command
+-- slowcontrol_reply : slow-control command contains a reply on a request
-- slowcontrol_notpresent : slow-control not available (empty signal from fifo)
-- wave_data : data with pileup waveforms from pileup multiplexer
-- wave_notpresent : pileup waveform not available (empty signal from fifo)\r
-- packet_firstword : first 32-bit data word of a packet
-- packet_lastword : last 32-bit data word of a packet
-- packet_datawrite : write signal for packet data
+-- packet_inpipe : more data to come soon
-- error : error on incomming data (no sequential index)
--
-- Components:
--- crc8_add_check32 : add and checks a CRC8 code to a stream of 32 bits data words
--- the check is not used in this module
+-- crc8_add_check32 : add and checks a CRC8 code to a stream of 32 bits data words (check is not used)
--
----------------------------------------------------------------------------------
port (
clock : in std_logic;
reset : in std_logic;
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+ enable_waveform : in std_logic;
-- signals to/from data fifo :
- pulse_data : in std_logic_vector(35 downto 0);
+ pulse_channel : in std_logic_vector(7 downto 0);
+ pulse_status : in std_logic_vector(7 downto 0);
+ pulse_superburst : in std_logic_vector(30 downto 0);
+ pulse_timestamp : in std_logic_vector(15 downto 0);
+ pulse_energy : in std_logic_vector(15 downto 0);
+ pulse_CFvalbefore : in std_logic_vector(15 downto 0);
+ pulse_CFvalafter : in std_logic_vector(15 downto 0);
pulse_notpresent : in std_logic; -- empty signal from fifo
pulse_inpipe : in std_logic;
pulse_read : out std_logic; -- read from FWFT fifo
packet_firstword : out std_logic;
packet_lastword : out std_logic;
packet_datawrite : out std_logic;
+ packet_inpipe : out std_logic;
packet_fifofull : in std_logic;
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0));
+ error : out std_logic
+ );
end FEE_combine_data;
architecture Behavioral of FEE_combine_data is
signal packet_lastword_S : std_logic;
signal packet_firstword_S : std_logic := '1';
-
---signal delay_inpipe_pulse_S : std_logic := '0';
---signal delay_inpipe_wave_S : std_logic := '0';
-
signal wave_read0_S : std_logic := '0';
signal wave_read_S : std_logic := '0';
signal superburst_S : std_logic_vector (15 downto 0);
signal timestamp_S : std_logic_vector (15 downto 0);
signal statusbyte_S : std_logic_vector (7 downto 0);
---signal channel_S : std_logic_vector (7 downto 0);
+signal channel_S : std_logic_vector (7 downto 0);
signal energy_S : std_logic_vector (15 downto 0);
signal CF_before_S : std_logic_vector (15 downto 0);
signal CF_after_S : std_logic_vector (15 downto 0);
-signal waveisolder_S : std_logic := '0';
+attribute mark_debug : string;
+-- attribute mark_debug of wave_notpresent : signal is "true";
+-- attribute mark_debug of wave_inpipe : signal is "true";
+-- attribute mark_debug of wave_read : signal is "true";
+-- attribute mark_debug of tx_state_S : signal is "true";
+-- attribute mark_debug of error_S : signal is "true";
+-- attribute mark_debug of statusbyte_S : signal is "true";
+-- attribute mark_debug of pulse_read_S : signal is "true";
+
+-- attribute mark_debug of pulse_data : signal is "true";
+-- attribute mark_debug of pulse_notpresent : signal is "true";
+-- attribute mark_debug of pulse_inpipe : signal is "true";
+-- attribute mark_debug of pulse_read : signal is "true";
+
+
+-- attribute mark_debug of energy_S : signal is "true";
+-- attribute mark_debug of crc8_data_in_S : signal is "true";
+-- attribute mark_debug of crc8_data_in_valid_S : signal is "true";
+-- attribute mark_debug of crc8_data_in_last_S : signal is "true";
+-- attribute mark_debug of packet_data_out : signal is "true";
+-- attribute mark_debug of crc8_data_out_valid_S : signal is "true";
+-- attribute mark_debug of crc8_data_out_last_S : signal is "true";
+-- attribute mark_debug of packet_firstword : signal is "true";
+-- attribute mark_debug of packet_lastword : signal is "true";
+-- attribute mark_debug of packet_datawrite : signal is "true";
+-- attribute mark_debug of packet_fifofull : signal is "true";
+-- attribute mark_debug of packet_inpipe : signal is "true";
+-- attribute mark_debug of crc8_reset_S : signal is "true";
+-- attribute mark_debug of crc8_clear_S : signal is "true";
+-- attribute mark_debug of crc8_writeword_S : signal is "true";
+-- attribute mark_debug of prev_crc8_data_out_valid_S : signal is "true";
+-- attribute mark_debug of prev_crc8_data_out_last_S : signal is "true";
+
+
begin
error <= error_S;
-
+packet_inpipe <= '1' when
+ (((pulse_inpipe='1') and (enable_waveform='0')) or ((wave_inpipe='1') and (enable_waveform='1')) or (tx_state_S/=idle))
+ or (((pulse_notpresent='0') and (enable_waveform='0')) or (slowcontrol_notpresent='0') or ((wave_notpresent='0') and (enable_waveform='1')))
+ or ((crc8_writeword_S='1') or (crc8_data_out_valid_S='1'))
+ else '0';
+
crc8_data_in_valid_S <= '1' when (crc8_writeword_S='1') and (packet_fifofull='0') else '0';
crc8_reset_S <= '1' when (crc8_clear_S='1') or (reset='1') else '0';
crc8check: crc8_add_check32 port map(
pulse_read <= pulse_read_S;
slowcontrol_read <= slowcontrol_read_S;
---process(clock)
---variable inpipe_counter_V : integer range 0 to INPIPE_DELAY := 0;
---begin
--- if rising_edge(clock) then
--- if reset='1' then
--- inpipe_counter_V := 0;
--- delay_inpipe_pulse_S <= '0';
--- else
--- if (pulse_read_S='1') or -- and (dfifo_prog_empty_S(index)='1')) or
--- (wave_read_S='1') -- and (dfifo_prog_empty_S(index_other)='1'))
--- then
--- inpipe_counter_V := INPIPE_DELAY;
--- delay_inpipe_pulse_S <= '1';
--- else
--- if inpipe_counter_V/=0 then
--- inpipe_counter_V := inpipe_counter_V-1;
--- delay_inpipe_pulse_S <= '1';
--- else
--- delay_inpipe_pulse_S <= '0';
--- end if;
--- end if;
--- end if;
--- end if;
---end process;
---
---process(clock)
---variable inpipe_counter_V : integer range 0 to INPIPE_DELAY := 0;
---begin
--- if rising_edge(clock) then
--- if reset='1' then
--- inpipe_counter_V := 0;
--- delay_inpipe_wave_S <= '0';
--- else
--- if (wave_read_S='1') or -- and (dfifo_prog_empty_S(index)='1')) or
--- (pulse_read_S='1') -- and (dfifo_prog_empty_S(index_other)='1'))
--- then
--- inpipe_counter_V := INPIPE_DELAY;
--- delay_inpipe_wave_S <= '1';
--- else
--- if inpipe_counter_V/=0 then
--- inpipe_counter_V := inpipe_counter_V-1;
--- delay_inpipe_wave_S <= '1';
--- else
--- delay_inpipe_wave_S <= '0';
--- end if;
--- end if;
--- end if;
--- end if;
---end process;
-waveisolder_S <= '1' when ((wave_data(31 downto 16)<pulse_data(31 downto 16)) and (not ((wave_data(31 downto 30)="00") and (pulse_data(31 downto 30)="11")))) or
- ((wave_data(31 downto 16)=pulse_data(31 downto 16)) and (wave_data(15 downto 0)<pulse_data(15 downto 0)))
+wave_read_S <= '1' when
+ ((enable_waveform='0') and (wave_notpresent='0'))
+ or ((enable_waveform='1') and (tx_state_S=idle) and (wave_notpresent='0') and (slowcontrol_notpresent='1'))
+ or ((tx_state_S=wave0) and (wave_notpresent='0'))
+ or ((tx_state_S=wave2) and (wave_notpresent='0') and (wave_data(35 downto 32)/="0000"))
else '0';
-\r
-wave_read_S <= '1' when (wave_data(35 downto 32)/="0000") and (tx_state_S=idle) and (wave_notpresent='0') else wave_read0_S;\r
+
+-- wave_read_S <= '1' when
+ -- ((wave_data(35 downto 32)/="0000") and (tx_state_S=idle) and (wave_notpresent='0'))
+ -- or ((enable_waveform='0') and (wave_notpresent='0'))
+ -- else wave_read0_S;\r
-wave_read0_S <= '1' when (wave_notpresent='0') and (packet_fifofull='0') and
- (((pulse_notpresent='0') or (pulse_inpipe='0')) or (tx_state_S/=idle)) and
- ((tx_state_S=wave0) or (tx_state_S=wave2) or
- ((tx_state_S=idle) and (slowcontrol_notpresent='1') and ((pulse_notpresent='1') or (waveisolder_S='1'))))
- else '0';
+-- wave_read0_S <= '1' when
+ -- (wave_notpresent='0') and (packet_fifofull='0') and (enable_waveform='1') and (tx_state_S/=idle)
+ -- and ((tx_state_S=wave0) or (tx_state_S=wave2) or ((tx_state_S=idle) and (slowcontrol_notpresent='1')))
+ -- else '0';
-pulse_read_S <= '1' when (pulse_data(35 downto 34)/="00") and (tx_state_S=idle) and (pulse_notpresent='0') else pulse_read0_S;\r
+pulse_read_S <= '1' when ((tx_state_S=idle) and (pulse_notpresent='0'))
+ or ((enable_waveform='1') and (pulse_notpresent='0')) else pulse_read0_S;\r
-pulse_read0_S <= '1' when (pulse_notpresent='0') and (packet_fifofull='0') and
- ((wave_notpresent='0') or (wave_inpipe='0') or (tx_state_S/=idle)) and
- ((tx_state_S=data0) or (tx_state_S=data1) or
- ((tx_state_S=idle) and (slowcontrol_notpresent='1') and ((wave_notpresent='1') or (waveisolder_S='0'))))
+pulse_read0_S <= '1' when
+ (pulse_notpresent='0') and (packet_fifofull='0') and (enable_waveform='0')
+ and ((tx_state_S=idle) and (slowcontrol_notpresent='1'))
else '0';
slowcontrol_read_S <= '1' when (slowcontrol_notpresent='0') and (packet_fifofull='0') and (tx_state_S=idle) else '0';
else
crc8_data_in_last_S <= '0';
end if;
-
- if pulse_read_S='1' then
- if pulse_data(35 downto 34)="00" then
- error_S <= '0';
--- channel_S(0) <= pulse_data(33);
- if pulse_data(32)='1' then
- statusbyte_S <= STATBYTE_FEEPULSESKIPPED;
- else
- statusbyte_S <= x"00";
- end if;
- superburst_S <= pulse_data(31 downto 16);
- timestamp_S <= pulse_data(15 downto 0);
- tx_state_S <= data0;
- else
- error_S <= '1';
- end if;
+ if (enable_waveform='0') and (pulse_read_S='1') then
+ error_S <= '0';
+ tx_state_S <= data0;
elsif slowcontrol_read_S='1' then
error_S <= '0';
tx_state_S <= slow0;
- elsif wave_read_S='1' then
+ elsif (enable_waveform='1') and (wave_read_S='1') then
if wave_data(35 downto 32)="0000" then
superburst_S <= wave_data(31 downto 16);
timestamp_S <= wave_data(15 downto 0);
else
end if;
when data0 =>
- if pulse_read_S='1' then
- timeoutcounter_V := 0;
- if pulse_data(35 downto 34)="01" then
--- channel_S(7 downto 0) <= pulse_data(23 downto 16);
- energy_S <= pulse_data(15 downto 0);
- crc8_data_in_S <= x"DA" & pulse_data(23 downto 16) & superburst_S;
- crc8_writeword_S <= '1';
- crc8_data_in_last_S <= '0';
- tx_state_S <= data1;
- else
- error_S <= '1';
- tx_state_S <= init;
+ statusbyte_S <= pulse_status;
+ channel_S <= pulse_channel;
+ superburst_S <= pulse_superburst(15 downto 0);
+ timestamp_S <= pulse_timestamp;
+ energy_S <= pulse_energy;
+ CF_before_S <= pulse_CFvalbefore;
+ CF_after_S <= pulse_CFvalafter;
+-- if packet_fifofull='0' then
+ if (NROFFEEFPGAS=1) or (GEO='0') then
+ crc8_data_in_S <= x"DA" & pulse_channel & pulse_superburst(15 downto 0);
+ else -- map ADC channel number to higher level
+ crc8_data_in_S <= x"DA" & pulse_channel+conv_std_logic_vector(NROFFEEADCS,8) & pulse_superburst(15 downto 0);
end if;
- else
- if timeoutcounter_V/=15 then
- timeoutcounter_V := timeoutcounter_V+1;
- else
- error_S <= '1';
- tx_state_S <= init;
- end if;
- end if;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= data1;
+-- end if;
when data1 =>
- if pulse_read_S='1' then
- timeoutcounter_V := 0;
- if pulse_data(35 downto 34)="10" then
- CF_before_S <= pulse_data(31 downto 16);
- CF_after_S <= pulse_data(15 downto 0);
- crc8_data_in_S <= x"0000" & energy_S;
- crc8_writeword_S <= '1';
- crc8_data_in_last_S <= '0';
- tx_state_S <= data2;
- else
- error_S <= '1';
- tx_state_S <= init;
- end if;
- else
- if timeoutcounter_V/=15 then
- timeoutcounter_V := timeoutcounter_V+1;
- else
- error_S <= '1';
- tx_state_S <= init;
- end if;
+ if packet_fifofull='0' then
+ crc8_data_in_S <= timestamp_S & energy_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= data2;
end if;
when data2 =>
- crc8_data_in_S <= CF_before_S & CF_after_S;
- crc8_writeword_S <= '1';
- crc8_data_in_last_S <= '0';
- crc8_lastword_S <= timestamp_S & statusbyte_S & x"00";
- crc8_lastwrite_S <= '1';
- tx_state_S <= idle;
-
+ if packet_fifofull='0' then
+ crc8_data_in_S <= CF_before_S & CF_after_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ crc8_lastword_S <= x"0000" & statusbyte_S & x"00";
+ crc8_lastwrite_S <= '1';
+ tx_state_S <= idle;
+ end if;
when wave0 =>
if wave_read_S='1' then
timeoutcounter_V := 0;
if wave_data(35 downto 32)="0001" then
statusbyte_S <= wave_data(31 downto 24);
--- channel_S <= wave_data(7 downto 0);
else
error_S <= '1';
tx_state_S <= init;
end if;
- crc8_data_in_S <= x"AF" & wave_data(7 downto 0) & superburst_S;
+-- channel_S <= wave_data(7 downto 0);
+ if (NROFFEEFPGAS=1) or (GEO='0') then
+ crc8_data_in_S <= x"AF" & wave_data(7 downto 0) & superburst_S;
+ else -- map ADC channel number to higher level
+ crc8_data_in_S <= x"AF" & wave_data(7 downto 0)+conv_std_logic_vector(NROFFEEADCS,8) & superburst_S;
+ end if;
crc8_writeword_S <= '1';
crc8_data_in_last_S <= '0';
tx_state_S <= wave1;
end if;
end if;
end process datahandling;
-
-\r
-\r
-\r
-testword0(3 downto 0) <= pulse_data(35 downto 32);
-testword0(4) <= pulse_notpresent;
-testword0(5) <= pulse_inpipe;
-testword0(6) <= pulse_read_S;
-testword0(7) <= pulse_read0_S;
-\r
-testword0(11 downto 8) <= wave_data(35 downto 32);
-testword0(12) <= wave_notpresent;
-testword0(13) <= wave_inpipe;
-testword0(14) <= wave_read_S;
-testword0(15) <= wave_read0_S;
-\r
-testword0(19 downto 16) <= \r
- x"0" when tx_state_S=init else\r
- x"1" when tx_state_S=idle else\r
- x"2" when tx_state_S=data0 else\r
- x"3" when tx_state_S=data1 else\r
- x"4" when tx_state_S=data2 else\r
- x"5" when tx_state_S=wave0 else\r
- x"6" when tx_state_S=wave1 else\r
- x"7" when tx_state_S=wave2 else\r
- x"8" when tx_state_S=slow0 else\r
- x"f";\r
-
-testword0(20) <= waveisolder_S;\r
-testword0(21) <= crc8_reset_S;\r
-testword0(22) <= crc8_clear_S;\r
-testword0(23) <= crc8_data_in_valid_S;\r
-testword0(24) <= crc8_data_in_last_S;\r
-testword0(25) <= crc8_writeword_S;\r
-testword0(26) <= crc8_data_out_valid_S;\r
-testword0(27) <= crc8_data_out_last_S;\r
-testword0(28) <= '0';\r
-testword0(29) <= crc8_lastwrite_S;\r
-testword0(30) <= slowcontrol_notpresent;\r
-testword0(31) <= slowcontrol_read_S;\r
-testword0(32) <= packet_datawrite_S;\r
-testword0(33) <= packet_lastword_S;\r
-testword0(34) <= packet_firstword_S;\r
-\r
\r
-testword0(35) <= error_S;\r
-\r
\r
end Behavioral;\r
\r
-----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
--- Engineer: Peter Schakel
--- Create Date: 30-01-2012
--- Module Name: FEE_dual_pulse_waveform
--- Description: Module to detect pulses and outputs them as waveforms with single pulse or pile-up, dual gain inputs
--- Modifications:
--- 08-09-2014 Added: Constant Fraction values before and after zero-crossing
--- 16-09-2014 name changed from dual_pulse_waveform to FEE_dual_pulse_waveform
--- 22-09-2014 single clock
--- 24-09-2014 enable_highgain and enable_lowgain inputs added
--- 10-10-2014 Integral as measurement for the energy instead of maximum
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.std_logic_ARITH.ALL;
-use IEEE.std_logic_UNSIGNED.ALL;
-
-
-------------------------------------------------------------------------------------------------------
--- FEE_dual_pulse_waveform
--- Module to detect pulses and outputs them as waveforms with single pulse or pile-up
--- Two ADC inputs, one for the high gain and one for the low gain are corrected for baseline fluctuations.
--- If a pulse or pileup is detected at the low-gain input, the high-gain input is ignored.
--- Pulses are detected: check if the ADC signal is above the adjustable tresshold.
--- The samples are stored in buffer memory as waveform.
--- The actual superburst-number and a timestamp within the superburst is added.
--- Waveforms longer than an adjustable duration are treated as pileup waveforms,
--- waveforms shorter than this, but longer as an adjustable minimum duration are tested for Integral/Maximum ratio:
--- The waveform is discarded if the maximum multiplied with IdivMAX_discard value is larger than the integral.
--- The waveform is regarded as pileup if the maximum multiplied with IdivMAX_pileup value is smaller than the integral.
--- From the single pulse waveforms the Constant Fraction values before and after the zero-crossing are put in the
--- resulting packet, as well as two successive samples containing the maximum of the pulse.
---
---
--- generics
--- ADCBITS : number of ADC-bits
--- BWBITS : number of bits for the IIR filter bandwidth
--- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
--- IDIVMAXBITS : number of bits for maximum to integral ratio check
--- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
--- CF_DELAYBITS : number of bits for the Constant Fraction delay
---
--- inputs
--- clock : clock
--- reset : synchrounous reset
--- enable : enable pulse detection
--- superburstnumber : actual superburstnumber
--- timestampcounter : timestampcounter within superburst
--- ADCdata_highgain : ADC signal from the high-gain input
--- ADCdata_lowgain : ADC signal from the low-gain input
--- threshold_highgain : threshold above baseline for start of pulse (high gain)
--- threshold_lowgain : threshold above baseline for start of pulse (low gain)
--- enable_highgain : enable high gain input
--- enable_lowgain : enable low gain input
--- IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
--- maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline
--- minpulselength : number of samples below which the pulse is ignored
--- pileuplength : number of samples above which the pulse is treated as pileup
--- maxwavelength : maximum number of samples that can be saved in one waveform
--- IdivMAX_discard : when this value multiplied with the maximum is larger than the integral then the waveform is discarded
--- IdivMAX_pileup : when this value multiplied with the maximum is smaller than the integral then the waveform is regarded as pileup
--- fullsize_wave_highgain : take waveforms with maximum size for highgain input
--- fullsize_wave_lowgain : take waveforms with maximum size for lowgain input
--- pulsedata_allowed : writing of pulse 36-bits data result allowed
--- pulsedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
--- pileupdata_allowed : writing of pileup 36-bits data result allowed
--- pileupdata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
---
--- outputs
--- ADC_minus_baseline_highgain : baseline compensated signal from high gain input, signed
--- ADC_minus_baseline_lowgain : baseline compensated signal from low gain input, signed
--- pulsedata_write : write 36-bits pulse data result
--- pulsedata_out : 36-bits pulse data result:
--- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
--- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
--- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
--- pileupdata_write : write 36-bits pileup data result
--- pileupdata_out : 36-bits pileup data result:
--- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
--- bits(35..32)="0001" :
--- bits(31..24) = statusbyte
--- bits(23..8) = 0
--- bits(7..0) = adcnumber (channel identification)
--- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
--- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
--- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
--- pulsedetect : indicates if a pulse (regular or pileup) is detected on the high or low-gain input
--- overflow : pulse or pileup waveform is lost
---
--- Components:
--- FEE_baselinefollower_eventdetector : baseline follower with detection of pulse
--- FEE_pileup_check : check length of pulse and Maximum/Integral ratio to determine if pileup occurred
--- FEE_extract_pulse : perform maximum check and constant fraction
--- FEE_pulsewaveform_buffer : buffer for waveform data, timestamps arre added
--- FEE_waveform_to_36bits : convert waveform data to 36-bits wide data stream
--- FEE_wavemux2to1 : select next waveform, based on timestamp
--- FEE_pulse2to1_pulse : combine hits from high and low gain ADC inputs to one data packet stream
---
-------------------------------------------------------------------------------------------------------
-
-
-
-entity FEE_dual_pulse_waveform is
- generic (
- ADCBITS : natural := 14;
- BWBITS : natural := 10;
- WAVEFORMBUFFERSIZE : natural := 11;
- IDIVMAXBITS : natural := 6;
- INTEGRALRATIOBITS : natural := 3;
- CF_DELAYBITS : natural := 8
- );
- Port (
- clock : in std_logic;
- reset : in std_logic;
- enable : in std_logic;
- adcnumber : in std_logic_vector(7 downto 0);
- cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
- superburstnumber : in std_logic_vector(30 downto 0);
- timestampcounter : in std_logic_vector(15 downto 0);
- ADCdata_highgain : in std_logic_vector((ADCBITS-1) downto 0);
- ADCdata_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
- threshold_highgain : in std_logic_vector((ADCBITS-1) downto 0);
- threshold_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
- enable_highgain : in std_logic;
- enable_lowgain : in std_logic;
- IIRfilterBW : in std_logic_vector(2 downto 0);
- maxabovebaseline : in std_logic_vector(3 downto 0);
- minpulselength : in std_logic_vector(7 downto 0);
- pileuplength : in std_logic_vector(7 downto 0);
- maxwavelength : in std_logic_vector(7 downto 0);
- IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);
- IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);
- fullsize_wave_highgain : in std_logic;
- fullsize_wave_lowgain : in std_logic;
- ADC_minus_baseline_highgain : out std_logic_vector(ADCBITS downto 0);
- ADC_minus_baseline_lowgain : out std_logic_vector(ADCBITS downto 0);
- pulsedata_allowed : in std_logic;
- pulsedata_almostfull : in std_logic;
- pulsedata_write : out std_logic;
- pulsedata_out : out std_logic_vector(35 downto 0);
- pileupdata_allowed : in std_logic;
- pileupdata_almostfull : in std_logic;
- pileupdata_write : out std_logic;
- pileupdata_out : out std_logic_vector(35 downto 0);
- pulsedetect : out std_logic;
- overflow : out std_logic;
- testword0 : out std_logic_vector(35 downto 0);
- testword1 : out std_logic_vector(35 downto 0);
- testword2 : out std_logic_vector(35 downto 0)
- );
-end FEE_dual_pulse_waveform;
-
-architecture Behavioral of FEE_dual_pulse_waveform is
-
-component FEE_baselinefollower_eventdetector is
- generic (
- ADCBITS : natural := ADCBITS;
- BWBITS : natural := BWBITS
- );
- port (
- clock : in std_logic;
- reset : in std_logic;
- enable : in std_logic;
- ADCdata : in std_logic_vector((ADCBITS-1) downto 0);
- threshold : in std_logic_vector((ADCBITS-1) downto 0);
- IIRfilterBW : in std_logic_vector(2 downto 0);
- maxabovebaseline : in std_logic_vector(3 downto 0);
- baseline : out std_logic_vector((ADCBITS-1) downto 0);
- ADC_delayed : out std_logic_vector(ADCBITS-1 downto 0);
- ADC_minus_baseline : out std_logic_vector(ADCBITS downto 0);
- baseline_inhibit : out std_logic;
- pulse_active : out std_logic;
- pulse_rising : out std_logic;
- max_data : out std_logic_vector(ADCBITS-1 downto 0)
- );
-end component;
-
-component FEE_pileup_check is
- generic (
- ADCBITS : natural := ADCBITS;
- IDIVMAXBITS : natural := IDIVMAXBITS;
- INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS
- );
- Port (
- clock : in std_logic;
- reset : in std_logic;
- superburstnumber : in std_logic_vector(30 downto 0);
- timestampcounter : in std_logic_vector(15 downto 0);
- ADC_highgain : in std_logic_vector(ADCBITS downto 0); -- signed
- enable_highgain : in std_logic;
- max_data_highgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
- pulse_active_highgain : in std_logic;
- pulse_rising_highgain : in std_logic;
- clipping_highgain : in std_logic;
- ADC_lowgain : in std_logic_vector(ADCBITS downto 0); -- signed
- enable_lowgain : in std_logic;
- max_data_lowgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
- pulse_active_lowgain : in std_logic;
- pulse_rising_lowgain : in std_logic;
- minpulselength : in std_logic_vector(7 downto 0);
- pileuplength : in std_logic_vector(7 downto 0);
- maxwavelength : in std_logic_vector(7 downto 0);
- IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);
- IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);
- fullsize_wave_highgain : in std_logic;
- fullsize_wave_lowgain : in std_logic;
- pulse_valid_highgain : out std_logic;
- singlepulse_highgain : out std_logic;
- pileuppulse_highgain : out std_logic;
- clearpulse_highgain : out std_logic;
+----------------------------------------------------------------------------------\r
+-- Company: KVI-cart/RUG/Groningen University\r
+-- Engineer: Peter Schakel\r
+-- Create Date: 30-01-2012\r
+-- Module Name: FEE_dual_pulse_waveform\r
+-- Description: Module to detect pulses and outputs them as waveforms with single pulse or pile-up, dual gain inputs\r
+-- Modifications:\r
+-- 08-09-2014 Added: Constant Fraction values before and after zero-crossing\r
+-- 16-09-2014 name changed from dual_pulse_waveform to FEE_dual_pulse_waveform\r
+-- 22-09-2014 single clock\r
+-- 24-09-2014 enable_highgain and enable_lowgain inputs added\r
+-- 10-10-2014 Integral as measurement for the energy instead of maximum\r
+-- 24-04-2015 Moving Window Deconvolution added\r
+-- 19-08-2015 Force_hit added: force waveform acquisition with SODA command\r
+-- 23-10-2015 wavedata_inpipe added, earlier reading of data, outputs data when available \r
+-- 28-10-2016 Enable_waveform input added\r
+-- 23-02-2017 Parallel data from Feature Extraction instead of 36-bits\r
+-- 05-04-2017 Pileup correction, added second MWD, optimized for area, \r
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+use IEEE.std_logic_ARITH.ALL;\r
+use IEEE.std_logic_UNSIGNED.ALL;\r
+USE work.panda_package.all;\r
+\r
+\r
+------------------------------------------------------------------------------------------------------\r
+-- FEE_dual_pulse_waveform\r
+-- Module to detect and analyse pulses and outputs them with data that determines time and energy.\r
+-- There is also a mode in which the pulses are passed on as waveforms.\r
+-- Two ADC inputs, one for the high gain and one for the low gain are corrected for baseline fluctuations.\r
+-- If a pulse at the high-gain input is clipping, the result of the low-gain input is taken.\r
+-- Pulses are detected: check if the ADC signal is above the adjustable tresshold.\r
+-- The samples are also stored in buffer memory as waveform.\r
+-- The actual superburst-number and a timestamp within the superburst is added.\r
+-- Waveforms longer than an adjustable duration are treated as pileup : parallel processed with shorter detection settings (MWD and CF).\r
+-- Waveforms shorter than this, but longer as an adjustable minimum duration are tested for Integral/Maximum ratio:\r
+-- The waveform is discarded if the maximum multiplied with IdivMAX_discard value is larger than the integral.\r
+-- The waveform is regarded as pileup if the maximum multiplied with IdivMAX_pileup value is smaller than the integral.\r
+-- The integral value determines the energy.\r
+-- From the single pulse waveforms and the pileup pulses the Constant Fraction values before and after the zero-crossing are put in the\r
+-- resulting packet.\r
+--\r
+--\r
+-- generics\r
+-- ADCNUMBER : number of the ADC to put in the resulting data\r
+-- ADCBITS : number of ADC-bits\r
+-- BASELINE_BWBITS : number of bits for the IIR filter bandwidth\r
+-- MWD_WIDTHBITS : number of bits for the width\r
+-- MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations\r
+-- MWD2_WIDTHBITS : number of bits for the width of second MWD\r
+-- MWD2_SCALEBITS : number of bits for tau factor for second MWD, also scaling for calculations\r
+-- MWD_DOUBLEFILTER : two MWD filters in series for single pulses\r
+-- MWD_PU_DOUBLEFILTER : two MWD filters in series for pileup\r
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size\r
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check\r
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)\r
+-- MAXPILEUPHITS : maximum number of hits in one pileup waveform\r
+-- CF_DELAYBITS : number of bits for the Constant Fraction delay\r
+-- NOWAVEFORMS : produce hit results, do not produce waveforms\r
+-- \r
+-- inputs\r
+-- clock : clock\r
+-- reset : synchrounous reset\r
+-- enable : enable pulse detection\r
+-- enable_waveform : outputs waveforms and not feature extraction data\r
+-- force_hit : force hit at input\r
+-- CF_delay : delay for the Constant Fraction method for single pulses\r
+-- CFpu_delay : delay for the Constant Fraction method for pileup pulses\r
+-- superburstnumber : actual superburstnumber\r
+-- superburstupdate : new superburstnumber\r
+-- ADCdata_highgain : ADC signal from the high-gain input\r
+-- ADCdata_lowgain : ADC signal from the low-gain input\r
+-- MWD1_width : width of the first MWD filter\r
+-- MWD1_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for first single pulse MWD\r
+-- MWD2_width : width of the second MWD filter\r
+-- MWD2_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for second single pulse MWD\r
+-- MWDpu1_width : width of the first pileup MWD filter\r
+-- MWDpu1_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for first pileup MWD\r
+-- MWDpu2_width : width of the second pileup MWD filter\r
+-- MWDpu2_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for second pileup MWD\r
+-- threshold_highgain : threshold above baseline for start of pulse (high gain)\r
+-- threshold_lowgain : threshold above baseline for start of pulse (low gain)\r
+-- enable_highgain : enable high gain input\r
+-- enable_lowgain : enable low gain input\r
+-- enable_rawdata : send raw data in waveform instead of baseline corrected data\r
+-- IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BASELINE_BWBITS)/samplefrequency)\r
+-- maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline \r
+-- minpulselength : number of samples below which the pulse is ignored\r
+-- pileuplength : number of samples above which the pulse is treated as pileup\r
+-- maxwavelength : maximum number of samples that can be saved in one waveform\r
+-- IdivMAX_discard : when this value multiplied with the maximum is larger than the integral then the waveform is discarded\r
+-- IdivMAX_pileup : when this value multiplied with the maximum is smaller than the integral then the waveform is regarded as pileup\r
+-- fullsize_wave_highgain : take waveforms with maximum size for highgain input\r
+-- fullsize_wave_lowgain : take waveforms with maximum size for lowgain input\r
+-- pulsedata_allowed : writing of pulse 36-bits data result allowed\r
+-- pulsedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform\r
+-- wavedata_allowed : writing of pileup 36-bits data result allowed\r
+-- wavedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform\r
+-- \r
+-- outputs\r
+-- pulsedata_write : write 36-bits pulse data result\r
+-- pulsedata_lowgain : high or low gain channel\r
+-- pulsedata_superburst : superburstnumber\r
+-- pulsedata_timestamp : time within superburst\r
+-- pulsedata_energy : energy of the hit\r
+-- pulsedata_CFvalbefore : Constant Fraction result: sample before zero-crossing\r
+-- pulsedata_CFvalafter : Constant Fraction result: sample after zero-crossing\r
+-- pulsedata_status : status byte\r
+-- wavedata_available : waveform data available\r
+-- wavedata_write : write 36-bits pileup data result\r
+-- wavedata_out : 36-bits pileup data result:\r
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
+-- bits(35..32)="0001" : \r
+-- bits(31..24) = statusbyte \r
+-- bits(23..8) = 0\r
+-- bits(7..0) = adcnumber (channel identification)\r
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
+-- pulsedetect : indicates if a pulse (regular or pileup) is detected on the high or low-gain input\r
+-- overflow : pulse or pileup waveform is lost\r
+-- error : error occured\r
+--\r
+-- Components:\r
+-- FEE_baselinefollower_eventdetector : baseline follower with detection of pulse\r
+-- FEE_pileup_check : check length of pulse and Maximum/Integral ratio to determine if pileup occurred\r
+-- FEE_pulse_detect : detect pulse for pileup data\r
+-- FEE_extract_pulse : perform maximum check and constant fraction\r
+-- FEE_collect_pileup_pulses : Collect results of Feature Extraction for pileup pulses\r
+-- FEE_pulsewaveform_buffer : buffer for waveform data, timestamps arre added\r
+-- FEE_waveform_to_36bits : convert waveform data to 36-bits wide data stream \r
+-- FEE_wavemux2to1 : select next waveform, based on timestamp\r
+--\r
+------------------------------------------------------------------------------------------------------\r
+\r
+\r
+\r
+entity FEE_dual_pulse_waveform is\r
+ generic (\r
+ ADCNUMBER : natural := 0;\r
+ ADCBITS : natural := 14;\r
+ BASELINE_BWBITS : natural := 10;\r
+ MWD_WIDTHBITS : natural := 5;\r
+ MWD_SCALEBITS : natural := 16;\r
+ MWD2_WIDTHBITS : natural := 2;\r
+ MWD2_SCALEBITS : natural := 16;\r
+ MWD_DOUBLEFILTER : boolean := false;\r
+ MWD_PU_DOUBLEFILTER : boolean := false;\r
+ WAVEFORMBUFFERSIZE : natural := 11;\r
+ IDIVMAXBITS : natural := 6;\r
+ INTEGRALRATIOBITS : natural := 3;\r
+ CF_DELAYBITS : natural := 8;\r
+ MAXPILEUPHITS : natural := 3;\r
+ NOWAVEFORMS : boolean := false\r
+ );\r
+ Port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ enable : in std_logic;\r
+ enable_waveform : in std_logic;\r
+ force_hit : in std_logic;\r
+ CF_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);\r
+ CFpu_delay : in std_logic_vector(1 downto 0);\r
+ superburstnumber : in std_logic_vector(30 downto 0); \r
+ superburstupdate : in std_logic; \r
+ ADCdata_highgain : in std_logic_vector(ADCBITS-1 downto 0);\r
+ ADCdata_lowgain : in std_logic_vector(ADCBITS-1 downto 0);\r
+ MWD1_width : in std_logic_vector(MWD_WIDTHBITS-1 downto 0);\r
+ MWD1_tau_factor : in std_logic_vector(MWD_SCALEBITS-1 downto 0);\r
+ MWD2_width : in std_logic_vector(MWD2_WIDTHBITS-1 downto 0);\r
+ MWD2_tau_factor : in std_logic_vector(MWD2_SCALEBITS-1 downto 0);\r
+ MWDpu1_width : in std_logic_vector(1 downto 0);\r
+ MWDpu1_tau_factor : in std_logic_vector(MWD_SCALEBITS-1 downto 0);\r
+ MWDpu2_width : in std_logic_vector(MWD2_WIDTHBITS-1 downto 0);\r
+ MWDpu2_tau_factor : in std_logic_vector(MWD2_SCALEBITS-1 downto 0);\r
+ threshold_highgain : in std_logic_vector(ADCBITS-1 downto 0);\r
+ threshold_lowgain : in std_logic_vector(ADCBITS-1 downto 0);\r
+ enable_highgain : in std_logic;\r
+ enable_lowgain : in std_logic;\r
+ enable_rawdata : in std_logic;\r
+ IIRfilterBW : in std_logic_vector(2 downto 0);\r
+ maxabovebaseline : in std_logic_vector(3 downto 0);\r
+ minpulselength : in std_logic_vector(7 downto 0);\r
+ pileuplength : in std_logic_vector(7 downto 0);\r
+ maxwavelength : in std_logic_vector(7 downto 0);\r
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
+ fullsize_wave_highgain : in std_logic;\r
+ fullsize_wave_lowgain : in std_logic;\r
+ pulsedata_allowed : in std_logic;\r
+ pulsedata_write : out std_logic;\r
+ pulsedata_lowgain : out std_logic;\r
+ pulsedata_superburst : out std_logic_vector(30 downto 0);\r
+ pulsedata_timestamp : out std_logic_vector(15 downto 0);\r
+ pulsedata_energy : out std_logic_vector(15 downto 0);\r
+ pulsedata_CFvalbefore : out std_logic_vector(15 downto 0);\r
+ pulsedata_CFvalafter : out std_logic_vector(15 downto 0);\r
+ pulsedata_status : out std_logic_vector(7 downto 0);\r
+ wavedata_allowed : in std_logic;\r
+ wavedata_almostfull : in std_logic;\r
+ wavedata_available : out std_logic;\r
+ wavedata_write : out std_logic;\r
+ wavedata_out : out std_logic_vector(35 downto 0);\r
+ pulsedetect : out std_logic;\r
+ overflow : out std_logic;\r
+ error : out std_logic\r
+ );\r
+end FEE_dual_pulse_waveform;\r
+\r
+architecture Behavioral of FEE_dual_pulse_waveform is\r
+\r
+component FEE_baselinefollower_eventdetector is\r
+ generic (\r
+ ADCBITS : natural := ADCBITS;\r
+ BASELINE_BWBITS : natural := BASELINE_BWBITS;\r
+ MWD_WIDTHBITS : natural := MWD_WIDTHBITS;\r
+ MWD_SCALEBITS : natural := MWD_SCALEBITS;\r
+ MWD2_WIDTHBITS : natural := MWD2_WIDTHBITS;\r
+ MWD2_SCALEBITS : natural := MWD2_SCALEBITS;\r
+ MWD_DOUBLEFILTER : boolean := MWD_DOUBLEFILTER\r
+ );\r
+ port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ enable : in std_logic;\r
+ ADCdata : in std_logic_vector(ADCBITS-1 downto 0);\r
+ MWD1_width : in std_logic_vector((MWD_WIDTHBITS-1) downto 0);\r
+ MWD1_tau_factor : in std_logic_vector((MWD_SCALEBITS-1) downto 0);\r
+ MWD2_width : in std_logic_vector(MWD2_WIDTHBITS-1 downto 0);\r
+ MWD2_tau_factor : in std_logic_vector((MWD2_SCALEBITS-1) downto 0);\r
+ threshold : in std_logic_vector(ADCBITS-1 downto 0);\r
+ IIRfilterBW : in std_logic_vector(2 downto 0);\r
+ maxabovebaseline : in std_logic_vector(3 downto 0);\r
+ ADC_minus_baseline : out std_logic_vector(ADCBITS downto 0);\r
+ baseline_inhibit : out std_logic;\r
+ pulse_active : out std_logic;\r
+ pulse_rising : out std_logic;\r
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)\r
+ );\r
+end component;\r
+\r
+component FEE_pileup_check is\r
+ generic (\r
+ ADCBITS : natural := ADCBITS;\r
+ IDIVMAXBITS : natural := IDIVMAXBITS;\r
+ INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS\r
+ );\r
+ Port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ superburstnumber : in std_logic_vector(30 downto 0); \r
+ timestampcounter : in std_logic_vector(15 downto 0); \r
+ force_hit : in std_logic;\r
+ ADC_highgain : in std_logic_vector(ADCBITS downto 0); -- signed\r
+ enable_highgain : in std_logic;\r
+ threshold_highgain : in std_logic_vector(ADCBITS-1 downto 0);\r
+ max_data_highgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned\r
+ pulse_active_highgain : in std_logic;\r
+ pulse_rising_highgain : in std_logic;\r
+ clipping_highgain : in std_logic;\r
+ ADC_lowgain : in std_logic_vector(ADCBITS downto 0); -- signed\r
+ enable_lowgain : in std_logic;\r
+ threshold_lowgain : in std_logic_vector(ADCBITS-1 downto 0);\r
+ max_data_lowgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned\r
+ pulse_active_lowgain : in std_logic;\r
+ pulse_rising_lowgain : in std_logic;\r
+ minpulselength : in std_logic_vector(7 downto 0);\r
+ pileuplength : in std_logic_vector(7 downto 0);\r
+ maxwavelength : in std_logic_vector(7 downto 0);\r
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
+ fullsize_wave_highgain : in std_logic;\r
+ fullsize_wave_lowgain : in std_logic;\r
+ pulse_valid_highgain : out std_logic;\r
+ singlepulse_highgain : out std_logic;\r
+ pileuppulse_highgain : out std_logic;\r
+ clearpulse_highgain : out std_logic;\r
integral_highgain : out std_logic_vector(15 downto 0);\r
pulse_valid_lowgain : out std_logic;\r
singlepulse_lowgain : out std_logic;\r
pileuppulse_lowgain : out std_logic;\r
clearpulse_lowgain : out std_logic;\r
integral_lowgain : out std_logic_vector(15 downto 0);\r
- superburst : out std_logic_vector(15 downto 0);\r
- timestamp : out std_logic_vector(15 downto 0);\r
- testword0 : out std_logic_vector(35 downto 0)
- );
-end component;
-
-\r
-component FEE_extract_pulse is
- generic (
- ADCBITS : natural := ADCBITS;
- WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
- CF_DELAYBITS : natural := CF_DELAYBITS
- );
- Port (
- clock : in std_logic;
- reset : in std_logic;
- cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
- pulse_valid : in std_logic;
- pulse_rising : in std_logic;
- pulse_detected : in std_logic;
- pileup_detected : in std_logic;
- clear_waveform : in std_logic;
- data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
+ superburst : out std_logic_vector(30 downto 0);\r
+ timestamp : out std_logic_vector(15 downto 0)\r
+ );\r
+end component;\r
+\r
+component FEE_pulse_detect is\r
+ generic (\r
+ ADCDATABITS : natural := ADCBITS;\r
+ INTEGRALBITS : natural := 0\r
+ );\r
+ Port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ ADCdata : in std_logic_vector(ADCDATABITS downto 0); -- signed\r
+ pulse_active : in std_logic;\r
+ minpulselength : in std_logic_vector(4 downto 0);\r
+ pulse_valid : out std_logic;\r
+ singlepulse : out std_logic;\r
+ integral : out std_logic_vector(15 downto 0)\r
+ );\r
+end component;\r
+\r
+component FEE_extract_pulse is\r
+ generic (\r
+ ADCBITS : natural := ADCBITS;\r
+ CF_DELAYBITS : natural := CF_DELAYBITS\r
+ );\r
+ Port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);\r
+ pulse_valid : in std_logic;\r
+ pulse_detected : in std_logic;\r
+ pileup_detected : in std_logic;\r
+ clear_waveform : in std_logic;\r
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data\r
integral : in std_logic_vector(15 downto 0);\r
- superburstnumber : in std_logic_vector(30 downto 0);
+ superburstnumber : in std_logic_vector(30 downto 0);\r
timestamp : in std_logic_vector(15 downto 0);\r
pulse_write : out std_logic;\r
- pulse_superburst : out std_logic_vector(15 downto 0);\r
+ pulse_superburst : out std_logic_vector(30 downto 0);\r
pulse_timestamp : out std_logic_vector(15 downto 0);\r
pulse_skipped : out std_logic;\r
pulse_energy : out std_logic_vector(15 downto 0);\r
pulse_CF1 : out std_logic_vector(15 downto 0);\r
pulse_CF2 : out std_logic_vector(15 downto 0)\r
);\r
-end component;
-\r
-
-component FEE_pulsewaveform_buffer is
- generic (
- ADCBITS : natural := ADCBITS;
- WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE
- );
- Port (
- clock : in std_logic;
- reset : in std_logic;
- pulse_valid : in std_logic;
- pulse_rising : in std_logic;
- pulse_detected : in std_logic;
- pileup_detected : in std_logic;
- clear_waveform : in std_logic;
- data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
- superburst : in std_logic_vector(15 downto 0);
- timestamp : in std_logic_vector(15 downto 0);
- data_out : out std_logic_vector(35 downto 0);
- data_out_read : in std_logic;
- data_out_available : out std_logic;
- overflow : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)
- );
-end component;
-
-component FEE_waveform_to_36bits is
- Port (
- clock : in std_logic;
- reset : in std_logic;
- adcnumber : in std_logic_vector(7 downto 0);
- data_in : in std_logic_vector(35 downto 0);
- data_in_available : in std_logic;
- data_in_read : out std_logic;
- overflow_in : in std_logic;
- pileupdata_out : out std_logic_vector(35 downto 0);
- pileupdata_write : out std_logic;
- pileupdata_allowed : in std_logic;
- pileupdata_almostfull : in std_logic;
- error : out std_logic;
- overflow_out : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)
- );
-end component;
-
-component FEE_wavemux2to1 is
- generic(
- TIMEOUTBITS : natural := 16
- );
- Port (
- clock : in std_logic;
- reset : in std_logic;
- data1_in : in std_logic_vector(35 downto 0);
- data1_in_write : in std_logic;
- data1_in_available : in std_logic;
- data1_in_allowed : out std_logic;
- data2_in : in std_logic_vector(35 downto 0);
- data2_in_write : in std_logic;
- data2_in_available : in std_logic;
- data2_in_allowed : out std_logic;
- data_out : out std_logic_vector(35 downto 0);
- data_out_write : out std_logic;
- data_out_available : out std_logic;
- data_out_allowed : in std_logic;
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)
- );
-end component;
-\r
-component FEE_pulse2to1_pulse is\r
- Port (
- clock : in std_logic;
- reset : in std_logic;
- channel : in std_logic_vector(7 downto 0);
- pulse1_write : in std_logic;\r
- pulse1_superburst : in std_logic_vector(15 downto 0);\r
- pulse1_timestamp : in std_logic_vector(15 downto 0);\r
- pulse1_skipped : in std_logic;\r
- pulse1_energy : in std_logic_vector(15 downto 0);\r
- pulse1_CF1 : in std_logic_vector(15 downto 0);\r
- pulse1_CF2 : in std_logic_vector(15 downto 0);\r
- pulse2_write : in std_logic;\r
- pulse2_superburst : in std_logic_vector(15 downto 0);\r
- pulse2_timestamp : in std_logic_vector(15 downto 0);\r
- pulse2_skipped : in std_logic;\r
- pulse2_energy : in std_logic_vector(15 downto 0);\r
- pulse2_CF1 : in std_logic_vector(15 downto 0);\r
- pulse2_CF2 : in std_logic_vector(15 downto 0);\r
- pulse_skipped : out std_logic;
- data_out : out std_logic_vector(35 downto 0);
- data_out_write : out std_logic;
- data_out_almostfull : in std_logic;
- data_out_allowed : in std_logic
- );
-end component;
-\r
-
-
-signal pulsedetect_S : std_logic := '0';
-
-signal pulse_active_highgain_S : std_logic := '0';
-signal pulse_rising_highgain0_S : std_logic := '0';
-signal pulse_rising_highgain_S : std_logic := '0';
-signal pulse_active_lowgain_S : std_logic := '0';
-signal pulse_rising_lowgain0_S : std_logic := '0';
-signal pulse_rising_lowgain_S : std_logic := '0';
-signal ADC_minus_baseline_highgain0_S : std_logic_vector(ADCBITS downto 0);
-signal ADC_minus_baseline_lowgain0_S : std_logic_vector(ADCBITS downto 0);
-signal ADC_minus_baseline_highgain_S : std_logic_vector(ADCBITS downto 0);
-signal ADC_minus_baseline_lowgain_S : std_logic_vector(ADCBITS downto 0);
-
-signal pulse_valid_highgain0_S : std_logic := '0';
-signal pulse_valid_highgain_S : std_logic := '0';
-signal singlepulse_highgain_S : std_logic := '0';
-signal pileuppulse_highgain_S : std_logic := '0';
-signal clearpulse_highgain_S : std_logic := '0';
-signal integral_highgain_S : std_logic_vector(15 downto 0);
-signal max_data_highgain_S : std_logic_vector(ADCBITS-1 downto 0);
-signal clipping_highgain_S : std_logic := '0';
-
-signal baseline_highgain_S : std_logic_vector(ADCBITS-1 downto 0);
-signal baseline_inhibit_highgain_S : std_logic := '0';
-signal baseline_lowgain_S : std_logic_vector(ADCBITS-1 downto 0);
-signal baseline_inhibit_lowgain_S : std_logic := '0';
-
-signal pulse_valid_lowgain0_S : std_logic := '0';
-signal pulse_valid_lowgain_S : std_logic := '0';
-signal singlepulse_lowgain_S : std_logic := '0';
-signal pileuppulse_lowgain_S : std_logic := '0';
-signal clearpulse_lowgain_S : std_logic := '0';\r
-signal integral_lowgain_S : std_logic_vector(15 downto 0);
-signal max_data_lowgain_S : std_logic_vector(ADCBITS-1 downto 0);
-signal superburst_S : std_logic_vector(15 downto 0);
-signal timestamp_S : std_logic_vector(15 downto 0);
-
-signal adcnumber_highgain_S : std_logic_vector(7 downto 0);
-signal data_out_highgain_S : std_logic_vector(35 downto 0);
-signal data_out_available_highgain_S : std_logic := '0';
-signal data_out_read_highgain_S : std_logic := '0';
-signal overflow_highgain_S : std_logic := '0';
-signal overflow_hg_S : std_logic := '0';
-signal pileupdata1_out_S : std_logic_vector(35 downto 0);
-signal pileupdata1_write_S : std_logic := '0';
-signal pileupdata1_allowed_S : std_logic := '0';
-\r
-signal pulse_write_highgain_S : std_logic;
-signal pulse_superburst_highgain_S : std_logic_vector(15 downto 0);
-signal pulse_timestamp_highgain_S : std_logic_vector(15 downto 0);
-signal pulse_skipped_highgain_S : std_logic;
-signal pulse_energy_highgain_S : std_logic_vector(15 downto 0);
-signal pulse_CF1_highgain_S : std_logic_vector(15 downto 0);
-signal pulse_CF2_highgain_S : std_logic_vector(15 downto 0);
-\r
-signal pulse_write_lowgain_S : std_logic;
-signal pulse_superburst_lowgain_S : std_logic_vector(15 downto 0);
-signal pulse_timestamp_lowgain_S : std_logic_vector(15 downto 0);
-signal pulse_skipped_lowgain_S : std_logic;
-signal pulse_energy_lowgain_S : std_logic_vector(15 downto 0);
-signal pulse_CF1_lowgain_S : std_logic_vector(15 downto 0);
-signal pulse_CF2_lowgain_S : std_logic_vector(15 downto 0);
+end component;\r
+\r
+component FEE_collect_pileup_pulses is\r
+ generic (\r
+ MAXPILEUPHITS : natural := MAXPILEUPHITS\r
+ );\r
+ Port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ pulse_active : in std_logic;\r
+ pileup_valid : in std_logic;\r
+ detect_singlepulse : in std_logic;\r
+ detect_pileuppulse : in std_logic;\r
+ detect_clearpulse : in std_logic;\r
+ detect_purge : in std_logic;\r
+ data_in_write : in std_logic; \r
+ data_in_superburst : in std_logic_vector(30 downto 0);\r
+ data_in_timestamp : in std_logic_vector(15 downto 0);\r
+ data_in_energy : in std_logic_vector(15 downto 0);\r
+ data_in_CF1 : in std_logic_vector(15 downto 0);\r
+ data_in_CF2 : in std_logic_vector(15 downto 0);\r
+ data_out_write : out std_logic;\r
+ data_out_superburst : out std_logic_vector(30 downto 0);\r
+ data_out_timestamp : out std_logic_vector(15 downto 0);\r
+ data_out_energy : out std_logic_vector(15 downto 0);\r
+ data_out_CF1 : out std_logic_vector(15 downto 0);\r
+ data_out_CF2 : out std_logic_vector(15 downto 0);\r
+ data_out_skipped : out std_logic\r
+ );\r
+end component;\r
+ \r
+component FEE_pulsewaveform_buffer is\r
+ generic (\r
+ ADCBITS : natural := ADCBITS;\r
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE\r
+ );\r
+ Port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ pulse_valid : in std_logic;\r
+ pulse_rising : in std_logic;\r
+ pulse_detected : in std_logic;\r
+ pileup_detected : in std_logic;\r
+ clear_waveform : in std_logic;\r
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data\r
+ superburst : in std_logic_vector(15 downto 0);\r
+ timestamp : in std_logic_vector(15 downto 0);\r
+ data_out : out std_logic_vector(35 downto 0);\r
+ data_out_read : in std_logic;\r
+ data_out_available : out std_logic;\r
+ overflow : out std_logic\r
+ );\r
+end component;\r
+\r
+component FEE_waveform_to_36bits is\r
+ generic (\r
+ ADCNUMBER : natural := 0\r
+ );\r
+ Port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ data_in : in std_logic_vector(35 downto 0); \r
+ data_in_available : in std_logic;\r
+ data_in_read : out std_logic;\r
+ overflow_in : in std_logic;\r
+ wavedata_out : out std_logic_vector(35 downto 0);\r
+ wavedata_write : out std_logic;\r
+ wavedata_inpipe : out std_logic;\r
+ wavedata_allowed : in std_logic;\r
+ wavedata_almostfull : in std_logic;\r
+ error : out std_logic;\r
+ overflow_out : out std_logic\r
+ );\r
+end component;\r
+\r
+component FEE_wavemux2to1 is\r
+ generic(\r
+ TIMEOUTBITS : natural := 9\r
+ );\r
+ Port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ data1_in : in std_logic_vector(35 downto 0); \r
+ data1_in_write : in std_logic;\r
+ data1_in_available : in std_logic;\r
+ data1_in_allowed : out std_logic;\r
+ data2_in : in std_logic_vector(35 downto 0); \r
+ data2_in_write : in std_logic;\r
+ data2_in_available : in std_logic;\r
+ data2_in_allowed : out std_logic;\r
+ data_out : out std_logic_vector(35 downto 0);\r
+ data_out_write : out std_logic;\r
+ data_out_available : out std_logic;\r
+ data_out_allowed : in std_logic;\r
+ error : out std_logic;\r
+ timeerror : out std_logic\r
+ );\r
+end component;\r
+\r
+constant ZEROS : std_logic_vector(63 downto 0) := (others => '0');\r
+constant ONES : std_logic_vector(63 downto 0) := (others => '1');\r
+type pileupbuffer_superburst_type is array(0 to MAXPILEUPHITS-1) of std_logic_vector(30 downto 0);\r
+type pileupbuffer_16bits_type is array(0 to MAXPILEUPHITS-1) of std_logic_vector(15 downto 0);\r
+\r
+signal reset_buffer_S : std_logic;\r
+signal pulsedetect_S : std_logic;\r
+signal enable_S : std_logic;\r
+signal enable_highgain_S : std_logic;\r
+signal enable_lowgain_S : std_logic;\r
+signal timestampcounter_S : std_logic_vector(15 downto 0);\r
+signal superburstnumber_S : std_logic_vector(30 downto 0);\r
+signal pileuplength_S : std_logic_vector(7 downto 0);\r
+signal IdivMAX_pileup_S : std_logic_vector(IDIVMAXBITS-1 downto 0);\r
+\r
+signal ADCdata_highgain_S : std_logic_vector(ADCBITS-1 downto 0);\r
+signal pulse_active_highgain_S : std_logic := '0';\r
+signal pulse_rising_highgain0_S : std_logic := '0';\r
+signal pulse_rising_highgain_S : std_logic := '0';\r
+signal pulse_active_lowgain_S : std_logic := '0';\r
+signal pulse_rising_lowgain0_S : std_logic := '0';\r
+signal pulse_rising_lowgain_S : std_logic := '0';\r
+signal ADC_minus_baseline_highgain0_S : std_logic_vector(ADCBITS downto 0);\r
+signal ADC_minus_baseline_lowgain0_S : std_logic_vector(ADCBITS downto 0);\r
+signal ADC_minus_baseline_highgain_S : std_logic_vector(ADCBITS downto 0);\r
+signal ADC_minus_baseline_lowgain_S : std_logic_vector(ADCBITS downto 0);\r
+signal pulse_skipped_occurred_S : std_logic := '0';\r
+\r
+\r
+\r
+signal ADCdata_lowgain_S : std_logic_vector(ADCBITS-1 downto 0);\r
+signal detect_pulse_valid_highgain0_S : std_logic := '0';\r
+signal detect_pulse_valid_highgain_S : std_logic := '0';\r
+signal detect_singlepulse_highgain_S : std_logic := '0';\r
+signal detect_pileuppulse_highgain_S : std_logic := '0';\r
+signal detect_clearpulse_highgain_S : std_logic := '0';\r
+signal detect_pileupvalidpulse_highgain_S : std_logic;\r
+signal detect_integral_highgain_S : std_logic_vector(15 downto 0);\r
+signal detect_purge_highgain_S : std_logic;\r
+signal max_data_highgain_S : std_logic_vector(ADCBITS-1 downto 0);\r
+signal clipping_highgain_S : std_logic := '0';\r
+\r
+signal baseline_inhibit_highgain_S : std_logic := '0';\r
+signal baseline_inhibit_lowgain_S : std_logic := '0';\r
+\r
+signal detect_pulse_valid_lowgain0_S : std_logic := '0';\r
+signal detect_pulse_valid_lowgain_S : std_logic := '0';\r
+signal detect_singlepulse_lowgain_S : std_logic := '0';\r
+signal detect_pileuppulse_lowgain_S : std_logic := '0';\r
+signal detect_clearpulse_lowgain_S : std_logic := '0';\r
+signal detect_pileupvalidpulse_lowgain_S : std_logic;\r
+signal detect_integral_lowgain_S : std_logic_vector(15 downto 0);\r
+signal detect_purge_lowgain_S : std_logic;\r
+signal max_data_lowgain_S : std_logic_vector(ADCBITS-1 downto 0);\r
+signal detect_superburst_S : std_logic_vector(30 downto 0);\r
+signal detect_timestamp_S : std_logic_vector(15 downto 0);\r
+\r
+signal wavedata_highgain_S : std_logic_vector(35 downto 0);\r
+signal wavedata_available_highgain_S : std_logic := '0';\r
+signal wavedata_read_highgain_S : std_logic := '0';\r
+signal wave_overflow_highgain_S : std_logic := '0';\r
+signal wave_overflow_hg_S : std_logic := '0';\r
+signal wavedata1_out_S : std_logic_vector(35 downto 0);\r
+signal wavedata1_write_S : std_logic;\r
+signal wavedata1_allowed_S : std_logic;\r
+signal wavedata1_inpipe_S : std_logic;\r
+\r
+signal pulse_write_highgain_S : std_logic;\r
+signal pulse_superburst_highgain_S : std_logic_vector(30 downto 0);\r
+signal pulse_timestamp_highgain_S : std_logic_vector(15 downto 0);\r
+signal pulse_skipped_highgain_S : std_logic;\r
+signal pulse_energy_highgain_S : std_logic_vector(15 downto 0);\r
+signal pulse_CF1_highgain_S : std_logic_vector(15 downto 0);\r
+signal pulse_CF2_highgain_S : std_logic_vector(15 downto 0);\r
+\r
+signal threshold_pileup_highgain_S : std_logic_vector(ADCBITS-1 downto 0);\r
+signal pileup_ADC_minus_baseline_highgain0_S : std_logic_vector(ADCBITS downto 0);\r
+signal pileup_ADC_minus_baseline_highgain_S : std_logic_vector(ADCBITS downto 0);\r
+\r
+signal pileup_active_highgain_S : std_logic;\r
+signal pileup_rising_highgain0_S : std_logic;\r
+signal pileup_valid_highgain_S : std_logic;\r
+signal pileup_pulse_highgain_S : std_logic;\r
+signal pileup_integral_highgain_S : std_logic_vector(15 downto 0);\r
+\r
+signal pileupdta_write_highgain_S : std_logic;\r
+signal pileupdta_superburst_highgain_S : std_logic_vector(30 downto 0);\r
+signal pileupdta_timestamp_highgain_S : std_logic_vector(15 downto 0);\r
+signal pileupdta_energy_highgain_S : std_logic_vector(15 downto 0);\r
+signal pileupdta_CF1_highgain_S : std_logic_vector(15 downto 0);\r
+signal pileupdta_CF2_highgain_S : std_logic_vector(15 downto 0);\r
+\r
+signal pulse_write_lowgain_S : std_logic;\r
+signal pulse_superburst_lowgain_S : std_logic_vector(30 downto 0);\r
+signal pulse_timestamp_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pulse_skipped_lowgain_S : std_logic;\r
+signal pulse_energy_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pulse_CF1_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pulse_CF2_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pulsedata_status0_S : std_logic_vector(7 downto 0);\r
+signal pulsedata_status1_S : std_logic_vector(7 downto 0);\r
+\r
+signal threshold_pileup_lowgain_S : std_logic_vector(ADCBITS-1 downto 0);\r
+signal pileup_ADC_minus_baseline_lowgain0_S : std_logic_vector(ADCBITS downto 0);\r
+signal pileup_ADC_minus_baseline_lowgain_S : std_logic_vector(ADCBITS downto 0);\r
+\r
+signal pileup_active_lowgain_S : std_logic;\r
+signal pileup_rising_lowgain0_S : std_logic;\r
+signal pileup_valid_lowgain_S : std_logic;\r
+signal pileup_pulse_lowgain_S : std_logic;\r
+signal pileup_integral_lowgain_S : std_logic_vector(15 downto 0);\r
+\r
+signal pileupdta_write_lowgain_S : std_logic;\r
+signal pileupdta_superburst_lowgain_S : std_logic_vector(30 downto 0);\r
+signal pileupdta_timestamp_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pileupdta_energy_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pileupdta_CF1_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pileupdta_CF2_lowgain_S : std_logic_vector(15 downto 0);\r
+\r
+signal pileup_write_highgain_S : std_logic;\r
+signal pileup_superburst_highgain_S : std_logic_vector(30 downto 0);\r
+signal pileup_timestamp_highgain_S : std_logic_vector(15 downto 0);\r
+signal pileup_energy_highgain_S : std_logic_vector(15 downto 0);\r
+signal pileup_CF1_highgain_S : std_logic_vector(15 downto 0);\r
+signal pileup_CF2_highgain_S : std_logic_vector(15 downto 0);\r
+signal pileup_skipped_highgain_S : std_logic := '0';\r
+\r
+signal pileup_write_lowgain_S : std_logic;\r
+signal pileup_superburst_lowgain_S : std_logic_vector(30 downto 0);\r
+signal pileup_timestamp_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pileup_energy_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pileup_CF1_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pileup_CF2_lowgain_S : std_logic_vector(15 downto 0);\r
+signal pileup_skipped_lowgain_S : std_logic := '0';\r
+\r
+signal pulsedata_superburst_S : std_logic_vector(30 downto 0);\r
+signal pulsedata_timestamp_S : std_logic_vector(15 downto 0);\r
+\r
+signal wavedata_lowgain_S : std_logic_vector(35 downto 0);\r
+signal wavedata_available_lowgain_S : std_logic := '0';\r
+signal wavedata_read_lowgain_S : std_logic := '0';\r
+signal wave_overflow_lowgain_S : std_logic := '0';\r
+signal wave_overflow_lg_S : std_logic := '0';\r
+signal wavedata2_out_S : std_logic_vector(35 downto 0);\r
+signal wavedata2_write_S : std_logic;\r
+signal wavedata2_allowed_S : std_logic;\r
+signal wavedata2_inpipe_S : std_logic;\r
+\r
+signal pulsedata_write_S : std_logic := '0';\r
+signal wavedata_out_S : std_logic_vector(35 downto 0);\r
+signal wavedata_write_S : std_logic := '0';\r
+\r
+signal wave_error_S : std_logic := '0';\r
+signal wave_error_to36_1_S : std_logic := '0';\r
+signal wave_error_to36_2_S : std_logic := '0';\r
+signal data_error_S : std_logic := '0';\r
+signal pulsetime_error_S : std_logic := '0';\r
+\r
+ \r
+attribute mark_debug : string;\r
+\r
+-- attribute mark_debug of clipping_highgain_S : signal is "true";\r
+\r
+-- attribute mark_debug of ADCdata_highgain_S : signal is "true";\r
+-- attribute mark_debug of pulse_active_highgain_S : signal is "true";\r
+-- attribute mark_debug of ADC_minus_baseline_highgain_S : signal is "true";\r
+-- attribute mark_debug of detect_singlepulse_highgain_S : signal is "true";\r
+-- attribute mark_debug of detect_pileuppulse_highgain_S : signal is "true";\r
+-- attribute mark_debug of detect_clearpulse_highgain_S : signal is "true";\r
+-- attribute mark_debug of detect_pileupvalidpulse_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_write_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_skipped_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_ADC_minus_baseline_highgain0_S : signal is "true";\r
+-- attribute mark_debug of pileup_active_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_integral_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_valid_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_pulse_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileupdta_write_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_hitcount_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_resultcount_highgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_readcount_highgain_S : signal is "true";\r
+\r
+-- attribute mark_debug of ADCdata_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pulse_active_lowgain_S : signal is "true";\r
+-- attribute mark_debug of ADC_minus_baseline_lowgain_S : signal is "true";\r
+-- attribute mark_debug of detect_singlepulse_lowgain_S : signal is "true";\r
+-- attribute mark_debug of detect_pileuppulse_lowgain_S : signal is "true";\r
+-- attribute mark_debug of detect_clearpulse_lowgain_S : signal is "true";\r
+-- attribute mark_debug of detect_pileupvalidpulse_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_write_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_skipped_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_ADC_minus_baseline_lowgain0_S : signal is "true";\r
+-- attribute mark_debug of pileup_active_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_integral_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_valid_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_pulse_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileupdta_write_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_hitcount_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_resultcount_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pileup_readcount_lowgain_S : signal is "true";\r
+\r
+-- attribute mark_debug of pulse_write_highgain_S : signal is "true";\r
+-- attribute mark_debug of pulse_skipped_highgain_S : signal is "true";\r
+-- attribute mark_debug of pulse_write_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pulse_skipped_lowgain_S : signal is "true";\r
+-- attribute mark_debug of pulsedata_write_S : signal is "true";\r
+-- attribute mark_debug of pulsedata_allowed : signal is "true";\r
+\r
+-- attribute mark_debug of wavedata1_write_S : signal is "true";\r
+-- attribute mark_debug of wavedata1_inpipe_S : signal is "true";\r
+-- attribute mark_debug of wavedata1_allowed_S : signal is "true";\r
+-- attribute mark_debug of wavedata2_write_S : signal is "true";\r
+-- attribute mark_debug of wavedata2_inpipe_S : signal is "true";\r
+-- attribute mark_debug of wavedata2_allowed_S : signal is "true";\r
+-- attribute mark_debug of wavedata_write_S : signal is "true";\r
+-- attribute mark_debug of wavedata_available : signal is "true";\r
+-- attribute mark_debug of wavedata_allowed : signal is "true";\r
+\r
+-- attribute mark_debug of wave_overflow_highgain_S : signal is "true";\r
+-- attribute mark_debug of wave_overflow_lowgain_S : signal is "true";\r
+-- attribute mark_debug of wave_overflow_hg_S : signal is "true";\r
+-- attribute mark_debug of wave_overflow_lg_S : signal is "true";\r
+\r
+begin\r
+\r
+error <= '1' when ((wave_error_to36_1_S='1') or (wave_error_to36_2_S='1') or (wave_error_S='1')) and (enable_waveform='1') else '0';\r
+overflow <= '1' when \r
+ (((wave_overflow_highgain_S='1') or (wave_overflow_lowgain_S='1') or (wave_overflow_hg_S='1') or (wave_overflow_lg_S='1')) and (enable_waveform='1'))\r
+-- or ((pulse_skipped_highgain_S='1') and (pulse_write_highgain_S='1') and (enable_waveform='0'))\r
+-- or ((pulse_skipped_lowgain_S='1') and (pulse_write_lowgain_S='1') and (enable_waveform='0')) \r
+ or ((pulse_skipped_occurred_S='1') and (enable_waveform='0'))\r
+ else '0';\r
+\r
+enable_S <= '1' when (enable='1') and ((enable_highgain='1') or (enable_lowgain='1')) else '0';\r
+enable_highgain_S <= '1' when (enable_highgain='1') or ((enable_lowgain='0') and (enable_highgain='0')) else '0';\r
+enable_lowgain_S <= '1' when (enable_lowgain='1') or ((enable_lowgain='0') and (enable_highgain='0')) else '0';\r
+\r
+\r
+pulsedetect <= pulsedetect_S;\r
+pulsedetect_S <= '1' when (detect_singlepulse_highgain_S='1') or (detect_pileuppulse_highgain_S='1') \r
+ or (detect_singlepulse_lowgain_S='1') or (detect_pileuppulse_lowgain_S='1') else '0';\r
+\r
+ADCdata_highgain_S <= ADCdata_highgain;\r
+ADCdata_lowgain_S <= ADCdata_lowgain;\r
+\r
+\r
+timestampcounter: process(clock)\r
+begin\r
+ if (rising_edge(clock)) then \r
+ if superburstupdate='1' then\r
+ timestampcounter_S <= (others => '0');\r
+ superburstnumber_S <= superburstnumber;\r
+ else\r
+ timestampcounter_S <= timestampcounter_S+1;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+-- Regular hits ------------------------------------------------------------------------------------------------------------\r
+\r
+baseline_high: FEE_baselinefollower_eventdetector \r
+ generic map(\r
+ ADCBITS => ADCBITS,\r
+ BASELINE_BWBITS => BASELINE_BWBITS,\r
+ MWD_WIDTHBITS => MWD_WIDTHBITS,\r
+ MWD_SCALEBITS => MWD_SCALEBITS,\r
+ MWD2_WIDTHBITS => MWD2_WIDTHBITS,\r
+ MWD2_SCALEBITS => MWD2_SCALEBITS,\r
+ MWD_DOUBLEFILTER => MWD_DOUBLEFILTER)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ enable => enable_S,\r
+ ADCdata => ADCdata_highgain_S,\r
+ MWD1_width => MWD1_width,\r
+ MWD1_tau_factor => MWD1_tau_factor,\r
+ MWD2_width => MWD2_width,\r
+ MWD2_tau_factor => MWD2_tau_factor,\r
+ threshold => threshold_highgain,\r
+ IIRfilterBW => IIRfilterBW,\r
+ maxabovebaseline => maxabovebaseline,\r
+ ADC_minus_baseline => ADC_minus_baseline_highgain0_S,\r
+ baseline_inhibit => baseline_inhibit_highgain_S,\r
+ pulse_active => pulse_active_highgain_S,\r
+ pulse_rising => pulse_rising_highgain0_S,\r
+ max_data => max_data_highgain_S);\r
+\r
+baseline_low: FEE_baselinefollower_eventdetector \r
+ generic map(\r
+ ADCBITS => ADCBITS,\r
+ BASELINE_BWBITS => BASELINE_BWBITS,\r
+ MWD_WIDTHBITS => MWD_WIDTHBITS,\r
+ MWD_SCALEBITS => MWD_SCALEBITS,\r
+ MWD2_WIDTHBITS => MWD2_WIDTHBITS,\r
+ MWD2_SCALEBITS => MWD2_SCALEBITS,\r
+ MWD_DOUBLEFILTER => MWD_DOUBLEFILTER)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ enable => enable_S,\r
+ ADCdata => ADCdata_lowgain_S,\r
+ MWD1_width => MWD1_width,\r
+ MWD1_tau_factor => MWD1_tau_factor,\r
+ MWD2_width => MWD2_width,\r
+ MWD2_tau_factor => MWD2_tau_factor,\r
+ threshold => threshold_lowgain,\r
+ IIRfilterBW => IIRfilterBW,\r
+ maxabovebaseline => maxabovebaseline,\r
+ ADC_minus_baseline => ADC_minus_baseline_lowgain0_S,\r
+ baseline_inhibit => baseline_inhibit_lowgain_S,\r
+ pulse_active => pulse_active_lowgain_S,\r
+ pulse_rising => pulse_rising_lowgain0_S,\r
+ max_data => max_data_lowgain_S);\r
+ \r
+pileuplength_S <= pileuplength when enable_waveform='0' else (others => '0');\r
+IdivMAX_pileup_S <= IdivMAX_pileup when enable_waveform='0' else (others => '1');\r
+pileup_check1: FEE_pileup_check port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ superburstnumber => superburstnumber_S,\r
+ timestampcounter => timestampcounter_S, \r
+ force_hit => force_hit,\r
+ ADC_highgain => ADC_minus_baseline_highgain0_S,\r
+ enable_highgain => enable_highgain_S,\r
+ threshold_highgain => threshold_highgain,\r
+ max_data_highgain => max_data_highgain_S,\r
+ pulse_active_highgain => pulse_active_highgain_S,\r
+ pulse_rising_highgain => pulse_rising_highgain0_S,\r
+ clipping_highgain => clipping_highgain_S,\r
+ ADC_lowgain => ADC_minus_baseline_lowgain0_S,\r
+ enable_lowgain => enable_lowgain_S,\r
+ threshold_lowgain => threshold_lowgain,\r
+ max_data_lowgain => max_data_lowgain_S,\r
+ pulse_active_lowgain => pulse_active_lowgain_S,\r
+ pulse_rising_lowgain => pulse_rising_lowgain0_S,\r
+ minpulselength => minpulselength,\r
+ pileuplength => pileuplength_S,\r
+ maxwavelength => maxwavelength,\r
+ IdivMAX_discard => IdivMAX_discard,\r
+ IdivMAX_pileup => IdivMAX_pileup_S,\r
+ fullsize_wave_highgain => fullsize_wave_highgain,\r
+ fullsize_wave_lowgain => fullsize_wave_lowgain,\r
+ pulse_valid_highgain => detect_pulse_valid_highgain0_S,\r
+ singlepulse_highgain => detect_singlepulse_highgain_S,\r
+ pileuppulse_highgain => detect_pileuppulse_highgain_S,\r
+ clearpulse_highgain => detect_clearpulse_highgain_S,\r
+ integral_highgain => detect_integral_highgain_S,\r
+ pulse_valid_lowgain => detect_pulse_valid_lowgain0_S,\r
+ singlepulse_lowgain => detect_singlepulse_lowgain_S,\r
+ pileuppulse_lowgain => detect_pileuppulse_lowgain_S,\r
+ clearpulse_lowgain => detect_clearpulse_lowgain_S,\r
+ integral_lowgain => detect_integral_lowgain_S,\r
+ superburst => detect_superburst_S,\r
+ timestamp => detect_timestamp_S);\r
\r
\r
-
-signal adcnumber_lowgain_S : std_logic_vector(7 downto 0);
-signal data_out_lowgain_S : std_logic_vector(35 downto 0);
-signal data_out_available_lowgain_S : std_logic := '0';
-signal data_out_read_lowgain_S : std_logic := '0';
-signal overflow_lowgain_S : std_logic := '0';
-signal overflow_lg_S : std_logic := '0';
-signal pileupdata2_out_S : std_logic_vector(35 downto 0);
-signal pileupdata2_write_S : std_logic := '0';
-signal pileupdata2_allowed_S : std_logic := '0';
-
-signal pulsedata_out_S : std_logic_vector(35 downto 0);
-signal pulsedata_write_S : std_logic := '0';
-signal pileupdata_out_S : std_logic_vector(35 downto 0);
-signal pileupdata_write_S : std_logic := '0';
-
-signal error_pulse_S : std_logic := '0';
-signal error_pileup_S : std_logic := '0';
-signal error_to36_1_S : std_logic := '0';
-signal error_to36_2_S : std_logic := '0';
-
-signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');
-signal testword1_S : std_logic_vector(35 downto 0) := (others => '0');
-signal testword2_S : std_logic_vector(35 downto 0) := (others => '0');
-
-begin
-
-pulsedetect <= pulsedetect_S;
-pulsedetect_S <= '1' when (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1')
- or (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') else '0';
-
-FEE_baselinefollower_eventdetector_highgain: FEE_baselinefollower_eventdetector port map(
- clock => clock,
- reset => reset,
- enable => enable,
- ADCdata => ADCdata_highgain,
- threshold => threshold_highgain,
- IIRfilterBW => IIRfilterBW,
- maxabovebaseline => maxabovebaseline,
- baseline => baseline_highgain_S,
- ADC_delayed => open,
- ADC_minus_baseline => ADC_minus_baseline_highgain0_S,
- baseline_inhibit => baseline_inhibit_highgain_S,
- pulse_active => pulse_active_highgain_S,
- pulse_rising => pulse_rising_highgain0_S,
- max_data => max_data_highgain_S);
-ADC_minus_baseline_highgain <= ADC_minus_baseline_highgain_S;
-
-FEE_baselinefollower_eventdetector_lowgain: FEE_baselinefollower_eventdetector port map(
- clock => clock,
- reset => reset,
- enable => enable,
- ADCdata => ADCdata_lowgain,
- threshold => threshold_lowgain,
- IIRfilterBW => IIRfilterBW,
- maxabovebaseline => maxabovebaseline,
- baseline => baseline_lowgain_S,
- ADC_delayed => open,
- ADC_minus_baseline => ADC_minus_baseline_lowgain0_S,
- baseline_inhibit => baseline_inhibit_lowgain_S,
- pulse_active => pulse_active_lowgain_S,
- pulse_rising => pulse_rising_lowgain0_S,
- max_data => max_data_lowgain_S);
-ADC_minus_baseline_lowgain <= ADC_minus_baseline_lowgain_S;
-
-FEE_pileup_check1: FEE_pileup_check port map(
- clock => clock,
- reset => reset,
- superburstnumber => superburstnumber,
- timestampcounter => timestampcounter,
- ADC_highgain => ADC_minus_baseline_highgain0_S,
- enable_highgain => enable_highgain,
- max_data_highgain => max_data_highgain_S,
- pulse_active_highgain => pulse_active_highgain_S,
- pulse_rising_highgain => pulse_rising_highgain0_S,
- clipping_highgain => clipping_highgain_S,
- ADC_lowgain => ADC_minus_baseline_lowgain0_S,
- enable_lowgain => enable_lowgain,
- max_data_lowgain => max_data_lowgain_S,
- pulse_active_lowgain => pulse_active_lowgain_S,
- pulse_rising_lowgain => pulse_rising_lowgain0_S,
- minpulselength => minpulselength,
- pileuplength => pileuplength,
- maxwavelength => maxwavelength,
- IdivMAX_discard => IdivMAX_discard,
- IdivMAX_pileup => IdivMAX_pileup,
- fullsize_wave_highgain => fullsize_wave_highgain,
- fullsize_wave_lowgain => fullsize_wave_lowgain,
- pulse_valid_highgain => pulse_valid_highgain0_S,
- singlepulse_highgain => singlepulse_highgain_S,
- pileuppulse_highgain => pileuppulse_highgain_S,
- clearpulse_highgain => clearpulse_highgain_S,
- integral_highgain => integral_highgain_S,\r
- pulse_valid_lowgain => pulse_valid_lowgain0_S,
- singlepulse_lowgain => singlepulse_lowgain_S,
- pileuppulse_lowgain => pileuppulse_lowgain_S,
- clearpulse_lowgain => clearpulse_lowgain_S,
- integral_lowgain => integral_lowgain_S,\r
- superburst => superburst_S,\r
- timestamp => timestamp_S,
- testword0 => open);
-\r
-
-process(clock)
-begin
+process(clock)\r
+begin\r
if (rising_edge(clock)) then \r
- if enable_highgain='1' then
- pulse_valid_highgain_S <= pulse_valid_highgain0_S;
+ if enable_highgain_S='1' then\r
+ detect_pulse_valid_highgain_S <= detect_pulse_valid_highgain0_S;\r
pulse_rising_highgain_S <= pulse_rising_highgain0_S;\r
else\r
- pulse_valid_highgain_S <= '0';
+ detect_pulse_valid_highgain_S <= '0';\r
pulse_rising_highgain_S <= '0';\r
- end if;
- ADC_minus_baseline_highgain_S <= ADC_minus_baseline_highgain0_S;\r
- if enable_lowgain='1' then
- pulse_valid_lowgain_S <= pulse_valid_lowgain0_S;
+ end if;\r
+ if enable_rawdata='1' then\r
+ ADC_minus_baseline_highgain_S <= '0' & ADCdata_highgain_S;\r
+ else\r
+ ADC_minus_baseline_highgain_S <= ADC_minus_baseline_highgain0_S;\r
+ end if;\r
+ if enable_lowgain_S='1' then\r
+ detect_pulse_valid_lowgain_S <= detect_pulse_valid_lowgain0_S;\r
pulse_rising_lowgain_S <= pulse_rising_lowgain0_S;\r
else\r
- pulse_valid_lowgain_S <= '0';
+ detect_pulse_valid_lowgain_S <= '0';\r
pulse_rising_lowgain_S <= '0';\r
- end if;
- ADC_minus_baseline_lowgain_S <= ADC_minus_baseline_lowgain0_S;
- if pulse_active_highgain_S='1' then
- if ADCdata_highgain((ADCBITS-1) downto (ADCBITS-4)) = "1111" then
- clipping_highgain_S <= '1';
- end if;
- else
- clipping_highgain_S <= '0';
- end if;
- end if;
+ end if;\r
+ if enable_rawdata='1' then\r
+ ADC_minus_baseline_lowgain_S <= '0' & ADCdata_lowgain_S;\r
+ else\r
+ ADC_minus_baseline_lowgain_S <= ADC_minus_baseline_lowgain0_S;\r
+ end if;\r
+ if pulse_active_highgain_S='1' then\r
+ if ADCdata_highgain_S((ADCBITS-1) downto (ADCBITS-4)) = "1111" then\r
+ clipping_highgain_S <= '1';\r
+ end if;\r
+ if (detect_pulse_valid_highgain_S='1') and (ADC_minus_baseline_highgain0_S(ADCBITS)='0') and (ADC_minus_baseline_highgain0_S(ADCBITS-1 downto 0)=ONES(ADCBITS-1 downto 0)) then\r
+ clipping_highgain_S <= '1';\r
+ end if;\r
+ else\r
+ clipping_highgain_S <= '0';\r
+ end if;\r
+ end if;\r
end process;\r
\r
-FEE_extract_pulse1: FEE_extract_pulse port map(
- clock => clock,
- reset => reset,
- cf_delay => cf_delay,
- pulse_valid => pulse_valid_highgain_S,
- pulse_rising => pulse_rising_highgain_S,
- pulse_detected => singlepulse_highgain_S,
- pileup_detected => pileuppulse_highgain_S,
- clear_waveform => clearpulse_highgain_S,
+extract_high: FEE_extract_pulse \r
+ generic map(\r
+ ADCBITS => ADCBITS,\r
+ CF_DELAYBITS => CF_DELAYBITS)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ cf_delay => CF_delay,\r
+ pulse_valid => detect_pulse_valid_highgain_S,\r
+ pulse_detected => detect_singlepulse_highgain_S,\r
+ pileup_detected => detect_pileuppulse_highgain_S,\r
+ clear_waveform => detect_clearpulse_highgain_S,\r
data_in => ADC_minus_baseline_highgain_S,\r
- integral => integral_highgain_S,\r
- superburstnumber => superburstnumber,
- timestamp => timestampcounter,\r
- pulse_write => pulse_write_highgain_S,
- pulse_superburst => pulse_superburst_highgain_S,
+ integral => detect_integral_highgain_S,\r
+ superburstnumber => superburstnumber_S,\r
+ timestamp => timestampcounter_S,\r
+ pulse_write => pulse_write_highgain_S,\r
+ pulse_superburst => pulse_superburst_highgain_S,\r
pulse_timestamp => pulse_timestamp_highgain_S,\r
- pulse_skipped => pulse_skipped_highgain_S,
- pulse_energy => pulse_energy_highgain_S,
- pulse_CF1 => pulse_CF1_highgain_S,
+ pulse_skipped => pulse_skipped_highgain_S,\r
+ pulse_energy => pulse_energy_highgain_S,\r
+ pulse_CF1 => pulse_CF1_highgain_S,\r
pulse_CF2 => pulse_CF2_highgain_S);\r
\r
-FEE_extract_pulse2: FEE_extract_pulse port map(
- clock => clock,
- reset => reset,
- cf_delay => cf_delay,
- pulse_valid => pulse_valid_lowgain_S,
- pulse_rising => pulse_rising_lowgain_S,
- pulse_detected => singlepulse_lowgain_S,
- pileup_detected => pileuppulse_lowgain_S,
- clear_waveform => clearpulse_lowgain_S,
+extract_low: FEE_extract_pulse \r
+ generic map(\r
+ ADCBITS => ADCBITS,\r
+ CF_DELAYBITS => CF_DELAYBITS)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ cf_delay => CF_delay,\r
+ pulse_valid => detect_pulse_valid_lowgain_S,\r
+ pulse_detected => detect_singlepulse_lowgain_S,\r
+ pileup_detected => detect_pileuppulse_lowgain_S,\r
+ clear_waveform => detect_clearpulse_lowgain_S,\r
data_in => ADC_minus_baseline_lowgain_S,\r
- integral => integral_lowgain_S,\r
- superburstnumber => superburstnumber,
- timestamp => timestampcounter,\r
- pulse_write => pulse_write_lowgain_S,
- pulse_superburst => pulse_superburst_lowgain_S,
- pulse_timestamp => pulse_timestamp_lowgain_S,
- pulse_skipped => pulse_skipped_lowgain_S,
- pulse_energy => pulse_energy_lowgain_S,
- pulse_CF1 => pulse_CF1_lowgain_S,
+ integral => detect_integral_lowgain_S,\r
+ superburstnumber => superburstnumber_S,\r
+ timestamp => timestampcounter_S,\r
+ pulse_write => pulse_write_lowgain_S,\r
+ pulse_superburst => pulse_superburst_lowgain_S,\r
+ pulse_timestamp => pulse_timestamp_lowgain_S,\r
+ pulse_skipped => pulse_skipped_lowgain_S,\r
+ pulse_energy => pulse_energy_lowgain_S,\r
+ pulse_CF1 => pulse_CF1_lowgain_S,\r
pulse_CF2 => pulse_CF2_lowgain_S); \r
\r
-FEE_pulsewaveform_buffer1: FEE_pulsewaveform_buffer port map(
- clock => clock,
- reset => reset,
- pulse_valid => pulse_valid_highgain_S,
- pulse_rising => pulse_rising_highgain_S,
- pulse_detected => singlepulse_highgain_S,
- pileup_detected => pileuppulse_highgain_S,
- clear_waveform => clearpulse_highgain_S,
- data_in => ADC_minus_baseline_highgain_S,
- superburst => superburst_S,
- timestamp => timestamp_S,
- data_out => data_out_highgain_S,
- data_out_read => data_out_read_highgain_S,
- data_out_available => data_out_available_highgain_S,
- overflow => overflow_highgain_S,
- testword0 => testword1);
-
-FEE_pulsewaveform_buffer2: FEE_pulsewaveform_buffer port map(
- clock => clock,
- reset => reset,
- pulse_valid => pulse_valid_lowgain_S,
- pulse_rising => pulse_rising_lowgain_S,
- pulse_detected => singlepulse_lowgain_S,
- pileup_detected => pileuppulse_lowgain_S,
- clear_waveform => clearpulse_lowgain_S,
- data_in => ADC_minus_baseline_lowgain_S,
- superburst => superburst_S,
- timestamp => timestamp_S,
- data_out => data_out_lowgain_S,
- data_out_read => data_out_read_lowgain_S,
- data_out_available => data_out_available_lowgain_S,
- overflow => overflow_lowgain_S,
- testword0 => open); \r
-
-FEE_pulse2to1_pulse1: FEE_pulse2to1_pulse port map(
- clock => clock,
- reset => reset,
- channel => adcnumber,
- pulse1_write => pulse_write_highgain_S,
- pulse1_superburst => pulse_superburst_highgain_S,
- pulse1_timestamp => pulse_timestamp_highgain_S,\r
- pulse1_skipped => pulse_skipped_highgain_S,
- pulse1_energy => pulse_energy_highgain_S,
- pulse1_CF1 => pulse_CF1_highgain_S,
- pulse1_CF2 => pulse_CF2_highgain_S,\r
- pulse2_write => pulse_write_lowgain_S,
- pulse2_superburst => pulse_superburst_lowgain_S,
- pulse2_timestamp => pulse_timestamp_lowgain_S,
- pulse2_skipped => pulse_skipped_lowgain_S,
- pulse2_energy => pulse_energy_lowgain_S,
- pulse2_CF1 => pulse_CF1_lowgain_S,
- pulse2_CF2 => pulse_CF2_lowgain_S, \r
- pulse_skipped => open, \r
- data_out => pulsedata_out_S,
- data_out_write => pulsedata_write_S,
- data_out_almostfull => pulsedata_almostfull,
- data_out_allowed => pulsedata_allowed);
-pulsedata_out <= pulsedata_out_S;
-pulsedata_write <= pulsedata_write_S;\r
-\r
-\r
-
-adcnumber_highgain_S <= adcnumber AND x"fe";
-FEE_waveform_to_36bits1: FEE_waveform_to_36bits port map(
- clock => clock,
- reset => reset,
- adcnumber => adcnumber_highgain_S,
- data_in => data_out_highgain_S,
- data_in_available => data_out_available_highgain_S,
- data_in_read => data_out_read_highgain_S,
- overflow_in => overflow_highgain_S,
- pileupdata_out => pileupdata1_out_S,
- pileupdata_write => pileupdata1_write_S,
- pileupdata_allowed => pileupdata1_allowed_S,
- pileupdata_almostfull => pileupdata_almostfull,
- overflow_out => overflow_hg_S,
- error => error_to36_1_S,
- testword0 => open);
-
-adcnumber_lowgain_S <= adcnumber OR x"01";
-FEE_waveform_to_36bits2: FEE_waveform_to_36bits port map(
- clock => clock,
- reset => reset,
- adcnumber => adcnumber_lowgain_S,
- data_in => data_out_lowgain_S,
- data_in_available => data_out_available_lowgain_S,
- data_in_read => data_out_read_lowgain_S,
- overflow_in => overflow_lowgain_S,
- pileupdata_out => pileupdata2_out_S,
- pileupdata_write => pileupdata2_write_S,
- pileupdata_allowed => pileupdata2_allowed_S,
- pileupdata_almostfull => pileupdata_almostfull,
- overflow_out => overflow_lg_S,
- error => error_to36_2_S,
- testword0 => open);
-overflow <= '1' when (overflow_highgain_S='1') or (overflow_lowgain_S='1') or (overflow_hg_S='1') or (overflow_lg_S='1') else '0';
-
-FEE_wavemux2to1_pileup: FEE_wavemux2to1 port map(
- clock => clock,
- reset => reset,
- data1_in => pileupdata1_out_S,
- data1_in_write => pileupdata1_write_S,
- data1_in_available => data_out_available_highgain_S, -- '0',
- data1_in_allowed => pileupdata1_allowed_S,
- data2_in => pileupdata2_out_S,
- data2_in_write => pileupdata2_write_S,
- data2_in_available => data_out_available_lowgain_S, -- '0',
- data2_in_allowed => pileupdata2_allowed_S,
- data_out => pileupdata_out_S,
- data_out_write => pileupdata_write_S,
- data_out_available => open,
- data_out_allowed => pileupdata_allowed,
- error => error_pileup_S,
- testword0 => testword2);
-pileupdata_out <= pileupdata_out_S;
-pileupdata_write <= pileupdata_write_S;
+-- Pileup Highgain ------------------------------------------------------------------------------------------------------------\\r
+\r
+threshold_pileup_highgain_S <= threshold_highgain;\r
+baseline_pileup_high: FEE_baselinefollower_eventdetector\r
+ generic map(\r
+ ADCBITS => ADCBITS,\r
+ BASELINE_BWBITS => BASELINE_BWBITS,\r
+ MWD_WIDTHBITS => 2,\r
+ MWD_SCALEBITS => MWD_SCALEBITS,\r
+ MWD2_WIDTHBITS => MWD2_WIDTHBITS,\r
+ MWD2_SCALEBITS => MWD2_SCALEBITS,\r
+ MWD_DOUBLEFILTER => MWD_PU_DOUBLEFILTER)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ enable => enable_S,\r
+ ADCdata => ADCdata_highgain_S,\r
+ MWD1_width => MWDpu1_width,\r
+ MWD1_tau_factor => MWDpu1_tau_factor,\r
+ MWD2_width => MWDpu2_width,\r
+ MWD2_tau_factor => MWDpu2_tau_factor,\r
+ threshold => threshold_pileup_highgain_S,\r
+ IIRfilterBW => IIRfilterBW,\r
+ maxabovebaseline => maxabovebaseline,\r
+ ADC_minus_baseline => pileup_ADC_minus_baseline_highgain0_S,\r
+ baseline_inhibit => open,\r
+ pulse_active => pileup_active_highgain_S,\r
+ pulse_rising => pileup_rising_highgain0_S,\r
+ max_data => open);\r
+\r
+pileup_detect_high: FEE_pulse_detect port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ ADCdata => pileup_ADC_minus_baseline_highgain0_S,\r
+ pulse_active => pileup_active_highgain_S,\r
+ minpulselength => "000" & MWDpu1_width,\r
+ pulse_valid => pileup_valid_highgain_S,\r
+ singlepulse => pileup_pulse_highgain_S,\r
+ integral => pileup_integral_highgain_S);\r
+ \r
+process(clock)\r
+begin\r
+ if (rising_edge(clock)) then \r
+ pileup_ADC_minus_baseline_highgain_S <= pileup_ADC_minus_baseline_highgain0_S;\r
+ end if;\r
+end process; \r
+\r
+extract_pu_high: FEE_extract_pulse\r
+ generic map(\r
+ ADCBITS => ADCBITS,\r
+ CF_DELAYBITS => 2)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ cf_delay => CFpu_delay,\r
+ pulse_valid => pileup_valid_highgain_S,\r
+ pulse_detected => pileup_pulse_highgain_S,\r
+ pileup_detected => '0',\r
+ clear_waveform => '0',\r
+ data_in => pileup_ADC_minus_baseline_highgain_S,\r
+ integral => pileup_integral_highgain_S,\r
+ superburstnumber => superburstnumber_S,\r
+ timestamp => timestampcounter_S,\r
+ pulse_write => pileupdta_write_highgain_S,\r
+ pulse_superburst => pileupdta_superburst_highgain_S,\r
+ pulse_timestamp => pileupdta_timestamp_highgain_S,\r
+ pulse_skipped => open,\r
+ pulse_energy => pileupdta_energy_highgain_S,\r
+ pulse_CF1 => pileupdta_CF1_highgain_S,\r
+ pulse_CF2 => pileupdta_CF2_highgain_S);\r
+\r
+FEE_collect_pileup_pulses_high: FEE_collect_pileup_pulses port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ pulse_active => pulse_active_highgain_S,\r
+ pileup_valid => pileup_valid_highgain_S,\r
+ detect_singlepulse => detect_singlepulse_highgain_S,\r
+ detect_pileuppulse => detect_pileuppulse_highgain_S,\r
+ detect_clearpulse => detect_clearpulse_highgain_S,\r
+ detect_purge => detect_purge_highgain_S,\r
+ data_in_write => pileupdta_write_highgain_S,\r
+ data_in_superburst => pileupdta_superburst_highgain_S,\r
+ data_in_timestamp => pileupdta_timestamp_highgain_S,\r
+ data_in_energy => pileupdta_energy_highgain_S,\r
+ data_in_CF1 => pileupdta_CF1_highgain_S,\r
+ data_in_CF2 => pileupdta_CF2_highgain_S,\r
+ data_out_write => pileup_write_highgain_S,\r
+ data_out_superburst => pileup_superburst_highgain_S,\r
+ data_out_timestamp => pileup_timestamp_highgain_S,\r
+ data_out_energy => pileup_energy_highgain_S,\r
+ data_out_CF1 => pileup_CF1_highgain_S,\r
+ data_out_CF2 => pileup_CF2_highgain_S,\r
+ data_out_skipped => pileup_skipped_highgain_S);\r
+detect_purge_highgain_S <= '1' when (detect_pileuppulse_lowgain_S='1') or (detect_singlepulse_lowgain_S='1') else '0';\r
+ \r
+ \r
+-- Pileup Lowgain ------------------------------------------------------------------------------------------------------------\r
+threshold_pileup_lowgain_S <= threshold_lowgain;\r
+baseline_pileup_low: FEE_baselinefollower_eventdetector \r
+ generic map(\r
+ ADCBITS => ADCBITS,\r
+ BASELINE_BWBITS => BASELINE_BWBITS,\r
+ MWD_WIDTHBITS => 2,\r
+ MWD_SCALEBITS => MWD_SCALEBITS,\r
+ MWD2_WIDTHBITS => MWD2_WIDTHBITS,\r
+ MWD2_SCALEBITS => MWD2_SCALEBITS,\r
+ MWD_DOUBLEFILTER => MWD_PU_DOUBLEFILTER)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ enable => enable_S,\r
+ ADCdata => ADCdata_lowgain_S,\r
+ MWD1_width => MWDpu1_width,\r
+ MWD1_tau_factor => MWDpu1_tau_factor,\r
+ MWD2_width => MWDpu2_width,\r
+ MWD2_tau_factor => MWDpu2_tau_factor,\r
+ threshold => threshold_pileup_lowgain_S,\r
+ IIRfilterBW => IIRfilterBW,\r
+ maxabovebaseline => maxabovebaseline,\r
+ ADC_minus_baseline => pileup_ADC_minus_baseline_lowgain0_S,\r
+ baseline_inhibit => open,\r
+ pulse_active => pileup_active_lowgain_S,\r
+ pulse_rising => pileup_rising_lowgain0_S,\r
+ max_data => open);\r
+\r
+pileup_detect_low: FEE_pulse_detect port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ ADCdata => pileup_ADC_minus_baseline_lowgain0_S,\r
+ pulse_active => pileup_active_lowgain_S,\r
+ minpulselength => "000" & MWDpu1_width,\r
+ pulse_valid => pileup_valid_lowgain_S,\r
+ singlepulse => pileup_pulse_lowgain_S,\r
+ integral => pileup_integral_lowgain_S);\r
+ \r
+process(clock)\r
+begin\r
+ if (rising_edge(clock)) then \r
+ pileup_ADC_minus_baseline_lowgain_S <= pileup_ADC_minus_baseline_lowgain0_S;\r
+ end if;\r
+end process; \r
+\r
+extract_pu_low: FEE_extract_pulse \r
+ generic map(\r
+ ADCBITS => ADCBITS,\r
+ CF_DELAYBITS => 2)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ cf_delay => CFpu_delay,\r
+ pulse_valid => pileup_valid_lowgain_S,\r
+ pulse_detected => pileup_pulse_lowgain_S,\r
+ pileup_detected => '0',\r
+ clear_waveform => '0',\r
+ data_in => pileup_ADC_minus_baseline_lowgain_S,\r
+ integral => pileup_integral_lowgain_S,\r
+ superburstnumber => superburstnumber_S,\r
+ timestamp => timestampcounter_S,\r
+ pulse_write => pileupdta_write_lowgain_S,\r
+ pulse_superburst => pileupdta_superburst_lowgain_S,\r
+ pulse_timestamp => pileupdta_timestamp_lowgain_S,\r
+ pulse_skipped => open,\r
+ pulse_energy => pileupdta_energy_lowgain_S,\r
+ pulse_CF1 => pileupdta_CF1_lowgain_S,\r
+ pulse_CF2 => pileupdta_CF2_lowgain_S);\r
+\r
+FEE_collect_pileup_pulses_low: FEE_collect_pileup_pulses port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ pulse_active => pulse_active_lowgain_S,\r
+ pileup_valid => pileup_valid_lowgain_S,\r
+ detect_singlepulse => detect_singlepulse_lowgain_S,\r
+ detect_pileuppulse => detect_pileuppulse_lowgain_S,\r
+ detect_clearpulse => detect_clearpulse_lowgain_S,\r
+ detect_purge => detect_purge_lowgain_S,\r
+ data_in_write => pileupdta_write_lowgain_S,\r
+ data_in_superburst => pileupdta_superburst_lowgain_S,\r
+ data_in_timestamp => pileupdta_timestamp_lowgain_S,\r
+ data_in_energy => pileupdta_energy_lowgain_S,\r
+ data_in_CF1 => pileupdta_CF1_lowgain_S,\r
+ data_in_CF2 => pileupdta_CF2_lowgain_S,\r
+ data_out_write => pileup_write_lowgain_S,\r
+ data_out_superburst => pileup_superburst_lowgain_S,\r
+ data_out_timestamp => pileup_timestamp_lowgain_S,\r
+ data_out_energy => pileup_energy_lowgain_S,\r
+ data_out_CF1 => pileup_CF1_lowgain_S,\r
+ data_out_CF2 => pileup_CF2_lowgain_S,\r
+ data_out_skipped => pileup_skipped_lowgain_S);\r
+detect_purge_lowgain_S <= '1' when (detect_pileuppulse_highgain_S='1') or (detect_singlepulse_highgain_S='1') else '0';\r
+ \r
+ \r
+-- Write to output ------------------------------------------------------------------------------------------------------------\r
+pulsedata_write <= '1' when (pulsedata_write_S='1') and (pulsedata_allowed='1') else '0';\r
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ if (pulsedata_write_S='1') and (pulsedata_allowed='0') then\r
+ pulse_skipped_occurred_S <= '1';\r
+ end if;\r
+ if (pulsedata_write_S='1') and (pulsedata_allowed='1') then\r
+ pulse_skipped_occurred_S <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
+ \r
+-- pulsedata_write_S <= '1' when (enable_waveform='0') \r
+ -- and (((pulse_write_highgain_S='1') and (conv_integer(unsigned(pulse_energy_highgain_S))>conv_integer(unsigned(threshold_highgain))))\r
+ -- or ((pulse_write_lowgain_S='1') and (conv_integer(unsigned(pulse_energy_lowgain_S))>conv_integer(unsigned(threshold_lowgain))))\r
+ -- or ((pileup_write_highgain_S='1') and (conv_integer(unsigned(pileup_energy_highgain_S))>conv_integer(unsigned(threshold_highgain))))\r
+ -- or ((pileup_write_lowgain_S='1') and (conv_integer(unsigned(pileup_energy_lowgain_S))>conv_integer(unsigned(threshold_lowgain)))))\r
+ -- else '0';\r
+pulsedata_write_S <= '1' when (enable_waveform='0') \r
+ and ((pulse_write_highgain_S='1')\r
+ or (pulse_write_lowgain_S='1')\r
+ or (pileup_write_highgain_S='1')\r
+ or (pileup_write_lowgain_S='1'))\r
+ else '0';\r
+pulsedata_superburst <= pulsedata_superburst_S;\r
+pulsedata_superburst_S <= \r
+ pulse_superburst_highgain_S when pulse_write_highgain_S='1' else\r
+ pulse_superburst_lowgain_S when pulse_write_lowgain_S='1' else\r
+ pileup_superburst_highgain_S when pileup_write_highgain_S='1' else\r
+ pileup_superburst_lowgain_S when pileup_write_lowgain_S='1'\r
+;-- else (others => '0');\r
+pulsedata_timestamp <= pulsedata_timestamp_S;\r
+pulsedata_timestamp_S <= \r
+ pulse_timestamp_highgain_S when pulse_write_highgain_S='1' else\r
+ pulse_timestamp_lowgain_S when pulse_write_lowgain_S='1' else\r
+ pileup_timestamp_highgain_S when pileup_write_highgain_S='1' else\r
+ pileup_timestamp_lowgain_S when pileup_write_lowgain_S='1' \r
+;-- else (others => '0');\r
+pulsedata_energy <=\r
+ pulse_energy_highgain_S when pulse_write_highgain_S='1' else\r
+ pulse_energy_lowgain_S when pulse_write_lowgain_S='1' else\r
+ pileup_energy_highgain_S when pileup_write_highgain_S='1' else\r
+ pileup_energy_lowgain_S when pileup_write_lowgain_S='1' \r
+;-- else (others => '0');\r
+pulsedata_CFvalbefore <=\r
+ pulse_CF1_highgain_S when pulse_write_highgain_S='1' else\r
+ pulse_CF1_lowgain_S when pulse_write_lowgain_S='1' else\r
+ pileup_CF1_highgain_S when pileup_write_highgain_S='1' else\r
+ pileup_CF1_lowgain_S when pileup_write_lowgain_S='1' \r
+;-- else (others => '0');\r
+pulsedata_CFvalafter <=\r
+ pulse_CF2_highgain_S when pulse_write_highgain_S='1' else\r
+ pulse_CF2_lowgain_S when pulse_write_lowgain_S='1' else\r
+ pileup_CF2_highgain_S when pileup_write_highgain_S='1' else\r
+ pileup_CF2_lowgain_S when pileup_write_lowgain_S='1' \r
+;-- else (others => '0');\r
+pulsedata_status0_S <= \r
+ STATBYTE_FEEPULSESKIPPED when ((pulse_skipped_highgain_S='1') and (pulse_write_highgain_S='1')) \r
+ or ((pulse_skipped_lowgain_S='1') and (pulse_write_lowgain_S='1')) \r
+ or ((pileup_skipped_highgain_S='1') and (pileup_write_highgain_S='1'))\r
+ or ((pileup_skipped_lowgain_S='1') and (pileup_write_lowgain_S='1'))\r
+ or (pulse_skipped_occurred_S='1') else\r
+ (others => '0');\r
+pulsedata_status1_S <= \r
+ STATBYTE_PILEUPHIT when (pileup_write_highgain_S='1') or (pileup_write_lowgain_S='1') else\r
+ (others => '0');\r
+pulsedata_status <= pulsedata_status0_S or pulsedata_status1_S;\r
+pulsedata_lowgain <= '1' when (pulse_write_lowgain_S='1') or (pileup_write_lowgain_S='1') else '0';\r
+\r
+gen_waves: if NOWAVEFORMS=false generate\r
+reset_buffer_S <= '1' when (reset='1') or (enable_waveform='0') else '0';\r
+FEE_pulsewaveform_buffer1: FEE_pulsewaveform_buffer port map(\r
+ clock => clock,\r
+ reset => reset_buffer_S,\r
+ pulse_valid => detect_pulse_valid_highgain_S,\r
+ pulse_rising => pulse_rising_highgain_S,\r
+ pulse_detected => detect_singlepulse_highgain_S,\r
+ pileup_detected => detect_pileuppulse_highgain_S,\r
+ clear_waveform => detect_clearpulse_highgain_S,\r
+ data_in => ADC_minus_baseline_highgain_S,\r
+ superburst => detect_superburst_S(15 downto 0),\r
+ timestamp => detect_timestamp_S,\r
+ data_out => wavedata_highgain_S,\r
+ data_out_read => wavedata_read_highgain_S,\r
+ data_out_available => wavedata_available_highgain_S,\r
+ overflow => wave_overflow_highgain_S);\r
+\r
+FEE_pulsewaveform_buffer2: FEE_pulsewaveform_buffer port map(\r
+ clock => clock,\r
+ reset => reset_buffer_S,\r
+ pulse_valid => detect_pulse_valid_lowgain_S,\r
+ pulse_rising => pulse_rising_lowgain_S,\r
+ pulse_detected => detect_singlepulse_lowgain_S,\r
+ pileup_detected => detect_pileuppulse_lowgain_S,\r
+ clear_waveform => detect_clearpulse_lowgain_S,\r
+ data_in => ADC_minus_baseline_lowgain_S,\r
+ superburst => detect_superburst_S(15 downto 0),\r
+ timestamp => detect_timestamp_S,\r
+ data_out => wavedata_lowgain_S,\r
+ data_out_read => wavedata_read_lowgain_S,\r
+ data_out_available => wavedata_available_lowgain_S,\r
+ overflow => wave_overflow_lowgain_S); \r
+ \r
+FEE_waveform_to_36bits1: FEE_waveform_to_36bits \r
+ generic map(\r
+ ADCNUMBER => ADCNUMBER)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ data_in => wavedata_highgain_S,\r
+ data_in_available => wavedata_available_highgain_S,\r
+ data_in_read => wavedata_read_highgain_S,\r
+ overflow_in => wave_overflow_highgain_S,\r
+ wavedata_out => wavedata1_out_S,\r
+ wavedata_write => wavedata1_write_S,\r
+ wavedata_inpipe => wavedata1_inpipe_S,\r
+ wavedata_allowed => wavedata1_allowed_S,\r
+ wavedata_almostfull => wavedata_almostfull,\r
+ overflow_out => wave_overflow_hg_S,\r
+ error => wave_error_to36_1_S);\r
+\r
+FEE_waveform_to_36bits2: FEE_waveform_to_36bits \r
+ generic map(\r
+ ADCNUMBER => ADCNUMBER+1)\r
+ port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ data_in => wavedata_lowgain_S,\r
+ data_in_available => wavedata_available_lowgain_S,\r
+ data_in_read => wavedata_read_lowgain_S,\r
+ overflow_in => wave_overflow_lowgain_S,\r
+ wavedata_out => wavedata2_out_S,\r
+ wavedata_write => wavedata2_write_S,\r
+ wavedata_inpipe => wavedata2_inpipe_S,\r
+ wavedata_allowed => wavedata2_allowed_S,\r
+ wavedata_almostfull => wavedata_almostfull,\r
+ overflow_out => wave_overflow_lg_S,\r
+ error => wave_error_to36_2_S);\r
+\r
+FEE_wavemux2to1_pileup: FEE_wavemux2to1 port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ data1_in => wavedata1_out_S,\r
+ data1_in_write => wavedata1_write_S,\r
+ data1_in_available => wavedata1_inpipe_S,\r
+ data1_in_allowed => wavedata1_allowed_S,\r
+ data2_in => wavedata2_out_S,\r
+ data2_in_write => wavedata2_write_S,\r
+ data2_in_available => wavedata2_inpipe_S,\r
+ data2_in_allowed => wavedata2_allowed_S,\r
+ data_out => wavedata_out_S,\r
+ data_out_write => wavedata_write_S,\r
+ data_out_available => wavedata_available,\r
+ data_out_allowed => wavedata_allowed,\r
+ error => wave_error_S,\r
+ timeerror => open);\r
+wavedata_out <= wavedata_out_S;\r
+wavedata_write <= wavedata_write_S;\r
+end generate;\r
+\r
+\r
+gen_nowaves: if NOWAVEFORMS=true generate\r
+ wavedata_out <= (others => '0');\r
+ wavedata_write <= '0';\r
+ wavedata_available <= '0';\r
+ wave_error_S <= '0';\r
+end generate;\r
\r
-----------------------------------------------------------------\r
-- tests:\r
-
+\r
process(clock)\r
-variable prev_data_V : std_logic_vector(3 downto 0);
-begin
+variable prev_data_V : std_logic_vector(3 downto 0);\r
+begin\r
if rising_edge(clock) then\r
- testword0_S(35) <= '0';\r
- if pileupdata_write_S='1' then\r
- case pileupdata_out_S(35 downto 32) is\r
+ data_error_S <= '0';\r
+ if wavedata_write_S='1' then\r
+ case wavedata_out_S(35 downto 32) is\r
when "0000" =>\r
if (prev_data_V/="0100") and (prev_data_V/="0101") then\r
- testword0_S(35) <= '1';\r
+ data_error_S <= '1';\r
end if;\r
when "0001" =>\r
if (prev_data_V/="0000") then\r
- testword0_S(35) <= '1';\r
+ data_error_S <= '1';\r
end if;\r
when "0010" =>\r
if (prev_data_V/="0001") and (prev_data_V/="0010") then\r
- testword0_S(35) <= '1';\r
+ data_error_S <= '1';\r
end if;\r
when "0100" =>\r
if (prev_data_V/="0010") then\r
- testword0_S(35) <= '1';\r
+ data_error_S <= '1';\r
end if;\r
when "0101" =>\r
if (prev_data_V/="0010") then\r
- testword0_S(35) <= '1';\r
+ data_error_S <= '1';\r
end if;\r
when others =>\r
- testword0_S(35) <= '1';\r
+ data_error_S <= '1';\r
end case;\r
- prev_data_V := pileupdata_out_S(35 downto 32);\r
- end if;
- end if;
+ prev_data_V := wavedata_out_S(35 downto 32);\r
+ end if;\r
+ end if;\r
end process;\r
\r
+process(clock)\r
+variable sb_V : std_logic_vector(30 downto 0) := (others => '0');\r
+variable tm_V : std_logic_vector(15 downto 0) := (others => '0');\r
+begin\r
+ if rising_edge(clock) then\r
+ pulsetime_error_S <= '0';\r
+ if (pulsedata_write_S='1') and (pulsedata_allowed='1') then\r
+ if (pulsedata_superburst_S & pulsedata_timestamp_S) < (sb_V & tm_V) then\r
+ pulsetime_error_S <= '1';\r
+ end if;\r
+ sb_V := pulsedata_superburst_S;\r
+ tm_V := pulsedata_timestamp_S;\r
+ end if;\r
+ end if;\r
+end process;\r
\r
-testword0 <= testword0_S;\r
-\r
-\r
-\r
-testword0_S(3 downto 0) <= data_out_highgain_S(35 downto 32);
-testword0_S(4) <= data_out_read_highgain_S;
-testword0_S(5) <= data_out_available_highgain_S;
---testword0_S(6) <= overflow_highgain_S;
-testword0_S(9 downto 6) <= data_out_lowgain_S(35 downto 32);
-testword0_S(10) <= data_out_read_lowgain_S;
-testword0_S(11) <= data_out_available_lowgain_S;
---testword0_S(13) <= overflow_lowgain_S;
-\r
-testword0_S(15 downto 12) <= pileupdata1_out_S(35 downto 32);
-testword0_S(16) <= pileupdata1_write_S;
-testword0_S(17) <= pileupdata1_allowed_S;
-testword0_S(18) <= pileupdata_almostfull;
---testword0_S(21) <= overflow_hg_S;
-testword0_S(19) <= error_to36_1_S;
-
-testword0_S(23 downto 20) <= pileupdata2_out_S(35 downto 32);
-testword0_S(24) <= pileupdata2_write_S;
-testword0_S(25) <= pileupdata2_allowed_S;
-testword0_S(26) <= pileupdata_almostfull;
---testword0_S(30) <= overflow_lg_S;
-testword0_S(27) <= error_to36_2_S;
-testword0_S(28) <= error_pileup_S;
-\r
-testword0_S(32 downto 29) <= pileupdata_out_S(35 downto 32);\r
-testword0_S(33) <= pileupdata_write_S;\r
-testword0_S(34) <= pileupdata_allowed;\r
+ \r
+ \r
+end Behavioral;\r
\r
\r
-
-end Behavioral;
-
-
-- Modifications: \r
-- 16-09-2014: name changed from eventdetector to FEE_eventdetector
-- 10-10-2014: threshold for end of pulse is half the normal threshold
+-- 15-04-2016: max_data output clipped to positive values
----------------------------------------------------------------------------------\r
\r
library IEEE;
process(clock)\r
variable counter_V : std_logic_vector(3 downto 0);\r
---variable below_zero_V : std_logic;
begin
if rising_edge(clock) then\r
if reset='1' then\r
if abovetriggerlevel_S='1' then\r
freeze_extend_S <= '1';\r
counter_V := (others => '0');\r
- -- below_zero_V := '0';\r
elsif counter_V(counter_V'left)='0' then\r
- -- if (conv_integer(signed(data_in))>0) and (below_zero_V='0') then\r
- -- counter_V := (others => '0');\r
- -- else\r
- -- below_zero_V := '1';\r
- counter_V := counter_V+1;\r
- -- end if;\r
+ counter_V := counter_V+1;\r
freeze_extend_S <= '1';\r
else\r
freeze_extend_S <= '0';\r
end if;\r
end process;\r
-pulsetoolong_S <= counter_S(conv_integer(unsigned(maxabovebaseline)));
+pulsetoolong_S <= counter_S(10); --// counter_S(conv_integer(unsigned(maxabovebaseline)));
data_below_max_S <= '1' when conv_integer(signed(data_in))<=conv_integer(signed(max_data_S)) else '0';
pulse_rising <= '1'
when (data_below_max_S='0')
else
if abovetriggerlevel_S='0' then
counter_S <= (others => '0');
- max_data_S <= data_in;\r
+ if data_in>=0 then
+ max_data_S <= data_in;
+ else
+ max_data_S <= (others => '0');
+ end if;\r
half_threshold_S <= '0';
elsif pulsetoolong_S='0' then\r
if (half_threshold_S='0') and (counter_S(2)='1') then\r
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 02-09-2014
-- Module Name: FEE_extract_pulse
-- Modifications:
-- 10-10-2014 Integral as measurement for the energy instead of maximum
-- 27-10-2014 Constant Fraction with negative or equal instead of negative
+-- 27-05-2016 Increase time window to measure valid CF zerocrossing
+-- 21-01-2017 Enable shorter pulses, integrate one additional sample at the end of the pulse
+-- 05-04-2017 Shift register optimized for area
----------------------------------------------------------------------------------
library IEEE;
--
-- generics
-- ADCBITS : Number of bits from the ADC's. The input data is signed and has ADCBITS+1 bits.
--- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
-- CF_DELAYBITS : number of bits for the Constant Fraction delay
--
-- inputs
-- reset : synchrounous reset
-- cf_delay : delay (number of ADC samples) for the constant fraction
-- pulse_valid : input data is valid pulse data
--- pulse_rising : the pulse has not yet reached its maximum
-- pulse_detected : previous samples are regarded as valid pulse data
-- pileup_detected : previous samples are regarded as pileup waveform data
-- clear_waveform : previous samples do not give valid data, clear this data
entity FEE_extract_pulse is
generic (
ADCBITS : natural := 14;
- WAVEFORMBUFFERSIZE : natural := 10;
CF_DELAYBITS : natural := 8
);
Port (
reset : in std_logic;
cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
pulse_valid : in std_logic;
- pulse_rising : in std_logic;
pulse_detected : in std_logic;
pileup_detected : in std_logic;
clear_waveform : in std_logic;
superburstnumber : in std_logic_vector(30 downto 0);
timestamp : in std_logic_vector(15 downto 0);\r
pulse_write : out std_logic;\r
- pulse_superburst : out std_logic_vector(15 downto 0);\r
+ pulse_superburst : out std_logic_vector(30 downto 0);\r
pulse_timestamp : out std_logic_vector(15 downto 0);\r
pulse_skipped : out std_logic;\r
pulse_energy : out std_logic_vector(15 downto 0);\r
component shift_register is
generic (
- width : natural := ADCBITS+1; -- signed signal
+ width : natural := ADCBITS+1;
depthbits : natural := CF_DELAYBITS
);
port (
depth : in std_logic_vector((depthbits-1) downto 0);
data_out : out std_logic_vector((width-1) downto 0));
end component;
-\r
-constant zeros : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');\r
+component shift_register_small is
+ generic (
+ width : natural := ADCBITS+1;
+ depthbits : natural := CF_DELAYBITS
+ );
+ port (
+ clock : in std_logic;
+ data_in : in std_logic_vector((width-1) downto 0);
+ depth : in std_logic_vector((depthbits-1) downto 0);
+ data_out : out std_logic_vector((width-1) downto 0));
+end component;
+
\r
signal pulse_write_S : std_logic;\r
-signal pulse_superburst_S : std_logic_vector(15 downto 0);\r
-signal pulse_timestamp_S : std_logic_vector(15 downto 0);\r
+signal pulse_superburst_S : std_logic_vector(30 downto 0);\r
+signal pulse_timestamp_S : std_logic_vector(15 downto 0);
+signal pulse_energy_S : std_logic_vector(15 downto 0);
signal pulse_max_S : std_logic_vector(ADCBITS downto 0); \r
signal pulse_CF1_S : std_logic_vector(15 downto 0);\r
signal pulse_CF2_S : std_logic_vector(15 downto 0);\r
+signal pulse_detected_S : std_logic;
signal prev_setmax_S : std_logic; -- maximum set in previous clock cycle\r
signal prev_pulse_valid_S : std_logic; -- valid signal in previous clock cycle\r
-signal after_max_counter_S : std_logic_vector(CF_DELAYBITS downto 0) := (others => '0');\r
+signal after_max_counter_S : std_logic_vector(CF_DELAYBITS+1 downto 0) := (others => '0');\r
\r
signal pulse_skipped_S : std_logic := '0'; \r
-signal CF_available_S : std_logic := '0'; \r
+signal CF_available0_S : std_logic := '0';
+signal CF_available_S : std_logic;
\r
signal data_delayed_S : std_logic_vector(ADCBITS downto 0) := (others => '0');
signal data_delayedx4_S : std_logic_vector(ADCBITS+2 downto 0) := (others => '0');
signal prev_cf_signal_S : std_logic_vector(ADCBITS+3 downto 0) := (others => '0');
signal cf_negorzero_S : std_logic;\r
signal prev_cf_negorzero_S : std_logic;\r
-signal enable_CF_S : std_logic;\r
+signal enable_CF_S : std_logic;
+signal enable1_CF_S : std_logic;
+
+attribute mark_debug : string;
+
+
+-- attribute mark_debug of pulse_valid : signal is "true";
+-- attribute mark_debug of pulse_detected : signal is "true";
+-- attribute mark_debug of pulse_detected_S : signal is "true";
+-- attribute mark_debug of pulse_write_S : signal is "true";
+-- attribute mark_debug of CF_available0_S : signal is "true";
+-- attribute mark_debug of CF_available_S : signal is "true";
+-- attribute mark_debug of prev_setmax_S : signal is "true";
+-- attribute mark_debug of enable_CF_S : signal is "true";
+-- attribute mark_debug of after_max_counter_S : signal is "true";
+-- attribute mark_debug of cf_negorzero_S : signal is "true";
+-- attribute mark_debug of prev_cf_negorzero_S : signal is "true";
+-- attribute mark_debug of cf_signal_S : signal is "true";
+-- attribute mark_debug of pulse_skipped_S : signal is "true";
+
\r
begin\r
\r
pulse_write <= pulse_write_S;\r
pulse_superburst <= pulse_superburst_S;\r
-pulse_timestamp <= pulse_timestamp_S;\r
-pulse_skipped <= pulse_skipped_S;\r
-pulse_energy <= integral;\r
+pulse_timestamp <= pulse_timestamp_S;
+pulse_energy <= pulse_energy_S;\r
pulse_CF1 <= pulse_CF1_S;\r
pulse_CF2 <= pulse_CF2_S;\r
-\r
-pulse_write_S <= pulse_detected when CF_available_S='1' else '0';\r
-\r
-check_skipped: process(clock)\r
-variable holdcounter_V : integer range 0 to 3 := 3; -- keep value at the output for 4 clock cycles
-begin\r
- if rising_edge(clock) then\r
- if (pulse_detected='1') and (CF_available_S='0') then\r
- pulse_skipped_S <= '1';\r
- elsif pulse_detected='1' then\r
- holdcounter_V := 0;\r
- elsif holdcounter_V<3 then\r
- holdcounter_V := holdcounter_V+1;\r
- if holdcounter_V=2 then\r
- pulse_skipped_S <= '0';\r
- end if;\r
- end if;\r
- end if;\r
-end process;\r
-\r
+process(clock)
+begin
+ if rising_edge(clock) then
+ pulse_write_S <= '0';
+ if pulse_detected='1' then
+-- pulse_energy_S <= integral;
+ end if;
+ if pulse_detected_S='1' then
+ pulse_energy_S <= integral;
+ if CF_available_S='1' then
+ pulse_skipped <= pulse_skipped_S;
+ pulse_write_S <= '1';
+ pulse_skipped_S <= '0';
+ else
+ pulse_skipped_S <= '1';
+ end if;
+ end if;
+ pulse_detected_S <= pulse_detected;
+ end if;
+end process;
\r
get_maxima: process(clock)
begin\r
after_max: process(clock)
begin\r
if rising_edge(clock) then\r
- if reset='1' then\r
- enable_CF_S <= '0';\r
- else \r
- if (pulse_valid='0') then\r
- enable_CF_S <= '0';\r
+ if (pulse_valid='0') then\r
+ enable1_CF_S <= '0';\r
+ else\r
+ if prev_pulse_valid_S='0' then\r
+ enable1_CF_S <= '1';\r
else\r
- if prev_pulse_valid_S='0' then\r
- enable_CF_S <= '1';\r
+ if prev_setmax_S='1' then\r
+ after_max_counter_S <= (others => '0');\r
else\r
- if prev_setmax_S='1' then\r
- after_max_counter_S <= (others => '0');\r
- else\r
- if after_max_counter_S(CF_DELAYBITS-1 downto 0) = cf_delay then\r
- enable_CF_S <= '0';\r
- end if;\r
- if after_max_counter_S(CF_DELAYBITS)='0' then\r
- after_max_counter_S <= after_max_counter_S+1;\r
- end if;\r
+ if after_max_counter_S(CF_DELAYBITS downto 0) = cf_delay & '0' then\r
+ enable1_CF_S <= '0';\r
+ end if;\r
+ if after_max_counter_S(after_max_counter_S'left)='0' then\r
+ after_max_counter_S <= after_max_counter_S+1;\r
end if;\r
end if;\r
end if;\r
end if;\r
end if;\r
end process;
+enable_CF_S <= '1' when (enable1_CF_S='1') or ((pulse_valid='1') and (prev_pulse_valid_S='0')) or (pulse_detected='1') or (pulse_detected_S='1') else '0';
-shiftregister1: shift_register
+shiftregister1: shift_register_small
generic map(
width => ADCBITS+1, -- signed signal
depthbits => CF_DELAYBITS
)
port map(
clock => clock,
- reset => reset,
- hold => '0',
+-- reset => '0',
+-- hold => '0',
data_in => data_in,
depth => cf_delay,
data_out => data_delayed_S);\r
variable pulse_CF2_V : integer range -2**(ADCBITS+3) to 2**(ADCBITS+3)-1;
begin
if (rising_edge(clock)) then\r
- if reset='1' then\r
- CF_available_S <= '0';\r
- else
- if (pulse_valid='0') and (pulse_detected='0') then\r
- CF_available_S <= '0';\r
- else\r
- if prev_cf_negorzero_S='1' then\r
- if cf_negorzero_S='0' then\r
- if enable_CF_S='1' then\r
- pulse_CF1_V := -conv_integer(signed(prev_cf_signal_S));\r
- if pulse_CF1_V>65535 then\r
- pulse_CF1_S <= x"ffff";\r
- else\r
- pulse_CF1_S <= conv_std_logic_vector(pulse_CF1_V,16);\r
- end if;\r
- pulse_CF2_V := conv_integer(signed(cf_signal_S));\r
- if pulse_CF2_V>65535 then\r
- pulse_CF2_S <= x"ffff";\r
- else\r
- pulse_CF2_S <= conv_std_logic_vector(pulse_CF2_V,16);\r
- end if;\r
- pulse_superburst_S <= superburstnumber(15 downto 0);\r
- pulse_timestamp_S <= timestamp;\r
- CF_available_S <= '1';\r
+ if (pulse_valid='0') and (pulse_detected='0') and (pulse_detected_S='0') then\r
+ CF_available0_S <= '0';\r
+ else\r
+ if prev_cf_negorzero_S='1' then\r
+ if cf_negorzero_S='0' then\r
+ if enable_CF_S='1' then\r
+ pulse_CF1_V := -conv_integer(signed(prev_cf_signal_S));\r
+ if pulse_CF1_V>65535 then\r
+ pulse_CF1_S <= x"ffff";\r
+ else\r
+ pulse_CF1_S <= conv_std_logic_vector(pulse_CF1_V,16);\r
+ end if;\r
+ pulse_CF2_V := conv_integer(signed(cf_signal_S));\r
+ if pulse_CF2_V>65535 then\r
+ pulse_CF2_S <= x"ffff";\r
+ else\r
+ pulse_CF2_S <= conv_std_logic_vector(pulse_CF2_V,16);\r
end if;\r
- else\r
+ pulse_superburst_S <= superburstnumber;\r
+ pulse_timestamp_S <= timestamp;\r
+ CF_available0_S <= '1';\r
end if;\r
+ else\r
end if;\r
end if;\r
end if;\r
prev_cf_signal_S <= cf_signal_S;\r
end if;\r
end process;\r
-\r
+CF_available_S <= '1' when (CF_available0_S='1')
+ or (((pulse_valid='1') or (pulse_detected_S='1'))
+ and ((prev_cf_negorzero_S='1') and (cf_negorzero_S='0') and (enable_CF_S='1')))
+ else '0';\r
end Behavioral;
signal fifo_databuf_S : std_logic_vector(31 downto 0);
signal data_out_S : std_logic_vector(7 downto 0);
signal char_is_k_S : std_logic;
-signal fifo_empty_S : std_logic;
-signal prev_fifo_empty_S : std_logic;
+signal fifo_empty_S : std_logic;\r
signal fifo_buffilled_S : std_logic := '0';
-signal fifo_read_after1clk_S : std_logic := '0';
+signal fifo_read_after1clk_S : std_logic := '0';\r
signal TX_DLM_S : std_logic;
-signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);
-signal bytecounter_S : integer range 0 to 3 := 0;
+signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);\r
+signal bytecounter_S : integer range 0 to 3 := 0;\r
signal write_data_S : std_logic;
signal lastbytefilled_S : std_logic;
-signal lastbyte_S : std_logic_vector(7 downto 0);
-
+signal lastbyte_S : std_logic_vector(7 downto 0);\r
+\r
begin
-
+\r
process (read_clock)
begin
- if rising_edge(read_clock) then
- data_out <= data_out_S;
+ if rising_edge(read_clock) then\r
+ data_out <= data_out_S;\r
char_is_k <= char_is_k_S;
end if;
-end process;
-
-
+end process;\r
+\r
+ \r
fifo: async_fifo_512x32 port map(
rst => reset,
wr_clk => write_clock,
fifo_read_S <= '1' when (fifo_empty_S='0') and (TX_DLM='0') and (fifo_read_after1clk_S='0') and (lastbytefilled_S='0')
and (((bytecounter_S=0) and (fifo_buffilled_S='0')) or ((bytecounter_S=3) and (fifo_buffilled_S='0')))
- else '0';
+ else '0';\r
-data_out_S <=
+data_out_S <= \r
KCHARSODA when TX_DLM='1' else
- TX_DLM_WORD_S when (TX_DLM_S='1') else
- KCHAR285 when (write_data_S='0') else
- lastbyte_S when (lastbytefilled_S='1') else
- fifo_dataout_S(31 downto 24) when (fifo_read_after1clk_S='1') else
- fifo_databuf_S((3-bytecounter_S)*8+7 downto (3-bytecounter_S)*8);
-
+ TX_DLM_WORD_S when (TX_DLM_S='1') else\r
+ KCHAR285 when (write_data_S='0') else\r
+ lastbyte_S when (lastbytefilled_S='1') else\r
+ fifo_dataout_S(31 downto 24) when (fifo_read_after1clk_S='1') else\r
+ fifo_databuf_S((3-bytecounter_S)*8+7 downto (3-bytecounter_S)*8);\r
+ \r
char_is_k_S <=
'1' when TX_DLM='1' else
- '0' when (TX_DLM_S='1') else
- '1' when (write_data_S='0') else
- '0' when fifo_read_after1clk_S='1' else
+ '0' when (TX_DLM_S='1') else\r
+ '1' when (write_data_S='0') else\r
+ '0' when fifo_read_after1clk_S='1' else \r
'0';
-
-write_data_S <= '1' when ((TX_DLM='0') and (TX_DLM_S='0')) and
- ((fifo_read_after1clk_S='1') or (bytecounter_S/=0) or (fifo_buffilled_S='1') or (lastbytefilled_S='1')) else '0';
-
+\r
+write_data_S <= '1' when ((TX_DLM='0') and (TX_DLM_S='0')) and \r
+ ((fifo_read_after1clk_S='1') or (bytecounter_S/=0) or (fifo_buffilled_S='1') or (lastbytefilled_S='1')) else '0';\r
+\r
tx_process : process (read_clock)
begin
if rising_edge(read_clock) then
if reset='1' then
fifo_read_after1clk_S <= '0';
- TX_DLM_S <= '0';
- lastbytefilled_S <= '0';
+ TX_DLM_S <= '0';\r
+ lastbytefilled_S <= '0';\r
bytecounter_S <= 0;
- else
- TX_DLM_S <= TX_DLM;
- if TX_DLM='1' then
- TX_DLM_WORD_S <= TX_DLM_WORD;
- end if;
+ else\r
+ TX_DLM_S <= TX_DLM;\r
+ if TX_DLM='1' then\r
+ TX_DLM_WORD_S <= TX_DLM_WORD;\r
+ end if;\r
fifo_read_after1clk_S <= fifo_read_S;
- prev_fifo_empty_S <= fifo_empty_S;
- if not ((TX_DLM='1') or (TX_DLM_S='1') or (write_data_S='0')) then
- lastbytefilled_S <= '0';
- end if;
- if (fifo_read_after1clk_S='1') then
- if (TX_DLM='1') and (fifo_buffilled_S='0') and (bytecounter_S=3) then
- lastbytefilled_S <= '1';
- lastbyte_S <= fifo_databuf_S(7 downto 0);
- end if;
- fifo_databuf_S <= fifo_dataout_S;
- fifo_buffilled_S <= '1';
- end if;
- if (TX_DLM='1') or (TX_DLM_S='1') then
- elsif lastbytefilled_S='1' then
- bytecounter_S <= 0;
- else
- case bytecounter_S is
- when 0 =>
- if (fifo_buffilled_S='1') or (fifo_read_after1clk_S='1') then
- fifo_buffilled_S <= '1';
- bytecounter_S <= 1;
- end if;
- when 1 =>
- fifo_buffilled_S <= '1';
- bytecounter_S <= 2;
- when 2 =>
- fifo_buffilled_S <= '0';
- bytecounter_S <= 3;
- when 3 =>
- fifo_buffilled_S <= '0';
- bytecounter_S <= 0;
- when others =>
- fifo_buffilled_S <= '0';
- bytecounter_S <= 0;
- end case;
- end if;
+ if not ((TX_DLM='1') or (TX_DLM_S='1') or (write_data_S='0')) then\r
+ lastbytefilled_S <= '0';\r
+ end if;\r
+ if (TX_DLM='1') and (fifo_buffilled_S='0') and (bytecounter_S=3) then \r
+ lastbytefilled_S <= '1';\r
+ lastbyte_S <= fifo_databuf_S(7 downto 0);\r
+ end if;\r
+ if (fifo_read_after1clk_S='1') then\r
+ fifo_databuf_S <= fifo_dataout_S;\r
+ fifo_buffilled_S <= '1';\r
+ end if; \r
+ if (TX_DLM='1') or (TX_DLM_S='1') then\r
+ elsif lastbytefilled_S='1' then\r
+ bytecounter_S <= 0;\r
+ else\r
+ case bytecounter_S is\r
+ when 0 =>\r
+ if (fifo_buffilled_S='1') or (fifo_read_after1clk_S='1') then\r
+ fifo_buffilled_S <= '1';\r
+ bytecounter_S <= 1;\r
+ end if;\r
+ when 1 =>\r
+ fifo_buffilled_S <= '1';\r
+ bytecounter_S <= 2;\r
+ when 2 =>\r
+ fifo_buffilled_S <= '0';\r
+ bytecounter_S <= 3;\r
+ when 3 =>\r
+ fifo_buffilled_S <= '0';\r
+ bytecounter_S <= 0;\r
+ when others =>\r
+ fifo_buffilled_S <= '0';\r
+ bytecounter_S <= 0;\r
+ end case;\r
+ end if;\r
end if;
end if;
end process;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 14-03-2016
+-- Module Name: FEE_fiforead2write
+-- Description: Converts reading from fifo to write
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+----------------------------------------------------------------------------------
+-- FEE_fiforead2write
+-- Converts reading from fifo to write
+--
+--
+--
+-- Library
+--
+--
+-- Generics
+-- BITS : number of bits at input and output
+--
+-- Inputs:
+-- clock : clock input for 64 bits data
+-- data_in : input data
+-- data_in_empty : empty from connected fifo
+-- data_out_allowed : writing of input data is allowed
+--
+-- Outputs:
+-- data_in_read : read data from fifo
+-- data_out : output data
+-- data_out_write : write signal for output data
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_fiforead2write is
+ generic(
+ BITS : integer := 32
+ );
+ port(
+ clock : in std_logic;
+ data_in : in std_logic_vector(BITS-1 downto 0);
+ data_in_empty : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(BITS-1 downto 0);
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic
+ );
+end FEE_fiforead2write;
+
+
+
+architecture behaviour of FEE_fiforead2write is
+
+signal data_in_read_S : std_logic;
+signal data_in_read_aftr1clk_S : std_logic := '0';
+signal data_out_filled_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+signal data_out_buf_S : std_logic_vector(BITS-1 downto 0);
+signal data_out_S : std_logic_vector(BITS-1 downto 0);
+
+
+begin
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_in_empty='0') and (data_out_allowed='1') and (data_out_filled_S='0') else '0';
+out_process: process(clock)
+begin
+ if rising_edge(clock) then
+ data_out_trywrite_S <= '0';
+ data_in_read_aftr1clk_S <= data_in_read_S;
+ if data_in_read_aftr1clk_S='1' then
+ if data_out_allowed='1' then
+ if (data_out_trywrite_S='1') then
+ if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+ data_out_S <= data_out_buf_S;
+ data_out_buf_S <= data_in;
+ data_out_trywrite_S <= '1'; -- write previous data
+ data_out_filled_S <= '1';
+ else -- write new data
+ data_out_S <= data_in;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '0';
+ end if;
+ else -- data_out_trywrite_S='0'
+ if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+ data_out_S <= data_out_buf_S;
+ data_out_buf_S <= data_in;
+ data_out_trywrite_S <= '1'; -- write previous data
+ data_out_filled_S <= '1';
+ else -- -- data_out_filled_S='0', write new data
+ data_out_S <= data_in;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '0';
+ end if;
+ end if;
+ else -- data_out_allowed='0'
+ if data_out_trywrite_S='1' then -- try again, save new data
+ data_out_buf_S <= data_in;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '1';
+ if data_out_filled_S='1' then
+ --error
+ end if;
+ else -- data_out_trywrite_S='0'
+ if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+ data_out_S <= data_out_buf_S;
+ data_out_buf_S <= data_in;
+ data_out_trywrite_S <= '1'; -- write previous data
+ data_out_filled_S <= '1';
+ else -- data_out_filled_S='0'
+ data_out_S <= data_in;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '0';
+ end if;
+ end if;
+ end if;
+ elsif (data_out_allowed='0') and (data_out_trywrite_S='1') then -- try again
+ data_out_trywrite_S <= '1';
+ elsif data_out_filled_S='1' then
+ if data_out_allowed='1' then
+ data_out_S <= data_out_buf_S;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '0';
+ end if;
+ else
+ end if;
+ end if;
+end process;
+data_out_write <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+data_out <= data_out_S;
+
+end behaviour;
+
signal rxReset_S : std_logic :='0';\r
signal rxRecClk_S : std_logic :='0';\r
signal rxRecClk_buf_S : std_logic :='0';\r
-signal rxRecClk_double_S : std_logic :='0';\r
\r
signal rxLocked_S : std_logic;\r
signal txLocked_S : std_logic;\r
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
signal gtx0_txdlyaligndisable_i : std_logic;
- signal gtx0_txdlyalignmonenb_i : std_logic;
+ signal gtx0_txdlyalignmonenb_i : std_logic := '0';
signal gtx0_txdlyalignmonitor_i : std_logic_vector(7 downto 0);
signal gtx0_txdlyalignreset_i : std_logic;
signal gtx0_txenpmaphasealign_i : std_logic;
-- O => rxRecClk_buf_S);\r
rxrecclk_bufr1_i : BUFR
- generic map ( BUFR_DIVIDE => "BYPASS" )
+ generic map ( \r
+ BUFR_DIVIDE => "BYPASS",\r
+ SIM_DEVICE => "VIRTEX6")
port map (
CE => '1',
CLR => '0',
-- I => txOutClk_S);\r
txLocked_S <= '1' when (txResetdone_S='1') and (gtx0_tx_sync_done_i='1') else '0'; \r
\r
-rxRecClk_double_S <= '0';\r
- \r
process(rxRecClk_buf_S)
begin
if rising_edge(rxRecClk_buf_S) then\r
architecture Behavioral of FEE_measure_frequency is
signal counter_S : std_logic_vector(31 downto 0) := (others => '0');
+signal frequency_S : std_logic_vector(31 downto 0) := (others => '0');
begin
-\r
+
+frequency <= frequency_S;\r
process(clock)\r
begin
if (rising_edge(clock)) then \r
if onesecondpulse='1' then\r
- frequency <= counter_S;\r
+ frequency_S <= counter_S;\r
if pulse='1' then\r
counter_S <= x"00000001";\r
else\r
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 05-03-2012
-- Module Name: FEE_mux2to1
-- Description: compare timestamp of 36bits data pass on first
-- Modifications:
-- 16-10-2014: 3*36bits words; bits 35 and 34 as indenticication
+-- 25-09-2015: compare bug fixed at FFFF->0000 superburst change
+-- 12-10-2015: bug fixed : pulse skipped bit in wrong channel
+-- 22-02-2017: rewritten to parallel data instead of 36bits words
----------------------------------------------------------------------------------
library IEEE;
------------------------------------------------------------------------------------------------------
-- FEE_mux2to1
--- Compare timestamp of 36bits data and pass on first
--- If data from only one is available then this is passed on directly
--- The 36-bits data contains packets with 3 words:
--- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
--- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
--- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- Compare timestamp of two hits and pass data on in right order.
+-- If data from only one is available then this data is passed on directly
+-- The data consists of the members of a hit :
+-- channel : number of the ADC
+-- statusbyte : 8 bits with status
+-- energy : energy of a hit
+-- CFvalbefore : Constant Fraction method : sample before zero crossing
+-- CFvalafter : Constant Fraction method : sample after zero crossing
+-- timestamp : integer part of the timestamp of a hit within the superburst, unit: sample-clock cycles
+-- superburst : number of the superburst to which the hit belongs
--
--
-- generics
--
-- inputs
--- clock : ADC sampling clock
--- reset : synchrounous reset
--- data1_in : data from first 36-bits input, 3 words:
--- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
--- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
--- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
--- data1_in_write : write signal for data1_in
--- data1_in_available : more data available: wait with timestamp check until the timestamp is read
--- data2_in : data from second 36-bits input, 3 words:
--- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
--- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
--- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
--- data2_in_write : write signal for data2_in
--- data2_in_available : more data available: wait with timestamp check until the timestamp is read
--- data_out_allowed : writing of resulting data allowed
+-- clock : ADC sampling clock
+-- reset : synchronous reset
+-- channel1 : data input 1 : adc channel
+-- statusbyte1 : data input 1 : status
+-- energy1 : data input 1 : pulse energy
+-- CFvalbefore1 : data input 1 : Constant Fraction method : sample before zero crossing
+-- CFvalafter1 : data input 1 : Constant Fraction method : sample after zero crossing
+-- timestamp1 : data input 1 : time
+-- superburst1 : data input 1 : superburst number
+-- data1_in_write : write signal for data1_in
+-- data1_in_inpipe : more data available: wait with timestamp check until the timestamp is read
+-- channel2 : data input 2 : adc channel
+-- statusbyte2 : data input 2 : status
+-- energy2 : data input 2 : pulse energy
+-- CFvalbefore2 : data input 2 : Constant Fraction method : sample before zero crossing
+-- CFvalafter2 : data input 2 : Constant Fraction method : sample after zero crossing
+-- timestamp2 : data input 2 : time
+-- superburst2 : data input 2 : superburst number
+-- data2_in_write : write signal for data2_in
+-- data2_in_inpipe : more data available: wait with timestamp check until the timestamp is read
+-- data_out_allowed : writing of resulting data allowed
--
-- outputs
--- data1_in_allowed : signal to allow data input 1
--- data2_in_allowed : signal to allow data input 2
--- data_out : 36-bits data with valid pulse waveform, 3 words:
--- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
--- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
--- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
--- data_out_write : write signal for 36-bits output data
--- data_out_available : data available: in this module or at the input
--- error : error in data bits 35..32
+-- data1_in_allowed : signal to allow data input 1
+-- data2_in_allowed : signal to allow data input 2
+-- channel : data output : adc channel
+-- statusbyte : data output : status
+-- energy : data output : pulse energy
+-- CFvalbefore : data output : Constant Fraction method : sample before zero crossing
+-- CFvalafter : data output : Constant Fraction method : sample after zero crossing
+-- timestamp : data output : time
+-- superburst : data output : superburst number
+-- data_out_write : write signal for 36-bits output data
+-- data_out_inpipe : data available: in this module or at the input
+-- error : error in data bits 35..32
--
-- components
--
entity FEE_mux2to1 is
- Port (
+ port (
clock : in std_logic;
reset : in std_logic;
- data1_in : in std_logic_vector(35 downto 0);
+ channel1 : in std_logic_vector(7 downto 0);
+ statusbyte1 : in std_logic_vector(7 downto 0);
+ energy1 : in std_logic_vector(15 downto 0);
+ CFvalbefore1 : in std_logic_vector(15 downto 0);
+ CFvalafter1 : in std_logic_vector(15 downto 0);
+ timestamp1 : in std_logic_vector(15 downto 0);
+ superburst1 : in std_logic_vector(30 downto 0);
data1_in_write : in std_logic;
- data1_in_available : in std_logic;
+ data1_in_inpipe : in std_logic;
data1_in_allowed : out std_logic;
- data2_in : in std_logic_vector(35 downto 0);
+ channel2 : in std_logic_vector(7 downto 0);
+ statusbyte2 : in std_logic_vector(7 downto 0);
+ energy2 : in std_logic_vector(15 downto 0);
+ CFvalbefore2 : in std_logic_vector(15 downto 0);
+ CFvalafter2 : in std_logic_vector(15 downto 0);
+ timestamp2 : in std_logic_vector(15 downto 0);
+ superburst2 : in std_logic_vector(30 downto 0);
data2_in_write : in std_logic;
- data2_in_available : in std_logic;
+ data2_in_inpipe : in std_logic;
data2_in_allowed : out std_logic;
- data_out : out std_logic_vector(35 downto 0);
+ channel : out std_logic_vector(7 downto 0);
+ statusbyte : out std_logic_vector(7 downto 0);
+ energy : out std_logic_vector(15 downto 0);
+ CFvalbefore : out std_logic_vector(15 downto 0);
+ CFvalafter : out std_logic_vector(15 downto 0);
+ timestamp : out std_logic_vector(15 downto 0);
+ superburst : out std_logic_vector(30 downto 0);
data_out_write : out std_logic;
- data_out_available : out std_logic;
+ data_out_inpipe : out std_logic;
data_out_allowed : in std_logic;
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)
+ error : out std_logic
);
end FEE_mux2to1;
architecture Behavioral of FEE_mux2to1 is
-constant TIMEOUTBITS : integer := 6;
-signal timeout_counter_S : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
-
-signal error_S : std_logic := '0';
-signal read_pulse1_S : std_logic := '0';
-signal read_pulse2_S : std_logic := '0';
-signal data1_in_allowed_S : std_logic := '0';
-signal data2_in_allowed_S : std_logic := '0';
-signal data1_in_write_S : std_logic := '0';
-signal data2_in_write_S : std_logic := '0';
-signal data_out_trywrite_S : std_logic := '0';
-signal data_out_write_S : std_logic := '0';
-signal data_out_available_S : std_logic := '0';
-signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');
+attribute syn_keep : boolean;
+attribute syn_preserve : boolean;
+
+constant TIMEOUTBITS : integer := 12;
+--//signal timeout_counter_S : std_logic_vector(TIMEOUTBITS downto 0) := (others => '0');
+signal clear_timeout_counter_S : std_logic := '0';
+signal inc_timeout_counter_S : std_logic := '0';
+
+
+
+signal error_S : std_logic;
+signal data1_in_write_S : std_logic;
+signal data2_in_write_S : std_logic;
+signal data_out_write_S : std_logic;
+signal data1_in_inpipe_S : std_logic;
+signal data2_in_inpipe_S : std_logic;
+signal data_out_inpipe_S : std_logic;
+signal data1_in_allowed_S : std_logic;
+signal data2_in_allowed_S : std_logic;
+signal data_out_allowed_S : std_logic;
signal data1_timestamp_valid_S : std_logic := '0';
signal data2_timestamp_valid_S : std_logic := '0';
-begin
+signal outreg_filled_S : std_logic := '0';
-error <= error_S;
+signal time1equalorlarger_S : std_logic := '0';
+signal time2equalorlarger_S : std_logic := '0';
-data_out_available <= data_out_available_S;
-data_out_available_S <= '1' when (data1_in_available='1') or (data2_in_available='1')
- or (data_out_trywrite_S='1')
- or (data1_timestamp_valid_S='1') or (data2_timestamp_valid_S='1')
- else '0';
-data_out <= data_out_S;
-data_out_write <= data_out_write_S;
-data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+-- attribute mark_debug : string;
+-- attribute mark_debug of data1_in_allowed_S : signal is "true";
+-- attribute mark_debug of data2_in_allowed_S : signal is "true";
+-- attribute mark_debug of data1_in_write_S : signal is "true";
+-- attribute mark_debug of data2_in_write_S : signal is "true";
+-- attribute mark_debug of data1_in_inpipe_S : signal is "true";
+-- attribute mark_debug of data2_in_inpipe_S : signal is "true";
+-- attribute mark_debug of inc_timeout_counter_S : signal is "true";
+-- attribute mark_debug of clear_timeout_counter_S : signal is "true";
+-- attribute mark_debug of data_out_inpipe_S : signal is "true";
-data1_in_allowed <= data1_in_allowed_S;
-data1_in_allowed_S <= '1' when (data_out_allowed='1')
- and ((read_pulse1_S='1')
- or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data1_timestamp_valid_S='0')))
- else '0';
+
+
+begin
+data1_in_allowed <= data1_in_allowed_S;
data2_in_allowed <= data2_in_allowed_S;
-data2_in_allowed_S <= '1' when (data_out_allowed='1')
- and ((read_pulse2_S='1')
- or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data2_timestamp_valid_S='0')))
+data_out_allowed_S <= data_out_allowed;
+data1_in_write_S <= data1_in_write;
+data2_in_write_S <= data2_in_write;
+data_out_write <= data_out_write_S;
+data1_in_inpipe_S <= data1_in_inpipe;
+data2_in_inpipe_S <= data2_in_inpipe;
+data_out_inpipe <= data_out_inpipe_S;
+
+error <= error_S;
+
+data_out_write_S <= '1' when (outreg_filled_S='1') and (data_out_allowed_S='1') else '0';
+
+data_out_inpipe_S <= '1' when
+ (data1_in_inpipe_S='1') or (data2_in_inpipe_S='1') or
+ (outreg_filled_S='1')
+ else '0';
+
+--data1_in_allowed_S <= '1' when
+-- ((data_out_allowed_S='1') or (outreg_filled_S='0')) and
+-- (data1_timestamp_valid_S='1')
+-- else '0';
+data1_in_allowed_S <= '1' when
+ (outreg_filled_S='0') and
+ (data1_timestamp_valid_S='1')
else '0';
---data2_in_allowed_S <= '1' when (data_out_allowed='1')
--- and ((read_pulse2_S='1')
--- or (((read_pulse1_S='0') and (data1_timestamp_valid_S='0'))
--- and ((read_pulse2_S='0') and (data2_timestamp_valid_S='0'))))
+
+--data2_in_allowed_S <= '1' when
+-- ((data_out_allowed_S='1') or (outreg_filled_S='0')) and
+-- (data2_timestamp_valid_S='1') and
+-- (data1_in_write_S='0')
-- else '0';
+data2_in_allowed_S <= '1' when
+ (outreg_filled_S='0') and
+ (data2_timestamp_valid_S='1') and
+ (data1_in_write_S='0')
+ else '0';
-data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';
-data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';
-readprocess: process(clock)
-variable data1_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
-variable data2_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
-variable data1_timestamp_valid_V : std_logic;
-variable data2_timestamp_valid_V : std_logic;
-variable data1_lowchannel_V : std_logic;
-variable data2_lowchannel_V : std_logic;
-variable data1_pulseskipped_V : std_logic;
-variable data2_pulseskipped_V : std_logic;
+time1equalorlarger_S <= '1' when
+ (superburst1>superburst2) or
+ ((superburst1=superburst2) and
+ (timestamp1>=timestamp2))
+ else '0';
+time2equalorlarger_S <= '1' when
+ (superburst2>superburst1) or
+ ((superburst2=superburst1) and
+ (timestamp2>=timestamp1))
+ else '0';
+
+
+data1_timestamp_valid_S <= '1' when -- when timestamp1<=timestamp2
+ ((time2equalorlarger_S='1') and (data1_in_inpipe_S='1')) or
+ (data2_in_inpipe_S='0')
+ else '0';
+data2_timestamp_valid_S <= '1' when -- when timestamp2<=timestamp1
+ ((time1equalorlarger_S='1') and (data2_in_inpipe_S='1')) or
+ (data1_in_inpipe_S='0')
+ else '0';
+
+process(clock)
begin
- if rising_edge(clock) then
+ if rising_edge(clock) then
+ clear_timeout_counter_S <= '0';
+ inc_timeout_counter_S <= '0';
if reset='1' then
- data_out_trywrite_S <= '0';
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- data1_timestamp_valid_S <= '0';
- data2_timestamp_valid_S <= '0';
- timeout_counter_S <= (others => '0');
+ error_S <= '0';
+ timestamp <= (others => '0');
+ outreg_filled_S <= '0';
else
- if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
- data_out_trywrite_S <= '1'; -- try again
- timeout_counter_S <= (others => '0');
+ if data1_in_write_S='1' then
+ clear_timeout_counter_S <= '1';
+ channel <= channel1;
+ statusbyte <= statusbyte1;
+ energy <= energy1;
+ CFvalbefore <= CFvalbefore1;
+ CFvalafter <= CFvalafter1;
+ timestamp <= timestamp1;
+ superburst <= superburst1;
+ outreg_filled_S <= '1';
+ error_S <= '0';
+ elsif data2_in_write_S='1' then
+ clear_timeout_counter_S <= '1';
+ channel <= channel2;
+ statusbyte <= statusbyte2;
+ energy <= energy2;
+ CFvalbefore <= CFvalbefore2;
+ CFvalafter <= CFvalafter2;
+ timestamp <= timestamp2;
+ superburst <= superburst2;
+ outreg_filled_S <= '1';
+ error_S <= '0';
else
- if read_pulse1_S='1' then
- data1_timestamp_valid_V := '0';
- if data1_in_write_S='1' then
- timeout_counter_S <= (others => '0');
- if (data1_in(35 downto 34)="01") then -- next data
- error_S <= '0';
- data_out_S <= data1_in;
- data_out_trywrite_S <= '1';
- elsif (data1_in(35 downto 34)="10") then -- last data
- error_S <= '0';
- data_out_S <= data1_in;
- read_pulse1_S <= '0';
- data_out_trywrite_S <= '1';
- else -- error
- error_S <= '1';
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- data_out_trywrite_S <= '0';
- end if;
- else
- data_out_trywrite_S <= '0';
- if timeout_counter_S(TIMEOUTBITS-1)='1' then
- error_S <= '1';
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- else
- if data_out_allowed='1' then
- timeout_counter_S <= timeout_counter_S+1;
- end if;
- error_S <= '0';
- end if;
- end if;
- elsif read_pulse2_S='1' then
- data2_timestamp_valid_V := '0';
- if data2_in_write_S='1' then
- timeout_counter_S <= (others => '0');
- if (data2_in(35 downto 34)="01") then -- next data
- error_S <= '0';
- data_out_S <= data2_in;
- data_out_trywrite_S <= '1';
- elsif (data2_in(35 downto 34)="10") then -- last data
- error_S <= '0';
- data_out_S <= data2_in;
- read_pulse2_S <= '0';
- data_out_trywrite_S <= '1';
- else -- error
- error_S <= '1';
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- data_out_trywrite_S <= '0';
- end if;
- else
- data_out_trywrite_S <= '0';
- if timeout_counter_S(TIMEOUTBITS-1)='1' then
- error_S <= '1';
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- else
- if data_out_allowed='1' then
- timeout_counter_S <= timeout_counter_S+1;
- end if;
- error_S <= '0';
- end if;
- end if;
+ if data_out_write_S='1' then
+ outreg_filled_S <= '0';
+ clear_timeout_counter_S <= '1';
+ elsif outreg_filled_S='1' then
+--// -- if timeout_counter_S(TIMEOUTBITS)='1' then
+ -- error_S <= '1';
+ -- outreg_filled_S <= '0';
+ -- else
+ -- inc_timeout_counter_S <= '1';
+ -- end if;
else
- timeout_counter_S <= (others => '0');
- if data1_in_write_S='1' then
- if (data1_in(35 downto 34)="00") then
- data1_timestamp_V := data1_in(31 downto 0);
- data1_lowchannel_V := data1_in(33);
- data1_pulseskipped_V := data1_in(32);
- data1_timestamp_valid_V := '1';
- else -- error
- error_S <= '1';
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- end if;
- end if;
- if data2_in_write_S='1' then
- if (data2_in(35 downto 34)="00") then
- data2_timestamp_V := data2_in(31 downto 0);
- data2_lowchannel_V := data1_in(33);
- data2_pulseskipped_V := data1_in(32);
- data2_timestamp_valid_V := '1';
- else -- error
- error_S <= '1';
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- end if;
- end if;
- if data1_timestamp_valid_V='1' then
- if data2_timestamp_valid_V='1' then
- if (data1_timestamp_V(31 downto 0)<data2_timestamp_V(31 downto 0)) -- select 1
- or (((data1_timestamp_V(31 downto 30)="11") and (data2_timestamp_V(31 downto 30)="00"))) then
- read_pulse1_S <= '1';
- data1_timestamp_valid_V := '0';
- data_out_trywrite_S <= '1';
- data_out_S <= "00" & data1_lowchannel_V & data1_pulseskipped_V & data1_timestamp_V;
- else -- select 2
- read_pulse2_S <= '1';
- data2_timestamp_valid_V := '0';
- data_out_trywrite_S <= '1';
- data_out_S <= "00" & data2_lowchannel_V & data2_pulseskipped_V & data2_timestamp_V;
- end if;
- elsif data2_in_available='1' then -- data expected: wait
- data_out_trywrite_S <= '0';
- else -- write 1
- read_pulse1_S <= '1';
- data1_timestamp_valid_V := '0';
- data_out_trywrite_S <= '1';
- data_out_S <= "00" & data1_lowchannel_V & data1_pulseskipped_V & data1_timestamp_V;
- end if;
- elsif data2_timestamp_valid_V='1' then
- if data1_in_available='1' then -- data expected: wait
- data_out_trywrite_S <= '0';
- else -- write 2
- read_pulse2_S <= '1';
- data2_timestamp_valid_V := '0';
- data_out_trywrite_S <= '1';
- data_out_S <= "00" & data2_lowchannel_V & data2_pulseskipped_V & data2_timestamp_V;
- end if;
- else -- no valid timestamps
- data_out_trywrite_S <= '0';
- end if;
- end if;
- data1_timestamp_valid_S <= data1_timestamp_valid_V;
- data2_timestamp_valid_S <= data2_timestamp_valid_V;
+ clear_timeout_counter_S <= '1';
+ end if;
end if;
end if;
end if;
end process;
-
-
-
-
--- testword0 <= (others => '0');
-
-testword0(0) <= data1_in_write;
-testword0(1) <= data1_in_available;
-testword0(2) <= data1_in_allowed_S;
-testword0(3) <= read_pulse1_S;
-testword0(4) <= data1_in_write_S;
-testword0(5) <= data1_timestamp_valid_S;
-testword0(9 downto 6) <= data1_in(35 downto 32);
-
-testword0(10) <= data2_in_write;
-testword0(11) <= data2_in_available;
-testword0(12) <= data2_in_allowed_S;
-testword0(13) <= read_pulse2_S;
-testword0(14) <= data2_in_write_S;
-testword0(15) <= data2_timestamp_valid_S;
-testword0(19 downto 16) <= data2_in(35 downto 32);
-
-
-testword0(20) <= data_out_trywrite_S;
-testword0(21) <= data_out_write_S;
-testword0(22) <= data_out_available_S;
-testword0(23) <= data_out_allowed;
-testword0(27 downto 24) <= data_out_S(35 downto 32);
-testword0(28) <= error_S;
-
-testword0(35 downto 29) <= (others => '0');
+--//-- process(clock)
+-- begin
+ -- if rising_edge(clock) then
+ -- if (reset='1') or (clear_timeout_counter_S='1') then
+ -- timeout_counter_S <= (others => '0');
+ -- elsif inc_timeout_counter_S='1' then
+ -- timeout_counter_S <= timeout_counter_S+1;
+ -- end if;
+ -- end if;
+-- end process;
end Behavioral;
signal data_in_read_S : std_logic := '0';
signal data_in_read_after1clk_S : std_logic := '0';
signal data_out_trywrite_S : std_logic := '0';
+signal data_out_allowed_S : std_logic := '0';
\r
\r
begin
\r
-data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or \r
- (data_in_saved_S='1') else '0';\r
+data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or (data_in_saved_S='1') else '0';
\r
data_in_read <= data_in_read_S;\r
-data_in_read_S <= '1' when (data_out_allowed='1') and (data_in_available='1') and (data_in_saved_S='0') else '0';\r
+data_in_read_S <= '1' when \r
+((data_out_allowed='1') or ((data_in_saved_S='0') and (data_out_allowed='0') and (data_out_allowed_S='0') and (data_in_read_after1clk_S='0')))\r
+ and (data_in_available='1') and (data_in_saved_S='0') else '0';
+
\r
data_out_write <= data_out_write_S;\r
data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';\r
end if;\r
data_in_read_after1clk_S <= data_in_read_S;\r
end if;\r
+ data_out_allowed_S <= data_out_allowed;
end if;\r
end process;
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 16-03-2012
-- Module Name: FEE_pileup_check
-- 16-09-2014 name changed from pileup_check to FEE_pileup_check
-- 24-09-2014 enable_highgain and enable_lowgain inputs added
-- 10-10-2014 Integral output added, as measurement for the energy instead of maximum
+-- 19-08-2015 Force_hit added: force waveform acquisition with SODA command
+-- 15-12-2015 Clipping check registered
+-- 01-02-2016 Check for waveforms with only small values
+-- 15-04-2016 Bug repaired for high gain waveforms with maximum length
+-- 24-02-2017 Superburstnumber to 31 bits instead of 16 bits
----------------------------------------------------------------------------------\r
\r
library IEEE;\r
-- reset : synchrounous reset\r
-- superburstnumber : actual superburstnumber\r
-- timestampcounter : timestampcounter within superburst\r
+-- force_hit : force hit at input
-- ADC_highgain : signed ADC value, corrected for baseline\r
-- enable_highgain : enable high gain input
+-- threshold_highgain : threshold for high gain, in this module used to check for wavforms with only small signals
-- max_data_highgain : maximum of the waveform, calculated by the eventdetector (unsigned)
-- pulse_active_highgain : high gain pulse active (signal above threshold)\r
--- pulse_rising_highgain : high gain pulse has not yet reached maximum\r
+-- pulse_rising_highgain : high gain pulse has not yet reached maximum
+-- clipping_highgain : high gain pulse is clipping to maximum value: low gain input should be taken
-- ADC_lowgain : signed ADC value, corrected for baseline\r
-- enable_lowgain : enable low gain input
+-- threshold_lowgain : threshold for low gain, in this module used to check for wavforms with only small signals
-- max_data_lowgain : maximum of the waveform, calculated by the eventdetector (unsigned)
-- pulse_active_lowgain : low gain pulse active (signal above threshold)\r
-- pulse_rising_lowgain : low gain pulse has not yet reached maximum\r
reset : in std_logic;\r
superburstnumber : in std_logic_vector(30 downto 0); \r
timestampcounter : in std_logic_vector(15 downto 0); \r
+ force_hit : in std_logic;
ADC_highgain : in std_logic_vector(ADCBITS downto 0); -- signed\r
enable_highgain : in std_logic;
+ threshold_highgain : in std_logic_vector(ADCBITS-1 downto 0);
max_data_highgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
pulse_active_highgain : in std_logic;\r
pulse_rising_highgain : in std_logic;\r
clipping_highgain : in std_logic;\r
ADC_lowgain : in std_logic_vector(ADCBITS downto 0); -- signed\r
enable_lowgain : in std_logic;
+ threshold_lowgain : in std_logic_vector(ADCBITS-1 downto 0);
max_data_lowgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
pulse_active_lowgain : in std_logic;\r
pulse_rising_lowgain : in std_logic;\r
pileuppulse_lowgain : out std_logic;\r
clearpulse_lowgain : out std_logic;\r
integral_lowgain : out std_logic_vector(15 downto 0);\r
- superburst : out std_logic_vector(15 downto 0);\r
- timestamp : out std_logic_vector(15 downto 0);\r
- testword0 : out std_logic_vector(35 downto 0)\r
+ superburst : out std_logic_vector(30 downto 0);\r
+ timestamp : out std_logic_vector(15 downto 0)\r
);\r
end FEE_pileup_check;\r
\r
architecture Behavioral of FEE_pileup_check is\r
\r
constant ZEROS : std_logic_vector(31 downto 0) := (others => '0');\r
+\r
+\r
+signal force_hit_S : std_logic := '0';\r
+\r
signal pulse_highgain_tooshort_S : std_logic := '0';\r
signal pulse_highgain_toolong_S : std_logic := '0';\r
signal pulse_highgain_pileup_S : std_logic := '0';\r
signal counter_highgain_S : std_logic_vector(7 downto 0);\r
\r
signal singlepulse_lowgain_occured_S : std_logic := '0';\r
-signal pileuppulse_lowgain_occured_S : std_logic := '0';\r
+signal pileuppulse_lowgain_occured_S : std_logic := '0';
+\r
signal pulse_lowgain_tooshort_S : std_logic := '0';\r
signal pulse_lowgain_toolong_S : std_logic := '0';\r
signal pulse_lowgain_pileup_S : std_logic := '0';\r
signal clipping_highgain_S : std_logic := '0';\r
signal counter_lowgain_S : std_logic_vector(7 downto 0) := (others => '0');\r
\r
-signal superburst_highgain_S : std_logic_vector(15 downto 0) := (others => '0');\r
+signal superburst_highgain_S : std_logic_vector(30 downto 0) := (others => '0');\r
signal timestamp_highgain_S : std_logic_vector(15 downto 0) := (others => '0');\r
-signal superburst_lowgain_S : std_logic_vector(15 downto 0) := (others => '0');\r
+signal superburst_lowgain_S : std_logic_vector(30 downto 0) := (others => '0');\r
signal timestamp_lowgain_S : std_logic_vector(15 downto 0) := (others => '0');\r
\r
\r
-signal integral_highgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
-signal maxXconstant1_highgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
-signal maxXconstant2_highgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
-signal integral_highgain_stdl_S : std_logic_vector(ADCBITS+9 downto 0);\r
+signal integral_highgain_S : integer range -2**(16+INTEGRALRATIOBITS) to 2**(16+INTEGRALRATIOBITS)-1;
+signal maxXconstant1_highgain_S : integer range 0 to 2**(ADCBITS+IDIVMAXBITS)-1;
+signal maxXconstant2_highgain_S : integer range 0 to 2**(ADCBITS+IDIVMAXBITS)-1;
signal pulse_highgain_toonarrow_s : std_logic := '0';\r
-signal pulse_highgain_toowide_S : std_logic := '0';\r
+signal pulse_highgain_toowide_S : std_logic := '0';
+signal lowsignalwaveform_highgain_S : std_logic := '0';\r
\r
-\r
-signal integral_lowgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
-signal maxXconstant1_lowgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
-signal maxXconstant2_lowgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
-signal integral_lowgain_stdl_S : std_logic_vector(ADCBITS+9 downto 0);\r
+signal integral_lowgain_S : integer range -2**(16+INTEGRALRATIOBITS) to 2**(16+INTEGRALRATIOBITS)-1;\r
+signal maxXconstant1_lowgain_S : integer range 0 to 2**(ADCBITS+IDIVMAXBITS)-1;\r
+signal maxXconstant2_lowgain_S : integer range 0 to 2**(ADCBITS+IDIVMAXBITS)-1;\r
signal pulse_lowgain_toonarrow_s : std_logic := '0';\r
signal pulse_lowgain_toowide_S : std_logic := '0';\r
+signal lowsignalwaveform_lowgain_S : std_logic := '0';
\r
signal fullsize_wave_highgain_S : std_logic := '0';\r
signal fullsize_wave_lowgain_S : std_logic := '0';\r
signal pulse_active_lowgain_S : std_logic := '0';\r
signal prev_pulse_active_lowgains_s : std_logic := '0';\r
signal pulse_busy_lowgain_S : std_logic := '0';\r
+
+signal lowgain_chosen_S : std_logic := '0';
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of ADC_highgain : signal is "true";
+-- attribute mark_debug of max_data_highgain : signal is "true";
+-- attribute mark_debug of pulse_active_highgain : signal is "true";
+-- attribute mark_debug of pulse_active_highgain_S : signal is "true";
+-- attribute mark_debug of pulse_rising_highgain : signal is "true";
+-- attribute mark_debug of pulse_busy_highgain_S : signal is "true";
+-- attribute mark_debug of pulse_highgain_tooshort_S : signal is "true";
+-- attribute mark_debug of pulse_highgain_toolong_S : signal is "true";
+-- attribute mark_debug of pulse_highgain_pileup_S : signal is "true";
+-- attribute mark_debug of singlepulse_highgain_S : signal is "true";
+-- attribute mark_debug of pileuppulse_highgain_S : signal is "true";
+-- attribute mark_debug of clearpulse_highgain_S : signal is "true";
+-- attribute mark_debug of pulse_highgain_toonarrow_s : signal is "true";
+-- attribute mark_debug of pulse_highgain_toowide_S : signal is "true";
+-- attribute mark_debug of lowsignalwaveform_highgain_S : signal is "true";
+
+-- attribute mark_debug of singlepulse_lowgain_occured_S : signal is "true";
+-- attribute mark_debug of pileuppulse_lowgain_occured_S : signal is "true";
+
+-- attribute mark_debug of ADC_lowgain : signal is "true";
+-- attribute mark_debug of max_data_lowgain : signal is "true";
+-- attribute mark_debug of pulse_active_lowgain : signal is "true";
+-- attribute mark_debug of pulse_active_lowgain_S : signal is "true";
+-- attribute mark_debug of pulse_rising_lowgain : signal is "true";
+-- attribute mark_debug of pulse_busy_lowgain_S : signal is "true";
+-- attribute mark_debug of pulse_lowgain_tooshort_S : signal is "true";
+-- attribute mark_debug of pulse_lowgain_toolong_S : signal is "true";
+-- attribute mark_debug of pulse_lowgain_pileup_S : signal is "true";
+-- attribute mark_debug of singlepulse_lowgain_S : signal is "true";
+-- attribute mark_debug of pileuppulse_lowgain_S : signal is "true";
+-- attribute mark_debug of clearpulse_lowgain_S : signal is "true";
+-- attribute mark_debug of pulse_lowgain_toonarrow_s : signal is "true";
+-- attribute mark_debug of pulse_lowgain_toowide_S : signal is "true";
+-- attribute mark_debug of lowsignalwaveform_lowgain_S : signal is "true";
+
+-- attribute mark_debug of clipping_highgain : signal is "true";
+-- attribute mark_debug of clipping_highgain_S : signal is "true";
+
\r
--integer range 0 to 2**(ADCBITS+IDIVMAXBITS-1)-1;\r
begin\r
\r
-integral_highgain_stdl_S <= conv_std_logic_vector(integral_highgain_S,ADCBITS+10);\r
-integral_highgain <= \r
- x"0000" when (integral_highgain_stdl_S(ADCBITS+9)='1') else -- negative\r
- x"ffff" when (integral_highgain_stdl_S(ADCBITS+8 downto INTEGRALRATIOBITS+15)/=ZEROS(ADCBITS+8 downto INTEGRALRATIOBITS+15)) -- clip\r
- else integral_highgain_stdl_S(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);\r
-\r
-integral_lowgain_stdl_S <= conv_std_logic_vector(integral_lowgain_S,ADCBITS+10);\r
-integral_lowgain <= \r
- x"0000" when (integral_lowgain_stdl_S(ADCBITS+9)='1') else -- negative\r
- x"ffff" when (integral_lowgain_stdl_S(ADCBITS+8 downto INTEGRALRATIOBITS+15)/=ZEROS(ADCBITS+8 downto INTEGRALRATIOBITS+15)) -- clip\r
- else integral_lowgain_stdl_S(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);\r
-\r
+integral_highgain <= conv_std_logic_vector(integral_highgain_S,INTEGRALRATIOBITS+16+1)(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);
+integral_lowgain <= conv_std_logic_vector(integral_lowgain_S,INTEGRALRATIOBITS+16+1)(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);
\r
process(clock)\r
begin\r
if (rising_edge(clock)) then \r
- if (enable_highgain='1') then\r
- fullsize_wave_highgain_S <= fullsize_wave_highgain;\r
- else\r
- fullsize_wave_highgain_S <= '0';\r
- end if;\r
- if (enable_lowgain='1') then\r
- fullsize_wave_lowgain_S <= fullsize_wave_lowgain;\r
+ force_hit_S <= force_hit;\r
+ end if;\r
+end process;\r
+ \r
+-- process(clock)\r
+-- begin\r
+ -- if (rising_edge(clock)) then \r
+ -- if (enable_highgain='1') then\r
+ -- fullsize_wave_highgain_S <= fullsize_wave_highgain;\r
+ -- else\r
+ -- fullsize_wave_highgain_S <= '0';\r
+ -- end if;\r
+ -- if (enable_lowgain='1') then\r
+ -- fullsize_wave_lowgain_S <= fullsize_wave_lowgain;\r
+ -- else\r
+ -- fullsize_wave_lowgain_S <= '0';\r
+ -- end if;\r
+ -- end if;\r
+-- end process;\r
+fullsize_wave_highgain_S <= fullsize_wave_highgain when enable_highgain='1' else '0';
+fullsize_wave_lowgain_S <= fullsize_wave_lowgain when enable_lowgain='1' else '0';
+\r
+--clipping_highgain_S <= clipping_highgain;\r
+process(clock)\r
+begin\r
+ if (rising_edge(clock)) then \r
+ if (pulse_active_highgain='1') then\r
+ if clipping_highgain='1' then\r
+ clipping_highgain_S <= '1';\r
+ end if;\r
else\r
- fullsize_wave_lowgain_S <= '0';\r
+ if (pulse_active_lowgain='0') or (enable_lowgain='0') then\r
+ clipping_highgain_S <= '0';\r
+ end if;\r
end if;\r
end if;\r
end process;\r
\r
-clipping_highgain_S <= clipping_highgain;\r
-\r
-process(clock)\r
+process(clock)
+variable integral_highgain_V : integer range -2**(16+INTEGRALRATIOBITS) to 2**(16+INTEGRALRATIOBITS)-1 := 0;\r
begin\r
if rising_edge(clock) then\r
if (reset='1') then\r
- integral_highgain_S <= conv_integer(signed(ADC_highgain));\r
+ integral_highgain_V := conv_integer(signed(ADC_highgain));\r
else\r
if ((pulse_active_highgain='0') and (pulse_active_highgain_prev1_S='0')) or\r
((pulse_active_highgain='1') and (pulse_active_highgain_prev1_S='0') and (pulse_active_highgain_prev2_S='1'))then\r
- integral_highgain_S <= conv_integer(signed(ADC_highgain));\r
+ integral_highgain_V := conv_integer(signed(ADC_highgain));\r
+ elsif integral_highgain_S+conv_integer(signed(ADC_highgain))>2**(16+INTEGRALRATIOBITS)-1 then
+ integral_highgain_V := 2**(16+INTEGRALRATIOBITS)-1;
else\r
- integral_highgain_S <= integral_highgain_S+conv_integer(signed(ADC_highgain));\r
- end if;\r
- end if;\r
+ integral_highgain_V := integral_highgain_S+conv_integer(signed(ADC_highgain));\r
+ end if;
+ end if;
+ integral_highgain_S <= integral_highgain_V;
pulse_active_highgain_prev2_S <= pulse_active_highgain_prev1_S;
- pulse_active_highgain_prev1_S <= pulse_active_highgain;\r
+ pulse_active_highgain_prev1_S <= pulse_active_highgain;
end if;\r
end process;\r
\r
end process;\r
pulse_highgain_toonarrow_S <= '1' when maxXconstant1_highgain_S>integral_highgain_S else '0';\r
pulse_highgain_toowide_S <= '1' when maxXconstant2_highgain_S<integral_highgain_S else '0';\r
+
\r
process(clock)
+variable integral_lowgain_V : integer range -2**(16+INTEGRALRATIOBITS) to 2**(16+INTEGRALRATIOBITS)-1;
begin
if rising_edge(clock) then
- if (reset='1') then\r
- integral_lowgain_S <= conv_integer(signed(ADC_lowgain));
+ if (reset='1') then
+ integral_lowgain_V := conv_integer(signed(ADC_lowgain));
else
- if ((pulse_active_lowgain='0') and (pulse_active_lowgain_prev1_S='0')) or \r
- ((pulse_active_lowgain='1') and (pulse_active_lowgain_prev1_S='0') and (pulse_active_lowgain_prev2_S='1')) then -- if 2nd pulse within 1 clock
- integral_lowgain_S <= conv_integer(signed(ADC_lowgain));
+ if ((pulse_active_lowgain='0') and (pulse_active_lowgain_prev1_S='0')) or
+ ((pulse_active_lowgain='1') and (pulse_active_lowgain_prev1_S='0') and (pulse_active_lowgain_prev2_S='1'))then
+ integral_lowgain_V := conv_integer(signed(ADC_lowgain));
+ elsif integral_lowgain_S+conv_integer(signed(ADC_lowgain))>2**(16+INTEGRALRATIOBITS)-1 then
+ integral_lowgain_V := 2**(16+INTEGRALRATIOBITS)-1;
else
- integral_lowgain_S <= integral_lowgain_S+conv_integer(signed(ADC_lowgain));
+ integral_lowgain_V := integral_lowgain_S+conv_integer(signed(ADC_lowgain));
end if;
- end if;\r
+ end if;
+ integral_lowgain_S <= integral_lowgain_V;
pulse_active_lowgain_prev2_S <= pulse_active_lowgain_prev1_S;
pulse_active_lowgain_prev1_S <= pulse_active_lowgain;
end if;
and (pulse_highgain_toowide_S='0')\r
and ((singlepulse_lowgain_occured_S='0') -- and (pulse_lowgain_tooshort_S='1')\r
and (pileuppulse_lowgain_occured_S='0'))\r
+ and ((not ((pulse_active_lowgain='1') and (clipping_highgain_S='1'))) or (enable_lowgain='0'))\r
and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))\r
else '0';\r
singlepulse_highgain <= singlepulse_highgain_S;\r
(((pulse_active_highgain='0') and (prev_pulseactive_highgain_S='1')) \r
and ((pulse_highgain_toolong_S='0') and ((pulse_highgain_tooshort_S='0') and (pulse_highgain_toonarrow_S='0')))\r
and ((pulse_highgain_pileup_S='1') or (pulse_highgain_toowide_S='1'))\r
- and ((singlepulse_lowgain_occured_S='0') -- and (pulse_lowgain_tooshort_S='1') \r
- and (pileuppulse_lowgain_occured_S='0'))\r
- and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))\r
+ and ((singlepulse_lowgain_occured_S='0') and (singlepulse_lowgain_S='0') -- and (pulse_lowgain_tooshort_S='1') \r
+ and (pileuppulse_lowgain_occured_S='0') and (pileuppulse_lowgain_S='0'))\r
+ and ((not ((pulse_active_lowgain='1') and (clipping_highgain_S='1'))) or (enable_lowgain='0'))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))
+ and (lowsignalwaveform_highgain_S='0'))
or (((pulse_highgain_toolong_S='1') and (prev_pulse_highgain_toolong_S='0'))\r
- and ((singlepulse_lowgain_occured_S='0') -- and (pulse_lowgain_tooshort_S='1') \r
- and (pileuppulse_lowgain_occured_S='0'))\r
- and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))\r
+ and ((singlepulse_lowgain_occured_S='0') and (pileuppulse_lowgain_S='0') and (singlepulse_lowgain_S='0') -- and (pulse_lowgain_tooshort_S='1') \r
+ and (pileuppulse_lowgain_occured_S='0') and ((clipping_highgain_S='0') or (pulse_active_lowgain='0')))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))
+ and (lowsignalwaveform_highgain_S='0'))\r
or (((pulse_highgain_toolong_S='1') and (prev_pulse_highgain_toolong_S='0'))\r
and ((fullsize_wave_highgain_S='1') and (fullsize_wave_lowgain_S='0')))\r
else '0';\r
pulse_highgain_pileup_S <= '0';\r
pulse_busy_highgain_S <= '0';\r
else \r
- if (pulse_active_highgain_S='1') or (pulse_active_highgain='1') then\r
+ if (pulse_active_highgain_S='1') or (pulse_active_highgain='1') or (force_hit_S='1') then\r
pulse_busy_highgain_S <= enable_highgain;\r
if counter_highgain_S<maxwavelength then\r
counter_highgain_S <= counter_highgain_S+1;\r
pulse_highgain_toolong_S <= enable_highgain;\r
end if;\r
if (pulse_active_highgain_S='1') and (prev_pulseactive_highgainS_S='0') then\r
- superburst_highgain_S <= superburstnumber(15 downto 0);\r
+ superburst_highgain_S <= superburstnumber;\r
timestamp_highgain_S <= timestampcounter;\r
end if;\r
else\r
and ((pulse_lowgain_pileup_S='1') or (pulse_lowgain_toowide_S='1'))
and ((pulse_lowgain_toolong_S='0') and (pulse_lowgain_tooshort_S='0'))\r
and ((clipping_highgain_S='1') or (enable_highgain='0'))
- and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))\r
+ and (lowsignalwaveform_lowgain_S='0'))
or (((pulse_lowgain_toolong_S='1') and (prev_pulse_lowgain_toolong_S='0'))\r
and ((clipping_highgain_S='1') or (enable_highgain='0'))\r
- and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))\r
+ and (lowsignalwaveform_lowgain_S='0'))
or (((pulse_lowgain_toolong_S='1') and (prev_pulse_lowgain_toolong_S='0'))\r
and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='1')))\r
else '0';\r
pulse_lowgain_pileup_S <= '0';\r
pulse_busy_lowgain_S <= '0';\r
else\r
- if (pulse_active_lowgain_S='1') or (pulse_active_lowgain='1') then\r
+ if (pulse_active_lowgain_S='1') or (pulse_active_lowgain='1') or (force_hit_S='1') then\r
pulse_busy_lowgain_S <= enable_lowgain;\r
if counter_lowgain_S<maxwavelength then\r
counter_lowgain_S <= counter_lowgain_S+1;\r
pulse_lowgain_toolong_S <= enable_lowgain;\r
end if;\r
if (pulse_active_lowgain_S='1') or (prev_pulse_active_lowgainS_S='0') then\r
- superburst_lowgain_S <= superburstnumber(15 downto 0);\r
+ superburst_lowgain_S <= superburstnumber;\r
timestamp_lowgain_S <= timestampcounter;\r
end if;\r
else\r
prev_pulseactive_lowgain_S <= pulse_active_lowgain;\r
prev_pulse_active_lowgainS_S <= pulse_active_lowgain_S;\r
end if;\r
-end process;\r
+end process;
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if ('0' & max_data_highgain)<=(threshold_highgain & '0') then
+ lowsignalwaveform_highgain_S <= '1';
+ else
+ lowsignalwaveform_highgain_S <= '0';
+ end if;
+ if ('0' & max_data_lowgain)<=(threshold_lowgain & '0') then
+ lowsignalwaveform_lowgain_S <= '1';
+ else
+ lowsignalwaveform_lowgain_S <= '0';
+ end if;
+ end if;
+end process;
\r
-process(clock)\r
-begin\r
- if rising_edge(clock) then\r
- if reset='1' then\r
- superburst <= (others => '0');\r
- timestamp <= (others => '0');\r
- else \r
- if (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') then\r
- superburst <= superburst_lowgain_S;\r
- timestamp <= timestamp_lowgain_S;\r
- elsif (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1') then\r
- superburst <= superburst_highgain_S;\r
- timestamp <= timestamp_highgain_S;\r
- end if;\r
- end if;\r
- end if;\r
+\r
+superburst <= superburst_lowgain_S when (lowgain_chosen_S='1') or (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') else superburst_highgain_S;
+timestamp <= timestamp_lowgain_S when (lowgain_chosen_S='1') or (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') else timestamp_highgain_S;
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') then
+ lowgain_chosen_S <= '1';
+ elsif (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1') then
+ lowgain_chosen_S <= '0';
+ end if;
+ end if;
end process;\r
\r
---testword0(0) <= pulse_active_highgain;\r
---testword0(1) <= pulse_rising_highgain;\r
---\r
---testword0(2) <= pulse_active_highgain_S; -- pulse_highgain_tooshort_S;\r
---testword0(3) <= pulse_highgain_toolong_S;\r
---testword0(4) <= prev_pulse_highgain_toolong_S;\r
---testword0(5) <= prev_pulseactive_highgain_S;\r
---testword0(6) <= singlepulse_highgain_S;\r
---testword0(7) <= pileuppulse_highgain_S;\r
---testword0(8) <= pulse_busy_highgain_S; -- pulse_highgain_toonarrow_s;\r
---testword0(9) <= pulse_highgain_toowide_S;\r
---\r
---testword0(15 downto 10) <= counter_highgain_S(5 downto 0);\r
---testword0(16) <= pulse_active_lowgain;\r
---testword0(17) <= pulse_rising_lowgain;\r
---testword0(18) <= pulse_active_lowgain_S; -- pulse_lowgain_tooshort_S;\r
---testword0(19) <= pulse_lowgain_toolong_S;\r
---testword0(20) <= prev_pulse_lowgain_toolong_S;\r
---testword0(21) <= prev_pulseactive_lowgain_S;\r
---testword0(22) <= singlepulse_lowgain_S;\r
---testword0(23) <= pileuppulse_lowgain_S;\r
---testword0(24) <= pulse_busy_lowgain_S; -- pulse_lowgain_toonarrow_s;\r
---testword0(25) <= pulse_lowgain_toowide_S;\r
---\r
---testword0(31 downto 26) <= counter_lowgain_S(5 downto 0);\r
---\r
---testword0(32) <= singlepulse_lowgain_occured_S;\r
---testword0(33) <= pileuppulse_lowgain_occured_S;\r
---testword0(34) <= clearpulse_highgain_S;\r
---testword0(35) <= clearpulse_lowgain_S;\r
-\r
-\r
-testword0(22) <= pulse_active_highgain;\r
-testword0(23) <= pulse_active_highgain_S; -- pulse_highgain_tooshort_S;\r
-testword0(24) <= singlepulse_highgain_S;\r
-testword0(25) <= pileuppulse_highgain_S;\r
-testword0(26) <= pulse_busy_highgain_S; -- pulse_highgain_toonarrow_s;\r
-testword0(27) <= pulse_active_lowgain;\r
-testword0(28) <= pulse_active_lowgain_S; -- pulse_lowgain_tooshort_S;\r
-testword0(29) <= singlepulse_lowgain_S;\r
-testword0(30) <= pileuppulse_lowgain_S;\r
-testword0(31) <= pulse_busy_lowgain_S; -- pulse_lowgain_toonarrow_s;\r
-testword0(32) <= singlepulse_lowgain_occured_S;\r
-testword0(33) <= pileuppulse_lowgain_occured_S;\r
-testword0(34) <= clearpulse_highgain_S;\r
-testword0(35) <= clearpulse_lowgain_S;\r
\r
end Behavioral;\r
\r
signal pulse1_skipbit_S : std_logic;
signal pulse2_skipbit_S : std_logic;
+-- attribute mark_debug : string;
+-- attribute mark_debug of pulse1_skipped : signal is "true";
+-- attribute mark_debug of pulse2_skipped : signal is "true";
+-- attribute mark_debug of pulse1_skipped_S : signal is "true";
+-- attribute mark_debug of pulse1_skipbit_S : signal is "true";
+-- attribute mark_debug of pulse2_skipped_S : signal is "true";
+-- attribute mark_debug of pulse2_skipbit_S : signal is "true";
+
begin\r
\r
pulse_skipped <= '1' when (pulse1_skipped_S='1') or (pulse2_skipped_S='1') else '0';\r
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 03-02-2012
-- Module Name: FEE_pulse_and_pileup_waveforms
-- 23-09-2014 sort pileup waveforms
-- 10-10-2014 Integral as measurement for the energy instead of maximum
-- 16-10-2014 inpipe signals
+-- 24-04-2015 Moving Window Deconvolution added\r
+-- 21-07-2015 Disable pulsedata_allowed_S and wavedata_allowed_S for better timing\r
+-- 19-08-2015 Force_hit added: force waveform acquisition with SODA command
+-- 23-10-2015 Check on buffer filled passed on to wave multiplexer: wavedata_moretocome_S signal
+-- 28-10-2016 Enable_waveform input added
+-- 23-02-2017 Parallel data from Feature Extraction instead of 36-bits
----------------------------------------------------------------------------------\r
\r
library IEEE;\r
-- on each input pulses are detected and the waveform is put in a buffer.\r
-- A timestamp is added, based on maximum signal in waveform.\r
-- From each high-gain and low-gain input pair only one waveform at the same time is choosen and passed on.\r
--- The waveform are distinguish for single pulse and pileup waveforms.\r
--- The single pulse waveforms are sorted, based on timestamp, and multiplexed to one stream.\r
--- The pileup waveforms multiplexed to one stream (unsorted).\r
--- The parameters are organised in registers A,B,C,D :\r
+-- The waveform are distinguish for single pulse and multiple pulses (pileup).\r
+-- The single pulse and multiple pulses are sorted, based on timestamp, and multiplexed to one stream.\r
+-- There is also a mode in which the waveforms are produced. They are also multiplexed and sorted to one stream.
+--\r
+-- The parameters are organised in 4 registers :\r
-- board_register A: write\r
-- register_A(7..0) = threshold High
-- register_A(15..8) = threshold Low
-- register_A(17) = disable Low
-- register_A(23..18) = I/Max discard
-- register_A(29..24) = I/Max pileup
+-- register_A(30) = enable raw data in waveform instead of baseline corrected data
-- board_register B: write
-- register_B(7..0) = minimum pulselength
-- register_B(15..8) = pileup length
-- register_B(23..16) = maximum wavelength
-- register_B(24) = fullsize High
-- register_B(25) = fullsize Low
--- register_B(29..26) = CF delay\r
+-- register_B(29..26) = CF delay
+-- register_B(31..30) = CF delay Pileup
+-- board_register C: write
+-- register_C(4..0) = MWD1_width
+-- register_C(9..8) = MWD2_width
+-- register_C(11..10) = MWDpu1_width
+-- register_C(13..12) = MWDpu2_width
+-- register_C(31..16) = MWD1_tau_factor , MWDpu_tau_factor
+-- board_register D: write
+-- register_D(15..0) = MWD2_tau_factor
+-- register_D(31..16) = MWD2pu_tau_factor
--\r
--\r
-- generics\r
--- NROFADCS : number of adc-inputs (two adc-inputs are a combined high-gain and low-gain pair)
--- ADCBITS : number of ADC-bits
--- BWBITS : number of bits for the baseline IIR filter bandwidth
--- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size\r
--- IDIVMAXBITS : number of bits for maximum to integral ratio check
--- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
--- CF_DELAYBITS : number of bits for the Constant Fraction delay
+-- NROFADCS : number of adc-inputs (two adc-inputs are a combined high-gain and low-gain pair)
+-- ADCBITS : number of ADC-bits
+-- MWD_WIDTHBITS : number of bits for the width
+-- MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations
+-- MWD2_WIDTHBITS : number of bits for the width of second MWD
+-- MWD2_SCALEBITS : number of bits for tau factor for second MWD, also scaling for calculations
+-- MWD_DOUBLEFILTER : two MWD filters in series for single pulses
+-- MWD_PU_DOUBLEFILTER : two MWD filters in series for pileup
+-- BASELINE_BWBITS : number of bits for the baseline IIR filter bandwidth
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size\r
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+-- CF_DELAYBITS : number of bits for the Constant Fraction delay
+-- MAXPILEUPHITS : maximum number of hits in one pileup waveform
+-- NOWAVEFORMS : no waveforms
-- \r
-- inputs\r
--- clock : clock\r
--- reset : synchrounous reset\r
--- superburstnumber : actual superburstnumber\r
--- timestampcounter : timestampcounter within superburst\r
--- ADCdata : array with ADC data for each input\r
--- enable_data : enable adc data\r
--- slowcontrol_byte_data : data from slowcontrol containing commands/settings (sent byte-wise)
--- slowcontrol_byte_write : write signal for the slowcontrol commands
--- slowcontrol_byte_request : indicates that the slowcontrol command is a request for data (status reading)
--- pulsedata_read : read signal for data with resulting single pulse waveforms\r
--- pileupdata_read : read signal for data with resulting pileup waveforms\r
+-- clock : clock\r
+-- reset : synchrounous reset\r
+-- superburstnumber : actual superburstnumber\r
+-- superburstupdate : new superburstnumber\r
+-- ADCdata : array with ADC data for each input\r
+-- enable_data : enable adc data\r
+-- enable_waveform : produce waveforms and not Feature Extraction data
+-- force_hit : force hit at input
+-- slowcontrol_byte_data : data from slowcontrol containing commands/settings (sent byte-wise)
+-- slowcontrol_byte_write : write signal for the slowcontrol commands
+-- slowcontrol_byte_request : indicates that the slowcontrol command is a request for data (status reading)
+-- pulsedata_read : read signal for data with resulting single pulse waveforms\r
+-- wavedata_read : read signal for data with resulting pileup waveforms\r
-- \r
-- outputs\r
--- pulsedata_out : 36 bits output data with resulting single pulse waveforms:\r
--- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
--- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
--- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
--- pulsedata_available : output single pulse data is available\r
--- pulsedata_inpipe : more single pulse data on its way
--- pileupdata_out : 36-bits output data with resulting pileup waveforms:
--- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
--- bits(35..32)="0001" : \r
+-- pulsedata_channel : results from Feature Extraction: ADC channel number
+-- pulsedata_status : results from Feature Extraction: status byte
+-- pulsedata_superburst : results from Feature Extraction: superburst number
+-- pulsedata_timestamp : results from Feature Extraction: timestamp within superburst
+-- pulsedata_energy : results from Feature Extraction: energy
+-- pulsedata_CFvalbefore : results from Feature Extraction: ADC sample before zero-crossing Constant Fraction method
+-- pulsedata_CFvalafter : results from Feature Extraction: ADC sample after zero-crossing Constant Fraction method
+-- pulsedata_available : output single pulse data is available\r
+-- pulsedata_inpipe : more single pulse data on its way
+-- wavedata_out : 36-bits output data with resulting pileup waveforms:
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
+-- bits(35..32)="0001" : \r
-- bits(31..24) = statusbyte (bit6=overflow) \r
-- bits(23..16) = 0\r
-- bits(7..0) = adcnumber (channel identifaction)\r
-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
--- pileupdata_available : output pileup data is available
--- pileupdata_inpipe : more pileup data on its way
--- pulsedetect : pulse detected for each of the ADC channels
--- overflow : overflow in data from one of the channels: data is lost\r
+-- wavedata_available : output pileup data is available
+-- wavedata_inpipe : more pileup data on its way
+-- pulsedetect : pulse detected for each of the ADC channels
+-- overflow : overflow in data from one of the channels: data is lost\r
+-- error : error in data\r
--\r
-- components\r
--- FEE_dual_pulse_waveform : module to extract waveform containing pulse from high_gain/low_gain pair\r
--- FEE_sorting_mux : multiplexer for pulse data, sort based on timestamp\r
--- FEE_sorting_wavemux : sorted multiplexer for waveform data\r
--- FEE_slowcontrol_receive_from_cpu : receive slowcontrol commands, byte-wise
+-- FEE_dual_pulse_waveform : module to extract waveform containing pulse from high_gain/low_gain pair\r
+-- FEE_sorting_mux : multiplexer for pulse data, sort based on timestamp\r
+-- FEE_sorting_wavemux : sorted multiplexer for waveform data\r
+-- FEE_slowcontrol_receive_from_cpu : receive slowcontrol commands, byte-wise
--\r
--\r
------------------------------------------------------------------------------------------------------\r
generic (
NROFADCS : natural := 16;
ADCBITS : natural := 14;
- BWBITS : natural := 10;
+ MWD_WIDTHBITS : natural := 5;
+ MWD_SCALEBITS : natural := 16;
+ MWD2_WIDTHBITS : natural := 2;
+ MWD2_SCALEBITS : natural := 16;
+ MWD_DOUBLEFILTER : boolean := false;
+ MWD_PU_DOUBLEFILTER : boolean := false;
+ BASELINE_BWBITS : natural := 10;
WAVEFORMBUFFERSIZE : natural := 11;
IDIVMAXBITS : natural := 6;
INTEGRALRATIOBITS : natural := 3;
- CF_DELAYBITS : natural := 8
+ CF_DELAYBITS : natural := 8;
+ MAXPILEUPHITS : natural := 3;
+ NOWAVEFORMS : boolean := false
);
Port (\r
clock : in std_logic;
reset : in std_logic;
superburstnumber : in std_logic_vector(30 downto 0); \r
- timestampcounter : in std_logic_vector(15 downto 0); \r
+ superburstupdate : in std_logic; \r
ADCdata : in array_adc_type;
enable_data : in std_logic;
+ enable_waveform : in std_logic;
+ force_hit : in std_logic;
slowcontrol_byte_data : in std_logic_vector (7 downto 0);
slowcontrol_byte_write : in std_logic;
slowcontrol_byte_request: in std_logic;
- pulsedata_out : out std_logic_vector(35 downto 0);
+ pulsedata_channel : out std_logic_vector(7 downto 0);
+ pulsedata_status : out std_logic_vector(7 downto 0);
+ pulsedata_superburst : out std_logic_vector(30 downto 0);
+ pulsedata_timestamp : out std_logic_vector(15 downto 0);
+ pulsedata_energy : out std_logic_vector(15 downto 0);
+ pulsedata_CFvalbefore : out std_logic_vector(15 downto 0);
+ pulsedata_CFvalafter : out std_logic_vector(15 downto 0);
pulsedata_read : in std_logic;
pulsedata_available : out std_logic;
pulsedata_inpipe : out std_logic;
- pileupdata_out : out std_logic_vector(35 downto 0);
- pileupdata_read : in std_logic;
- pileupdata_available : out std_logic;\r
- pileupdata_inpipe : out std_logic;
+ wavedata_out : out std_logic_vector(35 downto 0);
+ wavedata_read : in std_logic;
+ wavedata_available : out std_logic;\r
+ wavedata_inpipe : out std_logic;
pulsedetect : out std_logic_vector(0 to NROFADCS-1);
overflow : out std_logic;\r
- testindex : in integer range 0 to NROFADCS/2-1;\r
- testword0 : out std_logic_vector(35 downto 0);\r
- testword1 : out std_logic_vector(35 downto 0);\r
- testword2 : out std_logic_vector(35 downto 0)\r
+ error : out std_logic\r
);\r
end FEE_pulse_and_pileup_waveforms;\r
\r
\r
component FEE_dual_pulse_waveform is\r
generic (
+ ADCNUMBER : natural := 0;
ADCBITS : natural := ADCBITS;
- BWBITS : natural := BWBITS;
+ BASELINE_BWBITS : natural := BASELINE_BWBITS;
+ MWD_WIDTHBITS : natural := MWD_WIDTHBITS;
+ MWD_SCALEBITS : natural := MWD_SCALEBITS;
+ MWD2_WIDTHBITS : natural := MWD2_WIDTHBITS;
+ MWD2_SCALEBITS : natural := MWD2_SCALEBITS;
+ MWD_DOUBLEFILTER : boolean := MWD_DOUBLEFILTER;
+ MWD_PU_DOUBLEFILTER : boolean := MWD_PU_DOUBLEFILTER;
WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
IDIVMAXBITS : natural := IDIVMAXBITS;
INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS;
- CF_DELAYBITS : natural := CF_DELAYBITS
+ CF_DELAYBITS : natural := CF_DELAYBITS;
+ MAXPILEUPHITS : natural := MAXPILEUPHITS;
+ NOWAVEFORMS : boolean := NOWAVEFORMS
);
Port (\r
clock : in std_logic;
- reset : in std_logic;\r
- enable : in std_logic;\r
- adcnumber : in std_logic_vector(7 downto 0); \r
- cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
- superburstnumber : in std_logic_vector(30 downto 0); \r
- timestampcounter : in std_logic_vector(15 downto 0); \r
- ADCdata_highgain : in std_logic_vector((ADCBITS-1) downto 0);
- ADCdata_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
- threshold_highgain : in std_logic_vector((ADCBITS-1) downto 0);
- threshold_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
+ reset : in std_logic;
+ enable : in std_logic;
+ enable_waveform : in std_logic;
+ force_hit : in std_logic;
+ CF_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+ CFpu_delay : in std_logic_vector(1 downto 0);
+ superburstnumber : in std_logic_vector(30 downto 0);
+ superburstupdate : in std_logic;
+ ADCdata_highgain : in std_logic_vector(ADCBITS-1 downto 0);
+ ADCdata_lowgain : in std_logic_vector(ADCBITS-1 downto 0);
+ MWD1_width : in std_logic_vector(MWD_WIDTHBITS-1 downto 0);
+ MWD1_tau_factor : in std_logic_vector(MWD_SCALEBITS-1 downto 0);
+ MWD2_width : in std_logic_vector(MWD2_WIDTHBITS-1 downto 0);
+ MWD2_tau_factor : in std_logic_vector(MWD2_SCALEBITS-1 downto 0);
+ MWDpu1_width : in std_logic_vector(1 downto 0);
+ MWDpu1_tau_factor : in std_logic_vector(MWD_SCALEBITS-1 downto 0);
+ MWDpu2_width : in std_logic_vector(MWD2_WIDTHBITS-1 downto 0);
+ MWDpu2_tau_factor : in std_logic_vector(MWD2_SCALEBITS-1 downto 0);
+ threshold_highgain : in std_logic_vector(ADCBITS-1 downto 0);
+ threshold_lowgain : in std_logic_vector(ADCBITS-1 downto 0);
enable_highgain : in std_logic;
enable_lowgain : in std_logic;
+ enable_rawdata : in std_logic;
IIRfilterBW : in std_logic_vector(2 downto 0);
maxabovebaseline : in std_logic_vector(3 downto 0);
- minpulselength : in std_logic_vector(7 downto 0);\r
- pileuplength : in std_logic_vector(7 downto 0);\r
- maxwavelength : in std_logic_vector(7 downto 0);\r
- IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
- IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
- fullsize_wave_highgain : in std_logic;\r
- fullsize_wave_lowgain : in std_logic;\r
- ADC_minus_baseline_highgain : out std_logic_vector(ADCBITS downto 0);
- ADC_minus_baseline_lowgain : out std_logic_vector(ADCBITS downto 0);\r
- pulsedata_allowed : in std_logic;\r
- pulsedata_almostfull : in std_logic;
- pulsedata_write : out std_logic;\r
- pulsedata_out : out std_logic_vector(35 downto 0);\r
- pileupdata_allowed : in std_logic;\r
- pileupdata_almostfull : in std_logic;
- pileupdata_write : out std_logic;\r
- pileupdata_out : out std_logic_vector(35 downto 0);\r
+ minpulselength : in std_logic_vector(7 downto 0);
+ pileuplength : in std_logic_vector(7 downto 0);
+ maxwavelength : in std_logic_vector(7 downto 0);
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ fullsize_wave_highgain : in std_logic;
+ fullsize_wave_lowgain : in std_logic;
+ pulsedata_allowed : in std_logic;
+ pulsedata_write : out std_logic;
+ pulsedata_lowgain : out std_logic;
+ pulsedata_superburst : out std_logic_vector(30 downto 0);
+ pulsedata_timestamp : out std_logic_vector(15 downto 0);
+ pulsedata_energy : out std_logic_vector(15 downto 0);
+ pulsedata_CFvalbefore : out std_logic_vector(15 downto 0);
+ pulsedata_CFvalafter : out std_logic_vector(15 downto 0);
+ pulsedata_status : out std_logic_vector(7 downto 0);
+ wavedata_allowed : in std_logic;
+ wavedata_almostfull : in std_logic;
+ wavedata_available : out std_logic;
+ wavedata_write : out std_logic;
+ wavedata_out : out std_logic_vector(35 downto 0);
pulsedetect : out std_logic;
- overflow : out std_logic;\r
- testword0 : out std_logic_vector(35 downto 0);\r
- testword1 : out std_logic_vector(35 downto 0);\r
- testword2 : out std_logic_vector(35 downto 0)\r
+ overflow : out std_logic;
+ error : out std_logic
);\r
end component;\r
\r
Port (
clock : in std_logic;
reset : in std_logic;
- data_in : in array_halfadc36bits_type;
+ superburstnumber : in std_logic_vector(30 downto 0);
+ superburstupdate : in std_logic;
+ data_in_status : in array_halfadc8bits_type;
+ data_in_lowgain : in std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_superburst : in array_halfadc31bits_type;
+ data_in_timestamp : in array_halfadc16bits_type;
+ data_in_energy : in array_halfadc16bits_type;
+ data_in_CFvalbefore : in array_halfadc16bits_type;
+ data_in_CFvalafter : in array_halfadc16bits_type;
data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
- data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
- data_out : out std_logic_vector(35 downto 0);
+ data_out_channel : out std_logic_vector(7 downto 0);
+ data_out_status : out std_logic_vector(7 downto 0);
+ data_out_superburst : out std_logic_vector(30 downto 0);
+ data_out_timestamp : out std_logic_vector(15 downto 0);
+ data_out_energy : out std_logic_vector(15 downto 0);
+ data_out_CFvalbefore : out std_logic_vector(15 downto 0);
+ data_out_CFvalafter : out std_logic_vector(15 downto 0);
data_out_read : in std_logic;
data_out_available : out std_logic;
data_out_inpipe : out std_logic;
- error : out std_logic;\r
- testword0 : out std_logic_vector(35 downto 0);
- testword1 : out std_logic_vector(35 downto 0)
+ error : out std_logic
);
end component;\r
\r
reset : in std_logic;\r
data_in : in array_halfadc36bits_type;\r
data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);\r
+ data_in_available : in std_logic_vector(0 to NROFMUXINPUTS-1);\r
data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);\r
- data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);\r
data_out : out std_logic_vector(35 downto 0);\r
data_out_read : in std_logic;\r
data_out_available : out std_logic;\r
- data_out_inpipe : out std_logic;
- error : out std_logic;\r
- testword0 : out std_logic_vector(35 downto 0);
- testword1 : out std_logic_vector(35 downto 0)
+ data_out_inpipe : out std_logic;\r
+ error : out std_logic\r
);\r
end component;\r
\r
byte_write : in std_logic;
byte_request : in std_logic;
register_A : out std_logic_vector (31 downto 0);
- register_B : out std_logic_vector (31 downto 0)
+ register_B : out std_logic_vector (31 downto 0);
+ register_C : out std_logic_vector (31 downto 0);
+ register_D : out std_logic_vector (31 downto 0)
);
end component;
\r
constant zeros : std_logic_vector(0 to NROFADCS/2-1) := (others => '0');\r
signal ADCdata_S : array_adc_type;
signal enable_high_S : std_logic_vector(0 to NROFADCS/2-1);
-signal enable_low_S : std_logic_vector(0 to NROFADCS/2-1);
-signal adcnumber_S : array_halfadc8bits_type;\r
+signal enable_low_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal enable_rawdata_S : std_logic_vector(0 to NROFADCS/2-1);\r
+
signal pulsedata_allowed_S : std_logic_vector(0 to NROFADCS/2-1);\r
signal pulsedata_write_S : std_logic_vector(0 to NROFADCS/2-1);\r
-signal pulsedata_almostfull_S : std_logic_vector(0 to NROFADCS/2-1);\r
-signal pulsedata_out_S : array_halfadc36bits_type;\r
+signal pulsedata_status_S : array_halfadc8bits_type;
+signal pulsedata_lowgain_S : std_logic_vector(0 to NROFADCS/2-1);
+signal pulsedata_superburst_S : array_halfadc31bits_type;
+signal pulsedata_timestamp_S : array_halfadc16bits_type;
+signal pulsedata_energy_S : array_halfadc16bits_type;
+signal pulsedata_CFvalbefore_S : array_halfadc16bits_type;
+signal pulsedata_CFvalafter_S : array_halfadc16bits_type;
signal pulsedata_inpipe_S : std_logic;\r
-signal pileupdata_allowed_S : std_logic_vector(0 to NROFADCS/2-1);\r
-signal pileupdata_write_S : std_logic_vector(0 to NROFADCS/2-1);\r
-signal pileupdata_almostfull_S : std_logic_vector(0 to NROFADCS/2-1);\r
-signal pileupdata_out_S : array_halfadc36bits_type;\r
+signal pulsedata_error_S : std_logic;\r
+signal wavedata_allowed_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal wavedata_write_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal wavedata_almostfull_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal wavedata_moretocome_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal wavedata_out_S : array_halfadc36bits_type;\r
signal overflow_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal errorarray_S : std_logic_vector(0 to NROFADCS/2-1);\r
signal pulsedata_available_S : std_logic;\r
-signal pileupdata_available_S : std_logic;\r
-signal pileupdata_inpipe_S : std_logic;\r
+signal wavedata_available_S : std_logic;\r
+signal wavedata_inpipe_S : std_logic;\r
+signal wavedata_error_S : std_logic;\r
+signal wavedata_output_S : std_logic_vector(35 downto 0);
+signal reset_wavemux_S : std_logic;
\r
signal pulsedetect_S : std_logic_vector(0 to NROFADCS-1);
-signal pileupdata_output_S : std_logic_vector(35 downto 0);\r
\r
signal register_A_S : array_halfadc32bits_type := (others => (others => '0'));
signal register_B_S : array_halfadc32bits_type := (others => (others => '0'));
-\r
-signal dataerrors_S : std_logic_vector(0 to NROFADCS/2-1);\r
-\r
-signal testword0_S : array_halfadc36bits_type;\r
-signal testword1_S : array_halfadc36bits_type;\r
-signal testword2_S : array_halfadc36bits_type;\r
-\r
+signal register_C_S : array_halfadc32bits_type := (others => (others => '0'));
+signal register_D_S : array_halfadc32bits_type := (others => (others => '0'));
+\r
+attribute mark_debug : string;
+-- attribute mark_debug of pulsedata_almostfull_S : signal is "true";
+-- attribute mark_debug of pulsedata_write_S : signal is "true";
+-- attribute mark_debug of wavedata_almostfull_S : signal is "true";
+-- attribute mark_debug of wavedata_moretocome_S : signal is "true";
+-- attribute mark_debug of wavedata_write_S : signal is "true";
+-- attribute mark_debug of pulsedata_error_S : signal is "true";
+-- attribute mark_debug of wavedata_error_S : signal is "true";
+-- attribute mark_debug of errorarray_S : signal is "true";
+-- attribute mark_debug of error : signal is "true";
\r
begin\r
\r
+error <= '1' when (pulsedata_error_S='1') or (wavedata_error_S='1') or errorarray_S(0 to NROFADCS/2-1)/=zeros(0 to NROFADCS/2-1) else '0';\r
\r
- waves : for index in 0 to NROFADCS/2-1 generate\r
+ FEs: for index in 0 to NROFADCS/2-1 generate\r
\r
FEE_slowcontrol_receive_from_cpu_all: FEE_slowcontrol_receive_from_cpu port map(
clock => clock,
reset => reset,
- address => conv_std_logic_vector(index*2,8),
+ address => conv_std_logic_vector(index*NROFREGSPERCHANNEL,8),
byte_data => slowcontrol_byte_data,
byte_write => slowcontrol_byte_write,
byte_request => slowcontrol_byte_request,
register_A => register_A_S(index),
- register_B => register_B_S(index));
+ register_B => register_B_S(index),
+ register_C => register_C_S(index),
+ register_D => register_D_S(index));
\r
- adcnumber_S(index) <= conv_std_logic_vector(index*2,8);\r
- process(clock)
- begin
- if (rising_edge(clock)) then \r
+-- process(clock)
+-- begin
+-- if (rising_edge(clock)) then \r
enable_high_S(index) <= not register_A_S(index)(16);
- enable_low_S(index) <= not register_A_S(index)(17);
- end if;
- end process; \r
- ADCdata_S(index*2) <= ADCdata(index*2);-- when enable_high_S(index)='1' else (others => '0');\r
- ADCdata_S(index*2+1) <= ADCdata(index*2+1);-- when enable_low_S(index)='1' else (others => '0');\r
+ enable_low_S(index) <= not register_A_S(index)(17);\r
+ enable_rawdata_S(index) <= register_A_S(index)(30);
+-- end if;
+-- end process; \r
+ ADCdata_S(index*2) <= ADCdata(index*2);\r
+ ADCdata_S(index*2+1) <= ADCdata(index*2+1);\r
\r
- FEE_dual_pulse_waveform1: FEE_dual_pulse_waveform port map(\r
+ FEE_dual_pulse_waveform1: FEE_dual_pulse_waveform
+ generic map(
+ ADCNUMBER => index*2,
+ ADCBITS => ADCBITS,
+ BASELINE_BWBITS => BASELINE_BWBITS,
+ MWD_WIDTHBITS => MWD_WIDTHBITS,
+ MWD_SCALEBITS => MWD_SCALEBITS,
+ MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+ MWD2_SCALEBITS => MWD2_SCALEBITS,
+ MWD_DOUBLEFILTER => MWD_DOUBLEFILTER,
+ MWD_PU_DOUBLEFILTER => MWD_PU_DOUBLEFILTER,
+ WAVEFORMBUFFERSIZE => WAVEFORMBUFFERSIZE,
+ IDIVMAXBITS => IDIVMAXBITS,
+ INTEGRALRATIOBITS => INTEGRALRATIOBITS,
+ CF_DELAYBITS => CF_DELAYBITS,
+ MAXPILEUPHITS => MAXPILEUPHITS,
+ NOWAVEFORMS => NOWAVEFORMS
+ )
+ port map(\r
clock => clock,
reset => reset,
enable => enable_data,\r
- adcnumber => adcnumber_S(index),\r
- cf_delay => register_B_S(index)(29 downto 26),
+ enable_waveform => enable_waveform,
+ force_hit => force_hit,\r
+ cf_delay => register_B_S(index)(CF_DELAYBITS+25 downto 26),
+ CFpu_delay => register_B_S(index)(31 downto 30),
superburstnumber => superburstnumber,\r
- timestampcounter => timestampcounter,\r
+ superburstupdate => superburstupdate,\r
ADCdata_highgain => ADCdata_S(index*2),
ADCdata_lowgain => ADCdata_S(index*2+1),\r
+ MWD1_width => register_C_S(index)(MWD_WIDTHBITS-1 downto 0),
+ MWD1_tau_factor => register_C_S(index)(MWD_SCALEBITS+15 downto 16),
+ MWD2_width => register_C_S(index)(MWD2_WIDTHBITS+7 downto 8),
+ MWD2_tau_factor => register_D_S(index)(MWD2_SCALEBITS-1 downto 0),
+ MWDpu1_width => register_C_S(index)(11 downto 10),
+ MWDpu1_tau_factor => register_C_S(index)(MWD_SCALEBITS+15 downto 16),
+ MWDpu2_width => register_C_S(index)(MWD2_WIDTHBITS+11 downto 12),
+ MWDpu2_tau_factor => register_D_S(index)(MWD2_SCALEBITS+15 downto 16),
threshold_highgain(7 downto 0) => register_A_S(index)(7 downto 0),
threshold_highgain((ADCBITS-1) downto 8) => (others => '0'),
threshold_lowgain(7 downto 0) => register_A_S(index)(15 downto 8),
threshold_lowgain((ADCBITS-1) downto 8) => (others => '0'),
enable_highgain => enable_high_S(index),
enable_lowgain => enable_low_S(index),
+ enable_rawdata => enable_rawdata_S(index),
IIRfilterBW => (others => '0'),
maxabovebaseline => "1010",
minpulselength => register_B_S(index)(7 downto 0),\r
IdivMAX_pileup => register_A_S(index)(IDIVMAXBITS+23 downto 24),\r
fullsize_wave_highgain => register_B_S(index)(24),\r
fullsize_wave_lowgain => register_B_S(index)(25),\r
- ADC_minus_baseline_highgain => open, -- testword0_S(idx)(14 downto 0),
- ADC_minus_baseline_lowgain => open, -- testword0_S(idx)(30 downto 16),\r
pulsedata_allowed => pulsedata_allowed_S(index),\r
- pulsedata_almostfull => pulsedata_almostfull_S(index),
pulsedata_write => pulsedata_write_S(index),\r
- pulsedata_out => pulsedata_out_S(index),\r
- pileupdata_allowed => pileupdata_allowed_S(index),\r
- pileupdata_almostfull => pileupdata_almostfull_S(index),
- pileupdata_write => pileupdata_write_S(index),\r
- pileupdata_out => pileupdata_out_S(index),\r
+ pulsedata_lowgain => pulsedata_lowgain_S(index),
+ pulsedata_superburst => pulsedata_superburst_S(index),
+ pulsedata_timestamp => pulsedata_timestamp_S(index),
+ pulsedata_energy => pulsedata_energy_S(index),
+ pulsedata_CFvalbefore => pulsedata_CFvalbefore_S(index),
+ pulsedata_CFvalafter => pulsedata_CFvalafter_S(index),
+ pulsedata_status => pulsedata_status_S(index),
+ wavedata_allowed => '1', --// 21072015 wavedata_allowed_S(index),\r
+ wavedata_almostfull => wavedata_almostfull_S(index),
+ wavedata_available => wavedata_moretocome_S(index),
+ wavedata_write => wavedata_write_S(index),\r
+ wavedata_out => wavedata_out_S(index),\r
pulsedetect => pulsedetect_S(index),
overflow => overflow_S(index),\r
- testword0 => testword0_S(index),\r
- testword1 => testword1_S(index),\r
- testword2 => testword2_S(index));\r
-\r
-process(clock)\r
-type array_halfadc4bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(3 downto 0);\r
-variable prev_data_V : array_halfadc4bits_type;
-begin
- if rising_edge(clock) then\r
- dataerrors_S(index) <= '0';\r
- if pileupdata_write_S(index)='1' then\r
- case pileupdata_out_S(index)(35 downto 32) is\r
- when "0000" =>\r
- if (prev_data_V(index)/="0100") and (prev_data_V(index)/="0101") then\r
- dataerrors_S(index) <= '1';\r
- end if;\r
- when "0001" =>\r
- if (prev_data_V(index)/="0000") then\r
- dataerrors_S(index) <= '1';\r
- end if;\r
- when "0010" =>\r
- if (prev_data_V(index)/="0001") and (prev_data_V(index)/="0010") then\r
- dataerrors_S(index) <= '1';\r
- end if;\r
- when "0100" =>\r
- if (prev_data_V(index)/="0010") then\r
- dataerrors_S(index) <= '1';\r
- end if;\r
- when "0101" =>\r
- if (prev_data_V(index)/="0010") then\r
- dataerrors_S(index) <= '1';\r
- end if;\r
- when others =>\r
- dataerrors_S(index) <= '1';\r
- end case;\r
- prev_data_V(index) := pileupdata_out_S(index)(35 downto 32);\r
- end if;\r
- end if;
-end process;\r
+ error => errorarray_S(index));\r
\r
end generate;\r
overflow <= '1' when overflow_S(0 to NROFADCS/2-1)/=zeros(0 to NROFADCS/2-1) else '0';\r
pulsedetect_S(NROFADCS/2 to NROFADCS-1) <= (others => '0');\r
pulsedetect <= pulsedetect_S;\r
-\r
+
FEE_sorting_mux1: FEE_sorting_mux port map(
clock => clock,
reset => reset,
- data_in => pulsedata_out_S,
+ superburstnumber => superburstnumber,
+ superburstupdate => superburstupdate,
+ data_in_status => pulsedata_status_S,
+ data_in_lowgain => pulsedata_lowgain_S,
+ data_in_superburst => pulsedata_superburst_S,
+ data_in_timestamp => pulsedata_timestamp_S,
+ data_in_energy => pulsedata_energy_S,
+ data_in_CFvalbefore => pulsedata_CFvalbefore_S,
+ data_in_CFvalafter => pulsedata_CFvalafter_S,
data_in_write => pulsedata_write_S,
data_in_allowed => pulsedata_allowed_S,
- data_in_almostfull => pulsedata_almostfull_S,
- data_out => pulsedata_out,
+ data_out_channel => pulsedata_channel,
+ data_out_status => pulsedata_status,
+ data_out_superburst => pulsedata_superburst,
+ data_out_timestamp => pulsedata_timestamp,
+ data_out_energy => pulsedata_energy,
+ data_out_CFvalbefore => pulsedata_CFvalbefore,
+ data_out_CFvalafter => pulsedata_CFvalafter,
data_out_read => pulsedata_read,
data_out_available => pulsedata_available_S,
data_out_inpipe => pulsedata_inpipe_S,
- error => open,\r
- testword0 => open,
- testword1 => open);\r
+ error => pulsedata_error_S);\r
pulsedata_available <= pulsedata_available_S;
pulsedata_inpipe <= pulsedata_inpipe_S;\r
-\r
--- FEE_sorting_wavemux_pileup: FEE_sorting_wavemux port map(\r
-FEE_sorting_wavemux1: FEE_sorting_wavemux port map(
- clock => clock,
- reset => reset,
- data_in => pileupdata_out_S,
- data_in_write => pileupdata_write_S,
- data_in_allowed => pileupdata_allowed_S,
- data_in_almostfull => pileupdata_almostfull_S,
- data_out => pileupdata_output_S,
- data_out_read => pileupdata_read,
- data_out_available => pileupdata_available_S,
- data_out_inpipe => pileupdata_inpipe_S,
- error => open,\r
- testword0 => open,
- testword1 => open);\r
-pileupdata_available <= pileupdata_available_S;
-pileupdata_out <= pileupdata_output_S;\r
-pileupdata_inpipe <= pileupdata_inpipe_S;\r
-\r
-\r
-\r
---process(clock)
---type array_16_type is array(0 to NROFADCS/2-1) of std_logic_vector(15 downto 0);
---type array_8_type is array(0 to NROFADCS/2-1) of std_logic_vector(7 downto 0);
---variable l1 : line;
---variable l2 : line;
---variable c : std_logic_vector(63 downto 0) := x"0000000000000000";
---variable pulse_time_V : array_16_type;
---variable pulse_sb_V : array_16_type;
---variable pulse_energy_V : array_16_type;
---variable pulse_chan_V : array_8_type;
---variable wave_time_V : array_16_type;
---variable wave_sb_V : array_16_type;
---variable wave_chan_V : array_8_type;
---file file0: text;
---file file1: text;
---begin
--- if rising_edge(clock) then
--- if c=x"0000000000000000" then
--- file_open(file0,"D:\data\Panda\pulses.txt",WRITE_MODE);
--- file_open(file1,"D:\data\Panda\waves.txt",WRITE_MODE);
--- end if;
--- c := c+1;\r
--- for i in 0 to NROFADCS/2-1 loop\r
--- if pulsedata_write_S(i)='1' then\r
--- if pulsedata_out_S(i)(35 downto 34)="00" then\r
--- pulse_sb_V(i) := pulsedata_out_S(i)(31 downto 16);\r
--- pulse_time_V(i) := pulsedata_out_S(i)(15 downto 0);\r
--- elsif pulsedata_out_S(i)(35 downto 34)="01" then\r
--- pulse_chan_V(i) := pulsedata_out_S(i)(23 downto 16);\r
--- pulse_energy_V(i) := pulsedata_out_S(i)(15 downto 0);\r
--- hwrite(l1,c,right,16);
--- write(l1," ");
--- hwrite(l1,pulse_sb_V(i),right,4);
--- write(l1," ");
--- hwrite(l1,pulse_time_V(i),right,4);
--- write(l1," ");
--- hwrite(l1,pulse_chan_V(i),right,2);
--- write(l1," ");
--- hwrite(l1,pulse_energy_V(i),right,4);
--- writeline(file0,l1);
--- end if;\r
--- end if;\r
--- if pileupdata_write_S(i)='1' then\r
--- if pileupdata_out_S(i)(35 downto 32) ="0000" then\r
--- wave_sb_V(i) := pileupdata_out_S(i)(31 downto 16);\r
--- wave_time_V(i) := pileupdata_out_S(i)(15 downto 0);\r
--- elsif pileupdata_out_S(i)(35 downto 32) ="0001" then\r
--- wave_chan_V(i) := pileupdata_out_S(i)(7 downto 0);\r
--- hwrite(l2,c,right,16);
--- write(l2," ");
--- hwrite(l2,wave_sb_V(i),right,4);
--- write(l2," ");
--- hwrite(l2,wave_time_V(i),right,4);
--- write(l2," ");
--- hwrite(l2,wave_chan_V(i),right,2);
--- writeline(file1,l2); \r
--- end if;\r
--- end if;
--- end loop;\r
--- end if;
---end process;\r
-\r
-\r
-\r
-testword0(33 downto 0) <= testword0_S(testindex)(33 downto 0);\r
-testword0(35) <= testword0_S(testindex)(35);\r
-testword0(34) <= '1' when \r
- (testword0_S(0)(35)='1') or\r
- (testword0_S(1)(35)='1') or\r
- (testword0_S(2)(35)='1') or\r
- (testword0_S(3)(35)='1') or\r
- (testword0_S(4)(35)='1') or\r
- (testword0_S(5)(35)='1') or\r
- (testword0_S(6)(35)='1') or\r
- (testword0_S(7)(35)='1') or\r
- (testword0_S(8)(35)='1') or\r
- (testword0_S(9)(35)='1') or\r
- (testword0_S(10)(35)='1') or\r
- (testword0_S(11)(35)='1') or\r
- (testword0_S(12)(35)='1') or\r
- (testword0_S(13)(35)='1') or\r
- (testword0_S(14)(35)='1') or\r
- (testword0_S(15)(35)='1') else '0';\r
-\r
-\r
-\r
-\r
-testword1(15 downto 0) <= testword1_S(0)(15 downto 0);\r
-testword1(31 downto 16) <= dataerrors_S;\r
-testword1(32) <= '1' when dataerrors_S/=x"0000";\r
-testword1(35) <= testword0_S(testindex)(28);\r
-testword1(34) <= '1' when \r
- (testword0_S(0)(35)='1') or\r
- (testword0_S(1)(35)='1') or\r
- (testword0_S(2)(35)='1') or\r
- (testword0_S(3)(35)='1') or\r
- (testword0_S(4)(35)='1') or\r
- (testword0_S(5)(35)='1') or\r
- (testword0_S(6)(35)='1') or\r
- (testword0_S(7)(35)='1') or\r
- (testword0_S(8)(35)='1') or\r
- (testword0_S(9)(35)='1') or\r
- (testword0_S(10)(35)='1') or\r
- (testword0_S(11)(35)='1') or\r
- (testword0_S(12)(35)='1') or\r
- (testword0_S(13)(35)='1') or\r
- (testword0_S(14)(35)='1') or\r
- (testword0_S(15)(35)='1') else '0';\r
- \r
-testword2(33 downto 0) <= testword2_S(testindex)(33 downto 0);\r
-testword2(35) <= testword0_S(testindex)(35);\r
-testword2(34) <= testword0_S(testindex)(28);\r
---testword2(34) <= '1' when \r
--- (testword0_S(0)(35)='1') or\r
--- (testword0_S(1)(35)='1') or\r
--- (testword0_S(2)(35)='1') or\r
--- (testword0_S(3)(35)='1') or\r
--- (testword0_S(4)(35)='1') or\r
--- (testword0_S(5)(35)='1') or\r
--- (testword0_S(6)(35)='1') or\r
--- (testword0_S(7)(35)='1') or\r
--- (testword0_S(8)(35)='1') or\r
--- (testword0_S(9)(35)='1') or\r
--- (testword0_S(10)(35)='1') or\r
--- (testword0_S(11)(35)='1') or\r
--- (testword0_S(12)(35)='1') or\r
--- (testword0_S(13)(35)='1') or\r
--- (testword0_S(14)(35)='1') or\r
--- (testword0_S(15)(35)='1') else '0';\r
-\r
- \r
+
+gen_waveforms: if NOWAVEFORMS=false generate
+ reset_wavemux_S <= '1' when (reset='1') or (enable_waveform='0') else '0';\r
+ FEE_sorting_wavemux1: FEE_sorting_wavemux port map(
+ clock => clock,
+ reset => reset_wavemux_S,
+ data_in => wavedata_out_S,
+ data_in_write => wavedata_write_S,
+ data_in_available => wavedata_moretocome_S,
+ data_in_allowed => wavedata_allowed_S,
+ data_in_almostfull => wavedata_almostfull_S,\r
+ data_out => wavedata_output_S,
+ data_out_read => wavedata_read,
+ data_out_available => wavedata_available_S,
+ data_out_inpipe => wavedata_inpipe_S,
+ error => wavedata_error_S);\r
+ wavedata_available <= wavedata_available_S;
+ wavedata_out <= wavedata_output_S;\r
+ wavedata_inpipe <= wavedata_inpipe_S;\r
+end generate;\r
+gen_nowaveforms: if NOWAVEFORMS=true generate
+ wavedata_allowed_S <= (others => '1');
+ wavedata_almostfull_S <= (others => '0');
+ wavedata_output_S <= (others => '0');
+ wavedata_available_S <= '0';
+ wavedata_inpipe_S <= '0';
+ wavedata_error_S <= '0';
+end generate;
\r
end Behavioral;\r
\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI-cart/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 15-02-2017
+-- Module Name: FEE_pulse_detect
+-- Description: Checks and compares two pulselength's
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_pulse_detect
+-- Detect if ADC data contains a valid pulse. Comparing with threshold is done in other module.
+-- If the pulse-time is below an adjustable number of samples then the pulse is rejected.
+-- Also, the ADC samples are summated. The resulting integral determines the pulse energy.
+-- At the end of the pulse 1-clockcycle signals are generated for : valid pulse, pileup or cleanup
+--
+--
+--
+-- generics
+-- ADCDATABITS : number of ADC-bits
+-- INTEGRALBITS : number of scaling bits for integral (divide by 2^INTEGRALBITS)
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- ADCdata : signed ADC value, corrected for baseline
+-- pulse_active : high gain pulse active (signal above threshold)
+-- minpulselength : number of samples below which the pulse is ignored
+--
+-- outputs
+-- pulse_valid : high gain pulse data valid, and pulse not too long
+-- singlepulse : high gain pulse detected
+-- integral : high gain scaled integral output as value for the energy
+--
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_pulse_detect is
+ generic (
+ ADCDATABITS : natural := 14;
+ INTEGRALBITS : natural := 1
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ ADCdata : in std_logic_vector(ADCDATABITS downto 0); -- signed
+ pulse_active : in std_logic;
+ minpulselength : in std_logic_vector(4 downto 0);
+ pulse_valid : out std_logic;
+ singlepulse : out std_logic;
+ integral : out std_logic_vector(15 downto 0)
+ );
+end FEE_pulse_detect;
+
+architecture Behavioral of FEE_pulse_detect is
+
+constant ZEROS : std_logic_vector(31 downto 0) := (others => '0');
+constant MAXWAVELENGTH : std_logic_vector(4 downto 0) := (others => '1');
+
+signal pulse_tooshort_S : std_logic := '0';
+signal pulse_toolong_S : std_logic := '0';
+signal prev_pulseactive_S : std_logic := '0';
+signal singlepulse_S : std_logic := '0';
+signal pulse_active_prev1_S : std_logic := '0';
+signal pulse_active_prev2_S : std_logic := '0';
+signal counter_S : std_logic_vector(4 downto 0);
+
+signal integral_S : integer range -2**(16+INTEGRALBITS) to 2**(16+INTEGRALBITS)-1;
+
+signal pulse_active_S : std_logic := '0';
+signal pulse_busy_S : std_logic := '0';
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of ADCdata : signal is "true";
+
+begin
+
+integral <= (others => '0') when integral_S<0 else conv_std_logic_vector(integral_S,16+INTEGRALBITS)(16+INTEGRALBITS-1 downto INTEGRALBITS);
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if (reset='1') then
+ integral_S <= conv_integer(signed(ADCdata));
+ else
+ if ((pulse_active='0') and (pulse_active_prev1_S='0')) or
+ ((pulse_active='1') and (pulse_active_prev1_S='0') and (pulse_active_prev2_S='1'))then
+ integral_S <= conv_integer(signed(ADCdata));
+ else
+ if integral_S+conv_integer(signed(ADCdata))>2**(16+INTEGRALBITS)-1 then
+ integral_S <= 2**(16+INTEGRALBITS)-1;
+ else
+ integral_S <= integral_S+conv_integer(signed(ADCdata));
+ end if;
+ end if;
+ end if;
+ pulse_active_prev2_S <= pulse_active_prev1_S;
+ pulse_active_prev1_S <= pulse_active;
+ end if;
+end process;
+
+
+pulse_tooshort_S <= '1' when (counter_S<minpulselength) else '0';
+
+singlepulse_S <= '1'
+ when (((pulse_active='0') and (prev_pulseactive_S='1'))
+ or ((pulse_active='0') and (counter_S=MAXWAVELENGTH) and (pulse_toolong_S='0')))
+ and ((pulse_toolong_S='0') and (pulse_tooshort_S='0'))
+ else '0';
+singlepulse <= singlepulse_S;
+
+pulse_valid <= '1'
+ when (pulse_active_S='1') and (pulse_toolong_S='0')
+ else '0';
+
+pulse_active_S <= '1'
+ when (pulse_active='1')
+ else '0';
+
+
+process(clock)
+begin
+ if rising_edge(clock) then
+-- if reset='1' then
+-- counter_S <= (others => '0');
+-- pulse_toolong_S <= '0';
+-- pulse_busy_S <= '0';
+-- else
+ if (pulse_active_S='1') or (pulse_active='1') then
+ pulse_busy_S <= '1';
+ if counter_S<MAXWAVELENGTH then
+ counter_S <= counter_S+1;
+ pulse_toolong_S <= '0';
+ else
+ pulse_toolong_S <= '1';
+ end if;
+ else
+ pulse_busy_S <= '0';
+ pulse_toolong_S <= '0';
+ counter_S <= (others => '0');
+ end if;
+-- end if;
+ prev_pulseactive_S <= pulse_active;
+ end if;
+end process;
+
+
+end Behavioral;
+
+
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 31-01-2012
-- Module Name: FEE_pulsewaveform_buffer
data_out : out std_logic_vector(35 downto 0);
data_out_read : in std_logic;
data_out_available : out std_logic;
- overflow : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)
+ overflow : out std_logic
);
end FEE_pulsewaveform_buffer;
data_out : out std_logic_vector(DATA_BITS-1 downto 0)
);
end component;
+
+COMPONENT blockmem_xilinx
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
+ );
+END COMPONENT;
+
constant zeros : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
signal data_in_S : std_logic_vector(15 downto 0) := (others => '0');
signal sample0_S : std_logic_vector(15 downto 0) := (others => '0');
signal read_data_S : std_logic_vector(35 downto 0) := (others => '0');
signal data_out_available_S : std_logic := '0';
signal pileup_detected_S : std_logic := '0';
-signal pulse_rising_S : std_logic := '0';\r
signal prev_pulse_valid_S : std_logic := '0';\r
-signal lastsample_even_S : std_logic := '0';
signal space_enough_S : std_logic := '0';
data_in_S(ADCBITS downto 0) <= data_in;
-- data_in_S(15 downto ADCBITS+1) <= (others => '0');
data_in_S(15) <= data_in_S(14);
- pulse_rising_S <= pulse_rising;\r
end if;\r
end process;
-blockmem1: blockmem port map(
- clock => clock,
- write_enable => write_enable_S,
- write_address => write_address_S,
- data_in => write_data_S,
- read_address => read_address_S,
- data_out => read_data_S);
+-- blockmem1: blockmem port map(
+ -- clock => clock,
+ -- write_enable => write_enable_S,
+ -- write_address => write_address_S,
+ -- data_in => write_data_S,
+ -- read_address => read_address_S,
+ -- data_out => read_data_S);
data_out <= read_data_S;
+blockmem1: blockmem_xilinx port map(
+ clka => clock,
+ wea(0) => write_enable_S,
+ addra => write_address_S,
+ dina => write_data_S,
+ clkb => clock,
+ addrb => read_address_S,
+ doutb => read_data_S);
+
write_data_S <= \r
"1000" & superburst & timestamp when ((writemode_S=TIMESTAMP0) and (pileup_detected_S='1')) else
wavestart_address_S <= (others => '0');
nextstart_address_S <= (others => '0');
pileup_detected_S <= '0';
- lastsample_even_S <= '0';\r
writemode_S <= ACQUIRE_EVEN;
else\r
prev_pulse_valid_S <= pulse_valid;
pileup_detected_S <= '1';
write_address_S <= wavestart_address_S; -- for timestamp
nextstart_address_S <= write_address_S+1;\r
- lastsample_even_S <= '1';
writemode_S <= TIMESTAMP0;
elsif (clear_waveform='1') or (pulse_detected='1') then
write_address_S <= wavestart_address_S+1;
pileup_detected_S <= '1';
write_address_S <= wavestart_address_S; -- for timestamp
nextstart_address_S <= write_address_S+1;
- lastsample_even_S <= '0';
writemode_S <= TIMESTAMP0;
elsif (clear_waveform='1') or (pulse_detected='1') then
write_address_S <= wavestart_address_S+1;
end if;
end process;
\r
-\r
-
-testword0(1 downto 0) <=
- "00" when (writemode_S=ACQUIRE_EVEN) else
- "01" when (writemode_S=ACQUIRE_ODD) else
- "10" when (writemode_S=TIMESTAMP0) else
- "11" when (writemode_S=SKIPPULSE) else
- "11";
-
-testword0(2) <= space_enough_S;\r
-testword0(3) <= pulse_valid;
-testword0(4) <= pulse_detected;
-testword0(5) <= pileup_detected;
-testword0(6) <= clear_waveform;\r
-testword0(7) <= write_enable_S;\r
-testword0(15 downto 8) <= write_address_S(7 downto 0);
-testword0(19 downto 16) <= write_data_S(35 downto 32);
-\r
-\r
-testword0(27 downto 20) <= read_address_S(7 downto 0);
-testword0(31 downto 28) <= read_data_S(35 downto 32);
-testword0(32) <= data_out_read;\r
-testword0(33) <= data_out_available_S;\r
-testword0(34) <= '0';\r
-\r
-
-
+
end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 06-01-2017
+-- Module Name: FEE_receive_split
+-- Description: Split commands/data from fiber to 2 data streams
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_receive_split
+-- Split commands/data from fiber to 2 data streams.
+-- Addresses 0..FEESLOWCONTROLBOARDADDRESS-1 are passed on to local FEE
+-- Addresses FEESLOWCONTROLBOARDADDRESS..2*FEESLOWCONTROLBOARDADDRESS-1 are passed on to the remote FE
+-- Addresses 2*FEESLOWCONTROLBOARDADDRESS and beyound are passed on to both FE
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+-- 0x5C address(7..0) replybit 0000000 data(31..24)
+-- data(23..0) CRC8(7..0)
+--
+--
+--
+-- Library
+-- work.panda_package : for type declarations and constants
+--
+-- Generics:
+--
+-- Inputs:
+-- clock_in : clock for input data
+-- clock_local : clock for data to local FE
+-- clock_remote : clock for data to remote FE
+-- reset : reset all
+-- GEO : which FPGA on the board, 0:this is FPGA1, 1:this is FPGA2
+-- data_in : 32 bits data input from fiber module
+-- data_in_first : first 32 bits data in packet from fiber module
+-- data_in_last : last 32 bits data in packet from fiber module
+-- data_in_present : data available from fiber module or data write in case of GEO='1'
+-- data_in_fifofull : fifo for local data is full
+-- data_local_read : read for data to local FE
+-- data_remote_read : read for data to remote FE
+--
+-- Outputs:
+-- data_in_read : read signal to fiber module to read next data
+-- data_local : packet data to local FE
+-- data_local_first : first 32 bits word in packet to local FE
+-- data_local_last : last 32 bits word in packet to local FE
+-- data_local_present : data available in fifo to local FE
+-- data_remote : packet data to remote FE
+-- data_remote_first : first 32 bits word in packet to local FE
+-- data_ermote_last : last 32 bits word in packet to local FE
+-- data_remote_present : data available in fifo to remote FE
+-- error : error in data or data loss
+--
+-- Components:
+-- async_fifo_256x32 : asynchronous fifo for local and remote data
+--
+----------------------------------------------------------------------------------
+
+entity FEE_receive_split is
+ port (
+ clock_in : in std_logic;
+ clock_local : in std_logic;
+ clock_remote : in std_logic;
+ reset : in std_logic;
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+ data_in : in std_logic_vector (31 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_present : in std_logic;
+ data_in_fifofull : out std_logic;
+ data_in_read : out std_logic;
+ data_local : out std_logic_vector(31 downto 0);
+ data_local_first : out std_logic;
+ data_local_last : out std_logic;
+ data_local_present : out std_logic;
+ data_local_read : in std_logic;
+ data_remote : out std_logic_vector(31 downto 0);
+ data_remote_first : out std_logic;
+ data_remote_last : out std_logic;
+ data_remote_present : out std_logic;
+ data_remote_read : in std_logic;
+ error : out std_logic
+ );
+end FEE_receive_split;
+
+architecture Behavioral of FEE_receive_split is
+
+component async_fifo_256x32
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(31 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(31 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+
+signal data_in_read_S : std_logic;
+signal fifo_local_data_in_S : std_logic_vector(31 downto 0);
+signal fifo_remote_data_in_S : std_logic_vector(31 downto 0);
+signal fifo_local_write_S : std_logic;
+signal fifo_remote_write_S : std_logic;
+signal retry_local_write_S : std_logic := '0';
+signal retry_remote_write_S : std_logic := '0';
+signal valid_address_local_S : std_logic;
+signal valid_address_remote_S : std_logic;
+signal valid_data_local_S : std_logic := '0';
+signal valid_data_remote_S : std_logic := '0';
+signal fifo_local_full_S : std_logic;
+signal fifo_remote_full_S : std_logic;
+signal fifo_local_empty_S : std_logic;
+signal fifo_remote_empty_S : std_logic;
+signal data_in_read_aftr1clk_S : std_logic := '0';
+signal secondwordphase_S : std_logic := '0';
+signal error_S : std_logic;
+signal timeoutcnt_S : std_logic_vector(5 downto 0) := (others => '0');
+
+signal data_local_present_S : std_logic;
+signal data_local_S : std_logic_vector(31 downto 0);
+signal data_local_read_S : std_logic;
+signal data_local_read_aftr1clk_S : std_logic;
+signal local_phase_S : std_logic;
+signal data_remote_present_S : std_logic;
+signal data_remote_S : std_logic_vector(31 downto 0);
+signal data_remote_read_S : std_logic;
+signal data_remote_read_aftr1clk_S : std_logic;
+signal remote_phase_S : std_logic;
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of data_in_read_S : signal is "true";
+-- attribute mark_debug of fifo_local_full_S : signal is "true";
+-- attribute mark_debug of fifo_remote_full_S : signal is "true";
+-- attribute mark_debug of GEO : signal is "true";
+-- attribute mark_debug of data_in : signal is "true";
+-- attribute mark_debug of data_in_first : signal is "true";
+-- attribute mark_debug of data_in_last : signal is "true";
+-- attribute mark_debug of data_in_present : signal is "true";
+-- attribute mark_debug of data_in_fifofull : signal is "true";
+-- attribute mark_debug of data_in_read : signal is "true";
+-- attribute mark_debug of data_local : signal is "true";
+-- attribute mark_debug of data_local_first : signal is "true";
+-- attribute mark_debug of data_local_last : signal is "true";
+-- attribute mark_debug of data_local_present : signal is "true";
+-- attribute mark_debug of data_local_read : signal is "true";
+-- attribute mark_debug of data_remote : signal is "true";
+-- attribute mark_debug of data_remote_first : signal is "true";
+-- attribute mark_debug of data_remote_last : signal is "true";
+-- attribute mark_debug of data_remote_present : signal is "true";
+-- attribute mark_debug of data_remote_read : signal is "true";
+-- attribute mark_debug of error : signal is "true";
+
+
+begin
+
+error <= error_S;
+data_in_fifofull <= fifo_local_full_S;
+data_local_read_S <= data_local_read;
+data_local <= data_local_S;
+data_local_present <= data_local_present_S;
+data_local_first <= '1' when (data_local_read_aftr1clk_S='1') and (local_phase_S='0') else '0';
+data_local_last <= '1' when (data_local_read_aftr1clk_S='1') and (local_phase_S='1') else '0';
+process(clock_local)
+begin
+ if (rising_edge(clock_local)) then
+ if (data_local_read_aftr1clk_S='1') then
+ if local_phase_S='0' then
+ if data_local_S(31 downto 24)=x"5C" then
+ local_phase_S <= '1';
+ end if;
+ else
+ local_phase_S <= '0';
+ end if;
+ end if;
+ data_local_read_aftr1clk_S <= data_local_read_S;
+ end if;
+end process;
+
+data_remote_read_S <= data_remote_read or GEO;
+data_remote <= data_remote_S;
+data_remote_present <= data_remote_present_S;
+data_remote_first <= '1' when (data_remote_read_aftr1clk_S='1') and (remote_phase_S='0') else '0';
+data_remote_last <= '1' when (data_remote_read_aftr1clk_S='1') and (remote_phase_S='1') else '0';
+process(clock_remote)
+begin
+ if (rising_edge(clock_remote)) then
+ if (data_remote_read_aftr1clk_S='1') then
+ if remote_phase_S='0' then
+ if data_remote_S(31 downto 24)=x"5C" then
+ remote_phase_S <= '1';
+ end if;
+ else
+ remote_phase_S <= '0';
+ end if;
+ end if;
+ data_remote_read_aftr1clk_S <= data_remote_read_S;
+ end if;
+end process;
+
+fifo_local: async_fifo_256x32 port map(
+ rst => reset,
+ wr_clk => clock_in,
+ rd_clk => clock_local,
+ din => fifo_local_data_in_S,
+ wr_en => fifo_local_write_S,
+ rd_en => data_local_read_S,
+ dout => data_local_S,
+ full => fifo_local_full_S,
+ empty => fifo_local_empty_S);
+data_local_present_S <= '1' when fifo_local_empty_S='0' else '0';
+
+fifo_remote: async_fifo_256x32 port map(
+ rst => reset,
+ wr_clk => clock_in,
+ rd_clk => clock_remote,
+ din => fifo_remote_data_in_S,
+ wr_en => fifo_remote_write_S,
+ rd_en => data_remote_read_S,
+ dout => data_remote_S,
+ full => fifo_remote_full_S,
+ empty => fifo_remote_empty_S);
+data_remote_present_S <= '1' when fifo_remote_empty_S='0' else '0';
+
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+-- 0x5C address(7..0) replybit 0000000 data(31..24)
+-- data(23..0) CRC8(7..0)
+
+
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_in_present='1') and (fifo_local_full_S='0') and (fifo_remote_full_S='0') and (GEO='0') else '0';
+
+fifo_local_data_in_S <= data_in;
+fifo_remote_data_in_S <= data_in;
+
+valid_address_local_S <= '1' when (data_in(31 downto 24)=x"5C") and -- (data_in_first='1') and
+ ((conv_integer(unsigned(data_in(23 downto 16)))<FEESLOWCONTROLBOARDADDRESS/2) or
+ (conv_integer(unsigned(data_in(23 downto 16)))>=FEESLOWCONTROLBOARDADDRESS) or
+ (GEO='1')) else '0';
+valid_address_remote_S <= '1' when (data_in(31 downto 24)=x"5C") and (GEO='0') and -- (data_in_first='1') and
+ (conv_integer(unsigned(data_in(23 downto 16)))>=FEESLOWCONTROLBOARDADDRESS/2) else '0';
+
+fifo_local_write_S <= data_in_present when GEO='1'
+ else '1' when
+ ((data_in_read_aftr1clk_S='1') or (retry_local_write_S='1')) and
+ (((secondwordphase_S='0') and (valid_address_local_S='1')) or
+ ((secondwordphase_S='1') and (valid_data_local_S='1')))
+ else '0';
+fifo_remote_write_S <= '1' when
+ ((data_in_read_aftr1clk_S='1') or (retry_remote_write_S='1')) and
+ (((secondwordphase_S='0') and (valid_address_remote_S='1')) or
+ ((secondwordphase_S='1') and (valid_data_remote_S='1')))
+ else '0';
+
+process(clock_in)
+begin
+ if (rising_edge(clock_in)) then
+ retry_local_write_S <= '0';
+ retry_remote_write_S <= '0';
+ error_S <= '0';
+ if reset='1' then
+ timeoutcnt_S <= (others => '0');
+ secondwordphase_S <= '0';
+ valid_data_local_S <= '0';
+ valid_data_remote_S <= '0';
+ else
+ if (retry_local_write_S='1') and (fifo_local_write_S='1') and (fifo_local_full_S='1') then
+ retry_local_write_S <= '1';
+ end if;
+ if (retry_remote_write_S='1') and (fifo_remote_write_S='1') and (fifo_remote_full_S='1') then
+ retry_remote_write_S <= '1';
+ end if;
+ if data_in_read_aftr1clk_S='1' then
+ timeoutcnt_S <= (others => '0');
+ if secondwordphase_S='0' then
+ if (valid_address_local_S='1') then
+ valid_data_local_S <= '1';
+ if (fifo_local_full_S='1') then
+ retry_local_write_S <= '1';
+ end if;
+ else
+ valid_data_local_S <= '0';
+ end if;
+ if (valid_address_remote_S='1') then
+ valid_data_remote_S <= '1';
+ if (fifo_remote_full_S='1') then
+ retry_remote_write_S <= '1';
+ end if;
+ else
+ valid_data_remote_S <= '0';
+ end if;
+ if (valid_address_local_S='0') and (valid_address_remote_S='0') then
+ error_S <= '1';
+ secondwordphase_S <= '0';
+ valid_data_local_S <= '0';
+ valid_data_remote_S <= '0';
+ else
+ secondwordphase_S <= '1';
+ end if;
+ else
+ secondwordphase_S <= '0';
+ if (valid_data_local_S='1') then
+ if (fifo_local_full_S='1') then
+ retry_local_write_S <= '1';
+ else
+ valid_data_local_S <= '0';
+ end if;
+ end if;
+ if (valid_data_remote_S='1') then
+ if (fifo_remote_full_S='1') then
+ retry_remote_write_S <= '1';
+ else
+ valid_data_remote_S <= '0';
+ end if;
+ end if;
+ end if;
+ else
+ if (secondwordphase_S='1') and (fifo_local_full_S='0') and (fifo_remote_full_S='1') then
+ if timeoutcnt_S(timeoutcnt_S'left)='1' then
+ error_S <= '1';
+ timeoutcnt_S <= (others => '0');
+ secondwordphase_S <= '0';
+ valid_data_local_S <= '0';
+ valid_data_remote_S <= '0';
+ else
+ timeoutcnt_S <= timeoutcnt_S+1;
+ end if;
+ end if;
+ end if;
+ end if;
+ data_in_read_aftr1clk_S <= data_in_read_S;
+ end if;
+end process;
+
+
+end Behavioral;
-- 12-09-2014 New dataformat, name changed to FEE_slowcontrol_packet_receiver
-- 22-09-2014 single clock
-- 10-10-2014 bug with high rate of slow-control commands solved
+-- 18-01-2017 bug with high rate of slow-control commands solved
----------------------------------------------------------------------------------\r
\r
library IEEE;\r
use IEEE.std_logic_1164.ALL;\r
USE ieee.std_logic_unsigned.all ;
USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
\r
----------------------------------------------------------------------------------\r
-- FEE_slowcontrol_packet_receiver\r
\r
component sync_fifo_512x41\r
port (\r
- rst : in std_logic;\r
+ srst : in std_logic;\r
clk : in std_logic;\r
din : in std_logic_vector(40 downto 0);\r
wr_en : in std_logic;\r
signal sfifo_in_S : std_logic_vector (40 downto 0);\r
signal sfifo_out_S : std_logic_vector (40 downto 0);\r
signal sfifo_full_S : std_logic := '0';\r
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of crc8_slowerror_S : signal is "true";
+-- attribute mark_debug of error_S : signal is "true";
+-- attribute mark_debug of overflow : signal is "true";
+-- attribute mark_debug of slowcontrol_write_S : signal is "true";
+-- attribute mark_debug of sfifo_full_S : signal is "true";
+-- attribute mark_debug of packet_data_valid_S : signal is "true";
\r
begin\r
data_error <= '1' when (crc8_slowerror_S='1') or (error_S='1') else '0';
-overflow <= '1' when ((slowcontrol_write_S='1') and (sfifo_full_S='1')) else '0';\r
+overflow <= '1' when ((slowcontrol_write_S='1') and (sfifo_full_S='1'))
+or (crc8_slowerror_S='1') or (error_S='1') else '0';\r
\r
packet_data_read <= packet_data_read_S;\r
packet_data_read_S <= '1' when \r
else
if packet_data_valid_S='1' then
if packet_data_in(31 downto 24)=x"5C" then -- slowcontrol
- slowcontrol_address_S <= packet_data_in(23 downto 16);
+ if NROFFEEFPGAS=1 then
+ slowcontrol_address_S <= packet_data_in(23 downto 16);
+ else -- map all ADC channel addresses to base region
+ if (conv_integer(unsigned(packet_data_in(23 downto 16)))>=FEESLOWCONTROLBOARDADDRESS/2) and
+ (conv_integer(unsigned(packet_data_in(23 downto 16)))<FEESLOWCONTROLBOARDADDRESS) then
+ slowcontrol_address_S <= packet_data_in(23 downto 16)-conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS/2,8);
+ else
+ slowcontrol_address_S <= packet_data_in(23 downto 16);
+ end if;
+ end if;
slowcontrol_request_S <= packet_data_in(15);
slowcontrol_data_S(31 downto 24) <= packet_data_in(7 downto 0);
error_S <= '0';
begin
if rising_edge(clock) then
if reset='1' then
- slowcontrol_write_S <= '0';
+-- slowcontrol_write_S <= '0';
slowpacketvalid_S <= '0';
crc8_slowerror_S <= '0';
else
if slowpacketvalid_S='0' then
- slowcontrol_write_S <= '0';
+-- slowcontrol_write_S <= '0';
crc8_slowerror_S <= '0';
if (rec_state_S=slow1) and (packet_data_valid_S='1') and (enable_S='1') then
slowpacketvalid_S <= '1';
else
slowpacketvalid_S <= '0';
if (crc8_data_out_valid_S='1') and (crc8_data_out_last_S='1') and (crc8_error_S='0') then -- everything ok
- slowcontrol_write_S <= enable_S;
+-- slowcontrol_write_S <= enable_S;
crc8_slowerror_S <= '0';
else
- slowcontrol_write_S <= '0';
+-- slowcontrol_write_S <= '0';
crc8_slowerror_S <= enable_S;
end if;
end if;
end if;
end process slowcontrolpackethandling;
+slowcontrol_write_S <= '1' when (slowpacketvalid_S='1') and (crc8_data_out_valid_S='1') and (crc8_data_out_last_S='1') and (crc8_error_S='0') and (enable_S='1') else '0';
+
sfifo_in_S(31 downto 0) <= slowcontrol_data_S;
sfifo_in_S(39 downto 32) <= slowcontrol_address_S;
sfifo_in_S(40) <= slowcontrol_request_S;
sfifo: sync_fifo_512x41 port map(\r
- rst => reset,\r
+ srst => reset,\r
clk => clock,\r
din => sfifo_in_S,\r
wr_en => slowcontrol_write_S,\r
---------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 21-03-2011
-- Module Name: FEE_slowcontrol_receive_from_cpu
-- 12-09-2014 Reduce nrof Registers to 2, replaced channel by address
-- 22-09-2014 single clock
-- 08-10-2014 error signal removed
+-- 23-02-2017 back to 4 registers again
----------------------------------------------------------------------------------
library IEEE;
-- reset : synchronous reset
-- address : base-address of channel
-- byte_data : 8-bits slowcontrol data:
--- Byte0 : bit7..4=index of the channel bit3..2=index of register
+-- Byte0 : bit7..2=index of the channel bit1..0=index of register
-- Byte1,2,3,4 : 32-bits data, MSB first
-- byte_write : write signal for byte-data, only selected channel (with index in first byte equals channel) should read\r
-- byte_request : request signal for reading data, here only used for check and synchronization
-- Outputs:
-- register_A : 32-bits output register A
-- register_B : 32-bits output register B
+-- register_C : 32-bits output register C
+-- register_D : 32-bits output register D
--
-- Components:
--
byte_write : in std_logic;
byte_request : in std_logic;
register_A : out std_logic_vector (31 downto 0);
- register_B : out std_logic_vector (31 downto 0)
+ register_B : out std_logic_vector (31 downto 0);
+ register_C : out std_logic_vector (31 downto 0);
+ register_D : out std_logic_vector (31 downto 0)
);
end FEE_slowcontrol_receive_from_cpu;
signal byte_idx_S : integer range 0 to 4 := 0;
signal selected_S : std_logic := '0';
signal register_buf_S : std_logic_vector(31 downto 8);\r
-signal selected_reg_S : std_logic_vector(0 downto 0);\r
+signal selected_reg_S : std_logic_vector(1 downto 0);\r
\r
-signal register_A_S : std_logic_vector (31 downto 0) := x"12183264"; -- default FEE
-signal register_B_S : std_logic_vector (31 downto 0) := x"0C643208"; -- default FEE
+signal register_A_S : std_logic_vector (31 downto 0) := x"28043264"; -- x"12183264"; -- default FEE
+signal register_B_S : std_logic_vector (31 downto 0) := x"4C64140a"; -- x"4C641C05"; -- default FEE
+signal register_C_S : std_logic_vector (31 downto 0) := x"1B72020A"; -- default FEE
+signal register_D_S : std_logic_vector (31 downto 0) := x"00000000"; -- default FEE
+\r
+-- board_register A: write
+-- register_A(7..0) = threshold High
+-- register_A(15..8) = threshold Low
+-- register_A(16) = disable High
+-- register_A(17) = disable Low
+-- register_A(23..18) = I/Max discard
+-- register_A(29..24) = I/Max pileup
+-- register_A(30) = enable raw data in waveform instead of baseline corrected data
+-- board_register B: write
+-- register_B(7..0) = minimum pulselength
+-- register_B(15..8) = pileup length
+-- register_B(23..16) = maximum wavelength
+-- register_B(24) = fullsize High
+-- register_B(25) = fullsize Low
+-- register_B(29..26) = CF delay
+-- register_B(31..30) = CF delay Pileup
+-- board_register C: write
+-- register_C(4..0) = MWD1_width
+-- register_C(9..8) = MWD2_width
+-- register_C(11..10) = MWDpu1_width
+-- register_C(13..12) = MWDpu2_width
+-- register_C(31..16) = MWD1_tau_factor , MWD2_tau_factor
+-- board_register D: write
+-- register_D(15..0) = MWDpu1_tau_factor
+-- register_D(31..16) = MWDpu2_tau_factor
\r
--- register_A(7..0) = threshold High
--- register_A(15..8) = threshold Low
--- register_A(16) = disable High
--- register_A(17) = disable Low
--- register_A(23..18) = I/Max discard
--- register_A(29..24) = I/Max pileup
--- register_B(7..0) = minimum pulselength
--- register_B(15..8) = pileup length
--- register_B(23..16) = maximum wavelength
--- register_B(24) = fullsize High\r
--- register_B(25) = fullsize Low\r
--- register_B(29..26) = CF delay\r
\r
begin\r
\r
register_A <= register_A_S;\r
-register_B <= register_B_S;\r
+register_B <= register_B_S;
+register_C <= register_C_S;
+register_D <= register_D_S;
rd_process: process(clock)
else
if byte_idx_S=0 then\r
if (byte_write='1') then
- if (byte_data(7 downto 1)=address(7 downto 1)) then
+ if (byte_data(7 downto 2)=address(7 downto 2)) then
selected_S <= '1';
- selected_reg_S <= byte_data(0 downto 0);
+ selected_reg_S <= byte_data(1 downto 0);
else
selected_S <= '0';
end if;
register_buf_S(15 downto 8) <= byte_data;\r
when 4 => \r
case selected_reg_S is \r
- when "0" => register_A_S <= register_buf_S(31 downto 8) & byte_data;\r
- when "1" => register_B_S <= register_buf_S(31 downto 8) & byte_data;\r
+ when "00" => register_A_S <= register_buf_S(31 downto 8) & byte_data;\r
+ when "01" => register_B_S <= register_buf_S(31 downto 8) & byte_data;
+ when "10" => register_C_S <= register_buf_S(31 downto 8) & byte_data;
+ when "11" => register_D_S <= register_buf_S(31 downto 8) & byte_data;
when others =>\r
end case;\r
when others =>\r
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 05-03-2012
-- Module Name: FEE_sorting_mux
-- 22-09-2014: single clock
-- 11-10-2014: adc-channel number 8 bits
-- 16-10-2014: inpipe check
+-- 21-07-2015: data_out_inpipe clocked
+-- 13-10-2015: time difference between channel checked with fifo counts
+-- 05-11-2015: time difference between fifo input and output
+-- 04-19-2016: additional check on recent read from input fifo
+-- 21-02-2017: rewritten to parallel in/out instead of 36bits words
----------------------------------------------------------------------------------
library IEEE;
----------------------------------------------------------------------------------
-- FEE_sorting_mux
--- Multiplexes multiple input pulse data stream with waveform data to one stream.
--- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check
--- The data is sorted based on the 32-bits timestamp.
--- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.
+-- Multiplexes multiple input pulse data stream to one stream.
+-- The input contains hit data: channelnumber, superburstnumber, time within superburst, Constant Fraction method: sample before and after, energy and status.
+-- The data is sorted based on the superburst number, the 16-bits timestamp within the superburst and the fractional part.
+-- This sorting is done by comparing the time of 2 items; the first in time is passed on.
-- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
--
-- Library:
-- work.panda_package: constants and types
--
-- Generics:
--- NROFMUXINPUTS : number of input-channels\r
+-- NROFMUXINPUTS : number of input-channels
--
-- Inputs:
--- inputclock : clock for input data (write side incomming fifo)
--- MUXclock : clock for multiplexer part, between the fifos
--- outputclock : clock for output data (read side outgoing fifo)
+-- clock : clock for input data (write side incomming fifo)
-- reset : reset, must be long enough for all clocks
--- data_in : array of input data streams, structure of each (three 36-bits words):
--- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
--- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
--- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- superburstnumber : actual superburstnumber that is sent by SODA
+-- superburstupdate : new superburstnumber issued by SODA
+-- data_in_status : status-byte, for each connected FEE
+-- data_in_lowgain : high or low gain channel, for each connected FEE
+-- data_in_superburst : superburstnumber, for each connected FEE
+-- data_in_timestamp : time within superburst, for each connected FEE
+-- data_in_energy : energy of the hit, for each connected FEE
+-- data_in_CFvalbefore : Constant Fraction result: sample before zero-crossing, for each connected FEE
+-- data_in_CFvalafter : Constant Fraction result: sample after zero-crossing, for each connected FEE
-- data_in_write : write signal for data_in (write into fifo)
-- data_out_read : read signal for outgoing data (read from fifo)
--
-- Outputs:
-- data_in_allowed : write to input data allowed (not full)
--- data_in_almostfull : input fifo is too full for maximum length waveform
--- data_out : output data (three 36-bits words):
--- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
--- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
--- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
--- data_out_available : data_out available (output fifo not empty)\r
+-- data_out_channel : pulse-data : adc channel number
+-- data_out_status : pulse-data : status
+-- data_out_superburst : pulse-data : superburstnumber
+-- data_out_timestamp : pulse-data : time (ADC-clock)
+-- data_out_energy : pulse-data : energy
+-- data_out_CFvalbefore : pulse-data : Constant Fraction result: sample before zero-crossing
+-- data_out_CFvalafter : pulse-data : Constant Fraction result: sample after zero-crossing
+-- data_out_available : data_out available (output fifo not empty)
-- data_out_inpipe : more data on its way
-- error : data error, index in data words incorrect
--
--- Components:\r
--- FEE_mux_readfifo : read data from fifo and writes to next level\r
--- FEE_mux2to1 : compares the data and passes the first in time on\r
--- sync_fifo_progfull504_progempty128_512x36 : synchronous fifo with programmable full and empty
--- sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through
---
+-- Components:
+-- FEE_mux2to1 : compares the data and passes the first in time on
+-- sync_fifo_progempty32_FWFT_512x104 : synchronous fifo for input data
+-- sync_fifo_512x111 : synchronous fifo for output data
--
--
----------------------------------------------------------------------------------
entity FEE_sorting_mux is
generic(
- NROFMUXINPUTS : natural := 8
+ NROFMUXINPUTS : natural := 16
);
- Port (
+ port (
clock : in std_logic;
reset : in std_logic;
- data_in : in array_halfadc36bits_type;
+ superburstnumber : in std_logic_vector(30 downto 0);
+ superburstupdate : in std_logic;
+ data_in_status : in array_halfadc8bits_type;
+ data_in_lowgain : in std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_superburst : in array_halfadc31bits_type;
+ data_in_timestamp : in array_halfadc16bits_type;
+ data_in_energy : in array_halfadc16bits_type;
+ data_in_CFvalbefore : in array_halfadc16bits_type;
+ data_in_CFvalafter : in array_halfadc16bits_type;
data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
- data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
- data_out : out std_logic_vector(35 downto 0);
+ data_out_channel : out std_logic_vector(7 downto 0);
+ data_out_status : out std_logic_vector(7 downto 0);
+ data_out_superburst : out std_logic_vector(30 downto 0);
+ data_out_timestamp : out std_logic_vector(15 downto 0);
+ data_out_energy : out std_logic_vector(15 downto 0);
+ data_out_CFvalbefore : out std_logic_vector(15 downto 0);
+ data_out_CFvalafter : out std_logic_vector(15 downto 0);
data_out_read : in std_logic;
data_out_available : out std_logic;
data_out_inpipe : out std_logic;
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0);
- testword1 : out std_logic_vector(35 downto 0)
+ error : out std_logic
);
end FEE_sorting_mux;
-architecture Behavioral of FEE_sorting_mux is\r
-\r
-component FEE_mux2to1 is\r
- Port (\r
- clock : in std_logic;
- reset : in std_logic;\r
- data1_in : in std_logic_vector(35 downto 0); \r
- data1_in_write : in std_logic;\r
- data1_in_available : in std_logic;
- data1_in_allowed : out std_logic;\r
- data2_in : in std_logic_vector(35 downto 0); \r
- data2_in_write : in std_logic;\r
- data2_in_available : in std_logic;
- data2_in_allowed : out std_logic;\r
- data_out : out std_logic_vector(35 downto 0);\r
- data_out_write : out std_logic;\r
- data_out_available : out std_logic;
- data_out_allowed : in std_logic;\r
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)\r
- );\r
-end component;
-\r
-component FEE_mux_readfifo is
+
+architecture Behavioral of FEE_sorting_mux is
+
+component FEE_mux2to1 is
port (
clock : in std_logic;
reset : in std_logic;
- data_in : in std_logic_vector(35 downto 0);
- data_in_available : in std_logic;
- data_in_read : out std_logic;\r
- data_out : out std_logic_vector(35 downto 0);
+ channel1 : in std_logic_vector(7 downto 0);
+ statusbyte1 : in std_logic_vector(7 downto 0);
+ energy1 : in std_logic_vector(15 downto 0);
+ CFvalbefore1 : in std_logic_vector(15 downto 0);
+ CFvalafter1 : in std_logic_vector(15 downto 0);
+ timestamp1 : in std_logic_vector(15 downto 0);
+ superburst1 : in std_logic_vector(30 downto 0);
+ data1_in_write : in std_logic;
+ data1_in_inpipe : in std_logic;
+ data1_in_allowed : out std_logic;
+ channel2 : in std_logic_vector(7 downto 0);
+ statusbyte2 : in std_logic_vector(7 downto 0);
+ energy2 : in std_logic_vector(15 downto 0);
+ CFvalbefore2 : in std_logic_vector(15 downto 0);
+ CFvalafter2 : in std_logic_vector(15 downto 0);
+ timestamp2 : in std_logic_vector(15 downto 0);
+ superburst2 : in std_logic_vector(30 downto 0);
+ data2_in_write : in std_logic;
+ data2_in_inpipe : in std_logic;
+ data2_in_allowed : out std_logic;
+ channel : out std_logic_vector(7 downto 0);
+ statusbyte : out std_logic_vector(7 downto 0);
+ energy : out std_logic_vector(15 downto 0);
+ CFvalbefore : out std_logic_vector(15 downto 0);
+ CFvalafter : out std_logic_vector(15 downto 0);
+ timestamp : out std_logic_vector(15 downto 0);
+ superburst : out std_logic_vector(30 downto 0);
data_out_write : out std_logic;
data_out_inpipe : out std_logic;
- data_out_allowed : in std_logic);\r
+ data_out_allowed : in std_logic;
+ error : out std_logic
+ );
end component;
-\r
-component sync_fifo_progfull504_progempty128_512x36
- port (
- rst : in std_logic;
+
+component sync_fifo_progempty32_FWFT_512x104 is
+port (
+ srst : in std_logic;
clk : in std_logic;
- din : in std_logic_vector(35 downto 0);
+ din : in std_logic_vector(103 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
- dout : out std_logic_vector(35 downto 0);
+ dout : out std_logic_vector(103 downto 0);
full : out std_logic;
empty : out std_logic;
- prog_full : out std_logic;
- prog_empty : out std_logic);
+ prog_empty : out std_logic
+ );
end component;
-component sync_fifo_FWFT_512x36
+component sync_fifo_512x111
port (
- rst : in std_logic;
+ srst : in std_logic;
clk : in std_logic;
- din : in std_logic_vector(35 downto 0);
+ din : in std_logic_vector(110 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
- dout : out std_logic_vector(35 downto 0);
+ dout : out std_logic_vector(110 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
-\r
-\r
+
type twologarray_type is array(0 to 63) of natural;
constant twologarray : twologarray_type :=
(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
-constant mux2to1_gen_max : integer := twologarray(NROFMUXINPUTS); -- -1;
-constant INPIPE_DELAY : integer := 63;
-constant zeros : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-constant ones : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
-\r
---type mux2to1_gen_type is array(0 to mux2to1_gen_max-1) of integer;\r
---constant mux2to1_gen : mux2to1_gen_type := (8,4,2,1);\r
-\r
-type data_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);\r
-type singlebit_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic;\r
-\r
-signal error_S : std_logic := '0';\r
-\r
-signal data_S : data_type;\r
-signal data_out_inpipe_S : singlebit_type := (others => (others => '0'));
-signal data_write_S : singlebit_type := (others => (others => '0'));
-signal data_allowed_S : singlebit_type := (others => (others => '0'));
-signal error_array_S : singlebit_type := (others => (others => '0'));\r
-\r
-signal reset_MUXclock_S : std_logic := '0';\r
-\r
+constant mux2to1_gen_max : integer := twologarray(NROFMUXINPUTS);
+constant INPIPE_DELAY_BITS : integer := 4;
+constant ZEROS : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+constant ONES : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+
+type fiber_index_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(3 downto 0);
+type statusbyte_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(7 downto 0);
+type energy_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(15 downto 0);
+type timefraction_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(11 downto 0);
+type timestamp_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(15 downto 0);
+type superburstnumber_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(30 downto 0);
+
+type element8bits_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(7 downto 0);
+type element16bits_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(15 downto 0);
+type element31bits_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(30 downto 0);
+
+type matrix8bits_type is array(0 to mux2to1_gen_max) of element8bits_type;
+type matrix16bits_type is array(0 to mux2to1_gen_max) of element16bits_type;
+type matrix31bits_type is array(0 to mux2to1_gen_max) of element31bits_type;
+type matrix1bits_type is array(0 to mux2to1_gen_max) of std_logic_vector(0 to NROFMUXINPUTS-1);
+
+constant allZEROS : matrix1bits_type := (others => (others => '0'));
+
+signal error_S : std_logic := '0';
+signal reset_S : std_logic;
+signal timeout_counter_S : std_logic_vector (13 downto 0) := (others => '0');
+
+signal superburstnumber_S : std_logic_vector (30 downto 0) := (others => '0');
+signal timestampcounter_S : std_logic_vector (15 downto 0) := (others => '0');
+
+signal channel_S : matrix8bits_type;
+signal superburst_S : matrix31bits_type;
+signal statusbyte_S : matrix8bits_type;
+signal timestamp_S : matrix16bits_type;
+signal energy_S : matrix16bits_type;
+signal CFvalafter_S : matrix16bits_type;
+signal CFvalbefore_S : matrix16bits_type;
+
+signal data_out_inpipe_S : matrix1bits_type;
+signal data_write_S : matrix1bits_type;
+signal data_allowed_S : matrix1bits_type;
+signal error_array_S : matrix1bits_type;
+
+signal reset_MUXclock_S : std_logic := '0';
+
+
-- signals for fifo from adc-fe to adc-mux
signal dfifo_wr_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_wr1_S : std_logic_vector(0 to NROFMUXINPUTS-1);
+signal dfifo_wr2_S : std_logic_vector(0 to NROFMUXINPUTS-1);
signal dfifo_rd_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_out_S : array_halfadc36bits_type := (others => (others => '0'));
signal dfifo_full_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
signal dfifo_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal data_in_available_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_prog_full_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
signal dfifo_prog_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-\r
-signal delay_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
-signal read36_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal waitafterwrite_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-- signals for fifo from adc-mux to packet-composer
-signal tfifo_in_S : std_logic_vector (35 downto 0);\r
+signal tfifo_wr_S : std_logic := '0';
signal tfifo_rd_S : std_logic := '0';
signal tfifo_full_S : std_logic := '0';
signal tfifo_empty_S : std_logic := '0';
-\r
-type testword_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector (35 downto 0);\r
-signal testword0_S : testword_type;\r
-\r
+signal tfifo_statusbyte_S : std_logic_vector (7 downto 0);
+signal moretocome_S : std_logic;
+
+
+-- tests
+signal sorterroroccured_S : std_logic := '0';
+signal sorterrorcount_S : std_logic_vector (7 downto 0);
+
+signal sorterror_S : std_logic := '0';
+signal lastsuperburst_S : std_logic_vector (30 downto 0);
+signal lasttimestamp_S : std_logic_vector (15 downto 0);
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of error_array_S : signal is "true";
+-- attribute mark_debug of data_out_inpipe_S : signal is "true";
+-- attribute mark_debug of data_write_S : signal is "true";
+-- attribute mark_debug of data_allowed_S : signal is "true";
+
+
+begin
+
+error <= error_S;
+
+timestampcounter: process(clock)
begin
+ if (rising_edge(clock)) then
+ if superburstupdate='1' then
+ timestampcounter_S <= (others => '0');
+ superburstnumber_S <= superburstnumber;
+ else
+ timestampcounter_S <= timestampcounter_S+1;
+ end if;
+ end if;
+end process;
+
+
+mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate
-\r
-data_out_inpipe <= '1' \r
- when dfifo_empty_S/=ones(0 to NROFMUXINPUTS-1) or (tfifo_empty_S='0') or (data_out_inpipe_S(mux2to1_gen_max,0)='1')\r
- else '0';\r
-\r
-
-MUX_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate
-\r
-process(clock)\r
-type inpipe_counter_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to INPIPE_DELAY;\r
-variable inpipe_counter_V : inpipe_counter_type := (others => 0);\r
-variable index_other : integer range 0 to NROFMUXINPUTS-1;\r
-begin\r
- if rising_edge(clock) then\r
- if reset='1' then\r
- inpipe_counter_V(index) := 0;\r
- delay_inpipe_S(index) <= '0';\r
- else\r
- index_other := conv_integer(unsigned((conv_std_logic_vector(index,8) xor x"01")));\r
- if ((dfifo_wr_S(index)='1') and (dfifo_prog_empty_S(index)='1')) or\r
- ((dfifo_wr_S(index_other)='1') and (dfifo_prog_empty_S(index_other)='1'))\r
- then\r
- inpipe_counter_V(index) := INPIPE_DELAY;\r
- delay_inpipe_S(index) <= '1';\r
- else \r
- if inpipe_counter_V(index)/=0 then\r
- inpipe_counter_V(index) := inpipe_counter_V(index)-1;\r
- delay_inpipe_S(index) <= '1';\r
- else\r
- delay_inpipe_S(index) <= '0';\r
- end if;\r
- end if;\r
- end if;\r
- end if;\r
-end process;\r
-
-dfifo: sync_fifo_progfull504_progempty128_512x36 port map(
- rst => reset,
+dfifo: sync_fifo_progempty32_FWFT_512x104 port map(
+ srst => reset,
clk => clock,
- din => data_in(index),
+ din(15 downto 0) => data_in_CFvalbefore(index),
+ din(31 downto 16) => data_in_CFvalafter(index),
+ din(47 downto 32) => data_in_energy(index),
+ din(63 downto 48) => data_in_timestamp(index),
+ din(94 downto 64) => data_in_superburst(index),
+ din(95) => data_in_lowgain(index),
+ din(103 downto 96) => data_in_status(index),
wr_en => dfifo_wr_S(index),
rd_en => dfifo_rd_S(index),
- dout => dfifo_out_S(index),
+ dout(15 downto 0) => CFvalbefore_S(0)(index),
+ dout(31 downto 16) => CFvalafter_S(0)(index),
+ dout(47 downto 32) => energy_S(0)(index),
+ dout(63 downto 48) => timestamp_S(0)(index),
+ dout(94 downto 64) => superburst_S(0)(index),
+ dout(95) => channel_S(0)(index)(0),
+ dout(103 downto 96) => statusbyte_S(0)(index),
full => dfifo_full_S(index),
empty => dfifo_empty_S(index),
- prog_full => data_in_almostfull(index),
prog_empty => dfifo_prog_empty_S(index));
- \r
-dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
+
+dfifo_wr_S(index) <= data_in_write(index);
data_in_allowed(index) <= NOT dfifo_full_S(index);
-\r
-data_in_available_S(index) <= '1' when dfifo_empty_S(index)='0' else '0';\r
-\r
-FEE_mux_readfifo1: FEE_mux_readfifo port map(
- clock => clock,
- reset => reset,
- data_in => dfifo_out_S(index),
- data_in_available => data_in_available_S(index),
- data_in_read => dfifo_rd_S(index),\r
- data_out => data_S(0,index),
- data_out_write => data_write_S(0,index),
- data_out_inpipe => read36_inpipe_S(index),
- data_out_allowed => data_allowed_S(0,index));\r
-\r
-process(data_out_inpipe_S(0,index),read36_inpipe_S(index),delay_inpipe_S(index),dfifo_wr_S(index)) -- ,dfifo_prog_empty_S)\r
---variable index_other : integer range 0 to NROFMUXINPUTS-1;\r
-begin\r
--- index_other := conv_integer(unsigned((conv_std_logic_vector(index,16) xor x"0001")));\r
--- if (read36_inpipe_S(index)='1') or ((dfifo_prog_empty_S(index_other)='1') and (delay_inpipe_S(index)='1')) or\r
--- (dfifo_wr_occuredrecently_S(index)='1') or -- was there a write recently (time: one datapacket plus a few slowcontrols ?\r
- if (read36_inpipe_S(index)='1') or (delay_inpipe_S(index)='1') or\r
- (dfifo_wr_S(index)='1') then\r
- data_out_inpipe_S(0,index) <= '1';\r
- else\r
- data_out_inpipe_S(0,index) <= '0';\r
- end if;\r
-end process;\r
-
-end generate;\r
-\r
-\r
-MUX_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate \r
-\r
- MUX_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate
- \r
- FEE_mux2to1_1: FEE_mux2to1 port map(\r
+
+channel_S(0)(index)(7 downto 1) <= conv_std_logic_vector(index,7);
+
+waitafterwrite_S(index) <= '0'
+ when ((superburstnumber_S & timestampcounter_S)-(superburst_S(0)(index) & timestamp_S(0)(index))>255)
+ or (dfifo_prog_empty_S(index)='0')
+ else '1';
+data_write_S(0)(index) <= '1' when (data_allowed_S(0)(index)='1') and (dfifo_empty_S(index)='0') and (waitafterwrite_S(index)='0') else '0';
+dfifo_rd_S(index) <= data_write_S(0)(index);
+data_out_inpipe_S(0)(index) <= '1' when (dfifo_empty_S(index)='0') or (dfifo_wr_S(index)='1') or (dfifo_wr1_S(index)='1') or (dfifo_wr2_S(index)='1') else '0';
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ dfifo_wr1_S(index) <= dfifo_wr_S(index);
+ dfifo_wr2_S(index) <= dfifo_wr1_S(index);
+ end if;
+end process;
+
+end generate;
+
+
+multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate
+
+ multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate
+
+ FEE_mux2to1_1: FEE_mux2to1 port map(
clock => clock,
- reset => reset,
- data1_in => data_S(i1,i2*2),\r
- data1_in_write => data_write_S(i1,i2*2),\r
- data1_in_available => data_out_inpipe_S(i1,i2*2),
- data1_in_allowed => data_allowed_S(i1,i2*2),\r
- data2_in => data_S(i1,i2*2+1),\r
- data2_in_write => data_write_S(i1,i2*2+1),\r
- data2_in_available => data_out_inpipe_S(i1,i2*2+1),
- data2_in_allowed => data_allowed_S(i1,i2*2+1),\r
- data_out => data_S(i1+1,i2),\r
- data_out_write => data_write_S(i1+1,i2),\r
- data_out_available => data_out_inpipe_S(i1+1,i2),
- data_out_allowed => data_allowed_S(i1+1,i2),\r
- error => error_array_S(i1,i2),
- testword0 => testword0_S(i1,i2));\r
- \r
- end generate;\r
-end generate;\r
-\r
-process(clock)\r
+ reset => reset_S,
+ channel1 => channel_S(i1)(i2*2),
+ statusbyte1 => statusbyte_S(i1)(i2*2),
+ energy1 => energy_S(i1)(i2*2),
+ CFvalbefore1 => CFvalbefore_S(i1)(i2*2),
+ CFvalafter1 => CFvalafter_S(i1)(i2*2),
+ timestamp1 => timestamp_S(i1)(i2*2),
+ superburst1 => superburst_S(i1)(i2*2),
+ data1_in_write => data_write_S(i1)(i2*2),
+ data1_in_inpipe => data_out_inpipe_S(i1)(i2*2),
+ data1_in_allowed => data_allowed_S(i1)(i2*2),
+ channel2 => channel_S(i1)(i2*2+1),
+ statusbyte2 => statusbyte_S(i1)(i2*2+1),
+ energy2 => energy_S(i1)(i2*2+1),
+ CFvalbefore2 => CFvalbefore_S(i1)(i2*2+1),
+ CFvalafter2 => CFvalafter_S(i1)(i2*2+1),
+ timestamp2 => timestamp_S(i1)(i2*2+1),
+ superburst2 => superburst_S(i1)(i2*2+1),
+ data2_in_write => data_write_S(i1)(i2*2+1),
+ data2_in_inpipe => data_out_inpipe_S(i1)(i2*2+1),
+ data2_in_allowed => data_allowed_S(i1)(i2*2+1),
+ channel => channel_S(i1+1)(i2),
+ statusbyte => statusbyte_S(i1+1)(i2),
+ energy => energy_S(i1+1)(i2),
+ CFvalbefore => CFvalbefore_S(i1+1)(i2),
+ CFvalafter => CFvalafter_S(i1+1)(i2),
+ timestamp => timestamp_S(i1+1)(i2),
+ superburst => superburst_S(i1+1)(i2),
+ data_out_write => data_write_S(i1+1)(i2),
+ data_out_inpipe => data_out_inpipe_S(i1+1)(i2),
+ data_out_allowed => data_allowed_S(i1+1)(i2),
+ error => error_array_S(i1)(i2));
+
+ end generate;
+end generate;
+
+process(clock)
begin
- if (rising_edge(clock)) then \r
- error_S <= '0';\r
- for i1 in 0 to mux2to1_gen_max-1 loop \r
+ if (rising_edge(clock)) then
+ error_S <= '0';
+ for i1 in 0 to mux2to1_gen_max-1 loop
for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop
- if error_array_S(i1,i2)='1' then\r
- error_S <= '1';\r
- end if;\r
- end loop;\r
- end loop;\r
- end if;\r
+ if error_array_S(i1)(i2)='1' then
+ error_S <= '1';
+ end if;
+ end loop;
+ end loop;
+ end if;
+end process;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if data_out_inpipe_S=allZEROS then
+ moretocome_S <= '0';
+ else
+ moretocome_S <= '1';
+ end if;
+ end if;
end process;
-error <= error_S;\r
-\r
-data_allowed_S(mux2to1_gen_max,0) <= '1' when (tfifo_full_S='0') else '0';\r
-tfifo_in_S <= data_S(mux2to1_gen_max,0);
-tfifo: sync_fifo_FWFT_512x36 port map(
- rst => reset,
+
+data_allowed_S(mux2to1_gen_max)(0) <= '1' when (tfifo_full_S='0') else '0';
+
+tfifo_wr_S <= '1' when (data_write_S(mux2to1_gen_max)(0)='1') else '0';
+
+tfifo: sync_fifo_512x111 port map(
+ srst => reset,
clk => clock,
- din => tfifo_in_S,
- wr_en => data_write_S(mux2to1_gen_max,0),
+ din(15 downto 0) => CFvalbefore_S(mux2to1_gen_max)(0),
+ din(31 downto 16) => CFvalafter_S(mux2to1_gen_max)(0),
+ din(47 downto 32) => energy_S(mux2to1_gen_max)(0),
+ din(63 downto 48) => timestamp_S(mux2to1_gen_max)(0),
+ din(94 downto 64) => superburst_S(mux2to1_gen_max)(0),
+ din(102 downto 95) => statusbyte_S(mux2to1_gen_max)(0),
+ din(110 downto 103) => channel_S(mux2to1_gen_max)(0),
+ wr_en => tfifo_wr_S,
rd_en => tfifo_rd_S,
- dout => data_out,
+ dout(15 downto 0) => data_out_CFvalbefore,
+ dout(31 downto 16) => data_out_CFvalafter,
+ dout(47 downto 32) => data_out_energy,
+ dout(63 downto 48) => data_out_timestamp,
+ dout(94 downto 64) => data_out_superburst,
+ dout(102 downto 95) => data_out_status,
+ dout(110 downto 103) => data_out_channel,
full => tfifo_full_S,
- empty => tfifo_empty_S);\r
-\r
-
-tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';\r
-data_out_available <= '1' when tfifo_empty_S='0' else '0';\r
-\r
-\r
-\r
-\r
---testword0(33 downto 0) <= data_in(0)(33 downto 0);
---testword0(34) <= time_error_S;
---testword0(35) <= idx_error_S;
-testword1(33 downto 0) <= data_in(1)(33 downto 0);
-testword1(34) <= '0';
-testword1(35) <= '0';
-\r
-\r
-\r
-
-gentest: for i in 0 to 7 generate
-testword0(i) <= dfifo_full_S(i);\r
-end generate;\r
-
-testword0(8) <= dfifo_rd_S(7);\r
-testword0(9) <= data_in_available_S(7);\r
-\r
-testword0(10) <= data_write_S(0,7);\r
-testword0(11) <= data_out_inpipe_S(0,7);\r
-testword0(12) <= data_allowed_S(0,7);\r
-\r
-testword0(13) <= data_write_S(1,3);\r
-testword0(14) <= data_out_inpipe_S(1,3);\r
-testword0(15) <= data_allowed_S(1,3);\r
-\r
-testword0(16) <= data_write_S(2,1);\r
-testword0(17) <= data_out_inpipe_S(2,1);\r
-testword0(18) <= data_allowed_S(2,1);\r
-\r
-testword0(19) <= data_write_S(3,0);\r
-testword0(20) <= data_out_inpipe_S(3,0);\r
-testword0(21) <= data_allowed_S(3,0);\r
-\r
-\r
-testword0(22) <= data_write_S(0,0);\r
-testword0(23) <= data_out_inpipe_S(0,0);\r
-testword0(24) <= data_allowed_S(0,0);\r
-\r
-testword0(25) <= data_write_S(1,0);\r
-testword0(26) <= data_out_inpipe_S(1,0);\r
-testword0(27) <= data_allowed_S(1,0);\r
-\r
-testword0(28) <= data_write_S(2,0);\r
-testword0(29) <= data_out_inpipe_S(2,0);\r
-testword0(30) <= data_allowed_S(2,0);\r
-\r
-
-testword0(31) <= data_write_S(mux2to1_gen_max,0);
-testword0(32) <= tfifo_full_S;
-testword0(33) <= tfifo_rd_S;
-testword0(34) <= error_S;\r
-testword0(35) <= '0';
---\r
---\r
---\r
---testword1 <= testword0_S(2,0);
+ empty => tfifo_empty_S);
+tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';
+data_out_available <= '1' when tfifo_empty_S='0' else '0';
+
+data_out_inpipe <= '1' when (tfifo_empty_S='0') or (moretocome_S='1') else '0';
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if (tfifo_wr_S='1') or (tfifo_full_S='1') or (dfifo_empty_S=ONES) or (timeout_counter_S(timeout_counter_S'left)='1') then
+ timeout_counter_S <= (others => '0');
+ else
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ end if;
+end process;
+reset_S <= '1' when (reset='1') or (timeout_counter_S(timeout_counter_S'left)='1') else '0';
+
+sorterror_S <= '1' when (data_write_S(mux2to1_gen_max)(0)='1') and (
+ (superburst_S(mux2to1_gen_max)(0)<lastsuperburst_S)
+ or ((superburst_S(mux2to1_gen_max)(0)=lastsuperburst_S) and (timestamp_S(mux2to1_gen_max)(0)<lasttimestamp_S))
+ ) else '0';
+
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ lastsuperburst_S <= (others => '0');
+ lasttimestamp_S <= (others => '0');
+ sorterrorcount_S <= (others => '0');
+ else
+ if data_write_S(mux2to1_gen_max)(0)='1' then
+ if sorterror_S='0' then
+ lastsuperburst_S <= superburst_S(mux2to1_gen_max)(0);
+ lasttimestamp_S <= timestamp_S(mux2to1_gen_max)(0);
+ sorterrorcount_S <= (others => '0');
+ sorterroroccured_S <= '0';
+ else
+ sorterroroccured_S <= '1';
+ if sorterrorcount_S(sorterrorcount_S'left)='0' then
+ sorterrorcount_S <= sorterrorcount_S+1;
+ else
+ lastsuperburst_S <= (others => '0');
+ lasttimestamp_S <= (others => '0');
+ sorterrorcount_S <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
end Behavioral;
-----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
--- Engineer: Peter Schakel
--- Create Date: 03-02-2012
--- Module Name: FEE_sorting_wavemux
--- Description: Multiplexer for FEE data, sorting on timestamp
--- Modifications:
--- 23-09-2014 single clock, remove fullness fifo,
--- 16-10-2014 inpipe signals
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.all;
-USE ieee.std_logic_arith.all;
-USE work.panda_package.all;
-
-----------------------------------------------------------------------------------
--- FEE_sorting_wavemux
--- Multiplexes multiple input pulse data stream with waveform data to one stream.
--- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check
--- The data is sorted based on the 32-bits timestamp.
--- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.
--- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
---
--- Library:
--- work.panda_package: constants and types
---
--- Generics:
+----------------------------------------------------------------------------------\r
+-- Company: KVI-cart/RUG/Groningen University\r
+-- Engineer: Peter Schakel\r
+-- Create Date: 03-02-2012\r
+-- Module Name: FEE_sorting_wavemux\r
+-- Description: Multiplexer for FEE data, sorting on timestamp\r
+-- Modifications:\r
+-- 23-09-2014 single clock, remove fullness fifo, \r
+-- 16-10-2014 inpipe signals \r
+-- 21-07-2015 data_out_inpipe clocked\r
+-- 23-10-2015 added available, improved response to delayed input data\r
+-- 15-04-2016 improved check on input buffer read delaytime (waittillend_S)\r
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+USE ieee.std_logic_unsigned.all;\r
+USE ieee.std_logic_arith.all;\r
+USE work.panda_package.all;\r
+\r
+----------------------------------------------------------------------------------\r
+-- FEE_sorting_wavemux\r
+-- Multiplexes multiple input pulse data stream with waveform data to one stream.\r
+-- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check\r
+-- The data is sorted based on the 32-bits timestamp.\r
+-- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.\r
+-- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.\r
+--\r
+-- Library:\r
+-- work.panda_package: constants and types\r
+--\r
+-- Generics:\r
-- NROFMUXINPUTS : number of input-channels\r
---
--- Inputs:
--- clock : clock
--- reset : reset, must be long enough for all clocks
--- data_in : array of input data streams, structure of each:
+--\r
+-- Inputs:\r
+-- clock : clock\r
+-- reset : reset, must be long enough for all clocks\r
+-- data_in : array of input data streams, structure of each:\r
-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
-- bits(35..32)="0001" : \r
-- bits(31..24) = statusbyte (bit6=overflow) \r
-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
--- data_in_write : write signal for data_in (write into fifo)
--- data_out_read : read signal for outgoing data (read from fifo)
---
--- Outputs:
--- data_in_allowed : write to input data allowed (not full)
--- data_in_almostfull : input fifo is too full for maximum length waveform
--- data_out : output data
--- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
--- bits(35..32)="0001" :
--- bits(31..24) = statusbyte (bit6=overflow)
--- bits(23..8) = 0
--- bits(7..0) = adcnumber (channel identification)
--- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
--- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
--- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- data_in_write : write signal for data_in (write into fifo)\r
+-- data_in_available : more data available in pipeline\r
+-- data_out_read : read signal for outgoing data (read from fifo)\r
+-- \r
+-- Outputs:\r
+-- data_in_allowed : write to input data allowed (not full)\r
+-- data_in_almostfull : input fifo is too full for maximum length waveform\r
+-- data_out : output data\r
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
+-- bits(35..32)="0001" : \r
+-- bits(31..24) = statusbyte (bit6=overflow) \r
+-- bits(23..8) = 0\r
+-- bits(7..0) = adcnumber (channel identification)\r
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
-- data_out_available : data_out available (output fifo not empty)\r
--- data_out_inpipe : more data on its way
--- error : data error, index in data words incorrect
---
+-- data_out_inpipe : more data on its way\r
+-- error : data error, index in data words incorrect\r
+-- \r
-- Components:\r
-- FEE_wavemux_readfifo : read data from fifo and writes to next level\r
-- FEE_wavemux2to1 : compares the data and passes the first in time on\r
--- sync_fifo_progfull364_progempty128_512x36 : synchronous fifo with programmable full and empty
--- sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through
---
---
---
-----------------------------------------------------------------------------------
-
-entity FEE_sorting_wavemux is
- generic(
- NROFMUXINPUTS : natural := 16
- );
- Port (
- clock : in std_logic;
- reset : in std_logic;
- data_in : in array_halfadc36bits_type;
- data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
- data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
- data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
- data_out : out std_logic_vector(35 downto 0);
- data_out_read : in std_logic;
- data_out_available : out std_logic;
- data_out_inpipe : out std_logic;
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0);
- testword1 : out std_logic_vector(35 downto 0)
-);
-end FEE_sorting_wavemux;
-
-
+-- sync_fifo_progfull364_progempty128_512x36 : synchronous fifo with programmable full and empty\r
+-- sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through\r
+--\r
+--\r
+--\r
+----------------------------------------------------------------------------------\r
+\r
+entity FEE_sorting_wavemux is\r
+ generic(\r
+ NROFMUXINPUTS : natural := 16\r
+ );\r
+ Port ( \r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ data_in : in array_halfadc36bits_type;\r
+ data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);\r
+ data_in_available : in std_logic_vector(0 to NROFMUXINPUTS-1);\r
+ data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);\r
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);\r
+ data_out : out std_logic_vector(35 downto 0);\r
+ data_out_read : in std_logic;\r
+ data_out_available : out std_logic;\r
+ data_out_inpipe : out std_logic;\r
+ error : out std_logic\r
+ );\r
+end FEE_sorting_wavemux;\r
+\r
+\r
architecture Behavioral of FEE_sorting_wavemux is\r
\r
component FEE_wavemux2to1 is\r
- generic(
- TIMEOUTBITS : natural := 6
- );
+ generic(\r
+ TIMEOUTBITS : natural := 8\r
+ );\r
Port (\r
- clock : in std_logic;
+ clock : in std_logic;\r
reset : in std_logic;\r
data1_in : in std_logic_vector(35 downto 0); \r
data1_in_write : in std_logic;\r
- data1_in_available : in std_logic;
+ data1_in_available : in std_logic;\r
data1_in_allowed : out std_logic;\r
data2_in : in std_logic_vector(35 downto 0); \r
data2_in_write : in std_logic;\r
- data2_in_available : in std_logic;
+ data2_in_available : in std_logic;\r
data2_in_allowed : out std_logic;\r
data_out : out std_logic_vector(35 downto 0);\r
data_out_write : out std_logic;\r
- data_out_available : out std_logic;
+ data_out_available : out std_logic;\r
data_out_allowed : in std_logic;\r
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)\r
+ error : out std_logic;\r
+ timeerror : out std_logic\r
);\r
-end component;
-\r
-component FEE_wavemux_readfifo is
- port (
- clock : in std_logic;
- reset : in std_logic;
- data_in : in std_logic_vector(35 downto 0);
- data_in_available : in std_logic;
+end component;\r
+\r
+component FEE_wavemux_readfifo is\r
+ port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ data_in : in std_logic_vector(35 downto 0);\r
+ data_in_available : in std_logic;\r
data_in_read : out std_logic;\r
- data_out : out std_logic_vector(35 downto 0);
- data_out_write : out std_logic;
- data_out_inpipe : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);\r
+ data_out_write : out std_logic;\r
+ data_out_inpipe : out std_logic;\r
data_out_allowed : in std_logic);\r
-end component;
-\r
-component sync_fifo_progfull364_progempty128_512x36
- port (
- rst : in std_logic;
- clk : in std_logic;
- din : in std_logic_vector(35 downto 0);
- wr_en : in std_logic;
- rd_en : in std_logic;
- dout : out std_logic_vector(35 downto 0);
- full : out std_logic;
- empty : out std_logic;
- prog_full : out std_logic;
- prog_empty : out std_logic);
-end component;
-\r
-component sync_fifo_FWFT_512x36
- port (
- rst : in std_logic;
- clk : in std_logic;
- din : in std_logic_vector(35 downto 0);
- wr_en : in std_logic;
- rd_en : in std_logic;
- dout : out std_logic_vector(35 downto 0);
- full : out std_logic;
- empty : out std_logic);
-end component;
-\r
-type twologarray_type is array(0 to 63) of natural;
-constant twologarray : twologarray_type :=
-(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
-
-constant mux2to1_gen_max : integer := twologarray(NROFMUXINPUTS); -- -1;
-constant INPIPE_DELAY : integer := 63;
-constant zeros : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-constant ones : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+end component;\r
+\r
+component sync_fifo_progfull364_progempty128_512x36\r
+ port (\r
+ srst : in std_logic;\r
+ clk : in std_logic;\r
+ din : in std_logic_vector(35 downto 0);\r
+ wr_en : in std_logic;\r
+ rd_en : in std_logic;\r
+ dout : out std_logic_vector(35 downto 0);\r
+ full : out std_logic;\r
+ empty : out std_logic;\r
+ prog_full : out std_logic;\r
+ prog_empty : out std_logic);\r
+end component;\r
+\r
+component sync_fifo_FWFT_512x36\r
+ port (\r
+ srst : in std_logic;\r
+ clk : in std_logic;\r
+ din : in std_logic_vector(35 downto 0);\r
+ wr_en : in std_logic;\r
+ rd_en : in std_logic;\r
+ dout : out std_logic_vector(35 downto 0);\r
+ full : out std_logic;\r
+ empty : out std_logic);\r
+end component;\r
+\r
+type twologarray_type is array(0 to 63) of natural;\r
+constant twologarray : twologarray_type :=\r
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);\r
+\r
+constant mux2to1_gen_max : integer := twologarray(NROFMUXINPUTS); -- -1;\r
+constant INPIPE_DELAY_BITS : integer := 8; -- 8;\r
+constant ZEROS : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+constant ONES : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');\r
\r
--type mux2to1_gen_type is array(0 to mux2to1_gen_max-1) of integer;\r
--constant mux2to1_gen : mux2to1_gen_type := (8,4,2,1);\r
\r
-type data_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);\r
-type singlebit_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic;\r
+type data_type_arr is array(0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);\r
+type data_type is array(0 to mux2to1_gen_max) of data_type_arr;\r
+type singlebit_type is array(0 to mux2to1_gen_max) of std_logic_vector(0 to NROFMUXINPUTS-1);\r
\r
signal error_S : std_logic := '0';\r
+signal reset_S : std_logic;\r
+signal timeout_counter_S : std_logic_vector (13 downto 0) := (others => '0');\r
\r
signal data_S : data_type;\r
-signal data_out_inpipe_S : singlebit_type := (others => (others => '0'));
-signal data_write_S : singlebit_type := (others => (others => '0'));
-signal data_allowed_S : singlebit_type := (others => (others => '0'));
+signal data_out_inpipe_S : singlebit_type := (others => (others => '0'));\r
+signal data_write_S : singlebit_type := (others => (others => '0'));\r
+signal data_allowed_S : singlebit_type := (others => (others => '0'));\r
signal error_array_S : singlebit_type := (others => (others => '0'));\r
+signal timeerror_array_S : singlebit_type := (others => (others => '0'));\r
+\r
+-- signals for fifo from adc-fe to adc-mux\r
+signal dfifo_wr_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal dfifo_rd_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal dfifo_out_S : array_halfadc36bits_type := (others => (others => '0'));\r
+signal dfifo_full_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal dfifo_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal data_in_available_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal dfifo_prog_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal waittillend_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal data_in_almostfull_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal timedifflargeinout_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal norecentdfiforead_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
\r
--- signals for fifo from adc-fe to adc-mux
-signal dfifo_wr_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_rd_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_out_S : array_halfadc36bits_type := (others => (others => '0'));
-signal dfifo_full_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal data_in_available_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_prog_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-
-signal delay_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal read36_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-
--- signals for fifo from adc-mux to packet-composer
+signal delay_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal read36_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal read36_allowed_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+\r
+-- signals for fifo from adc-mux to packet-composer\r
signal tfifo_in_S : std_logic_vector (35 downto 0);\r
-signal tfifo_rd_S : std_logic := '0';
-signal tfifo_full_S : std_logic := '0';
-signal tfifo_empty_S : std_logic := '0';
+signal tfifo_write_S : std_logic := '0';\r
+signal tfifo_rd_S : std_logic := '0';\r
+signal tfifo_full_S : std_logic := '0';\r
+signal tfifo_empty_S : std_logic := '0';\r
+\r
+-- signals for timecheck\r
+signal prev_data0_S : std_logic_vector (35 downto 0) := (others => '0');\r
+signal timeerror_S : std_logic := '0';\r
+signal inputerror_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal fifoinerror_S : std_logic := '0';\r
+ \r
+signal data0_S : array_halfadc36bits_type;\r
+-- attribute mark_debug : string;\r
+-- attribute mark_debug of timeerror_S : signal is "true";\r
+-- attribute mark_debug of inputerror_S : signal is "true";\r
+-- attribute mark_debug of fifoinerror_S : signal is "true";\r
+-- attribute mark_debug of tfifo_in_S : signal is "true";\r
+-- attribute mark_debug of tfifo_write_S : signal is "true";\r
+-- attribute mark_debug of tfifo_full_S : signal is "true";\r
+-- attribute mark_debug of tfifo_empty_S : signal is "true";\r
+-- attribute mark_debug of dfifo_full_S : signal is "true";\r
+-- attribute mark_debug of dfifo_empty_S : signal is "true";\r
+-- attribute mark_debug of data_in_available_S : signal is "true";\r
+-- attribute mark_debug of dfifo_rd_S : signal is "true";\r
+-- attribute mark_debug of data_in_write : signal is "true";\r
+-- attribute mark_debug of data_in_available : signal is "true";\r
+-- attribute mark_debug of dfifo_prog_empty_S : signal is "true";\r
+-- attribute mark_debug of waittillend_S : signal is "true";\r
+-- attribute mark_debug of data_in_almostfull_S : signal is "true";\r
+-- attribute mark_debug of timedifflargeinout_S : signal is "true";\r
+-- attribute mark_debug of delay_inpipe_S : signal is "true";\r
+-- attribute mark_debug of read36_inpipe_S : signal is "true";\r
+-- attribute mark_debug of read36_allowed_S : signal is "true";\r
+-- attribute mark_debug of error_array_S : signal is "true";\r
+-- attribute mark_debug of data0_S : signal is "true";\r
+\r
+begin\r
+\r
+process(clock)\r
+begin\r
+ if (rising_edge(clock)) then \r
+ if (dfifo_empty_S/=ONES(0 to NROFMUXINPUTS-1)) \r
+ or (tfifo_empty_S='0') \r
+ or (data_out_inpipe_S(mux2to1_gen_max)(0)='1') \r
+ then\r
+ data_out_inpipe <= '1'; --//\r
+ else\r
+ data_out_inpipe <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
\r
-type testword_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector (35 downto 0);\r
-signal testword0_S : testword_type;\r
+FEE_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate \r
\r
-begin
-
-data_out_inpipe <= '1' \r
- when (dfifo_empty_S/=ones(0 to NROFMUXINPUTS-1)) or (tfifo_empty_S='0') or (data_out_inpipe_S(mux2to1_gen_max,0)='1')\r
+timedifflargeinout_S(index) <= '1' when\r
+ ((data_in(index)(31 downto 16)>data_S(0)(index)(31 downto 16)) and (data_in(index)(31 downto 16)-data_S(0)(index)(31 downto 16)>1)) or\r
+ ((data_in(index)(31 downto 16)<data_S(0)(index)(31 downto 16)) and (data_S(0)(index)(31 downto 16)-data_in(index)(31 downto 16)<x"ffff"))\r
else '0';\r
-
-FEE_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate
-
-process(clock)
-type inpipe_counter_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to INPIPE_DELAY;
-variable inpipe_counter_V : inpipe_counter_type := (others => 0);
-variable index_other : integer range 0 to NROFMUXINPUTS-1;
-begin
- if rising_edge(clock) then
- if reset='1' then
- inpipe_counter_V(index) := 0;
- delay_inpipe_S(index) <= '0';
- else
- index_other := conv_integer(unsigned((conv_std_logic_vector(index,8) xor x"01")));
- if ((dfifo_wr_S(index)='1') and (dfifo_prog_empty_S(index)='1')) or
- ((dfifo_wr_S(index_other)='1') and (dfifo_prog_empty_S(index_other)='1'))
- then
- inpipe_counter_V(index) := INPIPE_DELAY;
- delay_inpipe_S(index) <= '1';
- else
- if inpipe_counter_V(index)/=0 then
- inpipe_counter_V(index) := inpipe_counter_V(index)-1;
- delay_inpipe_S(index) <= '1';
- else
- delay_inpipe_S(index) <= '0';
- end if;
- end if;
- end if;
- end if;
-end process;
-
-
-dfifo: sync_fifo_progfull364_progempty128_512x36 port map(
- rst => reset,
- clk => clock,
- din => data_in(index),
- wr_en => dfifo_wr_S(index),
- rd_en => dfifo_rd_S(index),
- dout => dfifo_out_S(index),
- full => dfifo_full_S(index),
- empty => dfifo_empty_S(index),
- prog_full => data_in_almostfull(index),
- prog_empty => dfifo_prog_empty_S(index));
-
- dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
-data_in_allowed(index) <= NOT dfifo_full_S(index);
+\r
+process(clock)\r
+variable delaycount_V : std_logic_vector(INPIPE_DELAY_BITS downto 0) := (others => '0');\r
+begin\r
+ if rising_edge(clock) then\r
+ if (dfifo_wr_S(index)='1') and (data_in(index)(35 downto 32)="0000") and (dfifo_prog_empty_S(index)='1') and (norecentdfiforead_S(index)='0')\r
+ and ((timedifflargeinout_S(index)='0') or (data_S(0)(index)(35 downto 32)/="0000"))\r
+ then\r
+ waittillend_S(index) <= '1';\r
+ delaycount_V := (others => '0');\r
+ elsif delaycount_V(INPIPE_DELAY_BITS)='0' then\r
+ delaycount_V := delaycount_V+1;\r
+ waittillend_S(index) <= '1';\r
+ else\r
+ waittillend_S(index) <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+process(clock)\r
+variable delaycount_V : std_logic_vector(INPIPE_DELAY_BITS downto 0) := (others => '0');\r
+begin\r
+ if rising_edge(clock) then\r
+ norecentdfiforead_S(index) <= '0';\r
+ if (data_write_S(0)(index)='1') or (data_allowed_S(0)(index)='0') then \r
+ delaycount_V := (others => '0');\r
+ else\r
+ if (data_S(0)(index)(35 downto 32)="0000") then\r
+ if delaycount_V(delaycount_V'left)='0' then\r
+ delaycount_V := delaycount_V+1;\r
+ else\r
+ norecentdfiforead_S(index) <= '1';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+\r
+dfifo: sync_fifo_progfull364_progempty128_512x36 port map(\r
+ srst => reset,\r
+ clk => clock,\r
+ din => data_in(index),\r
+ wr_en => dfifo_wr_S(index),\r
+ rd_en => dfifo_rd_S(index),\r
+ dout => dfifo_out_S(index),\r
+ full => dfifo_full_S(index),\r
+ empty => dfifo_empty_S(index),\r
+ prog_full => data_in_almostfull_S(index),\r
+ prog_empty => dfifo_prog_empty_S(index));\r
+\r
+ dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';\r
+data_in_allowed(index) <= NOT dfifo_full_S(index);\r
+data_in_almostfull(index) <= data_in_almostfull_S(index);\r
\r
data_in_available_S(index) <= '1' when dfifo_empty_S(index)='0' else '0';\r
\r
-FEE_wavemux_readfifo1: FEE_wavemux_readfifo port map(
- clock => clock,
- reset => reset,
- data_in => dfifo_out_S(index),
- data_in_available => data_in_available_S(index),
+FEE_wavemux_readfifo1: FEE_wavemux_readfifo port map(\r
+ clock => clock,\r
+ reset => reset,\r
+ data_in => dfifo_out_S(index),\r
+ data_in_available => data_in_available_S(index),\r
data_in_read => dfifo_rd_S(index),\r
- data_out => data_S(0,index),
- data_out_write => data_write_S(0,index),
- data_out_inpipe => read36_inpipe_S(index),
- data_out_allowed => data_allowed_S(0,index));\r
-
-process(data_out_inpipe_S(0,index),read36_inpipe_S(index),delay_inpipe_S(index),dfifo_wr_S(index)) -- ,dfifo_prog_empty_S)
---variable index_other : integer range 0 to NROFMUXINPUTS-1;
-begin
--- index_other := conv_integer(unsigned((conv_std_logic_vector(index,16) xor x"0001")));
--- if (read36_inpipe_S(index)='1') or ((dfifo_prog_empty_S(index_other)='1') and (delay_inpipe_S(index)='1')) or
--- (dfifo_wr_occuredrecently_S(index)='1') or -- was there a write recently (time: one datapacket plus a few slowcontrols ?
- if (read36_inpipe_S(index)='1') or (delay_inpipe_S(index)='1') or
- (dfifo_wr_S(index)='1') then
- data_out_inpipe_S(0,index) <= '1';
- else
- data_out_inpipe_S(0,index) <= '0';
- end if;
-end process;
-
+ data_out => data_S(0)(index),\r
+ data_out_write => data_write_S(0)(index),\r
+ data_out_inpipe => read36_inpipe_S(index),\r
+ data_out_allowed => read36_allowed_S(index));\r
+read36_allowed_S(index) <= '1' when (data_allowed_S(0)(index)='1') and \r
+ ((waittillend_S(index)='0') or (data_S(0)(index)(35 downto 32)/="0000")) else '0';\r
+\r
+data0_S(index) <= data_S(0)(index);\r
+\r
+data_out_inpipe_S(0)(index) <= '1' when (data_in_available(index)='1') or (read36_inpipe_S(index)='1') else '0'; -- or (delay_inpipe_S(index)='1') else '0';\r
+ \r
end generate;\r
\r
\r
FEE_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate \r
\r
- FEE_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate
+ FEE_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate \r
\r
- FEE_wavemux2to1_1: FEE_wavemux2to1 port map(\r
- clock => clock,
- reset => reset,
- data1_in => data_S(i1,i2*2),\r
- data1_in_write => data_write_S(i1,i2*2),\r
- data1_in_available => data_out_inpipe_S(i1,i2*2),
- data1_in_allowed => data_allowed_S(i1,i2*2),\r
- data2_in => data_S(i1,i2*2+1),\r
- data2_in_write => data_write_S(i1,i2*2+1),\r
- data2_in_available => data_out_inpipe_S(i1,i2*2+1),
- data2_in_allowed => data_allowed_S(i1,i2*2+1),\r
- data_out => data_S(i1+1,i2),\r
- data_out_write => data_write_S(i1+1,i2),\r
- data_out_available => data_out_inpipe_S(i1+1,i2),
- data_out_allowed => data_allowed_S(i1+1,i2),\r
- error => error_array_S(i1,i2),
- testword0 => testword0_S(i1,i2));\r
+ FEE_wavemux2to1_1: FEE_wavemux2to1 \r
+ generic map(\r
+ TIMEOUTBITS => 11\r
+ ) \r
+ port map(\r
+ clock => clock,\r
+ reset => reset_S,\r
+ data1_in => data_S(i1)(i2*2),\r
+ data1_in_write => data_write_S(i1)(i2*2),\r
+ data1_in_available => data_out_inpipe_S(i1)(i2*2),\r
+ data1_in_allowed => data_allowed_S(i1)(i2*2),\r
+ data2_in => data_S(i1)(i2*2+1),\r
+ data2_in_write => data_write_S(i1)(i2*2+1),\r
+ data2_in_available => data_out_inpipe_S(i1)(i2*2+1),\r
+ data2_in_allowed => data_allowed_S(i1)(i2*2+1),\r
+ data_out => data_S(i1+1)(i2),\r
+ data_out_write => data_write_S(i1+1)(i2),\r
+ data_out_available => data_out_inpipe_S(i1+1)(i2),\r
+ data_out_allowed => data_allowed_S(i1+1)(i2),\r
+ error => error_array_S(i1)(i2),\r
+ timeerror => timeerror_array_S(i1)(i2));\r
\r
end generate;\r
end generate;\r
\r
process(clock)\r
-begin
+begin\r
if (rising_edge(clock)) then \r
error_S <= '0';\r
for i1 in 0 to mux2to1_gen_max-1 loop \r
- for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop
- if error_array_S(i1,i2)='1' then\r
+ for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop \r
+ if error_array_S(i1)(i2)='1' then\r
error_S <= '1';\r
end if;\r
end loop;\r
end loop;\r
end if;\r
-end process;
+end process;\r
error <= error_S;\r
\r
-data_allowed_S(mux2to1_gen_max,0) <= '1' when (tfifo_full_S='0') else '0';\r
-tfifo_in_S <= data_S(mux2to1_gen_max,0);
-tfifo: sync_fifo_FWFT_512x36 port map(
- rst => reset,
- clk => clock,
- din => tfifo_in_S,
- wr_en => data_write_S(mux2to1_gen_max,0),
- rd_en => tfifo_rd_S,
- dout => data_out,
- full => tfifo_full_S,
- empty => tfifo_empty_S);
-
+data_allowed_S(mux2to1_gen_max)(0) <= '1' when (tfifo_full_S='0') else '0';\r
+tfifo_in_S <= data_S(mux2to1_gen_max)(0);\r
+tfifo: sync_fifo_FWFT_512x36 port map(\r
+ srst => reset,\r
+ clk => clock,\r
+ din => tfifo_in_S,\r
+ wr_en => tfifo_write_S,\r
+ rd_en => tfifo_rd_S,\r
+ dout => data_out,\r
+ full => tfifo_full_S,\r
+ empty => tfifo_empty_S);\r
+tfifo_write_S <= data_write_S(mux2to1_gen_max)(0);\r
tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';\r
data_out_available <= '1' when tfifo_empty_S='0' else '0';\r
\r
-
-testword0 <= (others => '0');
-testword1 <= (others => '0');
+process(clock)\r
+begin\r
+ if (rising_edge(clock)) then\r
+ if (tfifo_write_S='1') or (tfifo_full_S='1') or (dfifo_empty_S=ONES) or (timeout_counter_S(timeout_counter_S'left)='1') then\r
+ timeout_counter_S <= (others => '0');\r
+ else\r
+ timeout_counter_S <= timeout_counter_S+1;\r
+ end if;\r
+ end if;\r
+end process;\r
+reset_S <= '1' when (reset='1') or (timeout_counter_S(timeout_counter_S'left)='1') else '0';\r
+\r
+\r
+process(clock)\r
+variable time_counter_V : integer range 0 to 2047 := 0;\r
+begin\r
+ if (rising_edge(clock)) then \r
+ timeerror_S <= '0';\r
+ if data_write_S(mux2to1_gen_max)(0)='1' then\r
+ if tfifo_in_S(35 downto 32)="0000" then\r
+ if tfifo_in_S(31 downto 16)=prev_data0_S(31 downto 16) then\r
+ if tfifo_in_S(15 downto 0)<prev_data0_S(15 downto 0) then\r
+ timeerror_S <= '1';\r
+ end if;\r
+ elsif tfifo_in_S(31 downto 16)<prev_data0_S(31 downto 16) then\r
+ if tfifo_in_S(31 downto 30)="00" and prev_data0_S(31 downto 30)="11" then\r
+ else\r
+ if time_counter_V<2000 then\r
+ timeerror_S <= '1';\r
+ end if;\r
+ end if;\r
+ elsif tfifo_in_S(31 downto 16)>prev_data0_S(31 downto 16) then\r
+ if tfifo_in_S(31 downto 30)="11" and prev_data0_S(31 downto 30)="00" then\r
+ if time_counter_V<2000 then\r
+ timeerror_S <= '1';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ time_counter_V := 0;\r
+ prev_data0_S <= tfifo_in_S;\r
+ end if;\r
+ else\r
+ time_counter_V := time_counter_V+1;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+process(clock)\r
+variable prevdata_V : std_logic_vector(3 downto 0) := "0000";\r
+begin\r
+ if (rising_edge(clock)) then \r
+ fifoinerror_S <= '0';\r
+ if tfifo_write_S='1' then\r
+ if (tfifo_in_S(35 downto 32)="0000") then\r
+ if (prevdata_V(3 downto 1)/="010") then fifoinerror_S <= '1'; end if;\r
+ elsif (tfifo_in_S(35 downto 32)="0001") then\r
+ if (prevdata_V/="0000") then fifoinerror_S <= '1'; end if;\r
+ elsif (tfifo_in_S(35 downto 32)="0010") then\r
+ if (prevdata_V/="0010") and (prevdata_V/="0001") then fifoinerror_S <= '1'; end if;\r
+ elsif (tfifo_in_S(35 downto 32)="0100") then\r
+ if (prevdata_V/="0010") then fifoinerror_S <= '1'; end if;\r
+ elsif (tfifo_in_S(35 downto 32)="0101") then \r
+ if (prevdata_V/="0010") then fifoinerror_S <= '1'; end if;\r
+ else\r
+ fifoinerror_S <= '1';\r
+ end if;\r
+ prevdata_V := tfifo_in_S(35 downto 32);\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+\r
+geninerrors: for i in 0 to NROFMUXINPUTS-1 generate\r
+process(clock)\r
+variable prevdata_V : std_logic_vector(3 downto 0) := "0000";\r
+begin\r
+ if (rising_edge(clock)) then \r
+ inputerror_S(i) <= '0';\r
+ if data_write_S(0)(i)='1' then\r
+ if (data_S(0)(i)(35 downto 32)="0000") then\r
+ if (prevdata_V(3 downto 1)/="010") then inputerror_S(i) <= '1'; end if;\r
+ elsif (data_S(0)(i)(35 downto 32)="0001") then\r
+ if (prevdata_V/="0000") then inputerror_S(i) <= '1'; end if;\r
+ elsif (data_S(0)(i)(35 downto 32)="0010") then\r
+ if (prevdata_V/="0010") and (prevdata_V/="0001") then inputerror_S(i) <= '1'; end if;\r
+ elsif (data_S(0)(i)(35 downto 32)="0100") then\r
+ if (prevdata_V/="0010") then inputerror_S(i) <= '1'; end if;\r
+ elsif (data_S(0)(i)(35 downto 32)="0101") then \r
+ if (prevdata_V/="0010") then inputerror_S(i) <= '1'; end if;\r
+ else\r
+ inputerror_S(i) <= '1';\r
+ end if;\r
+ prevdata_V := data_S(0)(i)(35 downto 32);\r
+ end if;\r
+ end if;\r
+end process;\r
+end generate;\r
+\r
+\r
+end Behavioral;\r
\r
-
-end Behavioral;
-
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 13-01-2017
+-- Module Name: FEE_transmit_combine
+-- Description: Combine data from two FPGAs to one data stream
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_transmit_combine
+-- Combine data from two FPGAs to one data stream.
+-- The data consist of hits, waveform or slow control.
+-- The hits and the waveforms are time ordered.
+--
+--
+-- The resulting data packets : 4 32-bit words, with CRC8 in last word
+-- 0xDA ADCnumber(7..0) superburstnumber(15..0)
+-- timestamp(15..0) energy(15..0)
+-- CF_before(15..0) CF_after(15..0)
+-- 0000 statusbyte(7..0) CRC8(7..0)
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+-- 0x5C address(7..0) replybit 0000000 data(31..24)
+-- data(23..0) CRC8(7..0)
+--
+-- The waveform packets : 32-bit words, with CRC8 in last word
+-- 0xAF ADCnumber(7..0) superburstnumber(15..0)
+-- timestamp(15..0) 0x00 statusbyte(7..0)
+-- 0 adc0(14..0) 0 adc1(14..0) : 2 adc-samples 15 bits signed
+-- 0 adc2(14..0) 0 adc3(14..0) : next 2 adc-samples 15 bits signed
+-- .........
+-- 1 adcn(14..0) 1 00 CRC8(7..0) : last 32-bit word: last adc-sample 15 bits signed
+-- or
+-- 0 0000 1 00 CRC8(7..0) : last 32-bit word: no sample--
+--
+--
+-- Library
+-- work.panda_package : for type declarations and constants
+--
+-- Generics:
+--
+-- Inputs:
+-- clock_local : clock for Feature Extraction in the same FPGA
+-- clock_remote : clock for Feature Extraction in the other FPGA
+-- clock_out : clock for output data
+-- reset : reset all
+-- GEO : indicates which FPGA, 0:this is FPGA1, 1:this is FPGA2
+-- data_local : data from local FE
+-- data_local_first : indicates first 32-bits data word in packet from local FE
+-- data_local_last : indicates last 32-bits data word in packet from local FE
+-- data_local_write : write signal for data from local FE
+-- data_local_inpipe : more data on its way from local FE
+-- data_remote : data from remote FE
+-- data_remote_first : indicates first 32-bits data word in packet from remote FE
+-- data_remote_last : indicates last 32-bits data word in packet from remote FE
+-- data_remote_write : write signal for data from remote FE
+-- data_remote_inpipe : more data on its way from remote FE
+-- data_out_fifofull : full signal from fifo connected to the output
+--
+-- Outputs:
+-- data_local_fifofull : input fifo for local data is full
+-- data_remote_fifofull : input fifo for remote data is full
+-- data_out : data to fiber module
+-- data_out_first : first 32-bit data word of a packet
+-- data_out_last : last 32-bit data word of a packet
+-- data_out_write : write signal for output data
+-- error : errors occurred: adjust with other FE instances for comparison
+--
+-- Components:
+-- async_progfull192_progempty128_fifo_256x34 : fifo to buffer data from local and remote FPGA
+--
+----------------------------------------------------------------------------------
+
+entity FEE_transmit_combine is
+ port (
+ clock_local : in std_logic;
+ clock_remote : in std_logic;
+ clock_out : in std_logic;
+ reset : in std_logic;
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+ enable_waveform : in std_logic;
+ data_local : in std_logic_vector (31 downto 0);
+ data_local_first : in std_logic;
+ data_local_last : in std_logic;
+ data_local_write : in std_logic;
+ data_local_inpipe : in std_logic;
+ data_local_fifofull : out std_logic;
+ data_remote : in std_logic_vector(31 downto 0);
+ data_remote_first : in std_logic;
+ data_remote_last : in std_logic;
+ data_remote_write : in std_logic;
+ data_remote_inpipe : in std_logic;
+ data_remote_fifofull : out std_logic;
+ data_remote_almostfull : out std_logic;
+ data_out : out std_logic_vector(31 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_fifofull : in std_logic;
+ error : out std_logic
+ );
+end FEE_transmit_combine;
+
+architecture Behavioral of FEE_transmit_combine is
+
+component async_progfull448_progempty128_fifo_512x34
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(33 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(33 downto 0);
+ full : out std_logic;
+ empty : out std_logic;
+ prog_full : out std_logic;
+ prog_empty : out std_logic);
+end component;
+
+type data_type is (NONE,HITDATA,SLOWCONTROL,WAVEFORM);
+signal fifo_local_progfull_S : std_logic;
+signal data_local_write_S : std_logic;
+signal errorin_local_S : std_logic;
+
+signal data_remote_write_S : std_logic;
+signal errorin_remote_S : std_logic;
+
+signal data_local_inpipe_S : std_logic;
+signal fifo_local_empty_S : std_logic;
+signal data_local_read_S : std_logic;
+signal fifo_local_read_aftr1clk_S : std_logic;
+signal data_local_S : std_logic_vector (31 downto 0);
+signal data_local_first_S : std_logic;
+signal data_local_last_S : std_logic;
+signal header_local_hits0_S : std_logic_vector (31 downto 0);
+signal header_local_hits1_S : std_logic_vector (31 downto 0);
+signal data_local_type_S : data_type;
+signal data_local_count_S : integer range 0 to 255 := 0;
+
+signal data_remote_inpipe_S : std_logic;
+signal fifo_remote_empty_S : std_logic;
+signal data_remote_read_S : std_logic;
+signal fifo_remote_read_aftr1clk_S : std_logic;
+signal data_remote_S : std_logic_vector (31 downto 0);
+signal data_remote_first_S : std_logic;
+signal data_remote_last_S : std_logic;
+signal header_remote_hits0_S : std_logic_vector (31 downto 0);
+signal header_remote_hits1_S : std_logic_vector (31 downto 0);
+signal data_remote_type_S : data_type;
+signal data_remote_count_S : integer range 0 to 255 := 0;
+
+type writemode_type is (WAITNEXT,LOCALSLOWCONTROL,REMOTESLOWCONTROL,LOCALHITS0,LOCALHITS1,LOCALHITS2,
+ REMOTEHITS0,REMOTEHITS1,REMOTEHITS2,LOCALWAVES0,LOCALWAVES1,REMOTEWAVES0,REMOTEWAVES1);
+signal writemode_S : writemode_type := WAITNEXT;
+signal timeoutcount_S : std_logic_vector (9 downto 0);
+signal errorout_S : std_logic;
+signal data_out_S : std_logic_vector (31 downto 0);
+signal data_out_write_S : std_logic;
+signal data_out_first_S : std_logic;
+signal data_out_last_S : std_logic;
+
+signal data_out_saved_S : std_logic_vector (31 downto 0);
+signal data_out_save_S : std_logic := '0';
+signal data_out_saved_first_S : std_logic;
+signal data_out_saved_last_S : std_logic;
+
+
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of errorout_S : signal is "true";
+-- attribute mark_debug of enable_waveform : signal is "true";
+-- attribute mark_debug of data_local : signal is "true";
+-- attribute mark_debug of data_local_first : signal is "true";
+-- attribute mark_debug of data_local_last : signal is "true";
+-- attribute mark_debug of data_local_write : signal is "true";
+-- attribute mark_debug of data_local_inpipe : signal is "true";
+-- attribute mark_debug of data_local_fifofull : signal is "true";
+-- attribute mark_debug of fifo_local_empty_S : signal is "true";
+-- attribute mark_debug of data_remote : signal is "true";
+-- attribute mark_debug of data_remote_first : signal is "true";
+-- attribute mark_debug of data_remote_last : signal is "true";
+-- attribute mark_debug of data_remote_write : signal is "true";
+-- attribute mark_debug of data_remote_inpipe : signal is "true";
+-- attribute mark_debug of data_remote_fifofull : signal is "true";
+-- attribute mark_debug of fifo_remote_empty_S : signal is "true";
+-- attribute mark_debug of data_remote_almostfull : signal is "true";
+-- attribute mark_debug of data_out : signal is "true";
+-- attribute mark_debug of data_out_first : signal is "true";
+-- attribute mark_debug of data_out_last : signal is "true";
+-- attribute mark_debug of data_out_write : signal is "true";
+-- attribute mark_debug of data_out_inpipe : signal is "true";
+-- attribute mark_debug of data_out_fifofull : signal is "true";
+-- attribute mark_debug of writemode_S : signal is "true";
+-- attribute mark_debug of data_local_count_S : signal is "true";
+-- attribute mark_debug of data_remote_count_S : signal is "true";
+
+
+begin
+
+error <= '1' when (errorout_S='1') or (errorin_local_S='1') or (errorin_remote_S='1') else '0';
+data_out_inpipe <= '1' when (data_local_inpipe_S='1') or (data_remote_inpipe_S='1') or (writemode_S/=WAITNEXT) or
+ (fifo_local_empty_S='0') or (fifo_remote_empty_S='0') else '0';
+data_out <= data_out_S when (data_out_save_S='0') else data_out_saved_S;
+data_out_write <= '1' when (data_out_write_S='1') and (data_out_fifofull='0') else '0';
+data_out_first <= data_out_first_S when (data_out_save_S='0') else data_out_saved_first_S;
+data_out_last <= data_out_last_S when (data_out_save_S='0') else data_out_saved_last_S;
+
+
+fifo_local: async_progfull448_progempty128_fifo_512x34 port map(
+ rst => reset,
+ wr_clk => clock_local,
+ rd_clk => clock_out,
+ din(33) => data_local_first,
+ din(32) => data_local_last,
+ din(31 downto 0) => data_local,
+ wr_en => data_local_write,
+ rd_en => data_local_read_S,
+ dout(33) => data_local_first_S,
+ dout(32) => data_local_last_S,
+ dout(31 downto 0) => data_local_S,
+ full => data_local_fifofull,
+ empty => fifo_local_empty_S,
+ prog_full => fifo_local_progfull_S,
+ prog_empty => open);
+
+fifo_remote_hits: async_progfull448_progempty128_fifo_512x34 port map(
+ rst => reset,
+ wr_clk => clock_remote,
+ rd_clk => clock_out,
+ din(33) => data_remote_first,
+ din(32) => data_remote_last,
+ din(31 downto 0) => data_remote,
+ wr_en => data_remote_write,
+ rd_en => data_remote_read_S,
+ dout(33) => data_remote_first_S,
+ dout(32) => data_remote_last_S,
+ dout(31 downto 0) => data_remote_S,
+ full => data_remote_fifofull,
+ empty => fifo_remote_empty_S,
+ prog_full => data_remote_almostfull,
+ prog_empty => open);
+
+
+process(clock_out)
+begin
+ if (rising_edge(clock_out)) then
+ data_local_inpipe_S <= data_local_inpipe;
+ data_remote_inpipe_S <= data_remote_inpipe;
+ end if;
+end process;
+
+
+data_local_read_S <= '1' when ((fifo_local_empty_S='0') and (data_out_fifofull='0') and (data_out_save_S='0')) and
+ (((data_local_count_S=0) or ((data_local_count_S=1) and (fifo_local_read_aftr1clk_S='0'))) or
+ (((writemode_S=LOCALHITS0) or (writemode_S=LOCALHITS1) or ((writemode_S=LOCALHITS2) and (fifo_local_read_aftr1clk_S='0'))) or
+ ((writemode_S=LOCALWAVES0) or ((writemode_S=LOCALWAVES1) and (data_local_last_S='0')))))
+ else '0';
+
+data_remote_read_S <= '1' when ((fifo_remote_empty_S='0') and (data_out_fifofull='0') and (data_out_save_S='0')) and
+ (((data_remote_count_S=0) or ((data_remote_count_S=1) and (fifo_remote_read_aftr1clk_S='0'))) or
+ (((writemode_S=REMOTEHITS0) or (writemode_S=REMOTEHITS1) or ((writemode_S=REMOTEHITS2) and (fifo_remote_read_aftr1clk_S='0'))) or
+ ((writemode_S=REMOTEWAVES0) or ((writemode_S=REMOTEWAVES1) and (data_remote_last_S='0'))))) else '0';
+
+process(clock_out)
+variable local_timestamp_V : std_logic_vector(31 downto 0);
+variable remote_timestamp_V : std_logic_vector(31 downto 0);
+begin
+ if (rising_edge(clock_out)) then
+ errorout_S <= '0';
+ data_out_write_S <= '0';
+ data_out_first_S <= '0';
+ data_out_last_S <= '0';
+ if (data_out_write_S='1') and (data_out_fifofull='1') then
+ data_out_write_S <= '1';
+ data_out_first_S <= data_out_first_S;
+ data_out_last_S <= data_out_last_S;
+ if (fifo_local_read_aftr1clk_S='1') or (fifo_remote_read_aftr1clk_S='1') then
+ data_out_save_S <= '1';
+ data_out_saved_S <= data_out_S;
+ data_out_saved_first_S <= data_out_first_S;
+ data_out_saved_last_S <= data_out_last_S;
+ end if;
+ elsif data_out_save_S='1' then
+ data_out_write_S <= '1';
+ data_out_save_S <= '0';
+ data_out_first_S <= data_out_first_S;
+ data_out_last_S <= data_out_last_S;
+ end if;
+ if (fifo_local_read_aftr1clk_S='1') then
+ if data_local_first_S='1' then
+ header_local_hits0_S <= data_local_S;
+ data_local_count_S <= 1;
+ if data_local_S(31 downto 24)=x"5c" then
+ data_local_type_S <= SLOWCONTROL;
+ elsif data_local_S(31 downto 24)=x"da" then
+ data_local_type_S <= HITDATA;
+ elsif data_local_S(31 downto 24)=x"af" then
+ data_local_type_S <= WAVEFORM;
+ else
+ data_local_type_S <= NONE;
+ data_local_count_S <= 0;
+ errorout_S <= '1';
+ end if;
+ elsif data_local_count_S=0 then
+ errorout_S <= '1';
+ elsif data_local_count_S=1 then
+ header_local_hits1_S <= data_local_S;
+ data_local_count_S <= data_local_count_S+1;
+ elsif data_local_count_S>1 then
+ data_local_count_S <= data_local_count_S+1;
+ end if;
+ end if;
+ if (fifo_remote_read_aftr1clk_S='1') then
+ if data_remote_first_S='1' then
+ header_remote_hits0_S <= data_remote_S;
+ data_remote_count_S <= 1;
+ if data_remote_S(31 downto 24)=x"5c" then
+ data_remote_type_S <= SLOWCONTROL;
+ elsif data_remote_S(31 downto 24)=x"da" then
+ data_remote_type_S <= HITDATA;
+ elsif data_remote_S(31 downto 24)=x"af" then
+ data_remote_type_S <= WAVEFORM;
+ else
+ data_remote_type_S <= NONE;
+ data_remote_count_S <= 0;
+ errorout_S <= '1';
+ end if;
+ elsif data_remote_count_S=0 then
+ errorout_S <= '1';
+ elsif data_remote_count_S=1 then
+ header_remote_hits1_S <= data_remote_S;
+ data_remote_count_S <= data_remote_count_S+1;
+ elsif data_remote_count_S>1 then
+ data_remote_count_S <= data_remote_count_S+1;
+ end if;
+ end if;
+
+ if (data_out_save_S='1') or ((data_out_fifofull='1') and (writemode_S=WAITNEXT)) then
+ else
+ case writemode_S is
+ when LOCALSLOWCONTROL =>
+ data_out_S <= header_local_hits1_S;
+ data_out_last_S <= '1';
+ data_out_write_S <= '1';
+ data_local_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ when REMOTESLOWCONTROL =>
+ data_out_S <= header_remote_hits1_S;
+ data_out_last_S <= '1';
+ data_out_write_S <= '1';
+ data_remote_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ when LOCALHITS0 =>
+ data_out_S <= header_local_hits1_S;
+ data_out_write_S <= not enable_waveform;
+ writemode_S <= LOCALHITS1;
+ when LOCALHITS1 =>
+ if (fifo_local_read_aftr1clk_S='1') then
+ data_out_S <= data_local_S;
+ data_out_write_S <= not enable_waveform;
+ writemode_S <= LOCALHITS2;
+ else
+ if timeoutcount_S(timeoutcount_S'left)='0' then
+ if data_out_fifofull='0' then
+ timeoutcount_S <= timeoutcount_S+1;
+ end if;
+ else
+ timeoutcount_S <= (others => '0');
+ errorout_S <= '1';
+ data_local_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ end if;
+ end if;
+ when LOCALHITS2 =>
+ if (fifo_local_read_aftr1clk_S='1') then
+ data_out_S <= data_local_S;
+ data_out_write_S <= not enable_waveform;
+ data_out_last_S <= '1';
+ data_local_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ else
+ if timeoutcount_S(timeoutcount_S'left)='0' then
+ if data_out_fifofull='0' then
+ timeoutcount_S <= timeoutcount_S+1;
+ end if;
+ else
+ timeoutcount_S <= (others => '0');
+ errorout_S <= '1';
+ data_local_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ end if;
+ end if;
+ when REMOTEHITS0 =>
+ data_out_S <= header_remote_hits1_S;
+ data_out_write_S <= not enable_waveform;
+ writemode_S <= REMOTEHITS1;
+ when REMOTEHITS1 =>
+ if (fifo_remote_read_aftr1clk_S='1') then
+ data_out_S <= data_remote_S;
+ data_out_write_S <= not enable_waveform;
+ writemode_S <= REMOTEHITS2;
+ else
+ if timeoutcount_S(timeoutcount_S'left)='0' then
+ if data_out_fifofull='0' then
+ timeoutcount_S <= timeoutcount_S+1;
+ end if;
+ else
+ timeoutcount_S <= (others => '0');
+ errorout_S <= '1';
+ data_remote_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ end if;
+ end if;
+ when REMOTEHITS2 =>
+ if (fifo_remote_read_aftr1clk_S='1') then
+ data_out_S <= data_remote_S;
+ data_out_write_S <= not enable_waveform;
+ data_out_last_S <= '1';
+ data_remote_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ else
+ if timeoutcount_S(timeoutcount_S'left)='0' then
+ if data_out_fifofull='0' then
+ timeoutcount_S <= timeoutcount_S+1;
+ end if;
+ else
+ timeoutcount_S <= (others => '0');
+ errorout_S <= '1';
+ data_remote_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ end if;
+ end if;
+ when LOCALWAVES0 =>
+ data_out_S <= header_local_hits1_S;
+ data_out_write_S <= enable_waveform;
+ writemode_S <= LOCALWAVES1;
+ when LOCALWAVES1 =>
+ if (fifo_local_read_aftr1clk_S='1') then
+ data_out_S <= data_local_S;
+ data_out_write_S <= enable_waveform;
+ data_out_last_S <= data_local_last_S;
+ if data_local_last_S='1' then
+ data_local_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ end if;
+ else
+ if timeoutcount_S(timeoutcount_S'left)='0' then
+ if data_out_fifofull='0' then
+ timeoutcount_S <= timeoutcount_S+1;
+ end if;
+ else
+ timeoutcount_S <= (others => '0');
+ errorout_S <= '1';
+ data_local_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ end if;
+ end if;
+ when REMOTEWAVES0 =>
+ data_out_S <= header_remote_hits1_S;
+ data_out_write_S <= enable_waveform;
+ writemode_S <= REMOTEWAVES1;
+ when REMOTEWAVES1 =>
+ if (fifo_remote_read_aftr1clk_S='1') then
+ data_out_S <= data_remote_S;
+ data_out_write_S <= enable_waveform;
+ data_out_last_S <= data_remote_last_S;
+ if data_remote_last_S='1' then
+ data_remote_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ end if;
+ else
+ if timeoutcount_S(timeoutcount_S'left)='0' then
+ if data_out_fifofull='0' then
+ timeoutcount_S <= timeoutcount_S+1;
+ end if;
+ else
+ timeoutcount_S <= (others => '0');
+ errorout_S <= '1';
+ data_remote_count_S <= 0;
+ writemode_S <= WAITNEXT;
+ end if;
+ end if;
+ when WAITNEXT =>
+ timeoutcount_S <= (others => '0');
+ if (data_local_count_S=2) and (data_local_type_S=SLOWCONTROL) then
+ data_out_S <= header_local_hits0_S;
+ data_out_first_S <= '1';
+ data_out_write_S <= '1';
+ writemode_S <= LOCALSLOWCONTROL;
+ elsif (data_remote_count_S=2) and (data_remote_type_S=SLOWCONTROL) then
+ data_out_S <= header_remote_hits0_S;
+ data_out_first_S <= '1';
+ data_out_write_S <= '1';
+ writemode_S <= REMOTESLOWCONTROL;
+ elsif ((data_local_count_S=2) and (data_remote_count_S=2)) then
+ local_timestamp_V := header_local_hits0_S(15 downto 0) & header_local_hits1_S(31 downto 16);
+ remote_timestamp_V := header_remote_hits0_S(15 downto 0) & header_remote_hits1_S(31 downto 16);
+ if ((local_timestamp_V(31 downto 0)<remote_timestamp_V(31 downto 0)) -- select local
+ or (((local_timestamp_V(31 downto 30)="11") and (remote_timestamp_V(31 downto 30)="00"))))
+ and (not ((local_timestamp_V(31 downto 30)="00") and (remote_timestamp_V(31 downto 30)="11"))) then
+ data_out_S <= header_local_hits0_S;
+ if data_local_type_S=HITDATA then
+ data_out_first_S <= '1';
+ data_out_write_S <= not enable_waveform;
+ writemode_S <= LOCALHITS0;
+ elsif data_local_type_S=WAVEFORM then
+ data_out_first_S <= '1';
+ data_out_write_S <= enable_waveform;
+ writemode_S <= LOCALWAVES0;
+ else
+ data_local_count_S <= 0;
+ errorout_S <= '1';
+ end if;
+ else
+ data_out_S <= header_remote_hits0_S;
+ if data_remote_type_S=HITDATA then
+ data_out_first_S <= '1';
+ data_out_write_S <= not enable_waveform;
+ writemode_S <= REMOTEHITS0;
+ elsif data_remote_type_S=WAVEFORM then
+ data_out_first_S <= '1';
+ data_out_write_S <= enable_waveform;
+ writemode_S <= REMOTEWAVES0;
+ else
+ data_remote_count_S <= 0;
+ errorout_S <= '1';
+ end if;
+ end if;
+ elsif ((data_local_count_S=2) and (fifo_remote_empty_S='1') and (data_remote_count_S/=2)) and (data_remote_inpipe_S='0') then
+ data_out_S <= header_local_hits0_S;
+ if data_local_type_S=HITDATA then
+ data_out_first_S <= '1';
+ data_out_write_S <= not enable_waveform;
+ writemode_S <= LOCALHITS0;
+ elsif data_local_type_S=WAVEFORM then
+ data_out_first_S <= '1';
+ data_out_write_S <= enable_waveform;
+ writemode_S <= LOCALWAVES0;
+ else
+ data_local_count_S <= 0;
+ errorout_S <= '1';
+ end if;
+ elsif ((fifo_local_empty_S='1') and (data_local_count_S/=2) and (data_remote_count_S=2)) and (data_local_inpipe_S='0') then
+ data_out_S <= header_remote_hits0_S;
+ if data_remote_type_S=HITDATA then
+ data_out_first_S <= '1';
+ data_out_write_S <= not enable_waveform;
+ writemode_S <= REMOTEHITS0;
+ elsif data_remote_type_S=WAVEFORM then
+ data_out_first_S <= '1';
+ data_out_write_S <= enable_waveform;
+ writemode_S <= REMOTEWAVES0;
+ else
+ data_remote_count_S <= 0;
+ errorout_S <= '1';
+ end if;
+ end if;
+ when others =>
+ end case;
+ end if;
+ fifo_local_read_aftr1clk_S <= data_local_read_S;
+ fifo_remote_read_aftr1clk_S <= data_remote_read_S;
+ end if;
+end process;
+
+end Behavioral;
-----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
--- Engineer: Peter Schakel
--- Create Date: 01-02-2012
--- Module Name: FEE_waveform_to_36bits
--- Description: put waveform data in 36-bits wide data stream
--- Modifications:
--- 14-08-2014: bug in read signal, output 'overflow_out' added
--- 16-09-2014: name changed from waveform_to_36bits to FEE_waveform_to_36bits
--- 11-10-2014: adc-channel number 8 bits
--- 23-10-2014: finish actual waveform in case of almost full signal
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.std_logic_ARITH.ALL;
-use IEEE.std_logic_UNSIGNED.ALL;
-use work.panda_package.all;
-
-
-------------------------------------------------------------------------------------------------------
--- FEE_waveform_to_36bits
--- Put waveform data in 36-bits wide data stream
--- Input waveform data is 36 bits wide, starting with timestamp and with the four highest bits for begin/time/end identification.
--- Output data is 36 bits wide with the four highest bits for identification
---
---
--- generics
---
--- inputs
--- clock : ADC sampling clock
--- reset : synchrounous reset
--- adcnumber : 8 bits indification of the adc channel
--- data_in : data from adc waveform buffer:
--- bits(35..32)="1000" : bits(31..0)=timestamp for pileup waveform
--- bits(35..32)="0010" : bits(31..16)=data sample, bits(15..0)=next data sample
--- bits(35..32)="0100" : bits(31..16)=last data sample, bits(15..0)=0000
--- bits(35..32)="0101" : bits(31..16)=last but one pulse data sample, bits(15..0)=last data sample
--- bits(35..32)="1111" : error, bits(31..0)=don't care
--- overflow_in : buffer overflow in adc waveform buffer, set bit in statusbyte
--- pileupdata_allowed : writing of pile-up data allowed
--- pileupdata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
---
--- outputs
--- data_in_read : read signal to adc waveform buffer
--- pileupdata_out : 36-bits data with pile-up waveform:
--- bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
--- bits(35..32)="0001" :
--- bits(31..24) = statusbyte (bit6=overflow)
--- bits(23..8) = 0
--- bits(7..0) = adcnumber (channel identifaction)
--- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
--- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
--- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
--- pileupdata_write : write signal for pile-up data output
--- overflow_out : buffer overflow: data skipped
--- error : error in incoming data
---
--- components
---
-------------------------------------------------------------------------------------------------------
-
-
-
-entity FEE_waveform_to_36bits is
- Port (
- clock : in std_logic;
- reset : in std_logic;
- adcnumber : in std_logic_vector(7 downto 0);
- data_in : in std_logic_vector(35 downto 0);
- data_in_available : in std_logic;
- data_in_read : out std_logic;
- overflow_in : in std_logic;
- pileupdata_out : out std_logic_vector(35 downto 0);
- pileupdata_write : out std_logic;
- pileupdata_allowed : in std_logic;
- pileupdata_almostfull : in std_logic;
- overflow_out : out std_logic;
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)
- );
-end FEE_waveform_to_36bits;
-
-architecture Behavioral of FEE_waveform_to_36bits is
-
-signal data_in_read_S : std_logic := '0';
-signal data_in_read_after1clk_S : std_logic := '0';
-signal pileupdata_write_S : std_logic := '0';
-signal pileupdata_trywrite_S : std_logic := '0';
-\r
-signal lastdata_S : std_logic := '0';
-signal lastdata0_S : std_logic := '0';
-signal lastdata1_S : std_logic := '0';
-
-signal writingadcnumber_S : std_logic := '0';
-signal writeadcnumber_S : std_logic := '0';
+----------------------------------------------------------------------------------\r
+-- Company: KVI-cart/RUG/Groningen University\r
+-- Engineer: Peter Schakel\r
+-- Create Date: 01-02-2012\r
+-- Module Name: FEE_waveform_to_36bits\r
+-- Description: put waveform data in 36-bits wide data stream\r
+-- Modifications:\r
+-- 14-08-2014: bug in read signal, output 'overflow_out' added\r
+-- 16-09-2014: name changed from waveform_to_36bits to FEE_waveform_to_36bits\r
+-- 11-10-2014: adc-channel number 8 bits\r
+-- 23-10-2014: finish actual waveform in case of almost full signal\r
+-- 23-10-2015: wavedata_inpipe added, earlier reading of data, outputs data when available \r
+-- 03-03-2017: signals renamed: wave instead of pileup\r
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+use IEEE.std_logic_ARITH.ALL;\r
+use IEEE.std_logic_UNSIGNED.ALL;\r
+use work.panda_package.all;\r
+\r
+\r
+------------------------------------------------------------------------------------------------------\r
+-- FEE_waveform_to_36bits\r
+-- Put waveform data in 36-bits wide data stream\r
+-- Input waveform data is 36 bits wide, starting with timestamp and with the four highest bits for begin/time/end identification.\r
+-- Output data is 36 bits wide with the four highest bits for identification\r
+--\r
+--\r
+-- generics\r
+-- ADCNUMBER : indification of the adc channel\r
+-- \r
+-- inputs\r
+-- clock : ADC sampling clock \r
+-- reset : synchrounous reset\r
+-- data_in : data from adc waveform buffer:\r
+-- bits(35..32)="1000" : bits(31..0)=timestamp for wave waveform\r
+-- bits(35..32)="0010" : bits(31..16)=data sample, bits(15..0)=next data sample\r
+-- bits(35..32)="0100" : bits(31..16)=last data sample, bits(15..0)=0000\r
+-- bits(35..32)="0101" : bits(31..16)=last but one pulse data sample, bits(15..0)=last data sample\r
+-- bits(35..32)="1111" : error, bits(31..0)=don't care\r
+-- overflow_in : buffer overflow in adc waveform buffer, set bit in statusbyte\r
+-- wavedata_allowed : writing of pile-up data allowed\r
+-- wavedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform\r
+-- \r
+-- outputs\r
+-- data_in_read : read signal to adc waveform buffer\r
+-- wavedata_out : 36-bits data with pile-up waveform:\r
+-- bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform\r
+-- bits(35..32)="0001" : \r
+-- bits(31..24) = statusbyte (bit6=overflow) \r
+-- bits(23..8) = 0\r
+-- bits(7..0) = adcnumber (channel identifaction)\r
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
+-- wavedata_write : write signal for pile-up data output\r
+-- wavedata_inpipe : more data in pipeline available\r
+-- overflow_out : buffer overflow: data skipped\r
+-- error : error in incoming data\r
+--\r
+-- components\r
+--\r
+------------------------------------------------------------------------------------------------------\r
+\r
+\r
+\r
+entity FEE_waveform_to_36bits is\r
+ generic (\r
+ ADCNUMBER : natural := 0\r
+ );\r
+ port (\r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ data_in : in std_logic_vector(35 downto 0); \r
+ data_in_available : in std_logic;\r
+ data_in_read : out std_logic;\r
+ overflow_in : in std_logic;\r
+ wavedata_out : out std_logic_vector(35 downto 0);\r
+ wavedata_write : out std_logic;\r
+ wavedata_inpipe : out std_logic;\r
+ wavedata_allowed : in std_logic;\r
+ wavedata_almostfull : in std_logic;\r
+ overflow_out : out std_logic;\r
+ error : out std_logic\r
+ );\r
+end FEE_waveform_to_36bits;\r
+\r
+architecture Behavioral of FEE_waveform_to_36bits is\r
+\r
+signal data_in_read_S : std_logic := '0';\r
+signal data_in_read_after1clk_S : std_logic := '0';\r
+signal wavedata_write_S : std_logic := '0';\r
+signal wavedata_trywrite_S : std_logic := '0';\r
+signal skipthiswave_S : std_logic := '0';\r
+\r
+signal writingadcnumber_S : std_logic := '0';\r
+signal writeadcnumber_S : std_logic := '0';\r
signal overflow_occurred_S : std_logic := '0';\r
signal clear_overflow_occurred_S : std_logic := '0';\r
signal overflow_in_S : std_logic := '0';\r
-signal error1_S : std_logic := '0';
-signal pileupdata_out_S : std_logic_vector(35 downto 0) := (others => '0');
-
-begin
-
-overflow_out <= overflow_occurred_S;
-error <= error1_S;
-data_in_read <= data_in_read_S;
-data_in_read_S <= '1'
- when (data_in_available='1') and (writingadcnumber_S='0') and (pileupdata_allowed='1') and \r
- ((pileupdata_almostfull='0') or (lastdata_S='0'))--and (prevent_reading_S='0')
- else '0';
-\r
-lastdata0_S <= '1' when (data_in_read_after1clk_S='1') and (data_in(35 downto 32)="010") else '0';\r
-lastdata_S <= '1' when (lastdata0_S='1') or (lastdata1_S='1') else '0';\r
-process(clock)
-begin
- if rising_edge(clock) then\r
- if reset='1' then\r
- lastdata1_S <= '0';\r
- else
- if data_in_read_after1clk_S='1' then\r
- lastdata1_S <= lastdata0_S;\r
- end if;\r
+signal error_S : std_logic := '0';\r
+signal error1_S : std_logic := '0';\r
+signal wavedata_out_S : std_logic_vector(35 downto 0) := (others => '0');\r
+signal data_in_saved_S : std_logic := '0';\r
+signal wavedata_allowed_S : std_logic := '0';\r
+signal data_in_S : std_logic_vector(35 downto 0) := (others => '0');\r
+\r
+-- attribute mark_debug : string;\r
+-- attribute mark_debug of data_in_read_after1clk_S : signal is "true";\r
+-- attribute mark_debug of wavedata_write_S : signal is "true";\r
+-- attribute mark_debug of wavedata_trywrite_S : signal is "true";\r
+-- attribute mark_debug of writingadcnumber_S : signal is "true";\r
+-- attribute mark_debug of writeadcnumber_S : signal is "true";\r
+-- attribute mark_debug of data_in_saved_S : signal is "true";\r
+-- attribute mark_debug of error_S : signal is "true";\r
+-- attribute mark_debug of error1_S : signal is "true";\r
+-- attribute mark_debug of overflow_occurred_S : signal is "true";\r
+-- attribute mark_debug of overflow_in_S : signal is "true";\r
+\r
+\r
+begin\r
+\r
+overflow_out <= overflow_occurred_S;\r
+error <= error1_S;\r
+--wavedata_inpipe <= '1' when (wavedata_trywrite_S='1') or (data_in_available='1') or (data_in_saved_S='1') or (data_in_read_after1clk_S='1') or (data_in_read_S='1') else '0';\r
+process(clock)\r
+begin\r
+ if (rising_edge(clock)) then \r
+ if (wavedata_trywrite_S='1') or (data_in_available='1') or (data_in_saved_S='1') or (data_in_read_after1clk_S='1') or (data_in_read_S='1') then\r
+ wavedata_inpipe <= '1';\r
+ else\r
+ wavedata_inpipe <= '0';\r
end if;\r
end if;\r
-end process;
-
-writingadcnumber_S <= '1' when
- (writeadcnumber_S='1')
- or ((data_in_read_after1clk_S='1') and (data_in(34 downto 32)="000"))
- else '0';
-
-pileupdata_out <= pileupdata_out_S;
-
-pileupdata_write <= pileupdata_write_S;
-pileupdata_write_S <= '1' when (pileupdata_trywrite_S='1') and (pileupdata_allowed='1') else '0';
-
-readprocess: process(clock)
-variable statusbyte_V : std_logic_vector(7 downto 0) := (others => '0');
-begin
+end process;\r
+\r
+data_in_read <= data_in_read_S;\r
+--data_in_read_S <= '1' \r
+-- when (data_in_available='1') and (writingadcnumber_S='0') and (wavedata_allowed='1') --and \r
+-- else '0';\r
+\r
+data_in_read_S <= '1' when \r
+((wavedata_allowed='1') or ((data_in_saved_S='0') and (wavedata_allowed='0') and (wavedata_allowed_S='0') and (data_in_read_after1clk_S='0')))\r
+ and (data_in_available='1') and (data_in_saved_S='0') and (writingadcnumber_S='0') else '0';\r
+\r
+\r
+--lastdata0_S <= '1' when (data_in_read_after1clk_S='1') and (data_in(35 downto 33)="010") else '0';\r
+--lastdata_S <= '1' when (lastdata0_S='1') or (lastdata1_S='1') else '0';\r
+--process(clock)\r
+--begin\r
+-- if rising_edge(clock) then\r
+-- if reset='1' then\r
+-- lastdata1_S <= '0';\r
+-- else\r
+-- if data_in_read_after1clk_S='1' then\r
+-- lastdata1_S <= lastdata0_S;\r
+-- end if;\r
+-- end if;\r
+-- end if;\r
+--end process;\r
+ \r
+writingadcnumber_S <= '1' when \r
+ (writeadcnumber_S='1') \r
+ or ((data_in_read_after1clk_S='1') and (data_in(34 downto 32)="000")) \r
+ else '0';\r
+\r
+wavedata_out <= wavedata_out_S; \r
+\r
+wavedata_write <= wavedata_write_S;\r
+wavedata_write_S <= '1' when (wavedata_trywrite_S='1') and (wavedata_allowed='1') else '0';\r
+\r
+readprocess: process(clock)\r
+variable statusbyte_V : std_logic_vector(7 downto 0) := (others => '0');\r
+begin\r
if rising_edge(clock) then\r
error1_S <= '0';\r
- clear_overflow_occurred_S <= '0';
- if reset='1' then
- pileupdata_trywrite_S <= '0';
- writeadcnumber_S <= '0';
- statusbyte_V := (others => '0');
- overflow_occurred_S <= '0';
+ clear_overflow_occurred_S <= '0';\r
+ if reset='1' then\r
+ wavedata_trywrite_S <= '0';\r
+ writeadcnumber_S <= '0';\r
+ statusbyte_V := (others => '0');\r
+ overflow_occurred_S <= '0';\r
data_in_read_after1clk_S <= '0';\r
- overflow_in_S <= overflow_in;
- else
- if ((overflow_in='1') and (overflow_in_S='0')) or (error1_S='1') then
+ overflow_in_S <= overflow_in;\r
+ else\r
+ if ((overflow_in='1') and (overflow_in_S='0')) or (error1_S='1') then\r
overflow_occurred_S <= '1';\r
elsif clear_overflow_occurred_S='1' then\r
overflow_occurred_S <= '0';\r
end if;\r
- overflow_in_S <= overflow_in;
- data_in_read_after1clk_S <= data_in_read_S;
- if data_in_read_after1clk_S='1' then
- case data_in(35 downto 32) is
- when "1000" =>
- pileupdata_out_S <= "0000" & data_in(31 downto 0);
- pileupdata_trywrite_S <= '1';
- writeadcnumber_S <= '1';
- when "0010" => -- samples
- writeadcnumber_S <= '0';
- pileupdata_out_S <= data_in;
- pileupdata_trywrite_S <= '1';
- when "0100" => -- last sample
- writeadcnumber_S <= '0';
- pileupdata_out_S <= data_in;
- pileupdata_trywrite_S <= '1';
- when "0101" => -- last samples
- writeadcnumber_S <= '0';
- pileupdata_out_S <= data_in;
- pileupdata_trywrite_S <= '1';
- when others =>
- error1_S <= '1';
- pileupdata_trywrite_S <= '0';
- end case;
- else -- not data_in_read_after1clk_S
- if (writeadcnumber_S='1') and (pileupdata_trywrite_S='1') and (pileupdata_allowed='1') then
+ overflow_in_S <= overflow_in;\r
+ data_in_read_after1clk_S <= data_in_read_S;\r
+\r
+ if (wavedata_write_S='0') and (wavedata_trywrite_S='1') then -- unsuccesfull try again\r
+ wavedata_trywrite_S <= '1';\r
+ if data_in_read_after1clk_S='1' then\r
+ data_in_S <= data_in;\r
+ data_in_saved_S <= '1';\r
+ end if;\r
+ elsif data_in_saved_S='1' then -- write saved data\r
+ case data_in_S(35 downto 32) is\r
+ when "1000" =>\r
+ wavedata_out_S <= "0000" & data_in_S(31 downto 0);\r
+ if wavedata_almostfull='1' then\r
+ overflow_occurred_S <= '1';\r
+ skipthiswave_S <= '1';\r
+ wavedata_trywrite_S <= '0';\r
+ else\r
+ skipthiswave_S <= '0';\r
+ wavedata_trywrite_S <= '1';\r
+ end if;\r
+ writeadcnumber_S <= '1';\r
+ when "0010" => -- samples\r
+ writeadcnumber_S <= '0';\r
+ wavedata_out_S <= data_in_S;\r
+ wavedata_trywrite_S <= not skipthiswave_S;\r
+ when "0100" => -- last sample\r
+ writeadcnumber_S <= '0';\r
+ wavedata_out_S <= data_in_S;\r
+ wavedata_trywrite_S <= not skipthiswave_S;\r
+ when "0101" => -- last samples\r
+ writeadcnumber_S <= '0';\r
+ wavedata_out_S <= data_in_S;\r
+ wavedata_trywrite_S <= not skipthiswave_S;\r
+ when others =>\r
+ error1_S <= '1';\r
+ writeadcnumber_S <= '0';\r
+ wavedata_trywrite_S <= '0';\r
+ skipthiswave_S <= '1';\r
+ end case;\r
+ if data_in_read_after1clk_S='1' then -- save next data\r
+ data_in_S <= data_in;\r
+ data_in_saved_S <= '1';\r
+ else\r
+ data_in_saved_S <= '0';\r
+ end if;\r
+ elsif data_in_read_after1clk_S='1' then\r
+ case data_in(35 downto 32) is\r
+ when "1000" =>\r
+ wavedata_out_S <= "0000" & data_in(31 downto 0);\r
+ if wavedata_almostfull='1' then\r
+ overflow_occurred_S <= '1';\r
+ skipthiswave_S <= '1';\r
+ wavedata_trywrite_S <= '0';\r
+ else\r
+ skipthiswave_S <= '0';\r
+ wavedata_trywrite_S <= '1';\r
+ end if;\r
+ writeadcnumber_S <= '1';\r
+ when "0010" => -- samples\r
+ writeadcnumber_S <= '0';\r
+ wavedata_out_S <= data_in;\r
+ wavedata_trywrite_S <= not skipthiswave_S;\r
+ when "0100" => -- last sample\r
+ writeadcnumber_S <= '0';\r
+ wavedata_out_S <= data_in;\r
+ wavedata_trywrite_S <= not skipthiswave_S;\r
+ when "0101" => -- last samples\r
+ writeadcnumber_S <= '0';\r
+ wavedata_out_S <= data_in;\r
+ wavedata_trywrite_S <= not skipthiswave_S;\r
+ when others =>\r
+ error1_S <= '1';\r
+ writeadcnumber_S <= '0';\r
+ wavedata_trywrite_S <= '0';\r
+ skipthiswave_S <= '1';\r
+ end case;\r
+ else -- not data_in_read_after1clk_S\r
+ if (writeadcnumber_S='1') and (wavedata_trywrite_S='1') and (wavedata_allowed='1') and (skipthiswave_S='0') then\r
if overflow_occurred_S='1' then\r
- statusbyte_V := STATBYTE_FEEPULSESKIPPED;
- clear_overflow_occurred_S <= '1';
- else
- statusbyte_V := (others => '0');
- end if;
- pileupdata_out_S <= "0001" & statusbyte_V & x"0000" & adcnumber;
- pileupdata_trywrite_S <= '1';
- writeadcnumber_S <= '0';
- elsif (pileupdata_trywrite_S='1') and (pileupdata_allowed='0') then -- keep trying
- pileupdata_trywrite_S <= '1';
- elsif (writeadcnumber_S='1') then
- writeadcnumber_S <= '0';
- else
- pileupdata_trywrite_S <= '0';
- end if;
- end if;
- end if;
- end if;
-end process;
-\r
-
-testword0(3 downto 0) <= data_in(35 downto 32);
-testword0(4) <= data_in_read_S;
-testword0(5) <= data_in_available;
-testword0(6) <= data_in_read_after1clk_S;
-testword0(7) <= data_in_read_S;
-testword0(11 downto 8) <= pileupdata_out_S(35 downto 32);
-testword0(12) <= pileupdata_write_S;
-testword0(13) <= pileupdata_trywrite_S;
-testword0(14) <= writingadcnumber_S;
-testword0(15) <= writeadcnumber_S;
-testword0(16) <= overflow_occurred_S;
-testword0(17) <= clear_overflow_occurred_S;
-testword0(18) <= overflow_in_S;
-testword0(19) <= error1_S;
-testword0(20) <= pileupdata_allowed;
-testword0(21) <= pileupdata_almostfull;
-testword0(22) <= writeadcnumber_S;
-\r
-end Behavioral;
-
-
+ statusbyte_V := STATBYTE_FEEPULSESKIPPED;\r
+ clear_overflow_occurred_S <= '1';\r
+ else \r
+ statusbyte_V := (others => '0');\r
+ end if;\r
+ wavedata_out_S <= "0001" & statusbyte_V & x"0000" & conv_std_logic_vector(ADCNUMBER,8);\r
+ wavedata_trywrite_S <= '1';\r
+ writeadcnumber_S <= '0';\r
+ elsif (writeadcnumber_S='1') then\r
+ writeadcnumber_S <= '0';\r
+ else\r
+ wavedata_trywrite_S <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ wavedata_allowed_S <= wavedata_allowed;\r
+ end if;\r
+end process;\r
+\r
+process(clock)\r
+variable prevdata_V : std_logic_vector(3 downto 0) := "0000";\r
+begin\r
+ if (rising_edge(clock)) then \r
+ error_S <= '0';\r
+ if wavedata_write_S='1' then\r
+ if (wavedata_out_S(35 downto 32)="0000") then\r
+ if (prevdata_V(3 downto 1)/="010") then error_S <= '1'; end if;\r
+ elsif (wavedata_out_S(35 downto 32)="0001") then\r
+ if (prevdata_V/="0000") then error_S <= '1'; end if;\r
+ elsif (wavedata_out_S(35 downto 32)="0010") then\r
+ if (prevdata_V/="0010") and (prevdata_V/="0001") then error_S <= '1'; end if;\r
+ elsif (wavedata_out_S(35 downto 32)="0100") then\r
+ if (prevdata_V/="0010") then error_S <= '1'; end if;\r
+ elsif (wavedata_out_S(35 downto 32)="0101") then \r
+ if (prevdata_V/="0010") then error_S <= '1'; end if;\r
+ else\r
+ error_S <= '1';\r
+ end if;\r
+ prevdata_V := wavedata_out_S(35 downto 32);\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+\r
+\r
+end Behavioral;\r
+\r
+\r
-----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
--- Engineer: Peter Schakel
--- Create Date: 03-02-2012
--- Module Name: FEE_wavemux2to1
--- Description: compare timestamp of 36bits data pass on first
--- Modifications:
--- 11-10-2014: adc-channel number 8 bits
--- 23-10-2014: proper end of packet in case of timeout
+----------------------------------------------------------------------------------\r
+-- Company: KVI-cart/RUG/Groningen University\r
+-- Engineer: Peter Schakel\r
+-- Create Date: 03-02-2012\r
+-- Module Name: FEE_wavemux2to1\r
+-- Description: compare timestamp of 36bits data pass on first\r
+-- Modifications:\r
+-- 11-10-2014: adc-channel number 8 bits\r
+-- 23-10-2014: proper end of packet in case of timeout\r
+-- 25-09-2015: compare bug fixed at FFFF->0000 superburst change\r
+-- 23-10-2015: code rewritten, now without variables\r
+-- 20-01-2017: check on valid first word for passing on new values\r
----------------------------------------------------------------------------------\r
\r
library IEEE;\r
--\r
--\r
-- generics\r
+-- TIMEOUTBITS : number of bits for timeout counter inwhich time the next word should be available\r
-- \r
-- inputs\r
-- clock : ADC sampling clock \r
--- reset : synchrounous reset\r
+-- reset : synchronous reset\r
-- data1_in : data from first 36-bits input\r
-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
-- bits(35..32)="0001" : \r
-- data_out_write : write signal for 36-bits output data\r
-- data_out_available : data available: in this module or at the input\r
-- error : error in data bits 35..32\r
+-- timeerror : error in time of output wave, only for debug\r
--\r
-- components\r
--\r
\r
\r
entity FEE_wavemux2to1 is\r
- generic(
- TIMEOUTBITS : natural := 6
- );
+ generic(\r
+ TIMEOUTBITS : natural := 8\r
+ );\r
Port (\r
- clock : in std_logic;
+ clock : in std_logic;\r
reset : in std_logic;\r
data1_in : in std_logic_vector(35 downto 0); \r
data1_in_write : in std_logic;\r
- data1_in_available : in std_logic;
+ data1_in_available : in std_logic;\r
data1_in_allowed : out std_logic;\r
data2_in : in std_logic_vector(35 downto 0); \r
data2_in_write : in std_logic;\r
- data2_in_available : in std_logic;
+ data2_in_available : in std_logic;\r
data2_in_allowed : out std_logic;\r
data_out : out std_logic_vector(35 downto 0);\r
data_out_write : out std_logic;\r
- data_out_available : out std_logic;
+ data_out_available : out std_logic;\r
data_out_allowed : in std_logic;\r
- error : out std_logic;
- testword0 : out std_logic_vector(35 downto 0)\r
+ error : out std_logic;\r
+ timeerror : out std_logic\r
);\r
end FEE_wavemux2to1;\r
\r
\r
architecture Behavioral of FEE_wavemux2to1 is\r
\r
-signal timeout_counter_S : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
-
-signal error_S : std_logic := '0';
-signal read_pulse1_S : std_logic := '0';
-signal read_pulse2_S : std_logic := '0';
-signal data1_in_allowed_S : std_logic := '0';
+--//signal timeout_counter_S : std_logic_vector(TIMEOUTBITS downto 0) := (others => '0');\r
+signal clear_timeout_counter_S : std_logic := '0';\r
+signal inc_timeout_counter_S : std_logic := '0';\r
+\r
+signal error_S : std_logic := '0';\r
+signal read_pulse1_S : std_logic := '0';\r
+signal read_pulse2_S : std_logic := '0';\r
+signal data1_in_allowed_S : std_logic := '0';\r
signal data2_in_allowed_S : std_logic := '0';\r
signal data1_in_write_S : std_logic := '0';\r
-signal data2_in_write_S : std_logic := '0';
-signal data_out_trywrite_S : std_logic := '0';
-signal data_out_write_S : std_logic := '0';
-signal data_out_available_S : std_logic := '0';
-signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');
-signal data1_timestamp_valid_S : std_logic := '0';
-signal data2_timestamp_valid_S : std_logic := '0';
-
+signal data2_in_write_S : std_logic := '0';\r
+signal data_out_trywrite_S : std_logic := '0';\r
+signal data_out_write_S : std_logic := '0';\r
+signal data_out_available_S : std_logic;\r
+signal data_out_S : std_logic_vector(35 downto 0);\r
+signal prevdata1first_S : std_logic := '0';\r
+signal prevdata2first_S : std_logic := '0';\r
+signal selectdata1_S : std_logic;\r
+signal data_outfilled_S : std_logic := '0';\r
+\r
+signal data1_in_available_S : std_logic;\r
+signal data2_in_available_S : std_logic;\r
+\r
+signal timeerror_S : std_logic;\r
+signal prevdataout_S : std_logic_vector(31 downto 0);\r
+signal derror_S : std_logic := '0';\r
+\r
+\r
+-- attribute mark_debug : string;\r
+-- attribute mark_debug of error_S : signal is "true";\r
+-- attribute mark_debug of data1_in_available : signal is "true";\r
+-- attribute mark_debug of read_pulse1_S : signal is "true";\r
+-- attribute mark_debug of data1_in_write_S : signal is "true";\r
+-- attribute mark_debug of data2_in_available : signal is "true";\r
+-- attribute mark_debug of read_pulse2_S : signal is "true";\r
+-- attribute mark_debug of data2_in_write_S : signal is "true";\r
+-- attribute mark_debug of timeout_counter_S : signal is "true";\r
+-- attribute mark_debug of data_out_trywrite_S : signal is "true";\r
+-- attribute mark_debug of data_out_write_S : signal is "true";\r
+-- attribute mark_debug of data_out_allowed : signal is "true";\r
+\r
+\r
begin\r
\r
-error <= error_S;
+error <= error_S;\r
+\r
+data1_in_available_S <= data1_in_available;\r
+data2_in_available_S <= data2_in_available;\r
+\r
\r
data_out_available <= data_out_available_S;\r
-data_out_available_S <= '1' when (data1_in_available='1') or (data2_in_available='1') \r
- or (data_out_trywrite_S='1') \r
- or (data1_timestamp_valid_S='1') or (data2_timestamp_valid_S='1')\r
- else '0';
-
-data_out <= data_out_S;
-data_out_write <= data_out_write_S;
-data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
-
-data1_in_allowed <= data1_in_allowed_S;
-data1_in_allowed_S <= '1' when (data_out_allowed='1')
- and ((read_pulse1_S='1')
- or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data1_timestamp_valid_S='0')))
- else '0';
-
-data2_in_allowed <= data2_in_allowed_S;
-data2_in_allowed_S <= '1' when (data_out_allowed='1')
- and ((read_pulse2_S='1')
- or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data2_timestamp_valid_S='0')))
- else '0';
-
---data2_in_allowed_S <= '1' when (data_out_allowed='1')
--- and ((read_pulse2_S='1')
--- or (((read_pulse1_S='0') and (data1_timestamp_valid_S='0'))
--- and ((read_pulse2_S='0') and (data2_timestamp_valid_S='0'))))
--- else '0';
-
+data_out_available_S <= '1' when (data1_in_available_S='1') or (data2_in_available_S='1') \r
+ or (data_out_trywrite_S='1') or (read_pulse1_S='1') or (read_pulse2_S='1')\r
+ else '0';\r
+\r
+data_out <= data_out_S;\r
+data_out_write <= data_out_write_S;\r
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';\r
+\r
+selectdata1_S <= '1' when \r
+ ((data1_in(31 downto 0)<data2_in(31 downto 0))\r
+ or (((data1_in(31 downto 30)="11") and (data2_in(31 downto 30)="00")))) \r
+ and (not ((data1_in(31 downto 30)="00") and (data2_in(31 downto 30)="11"))) \r
+ else '0';\r
+data1_in_allowed <= data1_in_allowed_S; \r
+--data1_in_allowed_S <= '1' when ((data_outfilled_S='0') or ((data_out_trywrite_S='1') and (data_out_write_S='1'))) and\r
+data1_in_allowed_S <= '1' when ((data_out_trywrite_S='0') or ((data_out_trywrite_S='1') and (data_out_write_S='1'))) and\r
+ ((read_pulse1_S='1') \r
+ or ((read_pulse2_S='0') and (data1_in(35 downto 32)="0000") and (data2_in(35 downto 32)="0000") and (selectdata1_S='1'))\r
+ or ((read_pulse2_S='0') and (data2_in_available_S='0'))\r
+--// or ((timeout_counter_S(TIMEOUTBITS)='1') and (selectdata1_S='1'))\r
+ )\r
+ else '0';\r
+data2_in_allowed <= data2_in_allowed_S;\r
+--data2_in_allowed_S <= '1' when ((data_outfilled_S='0') or ((data_out_trywrite_S='1') and (data_out_write_S='1'))) and\r
+data2_in_allowed_S <= '1' when ((data_out_trywrite_S='0') or ((data_out_trywrite_S='1') and (data_out_write_S='1'))) and\r
+ ((read_pulse2_S='1') \r
+ or ((read_pulse1_S='0') and (data1_in(35 downto 32)="0000") and (data2_in(35 downto 32)="0000") and (selectdata1_S='0'))\r
+ or ((read_pulse1_S='0') and (data1_in_available_S='0'))\r
+--// or ((timeout_counter_S(TIMEOUTBITS)='1') and (selectdata1_S='0'))\r
+ )\r
+ else '0';\r
+\r
+ \r
data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';\r
data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';\r
-
+\r
readprocess: process(clock)\r
-variable data1_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
-variable data2_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
-variable data1_timestamp_valid_V : std_logic := '0';
-variable data2_timestamp_valid_V : std_logic := '0';
-begin
- if rising_edge(clock) then
- if reset='1' then
- data_out_trywrite_S <= '0';
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- data1_timestamp_valid_S <= '0';
- data2_timestamp_valid_S <= '0';
- timeout_counter_S <= (others => '0');\r
+begin\r
+ if rising_edge(clock) then\r
+ clear_timeout_counter_S <= '0';\r
+ inc_timeout_counter_S <= '0';\r
+ error_S <= '0'; --// timeout_counter_S(TIMEOUTBITS);\r
+ if reset='1' then\r
+ data_out_trywrite_S <= '0';\r
+ data_outfilled_S <= '0';\r
+ read_pulse1_S <= '0';\r
+ read_pulse2_S <= '0';\r
+ clear_timeout_counter_S <= '1';\r
else\r
- if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
- data_out_trywrite_S <= '1'; -- try again
- timeout_counter_S <= (others => '0');\r
+ if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write\r
+ data_outfilled_S <= '1';\r
+ data_out_trywrite_S <= '1'; -- try again\r
+ clear_timeout_counter_S <= '1';\r
else\r
+ if (data_out_trywrite_S='1') and (data_out_write_S='1') then -- succesful write\r
+ data_outfilled_S <= '0';\r
+ end if; \r
if read_pulse1_S='1' then\r
- data1_timestamp_valid_V := '0';\r
if data1_in_write_S='1' then\r
- timeout_counter_S <= (others => '0');\r
+ clear_timeout_counter_S <= '1';\r
if (data1_in(35 downto 32)="0001") or (data1_in(35 downto 32)="0010") then -- next data\r
- error_S <= '0';\r
- data_out_S <= data1_in;
+ data_out_S <= data1_in;\r
data_out_trywrite_S <= '1';\r
+ data_outfilled_S <= '1';\r
elsif (data1_in(35 downto 33)="010") then -- last data\r
- error_S <= '0';\r
data_out_S <= data1_in;\r
- read_pulse1_S <= '0';
+ read_pulse1_S <= '0';\r
data_out_trywrite_S <= '1';\r
+ data_outfilled_S <= '1';\r
else -- error\r
error_S <= '1';\r
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
+ read_pulse1_S <= '0';\r
+ read_pulse2_S <= '0';\r
data_out_trywrite_S <= '0';\r
+ data_outfilled_S <= '0';\r
end if;\r
else\r
- data_out_trywrite_S <= '0';\r
- if timeout_counter_S(TIMEOUTBITS-1)='1' then\r
- data_out_S <= "0100" & x"00000000"; -- force last data\r
- data_out_trywrite_S <= '1';\r
- error_S <= '1';\r
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- timeout_counter_S <= (others => '0');\r
- else\r
+--// -- if timeout_counter_S(TIMEOUTBITS)='1' then\r
+ -- data_out_S <= "0100" & x"00000000"; -- force last data\r
+ -- data_out_trywrite_S <= '1';\r
+ -- error_S <= '1';\r
+ -- read_pulse1_S <= '0';\r
+ -- read_pulse2_S <= '0';\r
+ -- clear_timeout_counter_S <= '1';\r
+ -- data_outfilled_S <= '1';\r
+ -- else\r
+ data_out_trywrite_S <= '0';\r
+ data_outfilled_S <= '0';\r
if data_out_allowed='1' then\r
if data_out_write_S='1' then\r
- timeout_counter_S <= (others => '0');\r
+ clear_timeout_counter_S <= '1';\r
else\r
- timeout_counter_S <= timeout_counter_S+1;\r
+ inc_timeout_counter_S <= '1';\r
end if;\r
end if;\r
- error_S <= '0';\r
- end if;\r
- end if;
+--// end if;\r
+ end if;\r
elsif read_pulse2_S='1' then\r
- data2_timestamp_valid_V := '0';\r
if data2_in_write_S='1' then\r
- timeout_counter_S <= (others => '0');\r
+ clear_timeout_counter_S <= '1';\r
if (data2_in(35 downto 32)="0001") or (data2_in(35 downto 32)="0010") then -- next data\r
- error_S <= '0';\r
- data_out_S <= data2_in;
+ data_out_S <= data2_in;\r
data_out_trywrite_S <= '1';\r
+ data_outfilled_S <= '1';\r
elsif (data2_in(35 downto 33)="010") then -- last data\r
- error_S <= '0';\r
data_out_S <= data2_in;\r
- read_pulse2_S <= '0';
+ read_pulse2_S <= '0';\r
data_out_trywrite_S <= '1';\r
+ data_outfilled_S <= '1';\r
else -- error\r
error_S <= '1';\r
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
+ read_pulse1_S <= '0';\r
+ read_pulse2_S <= '0';\r
data_out_trywrite_S <= '0';\r
+ data_outfilled_S <= '0';\r
end if;\r
else\r
- data_out_trywrite_S <= '0';\r
- if timeout_counter_S(TIMEOUTBITS-1)='1' then\r
- data_out_S <= "0100" & x"00000000"; -- force last data\r
- data_out_trywrite_S <= '1';\r
- error_S <= '1';\r
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- timeout_counter_S <= (others => '0');\r
- else\r
+--// -- if timeout_counter_S(TIMEOUTBITS)='1' then\r
+ -- data_out_S <= "0100" & x"00000000"; -- force last data\r
+ -- data_out_trywrite_S <= '1';\r
+ -- error_S <= '1';\r
+ -- read_pulse1_S <= '0';\r
+ -- read_pulse2_S <= '0';\r
+ -- clear_timeout_counter_S <= '1';\r
+ -- data_outfilled_S <= '1';\r
+ -- else\r
+ data_out_trywrite_S <= '0';\r
+ data_outfilled_S <= '0';\r
if data_out_allowed='1' then\r
if data_out_write_S='1' then\r
- timeout_counter_S <= (others => '0');\r
+ clear_timeout_counter_S <= '1';\r
else\r
- timeout_counter_S <= timeout_counter_S+1;\r
+ inc_timeout_counter_S <= '1';\r
end if;\r
- end if;\r
- error_S <= '0';\r
+--// end if;\r
end if;\r
end if;\r
else\r
- timeout_counter_S <= (others => '0');\r
if data1_in_write_S='1' then\r
- if (data1_in(35 downto 32)="0000") then
- data1_timestamp_V := data1_in(31 downto 0);\r
- data1_timestamp_valid_V := '1';\r
- else -- error\r
- error_S <= '1';\r
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- end if;\r
- end if;\r
- if data2_in_write_S='1' then\r
- if (data2_in(35 downto 32)="0000") then
- data2_timestamp_V := data2_in(31 downto 0);\r
- data2_timestamp_valid_V := '1';\r
- else -- error\r
- error_S <= '1';\r
- read_pulse1_S <= '0';
- read_pulse2_S <= '0';
- data1_timestamp_valid_V := '0';
- data2_timestamp_valid_V := '0';
- end if;\r
- end if;\r
- if data1_timestamp_valid_V='1' then\r
- if data2_timestamp_valid_V='1' then\r
- if (data1_timestamp_V(31 downto 0)<data2_timestamp_V(31 downto 0)) -- select 1
- or (((data1_timestamp_V(31 downto 30)="11") and (data2_timestamp_V(31 downto 30)="00"))) then\r
- read_pulse1_S <= '1';\r
- data1_timestamp_valid_V := '0';\r
- data_out_trywrite_S <= '1'; \r
- data_out_S <= "0000" & data1_timestamp_V;
- else -- select 2\r
- read_pulse2_S <= '1';\r
- data2_timestamp_valid_V := '0';\r
- data_out_trywrite_S <= '1'; \r
- data_out_S <= "0000" & data2_timestamp_V;
+ read_pulse1_S <= '1';\r
+ read_pulse2_S <= '0';\r
+ data_out_S <= data1_in;\r
+ data_out_trywrite_S <= '1';\r
+ clear_timeout_counter_S <= '1';\r
+ data_outfilled_S <= '1';\r
+ elsif data2_in_write_S='1' then\r
+ read_pulse1_S <= '0';\r
+ read_pulse2_S <= '1';\r
+ data_out_S <= data2_in;\r
+ data_out_trywrite_S <= '1';\r
+ clear_timeout_counter_S <= '1';\r
+ data_outfilled_S <= '1';\r
+ else\r
+ if (data1_in_available='1') and (data2_in_available='0') then\r
+ clear_timeout_counter_S <= '1';\r
+ data_out_S <= data1_in;\r
+ elsif (data1_in_available='0') and (data2_in_available='1') then\r
+ clear_timeout_counter_S <= '1';\r
+ data_out_S <= data2_in;\r
+ elsif (data1_in_available='1') and (data2_in_available='1') then\r
+ if (data1_in(35 downto 32)="0000") and (data2_in(35 downto 32)="0000") then\r
+ if (selectdata1_S='0') then\r
+ data_out_S <= data2_in;\r
+ else\r
+ data_out_S <= data1_in;\r
+ end if;\r
+ end if;\r
+ if data_out_allowed='1' then\r
+--// -- if (timeout_counter_S(TIMEOUTBITS)='0') then\r
+ -- inc_timeout_counter_S <= '1';\r
+ -- else\r
+ -- error_S <= '1';\r
+ -- end if;\r
+ else\r
+ clear_timeout_counter_S <= '1';\r
end if;\r
- elsif data2_in_available='1' then -- data expected: wait\r
- data_out_trywrite_S <= '0';\r
- else -- write 1\r
- read_pulse1_S <= '1';\r
- data1_timestamp_valid_V := '0';\r
- data_out_trywrite_S <= '1'; \r
- data_out_S <= "0000" & data1_timestamp_V; \r
- end if;\r
- elsif data2_timestamp_valid_V='1' then
- if data1_in_available='1' then -- data expected: wait\r
- data_out_trywrite_S <= '0';\r
- else -- write 2\r
- read_pulse2_S <= '1';\r
- data2_timestamp_valid_V := '0';\r
- data_out_trywrite_S <= '1'; \r
- data_out_S <= "0000" & data2_timestamp_V; \r
end if;\r
- else -- no valid timestamps\r
+ data_outfilled_S <= '0';\r
data_out_trywrite_S <= '0';\r
end if;\r
end if; \r
- data1_timestamp_valid_S <= data1_timestamp_valid_V;
- data2_timestamp_valid_S <= data2_timestamp_valid_V;
- end if;
- end if;
- end if;
-end process;
-
-
-
-
--- testword0 <= (others => '0');
-
-testword0(0) <= data1_in_write;
-testword0(1) <= data1_in_available;
-testword0(2) <= data1_in_allowed_S;
-testword0(3) <= read_pulse1_S;
-testword0(4) <= data1_in_write_S;
-testword0(5) <= data1_timestamp_valid_S;
-testword0(9 downto 6) <= data1_in(35 downto 32);\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+ \r
+--//-- process(clock)\r
+-- begin\r
+ -- if rising_edge(clock) then \r
+ -- if (reset='1') or (clear_timeout_counter_S='1') then\r
+ -- timeout_counter_S <= (others => '0');\r
+ -- elsif inc_timeout_counter_S='1' then\r
+ -- timeout_counter_S <= timeout_counter_S+1;\r
+ -- end if;\r
+ -- end if;\r
+-- end process;\r
\r
-testword0(10) <= data2_in_write;
-testword0(11) <= data2_in_available;
-testword0(12) <= data2_in_allowed_S;
-testword0(13) <= read_pulse2_S;
-testword0(14) <= data2_in_write_S;
-testword0(15) <= data2_timestamp_valid_S;
-testword0(19 downto 16) <= data2_in(35 downto 32);\r
-
-
-testword0(20) <= data_out_trywrite_S;
-testword0(21) <= data_out_write_S;
-testword0(22) <= data_out_available_S;
-testword0(23) <= data_out_allowed;
-testword0(27 downto 24) <= data_out_S(35 downto 32);
-testword0(28) <= error_S;
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ timeerror_S <= '0';\r
+ if (data_out_write_S='1') and (data_out_S(35 downto 32)="0000") then \r
+ if data_out_S(31 downto 0)<prevdataout_S then\r
+ timeerror_S <= '1';\r
+ end if;\r
+ prevdataout_S <= data_out_S(31 downto 0);\r
+ end if;\r
+ end if;\r
+end process;\r
+timeerror <= timeerror_S;\r
+ \r
+process(clock)\r
+variable prevdata_V : std_logic_vector(3 downto 0) := "0000";\r
+begin\r
+ if (rising_edge(clock)) then \r
+ derror_S <= '0';\r
+ if data_out_write_S='1' then\r
+ if (data_out_S(35 downto 32)="0000") then\r
+ if (prevdata_V(3 downto 1)/="010") then derror_S <= '1'; end if;\r
+ elsif (data_out_S(35 downto 32)="0001") then\r
+ if (prevdata_V/="0000") then derror_S <= '1'; end if;\r
+ elsif (data_out_S(35 downto 32)="0010") then\r
+ if (prevdata_V/="0010") and (prevdata_V/="0001") then derror_S <= '1'; end if;\r
+ elsif (data_out_S(35 downto 32)="0100") then\r
+ if (prevdata_V/="0010") then derror_S <= '1'; end if;\r
+ elsif (data_out_S(35 downto 32)="0101") then \r
+ if (prevdata_V/="0010") then derror_S <= '1'; end if;\r
+ else\r
+ derror_S <= '1';\r
+ end if;\r
+ prevdata_V := data_out_S(35 downto 32);\r
+ end if;\r
+ end if;\r
+end process;\r
\r
-
-
-testword0(33 downto 29) <= timeout_counter_S(TIMEOUTBITS-1 downto TIMEOUTBITS-5);
-testword0(35 downto 34) <= (others => '0');
-
-
-end Behavioral;
-
-
+end Behavioral;\r
-- Description: Read 36-bits data from fifo and write to next module
-- Modifications:
-- 16-10-2014: inpipe signal
+-- 16-10-2015: reads one data word when output writing is not allowed
----------------------------------------------------------------------------------
library IEEE;
signal data_in_read_S : std_logic := '0';
signal data_in_read_after1clk_S : std_logic := '0';
signal data_out_trywrite_S : std_logic := '0';
+signal data_out_allowed_S : std_logic := '0';
begin
data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or (data_in_saved_S='1') else '0';
data_in_read <= data_in_read_S;
-data_in_read_S <= '1' when (data_out_allowed='1') and (data_in_available='1') and (data_in_saved_S='0') else '0';
+data_in_read_S <= '1' when
+((data_out_allowed='1') or ((data_in_saved_S='0') and (data_out_allowed='0') and (data_out_allowed_S='0') and (data_in_read_after1clk_S='0')))
+ and (data_in_available='1') and (data_in_saved_S='0') else '0';
+
data_out_write <= data_out_write_S;
data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
end if;
data_in_read_after1clk_S <= data_in_read_S;
end if;
+ data_out_allowed_S <= data_out_allowed;
end if;
end process;
--- /dev/null
+----------------------------------------
+-- Function : Code Gray counter.
+-- Coder : Alex Claros F.
+-- Date : 15/May/2005.
+-- Translator : Alexander H Pham (VHDL)
+----------------------------------------
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_arith.all;
+
+entity GrayCounter is
+ generic (
+ COUNTER_WIDTH : natural := 4
+ );
+ port ( --'Gray' code count output.
+ GrayCount_out :out std_logic_vector (COUNTER_WIDTH-1 downto 0);
+ Enable_in :in std_logic; -- Count enable.
+ Clear_in :in std_logic; -- Count reset.
+ clk :in std_logic -- Input clock
+ );
+end entity;
+
+architecture rtl of GrayCounter is
+ signal BinaryCount :std_logic_vector (COUNTER_WIDTH-1 downto 0);
+begin
+ process (clk)
+ variable b1 : std_logic_vector(COUNTER_WIDTH-2 downto 0);
+ variable b2 : std_logic_vector(COUNTER_WIDTH-2 downto 0);
+ begin
+ if (rising_edge(clk)) then
+ if (Clear_in = '1') then
+ --Gray count begins @ '1' with
+ BinaryCount <= conv_std_logic_vector(1, COUNTER_WIDTH);
+ GrayCount_out <= (others=>'0');
+ -- first 'Enable_in'.
+ elsif (Enable_in = '1') then
+ BinaryCount <= BinaryCount + 1;
+ b1 := BinaryCount(COUNTER_WIDTH-2 downto 0);
+ b2 := BinaryCount(COUNTER_WIDTH-1 downto 1);
+ GrayCount_out <= BinaryCount(COUNTER_WIDTH-1) & (b1 xor b2);
+ end if;
+ end if;
+ end process;
+
+end architecture;
\r
package panda_package is\r
\r
- constant NROFADCS : natural := 32;\r
- constant NROFFIBERS : natural := 4;\r
- constant ADCINDEXSHIFT : natural := 1;\r
- constant NROFMUXREGS : natural := 14;\r
- constant ADCBITS : natural := 14;\r
- constant ADCCLOCKFREQUENCY : natural := 80000000; -- 80000000; -- 62500000;\r
- constant FEESLOWCONTROLADRESSES : natural := 2*NROFADCS/(ADCINDEXSHIFT+1)+4;
- constant FEESLOWCONTROLBOARDADDRESS : natural := 2*NROFADCS/(ADCINDEXSHIFT+1);
-\r
+ constant DOPRECLUSTERING : boolean := false; \r
+ constant NROFFEEFPGAS : natural := 2;\r
+ constant NROFFEEADCS : natural := 32;\r
+ constant NROFFIBERS : natural := 4;\r
+ constant ADCINDEXSHIFT : natural := 1;\r
+ constant NROFMUXREGS : natural := 14;\r
+ constant ADCBITS : natural := 14;\r
+ constant NROFREGSPERCHANNEL : natural := 4;\r
+ constant ADCCLOCKFREQUENCY : natural := 80000000;\r
+ constant FEESLOWCONTROLADRESSES : natural := (NROFFEEFPGAS*NROFREGSPERCHANNEL*NROFFEEADCS)/(ADCINDEXSHIFT+1)+4*NROFFEEFPGAS; -- number of addressen for initialization all FEE adddresses\r
+ constant FEESLOWCONTROLBOARDADDRESS : natural := (NROFFEEFPGAS*NROFREGSPERCHANNEL*NROFFEEADCS)/(ADCINDEXSHIFT+1); -- number of addressen for initialization all FEE adddresses\r
+ \r
-- statusbyte in data stream :\r
- constant STATBYTE_DCPULSESKIPPED : std_logic_vector(7 downto 0) := "00000100";\r
- constant STATBYTE_DCWAVESKIPPED : std_logic_vector(7 downto 0) := "00000100";\r
- constant STATBYTE_DCCOMBINEDHITS : std_logic_vector(7 downto 0) := "00000001";\r
- constant STATBYTE_DCCOMBINEDDISCARDED : std_logic_vector(7 downto 0) := "00000010";\r
- constant STATBYTE_DCSUPERBURSTMISSED : std_logic_vector(7 downto 0) := "00001100";\r
-\r
- constant STATBYTE_FEEPULSESKIPPED : std_logic_vector(7 downto 0) := "01000000";\r
- constant STATBYTE_FEECFNOZEROCROSS : std_logic_vector(7 downto 0) := "00100000";\r
- constant STATBYTE_FEECFERROR : std_logic_vector(7 downto 0) := "00010000";\r
+ constant STATBYTE_DCPULSESKIPPED : std_logic_vector(7 downto 0) := "00000100";\r
+ constant STATBYTE_DCWAVESKIPPED : std_logic_vector(7 downto 0) := "00000100";\r
+ constant STATBYTE_DCCOMBINEDHITS : std_logic_vector(7 downto 0) := "00000001";\r
+ constant STATBYTE_DCCOMBINEDDISCARDED : std_logic_vector(7 downto 0) := "00000010";\r
+ constant STATBYTE_DCSUPERBURSTMISSED : std_logic_vector(7 downto 0) := "00001100";\r
+\r
+ constant STATBYTE_PILEUPHITBITNR : integer := 7;\r
+ constant STATBYTE_PILEUPHIT : std_logic_vector(7 downto 0) := (STATBYTE_PILEUPHITBITNR => '1', others => '0');\r
+ constant STATBYTE_FEEPULSESKIPPED : std_logic_vector(7 downto 0) := "01000000";\r
+ constant STATBYTE_FEECFNOZEROCROSS : std_logic_vector(7 downto 0) := "00100000";\r
+ constant STATBYTE_FEECFERROR : std_logic_vector(7 downto 0) := "00010000";\r
\r
-- fiber constants\r
constant KCHAR280 : std_logic_vector(7 downto 0) := "00011100"; -- 1C\r
constant KCHAR281 : std_logic_vector(7 downto 0) := "00111100"; -- 3C\r
constant KCHAR285 : std_logic_vector(7 downto 0) := "10111100"; -- BC\r
--- constant KCHAR277 : std_logic_vector(7 downto 0) := "11111011"; -- FB\r
+\r
constant KCHAR286 : std_logic_vector(7 downto 0) := x"DC";\r
\r
constant KCHARIDLE : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR285; -- 3CBC peter: bytes different for word sync\r
-- bit3 : received character not in table: fiber error\r
-- bit4 : pulse data skipped due to full multiplexer fifo\r
-- bit5 : receiver locked\r
+-- bit6 : data being sent to the output fiber (same for each fiber: there is only one output)\r
-- bit15..8 : number of pulse data packets skipped due to full buffers\r
-- bit31..16 : number of successful hamming code corrections\r
constant ADDRESS_MUX_MAXCFLUTS : std_logic_vector(23 downto 0) := x"800001";\r
-- bit1 : reset timestamp counters\r
-- bit2 : Enable data taking \r
-- bit3 : Disable data taking\r
--- bit4 : Enable Aurora interface to Computer Node\r
- constant ADDRESS_MUX_HISTOGRAM : std_logic_vector(23 downto 0) := x"800004";\r
+-- bit4 : Enable data to Compute Node\r
+-- bit5 : Enable waveforms to Compute Node\r
+-- bit6 : Select multiplexer status from waveform instead of pulses\r
+-- bit7 : Enable external SODA\r
+-- bit8 : Reset fibers to FEE\r
+-- bit9 : Disable packet limit (minimum time for one packet to prevent UDP buffer overrun)\r
+ constant ADDRESS_MUX_HISTOGRAM : std_logic_vector(23 downto 0) := x"800004"; --(disabled)\r
-- settings for the histogram : \r
-- bit0 : clear the histogram\r
-- bit1 : start reading of the histogram\r
-- bit 17 : select 1 low/high combination instead of 1 adc channel\r
constant ADDRESS_MUX_SYSMON : std_logic_vector(23 downto 0) := x"80000c";\r
-- write to FPGA system monitor\r
--- bit 31 : slect read/write, write='0', read='1'\r
+-- bit 31 : select read/write, write='0', read='1'\r
-- bit 30 : reset/reconfigure FPGA system monitor\r
-- bit 22..16 : 7-bits address of FPGA system monitor\r
-- bit 15..0 : 16-bits data for FPGA system monitor\r
-- bit 15..0 : data from FPGA system monitor\r
constant ADDRESS_MUX_CROSSSWITCH : std_logic_vector(23 downto 0) := x"80000d";\r
-- write to cross switch configuration\r
--- bit 7..0 : selected multiplexer input\r
--- bit 15..8 : ADC-channel to switch to selected multiplexer input (fibernr*NROFADCS+adcnumber or fibernr*NROFADCS/2+adcnumber/2 if high/low gain ADCs are used)\r
--- bit 16 : select if selected multiplexer input will be combined with neighbour (only for even inputs)\r
--- bit 31 : write to configuration register (extra check)\r
+-- bit 31..0 : corresponding ADC input will be combined with the same ADC input channel on the neighbouring ADC board\r
constant ADDRESS_MUX_ENERGYCORRECTION : std_logic_vector(23 downto 0) := x"80000e";\r
-- energy correction Look Up Table\r
-- bit 15..0 : gain correction (multiplying factor shifted by number of scalingsbits)\r
-- addresses slowcontrol commands for Multiplexer\r
constant ADDRESS_BOARDNUMBER : std_logic_vector(23 downto 0) := x"002000";\r
-- bit11..0 = sets the unique boardnumber\r
--- bit31 = initialize all FEE registers that have been set\r
+-- bit31 = initialize all FEE registers that have been set from the shadow registers in the Data Concentrator\r
\r
-- addresses slowcontrol commands for Front End Electronics board\r
+-- address 0..FEESLOWCONTROLBOARDADDRESS-1 are the addresses for each ADC channel.\r
+-- even numbered addresses contains register_A, odd numbered registers contains register_B\r
+-- board_register A: write\r
+-- register_A(7..0) = threshold High\r
+-- register_A(15..8) = threshold Low\r
+-- register_A(16) = disable High\r
+-- register_A(17) = disable Low\r
+-- register_A(23..18) = I/Max discard\r
+-- register_A(29..24) = I/Max pileup\r
+-- register_A(30) = enable raw data in waveform instead of baseline corrected data
+-- board_register B: write\r
+-- register_B(7..0) = minimum pulselength\r
+-- register_B(15..8) = pileup length\r
+-- register_B(23..16) = maximum wavelength\r
+-- register_B(24) = fullsize High\r
+-- register_B(25) = fullsize Low\r
+-- register_B(29..26) = CF delay\r
constant ADDRESS_FEE_CONTROL : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS,8);\r
-- bit0: reset all\r
+-- bit1: invert ADC signals\r
-- bit2: clear errors\r
-- bit3: enable waveforms\r
--- bit 17..16 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read\r
--- bit 18 = reset/initializes FPGA System monitor\r
- constant ADDRESS_FEE_STATUS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+1,8);\r
+-- bit20..16 = select channel for frequency measurement\r
+-- bit 21 = reset/initializes FPGA System monitor\r
+-- bit 23..22 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read\r
+ constant ADDRESS_FEE_STATUS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+1*NROFFEEFPGAS,8);\r
+-- write:\r
+-- bit4..0 : MWD width, depends on MWD_WIDTHBITS\r
+-- bit26..16 : lowest part of MWD tau factor, depends on MWD_TAUBITS\r
+-- read:\r
-- bit1 : Data Taken enabled (enable and disabled is done with SODA packets)\r
-- bit 5..4 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare\r
-- bit 15..6 = ADC value from FPGA System monitor\r
-- bit17 : error : receive data error (slowcontrol)\r
-- bit18 : error : slowcontrol buffer overrun\r
-- bit19 : error : not used\r
--- bit20 : error : transmit data error, multipleser error\r
+-- bit20 : error : transmit data error, multiplexer error\r
-- bit21 : error : receive data buffer overrun\r
-- bit22 : error : adc data buffer overrun\r
-- bit23 : error : receive fiber not locked\r
- constant ADDRESS_FEE_SLOWCONTROLERROR : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+2,8);\r
+ constant ADDRESS_FEE_SLOWCONTROLERROR : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+2*NROFFEEFPGAS,8);\r
-- data not important; this slowcontrol command indicates buffer full\r
- constant ADDRESS_FEE_MEASURE_FREQUENCY : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+3,8);\r
+ constant ADDRESS_FEE_MEASURE_FREQUENCY : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+3*NROFFEEFPGAS,8);\r
-- bit31..0 : number of hits in one second\r
- constant ADDRESS_FEE_REQUESTALLREGISTERS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+4,8);\r
+ constant ADDRESS_FEE_REQUESTALLREGISTERS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+4*NROFFEEFPGAS,8);\r
\r
type array_muxregister_type is array(0 to NROFMUXREGS-1) of std_logic_vector(31 downto 0);\r
\r
- type array_adc_type is array(0 to NROFADCS-1) of std_logic_vector(ADCBITS-1 downto 0);
- type array_adc64bits_type is array(0 to NROFADCS-1) of std_logic_vector(63 downto 0);\r
- type array_adc48bits_type is array(0 to NROFADCS-1) of std_logic_vector(47 downto 0);\r
- type array_adc36bits_type is array(0 to NROFADCS-1) of std_logic_vector(35 downto 0);\r
- type array_adc32bits_type is array(0 to NROFADCS-1) of std_logic_vector(31 downto 0);\r
- type array_adc24bits_type is array(0 to NROFADCS-1) of std_logic_vector(23 downto 0);\r
- type array_adc16bits_type is array(0 to NROFADCS-1) of std_logic_vector(15 downto 0);\r
- type array_adc9bits_type is array(0 to NROFADCS-1) of std_logic_vector(8 downto 0);\r
- type array_adc8bits_type is array(0 to NROFADCS-1) of std_logic_vector(7 downto 0);\r
- type array_adc4bits_type is array(0 to NROFADCS-1) of std_logic_vector(3 downto 0);\r
-\r
- type array_halfadc36bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(35 downto 0);
- type array_halfadc32bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(31 downto 0);
- type array_halfadc16bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(15 downto 0);
- type array_halfadc9bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(8 downto 0);
- type array_halfadc8bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(7 downto 0);\r
+ type array_adc_type is array(0 to NROFFEEADCS-1) of std_logic_vector(ADCBITS-1 downto 0);
+ type array_adc64bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(63 downto 0);\r
+ type array_adc48bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(47 downto 0);\r
+ type array_adc36bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(35 downto 0);\r
+ type array_adc32bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(31 downto 0);\r
+ type array_adc24bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(23 downto 0);\r
+ type array_adc16bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(15 downto 0);\r
+ type array_adc9bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(8 downto 0);\r
+ type array_adc8bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(7 downto 0);\r
+ type array_adc4bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(3 downto 0);\r
+\r
+ type array_halfadc36bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(35 downto 0);
+ type array_halfadc32bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(31 downto 0);\r
+ type array_halfadc31bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(30 downto 0);\r
+ type array_halfadc16bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(15 downto 0);
+ type array_halfadc9bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(8 downto 0);
+ type array_halfadc8bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(7 downto 0);\r
\r
type array_fiber64bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(63 downto 0);\r
type array_fiber48bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(47 downto 0);\r
type array_fiber8bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(7 downto 0);\r
type array_fiber4bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(3 downto 0);\r
\r
- type array_DCadc36bits_type is array(0 to NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(35 downto 0);\r
- type array_fiberXadc36bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(35 downto 0);\r
- type array_fiberXadc16bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(15 downto 0);\r
+ type array_DCadc36bits_type is array(0 to NROFFEEADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(35 downto 0);\r
+ type array_fiberXadc36bits_type is array(0 to NROFFIBERS*(NROFFEEADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(35 downto 0);\r
+ type array_fiberXadc16bits_type is array(0 to NROFFIBERS*(NROFFEEADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(15 downto 0);\r
type twologarray_type is array(0 to 128) of natural;\r
constant twologarray : twologarray_type :=\r
(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,\r
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7);\r
- type array_fiberXadcCrossSwitch_type is array(0 to NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(twologarray(NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1))-1 downto 0);\r
+ type array_fiberXadcCrossSwitch_type is array(0 to NROFFIBERS*NROFFEEADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(twologarray(NROFFIBERS*NROFFEEADCS/(ADCINDEXSHIFT+1))-1 downto 0);\r
\r
----------------------------------------------------------------------------------\r
-- add_hamming_code_26_32\r
--- /dev/null
+------------------------------------------------------------
+-- Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
+-- Coder : Alex Claros F.
+-- Date : 15/May/2005.
+-- Notes : This implementation is based on the article
+-- 'Asynchronous FIFO in Virtex-II FPGAs'
+-- writen by Peter Alfke. This TechXclusive
+-- article can be downloaded from the
+-- Xilinx website. It has some minor modifications.
+-- Coder : Deepak Kumar Tala (Verilog)
+-- Translator: Alexander H Pham (VHDL)
+------------------------------------------------------------
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
+
+entity asyncfifo is
+ generic (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 4
+ );
+ port (
+ reset : in std_logic;
+ read_clock : in std_logic;
+ read_request : in std_logic;
+ data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+ write_clock : in std_logic;
+ write_request : in std_logic;
+ data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ valid : out std_logic
+ );
+end entity;
+
+
+architecture rtl of asyncfifo is
+ ----/Internal connections & variables------
+ constant FIFO_DEPTH : integer := 2**ADDR_WIDTH;
+
+ type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
+ signal Mem : RAM (0 to FIFO_DEPTH-1);
+
+ signal pNextWordToWrite :std_logic_vector (ADDR_WIDTH-1 downto 0);
+ signal pNextWordToRead :std_logic_vector (ADDR_WIDTH-1 downto 0);
+ signal EqualAddresses :std_logic;
+ signal NextWriteAddressEn :std_logic;
+ signal NextReadAddressEn :std_logic;
+ signal Set_Status :std_logic;
+ signal Rst_Status :std_logic;
+ signal Status :std_logic;
+ signal PresetFull :std_logic;
+ signal PresetEmpty :std_logic;
+ signal empty_i,full_i :std_logic;
+
+ component GrayCounter is
+ generic (
+ COUNTER_WIDTH : natural := ADDR_WIDTH
+ );
+ port (
+ GrayCount_out :out std_logic_vector (COUNTER_WIDTH-1 downto 0);
+ Enable_in :in std_logic; --Count enable.
+ Clear_in :in std_logic; --Count reset.
+ clk :in std_logic
+ );
+ end component;
+begin
+
+ --------------Code--------------/
+ --Data ports logic:
+ --(Uses a dual-port RAM).
+ --'data_out' logic:
+ process (read_clock) begin
+ if (rising_edge(read_clock)) then
+ if (read_request = '1' and empty_i = '0') then
+ data_out <= Mem(conv_integer(pNextWordToRead));
+ end if;
+ end if;
+ end process;
+
+ --'data_in' logic:
+ process (write_clock) begin
+ if (rising_edge(write_clock)) then
+ if (write_request = '1' and full_i = '0') then
+ Mem(conv_integer(pNextWordToWrite)) <= data_in;
+ end if;
+ end if;
+ end process;
+
+ --Fifo addresses support logic:
+ --'Next Addresses' enable logic:
+ NextWriteAddressEn <= write_request and (not full_i);
+ NextReadAddressEn <= read_request and (not empty_i);
+
+ --Addreses (Gray counters) logic:
+ GrayCounter_pWr : GrayCounter
+ port map (
+ GrayCount_out => pNextWordToWrite,
+ Enable_in => NextWriteAddressEn,
+ Clear_in => reset,
+ clk => write_clock
+ );
+
+ GrayCounter_pRd : GrayCounter
+ port map (
+ GrayCount_out => pNextWordToRead,
+ Enable_in => NextReadAddressEn,
+ Clear_in => reset,
+ clk => read_clock
+ );
+
+ --'EqualAddresses' logic:
+ EqualAddresses <= '1' when (pNextWordToWrite = pNextWordToRead) else '0';
+
+ --'Quadrant selectors' logic:
+ process (pNextWordToWrite, pNextWordToRead)
+ variable set_status_bit0 :std_logic;
+ variable set_status_bit1 :std_logic;
+ variable rst_status_bit0 :std_logic;
+ variable rst_status_bit1 :std_logic;
+ begin
+ set_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xnor pNextWordToRead(ADDR_WIDTH-1);
+ set_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xor pNextWordToRead(ADDR_WIDTH-2);
+ Set_Status <= set_status_bit0 and set_status_bit1;
+
+ rst_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xor pNextWordToRead(ADDR_WIDTH-1);
+ rst_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xnor pNextWordToRead(ADDR_WIDTH-2);
+ Rst_Status <= rst_status_bit0 and rst_status_bit1;
+ end process;
+
+ --'Status' latch logic:
+ process (Set_Status, Rst_Status, reset) begin--D Latch w/ Asynchronous Clear & Preset.
+ if (Rst_Status = '1' or reset = '1') then
+ Status <= '0'; --Going 'Empty'.
+ elsif (Set_Status = '1') then
+ Status <= '1'; --Going 'Full'.
+ end if;
+ end process;
+
+ --'full' logic for the writing port:
+ PresetFull <= Status and EqualAddresses; --'Full' Fifo.
+
+ process (write_clock, PresetFull) begin --D Flip-Flop w/ Asynchronous Preset.
+ if (PresetFull = '1') then
+ full_i <= '1';
+ elsif (rising_edge(write_clock)) then
+ full_i <= '0';
+ end if;
+ end process;
+ full <= full_i;
+
+ --'empty' logic for the reading port:
+ PresetEmpty <= not Status and EqualAddresses; --'Empty' Fifo.
+
+ process (read_clock, PresetEmpty) begin --D Flip-Flop w/ Asynchronous Preset.
+ if (PresetEmpty = '1') then
+ empty_i <= '1';
+ elsif (rising_edge(read_clock)) then
+ empty_i <= '0';
+ end if;
+ end process;
+
+ empty <= empty_i;
+
+ process (read_clock) begin
+ if (rising_edge(read_clock)) then
+ if (empty_i='0') and (NextReadAddressEn='1') then
+ valid <= '1';
+ else
+ valid <= '0';
+ end if;
+ end if;
+ end process;
+end architecture;
\ No newline at end of file
end iirfilter_1order_selectBW;
architecture Behavioral of iirfilter_1order_selectBW is
-signal data_x_BW : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
-signal data_out_unscaled_delayed : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
-signal data_out_multiplied : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+signal data_x_BW : std_logic_vector((ADCBITS+BWBITS-1)downto 0); --// := (others => '0');
+signal data_out_unscaled_delayed : std_logic_vector((ADCBITS+BWBITS-1) downto 0); --// := (others => '0');
+signal data_out_multiplied : std_logic_vector((ADCBITS+BWBITS-1) downto 0); --// := (others => '0');
signal BWidx_i : integer range 0 to 7 := 0;
begin
variable data_out_unscaled : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
begin
if rising_edge(clock) then
- if reset='1' then
- data_out_unscaled_delayed((ADCBITS+BWBITS-1) downto BWBITS) <= data_in;
- data_out_unscaled_delayed((BWBITS-1) downto 0) <= (others => '0');
- data_out_multiplied(BWidx_i-1 downto 0) <= (others => '0');
- data_out_multiplied(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
- data_x_BW <= (others => '0');
- data_x_BW(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
- data_out <= data_in;
- else
+ -- if reset='1' then
+ -- data_out_unscaled_delayed((ADCBITS+BWBITS-1) downto BWBITS) <= data_in;
+ -- data_out_unscaled_delayed((BWBITS-1) downto 0) <= (others => '0');
+ -- data_out_multiplied(BWidx_i-1 downto 0) <= (others => '0');
+ -- data_out_multiplied(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+ -- data_x_BW <= (others => '0');
+ -- data_x_BW(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+ -- data_out <= data_in;
+ -- else
if inhibit='0' then
data_out_unscaled := data_x_BW + data_out_unscaled_delayed-data_out_multiplied;
data_out_unscaled_delayed <= data_out_unscaled;
data_out <= data_out_unscaled((ADCBITS+BWBITS-1) downto BWBITS);
end if;
- end if;
+-- end if;
end if;
end process;\r
-BWidx_i <= conv_integer(unsigned(BWidx));
+BWidx_i <= 0; --// conv_integer(unsigned(BWidx));
end Behavioral;
--- /dev/null
+-----------------------------------------------------------------------------------
+-- posedge_async_to_pulse
+-- Makes pulse with duration 1 clock-cycle from async positive edge
+--
+-- inputs
+-- clock_in : clock input for input signal
+-- clock_out : clock input to synchronize to
+-- en_clk : clock enable
+-- signal_in : rising edge of this signal will result in pulse
+--
+-- output
+-- pulse : pulse output : one clock cycle '1'
+--
+-----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity posedge_async_to_pulse is
+ port (
+ clock_out : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end posedge_async_to_pulse;
+
+architecture behavioral of posedge_async_to_pulse is
+
+ signal qff1 : std_logic := '0';
+ signal qff2 : std_logic := '0';
+ signal qff3 : std_logic := '0';
+begin
+
+process (signal_in,qff3)
+begin
+ if qff3='1' then
+ qff1 <= '0';
+ elsif rising_edge(signal_in) then
+ qff1 <= '1';
+ end if;
+end process;
+
+
+process (clock_out)
+begin
+ if rising_edge(clock_out) then
+ if qff3='1' then
+ qff2 <= '0';
+ else
+ qff2 <= qff1;
+ end if;
+ if (qff2='1') and (qff3='0') then
+ pulse <= '1';
+ else
+ pulse <= '0';
+ end if;
+ qff3 <= qff2;
+ end if;
+end process;
+
+end behavioral;
+
----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
-- Engineer: Peter Schakel
-- Create Date: 22-02-2009
-- Module Name: shift_register
architecture behavior of shift_register is
type arrtype is array((2**depthbits-1) downto 0) of std_logic_vector((width-1) downto 0);
-signal mem : arrtype; -- := (others => (others => '0'));
+signal mem : arrtype := (others => (others => '0'));
signal outptr : std_logic_vector((depthbits-1) downto 0) := (others => '0');
signal mem_out : std_logic_vector((width-1) downto 0) := (others => '0');
signal lastreset : std_logic := '0';
attribute syn_ramstyle : string;
attribute syn_ramstyle of mem : signal is "block_ram";
+attribute ram_style: string;
+attribute ram_style of mem : signal is "block";
begin
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI-cart/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 22-02-2009
+-- Module Name: shift_register_small
+-- Description: Shifts data for an adjustable number of clock cycles
+----------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- shift_register_small
+-- Shifts data for an adjustable number of clock cycles
+--
+-- generics
+-- width : number of bits for the data to shift
+-- DEPTHBITS : number of bits for the number of clock cycles to shift
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- hold : hold all values
+-- data_in : data to shift
+-- depth : number of clock cycles to shift for
+--
+-- outputs
+-- data_out : shifted data
+--
+-- components
+-- blockmem : simple dual ported memory with 1 clock
+-- blockmem1x18_xilinx,blockmem2x18_xilinx,blockmem3x18_xilinx,blockmem4x18_xilinxblockmem5x18_xilinx : Xilinx dual ported memory
+--
+------------------------------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity shift_register_small is
+ generic (
+ WIDTH : natural := 16;
+ DEPTHBITS : natural := 9
+ );
+ port (
+ clock : in std_logic;
+ data_in : in std_logic_vector((width-1) downto 0);
+ depth : in std_logic_vector((DEPTHBITS-1) downto 0);
+ data_out : out std_logic_vector((width-1) downto 0));
+end shift_register_small;
+
+architecture behavior of shift_register_small is
+
+component blockmem is
+ generic (
+ ADDRESS_BITS : natural := DEPTHBITS;
+ DATA_BITS : natural := width
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)
+ );
+end component;
+
+COMPONENT blockmem1x18_xilinx
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+ );
+END COMPONENT;
+
+COMPONENT blockmem2x18_xilinx
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+ );
+END COMPONENT;
+
+COMPONENT blockmem3x18_xilinx
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+ );
+END COMPONENT;
+
+COMPONENT blockmem4x18_xilinx
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+ );
+END COMPONENT;
+
+COMPONENT blockmem5x18_xilinx
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+ );
+END COMPONENT;
+
+type arrtype is array((2**DEPTHBITS-1) downto 0) of std_logic_vector((width-1) downto 0);
+signal mem : arrtype := (others => (others => '0'));
+signal outptr_S : std_logic_vector((DEPTHBITS-1) downto 0) := (others => '0');
+signal memadr_S : std_logic_vector((DEPTHBITS-1) downto 0) := (others => '0');
+
+signal mem_in_S : std_logic_vector(17 downto 0) := (others => '0');
+signal mem_out_S : std_logic_vector(17 downto 0) := (others => '0');
+
+attribute syn_ramstyle : string;
+attribute syn_ramstyle of mem : signal is "block_ram";
+attribute ram_style: string;
+attribute ram_style of mem : signal is "block";
+
+begin
+
+gen_others: if (DEPTHBITS>5) or (DEPTHBITS>18) generate
+ blockmem1: blockmem port map(
+ clock => clock,
+ write_enable => '1',
+ write_address => memadr_S,
+ data_in => data_in,
+ read_address => outptr_S,
+ data_out => data_out);
+end generate;
+
+
+mem_in_S(width-1 downto 0) <= data_in;
+data_out <= mem_out_S(width-1 downto 0);
+
+gen_1x18: if (DEPTHBITS=1) and (DEPTHBITS<=18) generate
+ blockmem1: blockmem1x18_xilinx port map(
+ clka => clock,
+ wea => (others => '1'),
+ addra => memadr_S,
+ dina => mem_in_S,
+ clkb => clock,
+ addrb => outptr_S,
+ doutb => mem_out_S);
+end generate;
+
+gen_2x18: if (DEPTHBITS=2) and (DEPTHBITS<=18) generate
+ blockmem1: blockmem2x18_xilinx port map(
+ clka => clock,
+ wea => (others => '1'),
+ addra => memadr_S,
+ dina => mem_in_S,
+ clkb => clock,
+ addrb => outptr_S,
+ doutb => mem_out_S);
+end generate;
+
+gen_3x18: if (DEPTHBITS=3) and (DEPTHBITS<=18) generate
+ blockmem1: blockmem3x18_xilinx port map(
+ clka => clock,
+ wea => (others => '1'),
+ addra => memadr_S,
+ dina => mem_in_S,
+ clkb => clock,
+ addrb => outptr_S,
+ doutb => mem_out_S);
+end generate;
+
+gen_4x18: if (DEPTHBITS=4) and (DEPTHBITS<=18) generate
+ blockmem1: blockmem4x18_xilinx port map(
+ clka => clock,
+ wea => (others => '1'),
+ addra => memadr_S,
+ dina => mem_in_S,
+ clkb => clock,
+ addrb => outptr_S,
+ doutb => mem_out_S);
+end generate;
+
+gen_5x18: if (DEPTHBITS=5) and (DEPTHBITS<=18) generate
+ blockmem1: blockmem5x18_xilinx port map(
+ clka => clock,
+ wea => (others => '1'),
+ addra => memadr_S,
+ dina => mem_in_S,
+ clkb => clock,
+ addrb => outptr_S,
+ doutb => mem_out_S);
+end generate;
+
+
+memadr_S <= outptr_S+depth;
+process (clock)
+begin
+ if rising_edge(clock) then
+ outptr_S <= outptr_S+1;
+ end if;
+end process;
+
+
+end behavior;
+++ /dev/null
------------------------------------------------------------------------------------------------
--- © Copyright 2007 - 2011, Xilinx, Inc. All rights reserved.
--- This file contains confidential and proprietary information of Xilinx, Inc. and is
--- protected under U.S. and international copyright and other intellectual property laws.
------------------------------------------------------------------------------------------------
---
--- Disclaimer:
--- This disclaimer is not a license and does not grant any rights to the materials
--- distributed herewith. Except as otherwise provided in a valid license issued to you
--- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
--- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
--- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
--- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
--- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
--- negligence, or under any other theory of liability) for any loss or damage of any
--- kind or nature related to, arising under or in connection with these materials,
--- including for any direct, or any indirect, special, incidental, or consequential
--- loss or damage (including loss of data, profits, goodwill, or any type of loss or
--- damage suffered as a result of any action brought by a third party) even if such
--- damage or loss was reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-safe, or for use in any
--- application requiring fail-safe performance, such as life-support or safety devices
--- or systems, Class III medical devices, nuclear facilities, applications related to
--- the deployment of airbags, or any other applications that could lead to death,
--- personal injury, or severe property or environmental damage (individually and
--- collectively, "Critical Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical Applications, subject only to
--- applicable laws and regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
---
--- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778
--- ____ ____
--- / /\/ /
--- /___/ \ / Vendor: Xilinx
--- \ \ \/ Version:
--- \ \ Filename: AdcData.vhd
--- / / Date Last Modified: 15 Feb 2011
--- /___/ /\ Date Created: 18 Dec 2007
--- \ \ / \
--- \___\/\___\
---
--- Device: Virtex-6
--- Author: Marc Defossez
--- Entity Name: AdcData
--- Purpose: 2-channel ADC data receiver interface.
--- The output of this module is alwasy fprmatted in 32-bit.
--- When the interface is for a 12-bit ADC then the output is formatted as:
--- 32 ---------- 16 , 15 ----------- 0
--- 0000 & (12-bit) , 0000 & (12-bit)
--- When the interface is for 14-bit or 16-bit the the ouput is formatted as:
--- 32 ---------- 16 , 15 ----------- 0
--- ( 16-bit ) , ( 16-bit )
--- In 1-wire mode the 32-bit output shows two channels
--- In 2-wire mode the 32-bit output shows two words of the same channel.
---
--- Tools: ISE_11.2.xx
--- Limitations: none
---
--- Revision History:
--- Rev 21 Jun 09
--- Adaption to Virtex-6
--- Rev 20 Oct 09
--- Removal of the input buffers.
--- FPGA is placed in a different hierarchical level for easyness of portability.
--- Rev 28 Oct 09
--- Removal of two mode options.
--- C_AdcBytOrBitMode and C_AdcMsbOrLsbFst are now coded as default BYTE MODE and MSB FIRST
--- This can still be changed by making the generics again available at higher HDL levels.
--- Rev 09 Dec 2010
--- Made sure the output of the interface is always FFs with enable.
--- Therefore instantiated the FFs in staid of using plain VHDL descriptions.
--- Rev 15 Feb 2011
--- Review of implementation of the AdcData hierarchical level.
---
------------------------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port: "*_i"
--- device pins: "*_pin"
--- ports: "- Names begin with Uppercase"
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------------------------
---
-library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.std_logic_UNSIGNED.all;
-library UNISIM;
- use UNISIM.VCOMPONENTS.all;
------------------------------------------------------------------------------------------------
--- Entity pin description
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-entity AdcData is
- generic (
- C_AdcBits : integer := 16; -- Can be 12, 14 or 16
- C_AdcBytOrBitMode : integer := 0; -- 1 = BIT mode, 0 = BYTE mode,
- C_AdcMsbOrLsbFst : integer := 0; -- 0 = MSB first, 1 = LSB first
- C_AdcWireInt : integer := 1 -- 1 = 1-wire, 2 = 2-wire.
- );
- port (
- DatD0_n : in std_logic;
- DatD0_p : in std_logic;
- DatD1_n : in std_logic;
- DatD1_p : in std_logic;
- DatClk : in std_logic;
- DatClkDiv : in std_logic;
- DatRst : in std_logic;
- DatEna : in std_logic;
- DatDone : in std_logic;
- DatBitSlip_p : in std_logic;
- DatBitSlip_n : in std_logic;
- DatSwapMux : in std_logic;
- DatMsbRegEna : in std_logic;
- DatLsbRegEna : in std_logic;
- DatReSync : in std_logic;
- DatOut : out std_logic_vector(31 downto 0)
- );
-end AdcData;
------------------------------------------------------------------------------------------------
--- Arcitecture section
------------------------------------------------------------------------------------------------
-architecture AdcData_struct of AdcData is
------------------------------------------------------------------------------------------------
--- Component Instantiation
------------------------------------------------------------------------------------------------
--- Components are instantiated through library naming.
------------------------------------------------------------------------------------------------
--- Constants, Signals and Attributes Declarations
------------------------------------------------------------------------------------------------
--- Functions
--- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
--- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
--- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
-function DatBits (Bits : integer) return integer is
-variable Temp : integer;
-begin
- if (Bits = 12) then
- Temp := 12;
- elsif (Bits = 14) then
- Temp := 16;
- elsif (Bits = 16) then
- Temp := 16;
- end if;
-return Temp;
-end function DatBits;
--- Constants
-constant IntIsrdsDataWidth : integer := DatBits(C_AdcBits)/4;
-constant Low : std_logic := '0';
-constant High : std_logic := '1';
--- Signals
-signal IntDatClk : std_logic;
-signal IntDatClk_n : std_logic;
---
--- ADC resolution = 12-bit: IntDatSrds0Out(5 downto 0) and IntDatSrds1Out(5 downto 0)
--- ADC resolution = 14-bit or 16-bit: IntDatSrds0Out(7 downto 0) and IntDatSrds1Out(7 downto 0)
-signal IntDatSrds0Out : std_logic_vector(7 downto 0);
-signal IntDatSrds1Out : std_logic_vector(7 downto 0);
-signal IntDatSrds0 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDatSrds1 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat0 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat1 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat0Mux : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat1Mux : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat0Swp : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat1Swp : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDatSwpBus : std_logic_vector(31 downto 0);
-signal IntDatDone : std_logic;
-signal IntDatEna : std_logic;
--- Attributes
------------------------------------------------------------------------------------------------
-begin
---
--- DatRst en DatEna are synchronised to DatClkDiv on a higher hierarchical level.
--- the higher level is "AdcToplevel".
-AdcData_Done_PROCESS : process (DatClkDiv, DatRst)
-begin
- if (DatRst = High) then
- IntDatDone <= Low;
- elsif (DatClkDiv'event and DatClkDiv = '1') then
- IntDatDone <= DatDone;
- end if;
-end process;
--- "IntDatDone" enables the ISERDES.
--- "IntDatEna" is the enable for the logic behind the ISERDES.
---
-IntDatEna <= High when (IntDatDone = High and DatEna = High) else Low;
------------------------------------------------------------------------------------------------
-IntDatClk <= DatClk; -- CLOCK FOR P-side ISERDES
-IntDatClk_n <= not DatClk; -- CLOCK FOR N_side ISERDES
------------------------------------------------------------------------------------------------
--- ISERDES for channel ZERO
------------------------------------------------------------------------------------------------
-AdcData_I_Isrds_D0_p : ISERDESE1
- generic map (
- SERDES_MODE => "MASTER", --
- INTERFACE_TYPE => "NETWORKING", --
- IOBDELAY => "NONE", --
- DATA_RATE => "SDR", --
- DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
- DYN_CLKDIV_INV_EN => FALSE, --
- DYN_CLK_INV_EN => FALSE, --
- NUM_CE => 1, --
- OFB_USED => FALSE --
- )
- port map (
- D => DatD0_p, -- in
- DDLY => Low, -- in
- DYNCLKDIVSEL => Low, -- in
- DYNCLKSEL => Low, -- in
- OFB => Low, -- in
- BITSLIP => DatBitSlip_p,-- in
- CE1 => IntDatDone, -- in
- CE2 => Low, -- in
- RST => DatRst, -- in
- CLK => IntDatClk, -- in
- CLKB => Low, -- in
- CLKDIV => DatClkDiv, -- in
- OCLK => Low, -- in
- SHIFTOUT1 => open, -- out
- SHIFTOUT2 => open, -- out
- O => open, -- out
- Q1 => IntDatSrds0Out(6), -- out (0)
- Q2 => IntDatSrds0Out(4), -- out (2)
- Q3 => IntDatSrds0Out(2), -- out (4)
- Q4 => IntDatSrds0Out(0), -- out (6)
- Q5 => open, -- out
- Q6 => open, -- out
- SHIFTIN1 => Low, -- in
- SHIFTIN2 => Low -- in
- );
-AdcData_I_Isrds_D0_n : ISERDESE1
- generic map (
- SERDES_MODE => "MASTER", --
- INTERFACE_TYPE => "NETWORKING", --
- IOBDELAY => "NONE", --
- DATA_RATE => "SDR", --
- DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
- DYN_CLKDIV_INV_EN => FALSE, --
- DYN_CLK_INV_EN => FALSE, --
- NUM_CE => 1, --
- OFB_USED => FALSE --
- )
- port map (
- D => DatD0_n, -- in
- DDLY => Low, -- in
- DYNCLKDIVSEL => Low, -- in
- DYNCLKSEL => Low, -- in
- OFB => Low, -- in
- BITSLIP => DatBitSlip_n,-- in
- CE1 => IntDatDone, -- in
- CE2 => Low, -- in
- RST => DatRst, -- in
- CLK => IntDatClk_n, -- in
- CLKB => Low, -- in
- CLKDIV => DatClkDiv, -- in
- OCLK => Low, -- in
- SHIFTOUT1 => open, -- out
- SHIFTOUT2 => open, -- out
- O => open, -- out
- Q1 => IntDatSrds0Out(7), -- out (1)
- Q2 => IntDatSrds0Out(5), -- out (3)
- Q3 => IntDatSrds0Out(3), -- out (5)
- Q4 => IntDatSrds0Out(1), -- out (7)
- Q5 => open, -- out
- Q6 => open, -- out
- SHIFTIN1 => Low, -- in
- SHIFTIN2 => Low -- in
- );
------------------------------------------------------------------------------------------------
--- ISERDES for channel ONE
------------------------------------------------------------------------------------------------
-AdcData_I_Isrds_D1_p : ISERDESE1
- generic map (
- SERDES_MODE => "MASTER", --
- INTERFACE_TYPE => "NETWORKING", --
- IOBDELAY => "NONE", --
- DATA_RATE => "SDR", --
- DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
- DYN_CLKDIV_INV_EN => FALSE, --
- DYN_CLK_INV_EN => FALSE, --
- NUM_CE => 1, --
- OFB_USED => FALSE --
- )
- port map (
- D => DatD1_p, -- in
- DDLY => Low, -- in
- DYNCLKDIVSEL => Low, -- in
- DYNCLKSEL => Low, -- in
- OFB => Low, -- in
- BITSLIP => DatBitSlip_p,-- in
- CE1 => IntDatDone, -- in
- CE2 => Low, -- in
- RST => DatRst, -- in
- CLK => IntDatClk, -- in
- CLKB => Low, -- in
- CLKDIV => DatClkDiv, -- in
- OCLK => Low, -- in
- SHIFTOUT1 => open, -- out
- SHIFTOUT2 => open, -- out
- O => open, -- out
- Q1 => IntDatSrds1Out(6), -- out (0)
- Q2 => IntDatSrds1Out(4), -- out (2)
- Q3 => IntDatSrds1Out(2), -- out (4)
- Q4 => IntDatSrds1Out(0), -- out (6)
- Q5 => open, -- out
- Q6 => open, -- out
- SHIFTIN1 => Low, -- in
- SHIFTIN2 => Low -- in
- );
-AdcData_I_Isrds_D1_n : ISERDESE1
- generic map (
- SERDES_MODE => "MASTER", --
- INTERFACE_TYPE => "NETWORKING", --
- IOBDELAY => "NONE", --
- DATA_RATE => "SDR", --
- DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
- DYN_CLKDIV_INV_EN => FALSE, --
- DYN_CLK_INV_EN => FALSE, --
- NUM_CE => 1, --
- OFB_USED => FALSE --
- )
- port map (
- D => DatD1_n, -- in
- DDLY => Low, -- in
- DYNCLKDIVSEL => Low, -- in
- DYNCLKSEL => Low, -- in
- OFB => Low, -- in
- BITSLIP => DatBitSlip_n,-- in
- CE1 => IntDatDone, -- in
- CE2 => Low, -- in
- RST => DatRst, -- in
- CLK => IntDatClk_n, -- in
- CLKB => Low, -- in
- CLKDIV => DatClkDiv, -- in
- OCLK => Low, -- in
- SHIFTOUT1 => open, -- out
- SHIFTOUT2 => open, -- out
- O => open, -- out
- Q1 => IntDatSrds1Out(7), -- out (1)
- Q2 => IntDatSrds1Out(5), -- out (3)
- Q3 => IntDatSrds1Out(3), -- out (5)
- Q4 => IntDatSrds1Out(1), -- out (7)
- Q5 => open, -- out
- Q6 => open, -- out
- SHIFTIN1 => Low, -- in
- SHIFTIN2 => Low -- in
- );
------------------------------------------------------------------------------------------------
-Gen_1_DatBus : if (DatBits(C_AdcBits)/2) = 6 generate
-begin
- IntDatSrds0 <= not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
- not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
- not IntDatSrds0Out(1) & IntDatSrds0Out(0);
- IntDatSrds1 <= not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
- not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
- not IntDatSrds1Out(1) & IntDatSrds1Out(0);
-end generate;
-Gen_2_DatBus : if (DatBits(C_AdcBits)/2) = 8 generate
-begin
- IntDatSrds0 <= not IntDatSrds0Out(7) & IntDatSrds0Out(6) &
- not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
- not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
- not IntDatSrds0Out(1) & IntDatSrds0Out(0);
- IntDatSrds1 <= not IntDatSrds1Out(7) & IntDatSrds1Out(6) &
- not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
- not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
- not IntDatSrds1Out(1) & IntDatSrds1Out(0);
-end generate;
------------------------------------------------------------------------------------------------
--- DATA REGISTER
------------------------------------------------------------------------------------------------
-Gen_1_DatReg : for n in (DatBits(C_AdcBits)/2)-1 downto 0 generate
- AdcData_I_Fdce_Reg0 : FDCE
- generic map (INIT => '0') -- bit
- port map (D => IntDatSrds0(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
- Q => IntDat0(n));
- AdcData_I_Fdce_Reg1 : FDCE
- generic map (INIT => '0') -- bit
- port map (D => IntDatSrds1(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
- Q => IntDat1(n));
-end generate Gen_1_DatReg;
------------------------------------------------------------------------------------------------
--- BIT SWAP MULTIPLEXER and REGISTER
--- Swap the bits in correct order when the pattern detected is bit swapped.
------------------------------------------------------------------------------------------------
-Gen_2_DatMux : for n in (DatBits(C_AdcBits)/4)-1 downto 0 generate
-begin
- IntDat0Mux((n*2)+1) <= IntDat0(n*2) when (DatSwapMux = '1') else IntDat0((n*2)+1);
- IntDat0Mux(n*2) <= IntDat0((n*2)+1) when (DatSwapMux = '1') else IntDat0(n*2);
- IntDat1Mux((n*2)+1) <= IntDat1(n*2) when (DatSwapMux = '1') else IntDat1((n*2)+1);
- IntDat1Mux(n*2) <= IntDat1((n*2)+1) when (DatSwapMux = '1') else IntDat1(n*2);
-end generate Gen_2_DatMux;
-Gen_3_DatReg : for n in (DatBits(C_AdcBits)/2)-1 downto 0 generate
- AdcData_I_Fdce_Reg2 : FDCE
- generic map (INIT => '0') -- bit
- port map (D => IntDat0Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
- Q => IntDat0Swp(n));
- AdcData_I_Fdce_Reg3 : FDCE
- generic map (INIT => '0') -- bit
- port map (D => IntDat1Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
- Q => IntDat1Swp(n));
-end generate Gen_3_DatReg;
------------------------------------------------------------------------------------------------
--- 1-WIRE, 12x SERIALIZATION for 12-bit ADCs
--- The data from one ADC will show up in the output of one interface channel. It is so that the
--- 32-bit output of the interface shows both channels. Bits 31:16 show the upper channel and
--- bits 15:0 show the lower channel.
------------------------------------------------------------------------------------------------
-Gen_1w_12b : if (C_AdcBits = 12 and C_AdcWireInt = 1) generate
- -- 1-wire mode is only coded for BIT wise operation.
- Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
--- -- MSB first.
--- -- Output : 31 16 15 0
--- -- : "0000" & MSB(5:0) & LSB(5:0) "0000" & MSB(5:0) & LSB(5:0)
- IntDatSwpBus <= "0000" & IntDat1Swp(5 downto 0) & IntDat1Swp(5 downto 0) &
- "0000" & IntDat0Swp(5 downto 0) & IntDat0Swp(5 downto 0);
- Gen_1_H : for n in 6 to 15 generate
- I_Fdce_HH : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_HL : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_H;
- Gen_1_L : for n in 0 to 5 generate
- I_Fdce_LH : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_LL : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_L;
- end generate;
- Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
- -- LSB first.
- -- Output : 31 22 & 21 16 & 15 6 & 5 0
- -- : "0000" & LSB(0:5) & MSB(0:5) "0000" & LSB(0:5) & MSB(0:5)
- IntDatSwpBus <= "0000" & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & -- 31-|
- IntDat1Swp(3) & IntDat1Swp(4) & IntDat1Swp(5) & -- |-22
- IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & -- 21-|
- IntDat1Swp(3) & IntDat1Swp(4) & IntDat1Swp(5) & -- |-16
- "0000" & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & -- 15-|
- IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5) & -- |-6
- IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & -- 5-|
- IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5); -- |-0
- Gen_1_H : for n in 6 to 15 generate
- I_Fdce_HH : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_HL : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_H;
- Gen_1_L : for n in 0 to 5 generate
- I_Fdce_LH : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_LL : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_L;
- end generate;
-end generate;
------------------------------------------------------------------------------------------------
--- 2-WIRE, 12x SERIALIZATION for 12-bit ADCs
--- Only one of these options can be chosen at a time.
--- 2-wire, Msb-Bit or Msb-Byte
--- 2-wire, Lsb-Bit or Lsb-Byte
------------------------------------------------------------------------------------------------
-Gen_2w_12b : if (C_AdcBits = 12 and C_AdcWireInt = 2) generate
- Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
- -- Bit mode, MSB First
- -- Bit : 5 4 3 2 1 0
- -- Channel 0 : D10, D8, D6, D4, D2, D0
- -- Channel 1 : D11, D9, D7, D5, D3, D1
- -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
- -- : 0 0 0 0, 1_5, 0_5, 1_4, 0_4, 1_3, 0_3, 1_2, 0_2, 1_1, 0_1, 1_0, 0_0
- Gen_1_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
- IntDatSwpBus <= "0000"
- & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
- & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
- & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
- & "0000"
- & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
- & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
- & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0);
- Gen_1_HL : for n in 0 to 15 generate
- I_Fdce_H : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_L : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_HL;
- end generate;
- -- Byte mode, MSB First
- -- Bit : 5 4 3 2 1 0
- -- Channel 0 : D5, D4, D3, D2, D1, D0
- -- Channel 1 : D11, D10, D9, D8, D7, D6
- -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
- -- : 0 0 0 0, 1_5, 1_4, 1_3, 1_2, 1_1, 1_0, 0_5, 0_4, 0_3, 0_2, 0_1, 0_0
- Gen_1_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode
- IntDatSwpBus <= "0000"
- & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(3) & IntDat1Swp(2)
- & IntDat1Swp(1) & IntDat1Swp(0) & IntDat0Swp(5) & IntDat0Swp(4)
- & IntDat0Swp(3) & IntDat0Swp(2) & IntDat0Swp(1) & IntDat0Swp(0)
- & "0000"
- & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(3) & IntDat1Swp(2)
- & IntDat1Swp(1) & IntDat1Swp(0) & IntDat0Swp(5) & IntDat0Swp(4)
- & IntDat0Swp(3) & IntDat0Swp(2) & IntDat0Swp(1) & IntDat0Swp(0);
- Gen_1_HL : for n in 0 to 15 generate
- I_Fdce_H : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_L : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_HL;
- end generate;
- end generate;
---
- Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
- -- Bit mode, LSB First
- -- Bit : 5 4 3 2 1 0
- -- Channel 0 : D0, D2, D4, D6, D8, D10
- -- Channel 1 : D1, D3, D5, D7, D9, D11
- -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
- -- : 0 0 0 0, 1_0, 0_0, 1_1, 0_1, 1_2, 0_2, 1_3, 0_3, 1_4, 0_4, 1_5, 0_5
- Gen_1_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
- IntDatSwpBus <= "0000"
- & IntDat1Swp(0) & IntDat0Swp(0) & IntDat1Swp(1) & IntDat0Swp(1)
- & IntDat1Swp(2) & IntDat0Swp(2) & IntDat1Swp(3) & IntDat0Swp(3)
- & IntDat1Swp(4) & IntDat0Swp(4) & IntDat1Swp(5) & IntDat0Swp(5)
- & "0000"
- & IntDat1Swp(0) & IntDat0Swp(0) & IntDat1Swp(1) & IntDat0Swp(1)
- & IntDat1Swp(2) & IntDat0Swp(2) & IntDat1Swp(3) & IntDat0Swp(3)
- & IntDat1Swp(4) & IntDat0Swp(4) & IntDat1Swp(5) & IntDat0Swp(5);
- Gen_1_HL : for n in 0 to 15 generate
- I_Fdce_H : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_L : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_HL;
- end generate;
- -- Byte Mode, LSB First
- -- Bit : 5 4 3 2 1 0
- -- Channel 0 : D0, D1, D2, D3, D4, D5
- -- Channel 1 : D6, D7, D8, D9, D10, D11
- -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
- -- : 0 0 0 0, 1_0, 1_1, 1_2, 1_3, 1_4, 1_5, 0_0, 0_1, 0_2, 0_3, 0_4, 0_5
- Gen_1_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode
- IntDatSwpBus <= "0000"
- & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
- & IntDat1Swp(4) & IntDat1Swp(5) & IntDat0Swp(0) & IntDat0Swp(1)
- & IntDat0Swp(2) & IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5)
- & "0000"
- & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
- & IntDat1Swp(4) & IntDat1Swp(5) & IntDat0Swp(0) & IntDat0Swp(1)
- & IntDat0Swp(2) & IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5);
- Gen_1_HL : for n in 0 to 15 generate
- I_Fdce_H : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_L : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_HL;
- end generate;
- end generate;
-end generate;
------------------------------------------------------------------------------------------------
--- 1-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
--- The data from one ADC will show up in the output of one interface channel. It is so that the
--- 32-bit output of the interface shows both channels. Bits 31:16 show the upper channel (CH_1)
--- and bits 15:0 show the lower (CH_0) channel.
------------------------------------------------------------------------------------------------
-Gen_1w_1416b : if (C_AdcBits /= 12 and C_AdcWireInt = 1) generate
- -- 1-wire is only coded for BIT wise operation
- Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
- IntDatSwpBus <= IntDat1Swp(7 downto 0) & IntDat1Swp(7 downto 0) &
- IntDat0Swp(7 downto 0) & IntDat0Swp(7 downto 0);
- Gen_1_HL : for n in 0 to 7 generate
- I_Fdce_HH : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+24), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+24));
- I_Fdce_HL : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+8), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+8));
- I_Fdce_LH : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_LL : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_HL;
- end generate;
- Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
- IntDatSwpBus <= IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3) &
- IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7) &
- IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3) &
- IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7) &
- IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) &
- IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(7) &
- IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) &
- IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(7);
- Gen_1_HL : for n in 0 to 7 generate
- I_Fdce_HH : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+24), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+24));
- I_Fdce_HL : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+8), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+8));
- I_Fdce_LH : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_LL : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_HL;
- end generate;
-end generate;
------------------------------------------------------------------------------------------------
--- 2-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
--- Only one of these options can be chosen at a time.
--- 2-wire, Msb-Bit or Msb-Byte
--- 2-wire, Lsb-Bit or Lsb-Byte
------------------------------------------------------------------------------------------------
-Gen_1416Bit : if (C_AdcBits /= 12 and C_AdcWireInt = 2) generate
--- Shift in order is assumed MSB first.
- Gen_2_Msb : if C_AdcMsbOrLsbFst = 0 generate
- -- Bit mode, MSB First, 14-bits (16-bits)
- -- Bit : 7, 6, 5, 4, 3, 2, 1, 0
- -- Channel 0 : 0/(D14), D12, D10, D8, D6, D4, D2, D0
- -- Channel 1 : 0/(D15), D13, D11, D9, D7, D5, D3, D1
- Gen1_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
- IntDatSwpBus <= IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
- & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
- & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
- & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
- & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
- & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
- & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
- & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2);
- Gen_1_H : for n in 0 to 15 generate
- I_Fdce_H : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_L : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_H;
- end generate;
- -- Byte Mode, MSB First, 14-bits (16-bits)
- -- Data Bit : 7, 6, 5, 4, 3, 2, 1, 0,
- -- Channel 0 : D7, D6, D5, D4, D3, D2, D1, D0,
- -- Channel 1 : 0/(D15), 0/(D14), D13, D12, D11, D10, D9, D8
- Gen1_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode (not tested)
- IntDatSwpBus <= IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(7) & IntDat1Swp(6)
- & IntDat1Swp(1) & IntDat1Swp(0) & IntDat1Swp(3) & IntDat1Swp(2)
- & IntDat0Swp(5) & IntDat0Swp(4) & IntDat0Swp(7) & IntDat0Swp(6)
- & IntDat0Swp(1) & IntDat0Swp(0) & IntDat0Swp(3) & IntDat0Swp(2)
- & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(7) & IntDat1Swp(6)
- & IntDat1Swp(1) & IntDat1Swp(0) & IntDat1Swp(3) & IntDat1Swp(2)
- & IntDat0Swp(5) & IntDat0Swp(4) & IntDat0Swp(7) & IntDat0Swp(6)
- & IntDat0Swp(1) & IntDat0Swp(0) & IntDat0Swp(3) & IntDat0Swp(2);
- Gen_1_H : for n in 0 to 15 generate
- I_Fdce_H : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_L : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_H;
- end generate;
- end generate;
--- Shift in order is assumed LSB first
- Gen_2_Lsb : if C_AdcMsbOrLsbFst = 1 generate
- -- Bit mode, LSB First, 14-bits (16-bit)
- -- Data Bit ; 7, 6, 5, 4, 3, 2, 1, 0
- -- Channel 0 : D0, D2, D4, D6, D8, D10, D12, 0/(D14)
- -- Channel 1 : D1, D3, D5, D7, D9, D11, D13, 0/(D15)
- Gen_2_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
- IntDatSwpBus <= IntDat0Swp(2) & IntDat1Swp(2) & IntDat0Swp(3) & IntDat1Swp(3)
- & IntDat0Swp(0) & IntDat1Swp(0) & IntDat0Swp(1) & IntDat1Swp(1)
- & IntDat0Swp(6) & IntDat1Swp(6) & IntDat0Swp(7) & IntDat1Swp(7)
- & IntDat0Swp(4) & IntDat1Swp(4) & IntDat0Swp(5) & IntDat1Swp(5)
- & IntDat0Swp(2) & IntDat1Swp(2) & IntDat0Swp(3) & IntDat1Swp(3)
- & IntDat0Swp(0) & IntDat1Swp(0) & IntDat0Swp(1) & IntDat1Swp(1)
- & IntDat0Swp(6) & IntDat1Swp(6) & IntDat0Swp(7) & IntDat1Swp(7)
- & IntDat0Swp(4) & IntDat1Swp(4) & IntDat0Swp(5) & IntDat1Swp(5);
- Gen_1_H : for n in 0 to 15 generate
- I_Fdce_H : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_L : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_H;
- end generate;
- -- Byte Mode, LSB First, 14-bits (16-bit)
- -- Data Bit : 7, 6, 5, 4, 3, 2, 1, 0
- -- Channel 0 : D0, D1, D2, D3, D4, D5, D6, D7
- -- Channel 1 : D8, D9, D10, D11, D12, D13, 0/(D14), 0/(D15)
- Gen_2_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode (not tested)
- IntDatSwpBus <= IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
- & IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7)
- & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3)
- & IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(6)
- & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
- & IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7)
- & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3)
- & IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(6);
- Gen_1_H : for n in 0 to 15 generate
- I_Fdce_H : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n+16));
- I_Fdce_L : FDCE
- generic map (INIT => '0')
- port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
- CLR => DatReSync, Q => DatOut(n));
- end generate Gen_1_H;
- end generate;
- end generate;
-end generate;
---
------------------------------------------------------------------------------------------------
-end AdcData_struct;
\ No newline at end of file
+++ /dev/null
------------------------------------------------------------------------------------------------\r
--- © Copyright 2007 - 2011, Xilinx, Inc. All rights reserved.\r
--- This file contains confidential and proprietary information of Xilinx, Inc. and is\r
--- protected under U.S. and international copyright and other intellectual property laws.\r
------------------------------------------------------------------------------------------------\r
---\r
--- Disclaimer:\r
--- This disclaimer is not a license and does not grant any rights to the materials\r
--- distributed herewith. Except as otherwise provided in a valid license issued to you\r
--- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS\r
--- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL\r
--- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED\r
--- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR\r
--- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including\r
--- negligence, or under any other theory of liability) for any loss or damage of any\r
--- kind or nature related to, arising under or in connection with these materials,\r
--- including for any direct, or any indirect, special, incidental, or consequential\r
--- loss or damage (including loss of data, profits, goodwill, or any type of loss or\r
--- damage suffered as a result of any action brought by a third party) even if such\r
--- damage or loss was reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
---\r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-safe, or for use in any\r
--- application requiring fail-safe performance, such as life-support or safety devices\r
--- or systems, Class III medical devices, nuclear facilities, applications related to\r
--- the deployment of airbags, or any other applications that could lead to death,\r
--- personal injury, or severe property or environmental damage (individually and\r
--- collectively, "Critical Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical Applications, subject only to\r
--- applicable laws and regulations governing limitations on product liability.\r
---\r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. \r
---\r
--- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx\r
--- \ \ \/ Version: \r
--- \ \ Filename: AdcFrame.vhd\r
--- / / Date Last Modified: 29 Mar 11\r
--- /___/ /\ Date Created: 05 Oct 07\r
--- \ \ / \\r
--- \___\/\___\\r
--- \r
--- Device: Virtex-6\r
--- Author: Marc Defossez\r
--- Entity Name: AdcFrame\r
--- Purpose: This file is part of an FPGA interface for a Texas Instruments ADC.\r
--- Tools: ISE_13.1\r
--- Limitations: none\r
---\r
--- Revision History:\r
--- Rev. 28 Oct 2009\r
--- Corrected the circuit to check for "Bouble Nibble" at the output of the ISEDRES.\r
--- Made the reaction of this circuit immediate (asynchrounous).\r
--- Then synchronousity steps in after registering the signals.\r
--- Rev. 16 feb 2011\r
--- Replace HDL synthesized FFs by instantiated FFs for frame data path.\r
--- Check implementation results is ISE_12.4 with PlanAhead through a AdcFrame_Toplevel.\r
--- Rev 07 Mar 2011\r
--- Modified the calculation of some "generate" parameters to be able to work in 1-wire\r
--- and 2-wire mode. generate parameters to create sets of FFs.\r
--- Rev 09 Mar 2011\r
--- Problem solved with 1-wire interface not finding correct frame pattern.\r
--- In the past 1-wire and 2-wire was selected with 0 and 1 while for recent interfaces\r
--- this is changed to 1 and 2 (To reflect in the selection the interface type).\r
--- The function calculating the frame pattern for use with the comparator still used\r
--- the old selection style. Result was that 2-wire functioned normally and 1-wire\r
--- returned a all zero compare pattern.\r
--- Finalized the integration and documentation of the "DoubleNibbleDetect".\r
------------------------------------------------------------------------------------------------\r
--- Naming Conventions:\r
--- active low signals: "*_n"\r
--- clock signals: "clk", "clk_div#", "clk_#x"\r
--- reset signals: "rst", "rst_n"\r
--- generics: "C_*"\r
--- user defined types: "*_TYPE"\r
--- state machine next state: "*_ns"\r
--- state machine current state: "*_cs"\r
--- combinatorial signals: "*_com"\r
--- pipelined or register delay signals: "*_d#"\r
--- counter signals: "*cnt*"\r
--- clock enable signals: "*_ce"\r
--- internal version of output port: "*_i"\r
--- device pins: "*_pin"\r
--- ports: "- Names begin with Uppercase"\r
--- processes: "*_PROCESS"\r
--- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
------------------------------------------------------------------------------------------------\r
---\r
-library IEEE;\r
- use IEEE.std_logic_1164.all;\r
- use IEEE.std_logic_UNSIGNED.all;\r
- use IEEE.std_logic_textio.all;\r
- use std.textio.all;\r
-library UNISIM;\r
- use UNISIM.VCOMPONENTS.all;\r
-library AdcFrame_lib;\r
- use AdcFrame_lib.all;\r
---library AdcMem;\r
--- use AdcMem.all;\r
- \r
------------------------------------------------------------------------------------------------\r
--- Entity pin description\r
------------------------------------------------------------------------------------------------\r
------------------------------------------------------------------------------------------------\r
-entity AdcFrame is\r
- generic (\r
- C_AdcBits : integer;\r
- C_AdcWireInt : integer;\r
- C_FrmPattern : string\r
- );\r
- port (\r
- FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT\r
- FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT\r
- FrmClkRst : in std_logic;\r
- FrmClkEna : in std_logic;\r
- FrmClk : in std_logic;\r
- FrmClkDiv : in std_logic;\r
- FrmClkDone : in std_logic; -- Input from clock syncronisation.\r
- FrmClkReSync : in std_logic;\r
- FrmClkBitSlip_p : out std_logic;\r
- FrmClkBitSlip_n : out std_logic;\r
- FrmClkSwapMux : out std_logic;\r
- FrmClkMsbRegEna : out std_logic;\r
- FrmClkLsbRegEna : out std_logic;\r
- FrmClkReSyncOut : out std_logic;\r
- FrmClkDat : out std_logic_vector(15 downto 0);\r
- FrmClkSyncWarn : out std_logic;\r
- Frame_out : out std_logic;\r
- testOK : out std_logic;\r
- testword0 : out std_logic_vector(35 downto 0)
- );\r
-end AdcFrame;\r
------------------------------------------------------------------------------------------------\r
--- Architecture section\r
------------------------------------------------------------------------------------------------\r
-architecture AdcFrame_struct of AdcFrame is\r
------------------------------------------------------------------------------------------------\r
--- Component Instantiation\r
------------------------------------------------------------------------------------------------\r
------------------------------------------------------------------------------------------------\r
--- Constants, Signals and Attributes Declarations\r
------------------------------------------------------------------------------------------------\r
--- Functions\r
--- A std_logic_vector is converted to a string.\r
- function stdlvec_to_str(inp: std_logic_vector) return string is\r
- variable temp: string(inp'left+1 downto 1) := (others => 'X');\r
- begin\r
- for i in inp'reverse_range loop\r
- if (inp(i) = '1') then\r
- temp(i+1) := '1';\r
- elsif (inp(i) = '0') then\r
- temp(i+1) := '0'; \r
- end if;\r
- end loop;\r
- return temp;\r
- end function stdlvec_to_str;\r
---\r
--- A string is converted to a std_logic_vector.\r
- function str_to_stdlvec(Inp: string) return std_logic_vector is\r
- variable Temp : std_logic_vector(Inp'range) := (others => 'X');\r
- begin \r
- for i in Inp'range loop\r
- if (Inp(i) = '1') then\r
- Temp(i) := '1';\r
- elsif (Inp(i) = '0') then\r
- Temp(i) := '0'; \r
- end if;\r
- end loop;\r
- return Temp;\r
- end function str_to_stdlvec;\r
---\r
--- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.\r
--- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.\r
--- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.\r
- function FrmBits (Bits : integer) return integer is\r
- variable Temp : integer;\r
- begin\r
- if (Bits = 12) then\r
- Temp := 12;\r
- elsif (Bits = 14) then\r
- Temp := 16;\r
- elsif (Bits = 16) then\r
- Temp := 16;\r
- end if;\r
- return Temp;\r
- end function FrmBits;\r
---\r
--- Word symmetry check\r
--- A word (16-bit) is checked for bit pair symmetry\r
--- Example: In one byte there are 16 possible symmetry positions.\r
--- 00000000, 00000011, 00001100, 00001111,\r
--- 00110000, 00110011, 00111100, 00111111,\r
--- 11000000, 11000011, 11001100, 11001111,\r
--- 11110000, 11110011, 11111100, 11111111,\r
--- Bit_7=Bit_6, Bit_5=Bit_4, Bit_3=Bit_2, and Bit_1=Bit_0\r
- function SymChck (Inp: std_logic_vector) return std_logic is\r
- variable Temp : std_logic_vector ((Inp'left-1)/2 downto 0) := (others => '0');\r
- variable Sym : std_logic := '0';\r
- begin\r
- for n in (Inp'left-1)/2 downto 0 loop\r
- Temp(n) := Inp((n*2)+1) xor Inp(n*2);\r
- Sym := Temp(n) or Sym;\r
- end loop;\r
- assert false\r
- report CR & " Pattern XORed/ORed = " & stdlvec_to_str(Temp) & CR\r
- severity note;\r
- return Sym;\r
- end function SymChck;\r
---\r
--- When a symmetric byte, bit pattern is found, make the requested pattern rotate\r
--- by one bit to become a non-symmetric pattern. \r
- function BitShft(Inp: std_logic_vector; Wire: integer) return std_logic_vector is\r
- variable Temp : std_logic_vector (Inp'range):= (others => '0');\r
- begin\r
--- Bit shift all bits.\r
--- Example: 16-bit frame word = 11111111_00000000 or 00000000_11110000\r
--- After shifting the word returned looks as: 11111110_00000001 and 00000000_01111000\r
- if (SymChck(Inp) = '0') then\r
- if (Wire = 1 ) then -- 1-wire, shift 15-bits\r
- for n in Inp'left downto 0 loop\r
- if (n /= 0) then\r
- Temp(n) := Inp(n-1);\r
- elsif (n = 0) then\r
- Temp(Temp'right) := Inp(Inp'left);\r
- end if;\r
- end loop;\r
- else -- (Wire = 2) -- 2-wire, shift 8-bits\r
- for n in (Inp'left-8) downto 0 loop\r
- if (n /= 0) then\r
- Temp(n) := Inp(n-1);\r
- elsif (n = 0) then\r
- Temp(Temp'right) := Inp(Inp'left-8);\r
- end if;\r
- end loop;\r
- end if;\r
- elsif (SymChck(Inp) = '1') then\r
- -- Don't do anything, return the word as it came in.\r
- Temp := Inp;\r
- end if;\r
- --\r
- assert false\r
- report CR &\r
- " Pattern Shifted = " & stdlvec_to_str(Temp) & CR & \r
- " Comparator Value A = " & stdlvec_to_str(Temp(15 downto 8)) & CR &\r
- " Comparator Value B = " & stdlvec_to_str(Temp(7 downto 0)) & CR\r
- severity note;\r
- return Temp;\r
- end function BitShft;\r
---\r
--- Bit swap operation: \r
--- Bit n of the output string gets bit n-1 of the input. ex: out(7) <= In(6).\r
--- Bit n-1 of the output string gets bit n of the input. ex: out(6) <= In(7).\r
--- Bit n-2 of the output string gets bit n-3 of the input. ex: out(5) <= In(4).\r
--- Bit n-3 of the output string gets bit n-2 of the input. ex: out(4) <= In(5).\r
--- and etcetera....\r
--- This: Bit_7, Bit_6, Bit_5, Bit_4, Bit_3, Bit_2, Bit_1, Bit_0.\r
--- Results in: Bit_6, Bit_7, Bit-$, Bit_5, Bit_2, Bit_3, Bit_0, Bit_1.\r
- function BitSwap(Inp: std_logic_vector) return std_logic_vector is\r
- variable Temp : std_logic_vector (Inp'range);\r
- begin\r
- for n in (Inp'left-1)/2 downto 0 loop\r
- Temp((n*2)+1) := Inp(n*2);\r
- Temp(n*2) := Inp((n*2)+1);\r
- end loop;\r
- assert false\r
- report CR &\r
- " Pattern Bit Swapped = " & stdlvec_to_str(Temp) & CR &\r
- " Comparator Value C = " & stdlvec_to_str(Temp(15 downto 8)) & CR &\r
- " Comparator Value D = " & stdlvec_to_str(Temp(7 downto 0)) & CR \r
- severity note;\r
- return Temp;\r
- end function BitSwap;\r
---\r
- function TermOrNot (Term : integer) return boolean is\r
- begin\r
- if (Term = 0) then\r
- return FALSE;\r
- else\r
- return TRUE;\r
- end if;\r
- end TermOrNot;\r
- \r
-component DoubleNibbleDetect is
- port (
- Clock : in std_logic;
- RstIn : in std_logic;
- Final : out std_logic;
- DataIn : in std_logic_vector(3 downto 0);
- DataOut : out std_logic_vector(3 downto 0)
- );
-end component;
-
-component GenPulse is
- port (
- Clk : in std_logic;
- Ena : in std_logic;
- SigIn : in std_logic;
- SigOut : out std_logic
- );
-end component;\r
-\r
---\r
--- Constants\r
--- Transform the pattern STRING into a std_logic_vector.\r
-constant IntPattern :\r
- std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := str_to_stdlvec(C_FrmPattern);\r
--- Shift the pattern for one bit.\r
-constant IntPatternBitShifted :\r
- std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitShft(IntPattern, C_AdcWireInt);\r
--- Bit swap the by one bit shifted pattern.\r
-constant IntPatternBitSwapped :\r
- std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitSwap(IntPatternBitShifted);\r
--- Define the bytes for pattern comparison.\r
-constant IntPatternA : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=\r
- IntPatternBitShifted(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);\r
-constant IntPatternB : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=\r
- IntPatternBitShifted((FrmBits(C_AdcBits)/2)-1 downto 0);\r
-constant IntPatternC : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=\r
- IntPatternBitSwapped(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);\r
-constant IntPatternD : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=\r
- IntPatternBitSwapped((FrmBits(C_AdcBits)/2)-1 downto 0);\r
--- Calculate the data width for a ISERDES. \r
-constant IntIsrdsDataWidth : integer := FrmBits(C_AdcBits)/4;\r
-constant Low : std_logic := '0';\r
-constant High : std_logic := '1';\r
-attribute keep : string;\r
--- Signals\r
-signal IntFrmClk : std_logic;\r
-signal IntFrmClk_n : std_logic;\r
-signal IntFrmSrdsOut : std_logic_vector (7 downto 0);\r
---\r
-signal IntFrmSrdsDatEvn : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);\r
-signal IntFrmSrdsDatOdd : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);\r
-signal IntFrmSrdsDatEvn_d : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);\r
-signal IntFrmSrdsDatOdd_d : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);\r
-signal IntFrmSrdsDat : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);\r
-signal IntFrmDat : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);\r
-signal IntFrmDatMux : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);\r
-signal IntFrmDatSwp : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);\r
-signal IntFrmDatSwpBus : std_logic_vector(15 downto 0);\r
-signal IntFrmClkDat : std_logic_vector(15 downto 0);\r
---\r
-signal IntFrmDbleNibFnlEvn : std_logic;\r
-signal IntFrmDbleNibFnlEvn_d : std_logic;\r
-signal IntFrmDbleNibFnlOdd : std_logic;\r
-signal IntFrmDbleNibFnlOdd_d : std_logic;\r
-signal IntFrmDbleNibFnl : std_logic;\r
---\r
-signal IntFrmEna : std_logic;\r
-signal IntFrmCmp : std_logic_vector(3 downto 0);\r
-signal IntFrmEquGte : std_logic;\r
-signal IntFrmEqu_d : std_logic;\r
-signal IntFrmSwapMux_d : std_logic;\r
-signal IntFrmSwapMux_d_Ena : std_logic;\r
-signal IntFrmLsbMsb_d : std_logic;\r
-signal IntFrmLsbMsb_d_Ena : std_logic;\r
-signal IntFrmMsbAllZero_d : std_logic;\r
-signal IntFrmMsbAllZero_d_Ena : std_logic;\r
---\r
-signal IntFrmRegEna_d : std_logic;\r
-signal IntFrmMsbRegEna_d : std_logic;\r
-signal IntFrmLsbRegEna_d : std_logic;\r
---\r
-signal IntFrmEvntCnt : std_logic_vector (3 downto 0); -- count event counter\r
-signal IntFrmEvntCntTc : std_logic;\r
-signal IntFrmEvntCntTc_d : std_logic;\r
-signal IntFrmSlipCnt : std_logic_vector (3 downto 0); -- count to 8\r
-signal IntFrmSlipCntTc : std_logic;\r
-signal IntFrmSlipCntTc_d : std_logic;\r
-signal IntFrmSlipCntTc_d1 : std_logic;\r
-signal IntFrmSlipCntTc_d2Ena : std_logic;\r
-signal IntFrmSlipCntTc_d2 : std_logic;\r
-signal IntFrmWarnCnt : std_logic_vector (2 downto 0);\r
-signal IntFrmWarnCntTc : std_logic;\r
-signal IntFrmWarnCntTc_d : std_logic;\r
-signal IntFrmClkReSync : std_logic;\r
-signal IntFrmReSyncOut : std_logic;\r
---\r
-signal IntFrmBitSlip : std_logic_vector (5 downto 0);\r
-signal IntFrmEquSet_d : std_Logic;\r
-\r
-signal Frame_out_S : std_Logic;\r
--- Attributes\r
-attribute keep of Frame_out_S : signal is "TRUE";\r
------------------------------------------------------------------------------------------------\r
-begin\r
------------------------------------------------------------------------------------------------\r
--- ISERDES FOR FRAME CAPTURE\r
------------------------------------------------------------------------------------------------\r
-IntFrmClk <= FrmClk;\r
-IntFrmClk_n <= not FrmClk;\r
---\r
-AdcFrame_I_Isrds_p : ISERDESE1\r
- generic map (\r
- SERDES_MODE => "MASTER", -- \r
- INTERFACE_TYPE => "NETWORKING", -- \r
- IOBDELAY => "NONE", -- \r
- DATA_RATE => "SDR", -- \r
- DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits\r
- DYN_CLKDIV_INV_EN => FALSE, -- \r
- DYN_CLK_INV_EN => FALSE, -- \r
- NUM_CE => 1, -- \r
- OFB_USED => FALSE -- \r
- )\r
- port map (\r
- D => FrmClk_p, -- in\r
- DDLY => Low, -- in\r
- DYNCLKDIVSEL => Low, -- in\r
- DYNCLKSEL => Low, -- in\r
- OFB => Low, -- in\r
- BITSLIP => IntFrmBitSlip(0),-- in\r
- CE1 => IntFrmEna, -- in\r
- CE2 => Low, -- in\r
- RST => FrmClkRst, -- in\r
- CLK => IntFrmClk, -- in\r
- CLKB => Low, -- in\r
- CLKDIV => FrmClkDiv, -- in\r
- OCLK => Low, -- in\r
- SHIFTOUT1 => open, -- out\r
- SHIFTOUT2 => open, -- out\r
- O => Frame_out_S, -- out\r
- Q1 => IntFrmSrdsOut(6), -- out (0)\r
- Q2 => IntFrmSrdsOut(4), -- out (2)\r
- Q3 => IntFrmSrdsOut(2), -- out (4)\r
- Q4 => IntFrmSrdsOut(0), -- out (6)\r
- Q5 => open, -- out\r
- Q6 => open, -- out\r
- SHIFTIN1 => Low, -- in\r
- SHIFTIN2 => Low -- in\r
- );\r
-Frame_out <= Frame_out_S;\r
-\r
-AdcFrame_I_Isrds_n : ISERDESE1\r
- generic map (\r
- SERDES_MODE => "MASTER", -- \r
- INTERFACE_TYPE => "NETWORKING", -- \r
- IOBDELAY => "NONE", -- \r
- DATA_RATE => "SDR", -- \r
- DATA_WIDTH => IntIsrdsDataWidth, -- 12-bit = 3 and 14/16 b its = 4\r
- DYN_CLKDIV_INV_EN => FALSE, -- \r
- DYN_CLK_INV_EN => FALSE, -- \r
- NUM_CE => 1, -- \r
- OFB_USED => FALSE -- \r
- )\r
- port map (\r
- D => FrmClk_n, -- in\r
- DDLY => Low, -- in\r
- DYNCLKDIVSEL => Low, -- in\r
- DYNCLKSEL => Low, -- in\r
- OFB => Low, -- in\r
- BITSLIP => IntFrmBitSlip(1),-- in\r
- CE1 => IntFrmEna, -- in\r
- CE2 => Low, -- in\r
- RST => FrmClkRst, -- in\r
- CLK => IntFrmClk_n, -- in\r
- CLKB => Low, -- in\r
- CLKDIV => FrmClkDiv, -- in\r
- OCLK => Low, -- in\r
- SHIFTOUT1 => open, -- out\r
- SHIFTOUT2 => open, -- out\r
- O => open, -- out\r
- Q1 => IntFrmSrdsOut(7), -- out (1)\r
- Q2 => IntFrmSrdsOut(5), -- out (3)\r
- Q3 => IntFrmSrdsOut(3), -- out (5)\r
- Q4 => IntFrmSrdsOut(1), -- out (7)\r
- Q5 => open, -- out\r
- Q6 => open, -- out\r
- SHIFTIN1 => Low, -- in\r
- SHIFTIN2 => Low -- in\r
- );\r
------------------------------------------------------------------------------------------------\r
--- INVERT THE NEEDED BITS.\r
------------------------------------------------------------------------------------------------\r
-Gen_1_FrmBus : if (FrmBits(C_AdcBits)/2) = 6 generate\r
- IntFrmSrdsDatEvn <= IntFrmSrdsOut(4) & IntFrmSrdsOut(2) & IntFrmSrdsOut(0);\r
- IntFrmSrdsDatOdd <= not IntFrmSrdsOut(5) & not IntFrmSrdsOut(3) & not IntFrmSrdsOut(1); \r
-end generate Gen_1_FrmBus;\r
-Gen_2_FrmBus : if (FrmBits(C_AdcBits)/2) = 8 generate\r
- IntFrmSrdsDatEvn <= IntFrmSrdsOut(6) & IntFrmSrdsOut(4) &\r
- IntFrmSrdsOut(2) & IntFrmSrdsOut(0);\r
- IntFrmSrdsDatOdd <= not IntFrmSrdsOut(7) & not IntFrmSrdsOut(5) &\r
- not IntFrmSrdsOut(3) & not IntFrmSrdsOut(1); \r
-end generate Gen_2_FrmBus;\r
------------------------------------------------------------------------------------------------\r
--- Double Nibble Detection.\r
--- When the ADC is used in 1-wire mode the frame pattern is 12 or 16 bits long.\r
--- It is captured in two ISERDES. One running at rising CLK and the orther runnsing at falling\r
--- CLK. For some reason, afetr a bitslip a ISERDES can output twice the same nibble of data. \r
--- This phenomenon is called ""Double nibble" and as written before happens after a\r
--- Bitslip request.\r
--- The output of each ISERDES is first checked for these double nibbles and if needed the\r
--- ISERDES output is corrected. After that the data is passed into the franme pattern\r
--- Recognition part of the design. \r
------------------------------------------------------------------------------------------------\r
-Gen_1_DbleNibChk : if (C_AdcWireInt = 1) generate\r
- AdcFrame_I_DblNbblDtct_Evn : DoubleNibbleDetect\r
- port map (\r
- Clock => FrmClkDiv, -- in\r
- RstIn => FrmClkRst, -- in\r
- Final => IntFrmDbleNibFnlEvn, -- out\r
- DataIn => IntFrmSrdsDatEvn, -- in [3:0]\r
- DataOut => IntFrmSrdsDatEvn_d -- out [3:0]\r
- );\r
---\r
- AdcFrame_I_DblNbblDtct_Odd : DoubleNibbleDetect\r
- port map (\r
- Clock => FrmClkDiv, -- in\r
- RstIn => FrmClkRst, -- in\r
- Final => IntFrmDbleNibFnlOdd, -- out\r
- DataIn => IntFrmSrdsDatOdd, -- in [3:0]\r
- DataOut => IntFrmSrdsDatOdd_d -- out [3:0]\r
- );\r
---\r
- AdcFrame_DblNibFnl_PROCESS : process (FrmClkDiv)\r
- begin\r
- if (FrmClkRst = '1' ) then\r
- IntFrmDbleNibFnlOdd_d <= '0';\r
- IntFrmDbleNibFnlEvn_d <= '0';\r
- elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
- if (IntFrmDbleNibFnlOdd = '1') then\r
- IntFrmDbleNibFnlOdd_d <= '1';\r
- else --(IntFrmDbleNibFnlOdd = '0')\r
- IntFrmDbleNibFnlOdd_d <= '0';\r
- end if;\r
- if (IntFrmDbleNibFnlEvn = '1') then\r
- IntFrmDbleNibFnlEvn_d <= '1';\r
- else --(IntFrmDbleNibFnlOdd = '0')\r
- IntFrmDbleNibFnlEvn_d <= '0';\r
- end if;\r
- end if;\r
- end process AdcFrame_DblNibFnl_PROCESS;\r
---\r
- IntFrmDbleNibFnl <= IntFrmDbleNibFnlOdd_d and IntFrmDbleNibFnlEvn_d;\r
-end generate Gen_1_DbleNibChk;\r
---\r
-Gen_2_DbleNibChk : if (C_AdcWireInt = 2) generate\r
- IntFrmSrdsDatEvn_d <= IntFrmSrdsDatEvn;\r
- IntFrmSrdsDatOdd_d <= IntFrmSrdsDatOdd;\r
- IntFrmDbleNibFnl <= Low;\r
-end generate Gen_2_DbleNibChk;\r
------------------------------------------------------------------------------------------------\r
--- DATA REGISTER\r
------------------------------------------------------------------------------------------------\r
-Gen_1_DatBus : for n in (FrmBits(C_AdcBits)/4) downto 1 generate\r
- IntFrmSrdsDat((n*2)-1) <= IntFrmSrdsDatOdd_d(n-1);\r
- IntFrmSrdsDat((n*2)-2) <= IntFrmSrdsDatEvn_d(n-1);\r
-end generate Gen_1_DatBus;\r
---\r
-Gen_1_DatReg : for n in (FrmBits(C_AdcBits)/2)-1 downto 0 generate \r
- AdcFrame_I_Fdce_Reg1 : FDCE\r
- generic map (INIT => '0') -- bit\r
- port map(D => IntFrmSrdsDat(n), CE => IntFrmEna, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmDat(n));\r
-end generate Gen_1_DatReg;\r
------------------------------------------------------------------------------------------------\r
--- BIT SWAP MULTIPLEXER and REGISTER\r
--- Swap the bits in correct order when the pattern detected is bit swapped.\r
------------------------------------------------------------------------------------------------\r
-Gen_2_DatMux : for n in (FrmBits(C_AdcBits)/4)-1 downto 0 generate\r
-begin\r
- IntFrmDatMux((n*2)+1) <= IntFrmDat(n*2) when (IntFrmSwapMux_d = '1') else IntFrmDat((n*2)+1);\r
- IntFrmDatMux(n*2) <= IntFrmDat((n*2)+1) when (IntFrmSwapMux_d = '1') else IntFrmDat(n*2);\r
-end generate Gen_2_DatMux;\r
-Gen_3_DatReg : for n in (FrmBits(C_AdcBits)/2)-1 downto 0 generate\r
- AdcFrame_I_Fdce_Reg2 : FDCE\r
- generic map (INIT => '0') -- bit\r
- port map (D => IntFrmDatMux(n), C => FrmClkDiv, CE => IntFrmEna, CLR => IntFrmReSyncOut,\r
- Q => IntFrmDatSwp(n));\r
-end generate Gen_3_DatReg;\r
------------------------------------------------------------------------------------------------\r
--- FRAME OUTPUT REGISTERS\r
------------------------------------------------------------------------------------------------\r
-Gen_4_OutReg12 : if C_AdcBits = 12 generate\r
- IntFrmDatSwpBus <= "0000" &\r
- IntFrmDatSwp(5) & IntFrmDatSwp(4) &\r
- IntFrmDatSwp(3) & IntFrmDatSwp(2) &\r
- IntFrmDatSwp(1) & IntFrmDatSwp(0) &\r
- IntFrmDatSwp(5) & IntFrmDatSwp(4) &\r
- IntFrmDatSwp(3) & IntFrmDatSwp(2) &\r
- IntFrmDatSwp(1) & IntFrmDatSwp(0);\r
- Gen_4_H : for n in 6 to 15 generate\r
- AdcFrame_I_Fdce_FrmClkDatMsb : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntFrmDatSwpBus(n), CE => IntFrmMsbRegEna_d, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));\r
- end generate Gen_4_H;\r
- Gen_4_L : for n in 0 to 5 generate\r
- AdcFrame_I_Fdce_FrmClkDatLsb : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntFrmDatSwpBus(n), CE => IntFrmLsbRegEna_d, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));\r
- end generate Gen_4_L;\r
-end generate Gen_4_OutReg12;\r
---\r
-Gen_5_OutReg12n : if C_AdcBits /= 12 generate\r
- IntFrmDatSwpBus <= IntFrmDatSwp(7) & IntFrmDatSwp(6) &\r
- IntFrmDatSwp(5) & IntFrmDatSwp(4) &\r
- IntFrmDatSwp(3) & IntFrmDatSwp(2) &\r
- IntFrmDatSwp(1) & IntFrmDatSwp(0) &\r
- IntFrmDatSwp(7) & IntFrmDatSwp(6) &\r
- IntFrmDatSwp(5) & IntFrmDatSwp(4) &\r
- IntFrmDatSwp(3) & IntFrmDatSwp(2) &\r
- IntFrmDatSwp(1) & IntFrmDatSwp(0);\r
- Gen_5_H : for n in 8 to 15 generate\r
- AdcFrame_I_Fdce_FrmClkDatMsb : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntFrmDatSwpBus(n), CE => IntFrmMsbRegEna_d, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));\r
- end generate Gen_5_H;\r
- Gen_5_L : for n in 0 to 7 generate\r
- AdcFrame_I_Fdce_FrmClkDatLsb : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntFrmDatSwpBus(n), CE => IntFrmLsbRegEna_d, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));\r
- end generate Gen_5_L;\r
-end generate Gen_5_OutReg12n;\r
---\r
-FrmClkDat <= IntFrmClkDat;\r
------------------------------------------------------------------------------------------------\r
--- FRAME PATTERN COMPARATOR \r
------------------------------------------------------------------------------------------------\r
-IntFrmCmp(2 downto 0) <= "101" when (IntFrmSrdsDat = IntPatternA) else -- Equ, , Msb\r
- "100" when (IntFrmSrdsDat = IntPatternB) else -- Equ, , Lsb\r
- "111" when (IntFrmSrdsDat = IntPatternC) else -- Equ, swpd, Msb\r
- "110" when (IntFrmSrdsDat = IntPatternD) else -- Equ, Swpd, Lsb\r
- "000";\r
-IntFrmCmp(3) <= High when (C_AdcWireInt = 2) else Low; -- Msb = all zero\r
---\r
--- When "Equ" goes high, one of the four patterns has been found.\r
--- The other two signals will reflect (Msb or Lsb, bitswapped or not) what pattern has been\r
--- found. WHen "Equ" thus goes high, store the status of all signals and make sure it can't\r
--- be changed.\r
---\r
-IntFrmEquGte <= (IntFrmCmp(2) or IntFrmEqu_d) and IntFrmEna;\r
---\r
-AdcFrame_I_Fdce_FrmMsbAllZero_d : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntFrmCmp(3), CE => IntFrmMsbAllZero_d_Ena, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmMsbAllZero_d);\r
-AdcFrame_I_Fdce_FrmEqu_d : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntFrmEquGte, CE => High, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmEqu_d);\r
-AdcFrame_I_Fdce_FrmSwapMux_d : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntFrmCmp(1), CE => IntFrmSwapMux_d_Ena, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmSwapMux_d);\r
-AdcFrame_I_Fdce_FrmLsbMsb_d : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntFrmCmp(0), CE => IntFrmLsbMsb_d_Ena, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmLsbMsb_d);\r
---\r
-IntFrmMsbAllZero_d_Ena <= IntFrmCmp(2) and not IntFrmEqu_d;\r
-IntFrmSwapMux_d_Ena <= IntFrmCmp(2)and not IntFrmEqu_d;\r
-IntFrmLsbMsb_d_Ena <= IntFrmCmp(2) and not IntFrmEqu_d;\r
-FrmClkSwapMux <= IntFrmSwapMux_d;\r
------------------------------------------------------------------------------------------------\r
--- OUTPUT REGISTER ENABLER\r
------------------------------------------------------------------------------------------------\r
-AdcFrame_EnaSel_PROCESS : process (FrmClkDiv, IntFrmMsbAllZero_d, IntFrmEqu_d)\r
-subtype IntFrmRegEnaCase is std_logic_vector(4 downto 0);\r
-begin\r
- if (IntFrmMsbAllZero_d = High) then\r
- IntFrmRegEna_d <= Low;\r
- IntFrmMsbRegEna_d <= High;\r
- IntFrmLsbRegEna_d <= High;\r
- elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
- case IntFrmRegEnaCase'(IntFrmLsbMsb_d, IntFrmEqu_d, IntFrmRegEna_d,\r
- IntFrmMsbRegEna_d, IntFrmLsbRegEna_d) is\r
- when "00001" => IntFrmRegEna_d <= '0';\r
- IntFrmMsbRegEna_d <= '0'; -- A\r
- IntFrmLsbRegEna_d <= '1'; --\r
- when "01001" => IntFrmRegEna_d <= '1';\r
- IntFrmMsbRegEna_d <= '0'; -- B\r
- IntFrmLsbRegEna_d <= '1'; --\r
- when "01101" => IntFrmRegEna_d <= '1';\r
- IntFrmMsbRegEna_d <= '1'; -- C\r
- IntFrmLsbRegEna_d <= '0'; --\r
- when "01110" => IntFrmRegEna_d <= '1';\r
- IntFrmMsbRegEna_d <= '0'; -- D, goto C \r
- IntFrmLsbRegEna_d <= '1'; --\r
- --\r
- when "11001" => IntFrmRegEna_d <= '1';\r
- IntFrmMsbRegEna_d <= '1'; -- E\r
- IntFrmLsbRegEna_d <= '0'; --\r
- when "11110" => IntFrmRegEna_d <= '1';\r
- IntFrmMsbRegEna_d <= '0'; -- F\r
- IntFrmLsbRegEna_d <= '1'; --\r
- when "11101" => IntFrmRegEna_d <= '1';\r
- IntFrmMsbRegEna_d <= '1'; -- G, goto F\r
- IntFrmLsbRegEna_d <= '0'; --\r
- --\r
- when others => IntFrmRegEna_d <= '0';\r
- IntFrmMsbRegEna_d <= '0';\r
- IntFrmLsbRegEna_d <= '1';\r
- end case;\r
- end if;\r
-end process;\r
-FrmClkMsbRegEna <= IntFrmMsbRegEna_d;\r
-FrmClkLsbRegEna <= IntFrmLsbRegEna_d;\r
------------------------------------------------------------------------------------------------\r
--- SAMPLE EVENT COUNTER\r
--- Take a frame sample every 16 ClkDiv cycles.\r
------------------------------------------------------------------------------------------------\r
-AdcFrame_EvntCnt_PROCESS : process (FrmClkDiv, IntFrmReSyncOut)\r
-begin\r
- if (IntFrmReSyncOut = High) then\r
- IntFrmEvntCnt <= (others => '0');\r
- IntFrmEvntCntTc_d <= Low;\r
- elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
- if (IntFrmEquSet_d = Low and IntFrmEna = High) then\r
- IntFrmEvntCnt <= IntFrmEvntCnt + "01";\r
- IntFrmEvntCntTc_d <= IntFrmEvntCntTc;\r
- end if;\r
- end if;\r
-end process;\r
-IntFrmEvntCntTc <= High when (IntFrmEvntCnt = "1110") else Low;\r
---IntFrmEvntCntTc <= High when (IntFrmEvntCnt = ((2**IntFrmEvntCnt'length)-2)) else Low;\r
------------------------------------------------------------------------------------------------\r
--- BITSLIP EVENT COUNTER\r
--- Bitslip 8 times for a 8-bit ISERDES and 6 times for a 6-bit ISERDES.\r
------------------------------------------------------------------------------------------------\r
-AdcFrame_SlipCnt_PROCESS : process (FrmClkDiv, IntFrmReSyncOut)\r
-begin\r
- if (IntFrmReSyncOut = High) then\r
- IntFrmSlipCnt <= (others => '0');\r
- elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
- if (IntFrmEvntCntTc_d = High) then\r
- IntFrmSlipCnt <= IntFrmSlipCnt + "01";\r
- end if;\r
- if (IntFrmEvntCntTc_d = High and IntFrmSlipCntTc = High) then\r
- IntFrmSlipCntTc_d <= High;\r
- else \r
- IntFrmSlipCntTc_d <= Low;\r
- end if;\r
- end if;\r
-end process;\r
---Terminal count points.\r
-AdcFrame_SlipCntTc_12 : if (FrmBits(C_AdcBits) = 12) generate\r
- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1011") else Low; -- 11 or X'B'\r
-end generate;\r
-AdcFrame_SlipCntTc_1_16 : if (FrmBits(C_AdcBits) = 16) generate\r
- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1111") else Low; -- 15 or X'F'\r
-end generate;\r
---AdcFrame_SlipCntTc_1_12 : if (C_AdcWireInt = 1 and FrmBits(C_AdcBits) = 12) generate\r
--- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1011") else Low; -- 11 or X'B'\r
---end generate;\r
---AdcFrame_SlipCntTc_2_12 : if (C_AdcWireInt = 2 and FrmBits(C_AdcBits) = 12) generate\r
--- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "0101") else Low; -- 5\r
---end generate;\r
---AdcFrame_SlipCntTc_1_16 : if (C_AdcWireInt = 1 and FrmBits(C_AdcBits) = 16) generate\r
--- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1111") else Low; -- 15 or X'F'\r
---end generate;\r
---AdcFrame_SlipCntTc_2_16 : if (C_AdcWireInt = 2 and FrmBits(C_AdcBits) = 16) generate\r
--- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "0111") else Low; -- 7\r
---end generate;\r
-AdcFrame_I_Fdce_SlipCntTc_1 : FDCE\r
- generic map (INIT => '0')\r
- port map (D => High, CE => IntFrmSlipCntTc_d, C => FrmClkDiv,\r
- CLR => IntFrmSlipCntTc_d2, Q => IntFrmSlipCntTc_d1);\r
-IntFrmSlipCntTc_d2Ena <= IntFrmSlipCntTc_d and IntFrmSlipCntTc_d1;\r
-AdcFrame_I_Fdce_SlipCntTc_2 : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntFrmSlipCntTc_d2Ena, CE => High, C => FrmClkDiv,\r
- CLR => IntFrmReSyncOut, Q => IntFrmSlipCntTc_d2);\r
------------------------------------------------------------------------------------------------\r
--- WARNING EVENT COUNTER\r
--- When this counter issues terminal count, sunchronisation was impossible for 8 times.\r
------------------------------------------------------------------------------------------------\r
-AdcFrame_WarnCnt_PROCESS : process (FrmClkDiv, FrmClkRst)\r
-begin\r
- if (FrmClkRst = High) then\r
- IntFrmWarnCnt <= (others => '0');\r
- IntFrmWarnCntTc_d <= Low;\r
- elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
- if (IntFrmSlipCntTc_d = High) then\r
- IntFrmWarnCnt <= IntFrmWarnCnt + "01";\r
- IntFrmWarnCntTc_d <= IntFrmWarnCntTc;\r
- end if;\r
- end if;\r
-end process;\r
-IntFrmWarnCntTc <= High when (IntFrmWarnCnt = "110") else Low;\r
-FrmClkSyncWarn <= IntFrmWarnCntTc_d;\r
------------------------------------------------------------------------------------------------\r
--- Enable, RESYNC or INTERNAL RESET\r
--- This is the reset logic for the whole design.\r
--- Whenever one of these signals (IntFrmSlipCntTc_d2, IntFrmDbleNibFnl, FrmClkReSync, FrmClkRst)\r
--- is high the circuit is pulled int reset (call it a re-sync operation).\r
--- \r
--- The only components not influenced by this are the ISERDES and the Sync Warning Counter.\r
--- they only act on the extrenal "FrmClkRst" input.\r
--- \r
--- A circuit enable "IntFrmEna" is generated when the inputs "FrmClkDone" and "FrmClkEna" are\r
--- high and when the "IntFrmReSync" reset is released.\r
------------------------------------------------------------------------------------------------\r
-AdcFrame_I_GenPulse_1 : GenPulse\r
- port map (\r
- Clk => FrmClkDiv, -- in\r
- Ena => High, -- in\r
- SigIn => FrmClkReSync, -- in\r
- SigOut => IntFrmClkReSync -- out\r
- );\r
-IntFrmReSyncOut <= IntFrmSlipCntTc_d2 or IntFrmDbleNibFnl or IntFrmClkReSync or FrmClkRst;\r
-FrmClkReSyncOut <= IntFrmReSyncOut;\r
---\r
-AdcFrame_I_Fdce_Done : FDCE\r
- generic map (INIT => '0') -- bit\r
- port map(D => FrmClkDone, CE => FrmClkEna, C => FrmClkDiv, CLR => IntFrmReSyncOut,\r
- Q => IntFrmEna);\r
------------------------------------------------------------------------------------------------\r
--- BITSLIP STATE MACHINE.\r
------------------------------------------------------------------------------------------------\r
-AdcFrame_Bitslip_PROCESS : process (IntFrmReSyncOut, FrmClkDiv)\r
-subtype IntFrmBitSlipCase is std_logic_vector(5 downto 0);\r
-begin\r
- if (IntFrmReSyncOut = High) then\r
- IntFrmBitSlip <= (others => '0');\r
- elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
- if (IntFrmEna = High and IntFrmEquSet_d = Low) then\r
- case IntFrmBitSlipCase'(IntFrmEqu_d, IntFrmEvntCntTc_d, IntFrmBitSlip(5),\r
- IntFrmBitSlip(4), IntFrmBitSlip(3), IntFrmBitSlip(2)) is\r
- when "000000" => IntFrmBitSlip <= "000000"; -- B \r
- when "010000" => IntFrmBitSlip <= "000101"; -- C Slip_p\r
- when "000001" => IntFrmBitSlip <= "000100"; -- D\r
- when "010001" => IntFrmBitSlip <= "001010"; -- E Slip_n\r
- when "000010" => IntFrmBitSlip <= "001000"; -- F\r
- when "010010" => IntFrmBitSlip <= "000101"; -- G Slip_p and goto D\r
- --\r
- when "100000" => IntFrmBitSlip <= "000000"; -- H \r
- when "110000" => IntFrmBitSlip <= "100101"; -- K Slip_p\r
- when "101001" => IntFrmBitSlip <= "110000"; -- L EquSet\r
- when "101100" => IntFrmBitSlip <= "110000"; -- M Halt\r
- --\r
- when "100001" => IntFrmBitSlip <= "000100"; -- N\r
- when "110001" => IntFrmBitSlip <= "101010"; -- P Slip_n\r
- when "101010" => IntFrmBitSlip <= "110000"; -- R EquSet goto M\r
- --\r
- when "100010" => IntFrmBitSlip <= "001000"; -- S\r
- when "110010" => IntFrmBitSlip <= "100101"; -- T Slip_p goto L\r
- --\r
- when others => IntFrmBitSlip <= "110000";\r
- end case;\r
- end if;\r
- end if;\r
-end process;\r
-FrmClkBitSlip_p <= IntFrmBitSlip(0);\r
-FrmClkBitSlip_n <= IntFrmBitSlip(1);\r
-IntFrmEquSet_d <= IntFrmBitSlip(4);\r
-\r
-\r
-testword0(7 downto 0) <= IntFrmSrdsOut;\r
-testOK <= '1' when IntFrmSrdsOut=x"A5" else '0';\r
-\r
---\r
------------------------------------------------------------------------------------------------\r
-end AdcFrame_struct;\r
+++ /dev/null
-----------------------------------------------------------------------------------------------\r
--- Copyright 2010, Xilinx, Inc. All rights reserved.\r
--- This file contains confidential and proprietary information of Xilinx, Inc. and is\r
--- protected under U.S. and international copyright and other intellectual property laws.\r
------------------------------------------------------------------------------------------------\r
---\r
--- Disclaimer:\r
--- This disclaimer is not a license and does not grant any rights to the materials\r
--- distributed herewith. Except as otherwise provided in a valid license issued to you\r
--- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS\r
--- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL\r
--- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED\r
--- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR\r
--- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including\r
--- negligence, or under any other theory of liability) for any loss or damage of any\r
--- kind or nature related to, arising under or in connection with these materials,\r
--- including for any direct, or any indirect, special, incidental, or consequential\r
--- loss or damage (including loss of data, profits, goodwill, or any type of loss or\r
--- damage suffered as a result of any action brought by a third party) even if such\r
--- damage or loss was reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
---\r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-safe, or for use in any\r
--- application requiring fail-safe performance, such as life-support or safety devices\r
--- or systems, Class III medical devices, nuclear facilities, applications related to\r
--- the deployment of airbags, or any other applications that could lead to death,\r
--- personal injury, or severe property or environmental damage (individually and\r
--- collectively, "Critical Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical Applications, subject only to\r
--- applicable laws and regulations governing limitations on product liability.\r
---\r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. \r
---\r
--- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx Inc.\r
--- \ \ \/ Version: \r
--- \ \ \r
--- / / Filename: AdcToplevel.vhd\r
--- /___/ /\ Date Created: Nov 07\r
--- \ \ / \ Date Last Modified: 7 Mar 2011\r
--- \___\/\___\\r
--- \r
--- Device: Virtex-6\r
--- Author: defossez\r
--- Entity Name: AdcToplevel\r
--- Purpose: Top level for an interface between a Virtex-6 FPGA and ADS6245 \r
--- Tools: ISE_13.1 \r
--- Limitations: none\r
---\r
--- Revision History:\r
--- Rev. 20 Oct 09\r
--- Made the ADC interface more generic, with speate FPGA IO file and etcetera.\r
--- Rev. 27 Dec 10\r
--- Retrived the file after accidental delete.\r
--- Rev. 7 Mar 11\r
--- - Adjustment of the range, in the entity declaration, of "AdcMemFlags" when\r
--- used for 1 and 2 wire interface.\r
--- - Brought the generic C_FrmPattern to the top level entity declaration. Now it is \r
--- possible to provide the frame pattern to search for when the AdcToplevel component\r
--- is instantiated.\r
--- - Added extensive comments for teh top level entity generics and ports.\r
------------------------------------------------------------------------------------------------\r
--- Naming Conventions:\r
--- active low signals: "*_n"\r
--- clock signals: "clk", "clk_div#", "clk_#x"\r
--- reset signals: "rst", "rst_n"\r
--- generics: "C_*"\r
--- user defined types: "*_TYPE"\r
--- state machine next state: "*_ns"\r
--- state machine current state: "*_cs"\r
--- combinatorial signals: "*_com"\r
--- pipelined or register delay signals: "*_d#"\r
--- counter signals: "*cnt*"\r
--- clock enable signals: "*_ce"\r
--- internal version of output port: "*_i"\r
--- device pins: "*_pin"\r
--- ports: "- Names begin with Uppercase"\r
--- processes: "*_PROCESS"\r
--- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
------------------------------------------------------------------------------------------------\r
---\r
-library IEEE;\r
- use IEEE.std_logic_1164.all;\r
- use IEEE.std_logic_UNSIGNED.all;\r
- use IEEE.std_logic_textio.all;\r
- use std.textio.all;\r
-library UNISIM;\r
- use UNISIM.VCOMPONENTS.all;\r
------------------------------------------------------------------------------------------------\r
--- Entity pin description\r
------------------------------------------------------------------------------------------------\r
--- GENERICS\r
--- C_AdcChnls -- ADC Channels available in a package.\r
--- C_AdcBits -- Value can be 12, 14, or 16 (14 is means 14-bit burried in 16-bit)\r
--- C_AdcWireInt -- 0 = 1-wire, 1 = 2-wire\r
--- C_FrmPattern -- Pattern to lock the frame to.\r
---\r
--- A 14 or 16 bit ADC in 2-wire mode has a 8-bit frame pattern. The C_FrmPattern parameter\r
--- must be set to: C_FrmPattern ==> "0000000011110000".\r
--- A 14 or 16 bit ADC in 1-wire mode has a 16-bit frame pattern. The C_FrmPattern parameter\r
--- must be set to: C_FrmPattern ==> "1111111100000000".\r
--- The same applies for a 12-bit ADC device.\r
--- C_FrmPattern : string := "111111000000"; -- 1-wire, 12 bit.\r
--- C_FrmPattern : string := "000000111000"; -- 2-wire, 12 bit.\r
---\r
--- C_StatTaps -- Number of taps the IDELAY starts from (Middle of the Tap chain).\r
--- C_IdelayCtrlLoc -- Hard location of the IDELAYCTRL component.\r
--- PORTS\r
--- DATA_n -- I -- ADC data input signals from the ADC device.\r
--- DATA_p -- I -- \r
--- DCLK_n, DCLK_p -- I -- High speed clock from the ADC device.\r
--- FCLK_n, FCLK_p -- I -- Word or frame clock from the ADC device.\r
--- SysRefClk -- I -- Reference clock for IDELAYCTRL (200 MHz).\r
--- AdcIntrfcRst -- I -- Reset for the interface from the application.\r
--- AdcIntrfcEna -- I -- Enable signal for the interface from the application.\r
--- AdcReSync -- I -- Signal to restart the resync process.\r
--- AdcFrmSyncWrn -- O -- Warning from the sync logic, alignment is not possible\r
--- AdcBitClkAlgnWrn -- O -- Status signal. BitClock adjusted.\r
--- AdcBitClkInvrtd -- O -- Bit clock state, rising or falling\r
--- AdcBitClkDone -- O -- Bit clock alignment done\r
--- AdcIdlyCtrlRdy -- O -- IDELAYCTRL ready\r
-\r
------------------------------------------------------------------------------------------------\r
-entity AdcToplevel is\r
- generic (\r
- C_AdcChnls : integer := 4; -- Number of ADC in a package \r
- C_AdcWireInt : integer := 2; -- 2 = 2-wire, 1 = 1-wire interface\r
- C_BufioLoc : string := "BUFIODQS_X0Y12";\r
- C_BufrLoc : string := "BUFR_X0Y6";\r
- C_AdcBits : integer := 16;\r
- C_StatTaps : integer := 16;\r
- C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes\r
- C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y3";\r
- C_FrmPattern : string := "0000000011110000" -- Read above text!\r
- );\r
- port (\r
- DCLK_p : in std_logic;\r
- DCLK_n : in std_logic; -- Not used.\r
- FCLK_p : in std_logic;\r
- FCLK_n : in std_logic;\r
- DATA_p : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);\r
- DATA_n : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);\r
- -- application connections\r
- SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application\r
- AdcIntrfcRst : in std_logic;\r
- AdcIntrfcEna : in std_logic;\r
- AdcReSync : in std_logic;\r
- AdcFrmSyncWrn : out std_logic;\r
- AdcBitClkAlgnWrn : out std_logic;\r
- AdcBitClkInvrtd : out std_logic;\r
- AdcBitClkDone : out std_logic;\r
- AdcIdlyCtrlRdy : out std_logic;\r
-\r
- AdcClkDiv : out std_logic;\r
- AdcDataClk : in std_logic;
- AdcDataClkNot : in std_logic;
- AdcDataOut : out std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);\r
- ADCs_ready : out std_logic;\r
- testOK : out std_logic;\r
- testword0 : out std_logic_vector(35 downto 0)
- );\r
-end AdcToplevel;\r
------------------------------------------------------------------------------------------------\r
--- Arcitecture section\r
------------------------------------------------------------------------------------------------\r
-architecture AdcToplevel_struct of AdcToplevel is\r
------------------------------------------------------------------------------------------------\r
--- Component Instantiation\r
------------------------------------------------------------------------------------------------\r
------------------------------------------------------------------------------------------------\r
--- Constants, Signals and Attributes Declarations\r
------------------------------------------------------------------------------------------------\r
--- Functions\r
-function int_to_chr(int: integer) return character is\r
- variable temp : character;\r
-begin\r
- case int is\r
- when 0 => temp := '0';\r
- when 1 => temp := '1';\r
- when 2 => temp := '2';\r
- when 3 => temp := '3';\r
- when 4 => temp := '4';\r
- when 5 => temp := '5';\r
- when 6 => temp := '6';\r
- when 7 => temp := '7';\r
- when 8 => temp := '8';\r
- when 9 => temp := '9';\r
- when 10 => temp := 'A';\r
- when 11 => temp := 'B';\r
- when 12 => temp := 'C';\r
- when 13 => temp := 'D';\r
- when 14 => temp := 'E';\r
- when 15 => temp := 'F';\r
- when 16 => temp := 'G';\r
- when 17 => temp := 'H';\r
- when 18 => temp := 'I';\r
- when 19 => temp := 'J';\r
- when 20 => temp := 'K';\r
- when 21 => temp := 'L';\r
- when 22 => temp := 'M';\r
- when 23 => temp := 'N';\r
- when 24 => temp := 'O';\r
- when 25 => temp := 'P';\r
- when 26 => temp := 'Q';\r
- when 27 => temp := 'R';\r
- when 28 => temp := 'S';\r
- when 29 => temp := 'T';\r
- when 30 => temp := 'U';\r
- when 31 => temp := 'V';\r
- when 32 => temp := 'W';\r
- when 33 => temp := 'X';\r
- when 34 => temp := 'Y';\r
- when 35 => temp := 'Z';\r
- when others => temp := '?';\r
- end case;\r
-return temp;\r
-end function int_to_chr;\r
---\r
-function int_to_str(int: integer; base: integer) return string is\r
- variable temp: string(1 to 10);\r
- variable num: integer;\r
- variable abs_int: integer;\r
- variable len: integer := 1;\r
- variable power: integer := 1;\r
-begin\r
- abs_int := abs(int); -- Negative numbers\r
- num := abs_int;\r
- \r
- while num >= base loop -- Determine how many\r
- len := len + 1; -- characters required\r
- num := num / base; -- to represent the\r
- end loop ; -- number.\r
-\r
- for i in len downto 1 loop -- Convert the number to\r
- temp(i) := int_to_chr(abs_int/power mod base); -- a string starting\r
- power := power * base; -- with the right hand\r
- end loop ; -- side.\r
-\r
- -- return result and add sign if required\r
- if int < 0 then\r
- return '-'& temp(1 to len);\r
- else\r
- return temp(1 to len);\r
- end if;\r
-end function int_to_str;\r
--- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.\r
--- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.\r
--- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.\r
-function AdcBits (Bits : integer) return integer is\r
-variable Temp : integer;\r
-begin\r
- if (Bits = 12) then\r
- Temp := 12;\r
- elsif (Bits = 14) then\r
- Temp := 16;\r
- elsif (Bits = 16) then\r
- Temp := 16;\r
- end if;\r
-return Temp;\r
-end function AdcBits;\r
-\r
-component AdcClock is\r
- generic (\r
- C_BufioLoc : string := C_BufioLoc;\r
- C_BufrLoc : string := C_BufrLoc;\r
- C_AdcBits : integer := C_AdcBits;\r
- C_StatTaps : integer := C_StatTaps\r
- );\r
- port (\r
- BitClk : in std_logic;\r
- BitClkRst : in std_logic;\r
- BitClkEna : in std_logic;\r
- BitClkReSync : in std_logic;\r
- BitClkDivReset : in std_logic;\r
- BitClk_MonClkOut : out std_logic; -- CLK output\r
- BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input\r
- BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output\r
- BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input\r
- BitClkAlignWarn : out std_logic;\r
- BitClkInvrtd : out std_logic;\r
- BitClkDone : out std_logic\r
- );\r
-end component;\r
-\r
-component AdcFrame is\r
- generic (\r
- C_AdcBits : integer;\r
- C_AdcWireInt : integer;\r
- C_FrmPattern : string\r
- );\r
- port (\r
- FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT\r
- FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT\r
- FrmClkRst : in std_logic;\r
- FrmClkEna : in std_logic;\r
- FrmClk : in std_logic;\r
- FrmClkDiv : in std_logic;\r
- FrmClkDone : in std_logic; -- Input from clock syncronisation.\r
- FrmClkReSync : in std_logic;\r
- FrmClkBitSlip_p : out std_logic;\r
- FrmClkBitSlip_n : out std_logic;\r
- FrmClkSwapMux : out std_logic;\r
- FrmClkMsbRegEna : out std_logic;\r
- FrmClkLsbRegEna : out std_logic;\r
- FrmClkReSyncOut : out std_logic;\r
- FrmClkDat : out std_logic_vector(15 downto 0);\r
- FrmClkSyncWarn : out std_logic;\r
- Frame_out : out std_logic;\r
- testOK : out std_logic;\r
- testword0 : out std_logic_vector(35 downto 0)
- );\r
-end component;\r
-\r
-component AdcData is
- generic (
- C_AdcBits : integer := C_AdcBits; -- Can be 12, 14 or 16
- C_AdcBytOrBitMode : integer := 1; -- 1 = BIT mode, 0 = BYTE mode,
- C_AdcMsbOrLsbFst : integer := 0; -- 0 = MSB first, 1 = LSB first
- C_AdcWireInt : integer := C_AdcWireInt -- 1 = 1-wire, 2 = 2-wire.
- );
- port (
- DatD0_n : in std_logic;
- DatD0_p : in std_logic;
- DatD1_n : in std_logic;
- DatD1_p : in std_logic;
- DatClk : in std_logic;
- DatClkDiv : in std_logic;
- DatRst : in std_logic;
- DatEna : in std_logic;
- DatDone : in std_logic;
- DatBitSlip_p : in std_logic;
- DatBitSlip_n : in std_logic;
- DatSwapMux : in std_logic;
- DatMsbRegEna : in std_logic;
- DatLsbRegEna : in std_logic;
- DatReSync : in std_logic;
- DatOut : out std_logic_vector(31 downto 0)
- );
-end component;\r
-\r
-attribute keep : string;
-\r
--- Constants\r
-constant Low : std_logic := '0';\r
-constant High : std_logic := '1';\r
--- Signals\r
-signal IntIdlyCtrlRdy : std_logic := '0';\r
-signal IntRst0 : std_logic := '0';\r
-signal IntRst : std_logic := '0';\r
-signal IntEna_d : std_logic := '0';\r
-signal IntEna : std_logic := '0';\r
---\r
-signal IntBitClkDone : std_logic := '0';\r
-signal IntClk : std_logic := '0';\r
-signal IntClkDiv : std_logic := '0';\r
-attribute keep of IntClkDiv : signal is "TRUE";
-signal IntClkBitSlip_p : std_logic := '0';\r
-signal IntClkBitSlip_n : std_logic := '0';\r
-signal IntClkSwapMux : std_logic := '0';\r
-signal IntClkMsbRegEna : std_logic := '0';\r
-signal IntClkLsbRegEna : std_logic := '0';\r
-signal IntFrmClkReSyncOut : std_logic := '0';\r
-signal IntDataOut : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0) := (others => '0');\r
-signal IntDataOut_S : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0) := (others => '0');\r
--- Attributes\r
-attribute LOC : string;\r
------------------------------------------------------------------------------------------------\r
---\r
-signal AdcBitClkAlgnWrn_S : std_logic := '0';
-signal AdcBitClkInvrtd_S : std_logic := '0';
-signal adcfrmsyncwrn_S : std_logic := '0';
-signal AdcIdlyCtrlRdy_S : std_logic := '0';
-signal testOK_S : std_logic := '0';
-signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');\r
-signal AdcReSync_S : std_logic := '0';
-signal slipoccurred_S : std_logic := '0';\r
-signal slipsoccurred_S : std_logic := '0';\r
-signal slipcounter_S : integer range 0 to 255 := 0;\r
-signal IntBitClkDone_S : std_logic := '0';\r
-signal ClockResync_S : std_logic := '0';\r
-signal ClockResync0_S : std_logic := '0';\r
-\r
-signal IntEna_S : std_logic := '0';\r
-signal IntRst_S : std_logic := '0';\r
-signal frame_S : std_logic := '0';\r
-signal reset_clockdiv_S : std_logic := '0';\r
-\r
-signal AdcData_negedge : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
-signal AdcDataOut_S : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
-\r
-\r
--- Attributes\r
-attribute keep of reset_clockdiv_S : signal is "TRUE";\r
-\r
-begin\r
-\r
-AdcClkDiv <= IntClkDiv;\r
---AdcDataOut <= IntDataOut;\r
-
---process(IntClkDiv)
---begin
--- if falling_edge(IntClkDiv) then
--- AdcData_negedge <= IntDataOut;
--- end if;
---end process;\r
-\r
-process(IntClkDiv)
-begin
- if rising_edge(IntClkDiv) then
- IntDataOut_S <= IntDataOut;
- end if;
-end process;\r
-\r
-process(AdcDataClkNot)
-begin
- if rising_edge(AdcDataClkNot) then
- AdcData_negedge <= IntDataOut_S;
- end if;
-end process;\r
-
-process(AdcDataClk)
-begin
- if rising_edge(AdcDataClk) then \r
- AdcDataOut <= AdcDataOut_S;
- AdcDataOut_S <= AdcData_negedge;
- end if;
-end process;
-\r
-\r
------------------------------------------------------------------------------------------------\r
--- IDELAYCTRL\r
--- An IDELAYCTRL component must be used per IO-bank. Normally a ADC port fits a whole\r
--- IO-Bank. The number of IDELAYCTRL components should thus fit with the number of ADC port.\r
--- In case of this test design, two ADC ports fit into one IO-Bank, thus only one IDLEAYCTRL\r
--- component is needed.\r
--- Don not forget to hook the outputs of the IDELAYCTRL components correctly to the reset and\r
--- enable for each ADC block.\r
--- Don not forget to LOC the IDELAYCTRL components down.\r
------------------------------------------------------------------------------------------------\r
-Gen_0 : if C_AdcUseIdlyCtrl = 0 generate\r
- AdcIdlyCtrlRdy_S <= High;\r
-end generate Gen_0;\r
-Gen_1 : if C_AdcUseIdlyCtrl = 1 generate\r
-attribute LOC of AdcToplevel_I_IdlyCtrl_0 : label is C_AdcIdlyCtrlLoc;\r
-begin\r
- AdcToplevel_I_IdlyCtrl_0 : IDELAYCTRL\r
- port map (REFCLK => SysRefClk, RST => reset_clockdiv_S , RDY => AdcIdlyCtrlRdy_S);--peter AdcIntrfcRst\r
-end generate Gen_1;\r
-AdcIdlyCtrlRdy <= AdcIdlyCtrlRdy_S;\r
--- IntRst and IntEna are the reset and enable signals to be used in the interafce.\r
--- they are generated from the incomming system enable and reset.\r
-\r
-AdcToplevel_I_Fdpe_Rst : FDPE\r
- generic map (INIT => '1')\r
- port map (C => IntClkDiv, CE => High, PRE => reset_clockdiv_S, D => Low, Q => IntRst);--peter AdcIntrfcRst\r
-\r
- \r
-\r
-AdcToplevel_I_Fdce_Ena_0 : FDCE\r
- generic map (INIT => '0')\r
- port map (C => IntClkDiv, CE => AdcIntrfcEna, CLR => IntRst, D => High, Q => IntEna_d);\r
-AdcToplevel_I_Fdce_Ena_1 : FDCE\r
- generic map (INIT => '0')\r
- port map (C => IntClkDiv, CE => High, CLR => IntRst, D => IntEna_d, Q => IntEna);\r
------------------------------------------------------------------------------------------------\r
--- C_AdcChnls = c\r
--- C_AdcWireInt = w\r
--- C_AdcBits = b\r
------------------------------------------------------------------------------------------------\r
--- BIT CLOCK\r
--- IntClk and IntClkDiv are the clock to be used in the interface.\r
------------------------------------------------------------------------------------------------\r
--- There is no IBUFGDS used on this level of the design.\r
--- The IBUFGDS can be found in the AdcIo level.\r
--- That is this the reason why the DCLK_n is not used here.\r
--- At the AdcIo level the DCLK_n output is connected to GND.\r
-AdcToplevel_I_AdcClock : AdcClock -- entity AdcClock.AdcClock\r
-generic map (\r
- C_BufioLoc => C_BufioLoc, -- string \r
- C_BufrLoc => C_BufrLoc, -- string\r
- C_AdcBits => C_AdcBits, -- integer\r
- C_StatTaps => C_StatTaps -- integer\r
- )\r
-port map (\r
- BitClk => DCLK_p, -- in\r
- BitClkRst => IntRst, -- in\r
- BitClkEna => '1', -- IntEna_S, -- in\r
- BitClkReSync => ClockResync_S, -- AdcReSync_S, -- in\r
- BitClkDivReset => reset_clockdiv_S,\r
- BitClk_MonClkOut => IntClk, -- out -->--|---->----\r
- BitClk_MonClkIn => IntClk, -- in --<--|\r
- BitClk_RefClkOut => IntClkDiv, -- out -->----|-->----\r
- BitClk_RefClkIn => IntClkDiv, -- in --<----|\r
- BitClkAlignWarn => AdcBitClkAlgnWrn_S,-- out\r
- BitClkInvrtd => AdcBitClkInvrtd_S, -- out\r
- BitClkDone => IntBitClkDone -- out Enables the AdcFrame block.\r
-);\r
-AdcBitClkDone <= IntBitClkDone; -- IntBitClkDone_S;\r
-AdcBitClkInvrtd <= AdcBitClkInvrtd_S;
-AdcBitClkAlgnWrn <= AdcBitClkAlgnWrn_S;
------------------------------------------------------------------------------------------------\r
--- WORD / FRAME CLOCK\r
------------------------------------------------------------------------------------------------\r
-AdcToplevel_I_AdcFrame : AdcFrame -- entity AdcFrame_Lib.AdcFrame\r
-generic map (\r
- C_AdcBits => C_AdcBits, -- integer;\r
- C_AdcWireInt => C_AdcWireInt, -- integer;\r
- C_FrmPattern => C_FrmPattern -- string -- 1 or 2-wire, 12 or 16(14)-bit\r
-)\r
-port map (\r
- FrmClk_n => FCLK_n, -- in input n from IBUFDS_DIFF_OUT\r
- FrmClk_p => FCLK_p, -- in input p from IBUFDS_DIFF_OUT\r
- FrmClkRst => IntRst_S, -- in\r
- FrmClkEna => IntEna_S, -- in\r
- FrmClk => IntClk, -- in\r
- FrmClkDiv => IntClkDiv, -- in\r
- FrmClkDone => IntBitClkDone, -- IntBitClkDone_S, -- in From AdcClock done.\r
- FrmClkReSync => AdcReSync_S, -- in\r
- FrmClkBitSlip_p => IntClkBitSlip_p, -- out\r
- FrmClkBitSlip_n => IntClkBitSlip_n, -- out\r
- FrmClkSwapMux => IntClkSwapMux, -- out\r
- FrmClkMsbRegEna => IntClkMsbRegEna, -- out\r
- FrmClkLsbRegEna => IntClkLsbRegEna, -- out\r
- FrmClkReSyncOut => IntFrmClkReSyncOut, -- out\r
- FrmClkDat => open, -- out\r
- FrmClkSyncWarn => AdcFrmSyncWrn_S, -- out\r
- Frame_out => frame_S,\r
- testOK => testOK_S,\r
- testword0 => testword0_S
-);\r
-adcfrmsyncwrn <= adcfrmsyncwrn_S;\r
-testOK <= testOK_S;
------------------------------------------------------------------------------------------------\r
--- DATA INPUTS\r
--- Default the interface is set in BYTE and MSB first mode.\r
--- This is coded in the AdcData level and can be mnodified if wanted.\r
--- Enable the generics and all selection possibilities are available. \r
------------------------------------------------------------------------------------------------\r
-Gen_2 : for cw in ((C_AdcChnls/2)*C_AdcWireInt)-1 downto 0 generate\r
--- assert false\r
--- report int_to_str((32*((cw+1)+(p*C_AdcChnls))),10)\r
--- severity note;\r
- AdcToplevel_I_AdcData : AdcData -- entity AdcData.AdcData\r
- generic map (\r
- C_AdcBits => C_AdcBits, -- Can be 12, 14 or 16\r
- C_AdcWireInt => C_AdcWireInt -- 1 = 1-wire, 2 = 2-wire.\r
- )\r
- port map (\r
- DatD0_n => DATA_n(cw*2), -- in \r
- DatD0_p => DATA_p(cw*2), -- in \r
- DatD1_n => DATA_n((cw*2)+1), -- in \r
- DatD1_p => DATA_p((cw*2)+1), -- in \r
- DatClk => IntClk, -- in \r
- DatClkDiv => IntClkDiv, -- in \r
- DatRst => IntRst_S, -- in \r
- DatEna => IntEna_S, -- in \r
- DatDone => IntBitClkDone, -- IntBitClkDone_S, -- in \r
- DatBitSlip_p => IntClkBitSlip_p, -- in \r
- DatBitSlip_n => IntClkBitSlip_n, -- in \r
- DatSwapMux => IntClkSwapMux, -- in \r
- DatMsbRegEna => IntClkMsbRegEna, -- in \r
- DatLsbRegEna => IntClkLsbRegEna, -- in \r
- DatReSync => IntFrmClkReSyncOut, -- in\r
- DatOut => IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-32)\r
- );\r
- \r
- \r
---AdcDataOut((32*(cw+1))-1 downto (32*(cw+1))-(32/C_AdcWireInt)) <= IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-(32/C_AdcWireInt));\r
-\r
-\r
-\r
-end generate Gen_2;\r
-\r
- \r
-process(IntClkDiv)\r
-begin\r
- if (rising_edge(IntClkDiv)) then \r
- AdcReSync_S <= AdcReSync;\r
- end if;\r
-end process;\r
-\r
--- reset_clockdiv_S <= '1' when (frame_S='0') and (reset_clockdiv0_S='1') else '0';\r
-reset_clockdiv : FDPE\r
- generic map (INIT => '1')\r
- port map (C => frame_S, CE => High, PRE => AdcIntrfcRst, D => Low, Q => reset_clockdiv_S);\r
-\r
---process(SysRefClk)\r
---begin\r
--- if (rising_edge(SysRefClk)) then \r
--- if (AdcIntrfcRst='1') then -- or (ClockResync0_S='1') then\r
--- reset_clockdiv0_S <= '1';\r
--- elsif frame_S='1' then\r
--- reset_clockdiv0_S <= '0';\r
--- end if;\r
--- end if;\r
---end process;\r
-\r
---process(IntClkDiv,reset_clockdiv0_S)\r
---variable counter_V : integer range 0 to 3 := 0;\r
---begin\r
--- if reset_clockdiv0_S='1' then\r
--- ClockResync_S <= '0';\r
--- counter_V := 0;\r
--- elsif (rising_edge(IntClkDiv)) then\r
--- if counter_V<3 then\r
--- counter_V := counter_V+1;\r
--- ClockResync_S <= '1';\r
--- else\r
--- ClockResync_S <= '0';\r
--- end if;\r
--- end if;\r
---end process;\r
-ClockResync_S <= ClockResync0_S;\r
-process(IntClkDiv,AdcIntrfcRst) -- reset_clockdiv_S)\r
-begin\r
--- if reset_clockdiv_S='1' then\r
- if AdcIntrfcRst='1' then\r
- slipoccurred_S <= '0';\r
- slipsoccurred_S <= '0';\r
- slipcounter_S <= 0;\r
- ClockResync0_S <= '0';\r
- IntBitClkDone_S <= '0';\r
- IntEna_S <= '0';\r
- IntRst_S <= '0';\r
- ADCs_ready <= '0';\r
- elsif (rising_edge(IntClkDiv)) then\r
- if (IntBitClkDone='0') or (ClockResync_S='1') then\r
- slipcounter_S <= 0;\r
- slipoccurred_S <= '0';\r
- slipsoccurred_S <= '0';\r
- ClockResync0_S <= '0';\r
- IntBitClkDone_S <= '0';\r
- IntEna_S <= '0';\r
- IntRst_S <= '0';\r
- ADCs_ready <= '0';\r
- elsif slipcounter_S<2 then\r
- slipcounter_S <= slipcounter_S+1;\r
- ClockResync0_S <= '0';\r
- slipoccurred_S <= '0';\r
- slipsoccurred_S <= '0';\r
- IntBitClkDone_S <= '0';\r
- IntEna_S <= '0';\r
- IntRst_S <= '0';\r
- elsif slipcounter_S<31 then\r
- slipcounter_S <= slipcounter_S+1;\r
- ClockResync0_S <= '0';\r
- slipoccurred_S <= '0';\r
- slipsoccurred_S <= '0';\r
- IntBitClkDone_S <= '0';\r
- IntEna_S <= '0';\r
- IntRst_S <= '0';\r
- elsif slipcounter_S<33 then\r
- slipcounter_S <= slipcounter_S+1;\r
- IntRst_S <= '1';\r
- elsif slipcounter_S<63 then\r
- slipcounter_S <= slipcounter_S+1;\r
- IntRst_S <= '0';\r
- elsif slipcounter_S<95 then\r
- slipcounter_S <= slipcounter_S+1;\r
- IntEna_S <= '1';\r
- elsif slipcounter_S<111 then\r
- slipcounter_S <= slipcounter_S+1;\r
- IntBitClkDone_S <= '1';\r
- elsif slipcounter_S<254 then\r
- slipcounter_S <= slipcounter_S+1;\r
- IntBitClkDone_S <= '1';\r
- if (IntClkBitSlip_p='1') then\r
- if slipoccurred_S='1' then \r
- slipsoccurred_S <= '1';\r
- end if;\r
- slipoccurred_S <= '1';\r
- end if;\r
- if (IntClkBitSlip_n='1') then\r
- slipsoccurred_S <= '1';\r
- slipoccurred_S <= '1';\r
- end if;\r
- elsif slipcounter_S<255 then\r
- slipcounter_S <= slipcounter_S+1;\r
--- if (slipsoccurred_S='1') or (testOK_S='0') or (IntClkSwapMux='1') or (AdcBitClkInvrtd_S='0') or (AdcBitClkAlgnWrn_S='1') then\r
- if (slipsoccurred_S='1') or (IntClkSwapMux='1') or (AdcBitClkAlgnWrn_S='1') then\r
--- if (testOK_S='0') or (IntClkSwapMux='1') or (AdcBitClkAlgnWrn_S='1') then\r
- ClockResync0_S <= '1';\r
- else\r
- ADCs_ready <= '1';\r
- end if;\r
- else\r
- ClockResync0_S <= '0';\r
- end if;\r
- end if;\r
-end process;\r
-\r
-\r
-\r
-\r
------------------------------------------------------------------------------------------------\r
---\r
-\r
---1000
-testword0(0) <= IntRst;
-testword0(1) <= AdcReSync_S;
-testword0(2) <= AdcBitClkAlgnWrn_S;
-testword0(3) <= AdcBitClkInvrtd_S;\r
-\r
---0001
-testword0(4) <= IntBitClkDone;
-testword0(5) <= IntClkBitSlip_p;
-testword0(6) <= IntClkBitSlip_n;
-testword0(7) <= IntClkSwapMux;\r
-\r
---0011
-testword0(8) <= IntRst_S; -- IntClkMsbRegEna;
-testword0(9) <= IntEna_S; -- IntClkLsbRegEna;
-testword0(10) <= IntFrmClkReSyncOut;
-testword0(11) <= AdcFrmSyncWrn_S;\r
-\r
---1000
-testword0(12) <= AdcIntrfcRst;
-testword0(13) <= testOK_S;\r
-testword0(14) <= Frame_S;\r
-testword0(15) <= AdcIdlyCtrlRdy_S;\r
-\r
-testword0(16) <= AdcReSync_S;\r
-testword0(17) <= slipoccurred_S;\r
-testword0(18) <= slipsoccurred_S;\r
-testword0(19) <= IntBitClkDone_S;\r
-testword0(20) <= ClockResync_S;\r
-testword0(21) <= ClockResync0_S;\r
-testword0(22) <= reset_clockdiv_S;\r
-testword0(23) <= reset_clockdiv_S;\r
-\r
-\r
--- testword0(23 downto 16) <= testword0_S(7 downto 0);\r
-
-testword0(35 downto 24) <= (others => '0');
-\r
-end AdcToplevel_struct;
\ No newline at end of file
+++ /dev/null
----------------------------------------------------------------------------------------------\r
--- © Copyright 2011, Xilinx, Inc. All rights reserved.\r
--- This file contains confidential and proprietary information of Xilinx, Inc. and is\r
--- protected under U.S. and international copyright and other intellectual property laws.\r
----------------------------------------------------------------------------------------------\r
---\r
--- Disclaimer:\r
--- This disclaimer is not a license and does not grant any rights to the materials\r
--- distributed herewith. Except as otherwise provided in a valid license issued to you\r
--- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS\r
--- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL\r
--- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED\r
--- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR\r
--- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including\r
--- negligence, or under any other theory of liability) for any loss or damage of any\r
--- kind or nature related to, arising under or in connection with these materials,\r
--- including for any direct, or any indirect, special, incidental, or consequential\r
--- loss or damage (including loss of data, profits, goodwill, or any type of loss or\r
--- damage suffered as a result of any action brought by a third party) even if such\r
--- damage or loss was reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
---\r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-safe, or for use in any\r
--- application requiring fail-safe performance, such as life-support or safety devices\r
--- or systems, Class III medical devices, nuclear facilities, applications related to\r
--- the deployment of airbags, or any other applications that could lead to death,\r
--- personal injury, or severe property or environmental damage (individually and\r
--- collectively, "Critical Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical Applications, subject only to\r
--- applicable laws and regulations governing limitations on product liability.\r
---\r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.\r
---\r
--- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx Inc.\r
--- \ \ \/ Version:\r
--- \ \ Filename: DoubleNibbleDetect.vhd\r
--- / / Date Created: 16 March, 2011\r
--- /___/ /\ Date Last Modified: 16 March, 2011\r
--- \ \ / \\r
--- \___\/\___\\r
---\r
--- Device: Virtex-6\r
--- Author: defossez\r
--- Entity Name: DoubleNibbleDetect\r
--- Purpose: Create a on-off signal that already reacts at the combinatorial input.\r
--- Tools: ISE_13.1\r
--- Limitations: none\r
---\r
--- Revision History:\r
--- Rev.\r
---\r
-------------------------------------------------------------------------------\r
--- Naming Conventions:\r
--- active low signals: "*_n"\r
--- clock signals: "clk", "clk_div#", "clk_#x"\r
--- reset signals: "rst", "rst_n"\r
--- generics: "C_*"\r
--- user defined types: "*_TYPE"\r
--- state machine next state: "*_ns"\r
--- state machine current state: "*_cs"\r
--- combinatorial signals: "*_com"\r
--- pipelined or register delay signals: "*_d#"\r
--- counter signals: "*cnt*"\r
--- clock enable signals: "*_ce"\r
--- internal version of output port: "*_i"\r
--- device pins: "*_pin"\r
--- ports: "- Names begin with Uppercase"\r
--- processes: "*_PROCESS"\r
--- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
----------------------------------------------------------------------------------------------\r
-library IEEE;\r
- use IEEE.std_logic_1164.all;\r
- use IEEE.std_logic_UNSIGNED.all;\r
-library UNISIM;\r
- use UNISIM.vcomponents.all;\r
----------------------------------------------------------------------------------------------\r
--- Entity pin description\r
----------------------------------------------------------------------------------------------\r
--- Clock : Clock for the design.\r
--- RstIn : Reset input. Resets the necessary logic at startup.\r
--- Final : This circuit checks a nibble (4-bit) for appearing twice, when for rotations or\r
--- slips are made, teh fifth ossurence resets the circuit. this is signalled ouside\r
--- so that a upper layer of design can take action. \r
--- DataIn : Nibble input.\r
--- DataOut : Corrected nibble output.\r
----------------------------------------------------------------------------------------------\r
-entity DoubleNibbleDetect is\r
- port (\r
- Clock : in std_logic;\r
- RstIn : in std_logic;\r
- Final : out std_logic;\r
- DataIn : in std_logic_vector(3 downto 0);\r
- DataOut : out std_logic_vector(3 downto 0)\r
- );\r
-end DoubleNibbleDetect;\r
----------------------------------------------------------------------------------------------\r
--- Architecture section\r
----------------------------------------------------------------------------------------------\r
-architecture DoubleNibbleDetect_struct of DoubleNibbleDetect is\r
----------------------------------------------------------------------------------------------\r
--- Component Instantiation\r
----------------------------------------------------------------------------------------------\r
----------------------------------------------------------------------------------------------\r
--- Constants, Signals and Attributes Declarations\r
----------------------------------------------------------------------------------------------\r
--- Functions\r
--- Constants\r
-constant Low : std_logic := '0';\r
-constant High : std_logic := '1';\r
--- Signals\r
-signal IntRegOutIn : std_logic_vector(3 downto 0);\r
-signal IntAddr : std_logic_vector(4 downto 0);\r
-signal IntSrlOut : std_logic_vector(3 downto 0);\r
---\r
-signal IntRegOutIn_s : std_logic_vector(3 downto 0);\r
-signal IntAddr_s : std_logic_vector(4 downto 0);\r
-signal IntSrlOut_s : std_logic_vector(3 downto 0);\r
-signal DataOut_s : std_logic_vector(3 downto 0);\r
---\r
-signal IntEqu : std_logic;\r
-signal IntEqu_d : std_logic;\r
-signal IntPulse : std_logic;\r
-signal IntSlipCnt : std_logic_vector(3 downto 0);\r
-signal IntSlipCnt_d : std_logic_vector(3 downto 0);\r
-signal IntSlipCntRst : std_logic;\r
-signal IntEquCnt : std_logic_vector(3 downto 0);\r
-signal IntEquCnt_d : std_logic_vector(3 downto 0);\r
---\r
-signal IntRstSet : std_logic;\r
-signal IntRstIn : std_logic;\r
-signal IntRstFf_d : std_logic_vector(7 downto 0) := X"00";\r
-signal IntRstIn_d : std_logic;\r
---\r
-signal IntAddrSet : std_logic_vector(3 downto 0);\r
--- Attributes\r
-attribute IOB : string;\r
-attribute HBLKNM : string;\r
----------------------------------------------------------------------------------------------\r
-begin\r
----------------------------------------------------------------------------------------------\r
--- Delay the start of the ciruit after reset.\r
----------------------------------------------------------------------------------------------\r
-IntRstIn <= RstIn or IntRstSet;\r
---\r
-Gen_Rst : for n in 0 to 7 generate\r
- Reg_Lsb : if n = 0 generate\r
- DbleNibl_I_Fdse : FDSE -- Synchronous set\r
- generic map (INIT => '0')\r
- port map (D => Low, CE => High, C => Clock, S => IntRstSet, Q => IntRstFf_d(n));\r
- end generate Reg_Lsb;\r
- Reg_MidL : if n > 0 and n <= 5 generate\r
- DbleNibl_I_Fdse : FDSE -- Synchronous set\r
- generic map (INIT => '0')\r
- port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstSet,\r
- Q => IntRstFf_d(n));\r
- end generate Reg_MidL;\r
- Reg_MidH : if n = 6 generate\r
- DbleNibl_I_Fdse : FDSE -- Synchronous set\r
- generic map (INIT => '0')\r
- port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstIn,\r
- Q => IntRstFf_d(n));\r
- end generate Reg_MidH;\r
- Reg_Msb : if n = 7 generate\r
- DbleNibl_I_Fdse : FDSE -- Synchronous set\r
- generic map (INIT => '0')\r
- port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstIn,\r
- Q => IntRstFf_d(n));\r
- --\r
- IntRstIn_d <= IntRstFf_d(n);\r
- end generate Reg_Msb;\r
-end generate Gen_Rst;\r
----------------------------------------------------------------------------------------------\r
--- Data path registers\r
----------------------------------------------------------------------------------------------\r
-Gen_Reg : for n in 3 downto 0 generate\r
- In_I_Fdce : FDCE\r
- generic map (INIT => '0')\r
- port map (D => DataIn(n), CE => High, C => Clock, CLR => IntRstIn_d,\r
- Q => IntRegOutIn_s(n));\r
-IntRegOutIn(n) <= IntRegOutIn_s(n); -- after 100 ps;\r
- DbleNibl_I_Srlc32e : SRLC32E\r
- generic map (INIT => X"00000000")\r
- port map (D => IntRegOutIn(n), A => IntAddr, CE => High, CLK => Clock, Q31 => open,\r
- Q => IntSrlOut_s(n));\r
-IntSrlOut(n) <= IntSrlOut_s(n); -- after 100 ps;\r
- Out_I_Fdce : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntSrlOut(n), CE => High, C => Clock, CLR => IntRstIn_d,\r
- Q => DataOut_s(n));\r
-DataOut(n) <= DataOut_s(n); -- after 100 ps;\r
-end generate Gen_Reg;\r
----------------------------------------------------------------------------------------------\r
--- Compare present and past for equality.\r
----------------------------------------------------------------------------------------------\r
-IntEqu <= '1' when (DataIn = IntRegOutIn) else '0';\r
------------------------------------------------------------------------------------------------\r
--- Generate the SRL addresses\r
----------------------------------------------------------------------------------------------\r
-IntAddr(3 downto 0) <= "0100" when (IntEquCnt_d = "0000" and IntSlipCnt_d = "0000") else\r
- "0011" when (IntEquCnt_d = "0001" and IntSlipCnt_d = "0111") else\r
- "0010" when (IntEquCnt_d = "0011" and IntSlipCnt_d = "0110") else\r
- "0001" when (IntEquCnt_d = "0010" and IntSlipCnt_d = "0010") else\r
- "0000" when (IntEquCnt_d = "0110" and IntSlipCnt_d = "0011") else\r
- "0100" when (IntEquCnt_d = "0111" and IntSlipCnt_d = "0001");\r
-IntAddr(4) <= Low;\r
---IntRstSet <= '1' when (IntEquCnt_d = "0111" and IntSlipCnt_d = "0001") else '0';\r
-IntRstSet <= '1' when (IntEquCnt_d = "0110" and IntSlipCnt_d = "0000" and IntPulse = '1')\r
- else '0';\r
-Final <= IntRstSet;\r
----------------------------------------------------------------------------------------------\r
--- Equal/Double nibble detect counters\r
----------------------------------------------------------------------------------------------\r
-IntPulse <= IntEqu or IntEqu_d;\r
---\r
-DbleNibl_I_Fdce : FDCE -- Asynchronous reset\r
- generic map (INIT => '0')\r
- port map (D => High, CE => IntEqu, C => Clock, CLR => IntSlipCntRst, Q => IntEqu_d);\r
--- When a double nibble is detected shift the pulse over four taps and reset the shifter\r
--- at the fifth tap.\r
----------------------------------------------------------------------------------------------\r
--- Slip Counter\r
--- When equality is detected, this counter counts till a preset number and then resets.\r
----------------------------------------------------------------------------------------------\r
-IntSlipCntRst <= '1' when (IntRstIn_d = '1' or IntSlipCnt_d = "0101") else '0';\r
---\r
-Gen_SlipCnt : for n in 3 downto 0 generate\r
- attribute HBLKNM of Cnt_I_Fdre : label is "SlipCnt";\r
- attribute IOB of Cnt_I_Fdre : label is "FALSE";\r
- begin\r
- Cnt_I_Fdre : FDRE -- Synchronous reset\r
- generic map (INIT => '0')\r
- port map (D => IntSlipCnt(n), CE => IntPulse, C => Clock, R => IntSlipCntRst,\r
- Q => IntSlipCnt_d(n));\r
-end generate Gen_SlipCnt;\r
--- These ar the "SlipCnt" states, orginized in Gray mode\r
-DbleNibl_SlipCnt_PROCESS : process (IntSlipCnt_d)\r
-begin\r
- case IntSlipCnt_d(3 downto 0) is\r
- when "0000" => IntSlipCnt <= "0001"; -- after 100 ps;\r
- when "0001" => IntSlipCnt <= "0011"; -- after 100 ps;\r
- when "0011" => IntSlipCnt <= "0010"; -- after 100 ps;\r
- when "0010" => IntSlipCnt <= "0110"; -- after 100 ps;\r
- when "0110" => IntSlipCnt <= "0111"; -- after 100 ps;\r
- when "0111" => IntSlipCnt <= "0101"; -- after 100 ps;\r
- when "0101" => IntSlipCnt <= "0000"; -- after 100 ps;\r
- when others => IntSlipCnt <= "0000"; -- after 100 ps;\r
- end case;\r
-end process;\r
----------------------------------------------------------------------------------------------\r
--- Equ Counter\r
--- Count how many times a double nibble is detected.\r
--- becuase a nibble of data is taken, it can only be four times.\r
--- When equality is detected for the fift time the system is reset.\r
----------------------------------------------------------------------------------------------\r
-Gen_EquCnt : for n in 3 downto 0 generate\r
- attribute HBLKNM of Equ_I_Fdre : label is "EquCnt";\r
- attribute IOB of Equ_I_Fdre : label is "FALSE";\r
- begin\r
- Equ_I_Fdre : FDRE -- Synchronous reset\r
- generic map (INIT => '0')\r
- port map (D => IntEquCnt(n), CE => IntEqu, C => Clock, R => IntRstIn_d,\r
- Q => IntEquCnt_d(n));\r
-end generate Gen_EquCnt;\r
---\r
-DbleNibl_EquCnt_PROCESS : process (IntEquCnt_d)\r
-begin\r
- case IntEquCnt_d(3 downto 0) is\r
- when "0000" => IntEquCnt <= "0001"; -- after 100 ps;\r
- when "0001" => IntEquCnt <= "0011"; -- after 100 ps;\r
- when "0011" => IntEquCnt <= "0010"; -- after 100 ps;\r
- when "0010" => IntEquCnt <= "0110"; -- after 100 ps;\r
- when "0110" => IntEquCnt <= "0111"; -- after 100 ps;\r
- when "0111" => IntEquCnt <= "0101"; -- after 100 ps;\r
- when "0101" => IntEquCnt <= "0100"; -- after 100 ps;\r
- when "0100" => IntEquCnt <= "1100"; -- after 100 ps;\r
- when "1100" => IntEquCnt <= "1101"; -- after 100 ps;\r
- when "1101" => IntEquCnt <= "1111"; -- after 100 ps;\r
- when "1111" => IntEquCnt <= "1110"; -- after 100 ps;\r
- when "1110" => IntEquCnt <= "1010"; -- after 100 ps;\r
- when "1010" => IntEquCnt <= "1011"; -- after 100 ps;\r
- when "1011" => IntEquCnt <= "1001"; -- after 100 ps;\r
- when "1001" => IntEquCnt <= "1000"; -- after 100 ps;\r
- when "1000" => IntEquCnt <= "0000"; -- after 100 ps;\r
- when others => IntEquCnt <= "0000"; -- after 100 ps;\r
- end case;\r
-end process;\r
---\r
----------------------------------------------------------------------------------------------\r
-end DoubleNibbleDetect_struct;\r
+++ /dev/null
------------------------------------------------------------------------------------------------\r
--- © Copyright 2008 - 2009, Xilinx, Inc. All rights reserved.\r
--- This file contains confidential and proprietary information of Xilinx, Inc. and is\r
--- protected under U.S. and international copyright and other intellectual property laws.\r
------------------------------------------------------------------------------------------------\r
---\r
--- Disclaimer:\r
--- This disclaimer is not a license and does not grant any rights to the materials\r
--- distributed herewith. Except as otherwise provided in a valid license issued to you\r
--- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS\r
--- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL\r
--- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED\r
--- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR\r
--- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including\r
--- negligence, or under any other theory of liability) for any loss or damage of any\r
--- kind or nature related to, arising under or in connection with these materials,\r
--- including for any direct, or any indirect, special, incidental, or consequential\r
--- loss or damage (including loss of data, profits, goodwill, or any type of loss or\r
--- damage suffered as a result of any action brought by a third party) even if such\r
--- damage or loss was reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
---\r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-safe, or for use in any\r
--- application requiring fail-safe performance, such as life-support or safety devices\r
--- or systems, Class III medical devices, nuclear facilities, applications related to\r
--- the deployment of airbags, or any other applications that could lead to death,\r
--- personal injury, or severe property or environmental damage (individually and\r
--- collectively, "Critical Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical Applications, subject only to\r
--- applicable laws and regulations governing limitations on product liability.\r
---\r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. \r
---\r
--- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx\r
--- \ \ \/ Version: \r
--- \ \ Filename: GenPulse.vhd\r
--- / / Date Last Modified: \r
--- /___/ /\ Date Created: 08 Mar 08 \r
--- \ \ / \\r
--- \___\/\___\\r
--- \r
--- Device: \r
--- Author: Marc Defossez\r
--- Entity Name: GenPulse\r
--- Purpose: Generate a clock cycle wide pulse from a wide high input\r
--- Tools: ISE_10.1\r
--- Limitations: none\r
---\r
--- Revision History:\r
--- Rev. \r
---\r
------------------------------------------------------------------------------------------------\r
--- Naming Conventions:\r
--- active low signals: "*_n"\r
--- clock signals: "clk", "clk_div#", "clk_#x"\r
--- reset signals: "rst", "rst_n"\r
--- generics: "C_*"\r
--- user defined types: "*_TYPE"\r
--- state machine next state: "*_ns"\r
--- state machine current state: "*_cs"\r
--- combinatorial signals: "*_com"\r
--- pipelined or register delay signals: "*_d#"\r
--- counter signals: "*cnt*"\r
--- clock enable signals: "*_ce"\r
--- internal version of output port: "*_i"\r
--- device pins: "*_pin"\r
--- ports: "- Names begin with Uppercase"\r
--- processes: "*_PROCESS"\r
--- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
------------------------------------------------------------------------------------------------\r
---\r
-library IEEE;\r
- use IEEE.std_logic_1164.all;\r
- use IEEE.std_logic_UNSIGNED.all;\r
-library UNISIM;\r
- use UNISIM.VCOMPONENTS.all;\r
------------------------------------------------------------------------------------------------\r
--- Entity pin description\r
------------------------------------------------------------------------------------------------\r
---\r
------------------------------------------------------------------------------------------------\r
-entity GenPulse is\r
- port (\r
- Clk : in std_logic;\r
- Ena : in std_logic;\r
- SigIn : in std_logic;\r
- SigOut : out std_logic\r
- );\r
-end GenPulse;\r
-\r
------------------------------------------------------------------------------------------------\r
--- Arcitecture section\r
------------------------------------------------------------------------------------------------\r
-architecture GenPulse_struct of GenPulse is\r
------------------------------------------------------------------------------------------------\r
--- Component Instantiation\r
------------------------------------------------------------------------------------------------\r
------------------------------------------------------------------------------------------------\r
--- Constants, Signals and Attributes Declarations\r
------------------------------------------------------------------------------------------------\r
--- Functions\r
--- Constants\r
--- constant Low : std_logic := '0';\r
--- constant High : std_logic := '1';\r
--- Signals\r
-signal IntSigOut : std_logic;\r
-signal IntSigIn_n : std_logic;\r
-signal IntSigClr : std_logic;\r
--- Attributes\r
------------------------------------------------------------------------------------------------\r
---\r
-begin\r
---\r
-GenPulse_I_Fdce_1 : FDCE\r
- generic map (INIT => '0')\r
- port map (D => SigIn, C => Clk, CLR => IntSigClr, CE => Ena, Q => IntSigOut);\r
---\r
-IntSigIn_n <= not SigIn;\r
---\r
-GenPulse_I_Fdce_2 : FDCE\r
- generic map (INIT => '0')\r
- port map (D => IntSigOut, C => Clk, CLR => IntSigIn_n, CE => IntSigOut, Q => IntSigClr);\r
---\r
-SigOut <= IntSigOut;\r
---\r
------------------------------------------------------------------------------------------------\r
-end GenPulse_struct;\r
---
\ No newline at end of file
+++ /dev/null
------------------------------------------------------------
--- LMK03033 CONTROL UNIT --
--- --
--- uWIRE configuration Loader --
------------------------------------------------------------
--- Device: xc5vlx50t-3ff665 --
--- ISE 11.4 --
--- created 15 Nov 2011 by Walter Puccio --
--- Uppsala University, IRFU --
--- Modified 23 Jan 2011 by P. Marciniewski --
--- Uppsala University, Dept of Physics and Astronomy --
------------------------------------------------------------
-\r
-\r
--- LMK03806:\r
--- refclock/R = VCO/(P*N)\r
--- CLKout = VCO/Divide\r
---\r
--- refclock : reference input clock\r
--- R = R-divider (register 28)\r
--- VCO = Voltage Controlled Oscillator = 2370..2600 MHz\r
--- P = Prescaler : 2..8\r
--- N = N-divider\r
--- CLKout = Clock outputs (CLKout0..11)\r
--- Divide = outputclock divider\r
---\r
--- 80MHz -> 80 MHz :\r
--- R=1, VCO=2560, P=2, N=16, divide=32\r
---
--- 40MHz -> 80 MHz :\r
--- R=1, VCO=2560, P=2, N=32, divide=32\r
--- 40MHz -> 80 MHz :\r
--- R=1, VCO=2560, P=4, N=16, divide=32\r
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
---use work.util_pack.ALL;
-
-entity LMK03806 is
- generic(
- CLK_DIV : integer := 6; -- slow down transfer
- ADCCLOCKFREQUENCY : natural := 62500000
- );
- PORT(
- clock : in std_logic; --Master clock
- CLKu : out std_logic; --Clk to LMK
- DATAu : out std_logic; --Data to LMK
- LEu : out std_logic; --Data Latch to LMK
- RDn : in std_logic; --Read back
- SYNC : out std_logic; --Sync CLK outputs LMK
- boot_PLL : in std_logic; --Start booting when set high
- reset_GTX : out std_logic; --delayed reset for GTX
- reset_ADCs : out std_logic; --delayed reset for ADCs
- booting : out std_logic; --busy signal \r
- testwordin : in std_logic_vector(15 downto 0)
- );
-end LMK03806;
-
-
-----------------------------------------------------------------
-
-architecture Behavioral of LMK03806 is
-constant NROFREGS : integer := 23+1+6;
-type RomType is array (0 to NROFREGS-1) of std_logic_vector(31 downto 0);
-type RomType32 is array (0 to 31) of std_logic_vector(31 downto 0);
--- parameters based on 'Clock design tool' from National Semiconductor
-CONSTANT TAB80M : RomType :=
--- 80MHz reference to 80MHz\r
- (
- x"00020000", -- R0 (Reset=1)
- x"00020000", -- R0 (Reset=1)
- X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
- X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
- X"00000401", --R1 (Div=40 OUT2,3 80MHz)
- X"00000401", --R1 (Div=40 OUT2,3 80MHz)
- X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
- X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
- X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
- X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
- X"00000404", --R4 (Div=40 OUT8,9 80MHz)
- X"00000404", --R4 (Div=40 OUT8,9 80MHz)
- X"00000405", --R5 (Div=40 OUT10,11 80MHz)
- X"00000405", --R5 (Div=40 OUT10,11 80MHz)
- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
- x"55555549", -- R9 (fixed pattern)
- x"1000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
- x"7B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
- x"0300000E", -- R14 (GPout1=weak pulldown)
- x"C1550410", -- R16 (fixed pattern)
- x"DD000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
- x"83A8001A", -- R26 (reffrequ=normal chargepump=100uA PLL_DLD_CNT=8192 ???????????)
- x"0010001C", -- R28 (R_divider=1
- x"0080041D", -- R29 (OSCin=63MHz..127MHz N_CALdivider=32
- x"0200041E", -- R30 (N_prescaler=2 N_divider=32)
- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
- ); \r
-\r
-\r
-CONSTANT TAB80M_orig : RomType :=
--- 80MHz reference to 80MHz
- (
- x"00020000", -- R0 (Reset=1)
- x"00020000", -- R0 (Reset=1)
- X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
- X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
- X"00000401", --R1 (Div=40 OUT2,3 80MHz)
- X"00000401", --R1 (Div=40 OUT2,3 80MHz)
- X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
- X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
- X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
- X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
- X"00000404", --R4 (Div=40 OUT8,9 80MHz)
- X"00000404", --R4 (Div=40 OUT8,9 80MHz)
- X"00000405", --R5 (Div=40 OUT10,11 80MHz)
- X"00000405", --R5 (Div=40 OUT10,11 80MHz)
- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
- x"55555549", -- R9 (fixed pattern)
- x"1000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
- x"7B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
- x"0300000E", -- R14 (GPout1=weak pulldown)
- x"C1550410", -- R16 (fixed pattern)
- x"DD000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
- x"83A8001A", -- R26 (reffrequ=normal chargepump=100uA PLL_DLD_CNT=8192 ???????????)
- x"0010001C", -- R28 (R_divider=1 ????????? :2
- x"0180021D", -- R29 (OSCin=63MHz..127MHz N_CALdivider=16
- x"0200021E", -- R30 (N_prescaler=2 N_divider=16)
- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
- );
-\r
---CONSTANT TAB62M5 : RomType :=
----- 62.5MHz reference to 62.5MHz\r
--- (
--- x"00020000", -- R0 (Reset=1)
--- x"00020000", -- R0 (Reset=1)
--- X"00000500", --R0 (Reset=0, Div=40 OUT0,1 62.5MHz)
--- X"00000500", --R0 (Reset=0, Div=40 OUT0,1 62.5MHz)
--- X"00000501", --R1 (Div=40 OUT2,3 62.5MHz)
--- X"00000501", --R1 (Div=40 OUT2,3 62.5MHz)
--- X"00000502", --R2 (Div=20 OUT4,5 125MHz, GTX0) 00000282
--- X"00000502", --R2 (Div=20 OUT4,5 125MHz, GTX0) 00000282
--- X"00000503", --R3 (Div=20 OUT6,7 125MHz, GTX1) 00000283
--- X"00000503", --R3 (Div=20 OUT6,7 125MHz, GTX1) 00000283
--- X"00000504", --R4 (Div=40 OUT8,9 62.5MHz)
--- X"00000504", --R4 (Div=40 OUT8,9 62.5MHz)
--- X"00000505", --R5 (Div=40 OUT10,11 62.5MHz)
--- X"00000505", --R5 (Div=40 OUT10,11 62.5MHz)
--- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
--- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
--- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
--- x"55555549", -- R9 (fixed pattern)
--- x"1000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
--- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
--- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
--- x"7B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
--- x"0300000E", -- R14 (GPout1=weak pulldown)
--- x"C1550410", -- R16 (fixed pattern)
--- x"DD000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
--- x"83A8001A", -- R26 (reffrequ=normal chargepump=100uA PLL_DLD_CNT=8192 ???????????)
--- x"0010001C", -- R28 (R_divider=1 ????????? :2
--- x"0080029D", -- R29 (OSCin=0..63MHz N_CALdivider=20
--- x"0200029E", -- R30 (N_prescaler=2 N_divider=20)
--- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
--- );
-
--- (
--- X"000204c0", --R0 (Reset=1, Div=38 OUT0,1)
--- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
--- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
--- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0)
--- X"00000163", --R3 (Div=19 OUT6,7 125MHz, GTX1)
--- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
--- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
--- X"11110006", --R6 (OUT3,2,1,0 : LVDS)
--- X"11110007", --R7 (OUT7,6,5,4 : LVDS)
--- X"11110008", --R8 (OUT11,10,9,8 : LVDS)
--- X"55555549", --R9 (fixed)
--- X"1002400a", --R10 (OSCout0=700mV OSCout1=off OSCout=disabled OSC0,1=bypass_divider OSCoutDIV=2)
--- X"3400000b", --R11 (SYNC=enabled, active=high, externalXTAL=disabled)
--- X"138c006c", --R12 (LD_MUX=PLL_DLD, LD_TYPE=output, Force sync)
--- X"7b03800d", --R13 (READ_BACK=pushpull, GPout0=weak pulldown)
--- X"0300000e", --R14 (GPout1=weak pulldown)
--- X"c1550410", --R16 (fixed)
--- X"00000018", --R24 (LoopFilter: C4=10pF, C3=10pF, R4=200Ohm, R3=200Ohm)
--- X"8fa8001a", --R26 (reffrequ=normal, chargepump=3.2mA, PLL_DLD_CNT=8192 ???????????)
--- X"0010001c", --R28 (R_divider=1,
--- X"0080027d", --R29 (OSCin=0..63MHz, N_CALdivider=19 ?????????????)
--- X"0100027e", --R30 (N_prescaler=2, N_divider=19)
--- X"0000001f" --R31 (ReadbackReg=0, Regs:unlocked)
--- );
-
--- (
--- x"80020140", -- R0 (Reset=1 Div=10 OUT0..1 -> PWD)
--- x"00000400", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
--- x"00000401", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
--- x"00000202", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
--- x"00000203", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
--- x"00000404", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
--- x"00000405", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
--- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
--- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
--- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
--- x"55555549", -- R9 (fixed pattern)
--- x"9102400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
--- x"343f100B", -- R11 (SYNC=enabled active=low, pulldownR externalXTAL=disabled) -- peter, was 3401100B
--- x"138C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync) -- peter, was 130C006C
--- x"3B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown) -- peter, was 3B03826D
--- x"0300000E", -- R14 (GPout1=weak pulldown)
--- x"C1550410", -- R16 (fixed pattern)
--- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
--- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
--- x"0010001C", -- R28 (R_divider=2 -- peter, was 0010001C
--- x"0180021D", -- R29 (OSCin=127..255Hz N_CALdivider=16 ?????????????) -- peter, was 0280011D
--- x"0200021E", -- R30 (N_prescaler=2 N_divider=16) -- peter, was 0200011E
--- x"001F001F" -- R31 (ReadbackReg=31 Regs:unlocked)
--- );
-
--- ( -- Pawel
--- x"80020140", -- R0 (Reset=1 Div=10 OUT0..1 -> PWD)
--- x"00000400", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
--- x"00000401", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
--- x"00000202", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
--- x"00000203", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
--- x"00000404", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
--- x"00000405", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
--- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
--- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
--- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
--- x"55555549", -- R9 (fixed pattern)
--- x"9102400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
--- x"3401100B", -- R11 (SYNC=enabled active=high externalXTAL=disabled)
--- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
--- x"3B03826D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
--- x"0300000E", -- R14 (GPout1=weak pulldown)
--- x"C1550410", -- R16 (fixed pattern)
--- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
--- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
--- x"0010001C", -- R28 (R_divider=1
--- x"0080021D", -- R29 (OSCin=0..63MHz N_CALdivider=19 ?????????????)
--- x"0200021E", -- R30 (N_prescaler=2 N_divider=19)
--- x"001F001F" -- R31 (ReadbackReg=0 Regs:unlocked)
--- );
-
--- ( -- Pawel
--- x"80020140", -- R0 (Reset=1 Div=10 OUT0..1 -> PWD)
--- x"00000500", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
--- x"00000501", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
--- x"00000282", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
--- x"00000283", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
--- x"00000504", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
--- x"00000505", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
--- x"00000500", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
--- x"00000501", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
--- x"00000282", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
--- x"00000283", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
--- x"00000504", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
--- x"00000505", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
--- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
--- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
--- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
--- x"55555549", -- R9 (fixed pattern)
--- x"9000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
--- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
--- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
--- x"7B02800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
--- x"0200000E", -- R14 (GPout1=weak pulldown)
--- x"C1550410", -- R16 (fixed pattern)
--- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
--- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
--- x"0020001C", -- R28 (R_divider=2
--- x"0180051D", -- R29 (OSCin=0..63MHz N_CALdivider=40 ?????????????)
--- x"0200051E", -- R30 (N_prescaler=2 N_divider=40)
--- x"001F001F" -- R31 (ReadbackReg=0 Regs:unlocked)
--- );
-
-
--- (
--- x"00020000", -- R0 (Reset=1)
--- x"00020000", -- R0 (Reset=1)
--- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
--- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
--- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
--- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
--- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0)
--- X"000004c2", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
--- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1)
--- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1)
--- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
--- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
--- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
--- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
--- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
--- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
--- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
--- x"55555549", -- R9 (fixed pattern)
--- x"9002400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
------- x"9000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
--- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
--- x"138C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
--- x"3B03826D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown) 130C006C
------- x"7B02800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
--- x"0300000E", -- R14 (GPout1=weak pulldown)
------- x"0200000E", -- R14 (GPout1=weak pulldown)
--- x"C1550410", -- R16 (fixed pattern)
--- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
--- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
--- x"0010001C", -- R28 (R_divider=1 ????????? :2
--- x"0080027D", -- R29 (OSCin=0..63MHz N_CALdivider=19 ?????????????)
--- x"0200027E", -- R30 (N_prescaler=2 N_divider=19)
--- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
--- );
-
-
--- (
--- x"00020000", -- R0 (Reset=1)
--- x"00020000", -- R0 (Reset=1)
--- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
--- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
--- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
--- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
--- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
--- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
--- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1) 00000263
--- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1) 00000263
--- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
--- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
--- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
--- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
--- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
--- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
--- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
--- x"55555549", -- R9 (fixed pattern)
------- x"9002400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
--- x"9000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
--- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
--- x"138C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
------- x"3B03826D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown) 130C006C
--- x"7B02800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
------- x"0300000E", -- R14 (GPout1=weak pulldown)
--- x"0200000E", -- R14 (GPout1=weak pulldown)
--- x"C1550410", -- R16 (fixed pattern)
--- x"77110018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
--- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
--- x"0020001C", -- R28 (R_divider=1 ????????? :2
--- x"0180027D", -- R29 (OSCin=0..63MHz N_CALdivider=19 ?????????????) 0080027D
--- x"0200027E", -- R30 (N_prescaler=2 N_divider=19)
--- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
--- );
-
-
-\r
-\r
-
-
-
-signal tab : RomType;
-signal SHIFT_REG : std_logic_vector(31 downto 0);
-signal PLLbootstate : std_logic_vector(3 downto 0);
-signal bit_cnt : std_logic_vector(6 downto 0);
-signal cnt_dly : std_logic_vector(3 downto 0);
-signal ptr : std_logic_vector(4 downto 0);
-
-signal boot_dly_cnt : std_logic_vector(31 downto 0) := (others => '0');
-signal pll_res : std_logic;
-
-signal pll_boot : std_logic;
-signal pll_clk : std_logic;
-signal pll_data : std_logic;
-signal pll_le : std_logic;
-signal pll_sync : std_logic;
-signal pll_reset_GTX : std_logic;
-signal pll_reset_ADCs : std_logic;
-
-signal reset_counter_V1 : std_logic_vector(15 downto 0);
-signal reset_counter_V2 : std_logic_vector(7 downto 0);
-
---------------------------------------------------------------------
-BEGIN
-
-tab <= TAB80M;-- when ADCCLOCKFREQUENCY=80000000 else TAB62M5;\r
-
---******************************************************************
--- RESET SEQUENCER
---******************************************************************
-
-process(clock)
-begin
- if rising_edge(clock) then
- if PLLbootstate /= x"0" then
- reset_counter_V1 <= (others => '0');
- pll_reset_ADCs <= '1';
- pll_reset_GTX <= '1';
- booting <= '1';
- else
- booting <= '0';
- if reset_counter_V1 < x"ffff" then
- reset_counter_V1 <= reset_counter_V1 + 1;
- else
- pll_reset_ADCs <= '0';
- pll_reset_GTX <= '0';
- end if;
- end if;
- end if;
-end process;
-
-
-process(clock)
-begin
- if rising_edge(clock) then
- if reset_counter_V2 < x"ff" then
- reset_counter_V2 <= reset_counter_V2 + 1;
- pll_res <= '1';
- else
- pll_res <= '0';
- end if;
- end if;
-end process;
-
-
---******************************************************************
--- PLL BOOT STATEMACHINE
---******************************************************************
-
-process(clock, pll_res)
-begin
- if pll_res = '1' then
- PLLbootstate <= (others => '0');
- pll_sync <= '1';
- --GOE <= '0';
- pll_clk <= '0';
- pll_le <= '0';
- ptr <= (others => '0');
-
- elsif rising_edge(clock) then
-
- pll_boot <= BOOT_PLL;
-
- case PLLbootstate is
- when x"0" => --IDLE here until BOOT_DLY goes High
- pll_sync <= '1';
- --GOE <= '0';
- pll_clk <= '0';
- pll_le <= '0';
- ptr <= (others => '0');
- if pll_boot = '1' then PLLbootstate <= x"1";
- end if;
-
---*******Start
- when x"1" => --Set up for TX
- pll_le <= '0';
- pll_clk <= '0';\r
-if ptr=24 then\r
-SHIFT_REG(15 downto 0) <= x"0018";\r
-SHIFT_REG(31 downto 16) <= testwordin;\r
-else
- SHIFT_REG <= tab(conv_integer(ptr));\r
-end if;
- bit_cnt <= (others => '0');
- cnt_dly <= (others => '0');
- PLLbootstate <= x"2";
-
- when x"2" => --CLK low
- pll_clk <= '0';
- if cnt_dly > CLK_DIV then
- cnt_dly <= (others => '0');
- PLLbootstate <= x"3";
- else cnt_dly <= cnt_dly + 1;
- end if;
-
- when x"3" => --CLK high
- pll_clk <= '1';
- if cnt_dly > CLK_DIV then
- cnt_dly <= (others => '0');
- bit_cnt <= bit_cnt + 1;
- PLLbootstate <= x"4";
- else cnt_dly <= cnt_dly + 1;
- end if;
-
- when x"4" => --Loop through all bits and regs
- pll_clk <= '0';
- cnt_dly <= (others => '0');
- SHIFT_REG <= SHIFT_REG(30 downto 0) & '0';
- if bit_cnt > 31 then --32 bits
- pll_le <= '1';
- if conv_integer(ptr) < NROFREGS-1 then --nr of regs
- ptr <= ptr + 1;
- PLLbootstate <= x"5";
- else
-----peter pll_sync <= '0';
- PLLbootstate <= x"6";
- end if;
- else PLLbootstate <= x"2";
- end if;
-
- when x"5" => --Latch Delay
- if cnt_dly > CLK_DIV then
- cnt_dly <= (others => '0');
- PLLbootstate <= x"1";
- else cnt_dly <= cnt_dly + 1;
- end if;
-
- when x"6" => --pll_sync Delay
- if cnt_dly > CLK_DIV then
- cnt_dly <= (others => '0');
- PLLbootstate <= x"7";
- else cnt_dly <= cnt_dly + 1;
- end if;
-
- when x"7" => --SYNC
- if cnt_dly > CLK_DIV then
- cnt_dly <= (others => '0');
- PLLbootstate <= x"8";
- pll_sync <= '0';
- else cnt_dly <= cnt_dly + 1;
- end if;
- pll_le <= '0';
-
- when x"8" => --SYNC
- if cnt_dly > CLK_DIV then
- cnt_dly <= (others => '0');
- PLLbootstate <= x"9";
- else cnt_dly <= cnt_dly + 1;
- end if;
- pll_le <= '0';
-
- when x"9" => --IDLE here until BOOT_PLL goes low
- pll_sync <= '1';
- pll_le <= '0';
- if pll_boot = '0' then PLLbootstate <= x"0";
- end if;
-
- when others => -- make sure other states wont lock up.
- PLLbootstate <= (others => '0');
- end case;
- end if;
-end process;
-
---Shift out bits, MSB first
-pll_data <= SHIFT_REG(31);
-
-
-CLKu <= pll_clk;
-DATAu <= pll_data;
-LEu <= pll_le;
-SYNC <= pll_sync;
-reset_GTX <= pll_reset_GTX;
-reset_ADCs <= pll_reset_ADCs;
-
-
-END Behavioral;
-
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
-\r
- <!-- -->\r
-\r
- <!-- For tool use only. Do not edit. -->\r
-\r
- <!-- -->\r
-\r
- <!-- ProjectNavigator created generated project file. -->\r
-\r
- <!-- For use in tracking generated file and other information -->\r
-\r
- <!-- allowing preservation of process status. -->\r
-\r
- <!-- -->\r
-\r
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
-\r
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
-\r
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FEE_ADC32board.xise"/>\r
-\r
- <files xmlns="http://www.xilinx.com/XMLSchema"/>\r
-\r
- <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
- <transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- </transforms>\r
-\r
-</generated_project>\r
+++ /dev/null
-NET "AD11A_N" DIFF_TERM = "TRUE";\r
-NET "AD11A_N" IOSTANDARD = LVDS_25;\r
-NET "AD11A_N" LOC = C17;\r
-NET "AD11A_P" DIFF_TERM = "TRUE";\r
-NET "AD11A_P" IOSTANDARD = LVDS_25;\r
-NET "AD11A_P" LOC = C16;\r
-NET "AD11B_N" DIFF_TERM = "TRUE";\r
-NET "AD11B_N" IOSTANDARD = LVDS_25;\r
-NET "AD11B_N" LOC = A18;\r
-NET "AD11B_P" DIFF_TERM = "TRUE";\r
-NET "AD11B_P" IOSTANDARD = LVDS_25;\r
-NET "AD11B_P" LOC = A17;\r
-NET "AD12A_N" DIFF_TERM = "TRUE";\r
-NET "AD12A_N" IOSTANDARD = LVDS_25;\r
-NET "AD12A_N" LOC = D18;\r
-NET "AD12A_P" DIFF_TERM = "TRUE";\r
-NET "AD12A_P" IOSTANDARD = LVDS_25;\r
-NET "AD12A_P" LOC = D17;\r
-NET "AD12B_N" DIFF_TERM = "TRUE";\r
-NET "AD12B_N" IOSTANDARD = LVDS_25;\r
-NET "AD12B_N" LOC = C18;\r
-NET "AD12B_P" DIFF_TERM = "TRUE";\r
-NET "AD12B_P" IOSTANDARD = LVDS_25;\r
-NET "AD12B_P" LOC = B18;\r
-NET "AD13A_N" DIFF_TERM = "TRUE";\r
-NET "AD13A_N" IOSTANDARD = LVDS_25;\r
-NET "AD13A_N" LOC = F17;\r
-NET "AD13A_P" DIFF_TERM = "TRUE";\r
-NET "AD13A_P" IOSTANDARD = LVDS_25;\r
-NET "AD13A_P" LOC = E17;\r
-NET "AD13B_N" DIFF_TERM = "TRUE";\r
-NET "AD13B_N" IOSTANDARD = LVDS_25;\r
-NET "AD13B_N" LOC = H15;\r
-NET "AD13B_P" DIFF_TERM = "TRUE";\r
-NET "AD13B_P" IOSTANDARD = LVDS_25;\r
-NET "AD13B_P" LOC = G15;\r
-NET "AD14A_N" DIFF_TERM = "TRUE";\r
-NET "AD14A_N" IOSTANDARD = LVDS_25;\r
-NET "AD14A_N" LOC = H16;\r
-NET "AD14A_P" DIFF_TERM = "TRUE";\r
-NET "AD14A_P" IOSTANDARD = LVDS_25;\r
-NET "AD14A_P" LOC = G16;\r
-NET "AD14B_N" DIFF_TERM = "TRUE";\r
-NET "AD14B_N" IOSTANDARD = LVDS_25;\r
-NET "AD14B_N" LOC = B16;\r
-NET "AD14B_P" DIFF_TERM = "TRUE";\r
-NET "AD14B_P" IOSTANDARD = LVDS_25;\r
-NET "AD14B_P" LOC = A16;\r
-NET "AD15A_N" DIFF_TERM = "TRUE";\r
-NET "AD15A_N" IOSTANDARD = LVDS_25;\r
-NET "AD15A_N" LOC = F14;\r
-NET "AD15A_P" DIFF_TERM = "TRUE";\r
-NET "AD15A_P" IOSTANDARD = LVDS_25;\r
-NET "AD15A_P" LOC = G14;\r
-NET "AD15B_N" DIFF_TERM = "TRUE";\r
-NET "AD15B_N" IOSTANDARD = LVDS_25;\r
-NET "AD15B_N" LOC = B14;\r
-NET "AD15B_P" DIFF_TERM = "TRUE";\r
-NET "AD15B_P" IOSTANDARD = LVDS_25;\r
-NET "AD15B_P" LOC = A14;\r
-NET "AD16A_N" DIFF_TERM = "TRUE";\r
-NET "AD16A_N" IOSTANDARD = LVDS_25;\r
-NET "AD16A_N" LOC = E14;\r
-NET "AD16A_P" DIFF_TERM = "TRUE";\r
-NET "AD16A_P" IOSTANDARD = LVDS_25;\r
-NET "AD16A_P" LOC = D14;\r
-NET "AD16B_N" DIFF_TERM = "TRUE";\r
-NET "AD16B_N" IOSTANDARD = LVDS_25;\r
-NET "AD16B_N" LOC = G13;\r
-NET "AD16B_P" DIFF_TERM = "TRUE";\r
-NET "AD16B_P" IOSTANDARD = LVDS_25;\r
-NET "AD16B_P" LOC = F13;\r
-NET "AD17A_N" DIFF_TERM = "TRUE";\r
-NET "AD17A_N" IOSTANDARD = LVDS_25;\r
-NET "AD17A_N" LOC = D13;\r
-NET "AD17A_P" DIFF_TERM = "TRUE";\r
-NET "AD17A_P" IOSTANDARD = LVDS_25;\r
-NET "AD17A_P" LOC = C13;\r
-NET "AD17B_N" DIFF_TERM = "TRUE";\r
-NET "AD17B_N" IOSTANDARD = LVDS_25;\r
-NET "AD17B_N" LOC = E12;\r
-NET "AD17B_P" DIFF_TERM = "TRUE";\r
-NET "AD17B_P" IOSTANDARD = LVDS_25;\r
-NET "AD17B_P" LOC = F12;\r
-NET "AD18A_N" DIFF_TERM = "TRUE";\r
-NET "AD18A_N" IOSTANDARD = LVDS_25;\r
-NET "AD18A_N" LOC = B13;\r
-NET "AD18A_P" DIFF_TERM = "TRUE";\r
-NET "AD18A_P" IOSTANDARD = LVDS_25;\r
-NET "AD18A_P" LOC = A13;\r
-NET "AD18B_N" DIFF_TERM = "TRUE";\r
-NET "AD18B_N" IOSTANDARD = LVDS_25;\r
-NET "AD18B_N" LOC = H13;\r
-NET "AD18B_P" DIFF_TERM = "TRUE";\r
-NET "AD18B_P" IOSTANDARD = LVDS_25;\r
-NET "AD18B_P" LOC = H12;\r
-\r
-NET "AD21A_N" DIFF_TERM = "TRUE";\r
-NET "AD21A_N" IOSTANDARD = LVDS_25;\r
-NET "AD21A_N" LOC = H22;\r
-NET "AD21A_P" DIFF_TERM = "TRUE";\r
-NET "AD21A_P" IOSTANDARD = LVDS_25;\r
-NET "AD21A_P" LOC = J22;\r
-NET "AD21B_N" DIFF_TERM = "TRUE";\r
-NET "AD21B_N" IOSTANDARD = LVDS_25;\r
-NET "AD21B_N" LOC = K22;\r
-NET "AD21B_P" DIFF_TERM = "TRUE";\r
-NET "AD21B_P" IOSTANDARD = LVDS_25;\r
-NET "AD21B_P" LOC = K21;\r
-NET "AD22A_N" DIFF_TERM = "TRUE";\r
-NET "AD22A_N" IOSTANDARD = LVDS_25;\r
-NET "AD22A_N" LOC = L17;\r
-NET "AD22A_P" DIFF_TERM = "TRUE";\r
-NET "AD22A_P" IOSTANDARD = LVDS_25;\r
-NET "AD22A_P" LOC = K17;\r
-NET "AD22B_N" DIFF_TERM = "TRUE";\r
-NET "AD22B_N" IOSTANDARD = LVDS_25;\r
-NET "AD22B_N" LOC = L19;\r
-NET "AD22B_P" DIFF_TERM = "TRUE";\r
-NET "AD22B_P" IOSTANDARD = LVDS_25;\r
-NET "AD22B_P" LOC = L18;\r
-NET "AD23A_N" DIFF_TERM = "TRUE";\r
-NET "AD23A_N" IOSTANDARD = LVDS_25;\r
-NET "AD23A_N" LOC = K20;\r
-NET "AD23A_P" DIFF_TERM = "TRUE";\r
-NET "AD23A_P" IOSTANDARD = LVDS_25;\r
-NET "AD23A_P" LOC = J20;\r
-NET "AD23B_N" DIFF_TERM = "TRUE";\r
-NET "AD23B_N" IOSTANDARD = LVDS_25;\r
-NET "AD23B_N" LOC = J17;\r
-NET "AD23B_P" DIFF_TERM = "TRUE";\r
-NET "AD23B_P" IOSTANDARD = LVDS_25;\r
-NET "AD23B_P" LOC = J18;\r
-NET "AD24A_N" DIFF_TERM = "TRUE";\r
-NET "AD24A_N" IOSTANDARD = LVDS_25;\r
-NET "AD24A_N" LOC = J19;\r
-NET "AD24A_P" DIFF_TERM = "TRUE";\r
-NET "AD24A_P" IOSTANDARD = LVDS_25;\r
-NET "AD24A_P" LOC = K19;\r
-NET "AD24B_N" DIFF_TERM = "TRUE";\r
-NET "AD24B_N" IOSTANDARD = LVDS_25;\r
-NET "AD24B_N" LOC = H21;\r
-NET "AD24B_P" DIFF_TERM = "TRUE";\r
-NET "AD24B_P" IOSTANDARD = LVDS_25;\r
-NET "AD24B_P" LOC = G21;\r
-NET "AD25A_N" DIFF_TERM = "TRUE";\r
-NET "AD25A_N" IOSTANDARD = LVDS_25;\r
-NET "AD25A_N" LOC = H18;\r
-NET "AD25A_P" DIFF_TERM = "TRUE";\r
-NET "AD25A_P" IOSTANDARD = LVDS_25;\r
-NET "AD25A_P" LOC = H17;\r
-NET "AD25B_N" DIFF_TERM = "TRUE";\r
-NET "AD25B_N" IOSTANDARD = LVDS_25;\r
-NET "AD25B_N" LOC = F19;\r
-NET "AD25B_P" DIFF_TERM = "TRUE";\r
-NET "AD25B_P" IOSTANDARD = LVDS_25;\r
-NET "AD25B_P" LOC = G19;\r
-NET "AD26A_N" DIFF_TERM = "TRUE";\r
-NET "AD26A_N" IOSTANDARD = LVDS_25;\r
-NET "AD26A_N" LOC = E22;\r
-NET "AD26A_P" DIFF_TERM = "TRUE";\r
-NET "AD26A_P" IOSTANDARD = LVDS_25;\r
-NET "AD26A_P" LOC = E21;\r
-NET "AD26B_N" DIFF_TERM = "TRUE";\r
-NET "AD26B_N" IOSTANDARD = LVDS_25;\r
-NET "AD26B_N" LOC = D19;\r
-NET "AD26B_P" DIFF_TERM = "TRUE";\r
-NET "AD26B_P" IOSTANDARD = LVDS_25;\r
-NET "AD26B_P" LOC = E19;\r
-NET "AD27A_N" DIFF_TERM = "TRUE";\r
-NET "AD27A_N" IOSTANDARD = LVDS_25;\r
-NET "AD27A_N" LOC = C20;\r
-NET "AD27A_P" DIFF_TERM = "TRUE";\r
-NET "AD27A_P" IOSTANDARD = LVDS_25;\r
-NET "AD27A_P" LOC = B20;\r
-NET "AD27B_N" DIFF_TERM = "TRUE";\r
-NET "AD27B_N" IOSTANDARD = LVDS_25;\r
-NET "AD27B_N" LOC = B21;\r
-NET "AD27B_P" DIFF_TERM = "TRUE";\r
-NET "AD27B_P" IOSTANDARD = LVDS_25;\r
-NET "AD27B_P" LOC = A21;\r
-NET "AD28A_N" DIFF_TERM = "TRUE";\r
-NET "AD28A_N" IOSTANDARD = LVDS_25;\r
-NET "AD28A_N" LOC = F18;\r
-NET "AD28A_P" DIFF_TERM = "TRUE";\r
-NET "AD28A_P" IOSTANDARD = LVDS_25;\r
-NET "AD28A_P" LOC = G18;\r
-NET "AD28B_N" DIFF_TERM = "TRUE";\r
-NET "AD28B_N" IOSTANDARD = LVDS_25;\r
-NET "AD28B_N" LOC = C21;\r
-NET "AD28B_P" DIFF_TERM = "TRUE";\r
-NET "AD28B_P" IOSTANDARD = LVDS_25;\r
-NET "AD28B_P" LOC = B22;\r
-\r
-NET "AD31A_N" DIFF_TERM = "TRUE";\r
-NET "AD31A_N" IOSTANDARD = LVDS_25;\r
-NET "AD31A_N" LOC = T21;\r
-NET "AD31A_P" DIFF_TERM = "TRUE";\r
-NET "AD31A_P" IOSTANDARD = LVDS_25;\r
-NET "AD31A_P" LOC = U21;\r
-NET "AD31B_N" DIFF_TERM = "TRUE";\r
-NET "AD31B_N" IOSTANDARD = LVDS_25;\r
-NET "AD31B_N" LOC = Y21;\r
-NET "AD31B_P" DIFF_TERM = "TRUE";\r
-NET "AD31B_P" IOSTANDARD = LVDS_25;\r
-NET "AD31B_P" LOC = AA21;\r
-NET "AD32A_N" DIFF_TERM = "TRUE";\r
-NET "AD32A_N" IOSTANDARD = LVDS_25;\r
-NET "AD32A_N" LOC = AB21;\r
-NET "AD32A_P" DIFF_TERM = "TRUE";\r
-NET "AD32A_P" IOSTANDARD = LVDS_25;\r
-NET "AD32A_P" LOC = AB20;\r
-NET "AD32B_N" DIFF_TERM = "TRUE";\r
-NET "AD32B_N" IOSTANDARD = LVDS_25;\r
-NET "AD32B_N" LOC = U20;\r
-NET "AD32B_P" DIFF_TERM = "TRUE";\r
-NET "AD32B_P" IOSTANDARD = LVDS_25;\r
-NET "AD32B_P" LOC = U19;\r
-NET "AD33A_N" DIFF_TERM = "TRUE";\r
-NET "AD33A_N" IOSTANDARD = LVDS_25;\r
-NET "AD33A_N" LOC = W20;\r
-NET "AD33A_P" DIFF_TERM = "TRUE";\r
-NET "AD33A_P" IOSTANDARD = LVDS_25;\r
-NET "AD33A_P" LOC = Y20;\r
-NET "AD33B_N" DIFF_TERM = "TRUE";\r
-NET "AD33B_N" IOSTANDARD = LVDS_25;\r
-NET "AD33B_N" LOC = V21;\r
-NET "AD33B_P" DIFF_TERM = "TRUE";\r
-NET "AD33B_P" IOSTANDARD = LVDS_25;\r
-NET "AD33B_P" LOC = V20;\r
-NET "AD34A_N" DIFF_TERM = "TRUE";\r
-NET "AD34A_N" IOSTANDARD = LVDS_25;\r
-NET "AD34A_N" LOC = AA22;\r
-NET "AD34A_P" DIFF_TERM = "TRUE";\r
-NET "AD34A_P" IOSTANDARD = LVDS_25;\r
-NET "AD34A_P" LOC = Y22;\r
-NET "AD34B_N" DIFF_TERM = "TRUE";\r
-NET "AD34B_N" IOSTANDARD = LVDS_25;\r
-NET "AD34B_N" LOC = T19;\r
-NET "AD34B_P" DIFF_TERM = "TRUE";\r
-NET "AD34B_P" IOSTANDARD = LVDS_25;\r
-NET "AD34B_P" LOC = T18;\r
-NET "AD35A_N" DIFF_TERM = "TRUE";\r
-NET "AD35A_N" IOSTANDARD = LVDS_25;\r
-NET "AD35A_N" LOC = R20;\r
-NET "AD35A_P" DIFF_TERM = "TRUE";\r
-NET "AD35A_P" IOSTANDARD = LVDS_25;\r
-NET "AD35A_P" LOC = R19;\r
-NET "AD35B_N" DIFF_TERM = "TRUE";\r
-NET "AD35B_N" IOSTANDARD = LVDS_25;\r
-NET "AD35B_N" LOC = P17;\r
-NET "AD35B_P" DIFF_TERM = "TRUE";\r
-NET "AD35B_P" IOSTANDARD = LVDS_25;\r
-NET "AD35B_P" LOC = N17;\r
-NET "AD36A_N" DIFF_TERM = "TRUE";\r
-NET "AD36A_N" IOSTANDARD = LVDS_25;\r
-NET "AD36A_N" LOC = R22;\r
-NET "AD36A_P" DIFF_TERM = "TRUE";\r
-NET "AD36A_P" IOSTANDARD = LVDS_25;\r
-NET "AD36A_P" LOC = P22;\r
-NET "AD36B_N" DIFF_TERM = "TRUE";\r
-NET "AD36B_N" IOSTANDARD = LVDS_25;\r
-NET "AD36B_N" LOC = N21;\r
-NET "AD36B_P" DIFF_TERM = "TRUE";\r
-NET "AD36B_P" IOSTANDARD = LVDS_25;\r
-NET "AD36B_P" LOC = N22;\r
-NET "AD37A_N" DIFF_TERM = "TRUE";\r
-NET "AD37A_N" IOSTANDARD = LVDS_25;\r
-NET "AD37A_N" LOC = M19;\r
-NET "AD37A_P" DIFF_TERM = "TRUE";\r
-NET "AD37A_P" IOSTANDARD = LVDS_25;\r
-NET "AD37A_P" LOC = M20;\r
-NET "AD37B_N" DIFF_TERM = "TRUE";\r
-NET "AD37B_N" IOSTANDARD = LVDS_25;\r
-NET "AD37B_N" LOC = L21;\r
-NET "AD37B_P" DIFF_TERM = "TRUE";\r
-NET "AD37B_P" IOSTANDARD = LVDS_25;\r
-NET "AD37B_P" LOC = L22;\r
-NET "AD38A_N" DIFF_TERM = "TRUE";\r
-NET "AD38A_N" IOSTANDARD = LVDS_25;\r
-NET "AD38A_N" LOC = N18;\r
-NET "AD38A_P" DIFF_TERM = "TRUE";\r
-NET "AD38A_P" IOSTANDARD = LVDS_25;\r
-NET "AD38A_P" LOC = M18;\r
-NET "AD38B_N" DIFF_TERM = "TRUE";\r
-NET "AD38B_N" IOSTANDARD = LVDS_25;\r
-NET "AD38B_N" LOC = N20;\r
-NET "AD38B_P" DIFF_TERM = "TRUE";\r
-NET "AD38B_P" IOSTANDARD = LVDS_25;\r
-NET "AD38B_P" LOC = M21;\r
-\r
-NET "AD41A_N" DIFF_TERM = "TRUE";\r
-NET "AD41A_N" IOSTANDARD = LVDS_25;\r
-NET "AD41A_N" LOC = U8;\r
-NET "AD41A_P" DIFF_TERM = "TRUE";\r
-NET "AD41A_P" IOSTANDARD = LVDS_25;\r
-NET "AD41A_P" LOC = V8;\r
-NET "AD41B_N" DIFF_TERM = "TRUE";\r
-NET "AD41B_N" IOSTANDARD = LVDS_25;\r
-NET "AD41B_N" LOC = Y7;\r
-NET "AD41B_P" DIFF_TERM = "TRUE";\r
-NET "AD41B_P" IOSTANDARD = LVDS_25;\r
-NET "AD41B_P" LOC = Y6;\r
-NET "AD42A_N" DIFF_TERM = "TRUE";\r
-NET "AD42A_N" IOSTANDARD = LVDS_25;\r
-NET "AD42A_N" LOC = T7;\r
-NET "AD42A_P" DIFF_TERM = "TRUE";\r
-NET "AD42A_P" IOSTANDARD = LVDS_25;\r
-NET "AD42A_P" LOC = T6;\r
-NET "AD42B_N" DIFF_TERM = "TRUE";\r
-NET "AD42B_N" IOSTANDARD = LVDS_25;\r
-NET "AD42B_N" LOC = AA6;\r
-NET "AD42B_P" DIFF_TERM = "TRUE";\r
-NET "AD42B_P" IOSTANDARD = LVDS_25;\r
-NET "AD42B_P" LOC = AB6;\r
-NET "AD43A_N" DIFF_TERM = "TRUE";\r
-NET "AD43A_N" IOSTANDARD = LVDS_25;\r
-NET "AD43A_N" LOC = W7;\r
-NET "AD43A_P" DIFF_TERM = "TRUE";\r
-NET "AD43A_P" IOSTANDARD = LVDS_25;\r
-NET "AD43A_P" LOC = V7;\r
-NET "AD43B_N" DIFF_TERM = "TRUE";\r
-NET "AD43B_N" IOSTANDARD = LVDS_25;\r
-NET "AD43B_N" LOC = AB8;\r
-NET "AD43B_P" DIFF_TERM = "TRUE";\r
-NET "AD43B_P" IOSTANDARD = LVDS_25;\r
-NET "AD43B_P" LOC = AB9;\r
-NET "AD44A_N" DIFF_TERM = "TRUE";\r
-NET "AD44A_N" IOSTANDARD = LVDS_25;\r
-NET "AD44A_N" LOC = V6;\r
-NET "AD44A_P" DIFF_TERM = "TRUE";\r
-NET "AD44A_P" IOSTANDARD = LVDS_25;\r
-NET "AD44A_P" LOC = U6;\r
-NET "AD44B_N" DIFF_TERM = "TRUE";\r
-NET "AD44B_N" IOSTANDARD = LVDS_25;\r
-NET "AD44B_N" LOC = W8;\r
-NET "AD44B_P" DIFF_TERM = "TRUE";\r
-NET "AD44B_P" IOSTANDARD = LVDS_25;\r
-NET "AD44B_P" LOC = W9;\r
-NET "AD45A_N" DIFF_TERM = "TRUE";\r
-NET "AD45A_N" IOSTANDARD = LVDS_25;\r
-NET "AD45A_N" LOC = T8;\r
-NET "AD45A_P" DIFF_TERM = "TRUE";\r
-NET "AD45A_P" IOSTANDARD = LVDS_25;\r
-NET "AD45A_P" LOC = R9;\r
-NET "AD45B_N" DIFF_TERM = "TRUE";\r
-NET "AD45B_N" IOSTANDARD = LVDS_25;\r
-NET "AD45B_N" LOC = Y11;\r
-NET "AD45B_P" DIFF_TERM = "TRUE";\r
-NET "AD45B_P" IOSTANDARD = LVDS_25;\r
-NET "AD45B_P" LOC = AA11;\r
-NET "AD46A_N" DIFF_TERM = "TRUE";\r
-NET "AD46A_N" IOSTANDARD = LVDS_25;\r
-NET "AD46A_N" LOC = Y10;\r
-NET "AD46A_P" DIFF_TERM = "TRUE";\r
-NET "AD46A_P" IOSTANDARD = LVDS_25;\r
-NET "AD46A_P" LOC = W10;\r
-NET "AD46B_N" DIFF_TERM = "TRUE";\r
-NET "AD46B_N" IOSTANDARD = LVDS_25;\r
-NET "AD46B_N" LOC = V11;\r
-NET "AD46B_P" DIFF_TERM = "TRUE";\r
-NET "AD46B_P" IOSTANDARD = LVDS_25;\r
-NET "AD46B_P" LOC = U11;\r
-NET "AD47A_N" DIFF_TERM = "TRUE";\r
-NET "AD47A_N" IOSTANDARD = LVDS_25;\r
-NET "AD47A_N" LOC = T11;\r
-NET "AD47A_P" DIFF_TERM = "TRUE";\r
-NET "AD47A_P" IOSTANDARD = LVDS_25;\r
-NET "AD47A_P" LOC = T12;\r
-NET "AD47B_N" DIFF_TERM = "TRUE";\r
-NET "AD47B_N" IOSTANDARD = LVDS_25;\r
-NET "AD47B_N" LOC = W12;\r
-NET "AD47B_P" DIFF_TERM = "TRUE";\r
-NET "AD47B_P" IOSTANDARD = LVDS_25;\r
-NET "AD47B_P" LOC = V12;\r
-NET "AD48A_N" DIFF_TERM = "TRUE";\r
-NET "AD48A_N" IOSTANDARD = LVDS_25;\r
-NET "AD48A_N" LOC = U10;\r
-NET "AD48A_P" DIFF_TERM = "TRUE";\r
-NET "AD48A_P" IOSTANDARD = LVDS_25;\r
-NET "AD48A_P" LOC = T9;\r
-NET "AD48B_N" DIFF_TERM = "TRUE";\r
-NET "AD48B_N" IOSTANDARD = LVDS_25;\r
-NET "AD48B_N" LOC = AA12;\r
-NET "AD48B_P" DIFF_TERM = "TRUE";\r
-NET "AD48B_P" IOSTANDARD = LVDS_25;\r
-NET "AD48B_P" LOC = Y12;\r
-\r
-NET "DATAu" LOC = B10;
-NET "CLKu" LOC = A11;
-NET "RDu" LOC = C10;
-NET "LEu" LOC = A12;
-NET "SYNC" LOC = G11;
-
-NET "S_CTRL" LOC = W14;
-NET "T_CTRL" LOC = Y14;
-NET "GEO" LOC = AB13;\r
-\r
-#\r
-NET "SCK" LOC = W17;\r
-NET "SDI" LOC = W18;\r
-NET "CSA[1]" LOC = AA17;\r
-NET "CSA[2]" LOC = AB18;\r
-NET "CSA[3]" LOC = V18;\r
-NET "CSA[4]" LOC = T16;\r
-NET "CSB[1]" LOC = Y17;\r
-NET "CSB[2]" LOC = AA18;\r
-NET "CSB[3]" LOC = V17;\r
-NET "CSB[4]" LOC = R16;\r
-\r
-NET "SDOA[1]" LOC = Y16;\r
-NET "SDOA[2]" LOC = AA19;\r
-NET "SDOA[3]" LOC = V13;\r
-NET "SDOA[4]" LOC = T17;\r
-NET "SDOB[1]" LOC = AA16;\r
-NET "SDOB[2]" LOC = AB19;\r
-NET "SDOB[3]" LOC = W13;\r
-NET "SDOB[4]" LOC = U18;\r
-\r
-#\r
-#NET "D<0>" LOC = "V15";\r
-#NET "D<1>" LOC = "U15";\r
-#NET "D<2>" LOC = "R15";\r
-#NET "D<3>" LOC = "R14";\r
-#NET "D<4>" LOC = "Y19";\r
-#NET "D<5>" LOC = "W19";\r
-#NET "D<6>" LOC = "U16";\r
-#NET "D<7>" LOC = "V16";\r
-NET "DCOA1_N" DIFF_TERM = "TRUE";\r
-NET "DCOA1_N" IOSTANDARD = LVDS_25;\r
-NET "DCOA1_N" LOC = F16;\r
-NET "DCOA1_P" DIFF_TERM = "TRUE";\r
-NET "DCOA1_P" IOSTANDARD = LVDS_25;\r
-NET "DCOA1_P" LOC = E16;\r
-NET "DCOA2_N" DIFF_TERM = "TRUE";\r
-NET "DCOA2_N" IOSTANDARD = LVDS_25;\r
-NET "DCOA2_N" LOC = D22;\r
-NET "DCOA2_P" DIFF_TERM = "TRUE";\r
-NET "DCOA2_P" IOSTANDARD = LVDS_25;\r
-NET "DCOA2_P" LOC = C22;\r
-NET "DCOA3_N" DIFF_TERM = "TRUE";\r
-NET "DCOA3_N" IOSTANDARD = LVDS_25;\r
-NET "DCOA3_N" LOC = P20;\r
-NET "DCOA3_P" DIFF_TERM = "TRUE";\r
-NET "DCOA3_P" IOSTANDARD = LVDS_25;\r
-NET "DCOA3_P" LOC = P19;\r
-NET "DCOA4_N" DIFF_TERM = "TRUE";\r
-NET "DCOA4_N" IOSTANDARD = LVDS_25;\r
-NET "DCOA4_N" LOC = Y9;\r
-NET "DCOA4_P" DIFF_TERM = "TRUE";\r
-NET "DCOA4_P" IOSTANDARD = LVDS_25;\r
-NET "DCOA4_P" LOC = AA9;\r
-NET "DCOB1_N" DIFF_TERM = "TRUE";\r
-NET "DCOB1_N" IOSTANDARD = LVDS_25;\r
-NET "DCOB1_N" LOC = B19;\r
-NET "DCOB1_P" DIFF_TERM = "TRUE";\r
-NET "DCOB1_P" IOSTANDARD = LVDS_25;\r
-NET "DCOB1_P" LOC = A19;\r
-NET "DCOB2_N" DIFF_TERM = "TRUE";\r
-NET "DCOB2_N" IOSTANDARD = LVDS_25;\r
-NET "DCOB2_N" LOC = E20;\r
-NET "DCOB2_P" DIFF_TERM = "TRUE";\r
-NET "DCOB2_P" IOSTANDARD = LVDS_25;\r
-NET "DCOB2_P" LOC = D20;\r
-NET "DCOB3_N" DIFF_TERM = "TRUE";\r
-NET "DCOB3_N" IOSTANDARD = LVDS_25;\r
-NET "DCOB3_N" LOC = V22;\r
-NET "DCOB3_P" DIFF_TERM = "TRUE";\r
-NET "DCOB3_P" IOSTANDARD = LVDS_25;\r
-NET "DCOB3_P" LOC = W22;\r
-NET "DCOB4_N" DIFF_TERM = "TRUE";\r
-NET "DCOB4_N" IOSTANDARD = LVDS_25;\r
-NET "DCOB4_N" LOC = AA8;\r
-NET "DCOB4_P" DIFF_TERM = "TRUE";\r
-NET "DCOB4_P" IOSTANDARD = LVDS_25;\r
-NET "DCOB4_P" LOC = AA7;\r
-\r
-NET "FRA1_N" DIFF_TERM = "TRUE";\r
-NET "FRA1_N" IOSTANDARD = LVDS_25;\r
-NET "FRA1_N" LOC = C15;\r
-NET "FRA1_P" DIFF_TERM = "TRUE";\r
-NET "FRA1_P" IOSTANDARD = LVDS_25;\r
-NET "FRA1_P" LOC = B15;\r
-NET "FRA2_N" DIFF_TERM = "TRUE";\r
-NET "FRA2_N" IOSTANDARD = LVDS_25;\r
-NET "FRA2_N" LOC = G20;\r
-NET "FRA2_P" DIFF_TERM = "TRUE";\r
-NET "FRA2_P" IOSTANDARD = LVDS_25;\r
-NET "FRA2_P" LOC = H20;\r
-NET "FRA3_N" DIFF_TERM = "TRUE";\r
-NET "FRA3_N" IOSTANDARD = LVDS_25;\r
-NET "FRA3_N" LOC = R17;\r
-NET "FRA3_P" DIFF_TERM = "TRUE";\r
-NET "FRA3_P" IOSTANDARD = LVDS_25;\r
-NET "FRA3_P" LOC = P18;\r
-NET "FRA4_N" DIFF_TERM = "TRUE";\r
-NET "FRA4_N" IOSTANDARD = LVDS_25;\r
-NET "FRA4_N" LOC = U9;\r
-NET "FRA4_P" DIFF_TERM = "TRUE";\r
-NET "FRA4_P" IOSTANDARD = LVDS_25;\r
-NET "FRA4_P" LOC = V10;\r
-NET "FRB1_N" DIFF_TERM = "TRUE";\r
-NET "FRB1_N" IOSTANDARD = LVDS_25;\r
-NET "FRB1_N" LOC = E15;\r
-NET "FRB1_P" DIFF_TERM = "TRUE";\r
-NET "FRB1_P" IOSTANDARD = LVDS_25;\r
-NET "FRB1_P" LOC = D15;\r
-NET "FRB2_N" DIFF_TERM = "TRUE";\r
-NET "FRB2_N" IOSTANDARD = LVDS_25;\r
-NET "FRB2_N" LOC = F22;\r
-NET "FRB2_P" DIFF_TERM = "TRUE";\r
-NET "FRB2_P" IOSTANDARD = LVDS_25;\r
-NET "FRB2_P" LOC = F21;\r
-NET "FRB3_N" DIFF_TERM = "TRUE";\r
-NET "FRB3_N" IOSTANDARD = LVDS_25;\r
-NET "FRB3_N" LOC = T22;\r
-NET "FRB3_P" DIFF_TERM = "TRUE";\r
-NET "FRB3_P" IOSTANDARD = LVDS_25;\r
-NET "FRB3_P" LOC = R21;\r
-NET "FRB4_N" DIFF_TERM = "TRUE";\r
-NET "FRB4_N" IOSTANDARD = LVDS_25;\r
-NET "FRB4_N" LOC = AB10;\r
-NET "FRB4_P" DIFF_TERM = "TRUE";\r
-NET "FRB4_P" IOSTANDARD = LVDS_25;\r
-NET "FRB4_P" LOC = AB11;\r
-\r
-NET "GCLK_N" DIFF_TERM = "TRUE";\r
-NET "GCLK_N" IOSTANDARD = LVDS_25;\r
-NET "GCLK_N" LOC = U13;\r
-NET "GCLK_P" DIFF_TERM = "TRUE";\r
-NET "GCLK_P" IOSTANDARD = LVDS_25;\r
-NET "GCLK_P" LOC = T13;\r
-\r
-\r
-NET "INTCOM0_N" LOC = "A6";\r
-NET "INTCOM0_P" LOC = "A7";\r
-NET "INTCOM1_N" LOC = "B6";\r
-NET "INTCOM1_P" LOC = "C6";\r
-NET "INTCOM2_N" LOC = "H10";\r
-NET "INTCOM2_P" LOC = "G10";\r
-NET "INTCOM3_N" LOC = "D9";\r
-NET "INTCOM3_P" LOC = "E9";\r
-NET "INTCOM4_N" LOC = "G9";\r
-NET "INTCOM4_P" LOC = "F9";\r
-NET "INTCOM5_N" LOC = "E6";\r
-NET "INTCOM5_P" LOC = "E7";\r
-NET "INTCOM6_N" LOC = "F11";\r
-NET "INTCOM6_P" LOC = "E11";\r
-NET "INTCOM7_N" LOC = "F7";\r
-NET "INTCOM7_P" LOC = "F8";\r
-\r
-NET "INTCOMC1_N" LOC = "C7";\r
-#NET "INTCOMC1_N" DIFF_TERM = "TRUE";\r
-#NET "INTCOMC1_N" IOSTANDARD = BLVDS_25;\r
-NET "INTCOMC1_P" LOC = "C8";\r
-#NET "INTCOMC1_P" DIFF_TERM = "TRUE";\r
-#NET "INTCOMC1_P" IOSTANDARD = BLVDS_25;\r
-NET "INTCOMC2_N" LOC = "D7";\r
-#NET "INTCOMC2_N" DIFF_TERM = "TRUE";\r
-#NET "INTCOMC2_N" IOSTANDARD = BLVDS_25;\r
-NET "INTCOMC2_P" LOC = "D8";\r
-#NET "INTCOMC2_P" DIFF_TERM = "TRUE";\r
-#NET "INTCOMC2_P" IOSTANDARD = BLVDS_25;\r
-\r
-\r
-NET "TCK_F" LOC = "AA14";\r
-NET "TDI_F" LOC = "AB16";\r
-NET "TDO_F" LOC = "AB15";\r
-NET "TMS_F" LOC = "AB14";\r
-\r
-\r
-\r
-#\r
-#NET "SM0_N" LOC = "B11";\r
-#NET "SM0_P" LOC = "C11";\r
-NET "SM1_N" LOC = "B9";\r
-NET "SM1_P" LOC = "A9";\r
-#NET "SM2_N" LOC = "E10";\r
-#NET "SM2_P" LOC = "D10";\r
-NET "SM3_N" LOC = "B8";\r
-NET "SM3_P" LOC = "A8";\r
-#\r
-#\r
-#NET "TEMP_IN" LOC = "U14";\r
-#NET "TEMP_OUT" LOC = "T14";\r
-#\r
-#NET "RX_N" LOC = "T2";\r
-#NET "RX_P" LOC = "T1";\r
-#NET "TX_N" LOC = "V2";\r
-#NET "TX_P" LOC = "V1";\r
-NET "MOD_DEF[0]" LOC = G8;\r
-NET "MOD_DEF[1]" LOC = H8;\r
-NET "MOD_DEF[2]" LOC = D12;\r
-NET "TX_DIS" LOC = H11;\r
-NET "LOS" LOC = C12;\r
-\r
-NET "MGTREFCLK_N" LOC = L3;\r
-NET "MGTREFCLK_P" LOC = L4;\r
-NET "RCV_CLK_N" LOC = Y15;\r
-NET "RCV_CLK_P" LOC = W15;\r
-NET "ST_CLK_N" LOC = G6;\r
-NET "ST_CLK_P" LOC = F6;\r
-NET "RX_N" LOC = G4;\r
-NET "RX_P" LOC = G3;\r
-NET "TX_N" LOC = K2;\r
-NET "TX_P" LOC = K1;\r
-\r
-#NET "PROGRAM_B" LOC = F5;\r
-\r
-#\r
-#NET "XRX0_N" LOC = "E4";\r
-#NET "XRX0_P" LOC = "E3";\r
-#NET "XRX1_N" LOC = "C4";\r
-#NET "XRX1_P" LOC = "C3";\r
-#NET "XTX0_N" LOC = "H2";\r
-#NET "XTX0_P" LOC = "H1";\r
-#NET "XTX1_N" LOC = "F2";\r
-#NET "XTX1_P" LOC = "F1";\r
-#Created by Constraints Editor (xc6vlx130t-ff484-3) - 2012/07/23\r
-#NET "DCOA1_P" TNM_NET = DCOA1_P;\r
-#TIMESPEC TS_DCOA1_P = PERIOD "DCOA1_P" 3.125 ns HIGH 50%;\r
-#NET "DCOA2_P" TNM_NET = DCOA2_P;\r
-#TIMESPEC TS_DCOA2_P = PERIOD "DCOA2_P" 3.125 ns HIGH 50%;\r
-#NET "DCOA3_P" TNM_NET = DCOA3_P;\r
-#TIMESPEC TS_DCOA3_P = PERIOD "DCOA3_P" 3.125 ns HIGH 50%;\r
-#NET "DCOA4_P" TNM_NET = DCOA4_P;\r
-#TIMESPEC TS_DCOA4_P = PERIOD "DCOA4_P" 3.125 HIGH 50%;\r
-#NET "DCOB1_P" TNM_NET = DCOB1_P;\r
-#TIMESPEC TS_DCOB1_P = PERIOD "DCOB1_P" 3.125 ns HIGH 50%;\r
-#NET "DCOB2_P" TNM_NET = DCOB2_P;\r
-#TIMESPEC TS_DCOB2_P = PERIOD "DCOB2_P" 3.125 ns HIGH 50%;\r
-#NET "DCOB3_P" TNM_NET = DCOB3_P;\r
-#TIMESPEC TS_DCOB3_P = PERIOD "DCOB3_P" 3.125 ns HIGH 50%;\r
-#NET "DCOB4_P" TNM_NET = DCOB4_P;\r
-#TIMESPEC TS_DCOB4_P = PERIOD "DCOB4_P" 3.125 ns HIGH 50%;\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" MAXSKEW = 100 ps;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" MAXDELAY = 500 ps;\r
-\r
-#390\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" MAXDELAY = 750 ps;\r
-\r
-# half of real frequency because of synchronisation with falling edge\r
-#NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv";\r
-#TIMESPEC TS_AdcToplevel1458_1_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" 12.5 ns HIGH 50 %;\r
-#NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv";\r
-#TIMESPEC TS_AdcToplevel2356_1_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" 12.5 ns HIGH 50 %;\r
-#\r
-#NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv";\r
-#TIMESPEC TS_AdcToplevel1458_2_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" 12.5 ns HIGH 50 %;\r
-#NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv";\r
-#TIMESPEC TS_AdcToplevel2356_2_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" 12.5 ns HIGH 50 %;\r
-#\r
-#NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv";\r
-#TIMESPEC TS_AdcToplevel1458_3_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" 12.5 ns HIGH 50 %;\r
-#NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv";\r
-#TIMESPEC TS_AdcToplevel2356_3_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" 12.5 ns HIGH 50 %;\r
-#\r
-#NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv";\r
-#TIMESPEC TS_AdcToplevel1458_4_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" 12.5 ns HIGH 50 %;\r
-#NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv";\r
-#TIMESPEC TS_AdcToplevel2356_4_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" 12.5 ns HIGH 50 %;\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk";\r
-TIMESPEC TS_AdcToplevel1458_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" 3 ns HIGH 50 %;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk";\r
-TIMESPEC TS_AdcToplevel2356_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" 3 ns HIGH 50 %;\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk";\r
-TIMESPEC TS_AdcToplevel1458_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" 3 ns HIGH 50 %;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk";\r
-TIMESPEC TS_AdcToplevel2356_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" 3 ns HIGH 50 %;\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk";\r
-TIMESPEC TS_AdcToplevel1458_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" 3 ns HIGH 50 %;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk";\r
-TIMESPEC TS_AdcToplevel2356_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" 3 ns HIGH 50 %;\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk";\r
-TIMESPEC TS_AdcToplevel1458_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" 3 ns HIGH 50 %;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk";\r
-TIMESPEC TS_AdcToplevel2356_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" 3 ns HIGH 50 %;\r
-\r
-\r
-#NET "ADC_clk_S" TNM_NET = "ADC_clk_S";\r
-#TIMESPEC TS_ADC_clk_S = PERIOD "ADC_clk_S" 12.5 ns HIGH 50 %;\r
-#NET "ADC_clk_S" MAXDELAY = 1.6 ns;
-#NET "ADC_clk_S" MAXSKEW = 1.6 ns;
-#NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "FEE_ADCinput_module1/ADC_clknot_S";\r
-#TIMESPEC TS_clknot_S = PERIOD "FEE_ADCinput_module1/ADC_clknot_S" 12.5 ns HIGH 50 %;\r
-#NET "FEE_ADCinput_module1/ADC_clknot_S" MAXDELAY = 1.6 ns;\r
-#NET "FEE_ADCinput_module1/ADC_clknot_S" MAXSKEW = 1.6 ns;\r
-#
-#TIMESPEC TS_AdcToplevel1458_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TO "ADC_clk_S" 4.5 ns;\r
-#\r
-#TIMESPEC TS_AdcToplevel1458_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;\r
-\r
-NET "ADC_clk_S" TNM_NET = "ADC_clk_S_clk";\r
-TIMESPEC TS_ADC_clk_S_clk = PERIOD "ADC_clk_S_clk" 12.5 ns HIGH 50 %;\r
-NET "ADC_clk_S" TNM_NET = "ADC_clk_S_net";\r
-NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "ADC_clknot_S_clk";\r
-TIMESPEC TS_ADC_clknot_S_clk = PERIOD "ADC_clknot_S_clk" 12.5 ns HIGH 50 %;\r
-NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "ADC_clknot_S_net";\r
-\r
-NET "ADC_clk_S" MAXDELAY = 1.6 ns;\r
-NET "ADC_clk_S" MAXSKEW = 1 ns;\r
-NET "FEE_ADCinput_module1/ADC_clknot_S" MAXDELAY = 1.4 ns;\r
-NET "FEE_ADCinput_module1/ADC_clknot_S" MAXSKEW = 1 ns;\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1458_1_per";\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv1458_2_per";\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv1458_3_per";\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv1458_4_per";\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv2356_1_per";\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv2356_2_per";\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv2356_3_per";\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv2356_4_per";\r
-\r
-TIMESPEC TS_AdcToplevel1458_1_IntClkDiv_per = PERIOD "IntClkDiv1458_1_per" 12.5 ns HIGH 50 %;\r
-TIMESPEC TS_AdcToplevel1458_2_IntClkDiv_per = PERIOD "IntClkDiv1458_2_per" 12.5 ns HIGH 50 %;\r
-TIMESPEC TS_AdcToplevel1458_3_IntClkDiv_per = PERIOD "IntClkDiv1458_3_per" 12.5 ns HIGH 50 %;\r
-TIMESPEC TS_AdcToplevel1458_4_IntClkDiv_per = PERIOD "IntClkDiv1458_4_per" 12.5 ns HIGH 50 %;\r
-TIMESPEC TS_AdcToplevel2356_1_IntClkDiv_per = PERIOD "IntClkDiv2356_1_per" 12.5 ns HIGH 50 %;\r
-TIMESPEC TS_AdcToplevel2356_2_IntClkDiv_per = PERIOD "IntClkDiv2356_2_per" 12.5 ns HIGH 50 %;\r
-TIMESPEC TS_AdcToplevel2356_3_IntClkDiv_per = PERIOD "IntClkDiv2356_3_per" 12.5 ns HIGH 50 %;\r
-TIMESPEC TS_AdcToplevel2356_4_IntClkDiv_per = PERIOD "IntClkDiv2356_4_per" 12.5 ns HIGH 50 %;\r
-\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1458_1_net";\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv1458_2_net";\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv1458_3_net";\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv1458_4_net";\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv2356_1_net";\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv2356_2_net";\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv2356_3_net";\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv2356_4_net";\r
-\r
-TIMESPEC TS_AdcToplevel1458_1_IntClkDiv_net = FROM "IntClkDiv1458_1_net" TO "ADC_clknot_S_net" 4 ns;\r
-TIMESPEC TS_AdcToplevel1458_2_IntClkDiv_net = FROM "IntClkDiv1458_2_net" TO "ADC_clknot_S_net" 4 ns;\r
-TIMESPEC TS_AdcToplevel1458_3_IntClkDiv_net = FROM "IntClkDiv1458_3_per" TO "ADC_clknot_S_net" 4 ns;\r
-TIMESPEC TS_AdcToplevel1458_4_IntClkDiv_net = FROM "IntClkDiv1458_4_per" TO "ADC_clknot_S_net" 4 ns;\r
-TIMESPEC TS_AdcToplevel2356_1_IntClkDiv_net = FROM "IntClkDiv2356_1_per" TO "ADC_clknot_S_net" 4 ns;\r
-TIMESPEC TS_AdcToplevel2356_2_IntClkDiv_net = FROM "IntClkDiv2356_2_per" TO "ADC_clknot_S_net" 4 ns;\r
-TIMESPEC TS_AdcToplevel2356_3_IntClkDiv_net = FROM "IntClkDiv2356_3_per" TO "ADC_clknot_S_net" 4 ns;\r
-TIMESPEC TS_AdcToplevel2356_4_IntClkDiv_net = FROM "IntClkDiv2356_4_per" TO "ADC_clknot_S_net" 4 ns;\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
-\r
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/reset_clockdiv_S" MAXSKEW = 250 ps;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/reset_clockdiv_S" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/reset_clockdiv_S" MAXDELAY = 850 ps;
-\r
-\r
-NET "FEE_ADCinput_module1/FRA1_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA1_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA2_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA2_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA3_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA3_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA4_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA4_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB1_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB1_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB2_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB2_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB3_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB3_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB4_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB4_N_S" MAXDELAY = 20 ps;
-\r
-NET "ST_CLK_P" TNM_NET = "ST_CLK_P";\r
-TIMESPEC TS_ST_CLK_P = PERIOD "ST_CLK_P" 6.43 ns HIGH 50 %;\r
-NET "ST_CLK_N" TNM_NET = "ST_CLK_N";\r
-TIMESPEC TS_ST_CLK_N = PERIOD "ST_CLK_N" 6.43 ns HIGH 50 %;\r
-\r
-INST "*AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds";\r
-INST "*AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrm_Isrds";\r
-INST "*AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcDat_Isrds";\r
-INST "*AdcClock/*" TNM = FFS "AdcClk_Ffs";\r
-INST "*AdcFrame/*" TNM = FFS "AdcFrm_Ffs";\r
-INST "*AdcData/*" TNM = FFS "AdcDat_Ffs";\r
-TIMESPEC TS_ClkIsrds_ClkFfs = FROM "AdcClk_Isrds" TO "AdcClk_Ffs" 2.4 ns;\r
-TIMESPEC TS_FrmIsrds_FrmFfs = FROM "AdcFrm_Isrds" TO "AdcFrm_Ffs" 2.4 ns;\r
-TIMESPEC TS_DatIsrds_DatFfs = FROM "AdcDat_Isrds" TO "AdcDat_Ffs" 2.4 ns;\r
-\r
-NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S_clk";\r
-TIMESPEC TS_clock_ADCref_S_clk = PERIOD "clock_ADCref_S_clk" 12.5 ns HIGH 50 %;\r
-NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S_net";\r
-\r
-NET "ST_CLK_S" TNM_NET = "ST_CLK_S_clk";\r
-TIMESPEC TS_ST_CLK_S_clk = PERIOD "ST_CLK_S_clk" 6.43 ns HIGH 50 %;\r
-NET "ST_CLK_S" TNM_NET = "ST_CLK_S_net";\r
-\r
-NET "GCLK_S" TNM_NET = "GCLK_S_clk";\r
-TIMESPEC TS_GCLK_S_clk = PERIOD "GCLK_S_clk" 12.5 ns HIGH 50 %;\r
-NET "GCLK_S" TNM_NET = "GCLK_S_net";\r
-\r
-#NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S";\r
-#TIMESPEC TS_rxSodaClk_S_clk = PERIOD "rxSodaClk_S_clk" 6.25 ns HIGH 50 %;\r
-#NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S_net";\r
-\r
-NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "rxSodaClk_S";\r
-TIMESPEC TS_rxSodaClk_S_clk = PERIOD "rxSodaClk_S_clk" 6.25 ns HIGH 50 %;\r
-NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "rxSodaClk_S_net";\r
-\r
-\r
-TIMESPEC TS_ADC_to_ADC = FROM "clock_ADCref_S_net" TO "clock_ADCref_S_net" 12.5 ns;\r
-TIMESPEC TS_ST_to_ST = FROM "ST_CLK_S_net" TO "ST_CLK_S_net" 6.43 ns;\r
-TIMESPEC TS_G_to_G = FROM "GCLK_S_net" TO "GCLK_S_net" 12.5 ns;\r
-TIMESPEC TS_SODA_to_SODA = FROM "rxSodaClk_S_net" TO "rxSodaClk_S_net" 6.25 ns;\r
-\r
-\r
-TIMESPEC TS_ADC_to_ST = FROM "clock_ADCref_S_net" TO "ST_CLK_S_net" TIG;\r
-TIMESPEC TS_ST_to_ADC = FROM "ST_CLK_S_net" TO "clock_ADCref_S_net" TIG;\r
-TIMESPEC TS_G_to_ST = FROM "GCLK_S_net" TO "ST_CLK_S_net" TIG;\r
-TIMESPEC TS_SODA_to_ST = FROM "rxSodaClk_S_net" TO "ST_CLK_S_net" TIG;\r
-TIMESPEC TS_SODA_to_G = FROM "rxSodaClk_S_net" TO "GCLK_S_net" TIG;\r
-TIMESPEC TS_SODA_to_ADC = FROM "rxSodaClk_S_net" TO "clock_ADCref_S_net" TIG;\r
-\r
-#NET "ST_CLK_S" TNM_NET = "ST_CLK_S";\r
-#NET "GCLK_S" TNM_NET = "GCLK_S";
-#NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S";
-##NET "clock125Mhz_S" TNM_NET = "clock125MHz_S";
-#NET "clock200Mhz_S" TNM_NET = "clock200MHz_S";
-##NET "clock100Mhz_S" TNM_NET = "clock100MHz_S";
-#
-##TIMESPEC TS_125M_to_ref = FROM "clock125MHz_S" TO "clock_ADCref_S" TIG;
-##TIMESPEC TS_ref_to_125M = FROM "clock_ADCref_S" TO "clock125MHz_S" TIG;
-#TIMESPEC TS_GCLK_to_ref = FROM "GCLK_S" TO "clock_ADCref_S" TIG;
-#TIMESPEC TS_ref_to_GCLK = FROM "clock_ADCref_S" TO "GCLK_S" TIG;
-##TIMESPEC TS_GCLK_to_125M = FROM "GCLK_S" TO "clock125MHz_S" TIG;
-##TIMESPEC TS_125M_to_GCLK = FROM "clock125MHz_S" TO "GCLK_S" TIG;
-#\r
-#
-##TIMESPEC TS_62M5_to_100M = FROM "clock62M5Hz_S" TO "clock100MHz_S" TIG;
-##TIMESPEC TS_100M_to_62M5 = FROM "clock100MHz_S" TO "clock62M5Hz_S" TIG;
-##TIMESPEC TS_125M_to_100M = FROM "clock125MHz_S" TO "clock100MHz_S" TIG;
-##TIMESPEC TS_100M_to_125M = FROM "clock100MHz_S" TO "clock125MHz_S" TIG;
-#
-#TIMESPEC TS_ref_to_200M = FROM "clock62M5Hz_S" TO "clock200MHz_S" TIG;
-#TIMESPEC TS_200M_to_ref = FROM "clock200MHz_S" TO "clock62M5Hz_S" TIG;
-#TIMESPEC TS_GCLK_to_200M = FROM "GCLK_S" TO "clock200MHz_S" TIG;
-#TIMESPEC TS_200M_to_GCLK = FROM "clock200MHz_S" TO "GCLK_S" TIG;
-##TIMESPEC TS_125M_to_200M = FROM "clock125MHz_S" TO "clock200MHz_S" TIG;
-##TIMESPEC TS_200M_to_125M = FROM "clock200MHz_S" TO "clock125MHz_S" TIG;
-#
-#TIMESPEC TS_ref_to_ST_CLK = FROM "clock_ADCref_S" TO "ST_CLK_S" TIG;
-#TIMESPEC TS_ST_CLK_to_ref = FROM "ST_CLK_S" TO "clock_ADCref_S" TIG;
-#TIMESPEC TS_GCLK_to_ST_CLK = FROM "GCLK_S" TO "ST_CLK_S" TIG;
-#TIMESPEC TS_ST_CLK_to_GCLK = FROM "ST_CLK_S" TO "GCLK_S" TIG;
-##TIMESPEC TS_125M_to_ST_CLK = FROM "clock125MHz_S" TO "ST_CLK_S" TIG;
-##TIMESPEC TS_ST_CLK_to_125M = FROM "ST_CLK_S" TO "clock125MHz_S" TIG;
-#TIMESPEC TS_200M_to_ST_CLK = FROM "clock200MHz_S" TO "ST_CLK_S" TIG;
-#TIMESPEC TS_ST_CLK_to_200M = FROM "ST_CLK_S" TO "clock200MHz_S" TIG;
-#\r
-#NET "ST_CLK_S_BUFG" TNM_NET = "ST_CLK_S_BUFG";
-#TIMESPEC TS_ref_to_ST_CLK_BUFG = FROM "clock_ADCref_S" TO "ST_CLK_S_BUFG" TIG;
-#TIMESPEC TS_ST_CLK_BUFG_to_ref = FROM "ST_CLK_S_BUFG" TO "clock_ADCref_S" TIG;
-#TIMESPEC TS_GCLK_to_ST_CLK_BUFG = FROM "GCLK_S" TO "ST_CLK_S_BUFG" TIG;
-#TIMESPEC TS_ST_CLK_BUFG_to_GCLK = FROM "ST_CLK_S_BUFG" TO "GCLK_S" TIG;
-##TIMESPEC TS_125M_to_ST_CLK_BUFG = FROM "clock125MHz_S" TO "ST_CLK_S_BUFG" TIG;
-##TIMESPEC TS_ST_CLK_BUFG_to_125M = FROM "ST_CLK_S_BUFG" TO "clock125MHz_S" TIG;
-#TIMESPEC TS_200M_to_ST_CLK_BUFG = FROM "clock200MHz_S" TO "ST_CLK_S_BUFG" TIG;
-#TIMESPEC TS_ST_CLK_BUFG_to_200M = FROM "ST_CLK_S_BUFG" TO "clock200MHz_S" TIG;\r
-\r
-#TIMESPEC TS_62M5_to_txUsrClk2 = FROM "clock62M5Hz_S" TO "FEE_gtxModule1/txUsrClk2_S" 20 ns;\r
-#TIMESPEC TS_txUsrClk2_to_62M5 = FROM "FEE_gtxModule1/txUsrClk2_S" TO "clock62M5Hz_S" 20 ns;\r
-\r
-NET "GCLK_P" TNM_NET = "GCLK_P";\r
-TIMESPEC TS_GCLK_P = PERIOD "GCLK_P" 12.5 ns HIGH 50 %;\r
-NET "GCLK_N" TNM_NET = "GCLK_N";\r
-TIMESPEC TS_GCLK_N = PERIOD "GCLK_N" 12.5 ns HIGH 50 %;\r
-\r
-NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P";\r
-TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 12.5 ns HIGH 50 %;\r
-NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N";\r
-TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 12.5 ns HIGH 50 %;\r
-\r
-NET "FEE_gtxModule1/txUsrClk_S" TNM_NET = "FEE_gtxModule1/txUsrClk_S";\r
-TIMESPEC TS_FEE_gtxModule1_txUsrClk_S = PERIOD "FEE_gtxModule1/txUsrClk_S" 5 ns HIGH 50 %;\r
-NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S";\r
-TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Virtex6_1_rxRecClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" 5 ns HIGH 50 %;\r
-NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S" TNM_NET = FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S;\r
-TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Virtex6_1_txOutClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S" 12.5 ns HIGH 50%;\r
-#INST FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/gtx_i/gtx0_gtxVirtex6FEE_i/gtxe1_i LOC=GTXE1_X0Y12;
-#INST FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/gtx_i LOC=GTXE1_X0Y12;
-\r
-#TIMESPEC TS_RXCLK_to_TXCLK = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" TO "FEE_gtxModule1/txUsrClk2_S" 3 ns;\r
-#TIMESPEC TS_TXCLK_to_RXCLK = FROM "FEE_gtxModule1/txUsrClk2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" 3 ns;\r
-#TIMESPEC TS_RXCLK_to_TXCLK0 = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk0_S" 3 ns;\r
-#TIMESPEC TS_TXCLK0_to_RXCLK = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk0_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" 3 ns;\r
-\r
-\r
-NET "GEO" IOSTANDARD = LVCMOS25;\r
-#NET "GEO" DRIVE = 12;\r
-NET "GEO" SLEW = SLOW;\r
-NET "GEO" PULLUP;\r
-net "GEO" TIG;\r
-#NET "S_CTRL" TIG;\r
-#NET "T_CTRL_S" TIG;\r
-\r
-#INST "FEE_ADCinput_module1/AdcTopleveL1458_1/*" AREA_GROUP=pblock_adc_A1;
-#AREA_GROUP "pblock_adc_A1" RANGE=SLICE_X30Y140:SLICE_X35Y159;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL2356_1/*" AREA_GROUP=pblock_adc_B1;
-#AREA_GROUP "pblock_adc_B1" RANGE=SLICE_X30Y120:SLICE_X35Y139;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL1458_2/*" AREA_GROUP=pblock_adc_A2;
-#AREA_GROUP "pblock_adc_A2" RANGE=SLICE_X0Y120:SLICE_X5Y139;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL2356_2/*" AREA_GROUP=pblock_adc_B2;
-#AREA_GROUP "pblock_adc_B2" RANGE=SLICE_X0Y140:SLICE_X5Y159;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL1458_3/*" AREA_GROUP=pblock_adc_A3;
-#AREA_GROUP "pblock_adc_A3" RANGE=SLICE_X0Y100:SLICE_X5Y119;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL2356_3/*" AREA_GROUP=pblock_adc_B3;
-#AREA_GROUP "pblock_adc_B3" RANGE=SLICE_X0Y80:SLICE_X5Y99;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL1458_4/*" AREA_GROUP=pblock_adc_A4;
-#AREA_GROUP "pblock_adc_A4" RANGE=SLICE_X64Y100:SLICE_X69Y119;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL2356_4/*" AREA_GROUP=pblock_adc_B4;
-#AREA_GROUP "pblock_adc_B4" RANGE=SLICE_X64Y80:SLICE_X69Y99;
-\r
-\r
-INST "FEE_ADCinput_module1/AdcTopleveL1458_1/*" AREA_GROUP=pblock_adc_1;
-INST "FEE_ADCinput_module1/AdcTopleveL2356_1/*" AREA_GROUP=pblock_adc_1;
-AREA_GROUP "pblock_adc_1" RANGE=SLICE_X30Y120:SLICE_X35Y159;
-
-INST "FEE_ADCinput_module1/AdcTopleveL1458_2/*" AREA_GROUP=pblock_adc_2;
-INST "FEE_ADCinput_module1/AdcTopleveL2356_2/*" AREA_GROUP=pblock_adc_2;
-AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y120:SLICE_X5Y159;
-
-INST "FEE_ADCinput_module1/AdcTopleveL1458_3/*" AREA_GROUP=pblock_adc_3;
-INST "FEE_ADCinput_module1/AdcTopleveL2356_3/*" AREA_GROUP=pblock_adc_3;
-AREA_GROUP "pblock_adc_3" RANGE=SLICE_X0Y80:SLICE_X5Y119;
-
-INST "FEE_ADCinput_module1/AdcTopleveL1458_4/*" AREA_GROUP=pblock_adc_4;
-INST "FEE_ADCinput_module1/AdcTopleveL2356_4/*" AREA_GROUP=pblock_adc_4;
-AREA_GROUP "pblock_adc_4" RANGE=SLICE_X64Y80:SLICE_X69Y119;
-\r
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="../FEE_modules/FEE_pulse_and_pileup_waveforms.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
- </file>
- <file xil_pn:name="../FEE_modules/FEE_sorting_wavemux.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
- </file>
- <file xil_pn:name="../FEE_modules/FEE_wavemux_readfifo.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
- </file>
- <file xil_pn:name="../FEE_modules/FEE_wavemux2to1.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
- </file>
- <file xil_pn:name="../FEE_modules/shift_register.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
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- <property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="Drive Done Pin High" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="3" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.top" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.top" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
- <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/virtex6/data/virtex6_performance_with_physicalsynthesis2.xds" xil_pn:valueState="non-default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="iMPACT Project File" xil_pn:value="FEE_V2_ADC32board.ipf" xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|sim_SODA2_tb|behavior" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="FEE_test_ADC32" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-20T09:50:16" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AA4862807094468B9C6DDA953391E7F7" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-
-library IEEE;
-use IEEE.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.all;
-USE ieee.std_logic_arith.all;
-library UNISIM;
-use UNISIM.VComponents.all;
-library work;
-use work.panda_package.all;
---use work.panda_pkg.all;
-
-entity top is
- Port ( \r
- GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2\r
- GCLK_P : in std_logic; -- clock equal to GTX refclock (62.5MHz or 80MHz)
- GCLK_N : in std_logic;\r
- \r
- ST_CLK_P : in std_logic; -- 155.52MHz\r
- ST_CLK_N : in std_logic;\r
-\r
-\r
-----ADC1--------------------------------------------- \r
- AD11A_P : in std_logic;
- AD11A_N : in std_logic;
- AD11B_P : in std_logic;
- AD11B_N : in std_logic;
- AD12A_P : in std_logic;
- AD12A_N : in std_logic;
- AD12B_P : in std_logic;
- AD12B_N : in std_logic;
- AD13A_P : in std_logic;
- AD13A_N : in std_logic;
- AD13B_P : in std_logic;
- AD13B_N : in std_logic;
- AD14A_P : in std_logic;
- AD14A_N : in std_logic;
- AD14B_P : in std_logic;
- AD14B_N : in std_logic;
- AD15A_P : in std_logic;
- AD15A_N : in std_logic;
- AD15B_P : in std_logic;
- AD15B_N : in std_logic;
- AD16A_P : in std_logic;
- AD16A_N : in std_logic;
- AD16B_P : in std_logic;
- AD16B_N : in std_logic;
- AD17A_P : in std_logic;
- AD17A_N : in std_logic;
- AD17B_P : in std_logic;
- AD17B_N : in std_logic;
- AD18A_P : in std_logic;
- AD18A_N : in std_logic;
- AD18B_P : in std_logic;
- AD18B_N : in std_logic;\r
- \r
- DCOA1_P : in std_logic;
- DCOA1_N : in std_logic;
- DCOB1_P : in std_logic;
- DCOB1_N : in std_logic;
- \r
- FRA1_P : in std_logic;
- FRA1_N : in std_logic;
- FRB1_P : in std_logic;
- FRB1_N : in std_logic;\r
-\r
-----ADC2--------------------------------------------- \r
- AD21A_P : in std_logic;
- AD21A_N : in std_logic;
- AD21B_P : in std_logic;
- AD21B_N : in std_logic;
- AD22A_P : in std_logic;
- AD22A_N : in std_logic;
- AD22B_P : in std_logic;
- AD22B_N : in std_logic;
- AD23A_P : in std_logic;
- AD23A_N : in std_logic;
- AD23B_P : in std_logic;
- AD23B_N : in std_logic;
- AD24A_P : in std_logic;
- AD24A_N : in std_logic;
- AD24B_P : in std_logic;
- AD24B_N : in std_logic;
- AD25A_P : in std_logic;
- AD25A_N : in std_logic;
- AD25B_P : in std_logic;
- AD25B_N : in std_logic;
- AD26A_P : in std_logic;
- AD26A_N : in std_logic;
- AD26B_P : in std_logic;
- AD26B_N : in std_logic;
- AD27A_P : in std_logic;
- AD27A_N : in std_logic;
- AD27B_P : in std_logic;
- AD27B_N : in std_logic;
- AD28A_P : in std_logic;
- AD28A_N : in std_logic;
- AD28B_P : in std_logic;
- AD28B_N : in std_logic;\r
-\r
- DCOA2_P : in std_logic;
- DCOA2_N : in std_logic;
- DCOB2_P : in std_logic;
- DCOB2_N : in std_logic;
- \r
- FRA2_P : in std_logic;
- FRA2_N : in std_logic;
- FRB2_P : in std_logic;
- FRB2_N : in std_logic;\r
-\r
-----ADC3--------------------------------------------- \r
- AD31A_P : in std_logic;
- AD31A_N : in std_logic;
- AD31B_P : in std_logic;
- AD31B_N : in std_logic;
- AD32A_P : in std_logic;
- AD32A_N : in std_logic;
- AD32B_P : in std_logic;
- AD32B_N : in std_logic;
- AD33A_P : in std_logic;
- AD33A_N : in std_logic;
- AD33B_P : in std_logic;
- AD33B_N : in std_logic;
- AD34A_P : in std_logic;
- AD34A_N : in std_logic;
- AD34B_P : in std_logic;
- AD34B_N : in std_logic;
- AD35A_P : in std_logic;
- AD35A_N : in std_logic;
- AD35B_P : in std_logic;
- AD35B_N : in std_logic;
- AD36A_P : in std_logic;
- AD36A_N : in std_logic;
- AD36B_P : in std_logic;
- AD36B_N : in std_logic;
- AD37A_P : in std_logic;
- AD37A_N : in std_logic;
- AD37B_P : in std_logic;
- AD37B_N : in std_logic;
- AD38A_P : in std_logic;
- AD38A_N : in std_logic;
- AD38B_P : in std_logic;
- AD38B_N : in std_logic;\r
-\r
- DCOA3_P : in std_logic;
- DCOA3_N : in std_logic;
- DCOB3_P : in std_logic;
- DCOB3_N : in std_logic;
- \r
- FRA3_P : in std_logic;
- FRA3_N : in std_logic;
- FRB3_P : in std_logic;
- FRB3_N : in std_logic;\r
-\r
-----ADC4--------------------------------------------- \r
- AD41A_P : in std_logic;
- AD41A_N : in std_logic;
- AD41B_P : in std_logic;
- AD41B_N : in std_logic;
- AD42A_P : in std_logic;
- AD42A_N : in std_logic;
- AD42B_P : in std_logic;
- AD42B_N : in std_logic;
- AD43A_P : in std_logic;
- AD43A_N : in std_logic;
- AD43B_P : in std_logic;
- AD43B_N : in std_logic;
- AD44A_P : in std_logic;
- AD44A_N : in std_logic;
- AD44B_P : in std_logic;
- AD44B_N : in std_logic;
- AD45A_P : in std_logic;
- AD45A_N : in std_logic;
- AD45B_P : in std_logic;
- AD45B_N : in std_logic;
- AD46A_P : in std_logic;
- AD46A_N : in std_logic;
- AD46B_P : in std_logic;
- AD46B_N : in std_logic;
- AD47A_P : in std_logic;
- AD47A_N : in std_logic;
- AD47B_P : in std_logic;
- AD47B_N : in std_logic;
- AD48A_P : in std_logic;
- AD48A_N : in std_logic;
- AD48B_P : in std_logic;
- AD48B_N : in std_logic; \r
- \r
- DCOA4_P : in std_logic;
- DCOA4_N : in std_logic;
- DCOB4_P : in std_logic;
- DCOB4_N : in std_logic;
- \r
- FRA4_P : in std_logic;
- FRA4_N : in std_logic;
- FRB4_P : in std_logic;
- FRB4_N : in std_logic;\r
- \r
-----ADCconfiguration--------------------------------------------- \r
- SCK : out std_logic;\r
- SDI : out std_logic;\r
- CSA : out std_logic_vector(1 to 4);\r
- CSB : out std_logic_vector(1 to 4);\r
- SDOA : inout std_logic_vector(1 to 4);\r
- SDOB : inout std_logic_vector(1 to 4);\r
-\r
-----GTX--------------------------------------------- \r
- MOD_DEF : in std_logic_vector(2 downto 0);\r
- LOS : in std_logic;\r
- TX_DIS : out std_logic;\r
- MGTREFCLK_P : in std_logic;\r
- MGTREFCLK_N : in std_logic;\r
-\r
- RX_P : in std_logic;\r
- RX_N : in std_logic;\r
- TX_P : out std_logic;\r
- TX_N : out std_logic;\r
-\r
-----PLL--------------------------------------------- \r
-\r
- S_CTRL : in std_logic; -- 1 : FPGA1 controls PLL&JTAG, 0 : FPGA2 controls PLL&JTAG\r
- T_CTRL : out std_logic; -- T_CTRL from FPGA1<>FPGA2 : FPGA1 controls PLL&JTAG\r
-\r
- RDu : in std_logic;\r
- CLKu : out std_logic;\r
- DATAu : out std_logic;\r
- LEu : out std_logic;\r
- SYNC : out std_logic;\r
- RCV_CLK_P : out std_logic; -- ref clock for PLL LMK03806\r
- RCV_CLK_N : out std_logic;\r
- \r
-----TMP104--------------------------------------------- \r
--- TEMP_IN : out std_logic;\r
--- TEMP_OUT : in std_logic;\r
- \r
-----test---------------------------------------------
- SM1_P : out std_logic;
- SM1_N : out std_logic;
- SM3_P : in std_logic;
- SM3_N : in std_logic;
-\r
- INTCOMC1_P : inout std_logic;
- INTCOMC1_N : inout std_logic;
- INTCOMC2_P : inout std_logic;
- INTCOMC2_N : inout std_logic;
-\r
- INTCOM0_P : inout std_logic;
- INTCOM0_N : inout std_logic;
- INTCOM1_P : inout std_logic;
- INTCOM1_N : inout std_logic;\r
- INTCOM2_P : inout std_logic;
- INTCOM2_N : inout std_logic;\r
- INTCOM3_P : inout std_logic;
- INTCOM3_N : inout std_logic;
- INTCOM4_P : inout std_logic;
- INTCOM4_N : inout std_logic;\r
- INTCOM5_P : inout std_logic;
- INTCOM5_N : inout std_logic;\r
- INTCOM6_P : inout std_logic;
- INTCOM6_N : inout std_logic;
- INTCOM7_P : inout std_logic;
- INTCOM7_N : inout std_logic;\r
-\r
- TCK_F : in std_logic;\r
- TDI_F : in std_logic;\r
- TDO_F : in std_logic;\r
- TMS_F : in std_logic\r
--- PROGRAM_B : inout std_logic
-\r
-\r
--- D : in std_logic_VECTOR (7 downto 0)
- );
-end top;
-\r
-\r
-
-architecture Behavioral of top is
-\r
-component clockmodule80M
-port (
- CLK_IN1 : in std_logic;
- CLK_OUT1 : out std_logic;
- LOCKED : out std_logic
- );
-end component;\r
-\r
-component clock155to200MHz
-port(
- CLK_IN1 : in std_logic;
- CLK_IN2 : in std_logic;
- CLK_IN_SEL : in std_logic;
- CLK_OUT1 : out std_logic;
- RESET : in std_logic;
- LOCKED : out std_logic
- );
-end component;\r
-\r
-component clockmodule80to80M\r
-port(\r
- CLK_IN1 : in std_logic;\r
- CLK_OUT1 : out std_logic;\r
- CLK_OUT2 : out std_logic;\r
- CLK_OUT3 : out std_logic;\r
- CLK_OUT4 : out std_logic;\r
- RESET : in std_logic;\r
- LOCKED : out std_logic\r
- );\r
-end component;\r
-\r
-component clockmodule40to80\r
-port(\r
- CLK_IN1 : in std_logic;\r
- CLK_OUT1 : out std_logic;\r
- LOCKED : out std_logic\r
- );\r
-end component;\r
-\r
-component clockmodule40switch\r
-port(\r
- CLK_IN1 : in std_logic;\r
- CLK_IN2 : in std_logic;\r
- CLK_IN_SEL : in std_logic;\r
- CLK_OUT1 : out std_logic;\r
- CLK_OUT2 : out std_logic;\r
- RESET : in std_logic;\r
- LOCKED : out std_logic\r
- );\r
-end component;\r
-\r
-component LMK03806 is
- generic(
- CLK_DIV : integer := 6; -- slow down transfer
- ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY
- );
- PORT( \r
- clock : in std_logic; --Master clock
- CLKu : out std_logic; --Clk to LMK
- DATAu : out std_logic; --Data to LMK
- LEu : out std_logic; --Data Latch to LMK
- RDn : in std_logic; --Read back
- SYNC : out std_logic; --Sync CLK outputs LMK
- boot_PLL : in std_logic; --Start booting when set high\r
- reset_GTX : out std_logic; --delayed reset for GTX
- reset_ADCs : out std_logic; --delayed reset for ADCs \r
- booting : out std_logic; --busy signal \r
- testwordin : in std_logic_vector(15 downto 0)
- );
-end component;
-\r
-component FEE_ADCinput_module is
- port (
- clock200MHz : in std_logic;
- reset : in std_logic;
- ADCs_enable : in std_logic;
-----ADC1---------------------------------------------
- AD11A_P : in std_logic;
- AD11A_N : in std_logic;
- AD11B_P : in std_logic;
- AD11B_N : in std_logic;
- AD12A_P : in std_logic;
- AD12A_N : in std_logic;
- AD12B_P : in std_logic;
- AD12B_N : in std_logic;
- AD13A_P : in std_logic;
- AD13A_N : in std_logic;
- AD13B_P : in std_logic;
- AD13B_N : in std_logic;
- AD14A_P : in std_logic;
- AD14A_N : in std_logic;
- AD14B_P : in std_logic;
- AD14B_N : in std_logic;
- AD15A_P : in std_logic;
- AD15A_N : in std_logic;
- AD15B_P : in std_logic;
- AD15B_N : in std_logic;
- AD16A_P : in std_logic;
- AD16A_N : in std_logic;
- AD16B_P : in std_logic;
- AD16B_N : in std_logic;
- AD17A_P : in std_logic;
- AD17A_N : in std_logic;
- AD17B_P : in std_logic;
- AD17B_N : in std_logic;
- AD18A_P : in std_logic;
- AD18A_N : in std_logic;
- AD18B_P : in std_logic;
- AD18B_N : in std_logic;
-
- DCOA1_P : in std_logic;
- DCOA1_N : in std_logic;
- DCOB1_P : in std_logic;
- DCOB1_N : in std_logic;
-
- FRA1_P : in std_logic;
- FRA1_N : in std_logic;
- FRB1_P : in std_logic;
- FRB1_N : in std_logic;
-
-----ADC2---------------------------------------------
- AD21A_P : in std_logic;
- AD21A_N : in std_logic;
- AD21B_P : in std_logic;
- AD21B_N : in std_logic;
- AD22A_P : in std_logic;
- AD22A_N : in std_logic;
- AD22B_P : in std_logic;
- AD22B_N : in std_logic;
- AD23A_P : in std_logic;
- AD23A_N : in std_logic;
- AD23B_P : in std_logic;
- AD23B_N : in std_logic;
- AD24A_P : in std_logic;
- AD24A_N : in std_logic;
- AD24B_P : in std_logic;
- AD24B_N : in std_logic;
- AD25A_P : in std_logic;
- AD25A_N : in std_logic;
- AD25B_P : in std_logic;
- AD25B_N : in std_logic;
- AD26A_P : in std_logic;
- AD26A_N : in std_logic;
- AD26B_P : in std_logic;
- AD26B_N : in std_logic;
- AD27A_P : in std_logic;
- AD27A_N : in std_logic;
- AD27B_P : in std_logic;
- AD27B_N : in std_logic;
- AD28A_P : in std_logic;
- AD28A_N : in std_logic;
- AD28B_P : in std_logic;
- AD28B_N : in std_logic;
-
- DCOA2_P : in std_logic;
- DCOA2_N : in std_logic;
- DCOB2_P : in std_logic;
- DCOB2_N : in std_logic;
-
- FRA2_P : in std_logic;
- FRA2_N : in std_logic;
- FRB2_P : in std_logic;
- FRB2_N : in std_logic;
-
-----ADC3---------------------------------------------
- AD31A_P : in std_logic;
- AD31A_N : in std_logic;
- AD31B_P : in std_logic;
- AD31B_N : in std_logic;
- AD32A_P : in std_logic;
- AD32A_N : in std_logic;
- AD32B_P : in std_logic;
- AD32B_N : in std_logic;
- AD33A_P : in std_logic;
- AD33A_N : in std_logic;
- AD33B_P : in std_logic;
- AD33B_N : in std_logic;
- AD34A_P : in std_logic;
- AD34A_N : in std_logic;
- AD34B_P : in std_logic;
- AD34B_N : in std_logic;
- AD35A_P : in std_logic;
- AD35A_N : in std_logic;
- AD35B_P : in std_logic;
- AD35B_N : in std_logic;
- AD36A_P : in std_logic;
- AD36A_N : in std_logic;
- AD36B_P : in std_logic;
- AD36B_N : in std_logic;
- AD37A_P : in std_logic;
- AD37A_N : in std_logic;
- AD37B_P : in std_logic;
- AD37B_N : in std_logic;
- AD38A_P : in std_logic;
- AD38A_N : in std_logic;
- AD38B_P : in std_logic;
- AD38B_N : in std_logic;
-
- DCOA3_P : in std_logic;
- DCOA3_N : in std_logic;
- DCOB3_P : in std_logic;
- DCOB3_N : in std_logic;
-
- FRA3_P : in std_logic;
- FRA3_N : in std_logic;
- FRB3_P : in std_logic;
- FRB3_N : in std_logic;
-
-----ADC4---------------------------------------------
- AD41A_P : in std_logic;
- AD41A_N : in std_logic;
- AD41B_P : in std_logic;
- AD41B_N : in std_logic;
- AD42A_P : in std_logic;
- AD42A_N : in std_logic;
- AD42B_P : in std_logic;
- AD42B_N : in std_logic;
- AD43A_P : in std_logic;
- AD43A_N : in std_logic;
- AD43B_P : in std_logic;
- AD43B_N : in std_logic;
- AD44A_P : in std_logic;
- AD44A_N : in std_logic;
- AD44B_P : in std_logic;
- AD44B_N : in std_logic;
- AD45A_P : in std_logic;
- AD45A_N : in std_logic;
- AD45B_P : in std_logic;
- AD45B_N : in std_logic;
- AD46A_P : in std_logic;
- AD46A_N : in std_logic;
- AD46B_P : in std_logic;
- AD46B_N : in std_logic;
- AD47A_P : in std_logic;
- AD47A_N : in std_logic;
- AD47B_P : in std_logic;
- AD47B_N : in std_logic;
- AD48A_P : in std_logic;
- AD48A_N : in std_logic;
- AD48B_P : in std_logic;
- AD48B_N : in std_logic;
-
- DCOA4_P : in std_logic;
- DCOA4_N : in std_logic;
- DCOB4_P : in std_logic;
- DCOB4_N : in std_logic;
-
- FRA4_P : in std_logic;
- FRA4_N : in std_logic;
- FRB4_P : in std_logic;
- FRB4_N : in std_logic;
- ADC_clk : out std_logic;
- ADCs_ready : out std_logic;\r
- adcdata : out array_adc_type
- );
-end component;
-\r
-component FEE_adc32_module is
- generic (
- NROFADCS : natural := NROFADCS;
- ADCBITS : natural := 14;
- BASELINE_BWBITS : natural := 10;
- WAVEFORMBUFFERSIZE : natural := 10;
- ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY;
- CF_DELAYBITS : natural := 4;
- CF_FRACTIONBIT : natural := 11;
- IDIVMAXBITS : natural := 6;
- INTEGRALRATIOBITS : natural := 3
- );
- port (
- clock : in std_logic;
- reset : in std_logic;\r
- enable_data : in std_logic;
- ADCdata : in array_adc_type;\r
- superburst_start : in std_logic;
- superburst_received : in std_logic_vector(30 downto 0);
- onesecondpulse : in std_logic;
- rxNotInTable : in std_logic;
- startupready : in std_logic;
- request_init : in std_logic;
- packet_in_data : in std_logic_vector (31 downto 0);
- packet_in_present : in std_logic;
- packet_in_read : out std_logic;\r
- packet_out_data : out std_logic_vector(31 downto 0);
- packet_out_last : out std_logic;
- packet_out_write : out std_logic;
- packet_out_fifofull : in std_logic;\r
- errorbyte_out : out std_logic_vector(7 downto 0);\r
- errorbyte_in : in std_logic_vector(7 downto 0);\r
- smaart_in : in std_logic;
- smaart_out : out std_logic;\r
- sysmon_data : in std_logic_vector(15 downto 0);\r
- sysmon_reset : out std_logic;\r
- sysmon_address : out std_logic_vector(6 downto 0);\r
- sysmon_read : out std_logic;\r
- testindex : in integer range 0 to NROFADCS/2-1;\r
- testword0 : out std_logic_vector(35 downto 0);
- testword1 : out std_logic_vector(35 downto 0);\r
- testword2 : out std_logic_vector(35 downto 0)\r
- );
-end component; \r
-\r
-component FEE_gtxModule is
- generic(
- ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY -- 80000000 -- 62500000
- );
- Port (
- gtpClk : in std_logic;
- asyncclk : in std_logic;\r
- reset : in std_logic;
- disable_GTX_reset : in std_logic;\r
-
- TX_DLM : in std_logic;
- TX_DLM_WORD : in std_logic_vector(7 downto 0);
- RX_DLM : out std_logic;
- RX_DLM_WORD : out std_logic_vector(7 downto 0);\r
- \r
- txAsyncClk : in std_logic;
- txAsyncData : in std_logic_vector(31 downto 0);
- txAsyncDataWrite : in std_logic;
- txAsyncLastData : in std_logic;
- txAsyncFifoFull : out std_logic;
- txUsrClk : out std_logic;\r
- txLocked : out std_logic;
-
- rxAsyncClk : in std_logic;
- rxAsyncData : out std_logic_vector(31 downto 0);
- rxAsyncDataRead : in std_logic;
- rxNotInTable : out std_logic;
- rxAsyncDataOverflow : out std_logic;
- rxAsyncDataPresent : out std_logic;
- rxSodaClk : out std_logic;
- rxSodaClk40 : out std_logic;
- rxLocked : out std_logic;\r
-
- gtpTxP0 : out std_logic;
- gtpTxN0 : out std_logic;
- gtpRxP0 : in std_logic;
- gtpRxN0 : in std_logic;
- testword0 : out std_logic_vector(35 downto 0)
- );
-end component;
-\r
-component soda_FEE_endpoint is
- generic(
- SODA_16BIT_INTERFACE : boolean := FALSE
- );
- port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
-
- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
- RX_DLM_IN : in std_logic;
- TX_DLM_OUT : out std_logic;
- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
-
-
- START_OF_SUPERBURST : out std_logic := '0';
- SUPER_BURST_NR : out std_logic_vector(30 downto 0) := (others => '0');
- SODA_CMD_VALID : out std_logic := '0';
- SODA_CMD_WORD : out std_logic_vector(30 downto 0) := (others => '0');
-
- STAT : out std_logic_vector(31 downto 0) := (others => '0') -- DEBUG
- );
-end component;\r
-\r
-component SystemMonitorModule is
- Port (
- clock : in std_logic;
- reset : in std_logic;
- address : in std_logic_vector(6 downto 0);
- data_write : in std_logic;
- data_in : in std_logic_vector(15 downto 0);
- data_read : in std_logic;
- data_out : out std_logic_vector(15 downto 0);
- alarms : out std_logic_vector(7 downto 0);
- testword0 : out std_logic_vector(35 downto 0));
-end component;\r
-\r
-component posedge_to_pulse is\r
- port (\r
- clock_in : in std_logic;\r
- clock_out : in std_logic;\r
- en_clk : in std_logic;\r
- signal_in : in std_logic;\r
- pulse : out std_logic\r
- );\r
-end component;\r
-\r
-component posedge_async_to_pulse is\r
- port (\r
- clock_out : in std_logic;\r
- signal_in : in std_logic;\r
- pulse : out std_logic\r
- );\r
-end component;\r
-\r
-component icon0
- port (
- CONTROL0 : inout std_logic_vector(35 downto 0);
- CONTROL1 : inout std_logic_vector(35 downto 0);
- CONTROL2 : inout std_logic_vector(35 downto 0);
- CONTROL3 : inout std_logic_vector(35 downto 0);
- CONTROL4 : inout std_logic_vector(35 downto 0));
-end component;
-
-component ila36
- port (
- CONTROL : inout std_logic_vector(35 downto 0);
- CLK : in std_logic;
- TRIG0 : in std_logic_vector(35 downto 0));
-end component;
-
-component ila128
- port (
- CONTROL : inout std_logic_vector(35 downto 0);
- CLK : in std_logic;
- TRIG0 : in std_logic_vector(127 downto 0));
-end component;
-
-component vio36
- port (
- CONTROL : inout std_logic_vector(35 downto 0);
- ASYNC_OUT : out std_logic_vector(35 downto 0));
-end component;
-\r
-attribute keep : string;\r
-constant DEBUG : boolean := false;\r
--- clocking\r
-signal ST_CLK_S : std_logic;\r
-attribute keep of ST_CLK_S : signal is "TRUE";\r
-signal clock_ADCrefdiv2_S : std_logic;
-signal clock_ADCref_S : std_logic; -- 62.5 or 80 MHz
-attribute keep of clock_ADCref_S : signal is "TRUE";\r
-signal clock100MHz_S : std_logic;
-signal clock200MHz_S : std_logic;\r
-signal clock80MHz_PLL1_S : std_logic;\r
-signal GCLK_S : std_logic;\r
-attribute keep of GCLK_S : signal is "TRUE";\r
-signal gtpClk_S : std_logic;\r
-signal RCV_CLK_P_S : std_logic;\r
-signal RCV_CLK_S : std_logic;
-signal RCV_CLK_not_S : std_logic;\r
-signal RCV_CLKref_S : std_logic;\r
-signal RCV_CLKrx_S : std_logic;\r
-signal ADC_clk_S : std_logic;\r
-attribute keep of ADC_clk_S : signal is "TRUE";\r
-signal txUsrClk_S : std_logic;\r
-\r
-\r
-signal clockPLL1_locked_S : std_logic;\r
-signal clockPLL2_reset_S : std_logic;\r
-signal clockmodule_locked_S : std_logic;\r
-signal clockswitch_locked_S : std_logic;\r
- \r
--- resetting\r
-signal coldstart_counter_S : std_logic_vector(7 downto 0) := (others => '0');
-signal coldstart_S : std_logic := '0';\r
-signal reset_S : std_logic := '0';\r
-signal reset_FEE_S : std_logic := '0';\r
-signal reset_FEE_ADCclk_S : std_logic := '0';\r
-signal resetting_S : std_logic := '0';
-signal resetting_stclk_S : std_logic := '0';
-signal IcontrolPLL_S : std_logic := '0';
-signal otherFPGAnotconfigured0_S : std_logic := '0';
-signal otherFPGAnotconfigured_S : std_logic := '0';
-signal PLLconfigured_S : std_logic := '0';
-signal startupready_S : std_logic := '0';
-signal selectPLLclk_S : std_logic := '0';
-signal selectPLLclk_stclk_S : std_logic := '0';
-signal disable_GTX_reset_S : std_logic := '0';\r
-signal GEO_S : std_logic := '0';
-signal GEO_stclk_S : std_logic := '0';
-signal T_CTRL_S : std_logic := '0';
-signal S_CTRL0_S : std_logic := '0';
-signal phaseSYNC_S : std_logic := '0';\r
-signal boot_PLL_S : std_logic := '0';\r
-signal PLL_booting_S : std_logic := '0';
-signal adcintrfcena_s : std_logic := '0';\r
-signal reset_ADCs_S : std_logic := '0';
-signal ADCs_enable_S : std_logic := '0';\r
-signal reset_GTX_S : std_logic := '0';\r
-signal reset_counter_S : integer range 0 to 65535 := 0;
-signal timeout_counter_S : integer range 0 to 65535 := 0;
-signal external_sync_out_S : std_logic := '0';\r
-signal external_sync_in0_S : std_logic := '0';\r
-signal external_sync_in_S : std_logic := '0';\r
-signal reset_rxSodaClk_S : std_logic;\r
-signal ADCs_ready_S : std_logic;\r
-\r
-\r
--- SODA\r
-signal EnableDataTaking_S : std_logic := '0';\r
-signal DisableDataTaking_S : std_logic := '0';\r
-signal enable_data_S : std_logic := '0';\r
-signal DataTaking_enabled_out_S : std_logic := '0';\r
-signal DataTaking_enabled_in_S : std_logic := '0';\r
-signal SODA_cmd_valid_S : std_logic := '0';\r
-signal SODA_cmd_word_S : std_logic_vector(30 downto 0);\r
-signal superburst_out_S : std_logic_vector(30 downto 0);
-signal superburst_in_S : std_logic_vector(30 downto 0);
-signal superburst_start0_S : std_logic;\r
-signal superburst_start1_S : std_logic;\r
-signal superburst_start_S : std_logic;\r
-signal superburst_startout0_S : std_logic;\r
-signal superburst_startout_S : std_logic;\r
-signal TX_DLM_S : std_logic;
-signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);
-signal RX_DLM_S : std_logic;
-signal RX_DLM_WORD_S : std_logic_vector(7 downto 0);
-
--- fiber data\r
-signal packet_in_data_S : std_logic_vector(31 downto 0);\r
-signal packet_out_data_S : std_logic_vector(31 downto 0) := (others => '0');\r
-signal packet_in_present_S : std_logic := '0';
-signal packet_in_read_S : std_logic := '0';
-signal packet_out_last_S : std_logic := '0';
-signal packet_out_write_S : std_logic := '0';
-signal packet_out_fifofull_S : std_logic := '0';
-signal rxNotInTable0_S : std_logic;
-signal rxNotInTable_S : std_logic;
-\r
-\r
--- clock check\r
-signal GCLKdiv10_S : std_logic := '0';
-signal GCLKdiv10_prev1_S : std_logic := '0';
-signal GCLKdiv10_prev2_S : std_logic := '0';
-signal PLLfrequencyERROR_S : std_logic := '0';
-\r
--- lmk03806\r
-signal CLKu_S : std_logic := '0';
-signal DATAu_S : std_logic := '0';
-signal LEu_S : std_logic := '0';
-signal SYNC_S : std_logic := '0';
-signal SYNC0_S : std_logic := '0';
-signal SYNC1_S : std_logic := '0';
-signal SYNC2_S : std_logic := '0';
-signal debug_sync_S : std_logic := '0';
-\r
--- ADCs\r
-signal adcdata_S : array_adc_type;
-\r
--- GTX\r
-signal LOS_S : std_logic;\r
-signal rxSodaClk_S : std_logic;\r
-attribute keep of rxSodaClk_S : signal is "TRUE";
-signal rxSodaClk40_S : std_logic;\r
-signal rxSodaClk40b_S : std_logic;\r
-signal rxSodaClk80_S : std_logic;\r
-signal rxLocked_S : std_logic;\r
-signal rxLocked0_S : std_logic;\r
-signal rxLocked_sync_S : std_logic;\r
-\r
--- phasedet\r
-signal phasedet_S : std_logic;\r
-signal GCLKdiv2_S : std_logic;\r
-signal GCLKdiv4_S : std_logic;\r
-signal rxSodaClkdiv4_S : std_logic;\r
-signal phaseerr_max_S : integer range 0 to 1023 := 0;
-signal phasedet_count_S : integer range 0 to 1023 := 0;
-signal phaseerr_count_S : integer range 0 to 1023 := 0;
-signal phasecheck_ready_S : std_logic := '0';
-signal phasecheck_ready1_S : std_logic := '0';
-signal phaseSYNCpulse_S : std_logic := '0';
-signal phasecheckcounter_S : integer range 0 to 255 := 0;
-\r
-\r
--- timestamp reset\r
---signal ResetToZero_S : std_logic;\r
-signal onesecondpulse_S : std_logic;\r
- \r
-signal SYNC_stclk_S : std_logic;\r
-signal SYNC_stclk2_S : std_logic;\r
-signal SYNC_adcclk_S : std_logic;\r
-signal SYNC_adcclk2_S : std_logic;\r
-signal SYNC_soda_S : std_logic;\r
-signal SYNC_soda2_S : std_logic;\r
-\r
--- system monitor\r
-signal sysmon_data_S : std_logic_vector(15 downto 0);\r
-signal sysmon_reset_S : std_logic;\r
-signal sysmon_address_S : std_logic_vector(6 downto 0);\r
-signal sysmon_read_S : std_logic;\r
-
--- test compare feature extraction results
-constant SECOND_FE_MODULE : boolean := false;\r
-signal adcdata2_S : array_adc_type;
-signal request_init_S : std_logic := '0';
-signal reset_FEE_ADCclk2_S : std_logic := '0';
-signal reset_FEE_ADCclk2a_S : std_logic := '0';
-signal packet_out_data2_S : std_logic_vector(31 downto 0);\r
-signal packet_in_read2_S : std_logic;
-signal packet_out_last2_S : std_logic;
-signal packet_out_write2_S : std_logic;
-signal unequal_counter_S : std_logic_vector(31 downto 0) := (others => '0');\r
-signal unequal_time_S : std_logic_vector(31 downto 0) := (others => '0');\r
-signal zero_data_S : std_logic;
-signal unequal_S : std_logic;
-signal errorbyte_S : std_logic_vector(7 downto 0) := (others => '0');
-\r
-\r
--- test
-signal control0_S : std_logic_vector(35 downto 0) := (others => '0');
-signal control1_S : std_logic_vector(35 downto 0) := (others => '0');
-signal control2_S : std_logic_vector(35 downto 0) := (others => '0');
-signal control3_S : std_logic_vector(35 downto 0) := (others => '0');
-signal control4_S : std_logic_vector(35 downto 0) := (others => '0');
-signal testword0a_S : std_logic_vector(35 downto 0) := (others => '0');
-signal testword0b_S : std_logic_vector(35 downto 0) := (others => '0');
-signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');
-signal testword1_S : std_logic_vector(35 downto 0) := (others => '0');\r
-signal testwordb_S : std_logic_vector(35 downto 0) := (others => '0');
-signal testword2_S : std_logic_vector(127 downto 0) := (others => '0');\r
-signal vioword_S : std_logic_vector(35 downto 0) := (others => '0');
-signal vioword2_S : std_logic_vector(35 downto 0) := (others => '0');
-signal testwordA0_S : std_logic_vector(35 downto 0) := (others => '0');
-signal testwordB0_S : std_logic_vector(35 downto 0) := (others => '0');
-
-signal selectnr_S : integer range 0 to 3 := 0;
-signal testclockDiv2_S : std_logic_vector(7 downto 0) := (others => '0');
-signal forced_reset_S : std_logic := '0';
-signal test_resetadc_s : std_logic := '0';\r
-signal testclocks_S : std_logic_vector(8 downto 0) := (others => '0');
-signal testclockDiv100_S : std_logic_vector(8 downto 0) := (others => '0');
-
-begin\r
--- GEO=0:this is FPGA1, GEO=1:this is FPGA2
--- S_CTRL=1 : FPGA1 controls PLL&JTAG
--- S_CTRL=0 : FPGA2 controls PLL&JTAG
-
--- T_CTRL1 T_CTRL2 PLL_controlled_by S_CTRL
--- 0 0 0 = FPGA2 0
--- 1 0 1 = FPGA1 1
--- 0 1 1 = FPGA1 1
--- 1 1 0 = FPGA2 0
-
-IcontrolPLL_S <= '1' when (GEO/=S_CTRL) else '0'; -- '1' when this FPGA controls the PLL
-
-coldstartprocess: process(ST_CLK_S)
-begin
- if rising_edge(ST_CLK_S) then
- if coldstart_counter_S/=x"ff" then
- coldstart_S <= '0';
- coldstart_counter_S <= coldstart_counter_S+1;
- else
- coldstart_S <= '1';
- end if;
- end if;
-end process;
-
-
-T_CTRL <= T_CTRL_S;
-T_CTRL_S <=
- coldstart_S when GEO='1' -- PLL_controlled_by FPGA2
- else '0' when PLLconfigured_S='0' -- PLL_controlled_by FPGA1 during booting
- else '1'; -- PLL_controlled_by FPGA2, but reference frequency from FPGA1
-PLLconfigured_S <= '1' when (PLL_booting_S='0') and (resetting_S='0') else '0';
-process(clock_ADCref_S)\r
-begin
- if rising_edge(clock_ADCref_S) then
- if GEO='0' then
- if T_CTRL_S=S_CTRL then
- if otherFPGAnotconfigured0_S='1' then
- otherFPGAnotconfigured_S <= '1';
- end if;
- otherFPGAnotconfigured0_S <= '1';
- else
- otherFPGAnotconfigured0_S <= '0';
- otherFPGAnotconfigured_S <= '0';
- end if;
- else
- otherFPGAnotconfigured0_S <= '0';
- otherFPGAnotconfigured_S <= '0';
- end if;
- end if;
-end process;
- \r
-sysclk_buf : IBUFGDS
- port map ( I => GCLK_P,
- IB => GCLK_N,
- O => GCLK_S);
-ST_CLK_buf : IBUFGDS
- port map ( I => ST_CLK_P,
- IB => ST_CLK_N,
- O => ST_CLK_S);\r
-\r
-clockmodule80Ma: clockmodule80M port map(
- CLK_IN1 => ST_CLK_S,
- CLK_OUT1 => clock80MHz_PLL1_S,
- LOCKED => clockPLL1_locked_S);\r
-clockmodule80to80Ma: clockmodule80to80M port map(
- CLK_IN1 => clock80MHz_PLL1_S,
- CLK_OUT1 => clock_ADCrefdiv2_S, -- 40MHz
- CLK_OUT2 => clock_ADCref_S, -- 80MHz
- CLK_OUT3 => clock100MHz_S,
- CLK_OUT4 => clock200MHz_S,\r
- RESET => clockPLL2_reset_S,
- LOCKED => clockmodule_locked_S);\r
-clockPLL2_reset_S <= '1' when clockPLL1_locked_S='0' else '0';\r
-
-\r
-reset_S <= '1' when (clockmodule_locked_S='0') or (forced_reset_S='1') else '0';\r
-resetprocess: process(clock_ADCref_S,reset_S,GEO)\r
-variable resetFEE_count_V : integer range 0 to 16 := 0;
-begin
- if reset_S='1' then
- reset_counter_S <= 0;
- boot_PLL_S <= '0';
- reset_GTX_S <= '1';\r
- resetting_S <= '1';\r
- rxLocked_sync_S <= '0';\r
- GEO_S <= GEO;\r
- resetFEE_count_V := 0;\r
- reset_FEE_S <= '1';
- disable_GTX_reset_S <= '0';\r
- elsif rising_edge(clock_ADCref_S) then\r
- rxLocked_sync_S <= rxLocked_S;\r
- if resetFEE_count_V<16 then\r
- resetFEE_count_V := resetFEE_count_V+1; \r
- reset_FEE_S <= '1';\r
- else\r
- reset_FEE_S <= '0';\r
- end if;\r
- GEO_S <= GEO;\r
- if GEO_S='0' then -- FPGA1\r
- if ((PLLfrequencyERROR_S='1') and (selectPLLclk_S='1')) or (otherFPGAnotconfigured_S='1') then -- restart all\r
- reset_counter_S <= 0;
- boot_PLL_S <= '0';
- reset_GTX_S <= '1';\r
- resetting_S <= '1';
- startupready_S <= '0';\r
- disable_GTX_reset_S <= '0';\r
- elsif reset_counter_S=1000 then -- start PLL boot
- reset_counter_S <= reset_counter_S+1;\r
- boot_PLL_S <= '1';\r
- timeout_counter_S <= 0;\r
- elsif reset_counter_S=1002 then -- wait for PLL boot finished\r
- boot_PLL_S <= '0';\r
- if PLL_booting_S='1' then\r
- if timeout_counter_S<65535 then\r
- timeout_counter_S <= timeout_counter_S+1;\r
- else\r
- timeout_counter_S <= 0;\r
- end if;
- else\r
- reset_counter_S <= reset_counter_S+1;
- timeout_counter_S <= 0;\r
- end if;\r
- elsif reset_counter_S=10000 then -- reset GTX\r
- resetting_S <= '0';\r
- reset_GTX_S <= '1';\r
- reset_counter_S <= reset_counter_S+1;
- elsif reset_counter_S=10001 then -- wait for rx-locked\r
- resetting_S <= '0';
- startupready_S <= '0';\r
- reset_GTX_S <= '0';\r
- if rxLocked_sync_S='1' then\r
- reset_counter_S <= reset_counter_S+1;
- end if;\r
- elsif reset_counter_S=11000 then -- disable resetting in GTX\r
- disable_GTX_reset_S <= '1';\r
- reset_counter_S <= reset_counter_S+1;\r
- elsif reset_counter_S=11010 then -- switch reference clock\r
- startupready_S <= '1';\r
- reset_counter_S <= reset_counter_S+1;\r
- elsif reset_counter_S=11080 then -- enable resetting in GTX\r
- disable_GTX_reset_S <= '0';\r
- reset_counter_S <= reset_counter_S+1;\r
- else\r
- if reset_counter_S/=65535 then
- reset_counter_S <= reset_counter_S+1;\r
- else -- final state\r
- resetting_S <= '0';
- startupready_S <= '1';\r
- end if;
- boot_PLL_S <= '0';
- reset_GTX_S <= '0';\r
- end if;\r
- else -- GEO=1\r
- disable_GTX_reset_S <= '0';\r
- if (S_CTRL0_S='1') or (otherFPGAnotconfigured_S='1') then\r
- reset_counter_S <= 0;
- boot_PLL_S <= '0';
- reset_GTX_S <= '1';\r
- resetting_S <= '1';
- startupready_S <= '0';\r
- elsif reset_counter_S=10000 then -- reset GTX
- resetting_S <= '0';
- reset_GTX_S <= '1';\r
- reset_counter_S <= reset_counter_S+1;
- elsif reset_counter_S=10001 then -- wait for rx-locked\r
- resetting_S <= '0';
- startupready_S <= '0';\r
- reset_GTX_S <= '0';\r
- if rxLocked_sync_S='1' then\r
- reset_counter_S <= reset_counter_S+1;
- end if;\r
- elsif reset_counter_S=11000 then -- switch reference clock\r
- startupready_S <= '1';\r
- reset_counter_S <= reset_counter_S+1;\r
- else\r
- if reset_counter_S/=65535 then
- reset_counter_S <= reset_counter_S+1;\r
- else\r
- resetting_S <= '0';
- startupready_S <= '1';\r
- end if;
- boot_PLL_S <= '0';
- reset_GTX_S <= '0';\r
- if startupready_S='1' then\r
- if rxLocked_sync_S='0' then \r
- end if;\r
- end if;\r
- end if;\r
- end if;
- S_CTRL0_S <= S_CTRL;
- end if;
-end process;\r
-\r
- -- ICAP_VIRTEX6: Internal Configuration Access Port
- -- Virtex-6
- -- Xilinx HDL Language Template, version 13.3
-
--- ICAP_VIRTEX6_inst : ICAP_VIRTEX6
--- generic map (
--- DEVICE_ID => X"4244093", -- Specifies the pre-programmed Device ID value
--- ICAP_WIDTH => "X8", -- Specifies the input and output data width to be used with the
--- -- ICAP_VIRTEX6.
--- SIM_CFG_FILE_NAME => "NONE" -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
--- -- model
--- )
--- port map (
--- BUSY => BUSY, -- 1-bit output: Busy/Ready output
--- O => O, -- 32-bit output: Configuration data output bus
--- CLK => CLK, -- 1-bit input: Clock Input
--- CSB => CSB, -- 1-bit input: Active-Low ICAP input Enable
--- I => I, -- 32-bit input: Configuration data input bus
--- RDWRB => RDWRB -- 1-bit input: Read/Write Select input
--- );
-\r
-resync_pulse1: posedge_to_pulse port map(\r
- clock_in => ST_CLK_S,\r
- clock_out => ST_CLK_S, -- clock_ADCref_S,\r
- en_clk => '1',\r
- signal_in => phaseSYNC_S,\r
- pulse => phaseSYNCpulse_S);\r
-\r
-syncpulse_proc: process(ST_CLK_S)
-variable synccount_V : integer range 0 to 15 := 0;\r
-begin
- if rising_edge(ST_CLK_S) then\r
- if synccount_V<15 then\r
- synccount_V := synccount_V+1;\r
- external_sync_out_S <= '1';\r
- else\r
- external_sync_out_S <= '0';\r
- if (phaseSYNCpulse_S='1') then\r
- synccount_V := 0;\r
- end if; \r
- end if;\r
- end if;\r
-end process;
-
-ADCresetprocess: process(clock_ADCref_S)
-variable adcreset_counter_V : integer range 0 to 65535 := 0;
-begin
- if rising_edge(clock_ADCref_S) then
- if (resetting_S='1') or ((PLL_booting_S='1') and (GEO_S='0')) or (startupready_S='0') or\r
- (test_resetADC_S='1') or (external_sync_out_S='1') or (external_sync_in_S='1') or\r
- ((phasecheck_ready1_S='0') and (GEO_S='0')) or\r
- ((rxLocked_sync_S='0') and (GEO_S='0'))\r
- then
- reset_ADCs_S <= '1';
- AdcIntrfcEna_S <= '0';
- adcreset_counter_V := 0;\r
- elsif adcreset_counter_V=65335 then -- wait for lock\r
- if rxLocked_sync_S='1' then\r
- adcreset_counter_V := adcreset_counter_V+1;
- reset_ADCs_S <= '0';
- end if;\r
- elsif adcreset_counter_V=65535 then
- reset_ADCs_S <= '0';
- AdcIntrfcEna_S <= '1';
- else
- adcreset_counter_V := adcreset_counter_V+1;
- end if;\r
- if GEO='1' then\r
- external_sync_in_S <= external_sync_in0_S;
- else\r
- external_sync_in_S <= '0';\r
- end if;\r
- if (SYNC0_S='0') or (external_sync_in_S='1') or (debug_sync_S='1') then\r
- SYNC1_S <= '1';\r
- else\r
- SYNC1_S <= '0';\r
- end if;
- phasecheck_ready1_S <= phasecheck_ready_S;\r
- end if;
-end process;
-\r
-\r
---syncbuf1: IOBUFDS\r
--- generic map (\r
--- IOSTANDARD => "BLVDS_25"\r
--- )
--- port map (
--- O => external_sync_in0_S, -- Buffer output
--- IO => INTCOMC1_P, -- Diff_p inout (connect directly to top-level port)
--- IOB => INTCOMC1_N, -- Diff_n inout (connect directly to top-level port)
--- I => external_sync_out_S, -- Buffer input
--- T => GEO -- 3-state enable input, high=input, low=output
--- );\r
---\r
---startsuperburst1: IOBUFDS\r
--- generic map (\r
--- IOSTANDARD => "BLVDS_25"\r
--- )
--- port map (
--- O => superburst_start0_S,
--- IO => INTCOMC2_P,
--- IOB => INTCOMC2_N,
--- I => superburst_startout_S,
--- T => GEO
--- );\r
-\r
-IOBUF1 : IOBUF port map (
- O => external_sync_in0_S, -- Buffer output
- IO => INTCOMC1_P, -- Buffer inout port (connect directly to top-level port)
- I => external_sync_out_S, -- Buffer input
- T => GEO -- 3-state enable input, high=input, low=output
- );\r
- \r
-IOBUF2 : IOBUF port map (
- O => superburst_start0_S, -- Buffer output
- IO => INTCOMC1_N, -- Buffer inout port (connect directly to top-level port)
- I => superburst_startout_S, -- Buffer input
- T => GEO -- 3-state enable input, high=input, low=output
- ); \r
- \r
-IOBUF3 : IOBUF port map (
- O => DataTaking_enabled_in_S, -- Buffer output
- IO => INTCOMC2_N, -- Buffer inout port (connect directly to top-level port)
- I => DataTaking_enabled_out_S, -- Buffer input
- T => GEO -- 3-state enable input, high=input, low=output
- ); \r
-\r
---INTCOMC1_P <= external_sync_out_S when GEO='0' else 'Z';\r
---external_sync_in0_S <= INTCOMC1_P;\r
---INTCOMC1_N <= superburst_startout_S when GEO='0' else 'Z';\r
---superburst_start0_S <= INTCOMC1_N;\r
---INTCOMC2_N <= DataTaking_enabled_out_S when GEO='0' else 'Z';\r
---DataTaking_enabled_in_S <= INTCOMC2_N;\r
-\r
-
-process(ADC_clk_S,startupready_S)\r
-variable enable_data_V : std_logic := '0';\r
-variable DataTaking_enabled_V : std_logic := '0';\r
-begin\r
- if (startupready_S='0') then\r
- enable_data_V := '0';\r
- enable_data_S <= '0';
- elsif (rising_edge(ADC_clk_S)) then\r
- enable_data_S <= DataTaking_enabled_V;\r
- DataTaking_enabled_V := DataTaking_enabled_in_S;\r
- end if;\r
-end process;\r
-\r
-process(ADC_clk_S)\r
-begin\r
- if (rising_edge(ADC_clk_S)) then\r
- superburst_start1_S <= superburst_start0_S;\r
- end if;\r
-end process;\r
-\r
-sync_startofsuperburst: posedge_to_pulse port map(\r
- clock_in => ADC_clk_S,\r
- clock_out => ADC_clk_S,\r
- en_clk => '1',\r
- signal_in => superburst_start1_S,\r
- pulse => superburst_start_S);\r
-\r
-INTCOM0_P <= superburst_out_S(0) when GEO='0' else 'Z';\r
-INTCOM0_N <= superburst_out_S(1) when GEO='0' else 'Z';\r
-INTCOM1_P <= superburst_out_S(2) when GEO='0' else 'Z';\r
-INTCOM1_N <= superburst_out_S(3) when GEO='0' else 'Z';\r
-INTCOM2_P <= superburst_out_S(4) when GEO='0' else 'Z';\r
-INTCOM2_N <= superburst_out_S(5) when GEO='0' else 'Z';\r
-INTCOM3_P <= superburst_out_S(6) when GEO='0' else 'Z';\r
-INTCOM3_N <= superburst_out_S(7) when GEO='0' else 'Z';\r
-INTCOM4_P <= superburst_out_S(8) when GEO='0' else 'Z';\r
-INTCOM4_N <= superburst_out_S(9) when GEO='0' else 'Z';\r
-INTCOM5_P <= superburst_out_S(10) when GEO='0' else 'Z';\r
-INTCOM5_N <= superburst_out_S(11) when GEO='0' else 'Z';\r
-INTCOM6_P <= superburst_out_S(12) when GEO='0' else 'Z';\r
-INTCOM6_N <= superburst_out_S(13) when GEO='0' else 'Z';\r
-INTCOM7_P <= superburst_out_S(14) when GEO='0' else 'Z';\r
-INTCOM7_N <= superburst_out_S(15) when GEO='0' else 'Z';\r
-\r
-superburst_in_S(0) <= INTCOM0_P;\r
-superburst_in_S(1) <= INTCOM0_N;\r
-superburst_in_S(2) <= INTCOM1_P;\r
-superburst_in_S(3) <= INTCOM1_N;\r
-superburst_in_S(4) <= INTCOM2_P;\r
-superburst_in_S(5) <= INTCOM2_N;\r
-superburst_in_S(6) <= INTCOM3_P;\r
-superburst_in_S(7) <= INTCOM3_N;\r
-superburst_in_S(8) <= INTCOM4_P;\r
-superburst_in_S(9) <= INTCOM4_N;\r
-superburst_in_S(10) <= INTCOM5_P;\r
-superburst_in_S(11) <= INTCOM5_N;\r
-superburst_in_S(12) <= INTCOM6_P;\r
-superburst_in_S(13) <= INTCOM6_N;\r
-superburst_in_S(14) <= INTCOM7_P;\r
-superburst_in_S(15) <= INTCOM7_N;\r
-superburst_in_S(30 downto 16) <= (others => '0');\r
- \r
-sync_SYNC_stclk_S: posedge_to_pulse port map(\r
- clock_in => clock_ADCref_S,\r
- clock_out => ST_CLK_S,\r
- en_clk => '1',\r
- signal_in => SYNC1_S,\r
- pulse => SYNC2_S);\r
-\r
-SYNC <= not SYNC2_S;\r
-\r
-\r
-process(rxSodaClk40_S)
-begin
- if (rising_edge(rxSodaClk40_S)) then
- rxSodaClkdiv4_S <= not rxSodaClkdiv4_S;
- end if;
-end process;\r
-process(GCLK_S)\r
-begin
- if (rising_edge(GCLK_S)) then\r
- if GCLKdiv2_S='1' then
- GCLKdiv4_S <= not GCLKdiv4_S;\r
- end if;
- GCLKdiv2_S <= not GCLKdiv2_S;\r
- end if;
-end process;\r
-phaseerr_max_S <= 50 when vioword_S(23 downto 16)=x"00" else conv_integer(unsigned(vioword_S(23 downto 16)));\r
-phasedet_S <= '1' when GCLKdiv4_S/=rxSodaClkdiv4_S else '0';\r
-process(ST_CLK_S)\r
-variable waitcounter_V : integer range 0 to 155520 := 0;\r
-begin
- if (rising_edge(ST_CLK_S)) then
- if (resetting_stclk_S='1') or (selectPLLclk_stclk_S='0') or (GEO_stclk_S='1') then\r
- waitcounter_V := 0;\r
- phasedet_count_S <= 0;\r
- phaseerr_count_S <= 0;\r
- phasecheckcounter_S <= 0;\r
- phaseSYNC_S <= '0';\r
- elsif (waitcounter_V<155520) then -- *(1+conv_integer(unsigned(vioword_S(27 downto 24))))) then\r
- waitcounter_V := waitcounter_V+1;\r
- phasedet_count_S <= 0;\r
- phaseerr_count_S <= 0;\r
- phasecheckcounter_S <= 0;\r
- phaseSYNC_S <= '0';\r
- elsif (waitcounter_V=155520) then -- always one syncpulse\r
- waitcounter_V := waitcounter_V+1;\r
- phasedet_count_S <= 0;\r
- phaseerr_count_S <= 0;\r
- phasecheckcounter_S <= 0;\r
- phaseSYNC_S <= '1';\r
- else\r
- if phasedet_count_S=1023 then\r
- if phasecheckcounter_S<255 then\r
- phasecheck_ready_S <= '0';
- phasecheckcounter_S <= phasecheckcounter_S+1;\r
- if (phaseerr_count_S>phaseerr_max_S) then\r
- if vioword_S(5)='0' then\r
- phaseSYNC_S <= '1';\r
- waitcounter_V := 0;\r
- else\r
- phaseSYNC_S <= '0';\r
- end if;\r
- else\r
- phaseSYNC_S <= '0';\r
- end if;
- else
- phasecheck_ready_S <= '1';\r
- if (phaseerr_count_S>200) then\r
--- if (phaseerr_count_S>400) then\r
- if vioword_S(5)='0' then\r
- phaseSYNC_S <= '1';\r
- waitcounter_V := 0;\r
- else\r
- phaseSYNC_S <= '0';\r
- end if;
- else\r
- phaseSYNC_S <= '0';\r
- end if;\r
- end if;\r
- phasedet_count_S <= 0;\r
- if phasedet_S='1' then\r
- phaseerr_count_S <= 1;\r
- else\r
- phaseerr_count_S <= 0;\r
- end if;\r
- else\r
- phaseSYNC_S <= '0';\r
- phasedet_count_S <= phasedet_count_S+1;\r
- if phasedet_S='1' then\r
- phaseerr_count_S <= phaseerr_count_S+1;\r
- end if;\r
- end if;\r
- end if;\r
- resetting_stclk_S <= resetting_S;
- selectPLLclk_stclk_S <= selectPLLclk_S;
- GEO_stclk_S <= GEO;
- end if;
-end process;\r
-
-
-gclk_div10_process: process(GCLK_S)
-variable counter_V : integer range 0 to 99 := 0;
-begin
- if (rising_edge(GCLK_S)) then
- if counter_V<49 then -- 99 for 125MHz
- counter_V := counter_V+1;
- else
- counter_V := 0;
- GCLKdiv10_S <= not GCLKdiv10_S;
- end if;
- end if;
-end process;
-checkfrequency_process: process(ST_CLK_S)
-variable counter_V : integer range 0 to 255 := 0;
-variable first_check_V : integer range 0 to 7 := 0;
-begin
- if (rising_edge(ST_CLK_S)) then
- if (resetting_stclk_S='1') or (selectPLLclk_stclk_S='0') or (GEO_stclk_S='1') then
- PLLfrequencyERROR_S <= '0';
- first_check_V := 0;
- else
- if GCLKdiv10_prev1_S/=GCLKdiv10_prev2_S then
- if (((counter_V>=122) or (counter_V<=125)) and (ADCCLOCKFREQUENCY=62500000)) or \r
- (((counter_V>=96) or (counter_V<=99)) and (ADCCLOCKFREQUENCY=80000000)) then \r
- PLLfrequencyERROR_S <= '0';
- if first_check_V/=7 then
- first_check_V := first_check_V+1;\r
- end if;\r
- else
- if first_check_V=7 then
- PLLfrequencyERROR_S <= '1';\r
- first_check_V := 0;\r
- else
- first_check_V := first_check_V+1;\r
- end if;
- end if;
- counter_V := 0;
- elsif counter_V<255 then
- counter_V := counter_V+1;
- end if;
- end if;
- GCLKdiv10_prev2_S <= GCLKdiv10_prev1_S;
- GCLKdiv10_prev1_S <= GCLKdiv10_S;
- end if;
-end process;
-\r
-external_PLL: LMK03806 port map(
- clock => clock_ADCref_S,
- CLKu => CLKu_S,
- DATAu => DATAu_S,
- LEu => LEu_S,
- RDn => RDu,
- SYNC => SYNC0_S,
- boot_PLL => boot_PLL_S,
- reset_GTX => open, -- reset_GTX_S,
- reset_ADCs => open, -- reset_ADCs0_S,
- booting => PLL_booting_S,\r
- testwordin => vioword2_S(15 downto 0));
-CLKu <= CLKu_S;
-DATAu <= DATAu_S;
-LEu <= LEu_S;\r
-\r
--- ADC configuration --------------------------------------------------------------\r
- SCK <= '0'; -- 2-lane 16-bits serialization\r
- SDI <= '0'; -- normal mode (not sleeping)\r
- CSA <= (others => '0'); -- 2-lane 16-bits serialization\r
- CSB <= (others => '0'); -- 2-lane 16-bits serialization\r
- SDOA <= (others => '0'); -- no internal termination\r
- SDOB <= (others => '0'); -- no internal termination\r
-\r
-\r
-
-GTX_refclock: IBUFDS_GTXE1 port map(
- O => gtpClk_S,
- ODIV2 => open,
- CEB => '0',
- I => MGTREFCLK_P,
- IB => MGTREFCLK_N);
-
---select_RCV_CLK : BUFGMUX_CTRL port map(
--- O => RCV_CLK_S,
--- I0 => clock_ADCref_S,
--- I1 => rxSodaClk80_S,
--- S => selectPLLclk_S); ---- rxLocked_S);\r
---RCV_CLK_S <= clock_ADCref_S; \r
-process (clock_ADCref_S)\r
-begin
- if (rising_edge(clock_ADCref_S)) then \r
- if vioword_S(11)='0' then\r
- if (startupready_S='1') and (rxLocked_S='1') then
- selectPLLclk_S <= '1';\r
- else \r
- selectPLLclk_S <= '0';\r
- end if;\r
- else\r
- selectPLLclk_S <= vioword_S(10); --//\r
- end if;\r
- end if;
-end process;\r
-
---rxRecClk40_BUFG: BUFG port map(
--- I => rxSodaClk40_S,
--- O => rxSodaClk40b_S);
---clockmodule40to80_1: clockmodule40to80 port map(\r
--- CLK_IN1 => rxSodaClk40b_S,\r
--- CLK_OUT1 => rxSodaClk80_S,\r
--- LOCKED => open);\r
-\r
-clockmodule40switch1: clockmodule40switch port map(\r
- CLK_IN1 => rxSodaClk40_S,\r
- CLK_IN2 => clock_ADCrefdiv2_S,\r
- CLK_IN_SEL => selectPLLclk_S,\r
- CLK_OUT1 => RCV_CLK_S,\r
- CLK_OUT2 => open,\r
- RESET => '0',\r
- LOCKED => clockswitch_locked_S);\r
-\r
---process (clock_ADCref_S)\r
---begin
--- if (rising_edge(clock_ADCref_S)) then
--- RCV_CLKref_S <= not RCV_CLKref_S;\r
--- end if;\r
---end process;\r
---process (rxSodaClk80_S)\r
---begin
--- if (rising_edge(rxSodaClk80_S)) then
--- RCV_CLKrx_S <= not RCV_CLKrx_S;\r
--- end if;
---end process;\r
---RCV_CLK_S <= RCV_CLKrx_S when selectPLLclk_S='1' else RCV_CLKref_S; \r
---\r
---U2 : OBUFDS port map( -- OBUFDS_LVDSEXT_33
--- I => RCV_CLK_S,
--- O => RCV_CLK_P,
--- OB => RCV_CLK_N);\r
- \r
-
-RCV_CLK_not_S <= not RCV_CLK_S;
-U1 : FDDRRSE port map(\r
- Q => RCV_CLK_P_S,
- C0 => RCV_CLK_S,
- C1 => RCV_CLK_not_S,
- CE => '1', -- 1 for fpga1 not GEO, --
- D0 => '1', -- 1 for fpga1 not GEO, --
- D1 => '0',
- R => '0',
- S => '0');
-U2 : OBUFDS port map( -- OBUFDS_LVDSEXT_33
- I => RCV_CLK_P_S,
- O => RCV_CLK_P,
- OB => RCV_CLK_N);\r
- \r
-\r
-\r
-LOS_S <= '1' when (LOS='1') or (MOD_DEF(0)='1') else '0';
-TX_DIS <= '0'; -- SFP always enabled
-\r
-process(ADC_clk_S) -- synchronise to 1 clock
-begin
- if (rising_edge(ADC_clk_S)) then
- reset_FEE_ADCclk_S <= reset_FEE_S;
- ADCs_enable_S <= AdcIntrfcEna_S;\r
- end if;
-end process;\r
-\r
-FEE_ADCinput_module1: FEE_ADCinput_module port map(
- clock200MHz => clock200MHz_S,
- reset => reset_ADCs_S,
- ADCs_enable => ADCs_enable_S,
-----ADC1---------------------------------------------
- AD11A_P => AD11A_P,
- AD11A_N => AD11A_N,
- AD11B_P => AD11B_P,
- AD11B_N => AD11B_N,
- AD12A_P => AD12A_P,
- AD12A_N => AD12A_N,
- AD12B_P => AD12B_P,
- AD12B_N => AD12B_N,
- AD13A_P => AD13A_P,
- AD13A_N => AD13A_N,
- AD13B_P => AD13B_P,
- AD13B_N => AD13B_N,
- AD14A_P => AD14A_P,
- AD14A_N => AD14A_N,
- AD14B_P => AD14B_P,
- AD14B_N => AD14B_N,
- AD15A_P => AD15A_P,
- AD15A_N => AD15A_N,
- AD15B_P => AD15B_P,
- AD15B_N => AD15B_N,
- AD16A_P => AD16A_P,
- AD16A_N => AD16A_N,
- AD16B_P => AD16B_P,
- AD16B_N => AD16B_N,
- AD17A_P => AD17A_P,
- AD17A_N => AD17A_N,
- AD17B_P => AD17B_P,
- AD17B_N => AD17B_N,
- AD18A_P => AD18A_P,
- AD18A_N => AD18A_N,
- AD18B_P => AD18B_P,
- AD18B_N => AD18B_N,
-
- DCOA1_P => DCOA1_P,
- DCOA1_N => DCOA1_N,
- DCOB1_P => DCOB1_P,
- DCOB1_N => DCOB1_N,
-
- FRA1_P => FRA1_P ,
- FRA1_N => FRA1_N ,
- FRB1_P => FRB1_P ,
- FRB1_N => FRB1_N ,
-
- ----ADC2---------------------------------------------
- AD21A_P => AD21A_P,
- AD21A_N => AD21A_N,
- AD21B_P => AD21B_P,
- AD21B_N => AD21B_N,
- AD22A_P => AD22A_P,
- AD22A_N => AD22A_N,
- AD22B_P => AD22B_P,
- AD22B_N => AD22B_N,
- AD23A_P => AD23A_P,
- AD23A_N => AD23A_N,
- AD23B_P => AD23B_P,
- AD23B_N => AD23B_N,
- AD24A_P => AD24A_P,
- AD24A_N => AD24A_N,
- AD24B_P => AD24B_P,
- AD24B_N => AD24B_N,
- AD25A_P => AD25A_P,
- AD25A_N => AD25A_N,
- AD25B_P => AD25B_P,
- AD25B_N => AD25B_N,
- AD26A_P => AD26A_P,
- AD26A_N => AD26A_N,
- AD26B_P => AD26B_P,
- AD26B_N => AD26B_N,
- AD27A_P => AD27A_P,
- AD27A_N => AD27A_N,
- AD27B_P => AD27B_P,
- AD27B_N => AD27B_N,
- AD28A_P => AD28A_P,
- AD28A_N => AD28A_N,
- AD28B_P => AD28B_P,
- AD28B_N => AD28B_N,
-
- DCOA2_P => DCOA2_P,
- DCOA2_N => DCOA2_N,
- DCOB2_P => DCOB2_P,
- DCOB2_N => DCOB2_N,
-
- FRA2_P => FRA2_P ,
- FRA2_N => FRA2_N ,
- FRB2_P => FRB2_P ,
- FRB2_N => FRB2_N ,
-
- ----ADC3---------------------------------------------
- AD31A_P => AD31A_P,
- AD31A_N => AD31A_N,
- AD31B_P => AD31B_P,
- AD31B_N => AD31B_N,
- AD32A_P => AD32A_P,
- AD32A_N => AD32A_N,
- AD32B_P => AD32B_P,
- AD32B_N => AD32B_N,
- AD33A_P => AD33A_P,
- AD33A_N => AD33A_N,
- AD33B_P => AD33B_P,
- AD33B_N => AD33B_N,
- AD34A_P => AD34A_P,
- AD34A_N => AD34A_N,
- AD34B_P => AD34B_P,
- AD34B_N => AD34B_N,
- AD35A_P => AD35A_P,
- AD35A_N => AD35A_N,
- AD35B_P => AD35B_P,
- AD35B_N => AD35B_N,
- AD36A_P => AD36A_P,
- AD36A_N => AD36A_N,
- AD36B_P => AD36B_P,
- AD36B_N => AD36B_N,
- AD37A_P => AD37A_P,
- AD37A_N => AD37A_N,
- AD37B_P => AD37B_P,
- AD37B_N => AD37B_N,
- AD38A_P => AD38A_P,
- AD38A_N => AD38A_N,
- AD38B_P => AD38B_P,
- AD38B_N => AD38B_N,
-
- DCOA3_P => DCOA3_P,
- DCOA3_N => DCOA3_N,
- DCOB3_P => DCOB3_P,
- DCOB3_N => DCOB3_N,
-
- FRA3_P => FRA3_P ,
- FRA3_N => FRA3_N ,
- FRB3_P => FRB3_P ,
- FRB3_N => FRB3_N ,
-
- ----ADC4---------------------------------------------
- AD41A_P => AD41A_P,
- AD41A_N => AD41A_N,
- AD41B_P => AD41B_P,
- AD41B_N => AD41B_N,
- AD42A_P => AD42A_P,
- AD42A_N => AD42A_N,
- AD42B_P => AD42B_P,
- AD42B_N => AD42B_N,
- AD43A_P => AD43A_P,
- AD43A_N => AD43A_N,
- AD43B_P => AD43B_P,
- AD43B_N => AD43B_N,
- AD44A_P => AD44A_P,
- AD44A_N => AD44A_N,
- AD44B_P => AD44B_P,
- AD44B_N => AD44B_N,
- AD45A_P => AD45A_P,
- AD45A_N => AD45A_N,
- AD45B_P => AD45B_P,
- AD45B_N => AD45B_N,
- AD46A_P => AD46A_P,
- AD46A_N => AD46A_N,
- AD46B_P => AD46B_P,
- AD46B_N => AD46B_N,
- AD47A_P => AD47A_P,
- AD47A_N => AD47A_N,
- AD47B_P => AD47B_P,
- AD47B_N => AD47B_N,
- AD48A_P => AD48A_P,
- AD48A_N => AD48A_N,
- AD48B_P => AD48B_P,
- AD48B_N => AD48B_N,
-
- DCOA4_P => DCOA4_P,
- DCOA4_N => DCOA4_N,
- DCOB4_P => DCOB4_P,
- DCOB4_N => DCOB4_N,
-
- FRA4_P => FRA4_P ,
- FRA4_N => FRA4_N ,
- FRB4_P => FRB4_P ,
- FRB4_N => FRB4_N ,
-
- ADC_clk => ADC_clk_S,
- ADCs_ready => ADCs_ready_S,\r
- adcdata => adcdata_S
- );
-\r
-gen_FEE: if DEBUG=false generate\r
-FEE_module1: FEE_adc32_module port map(
- clock => ADC_clk_S,
- reset => reset_FEE_ADCclk_S,
- enable_data => enable_data_S,
- ADCdata => adcdata_S,
- superburst_start => superburst_start_S,
- superburst_received => superburst_in_S,\r
- onesecondpulse => onesecondpulse_S,
- rxNotInTable => rxNotInTable_S,
- startupready => startupready_S,
- request_init => request_init_S,
- packet_in_data => packet_in_data_S,
- packet_in_present => packet_in_present_S,
- packet_in_read => packet_in_read_S,
- packet_out_data => packet_out_data_S,
- packet_out_last => packet_out_last_S,
- packet_out_write => packet_out_write_S,
- packet_out_fifofull => packet_out_fifofull_S,\r
- errorbyte_out => errorbyte_S,\r
- errorbyte_in => errorbyte_S,\r
- smaart_in => '0', -- TEMP_OUT,
- smaart_out => open,\r
- sysmon_data => sysmon_data_S,\r
- sysmon_reset => sysmon_reset_S,\r
- sysmon_address => sysmon_address_S,\r
- sysmon_read => sysmon_read_S,\r
- testindex => conv_integer(unsigned(vioword_S(15 downto 12))),\r
- testword0 => open,
- testword1 => open,
- testword2 => open
- ); -- TEMP_IN);
-end generate;\r
-
-gen_second_FE_module: if SECOND_FE_MODULE=TRUE generate
-
-\r
- FEE_module2: FEE_adc32_module port map(
- clock => ADC_clk_S,
- reset => reset_FEE_ADCclk2_S,
- enable_data => enable_data_S,
- ADCdata => adcdata2_S,
- superburst_start => superburst_start_S,
- superburst_received => superburst_in_S,
- onesecondpulse => onesecondpulse_S,
- rxNotInTable => rxNotInTable_S,
- startupready => startupready_S,
- request_init => request_init_S,
- packet_in_data => packet_in_data_S,
- packet_in_present => packet_in_present_S,
- packet_in_read => packet_in_read2_S,
- packet_out_data => packet_out_data2_S,
- packet_out_last => packet_out_last2_S,
- packet_out_write => packet_out_write2_S,
- packet_out_fifofull => packet_out_fifofull_S,\r
- errorbyte_out => open,\r
- errorbyte_in => errorbyte_S,\r
- smaart_in => '0', -- TEMP_OUT,
- smaart_out => open,\r
- sysmon_data => sysmon_data_S,\r
- sysmon_reset => open,\r
- sysmon_address => open,\r
- sysmon_read => open,\r
- testindex => conv_integer(unsigned(vioword_S(15 downto 12))),\r
- testword0 => open,
- testword1 => testword0b_S, -- testword0_S,
- testword2 => open
- ); -- TEMP_IN);
-\r
- reset_FEE_ADCclk2_S <= '1' when (reset_FEE_ADCclk_S='1') or (reset_FEE_ADCclk2a_S='1') else '0';\r
- zero_data_S <= '1' when (vioword_S(9)='1') else '0';\r
- adcdata2_S <= adcdata_S when zero_data_S='0' else (others => (others => '0'));
-\r
- process(ADC_clk_S)
- begin
- if (rising_edge(ADC_clk_S)) then
- unequal_S <= '0';\r
- request_init_S <= '0';
- if (zero_data_S='1') or (reset_FEE_ADCclk_S='1') or (vioword_S(8)='1') then\r
- unequal_counter_S <= (others => '0');\r
- reset_FEE_ADCclk2a_S <= '1';\r
- unequal_time_S <= (others => '0');\r
- else
- if unequal_counter_S(31 downto 0)=x"0000000f" then
- reset_FEE_ADCclk2a_S <= '0';\r
- end if;\r
- if unequal_counter_S=x"000000ff" then
- request_init_S <= '1';
- end if;\r
- if (packet_in_read2_S/=packet_in_read_S) or \r
- (packet_out_data2_S/=packet_out_data_S) or \r
- (packet_out_last2_S/=packet_out_last_S) or \r
- (packet_out_write2_S/=packet_out_write_S) then\r
- unequal_time_S <= unequal_counter_S;\r
- unequal_S <= '1';\r
- end if;\r
- if unequal_counter_S/=x"ffffffff" then\r
- unequal_counter_S <= unequal_counter_S+1;\r
- end if;\r
- end if;
- end if;
- end process;\r
-
-end generate;\r
-\r
-process(ADC_clk_S)\r
-variable counter : integer range 0 to ADCCLOCKFREQUENCY-1 := 0;
-begin
- if (rising_edge(ADC_clk_S)) then \r
- if counter/=0 then\r
- counter := counter-1;\r
- onesecondpulse_S <= '0';\r
- else\r
- counter := ADCCLOCKFREQUENCY-1;\r
- onesecondpulse_S <= '1';\r
- end if;\r
- end if;\r
-end process;\r
-
-FEE_gtxModule1: FEE_gtxModule port map(
- gtpClk => gtpClk_S,
- asyncclk => clock_ADCref_S,\r
- reset => reset_GTX_S,\r
- disable_GTX_reset => disable_GTX_reset_S,
- TX_DLM => TX_DLM_S,
- TX_DLM_WORD => TX_DLM_WORD_S,
- RX_DLM => RX_DLM_S,
- RX_DLM_WORD => RX_DLM_WORD_S,
- txAsyncClk => ADC_clk_S,
- txAsyncData => packet_out_data_S,
- txAsyncDataWrite => packet_out_write_S,
- txAsyncLastData => packet_out_last_S,
- txAsyncFifoFull => packet_out_fifofull_S,
- txUsrClk => txUsrClk_S,\r
- txLocked => open,
- rxAsyncClk => ADC_clk_S,
- rxAsyncData => packet_in_data_S,
- rxAsyncDataRead => packet_in_read_S,
- rxNotInTable => rxNotInTable0_S,
- rxAsyncDataOverflow => open,
- rxAsyncDataPresent => packet_in_present_S,
- rxSodaClk => rxSodaClk_S,
- rxSodaClk40 => rxSodaClk40_S,
- rxLocked => rxLocked0_S,
- gtpTxP0 => TX_P,
- gtpTxN0 => TX_N,
- gtpRxP0 => RX_P,
- gtpRxN0 => RX_N,
- testword0 => testwordb_S -- testword0(35 downto 0)\r
- );
-\r
-posedge_to_pulse_notintable: posedge_to_pulse port map(
- clock_in => rxSodaClk_S,
- clock_out => ADC_clk_S,
- en_clk => '1',
- signal_in => rxNotInTable0_S,
- pulse => rxNotInTable_S);\r
-\r
-rxLocked_S <= '1' when ((rxLocked0_S='1') or (disable_GTX_reset_S='1')) and (LOS_S='0') else '0';
-\r
-\r
-datatakingprocess: process(rxSodaClk_S)
-begin
- if (rising_edge(rxSodaClk_S)) then
- if DisableDataTaking_S='1' then
- DataTaking_enabled_out_S <= '0';
- elsif EnableDataTaking_S='1' then
- DataTaking_enabled_out_S <= '1';
- end if;
- end if;
-end process;
-\r
-\r
-process(rxSodaClk_S)\r
-begin\r
- if (rising_edge(rxSodaClk_S)) then\r
- reset_rxSodaClk_S <= reset_S;\r
- end if;\r
-end process;\r
-\r
- \r
-posedge_to_pulse_superburst_startout: posedge_to_pulse port map(
- clock_in => rxSodaClk_S,
- clock_out => ADC_clk_S,
- en_clk => '1',
- signal_in => superburst_startout0_S,
- pulse => superburst_startout_S);\r
-
-soda_FEE_endpoint1: soda_FEE_endpoint port map(
- SYSCLK => rxSodaClk_S,
- RESET => reset_rxSodaClk_S,
- CLEAR => '0',
- CLK_EN => '1',
- RX_DLM_WORD_IN => RX_DLM_WORD_S,
- RX_DLM_IN => RX_DLM_S,
- TX_DLM_OUT => TX_DLM_S,
- TX_DLM_WORD_OUT => TX_DLM_WORD_S,
- START_OF_SUPERBURST => superburst_startout0_S,
- SUPER_BURST_NR => superburst_out_S,
- SODA_CMD_VALID => SODA_cmd_valid_S,
- SODA_CMD_WORD => SODA_cmd_word_S,
- STAT => open);
---ResetToZero_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(30)='1') else '0'; -- reset timestamp to I/O pin\r
-EnableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(29)='1') else '0';\r
-DisableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(28)='1') else '0';\r
-\r
-SystemMonitorModule1: SystemMonitorModule port map(
- clock => ADC_clk_S,
- reset => sysmon_reset_S,
- address => sysmon_address_S,
- data_write => '0',
- data_in => (others => '0'),
- data_read => sysmon_read_S,
- data_out => sysmon_data_S,
- alarms => open,
- testword0 => open);\r
-\r
-\r
-icon1: icon0 port map(
- CONTROL0 => control0_S,
- CONTROL1 => control1_S,
- CONTROL2 => control2_S,
- CONTROL3 => control3_S,
- CONTROL4 => control4_S);
-
-ila36_1: ila36 port map(
- CONTROL => control0_S,
- CLK => txUsrClk_S, -- ADC_clk_S, -- ST_CLK_S,
- TRIG0 => testword1_S); -- testword0_S
-\r
-ila36_2: ila36 port map(
- CONTROL => control1_S,
- CLK => rxSodaClk_S, -- clock_ADCref_S, -- ADC_clk_S, ,clock_ADCref_S
- TRIG0 => testword1_S);\r
-
-ila128_1: ila128 port map(
- CONTROL => control2_S,
- CLK => clock_ADCref_S, -- ADC_clk_S,
- TRIG0 => testword2_S); -- (others => '0')); --
-\r
-vio36_1: vio36 port map (\r
- CONTROL => control3_S,
- ASYNC_OUT => vioword_S);\r
-
-vio36_2: vio36 port map (\r
- CONTROL => control4_S,
- ASYNC_OUT => vioword2_S);\r
-
---testword0_S(31 downto 0) <= unequal_time_S;\r
---testword0_S(32) <= reset_FEE_ADCclk2_S;\r
---testword0_S(33) <= zero_data_S;\r
---testword0_S(34) <= unequal_S;\r
---testword0_S(35) <= '1' when unequal_counter_S=x"ffffffff" else '0';\r
-\r
--- testword0_S <= testword0a_S when vioword_S(10)='0' else testword0b_S;\r
-\r
-testclocks_S(0) <= clock_ADCref_S;\r
-testclocks_S(1) <= clock_ADCrefdiv2_S;\r
-testclocks_S(2) <= clock100MHz_S;\r
-testclocks_S(3) <= clock200MHz_S;\r
-testclocks_S(4) <= RCV_CLK_S;\r
-testclocks_S(5) <= GCLK_S;\r
-testclocks_S(6) <= rxSodaClk_S;
-testclocks_S(7) <= rxSodaClk40_S;
-testclocks_S(8) <= ADC_clk_S;\r
-gen_testclocks: for i in 0 to 8 generate\r
-process(testclocks_S(i))
-variable cnt_V : integer range 0 to 99 := 0;
-begin
- if (rising_edge(testclocks_S(i))) then
- if cnt_V<99 then
- cnt_V := cnt_V+1;
- else
- cnt_V := 0;
- testclockDiv100_S(i) <= not testclockDiv100_S(i);
- end if;
- end if;
-end process;
-end generate;\r
---testword0_S(8 downto 0) <= testclockDiv100_S;\r
---testword0_S(9) <= LOS_S;\r
---testword0_S(10) <= rxLocked_S;\r
---testword0_S(11) <= rxLocked0_S;\r
---testword0_S(12) <= rxLocked_sync_S;\r
---testword0_S(13) <= selectPLLclk_S;\r
---testword0_S(14) <= rxLocked_S;\r
---testword0_S(23 downto 16) <= RX_DLM_WORD_S;\r
---testword0_S(24) <= RX_DLM_S;\r
---testword0_S(32 downto 25) <= TX_DLM_WORD_S;\r
---testword0_S(33) <= TX_DLM_S;\r
---testword0_S(34) <= superburst_startout_S;\r
---testword0_S(35) <= SODA_cmd_valid_S;\r
-\r
-testword0_S(15 downto 0) <= superburst_out_S(15 downto 0);\r
-testword0_S(31 downto 16) <= superburst_in_S(15 downto 0);
-testword0_S(32) <= superburst_startout_S;\r
-testword0_S(33) <= superburst_start0_S;\r
-testword0_S(34) <= superburst_start1_S;\r
-testword0_S(35) <= superburst_start_S;\r
-\r
-\r
---testword2_S(31 downto 0) <= unequal_time_S;\r
---testword2_S(32) <= reset_FEE_ADCclk2_S;\r
---testword2_S(33) <= zero_data_S;\r
---testword2_S(34) <= unequal_S;\r
---testword2_S(35) <= '1' when unequal_counter_S=x"ffffffff" else '0';\r
---testword2_S(67 downto 36) <= packet_out_data_S;\r
---testword2_S(68) <= packet_out_write_S;\r
---testword2_S(69) <= packet_out_last_S;\r
---testword2_S(70) <= packet_out_fifofull_S;\r
---testword2_S(71) <= '0';\r
---testword2_S(103 downto 72) <= packet_out_data2_S;\r
---testword2_S(104) <= packet_out_write2_S;\r
---testword2_S(105) <= packet_out_last2_S;\r
---testword2_S(106) <= packet_out_fifofull_S;\r
---testword2_S(107) <= '0';\r
-\r
-testword1_S(30 downto 0) <= testwordb_S(30 downto 0); \r
-testword1_S(31) <= errorbyte_S(0); \r
-testword1_S(32) <= errorbyte_S(1); \r
-testword1_S(33) <= errorbyte_S(2); \r
-testword1_S(34) <= errorbyte_S(4); \r
-testword1_S(35) <= errorbyte_S(6); \r
-\r
-testword2_S(0) <= rxLocked_sync_S; -- coldstart_S;\r
-testword2_S(1) <= reset_S;\r
-testword2_S(2) <= resetting_S;\r
-testword2_S(3) <= reset_GTX_S; -- IcontrolPLL_S;\r
-testword2_S(4) <= reset_ADCs_S; -- otherFPGAnotconfigured0_S;\r
-testword2_S(5) <= otherFPGAnotconfigured_S;\r
-testword2_S(6) <= PLLconfigured_S;\r
-testword2_S(7) <= selectPLLclk_S;\r
-testword2_S(8) <= startupready_S; -- T_CTRL_S;\r
-testword2_S(9) <= external_sync_in_S; \r
-testword2_S(10) <= rxLocked_S;\r
-testword2_S(11) <= S_CTRL0_S;\r
-testword2_S(12) <= boot_PLL_S;\r
-testword2_S(13) <= PLL_booting_S;\r
-testword2_S(14) <= adcintrfcena_s;\r
-testword2_S(15) <= phasecheck_ready1_S;\r
-testword2_S(16) <= GCLKdiv4_S; --reset_GTX_S;\r
-testword2_S(17) <= rxSodaClkdiv4_S; --ADCs_ready_S;\r
-testword2_S(18) <= '1' when phasedet_count_S=1023 else '0'; --GEO;\r
-testword2_S(19) <= '1' when phasecheckcounter_S<255 else '0'; -- PLLfrequencyERROR_S;\r
-testword2_S(20) <= SYNC_S;\r
-testword2_S(21) <= PLLfrequencyERROR_S;\r
-testword2_S(22) <= phasedet_S;\r
-testword2_S(23) <= phaseSYNC_S;\r
-testword2_S(24) <= clockswitch_locked_S;\r
-testword2_S(25) <= phaseSYNCpulse_S;\r
-testword2_S(35 downto 26) <= conv_std_logic_vector(phaseerr_count_S,10);
-\r
-selectnr_S <= conv_integer(vioword_S(35 downto 34));\r
-
-generatetest1 : for index in 0 to 7 generate
--- testword2_S(index*16+13 downto index*16+0) <= adcdata_S(selectnr_S*8+index)(13 downto 0);
--- testword2_S(index*16+15 downto index*16+14) <= (others => '0');
-end generate;
-
-forced_reset_S <= vioword_S(0);
-\r
-process(clock_ADCref_S)
-variable prev_vioword2 : std_logic := '0';
-variable prev_vioword3 : std_logic := '0';
-begin
- if (rising_edge(clock_ADCref_S)) then
- if prev_vioword2 /= vioword_S(2) then
- test_resetADC_S <= '1';
- else
- test_resetADC_S <= '0';
- end if;
- prev_vioword2 := vioword_S(2);
- if prev_vioword3 /= vioword_S(3) then
- debug_sync_S <= '1';
- else
- debug_sync_S <= '0';
- end if;
- prev_vioword3 := vioword_S(3);
- end if;
-end process;\r
-\r
-process(ST_CLK_S)
-begin
- if (rising_edge(ST_CLK_S)) then
- testclockDiv2_S(0) <= not testclockDiv2_S(0);
- end if;
-end process;\r
-process(clock_ADCref_S)
-begin
- if (rising_edge(clock_ADCref_S)) then
- testclockDiv2_S(1) <= not testclockDiv2_S(1);
- end if;
-end process;\r
-process(clock_ADCrefdiv2_S)
-begin
- if (rising_edge(clock_ADCrefdiv2_S)) then
- testclockDiv2_S(2) <= not testclockDiv2_S(2);
- end if;
-end process;\r
-process(RCV_CLK_S)
-begin
- if (rising_edge(RCV_CLK_S)) then
- testclockDiv2_S(3) <= not testclockDiv2_S(3);
- end if;
-end process;
-process(GCLK_S)
-begin
- if (rising_edge(GCLK_S)) then
- testclockDiv2_S(4) <= not testclockDiv2_S(4);
- end if;
-end process;\r
-process(rxSodaClk_S)
-begin
- if (rising_edge(rxSodaClk_S)) then
- testclockDiv2_S(5) <= not testclockDiv2_S(5);
- end if;
-end process;
-process(txUsrClk_S)
-begin
- if (rising_edge(txUsrClk_S)) then
- testclockDiv2_S(6) <= not testclockDiv2_S(6);
- end if;
-end process;\r
-process(ADC_clk_S)
-begin
- if (rising_edge(ADC_clk_S)) then
- testclockDiv2_S(7) <= not testclockDiv2_S(7);
- end if;
-end process;\r
-
-
-SM1_P <= testclockDiv2_S(conv_integer(unsigned(vioword_S(32 downto 30))));
-SM1_N <= testclockDiv2_S(conv_integer(unsigned(vioword_S(32 downto 30))));\r
-
---SM3_P <= '0'; -- testclockDiv2_S(conv_integer(unsigned(vioword_S(31 downto 30))));
---SM3_N <= '0'; -- testclockDiv2_S(conv_integer(unsigned(vioword_S(31 downto 30))));\r
-\r
-\r
-end Behavioral;
-
+++ /dev/null
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 FEE_clockbuf80MHz
-RECTANGLE Normal 32 32 576 1088
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk_in1
-PINATTR Polarity IN
-LINE Normal 608 80 576 80
-PIN 608 80 RIGHT 36
-PINATTR PinName clk_out1
-PINATTR Polarity OUT
-LINE Normal 608 176 576 176
-PIN 608 176 RIGHT 36
-PINATTR PinName clk_out2
-PINATTR Polarity OUT
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
-\r
- <!-- -->\r
-\r
- <!-- For tool use only. Do not edit. -->\r
-\r
- <!-- -->\r
-\r
- <!-- ProjectNavigator created generated project file. -->\r
-\r
- <!-- For use in tracking generated file and other information -->\r
-\r
- <!-- allowing preservation of process status. -->\r
-\r
- <!-- -->\r
-\r
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
-\r
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
-\r
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FEE_clockbuf80MHz.xise"/>\r
-\r
- <files xmlns="http://www.xilinx.com/XMLSchema">\r
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="FEE_clockbuf80MHz.asy" xil_pn:origination="imported"/>\r
- <file xil_pn:fileType="FILE_VHO" xil_pn:name="FEE_clockbuf80MHz.vho" xil_pn:origination="imported"/>\r
- </files>\r
-\r
- <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
- <transform xil_pn:end_ts="1411996303" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1411996303">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2931233228134520341" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3005896570206739925" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9209316580054018149" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- </transforms>\r
-\r
-</generated_project>\r
+++ /dev/null
-# file: FEE_clockbuf80MHz.ucf\r
-# \r
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
-# \r
-# This file contains confidential and proprietary information\r
-# of Xilinx, Inc. and is protected under U.S. and\r
-# international copyright and other intellectual property\r
-# laws.\r
-# \r
-# DISCLAIMER\r
-# This disclaimer is not a license and does not grant any\r
-# rights to the materials distributed herewith. Except as\r
-# otherwise provided in a valid license issued to you by\r
-# Xilinx, and to the maximum extent permitted by applicable\r
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-# (2) Xilinx shall not be liable (whether in contract or tort,\r
-# including negligence, or under any other theory of\r
-# liability) for any loss or damage of any kind or nature\r
-# related to, arising under or in connection with these\r
-# materials, including for any direct, or any indirect,\r
-# special, incidental, or consequential loss or damage\r
-# (including loss of data, profits, goodwill, or any type of\r
-# loss or damage suffered as a result of any action brought\r
-# by a third party) even if such damage or loss was\r
-# reasonably foreseeable or Xilinx had been advised of the\r
-# possibility of the same.\r
-# \r
-# CRITICAL APPLICATIONS\r
-# Xilinx products are not designed or intended to be fail-\r
-# safe, or for use in any application requiring fail-safe\r
-# performance, such as life-support or safety devices or\r
-# systems, Class III medical devices, nuclear facilities,\r
-# applications related to the deployment of airbags, or any\r
-# other applications that could lead to death, personal\r
-# injury, or severe property or environmental damage\r
-# (individually and collectively, "Critical\r
-# Applications"). Customer assumes the sole risk and\r
-# liability of any use of Xilinx products in Critical\r
-# Applications, subject only to applicable laws and\r
-# regulations governing limitations on product liability.\r
-# \r
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-# PART OF THIS FILE AT ALL TIMES.\r
-# \r
-\r
-# Input clock periods. These duplicate the values entered for the\r
-# input clocks. You can use these to time your system\r
-#----------------------------------------------------------------\r
-NET "CLK_IN1" TNM_NET = "CLK_IN1";\r
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 12.500 ns HIGH 50% INPUT_JITTER 125.0ps;\r
-\r
-\r
-# FALSE PATH constraints \r
-\r
+++ /dev/null
--- \r
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
--- \r
-------------------------------------------------------------------------------\r
--- User entered comments\r
-------------------------------------------------------------------------------\r
--- None\r
---\r
-------------------------------------------------------------------------------\r
--- "Output Output Phase Duty Pk-to-Pk Phase"\r
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
-------------------------------------------------------------------------------\r
--- CLK_OUT1____80.000______0.000______50.0______147.966____103.963\r
--- CLK_OUT2____80.000____180.000______50.0______147.966____103.963\r
---\r
-------------------------------------------------------------------------------\r
--- "Input Clock Freq (MHz) Input Jitter (UI)"\r
-------------------------------------------------------------------------------\r
--- __primary______________80____________0.010\r
-\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-component FEE_clockbuf80MHz\r
-port\r
- (-- Clock in ports\r
- CLK_IN1 : in std_logic;\r
- -- Clock out ports\r
- CLK_OUT1 : out std_logic;\r
- CLK_OUT2 : out std_logic\r
- );\r
-end component;\r
-\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : FEE_clockbuf80MHz\r
- port map\r
- (-- Clock in ports\r
- CLK_IN1 => CLK_IN1,\r
- -- Clock out ports\r
- CLK_OUT1 => CLK_OUT1,\r
- CLK_OUT2 => CLK_OUT2);\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Thu Sep 25 14:23:17 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:clk_wiz:3.6\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6\r
-# END Select\r
-# BEGIN Parameters\r
-CSET calc_done=DONE\r
-CSET clk_in_sel_port=CLK_IN_SEL\r
-CSET clk_out1_port=CLK_OUT1\r
-CSET clk_out1_use_fine_ps_gui=false\r
-CSET clk_out2_port=CLK_OUT2\r
-CSET clk_out2_use_fine_ps_gui=false\r
-CSET clk_out3_port=CLK_OUT3\r
-CSET clk_out3_use_fine_ps_gui=false\r
-CSET clk_out4_port=CLK_OUT4\r
-CSET clk_out4_use_fine_ps_gui=false\r
-CSET clk_out5_port=CLK_OUT5\r
-CSET clk_out5_use_fine_ps_gui=false\r
-CSET clk_out6_port=CLK_OUT6\r
-CSET clk_out6_use_fine_ps_gui=false\r
-CSET clk_out7_port=CLK_OUT7\r
-CSET clk_out7_use_fine_ps_gui=false\r
-CSET clk_valid_port=CLK_VALID\r
-CSET clkfb_in_n_port=CLKFB_IN_N\r
-CSET clkfb_in_p_port=CLKFB_IN_P\r
-CSET clkfb_in_port=CLKFB_IN\r
-CSET clkfb_in_signaling=SINGLE\r
-CSET clkfb_out_n_port=CLKFB_OUT_N\r
-CSET clkfb_out_p_port=CLKFB_OUT_P\r
-CSET clkfb_out_port=CLKFB_OUT\r
-CSET clkfb_stopped_port=CLKFB_STOPPED\r
-CSET clkin1_jitter_ps=125.0\r
-CSET clkin1_ui_jitter=0.010\r
-CSET clkin2_jitter_ps=100.0\r
-CSET clkin2_ui_jitter=0.010\r
-CSET clkout1_drives=BUFG\r
-CSET clkout1_requested_duty_cycle=50.000\r
-CSET clkout1_requested_out_freq=80\r
-CSET clkout1_requested_phase=0.000\r
-CSET clkout2_drives=BUFG\r
-CSET clkout2_requested_duty_cycle=50.000\r
-CSET clkout2_requested_out_freq=80\r
-CSET clkout2_requested_phase=180\r
-CSET clkout2_used=true\r
-CSET clkout3_drives=BUFG\r
-CSET clkout3_requested_duty_cycle=50.000\r
-CSET clkout3_requested_out_freq=80\r
-CSET clkout3_requested_phase=0.000\r
-CSET clkout3_used=false\r
-CSET clkout4_drives=BUFG\r
-CSET clkout4_requested_duty_cycle=50.000\r
-CSET clkout4_requested_out_freq=80\r
-CSET clkout4_requested_phase=0.000\r
-CSET clkout4_used=false\r
-CSET clkout5_drives=BUFG\r
-CSET clkout5_requested_duty_cycle=50.000\r
-CSET clkout5_requested_out_freq=80\r
-CSET clkout5_requested_phase=0.000\r
-CSET clkout5_used=false\r
-CSET clkout6_drives=BUFG\r
-CSET clkout6_requested_duty_cycle=50.000\r
-CSET clkout6_requested_out_freq=80\r
-CSET clkout6_requested_phase=0.000\r
-CSET clkout6_used=false\r
-CSET clkout7_drives=BUFG\r
-CSET clkout7_requested_duty_cycle=50.000\r
-CSET clkout7_requested_out_freq=80\r
-CSET clkout7_requested_phase=0.000\r
-CSET clkout7_used=false\r
-CSET clock_mgr_type=MANUAL\r
-CSET component_name=FEE_clockbuf80MHz\r
-CSET daddr_port=DADDR\r
-CSET dclk_port=DCLK\r
-CSET dcm_clk_feedback=1X\r
-CSET dcm_clk_out1_port=CLK0\r
-CSET dcm_clk_out2_port=CLK0\r
-CSET dcm_clk_out3_port=CLK0\r
-CSET dcm_clk_out4_port=CLK0\r
-CSET dcm_clk_out5_port=CLK0\r
-CSET dcm_clk_out6_port=CLK0\r
-CSET dcm_clkdv_divide=2.0\r
-CSET dcm_clkfx_divide=1\r
-CSET dcm_clkfx_multiply=4\r
-CSET dcm_clkgen_clk_out1_port=CLKFX\r
-CSET dcm_clkgen_clk_out2_port=CLKFX\r
-CSET dcm_clkgen_clk_out3_port=CLKFX\r
-CSET dcm_clkgen_clkfx_divide=1\r
-CSET dcm_clkgen_clkfx_md_max=0.000\r
-CSET dcm_clkgen_clkfx_multiply=4\r
-CSET dcm_clkgen_clkfxdv_divide=2\r
-CSET dcm_clkgen_clkin_period=10.000\r
-CSET dcm_clkgen_notes=None\r
-CSET dcm_clkgen_spread_spectrum=NONE\r
-CSET dcm_clkgen_startup_wait=false\r
-CSET dcm_clkin_divide_by_2=false\r
-CSET dcm_clkin_period=10.000\r
-CSET dcm_clkout_phase_shift=NONE\r
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS\r
-CSET dcm_notes=None\r
-CSET dcm_phase_shift=0\r
-CSET dcm_pll_cascade=NONE\r
-CSET dcm_startup_wait=false\r
-CSET den_port=DEN\r
-CSET din_port=DIN\r
-CSET dout_port=DOUT\r
-CSET drdy_port=DRDY\r
-CSET dwe_port=DWE\r
-CSET feedback_source=FDBK_AUTO\r
-CSET in_freq_units=Units_MHz\r
-CSET in_jitter_units=Units_UI\r
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED\r
-CSET jitter_options=UI\r
-CSET jitter_sel=No_Jitter\r
-CSET locked_port=LOCKED\r
-CSET mmcm_bandwidth=OPTIMIZED\r
-CSET mmcm_clkfbout_mult_f=12.000\r
-CSET mmcm_clkfbout_phase=0.000\r
-CSET mmcm_clkfbout_use_fine_ps=false\r
-CSET mmcm_clkin1_period=12.500\r
-CSET mmcm_clkin2_period=10.000\r
-CSET mmcm_clkout0_divide_f=12.000\r
-CSET mmcm_clkout0_duty_cycle=0.500\r
-CSET mmcm_clkout0_phase=0.000\r
-CSET mmcm_clkout0_use_fine_ps=false\r
-CSET mmcm_clkout1_divide=12\r
-CSET mmcm_clkout1_duty_cycle=0.500\r
-CSET mmcm_clkout1_phase=180.000\r
-CSET mmcm_clkout1_use_fine_ps=false\r
-CSET mmcm_clkout2_divide=1\r
-CSET mmcm_clkout2_duty_cycle=0.500\r
-CSET mmcm_clkout2_phase=0.000\r
-CSET mmcm_clkout2_use_fine_ps=false\r
-CSET mmcm_clkout3_divide=1\r
-CSET mmcm_clkout3_duty_cycle=0.500\r
-CSET mmcm_clkout3_phase=0.000\r
-CSET mmcm_clkout3_use_fine_ps=false\r
-CSET mmcm_clkout4_cascade=false\r
-CSET mmcm_clkout4_divide=1\r
-CSET mmcm_clkout4_duty_cycle=0.500\r
-CSET mmcm_clkout4_phase=0.000\r
-CSET mmcm_clkout4_use_fine_ps=false\r
-CSET mmcm_clkout5_divide=1\r
-CSET mmcm_clkout5_duty_cycle=0.500\r
-CSET mmcm_clkout5_phase=0.000\r
-CSET mmcm_clkout5_use_fine_ps=false\r
-CSET mmcm_clkout6_divide=1\r
-CSET mmcm_clkout6_duty_cycle=0.500\r
-CSET mmcm_clkout6_phase=0.000\r
-CSET mmcm_clkout6_use_fine_ps=false\r
-CSET mmcm_clock_hold=false\r
-CSET mmcm_compensation=ZHOLD\r
-CSET mmcm_divclk_divide=1\r
-CSET mmcm_notes=None\r
-CSET mmcm_ref_jitter1=0.010\r
-CSET mmcm_ref_jitter2=0.010\r
-CSET mmcm_startup_wait=false\r
-CSET num_out_clks=2\r
-CSET override_dcm=false\r
-CSET override_dcm_clkgen=false\r
-CSET override_mmcm=false\r
-CSET override_pll=false\r
-CSET platform=nt64\r
-CSET pll_bandwidth=OPTIMIZED\r
-CSET pll_clk_feedback=CLKFBOUT\r
-CSET pll_clkfbout_mult=4\r
-CSET pll_clkfbout_phase=0.000\r
-CSET pll_clkin_period=10.000\r
-CSET pll_clkout0_divide=1\r
-CSET pll_clkout0_duty_cycle=0.500\r
-CSET pll_clkout0_phase=0.000\r
-CSET pll_clkout1_divide=1\r
-CSET pll_clkout1_duty_cycle=0.500\r
-CSET pll_clkout1_phase=0.000\r
-CSET pll_clkout2_divide=1\r
-CSET pll_clkout2_duty_cycle=0.500\r
-CSET pll_clkout2_phase=0.000\r
-CSET pll_clkout3_divide=1\r
-CSET pll_clkout3_duty_cycle=0.500\r
-CSET pll_clkout3_phase=0.000\r
-CSET pll_clkout4_divide=1\r
-CSET pll_clkout4_duty_cycle=0.500\r
-CSET pll_clkout4_phase=0.000\r
-CSET pll_clkout5_divide=1\r
-CSET pll_clkout5_duty_cycle=0.500\r
-CSET pll_clkout5_phase=0.000\r
-CSET pll_compensation=SYSTEM_SYNCHRONOUS\r
-CSET pll_divclk_divide=1\r
-CSET pll_notes=None\r
-CSET pll_ref_jitter=0.010\r
-CSET power_down_port=POWER_DOWN\r
-CSET prim_in_freq=80\r
-CSET prim_in_jitter=0.010\r
-CSET prim_source=No_buffer\r
-CSET primary_port=CLK_IN1\r
-CSET primitive=MMCM\r
-CSET primtype_sel=MMCM_ADV\r
-CSET psclk_port=PSCLK\r
-CSET psdone_port=PSDONE\r
-CSET psen_port=PSEN\r
-CSET psincdec_port=PSINCDEC\r
-CSET relative_inclk=REL_PRIMARY\r
-CSET reset_port=RESET\r
-CSET secondary_in_freq=100.000\r
-CSET secondary_in_jitter=0.010\r
-CSET secondary_port=CLK_IN2\r
-CSET secondary_source=Single_ended_clock_capable_pin\r
-CSET ss_mod_freq=250\r
-CSET ss_mode=CENTER_HIGH\r
-CSET status_port=STATUS\r
-CSET summary_strings=empty\r
-CSET use_clk_valid=false\r
-CSET use_clkfb_stopped=false\r
-CSET use_dyn_phase_shift=false\r
-CSET use_dyn_reconfig=false\r
-CSET use_freeze=false\r
-CSET use_freq_synth=false\r
-CSET use_inclk_stopped=false\r
-CSET use_inclk_switchover=false\r
-CSET use_locked=false\r
-CSET use_max_i_jitter=false\r
-CSET use_min_o_jitter=false\r
-CSET use_min_power=false\r
-CSET use_phase_alignment=true\r
-CSET use_power_down=false\r
-CSET use_reset=false\r
-CSET use_spread_spectrum=false\r
-CSET use_spread_spectrum_1=false\r
-CSET use_status=false\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2012-05-10T12:44:55Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: f339ac6c\r
+++ /dev/null
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- <bindings>
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- <libraries/>
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- <autoManagedFiles>
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-
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+++ /dev/null
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 SystemMonitorVirtex
-RECTANGLE Normal 32 32 640 1504
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName di_in[15:0]
-PINATTR Polarity IN
-LINE Wide 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName daddr_in[6:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName den_in
-PINATTR Polarity IN
-LINE Normal 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName dwe_in
-PINATTR Polarity IN
-LINE Normal 0 208 32 208
-PIN 0 208 LEFT 36
-PINATTR PinName dclk_in
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName reset_in
-PINATTR Polarity IN
-LINE Normal 0 400 32 400
-PIN 0 400 LEFT 36
-PINATTR PinName vp_in
-PINATTR Polarity IN
-LINE Normal 0 432 32 432
-PIN 0 432 LEFT 36
-PINATTR PinName vn_in
-PINATTR Polarity IN
-LINE Wide 672 80 640 80
-PIN 672 80 RIGHT 36
-PINATTR PinName do_out[15:0]
-PINATTR Polarity OUT
-LINE Normal 672 112 640 112
-PIN 672 112 RIGHT 36
-PINATTR PinName drdy_out
-PINATTR Polarity OUT
-LINE Normal 672 176 640 176
-PIN 672 176 RIGHT 36
-PINATTR PinName user_temp_alarm_out
-PINATTR Polarity OUT
-LINE Normal 672 208 640 208
-PIN 672 208 RIGHT 36
-PINATTR PinName vccint_alarm_out
-PINATTR Polarity OUT
-LINE Normal 672 240 640 240
-PIN 672 240 RIGHT 36
-PINATTR PinName vccaux_alarm_out
-PINATTR Polarity OUT
-LINE Normal 672 272 640 272
-PIN 672 272 RIGHT 36
-PINATTR PinName ot_out
-PINATTR Polarity OUT
-LINE Wide 672 336 640 336
-PIN 672 336 RIGHT 36
-PINATTR PinName channel_out[4:0]
-PINATTR Polarity OUT
-LINE Normal 672 368 640 368
-PIN 672 368 RIGHT 36
-PINATTR PinName eoc_out
-PINATTR Polarity OUT
-LINE Normal 672 400 640 400
-PIN 672 400 RIGHT 36
-PINATTR PinName eos_out
-PINATTR Polarity OUT
-LINE Normal 672 432 640 432
-PIN 672 432 RIGHT 36
-PINATTR PinName busy_out
-PINATTR Polarity OUT
-LINE Normal 672 464 640 464
-PIN 672 464 RIGHT 36
-PINATTR PinName jtaglocked_out
-PINATTR Polarity OUT
-LINE Normal 672 496 640 496
-PIN 672 496 RIGHT 36
-PINATTR PinName jtagmodified_out
-PINATTR Polarity OUT
-LINE Normal 672 528 640 528
-PIN 672 528 RIGHT 36
-PINATTR PinName jtagbusy_out
-PINATTR Polarity OUT
-\r
+++ /dev/null
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- <!-- -->\r
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- <!-- For tool use only. Do not edit. -->\r
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- <!-- ProjectNavigator created generated project file. -->\r
-\r
- <!-- For use in tracking generated file and other information -->\r
-\r
- <!-- allowing preservation of process status. -->\r
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- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
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+++ /dev/null
--- file: SystemMonitorVirtex.vhd\r
--- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-Library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
-entity SystemMonitorVirtex is\r
- port (\r
- DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port\r
- DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port\r
- DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port\r
- DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port\r
- DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port\r
- RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic\r
- BUSY_OUT : out STD_LOGIC; -- ADC Busy signal\r
- CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs\r
- DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port\r
- DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port\r
- EOC_OUT : out STD_LOGIC; -- End of Conversion Signal\r
- EOS_OUT : out STD_LOGIC; -- End of Sequence Signal\r
- JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal\r
- JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG\r
- JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred\r
- OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output\r
- VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output\r
- VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output\r
- USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output\r
- VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair\r
- VN_IN : in STD_LOGIC\r
-);\r
-end SystemMonitorVirtex;\r
-\r
-architecture xilinx of SystemMonitorVirtex is\r
-\r
- attribute X_CORE_INFO : string;\r
- attribute X_CORE_INFO of xilinx : architecture is "sysmon_wiz_v2_1, Coregen 12.4";\r
-\r
- signal aux_channel_p : std_logic_vector (15 downto 0);\r
- signal aux_channel_n : std_logic_vector (15 downto 0);\r
-\r
-begin\r
-\r
- aux_channel_p(0) <= '0';\r
- aux_channel_n(0) <= '0';\r
-\r
- aux_channel_p(1) <= '0';\r
- aux_channel_n(1) <= '0';\r
-\r
- aux_channel_p(2) <= '0';\r
- aux_channel_n(2) <= '0';\r
-\r
- aux_channel_p(3) <= '0';\r
- aux_channel_n(3) <= '0';\r
-\r
- aux_channel_p(4) <= '0';\r
- aux_channel_n(4) <= '0';\r
-\r
- aux_channel_p(5) <= '0';\r
- aux_channel_n(5) <= '0';\r
-\r
- aux_channel_p(6) <= '0';\r
- aux_channel_n(6) <= '0';\r
-\r
- aux_channel_p(7) <= '0';\r
- aux_channel_n(7) <= '0';\r
-\r
- aux_channel_p(8) <= '0';\r
- aux_channel_n(8) <= '0';\r
-\r
- aux_channel_p(9) <= '0';\r
- aux_channel_n(9) <= '0';\r
-\r
- aux_channel_p(10) <= '0';\r
- aux_channel_n(10) <= '0';\r
-\r
- aux_channel_p(11) <= '0';\r
- aux_channel_n(11) <= '0';\r
-\r
- aux_channel_p(12) <= '0';\r
- aux_channel_n(12) <= '0';\r
-\r
- aux_channel_p(13) <= '0';\r
- aux_channel_n(13) <= '0';\r
-\r
- aux_channel_p(14) <= '0';\r
- aux_channel_n(14) <= '0';\r
-\r
- aux_channel_p(15) <= '0';\r
- aux_channel_n(15) <= '0';\r
-\r
-\r
- SYSMON_INST : SYSMON\r
- generic map(\r
- INIT_40 => X"0000", -- config reg 0\r
- INIT_41 => X"3000", -- config reg 1\r
- INIT_42 => X"1900", -- config reg 2\r
- INIT_48 => X"0100", -- Sequencer channel selection\r
- INIT_49 => X"0000", -- Sequencer channel selection\r
- INIT_4A => X"0000", -- Sequencer Average selection\r
- INIT_4B => X"0000", -- Sequencer Average selection\r
- INIT_4C => X"0000", -- Sequencer Bipolar selection\r
- INIT_4D => X"0000", -- Sequencer Bipolar selection\r
- INIT_4E => X"0000", -- Sequencer Acq time selection\r
- INIT_4F => X"0000", -- Sequencer Acq time selection\r
- INIT_50 => X"b5ed", -- Temp alarm trigger\r
- INIT_51 => X"5999", -- Vccint upper alarm limit\r
- INIT_52 => X"e000", -- Vccaux upper alarm limit\r
- INIT_53 => X"ca33", -- Temp alarm OT upper\r
- INIT_54 => X"a93a", -- Temp alarm reset\r
- INIT_55 => X"5111", -- Vccint lower alarm limit\r
- INIT_56 => X"caaa", -- Vccaux lower alarm limit\r
- INIT_57 => X"ae4e", -- Temp alarm OT reset\r
- SIM_DEVICE => "VIRTEX6",\r
- SIM_MONITOR_FILE => "design.txt"\r
- )\r
-\r
-port map (\r
- CONVST => '0',\r
- CONVSTCLK => '0',\r
- DADDR(6 downto 0) => DADDR_IN(6 downto 0),\r
- DCLK => DCLK_IN,\r
- DEN => DEN_IN,\r
- DI(15 downto 0) => DI_IN(15 downto 0),\r
- DWE => DWE_IN,\r
- RESET => RESET_IN,\r
- VAUXN(15 downto 0) => aux_channel_n(15 downto 0),\r
- VAUXP(15 downto 0) => aux_channel_p(15 downto 0),\r
- ALM(2) => VCCAUX_ALARM_OUT,\r
- ALM(1) => VCCINT_ALARM_OUT,\r
- ALM(0) => USER_TEMP_ALARM_OUT,\r
- BUSY => BUSY_OUT,\r
- CHANNEL(4 downto 0) => CHANNEL_OUT(4 downto 0),\r
- DO(15 downto 0) => DO_OUT(15 downto 0),\r
- DRDY => DRDY_OUT,\r
- EOC => EOC_OUT,\r
- EOS => EOS_OUT,\r
- JTAGBUSY => JTAGBUSY_OUT,\r
- JTAGLOCKED => JTAGLOCKED_OUT,\r
- JTAGMODIFIED => JTAGMODIFIED_OUT,\r
- OT => OT_OUT,\r
- VN => VN_IN,\r
- VP => VP_IN\r
- );\r
-end xilinx;\r
-\r
+++ /dev/null
--- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
---\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-component SystemMonitorVirtex\r
- port (\r
- DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port\r
- DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port\r
- DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port\r
- DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port\r
- DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port\r
- RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic\r
- BUSY_OUT : out STD_LOGIC; -- ADC Busy signal\r
- CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs\r
- DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port\r
- DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port\r
- EOC_OUT : out STD_LOGIC; -- End of Conversion Signal\r
- EOS_OUT : out STD_LOGIC; -- End of Sequence Signal\r
- JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal\r
- JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG\r
- JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred\r
- OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output\r
- VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output\r
- VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output\r
- USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output\r
- VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair\r
- VN_IN : in STD_LOGIC\r
-);\r
-end component;\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
-\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : SystemMonitorVirtex\r
- port map ( \r
- DADDR_IN => DADDR_IN, \r
- DCLK_IN => DCLK_IN, \r
- DEN_IN => DEN_IN, \r
- DI_IN => DI_IN,\r
- DWE_IN => DWE_IN, \r
- RESET_IN => RESET_IN, \r
- BUSY_OUT => BUSY_OUT,\r
- CHANNEL_OUT => CHANNEL_OUT,\r
- DO_OUT => DO_OUT,\r
- DRDY_OUT => DRDY_OUT,\r
- EOC_OUT => EOC_OUT,\r
- EOS_OUT => EOS_OUT,\r
- JTAGBUSY_OUT => JTAGBUSY_OUT,\r
- JTAGLOCKED_OUT => JTAGLOCKED_OUT,\r
- JTAGMODIFIED_OUT => JTAGMODIFIED_OUT,\r
- OT_OUT => OT_OUT,\r
- VCCAUX_ALARM_OUT => VCCAUX_ALARM_OUT,\r
- VCCINT_ALARM_OUT => VCCINT_ALARM_OUT,\r
- USER_TEMP_ALARM_OUT => USER_TEMP_ALARM_OUT,\r
- VP_IN => VP_IN, \r
- VN_IN => VN_IN\r
- );\r
-\r
--- INST_TAG_END ------ End INSTANTIATION Template ---------\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 13.3\r
-# Date: Wed Oct 17 13:30:12 2012\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:sysmon_wiz:2.1\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT System_Monitor_Wizard family Xilinx,_Inc. 2.1\r
-# END Select\r
-# BEGIN Parameters\r
-CSET acquisition_time_vauxp0_vauxn0=false\r
-CSET acquisition_time_vauxp10_vauxn10=false\r
-CSET acquisition_time_vauxp11_vauxn11=false\r
-CSET acquisition_time_vauxp12_vauxn12=false\r
-CSET acquisition_time_vauxp13_vauxn13=false\r
-CSET acquisition_time_vauxp14_vauxn14=false\r
-CSET acquisition_time_vauxp15_vauxn15=false\r
-CSET acquisition_time_vauxp1_vauxn1=false\r
-CSET acquisition_time_vauxp2_vauxn2=false\r
-CSET acquisition_time_vauxp3_vauxn3=false\r
-CSET acquisition_time_vauxp4_vauxn4=false\r
-CSET acquisition_time_vauxp5_vauxn5=false\r
-CSET acquisition_time_vauxp6_vauxn6=false\r
-CSET acquisition_time_vauxp7_vauxn7=false\r
-CSET acquisition_time_vauxp8_vauxn8=false\r
-CSET acquisition_time_vauxp9_vauxn9=false\r
-CSET acquisition_time_vp_vn=false\r
-CSET adc_conversion_rate=100.0\r
-CSET adc_offset_and_gain_calibration=false\r
-CSET adc_offset_calibration=false\r
-CSET average_enable_temperature=false\r
-CSET average_enable_vauxp0_vauxn0=false\r
-CSET average_enable_vauxp10_vauxn10=false\r
-CSET average_enable_vauxp11_vauxn11=false\r
-CSET average_enable_vauxp12_vauxn12=false\r
-CSET average_enable_vauxp13_vauxn13=false\r
-CSET average_enable_vauxp14_vauxn14=false\r
-CSET average_enable_vauxp15_vauxn15=false\r
-CSET average_enable_vauxp1_vauxn1=false\r
-CSET average_enable_vauxp2_vauxn2=false\r
-CSET average_enable_vauxp3_vauxn3=false\r
-CSET average_enable_vauxp4_vauxn4=false\r
-CSET average_enable_vauxp5_vauxn5=false\r
-CSET average_enable_vauxp6_vauxn6=false\r
-CSET average_enable_vauxp7_vauxn7=false\r
-CSET average_enable_vauxp8_vauxn8=false\r
-CSET average_enable_vauxp9_vauxn9=false\r
-CSET average_enable_vccaux=false\r
-CSET average_enable_vccint=false\r
-CSET average_enable_vp_vn=false\r
-CSET bipolar_operation=false\r
-CSET bipolar_vauxp0_vauxn0=false\r
-CSET bipolar_vauxp10_vauxn10=false\r
-CSET bipolar_vauxp11_vauxn11=false\r
-CSET bipolar_vauxp12_vauxn12=false\r
-CSET bipolar_vauxp13_vauxn13=false\r
-CSET bipolar_vauxp14_vauxn14=false\r
-CSET bipolar_vauxp15_vauxn15=false\r
-CSET bipolar_vauxp1_vauxn1=false\r
-CSET bipolar_vauxp2_vauxn2=false\r
-CSET bipolar_vauxp3_vauxn3=false\r
-CSET bipolar_vauxp4_vauxn4=false\r
-CSET bipolar_vauxp5_vauxn5=false\r
-CSET bipolar_vauxp6_vauxn6=false\r
-CSET bipolar_vauxp7_vauxn7=false\r
-CSET bipolar_vauxp8_vauxn8=false\r
-CSET bipolar_vauxp9_vauxn9=false\r
-CSET bipolar_vp_vn=false\r
-CSET channel_averaging=None\r
-CSET channel_enable_calibration=false\r
-CSET channel_enable_temperature=false\r
-CSET channel_enable_vauxp0_vauxn0=false\r
-CSET channel_enable_vauxp10_vauxn10=false\r
-CSET channel_enable_vauxp11_vauxn11=false\r
-CSET channel_enable_vauxp12_vauxn12=false\r
-CSET channel_enable_vauxp13_vauxn13=false\r
-CSET channel_enable_vauxp14_vauxn14=false\r
-CSET channel_enable_vauxp15_vauxn15=false\r
-CSET channel_enable_vauxp1_vauxn1=false\r
-CSET channel_enable_vauxp2_vauxn2=false\r
-CSET channel_enable_vauxp3_vauxn3=false\r
-CSET channel_enable_vauxp4_vauxn4=false\r
-CSET channel_enable_vauxp5_vauxn5=false\r
-CSET channel_enable_vauxp6_vauxn6=false\r
-CSET channel_enable_vauxp7_vauxn7=false\r
-CSET channel_enable_vauxp8_vauxn8=false\r
-CSET channel_enable_vauxp9_vauxn9=false\r
-CSET channel_enable_vccaux=false\r
-CSET channel_enable_vccint=false\r
-CSET channel_enable_vp_vn=false\r
-CSET channel_enable_vrefn=false\r
-CSET channel_enable_vrefp=false\r
-CSET component_name=SystemMonitorVirtex\r
-CSET dclk_frequency=62.5\r
-CSET enable_busy=true\r
-CSET enable_calibration_averaging=true\r
-CSET enable_channel=true\r
-CSET enable_convst=false\r
-CSET enable_convstclk=false\r
-CSET enable_dclk=true\r
-CSET enable_drp=true\r
-CSET enable_eoc=true\r
-CSET enable_eos=true\r
-CSET enable_jtagbusy=true\r
-CSET enable_jtaglocked=true\r
-CSET enable_jtagmodified=true\r
-CSET enable_reset=true\r
-CSET increase_acquisition_time=false\r
-CSET ot_alarm=true\r
-CSET sensor_offset_and_gain_calibration=false\r
-CSET sensor_offset_calibration=false\r
-CSET sequencer_mode=Off\r
-CSET sim_file_name=design\r
-CSET single_channel_acquisition_time=false\r
-CSET single_channel_enable_calibration=true\r
-CSET single_channel_selection=Temperature\r
-CSET startup_channel_selection=single_channel\r
-CSET temperature_alarm_ot_reset=70.0\r
-CSET temperature_alarm_ot_trigger=125.0\r
-CSET temperature_alarm_reset=60.0\r
-CSET temperature_alarm_trigger=85.0\r
-CSET timing_mode=Continuous\r
-CSET user_temp_alarm=true\r
-CSET vccaux_alarm=true\r
-CSET vccaux_alarm_lower=2.375\r
-CSET vccaux_alarm_upper=2.625\r
-CSET vccint_alarm=true\r
-CSET vccint_alarm_lower=0.95\r
-CSET vccint_alarm_upper=1.05\r
-# END Parameters\r
-GENERATE\r
-# CRC: f7c86d59\r
+++ /dev/null
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-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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- <files>
- <file xil_pn:name="SystemMonitorVirtex.vhd" xil_pn:type="FILE_VHDL">
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- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="SystemMonitorVirtex" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
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+++ /dev/null
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-<!-- changes made to this file may result in unpredictable -->\r
-<!-- behavior or data corruption. It is strongly advised that -->\r
-<!-- users do not edit the contents of this file. -->\r
-<!-- -->\r
-<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
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-<messages>\r
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+++ /dev/null
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-XILINX-XDM V1.6e
-$3a6
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\7fM4192we?4650;3xL7063td::>4?:0yK637<utwvLMMt40;9f0`e:=98qMNM{1
\7fCDU}zHI
\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
---------------------------------------------------------------------------------\r
--- You must compile the wrapper file async_fifo_16x9.vhd when simulating\r
--- the core, async_fifo_16x9. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
--- The synthesis directives "translate_off/translate_on" specified\r
--- below are supported by Xilinx, Mentor Graphics and Synplicity\r
--- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
--- synthesis translate_off\r
-LIBRARY XilinxCoreLib;\r
--- synthesis translate_on\r
-ENTITY async_fifo_16x9 IS\r
- PORT (\r
- rst : IN STD_LOGIC;\r
- wr_clk : IN STD_LOGIC;\r
- rd_clk : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END async_fifo_16x9;\r
-\r
-ARCHITECTURE async_fifo_16x9_a OF async_fifo_16x9 IS\r
--- synthesis translate_off\r
-COMPONENT wrapped_async_fifo_16x9\r
- PORT (\r
- rst : IN STD_LOGIC;\r
- wr_clk : IN STD_LOGIC;\r
- rd_clk : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
-\r
--- Configuration specification\r
- FOR ALL : wrapped_async_fifo_16x9 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
- GENERIC MAP (\r
- c_add_ngc_constraint => 0,\r
- c_application_type_axis => 0,\r
- c_application_type_rach => 0,\r
- c_application_type_rdch => 0,\r
- c_application_type_wach => 0,\r
- c_application_type_wdch => 0,\r
- c_application_type_wrch => 0,\r
- c_axi_addr_width => 32,\r
- c_axi_aruser_width => 1,\r
- c_axi_awuser_width => 1,\r
- c_axi_buser_width => 1,\r
- c_axi_data_width => 64,\r
- c_axi_id_width => 4,\r
- c_axi_ruser_width => 1,\r
- c_axi_type => 0,\r
- c_axi_wuser_width => 1,\r
- c_axis_tdata_width => 64,\r
- c_axis_tdest_width => 4,\r
- c_axis_tid_width => 8,\r
- c_axis_tkeep_width => 4,\r
- c_axis_tstrb_width => 4,\r
- c_axis_tuser_width => 4,\r
- c_axis_type => 0,\r
- c_common_clock => 0,\r
- c_count_type => 0,\r
- c_data_count_width => 4,\r
- c_default_value => "BlankString",\r
- c_din_width => 9,\r
- c_din_width_axis => 1,\r
- c_din_width_rach => 32,\r
- c_din_width_rdch => 64,\r
- c_din_width_wach => 32,\r
- c_din_width_wdch => 64,\r
- c_din_width_wrch => 2,\r
- c_dout_rst_val => "0",\r
- c_dout_width => 9,\r
- c_enable_rlocs => 0,\r
- c_enable_rst_sync => 1,\r
- c_error_injection_type => 0,\r
- c_error_injection_type_axis => 0,\r
- c_error_injection_type_rach => 0,\r
- c_error_injection_type_rdch => 0,\r
- c_error_injection_type_wach => 0,\r
- c_error_injection_type_wdch => 0,\r
- c_error_injection_type_wrch => 0,\r
- c_family => "virtex6",\r
- c_full_flags_rst_val => 1,\r
- c_has_almost_empty => 0,\r
- c_has_almost_full => 0,\r
- c_has_axi_aruser => 0,\r
- c_has_axi_awuser => 0,\r
- c_has_axi_buser => 0,\r
- c_has_axi_rd_channel => 0,\r
- c_has_axi_ruser => 0,\r
- c_has_axi_wr_channel => 0,\r
- c_has_axi_wuser => 0,\r
- c_has_axis_tdata => 0,\r
- c_has_axis_tdest => 0,\r
- c_has_axis_tid => 0,\r
- c_has_axis_tkeep => 0,\r
- c_has_axis_tlast => 0,\r
- c_has_axis_tready => 1,\r
- c_has_axis_tstrb => 0,\r
- c_has_axis_tuser => 0,\r
- c_has_backup => 0,\r
- c_has_data_count => 0,\r
- c_has_data_counts_axis => 0,\r
- c_has_data_counts_rach => 0,\r
- c_has_data_counts_rdch => 0,\r
- c_has_data_counts_wach => 0,\r
- c_has_data_counts_wdch => 0,\r
- c_has_data_counts_wrch => 0,\r
- c_has_int_clk => 0,\r
- c_has_master_ce => 0,\r
- c_has_meminit_file => 0,\r
- c_has_overflow => 0,\r
- c_has_prog_flags_axis => 0,\r
- c_has_prog_flags_rach => 0,\r
- c_has_prog_flags_rdch => 0,\r
- c_has_prog_flags_wach => 0,\r
- c_has_prog_flags_wdch => 0,\r
- c_has_prog_flags_wrch => 0,\r
- c_has_rd_data_count => 0,\r
- c_has_rd_rst => 0,\r
- c_has_rst => 1,\r
- c_has_slave_ce => 0,\r
- c_has_srst => 0,\r
- c_has_underflow => 0,\r
- c_has_valid => 0,\r
- c_has_wr_ack => 0,\r
- c_has_wr_data_count => 0,\r
- c_has_wr_rst => 0,\r
- c_implementation_type => 2,\r
- c_implementation_type_axis => 1,\r
- c_implementation_type_rach => 1,\r
- c_implementation_type_rdch => 1,\r
- c_implementation_type_wach => 1,\r
- c_implementation_type_wdch => 1,\r
- c_implementation_type_wrch => 1,\r
- c_init_wr_pntr_val => 0,\r
- c_interface_type => 0,\r
- c_memory_type => 1,\r
- c_mif_file_name => "BlankString",\r
- c_msgon_val => 1,\r
- c_optimization_mode => 0,\r
- c_overflow_low => 0,\r
- c_preload_latency => 1,\r
- c_preload_regs => 0,\r
- c_prim_fifo_type => "512x36",\r
- c_prog_empty_thresh_assert_val => 2,\r
- c_prog_empty_thresh_assert_val_axis => 1022,\r
- c_prog_empty_thresh_assert_val_rach => 1022,\r
- c_prog_empty_thresh_assert_val_rdch => 1022,\r
- c_prog_empty_thresh_assert_val_wach => 1022,\r
- c_prog_empty_thresh_assert_val_wdch => 1022,\r
- c_prog_empty_thresh_assert_val_wrch => 1022,\r
- c_prog_empty_thresh_negate_val => 3,\r
- c_prog_empty_type => 0,\r
- c_prog_empty_type_axis => 0,\r
- c_prog_empty_type_rach => 0,\r
- c_prog_empty_type_rdch => 0,\r
- c_prog_empty_type_wach => 0,\r
- c_prog_empty_type_wdch => 0,\r
- c_prog_empty_type_wrch => 0,\r
- c_prog_full_thresh_assert_val => 13,\r
- c_prog_full_thresh_assert_val_axis => 1023,\r
- c_prog_full_thresh_assert_val_rach => 1023,\r
- c_prog_full_thresh_assert_val_rdch => 1023,\r
- c_prog_full_thresh_assert_val_wach => 1023,\r
- c_prog_full_thresh_assert_val_wdch => 1023,\r
- c_prog_full_thresh_assert_val_wrch => 1023,\r
- c_prog_full_thresh_negate_val => 12,\r
- c_prog_full_type => 0,\r
- c_prog_full_type_axis => 0,\r
- c_prog_full_type_rach => 0,\r
- c_prog_full_type_rdch => 0,\r
- c_prog_full_type_wach => 0,\r
- c_prog_full_type_wdch => 0,\r
- c_prog_full_type_wrch => 0,\r
- c_rach_type => 0,\r
- c_rd_data_count_width => 4,\r
- c_rd_depth => 16,\r
- c_rd_freq => 1,\r
- c_rd_pntr_width => 4,\r
- c_rdch_type => 0,\r
- c_reg_slice_mode_axis => 0,\r
- c_reg_slice_mode_rach => 0,\r
- c_reg_slice_mode_rdch => 0,\r
- c_reg_slice_mode_wach => 0,\r
- c_reg_slice_mode_wdch => 0,\r
- c_reg_slice_mode_wrch => 0,\r
- c_synchronizer_stage => 2,\r
- c_underflow_low => 0,\r
- c_use_common_overflow => 0,\r
- c_use_common_underflow => 0,\r
- c_use_default_settings => 0,\r
- c_use_dout_rst => 1,\r
- c_use_ecc => 0,\r
- c_use_ecc_axis => 0,\r
- c_use_ecc_rach => 0,\r
- c_use_ecc_rdch => 0,\r
- c_use_ecc_wach => 0,\r
- c_use_ecc_wdch => 0,\r
- c_use_ecc_wrch => 0,\r
- c_use_embedded_reg => 0,\r
- c_use_fifo16_flags => 0,\r
- c_use_fwft_data_count => 0,\r
- c_valid_low => 0,\r
- c_wach_type => 0,\r
- c_wdch_type => 0,\r
- c_wr_ack_low => 0,\r
- c_wr_data_count_width => 4,\r
- c_wr_depth => 16,\r
- c_wr_depth_axis => 1024,\r
- c_wr_depth_rach => 16,\r
- c_wr_depth_rdch => 1024,\r
- c_wr_depth_wach => 16,\r
- c_wr_depth_wdch => 1024,\r
- c_wr_depth_wrch => 16,\r
- c_wr_freq => 1,\r
- c_wr_pntr_width => 4,\r
- c_wr_pntr_width_axis => 10,\r
- c_wr_pntr_width_rach => 4,\r
- c_wr_pntr_width_rdch => 10,\r
- c_wr_pntr_width_wach => 4,\r
- c_wr_pntr_width_wdch => 10,\r
- c_wr_pntr_width_wrch => 4,\r
- c_wr_response_latency => 1,\r
- c_wrch_type => 0\r
- );\r
--- synthesis translate_on\r
-BEGIN\r
--- synthesis translate_off\r
-U0 : wrapped_async_fifo_16x9\r
- PORT MAP (\r
- rst => rst,\r
- wr_clk => wr_clk,\r
- rd_clk => rd_clk,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty\r
- );\r
--- synthesis translate_on\r
-\r
-END async_fifo_16x9_a;\r
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
-\r
---------------------------------------------------------------------------------\r
--- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
--- --\r
--- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
--- memory queue generator. Use it to generate resource and performance --\r
--- optimized FIFOs with common or independent read/write clock domains, --\r
--- and optional fixed or programmable full and empty flags and --\r
--- handshaking signals. Choose from a selection of memory resource --\r
--- types for implementation. Optional Hamming code based error --\r
--- detection and correction as well as error injection capability for --\r
--- system test help to insure data integrity. FIFO width and depth are --\r
--- parameterizable, and for native interface FIFOs, asymmetric read and --\r
--- write port widths are also supported. --\r
---------------------------------------------------------------------------------\r
-\r
--- Interfaces:\r
--- AXI4Stream_MASTER_M_AXIS\r
--- AXI4Stream_SLAVE_S_AXIS\r
--- AXI4_MASTER_M_AXI\r
--- AXI4_SLAVE_S_AXI\r
--- AXI4Lite_MASTER_M_AXI\r
--- AXI4Lite_SLAVE_S_AXI\r
--- master_aclk\r
--- slave_aclk\r
--- slave_aresetn\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-COMPONENT async_fifo_16x9\r
- PORT (\r
- rst : IN STD_LOGIC;\r
- wr_clk : IN STD_LOGIC;\r
- rd_clk : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
-\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : async_fifo_16x9\r
- PORT MAP (\r
- rst => rst,\r
- wr_clk => wr_clk,\r
- rd_clk => rd_clk,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty\r
- );\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
-\r
--- You must compile the wrapper file async_fifo_16x9.vhd when simulating\r
--- the core, async_fifo_16x9. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Thu Nov 27 10:27:02 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
-# END Select\r
-# BEGIN Parameters\r
-CSET add_ngc_constraint_axi=false\r
-CSET almost_empty_flag=false\r
-CSET almost_full_flag=false\r
-CSET aruser_width=1\r
-CSET awuser_width=1\r
-CSET axi_address_width=32\r
-CSET axi_data_width=64\r
-CSET axi_type=AXI4_Stream\r
-CSET axis_type=FIFO\r
-CSET buser_width=1\r
-CSET clock_enable_type=Slave_Interface_Clock_Enable\r
-CSET clock_type_axi=Common_Clock\r
-CSET component_name=async_fifo_16x9\r
-CSET data_count=false\r
-CSET data_count_width=4\r
-CSET disable_timing_violations=false\r
-CSET disable_timing_violations_axi=false\r
-CSET dout_reset_value=0\r
-CSET empty_threshold_assert_value=2\r
-CSET empty_threshold_assert_value_axis=1022\r
-CSET empty_threshold_assert_value_rach=1022\r
-CSET empty_threshold_assert_value_rdch=1022\r
-CSET empty_threshold_assert_value_wach=1022\r
-CSET empty_threshold_assert_value_wdch=1022\r
-CSET empty_threshold_assert_value_wrch=1022\r
-CSET empty_threshold_negate_value=3\r
-CSET enable_aruser=false\r
-CSET enable_awuser=false\r
-CSET enable_buser=false\r
-CSET enable_common_overflow=false\r
-CSET enable_common_underflow=false\r
-CSET enable_data_counts_axis=false\r
-CSET enable_data_counts_rach=false\r
-CSET enable_data_counts_rdch=false\r
-CSET enable_data_counts_wach=false\r
-CSET enable_data_counts_wdch=false\r
-CSET enable_data_counts_wrch=false\r
-CSET enable_ecc=false\r
-CSET enable_ecc_axis=false\r
-CSET enable_ecc_rach=false\r
-CSET enable_ecc_rdch=false\r
-CSET enable_ecc_wach=false\r
-CSET enable_ecc_wdch=false\r
-CSET enable_ecc_wrch=false\r
-CSET enable_read_channel=false\r
-CSET enable_read_pointer_increment_by2=false\r
-CSET enable_reset_synchronization=true\r
-CSET enable_ruser=false\r
-CSET enable_tdata=false\r
-CSET enable_tdest=false\r
-CSET enable_tid=false\r
-CSET enable_tkeep=false\r
-CSET enable_tlast=false\r
-CSET enable_tready=true\r
-CSET enable_tstrobe=false\r
-CSET enable_tuser=false\r
-CSET enable_write_channel=false\r
-CSET enable_wuser=false\r
-CSET fifo_application_type_axis=Data_FIFO\r
-CSET fifo_application_type_rach=Data_FIFO\r
-CSET fifo_application_type_rdch=Data_FIFO\r
-CSET fifo_application_type_wach=Data_FIFO\r
-CSET fifo_application_type_wdch=Data_FIFO\r
-CSET fifo_application_type_wrch=Data_FIFO\r
-CSET fifo_implementation=Independent_Clocks_Block_RAM\r
-CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
-CSET full_flags_reset_value=1\r
-CSET full_threshold_assert_value=13\r
-CSET full_threshold_assert_value_axis=1023\r
-CSET full_threshold_assert_value_rach=1023\r
-CSET full_threshold_assert_value_rdch=1023\r
-CSET full_threshold_assert_value_wach=1023\r
-CSET full_threshold_assert_value_wdch=1023\r
-CSET full_threshold_assert_value_wrch=1023\r
-CSET full_threshold_negate_value=12\r
-CSET id_width=4\r
-CSET inject_dbit_error=false\r
-CSET inject_dbit_error_axis=false\r
-CSET inject_dbit_error_rach=false\r
-CSET inject_dbit_error_rdch=false\r
-CSET inject_dbit_error_wach=false\r
-CSET inject_dbit_error_wdch=false\r
-CSET inject_dbit_error_wrch=false\r
-CSET inject_sbit_error=false\r
-CSET inject_sbit_error_axis=false\r
-CSET inject_sbit_error_rach=false\r
-CSET inject_sbit_error_rdch=false\r
-CSET inject_sbit_error_wach=false\r
-CSET inject_sbit_error_wdch=false\r
-CSET inject_sbit_error_wrch=false\r
-CSET input_data_width=9\r
-CSET input_depth=16\r
-CSET input_depth_axis=1024\r
-CSET input_depth_rach=16\r
-CSET input_depth_rdch=1024\r
-CSET input_depth_wach=16\r
-CSET input_depth_wdch=1024\r
-CSET input_depth_wrch=16\r
-CSET interface_type=Native\r
-CSET output_data_width=9\r
-CSET output_depth=16\r
-CSET overflow_flag=false\r
-CSET overflow_flag_axi=false\r
-CSET overflow_sense=Active_High\r
-CSET overflow_sense_axi=Active_High\r
-CSET performance_options=Standard_FIFO\r
-CSET programmable_empty_type=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
-CSET programmable_full_type=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
-CSET rach_type=FIFO\r
-CSET rdch_type=FIFO\r
-CSET read_clock_frequency=1\r
-CSET read_data_count=false\r
-CSET read_data_count_width=4\r
-CSET register_slice_mode_axis=Fully_Registered\r
-CSET register_slice_mode_rach=Fully_Registered\r
-CSET register_slice_mode_rdch=Fully_Registered\r
-CSET register_slice_mode_wach=Fully_Registered\r
-CSET register_slice_mode_wdch=Fully_Registered\r
-CSET register_slice_mode_wrch=Fully_Registered\r
-CSET reset_pin=true\r
-CSET reset_type=Asynchronous_Reset\r
-CSET ruser_width=1\r
-CSET synchronization_stages=2\r
-CSET synchronization_stages_axi=2\r
-CSET tdata_width=64\r
-CSET tdest_width=4\r
-CSET tid_width=8\r
-CSET tkeep_width=4\r
-CSET tstrb_width=4\r
-CSET tuser_width=4\r
-CSET underflow_flag=false\r
-CSET underflow_flag_axi=false\r
-CSET underflow_sense=Active_High\r
-CSET underflow_sense_axi=Active_High\r
-CSET use_clock_enable=false\r
-CSET use_dout_reset=true\r
-CSET use_embedded_registers=false\r
-CSET use_extra_logic=false\r
-CSET valid_flag=false\r
-CSET valid_sense=Active_High\r
-CSET wach_type=FIFO\r
-CSET wdch_type=FIFO\r
-CSET wrch_type=FIFO\r
-CSET write_acknowledge_flag=false\r
-CSET write_acknowledge_sense=Active_High\r
-CSET write_clock_frequency=1\r
-CSET write_data_count=false\r
-CSET write_data_count_width=4\r
-CSET wuser_width=1\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2012-11-19T12:39:56Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: e70f47ef\r
+++ /dev/null
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+++ /dev/null
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-SymbolType BLOCK
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-RECTANGLE Normal 32 32 800 3680
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Normal 0 208 32 208
-PIN 0 208 LEFT 36
-PINATTR PinName wr_clk
-PINATTR Polarity IN
-LINE Wide 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName din[31:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 464 32 464
-PIN 0 464 LEFT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Normal 832 240 800 240
-PIN 832 240 RIGHT 36
-PINATTR PinName rd_clk
-PINATTR Polarity IN
-LINE Wide 832 272 800 272
-PIN 832 272 RIGHT 36
-PINATTR PinName dout[31:0]
-PINATTR Polarity OUT
-LINE Normal 832 304 800 304
-PIN 832 304 RIGHT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 832 496 800 496
-PIN 832 496 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-\r
+++ /dev/null
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+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$2a0
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\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2012 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
---------------------------------------------------------------------------------\r
--- You must compile the wrapper file async_fifo_512x32.vhd when simulating\r
--- the core, async_fifo_512x32. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
--- The synthesis directives "translate_off/translate_on" specified\r
--- below are supported by Xilinx, Mentor Graphics and Synplicity\r
--- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
--- synthesis translate_off\r
-LIBRARY XilinxCoreLib;\r
--- synthesis translate_on\r
-ENTITY async_fifo_512x32 IS\r
- PORT (\r
- rst : IN STD_LOGIC;\r
- wr_clk : IN STD_LOGIC;\r
- rd_clk : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END async_fifo_512x32;\r
-\r
-ARCHITECTURE async_fifo_512x32_a OF async_fifo_512x32 IS\r
--- synthesis translate_off\r
-COMPONENT wrapped_async_fifo_512x32\r
- PORT (\r
- rst : IN STD_LOGIC;\r
- wr_clk : IN STD_LOGIC;\r
- rd_clk : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
-\r
--- Configuration specification\r
- FOR ALL : wrapped_async_fifo_512x32 USE ENTITY XilinxCoreLib.fifo_generator_v8_3(behavioral)\r
- GENERIC MAP (\r
- c_add_ngc_constraint => 0,\r
- c_application_type_axis => 0,\r
- c_application_type_rach => 0,\r
- c_application_type_rdch => 0,\r
- c_application_type_wach => 0,\r
- c_application_type_wdch => 0,\r
- c_application_type_wrch => 0,\r
- c_axi_addr_width => 32,\r
- c_axi_aruser_width => 1,\r
- c_axi_awuser_width => 1,\r
- c_axi_buser_width => 1,\r
- c_axi_data_width => 64,\r
- c_axi_id_width => 4,\r
- c_axi_ruser_width => 1,\r
- c_axi_type => 0,\r
- c_axi_wuser_width => 1,\r
- c_axis_tdata_width => 64,\r
- c_axis_tdest_width => 4,\r
- c_axis_tid_width => 8,\r
- c_axis_tkeep_width => 4,\r
- c_axis_tstrb_width => 4,\r
- c_axis_tuser_width => 4,\r
- c_axis_type => 0,\r
- c_common_clock => 0,\r
- c_count_type => 0,\r
- c_data_count_width => 9,\r
- c_default_value => "BlankString",\r
- c_din_width => 32,\r
- c_din_width_axis => 1,\r
- c_din_width_rach => 32,\r
- c_din_width_rdch => 64,\r
- c_din_width_wach => 32,\r
- c_din_width_wdch => 64,\r
- c_din_width_wrch => 2,\r
- c_dout_rst_val => "0",\r
- c_dout_width => 32,\r
- c_enable_rlocs => 0,\r
- c_enable_rst_sync => 1,\r
- c_error_injection_type => 0,\r
- c_error_injection_type_axis => 0,\r
- c_error_injection_type_rach => 0,\r
- c_error_injection_type_rdch => 0,\r
- c_error_injection_type_wach => 0,\r
- c_error_injection_type_wdch => 0,\r
- c_error_injection_type_wrch => 0,\r
- c_family => "virtex6",\r
- c_full_flags_rst_val => 1,\r
- c_has_almost_empty => 0,\r
- c_has_almost_full => 0,\r
- c_has_axi_aruser => 0,\r
- c_has_axi_awuser => 0,\r
- c_has_axi_buser => 0,\r
- c_has_axi_rd_channel => 0,\r
- c_has_axi_ruser => 0,\r
- c_has_axi_wr_channel => 0,\r
- c_has_axi_wuser => 0,\r
- c_has_axis_tdata => 0,\r
- c_has_axis_tdest => 0,\r
- c_has_axis_tid => 0,\r
- c_has_axis_tkeep => 0,\r
- c_has_axis_tlast => 0,\r
- c_has_axis_tready => 1,\r
- c_has_axis_tstrb => 0,\r
- c_has_axis_tuser => 0,\r
- c_has_backup => 0,\r
- c_has_data_count => 0,\r
- c_has_data_counts_axis => 0,\r
- c_has_data_counts_rach => 0,\r
- c_has_data_counts_rdch => 0,\r
- c_has_data_counts_wach => 0,\r
- c_has_data_counts_wdch => 0,\r
- c_has_data_counts_wrch => 0,\r
- c_has_int_clk => 0,\r
- c_has_master_ce => 0,\r
- c_has_meminit_file => 0,\r
- c_has_overflow => 0,\r
- c_has_prog_flags_axis => 0,\r
- c_has_prog_flags_rach => 0,\r
- c_has_prog_flags_rdch => 0,\r
- c_has_prog_flags_wach => 0,\r
- c_has_prog_flags_wdch => 0,\r
- c_has_prog_flags_wrch => 0,\r
- c_has_rd_data_count => 0,\r
- c_has_rd_rst => 0,\r
- c_has_rst => 1,\r
- c_has_slave_ce => 0,\r
- c_has_srst => 0,\r
- c_has_underflow => 0,\r
- c_has_valid => 0,\r
- c_has_wr_ack => 0,\r
- c_has_wr_data_count => 0,\r
- c_has_wr_rst => 0,\r
- c_implementation_type => 2,\r
- c_implementation_type_axis => 1,\r
- c_implementation_type_rach => 1,\r
- c_implementation_type_rdch => 1,\r
- c_implementation_type_wach => 1,\r
- c_implementation_type_wdch => 1,\r
- c_implementation_type_wrch => 1,\r
- c_init_wr_pntr_val => 0,\r
- c_interface_type => 0,\r
- c_memory_type => 1,\r
- c_mif_file_name => "BlankString",\r
- c_msgon_val => 1,\r
- c_optimization_mode => 0,\r
- c_overflow_low => 0,\r
- c_preload_latency => 1,\r
- c_preload_regs => 0,\r
- c_prim_fifo_type => "512x36",\r
- c_prog_empty_thresh_assert_val => 2,\r
- c_prog_empty_thresh_assert_val_axis => 1022,\r
- c_prog_empty_thresh_assert_val_rach => 1022,\r
- c_prog_empty_thresh_assert_val_rdch => 1022,\r
- c_prog_empty_thresh_assert_val_wach => 1022,\r
- c_prog_empty_thresh_assert_val_wdch => 1022,\r
- c_prog_empty_thresh_assert_val_wrch => 1022,\r
- c_prog_empty_thresh_negate_val => 3,\r
- c_prog_empty_type => 0,\r
- c_prog_empty_type_axis => 5,\r
- c_prog_empty_type_rach => 5,\r
- c_prog_empty_type_rdch => 5,\r
- c_prog_empty_type_wach => 5,\r
- c_prog_empty_type_wdch => 5,\r
- c_prog_empty_type_wrch => 5,\r
- c_prog_full_thresh_assert_val => 509,\r
- c_prog_full_thresh_assert_val_axis => 1023,\r
- c_prog_full_thresh_assert_val_rach => 1023,\r
- c_prog_full_thresh_assert_val_rdch => 1023,\r
- c_prog_full_thresh_assert_val_wach => 1023,\r
- c_prog_full_thresh_assert_val_wdch => 1023,\r
- c_prog_full_thresh_assert_val_wrch => 1023,\r
- c_prog_full_thresh_negate_val => 508,\r
- c_prog_full_type => 0,\r
- c_prog_full_type_axis => 5,\r
- c_prog_full_type_rach => 5,\r
- c_prog_full_type_rdch => 5,\r
- c_prog_full_type_wach => 5,\r
- c_prog_full_type_wdch => 5,\r
- c_prog_full_type_wrch => 5,\r
- c_rach_type => 0,\r
- c_rd_data_count_width => 9,\r
- c_rd_depth => 512,\r
- c_rd_freq => 1,\r
- c_rd_pntr_width => 9,\r
- c_rdch_type => 0,\r
- c_reg_slice_mode_axis => 0,\r
- c_reg_slice_mode_rach => 0,\r
- c_reg_slice_mode_rdch => 0,\r
- c_reg_slice_mode_wach => 0,\r
- c_reg_slice_mode_wdch => 0,\r
- c_reg_slice_mode_wrch => 0,\r
- c_underflow_low => 0,\r
- c_use_common_overflow => 0,\r
- c_use_common_underflow => 0,\r
- c_use_default_settings => 0,\r
- c_use_dout_rst => 1,\r
- c_use_ecc => 0,\r
- c_use_ecc_axis => 0,\r
- c_use_ecc_rach => 0,\r
- c_use_ecc_rdch => 0,\r
- c_use_ecc_wach => 0,\r
- c_use_ecc_wdch => 0,\r
- c_use_ecc_wrch => 0,\r
- c_use_embedded_reg => 0,\r
- c_use_fifo16_flags => 0,\r
- c_use_fwft_data_count => 0,\r
- c_valid_low => 0,\r
- c_wach_type => 0,\r
- c_wdch_type => 0,\r
- c_wr_ack_low => 0,\r
- c_wr_data_count_width => 9,\r
- c_wr_depth => 512,\r
- c_wr_depth_axis => 1024,\r
- c_wr_depth_rach => 16,\r
- c_wr_depth_rdch => 1024,\r
- c_wr_depth_wach => 16,\r
- c_wr_depth_wdch => 1024,\r
- c_wr_depth_wrch => 16,\r
- c_wr_freq => 1,\r
- c_wr_pntr_width => 9,\r
- c_wr_pntr_width_axis => 10,\r
- c_wr_pntr_width_rach => 4,\r
- c_wr_pntr_width_rdch => 10,\r
- c_wr_pntr_width_wach => 4,\r
- c_wr_pntr_width_wdch => 10,\r
- c_wr_pntr_width_wrch => 4,\r
- c_wr_response_latency => 1,\r
- c_wrch_type => 0\r
- );\r
--- synthesis translate_on\r
-BEGIN\r
--- synthesis translate_off\r
-U0 : wrapped_async_fifo_512x32\r
- PORT MAP (\r
- rst => rst,\r
- wr_clk => wr_clk,\r
- rd_clk => rd_clk,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty\r
- );\r
--- synthesis translate_on\r
-\r
-END async_fifo_512x32_a;\r
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2012 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
-\r
---------------------------------------------------------------------------------\r
--- Generated from core with identifier: xilinx.com:ip:fifo_generator:8.3 --\r
--- --\r
--- The FIFO Generator is a parameterizable first-in/first-out memory --\r
--- queue generator. Use it to generate resource and performance --\r
--- optimized FIFOs with common or independent read/write clock domains, --\r
--- and optional fixed or programmable full and empty flags and --\r
--- handshaking signals. Choose from a selection of memory resource --\r
--- types for implementation. Optional Hamming code based error --\r
--- detection and correction as well as error injection capability for --\r
--- system test help to insure data integrity. FIFO width and depth are --\r
--- parameterizable, and for native interface FIFOs, asymmetric read and --\r
--- write port widths are also supported. --\r
---------------------------------------------------------------------------------\r
-\r
--- Interfaces:\r
--- AXI4Stream_MASTER_M_AXIS\r
--- AXI4Stream_SLAVE_S_AXIS\r
--- AXI4_MASTER_M_AXI\r
--- AXI4_SLAVE_S_AXI\r
--- AXI4Lite_MASTER_M_AXI\r
--- AXI4Lite_SLAVE_S_AXI\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-COMPONENT async_fifo_512x32\r
- PORT (\r
- rst : IN STD_LOGIC;\r
- wr_clk : IN STD_LOGIC;\r
- rd_clk : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
-\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : async_fifo_512x32\r
- PORT MAP (\r
- rst => rst,\r
- wr_clk => wr_clk,\r
- rd_clk => rd_clk,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty\r
- );\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
-\r
--- You must compile the wrapper file async_fifo_512x32.vhd when simulating\r
--- the core, async_fifo_512x32. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 13.3\r
-# Date: Thu Jul 26 14:36:50 2012\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:fifo_generator:8.3\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.3\r
-# END Select\r
-# BEGIN Parameters\r
-CSET add_ngc_constraint_axi=false\r
-CSET almost_empty_flag=false\r
-CSET almost_full_flag=false\r
-CSET aruser_width=1\r
-CSET awuser_width=1\r
-CSET axi_address_width=32\r
-CSET axi_data_width=64\r
-CSET axi_type=AXI4_Stream\r
-CSET axis_type=FIFO\r
-CSET buser_width=1\r
-CSET clock_enable_type=Slave_Interface_Clock_Enable\r
-CSET clock_type_axi=Common_Clock\r
-CSET component_name=async_fifo_512x32\r
-CSET data_count=false\r
-CSET data_count_width=9\r
-CSET disable_timing_violations=false\r
-CSET disable_timing_violations_axi=false\r
-CSET dout_reset_value=0\r
-CSET empty_threshold_assert_value=2\r
-CSET empty_threshold_assert_value_axis=1022\r
-CSET empty_threshold_assert_value_rach=1022\r
-CSET empty_threshold_assert_value_rdch=1022\r
-CSET empty_threshold_assert_value_wach=1022\r
-CSET empty_threshold_assert_value_wdch=1022\r
-CSET empty_threshold_assert_value_wrch=1022\r
-CSET empty_threshold_negate_value=3\r
-CSET enable_aruser=false\r
-CSET enable_awuser=false\r
-CSET enable_buser=false\r
-CSET enable_common_overflow=false\r
-CSET enable_common_underflow=false\r
-CSET enable_data_counts_axis=false\r
-CSET enable_data_counts_rach=false\r
-CSET enable_data_counts_rdch=false\r
-CSET enable_data_counts_wach=false\r
-CSET enable_data_counts_wdch=false\r
-CSET enable_data_counts_wrch=false\r
-CSET enable_ecc=false\r
-CSET enable_ecc_axis=false\r
-CSET enable_ecc_rach=false\r
-CSET enable_ecc_rdch=false\r
-CSET enable_ecc_wach=false\r
-CSET enable_ecc_wdch=false\r
-CSET enable_ecc_wrch=false\r
-CSET enable_handshake_flag_options_axis=false\r
-CSET enable_handshake_flag_options_rach=false\r
-CSET enable_handshake_flag_options_rdch=false\r
-CSET enable_handshake_flag_options_wach=false\r
-CSET enable_handshake_flag_options_wdch=false\r
-CSET enable_handshake_flag_options_wrch=false\r
-CSET enable_read_channel=false\r
-CSET enable_read_pointer_increment_by2=false\r
-CSET enable_reset_synchronization=true\r
-CSET enable_ruser=false\r
-CSET enable_tdata=false\r
-CSET enable_tdest=false\r
-CSET enable_tid=false\r
-CSET enable_tkeep=false\r
-CSET enable_tlast=false\r
-CSET enable_tready=true\r
-CSET enable_tstrobe=false\r
-CSET enable_tuser=false\r
-CSET enable_write_channel=false\r
-CSET enable_wuser=false\r
-CSET fifo_application_type_axis=Data_FIFO\r
-CSET fifo_application_type_rach=Data_FIFO\r
-CSET fifo_application_type_rdch=Data_FIFO\r
-CSET fifo_application_type_wach=Data_FIFO\r
-CSET fifo_application_type_wdch=Data_FIFO\r
-CSET fifo_application_type_wrch=Data_FIFO\r
-CSET fifo_implementation=Independent_Clocks_Block_RAM\r
-CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
-CSET full_flags_reset_value=1\r
-CSET full_threshold_assert_value=509\r
-CSET full_threshold_assert_value_axis=1023\r
-CSET full_threshold_assert_value_rach=1023\r
-CSET full_threshold_assert_value_rdch=1023\r
-CSET full_threshold_assert_value_wach=1023\r
-CSET full_threshold_assert_value_wdch=1023\r
-CSET full_threshold_assert_value_wrch=1023\r
-CSET full_threshold_negate_value=508\r
-CSET id_width=4\r
-CSET inject_dbit_error=false\r
-CSET inject_dbit_error_axis=false\r
-CSET inject_dbit_error_rach=false\r
-CSET inject_dbit_error_rdch=false\r
-CSET inject_dbit_error_wach=false\r
-CSET inject_dbit_error_wdch=false\r
-CSET inject_dbit_error_wrch=false\r
-CSET inject_sbit_error=false\r
-CSET inject_sbit_error_axis=false\r
-CSET inject_sbit_error_rach=false\r
-CSET inject_sbit_error_rdch=false\r
-CSET inject_sbit_error_wach=false\r
-CSET inject_sbit_error_wdch=false\r
-CSET inject_sbit_error_wrch=false\r
-CSET input_data_width=32\r
-CSET input_depth=512\r
-CSET input_depth_axis=1024\r
-CSET input_depth_rach=16\r
-CSET input_depth_rdch=1024\r
-CSET input_depth_wach=16\r
-CSET input_depth_wdch=1024\r
-CSET input_depth_wrch=16\r
-CSET interface_type=Native\r
-CSET output_data_width=32\r
-CSET output_depth=512\r
-CSET overflow_flag=false\r
-CSET overflow_flag_axi=false\r
-CSET overflow_sense=Active_High\r
-CSET overflow_sense_axi=Active_High\r
-CSET performance_options=Standard_FIFO\r
-CSET programmable_empty_type=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_axis=Empty\r
-CSET programmable_empty_type_rach=Empty\r
-CSET programmable_empty_type_rdch=Empty\r
-CSET programmable_empty_type_wach=Empty\r
-CSET programmable_empty_type_wdch=Empty\r
-CSET programmable_empty_type_wrch=Empty\r
-CSET programmable_full_type=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_axis=Full\r
-CSET programmable_full_type_rach=Full\r
-CSET programmable_full_type_rdch=Full\r
-CSET programmable_full_type_wach=Full\r
-CSET programmable_full_type_wdch=Full\r
-CSET programmable_full_type_wrch=Full\r
-CSET rach_type=FIFO\r
-CSET rdch_type=FIFO\r
-CSET read_clock_frequency=1\r
-CSET read_data_count=false\r
-CSET read_data_count_width=9\r
-CSET register_slice_mode_axis=Fully_Registered\r
-CSET register_slice_mode_rach=Fully_Registered\r
-CSET register_slice_mode_rdch=Fully_Registered\r
-CSET register_slice_mode_wach=Fully_Registered\r
-CSET register_slice_mode_wdch=Fully_Registered\r
-CSET register_slice_mode_wrch=Fully_Registered\r
-CSET reset_pin=true\r
-CSET reset_type=Asynchronous_Reset\r
-CSET ruser_width=1\r
-CSET tdata_width=64\r
-CSET tdest_width=4\r
-CSET tid_width=8\r
-CSET tkeep_width=4\r
-CSET tstrb_width=4\r
-CSET tuser_width=4\r
-CSET underflow_flag=false\r
-CSET underflow_flag_axi=false\r
-CSET underflow_sense=Active_High\r
-CSET underflow_sense_axi=Active_High\r
-CSET use_clock_enable=false\r
-CSET use_dout_reset=true\r
-CSET use_embedded_registers=false\r
-CSET use_extra_logic=false\r
-CSET valid_flag=false\r
-CSET valid_sense=Active_High\r
-CSET wach_type=FIFO\r
-CSET wdch_type=FIFO\r
-CSET wrch_type=FIFO\r
-CSET write_acknowledge_flag=false\r
-CSET write_acknowledge_sense=Active_High\r
-CSET write_clock_frequency=1\r
-CSET write_data_count=false\r
-CSET write_data_count_width=9\r
-CSET wuser_width=1\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2011-03-14T07:12:32.000Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: 5b1bf9c4\r
+++ /dev/null
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-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
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- <property xil_pn:name="PROP_DesignName" xil_pn:value="async_fifo_512x32" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
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+++ /dev/null
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 clockmodule40switch
-RECTANGLE Normal 32 32 576 1088
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk_in1
-PINATTR Polarity IN
-LINE Normal 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName clk_in2
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName clk_in_sel
-PINATTR Polarity IN
-LINE Normal 0 432 32 432
-PIN 0 432 LEFT 36
-PINATTR PinName reset
-PINATTR Polarity IN
-LINE Normal 608 80 576 80
-PIN 608 80 RIGHT 36
-PINATTR PinName clk_out1
-PINATTR Polarity OUT
-LINE Normal 608 176 576 176
-PIN 608 176 RIGHT 36
-PINATTR PinName clk_out2
-PINATTR Polarity OUT
-LINE Normal 608 976 576 976
-PIN 608 976 RIGHT 36
-PINATTR PinName locked
-PINATTR Polarity OUT
-\r
+++ /dev/null
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- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
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+++ /dev/null
-# file: clockmodule40switch.ucf\r
-# \r
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
-# \r
-# This file contains confidential and proprietary information\r
-# of Xilinx, Inc. and is protected under U.S. and\r
-# international copyright and other intellectual property\r
-# laws.\r
-# \r
-# DISCLAIMER\r
-# This disclaimer is not a license and does not grant any\r
-# rights to the materials distributed herewith. Except as\r
-# otherwise provided in a valid license issued to you by\r
-# Xilinx, and to the maximum extent permitted by applicable\r
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-# (2) Xilinx shall not be liable (whether in contract or tort,\r
-# including negligence, or under any other theory of\r
-# liability) for any loss or damage of any kind or nature\r
-# related to, arising under or in connection with these\r
-# materials, including for any direct, or any indirect,\r
-# special, incidental, or consequential loss or damage\r
-# (including loss of data, profits, goodwill, or any type of\r
-# loss or damage suffered as a result of any action brought\r
-# by a third party) even if such damage or loss was\r
-# reasonably foreseeable or Xilinx had been advised of the\r
-# possibility of the same.\r
-# \r
-# CRITICAL APPLICATIONS\r
-# Xilinx products are not designed or intended to be fail-\r
-# safe, or for use in any application requiring fail-safe\r
-# performance, such as life-support or safety devices or\r
-# systems, Class III medical devices, nuclear facilities,\r
-# applications related to the deployment of airbags, or any\r
-# other applications that could lead to death, personal\r
-# injury, or severe property or environmental damage\r
-# (individually and collectively, "Critical\r
-# Applications"). Customer assumes the sole risk and\r
-# liability of any use of Xilinx products in Critical\r
-# Applications, subject only to applicable laws and\r
-# regulations governing limitations on product liability.\r
-# \r
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-# PART OF THIS FILE AT ALL TIMES.\r
-# \r
-\r
-# Input clock periods. These duplicate the values entered for the\r
-# input clocks. You can use these to time your system\r
-#----------------------------------------------------------------\r
-NET "CLK_IN1" TNM_NET = "CLK_IN1";\r
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;\r
-NET "CLK_IN2" TNM_NET = "CLK_IN2";\r
-TIMESPEC "TS_CLK_IN2" = PERIOD "CLK_IN2" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;\r
-\r
-\r
-# FALSE PATH constraints \r
-PIN "RESET" TIG;\r
-\r
+++ /dev/null
--- \r
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
--- \r
-------------------------------------------------------------------------------\r
--- User entered comments\r
-------------------------------------------------------------------------------\r
--- None\r
---\r
-------------------------------------------------------------------------------\r
--- "Output Output Phase Duty Pk-to-Pk Phase"\r
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
-------------------------------------------------------------------------------\r
--- CLK_OUT1____40.000______0.000______50.0______247.096____196.976\r
--- CLK_OUT2____80.000______0.000______50.0______200.412____196.976\r
---\r
-------------------------------------------------------------------------------\r
--- "Input Clock Freq (MHz) Input Jitter (UI)"\r
-------------------------------------------------------------------------------\r
--- __primary______________40____________0.010\r
--- _secondary____________40____________0.010\r
-\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-component clockmodule40switch\r
-port\r
- (-- Clock in ports\r
- CLK_IN1 : in std_logic;\r
- CLK_IN2 : in std_logic;\r
- CLK_IN_SEL : in std_logic;\r
- -- Clock out ports\r
- CLK_OUT1 : out std_logic;\r
- CLK_OUT2 : out std_logic;\r
- -- Status and control signals\r
- RESET : in std_logic;\r
- LOCKED : out std_logic\r
- );\r
-end component;\r
-\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : clockmodule40switch\r
- port map\r
- (-- Clock in ports\r
- CLK_IN1 => CLK_IN1,\r
- CLK_IN2 => CLK_IN2,\r
- CLK_IN_SEL => CLK_IN_SEL,\r
- -- Clock out ports\r
- CLK_OUT1 => CLK_OUT1,\r
- CLK_OUT2 => CLK_OUT2,\r
- -- Status and control signals\r
- RESET => RESET,\r
- LOCKED => LOCKED);\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Wed Nov 26 08:54:36 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:clk_wiz:3.6\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6\r
-# END Select\r
-# BEGIN Parameters\r
-CSET calc_done=DONE\r
-CSET clk_in_sel_port=CLK_IN_SEL\r
-CSET clk_out1_port=CLK_OUT1\r
-CSET clk_out1_use_fine_ps_gui=false\r
-CSET clk_out2_port=CLK_OUT2\r
-CSET clk_out2_use_fine_ps_gui=false\r
-CSET clk_out3_port=CLK_OUT3\r
-CSET clk_out3_use_fine_ps_gui=false\r
-CSET clk_out4_port=CLK_OUT4\r
-CSET clk_out4_use_fine_ps_gui=false\r
-CSET clk_out5_port=CLK_OUT5\r
-CSET clk_out5_use_fine_ps_gui=false\r
-CSET clk_out6_port=CLK_OUT6\r
-CSET clk_out6_use_fine_ps_gui=false\r
-CSET clk_out7_port=CLK_OUT7\r
-CSET clk_out7_use_fine_ps_gui=false\r
-CSET clk_valid_port=CLK_VALID\r
-CSET clkfb_in_n_port=CLKFB_IN_N\r
-CSET clkfb_in_p_port=CLKFB_IN_P\r
-CSET clkfb_in_port=CLKFB_IN\r
-CSET clkfb_in_signaling=SINGLE\r
-CSET clkfb_out_n_port=CLKFB_OUT_N\r
-CSET clkfb_out_p_port=CLKFB_OUT_P\r
-CSET clkfb_out_port=CLKFB_OUT\r
-CSET clkfb_stopped_port=CLKFB_STOPPED\r
-CSET clkin1_jitter_ps=250.0\r
-CSET clkin1_ui_jitter=0.010\r
-CSET clkin2_jitter_ps=250.0\r
-CSET clkin2_ui_jitter=0.010\r
-CSET clkout1_drives=BUFG\r
-CSET clkout1_requested_duty_cycle=50.000\r
-CSET clkout1_requested_out_freq=40\r
-CSET clkout1_requested_phase=0.000\r
-CSET clkout2_drives=BUFG\r
-CSET clkout2_requested_duty_cycle=50.000\r
-CSET clkout2_requested_out_freq=80\r
-CSET clkout2_requested_phase=0.000\r
-CSET clkout2_used=true\r
-CSET clkout3_drives=BUFG\r
-CSET clkout3_requested_duty_cycle=50.000\r
-CSET clkout3_requested_out_freq=100.000\r
-CSET clkout3_requested_phase=0.000\r
-CSET clkout3_used=false\r
-CSET clkout4_drives=BUFG\r
-CSET clkout4_requested_duty_cycle=50.000\r
-CSET clkout4_requested_out_freq=100.000\r
-CSET clkout4_requested_phase=0.000\r
-CSET clkout4_used=false\r
-CSET clkout5_drives=BUFG\r
-CSET clkout5_requested_duty_cycle=50.000\r
-CSET clkout5_requested_out_freq=100.000\r
-CSET clkout5_requested_phase=0.000\r
-CSET clkout5_used=false\r
-CSET clkout6_drives=BUFG\r
-CSET clkout6_requested_duty_cycle=50.000\r
-CSET clkout6_requested_out_freq=100.000\r
-CSET clkout6_requested_phase=0.000\r
-CSET clkout6_used=false\r
-CSET clkout7_drives=BUFG\r
-CSET clkout7_requested_duty_cycle=50.000\r
-CSET clkout7_requested_out_freq=100.000\r
-CSET clkout7_requested_phase=0.000\r
-CSET clkout7_used=false\r
-CSET clock_mgr_type=MANUAL\r
-CSET component_name=clockmodule40switch\r
-CSET daddr_port=DADDR\r
-CSET dclk_port=DCLK\r
-CSET dcm_clk_feedback=1X\r
-CSET dcm_clk_out1_port=CLK0\r
-CSET dcm_clk_out2_port=CLK0\r
-CSET dcm_clk_out3_port=CLK0\r
-CSET dcm_clk_out4_port=CLK0\r
-CSET dcm_clk_out5_port=CLK0\r
-CSET dcm_clk_out6_port=CLK0\r
-CSET dcm_clkdv_divide=2.0\r
-CSET dcm_clkfx_divide=1\r
-CSET dcm_clkfx_multiply=4\r
-CSET dcm_clkgen_clk_out1_port=CLKFX\r
-CSET dcm_clkgen_clk_out2_port=CLKFX\r
-CSET dcm_clkgen_clk_out3_port=CLKFX\r
-CSET dcm_clkgen_clkfx_divide=1\r
-CSET dcm_clkgen_clkfx_md_max=0.000\r
-CSET dcm_clkgen_clkfx_multiply=4\r
-CSET dcm_clkgen_clkfxdv_divide=2\r
-CSET dcm_clkgen_clkin_period=10.000\r
-CSET dcm_clkgen_notes=None\r
-CSET dcm_clkgen_spread_spectrum=NONE\r
-CSET dcm_clkgen_startup_wait=false\r
-CSET dcm_clkin_divide_by_2=false\r
-CSET dcm_clkin_period=10.000\r
-CSET dcm_clkout_phase_shift=NONE\r
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS\r
-CSET dcm_notes=None\r
-CSET dcm_phase_shift=0\r
-CSET dcm_pll_cascade=NONE\r
-CSET dcm_startup_wait=false\r
-CSET den_port=DEN\r
-CSET din_port=DIN\r
-CSET dout_port=DOUT\r
-CSET drdy_port=DRDY\r
-CSET dwe_port=DWE\r
-CSET feedback_source=FDBK_AUTO\r
-CSET in_freq_units=Units_MHz\r
-CSET in_jitter_units=Units_UI\r
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED\r
-CSET jitter_options=UI\r
-CSET jitter_sel=No_Jitter\r
-CSET locked_port=LOCKED\r
-CSET mmcm_bandwidth=OPTIMIZED\r
-CSET mmcm_clkfbout_mult_f=24.000\r
-CSET mmcm_clkfbout_phase=0.000\r
-CSET mmcm_clkfbout_use_fine_ps=false\r
-CSET mmcm_clkin1_period=25.000\r
-CSET mmcm_clkin2_period=25.000\r
-CSET mmcm_clkout0_divide_f=24.000\r
-CSET mmcm_clkout0_duty_cycle=0.500\r
-CSET mmcm_clkout0_phase=0.000\r
-CSET mmcm_clkout0_use_fine_ps=false\r
-CSET mmcm_clkout1_divide=12\r
-CSET mmcm_clkout1_duty_cycle=0.500\r
-CSET mmcm_clkout1_phase=0.000\r
-CSET mmcm_clkout1_use_fine_ps=false\r
-CSET mmcm_clkout2_divide=1\r
-CSET mmcm_clkout2_duty_cycle=0.500\r
-CSET mmcm_clkout2_phase=0.000\r
-CSET mmcm_clkout2_use_fine_ps=false\r
-CSET mmcm_clkout3_divide=1\r
-CSET mmcm_clkout3_duty_cycle=0.500\r
-CSET mmcm_clkout3_phase=0.000\r
-CSET mmcm_clkout3_use_fine_ps=false\r
-CSET mmcm_clkout4_cascade=false\r
-CSET mmcm_clkout4_divide=1\r
-CSET mmcm_clkout4_duty_cycle=0.500\r
-CSET mmcm_clkout4_phase=0.000\r
-CSET mmcm_clkout4_use_fine_ps=false\r
-CSET mmcm_clkout5_divide=1\r
-CSET mmcm_clkout5_duty_cycle=0.500\r
-CSET mmcm_clkout5_phase=0.000\r
-CSET mmcm_clkout5_use_fine_ps=false\r
-CSET mmcm_clkout6_divide=1\r
-CSET mmcm_clkout6_duty_cycle=0.500\r
-CSET mmcm_clkout6_phase=0.000\r
-CSET mmcm_clkout6_use_fine_ps=false\r
-CSET mmcm_clock_hold=false\r
-CSET mmcm_compensation=ZHOLD\r
-CSET mmcm_divclk_divide=1\r
-CSET mmcm_notes=None\r
-CSET mmcm_ref_jitter1=0.010\r
-CSET mmcm_ref_jitter2=0.010\r
-CSET mmcm_startup_wait=false\r
-CSET num_out_clks=2\r
-CSET override_dcm=false\r
-CSET override_dcm_clkgen=false\r
-CSET override_mmcm=false\r
-CSET override_pll=false\r
-CSET platform=nt64\r
-CSET pll_bandwidth=OPTIMIZED\r
-CSET pll_clk_feedback=CLKFBOUT\r
-CSET pll_clkfbout_mult=4\r
-CSET pll_clkfbout_phase=0.000\r
-CSET pll_clkin_period=10.000\r
-CSET pll_clkout0_divide=1\r
-CSET pll_clkout0_duty_cycle=0.500\r
-CSET pll_clkout0_phase=0.000\r
-CSET pll_clkout1_divide=1\r
-CSET pll_clkout1_duty_cycle=0.500\r
-CSET pll_clkout1_phase=0.000\r
-CSET pll_clkout2_divide=1\r
-CSET pll_clkout2_duty_cycle=0.500\r
-CSET pll_clkout2_phase=0.000\r
-CSET pll_clkout3_divide=1\r
-CSET pll_clkout3_duty_cycle=0.500\r
-CSET pll_clkout3_phase=0.000\r
-CSET pll_clkout4_divide=1\r
-CSET pll_clkout4_duty_cycle=0.500\r
-CSET pll_clkout4_phase=0.000\r
-CSET pll_clkout5_divide=1\r
-CSET pll_clkout5_duty_cycle=0.500\r
-CSET pll_clkout5_phase=0.000\r
-CSET pll_compensation=SYSTEM_SYNCHRONOUS\r
-CSET pll_divclk_divide=1\r
-CSET pll_notes=None\r
-CSET pll_ref_jitter=0.010\r
-CSET power_down_port=POWER_DOWN\r
-CSET prim_in_freq=40\r
-CSET prim_in_jitter=0.010\r
-CSET prim_source=Global_buffer\r
-CSET primary_port=CLK_IN1\r
-CSET primitive=MMCM\r
-CSET primtype_sel=MMCM_ADV\r
-CSET psclk_port=PSCLK\r
-CSET psdone_port=PSDONE\r
-CSET psen_port=PSEN\r
-CSET psincdec_port=PSINCDEC\r
-CSET relative_inclk=REL_PRIMARY\r
-CSET reset_port=RESET\r
-CSET secondary_in_freq=40\r
-CSET secondary_in_jitter=0.010\r
-CSET secondary_port=CLK_IN2\r
-CSET secondary_source=Global_buffer\r
-CSET ss_mod_freq=250\r
-CSET ss_mode=CENTER_HIGH\r
-CSET status_port=STATUS\r
-CSET summary_strings=empty\r
-CSET use_clk_valid=false\r
-CSET use_clkfb_stopped=false\r
-CSET use_dyn_phase_shift=false\r
-CSET use_dyn_reconfig=false\r
-CSET use_freeze=false\r
-CSET use_freq_synth=true\r
-CSET use_inclk_stopped=false\r
-CSET use_inclk_switchover=true\r
-CSET use_locked=true\r
-CSET use_max_i_jitter=false\r
-CSET use_min_o_jitter=false\r
-CSET use_min_power=false\r
-CSET use_phase_alignment=true\r
-CSET use_power_down=false\r
-CSET use_reset=true\r
-CSET use_spread_spectrum=false\r
-CSET use_spread_spectrum_1=false\r
-CSET use_status=false\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2012-05-10T12:44:55Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: 41fd2223\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="clockmodule40switch.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="clockmodule40switch.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clockmodule40switch|xilinx" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="clockmodule40switch.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clockmodule40switch" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="clockmodule40switch" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-26T09:55:02" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1222C6006EB742BD9905A04365D9D9E4" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings>
- <binding xil_pn:location="/clockmodule40switch" xil_pn:name="clockmodule40switch.ucf"/>
- </bindings>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 clockmodule80M
-RECTANGLE Normal 32 32 576 1088
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk_in1
-PINATTR Polarity IN
-LINE Normal 608 80 576 80
-PIN 608 80 RIGHT 36
-PINATTR PinName clk_out1
-PINATTR Polarity OUT
-LINE Normal 608 976 576 976
-PIN 608 976 RIGHT 36
-PINATTR PinName locked
-PINATTR Polarity OUT
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
-\r
- <!-- -->\r
-\r
- <!-- For tool use only. Do not edit. -->\r
-\r
- <!-- -->\r
-\r
- <!-- ProjectNavigator created generated project file. -->\r
-\r
- <!-- For use in tracking generated file and other information -->\r
-\r
- <!-- allowing preservation of process status. -->\r
-\r
- <!-- -->\r
-\r
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
-\r
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
-\r
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clockmodule80M.xise"/>\r
-\r
- <files xmlns="http://www.xilinx.com/XMLSchema">\r
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="clockmodule80M.asy" xil_pn:origination="imported"/>\r
- <file xil_pn:fileType="FILE_VHO" xil_pn:name="clockmodule80M.vho" xil_pn:origination="imported"/>\r
- </files>\r
-\r
- <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
- <transform xil_pn:end_ts="1409562302" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1409562302">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4328670307819663427" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5868735601060516189" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="136310429885004787" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- </transforms>\r
-\r
-</generated_project>\r
+++ /dev/null
-# file: clockmodule80M.ucf\r
-# \r
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
-# \r
-# This file contains confidential and proprietary information\r
-# of Xilinx, Inc. and is protected under U.S. and\r
-# international copyright and other intellectual property\r
-# laws.\r
-# \r
-# DISCLAIMER\r
-# This disclaimer is not a license and does not grant any\r
-# rights to the materials distributed herewith. Except as\r
-# otherwise provided in a valid license issued to you by\r
-# Xilinx, and to the maximum extent permitted by applicable\r
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-# (2) Xilinx shall not be liable (whether in contract or tort,\r
-# including negligence, or under any other theory of\r
-# liability) for any loss or damage of any kind or nature\r
-# related to, arising under or in connection with these\r
-# materials, including for any direct, or any indirect,\r
-# special, incidental, or consequential loss or damage\r
-# (including loss of data, profits, goodwill, or any type of\r
-# loss or damage suffered as a result of any action brought\r
-# by a third party) even if such damage or loss was\r
-# reasonably foreseeable or Xilinx had been advised of the\r
-# possibility of the same.\r
-# \r
-# CRITICAL APPLICATIONS\r
-# Xilinx products are not designed or intended to be fail-\r
-# safe, or for use in any application requiring fail-safe\r
-# performance, such as life-support or safety devices or\r
-# systems, Class III medical devices, nuclear facilities,\r
-# applications related to the deployment of airbags, or any\r
-# other applications that could lead to death, personal\r
-# injury, or severe property or environmental damage\r
-# (individually and collectively, "Critical\r
-# Applications"). Customer assumes the sole risk and\r
-# liability of any use of Xilinx products in Critical\r
-# Applications, subject only to applicable laws and\r
-# regulations governing limitations on product liability.\r
-# \r
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-# PART OF THIS FILE AT ALL TIMES.\r
-# \r
-\r
-# Input clock periods. These duplicate the values entered for the\r
-# input clocks. You can use these to time your system\r
-#----------------------------------------------------------------\r
-NET "CLK_IN1" TNM_NET = "CLK_IN1";\r
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 6.430 ns HIGH 50% INPUT_JITTER 64.3ps;\r
-\r
-\r
-# FALSE PATH constraints \r
-\r
+++ /dev/null
--- \r
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
--- \r
-------------------------------------------------------------------------------\r
--- User entered comments\r
-------------------------------------------------------------------------------\r
--- None\r
---\r
-------------------------------------------------------------------------------\r
--- "Output Output Phase Duty Pk-to-Pk Phase"\r
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
-------------------------------------------------------------------------------\r
--- CLK_OUT1____99.999______0.000______50.0______144.151____174.045\r
---\r
-------------------------------------------------------------------------------\r
--- "Input Clock Freq (MHz) Input Jitter (UI)"\r
-------------------------------------------------------------------------------\r
--- __primary__________155.52____________0.010\r
-\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-component clockmodule80M\r
-port\r
- (-- Clock in ports\r
- CLK_IN1 : in std_logic;\r
- -- Clock out ports\r
- CLK_OUT1 : out std_logic;\r
- -- Status and control signals\r
- LOCKED : out std_logic\r
- );\r
-end component;\r
-\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : clockmodule80M\r
- port map\r
- (-- Clock in ports\r
- CLK_IN1 => CLK_IN1,\r
- -- Clock out ports\r
- CLK_OUT1 => CLK_OUT1,\r
- -- Status and control signals\r
- LOCKED => LOCKED);\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Wed Nov 26 08:35:23 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:clk_wiz:3.6\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6\r
-# END Select\r
-# BEGIN Parameters\r
-CSET calc_done=DONE\r
-CSET clk_in_sel_port=CLK_IN_SEL\r
-CSET clk_out1_port=CLK_OUT1\r
-CSET clk_out1_use_fine_ps_gui=false\r
-CSET clk_out2_port=CLK_OUT2\r
-CSET clk_out2_use_fine_ps_gui=false\r
-CSET clk_out3_port=CLK_OUT3\r
-CSET clk_out3_use_fine_ps_gui=false\r
-CSET clk_out4_port=CLK_OUT4\r
-CSET clk_out4_use_fine_ps_gui=false\r
-CSET clk_out5_port=CLK_OUT5\r
-CSET clk_out5_use_fine_ps_gui=false\r
-CSET clk_out6_port=CLK_OUT6\r
-CSET clk_out6_use_fine_ps_gui=false\r
-CSET clk_out7_port=CLK_OUT7\r
-CSET clk_out7_use_fine_ps_gui=false\r
-CSET clk_valid_port=CLK_VALID\r
-CSET clkfb_in_n_port=CLKFB_IN_N\r
-CSET clkfb_in_p_port=CLKFB_IN_P\r
-CSET clkfb_in_port=CLKFB_IN\r
-CSET clkfb_in_signaling=SINGLE\r
-CSET clkfb_out_n_port=CLKFB_OUT_N\r
-CSET clkfb_out_p_port=CLKFB_OUT_P\r
-CSET clkfb_out_port=CLKFB_OUT\r
-CSET clkfb_stopped_port=CLKFB_STOPPED\r
-CSET clkin1_jitter_ps=64.3\r
-CSET clkin1_ui_jitter=0.010\r
-CSET clkin2_jitter_ps=100.0\r
-CSET clkin2_ui_jitter=0.010\r
-CSET clkout1_drives=BUFG\r
-CSET clkout1_requested_duty_cycle=50.000\r
-CSET clkout1_requested_out_freq=100\r
-CSET clkout1_requested_phase=0.000\r
-CSET clkout2_drives=BUFG\r
-CSET clkout2_requested_duty_cycle=50.000\r
-CSET clkout2_requested_out_freq=100.000\r
-CSET clkout2_requested_phase=0.000\r
-CSET clkout2_used=false\r
-CSET clkout3_drives=BUFG\r
-CSET clkout3_requested_duty_cycle=50.000\r
-CSET clkout3_requested_out_freq=100.000\r
-CSET clkout3_requested_phase=0.000\r
-CSET clkout3_used=false\r
-CSET clkout4_drives=BUFG\r
-CSET clkout4_requested_duty_cycle=50.000\r
-CSET clkout4_requested_out_freq=100.000\r
-CSET clkout4_requested_phase=0.000\r
-CSET clkout4_used=false\r
-CSET clkout5_drives=BUFG\r
-CSET clkout5_requested_duty_cycle=50.000\r
-CSET clkout5_requested_out_freq=100.000\r
-CSET clkout5_requested_phase=0.000\r
-CSET clkout5_used=false\r
-CSET clkout6_drives=BUFG\r
-CSET clkout6_requested_duty_cycle=50.000\r
-CSET clkout6_requested_out_freq=100.000\r
-CSET clkout6_requested_phase=0.000\r
-CSET clkout6_used=false\r
-CSET clkout7_drives=BUFG\r
-CSET clkout7_requested_duty_cycle=50.000\r
-CSET clkout7_requested_out_freq=100.000\r
-CSET clkout7_requested_phase=0.000\r
-CSET clkout7_used=false\r
-CSET clock_mgr_type=MANUAL\r
-CSET component_name=clockmodule80M\r
-CSET daddr_port=DADDR\r
-CSET dclk_port=DCLK\r
-CSET dcm_clk_feedback=1X\r
-CSET dcm_clk_out1_port=CLK0\r
-CSET dcm_clk_out2_port=CLK0\r
-CSET dcm_clk_out3_port=CLK0\r
-CSET dcm_clk_out4_port=CLK0\r
-CSET dcm_clk_out5_port=CLK0\r
-CSET dcm_clk_out6_port=CLK0\r
-CSET dcm_clkdv_divide=2.0\r
-CSET dcm_clkfx_divide=1\r
-CSET dcm_clkfx_multiply=4\r
-CSET dcm_clkgen_clk_out1_port=CLKFX\r
-CSET dcm_clkgen_clk_out2_port=CLKFX\r
-CSET dcm_clkgen_clk_out3_port=CLKFX\r
-CSET dcm_clkgen_clkfx_divide=1\r
-CSET dcm_clkgen_clkfx_md_max=0.000\r
-CSET dcm_clkgen_clkfx_multiply=4\r
-CSET dcm_clkgen_clkfxdv_divide=2\r
-CSET dcm_clkgen_clkin_period=10.000\r
-CSET dcm_clkgen_notes=None\r
-CSET dcm_clkgen_spread_spectrum=NONE\r
-CSET dcm_clkgen_startup_wait=false\r
-CSET dcm_clkin_divide_by_2=false\r
-CSET dcm_clkin_period=10.000\r
-CSET dcm_clkout_phase_shift=NONE\r
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS\r
-CSET dcm_notes=None\r
-CSET dcm_phase_shift=0\r
-CSET dcm_pll_cascade=NONE\r
-CSET dcm_startup_wait=false\r
-CSET den_port=DEN\r
-CSET din_port=DIN\r
-CSET dout_port=DOUT\r
-CSET drdy_port=DRDY\r
-CSET dwe_port=DWE\r
-CSET feedback_source=FDBK_AUTO\r
-CSET in_freq_units=Units_MHz\r
-CSET in_jitter_units=Units_UI\r
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED\r
-CSET jitter_options=UI\r
-CSET jitter_sel=No_Jitter\r
-CSET locked_port=LOCKED\r
-CSET mmcm_bandwidth=OPTIMIZED\r
-CSET mmcm_clkfbout_mult_f=43.000\r
-CSET mmcm_clkfbout_phase=0.000\r
-CSET mmcm_clkfbout_use_fine_ps=false\r
-CSET mmcm_clkin1_period=6.430\r
-CSET mmcm_clkin2_period=10.000\r
-CSET mmcm_clkout0_divide_f=13.375\r
-CSET mmcm_clkout0_duty_cycle=0.500\r
-CSET mmcm_clkout0_phase=0.000\r
-CSET mmcm_clkout0_use_fine_ps=false\r
-CSET mmcm_clkout1_divide=1\r
-CSET mmcm_clkout1_duty_cycle=0.500\r
-CSET mmcm_clkout1_phase=0.000\r
-CSET mmcm_clkout1_use_fine_ps=false\r
-CSET mmcm_clkout2_divide=1\r
-CSET mmcm_clkout2_duty_cycle=0.500\r
-CSET mmcm_clkout2_phase=0.000\r
-CSET mmcm_clkout2_use_fine_ps=false\r
-CSET mmcm_clkout3_divide=1\r
-CSET mmcm_clkout3_duty_cycle=0.500\r
-CSET mmcm_clkout3_phase=0.000\r
-CSET mmcm_clkout3_use_fine_ps=false\r
-CSET mmcm_clkout4_cascade=false\r
-CSET mmcm_clkout4_divide=1\r
-CSET mmcm_clkout4_duty_cycle=0.500\r
-CSET mmcm_clkout4_phase=0.000\r
-CSET mmcm_clkout4_use_fine_ps=false\r
-CSET mmcm_clkout5_divide=1\r
-CSET mmcm_clkout5_duty_cycle=0.500\r
-CSET mmcm_clkout5_phase=0.000\r
-CSET mmcm_clkout5_use_fine_ps=false\r
-CSET mmcm_clkout6_divide=1\r
-CSET mmcm_clkout6_duty_cycle=0.500\r
-CSET mmcm_clkout6_phase=0.000\r
-CSET mmcm_clkout6_use_fine_ps=false\r
-CSET mmcm_clock_hold=false\r
-CSET mmcm_compensation=ZHOLD\r
-CSET mmcm_divclk_divide=5\r
-CSET mmcm_notes=None\r
-CSET mmcm_ref_jitter1=0.010\r
-CSET mmcm_ref_jitter2=0.010\r
-CSET mmcm_startup_wait=false\r
-CSET num_out_clks=1\r
-CSET override_dcm=false\r
-CSET override_dcm_clkgen=false\r
-CSET override_mmcm=false\r
-CSET override_pll=false\r
-CSET platform=nt64\r
-CSET pll_bandwidth=OPTIMIZED\r
-CSET pll_clk_feedback=CLKFBOUT\r
-CSET pll_clkfbout_mult=4\r
-CSET pll_clkfbout_phase=0.000\r
-CSET pll_clkin_period=10.000\r
-CSET pll_clkout0_divide=1\r
-CSET pll_clkout0_duty_cycle=0.500\r
-CSET pll_clkout0_phase=0.000\r
-CSET pll_clkout1_divide=1\r
-CSET pll_clkout1_duty_cycle=0.500\r
-CSET pll_clkout1_phase=0.000\r
-CSET pll_clkout2_divide=1\r
-CSET pll_clkout2_duty_cycle=0.500\r
-CSET pll_clkout2_phase=0.000\r
-CSET pll_clkout3_divide=1\r
-CSET pll_clkout3_duty_cycle=0.500\r
-CSET pll_clkout3_phase=0.000\r
-CSET pll_clkout4_divide=1\r
-CSET pll_clkout4_duty_cycle=0.500\r
-CSET pll_clkout4_phase=0.000\r
-CSET pll_clkout5_divide=1\r
-CSET pll_clkout5_duty_cycle=0.500\r
-CSET pll_clkout5_phase=0.000\r
-CSET pll_compensation=SYSTEM_SYNCHRONOUS\r
-CSET pll_divclk_divide=1\r
-CSET pll_notes=None\r
-CSET pll_ref_jitter=0.010\r
-CSET power_down_port=POWER_DOWN\r
-CSET prim_in_freq=155.52\r
-CSET prim_in_jitter=0.010\r
-CSET prim_source=No_buffer\r
-CSET primary_port=CLK_IN1\r
-CSET primitive=MMCM\r
-CSET primtype_sel=MMCM_ADV\r
-CSET psclk_port=PSCLK\r
-CSET psdone_port=PSDONE\r
-CSET psen_port=PSEN\r
-CSET psincdec_port=PSINCDEC\r
-CSET relative_inclk=REL_PRIMARY\r
-CSET reset_port=RESET\r
-CSET secondary_in_freq=100.000\r
-CSET secondary_in_jitter=0.010\r
-CSET secondary_port=CLK_IN2\r
-CSET secondary_source=Single_ended_clock_capable_pin\r
-CSET ss_mod_freq=250\r
-CSET ss_mode=CENTER_HIGH\r
-CSET status_port=STATUS\r
-CSET summary_strings=empty\r
-CSET use_clk_valid=false\r
-CSET use_clkfb_stopped=false\r
-CSET use_dyn_phase_shift=false\r
-CSET use_dyn_reconfig=false\r
-CSET use_freeze=false\r
-CSET use_freq_synth=true\r
-CSET use_inclk_stopped=false\r
-CSET use_inclk_switchover=false\r
-CSET use_locked=true\r
-CSET use_max_i_jitter=false\r
-CSET use_min_o_jitter=false\r
-CSET use_min_power=false\r
-CSET use_phase_alignment=true\r
-CSET use_power_down=false\r
-CSET use_reset=false\r
-CSET use_spread_spectrum=false\r
-CSET use_spread_spectrum_1=false\r
-CSET use_status=false\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2012-05-10T12:44:55Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: c8df1962\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="clockmodule80M.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="clockmodule80M.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clockmodule80M|xilinx" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="clockmodule80M.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clockmodule80M" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="clockmodule80M" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-26T09:35:49" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A77989C9A5740C8BC9FB6A41BD011E7" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings>
- <binding xil_pn:location="/clockmodule80M" xil_pn:name="clockmodule80M.ucf"/>
- </bindings>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 clockmodule80to80M
-RECTANGLE Normal 32 32 576 1088
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk_in1
-PINATTR Polarity IN
-LINE Normal 0 432 32 432
-PIN 0 432 LEFT 36
-PINATTR PinName reset
-PINATTR Polarity IN
-LINE Normal 608 80 576 80
-PIN 608 80 RIGHT 36
-PINATTR PinName clk_out1
-PINATTR Polarity OUT
-LINE Normal 608 176 576 176
-PIN 608 176 RIGHT 36
-PINATTR PinName clk_out2
-PINATTR Polarity OUT
-LINE Normal 608 272 576 272
-PIN 608 272 RIGHT 36
-PINATTR PinName clk_out3
-PINATTR Polarity OUT
-LINE Normal 608 368 576 368
-PIN 608 368 RIGHT 36
-PINATTR PinName clk_out4
-PINATTR Polarity OUT
-LINE Normal 608 976 576 976
-PIN 608 976 RIGHT 36
-PINATTR PinName locked
-PINATTR Polarity OUT
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
-\r
- <!-- -->\r
-\r
- <!-- For tool use only. Do not edit. -->\r
-\r
- <!-- -->\r
-\r
- <!-- ProjectNavigator created generated project file. -->\r
-\r
- <!-- For use in tracking generated file and other information -->\r
-\r
- <!-- allowing preservation of process status. -->\r
-\r
- <!-- -->\r
-\r
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
-\r
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
-\r
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clockmodule80to80M.xise"/>\r
-\r
- <files xmlns="http://www.xilinx.com/XMLSchema">\r
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="clockmodule80to80M.asy" xil_pn:origination="imported"/>\r
- <file xil_pn:fileType="FILE_VHO" xil_pn:name="clockmodule80to80M.vho" xil_pn:origination="imported"/>\r
- </files>\r
-\r
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- <status xil_pn:value="SuccessfullyRun"/>\r
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- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6677609659508388402" xil_pn:start_ts="1418036842">\r
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+++ /dev/null
-# file: clockmodule80to80M.ucf\r
-# \r
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
-# \r
-# This file contains confidential and proprietary information\r
-# of Xilinx, Inc. and is protected under U.S. and\r
-# international copyright and other intellectual property\r
-# laws.\r
-# \r
-# DISCLAIMER\r
-# This disclaimer is not a license and does not grant any\r
-# rights to the materials distributed herewith. Except as\r
-# otherwise provided in a valid license issued to you by\r
-# Xilinx, and to the maximum extent permitted by applicable\r
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-# (2) Xilinx shall not be liable (whether in contract or tort,\r
-# including negligence, or under any other theory of\r
-# liability) for any loss or damage of any kind or nature\r
-# related to, arising under or in connection with these\r
-# materials, including for any direct, or any indirect,\r
-# special, incidental, or consequential loss or damage\r
-# (including loss of data, profits, goodwill, or any type of\r
-# loss or damage suffered as a result of any action brought\r
-# by a third party) even if such damage or loss was\r
-# reasonably foreseeable or Xilinx had been advised of the\r
-# possibility of the same.\r
-# \r
-# CRITICAL APPLICATIONS\r
-# Xilinx products are not designed or intended to be fail-\r
-# safe, or for use in any application requiring fail-safe\r
-# performance, such as life-support or safety devices or\r
-# systems, Class III medical devices, nuclear facilities,\r
-# applications related to the deployment of airbags, or any\r
-# other applications that could lead to death, personal\r
-# injury, or severe property or environmental damage\r
-# (individually and collectively, "Critical\r
-# Applications"). Customer assumes the sole risk and\r
-# liability of any use of Xilinx products in Critical\r
-# Applications, subject only to applicable laws and\r
-# regulations governing limitations on product liability.\r
-# \r
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-# PART OF THIS FILE AT ALL TIMES.\r
-# \r
-\r
-# Input clock periods. These duplicate the values entered for the\r
-# input clocks. You can use these to time your system\r
-#----------------------------------------------------------------\r
-NET "CLK_IN1" TNM_NET = "CLK_IN1";\r
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 10.000 ns HIGH 50% INPUT_JITTER 100.0ps;\r
-\r
-\r
-# FALSE PATH constraints \r
-PIN "RESET" TIG;\r
-\r
+++ /dev/null
--- \r
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
--- \r
-------------------------------------------------------------------------------\r
--- User entered comments\r
-------------------------------------------------------------------------------\r
--- None\r
---\r
-------------------------------------------------------------------------------\r
--- "Output Output Phase Duty Pk-to-Pk Phase"\r
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
-------------------------------------------------------------------------------\r
--- CLK_OUT1____40.000______0.000______50.0______174.629____114.212\r
--- CLK_OUT2____80.000______0.000______50.0______151.652____114.212\r
--- CLK_OUT3___100.000______0.000______50.0______144.719____114.212\r
--- CLK_OUT4___200.000______0.000______50.0______126.455____114.212\r
---\r
-------------------------------------------------------------------------------\r
--- "Input Clock Freq (MHz) Input Jitter (UI)"\r
-------------------------------------------------------------------------------\r
--- __primary_____________100____________0.010\r
-\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-component clockmodule80to80M\r
-port\r
- (-- Clock in ports\r
- CLK_IN1 : in std_logic;\r
- -- Clock out ports\r
- CLK_OUT1 : out std_logic;\r
- CLK_OUT2 : out std_logic;\r
- CLK_OUT3 : out std_logic;\r
- CLK_OUT4 : out std_logic;\r
- -- Status and control signals\r
- RESET : in std_logic;\r
- LOCKED : out std_logic\r
- );\r
-end component;\r
-\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : clockmodule80to80M\r
- port map\r
- (-- Clock in ports\r
- CLK_IN1 => CLK_IN1,\r
- -- Clock out ports\r
- CLK_OUT1 => CLK_OUT1,\r
- CLK_OUT2 => CLK_OUT2,\r
- CLK_OUT3 => CLK_OUT3,\r
- CLK_OUT4 => CLK_OUT4,\r
- -- Status and control signals\r
- RESET => RESET,\r
- LOCKED => LOCKED);\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Wed Nov 26 08:36:53 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:clk_wiz:3.6\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6\r
-# END Select\r
-# BEGIN Parameters\r
-CSET calc_done=DONE\r
-CSET clk_in_sel_port=CLK_IN_SEL\r
-CSET clk_out1_port=CLK_OUT1\r
-CSET clk_out1_use_fine_ps_gui=false\r
-CSET clk_out2_port=CLK_OUT2\r
-CSET clk_out2_use_fine_ps_gui=false\r
-CSET clk_out3_port=CLK_OUT3\r
-CSET clk_out3_use_fine_ps_gui=false\r
-CSET clk_out4_port=CLK_OUT4\r
-CSET clk_out4_use_fine_ps_gui=false\r
-CSET clk_out5_port=CLK_OUT5\r
-CSET clk_out5_use_fine_ps_gui=false\r
-CSET clk_out6_port=CLK_OUT6\r
-CSET clk_out6_use_fine_ps_gui=false\r
-CSET clk_out7_port=CLK_OUT7\r
-CSET clk_out7_use_fine_ps_gui=false\r
-CSET clk_valid_port=CLK_VALID\r
-CSET clkfb_in_n_port=CLKFB_IN_N\r
-CSET clkfb_in_p_port=CLKFB_IN_P\r
-CSET clkfb_in_port=CLKFB_IN\r
-CSET clkfb_in_signaling=SINGLE\r
-CSET clkfb_out_n_port=CLKFB_OUT_N\r
-CSET clkfb_out_p_port=CLKFB_OUT_P\r
-CSET clkfb_out_port=CLKFB_OUT\r
-CSET clkfb_stopped_port=CLKFB_STOPPED\r
-CSET clkin1_jitter_ps=100.0\r
-CSET clkin1_ui_jitter=0.010\r
-CSET clkin2_jitter_ps=100.0\r
-CSET clkin2_ui_jitter=0.010\r
-CSET clkout1_drives=BUFG\r
-CSET clkout1_requested_duty_cycle=50.000\r
-CSET clkout1_requested_out_freq=40.000\r
-CSET clkout1_requested_phase=0.000\r
-CSET clkout2_drives=BUFG\r
-CSET clkout2_requested_duty_cycle=50.000\r
-CSET clkout2_requested_out_freq=80.000\r
-CSET clkout2_requested_phase=0.000\r
-CSET clkout2_used=true\r
-CSET clkout3_drives=BUFG\r
-CSET clkout3_requested_duty_cycle=50.000\r
-CSET clkout3_requested_out_freq=100.000\r
-CSET clkout3_requested_phase=0.000\r
-CSET clkout3_used=true\r
-CSET clkout4_drives=BUFG\r
-CSET clkout4_requested_duty_cycle=50.000\r
-CSET clkout4_requested_out_freq=200\r
-CSET clkout4_requested_phase=0.000\r
-CSET clkout4_used=true\r
-CSET clkout5_drives=BUFG\r
-CSET clkout5_requested_duty_cycle=50.000\r
-CSET clkout5_requested_out_freq=200.000\r
-CSET clkout5_requested_phase=0.000\r
-CSET clkout5_used=false\r
-CSET clkout6_drives=BUFG\r
-CSET clkout6_requested_duty_cycle=50.000\r
-CSET clkout6_requested_out_freq=100.000\r
-CSET clkout6_requested_phase=0.000\r
-CSET clkout6_used=false\r
-CSET clkout7_drives=BUFG\r
-CSET clkout7_requested_duty_cycle=50.000\r
-CSET clkout7_requested_out_freq=100.000\r
-CSET clkout7_requested_phase=0.000\r
-CSET clkout7_used=false\r
-CSET clock_mgr_type=MANUAL\r
-CSET component_name=clockmodule80to80M\r
-CSET daddr_port=DADDR\r
-CSET dclk_port=DCLK\r
-CSET dcm_clk_feedback=1X\r
-CSET dcm_clk_out1_port=CLK0\r
-CSET dcm_clk_out2_port=CLK0\r
-CSET dcm_clk_out3_port=CLK0\r
-CSET dcm_clk_out4_port=CLK0\r
-CSET dcm_clk_out5_port=CLK0\r
-CSET dcm_clk_out6_port=CLK0\r
-CSET dcm_clkdv_divide=2.0\r
-CSET dcm_clkfx_divide=1\r
-CSET dcm_clkfx_multiply=4\r
-CSET dcm_clkgen_clk_out1_port=CLKFX\r
-CSET dcm_clkgen_clk_out2_port=CLKFX\r
-CSET dcm_clkgen_clk_out3_port=CLKFX\r
-CSET dcm_clkgen_clkfx_divide=1\r
-CSET dcm_clkgen_clkfx_md_max=0.000\r
-CSET dcm_clkgen_clkfx_multiply=4\r
-CSET dcm_clkgen_clkfxdv_divide=2\r
-CSET dcm_clkgen_clkin_period=10.000\r
-CSET dcm_clkgen_notes=None\r
-CSET dcm_clkgen_spread_spectrum=NONE\r
-CSET dcm_clkgen_startup_wait=false\r
-CSET dcm_clkin_divide_by_2=false\r
-CSET dcm_clkin_period=10.000\r
-CSET dcm_clkout_phase_shift=NONE\r
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS\r
-CSET dcm_notes=None\r
-CSET dcm_phase_shift=0\r
-CSET dcm_pll_cascade=NONE\r
-CSET dcm_startup_wait=false\r
-CSET den_port=DEN\r
-CSET din_port=DIN\r
-CSET dout_port=DOUT\r
-CSET drdy_port=DRDY\r
-CSET dwe_port=DWE\r
-CSET feedback_source=FDBK_AUTO\r
-CSET in_freq_units=Units_MHz\r
-CSET in_jitter_units=Units_UI\r
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED\r
-CSET jitter_options=UI\r
-CSET jitter_sel=No_Jitter\r
-CSET locked_port=LOCKED\r
-CSET mmcm_bandwidth=OPTIMIZED\r
-CSET mmcm_clkfbout_mult_f=8.000\r
-CSET mmcm_clkfbout_phase=0.000\r
-CSET mmcm_clkfbout_use_fine_ps=false\r
-CSET mmcm_clkin1_period=10.000\r
-CSET mmcm_clkin2_period=10.000\r
-CSET mmcm_clkout0_divide_f=20.000\r
-CSET mmcm_clkout0_duty_cycle=0.500\r
-CSET mmcm_clkout0_phase=0.000\r
-CSET mmcm_clkout0_use_fine_ps=false\r
-CSET mmcm_clkout1_divide=10\r
-CSET mmcm_clkout1_duty_cycle=0.500\r
-CSET mmcm_clkout1_phase=0.000\r
-CSET mmcm_clkout1_use_fine_ps=false\r
-CSET mmcm_clkout2_divide=8\r
-CSET mmcm_clkout2_duty_cycle=0.500\r
-CSET mmcm_clkout2_phase=0.000\r
-CSET mmcm_clkout2_use_fine_ps=false\r
-CSET mmcm_clkout3_divide=4\r
-CSET mmcm_clkout3_duty_cycle=0.500\r
-CSET mmcm_clkout3_phase=0.000\r
-CSET mmcm_clkout3_use_fine_ps=false\r
-CSET mmcm_clkout4_cascade=false\r
-CSET mmcm_clkout4_divide=4\r
-CSET mmcm_clkout4_duty_cycle=0.500\r
-CSET mmcm_clkout4_phase=0.000\r
-CSET mmcm_clkout4_use_fine_ps=false\r
-CSET mmcm_clkout5_divide=1\r
-CSET mmcm_clkout5_duty_cycle=0.500\r
-CSET mmcm_clkout5_phase=0.000\r
-CSET mmcm_clkout5_use_fine_ps=false\r
-CSET mmcm_clkout6_divide=1\r
-CSET mmcm_clkout6_duty_cycle=0.500\r
-CSET mmcm_clkout6_phase=0.000\r
-CSET mmcm_clkout6_use_fine_ps=false\r
-CSET mmcm_clock_hold=false\r
-CSET mmcm_compensation=ZHOLD\r
-CSET mmcm_divclk_divide=1\r
-CSET mmcm_notes=None\r
-CSET mmcm_ref_jitter1=0.010\r
-CSET mmcm_ref_jitter2=0.010\r
-CSET mmcm_startup_wait=false\r
-CSET num_out_clks=4\r
-CSET override_dcm=false\r
-CSET override_dcm_clkgen=false\r
-CSET override_mmcm=false\r
-CSET override_pll=false\r
-CSET platform=nt64\r
-CSET pll_bandwidth=OPTIMIZED\r
-CSET pll_clk_feedback=CLKFBOUT\r
-CSET pll_clkfbout_mult=4\r
-CSET pll_clkfbout_phase=0.000\r
-CSET pll_clkin_period=10.000\r
-CSET pll_clkout0_divide=1\r
-CSET pll_clkout0_duty_cycle=0.500\r
-CSET pll_clkout0_phase=0.000\r
-CSET pll_clkout1_divide=1\r
-CSET pll_clkout1_duty_cycle=0.500\r
-CSET pll_clkout1_phase=0.000\r
-CSET pll_clkout2_divide=1\r
-CSET pll_clkout2_duty_cycle=0.500\r
-CSET pll_clkout2_phase=0.000\r
-CSET pll_clkout3_divide=1\r
-CSET pll_clkout3_duty_cycle=0.500\r
-CSET pll_clkout3_phase=0.000\r
-CSET pll_clkout4_divide=1\r
-CSET pll_clkout4_duty_cycle=0.500\r
-CSET pll_clkout4_phase=0.000\r
-CSET pll_clkout5_divide=1\r
-CSET pll_clkout5_duty_cycle=0.500\r
-CSET pll_clkout5_phase=0.000\r
-CSET pll_compensation=SYSTEM_SYNCHRONOUS\r
-CSET pll_divclk_divide=1\r
-CSET pll_notes=None\r
-CSET pll_ref_jitter=0.010\r
-CSET power_down_port=POWER_DOWN\r
-CSET prim_in_freq=100\r
-CSET prim_in_jitter=0.010\r
-CSET prim_source=No_buffer\r
-CSET primary_port=CLK_IN1\r
-CSET primitive=MMCM\r
-CSET primtype_sel=MMCM_ADV\r
-CSET psclk_port=PSCLK\r
-CSET psdone_port=PSDONE\r
-CSET psen_port=PSEN\r
-CSET psincdec_port=PSINCDEC\r
-CSET relative_inclk=REL_PRIMARY\r
-CSET reset_port=RESET\r
-CSET secondary_in_freq=100.000\r
-CSET secondary_in_jitter=0.010\r
-CSET secondary_port=CLK_IN2\r
-CSET secondary_source=Single_ended_clock_capable_pin\r
-CSET ss_mod_freq=250\r
-CSET ss_mode=CENTER_HIGH\r
-CSET status_port=STATUS\r
-CSET summary_strings=empty\r
-CSET use_clk_valid=false\r
-CSET use_clkfb_stopped=false\r
-CSET use_dyn_phase_shift=false\r
-CSET use_dyn_reconfig=false\r
-CSET use_freeze=false\r
-CSET use_freq_synth=true\r
-CSET use_inclk_stopped=false\r
-CSET use_inclk_switchover=false\r
-CSET use_locked=true\r
-CSET use_max_i_jitter=false\r
-CSET use_min_o_jitter=false\r
-CSET use_min_power=false\r
-CSET use_phase_alignment=true\r
-CSET use_power_down=false\r
-CSET use_reset=true\r
-CSET use_spread_spectrum=false\r
-CSET use_spread_spectrum_1=false\r
-CSET use_status=false\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2012-05-10T12:44:55Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: f0b0ba04\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="clockmodule80to80M.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="clockmodule80to80M.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clockmodule80to80M|xilinx" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="clockmodule80to80M.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clockmodule80to80M" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="clockmodule80to80M" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-26T09:37:18" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5931B5D0516D4A0896A5522B5D44137B" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings>
- <binding xil_pn:location="/clockmodule80to80M" xil_pn:name="clockmodule80to80M.ucf"/>
- </bindings>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET package = ff484\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
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0;3xLg`33td9<=:50;3xLg`33td9<=;50;3xLg`33td9<=850;3xLg`33td9<=950;3xLg`33td9<=650;3xLg`33td9<=750;3xLg`33td9<=o50;3xLg`33td9<=l50;3xLg`33td9<=m50;3xLg`33td9<=j50;3xLg`33td9<=k50;3xLg`33td9<=h50;3xLg`33td9<<>50;3xLg`33td9<<?50;3xLg`33td9<<<50;3xLg`33td9<<=50;3xLg`33td9<<:50;3xLg`33td9<<;50;3xLg`33td9<<850;3xLg`33td9<<950;3xLg`33td9<<650;3xLg`33td9<<750;3xLg`33td9<<o50;3xLg`33td9<<l50;3xLg`33td9<<m50;3xLg`33td9<<j50;3xLg`33td9<<k50;3xLg`33td9<<h50;3xLg`33td9<?>50;3xLg`33td9<??50;3xLg`33td9<?<50;3xLg`33td9<?=50;3xLg`33td9<?:50;3xLg`33td9<?;50;3xLg`33td9<?850;3xLg`33td9<?950;3xLg`33td9<?650;3xLg`33td9<?750;3xLg`33td9<?o50;3xLg`33td9<?l50;3xLg`33td9<?m50;3xLg`33td9<?j50;3xLg`33td9<?k50;3xLg`33td9<?h50;3xLg`33td9<>>50;3xLg`33td9<>?50;3xLg`33td9<><50;3xLg`33td9<>=50;3xLg`33td9<>:50;3xLg`33td9<>;50;3xLg`33td9<>850;3xLg`33td9<>950;3xLg`33td9<>650;3xLg`33td9<>750;3xLg`33td9<>o50;3xLg`33td9<>l50;3xLg`33td9<>m50;3xLg`33td9<>j50;3xLg`33td9<>k50;3xLg`33td9<>h50;3xLg`33td9<9>50;3xLg`33td9<9?50;3xLg`33td9<9<50;3xLg`33td9<9=50;3xLg`33td9<9:50;3xLg`33td9<9;50;3xLg`33td9<9850;3xLg`33td9<9950;3xLg`33td9<9650;3xLg`33td9<9750;3xLg`33td9<9o50;3xLg`33td9<9l50;3xLg`33td9<9m50;3xLg`33td9<9j50;3xLg`33td9<9k50;3xLg`33td9<9h50;3xLg`33td9<8>50;3xLg`33td9<8?50;3xLg`33td9<8<50;3xLg`33td9<8=50;3xLg`33td9<8:50;3xLg`33td9<8;50;3xLg`33td9<8850;3xLg`33td9<8950;3xLg`33td9<8650;3xLg`33td9<8750;3xLg`33td9<8o50;3xLg`33td9<8l50;3xLg`33td9<8m50;3xLg`33td9<8j50;3xLg`33td9<8k50;3xLg`33td9<8h50;3xLg`33td9<;>50;3xLg`33td9<;?50;3xLg`33td9<;<50;3xLg`33td9<;=50;3xLg`33td9<;:50;3xLg`33td9<;;50;3xLg`33td9<;850;3xLg`33td9<;950;3xLg`33td9<;650;3xLg`33td9<;750;3xLg`33td9<;o50;3xLg`33td9<;l50;3xLg`33td9<;m50;3xLg`33td9<;j50;3xLg`33td9<;k50;3xLg`33td9<;h50;3xLg`33td9<:>50;3xLg`33td9<:?50;3xLg`33td9<:<50;3xLg`33td9<:=50;3xLg`33td9<::50;3xLg`33td9<:;50;3xLg`33td9<:850;3xLg`33td9<:950;3xLg`33td9<:650;3xLg`33td9<:750;3xLg`33td9<:o50;3xLg`33td9<:l50;3xLg`33td9<:m50;3xLg`33td9<:j50;3xLg`33td9<:k50;3xLg`33td9<:h50;3xLg`33td9<5>50;3xLg`33td9<5?50;3xLg`33td9<5<50;3xLg`33td9<5=50;3xLg`33td9<5:50;3xLg`33td9<5;50;3xLg`33td9<5850;3xLg`33td9<5950;3xLg`33td9<5650;3xLg`33td9<5750;3xLg`33td9<5o50;3xLg`33td9<5l50;3xLg`33td9<5m50;3xLg`33td9<5j50;3xLg`33td9<5k50;3xLg`33td9<5h50;3xLg`33td9<4>50;3xLg`33td9<4?50;3xLg`33td9<4<50;3xLg`33td9<4=50;3xLg`33td9<4:50;3xLg`33td9<4;50;3xLg`33td9<4850;3xLg`33td9<4950;3xLg`33td9<4650;3xLg`33td9<4750;3xLg`33td9<4o50;3xLg`33td9<4l50;3xLg`33td9<4m50;3xLg`33td9<4j50;3xLg`33td9<4k50;3xLg`33td9<4h50;3xLg`33td9<l>50;3xLg`33td9<l?50;3xLg`33td9<l<50;3xLg`33td9<l=50;3xLg`33td9<l:50;3xLg`33td9<l;50;3xLg`33td9<l850;3xLg`33td9<l950;3xLg`33td9<l650;3xLg`33td9<l750;3xLg`33td9<lo50;3xLg`33td9<ll50;3xLg`33td9<lm50;3xLg`33td9<lj50;3xLg`33td9<lk50;3xLg`33td9<lh50;3xLg`33td9<o>50;3xLg`33td9<o?50;3xLg`33td9<o<50;3xLg`33td9<o=50;3xLg`33td9<o:50;3xLg`33td9<o;50;3xLg`33td9<o850;3xLg`33td9<o950;3xLg`33td9<o650;3xLg`33td9<o750;3xLg`33td9<oo50;3xLg`33td9<ol50;3xLg`33td9<om50;3xLg`33td9<oj50;3xLg`33td9<ok50;3xLg`33td9<oh50;3xLg`33td9<n>50;3xLg`33td9<n?50;3xLg`33td9<n<50;3xLg`33td9<n=50;3xLg`33td9<n:50;3xLg`33td9<n;50;3xLg`33td9<n850;3xLg`33td9<n950;3xLg`33td9<n650;3xLg`33td9<n750;3xLg`33td9<no50;3xLg`33td9<nl50;3xLg`33td9<nm50;3xLg`33td9<nj50;3xLg`33td9<nk50;3xLg`33td9<nh50;3xLg`33td9<i>50;3xLg`33td9<i?50;3xLg`33td9<i<50;3xLg`33td9<i=50;3xLg`33td9<i:50;3xLg`33td9<i;50;3xLg`33td9<i850;3xLg`33td9<i950;3xLg`33td9<i650;3xLg`33td9<i750;3xLg`33td9<io50;3xLg`33td9<il50;3xLg`33td9<im50;3xLg`33td9<ij50;3xLg`33td9<ik50;3xLg`33td9<ih50;3xLg`33td9<h>50;3xLg`33td9<h?50;3xLg`33td9<h<50;3xLg`33td9<h=50;3xLg`33td9<h:50;3xLg`33td9<h;50;3xLg`33td9<h850;3xLg`33td9<h950;3xLg`33td9<h650;3xLg`33td9<h750;3xLg`33td9<ho50;3xLg`33td9<hl50;3xLg`33td9<hm50;3xLg`33td9<hj50;3xLg`33td9<hk50;3xLg`33td9<hh50;3xLg`33td9<k>50;3xLg`33td9<k?50;3xLg`33td9<k<50;3xLg`33td9<k=50;3xLg`33td9<k:50;3xLg`33td9<k;50;3xLg`33td9<k850;3xLg`33td9<k950;3xLg`33td9<k650;3xLg`33td9<k750;3xLg`33td9<ko50;3xLg`33td9<kl50;3xLg`33td9<km50;3xLg`33td9<kj50;3xLg`33td9<kk50;3xLg`33td9<kh50;3xLg`33td9==>50;3xLg`33td9==?50;3xLg`33td9==<50;3xLg`33td9===50;3xLg`33td9==:50;3xLg`33td9==;50;3xLg`33td9==850;3xLg`33td9==950;3xLg`33td9==650;3xLg`33td9==750;3xLg`33td9==o50;3xLg`33td9==l50;3xLg`33td9==m50;3xLg`33td9==j50;3xLg`33td9==k50;3xLg`33td9==h50;3xLg`33td9=<>50;3xLg`33td9=<?50;3xLg`33td9=<<50;3xLg`33td9=<=50;3xLg`33td9=<:50;3xLg`33td9=<;50;3xLg`33td9=<850;3xLg`33td9=<950;3xLg`33td9=<650;3xLg`33td9=<750;3xLg`33td9=<o50;3xLg`33td9=<l50;3xLg`33td9=<m50;3xLg`33td9=<j50;3xLg`33td9=<k50;3xLg`33td9=<h50;3xLg`33td9=?>50;3xLg`33td9=??50;3xLg`33td9=?<50;3xLg`33td9=?=50;3xLg`33td9=?:50;3xLg`33td9=?;50;3xLg`33td9=?850;3xLg`33td9=?950;3xLg`33td9=?650;3xLg`33td9=?750;3xLg`33td9=?o50;3xLg`33td9=?l50;3xLg`33td9=?m50;3xLg`33td9=?j50;3xLg`33td9=?k50;3xLg`33td9=?h50;3xLg`33td9=>>50;3xLg`33td9=>?50;3xLg`33td9=><50;3xLg`33td9=>=50;3xLg`33td9=>:50;3xLg`33td9=>;50;3xLg`33td9=>850;3xLg`33td9=>950;3xLg`33td9=>650;3xLg`33td9=>750;3xLg`33td9=>o50;3xLg`33td9=>l50;3xLg`33td9=>m50;3xLg`33td9=>j50;3xLg`33td9=>k50;3xLg`33td9=>h50;3xLg`33td9=9>50;3xLg`33td9=9?50;3xLg`33td9=9<50;3xLg`33td9=9=50;3xLg`33td9=9:50;3xLg`33td9=9;50;3xLg`33td9=9850;3xLg`33td9=9950;3xLg`33td9=9650;3xLg`33td9=9750;3xLg`33td9=9o50;3xLg`33td9=9l50;3xLg`33td9=9m50;3xLg`33td9=9j50;3xLg`33td9=9k50;3xLg`33td9=9h50;3xLg`33td9=8>50;3xLg`33td9=8?50;3xLg`33td9=8<50;3xLg`33td9=8=50;3xLg`33td9=8:50;3xLg`33td9=8;50;3xLg`33td9=8850;3xLg`33td9=8950;3xLg`33td9=8650;3xLg`33td9=8750;3xLg`33td9=8o50;3xLg`33td9=8l50;3xLg`33td9=8m50;3xLg`33td9=8j50;3xLg`33td9=8k50;3xLg`33td9=8h50;3xLg`33td9=;>50;3xLg`33td9=;?50;3xLg`33td9=;<50;3xLg`33td9=;=50;3xLg`33td9=;:50;3xLg`33td9=;;50;3xLg`33td9=;850;3xLg`33td9=;950;3xLg`33td9=;650;3xLg`33td9=;750;3xLg`33td9=;o50;3xLg`33td9=;l50;3xLg`33td9=;m50;3xLg`33td9=;j50;3xLg`33td9=;k50;3xLg`33td9=;h50;3xLg`33td9=:>50;3xLg`33td9=:?50;3xLg`33td9=:<50;3xLg`33td9=:=50;3xLg`33td9=::50;3xLg`33td9=:;50;3xLg`33td9=:850;3xLg`33td9=:950;3xLg`33td9=:650;3xLg`33td9=:750;3xLg`33td9=:o50;3xLg`33td9=:l50;3xLg`33td9=:m50;3xLg`33td9=:j50;3xLg`33td9=:k50;3xLg`33td9=:h50;3xLg`33td9=5>50;3xLg`33td9=5?50;3xLg`33td9=5<50;3xLg`33td9=5=50;3xLg`33td9=5:50;3xLg`33td9=5;50;3xLg`33td9=5850;3xLg`33td9=5950;3xLg`33td9=5650;3xLg`33td9=5750;3xLg`33td9=5o50;3xLg`33td9=5l50;3xLg`33td9=5m50;3xLg`33td9=5j50;3xLg`33td9=5k50;3xLg`33td9=5h50;3xLg`33td9=4>50;3xLg`33td9=4?50;3xLg`33td9=4<50;3xLg`33td9=4=50;3xLg`33td9=4:50;3xLg`33td9=4;50;3xLg`33td9=4850;3xLg`33td9=4950;3xLg`33td9=4650;3xLg`33td9=4750;3xLg`33td9=4o50;3xLg`33td9=4l50;3xLg`33td9=4m50;3xLg`33td9=4j50;3xLg`33td9=4k50;3xLg`33td9=4h50;3xLg`33td9=l>50;3xLg`33td9=l?50;3xLg`33td9=l<50;3xLg`33td9=l=50;3xLg`33td9=l:50;3xLg`33td9=l;50;3xLg`33td9=l850;3xLg`33td9=l950;3xLg`33td9=l650;3xLg`33td9=l750;3xLg`33td9=lo50;3xLg`33td9=ll50;3xLg`33td9=lm50;3xLg`33td9=lj50;3xLg`33td9=lk50;3xLg`33td9=lh50;3xLg`33td9=o>50;3xLg`33td9=o?50;3xLg`33td9=o<50;3xLg`33td9=o=50;3xLg`33td9=o:50;3xLg`33td9=o;50;3xLg`33td9=o850;3xLg`33td9=o950;3xLg`33td9=o650;3xLg`33td9=o750;3xLg`33td9=oo50;3xLg`33td9=ol50;3xLg`33td9=om50;3xLg`33td9=oj50;3xLg`33td9=ok50;3xLg`33td9=oh50;3xLg`33td9=n>50;3xLg`33td9=n?50;3xLg`33td9=n<50;3xLg`33td9=n=50;3xLg`33td9=n:50;3xLg`33td9=n;50;3xLg`33td9=n850;3xLg`33td9=n950;3xLg`33td9=n650;3xLg`33td9=n750;3xLg`33td9=no50;3xLg`33td9=nl50;3xLg`33td9=nm50;3xLg`33td9=nj50;3xLg`33td9=nk50;3xLg`33td9=nh50;3xLg`33td9=i>50;3xLg`33td9=i?50;3xLg`33td9=i<50;3xLg`33td9=i=50;3xLg`33td9=i:50;3xLg`33td9=i;50;3xLg`33td9=i850;3xLg`33td9=i950;3xLg`33td9=i650;3xLg`33td9=i750;3xLg`33td9=io50;3xLg`33td9=il50;3xLg`33td9=im50;3xLg`33td9=ij50;3xLg`33td9=ik50;3xLg`33td9=ih50;3xLg`33td9=h>50;3xLg`33td9=h?50;3xLg`33td9=h<50;3xLg`33td9=h=50;3xLg`33td9=h:50;3xLg`33td9=h;50;3xLg`33td9=h850;3xLg`33td9=h950;3xLg`33td9=h650;3xLg`33td9=h750;3xLg`33td9=ho50;3xLg`33td9=hl50;3xLg`33td9=hm50;3xLg`33td9=hj50;3xLg`33td9=hk50;3xLg`33td9=hh50;3xLg`33td9=k>50;3xLg`33td9=k?50;3xLg`33td9=k<50;3xLg`33td9=k=50;3xLg`33td9=k:50;3xLg`33td9=k;50;3xLg`33td9=k850;3xLg`33td9=k950;3xLg`33td9=k650;3xLg`33td9=k750;3xLg`33td9=ko50;3xLg`33td9=kl50;3xLg`33td9=km50;3xLg`33td9=kj50;3xLg`33td9=kk50;3xLg`33td9=kh50;3xLg`33td9>=>50;3xLg`33td9>=?50;3xLg`33td9>=<50;3xLg`33td9>==50;3xLg`33td9>=:50;3xLg`33td9>=;50;3xLg`33td9>=850;3xLg`33td9>=950;3xLg`33td9>=650;3xLg`33td9>=750;3xLg`33td9>=o50;3xLg`33td9>=l50;3xLg`33td9>=m50;3xLg`33td9>=j50;3xLg`33td9>=k50;3xLg`33td9>=h50;3xLg`33td9><>50;3xLg`33td9><?50;3xLg`33td9><<50;3xLg`33td9><=50;3xLg`33td9><:50;3xLg`33td9><;50;3xLg`33td9><850;3xLg`33td9><950;3xLg`33td9><650;3xLg`33td9><750;3xLg`33td9><o50;3xLg`33td9><l50;3xLg`33td9><m50;3xLg`33td9><j50;3xLg`33td9><k50;3xLg`33td9><h50;3xLg`33td9>?>50;3xLg`33td9>??50;3xLg`33td9>?<50;3xLg`33td9>?=50;3xLg`33td9>?:50;3xLg`33td9>?;50;3xLg`33td9>?850;3xLg`33td9>?950;3xLg`33td9>?650;3xLg`33td9>?750;3xLg`33td9>?o50;3xLg`33td9>?l50;3xLg`33td9>?m50;3xLg`33td9>?j50;3xLg`33td9>?k50;3xLg`33td9>?h50;3xLg`33td9>>>50;3xLg`33td9>>?50;3xLg`33td9>><50;3xLg`33td9>>=50;3xLg`33td9>>:50;3xLg`33td9>>;50;3xLg`33td9>>850;3xLg`33td9>>950;3xLg`33td9>>650;3xLg`33td9>>750;3xLg`33td9>>o50;3xLg`33td9>>l50;3xLg`33td9>>m50;3xLg`33td9>>j50;3xLg`33td9>>k50;3xLg`33td9>>h50;3xLg`33td9>9>50;3xLg`33td9>9?50;3xLg`33td9>9<50;3xLg`33td9>9=50;3xLg`33td9>9:50;3xLg`33td9>9;50;3xLg`33td9>9850;3xLg`33td9>9950;3xLg`33td9>9650;3xLg`33td9>9750;3xLg`33td9>9o50;3xLg`33td9>9l50;3xLg`33td9>9m50;3xLg`33td9>9j50;3xLg`33td9>9k50;3xLg`33td9>9h50;3xLg`33td9>8>50;3xLg`33td9>8?50;3xLg`33td9>8<50;3xLg`33td9>8=50;3xLg`33td9>8:50;3xLg`33td9>8;50;3xLg`33td9>8850;3xLg`33td9>8950;3xLg`33td9>8650;3xLg`33td9>8750;3xLg`33td9>8o50;3xLg`33td9>8l50;3xLg`33td9>8m50;3xLg`33td9>8j50;3xLg`33td9>8k50;3xLg`33td9>8h50;3xLg`33td9>;>50;3xLg`33td9>;?50;3xLg`33td9>;<50;3xLg`33td9>;=50;3xLg`33td9>;:50;3xLg`33td9>;;50;3xLg`33td9>;850;3xLg`33td9>;950;3xLg`33td9>;650;3xLg`33td9>;750;3xLg`33td9>;o50;3xLg`33td9>;l50;3xLg`33td9>;m50;3xLg`33td9>;j50;3xLg`33td9>;k50;3xLg`33td9>;h50;3xLg`33td9>:>50;3xLg`33td9>:?50;3xLg`33td9>:<50;3xLg`33td9>:=50;3xLg`33td9>::50;3xLg`33td9>:;50;3xLg`33td9>:850;3xLg`33td9>:950;3xLg`33td9>:650;3xLg`33td9>:750;3xLg`33td9>:o50;3xLg`33td9>:l50;3xLg`33td9>:m50;3xLg`33td9>:j50;3xLg`33td9>:k50;3xLg`33td9>:h50;3xLg`33td9>5>50;3xLg`33td9>5?50;3xLg`33td9>5<50;3xLg`33td9>5=50;3xLg`33td9>5:50;3xLg`33td9>5;50;3xLg`33td9>5850;3xLg`33td9>5950;3xLg`33td9>5650;3xLg`33td9>5750;3xLg`33td9>5o50;3xLg`33td9>5l50;3xLg`33td9>5m50;3xLg`33td9>5j50;3xLg`33td9>5k50;3xLg`33td9>5h50;3xLg`33td9>4>50;3xLg`33td9>4?50;3xLg`33td9>4<50;3xLg`33td9>4=50;3xLg`33td9>4:50;3xLg`33td9>4;50;3xLg`33td9>4850;3xLg`33td9>4950;3xLg`33td9>4650;3xLg`33td9>4750;3xLg`33td9>4o50;3xLg`33td9>4l50;3xLg`33td9>4m50;3xLg`33td9>4j50;3xLg`33td9>4k50;3xLg`33td9>4h50;3xLg`33td9>l>50;3xLg`33td9>l?50;3xLg`33td9>l<50;3xLg`33td9>l=50;3xLg`33td9>l:50;3xLg`33td9>l;50;3xLg`33td9>l850;3xLg`33td9>l950;3xLg`33td9>l650;3xLg`33td9>l750;3xLg`33td9>lo50;3xLg`33td9>ll50;3xLg`33td9>lm50;3xLg`33td9>lj50;3xLg`33td9>lk50;3xLg`33td9>lh50;3xLg`33td9>o>50;3xLg`33td9>o?50;3xLg`33td9>o<50;3xLg`33td9>o=50;3xLg`33td9>o:50;3xLg`33td9>o;50;3xLg`33td9>o850;3xLg`33td9>o950;3xLg`33td9>o650;3xLg`33td9>o750;3xLg`33td9>oo50;3xLg`33td9>ol50;3xLg`33td9>om50;3xLg`33td9>oj50;3xLg`33td9>ok50;3xLg`33td9>oh50;3xLg`33td9>n>50;3xLg`33td9>n?50;3xLg`33td9>n<50;3xLg`33td9>n=50;3xLg`33td9>n:50;3xLg`33td9>n;50;3xLg`33td9>n850;3xLg`33td9>n950;3xLg`33td9>n650;3xLg`33td9>n750;3xLg`33td9>no50;3xLg`33td9>nl50;3xLg`33td9>nm50;3xLg`33td9>nj50;3xLg`33td9>nk50;3xLg`33td9>nh50;3xLg`33td9>i>50;3xLg`33td9>i?50;3xLg`33td9>i<50;3xLg`33td9>i=50;3xLg`33td9>i:50;3xLg`33td9>i;50;3xLg`33td9>i850;3xLg`33td9>i950;3xLg`33td9>i650;3xLg`33td9>i750;3xLg`33td9>io50;3xLg`33td9>il50;3xLg`33td9>im50;3xLg`33td9>ij50;3xLg`33td9>ik50;3xLg`33td9>ih50;3xLg`33td9>h>50;3xLg`33td9>h?50;3xLg`33td9>h<50;3xLg`33td9>h=50;3xLg`33td9>h:50;3xLg`33td9>h;50;3xLg`33td9>h850;3xLg`33td9>h950;3xLg`33td9>h650;3xLg`33td9>h750;3xLg`33td9>ho50;3xLg`33td9>hl50;3xLg`33td9>hm50;3xLg`33td9>hj50;3xLg`33td9>hk50;3xLg`33td9>hh50;3xLg`33td9>k>50;3xLg`33td9>k?50;3xLg`33td9>k<50;3xLg`33td9>k=50;3xLg`33td9>k:50;3xLg`33td9>k;50;3xLg`33td9>k850;3xLg`33td9>k950;3xLg`33td9>k650;3xLg`33td9>k750;3xLg`33td9>ko50;3xLg`33td9>kl50;3xLg`33td9>km50;3xLg`33td9>kj50;3xLg`33td9>kk50;3xLg`33td9>kh50;3xLg`33td9?=>50;3xLg`33td9?=?50;3xLg`33td9?=<50;3xLg`33td9?==50;3xLg`33td9?=:50;3xLg`33td9?=;50;3xLg`33td9?=850;3xLg`33td9?=950;3xLg`33td9?=650;3xLg`33td9?=750;3xLg`33td9?=o50;3xLg`33td9?=l50;3xLg`33td9?=m50;3xLg`33td9?=j50;3xLg`33td9?=k50;3xLg`33td9?=h50;3xLg`33td9?<>50;3xLg`33td9?<?50;3xLg`33td9?<<50;3xLg`33td9?<=50;3xLg`33td9?<:50;3xLg`33td9?<;50;3xLg`33td9?<850;3xLg`33td9?<950;3xLg`33td9?<650;3xLg`33td9?<750;3xLg`33td9?<o50;3xLg`33td9?<l50;3xLg`33td9?<m50;3xLg`33td9?<j50;3xLg`33td9?<k50;3xLg`33td9?<h50;3xLg`33td9??>50;3xLg`33td9???50;3xLg`33td9??<50;3xLg`33td9??=50;3xLg`33td9??:50;3xLg`33td9??;50;3xLg`33td9??850;3xLg`33td9??950;3xLg`33td9??650;3xLg`33td9??750;3xLg`33td9??o50;3xLg`33td9??l50;3xLg`33td9??m50;3xLg`33td9??j50;3xLg`33td9??k50;3xLg`33td9??h50;3xLg`33td9?>>50;3xLg`33td9?>?50;3xLg`33td9?><50;3xLg`33td9?>=50;3xLg`33td9?>:50;3xLg`33td9?>;50;3xLg`33td9?>850;3xLg`33td9?>950;3xLg`33td9?>650;3xLg`33td9?>750;3xLg`33td9?>o50;3xLg`33td9?>l50;3xLg`33td9?>m50;3xLg`33td9?>j50;3xLg`33td9?>k50;3xLg`33td9?>h50;3xLg`33td9?9>50;3xLg`33td9?9?50;3xLg`33td9?9<50;3xLg`33td9?9=50;3xLg`33td9?9:50;3xLg`33td9?9;50;3xLg`33td9?9850;3xLg`33td9?9950;3xLg`33td9?9650;3xLg`33td9?9750;3xLg`33td9?9o50;3xLg`33td9?9l50;3xLg`33td9?9m50;3xLg`33td9?9j50;3xLg`33td9?9k50;3xLg`33td9?9h50;3xLg`33td9?8>50;3xLg`33td9?8?50;3xLg`33td9?8<50;3xLg`33td9?8=50;3xLg`33td9?8:50;3xLg`33td9?8;50;3xLg`33td9?8850;3xLg`33td9?8950;3xLg`33td9?8650;3xLg`33td9?8750;3xLg`33td9?8o50;3xLg`33td9?8l50;3xLg`33td9?8m50;3xLg`33td9?8j50;3xLg`33td9?8k50;3xLg`33td9?8h50;3xLg`33td9?;>50;3xLg`33td9?;?50;3xLg`33td9?;<50;3xLg`33td9?;=50;3xLg`33td9?;:50;3xLg`33td9?;;50;3xLg`33td9?;850;3xLg`33td9?;950;3xLg`33td9?;650;3xLg`33td9?;750;3xLg`33td9?;o50;3xLg`33td9?;l50;3xLg`33td9?;m50;3xLg`33td9?;j50;3xLg`33td9?;k50;3xLg`33td9?;h50;3xLg`33td9?:>50;3xLg`33td9?:?50;3xLg`33td9?:<50;3xLg`33td9?:=50;3xLg`33td9?::50;3xLg`33td9?:;50;3xLg`33td9?:850;3xLg`33td9?:950;3xLg`33td9?:650;3xLg`33td9?:750;3xLg`33td9?:o50;3xLg`33td9?:l50;3xLg`33td9?:m50;3xLg`33td9?:j50;3xLg`33td9?:k50;3xLg`33td9?:h50;3xLg`33td9?5>50;3xLg`33td9?5?50;3xLg`33td9?5<50;3xLg`33td9?5=50;3xLg`33td9?5:50;3xLg`33td9?5;50;3xLg`33td9?5850;3xLg`33td9?5950;3xLg`33td9?5650;3xLg`33td9?5750;3xLg`33td9?5o50;3xLg`33td9?5l50;3xLg`33td9?5m50;3xLg`33td9?5j50;3xLg`33td9?5k50;3xLg`33td9?5h50;3xLg`33td9?4>50;3xLg`33td9?4?50;3xLg`33td9?4<50;3xLg`33td9?4=50;3xLg`33td9?4:50;3xLg`33td9?4;50;3xLg`33td9?4850;3xLg`33td9?4950;3xLg`33td9?4650;3xLg`33td9?4750;3xLg`33td9?4o50;3xLg`33td9?4l50;3xLg`33td9?4m50;3xLg`33td9?4j50;3xLg`33td9?4k50;3xLg`33td9?4h50;3xLg`33td9?l>50;3xLg`33td9?l?50;3xLg`33td9?l<50;3xLg`33td9?l=50;3xLg`33td9?l:50;3xLg`33td9?l;50;3xLg`33td9?l850;3xLg`33td9?l950;3xLg`33td9?l650;3xLg`33td9?l750;3xLg`33td9?lo50;3xLg`33td9?ll50;3xLg`33td9?lm50;3xLg`33td9?lj50;3xLg`33td9?lk50;3xLg`33twvqMNL{3;`3?7f>123:isO@Cy3yEFWstJK
\ No newline at end of file
+++ /dev/null
-------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : double_reset.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module DOUBLE_RESET\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
-entity DOUBLE_RESET is\r
-port\r
-(\r
- CLK : in std_logic;\r
- PLLLKDET : in std_logic;\r
- GTXTEST_DONE : out std_logic;\r
- GTXTEST_BIT1 : out std_logic\r
-);\r
-\r
-end DOUBLE_RESET;\r
-\r
-architecture RTL of DOUBLE_RESET is\r
---***********************************Parameter Declarations********************\r
- constant DLY : time := 1 ns;\r
-\r
---*******************************Register Declarations************************\r
- signal plllkdet_sync : std_logic;\r
- signal plllkdet_r : std_logic;\r
- signal reset_dly_ctr : unsigned(10 downto 0);\r
- signal reset_dly_done : std_logic;\r
- signal testdone_f : std_logic_vector(3 downto 0);\r
-\r
-begin\r
---*******************************Main Body of Code****************************\r
-\r
- process(CLK )\r
- begin\r
- if(CLK'event and CLK = '1') then\r
- plllkdet_r <= PLLLKDET after DLY;\r
- plllkdet_sync <= plllkdet_r after DLY;\r
- end if;\r
- end process;\r
-\r
- GTXTEST_BIT1 <= reset_dly_done; \r
- GTXTEST_DONE <= testdone_f(0) when (reset_dly_ctr = b"00000000000") else '0';\r
-\r
- process(CLK )\r
- begin\r
- if(CLK'event and CLK = '1') then\r
- if (plllkdet_sync = '0') then\r
- reset_dly_ctr <= b"11111111111" after DLY;\r
- elsif (reset_dly_ctr /= b"00000000000") then\r
- reset_dly_ctr <= reset_dly_ctr - 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- process(CLK )\r
- begin\r
- if(CLK'event and CLK = '1') then\r
- if (plllkdet_sync = '0') then\r
- reset_dly_done <= '0' after DLY;\r
- elsif (reset_dly_ctr(10) = '0') then\r
- reset_dly_done <= reset_dly_ctr(8) after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- process(CLK )\r
- begin\r
- if(CLK'event and CLK = '1') then\r
- if(reset_dly_ctr /= b"00000000000") then\r
- testdone_f <= b"1111" after DLY;\r
- else\r
- testdone_f <= '0' & testdone_f(3 downto 1) after DLY; \r
- end if;\r
- end if;\r
- end process;\r
- \r
-\r
-end RTL;\r
+++ /dev/null
- Core Name: Xilinx LogiCORE FIFO Generator
- Version: 8.3
- Release Date: October 19, 2011
-
-
-================================================================================
-
-This document contains the following sections:
-
-1. Introduction
-2. New Features
-3. Supported Devices
-4. Resolved Issues
-5. Known Issues
-6. Technical Support
-7. Core Release History
-8. Legal Disclaimer
-
-================================================================================
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v8.2
-solution. For the latest core updates, see the product page at:
-
- http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
-
-
-2. NEW FEATURES
-
- - ISE 13.3 software support
- - QVirtex-6L device support
-
-3. SUPPORTED DEVICES
-
- The following device families are supported by the core for this release.
-
- - Zynq-7000*
-
- - Virtex-7
- - Virtex-7 XT (7vx485t)
- - Virtex-7 -2L
-
- - Kintex-7
- - Kintex-7 -2L
-
- - Artix-7*
-
- - Virtex-6 XC CXT/LXT/SXT/HXT
- - Virtex-6 XQ LXT/SXT
- - Virtex-6 -1L XC LXT/SXT
-
- - Spartan-6 XC LX/LXT
- - Spartan-6 XA
- - Spartan-6 XQ LX/LXT
- - Spartan-6 -1L XC LX
-
- - Virtex-5 XC LX/LXT/SXT/TXT/FXT
- - Virtex-5 XQ LX/ LXT/SXT/FXT
-
- - Virtex-4 XC LX/SX/FX
- - Virtex-4 XQ LX/SX/FX
- - Virtex-4 XQR LX/SX/FX
-
- - Spartan-3 XC
- - Spartan-3 XA
- - Spartan-3A XC 3A / 3A DSP / 3AN DSP
- - Spartan-3A XA 3A / 3A DSP
- - Spartan-3E XC
- - Spartan-3E XA
-
-*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
-
-4. RESOLVED ISSUES
-
-
-5. KNOWN ISSUES
-
- The following are known issues for v8.2 of this core at time of release:
-
- - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
- into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
- page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
- - CR 467240
- - AR 31379
-
- - When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
- correct behavior of the FIFO status flags cannot be guaranteed after the first write.
-
- Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
- For more information and additional workaround see Answer Record 41099.
-
-
- The most recent information, including known issues, workarounds, and
- resolutions for this version is provided in the IP Release Notes User Guide
- located at
-
- www.xilinx.com/support/documentation/user_guides/xtp025.pdf
-
-
-6. TECHNICAL SUPPORT
-
- To obtain technical support, create a WebCase at www.xilinx.com/support.
- Questions are routed to a team with expertise using this product.
-
- Xilinx provides technical support for use of this product when used
- according to the guidelines described in the core documentation, and
- cannot guarantee timing, functionality, or support of this product for
- designs that do not follow specified guidelines.
-
-
-7. CORE RELEASE HISTORY
-
-Date By Version Description
-================================================================================
-09/28/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L and QSpartan-6 device support
-06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7* and Zynq-7000* device support
-03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
-10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
-09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
-07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
-06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
-04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
-12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
-09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
-06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
-04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
-09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
-03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
-10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
-08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
-04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
-09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
-07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
-01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
-08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
-04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
-11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
-05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
-04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
-================================================================================
-
-8. Legal Disclaimer
-
- (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
-
- This file contains confidential and proprietary information
- of Xilinx, Inc. and is protected under U.S. and
- international copyright and other intellectual property
- laws.
-
- DISCLAIMER
- This disclaimer is not a license and does not grant any
- rights to the materials distributed herewith. Except as
- otherwise provided in a valid license issued to you by
- Xilinx, and to the maximum extent permitted by applicable
- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
- (2) Xilinx shall not be liable (whether in contract or tort,
- including negligence, or under any other theory of
- liability) for any loss or damage of any kind or nature
- related to, arising under or in connection with these
- materials, including for any direct, or any indirect,
- special, incidental, or consequential loss or damage
- (including loss of data, profits, goodwill, or any type of
- loss or damage suffered as a result of any action brought
- by a third party) even if such damage or loss was
- reasonably foreseeable or Xilinx had been advised of the
- possibility of the same.
-
- CRITICAL APPLICATIONS
- Xilinx products are not designed or intended to be fail-
- safe, or for use in any application requiring fail-safe
- performance, such as life-support or safety devices or
- systems, Class III medical devices, nuclear facilities,
- applications related to the deployment of airbags, or any
- other applications that could lead to death, personal
- injury, or severe property or environmental damage
- (individually and collectively, "Critical
- Applications"). Customer assumes the sole risk and
- liability of any use of Xilinx products in Critical
- Applications, subject only to applicable laws and
- regulations governing limitations on product liability.
-
- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
- PART OF THIS FILE AT ALL TIMES.
+++ /dev/null
--------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : frame_check.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\ \r
---\r
---\r
--- Module FRAME_CHECK\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard \r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-use ieee.numeric_std.all;\r
-use std.textio.all;\r
-use ieee.std_logic_textio.all;\r
-use ieee.std_logic_misc.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***********************************Entity Declaration************************\r
-\r
-entity FRAME_CHECK is\r
-generic\r
-(\r
- RX_DATA_WIDTH : integer := 16;\r
- RXCTRL_WIDTH : integer := 2;\r
- USE_COMMA : integer := 1;\r
- NONE_MSB_FIRST_DEC : integer := 0;\r
- COMMA_DOUBLE_DEC : integer := 0;\r
- CHANBOND_SEQ_LEN : integer := 1;\r
- WORDS_IN_BRAM : integer := 256;\r
- CONFIG_INDEPENDENT_LANES : integer := 0;\r
- START_OF_PACKET_CHAR : std_logic_vector(15 downto 0) ;\r
- COMMA_DOUBLE_CHAR : std_logic_vector(15 downto 0) := x"f628";\r
- MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"\r
-);\r
-port\r
-(\r
- -- User Interface\r
- RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0); \r
- RXCTRL_IN : in std_logic_vector((RXCTRL_WIDTH-1) downto 0); \r
- \r
- RX_ENMCOMMA_ALIGN : out std_logic;\r
- RX_ENPCOMMA_ALIGN : out std_logic;\r
- RX_ENCHAN_SYNC : out std_logic; \r
- RX_CHANBOND_SEQ : in std_logic; \r
-\r
- -- Control Interface\r
- INC_IN : in std_logic; \r
- INC_OUT : out std_logic; \r
- PATTERN_MATCH_N : out std_logic;\r
- RESET_ON_ERROR : in std_logic; \r
- \r
- -- Error Monitoring\r
- ERROR_COUNT : out std_logic_vector(7 downto 0);\r
- \r
- -- Track Data\r
- TRACK_DATA : out std_logic;\r
- \r
- -- System Interface\r
- USER_CLK : in std_logic; \r
- SYSTEM_RESET : in std_logic\r
- \r
-);\r
-\r
-\r
-end FRAME_CHECK;\r
-\r
-\r
-architecture RTL of FRAME_CHECK is\r
-\r
-\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
-\r
---***************************Internal Register Declarations********************\r
-\r
- signal begin_r : std_logic;\r
- signal data_error_detected_r : std_logic;\r
- signal error_count_r : unsigned(8 downto 0);\r
- signal error_detected_r : std_logic;\r
- signal read_counter_i : unsigned(8 downto 0); \r
- signal rx_chanbond_seq_r : std_logic;\r
- signal rx_chanbond_seq_r2 : std_logic;\r
- signal rx_chanbond_seq_r3 : std_logic;\r
- signal rx_data_r : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r2 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r3 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r4 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r5 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r6 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r7 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r_track : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rxctrl_r : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
- signal rxctrl_r2 : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
- signal rxctrl_r3 : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
- signal rxctrl_or : std_logic;\r
- signal start_of_packet_detected_r : std_logic; \r
- signal track_data_r : std_logic;\r
- signal track_data_r2 : std_logic;\r
- signal track_data_r3 : std_logic;\r
- signal track_data_r4 : std_logic;\r
- signal sel : std_logic_vector(1 downto 0);\r
- signal bram_data_r : std_logic_vector(31 downto 0);\r
- \r
- \r
---*********************************Wire Declarations***************************\r
- \r
- signal bram_data_i : std_logic_vector(31 downto 0);\r
-\r
- signal chanbondseq_in_data : std_logic;\r
- signal error_detected_c : std_logic;\r
- signal input_to_chanbond_data_i : std_logic;\r
- signal input_to_chanbond_reg_i : std_logic;\r
- signal next_begin_c : std_logic;\r
- signal next_data_error_detected_c : std_logic;\r
- signal next_track_data_c : std_logic;\r
- signal start_of_packet_detected_c : std_logic;\r
- signal rx_chanbond_reg : std_logic_vector((CHANBOND_SEQ_LEN-1) downto 0);\r
- signal rx_chanbond_reg_bitwise_or_i: std_logic;\r
- signal rx_data_aligned : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_has_start_char_c : std_logic;\r
- signal rx_data_matches_bram_c : std_logic;\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);\r
- signal tied_to_vcc_i : std_logic;\r
-\r
-\r
---*********************************Main Body of Code***************************\r
-begin\r
-\r
- --_______________________ Static signal Assigments _______________________ \r
-\r
- tied_to_ground_i <= '0';\r
- tied_to_ground_vec_i <= (others=>'0');\r
- tied_to_vcc_i <= '1';\r
-\r
- --______________________ Register RXDATA once to ease timing ______________ \r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- rx_data_r <= RX_DATA after DLY;\r
- end if;\r
- end process;\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- rxctrl_r <= RXCTRL_IN after DLY;\r
- end if;\r
- end process;\r
- --________________________________ State machine __________________________ \r
- \r
- \r
- -- State registers\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(RESET_ON_ERROR ='1' or SYSTEM_RESET = '1' ) then\r
- begin_r <= '1' after DLY;\r
- track_data_r <= '0' after DLY;\r
- data_error_detected_r <= '0' after DLY;\r
- else\r
- begin_r <= next_begin_c after DLY;\r
- track_data_r <= next_track_data_c after DLY;\r
- data_error_detected_r <= next_data_error_detected_c after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Next state logic\r
- next_begin_c <= (begin_r and not start_of_packet_detected_r) or data_error_detected_r ;\r
-\r
- next_track_data_c <= (begin_r and start_of_packet_detected_r) or (track_data_r and not error_detected_r);\r
- \r
- next_data_error_detected_c <= (track_data_r and error_detected_r); \r
- \r
- start_of_packet_detected_c <= INC_IN when (CONFIG_INDEPENDENT_LANES=0) else rx_data_has_start_char_c;\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- start_of_packet_detected_r <= start_of_packet_detected_c after DLY;\r
- end if; \r
- end process;\r
- \r
- -- Registering for timing\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- track_data_r2 <= track_data_r after DLY;\r
- end if; \r
- end process;\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- track_data_r3 <= track_data_r2 after DLY;\r
- end if; \r
- end process;\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- track_data_r4 <= track_data_r3 after DLY;\r
- end if; \r
- end process;\r
-\r
- --______________________________ Capture incoming data ____________________ \r
-\r
-\r
-\r
-datapath_width_32_40_16_or_20: if ((RX_DATA_WIDTH=16) or (RX_DATA_WIDTH=20) or (RX_DATA_WIDTH=32) or (RX_DATA_WIDTH=40)) generate\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- rx_data_r2 <= (others => '0') after DLY;\r
- rx_data_r4 <= (others => '0') after DLY;\r
- rx_data_r5 <= (others => '0') after DLY;\r
- rx_data_r6 <= (others => '0') after DLY;\r
- rx_data_r7 <= (others => '0') after DLY;\r
- rx_data_r_track <= (others => '0') after DLY;\r
- else\r
- rx_data_r2 <= rx_data_r after DLY;\r
- rx_data_r4 <= rx_data_r3 after DLY;\r
- rx_data_r5 <= rx_data_r4 after DLY;\r
- rx_data_r6 <= rx_data_r5 after DLY;\r
- rx_data_r7 <= rx_data_r6 after DLY;\r
- rx_data_r_track <= rx_data_r7 after DLY;\r
- end if;\r
- end if; \r
- end process;\r
-\r
- rx_data_aligned <= rx_data_r3;\r
-\r
- --___________________________ Code for Channel bonding ____________________ \r
- -- code to prevent checking of clock correction sequences for the start of packet char\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- rx_chanbond_seq_r <= RX_CHANBOND_SEQ after DLY;\r
- rx_chanbond_seq_r2 <= rx_chanbond_seq_r after DLY;\r
- rx_chanbond_seq_r3 <= rx_chanbond_seq_r2 after DLY;\r
- end if; \r
- end process;\r
-\r
- input_to_chanbond_reg_i <= rx_chanbond_seq_r2;\r
- input_to_chanbond_data_i <= tied_to_ground_i;\r
-end generate datapath_width_32_40_16_or_20;\r
-\r
-datapath_width_8_or_10: if ((RX_DATA_WIDTH=8) or (RX_DATA_WIDTH=10)) generate\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- rx_data_r2 <= (others => '0') after DLY;\r
- rx_data_r3 <= (others => '0') after DLY;\r
- rx_data_r4 <= (others => '0') after DLY;\r
- rx_data_r5 <= (others => '0') after DLY;\r
- rx_data_r_track <= (others => '0') after DLY;\r
- else\r
- rx_data_r2 <= rx_data_r after DLY;\r
- rx_data_r3 <= rx_data_r2 after DLY;\r
- rx_data_r4 <= rx_data_r3 after DLY;\r
- rx_data_r5 <= rx_data_r4 after DLY;\r
- rx_data_r_track <= rx_data_r5 after DLY;\r
- end if;\r
- end if; \r
- end process;\r
- \r
- rx_data_aligned <= RX_DATA;\r
- input_to_chanbond_reg_i <= RX_CHANBOND_SEQ;\r
- input_to_chanbond_data_i <= RX_CHANBOND_SEQ;\r
-end generate datapath_width_8_or_10;\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then\r
- rxctrl_r2 <= (others => '0') after DLY;\r
- rxctrl_r3 <= (others => '0') after DLY;\r
- else\r
- rxctrl_r2 <= rxctrl_r after DLY;\r
- rxctrl_r3 <= rxctrl_r2 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- --___________________________ Code for Channel bonding ____________________ \r
- -- code to prevent checking of clock correction sequences for the start of packet char\r
- register_chan_seq: for i in 0 to (CHANBOND_SEQ_LEN-1) generate\r
- case_i_equal_to_0: if (i=0) generate \r
- rx_chanbond_reg_0 : FD port map (Q => rx_chanbond_reg(i),D => input_to_chanbond_reg_i,C => USER_CLK);\r
- end generate case_i_equal_to_0;\r
- case_i_greater_than_0: if (i>0) generate \r
- rx_chanbond_reg_i :FD port map (Q => rx_chanbond_reg(i),D => rx_chanbond_reg(i-1),C => USER_CLK);\r
- end generate case_i_greater_than_0;\r
- end generate register_chan_seq;\r
- \r
- chanbondseq_in_data <= input_to_chanbond_data_i or rx_chanbond_reg_bitwise_or_i;\r
-\r
- process(rx_chanbond_reg)\r
- variable rx_chanbond_var : std_logic;\r
- variable i : std_logic;\r
- begin\r
- rx_chanbond_var := '0';\r
- bit_wise_or : for i in 0 to (CHANBOND_SEQ_LEN-1) loop\r
- rx_chanbond_var := rx_chanbond_var or rx_chanbond_reg(i);\r
- end loop;\r
- rx_chanbond_reg_bitwise_or_i <= rx_chanbond_var;\r
- end process;\r
-\r
- process(RXCTRL_IN)\r
- variable or_rxctrl_var : std_logic;\r
- variable i : std_logic;\r
- begin\r
- or_rxctrl_var := '0';\r
- bit_wise_rxctrl_or : for i in 0 to (RXCTRL_WIDTH-1) loop\r
- or_rxctrl_var := or_rxctrl_var or RXCTRL_IN(i);\r
- end loop;\r
- rxctrl_or <= or_rxctrl_var;\r
- end process;\r
-\r
-\r
-\r
- rx_data_has_start_char_c <= '1' when ((rx_data_aligned(7 downto 0) = START_OF_PACKET_CHAR(7 downto 0)) and (chanbondseq_in_data='0') and (rxctrl_or='1')) else '0';\r
-\r
- --_____________________________ Assign output ports _______________________ \r
-\r
- TRACK_DATA <= track_data_r; \r
-\r
-\r
- -- Drive the enamcommaalign port of the mgt for alignment\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- RX_ENMCOMMA_ALIGN <= '0' after DLY;\r
- else \r
- RX_ENMCOMMA_ALIGN <= '1' after DLY;\r
- end if;\r
- end if; \r
- end process;\r
-\r
- -- Drive the enapcommaalign port of the mgt for alignment\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- RX_ENPCOMMA_ALIGN <= '0' after DLY;\r
- else \r
- RX_ENPCOMMA_ALIGN <= '1' after DLY;\r
- end if;\r
- end if; \r
- end process;\r
-\r
- INC_OUT <= start_of_packet_detected_c; \r
-\r
- PATTERN_MATCH_N <= data_error_detected_r;\r
-\r
- -- Drive the enchansync port of the mgt for channel bonding\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- RX_ENCHAN_SYNC <= '0' after DLY;\r
- else \r
- RX_ENCHAN_SYNC <= '1' after DLY;\r
- end if;\r
- end if; \r
- end process;\r
- \r
- --___________________________ Check incoming data for errors ______________\r
- \r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- bram_data_r <= bram_data_i after DLY;\r
- end if; \r
- end process;\r
- \r
- --An error is detected when data read for the BRAM does not match the incoming data\r
-use_40bit : if RX_DATA_WIDTH = 40 generate\r
- rx_data_matches_bram_c <= '0' when (rx_data_r_track /= (tied_to_ground_vec_i(7 downto 0) & bram_data_r)) else '1';\r
-end generate use_40bit;\r
-\r
-not_40bit : if RX_DATA_WIDTH /= 40 generate\r
- rx_data_matches_bram_c <= '0' when (rx_data_r_track /= bram_data_r((RX_DATA_WIDTH-1) downto 0)) else '1';\r
-end generate not_40bit;\r
-\r
- error_detected_c <= track_data_r4 and not rx_data_matches_bram_c; \r
- \r
- \r
-enable_error_check : if USE_COMMA = 1 generate\r
- --We register the error_detected signal for use with the error counter logic\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(not(track_data_r = '1')) then \r
- error_detected_r <= '0' after DLY;\r
- else\r
- error_detected_r <= error_detected_c after DLY;\r
- end if;\r
- end if; \r
- end process;\r
-end generate enable_error_check;\r
-\r
-disable_error_check : if USE_COMMA = 0 generate\r
- -- Since the comma detect logic has not been enabled, the error counter has been disabled since\r
- -- it doesnt make sense to be searching for an align character in the data. To enable the error \r
- -- count again, please see the code above\r
- \r
- error_detected_r <= '0';\r
-\r
-end generate disable_error_check;\r
-\r
- \r
- --We count the total number of errors we detect. By keeping a count we make it less likely that we will miss\r
- --errors we did not directly observe. This counter must be reset when it reaches its max value\r
- process ( USER_CLK )\r
- begin\r
- if( USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET='1') then\r
- error_count_r <= (others => '0') after DLY;\r
- elsif(error_detected_r = '1') then\r
- error_count_r <= error_count_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
- \r
- \r
- --Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches\r
- --max value) to the module output\r
- ERROR_COUNT <= std_logic_vector(error_count_r(7 downto 0));\r
-\r
- --____________________________ Counter to read from BRAM __________________________ \r
-four_byte : if RX_DATA_WIDTH > 20 generate\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))) then\r
- read_counter_i <= (others => '0') after DLY;\r
- elsif(((start_of_packet_detected_r and not track_data_r)='1')) then\r
- read_counter_i <= "000000001" after DLY;\r
- else read_counter_i <= read_counter_i + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-end generate four_byte;\r
-\r
-one_or_two_byte : if RX_DATA_WIDTH <= 20 generate\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))\r
- or ((start_of_packet_detected_r and not track_data_r)='1')) then\r
- read_counter_i <= (others => '0') after DLY;\r
- else read_counter_i <= read_counter_i + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-end generate one_or_two_byte;\r
-\r
- --________________________________ BRAM Instantiation _____________________________ \r
-\r
- dual_port_block_ram_i : RAMB16_S36_S36 \r
- generic map\r
- (\r
- INIT_00 => MEM_00,\r
- INIT_01 => MEM_01,\r
- INIT_02 => MEM_02,\r
- INIT_03 => MEM_03,\r
- INIT_04 => MEM_04,\r
- INIT_05 => MEM_05,\r
- INIT_06 => MEM_06,\r
- INIT_07 => MEM_07,\r
- INIT_08 => MEM_08,\r
- INIT_09 => MEM_09,\r
- INIT_0A => MEM_0A,\r
- INIT_0B => MEM_0B,\r
- INIT_0C => MEM_0C,\r
- INIT_0D => MEM_0D,\r
- INIT_0E => MEM_0E,\r
- INIT_0F => MEM_0F,\r
- INIT_10 => MEM_10,\r
- INIT_11 => MEM_11,\r
- INIT_12 => MEM_12,\r
- INIT_13 => MEM_13,\r
- INIT_14 => MEM_14,\r
- INIT_15 => MEM_15,\r
- INIT_16 => MEM_16,\r
- INIT_17 => MEM_17,\r
- INIT_18 => MEM_18,\r
- INIT_19 => MEM_19,\r
- INIT_1A => MEM_1A,\r
- INIT_1B => MEM_1B,\r
- INIT_1C => MEM_1C,\r
- INIT_1D => MEM_1D,\r
- INIT_1E => MEM_1E,\r
- INIT_1F => MEM_1F,\r
- INIT_20 => MEM_20,\r
- INIT_21 => MEM_21,\r
- INIT_22 => MEM_22,\r
- INIT_23 => MEM_23,\r
- INIT_24 => MEM_24,\r
- INIT_25 => MEM_25,\r
- INIT_26 => MEM_26,\r
- INIT_27 => MEM_27,\r
- INIT_28 => MEM_28,\r
- INIT_29 => MEM_29,\r
- INIT_2A => MEM_2A,\r
- INIT_2B => MEM_2B,\r
- INIT_2C => MEM_2C,\r
- INIT_2D => MEM_2D,\r
- INIT_2E => MEM_2E,\r
- INIT_2F => MEM_2F,\r
- INIT_30 => MEM_30,\r
- INIT_31 => MEM_31,\r
- INIT_32 => MEM_32,\r
- INIT_33 => MEM_33,\r
- INIT_34 => MEM_34,\r
- INIT_35 => MEM_35,\r
- INIT_36 => MEM_36,\r
- INIT_37 => MEM_37,\r
- INIT_38 => MEM_38,\r
- INIT_39 => MEM_39,\r
- INIT_3A => MEM_3A,\r
- INIT_3B => MEM_3B,\r
- INIT_3C => MEM_3C,\r
- INIT_3D => MEM_3D,\r
- INIT_3E => MEM_3E,\r
- INIT_3F => MEM_3F,\r
- INITP_00 => MEMP_00,\r
- INITP_01 => MEMP_01,\r
- INITP_02 => MEMP_02,\r
- INITP_03 => MEMP_03,\r
- INITP_04 => MEMP_04,\r
- INITP_05 => MEMP_05,\r
- INITP_06 => MEMP_06,\r
- INITP_07 => MEMP_07\r
-\r
- )\r
- port map \r
- (\r
- ADDRA => std_logic_vector(read_counter_i),\r
- DIA => tied_to_ground_vec_i(31 downto 0),\r
- DIPA => tied_to_ground_vec_i(3 downto 0),\r
- DOA => bram_data_i,\r
- DOPA => open, \r
- WEA => tied_to_ground_i,\r
- ENA => tied_to_vcc_i,\r
- SSRA => tied_to_ground_i, \r
- CLKA => USER_CLK,\r
- \r
- ADDRB => tied_to_ground_vec_i(8 downto 0),\r
- DIB => tied_to_ground_vec_i(31 downto 0),\r
- DIPB => tied_to_ground_vec_i(3 downto 0),\r
- DOB => open, \r
- DOPB => open, \r
- WEB => tied_to_ground_i,\r
- ENB => tied_to_ground_i,\r
- SSRB => tied_to_ground_i,\r
- CLKB => tied_to_ground_i \r
- ); \r
- \r
- \r
-end RTL; \r
-\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : frame_gen.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\ \r
---\r
---\r
--- Module FRAME_GEN\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***********************************Entity Declaration************************\r
-\r
-entity FRAME_GEN is\r
-generic\r
-(\r
- WORDS_IN_BRAM : integer := 256;\r
- MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"\r
-); \r
-port\r
-(\r
- -- User Interface\r
- TX_DATA : out std_logic_vector(39 downto 0);\r
- TX_CHARISK : out std_logic_vector(3 downto 0); \r
-\r
- -- System Interface\r
- USER_CLK : in std_logic; \r
- SYSTEM_RESET : in std_logic\r
-); \r
-\r
-\r
-end FRAME_GEN;\r
-\r
-architecture RTL of FRAME_GEN is\r
-\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
-\r
---********************************* Wire Declarations************************** \r
-\r
- signal tx_charisk_i : std_logic_vector(3 downto 0);\r
- signal tx_data_bram_i : std_logic_vector(31 downto 0);\r
- signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_vcc_i : std_logic;\r
- signal tied_to_vcc_vec_i : std_logic_vector(15 downto 0);\r
-\r
---***************************Internal signalister Declarations******************** \r
-\r
- signal read_counter_i : unsigned(8 downto 0); \r
-\r
-\r
---*********************************Main Body of Code***************************\r
-begin\r
-\r
- tied_to_ground_vec_i <= (others=>'0');\r
- tied_to_ground_i <= '0';\r
- tied_to_vcc_i <= '1';\r
- \r
- --__________________________ Counter to read from BRAM ____________________ \r
- \r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1)))then\r
- read_counter_i <= (others => '0') after DLY;\r
- else\r
- read_counter_i <= read_counter_i + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Assign TX_DATA to BRAM output\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET='1') then\r
- TX_DATA <= (others => '0') after DLY;\r
- else\r
- TX_DATA <= (tied_to_ground_vec_i(7 downto 0) & tx_data_bram_i) after DLY; \r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Assign TX_CHARISK to BRAM output\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET='1') then\r
- TX_CHARISK <= (others => '0') after DLY;\r
- else\r
- TX_CHARISK <= tx_charisk_i after DLY; \r
- end if;\r
- end if;\r
- end process;\r
-\r
- --______________________________ BRAM Instantiation _______________________ \r
-\r
- dual_port_block_ram_i : RAMB16_S36_S36 \r
- generic map\r
- (\r
- INIT_00 => MEM_00,\r
- INIT_01 => MEM_01,\r
- INIT_02 => MEM_02,\r
- INIT_03 => MEM_03,\r
- INIT_04 => MEM_04,\r
- INIT_05 => MEM_05,\r
- INIT_06 => MEM_06,\r
- INIT_07 => MEM_07,\r
- INIT_08 => MEM_08,\r
- INIT_09 => MEM_09,\r
- INIT_0A => MEM_0A,\r
- INIT_0B => MEM_0B,\r
- INIT_0C => MEM_0C,\r
- INIT_0D => MEM_0D,\r
- INIT_0E => MEM_0E,\r
- INIT_0F => MEM_0F,\r
- INIT_10 => MEM_10,\r
- INIT_11 => MEM_11,\r
- INIT_12 => MEM_12,\r
- INIT_13 => MEM_13,\r
- INIT_14 => MEM_14,\r
- INIT_15 => MEM_15,\r
- INIT_16 => MEM_16,\r
- INIT_17 => MEM_17,\r
- INIT_18 => MEM_18,\r
- INIT_19 => MEM_19,\r
- INIT_1A => MEM_1A,\r
- INIT_1B => MEM_1B,\r
- INIT_1C => MEM_1C,\r
- INIT_1D => MEM_1D,\r
- INIT_1E => MEM_1E,\r
- INIT_1F => MEM_1F,\r
- INIT_20 => MEM_20,\r
- INIT_21 => MEM_21,\r
- INIT_22 => MEM_22,\r
- INIT_23 => MEM_23,\r
- INIT_24 => MEM_24,\r
- INIT_25 => MEM_25,\r
- INIT_26 => MEM_26,\r
- INIT_27 => MEM_27,\r
- INIT_28 => MEM_28,\r
- INIT_29 => MEM_29,\r
- INIT_2A => MEM_2A,\r
- INIT_2B => MEM_2B,\r
- INIT_2C => MEM_2C,\r
- INIT_2D => MEM_2D,\r
- INIT_2E => MEM_2E,\r
- INIT_2F => MEM_2F,\r
- INIT_30 => MEM_30,\r
- INIT_31 => MEM_31,\r
- INIT_32 => MEM_32,\r
- INIT_33 => MEM_33,\r
- INIT_34 => MEM_34,\r
- INIT_35 => MEM_35,\r
- INIT_36 => MEM_36,\r
- INIT_37 => MEM_37,\r
- INIT_38 => MEM_38,\r
- INIT_39 => MEM_39,\r
- INIT_3A => MEM_3A,\r
- INIT_3B => MEM_3B,\r
- INIT_3C => MEM_3C,\r
- INIT_3D => MEM_3D,\r
- INIT_3E => MEM_3E,\r
- INIT_3F => MEM_3F,\r
- INITP_00 => MEMP_00,\r
- INITP_01 => MEMP_01,\r
- INITP_02 => MEMP_02,\r
- INITP_03 => MEMP_03,\r
- INITP_04 => MEMP_04,\r
- INITP_05 => MEMP_05,\r
- INITP_06 => MEMP_06,\r
- INITP_07 => MEMP_07\r
- )\r
- port map \r
- (\r
- ADDRA => std_logic_vector(read_counter_i),\r
- DIA => tied_to_ground_vec_i(31 downto 0),\r
- DIPA => tied_to_ground_vec_i(3 downto 0),\r
- DOA => tx_data_bram_i,\r
- DOPA => tx_charisk_i, \r
- WEA => tied_to_ground_i,\r
- ENA => tied_to_vcc_i,\r
- SSRA => tied_to_ground_i, \r
- CLKA => USER_CLK,\r
- \r
- ADDRB => tied_to_ground_vec_i(8 downto 0),\r
- DIB => tied_to_ground_vec_i(31 downto 0),\r
- DIPB => tied_to_ground_vec_i(3 downto 0),\r
- DOB => open, \r
- DOPB => open, \r
- WEB => tied_to_ground_i,\r
- ENB => tied_to_ground_i,\r
- SSRB => tied_to_ground_i,\r
- CLKB => tied_to_ground_i \r
- ); \r
-\r
-end RTL;\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
-\r
- <!-- -->\r
-\r
- <!-- For tool use only. Do not edit. -->\r
-\r
- <!-- -->\r
-\r
- <!-- ProjectNavigator created generated project file. -->\r
-\r
- <!-- For use in tracking generated file and other information -->\r
-\r
- <!-- allowing preservation of process status. -->\r
-\r
- <!-- -->\r
-\r
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
-\r
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
-\r
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="gtxVirtex6FEE80.xise"/>\r
-\r
- <files xmlns="http://www.xilinx.com/XMLSchema">\r
- <file xil_pn:fileType="FILE_VHO" xil_pn:name="gtxvirtex6fee80.vho" xil_pn:origination="imported"/>\r
- </files>\r
-\r
- <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
- <transform xil_pn:end_ts="1409562302" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1409562302">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2856154284446432025" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4212411167637456903" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6456468924679109783" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- </transforms>\r
-\r
-</generated_project>\r
+++ /dev/null
-------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : gtxvirtex6fee80.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Instantiation Template\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-\r
-\r
---**************************Component Declarations*****************************\r
-\r
-\r
-component gtxVirtex6FEE80 \r
-generic\r
-(\r
- -- Simulation attributes\r
- WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
-);\r
-port\r
-(\r
- \r
- --_________________________________________________________________________\r
- --_________________________________________________________________________\r
- --GTX0 (X0_Y12)\r
-\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GTX0_RXCHARISK_OUT : out std_logic;
- GTX0_RXDISPERR_OUT : out std_logic;
- GTX0_RXNOTINTABLE_OUT : out std_logic;
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GTX0_RXENMCOMMAALIGN_IN : in std_logic;
- GTX0_RXENPCOMMAALIGN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
- GTX0_RXRECCLK_OUT : out std_logic;
- GTX0_RXRESET_IN : in std_logic;
- GTX0_RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GTX0_RXCDRRESET_IN : in std_logic;
- GTX0_RXN_IN : in std_logic;
- GTX0_RXP_IN : in std_logic;
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
- GTX0_RXDLYALIGNMONENB_IN : in std_logic;
- GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
- GTX0_RXDLYALIGNRESET_IN : in std_logic;
- GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
- GTX0_RXPMASETPHASE_IN : in std_logic;
- GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTX0_GTXRXRESET_IN : in std_logic;
- GTX0_MGTREFCLKRX_IN : in std_logic;
- GTX0_PLLRXRESET_IN : in std_logic;
- GTX0_RXPLLLKDET_OUT : out std_logic;
- GTX0_RXRESETDONE_OUT : out std_logic;
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- GTX0_PHYSTATUS_OUT : out std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GTX0_TXCHARISK_IN : in std_logic;
- ------------------------- Transmit Ports - GTX Ports -----------------------
- GTX0_GTXTEST_IN : in std_logic_vector(12 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
- GTX0_TXOUTCLK_OUT : out std_logic;
- GTX0_TXRESET_IN : in std_logic;
- GTX0_TXUSRCLK2_IN : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTX0_TXN_OUT : out std_logic;
- GTX0_TXP_OUT : out std_logic;
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
- GTX0_TXDLYALIGNMONENB_IN : in std_logic;
- GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- GTX0_TXDLYALIGNRESET_IN : in std_logic;
- GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
- GTX0_TXPMASETPHASE_IN : in std_logic;
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTX0_GTXTXRESET_IN : in std_logic;
- GTX0_TXRESETDONE_OUT : out std_logic
-\r
-\r
-);\r
-end component;\r
-\r
-\r
-\r
-component gtxvirtex6fee80_tx_sync \r
-port\r
-(\r
- TXENPMAPHASEALIGN : out std_logic;\r
- TXPMASETPHASE : out std_logic;\r
- TXDLYALIGNDISABLE : out std_logic;\r
- TXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-end component;\r
-\r
-component gtxvirtex6fee80_rx_sync \r
-port\r
-(\r
- RXENPMAPHASEALIGN : out std_logic;\r
- RXPMASETPHASE : out std_logic;\r
- RXDLYALIGNDISABLE : out std_logic;\r
- RXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
- ----------------------------- The GTX Wrapper -----------------------------\r
-\r
-\r
- gtxVirtex6FEE80_i : gtxVirtex6FEE80\r
- generic map\r
- (\r
- WRAPPER_SIM_GTXRESET_SPEEDUP => 1\r
- )\r
- port map\r
- (\r
- --_____________________________________________________________________\r
- --_____________________________________________________________________\r
- --GTX0 (X0Y12)\r
-\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GTX0_RXCHARISK_OUT => ,
- GTX0_RXDISPERR_OUT => ,
- GTX0_RXNOTINTABLE_OUT => ,
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GTX0_RXENMCOMMAALIGN_IN => ,
- GTX0_RXENPCOMMAALIGN_IN => ,
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTX0_RXDATA_OUT => ,
- GTX0_RXRECCLK_OUT => ,
- GTX0_RXRESET_IN => ,
- GTX0_RXUSRCLK2_IN => ,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GTX0_RXCDRRESET_IN => ,
- GTX0_RXN_IN => ,
- GTX0_RXP_IN => ,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GTX0_RXDLYALIGNDISABLE_IN => ,
- GTX0_RXDLYALIGNMONENB_IN => ,
- GTX0_RXDLYALIGNMONITOR_OUT => ,
- GTX0_RXDLYALIGNOVERRIDE_IN => ,
- GTX0_RXDLYALIGNRESET_IN => ,
- GTX0_RXENPMAPHASEALIGN_IN => ,
- GTX0_RXPMASETPHASE_IN => ,
- GTX0_RXSTATUS_OUT => ,
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- GTX0_RXLOSSOFSYNC_OUT => ,
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTX0_GTXRXRESET_IN => ,
- GTX0_MGTREFCLKRX_IN => ,
- GTX0_PLLRXRESET_IN => ,
- GTX0_RXPLLLKDET_OUT => ,
- GTX0_RXRESETDONE_OUT => ,
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- GTX0_PHYSTATUS_OUT => ,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GTX0_TXCHARISK_IN => ,
- ------------------------- Transmit Ports - GTX Ports -----------------------
- GTX0_GTXTEST_IN => ,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTX0_TXDATA_IN => ,
- GTX0_TXOUTCLK_OUT => ,
- GTX0_TXRESET_IN => ,
- GTX0_TXUSRCLK2_IN => ,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTX0_TXN_OUT => ,
- GTX0_TXP_OUT => ,
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- GTX0_TXDLYALIGNDISABLE_IN => ,
- GTX0_TXDLYALIGNMONENB_IN => ,
- GTX0_TXDLYALIGNMONITOR_OUT => ,
- GTX0_TXDLYALIGNRESET_IN => ,
- GTX0_TXENPMAPHASEALIGN_IN => ,
- GTX0_TXPMASETPHASE_IN => ,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTX0_GTXTXRESET_IN => ,
- GTX0_TXRESETDONE_OUT =>
-\r
-\r
- );\r
-\r
-\r
-\r
- -----------------------Dedicated GTX Reference Clock Inputs ---------------\r
- -- Each dedicated refclk you are using in your design will need its own IBUFDS_GTXE1 instance\r
- \r
- q3_clk0_refclk_ibufds_i : IBUFDS_GTXE1\r
- port map\r
- (\r
- O => ,\r
- ODIV2 => ,\r
- CEB => ,\r
- I => , -- Connect to package pin L4\r
- IB => -- Connect to package pin L3\r
- );\r
-\r
-\r
-\r
-\r
-\r
- ------------------------------ TXSYNC module ------------------------------\r
- -- Since you are bypassing the TX Buffer in your wrapper, you will need to drive\r
- -- the phase alignment ports to align the phase of the TX Datapath. Include\r
- -- this module in your design to have phase alignment performed automatically as\r
- -- it is done in the example design.\r
-\r
- \r
- gtx0_txsync_i : gtxvirtex6fee80_tx_sync\r
- port map\r
- (\r
- TXENPMAPHASEALIGN => \r
- TXPMASETPHASE => \r
- TXDLYALIGNDISABLE => \r
- TXDLYALIGNRESET => \r
- SYNC_DONE => \r
- USER_CLK => \r
- RESET => ,\r
- );\r
-\r
-\r
- ---------------------------- RXSYNC modules -------------------------------\r
- -- The RXSYNC module performs phase synchronization for all the active RX datapaths. It\r
- -- waits for the user clocks to be stable, then drives the RX phase align signals on each\r
- -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
- \r
- -- Include one RX_SYNC module per Buffer bypassed RX datapath in your own design. RX_SYNC modules\r
- -- can also be shared, but when sharing, make sure to hold the module in reset until all lanes have \r
- -- a stable clock\r
- \r
- \r
- \r
- gtx0_rxsync_i : gtxvirtex6fee80_rx_sync\r
- port map\r
- (\r
- RXENPMAPHASEALIGN => \r
- RXPMASETPHASE => \r
- RXDLYALIGNDISABLE => \r
- RXDLYALIGNRESET => \r
- SYNC_DONE => \r
- USER_CLK => \r
- RESET => ,\r
- );\r
- \r
-\r
-\r
-\r
-\r
-\r
-\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Mon Dec 01 12:54:17 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:v6_gtxwizard:1.12\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT Virtex-6_FPGA_GTX_Transceiver_Wizard xilinx.com:ip:v6_gtxwizard:1.12\r
-# END Select\r
-# BEGIN Parameters\r
-CSET advanced_clocking=false\r
-CSET bytes_to_reduce_error=8\r
-CSET cb_seq_1_1=00000000\r
-CSET cb_seq_1_1_disp=false\r
-CSET cb_seq_1_1_k=false\r
-CSET cb_seq_1_1_mask=true\r
-CSET cb_seq_1_2=00000000\r
-CSET cb_seq_1_2_disp=false\r
-CSET cb_seq_1_2_k=false\r
-CSET cb_seq_1_2_mask=true\r
-CSET cb_seq_1_3=00000000\r
-CSET cb_seq_1_3_disp=false\r
-CSET cb_seq_1_3_k=false\r
-CSET cb_seq_1_3_mask=true\r
-CSET cb_seq_1_4=00000000\r
-CSET cb_seq_1_4_disp=false\r
-CSET cb_seq_1_4_k=false\r
-CSET cb_seq_1_4_mask=true\r
-CSET cb_seq_2_1=00000000\r
-CSET cb_seq_2_1_disp=false\r
-CSET cb_seq_2_1_k=false\r
-CSET cb_seq_2_1_mask=true\r
-CSET cb_seq_2_2=00000000\r
-CSET cb_seq_2_2_disp=false\r
-CSET cb_seq_2_2_k=false\r
-CSET cb_seq_2_2_mask=true\r
-CSET cb_seq_2_3=00000000\r
-CSET cb_seq_2_3_disp=false\r
-CSET cb_seq_2_3_k=false\r
-CSET cb_seq_2_3_mask=true\r
-CSET cb_seq_2_4=00000000\r
-CSET cb_seq_2_4_disp=false\r
-CSET cb_seq_2_4_k=false\r
-CSET cb_seq_2_4_mask=true\r
-CSET cb_sequence_1_max_skew=1\r
-CSET cb_sequence_2_max_skew=1\r
-CSET cb_sequence_length=1\r
-CSET cc_keep_one_idle=false\r
-CSET cc_seq_1_1=00000000\r
-CSET cc_seq_1_1_disp=false\r
-CSET cc_seq_1_1_k=true\r
-CSET cc_seq_1_1_mask=true\r
-CSET cc_seq_1_2=00000000\r
-CSET cc_seq_1_2_disp=false\r
-CSET cc_seq_1_2_k=true\r
-CSET cc_seq_1_2_mask=true\r
-CSET cc_seq_1_3=00000000\r
-CSET cc_seq_1_3_disp=false\r
-CSET cc_seq_1_3_k=true\r
-CSET cc_seq_1_3_mask=true\r
-CSET cc_seq_1_4=00000000\r
-CSET cc_seq_1_4_disp=false\r
-CSET cc_seq_1_4_k=true\r
-CSET cc_seq_1_4_mask=true\r
-CSET cc_seq_2_1=00000000\r
-CSET cc_seq_2_1_disp=false\r
-CSET cc_seq_2_1_k=true\r
-CSET cc_seq_2_1_mask=true\r
-CSET cc_seq_2_2=00000000\r
-CSET cc_seq_2_2_disp=false\r
-CSET cc_seq_2_2_k=true\r
-CSET cc_seq_2_2_mask=true\r
-CSET cc_seq_2_3=00000000\r
-CSET cc_seq_2_3_disp=false\r
-CSET cc_seq_2_3_k=true\r
-CSET cc_seq_2_3_mask=true\r
-CSET cc_seq_2_4=00000000\r
-CSET cc_seq_2_4_disp=false\r
-CSET cc_seq_2_4_k=true\r
-CSET cc_seq_2_4_mask=true\r
-CSET cc_sequence_length=1\r
-CSET cdr_ph_adj_time=10100\r
-CSET chan_bond_keep_align=false\r
-CSET chan_bond_seq_2_cfg=00000\r
-CSET clk_cor_precedence=CC\r
-CSET clk_cor_repeat_wait=0\r
-CSET column=Left\r
-CSET com_burst_val=15\r
-CSET comma_alignment=Any_Byte_Boundary\r
-CSET comma_double=false\r
-CSET comma_mask=1111111100\r
-CSET comma_preset=K28.5\r
-CSET component_name=gtxVirtex6FEE80\r
-CSET dec_mcomma_detect=false\r
-CSET dec_pcomma_detect=false\r
-CSET dec_valid_comma_only=false\r
-CSET decoding=8B/10B\r
-CSET dfe_mode=Fixed_tap_mode\r
-CSET disable_ac_coupling=true\r
-CSET driver_swing=1000\r
-CSET en_idle_reset_buf=false\r
-CSET enable_dfe=false\r
-CSET encoding=8B/10B\r
-CSET errors_to_lose_sync=256\r
-CSET fifo_lower_bounds=14\r
-CSET fifo_upper_bounds=16\r
-CSET highpass_pole_location=Use_RXEQPOLE_Port\r
-CSET max_cb_level=7\r
-CSET mcomma_detect=true\r
-CSET minus_comma=1010000011\r
-CSET oob_clk_divider=0000000\r
-CSET pci_express_mode=false\r
-CSET pcomma_detect=true\r
-CSET pll_sata=false\r
-CSET plus_comma=0101111100\r
-CSET postemphasis_level=00000\r
-CSET ppm_offset=0_(Synchronous)\r
-CSET preemphasis_level=0000\r
-CSET protocol_file=Start_from_scratch\r
-CSET refclk_ac_coupling_x0_y0=false\r
-CSET refclk_ac_coupling_x0_y1=false\r
-CSET refclk_ac_coupling_x0_y10=false\r
-CSET refclk_ac_coupling_x0_y11=false\r
-CSET refclk_ac_coupling_x0_y12=false\r
-CSET refclk_ac_coupling_x0_y13=false\r
-CSET refclk_ac_coupling_x0_y14=false\r
-CSET refclk_ac_coupling_x0_y15=false\r
-CSET refclk_ac_coupling_x0_y16=false\r
-CSET refclk_ac_coupling_x0_y17=false\r
-CSET refclk_ac_coupling_x0_y18=false\r
-CSET refclk_ac_coupling_x0_y19=false\r
-CSET refclk_ac_coupling_x0_y2=false\r
-CSET refclk_ac_coupling_x0_y20=false\r
-CSET refclk_ac_coupling_x0_y21=false\r
-CSET refclk_ac_coupling_x0_y22=false\r
-CSET refclk_ac_coupling_x0_y23=false\r
-CSET refclk_ac_coupling_x0_y3=false\r
-CSET refclk_ac_coupling_x0_y4=false\r
-CSET refclk_ac_coupling_x0_y5=false\r
-CSET refclk_ac_coupling_x0_y6=false\r
-CSET refclk_ac_coupling_x0_y7=false\r
-CSET refclk_ac_coupling_x0_y8=false\r
-CSET refclk_ac_coupling_x0_y9=false\r
-CSET rx_datapath_width=8\r
-CSET rx_decode_seq_match=true\r
-CSET rx_divider=/2\r
-CSET rx_en_idle_hold_cdr=false\r
-CSET rx_en_idle_hold_dfe=true\r
-CSET rx_en_idle_reset_fr=false\r
-CSET rx_en_idle_reset_ph=false\r
-CSET rx_en_mode_reset_buf=true\r
-CSET rx_en_rate_reset_buf=true\r
-CSET rx_en_realign_reset_buf=false\r
-CSET rx_fifo_addr_mode=FULL\r
-CSET rx_idle_hi_cnt=1000\r
-CSET rx_idle_lo_cnt=0000\r
-CSET rx_line_rate=2\r
-CSET rx_oob_threshold=011\r
-CSET rx_refclk_x0_y0=REFCLK1_Q0\r
-CSET rx_refclk_x0_y1=REFCLK1_Q0\r
-CSET rx_refclk_x0_y10=REFCLK1_Q2\r
-CSET rx_refclk_x0_y11=REFCLK1_Q2\r
-CSET rx_refclk_x0_y12=REFCLK0_Q3\r
-CSET rx_refclk_x0_y13=REFCLK1_Q3\r
-CSET rx_refclk_x0_y14=REFCLK1_Q3\r
-CSET rx_refclk_x0_y15=REFCLK1_Q3\r
-CSET rx_refclk_x0_y16=REFCLK1_Q4\r
-CSET rx_refclk_x0_y17=REFCLK1_Q4\r
-CSET rx_refclk_x0_y18=REFCLK1_Q4\r
-CSET rx_refclk_x0_y19=REFCLK1_Q4\r
-CSET rx_refclk_x0_y2=REFCLK1_Q0\r
-CSET rx_refclk_x0_y20=REFCLK1_Q5\r
-CSET rx_refclk_x0_y21=REFCLK1_Q5\r
-CSET rx_refclk_x0_y22=REFCLK1_Q5\r
-CSET rx_refclk_x0_y23=REFCLK1_Q5\r
-CSET rx_refclk_x0_y24=REFCLK1_Q6\r
-CSET rx_refclk_x0_y25=REFCLK1_Q6\r
-CSET rx_refclk_x0_y26=REFCLK1_Q6\r
-CSET rx_refclk_x0_y27=REFCLK1_Q6\r
-CSET rx_refclk_x0_y28=REFCLK1_Q7\r
-CSET rx_refclk_x0_y29=REFCLK1_Q7\r
-CSET rx_refclk_x0_y3=REFCLK1_Q0\r
-CSET rx_refclk_x0_y30=REFCLK1_Q7\r
-CSET rx_refclk_x0_y31=REFCLK1_Q7\r
-CSET rx_refclk_x0_y32=REFCLK1_Q8\r
-CSET rx_refclk_x0_y33=REFCLK1_Q8\r
-CSET rx_refclk_x0_y34=REFCLK1_Q8\r
-CSET rx_refclk_x0_y35=REFCLK1_Q8\r
-CSET rx_refclk_x0_y4=REFCLK1_Q1\r
-CSET rx_refclk_x0_y5=REFCLK1_Q1\r
-CSET rx_refclk_x0_y6=REFCLK1_Q1\r
-CSET rx_refclk_x0_y7=REFCLK1_Q1\r
-CSET rx_refclk_x0_y8=REFCLK1_Q2\r
-CSET rx_refclk_x0_y9=REFCLK1_Q2\r
-CSET rx_reference_clock=80.00\r
-CSET rx_slide_mode=OFF\r
-CSET rx_termination_voltage=MGTAVTT\r
-CSET rxlossofsyncport=true\r
-CSET rxrecclk_source=AUTO\r
-CSET rxrundisp_indicates_cc=false\r
-CSET rxusrclk_source=RXRECCLK\r
-CSET sas_max_comsas=52\r
-CSET sas_min_comsas=40\r
-CSET sata_burst_val=4\r
-CSET sata_idle_val=4\r
-CSET second_order_cdr_loop=false\r
-CSET show_realign_comma=true\r
-CSET sync_app=true\r
-CSET termination_ctrl=00000\r
-CSET termination_imp=50\r
-CSET termination_ovrd=false\r
-CSET trans_time_from_p2=60\r
-CSET trans_time_non_p2=25\r
-CSET trans_time_rate=FF\r
-CSET trans_time_to_p2=100\r
-CSET tx_datapath_width=8\r
-CSET tx_divider=/2\r
-CSET tx_drive_mode=DIRECT\r
-CSET tx_en_rate_reset_buf=true\r
-CSET tx_idle_assert_delay=100\r
-CSET tx_idle_deassert_delay=010\r
-CSET tx_line_rate=2\r
-CSET tx_refclk_x0_y0=use_rx_pll\r
-CSET tx_refclk_x0_y1=use_rx_pll\r
-CSET tx_refclk_x0_y10=use_rx_pll\r
-CSET tx_refclk_x0_y11=use_rx_pll\r
-CSET tx_refclk_x0_y12=use_rx_pll\r
-CSET tx_refclk_x0_y13=use_rx_pll\r
-CSET tx_refclk_x0_y14=use_rx_pll\r
-CSET tx_refclk_x0_y15=use_rx_pll\r
-CSET tx_refclk_x0_y16=use_rx_pll\r
-CSET tx_refclk_x0_y17=use_rx_pll\r
-CSET tx_refclk_x0_y18=use_rx_pll\r
-CSET tx_refclk_x0_y19=use_rx_pll\r
-CSET tx_refclk_x0_y2=use_rx_pll\r
-CSET tx_refclk_x0_y20=use_rx_pll\r
-CSET tx_refclk_x0_y21=use_rx_pll\r
-CSET tx_refclk_x0_y22=use_rx_pll\r
-CSET tx_refclk_x0_y23=use_rx_pll\r
-CSET tx_refclk_x0_y24=use_rx_pll\r
-CSET tx_refclk_x0_y25=use_rx_pll\r
-CSET tx_refclk_x0_y26=use_rx_pll\r
-CSET tx_refclk_x0_y27=use_rx_pll\r
-CSET tx_refclk_x0_y28=use_rx_pll\r
-CSET tx_refclk_x0_y29=use_rx_pll\r
-CSET tx_refclk_x0_y3=use_rx_pll\r
-CSET tx_refclk_x0_y30=use_rx_pll\r
-CSET tx_refclk_x0_y31=use_rx_pll\r
-CSET tx_refclk_x0_y32=use_rx_pll\r
-CSET tx_refclk_x0_y33=use_rx_pll\r
-CSET tx_refclk_x0_y34=use_rx_pll\r
-CSET tx_refclk_x0_y35=use_rx_pll\r
-CSET tx_refclk_x0_y4=use_rx_pll\r
-CSET tx_refclk_x0_y5=use_rx_pll\r
-CSET tx_refclk_x0_y6=use_rx_pll\r
-CSET tx_refclk_x0_y7=use_rx_pll\r
-CSET tx_refclk_x0_y8=use_rx_pll\r
-CSET tx_refclk_x0_y9=use_rx_pll\r
-CSET tx_reference_clock=80.00\r
-CSET tx_tdcc_cfg=11\r
-CSET txoutclk_source=AUTO\r
-CSET txpll_sata=00\r
-CSET txrx_invert=00011\r
-CSET txusrclk_source=TXOUTCLK\r
-CSET use_cb=false\r
-CSET use_cc=false\r
-CSET use_comma_detect=true\r
-CSET use_external_rxusrclk=false\r
-CSET use_external_txusrclk=false\r
-CSET use_gtx_x0_y0=false\r
-CSET use_gtx_x0_y1=false\r
-CSET use_gtx_x0_y10=false\r
-CSET use_gtx_x0_y11=false\r
-CSET use_gtx_x0_y12=true\r
-CSET use_gtx_x0_y13=false\r
-CSET use_gtx_x0_y14=false\r
-CSET use_gtx_x0_y15=false\r
-CSET use_gtx_x0_y16=false\r
-CSET use_gtx_x0_y17=false\r
-CSET use_gtx_x0_y18=false\r
-CSET use_gtx_x0_y19=false\r
-CSET use_gtx_x0_y2=false\r
-CSET use_gtx_x0_y20=false\r
-CSET use_gtx_x0_y21=false\r
-CSET use_gtx_x0_y22=false\r
-CSET use_gtx_x0_y23=false\r
-CSET use_gtx_x0_y24=false\r
-CSET use_gtx_x0_y25=false\r
-CSET use_gtx_x0_y26=false\r
-CSET use_gtx_x0_y27=false\r
-CSET use_gtx_x0_y28=false\r
-CSET use_gtx_x0_y29=false\r
-CSET use_gtx_x0_y3=false\r
-CSET use_gtx_x0_y30=false\r
-CSET use_gtx_x0_y31=false\r
-CSET use_gtx_x0_y32=false\r
-CSET use_gtx_x0_y33=false\r
-CSET use_gtx_x0_y34=false\r
-CSET use_gtx_x0_y35=false\r
-CSET use_gtx_x0_y4=false\r
-CSET use_gtx_x0_y5=false\r
-CSET use_gtx_x0_y6=false\r
-CSET use_gtx_x0_y7=false\r
-CSET use_gtx_x0_y8=false\r
-CSET use_gtx_x0_y9=false\r
-CSET use_no_rx=false\r
-CSET use_no_tx=false\r
-CSET use_port_comfinish=false\r
-CSET use_port_cominitdet=false\r
-CSET use_port_comsasdet=false\r
-CSET use_port_comwakedet=false\r
-CSET use_port_drp=false\r
-CSET use_port_enmcommaalign=true\r
-CSET use_port_enpcommaalign=true\r
-CSET use_port_gtxtest=false\r
-CSET use_port_loopback=false\r
-CSET use_port_phystatus=true\r
-CSET use_port_plllkdet=true\r
-CSET use_port_plllkdeten=true\r
-CSET use_port_pllpowerdown=false\r
-CSET use_port_refclkpowerdown=false\r
-CSET use_port_rxbufreset=false\r
-CSET use_port_rxbufstatus=false\r
-CSET use_port_rxbyteisaligned=false\r
-CSET use_port_rxbyterealign=false\r
-CSET use_port_rxcdrreset=true\r
-CSET use_port_rxchariscomma=false\r
-CSET use_port_rxcharisk=true\r
-CSET use_port_rxcommadet=false\r
-CSET use_port_rxlossofsync=true\r
-CSET use_port_rxoversampleerr=false\r
-CSET use_port_rxpolarity=false\r
-CSET use_port_rxpowerdown=false\r
-CSET use_port_rxrate=false\r
-CSET use_port_rxrecclk=true\r
-CSET use_port_rxreset=true\r
-CSET use_port_rxrundisp=false\r
-CSET use_port_rxslide=false\r
-CSET use_port_rxstatus=true\r
-CSET use_port_rxvalid=false\r
-CSET use_port_txbufstatus=false\r
-CSET use_port_txbypass8b10b=false\r
-CSET use_port_txchardispmode=false\r
-CSET use_port_txchardispval=false\r
-CSET use_port_txcominit=false\r
-CSET use_port_txcomsas=false\r
-CSET use_port_txcomwake=false\r
-CSET use_port_txdetectrx=false\r
-CSET use_port_txelecidle=false\r
-CSET use_port_txenprbstst=false\r
-CSET use_port_txinhibit=false\r
-CSET use_port_txkerr=false\r
-CSET use_port_txoutclk=true\r
-CSET use_port_txpolarity=false\r
-CSET use_port_txpowerdown=false\r
-CSET use_port_txprbsforceerr=false\r
-CSET use_port_txrate=false\r
-CSET use_port_txreset=true\r
-CSET use_port_txrundisp=false\r
-CSET use_prbs_detector=false\r
-CSET use_resistor_cal_circuit=false\r
-CSET use_rx_eq=false\r
-CSET use_rx_oob=false\r
-CSET use_rx_oversampling=false\r
-CSET use_rxbuffer=false\r
-CSET use_rxpllrefclk=false\r
-CSET use_rxprbserr_loopback=false\r
-CSET use_turbo_mode=false\r
-CSET use_two_cb_sequences=false\r
-CSET use_two_cc_sequences=false\r
-CSET use_tx_oversampling=false\r
-CSET use_txbuffer=false\r
-CSET use_txpllrefclk=false\r
-CSET wideband_highpass_mix=000\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2011-04-08T05:24:23Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: dc79b500\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="gtxVirtex6FEE80/example_design/mgt_usrclk_source_mmcm.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/example_design/double_reset.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_tx_sync.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_rx_sync.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/example_design/frame_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/example_design/frame_check.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_top.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
- </file>
- <file xil_pn:name="gtxvirtex6fee80_gtx.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
- </file>
- <file xil_pn:name="gtxvirtex6fee80.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/example_design/gtx_attributes.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/implement/data_vio.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/implement/icon.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- </file>
- <file xil_pn:name="gtxVirtex6FEE80/implement/ila.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gtxVirtex6FEE80_top|RTL" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_top.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gtxVirtex6FEE80_top" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="gtxVirtex6FEE80" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-12-01T13:54:54" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="DB12E7AF65204F95AA56371BC098BFF3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : double_reset.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module DOUBLE_RESET\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
-entity DOUBLE_RESET is\r
-port\r
-(\r
- CLK : in std_logic;\r
- PLLLKDET : in std_logic;\r
- GTXTEST_DONE : out std_logic;\r
- GTXTEST_BIT1 : out std_logic\r
-);\r
-\r
-end DOUBLE_RESET;\r
-\r
-architecture RTL of DOUBLE_RESET is\r
---***********************************Parameter Declarations********************\r
- constant DLY : time := 1 ns;\r
-\r
---*******************************Register Declarations************************\r
- signal plllkdet_sync : std_logic;\r
- signal plllkdet_r : std_logic;\r
- signal reset_dly_ctr : unsigned(10 downto 0);\r
- signal reset_dly_done : std_logic;\r
- signal testdone_f : std_logic_vector(3 downto 0);\r
-\r
-begin\r
---*******************************Main Body of Code****************************\r
-\r
- process(CLK )\r
- begin\r
- if(CLK'event and CLK = '1') then\r
- plllkdet_r <= PLLLKDET after DLY;\r
- plllkdet_sync <= plllkdet_r after DLY;\r
- end if;\r
- end process;\r
-\r
- GTXTEST_BIT1 <= reset_dly_done; \r
- GTXTEST_DONE <= testdone_f(0) when (reset_dly_ctr = b"00000000000") else '0';\r
-\r
- process(CLK )\r
- begin\r
- if(CLK'event and CLK = '1') then\r
- if (plllkdet_sync = '0') then\r
- reset_dly_ctr <= b"11111111111" after DLY;\r
- elsif (reset_dly_ctr /= b"00000000000") then\r
- reset_dly_ctr <= reset_dly_ctr - 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- process(CLK )\r
- begin\r
- if(CLK'event and CLK = '1') then\r
- if (plllkdet_sync = '0') then\r
- reset_dly_done <= '0' after DLY;\r
- elsif (reset_dly_ctr(10) = '0') then\r
- reset_dly_done <= reset_dly_ctr(8) after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- process(CLK )\r
- begin\r
- if(CLK'event and CLK = '1') then\r
- if(reset_dly_ctr /= b"00000000000") then\r
- testdone_f <= b"1111" after DLY;\r
- else\r
- testdone_f <= '0' & testdone_f(3 downto 1) after DLY; \r
- end if;\r
- end if;\r
- end process;\r
- \r
-\r
-end RTL;\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : frame_check.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\ \r
---\r
---\r
--- Module FRAME_CHECK\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard \r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-use ieee.numeric_std.all;\r
-use std.textio.all;\r
-use ieee.std_logic_textio.all;\r
-use ieee.std_logic_misc.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***********************************Entity Declaration************************\r
-\r
-entity FRAME_CHECK is\r
-generic\r
-(\r
- RX_DATA_WIDTH : integer := 16;\r
- RXCTRL_WIDTH : integer := 2;\r
- USE_COMMA : integer := 1;\r
- NONE_MSB_FIRST_DEC : integer := 0;\r
- COMMA_DOUBLE_DEC : integer := 0;\r
- CHANBOND_SEQ_LEN : integer := 1;\r
- WORDS_IN_BRAM : integer := 256;\r
- CONFIG_INDEPENDENT_LANES : integer := 0;\r
- START_OF_PACKET_CHAR : std_logic_vector(15 downto 0) ;\r
- COMMA_DOUBLE_CHAR : std_logic_vector(15 downto 0) := x"f628";\r
- MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"\r
-);\r
-port\r
-(\r
- -- User Interface\r
- RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0); \r
- RXCTRL_IN : in std_logic_vector((RXCTRL_WIDTH-1) downto 0); \r
- \r
- RX_ENMCOMMA_ALIGN : out std_logic;\r
- RX_ENPCOMMA_ALIGN : out std_logic;\r
- RX_ENCHAN_SYNC : out std_logic; \r
- RX_CHANBOND_SEQ : in std_logic; \r
-\r
- -- Control Interface\r
- INC_IN : in std_logic; \r
- INC_OUT : out std_logic; \r
- PATTERN_MATCH_N : out std_logic;\r
- RESET_ON_ERROR : in std_logic; \r
- \r
- -- Error Monitoring\r
- ERROR_COUNT : out std_logic_vector(7 downto 0);\r
- \r
- -- Track Data\r
- TRACK_DATA : out std_logic;\r
- \r
- -- System Interface\r
- USER_CLK : in std_logic; \r
- SYSTEM_RESET : in std_logic\r
- \r
-);\r
-\r
-\r
-end FRAME_CHECK;\r
-\r
-\r
-architecture RTL of FRAME_CHECK is\r
-\r
-\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
-\r
---***************************Internal Register Declarations********************\r
-\r
- signal begin_r : std_logic;\r
- signal data_error_detected_r : std_logic;\r
- signal error_count_r : unsigned(8 downto 0);\r
- signal error_detected_r : std_logic;\r
- signal read_counter_i : unsigned(8 downto 0); \r
- signal rx_chanbond_seq_r : std_logic;\r
- signal rx_chanbond_seq_r2 : std_logic;\r
- signal rx_chanbond_seq_r3 : std_logic;\r
- signal rx_data_r : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r2 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r3 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r4 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r5 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r6 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r7 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_r_track : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rxctrl_r : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
- signal rxctrl_r2 : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
- signal rxctrl_r3 : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
- signal rxctrl_or : std_logic;\r
- signal start_of_packet_detected_r : std_logic; \r
- signal track_data_r : std_logic;\r
- signal track_data_r2 : std_logic;\r
- signal track_data_r3 : std_logic;\r
- signal track_data_r4 : std_logic;\r
- signal sel : std_logic_vector(1 downto 0);\r
- signal bram_data_r : std_logic_vector(31 downto 0);\r
- \r
- \r
---*********************************Wire Declarations***************************\r
- \r
- signal bram_data_i : std_logic_vector(31 downto 0);\r
-\r
- signal chanbondseq_in_data : std_logic;\r
- signal error_detected_c : std_logic;\r
- signal input_to_chanbond_data_i : std_logic;\r
- signal input_to_chanbond_reg_i : std_logic;\r
- signal next_begin_c : std_logic;\r
- signal next_data_error_detected_c : std_logic;\r
- signal next_track_data_c : std_logic;\r
- signal start_of_packet_detected_c : std_logic;\r
- signal rx_chanbond_reg : std_logic_vector((CHANBOND_SEQ_LEN-1) downto 0);\r
- signal rx_chanbond_reg_bitwise_or_i: std_logic;\r
- signal rx_data_aligned : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- signal rx_data_has_start_char_c : std_logic;\r
- signal rx_data_matches_bram_c : std_logic;\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);\r
- signal tied_to_vcc_i : std_logic;\r
-\r
-\r
---*********************************Main Body of Code***************************\r
-begin\r
-\r
- --_______________________ Static signal Assigments _______________________ \r
-\r
- tied_to_ground_i <= '0';\r
- tied_to_ground_vec_i <= (others=>'0');\r
- tied_to_vcc_i <= '1';\r
-\r
- --______________________ Register RXDATA once to ease timing ______________ \r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- rx_data_r <= RX_DATA after DLY;\r
- end if;\r
- end process;\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- rxctrl_r <= RXCTRL_IN after DLY;\r
- end if;\r
- end process;\r
- --________________________________ State machine __________________________ \r
- \r
- \r
- -- State registers\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(RESET_ON_ERROR ='1' or SYSTEM_RESET = '1' ) then\r
- begin_r <= '1' after DLY;\r
- track_data_r <= '0' after DLY;\r
- data_error_detected_r <= '0' after DLY;\r
- else\r
- begin_r <= next_begin_c after DLY;\r
- track_data_r <= next_track_data_c after DLY;\r
- data_error_detected_r <= next_data_error_detected_c after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Next state logic\r
- next_begin_c <= (begin_r and not start_of_packet_detected_r) or data_error_detected_r ;\r
-\r
- next_track_data_c <= (begin_r and start_of_packet_detected_r) or (track_data_r and not error_detected_r);\r
- \r
- next_data_error_detected_c <= (track_data_r and error_detected_r); \r
- \r
- start_of_packet_detected_c <= INC_IN when (CONFIG_INDEPENDENT_LANES=0) else rx_data_has_start_char_c;\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- start_of_packet_detected_r <= start_of_packet_detected_c after DLY;\r
- end if; \r
- end process;\r
- \r
- -- Registering for timing\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- track_data_r2 <= track_data_r after DLY;\r
- end if; \r
- end process;\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- track_data_r3 <= track_data_r2 after DLY;\r
- end if; \r
- end process;\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- track_data_r4 <= track_data_r3 after DLY;\r
- end if; \r
- end process;\r
-\r
- --______________________________ Capture incoming data ____________________ \r
-\r
-\r
-\r
-datapath_width_32_40_16_or_20: if ((RX_DATA_WIDTH=16) or (RX_DATA_WIDTH=20) or (RX_DATA_WIDTH=32) or (RX_DATA_WIDTH=40)) generate\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- rx_data_r2 <= (others => '0') after DLY;\r
- rx_data_r4 <= (others => '0') after DLY;\r
- rx_data_r5 <= (others => '0') after DLY;\r
- rx_data_r6 <= (others => '0') after DLY;\r
- rx_data_r7 <= (others => '0') after DLY;\r
- rx_data_r_track <= (others => '0') after DLY;\r
- else\r
- rx_data_r2 <= rx_data_r after DLY;\r
- rx_data_r4 <= rx_data_r3 after DLY;\r
- rx_data_r5 <= rx_data_r4 after DLY;\r
- rx_data_r6 <= rx_data_r5 after DLY;\r
- rx_data_r7 <= rx_data_r6 after DLY;\r
- rx_data_r_track <= rx_data_r7 after DLY;\r
- end if;\r
- end if; \r
- end process;\r
-\r
- rx_data_aligned <= rx_data_r3;\r
-\r
- --___________________________ Code for Channel bonding ____________________ \r
- -- code to prevent checking of clock correction sequences for the start of packet char\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- rx_chanbond_seq_r <= RX_CHANBOND_SEQ after DLY;\r
- rx_chanbond_seq_r2 <= rx_chanbond_seq_r after DLY;\r
- rx_chanbond_seq_r3 <= rx_chanbond_seq_r2 after DLY;\r
- end if; \r
- end process;\r
-\r
- input_to_chanbond_reg_i <= rx_chanbond_seq_r2;\r
- input_to_chanbond_data_i <= tied_to_ground_i;\r
-end generate datapath_width_32_40_16_or_20;\r
-\r
-datapath_width_8_or_10: if ((RX_DATA_WIDTH=8) or (RX_DATA_WIDTH=10)) generate\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- rx_data_r2 <= (others => '0') after DLY;\r
- rx_data_r3 <= (others => '0') after DLY;\r
- rx_data_r4 <= (others => '0') after DLY;\r
- rx_data_r5 <= (others => '0') after DLY;\r
- rx_data_r_track <= (others => '0') after DLY;\r
- else\r
- rx_data_r2 <= rx_data_r after DLY;\r
- rx_data_r3 <= rx_data_r2 after DLY;\r
- rx_data_r4 <= rx_data_r3 after DLY;\r
- rx_data_r5 <= rx_data_r4 after DLY;\r
- rx_data_r_track <= rx_data_r5 after DLY;\r
- end if;\r
- end if; \r
- end process;\r
- \r
- rx_data_aligned <= RX_DATA;\r
- input_to_chanbond_reg_i <= RX_CHANBOND_SEQ;\r
- input_to_chanbond_data_i <= RX_CHANBOND_SEQ;\r
-end generate datapath_width_8_or_10;\r
-\r
-\r
-\r
- \r
-\r
-\r
-\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then\r
- rxctrl_r2 <= (others => '0') after DLY;\r
- rxctrl_r3 <= (others => '0') after DLY;\r
- else\r
- rxctrl_r2 <= rxctrl_r after DLY;\r
- rxctrl_r3 <= rxctrl_r2 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- --___________________________ Code for Channel bonding ____________________ \r
- -- code to prevent checking of clock correction sequences for the start of packet char\r
- register_chan_seq: for i in 0 to (CHANBOND_SEQ_LEN-1) generate\r
- case_i_equal_to_0: if (i=0) generate \r
- rx_chanbond_reg_0 : FD port map (Q => rx_chanbond_reg(i),D => input_to_chanbond_reg_i,C => USER_CLK);\r
- end generate case_i_equal_to_0;\r
- case_i_greater_than_0: if (i>0) generate \r
- rx_chanbond_reg_i :FD port map (Q => rx_chanbond_reg(i),D => rx_chanbond_reg(i-1),C => USER_CLK);\r
- end generate case_i_greater_than_0;\r
- end generate register_chan_seq;\r
- \r
- chanbondseq_in_data <= input_to_chanbond_data_i or rx_chanbond_reg_bitwise_or_i;\r
-\r
- process(rx_chanbond_reg)\r
- variable rx_chanbond_var : std_logic;\r
- variable i : std_logic;\r
- begin\r
- rx_chanbond_var := '0';\r
- bit_wise_or : for i in 0 to (CHANBOND_SEQ_LEN-1) loop\r
- rx_chanbond_var := rx_chanbond_var or rx_chanbond_reg(i);\r
- end loop;\r
- rx_chanbond_reg_bitwise_or_i <= rx_chanbond_var;\r
- end process;\r
-\r
- process(RXCTRL_IN)\r
- variable or_rxctrl_var : std_logic;\r
- variable i : std_logic;\r
- begin\r
- or_rxctrl_var := '0';\r
- bit_wise_rxctrl_or : for i in 0 to (RXCTRL_WIDTH-1) loop\r
- or_rxctrl_var := or_rxctrl_var or RXCTRL_IN(i);\r
- end loop;\r
- rxctrl_or <= or_rxctrl_var;\r
- end process;\r
-\r
-\r
-\r
- rx_data_has_start_char_c <= '1' when ((rx_data_aligned(7 downto 0) = START_OF_PACKET_CHAR(7 downto 0)) and (chanbondseq_in_data='0') and (rxctrl_or='1')) else '0';\r
-\r
- --_____________________________ Assign output ports _______________________ \r
-\r
- TRACK_DATA <= track_data_r; \r
-\r
-\r
- -- Drive the enamcommaalign port of the mgt for alignment\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- RX_ENMCOMMA_ALIGN <= '0' after DLY;\r
- else \r
- RX_ENMCOMMA_ALIGN <= '1' after DLY;\r
- end if;\r
- end if; \r
- end process;\r
-\r
- -- Drive the enapcommaalign port of the mgt for alignment\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- RX_ENPCOMMA_ALIGN <= '0' after DLY;\r
- else \r
- RX_ENPCOMMA_ALIGN <= '1' after DLY;\r
- end if;\r
- end if; \r
- end process;\r
-\r
- INC_OUT <= start_of_packet_detected_c; \r
-\r
- PATTERN_MATCH_N <= data_error_detected_r;\r
-\r
- -- Drive the enchansync port of the mgt for channel bonding\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET = '1') then \r
- RX_ENCHAN_SYNC <= '0' after DLY;\r
- else \r
- RX_ENCHAN_SYNC <= '1' after DLY;\r
- end if;\r
- end if; \r
- end process;\r
- \r
- --___________________________ Check incoming data for errors ______________\r
- \r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- bram_data_r <= bram_data_i after DLY;\r
- end if; \r
- end process;\r
- \r
- --An error is detected when data read for the BRAM does not match the incoming data\r
-use_40bit : if RX_DATA_WIDTH = 40 generate\r
- rx_data_matches_bram_c <= '0' when (rx_data_r_track /= (tied_to_ground_vec_i(7 downto 0) & bram_data_r)) else '1';\r
-end generate use_40bit;\r
-\r
-not_40bit : if RX_DATA_WIDTH /= 40 generate\r
- rx_data_matches_bram_c <= '0' when (rx_data_r_track /= bram_data_r((RX_DATA_WIDTH-1) downto 0)) else '1';\r
-end generate not_40bit;\r
-\r
- error_detected_c <= track_data_r4 and not rx_data_matches_bram_c; \r
- \r
- \r
-enable_error_check : if USE_COMMA = 1 generate\r
- --We register the error_detected signal for use with the error counter logic\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(not(track_data_r = '1')) then \r
- error_detected_r <= '0' after DLY;\r
- else\r
- error_detected_r <= error_detected_c after DLY;\r
- end if;\r
- end if; \r
- end process;\r
-end generate enable_error_check;\r
-\r
-disable_error_check : if USE_COMMA = 0 generate\r
- -- Since the comma detect logic has not been enabled, the error counter has been disabled since\r
- -- it doesnt make sense to be searching for an align character in the data. To enable the error \r
- -- count again, please see the code above\r
- \r
- error_detected_r <= '0';\r
-\r
-end generate disable_error_check;\r
-\r
- \r
- --We count the total number of errors we detect. By keeping a count we make it less likely that we will miss\r
- --errors we did not directly observe. This counter must be reset when it reaches its max value\r
- process ( USER_CLK )\r
- begin\r
- if( USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET='1') then\r
- error_count_r <= (others => '0') after DLY;\r
- elsif(error_detected_r = '1') then\r
- error_count_r <= error_count_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
- \r
- \r
- --Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches\r
- --max value) to the module output\r
- ERROR_COUNT <= std_logic_vector(error_count_r(7 downto 0));\r
-\r
- --____________________________ Counter to read from BRAM __________________________ \r
-four_byte : if RX_DATA_WIDTH > 20 generate\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))) then\r
- read_counter_i <= (others => '0') after DLY;\r
- elsif(((start_of_packet_detected_r and not track_data_r)='1')) then\r
- read_counter_i <= "000000001" after DLY;\r
- else read_counter_i <= read_counter_i + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-end generate four_byte;\r
-\r
-one_or_two_byte : if RX_DATA_WIDTH <= 20 generate\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))\r
- or ((start_of_packet_detected_r and not track_data_r)='1')) then\r
- read_counter_i <= (others => '0') after DLY;\r
- else read_counter_i <= read_counter_i + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-end generate one_or_two_byte;\r
-\r
- --________________________________ BRAM Instantiation _____________________________ \r
-\r
- dual_port_block_ram_i : RAMB16_S36_S36 \r
- generic map\r
- (\r
- INIT_00 => MEM_00,\r
- INIT_01 => MEM_01,\r
- INIT_02 => MEM_02,\r
- INIT_03 => MEM_03,\r
- INIT_04 => MEM_04,\r
- INIT_05 => MEM_05,\r
- INIT_06 => MEM_06,\r
- INIT_07 => MEM_07,\r
- INIT_08 => MEM_08,\r
- INIT_09 => MEM_09,\r
- INIT_0A => MEM_0A,\r
- INIT_0B => MEM_0B,\r
- INIT_0C => MEM_0C,\r
- INIT_0D => MEM_0D,\r
- INIT_0E => MEM_0E,\r
- INIT_0F => MEM_0F,\r
- INIT_10 => MEM_10,\r
- INIT_11 => MEM_11,\r
- INIT_12 => MEM_12,\r
- INIT_13 => MEM_13,\r
- INIT_14 => MEM_14,\r
- INIT_15 => MEM_15,\r
- INIT_16 => MEM_16,\r
- INIT_17 => MEM_17,\r
- INIT_18 => MEM_18,\r
- INIT_19 => MEM_19,\r
- INIT_1A => MEM_1A,\r
- INIT_1B => MEM_1B,\r
- INIT_1C => MEM_1C,\r
- INIT_1D => MEM_1D,\r
- INIT_1E => MEM_1E,\r
- INIT_1F => MEM_1F,\r
- INIT_20 => MEM_20,\r
- INIT_21 => MEM_21,\r
- INIT_22 => MEM_22,\r
- INIT_23 => MEM_23,\r
- INIT_24 => MEM_24,\r
- INIT_25 => MEM_25,\r
- INIT_26 => MEM_26,\r
- INIT_27 => MEM_27,\r
- INIT_28 => MEM_28,\r
- INIT_29 => MEM_29,\r
- INIT_2A => MEM_2A,\r
- INIT_2B => MEM_2B,\r
- INIT_2C => MEM_2C,\r
- INIT_2D => MEM_2D,\r
- INIT_2E => MEM_2E,\r
- INIT_2F => MEM_2F,\r
- INIT_30 => MEM_30,\r
- INIT_31 => MEM_31,\r
- INIT_32 => MEM_32,\r
- INIT_33 => MEM_33,\r
- INIT_34 => MEM_34,\r
- INIT_35 => MEM_35,\r
- INIT_36 => MEM_36,\r
- INIT_37 => MEM_37,\r
- INIT_38 => MEM_38,\r
- INIT_39 => MEM_39,\r
- INIT_3A => MEM_3A,\r
- INIT_3B => MEM_3B,\r
- INIT_3C => MEM_3C,\r
- INIT_3D => MEM_3D,\r
- INIT_3E => MEM_3E,\r
- INIT_3F => MEM_3F,\r
- INITP_00 => MEMP_00,\r
- INITP_01 => MEMP_01,\r
- INITP_02 => MEMP_02,\r
- INITP_03 => MEMP_03,\r
- INITP_04 => MEMP_04,\r
- INITP_05 => MEMP_05,\r
- INITP_06 => MEMP_06,\r
- INITP_07 => MEMP_07\r
-\r
- )\r
- port map \r
- (\r
- ADDRA => std_logic_vector(read_counter_i),\r
- DIA => tied_to_ground_vec_i(31 downto 0),\r
- DIPA => tied_to_ground_vec_i(3 downto 0),\r
- DOA => bram_data_i,\r
- DOPA => open, \r
- WEA => tied_to_ground_i,\r
- ENA => tied_to_vcc_i,\r
- SSRA => tied_to_ground_i, \r
- CLKA => USER_CLK,\r
- \r
- ADDRB => tied_to_ground_vec_i(8 downto 0),\r
- DIB => tied_to_ground_vec_i(31 downto 0),\r
- DIPB => tied_to_ground_vec_i(3 downto 0),\r
- DOB => open, \r
- DOPB => open, \r
- WEB => tied_to_ground_i,\r
- ENB => tied_to_ground_i,\r
- SSRB => tied_to_ground_i,\r
- CLKB => tied_to_ground_i \r
- ); \r
- \r
- \r
-end RTL; \r
-\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : frame_gen.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\ \r
---\r
---\r
--- Module FRAME_GEN\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***********************************Entity Declaration************************\r
-\r
-entity FRAME_GEN is\r
-generic\r
-(\r
- WORDS_IN_BRAM : integer := 256;\r
- MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"\r
-); \r
-port\r
-(\r
- -- User Interface\r
- TX_DATA : out std_logic_vector(39 downto 0);\r
- TX_CHARISK : out std_logic_vector(3 downto 0); \r
-\r
- -- System Interface\r
- USER_CLK : in std_logic; \r
- SYSTEM_RESET : in std_logic\r
-); \r
-\r
-\r
-end FRAME_GEN;\r
-\r
-architecture RTL of FRAME_GEN is\r
-\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
-\r
---********************************* Wire Declarations************************** \r
-\r
- signal tx_charisk_i : std_logic_vector(3 downto 0);\r
- signal tx_data_bram_i : std_logic_vector(31 downto 0);\r
- signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_vcc_i : std_logic;\r
- signal tied_to_vcc_vec_i : std_logic_vector(15 downto 0);\r
-\r
---***************************Internal signalister Declarations******************** \r
-\r
- signal read_counter_i : unsigned(8 downto 0); \r
-\r
-\r
---*********************************Main Body of Code***************************\r
-begin\r
-\r
- tied_to_ground_vec_i <= (others=>'0');\r
- tied_to_ground_i <= '0';\r
- tied_to_vcc_i <= '1';\r
- \r
- --__________________________ Counter to read from BRAM ____________________ \r
- \r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1)))then\r
- read_counter_i <= (others => '0') after DLY;\r
- else\r
- read_counter_i <= read_counter_i + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Assign TX_DATA to BRAM output\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET='1') then\r
- TX_DATA <= (others => '0') after DLY;\r
- else\r
- TX_DATA <= (tied_to_ground_vec_i(7 downto 0) & tx_data_bram_i) after DLY; \r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Assign TX_CHARISK to BRAM output\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(SYSTEM_RESET='1') then\r
- TX_CHARISK <= (others => '0') after DLY;\r
- else\r
- TX_CHARISK <= tx_charisk_i after DLY; \r
- end if;\r
- end if;\r
- end process;\r
-\r
- --______________________________ BRAM Instantiation _______________________ \r
-\r
- dual_port_block_ram_i : RAMB16_S36_S36 \r
- generic map\r
- (\r
- INIT_00 => MEM_00,\r
- INIT_01 => MEM_01,\r
- INIT_02 => MEM_02,\r
- INIT_03 => MEM_03,\r
- INIT_04 => MEM_04,\r
- INIT_05 => MEM_05,\r
- INIT_06 => MEM_06,\r
- INIT_07 => MEM_07,\r
- INIT_08 => MEM_08,\r
- INIT_09 => MEM_09,\r
- INIT_0A => MEM_0A,\r
- INIT_0B => MEM_0B,\r
- INIT_0C => MEM_0C,\r
- INIT_0D => MEM_0D,\r
- INIT_0E => MEM_0E,\r
- INIT_0F => MEM_0F,\r
- INIT_10 => MEM_10,\r
- INIT_11 => MEM_11,\r
- INIT_12 => MEM_12,\r
- INIT_13 => MEM_13,\r
- INIT_14 => MEM_14,\r
- INIT_15 => MEM_15,\r
- INIT_16 => MEM_16,\r
- INIT_17 => MEM_17,\r
- INIT_18 => MEM_18,\r
- INIT_19 => MEM_19,\r
- INIT_1A => MEM_1A,\r
- INIT_1B => MEM_1B,\r
- INIT_1C => MEM_1C,\r
- INIT_1D => MEM_1D,\r
- INIT_1E => MEM_1E,\r
- INIT_1F => MEM_1F,\r
- INIT_20 => MEM_20,\r
- INIT_21 => MEM_21,\r
- INIT_22 => MEM_22,\r
- INIT_23 => MEM_23,\r
- INIT_24 => MEM_24,\r
- INIT_25 => MEM_25,\r
- INIT_26 => MEM_26,\r
- INIT_27 => MEM_27,\r
- INIT_28 => MEM_28,\r
- INIT_29 => MEM_29,\r
- INIT_2A => MEM_2A,\r
- INIT_2B => MEM_2B,\r
- INIT_2C => MEM_2C,\r
- INIT_2D => MEM_2D,\r
- INIT_2E => MEM_2E,\r
- INIT_2F => MEM_2F,\r
- INIT_30 => MEM_30,\r
- INIT_31 => MEM_31,\r
- INIT_32 => MEM_32,\r
- INIT_33 => MEM_33,\r
- INIT_34 => MEM_34,\r
- INIT_35 => MEM_35,\r
- INIT_36 => MEM_36,\r
- INIT_37 => MEM_37,\r
- INIT_38 => MEM_38,\r
- INIT_39 => MEM_39,\r
- INIT_3A => MEM_3A,\r
- INIT_3B => MEM_3B,\r
- INIT_3C => MEM_3C,\r
- INIT_3D => MEM_3D,\r
- INIT_3E => MEM_3E,\r
- INIT_3F => MEM_3F,\r
- INITP_00 => MEMP_00,\r
- INITP_01 => MEMP_01,\r
- INITP_02 => MEMP_02,\r
- INITP_03 => MEMP_03,\r
- INITP_04 => MEMP_04,\r
- INITP_05 => MEMP_05,\r
- INITP_06 => MEMP_06,\r
- INITP_07 => MEMP_07\r
- )\r
- port map \r
- (\r
- ADDRA => std_logic_vector(read_counter_i),\r
- DIA => tied_to_ground_vec_i(31 downto 0),\r
- DIPA => tied_to_ground_vec_i(3 downto 0),\r
- DOA => tx_data_bram_i,\r
- DOPA => tx_charisk_i, \r
- WEA => tied_to_ground_i,\r
- ENA => tied_to_vcc_i,\r
- SSRA => tied_to_ground_i, \r
- CLKA => USER_CLK,\r
- \r
- ADDRB => tied_to_ground_vec_i(8 downto 0),\r
- DIB => tied_to_ground_vec_i(31 downto 0),\r
- DIPB => tied_to_ground_vec_i(3 downto 0),\r
- DOB => open, \r
- DOPB => open, \r
- WEB => tied_to_ground_i,\r
- ENB => tied_to_ground_i,\r
- SSRB => tied_to_ground_i,\r
- CLKB => tied_to_ground_i \r
- ); \r
-\r
-end RTL;\r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : gtxVirtex6FEE80_top.sdc\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\\r
-##\r
-##\r
-## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## Device: xc6vlx130t\r
-## Package: ff484\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-################################################################################\r
-\r
-\r
- \r
-# Buffer Constraints for synthesis\r
-define_attribute {n:gtx0_txoutclk_i} {syn_noclockbuf} {1};
-\r
-\r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : gtxVirtex6FEE80_top.ucf\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\\r
-##\r
-##\r
-## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## Device: xc6vlx130t\r
-## Package: ff484\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-################################## Clock Constraints ##########################\r
-\r
-NET "q3_clk0_refclk_i" TNM_NET = "q3_clk0_refclk_i";\r
-TIMESPEC "TS_q3_clk0_refclk_i" = PERIOD "q3_clk0_refclk_i" 12.5;\r
-\r
-\r
-\r
-# User Clock Constraints\r
-NET "gtx0_txusrclk2_i" TNM_NET = "gtx0_txusrclk2_i";
-TIMESPEC "TS_gtx0_txusrclk2_i" = PERIOD "gtx0_txusrclk2_i" 5.0;
-
-NET "gtx0_rxusrclk2_i" TNM_NET = "gtx0_rxusrclk2_i";
-TIMESPEC "TS_gtx0_rxusrclk2_i" = PERIOD "gtx0_rxusrclk2_i" 5.0;
-
-\r
-\r
-#################### locs for top level ports (ML623 Board) ###################\r
-\r
-\r
-\r
-####################### GTX reference clock constraints #######################\r
-NET Q3_CLK0_MGTREFCLK_PAD_N_IN LOC=L3;\r
-NET Q3_CLK0_MGTREFCLK_PAD_P_IN LOC=L4;\r
-\r
-\r
-################################# mgt wrapper constraints #####################\r
-\r
-##---------- Set placement for gtx0_gtx_wrapper_i/GTX_DUAL ------\r
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i LOC=GTXE1_X0Y12;\r
-\r
-\r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : gtxVirtex6FEE80_top.xcf\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\\r
-##\r
-##\r
-## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## Device: xc6vlx130t\r
-## Package: ff484\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-################################################################################\r
-\r
-\r
- \r
-# Buffer Constraints for synthesis\r
-BEGIN MODEL "gtxVirtex6FEE80_top"\r
-NET "gtx0_txoutclk_i" BUFFER_TYPE = none;
-\r
-END;\r
-\r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : gtx_attributes.ucf\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\\r
-##\r
-##\r
-## GTX ATTRIBUTES \r
-## This file contains the attributes for the active GTX transceivers in the\r
-## design. If you would like to use this file in your design, please make\r
-## sure that the path to the GTX instance is correct.\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-############################## Active GTX Attributes #######################\r
- \r
-##________________________ Attributes for GTX 0_____________________\r
- \r
-
-##--------------------------TX PLL----------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK_SOURCE = "RXPLL";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_OVERSAMPLE_MODE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_COM_CFG = 24'h21680a;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_CP_CFG = 8'h07;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_FB = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_OUT = 2;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_REF = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL45_FB = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_LKDET_CFG = 3'b111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK25_DIVIDER = 4;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_SATA = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_TDCC_CFG = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CAS_CLK_EN = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i POWER_SAVE = 10'b0000110100;
-
-##-----------------------TX Interface-------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_TXUSRCLK = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DATA_WIDTH = 10;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_USRCLK_CFG = 6'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_CTRL = "TXPLLREFCLK_DIV1";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_DLY = 10'b0000000000;
-
-##------------TX Buffering and Phase Alignment----------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_PMADATA_OPT = 1'b1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_TX_CFG = 20'h80082;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BUFFER_USE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BYTECLK_CFG = 6'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_EN_RATE_RESET_BUF = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_XCLK_SEL = "TXUSR";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_CTRINC = 4'b0100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_LPFINC = 4'b0110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_MONSEL = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_OVRDSETTING = 8'b10000000;
-
-##-----------------------TX Gearbox---------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEARBOX_ENDEC = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXGEARBOX_USE = "FALSE";
-
-##--------------TX Driver and OOB Signalling------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DRIVE_MODE = "DIRECT";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_ASSERT_DELAY = 3'b101;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_DEASSERT_DELAY = 3'b011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_HIZ = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_PD = "FALSE";
-
-##------------TX Pipe Control for PCI Express/SATA------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COM_BURST_VAL = 4'b1111;
-
-##----------------TX Attributes for PCI Express---------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_0 = 5'b11010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_1 = 5'b10000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_0 = 7'b1001110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_1 = 7'b1001001;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_2 = 7'b1000101;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_3 = 7'b1000010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_4 = 7'b1000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_0 = 7'b1000110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_1 = 7'b1000100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_2 = 7'b1000010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_3 = 7'b1000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_4 = 7'b1000000;
-
-##--------------------------RX PLL----------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_OVERSAMPLE_MODE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_COM_CFG = 24'h21680a;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_CP_CFG = 8'h07;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_FB = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_OUT = 2;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_REF = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL45_FB = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_LKDET_CFG = 3'b111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_CLK25_DIVIDER = 4;
-
-##-----------------------RX Interface-------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_RXUSRCLK = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DATA_WIDTH = 10;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_CTRL = "RXRECCLKPMA_DIV1";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_DLY = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXUSRCLK_DLY = 16'h0000;
-
-##--------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i AC_CAP_DIS = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CDR_PH_ADJ_TIME = 5'b10100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i OOBDETECT_THRESHOLD = 3'b011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CDR_SCAN = 27'h640404C;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RX_CFG = 25'h05ce008;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_GND = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_VTTRX = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_CDR = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_FR = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_PH = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DETECT_RX_CFG = 14'h1832;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_CTRL = 5'b00000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_OVRD = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CM_TRIM = 2'b01;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RXSYNC_CFG = 7'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CFG = 76'h0040000040000000003;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BGTEST_CFG = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BIAS_CFG = 17'h00000;
-
-##------------RX Decision Feedback Equalizer(DFE)-------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CAL_TIME = 5'b01100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CFG = 8'b00011011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_DFE = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_OFFSET = 8'h4C;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_SCANMODE = 2'b00;
-
-##-----------------------PRBS Detection-----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPRBSERR_LOOPBACK = 1'b0;
-
-##----------------Comma Detection and Alignment---------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i ALIGN_COMMA_WORD = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_10B_ENABLE = 10'b1111111100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_DOUBLE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_MCOMMA_DETECT = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_PCOMMA_DETECT = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_VALID_COMMA_ONLY = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_10B_VALUE = 10'b1010000011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_DETECT = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_10B_VALUE = 10'b0101111100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_DETECT = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DECODE_SEQ_MATCH = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_AUTO_WAIT = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_MODE = "OFF";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SHOW_REALIGN_COMMA = "TRUE";
-
-##---------------RX Loss-of-sync State Machine----------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_INVALID_INCR = 8;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_THRESHOLD = 256;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOSS_OF_SYNC_FSM = "TRUE";
-
-##-----------------------RX Gearbox---------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXGEARBOX_USE = "FALSE";
-
-##-----------RX Elastic Buffer and Phase alignment------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_BUFFER_USE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_BUF = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_MODE_RESET_BUF = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_RATE_RESET_BUF = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF2 = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_FIFO_ADDR_MODE = "FAST";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_HI_CNT = 4'b1000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_LO_CNT = 4'b0000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_XCLK_SEL = "RXUSR";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_CTRINC = 4'b1110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_EDGESET = 5'b00010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_LPFINC = 4'b1110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_MONSEL = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_OVRDSETTING = 8'b10000000;
-
-##----------------------Clock Correction----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_ADJ_LEN = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_DET_LEN = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_INSERT_IDLE_FLAG = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_KEEP_IDLE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MAX_LAT = 16;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MIN_LAT = 14;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_PRECEDENCE = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_REPEAT_WAIT = 0;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_1 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_2 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_3 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_4 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_ENABLE = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_1 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_2 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_3 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_4 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_ENABLE = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_USE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_CORRECT_USE = "FALSE";
-
-##----------------------Channel Bonding----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_1_MAX_SKEW = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_2_MAX_SKEW = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_KEEP_ALIGN = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_1 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_2 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_3 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_4 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_1 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_2 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_3 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_4 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_CFG = 5'b00000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_USE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_LEN = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCI_EXPRESS_MODE = "FALSE";
-
-##-----------RX Attributes for PCI Express/SATA/SAS----------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MAX_COMSAS = 52;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MIN_COMSAS = 40;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_BURST_VAL = 3'b100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_IDLE_VAL = 3'b100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_BURST = 11;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_INIT = 34;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_WAKE = 11;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_BURST = 6;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_INIT = 19;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_WAKE = 6;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_FROM_P2 = 12'h03c;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_NON_P2 = 8'h19;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_RATE = 8'hff;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_TO_P2 = 10'h064;
-\r
-\r
-\r
+++ /dev/null
-------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : gtxvirtex6fee80_rx_sync.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module gtxvirtex6fee80_rx_sync\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
-entity gtxvirtex6fee80_rx_sync is\r
-port\r
-(\r
- RXENPMAPHASEALIGN : out std_logic;\r
- RXPMASETPHASE : out std_logic;\r
- RXDLYALIGNDISABLE : out std_logic;\r
- RXDLYALIGNOVERRIDE : out std_logic;\r
- RXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-\r
-\r
-end gtxvirtex6fee80_rx_sync;\r
-\r
-architecture RTL of gtxvirtex6fee80_rx_sync is\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
-\r
---*******************************Register Declarations************************\r
-\r
- signal begin_r : std_logic;\r
- signal phase_align_r : std_logic;\r
- signal ready_r : std_logic;\r
- signal sync_counter_r : unsigned(5 downto 0);\r
- signal sync_done_count_r : unsigned(5 downto 0);\r
- signal align_reset_counter_r : unsigned(4 downto 0);\r
- signal wait_after_sync_r : std_logic;\r
- signal wait_before_setphase_counter_r : unsigned(5 downto 0);\r
- signal wait_before_setphase_r : std_logic;\r
- signal align_reset_r : std_logic;\r
- \r
---*******************************Wire Declarations****************************\r
- \r
- signal count_32_setphase_complete_r : std_logic;\r
- signal count_32_wait_complete_r : std_logic;\r
- signal count_align_reset_complete_r : std_logic;\r
- signal next_phase_align_c : std_logic;\r
- signal next_align_reset_c : std_logic;\r
- signal next_ready_c : std_logic;\r
- signal next_wait_after_sync_c : std_logic;\r
- signal next_wait_before_setphase_c : std_logic;\r
- signal sync_32_times_done_r : std_logic;\r
- \r
- attribute max_fanout:string; \r
- attribute max_fanout of ready_r : signal is "2";\r
-\r
-begin\r
---*******************************Main Body of Code****************************\r
-\r
- --________________________________ State machine __________________________ \r
- -- This state machine manages the phase alingment procedure of the GTX on the\r
- -- receive side. The module is held in reset till the usrclk source is stable\r
- -- and RXRESETDONE is asserted. In the case that a MMCM is used to generate \r
- -- rxusrclk, the mmcm_locked signal is used to indicate a stable usrclk source.\r
- -- Once RXRESETDONE and mmcm_locked are asserted, the state machine goes \r
- -- into the align_reset_r state where RXDLYALIGNRESET is asserted for 20 cycles. \r
- -- After this, it goes into the wait_before_setphase_r state for 32 cycles. \r
- -- After asserting RXENPMAPHASEALIGN and waiting 32 cycles, it enters the \r
- -- phase_align_r state where RXPMASETPHASE is asserted for 32 clock cycles. \r
- -- After the port is deasserted, the state machine goes into a wait state for\r
- -- 32 cycles. This procedure is repeated 32 times.\r
- \r
- -- State registers\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(RESET='1') then\r
- begin_r <= '1' after DLY;\r
- align_reset_r <= '0' after DLY;\r
- wait_before_setphase_r <= '0' after DLY;\r
- phase_align_r <= '0' after DLY;\r
- wait_after_sync_r <= '0' after DLY;\r
- ready_r <= '0' after DLY;\r
- else\r
- begin_r <= '0' after DLY;\r
- align_reset_r <= next_align_reset_c after DLY;\r
- wait_before_setphase_r <= next_wait_before_setphase_c after DLY;\r
- phase_align_r <= next_phase_align_c after DLY;\r
- wait_after_sync_r <= next_wait_after_sync_c after DLY;\r
- ready_r <= next_ready_c after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Next state logic\r
- next_align_reset_c <= begin_r or\r
- (align_reset_r and not count_align_reset_complete_r);\r
- \r
- next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or\r
- (wait_before_setphase_r and not count_32_wait_complete_r); \r
- \r
- next_phase_align_c <= (wait_before_setphase_r and count_32_wait_complete_r) or\r
- (phase_align_r and not count_32_setphase_complete_r) or\r
- (wait_after_sync_r and count_32_wait_complete_r and not sync_32_times_done_r);\r
- \r
- next_wait_after_sync_c <= (phase_align_r and count_32_setphase_complete_r) or\r
- (wait_after_sync_r and not count_32_wait_complete_r);\r
-\r
- next_ready_c <= (wait_after_sync_r and count_32_wait_complete_r and sync_32_times_done_r) or\r
- ready_r;\r
-\r
- --______ Counter for holding RXDLYALIGNRESET for 20 RXUSRCLK2 cycles ______\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (align_reset_r='0') then\r
- align_reset_counter_r <= (others=>'0') after DLY;\r
- else\r
- align_reset_counter_r <= align_reset_counter_r + 1 after DLY;\r
- end if;\r
- end if ;\r
- end process;\r
- \r
- count_align_reset_complete_r <= align_reset_counter_r(4)\r
- and align_reset_counter_r(2);\r
- \r
- --_______Counter for waiting 32 clock cycles before RXPMASETPHASE _________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if ((wait_before_setphase_r='0') and (wait_after_sync_r='0')) then\r
- wait_before_setphase_counter_r <= (others=>'0') after DLY;\r
- else\r
- wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- count_32_wait_complete_r <= wait_before_setphase_counter_r(5);\r
- \r
- --_______________ Counter for holding SYNC for SYNC_CYCLES ________________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (phase_align_r='0') then\r
- sync_counter_r <= (others=>'0') after DLY;\r
- else\r
- sync_counter_r <= sync_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- count_32_setphase_complete_r <= sync_counter_r(5);\r
-\r
- --__________ Counter for counting number of times sync is done ____________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (RESET='1') then\r
- sync_done_count_r <= (others=>'0') after DLY;\r
- elsif((count_32_wait_complete_r ='1') and (phase_align_r = '1')) then\r
- sync_done_count_r <= sync_done_count_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- sync_32_times_done_r <= sync_done_count_r(5);\r
-\r
- --_______________ Assign the phase align ports into the GTX _______________\r
-\r
- RXDLYALIGNRESET <= align_reset_r;\r
- RXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);\r
- RXPMASETPHASE <= phase_align_r;\r
- RXDLYALIGNDISABLE <= '1';\r
- RXDLYALIGNOVERRIDE <= '1';\r
-\r
- --_______________________ Assign the sync_done port _______________________\r
- \r
- SYNC_DONE <= ready_r;\r
- \r
- \r
-end RTL;\r
+++ /dev/null
-------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx\r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : gtxvirtex6fee80_top.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module gtxVirtex6FEE80_top\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***********************************Entity Declaration************************\r
-\r
-entity gtxVirtex6FEE80_top is\r
-generic\r
-(\r
- EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 1;\r
- EXAMPLE_LANE_WITH_START_CHAR : integer := 0; -- specifies lane with unique start frame ch\r
- EXAMPLE_WORDS_IN_BRAM : integer := 512; -- specifies amount of data in BRAM\r
- EXAMPLE_SIM_GTXRESET_SPEEDUP : integer := 1; -- simulation setting for GTX SecureIP model\r
- EXAMPLE_USE_CHIPSCOPE : integer := 1 -- Set to 1 to use Chipscope to drive resets\r
-);\r
-port\r
-(\r
- Q3_CLK0_MGTREFCLK_PAD_N_IN : in std_logic;\r
- Q3_CLK0_MGTREFCLK_PAD_P_IN : in std_logic;\r
- GTXTXRESET_IN : in std_logic;\r
- GTXRXRESET_IN : in std_logic;\r
- TRACK_DATA_OUT : out std_logic;\r
- RXN_IN : in std_logic;\r
- RXP_IN : in std_logic;\r
- TXN_OUT : out std_logic;\r
- TXP_OUT : out std_logic\r
- \r
-);\r
-\r
-\r
-end gtxVirtex6FEE80_top;\r
- \r
-architecture RTL of gtxVirtex6FEE80_top is\r
-\r
---**************************Component Declarations*****************************\r
-\r
-\r
-component gtxVirtex6FEE80 \r
-generic\r
-(\r
- -- Simulation attributes\r
- WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
-);\r
-port\r
-(\r
-\r
- --_________________________________________________________________________\r
- --_________________________________________________________________________\r
- --GTX0 (X0_Y12)\r
-\r
- GTX0_DOUBLE_RESET_CLK_IN : in std_logic;\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GTX0_RXCHARISK_OUT : out std_logic;
- GTX0_RXDISPERR_OUT : out std_logic;
- GTX0_RXNOTINTABLE_OUT : out std_logic;
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GTX0_RXENMCOMMAALIGN_IN : in std_logic;
- GTX0_RXENPCOMMAALIGN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
- GTX0_RXRECCLK_OUT : out std_logic;
- GTX0_RXRESET_IN : in std_logic;
- GTX0_RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GTX0_RXCDRRESET_IN : in std_logic;
- GTX0_RXN_IN : in std_logic;
- GTX0_RXP_IN : in std_logic;
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
- GTX0_RXDLYALIGNMONENB_IN : in std_logic;
- GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
- GTX0_RXDLYALIGNRESET_IN : in std_logic;
- GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
- GTX0_RXPMASETPHASE_IN : in std_logic;
- GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTX0_GTXRXRESET_IN : in std_logic;
- GTX0_MGTREFCLKRX_IN : in std_logic;
- GTX0_PLLRXRESET_IN : in std_logic;
- GTX0_RXPLLLKDET_OUT : out std_logic;
- GTX0_RXRESETDONE_OUT : out std_logic;
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- GTX0_PHYSTATUS_OUT : out std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GTX0_TXCHARISK_IN : in std_logic;
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
- GTX0_TXOUTCLK_OUT : out std_logic;
- GTX0_TXRESET_IN : in std_logic;
- GTX0_TXUSRCLK2_IN : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTX0_TXN_OUT : out std_logic;
- GTX0_TXP_OUT : out std_logic;
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
- GTX0_TXDLYALIGNMONENB_IN : in std_logic;
- GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- GTX0_TXDLYALIGNRESET_IN : in std_logic;
- GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
- GTX0_TXPMASETPHASE_IN : in std_logic;
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTX0_GTXTXRESET_IN : in std_logic;
- GTX0_TXRESETDONE_OUT : out std_logic
-\r
-\r
-);\r
-end component;\r
-\r
-component MGT_USRCLK_SOURCE \r
-generic\r
-(\r
- FREQUENCY_MODE : string := "LOW"; \r
- PERFORMANCE_MODE : string := "MAX_SPEED" \r
-);\r
-port\r
-(\r
- DIV1_OUT : out std_logic;\r
- DIV2_OUT : out std_logic;\r
- DCM_LOCKED_OUT : out std_logic;\r
- CLK_IN : in std_logic;\r
- DCM_RESET_IN : in std_logic\r
-\r
-);\r
-end component;\r
-\r
-component FRAME_GEN \r
-generic\r
-(\r
- WORDS_IN_BRAM : integer := 256;\r
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-); \r
-port\r
-(\r
- -- User Interface\r
- TX_DATA : out std_logic_vector(39 downto 0);\r
- TX_CHARISK : out std_logic_vector(3 downto 0); \r
-\r
- -- System Interface\r
- USER_CLK : in std_logic;\r
- SYSTEM_RESET : in std_logic\r
-); \r
-end component;\r
-\r
-component FRAME_CHECK \r
-generic\r
-(\r
- RX_DATA_WIDTH : integer := 16;\r
- RXCTRL_WIDTH : integer := 2;\r
- USE_COMMA : integer := 1;\r
- NONE_MSB_FIRST_DEC : integer := 0;\r
- COMMA_DOUBLE_DEC : integer := 0;\r
- CHANBOND_SEQ_LEN : integer := 1;\r
- WORDS_IN_BRAM : integer := 256;\r
- CONFIG_INDEPENDENT_LANES : integer := 0;\r
- START_OF_PACKET_CHAR : std_logic_vector(15 downto 0) ;\r
- COMMA_DOUBLE_CHAR : std_logic_vector(15 downto 0) := x"f628";\r
- MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
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-);\r
-port\r
-(\r
- -- User Interface\r
- RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- \r
- RXCTRL_IN : in std_logic_vector((RXCTRL_WIDTH-1) downto 0); \r
- RX_ENMCOMMA_ALIGN : out std_logic;\r
- RX_ENPCOMMA_ALIGN : out std_logic;\r
- \r
- RX_ENCHAN_SYNC : out std_logic; \r
- RX_CHANBOND_SEQ : in std_logic; \r
-\r
- -- Control Interface\r
- INC_IN : in std_logic; \r
- INC_OUT : out std_logic; \r
- PATTERN_MATCH_N : out std_logic;\r
- RESET_ON_ERROR : in std_logic; \r
- \r
- -- Error Monitoring\r
- ERROR_COUNT : out std_logic_vector(7 downto 0);\r
- \r
- -- Track Data\r
- TRACK_DATA : out std_logic;\r
- \r
- -- System Interface\r
- USER_CLK : in std_logic;\r
- SYSTEM_RESET : in std_logic\r
- \r
-);\r
-end component;\r
-\r
-component MGT_USRCLK_SOURCE_MMCM\r
-generic\r
-(\r
- MULT : real := 2.0;\r
- DIVIDE : integer := 2; \r
- CLK_PERIOD : real := 6.4; \r
- OUT0_DIVIDE : real := 2.0;\r
- OUT1_DIVIDE : integer := 2;\r
- OUT2_DIVIDE : integer := 2;\r
- OUT3_DIVIDE : integer := 2\r
-);\r
-port\r
-(\r
- CLKFBOUT : out std_logic; \r
- CLK0_OUT : out std_logic;\r
- CLK1_OUT : out std_logic;\r
- CLK2_OUT : out std_logic;\r
- CLK3_OUT : out std_logic;\r
- CLK_IN : in std_logic;\r
- MMCM_LOCKED_OUT : out std_logic;\r
- MMCM_RESET_IN : in std_logic\r
-);\r
-end component;\r
-\r
-component gtxVirtex6FEE80_tx_sync\r
-generic\r
-(\r
- -- Simulation attributes\r
- SIM_TXPMASETPHASE_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
-);\r
-port\r
-(\r
- TXENPMAPHASEALIGN : out std_logic;\r
- TXPMASETPHASE : out std_logic;\r
- TXDLYALIGNDISABLE : out std_logic;\r
- TXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-end component;\r
-\r
-component gtxVirtex6FEE80_rx_sync\r
-port\r
-(\r
- RXENPMAPHASEALIGN : out std_logic;\r
- RXPMASETPHASE : out std_logic;\r
- RXDLYALIGNDISABLE : out std_logic;\r
- RXDLYALIGNOVERRIDE : out std_logic;\r
- RXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-end component;\r
-\r
-\r
--- Chipscope modules\r
-attribute syn_black_box : boolean;\r
-attribute syn_noprune : boolean;\r
-\r
-\r
-component data_vio\r
-port\r
-(\r
- control : inout std_logic_vector(35 downto 0);\r
- clk : in std_logic;\r
- async_in : in std_logic_vector(31 downto 0);\r
- async_out : out std_logic_vector(31 downto 0);\r
- sync_in : in std_logic_vector(31 downto 0);\r
- sync_out : out std_logic_vector(31 downto 0)\r
-);\r
-end component;\r
-attribute syn_black_box of data_vio : component is TRUE;\r
-attribute syn_noprune of data_vio : component is TRUE;\r
-\r
-\r
-component icon\r
-port\r
-(\r
- control0 : inout std_logic_vector(35 downto 0);\r
- control1 : inout std_logic_vector(35 downto 0);\r
- control2 : inout std_logic_vector(35 downto 0);\r
- control3 : inout std_logic_vector(35 downto 0)\r
-);\r
-end component;\r
-attribute syn_black_box of icon : component is TRUE;\r
-attribute syn_noprune of icon : component is TRUE;\r
-\r
-\r
-component ila\r
-port\r
-(\r
- control : inout std_logic_vector(35 downto 0);\r
- clk : in std_logic;\r
- trig0 : in std_logic_vector(84 downto 0)\r
-);\r
-end component;\r
-\r
-\r
-attribute syn_black_box of ila : component is TRUE;\r
-attribute syn_noprune of ila : component is TRUE;\r
-\r
-\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
- \r
- attribute max_fanout : string; \r
-\r
---************************** Register Declarations ****************************\r
-\r
- signal gtx0_txresetdone_r : std_logic;\r
- signal gtx0_txresetdone_r2 : std_logic;\r
- signal gtx0_rxresetdone_i_r : std_logic;\r
- signal gtx0_rxresetdone_r : std_logic;\r
- signal gtx0_rxresetdone_r2 : std_logic;\r
- signal gtx0_rxresetdone_r3 : std_logic;\r
- attribute max_fanout of gtx0_rxresetdone_i_r : signal is "1";\r
- signal gtx0_rxdata_r : std_logic_vector(7 downto 0);\r
- signal gtx0_rxcharisk_r : std_logic_vector(0 downto 0); \r
-\r
-\r
---**************************** Wire Declarations ******************************\r
- -------------------------- MGT Wrapper Wires ------------------------------\r
- --________________________________________________________________________\r
- --________________________________________________________________________\r
- --GTX0 (X0Y12)\r
-\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- signal gtx0_rxcharisk_i : std_logic;
- signal gtx0_rxdisperr_i : std_logic;
- signal gtx0_rxnotintable_i : std_logic;
- --------------- Receive Ports - Comma Detection and Alignment --------------
- signal gtx0_rxenmcommaalign_i : std_logic;
- signal gtx0_rxenpcommaalign_i : std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- signal gtx0_rxdata_i : std_logic_vector(7 downto 0);
- signal gtx0_rxrecclk_i : std_logic;
- signal gtx0_rxreset_i : std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- signal gtx0_rxcdrreset_i : std_logic;
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- signal gtx0_rxdlyaligndisable_i : std_logic;
- signal gtx0_rxdlyalignmonenb_i : std_logic;
- signal gtx0_rxdlyalignmonitor_i : std_logic_vector(7 downto 0);
- signal gtx0_rxdlyalignoverride_i : std_logic;
- signal gtx0_rxdlyalignreset_i : std_logic;
- signal gtx0_rxenpmaphasealign_i : std_logic;
- signal gtx0_rxpmasetphase_i : std_logic;
- signal gtx0_rxstatus_i : std_logic_vector(2 downto 0);
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- signal gtx0_rxlossofsync_i : std_logic_vector(1 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- signal gtx0_gtxrxreset_i : std_logic;
- signal gtx0_pllrxreset_i : std_logic;
- signal gtx0_rxplllkdet_i : std_logic;
- signal gtx0_rxresetdone_i : std_logic;
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- signal gtx0_phystatus_i : std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- signal gtx0_txcharisk_i : std_logic;
- ------------------ Transmit Ports - TX Data Path interface -----------------
- signal gtx0_txdata_i : std_logic_vector(7 downto 0);
- signal gtx0_txoutclk_i : std_logic;
- signal gtx0_txreset_i : std_logic;
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- signal gtx0_txdlyaligndisable_i : std_logic;
- signal gtx0_txdlyalignmonenb_i : std_logic;
- signal gtx0_txdlyalignmonitor_i : std_logic_vector(7 downto 0);
- signal gtx0_txdlyalignreset_i : std_logic;
- signal gtx0_txenpmaphasealign_i : std_logic;
- signal gtx0_txpmasetphase_i : std_logic;
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- signal gtx0_gtxtxreset_i : std_logic;
- signal gtx0_txresetdone_i : std_logic;
-\r
-\r
-\r
-\r
- signal gtx0_tx_system_reset_c : std_logic;\r
- signal gtx0_rx_system_reset_c : std_logic;\r
- signal gtx0_double_reset_clk_i : std_logic;\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);\r
- signal tied_to_vcc_i : std_logic;\r
- signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);\r
- signal drp_clk_in_i : std_logic;\r
- \r
-\r
- ----------------------------- User Clocks ---------------------------------\r
-\r
- signal gtx0_txusrclk2_i : std_logic;
- signal gtx0_rxusrclk2_i : std_logic;
- signal txoutclk_mmcm0_locked_i : std_logic;
- signal txoutclk_mmcm0_reset_i : std_logic;
- signal gtx0_txoutclk_to_mmcm_i : std_logic;
-\r
-\r
- ----------------------------- Reference Clocks ----------------------------\r
- \r
- signal q3_clk0_refclk_i : std_logic;\r
- signal q3_clk0_refclk_i_bufg : std_logic;\r
-\r
- ----------------------- Frame check/gen Module Signals --------------------\r
- \r
- signal gtx0_matchn_i : std_logic;\r
- \r
- signal gtx0_txcharisk_float_i : std_logic_vector(2 downto 0);\r
- \r
- signal gtx0_txdata_float_i : std_logic_vector(31 downto 0);\r
- \r
- signal gtx0_track_data_i : std_logic;\r
- signal gtx0_block_sync_i : std_logic;\r
- signal gtx0_error_count_i : std_logic_vector(7 downto 0);\r
- signal gtx0_frame_check_reset_i : std_logic;\r
- signal gtx0_inc_in_i : std_logic;\r
- signal gtx0_inc_out_i : std_logic;\r
- signal gtx0_unscrambled_data_i : std_logic_vector(7 downto 0);\r
-\r
- signal reset_on_data_error_i : std_logic;\r
- signal track_data_out_i : std_logic;\r
- \r
- \r
- ------------------------- Sync Module Signals -----------------------------\r
-\r
- signal gtx0_rx_sync_done_i : std_logic;\r
- signal gtx0_reset_rxsync_c : std_logic;\r
-\r
-\r
- signal gtx0_tx_sync_done_i : std_logic;\r
- signal gtx0_reset_txsync_c : std_logic;\r
-\r
- ----------------------- Chipscope Signals ---------------------------------\r
-\r
- signal tx_data_vio_control_i : std_logic_vector(35 downto 0);
- signal rx_data_vio_control_i : std_logic_vector(35 downto 0);
- signal shared_vio_control_i : std_logic_vector(35 downto 0);
- signal ila_control_i : std_logic_vector(35 downto 0);
- signal tx_data_vio_async_in_i : std_logic_vector(31 downto 0);
- signal tx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
- signal tx_data_vio_async_out_i : std_logic_vector(31 downto 0);
- signal tx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
- signal rx_data_vio_async_in_i : std_logic_vector(31 downto 0);
- signal rx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
- signal rx_data_vio_async_out_i : std_logic_vector(31 downto 0);
- signal rx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
- signal shared_vio_in_i : std_logic_vector(31 downto 0);
- signal shared_vio_out_i : std_logic_vector(31 downto 0);
- signal ila_in_i : std_logic_vector(84 downto 0);
-
- signal gtx0_tx_data_vio_async_in_i : std_logic_vector(31 downto 0);
- signal gtx0_tx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
- signal gtx0_tx_data_vio_async_out_i : std_logic_vector(31 downto 0);
- signal gtx0_tx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
- signal gtx0_rx_data_vio_async_in_i : std_logic_vector(31 downto 0);
- signal gtx0_rx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
- signal gtx0_rx_data_vio_async_out_i : std_logic_vector(31 downto 0);
- signal gtx0_rx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
- signal gtx0_ila_in_i : std_logic_vector(84 downto 0);
-
-\r
- signal gtxtxreset_i : std_logic;\r
- signal gtxrxreset_i : std_logic;\r
-\r
- signal user_tx_reset_i : std_logic;\r
- signal user_rx_reset_i : std_logic;\r
- signal tx_vio_clk_i : std_logic;\r
- signal tx_vio_clk_mux_out_i : std_logic;\r
- signal rx_vio_ila_clk_i : std_logic;\r
- signal rx_vio_ila_clk_mux_out_i : std_logic;\r
-\r
- \r
---**************************** Main Body of Code *******************************\r
-begin\r
-\r
- -- Static signal Assigments\r
- tied_to_ground_i <= '0';\r
- tied_to_ground_vec_i <= x"0000000000000000";\r
- tied_to_vcc_i <= '1';\r
- tied_to_vcc_vec_i <= x"ff";\r
-\r
-\r
-\r
- \r
- \r
-\r
- -----------------------Dedicated GTX Reference Clock Inputs ---------------\r
- -- The dedicated reference clock inputs you selected in the GUI are implemented using\r
- -- IBUFDS_GTXE1 instances.\r
- --\r
- -- In the UCF file for this example design, you will see that each of\r
- -- these IBUFDS_GTXE1 instances has been LOCed to a particular set of pins. By LOCing to these\r
- -- locations, we tell the tools to use the dedicated input buffers to the GTX reference\r
- -- clock network, rather than general purpose IOs. To select other pins, consult the \r
- -- Implementation chapter of UG___, or rerun the wizard.\r
- --\r
- -- This network is the highest performace (lowest jitter) option for providing clocks\r
- -- to the GTX transceivers.\r
- \r
- q3_clk0_refclk_ibufds_i : IBUFDS_GTXE1\r
- port map\r
- (\r
- O => q3_clk0_refclk_i,\r
- ODIV2 => open,\r
- CEB => tied_to_ground_i,\r
- I => Q3_CLK0_MGTREFCLK_PAD_P_IN,\r
- IB => Q3_CLK0_MGTREFCLK_PAD_N_IN\r
- );\r
-\r
- \r
-\r
- q3_clk0_refclk_bufg_i : BUFG\r
- port map\r
- (\r
- I => q3_clk0_refclk_i,\r
- O => q3_clk0_refclk_i_bufg\r
- );\r
-\r
- -----------------------Clock Input to Double Reset Module------------------\r
- gtx0_double_reset_clk_i <= q3_clk0_refclk_i_bufg;\r
-\r
-\r
- ----------------------------------- User Clocks ---------------------------\r
- \r
- -- The clock resources in this section were added based on userclk source selections on\r
- -- the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks:\r
- -- * The userclk and userclk2 for each GTX datapath (TX and RX) must be phase aligned to \r
- -- avoid data errors in the fabric interface whenever the datapath is wider than 10 bits\r
- -- * To minimize clock resources, you can share clocks between GTXs. GTXs using the same frequency\r
- -- or multiples of the same frequency can be accomadated using MMCMs. Use caution when\r
- -- using RXRECCLK as a clock source, however - these clocks can typically only be shared if all\r
- -- the channels using the clock are receiving data from TX channels that share a reference clock \r
- -- source with each other.\r
-\r
- txoutclk_mmcm0_reset_i <= not gtx0_rxplllkdet_i;
- txoutclk_mmcm0_i : MGT_USRCLK_SOURCE_MMCM
- generic map
- (
- MULT => 15.0,
- DIVIDE => 1,
- CLK_PERIOD => 12.5,
- OUT0_DIVIDE => 6.0,
- OUT1_DIVIDE => 1,
- OUT2_DIVIDE => 1,
- OUT3_DIVIDE => 1
- )
- port map
- (
- CLKFBOUT => open,
- CLK0_OUT => gtx0_txusrclk2_i,
- CLK1_OUT => open,
- CLK2_OUT => open,
- CLK3_OUT => open,
- CLK_IN => gtx0_txoutclk_i,
- MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
- MMCM_RESET_IN => txoutclk_mmcm0_reset_i
- );
-
-
- rxrecclk_bufr1_i : BUFR
- generic map
- (
- BUFR_DIVIDE => "BYPASS"
- )
- port map
- (
- CE => '1',
- CLR => '0',
- I => gtx0_rxrecclk_i,
- O => gtx0_rxusrclk2_i
- );
-
-
-\r
-\r
- ----------------------------- The GTX Wrapper -----------------------------\r
- \r
- -- Use the instantiation template in the example directory to add the GTX wrapper to your design.\r
- -- In this example, the wrapper is wired up for basic operation with a frame generator and frame \r
- -- checker. The GTXs will reset, then attempt to align and transmit data. If channel bonding is \r
- -- enabled, bonding should occur after alignment.\r
-\r
-\r
- gtxVirtex6FEE80_i : gtxVirtex6FEE80\r
- generic map\r
- (\r
- WRAPPER_SIM_GTXRESET_SPEEDUP => EXAMPLE_SIM_GTXRESET_SPEEDUP\r
- )\r
- port map\r
- (\r
- \r
- \r
- \r
- \r
-\r
- --_____________________________________________________________________\r
- --_____________________________________________________________________\r
- --GTX0 (X0Y12)\r
- GTX0_DOUBLE_RESET_CLK_IN => gtx0_double_reset_clk_i,\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GTX0_RXCHARISK_OUT => gtx0_rxcharisk_i,
- GTX0_RXDISPERR_OUT => gtx0_rxdisperr_i,
- GTX0_RXNOTINTABLE_OUT => gtx0_rxnotintable_i,
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GTX0_RXENMCOMMAALIGN_IN => gtx0_rxenmcommaalign_i,
- GTX0_RXENPCOMMAALIGN_IN => gtx0_rxenpcommaalign_i,
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTX0_RXDATA_OUT => gtx0_rxdata_i,
- GTX0_RXRECCLK_OUT => gtx0_rxrecclk_i,
- GTX0_RXRESET_IN => gtx0_rxreset_i,
- GTX0_RXUSRCLK2_IN => gtx0_rxusrclk2_i,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GTX0_RXCDRRESET_IN => gtx0_rxcdrreset_i,
- GTX0_RXN_IN => RXN_IN,
- GTX0_RXP_IN => RXP_IN,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GTX0_RXDLYALIGNDISABLE_IN => gtx0_rxdlyaligndisable_i,
- GTX0_RXDLYALIGNMONENB_IN => gtx0_rxdlyalignmonenb_i,
- GTX0_RXDLYALIGNMONITOR_OUT => gtx0_rxdlyalignmonitor_i,
- GTX0_RXDLYALIGNOVERRIDE_IN => gtx0_rxdlyalignoverride_i,
- GTX0_RXDLYALIGNRESET_IN => gtx0_rxdlyalignreset_i,
- GTX0_RXENPMAPHASEALIGN_IN => gtx0_rxenpmaphasealign_i,
- GTX0_RXPMASETPHASE_IN => gtx0_rxpmasetphase_i,
- GTX0_RXSTATUS_OUT => gtx0_rxstatus_i,
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- GTX0_RXLOSSOFSYNC_OUT => gtx0_rxlossofsync_i,
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTX0_GTXRXRESET_IN => gtx0_gtxrxreset_i,
- GTX0_MGTREFCLKRX_IN => q3_clk0_refclk_i,
- GTX0_PLLRXRESET_IN => gtx0_pllrxreset_i,
- GTX0_RXPLLLKDET_OUT => gtx0_rxplllkdet_i,
- GTX0_RXRESETDONE_OUT => gtx0_rxresetdone_i,
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- GTX0_PHYSTATUS_OUT => gtx0_phystatus_i,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GTX0_TXCHARISK_IN => gtx0_txcharisk_i,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTX0_TXDATA_IN => gtx0_txdata_i,
- GTX0_TXOUTCLK_OUT => gtx0_txoutclk_i,
- GTX0_TXRESET_IN => gtx0_txreset_i,
- GTX0_TXUSRCLK2_IN => gtx0_txusrclk2_i,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTX0_TXN_OUT => TXN_OUT,
- GTX0_TXP_OUT => TXP_OUT,
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- GTX0_TXDLYALIGNDISABLE_IN => gtx0_txdlyaligndisable_i,
- GTX0_TXDLYALIGNMONENB_IN => gtx0_txdlyalignmonenb_i,
- GTX0_TXDLYALIGNMONITOR_OUT => gtx0_txdlyalignmonitor_i,
- GTX0_TXDLYALIGNRESET_IN => gtx0_txdlyalignreset_i,
- GTX0_TXENPMAPHASEALIGN_IN => gtx0_txenpmaphasealign_i,
- GTX0_TXPMASETPHASE_IN => gtx0_txpmasetphase_i,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTX0_GTXTXRESET_IN => gtx0_gtxtxreset_i,
- GTX0_TXRESETDONE_OUT => gtx0_txresetdone_i
-\r
-\r
- );\r
-\r
- -- Hold the TX in reset till the TX user clocks are stable\r
- gtx0_txreset_i <= not txoutclk_mmcm0_locked_i;\r
-\r
- -- Hold the RX in reset till the RX user clocks are stable\r
- \r
- gtx0_rxreset_i <= not gtx0_rxplllkdet_i;\r
-\r
-\r
-\r
- ------------------------------ TXSYNC module ------------------------------\r
- -- The TXSYNC module performs phase synchronization for all the active TX datapaths. It\r
- -- waits for the user clocks to be stable, then drives the phase align signals on each\r
- -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
- \r
- -- Include the TX_SYNC module in your own design to perform phase synchronization if\r
- -- your protocol bypasses the TX Buffers\r
-\r
- \r
- \r
- gtx0_reset_txsync_c <= not gtx0_txresetdone_r2; \r
-\r
- -- SIM_TXPMASETPHASE_SPEEDUP is a simulation only attribute and MUST be set to 0 \r
- -- during implementation \r
- gtx0_txsync_i : gtxVirtex6FEE80_tx_sync\r
- generic map\r
- (\r
- SIM_TXPMASETPHASE_SPEEDUP => EXAMPLE_SIM_GTXRESET_SPEEDUP\r
- )\r
- port map\r
- (\r
- TXENPMAPHASEALIGN => gtx0_txenpmaphasealign_i,\r
- TXPMASETPHASE => gtx0_txpmasetphase_i,\r
- TXDLYALIGNDISABLE => gtx0_txdlyaligndisable_i,\r
- TXDLYALIGNRESET => gtx0_txdlyalignreset_i,\r
- SYNC_DONE => gtx0_tx_sync_done_i,\r
- USER_CLK => gtx0_txusrclk2_i,\r
- RESET => gtx0_reset_txsync_c\r
- );\r
-\r
- ---------------------------- RXSYNC modules -------------------------------\r
- -- The RXSYNC module performs phase synchronization for all the active RX datapaths. It\r
- -- waits for the user clocks to be stable, then drives the RX phase align signals on each\r
- -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
- \r
- -- Include one RX_SYNC module per Buffer bypassed RX datapath in your own design. RX_SYNC modules\r
- -- can also be shared, but when sharing, make sure to hold the module in reset until all lanes have \r
- -- a stable clock\r
- \r
- \r
- gtx0_rxsync_i : gtxVirtex6FEE80_rx_sync\r
- port map\r
- (\r
- RXENPMAPHASEALIGN => gtx0_rxenpmaphasealign_i,\r
- RXPMASETPHASE => gtx0_rxpmasetphase_i,\r
- RXDLYALIGNDISABLE => gtx0_rxdlyaligndisable_i,\r
- RXDLYALIGNOVERRIDE => gtx0_rxdlyalignoverride_i,\r
- RXDLYALIGNRESET => gtx0_rxdlyalignreset_i,\r
- SYNC_DONE => gtx0_rx_sync_done_i,\r
- USER_CLK => gtx0_rxusrclk2_i,\r
- RESET => gtx0_reset_rxsync_c\r
- );\r
- \r
- gtx0_reset_rxsync_c <= '1' when (gtx0_rxresetdone_r3 = '0') else '0';\r
- \r
-\r
-\r
- -------------------------- User Module Resets -----------------------------\r
- -- All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules\r
- -- are held in reset till the RESETDONE goes high. \r
- -- The RESETDONE is registered a couple of times on USRCLK2 and connected \r
- -- to the reset of the modules\r
- \r
- process( gtx0_rxusrclk2_i)\r
- begin\r
- if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
- gtx0_rxresetdone_i_r <= gtx0_rxresetdone_i after DLY;\r
- end if; \r
- end process; \r
-\r
- process( gtx0_rxusrclk2_i,gtx0_rxresetdone_i_r)\r
- begin\r
- if(gtx0_rxresetdone_i_r = '0') then\r
- gtx0_rxresetdone_r <= '0' after DLY;\r
- gtx0_rxresetdone_r2 <= '0' after DLY;\r
- elsif(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
- gtx0_rxresetdone_r <= gtx0_rxresetdone_i_r after DLY;\r
- gtx0_rxresetdone_r2 <= gtx0_rxresetdone_r after DLY;\r
- end if;\r
- end process;\r
-\r
- process( gtx0_rxusrclk2_i)\r
- begin\r
- if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
- gtx0_rxresetdone_r3 <= gtx0_rxresetdone_r2 after DLY;\r
- end if; \r
- end process; \r
-\r
- process( gtx0_txusrclk2_i,gtx0_txresetdone_i)\r
- begin\r
- if(gtx0_txresetdone_i = '0') then\r
- gtx0_txresetdone_r <= '0' after DLY;\r
- gtx0_txresetdone_r2 <= '0' after DLY;\r
- elsif(gtx0_txusrclk2_i'event and gtx0_txusrclk2_i = '1') then\r
- gtx0_txresetdone_r <= gtx0_txresetdone_i after DLY;\r
- gtx0_txresetdone_r2 <= gtx0_txresetdone_r after DLY;\r
- end if;\r
- end process;\r
-\r
-\r
- ------------------------------ Frame Generators ---------------------------\r
- -- The example design uses Block RAM based frame generators to provide test\r
- -- data to the GTXs for transmission. By default the frame generators are \r
- -- loaded with an incrementing data sequence that includes commas/alignment\r
- -- characters for alignment. If your protocol uses channel bonding, the \r
- -- frame generator will also be preloaded with a channel bonding sequence.\r
- \r
- -- You can modify the data transmitted by changing the INIT values of the frame\r
- -- generator in this file. Pay careful attention to bit order and the spacing\r
- -- of your control and alignment characters.\r
-\r
- gtx0_frame_gen : FRAME_GEN\r
- generic map\r
- (\r
- WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM,\r
- MEM_00 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_01 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_02 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_03 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_04 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_05 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_06 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_07 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_08 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_09 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_0A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_0B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_0C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_0D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_0E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_0F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_10 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_11 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_12 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_13 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_14 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_15 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_16 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_17 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_18 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_19 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_1A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_1B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_1C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_1D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_1E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_1F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_20 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_21 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_22 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_23 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_24 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_25 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_26 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_27 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_28 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_29 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_2A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_2B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_2C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_2D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_2E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_2F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_30 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_31 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_32 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_33 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_34 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_35 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_36 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_37 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_38 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_39 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_3A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_3B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_3C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_3D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_3E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_3F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEMP_00 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_02 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_04 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_06 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_07 => x"0000000000000000000000000000000000000000000000000000000000000000"\r
- )\r
- port map\r
- (\r
- -- User Interface\r
- TX_DATA(39 downto 8) => gtx0_txdata_float_i,\r
- TX_DATA(7 downto 0) => gtx0_txdata_i,\r
- \r
- TX_CHARISK(3 downto 1) => gtx0_txcharisk_float_i,\r
- TX_CHARISK(0) => gtx0_txcharisk_i,\r
- -- System Interface\r
- USER_CLK => gtx0_txusrclk2_i,\r
- SYSTEM_RESET => gtx0_tx_system_reset_c\r
- );\r
- \r
-\r
-\r
- ---------------------------------- Frame Checkers -------------------------\r
- -- The example design uses Block RAM based frame checkers to verify incoming \r
- -- data. By default the frame generators are loaded with a data sequence that \r
- -- matches the outgoing sequence of the frame generators for the TX ports.\r
- \r
- -- You can modify the expected data sequence by changing the INIT values of the frame\r
- -- checkers in this file. Pay careful attention to bit order and the spacing\r
- -- of your control and alignment characters.\r
- \r
- -- When the frame checker receives data, it attempts to synchronise to the \r
- -- incoming pattern by looking for the first sequence in the pattern. Once it \r
- -- finds the first sequence, it increments through the sequence, and indicates an \r
- -- error whenever the next value received does not match the expected value.\r
-\r
- gtx0_frame_check_reset_i <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else gtx0_matchn_i;\r
-\r
- -- gtx0_frame_check0 is always connected to the lane with the start of char\r
- -- and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off\r
- gtx0_inc_in_i <= '0';\r
-\r
- process(gtx0_rxusrclk2_i)\r
- begin \r
- if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then\r
- gtx0_rxdata_r <= gtx0_rxdata_i after DLY;\r
- end if;\r
- end process;\r
-\r
- process(gtx0_rxusrclk2_i)\r
- begin \r
- if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then\r
- gtx0_rxcharisk_r(0) <= gtx0_rxcharisk_i after DLY;\r
- end if;\r
- end process;\r
- \r
-\r
- \r
- \r
- gtx0_frame_check : FRAME_CHECK\r
- generic map\r
- (\r
- RX_DATA_WIDTH => 8,\r
- RXCTRL_WIDTH => 1,\r
- USE_COMMA => 1,\r
- WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM,\r
- CONFIG_INDEPENDENT_LANES => 1,\r
- START_OF_PACKET_CHAR => x"02bc",\r
- MEM_00 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_01 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_02 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_03 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_04 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_05 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_06 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_07 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_08 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_09 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_0A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_0B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_0C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_0D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_0E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_0F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_10 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_11 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_12 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_13 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_14 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_15 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_16 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_17 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_18 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_19 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_1A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_1B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_1C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_1D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_1E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_1F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_20 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_21 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_22 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_23 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_24 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_25 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_26 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_27 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_28 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_29 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_2A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_2B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_2C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_2D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_2E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_2F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_30 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_31 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_32 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_33 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_34 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_35 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_36 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_37 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_38 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_39 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_3A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_3B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_3C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_3D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_3E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_3F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEMP_00 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_02 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_04 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_06 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_07 => x"0000000000000000000000000000000000000000000000000000000000000000"\r
- )\r
- port map\r
- (\r
- -- MGT Interface\r
- RX_DATA => gtx0_rxdata_r,\r
- RXCTRL_IN => gtx0_rxcharisk_r,\r
- RX_ENMCOMMA_ALIGN => gtx0_rxenmcommaalign_i,\r
- RX_ENPCOMMA_ALIGN => gtx0_rxenpcommaalign_i,\r
- RX_ENCHAN_SYNC => open,\r
- RX_CHANBOND_SEQ => tied_to_ground_i,\r
- -- Control Interface\r
- INC_IN => gtx0_inc_in_i,\r
- INC_OUT => gtx0_inc_out_i,\r
- PATTERN_MATCH_N => gtx0_matchn_i,\r
- RESET_ON_ERROR => gtx0_frame_check_reset_i,\r
- -- System Interface\r
- USER_CLK => gtx0_rxusrclk2_i,\r
- SYSTEM_RESET => gtx0_rx_system_reset_c,\r
- ERROR_COUNT => gtx0_error_count_i,\r
- TRACK_DATA => gtx0_track_data_i\r
- );\r
- \r
-\r
-\r
- TRACK_DATA_OUT <= track_data_out_i;\r
-\r
- track_data_out_i <= \r
- gtx0_track_data_i ;\r
-\r
-\r
-\r
- ----------------------------- Chipscope Connections -----------------------\r
- -- When the example design is run in hardware, it uses chipscope to allow the\r
- -- example design and GTX wrapper to be controlled and monitored. The \r
- -- EXAMPLE_USE_CHIPSCOPE parameter allows chipscope to be removed for simulation.\r
- \r
-chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate\r
- \r
- \r
- -- Shared VIO for all transievers \r
- shared_vio_i : data_vio\r
- port map\r
- (\r
- control => shared_vio_control_i,\r
- clk => tied_to_ground_i,\r
- async_in => shared_vio_in_i,\r
- async_out => shared_vio_out_i,\r
- sync_in => tied_to_ground_vec_i(31 downto 0),\r
- sync_out => open\r
- );\r
- \r
- -- ICON for all VIOs \r
- i_icon : icon\r
- port map\r
- (\r
- control0 => shared_vio_control_i,\r
- control1 => tx_data_vio_control_i,\r
- control2 => rx_data_vio_control_i,\r
- control3 => ila_control_i\r
- );\r
-\r
- \r
- -- TX VIO \r
- tx_data_vio_i : data_vio\r
- port map\r
- (\r
- control => tx_data_vio_control_i,\r
- clk => gtx0_txusrclk2_i,\r
- async_in => tx_data_vio_async_in_i,\r
- async_out => tx_data_vio_async_out_i,\r
- sync_in => tx_data_vio_sync_in_i,\r
- sync_out => tx_data_vio_sync_out_i\r
- );\r
- \r
- -- RX VIO \r
- rx_data_vio_i : data_vio\r
- port map\r
- (\r
- control => rx_data_vio_control_i,\r
- clk => gtx0_rxusrclk2_i,\r
- async_in => rx_data_vio_async_in_i,\r
- async_out => rx_data_vio_async_out_i,\r
- sync_in => rx_data_vio_sync_in_i,\r
- sync_out => rx_data_vio_sync_out_i\r
- );\r
- \r
- -- RX ILA\r
- ila_i : ila\r
- port map\r
- (\r
- control => ila_control_i,\r
- clk => gtx0_rxusrclk2_i,\r
- trig0 => ila_in_i\r
- );\r
-\r
-\r
-\r
- -- assign resets for frame_gen modules\r
- gtx0_tx_system_reset_c <= not gtx0_tx_sync_done_i or user_tx_reset_i;\r
- -- assign resets for frame_check modules\r
- gtx0_rx_system_reset_c <= not gtx0_rx_sync_done_i or user_rx_reset_i;\r
-\r
- gtx0_gtxtxreset_i <= gtxtxreset_i or gtxrxreset_i;\r
- gtx0_gtxrxreset_i <= gtxtxreset_i or gtxrxreset_i;\r
-
- -- Shared VIO Outputs
- gtxtxreset_i <= shared_vio_out_i(31);
- gtxrxreset_i <= shared_vio_out_i(30);
- user_tx_reset_i <= shared_vio_out_i(29);
- user_rx_reset_i <= shared_vio_out_i(28);
-
- -- Shared VIO Inputs
- shared_vio_in_i(31 downto 0) <= "00000000000000000000000000000000";
-
- -- Chipscope connections on GTX 0
- gtx0_tx_data_vio_async_in_i(31) <= '0';
- gtx0_tx_data_vio_async_in_i(30) <= gtx0_txresetdone_i;
- gtx0_tx_data_vio_async_in_i(29 downto 22) <= gtx0_txdlyalignmonitor_i;
- gtx0_tx_data_vio_async_in_i(21 downto 0) <= "0000000000000000000000";
- gtx0_tx_data_vio_sync_in_i(31 downto 0) <= "00000000000000000000000000000000";
- gtx0_txdlyalignmonenb_i <= tx_data_vio_async_out_i(30);
- gtx0_rx_data_vio_async_in_i(31) <= gtx0_rxplllkdet_i;
- gtx0_rx_data_vio_async_in_i(30) <= gtx0_rxresetdone_i;
- gtx0_rx_data_vio_async_in_i(29 downto 22) <= gtx0_rxdlyalignmonitor_i;
- gtx0_rx_data_vio_async_in_i(21 downto 0) <= "0000000000000000000000";
- gtx0_rx_data_vio_sync_in_i(31 downto 0) <= "00000000000000000000000000000000";
- gtx0_pllrxreset_i <= rx_data_vio_async_out_i(31);
- gtx0_rxcdrreset_i <= rx_data_vio_async_out_i(30);
- gtx0_ila_in_i(84) <= gtx0_rxcharisk_i;
- gtx0_ila_in_i(83) <= gtx0_rxdisperr_i;
- gtx0_ila_in_i(82) <= gtx0_rxnotintable_i;
- gtx0_ila_in_i(81 downto 74) <= gtx0_rxdata_i;
- gtx0_ila_in_i(73 downto 71) <= gtx0_rxstatus_i;
- gtx0_ila_in_i(70 downto 69) <= gtx0_rxlossofsync_i;
- gtx0_ila_in_i(68) <= gtx0_phystatus_i;
- gtx0_ila_in_i(67 downto 60) <= gtx0_error_count_i;
- gtx0_ila_in_i(59 downto 0) <= "000000000000000000000000000000000000000000000000000000000000";
-\r
-\r
-\r
- tx_data_vio_async_in_i <= gtx0_tx_data_vio_async_in_i;
-\r
-\r
- tx_data_vio_sync_in_i <= gtx0_tx_data_vio_sync_in_i;
-\r
- rx_data_vio_async_in_i <= gtx0_rx_data_vio_async_in_i;
-\r
-\r
- rx_data_vio_sync_in_i <= gtx0_rx_data_vio_sync_in_i;
-\r
-\r
- ila_in_i <= gtx0_ila_in_i;
-\r
-\r
-end generate chipscope;\r
-\r
-\r
-no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate\r
-\r
- -- If Chipscope is not being used, drive GTX reset signal\r
- -- from the top level ports\r
- gtx0_gtxtxreset_i <= GTXTXRESET_IN;\r
- gtx0_gtxrxreset_i <= GTXRXRESET_IN;\r
-\r
- -- assign resets for frame_gen modules\r
- gtx0_tx_system_reset_c <= not gtx0_tx_sync_done_i;\r
- -- assign resets for frame_check modules\r
- gtx0_rx_system_reset_c <= not gtx0_rx_sync_done_i;\r
-\r
- gtxtxreset_i <= tied_to_ground_i;
- gtxrxreset_i <= tied_to_ground_i;
- user_tx_reset_i <= tied_to_ground_i;
- user_rx_reset_i <= tied_to_ground_i;
- gtx0_txdlyalignmonenb_i <= tied_to_ground_i;
- gtx0_pllrxreset_i <= tied_to_ground_i;
- gtx0_rxcdrreset_i <= tied_to_ground_i;
-\r
-\r
-\r
-end generate no_chipscope;\r
-\r
-\r
-end RTL;\r
-\r
-\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx\r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : gtxvirtex6fee80_tx_sync.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module gtxvirtex6fee80_tx_sync\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
-entity gtxvirtex6fee80_tx_sync is\r
-generic\r
-(\r
- SIM_TXPMASETPHASE_SPEEDUP : integer:=0\r
-); \r
-port\r
-(\r
- TXENPMAPHASEALIGN : out std_logic;\r
- TXPMASETPHASE : out std_logic;\r
- TXDLYALIGNDISABLE : out std_logic;\r
- TXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-\r
-\r
-end gtxvirtex6fee80_tx_sync;\r
-\r
-architecture RTL of gtxvirtex6fee80_tx_sync is\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
-\r
---*******************************Register Declarations************************\r
-\r
- signal begin_r : std_logic;\r
- signal phase_align_r : std_logic;\r
- signal ready_r : std_logic;\r
- signal sync_counter_r : unsigned(15 downto 0);\r
- signal wait_before_setphase_counter_r : unsigned(5 downto 0);\r
- signal align_reset_counter_r : unsigned(4 downto 0);\r
- signal wait_before_setphase_r : std_logic;\r
- signal align_reset_r : std_logic;\r
- \r
---*******************************Wire Declarations****************************\r
- \r
- signal count_setphase_complete_r : std_logic;\r
- signal count_32_complete_r : std_logic;\r
- signal count_align_reset_complete_r : std_logic;\r
- signal next_phase_align_c : std_logic;\r
- signal next_ready_c : std_logic;\r
- signal next_wait_before_setphase_c : std_logic;\r
- signal next_align_reset_c : std_logic;\r
-\r
-begin\r
---*******************************Main Body of Code****************************\r
-\r
- --________________________________ State machine __________________________ \r
- -- This state machine manages the TX phase alignment procedure of the GTX.\r
- -- The module is held in reset till TXRESETDONE is asserted. Once TXRESETDONE \r
- -- is asserted, the state machine goes into the align_reset_r state, asserting\r
- -- TXDLYALIGNRESET for 20 TXUSRCLK2 cycles. After this, it goes into the \r
- -- wait_before_setphase_r state for 32 cycles. After asserting TXENPMAPHASEALIGN and \r
- -- waiting 32 cycles, it goes into the phase_align_r state where the last \r
- -- part of the alignment procedure is completed. This involves asserting \r
- -- TXPMASETPHASE for 8192 (TXPLL_DIVSEL_OUT=1), 16384 (TXPLL_DIVSEL_OUT=2), \r
- -- or 32768 (TXPLL_DIVSEL_OUT=4) clock cycles. After completion of the phase \r
- -- alignment procedure, TXDLYALIGNDISABLE is deasserted.\r
- \r
- -- State registers\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(RESET='1') then\r
- begin_r <= '1' after DLY;\r
- align_reset_r <= '0' after DLY;\r
- wait_before_setphase_r <= '0' after DLY;\r
- phase_align_r <= '0' after DLY;\r
- ready_r <= '0' after DLY;\r
- else\r
- begin_r <= '0' after DLY;\r
- align_reset_r <= next_align_reset_c after DLY;\r
- wait_before_setphase_r <= next_wait_before_setphase_c after DLY;\r
- phase_align_r <= next_phase_align_c after DLY;\r
- ready_r <= next_ready_c after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Next state logic\r
- next_align_reset_c <= begin_r or \r
- (align_reset_r and not count_align_reset_complete_r);\r
- \r
- next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or \r
- (wait_before_setphase_r and not count_32_complete_r);\r
- \r
- next_phase_align_c <= (wait_before_setphase_r and count_32_complete_r) or\r
- (phase_align_r and not count_setphase_complete_r);\r
- \r
- next_ready_c <= (phase_align_r and count_setphase_complete_r) or\r
- ready_r;\r
-\r
- --______ Counter for holding TXDLYALIGNRESET for 20 TXUSRCLK2 cycles ______\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (align_reset_r='0') then\r
- align_reset_counter_r <= (others=>'0') after DLY;\r
- else\r
- align_reset_counter_r <= align_reset_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
- \r
- count_align_reset_complete_r <= align_reset_counter_r(4) \r
- and align_reset_counter_r(2);\r
-\r
- --______ Counter for waiting 32 clock cycles before TXPMASETPHASE _________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (wait_before_setphase_r='0') then\r
- wait_before_setphase_counter_r <= (others=>'0') after DLY;\r
- else\r
- wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- count_32_complete_r <= wait_before_setphase_counter_r(5);\r
-\r
- --_______________ Counter for holding SYNC for SYNC_CYCLES ________________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (phase_align_r='0') then\r
- sync_counter_r <= (others=>'0') after DLY;\r
- else\r
- sync_counter_r <= sync_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
-fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=1) generate\r
- -- 64 cycles of setphase for simulation\r
- count_setphase_complete_r <= sync_counter_r(6);\r
-end generate fast_simulation;\r
-\r
-no_fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=0) generate\r
- -- 16384 cycles of setphase for output divider of 2\r
- count_setphase_complete_r <= sync_counter_r(14);\r
-end generate no_fast_simulation;\r
-\r
- --_______________ Assign the phase align ports into the GTX _______________\r
-\r
- TXDLYALIGNRESET <= '0';\r
- TXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);\r
- TXPMASETPHASE <= phase_align_r;\r
- TXDLYALIGNDISABLE <= '1';\r
-\r
- --_______________________ Assign the sync_done port _______________________\r
- \r
- SYNC_DONE <= ready_r;\r
- \r
- \r
-end RTL;\r
+++ /dev/null
-------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : mgt_usrclk_source_mmcm.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\ \r
---\r
---\r
--- Module MGT_USRCLK_SOURCE_MMCM (for use with Virtex-6 GTX Transceivers)\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-use ieee.std_logic_unsigned.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***********************************Entity Declaration*******************************\r
-entity MGT_USRCLK_SOURCE_MMCM is\r
-generic\r
-(\r
- MULT : real := 2.0;\r
- DIVIDE : integer := 2; \r
- CLK_PERIOD : real := 6.4; \r
- OUT0_DIVIDE : real := 2.0;\r
- OUT1_DIVIDE : integer := 2;\r
- OUT2_DIVIDE : integer := 2;\r
- OUT3_DIVIDE : integer := 2\r
-);\r
-port\r
-(\r
- CLKFBOUT : out std_logic; \r
- CLK0_OUT : out std_logic;\r
- CLK1_OUT : out std_logic;\r
- CLK2_OUT : out std_logic;\r
- CLK3_OUT : out std_logic;\r
- CLK_IN : in std_logic;\r
- MMCM_LOCKED_OUT : out std_logic;\r
- MMCM_RESET_IN : in std_logic\r
-);\r
-\r
-\r
-end MGT_USRCLK_SOURCE_MMCM;\r
-\r
-architecture RTL of MGT_USRCLK_SOURCE_MMCM is\r
---*********************************Wire Declarations**********************************\r
-\r
- signal tied_to_ground_vec_i : std_logic_vector(15 downto 0);\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_vcc_i : std_logic;\r
- signal clkout0_i : std_logic;\r
- signal clkout1_i : std_logic;\r
- signal clkout2_i : std_logic;\r
- signal clkout3_i : std_logic;\r
- signal clkfbout_i : std_logic;\r
- signal clkfbout_buf : std_logic;\r
-\r
-begin\r
-\r
---*********************************** Beginning of Code *******************************\r
-\r
- -- Static signal Assigments \r
- tied_to_ground_i <= '0';\r
- tied_to_ground_vec_i <= (others=>'0');\r
- tied_to_vcc_i <= '1';\r
-\r
- -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback\r
- -- for improved jitter performance, and to avoid consuming an additional BUFG\r
- mmcm_adv_i : MMCM_ADV\r
- generic map\r
- (\r
- COMPENSATION => "ZHOLD",\r
- CLKFBOUT_MULT_F => MULT,\r
- DIVCLK_DIVIDE => DIVIDE,\r
- CLKFBOUT_PHASE => 0.0,\r
- CLKIN1_PERIOD => CLK_PERIOD,\r
- CLKIN2_PERIOD => 10.0, -- Not used\r
- CLKOUT0_DIVIDE_F => OUT0_DIVIDE,\r
- CLKOUT0_PHASE => 0.0,\r
- CLKOUT1_DIVIDE => OUT1_DIVIDE,\r
- CLKOUT1_PHASE => 0.0,\r
- CLKOUT2_DIVIDE => OUT2_DIVIDE,\r
- CLKOUT2_PHASE => 0.0,\r
- CLKOUT3_DIVIDE => OUT3_DIVIDE,\r
- CLKOUT3_PHASE => 0.0,\r
- CLOCK_HOLD => TRUE \r
- )\r
- port map\r
- (\r
- CLKIN1 => CLK_IN,\r
- CLKIN2 => tied_to_ground_i,\r
- CLKINSEL => tied_to_vcc_i,\r
- CLKFBIN => clkfbout_buf,\r
- CLKOUT0 => clkout0_i,\r
- CLKOUT0B => open,\r
- CLKOUT1 => clkout1_i,\r
- CLKOUT1B => open,\r
- CLKOUT2 => clkout2_i,\r
- CLKOUT2B => open,\r
- CLKOUT3 => clkout3_i,\r
- CLKOUT3B => open,\r
- CLKOUT4 => open,\r
- CLKOUT5 => open,\r
- CLKOUT6 => open,\r
- CLKFBOUT => clkfbout_i,\r
- CLKFBOUTB => open,\r
- CLKFBSTOPPED => open,\r
- CLKINSTOPPED => open,\r
- DO => open,\r
- DRDY => open,\r
- DADDR => tied_to_ground_vec_i(6 downto 0),\r
- DCLK => tied_to_ground_i,\r
- DEN => tied_to_ground_i,\r
- DI => tied_to_ground_vec_i(15 downto 0),\r
- DWE => tied_to_ground_i,\r
- LOCKED => MMCM_LOCKED_OUT,\r
- PSCLK => tied_to_ground_i,\r
- PSEN => tied_to_ground_i, \r
- PSINCDEC => tied_to_ground_i, \r
- PSDONE => open, \r
- PWRDWN => tied_to_ground_i,\r
- RST => MMCM_RESET_IN \r
- );\r
- \r
- clkfb_bufg_i : BUFG \r
- port map\r
- (\r
- O => clkfbout_buf, \r
- I => clkfbout_i\r
- ); \r
- CLKFBOUT <= clkfbout_buf;\r
- \r
- clkout0_bufg_i : BUFG \r
- port map\r
- (\r
- O => CLK0_OUT, \r
- I => clkout0_i\r
- ); \r
-\r
-\r
- clkout1_bufg_i : BUFG \r
- port map\r
- (\r
- O => CLK1_OUT,\r
- I => clkout1_i\r
- );\r
- \r
- \r
- clkout2_bufg_i : BUFG \r
- port map\r
- (\r
- O => CLK2_OUT, \r
- I => clkout2_i\r
- ); \r
-\r
-\r
- clkout3_bufg_i : BUFG \r
- port map\r
- (\r
- O => CLK3_OUT,\r
- I => clkout3_i\r
- ); \r
- \r
-end RTL;\r
- \r
+++ /dev/null
-description=User generated protocol\r
-rx_line_rate=2\r
-use_rx_oversampling=false\r
-rx_divider=/2\r
-rx_datapath_width=10\r
-decoding=8B/10B\r
-rx_reference_clock=80.00\r
-tx_line_rate=2\r
-use_tx_oversampling=false\r
-tx_divider=/2\r
-tx_datapath_width=10\r
-encoding=8B/10B\r
-tx_reference_clock=80.00\r
-use_port_rxoversampleerr=false\r
-use_port_drp=false\r
-ppm_offset=0_(Synchronous)\r
-use_port_txbypass8b10b=false\r
-use_port_txchardispmode=false\r
-use_port_txchardispval=false\r
-use_port_txkerr=false\r
-use_port_txrundisp=false\r
-use_port_rxchariscomma=false\r
-use_port_rxcharisk=true\r
-use_port_rxrundisp=false\r
-use_txbuffer=false\r
-use_rxbuffer=false\r
-txusrclk_source=TXOUTCLK\r
-use_external_txusrclk=false\r
-rxusrclk_source=RXRECCLK\r
-use_external_rxusrclk=false\r
-use_port_txoutclk=true\r
-use_port_txreset=true\r
-use_port_txbufstatus=false\r
-use_port_rxreset=true\r
-use_port_rxrecclk=true\r
-use_port_rxbufstatus=false\r
-use_port_rxbufreset=false\r
-use_comma_detect=true\r
-dec_valid_comma_only=false\r
-comma_preset=K28.5\r
-plus_comma=0101111100\r
-minus_comma=1010000011\r
-comma_mask=1111111100\r
-comma_double=false\r
-comma_alignment=Any_Byte_Boundary\r
-use_port_enpcommaalign=true\r
-use_port_enmcommaalign=true\r
-use_port_rxslide=false\r
-use_port_rxbyteisaligned=false\r
-use_port_rxbyterealign=false\r
-use_port_rxcommadet=false\r
-preemphasis_level=0000\r
-driver_swing=1000\r
-wideband_highpass_mix=000\r
-enable_dfe=false\r
-dfe_mode=Fixed_tap_mode\r
-disable_ac_coupling=true\r
-rx_termination_voltage=MGTAVTT\r
-postemphasis_level=00000\r
-use_port_txpolarity=false\r
-use_port_txinhibit=false\r
-use_port_rxpolarity=false\r
-use_port_rxcdrreset=true\r
-pci_express_mode=false\r
-com_burst_val=15\r
-sata_burst_val=4\r
-sata_idle_val=4\r
-trans_time_to_p2=100\r
-trans_time_from_p2=60\r
-trans_time_non_p2=25\r
-use_port_loopback=false\r
-use_port_rxpowerdown=false\r
-use_port_rxstatus=true\r
-use_port_rxvalid=false\r
-use_port_cominitdet=false\r
-use_port_comsasdet=false\r
-use_port_comwakedet=false\r
-use_port_txcominit=false\r
-use_port_txcomsas=false\r
-use_port_txcomwake=false\r
-use_port_comfinish=false\r
-use_port_txpowerdown=false\r
-use_port_txdetectrx=false\r
-use_port_txelecidle=false\r
-use_port_phystatus=true\r
-use_rx_oob=false\r
-rx_oob_threshold=011\r
-use_prbs_detector=false\r
-use_port_txenprbstst=false\r
-use_port_txprbsforceerr=false\r
-use_port_rxlossofsync=true\r
-rxlossofsyncport=true\r
-errors_to_lose_sync=256\r
-bytes_to_reduce_error=8\r
-use_cb=false\r
-cb_sequence_length=1\r
-cb_sequence_1_max_skew=1\r
-use_two_cb_sequences=false\r
-cb_sequence_2_max_skew=1\r
-cb_seq_1_1_mask=true\r
-cb_seq_1_1=00000000\r
-cb_seq_1_1_k=false\r
-cb_seq_1_1_disp=false\r
-cb_seq_1_2_mask=true\r
-cb_seq_1_2=00000000\r
-cb_seq_1_2_k=false\r
-cb_seq_1_2_disp=false\r
-cb_seq_1_3_mask=true\r
-cb_seq_1_3=00000000\r
-cb_seq_1_3_k=false\r
-cb_seq_1_3_disp=false\r
-cb_seq_1_4_mask=true\r
-cb_seq_1_4=00000000\r
-cb_seq_1_4_k=false\r
-cb_seq_1_4_disp=false\r
-cb_seq_2_1_mask=true\r
-cb_seq_2_1=00000000\r
-cb_seq_2_1_k=false\r
-cb_seq_2_1_disp=false\r
-cb_seq_2_2_mask=true\r
-cb_seq_2_2=00000000\r
-cb_seq_2_2_k=false\r
-cb_seq_2_2_disp=false\r
-cb_seq_2_3_mask=true\r
-cb_seq_2_3=00000000\r
-cb_seq_2_3_k=false\r
-cb_seq_2_3_disp=false\r
-cb_seq_2_4_mask=true\r
-cb_seq_2_4=00000000\r
-cb_seq_2_4_k=false\r
-cb_seq_2_4_disp=false\r
-use_cc=false\r
-cc_sequence_length=1\r
-fifo_upper_bounds=16\r
-fifo_lower_bounds=14\r
-use_two_cc_sequences=false\r
-cc_seq_1_1_mask=true\r
-cc_seq_1_1=00000000\r
-cc_seq_1_1_k=true\r
-cc_seq_1_1_disp=false\r
-cc_seq_1_2_mask=true\r
-cc_seq_1_2=00000000\r
-cc_seq_1_2_k=true\r
-cc_seq_1_2_disp=false\r
-cc_seq_1_3_mask=true\r
-cc_seq_1_3=00000000\r
-cc_seq_1_3_k=true\r
-cc_seq_1_3_disp=false\r
-cc_seq_1_4_mask=true\r
-cc_seq_1_4=00000000\r
-cc_seq_1_4_k=true\r
-cc_seq_1_4_disp=false\r
-cc_seq_2_1_mask=true\r
-cc_seq_2_1=00000000\r
-cc_seq_2_1_k=true\r
-cc_seq_2_1_disp=false\r
-cc_seq_2_2_mask=true\r
-cc_seq_2_2=00000000\r
-cc_seq_2_2_k=true\r
-cc_seq_2_2_disp=false\r
-cc_seq_2_3_mask=true\r
-cc_seq_2_3=00000000\r
-cc_seq_2_3_k=true\r
-cc_seq_2_3_disp=false\r
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-clk_cor_precedence=CC\r
-clk_cor_repeat_wait=0\r
-txpll_sata=00\r
-tx_en_rate_reset_buf=true\r
-tx_drive_mode=DIRECT\r
-show_realign_comma=true\r
-rx_en_mode_reset_buf=true\r
-rx_en_rate_reset_buf=true\r
-rx_en_realign_reset_buf=false\r
-rx_fifo_addr_mode=FULL\r
-chan_bond_seq_2_cfg=00000\r
-sas_max_comsas=52\r
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-trans_time_rate=FF\r
-chan_bond_keep_align=false\r
-tx_tdcc_cfg=11\r
-tx_idle_assert_delay=100\r
-tx_idle_deassert_delay=010\r
-\r
+++ /dev/null
-#ChipScope Pro Analyzer Project File, Version 3.0\r
-#Thu Jul 27 15:56:09 IST 2006\r
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-unit.1.3.port.0.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.10.name=TriggerPort0[10]
-unit.1.3.port.0.s.10.orderindex=-1
-unit.1.3.port.0.s.10.visible=1
-unit.1.3.port.0.s.11.alias=unused11
-unit.1.3.port.0.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.11.name=TriggerPort0[11]
-unit.1.3.port.0.s.11.orderindex=-1
-unit.1.3.port.0.s.11.visible=1
-unit.1.3.port.0.s.12.alias=unused12
-unit.1.3.port.0.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.12.name=TriggerPort0[12]
-unit.1.3.port.0.s.12.orderindex=-1
-unit.1.3.port.0.s.12.visible=1
-unit.1.3.port.0.s.13.alias=unused13
-unit.1.3.port.0.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.13.name=TriggerPort0[13]
-unit.1.3.port.0.s.13.orderindex=-1
-unit.1.3.port.0.s.13.visible=1
-unit.1.3.port.0.s.14.alias=unused14
-unit.1.3.port.0.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.14.name=TriggerPort0[14]
-unit.1.3.port.0.s.14.orderindex=-1
-unit.1.3.port.0.s.14.visible=1
-unit.1.3.port.0.s.15.alias=unused15
-unit.1.3.port.0.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.15.name=TriggerPort0[15]
-unit.1.3.port.0.s.15.orderindex=-1
-unit.1.3.port.0.s.15.visible=1
-unit.1.3.port.0.s.16.alias=unused16
-unit.1.3.port.0.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.16.name=TriggerPort0[16]
-unit.1.3.port.0.s.16.orderindex=-1
-unit.1.3.port.0.s.16.visible=1
-unit.1.3.port.0.s.17.alias=unused17
-unit.1.3.port.0.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.17.name=TriggerPort0[17]
-unit.1.3.port.0.s.17.orderindex=-1
-unit.1.3.port.0.s.17.visible=1
-unit.1.3.port.0.s.18.alias=unused18
-unit.1.3.port.0.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.18.name=TriggerPort0[18]
-unit.1.3.port.0.s.18.orderindex=-1
-unit.1.3.port.0.s.18.visible=1
-unit.1.3.port.0.s.19.alias=unused19
-unit.1.3.port.0.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.19.name=TriggerPort0[19]
-unit.1.3.port.0.s.19.orderindex=-1
-unit.1.3.port.0.s.19.visible=1
-unit.1.3.port.0.s.20.alias=unused20
-unit.1.3.port.0.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.20.name=TriggerPort0[20]
-unit.1.3.port.0.s.20.orderindex=-1
-unit.1.3.port.0.s.20.visible=1
-unit.1.3.port.0.s.21.alias=unused21
-unit.1.3.port.0.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.21.name=TriggerPort0[21]
-unit.1.3.port.0.s.21.orderindex=-1
-unit.1.3.port.0.s.21.visible=1
-unit.1.3.port.0.s.22.alias=unused22
-unit.1.3.port.0.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.22.name=TriggerPort0[22]
-unit.1.3.port.0.s.22.orderindex=-1
-unit.1.3.port.0.s.22.visible=1
-unit.1.3.port.0.s.23.alias=unused23
-unit.1.3.port.0.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.23.name=TriggerPort0[23]
-unit.1.3.port.0.s.23.orderindex=-1
-unit.1.3.port.0.s.23.visible=1
-unit.1.3.port.0.s.24.alias=unused24
-unit.1.3.port.0.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.24.name=TriggerPort0[24]
-unit.1.3.port.0.s.24.orderindex=-1
-unit.1.3.port.0.s.24.visible=1
-unit.1.3.port.0.s.25.alias=unused25
-unit.1.3.port.0.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.25.name=TriggerPort0[25]
-unit.1.3.port.0.s.25.orderindex=-1
-unit.1.3.port.0.s.25.visible=1
-unit.1.3.port.0.s.26.alias=unused26
-unit.1.3.port.0.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.26.name=TriggerPort0[26]
-unit.1.3.port.0.s.26.orderindex=-1
-unit.1.3.port.0.s.26.visible=1
-unit.1.3.port.0.s.27.alias=unused27
-unit.1.3.port.0.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.27.name=TriggerPort0[27]
-unit.1.3.port.0.s.27.orderindex=-1
-unit.1.3.port.0.s.27.visible=1
-unit.1.3.port.0.s.28.alias=unused28
-unit.1.3.port.0.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.28.name=TriggerPort0[28]
-unit.1.3.port.0.s.28.orderindex=-1
-unit.1.3.port.0.s.28.visible=1
-unit.1.3.port.0.s.29.alias=unused29
-unit.1.3.port.0.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.29.name=TriggerPort0[29]
-unit.1.3.port.0.s.29.orderindex=-1
-unit.1.3.port.0.s.29.visible=1
-unit.1.3.port.0.s.30.alias=unused30
-unit.1.3.port.0.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.30.name=TriggerPort0[30]
-unit.1.3.port.0.s.30.orderindex=-1
-unit.1.3.port.0.s.30.visible=1
-unit.1.3.port.0.s.31.alias=unused31
-unit.1.3.port.0.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.31.name=TriggerPort0[31]
-unit.1.3.port.0.s.31.orderindex=-1
-unit.1.3.port.0.s.31.visible=1
-unit.1.3.port.0.s.32.alias=unused32
-unit.1.3.port.0.s.32.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.32.name=TriggerPort0[32]
-unit.1.3.port.0.s.32.orderindex=-1
-unit.1.3.port.0.s.32.visible=1
-unit.1.3.port.0.s.33.alias=unused33
-unit.1.3.port.0.s.33.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.33.name=TriggerPort0[33]
-unit.1.3.port.0.s.33.orderindex=-1
-unit.1.3.port.0.s.33.visible=1
-unit.1.3.port.0.s.34.alias=unused34
-unit.1.3.port.0.s.34.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.34.name=TriggerPort0[34]
-unit.1.3.port.0.s.34.orderindex=-1
-unit.1.3.port.0.s.34.visible=1
-unit.1.3.port.0.s.35.alias=unused35
-unit.1.3.port.0.s.35.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.35.name=TriggerPort0[35]
-unit.1.3.port.0.s.35.orderindex=-1
-unit.1.3.port.0.s.35.visible=1
-unit.1.3.port.0.s.36.alias=unused36
-unit.1.3.port.0.s.36.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.36.name=TriggerPort0[36]
-unit.1.3.port.0.s.36.orderindex=-1
-unit.1.3.port.0.s.36.visible=1
-unit.1.3.port.0.s.37.alias=unused37
-unit.1.3.port.0.s.37.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.37.name=TriggerPort0[37]
-unit.1.3.port.0.s.37.orderindex=-1
-unit.1.3.port.0.s.37.visible=1
-unit.1.3.port.0.s.38.alias=unused38
-unit.1.3.port.0.s.38.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.38.name=TriggerPort0[38]
-unit.1.3.port.0.s.38.orderindex=-1
-unit.1.3.port.0.s.38.visible=1
-unit.1.3.port.0.s.39.alias=unused39
-unit.1.3.port.0.s.39.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.39.name=TriggerPort0[39]
-unit.1.3.port.0.s.39.orderindex=-1
-unit.1.3.port.0.s.39.visible=1
-unit.1.3.port.0.s.40.alias=unused40
-unit.1.3.port.0.s.40.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.40.name=TriggerPort0[40]
-unit.1.3.port.0.s.40.orderindex=-1
-unit.1.3.port.0.s.40.visible=1
-unit.1.3.port.0.s.41.alias=unused41
-unit.1.3.port.0.s.41.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.41.name=TriggerPort0[41]
-unit.1.3.port.0.s.41.orderindex=-1
-unit.1.3.port.0.s.41.visible=1
-unit.1.3.port.0.s.42.alias=unused42
-unit.1.3.port.0.s.42.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.42.name=TriggerPort0[42]
-unit.1.3.port.0.s.42.orderindex=-1
-unit.1.3.port.0.s.42.visible=1
-unit.1.3.port.0.s.43.alias=unused43
-unit.1.3.port.0.s.43.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.43.name=TriggerPort0[43]
-unit.1.3.port.0.s.43.orderindex=-1
-unit.1.3.port.0.s.43.visible=1
-unit.1.3.port.0.s.44.alias=unused44
-unit.1.3.port.0.s.44.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.44.name=TriggerPort0[44]
-unit.1.3.port.0.s.44.orderindex=-1
-unit.1.3.port.0.s.44.visible=1
-unit.1.3.port.0.s.45.alias=unused45
-unit.1.3.port.0.s.45.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.45.name=TriggerPort0[45]
-unit.1.3.port.0.s.45.orderindex=-1
-unit.1.3.port.0.s.45.visible=1
-unit.1.3.port.0.s.46.alias=unused46
-unit.1.3.port.0.s.46.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.46.name=TriggerPort0[46]
-unit.1.3.port.0.s.46.orderindex=-1
-unit.1.3.port.0.s.46.visible=1
-unit.1.3.port.0.s.47.alias=unused47
-unit.1.3.port.0.s.47.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.47.name=TriggerPort0[47]
-unit.1.3.port.0.s.47.orderindex=-1
-unit.1.3.port.0.s.47.visible=1
-unit.1.3.port.0.s.48.alias=unused48
-unit.1.3.port.0.s.48.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.48.name=TriggerPort0[48]
-unit.1.3.port.0.s.48.orderindex=-1
-unit.1.3.port.0.s.48.visible=1
-unit.1.3.port.0.s.49.alias=unused49
-unit.1.3.port.0.s.49.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.49.name=TriggerPort0[49]
-unit.1.3.port.0.s.49.orderindex=-1
-unit.1.3.port.0.s.49.visible=1
-unit.1.3.port.0.s.50.alias=unused50
-unit.1.3.port.0.s.50.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.50.name=TriggerPort0[50]
-unit.1.3.port.0.s.50.orderindex=-1
-unit.1.3.port.0.s.50.visible=1
-unit.1.3.port.0.s.51.alias=unused51
-unit.1.3.port.0.s.51.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.51.name=TriggerPort0[51]
-unit.1.3.port.0.s.51.orderindex=-1
-unit.1.3.port.0.s.51.visible=1
-unit.1.3.port.0.s.52.alias=unused52
-unit.1.3.port.0.s.52.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.52.name=TriggerPort0[52]
-unit.1.3.port.0.s.52.orderindex=-1
-unit.1.3.port.0.s.52.visible=1
-unit.1.3.port.0.s.53.alias=unused53
-unit.1.3.port.0.s.53.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.53.name=TriggerPort0[53]
-unit.1.3.port.0.s.53.orderindex=-1
-unit.1.3.port.0.s.53.visible=1
-unit.1.3.port.0.s.54.alias=unused54
-unit.1.3.port.0.s.54.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.54.name=TriggerPort0[54]
-unit.1.3.port.0.s.54.orderindex=-1
-unit.1.3.port.0.s.54.visible=1
-unit.1.3.port.0.s.55.alias=unused55
-unit.1.3.port.0.s.55.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.55.name=TriggerPort0[55]
-unit.1.3.port.0.s.55.orderindex=-1
-unit.1.3.port.0.s.55.visible=1
-unit.1.3.port.0.s.56.alias=unused56
-unit.1.3.port.0.s.56.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.56.name=TriggerPort0[56]
-unit.1.3.port.0.s.56.orderindex=-1
-unit.1.3.port.0.s.56.visible=1
-unit.1.3.port.0.s.57.alias=unused57
-unit.1.3.port.0.s.57.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.57.name=TriggerPort0[57]
-unit.1.3.port.0.s.57.orderindex=-1
-unit.1.3.port.0.s.57.visible=1
-unit.1.3.port.0.s.58.alias=unused58
-unit.1.3.port.0.s.58.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.58.name=TriggerPort0[58]
-unit.1.3.port.0.s.58.orderindex=-1
-unit.1.3.port.0.s.58.visible=1
-unit.1.3.port.0.s.59.alias=unused59
-unit.1.3.port.0.s.59.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.59.name=TriggerPort0[59]
-unit.1.3.port.0.s.59.orderindex=-1
-unit.1.3.port.0.s.59.visible=1
-unit.1.3.portcount=1
-unit.1.3.samplesPerTrigger=1
-unit.1.3.triggerCapture=1
-unit.1.3.triggerNSamplesTS=0
-unit.1.3.triggerPosition=0
-unit.1.3.triggerWindowCount=1
-unit.1.3.triggerWindowDepth=1024
-unit.1.3.triggerWindowTS=0
-unit.1.3.waveform.count=8
-unit.1.3.waveform.posn.0.channel=84
-unit.1.3.waveform.posn.0.name=DataPort[84]
-unit.1.3.waveform.posn.0.type=signal
-unit.1.3.waveform.posn.1.channel=83
-unit.1.3.waveform.posn.1.name=DataPort[83]
-unit.1.3.waveform.posn.1.type=signal
-unit.1.3.waveform.posn.2.channel=82
-unit.1.3.waveform.posn.2.name=DataPort[82]
-unit.1.3.waveform.posn.2.type=signal
-unit.1.3.waveform.posn.3.name=rxdata
-unit.1.3.waveform.posn.3.channel=2147483646
-unit.1.3.waveform.posn.3.type=bus
-unit.1.3.waveform.posn.3.radix=1
-unit.1.3.waveform.posn.4.name=rxstatus
-unit.1.3.waveform.posn.4.channel=2147483646
-unit.1.3.waveform.posn.4.type=bus
-unit.1.3.waveform.posn.4.radix=1
-unit.1.3.waveform.posn.5.name=rxlossofsync
-unit.1.3.waveform.posn.5.channel=2147483646
-unit.1.3.waveform.posn.5.type=bus
-unit.1.3.waveform.posn.5.radix=1
-unit.1.3.waveform.posn.6.channel=68
-unit.1.3.waveform.posn.6.name=DataPort[68]
-unit.1.3.waveform.posn.6.type=signal
-unit.1.3.waveform.posn.7.name=error_count
-unit.1.3.waveform.posn.7.channel=2147483646
-unit.1.3.waveform.posn.7.type=bus
-unit.1.3.waveform.posn.7.radix=1
-\r
-\r
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$b25
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0;3xLg`33td9<=:50;3xLg`33td9<=;50;3xLg`33td9<=850;3xLg`33td9<=950;3xLg`33td9<=650;3xLg`33td9<=750;3xLg`33td9<=o50;3xLg`33td9<=l50;3xLg`33td9<=m50;3xLg`33td9<=j50;3xLg`33td9<=k50;3xLg`33td9<=h50;3xLg`33td9<<>50;3xLg`33td9<<?50;3xLg`33td9<<<50;3xLg`33td9<<=50;3xLg`33td9<<:50;3xLg`33td9<<;50;3xLg`33td9<<850;3xLg`33td9<<950;3xLg`33td9<<650;3xLg`33td9<<750;3xLg`33td9<<o50;3xLg`33td9<<l50;3xLg`33td9<<m50;3xLg`33td9<<j50;3xLg`33td9<<k50;3xLg`33td9<<h50;3xLg`33td9<?>50;3xLg`33td9<??50;3xLg`33td9<?<50;3xLg`33td9<?=50;3xLg`33td9<?:50;3xLg`33td9<?;50;3xLg`33td9<?850;3xLg`33td9<?950;3xLg`33td9<?650;3xLg`33td9<?750;3xLg`33td9<?o50;3xLg`33td9<?l50;3xLg`33td9<?m50;3xLg`33td9<?j50;3xLg`33td9<?k50;3xLg`33td9<?h50;3xLg`33td9<>>50;3xLg`33td9<>?50;3xLg`33td9<><50;3xLg`33td9<>=50;3xLg`33td9<>:50;3xLg`33td9<>;50;3xLg`33td9<>850;3xLg`33td9<>950;3xLg`33td9<>650;3xLg`33td9<>750;3xLg`33td9<>o50;3xLg`33td9<>l50;3xLg`33td9<>m50;3xLg`33td9<>j50;3xLg`33td9<>k50;3xLg`33td9<>h50;3xLg`33td9<9>50;3xLg`33td9<9?50;3xLg`33td9<9<50;3xLg`33td9<9=50;3xLg`33td9<9:50;3xLg`33td9<9;50;3xLg`33td9<9850;3xLg`33td9<9950;3xLg`33td9<9650;3xLg`33td9<9750;3xLg`33td9<9o50;3xLg`33td9<9l50;3xLg`33td9<9m50;3xLg`33td9<9j50;3xLg`33td9<9k50;3xLg`33td9<9h50;3xLg`33td9<8>50;3xLg`33td9<8?50;3xLg`33td9<8<50;3xLg`33td9<8=50;3xLg`33td9<8:50;3xLg`33td9<8;50;3xLg`33td9<8850;3xLg`33td9<8950;3xLg`33td9<8650;3xLg`33td9<8750;3xLg`33td9<8o50;3xLg`33td9<8l50;3xLg`33td9<8m50;3xLg`33td9<8j50;3xLg`33td9<8k50;3xLg`33td9<8h50;3xLg`33td9<;>50;3xLg`33td9<;?50;3xLg`33td9<;<50;3xLg`33td9<;=50;3xLg`33td9<;:50;3xLg`33td9<;;50;3xLg`33td9<;850;3xLg`33td9<;950;3xLg`33td9<;650;3xLg`33td9<;750;3xLg`33td9<;o50;3xLg`33td9<;l50;3xLg`33td9<;m50;3xLg`33td9<;j50;3xLg`33td9<;k50;3xLg`33td9<;h50;3xLg`33td9<:>50;3xLg`33td9<:?50;3xLg`33td9<:<50;3xLg`33td9<:=50;3xLg`33td9<::50;3xLg`33td9<:;50;3xLg`33td9<:850;3xLg`33td9<:950;3xLg`33td9<:650;3xLg`33td9<:750;3xLg`33td9<:o50;3xLg`33td9<:l50;3xLg`33td9<:m50;3xLg`33td9<:j50;3xLg`33td9<:k50;3xLg`33td9<:h50;3xLg`33td9<5>50;3xLg`33td9<5?50;3xLg`33td9<5<50;3xLg`33td9<5=50;3xLg`33td9<5:50;3xLg`33td9<5;50;3xLg`33td9<5850;3xLg`33td9<5950;3xLg`33td9<5650;3xLg`33td9<5750;3xLg`33td9<5o50;3xLg`33td9<5l50;3xLg`33td9<5m50;3xLg`33td9<5j50;3xLg`33td9<5k50;3xLg`33td9<5h50;3xLg`33td9<4>50;3xLg`33td9<4?50;3xLg`33td9<4<50;3xLg`33td9<4=50;3xLg`33td9<4:50;3xLg`33td9<4;50;3xLg`33td9<4850;3xLg`33td9<4950;3xLg`33td9<4650;3xLg`33td9<4750;3xLg`33td9<4o50;3xLg`33td9<4l50;3xLg`33td9<4m50;3xLg`33td9<4j50;3xLg`33td9<4k50;3xLg`33td9<4h50;3xLg`33td9<l>50;3xLg`33td9<l?50;3xLg`33td9<l<50;3xLg`33td9<l=50;3xLg`33td9<l:50;3xLg`33td9<l;50;3xLg`33td9<l850;3xLg`33td9<l950;3xLg`33td9<l650;3xLg`33td9<l750;3xLg`33td9<lo50;3xLg`33td9<ll50;3xLg`33td9<lm50;3xLg`33td9<lj50;3xLg`33td9<lk50;3xLg`33td9<lh50;3xLg`33td9<o>50;3xLg`33td9<o?50;3xLg`33td9<o<50;3xLg`33td9<o=50;3xLg`33td9<o:50;3xLg`33td9<o;50;3xLg`33td9<o850;3xLg`33td9<o950;3xLg`33td9<o650;3xLg`33td9<o750;3xLg`33td9<oo50;3xLg`33td9<ol50;3xLg`33td9<om50;3xLg`33td9<oj50;3xLg`33td9<ok50;3xLg`33td9<oh50;3xLg`33td9<n>50;3xLg`33td9<n?50;3xLg`33td9<n<50;3xLg`33td9<n=50;3xLg`33td9<n:50;3xLg`33td9<n;50;3xLg`33td9<n850;3xLg`33td9<n950;3xLg`33td9<n650;3xLg`33td9<n750;3xLg`33td9<no50;3xLg`33td9<nl50;3xLg`33td9<nm50;3xLg`33td9<nj50;3xLg`33td9<nk50;3xLg`33td9<nh50;3xLg`33td9<i>50;3xLg`33td9<i?50;3xLg`33td9<i<50;3xLg`33td9<i=50;3xLg`33td9<i:50;3xLg`33td9<i;50;3xLg`33td9<i850;3xLg`33td9<i950;3xLg`33td9<i650;3xLg`33td9<i750;3xLg`33td9<io50;3xLg`33td9<il50;3xLg`33td9<im50;3xLg`33td9<ij50;3xLg`33td9<ik50;3xLg`33td9<ih50;3xLg`33td9<h>50;3xLg`33td9<h?50;3xLg`33td9<h<50;3xLg`33td9<h=50;3xLg`33td9<h:50;3xLg`33td9<h;50;3xLg`33td9<h850;3xLg`33td9<h950;3xLg`33td9<h650;3xLg`33td9<h750;3xLg`33td9<ho50;3xLg`33td9<hl50;3xLg`33td9<hm50;3xLg`33td9<hj50;3xLg`33td9<hk50;3xLg`33td9<hh50;3xLg`33td9<k>50;3xLg`33td9<k?50;3xLg`33td9<k<50;3xLg`33td9<k=50;3xLg`33td9<k:50;3xLg`33td9<k;50;3xLg`33td9<k850;3xLg`33td9<k950;3xLg`33td9<k650;3xLg`33td9<k750;3xLg`33td9<ko50;3xLg`33td9<kl50;3xLg`33td9<km50;3xLg`33td9<kj50;3xLg`33td9<kk50;3xLg`33td9<kh50;3xLg`33td9==>50;3xLg`33td9==?50;3xLg`33td9==<50;3xLg`33td9===50;3xLg`33td9==:50;3xLg`33td9==;50;3xLg`33td9==850;3xLg`33td9==950;3xLg`33td9==650;3xLg`33td9==750;3xLg`33td9==o50;3xLg`33td9==l50;3xLg`33td9==m50;3xLg`33td9==j50;3xLg`33td9==k50;3xLg`33td9==h50;3xLg`33td9=<>50;3xLg`33td9=<?50;3xLg`33td9=<<50;3xLg`33td9=<=50;3xLg`33td9=<:50;3xLg`33td9=<;50;3xLg`33td9=<850;3xLg`33td9=<950;3xLg`33td9=<650;3xLg`33td9=<750;3xLg`33td9=<o50;3xLg`33td9=<l50;3xLg`33td9=<m50;3xLg`33td9=<j50;3xLg`33td9=<k50;3xLg`33td9=<h50;3xLg`33td9=?>50;3xLg`33td9=??50;3xLg`33td9=?<50;3xLg`33td9=?=50;3xLg`33td9=?:50;3xLg`33td9=?;50;3xLg`33td9=?850;3xLg`33td9=?950;3xLg`33td9=?650;3xLg`33td9=?750;3xLg`33td9=?o50;3xLg`33td9=?l50;3xLg`33td9=?m50;3xLg`33td9=?j50;3xLg`33td9=?k50;3xLg`33td9=?h50;3xLg`33td9=>>50;3xLg`33td9=>?50;3xLg`33td9=><50;3xLg`33td9=>=50;3xLg`33td9=>:50;3xLg`33td9=>;50;3xLg`33td9=>850;3xLg`33td9=>950;3xLg`33td9=>650;3xLg`33td9=>750;3xLg`33td9=>o50;3xLg`33td9=>l50;3xLg`33td9=>m50;3xLg`33td9=>j50;3xLg`33td9=>k50;3xLg`33td9=>h50;3xLg`33td9=9>50;3xLg`33td9=9?50;3xLg`33td9=9<50;3xLg`33td9=9=50;3xLg`33td9=9:50;3xLg`33td9=9;50;3xLg`33td9=9850;3xLg`33td9=9950;3xLg`33td9=9650;3xLg`33td9=9750;3xLg`33td9=9o50;3xLg`33td9=9l50;3xLg`33td9=9m50;3xLg`33td9=9j50;3xLg`33td9=9k50;3xLg`33td9=9h50;3xLg`33td9=8>50;3xLg`33td9=8?50;3xLg`33td9=8<50;3xLg`33td9=8=50;3xLg`33td9=8:50;3xLg`33td9=8;50;3xLg`33td9=8850;3xLg`33td9=8950;3xLg`33td9=8650;3xLg`33td9=8750;3xLg`33td9=8o50;3xLg`33td9=8l50;3xLg`33td9=8m50;3xLg`33td9=8j50;3xLg`33td9=8k50;3xLg`33td9=8h50;3xLg`33td9=;>50;3xLg`33td9=;?50;3xLg`33td9=;<50;3xLg`33td9=;=50;3xLg`33td9=;:50;3xLg`33td9=;;50;3xLg`33td9=;850;3xLg`33td9=;950;3xLg`33td9=;650;3xLg`33td9=;750;3xLg`33td9=;o50;3xLg`33td9=;l50;3xLg`33td9=;m50;3xLg`33td9=;j50;3xLg`33td9=;k50;3xLg`33td9=;h50;3xLg`33td9=:>50;3xLg`33td9=:?50;3xLg`33td9=:<50;3xLg`33td9=:=50;3xLg`33td9=::50;3xLg`33td9=:;50;3xLg`33td9=:850;3xLg`33td9=:950;3xLg`33td9=:650;3xLg`33td9=:750;3xLg`33td9=:o50;3xLg`33td9=:l50;3xLg`33td9=:m50;3xLg`33td9=:j50;3xLg`33td9=:k50;3xLg`33td9=:h50;3xLg`33td9=5>50;3xLg`33td9=5?50;3xLg`33td9=5<50;3xLg`33td9=5=50;3xLg`33td9=5:50;3xLg`33td9=5;50;3xLg`33td9=5850;3xLg`33td9=5950;3xLg`33td9=5650;3xLg`33td9=5750;3xLg`33td9=5o50;3xLg`33td9=5l50;3xLg`33td9=5m50;3xLg`33td9=5j50;3xLg`33td9=5k50;3xLg`33td9=5h50;3xLg`33td9=4>50;3xLg`33td9=4?50;3xLg`33td9=4<50;3xLg`33td9=4=50;3xLg`33td9=4:50;3xLg`33td9=4;50;3xLg`33td9=4850;3xLg`33td9=4950;3xLg`33td9=4650;3xLg`33td9=4750;3xLg`33td9=4o50;3xLg`33td9=4l50;3xLg`33td9=4m50;3xLg`33td9=4j50;3xLg`33td9=4k50;3xLg`33td9=4h50;3xLg`33td9=l>50;3xLg`33td9=l?50;3xLg`33td9=l<50;3xLg`33td9=l=50;3xLg`33td9=l:50;3xLg`33td9=l;50;3xLg`33td9=l850;3xLg`33td9=l950;3xLg`33td9=l650;3xLg`33td9=l750;3xLg`33td9=lo50;3xLg`33td9=ll50;3xLg`33td9=lm50;3xLg`33td9=lj50;3xLg`33td9=lk50;3xLg`33td9=lh50;3xLg`33td9=o>50;3xLg`33td9=o?50;3xLg`33td9=o<50;3xLg`33td9=o=50;3xLg`33td9=o:50;3xLg`33td9=o;50;3xLg`33td9=o850;3xLg`33td9=o950;3xLg`33td9=o650;3xLg`33td9=o750;3xLg`33td9=oo50;3xLg`33td9=ol50;3xLg`33td9=om50;3xLg`33td9=oj50;3xLg`33td9=ok50;3xLg`33td9=oh50;3xLg`33td9=n>50;3xLg`33td9=n?50;3xLg`33td9=n<50;3xLg`33td9=n=50;3xLg`33td9=n:50;3xLg`33td9=n;50;3xLg`33td9=n850;3xLg`33td9=n950;3xLg`33td9=n650;3xLg`33td9=n750;3xLg`33td9=no50;3xLg`33td9=nl50;3xLg`33td9=nm50;3xLg`33td9=nj50;3xLg`33td9=nk50;3xLg`33td9=nh50;3xLg`33td9=i>50;3xLg`33td9=i?50;3xLg`33td9=i<50;3xLg`33td9=i=50;3xLg`33td9=i:50;3xLg`33td9=i;50;3xLg`33td9=i850;3xLg`33td9=i950;3xLg`33td9=i650;3xLg`33td9=i750;3xLg`33td9=io50;3xLg`33td9=il50;3xLg`33td9=im50;3xLg`33td9=ij50;3xLg`33td9=ik50;3xLg`33td9=ih50;3xLg`33td9=h>50;3xLg`33td9=h?50;3xLg`33td9=h<50;3xLg`33td9=h=50;3xLg`33td9=h:50;3xLg`33td9=h;50;3xLg`33td9=h850;3xLg`33td9=h950;3xLg`33td9=h650;3xLg`33td9=h750;3xLg`33td9=ho50;3xLg`33td9=hl50;3xLg`33td9=hm50;3xLg`33td9=hj50;3xLg`33td9=hk50;3xLg`33td9=hh50;3xLg`33td9=k>50;3xLg`33td9=k?50;3xLg`33td9=k<50;3xLg`33td9=k=50;3xLg`33td9=k:50;3xLg`33td9=k;50;3xLg`33td9=k850;3xLg`33td9=k950;3xLg`33td9=k650;3xLg`33td9=k750;3xLg`33td9=ko50;3xLg`33td9=kl50;3xLg`33td9=km50;3xLg`33td9=kj50;3xLg`33td9=kk50;3xLg`33td9=kh50;3xLg`33td9>=>50;3xLg`33td9>=?50;3xLg`33td9>=<50;3xLg`33td9>==50;3xLg`33td9>=:50;3xLg`33td9>=;50;3xLg`33td9>=850;3xLg`33td9>=950;3xLg`33td9>=650;3xLg`33td9>=750;3xLg`33td9>=o50;3xLg`33td9>=l50;3xLg`33td9>=m50;3xLg`33td9>=j50;3xLg`33td9>=k50;3xLg`33td9>=h50;3xLg`33td9><>50;3xLg`33td9><?50;3xLg`33td9><<50;3xLg`33td9><=50;3xLg`33td9><:50;3xLg`33td9><;50;3xLg`33td9><850;3xLg`33td9><950;3xLg`33td9><650;3xLg`33td9><750;3xLg`33td9><o50;3xLg`33td9><l50;3xLg`33td9><m50;3xLg`33td9><j50;3xLg`33td9><k50;3xLg`33td9><h50;3xLg`33td9>?>50;3xLg`33td9>??50;3xLg`33td9>?<50;3xLg`33td9>?=50;3xLg`33td9>?:50;3xLg`33td9>?;50;3xLg`33td9>?850;3xLg`33td9>?950;3xLg`33td9>?650;3xLg`33td9>?750;3xLg`33td9>?o50;3xLg`33td9>?l50;3xLg`33td9>?m50;3xLg`33td9>?j50;3xLg`33td9>?k50;3xLg`33td9>?h50;3xLg`33td9>>>50;3xLg`33td9>>?50;3xLg`33td9>><50;3xLg`33td9>>=50;3xLg`33td9>>:50;3xLg`33td9>>;50;3xLg`33td9>>850;3xLg`33td9>>950;3xLg`33td9>>650;3xLg`33td9>>750;3xLg`33td9>>o50;3xLg`33td9>>l50;3xLg`33td9>>m50;3xLg`33td9>>j50;3xLg`33td9>>k50;3xLg`33td9>>h50;3xLg`33td9>9>50;3xLg`33td9>9?50;3xLg`33td9>9<50;3xLg`33td9>9=50;3xLg`33td9>9:50;3xLg`33td9>9;50;3xLg`33td9>9850;3xLg`33td9>9950;3xLg`33td9>9650;3xLg`33td9>9750;3xLg`33td9>9o50;3xLg`33td9>9l50;3xLg`33td9>9m50;3xLg`33td9>9j50;3xLg`33td9>9k50;3xLg`33td9>9h50;3xLg`33td9>8>50;3xLg`33td9>8?50;3xLg`33td9>8<50;3xLg`33td9>8=50;3xLg`33td9>8:50;3xLg`33td9>8;50;3xLg`33td9>8850;3xLg`33td9>8950;3xLg`33td9>8650;3xLg`33td9>8750;3xLg`33td9>8o50;3xLg`33td9>8l50;3xLg`33td9>8m50;3xLg`33td9>8j50;3xLg`33td9>8k50;3xLg`33td9>8h50;3xLg`33td9>;>50;3xLg`33td9>;?50;3xLg`33td9>;<50;3xLg`33td9>;=50;3xLg`33td9>;:50;3xLg`33td9>;;50;3xLg`33td9>;850;3xLg`33td9>;950;3xLg`33td9>;650;3xLg`33td9>;750;3xLg`33td9>;o50;3xLg`33td9>;l50;3xLg`33td9>;m50;3xLg`33td9>;j50;3xLg`33td9>;k50;3xLg`33td9>;h50;3xLg`33td9>:>50;3xLg`33td9>:?50;3xLg`33td9>:<50;3xLg`33td9>:=50;3xLg`33td9>::5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\ No newline at end of file
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
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\ No newline at end of file
+++ /dev/null
-\r
-REM\r
-REM ____ ____\r
-REM / /\/ /\r
-REM /___/ \ / Vendor: Xilinx\r
-REM \ \ \/ Version : 1.12\r
-REM \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-REM / / Filename : implement_bat.ejava\r
-REM /___/ /\ \r
-REM \ \ / \\r
-REM \___\/\___\\r
-REM\r
-REM\r
-REM implement.sh script\r
-REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-REM\r
-REM\r
-REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-REM \r
-REM This file contains confidential and proprietary information\r
-REM of Xilinx, Inc. and is protected under U.S. and \r
-REM international copyright and other intellectual property\r
-REM laws.\r
-REM \r
-REM DISCLAIMER\r
-REM This disclaimer is not a license and does not grant any\r
-REM rights to the materials distributed herewith. Except as\r
-REM otherwise provided in a valid license issued to you by\r
-REM Xilinx, and to the maximum extent permitted by applicable\r
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-REM (2) Xilinx shall not be liable (whether in contract or tort,\r
-REM including negligence, or under any other theory of\r
-REM liability) for any loss or damage of any kind or nature\r
-REM related to, arising under or in connection with these\r
-REM materials, including for any direct, or any indirect,\r
-REM special, incidental, or consequential loss or damage\r
-REM (including loss of data, profits, goodwill, or any type of\r
-REM loss or damage suffered as a result of any action brought\r
-REM by a third party) even if such damage or loss was\r
-REM reasonably foreseeable or Xilinx had been advised of the\r
-REM possibility of the same.\r
-REM\r
-REM CRITICAL APPLICATIONS\r
-REM Xilinx products are not designed or intended to be fail-\r
-REM safe, or for use in any application requiring fail-safe\r
-REM performance, such as life-support or safety devices or\r
-REM systems, Class III medical devices, nuclear facilities,\r
-REM applications related to the deployment of airbags, or any\r
-REM other applications that could lead to death, personal\r
-REM injury, or severe property or environmental damage\r
-REM (individually and collectively, "Critical\r
-REM Applications"). Customer assumes the sole risk and\r
-REM liability of any use of Xilinx products in Critical\r
-REM Applications, subject only to applicable laws and\r
-REM regulations governing limitations on product liability.\r
-REM\r
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-REM PART OF THIS FILE AT ALL TIMES.\r
-\r
-REM Set XST as default synthesizer\r
-\r
-REM Read command line arguments\r
-\r
-REM Change CWD to results\r
-\r
-REM Clean results directory\r
-REM Create results directory\r
-REM Change current directory to results\r
-ECHO WARNING: Removing existing results directory\r
-RMDIR /S /Q results\r
-MKDIR results\r
-COPY xst.prj .\results\\r
-COPY xst.scr .\results\\r
-COPY *.ngc .\results\\r
-\r
-REM Run Synthesis\r
-\r
-ECHO "### Running Xst - "\r
-xst -ifn xst.scr\r
-\r
-COPY gtxVirtex6FEE80_top.ngc .\results\r
-cd .\results\r
-\r
-REM Run ngdbuild\r
-\r
-ngdbuild -uc ..\..\example_design\gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.ngc gtxVirtex6FEE80_top.ngd\r
-\r
-REM end run ngdbuild section\r
-\r
-REM Run map\r
-\r
-ECHO 'Running NGD'\r
-map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd\r
-\r
-REM Run par\r
-\r
-ECHO 'Running par'\r
-par mapped.ncd routed.ncd \r
-\r
-REM Report par results\r
-\r
-ECHO 'Running design through bitgen'\r
-bitgen -w routed.ncd\r
-\r
-REM Trace Report\r
-\r
-ECHO 'Running trce'\r
-trce -e 10 routed.ncd mapped.pcf -o routed\r
-\r
-REM Run netgen\r
-\r
-ECHO 'Running netgen to create gate level VHDL model'\r
-netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd\r
-\r
-REM Change directory to implement\r
-\r
-CD ..\r
-\r
+++ /dev/null
-#!/bin/bash\r
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : implement_sh.ejava \r
-## /___/ /\ \r
-## \ \ / \\r
-## \___\/\___\\r
-##\r
-##\r
-## implement.sh script \r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-#-----------------------------------------------------------------------------\r
-# Script to synthesize and implement the RTL provided for the GTX wizard\r
-#-----------------------------------------------------------------------------\r
-\r
-##---------------------Change CWD to results-------------------------------------\r
-\r
-#Clean results directory\r
-#Create results directory\r
-#Change current directory to results\r
-echo "WARNING: Removing existing results directory"\r
-rm -rf results\r
-mkdir results\r
-cp xst.prj ./results\r
-cp xst.scr ./results\r
-cp *.ngc ./results\r
-\r
-##-----------------------------Run Synthesis-------------------------------------\r
-\r
-echo "### Running Xst - "\r
-xst -ifn xst.scr\r
-\r
-cp gtxVirtex6FEE80_top.ngc ./results\r
-cd ./results\r
-\r
-##-------------------------------Run ngdbuild---------------------------------------\r
-\r
-echo 'Running ngdbuild'\r
-ngdbuild -uc ../../example_design/gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.ngc gtxVirtex6FEE80_top.ngd\r
-\r
-#end run ngdbuild section\r
-\r
-##-------------------------------Run map-------------------------------------------\r
-\r
-echo 'Running map'\r
-map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd\r
-\r
-##-------------------------------Run par-------------------------------------------\r
-\r
-echo 'Running par'\r
-par mapped.ncd routed.ncd\r
-\r
-##---------------------------Report par results-------------------------------------\r
-\r
-echo 'Running design through bitgen'\r
-bitgen -w routed.ncd\r
-\r
-##-------------------------------Trace Report---------------------------------------\r
-\r
-echo 'Running trce'\r
-trce -e 10 routed.ncd mapped.pcf -o routed \r
-\r
-##-------------------------------Run netgen------------------------------------------\r
-\r
-echo 'Running netgen to create gate level VHDL model'\r
-netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd\r
-\r
-#Change directory to implement\r
-\r
-cd ..\r
-\r
+++ /dev/null
-\r
-REM\r
-REM ____ ____\r
-REM / /\/ /\r
-REM /___/ \ / Vendor: Xilinx\r
-REM \ \ \/ Version : 1.12\r
-REM \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-REM / / Filename : implement_synplify_bat.ejava\r
-REM /___/ /\ \r
-REM \ \ / \\r
-REM \___\/\___\\r
-REM\r
-REM\r
-REM implement_synplify.bat script\r
-REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-REM\r
-REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-REM \r
-REM This file contains confidential and proprietary information\r
-REM of Xilinx, Inc. and is protected under U.S. and \r
-REM international copyright and other intellectual property\r
-REM laws.\r
-REM \r
-REM DISCLAIMER\r
-REM This disclaimer is not a license and does not grant any\r
-REM rights to the materials distributed herewith. Except as\r
-REM otherwise provided in a valid license issued to you by\r
-REM Xilinx, and to the maximum extent permitted by applicable\r
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-REM (2) Xilinx shall not be liable (whether in contract or tort,\r
-REM including negligence, or under any other theory of\r
-REM liability) for any loss or damage of any kind or nature\r
-REM related to, arising under or in connection with these\r
-REM materials, including for any direct, or any indirect,\r
-REM special, incidental, or consequential loss or damage\r
-REM (including loss of data, profits, goodwill, or any type of\r
-REM loss or damage suffered as a result of any action brought\r
-REM by a third party) even if such damage or loss was\r
-REM reasonably foreseeable or Xilinx had been advised of the\r
-REM possibility of the same.\r
-REM\r
-REM CRITICAL APPLICATIONS\r
-REM Xilinx products are not designed or intended to be fail-\r
-REM safe, or for use in any application requiring fail-safe\r
-REM performance, such as life-support or safety devices or\r
-REM systems, Class III medical devices, nuclear facilities,\r
-REM applications related to the deployment of airbags, or any\r
-REM other applications that could lead to death, personal\r
-REM injury, or severe property or environmental damage\r
-REM (individually and collectively, "Critical\r
-REM Applications"). Customer assumes the sole risk and\r
-REM liability of any use of Xilinx products in Critical\r
-REM Applications, subject only to applicable laws and\r
-REM regulations governing limitations on product liability.\r
-REM\r
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-REM PART OF THIS FILE AT ALL TIMES.\r
-\r
-REM Set XST as default synthesizer\r
-\r
-REM Read command line arguments\r
-\r
-REM Change CWD to results\r
-\r
-REM Clean results directory\r
-REM Create results directory\r
-REM Change current directory to results\r
-ECHO WARNING: Removing existing results directory\r
-RMDIR /S /Q results\r
-MKDIR results\r
-COPY synplify.prj .\results\\r
-COPY *.ngc .\results\\r
-\r
-REM Run Synthesis\r
-\r
-ECHO "### Running Synplify Pro - "\r
-synplify_pro -batch synplify.prj\r
-\r
-COPY gtxVirtex6FEE80_top.edf .\results\r
-cd .\results\r
-\r
-REM Run ngdbuild\r
-\r
-ngdbuild -uc ..\..\example_design\gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.edf gtxVirtex6FEE80_top.ngd\r
-\r
-REM end run ngdbuild section\r
-\r
-REM Run map\r
-\r
-ECHO 'Running NGD'\r
-map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd\r
-\r
-REM Run par\r
-\r
-ECHO 'Running par'\r
-par mapped.ncd routed.ncd \r
-\r
-REM Report par results\r
-\r
-ECHO 'Running design through bitgen'\r
-bitgen -w routed.ncd\r
-\r
-REM Trace Report\r
-\r
-ECHO 'Running trce'\r
-trce -e 10 routed.ncd mapped.pcf -o routed\r
-\r
-REM Run netgen\r
-\r
-ECHO 'Running netgen to create gate level VHDL model'\r
-netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd\r
-\r
-REM Change directory to implement\r
-\r
-CD ..\r
-\r
+++ /dev/null
-#!/bin/bash\r
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : implement_synplify_sh.ejava \r
-## /___/ /\ \r
-## \ \ / \\r
-## \___\/\___\\r
-##\r
-##\r
-## implement_synplify.sh script \r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-#-----------------------------------------------------------------------------\r
-# Script to synthesize and implement the RTL provided for the GTX wizard\r
-#-----------------------------------------------------------------------------\r
-\r
-##---------------------Change CWD to results-------------------------------------\r
-\r
-#Clean results directory\r
-#Create results directory\r
-#Change current directory to results\r
-echo "WARNING: Removing existing results directory"\r
-rm -rf results\r
-mkdir results\r
-cp synplify.prj ./results\r
-cp *.ngc ./results\r
-\r
-##-----------------------------Run Synthesis-------------------------------------\r
-\r
-echo "### Running Synplify Pro - "\r
-synplify_pro -batch synplify.prj\r
-\r
-cp gtxVirtex6FEE80_top.edf ./results\r
-cd ./results\r
-\r
-##-------------------------------Run ngdbuild---------------------------------------\r
-\r
-echo 'Running ngdbuild'\r
-ngdbuild -uc ../../example_design/gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.edf gtxVirtex6FEE80_top.ngd\r
-\r
-#end run ngdbuild section\r
-\r
-##-------------------------------Run map-------------------------------------------\r
-\r
-echo 'Running map'\r
-map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd\r
-\r
-##-------------------------------Run par-------------------------------------------\r
-\r
-echo 'Running par'\r
-par mapped.ncd routed.ncd\r
-\r
-##---------------------------Report par results-------------------------------------\r
-\r
-echo 'Running design through bitgen'\r
-bitgen -w routed.ncd\r
-\r
-##-------------------------------Trace Report---------------------------------------\r
-\r
-echo 'Running trce'\r
-trce -e 10 routed.ncd mapped.pcf -o routed \r
-\r
-##-------------------------------Run netgen------------------------------------------\r
-\r
-echo 'Running netgen to create gate level VHDL model'\r
-netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd\r
-\r
-#Change directory to implement\r
-\r
-cd ..\r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : planAhead_ise.bat \r
-## /___/ /\ \r
-## \ \ / \\r
-## \___\/\___\\r
-##\r
-##\r
-## planAhead_ise.bat script \r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-##\r
-## planAhead_ise.bat script \r
-##\r
-################################################################################\r
-\r
-#-----------------------------------------------------------------------------\r
-# Command to run the planAhead in batch mode \r
-#-----------------------------------------------------------------------------\r
-planAhead -mode batch -source planAhead_ise.tcl\r
-#end\r
+++ /dev/null
-#!/bin/bash\r
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : planAhead_ise.sh \r
-## /___/ /\ \r
-## \ \ / \\r
-## \___\/\___\\r
-##\r
-##\r
-## planAhead_ise.sh script \r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-##\r
-##\r
-################################################################################\r
-\r
-#-----------------------------------------------------------------------------\r
-# Command to run the planAhead in batch mode \r
-#-----------------------------------------------------------------------------\r
-planAhead -mode batch -source ./planAhead_ise.tcl\r
-#end\r
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : planAhead_ise.tcl \r
-## /___/ /\ \r
-## \ \ / \\r
-## \___\/\___\\r
-##\r
-##\r
-## planAhead_ise.tcl script \r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-##\r
-##\r
-################################################################################\r
-\r
-## Environment Setup\r
-set projDir [file dirname [info script]]\r
-set projName gtxVirtex6FEE80\r
-set topName gtxVirtex6FEE80_top\r
-set device xc6vlx130t-ff484-3\r
-\r
-## if the project directory exists, delete it and create a new clean one\r
-if {[file exists $projDir/$projName]} {\r
-file delete -force $projDir/$projName\r
-}\r
-\r
-## Create Project\r
-create_project $projName $projDir/$projName -part $device\r
-\r
-## Project Option\r
-set_property design_mode RTL [get_filesets sources_1]\r
-\r
-## Source Files\r
-add_files -norecurse ../example_design/mgt_usrclk_source_mmcm.vhd\r
-add_files -norecurse ../example_design/gtxvirtex6fee80_tx_sync.vhd\r
-add_files -norecurse ../example_design/gtxvirtex6fee80_rx_sync.vhd\r
-add_files -norecurse ../example_design/double_reset.vhd\r
-add_files -norecurse ../example_design/frame_gen.vhd\r
-add_files -norecurse ../example_design/frame_check.vhd\r
-add_files -norecurse ../../gtxvirtex6fee80_gtx.vhd\r
-add_files -norecurse ../../gtxvirtex6fee80.vhd\r
-add_files -norecurse ../example_design/gtxvirtex6fee80_top.vhd\r
-\r
-## UCF Files\r
-import_files -fileset [get_filesets constrs_1] -force -norecurse ../example_design/gtxVirtex6FEE80_top.ucf\r
-import_files -fileset [get_filesets constrs_1] -force -norecurse ../example_design/gtx_attributes.ucf\r
-\r
-## NGC Files\r
-import_files -fileset [get_filesets sources_1] -force -norecurse ../implement/data_vio.ngc \r
-import_files -fileset [get_filesets sources_1] -force -norecurse ../implement/ila.ngc \r
-import_files -fileset [get_filesets sources_1] -force -norecurse ../implement/icon.ngc\r
- \r
- \r
-\r
-## Set the Top module\r
-set_property top $topName [get_property srcset [current_run]]\r
-\r
-## Run Synthesis\r
-launch_runs -runs synth_1\r
-wait_on_run synth_1\r
-\r
-## Run Implementation\r
-set_property strategy {ISE Defaults} [get_runs impl_1]\r
-\r
-\r
-#config_run -run impl_1 -program par -option -ol -value high\r
-\r
-launch_runs -runs impl_1\r
-wait_on_run impl_1\r
-\r
-## Run BitGen\r
-set_property add_step Bitgen [get_runs impl_1]\r
-launch_runs -runs impl_1\r
-wait_on_run impl_1\r
-\r
-exit\r
-## End\r
+++ /dev/null
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\ No newline at end of file
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : synplify.prj \r
-## /___/ /\ \r
-## \ \ / \\r
-## \___\/\___\\r
-##\r
-##\r
-## synplify.prj\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-add_file -vhdl "../example_design/mgt_usrclk_source_mmcm.vhd"\r
-add_file -vhdl "../example_design/gtxvirtex6fee80_tx_sync.vhd"\r
-add_file -vhdl "../example_design/gtxvirtex6fee80_rx_sync.vhd"\r
-add_file -vhdl "../example_design/double_reset.vhd"\r
-add_file -vhdl "../example_design/frame_gen.vhd"\r
-add_file -vhdl "../example_design/frame_check.vhd"\r
-add_file -vhdl "../../gtxvirtex6fee80_gtx.vhd"\r
-add_file -vhdl "../../gtxvirtex6fee80.vhd"\r
-add_file -vhdl "../example_design/gtxvirtex6fee80_top.vhd"\r
-\r
-add_file -constraint "../example_design/gtxvirtex6fee80_top.sdc"\r
-\r
-project -result_file "gtxvirtex6fee80_top.edf"\r
-set_option -top_module gtxVirtex6FEE80_top\r
-set_option -technology virtex6\r
-set_option -part xc6vlx130t\r
-set_option -package ff484\r
-set_option -speed_grade -3\r
-\r
-#compilation/mapping options\r
-set_option -default_enum_encoding default\r
-set_option -symbolic_fsm_compiler 1\r
-set_option -resource_sharing 1\r
-\r
-#map options\r
-set_option -frequency 160.000\r
-set_option -fanout_limit 100\r
-set_option -disable_io_insertion 0\r
-set_option -pipe 0\r
-set_option -retiming 0\r
-\r
-#simulation options\r
-set_option -write_verilog 0\r
-set_option -write_vhdl 0\r
-set_option -vlog_std v2001\r
-\r
-#Do not generate ncf constraints file\r
-set_option -write_apr_constraint 0\r
-\r
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
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\ No newline at end of file
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : xst.prj \r
-## /___/ /\ \r
-## \ \ / \\r
-## \___\/\___\\r
-##\r
-##\r
-## xst.prj\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-vhdl work "../example_design/mgt_usrclk_source_mmcm.vhd"\r
-vhdl work "../example_design/gtxvirtex6fee80_tx_sync.vhd"\r
-vhdl work "../example_design/gtxvirtex6fee80_rx_sync.vhd"\r
-vhdl work "../example_design/double_reset.vhd"\r
-vhdl work "../example_design/frame_gen.vhd"\r
-vhdl work "../example_design/frame_check.vhd"\r
-vhdl work "../../gtxvirtex6fee80_gtx.vhd"\r
-vhdl work "../../gtxvirtex6fee80.vhd"\r
-vhdl work "../example_design/gtxvirtex6fee80_top.vhd"\r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : xst.scr \r
-## /___/ /\ \r
-## \ \ / \\r
-## \___\/\___\\r
-##\r
-##\r
-## xst.scr \r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-run\r
--ifn xst.prj\r
--ifmt mixed \r
--ofn gtxVirtex6FEE80_top.ngc \r
--ofmt NGC\r
--p xc6vlx130t-3ff484\r
--top gtxVirtex6FEE80_top\r
--opt_mode Speed\r
--opt_level 1\r
--iuc NO\r
--keep_hierarchy NO\r
--glob_opt AllClockNets\r
--rtlview Yes\r
--read_cores YES\r
--write_timing_constraints NO\r
--cross_clock_analysis NO\r
--hierarchy_separator /\r
--bus_delimiter ()\r
--case maintain\r
--slice_utilization_ratio 100\r
--fsm_extract YES\r
--fsm_encoding Auto\r
--ram_extract No\r
--ram_style Auto\r
--rom_extract No\r
--rom_style Auto\r
--shreg_extract YES\r
--resource_sharing YES\r
--mult_style auto\r
--iobuf YES\r
--max_fanout REDUCE\r
--bufg 16\r
--register_duplication YES\r
--signal_encoding user\r
--iob true\r
--slice_utilization_ratio_maxmargin 5\r
--uc ../example_design/gtxVirtex6FEE80_top.xcf\r
+++ /dev/null
---------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : demo_tb.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\ \r
---\r
---\r
--- Module DEMO_TB\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard \r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-library std; -- for Printing\r
-use std.textio.all;\r
-\r
-entity DEMO_TB is\r
-end DEMO_TB;\r
-\r
-architecture RTL of DEMO_TB is\r
-\r
---*************************Parameter Declarations******************************\r
-\r
- constant TX_REFCLK_PERIOD : time := 12.5 ns;\r
- constant RX_REFCLK_PERIOD : time := 12.5 ns; \r
- \r
---**************************** Component Declarations *************************\r
-\r
- component gtxVirtex6FEE80_top \r
- generic\r
- (\r
- EXAMPLE_CONFIG_INDEPENDENT_LANES: integer := 1;\r
- EXAMPLE_LANE_WITH_START_CHAR : integer := 0;\r
- EXAMPLE_WORDS_IN_BRAM : integer := 512;\r
- EXAMPLE_SIM_GTXRESET_SPEEDUP : integer := 1;\r
- EXAMPLE_USE_CHIPSCOPE : integer := 0 --0 - drive resets from top level ports\r
- );\r
- port\r
- (\r
- Q3_CLK0_MGTREFCLK_PAD_N_IN : in std_logic;\r
- Q3_CLK0_MGTREFCLK_PAD_P_IN : in std_logic;\r
- GTXTXRESET_IN : in std_logic;\r
- GTXRXRESET_IN : in std_logic;\r
- TRACK_DATA_OUT : out std_logic;\r
- RXN_IN : in std_logic;\r
- RXP_IN : in std_logic;\r
- TXN_OUT : out std_logic;\r
- TXP_OUT : out std_logic\r
- );\r
- end component;\r
-\r
- component SIM_RESET_MGT_MODEL \r
- port \r
- (\r
- GSR_IN : in std_logic\r
- );\r
- end component;\r
-\r
---************************Internal Register Declarations***********************\r
-\r
---************************** Register Declarations **************************** \r
-\r
- signal tx_refclk_n_r : std_logic;\r
- signal rx_refclk_n_r : std_logic;\r
- signal drp_clk_r : std_logic;\r
- signal tx_usrclk_r : std_logic;\r
- signal rx_usrclk_r : std_logic;\r
- signal gsr_r : std_logic;\r
- signal gts_r : std_logic;\r
- signal reset_i : std_logic;\r
- signal track_data_high_r : std_logic;\r
- signal track_data_low_r : std_logic; \r
-\r
---********************************Wire Declarations**********************************\r
- \r
- ----------------------------------- Global Signals ------------------------------\r
- signal tx_refclk_p_r : std_logic;\r
- signal rx_refclk_p_r : std_logic; \r
- signal tied_to_ground_i : std_logic;\r
- ---------------------------- Example Module Connections -------------------------\r
- signal rxn_in_i : std_logic;\r
- signal rxp_in_i : std_logic;\r
- signal txn_out_i : std_logic;\r
- signal txp_out_i : std_logic;\r
-\r
-\r
- signal gtx0_txplllkdet_i : std_logic;\r
- signal gtx0_rxplllkdet_i : std_logic; \r
-\r
- signal track_data_i : std_logic;\r
-\r
-\r
---*********************************Main Body of Code**********************************\r
-begin\r
-\r
- -- ------------------------------- Tie offs ------------------------------- \r
- \r
- tied_to_ground_i <= '0';\r
- \r
- -- ------------------------- MGT Serial Connections -----------------------\r
-\r
- rxn_in_i <= txn_out_i;\r
- rxp_in_i <= txp_out_i; \r
-\r
- ------- Instantiate the ROC module for resetting the VHDL MGT Smart Model ------\r
- ------- Instantiate SIM_RESET_MGT_MODEL module only for Functional simulation ------\r
- ------- For Timing simulation please comment out the instance of SIM_RESET_MGT_MODEL ------\r
-\r
- sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL \r
- port map \r
- (\r
- GSR_IN => reset_i\r
- );\r
-\r
- ---------------------- Generate Reference Clock input --------------------\r
- \r
- process\r
- begin\r
- tx_refclk_n_r <= '1';\r
- wait for TX_REFCLK_PERIOD/2;\r
- tx_refclk_n_r <= '0';\r
- wait for TX_REFCLK_PERIOD/2;\r
- end process;\r
-\r
- tx_refclk_p_r <= not tx_refclk_n_r;\r
- \r
- process\r
- begin\r
- rx_refclk_n_r <= '1';\r
- wait for RX_REFCLK_PERIOD/2;\r
- rx_refclk_n_r <= '0';\r
- wait for RX_REFCLK_PERIOD/2;\r
- end process;\r
-\r
- rx_refclk_p_r <= not rx_refclk_n_r;\r
- \r
-\r
- \r
- \r
- ----------------------------------- Resets ---------------------------------\r
- \r
- process\r
- begin\r
- reset_i <= '1';\r
- wait for 100 ns;\r
- reset_i <= '0';\r
- wait; \r
- end process;\r
-\r
- -------------------------------- Track Data --------------------------------\r
- \r
- process\r
-\r
- procedure tbprint (message : in string) is\r
- variable outline : line;\r
- begin\r
- write(outline, string'("## Time: "));\r
- write(outline, NOW, RIGHT, 0, ps);\r
- write(outline, string'(" "));\r
- write(outline, string'(message)); \r
- writeline(output,outline);\r
- end tbprint;\r
-\r
-\r
- begin\r
- track_data_high_r <= '0';\r
- wait for 223 us;\r
- if (track_data_i = '1') then\r
- track_data_high_r <= '1';\r
- end if;\r
- wait for 2 us;\r
- if ((track_data_high_r = '1') and (track_data_low_r = '0')) then\r
- tbprint("------- TEST PASSED -------");\r
- assert false report "Simulation Stopped." severity failure;\r
- else\r
- tbprint("####### ERROR: TEST FAILED ! #######");\r
- assert false report "Test Failed." severity failure;\r
- end if;\r
- end process;\r
- \r
- process\r
- begin\r
- track_data_low_r <= '0';\r
- wait for 223 us;\r
- wait until track_data_i = '0';\r
- track_data_low_r <= '1';\r
- end process; \r
- ------------------- Instantiate an gtxVirtex6FEE80_top module -----------------\r
-\r
- gtxVirtex6FEE80_top_i : gtxVirtex6FEE80_top\r
- generic map\r
- (\r
- EXAMPLE_SIM_GTXRESET_SPEEDUP=> 1, -- Speedup is turned on for simulation\r
- EXAMPLE_USE_CHIPSCOPE => 0 --1 - use chipscope to drive resets,\r
- --0 - drive resets from top level ports\r
- )\r
- port map\r
- (\r
- Q3_CLK0_MGTREFCLK_PAD_N_IN => rx_refclk_n_r,\r
- Q3_CLK0_MGTREFCLK_PAD_P_IN => rx_refclk_p_r,\r
- GTXTXRESET_IN => reset_i,\r
- GTXRXRESET_IN => reset_i,\r
- TRACK_DATA_OUT => track_data_i,\r
- RXN_IN => rxn_in_i,\r
- RXP_IN => rxp_in_i,\r
- TXN_OUT => txn_out_i,\r
- TXP_OUT => txp_out_i\r
- );\r
-\r
-end RTL;\r
-\r
+++ /dev/null
---------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : demo_tb.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\ \r
---\r
---\r
--- Module DEMO_TB_IMP\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard \r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-library std; -- for Printing\r
-use std.textio.all;\r
-\r
-entity DEMO_TB_IMP is\r
-end DEMO_TB_IMP;\r
-\r
-architecture RTL of DEMO_TB_IMP is\r
-\r
---*************************Parameter Declarations******************************\r
-\r
- constant TX_REFCLK_PERIOD : time := 12.5 ns;\r
- constant RX_REFCLK_PERIOD : time := 12.5 ns; \r
- \r
---**************************** Component Declarations *************************\r
-\r
- component gtxVirtex6FEE80_top \r
- port\r
- (\r
- Q3_CLK0_MGTREFCLK_PAD_N_IN : in std_logic;\r
- Q3_CLK0_MGTREFCLK_PAD_P_IN : in std_logic;\r
- GTXTXRESET_IN : in std_logic;\r
- GTXRXRESET_IN : in std_logic;\r
- TRACK_DATA_OUT : out std_logic;\r
- RXN_IN : in std_logic;\r
- RXP_IN : in std_logic;\r
- TXN_OUT : out std_logic;\r
- TXP_OUT : out std_logic\r
- );\r
- end component;\r
-\r
- component SIM_RESET_MGT_MODEL \r
- port \r
- (\r
- GSR_IN : in std_logic\r
- );\r
- end component;\r
-\r
---************************Internal Register Declarations***********************\r
-\r
---************************** Register Declarations **************************** \r
-\r
- signal tx_refclk_n_r : std_logic;\r
- signal rx_refclk_n_r : std_logic;\r
- signal drp_clk_r : std_logic;\r
- signal tx_usrclk_r : std_logic;\r
- signal rx_usrclk_r : std_logic;\r
- signal gsr_r : std_logic;\r
- signal gts_r : std_logic;\r
- signal reset_i : std_logic;\r
- signal track_data_high_r : std_logic;\r
- signal track_data_low_r : std_logic; \r
-\r
---********************************Wire Declarations**********************************\r
- \r
- ----------------------------------- Global Signals ------------------------------\r
- signal tx_refclk_p_r : std_logic;\r
- signal rx_refclk_p_r : std_logic; \r
- signal tied_to_ground_i : std_logic;\r
- ---------------------------- Example Module Connections -------------------------\r
- signal rxn_in_i : std_logic;\r
- signal rxp_in_i : std_logic;\r
- signal txn_out_i : std_logic;\r
- signal txp_out_i : std_logic;\r
-\r
-\r
- signal gtx0_txplllkdet_i : std_logic;\r
- signal gtx0_rxplllkdet_i : std_logic; \r
-\r
- signal track_data_i : std_logic;\r
-\r
-\r
---*********************************Main Body of Code**********************************\r
-begin\r
-\r
- -- ------------------------------- Tie offs ------------------------------- \r
- \r
- tied_to_ground_i <= '0';\r
- \r
- -- ------------------------- MGT Serial Connections -----------------------\r
-\r
- rxn_in_i <= txn_out_i;\r
- rxp_in_i <= txp_out_i; \r
-\r
- ------- Instantiate the ROC module for resetting the VHDL MGT Smart Model ------\r
- ------- Instantiate SIM_RESET_MGT_MODEL module only for Functional simulation ------\r
- ------- For Timing simulation please comment out the instance of SIM_RESET_MGT_MODEL ------\r
-\r
- sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL \r
- port map \r
- (\r
- GSR_IN => reset_i\r
- );\r
-\r
- ---------------------- Generate Reference Clock input --------------------\r
- \r
- process\r
- begin\r
- tx_refclk_n_r <= '1';\r
- wait for TX_REFCLK_PERIOD/2;\r
- tx_refclk_n_r <= '0';\r
- wait for TX_REFCLK_PERIOD/2;\r
- end process;\r
-\r
- tx_refclk_p_r <= not tx_refclk_n_r;\r
- \r
- process\r
- begin\r
- rx_refclk_n_r <= '1';\r
- wait for RX_REFCLK_PERIOD/2;\r
- rx_refclk_n_r <= '0';\r
- wait for RX_REFCLK_PERIOD/2;\r
- end process;\r
-\r
- rx_refclk_p_r <= not rx_refclk_n_r;\r
- \r
-\r
- \r
- \r
- ----------------------------------- Resets ---------------------------------\r
- \r
- process\r
- begin\r
- reset_i <= '1';\r
- wait for 100 ns;\r
- reset_i <= '0';\r
- wait; \r
- end process;\r
-\r
- -------------------------------- Track Data --------------------------------\r
- \r
- process\r
-\r
- procedure tbprint (message : in string) is\r
- variable outline : line;\r
- begin\r
- write(outline, string'("## Time: "));\r
- write(outline, NOW, RIGHT, 0, ps);\r
- write(outline, string'(" "));\r
- write(outline, string'(message)); \r
- writeline(output,outline);\r
- end tbprint;\r
-\r
- begin\r
- track_data_high_r <= '0';\r
- wait for 223 us;\r
- if (track_data_i = '1') then\r
- track_data_high_r <= '1';\r
- end if;\r
- wait for 2 us;\r
- if ((track_data_high_r = '1') and (track_data_low_r = '0')) then\r
- tbprint("------- TEST PASSED -------");\r
- assert false report "Simulation Stopped." severity failure;\r
- else\r
- tbprint("####### ERROR: TEST FAILED ! #######");\r
- assert false report "Test Failed." severity failure;\r
- end if;\r
- end process;\r
- \r
- process\r
- begin\r
- track_data_low_r <= '0';\r
- wait for 223 us;\r
- wait until track_data_i = '0';\r
- track_data_low_r <= '1';\r
- end process; \r
- ------------------- Instantiate an gtxVirtex6FEE80_top module -----------------\r
-\r
- gtxVirtex6FEE80_top_i : gtxVirtex6FEE80_top\r
- port map\r
- (\r
- Q3_CLK0_MGTREFCLK_PAD_N_IN => rx_refclk_n_r,\r
- Q3_CLK0_MGTREFCLK_PAD_P_IN => rx_refclk_p_r,\r
- GTXTXRESET_IN => reset_i,\r
- GTXRXRESET_IN => reset_i,\r
- TRACK_DATA_OUT => track_data_i,\r
- RXN_IN => rxn_in_i,\r
- RXP_IN => rxp_in_i,\r
- TXN_OUT => txn_out_i,\r
- TXP_OUT => txp_out_i\r
- );\r
-\r
-end RTL;\r
-\r
+++ /dev/null
-REM ____ ____ \r
-REM / /\/ / \r
-REM /___/ \ / Vendor: Xilinx \r
-REM \ \ \/ Version : 1.12\r
-REM \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-REM / / Filename : simulate_isim.bat\r
-REM /___/ /\ \r
-REM \ \ / \ \r
-REM \___\/\___\ \r
-REM\r
-REM\r
-REM Script SIMULATE_ISIM.BAT\r
-REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-REM\r
-REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-REM\r
-REM This file contains confidential and proprietary information\r
-REM of Xilinx, Inc. and is protected under U.S. and\r
-REM international copyright and other intellectual property\r
-REM laws.\r
-REM\r
-REM DISCLAIMER\r
-REM This disclaimer is not a license and does not grant any\r
-REM rights to the materials distributed herewith. Except as\r
-REM otherwise provided in a valid license issued to you by\r
-REM Xilinx, and to the maximum extent permitted by applicable\r
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-REM (2) Xilinx shall not be liable (whether in contract or tort,\r
-REM including negligence, or under any other theory of\r
-REM liability) for any loss or damage of any kind or nature\r
-REM related to, arising under or in connection with these\r
-REM materials, including for any direct, or any indirect,\r
-REM special, incidental, or consequential loss or damage\r
-REM (including loss of data, profits, goodwill, or any type of\r
-REM loss or damage suffered as a result of any action brought\r
-REM by a third party) even if such damage or loss was\r
-REM reasonably foreseeable or Xilinx had been advised of the\r
-REM possibility of the same.\r
-REM\r
-REM CRITICAL APPLICATIONS\r
-REM Xilinx products are not designed or intended to be fail-\r
-REM safe, or for use in any application requiring fail-safe\r
-REM performance, such as life-support or safety devices or\r
-REM systems, Class III medical devices, nuclear facilities,\r
-REM applications related to the deployment of airbags, or any\r
-REM other applications that could lead to death, personal\r
-REM injury, or severe property or environmental damage\r
-REM (individually and collectively, "Critical\r
-REM Applications"). Customer assumes the sole risk and\r
-REM liability of any use of Xilinx products in Critical\r
-REM Applications, subject only to applicable laws and\r
-REM regulations governing limitations on product liability.\r
-REM \r
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-REM PART OF THIS FILE AT ALL TIMES.\r
-\r
-\r
-REM ***************************** Beginning of Script ***************************\r
- \r
-REM Create and map work directory\r
-mkdir work\r
-\r
-REM MGT Wrapper\r
-vhpcomp -work work ..\..\..\gtxvirtex6fee80_gtx.vhd\r
-vhpcomp -work work ..\..\..\gtxvirtex6fee80.vhd\r
-\r
-\r
-REM Clock Modules \r
-vhpcomp -work work ..\..\example_design\mgt_usrclk_source_mmcm.vhd\r
-\r
-REM Example Design modules\r
-vhpcomp -work work ..\..\example_design\gtxvirtex6fee80_tx_sync.vhd\r
-vhpcomp -work work ..\..\example_design\gtxvirtex6fee80_rx_sync.vhd\r
-vhpcomp -work work ..\..\example_design\double_reset.vhd\r
-vhpcomp -work work ..\..\example_design\frame_gen.vhd\r
-vhpcomp -work work ..\..\example_design\frame_check.vhd\r
-vhpcomp -work work ..\..\example_design\gtxvirtex6fee80_top.vhd\r
-\r
-vhpcomp -work work ..\demo_tb.vhd\r
-\r
-REM Other modules\r
-vhpcomp -work work ..\sim_reset_mgt_model.vhd\r
-\r
-REM Load Design\r
-fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe\r
-\r
-.\demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim \r
-\r
+++ /dev/null
-#!/bin/sh\r
-################################################################################\r
-## ____ ____ \r
-## / /\/ / \r
-## /___/ \ / Vendor: Xilinx \r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : simulate_isim.sh\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\ \r
-##\r
-##\r
-## Script SIMULATE_ISIM.SH\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-\r
-##***************************** Beginning of Script ***************************\r
- \r
-## Create and map work directory\r
-mkdir work\r
-\r
-##MGT Wrapper\r
-vhpcomp -work work ../../../gtxvirtex6fee80_gtx.vhd;\r
-vhpcomp -work work ../../../gtxvirtex6fee80.vhd;\r
-\r
-\r
-##Clock Modules \r
-vhpcomp -work work ../../example_design/mgt_usrclk_source_mmcm.vhd;\r
-\r
-##Example Design modules\r
-vhpcomp -work work ../../example_design/gtxvirtex6fee80_tx_sync.vhd;\r
-vhpcomp -work work ../../example_design/gtxvirtex6fee80_rx_sync.vhd;\r
-vhpcomp -work work ../../example_design/double_reset.vhd;\r
-vhpcomp -work work ../../example_design/frame_gen.vhd;\r
-vhpcomp -work work ../../example_design/frame_check.vhd;\r
-vhpcomp -work work ../../example_design/gtxvirtex6fee80_top.vhd;\r
-\r
-vhpcomp -work work ../demo_tb.vhd;\r
-\r
-##Other modules\r
-vhpcomp -work work ../sim_reset_mgt_model.vhd;\r
-\r
-##Load Design\r
-fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe\r
-\r
-./demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim \r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____ \r
-## / /\/ / \r
-## /___/ \ / Vendor: Xilinx \r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : simulate_mti.do\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\ \r
-##\r
-##\r
-## Script SIMULATE_MTI.DO\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-##***************************** Beginning of Script ***************************\r
- \r
-## If MTI_LIBS is defined, map unisim and simprim directories using MTI_LIBS\r
-## This mode of mapping the unisims libraries is provided for backward \r
-## compatibility with previous wizard releases. If you don't set MTI_LIBS\r
-## the unisim libraries will be loaded from the paths set up by compxlib in\r
-## your modelsim.ini file\r
-\r
-set XILINX $env(XILINX)\r
-if [info exists env(MTI_LIBS)] { \r
- set MTI_LIBS $env(MTI_LIBS)\r
- vlib UNISIM\r
- vlib SECUREIP\r
- vmap UNISIM $MTI_LIBS/unisim\r
- vmap SECUREIP $MTI_LIBS/secureip\r
- \r
-}\r
- \r
-\r
-## Create and map work directory\r
-vlib work\r
-vmap work work\r
-\r
-##MGT Wrapper\r
-vcom -93 -work work ../../../gtxvirtex6fee80_gtx.vhd;\r
-vcom -93 -work work ../../../gtxvirtex6fee80.vhd;\r
-\r
-\r
-##Clock Modules \r
-vcom -93 -work work ../../example_design/mgt_usrclk_source_mmcm.vhd;\r
-\r
-\r
-##Example Design modules\r
-vcom -93 -work work ../../example_design/gtxvirtex6fee80_tx_sync.vhd;\r
-vcom -93 -work work ../../example_design/gtxvirtex6fee80_rx_sync.vhd;\r
-vcom -93 -work work ../../example_design/double_reset.vhd;\r
-vcom -93 -work work ../../example_design/frame_gen.vhd;\r
-vcom -93 -work work ../../example_design/frame_check.vhd;\r
-vcom -93 -work work ../../example_design/gtxvirtex6fee80_top.vhd;\r
-\r
-vcom -93 -work work ../demo_tb.vhd;\r
-\r
-##Other modules\r
-vcom -93 -work work ../sim_reset_mgt_model.vhd;\r
-\r
-##Load Design\r
-vsim -t 1ps work.DEMO_TB -voptargs="+acc" \r
-\r
-\r
-##Load signals in wave window\r
-view wave\r
-do wave_mti.do\r
-\r
-##Run simulation\r
-run 226 us\r
-\r
-\r
-\r
+++ /dev/null
-REM ############################################################################\r
-REM ____ ____ \r
-REM / /\/ / \r
-REM /___/ \ / Vendor: Xilinx \r
-REM \ \ \/ Version : 1.12\r
-REM \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-REM / / Filename : simulate_ncsim.bat\r
-REM /___/ /\ \r
-REM \ \ / \ \r
-REM \___\/\___\ \r
-REM\r
-REM\r
-REM Script SIMULATE_NCSIM.BAT\r
-REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-REM\r
-REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-REM \r
-REM This file contains confidential and proprietary information\r
-REM of Xilinx, Inc. and is protected under U.S. and \r
-REM international copyright and other intellectual property\r
-REM laws.\r
-REM \r
-REM DISCLAIMER\r
-REM This disclaimer is not a license and does not grant any\r
-REM rights to the materials distributed herewith. Except as\r
-REM otherwise provided in a valid license issued to you by\r
-REM Xilinx, and to the maximum extent permitted by applicable\r
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-REM (2) Xilinx shall not be liable (whether in contract or tort,\r
-REM including negligence, or under any other theory of\r
-REM liability) for any loss or damage of any kind or nature\r
-REM related to, arising under or in connection with these\r
-REM materials, including for any direct, or any indirect,\r
-REM special, incidental, or consequential loss or damage\r
-REM (including loss of data, profits, goodwill, or any type of\r
-REM loss or damage suffered as a result of any action brought\r
-REM by a third party) even if such damage or loss was\r
-REM reasonably foreseeable or Xilinx had been advised of the\r
-REM possibility of the same.\r
-REM\r
-REM CRITICAL APPLICATIONS\r
-REM Xilinx products are not designed or intended to be fail-\r
-REM safe, or for use in any application requiring fail-safe\r
-REM performance, such as life-support or safety devices or\r
-REM systems, Class III medical devices, nuclear facilities,\r
-REM applications related to the deployment of airbags, or any\r
-REM other applications that could lead to death, personal\r
-REM injury, or severe property or environmental damage\r
-REM (individually and collectively, "Critical\r
-REM Applications"). Customer assumes the sole risk and\r
-REM liability of any use of Xilinx products in Critical\r
-REM Applications, subject only to applicable laws and\r
-REM regulations governing limitations on product liability.\r
-REM\r
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-REM PART OF THIS FILE AT ALL TIMES.\r
-\r
-REM **************************** Beginning of Script ***************************\r
-\r
- \r
-REM Ensure the follwoing\r
-REM The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,\r
-REM UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.\r
-REM Variables LMC_HOME and XILINX are set \r
-REM Define the mapping for the work library in cds.lib file. DEFINE work ./work\r
-\r
-mkdir work\r
-REM MGT Wrapper\r
-ncvhdl -RELAX -V93 -work work ..\..\..\gtxvirtex6fee80_gtx.vhd\r
-ncvhdl -RELAX -V93 -work work ..\..\..\gtxvirtex6fee80.vhd\r
-\r
-\r
- \r
-REM Clock Modules \r
-ncvhdl -RELAX -V93 -work work ..\..\example_design\mgt_usrclk_source_mmcm.vhd\r
-\r
-REM Example Design modules\r
-ncvhdl -RELAX -V93 -work work ..\..\example_design\gtxvirtex6fee80_tx_sync.vhd\r
-ncvhdl -RELAX -V93 -work work ..\..\example_design\gtxvirtex6fee80_rx_sync.vhd\r
-ncvhdl -RELAX -V93 -work work ..\..\example_design\double_reset.vhd\r
-ncvhdl -RELAX -V93 -work work ..\..\example_design\frame_gen.vhd\r
-ncvhdl -RELAX -V93 -work work ..\..\example_design\frame_check.vhd\r
-ncvhdl -RELAX -V93 -work work ..\..\example_design\gtxvirtex6fee80_top.vhd\r
-\r
-ncvhdl -RELAX -V93 -work work ..\demo_tb.vhd\r
-\r
-REM Other modules\r
-ncvhdl -RELAX -V93 -work work ..\sim_reset_mgt_model.vhd\r
-\r
-REM Elaborate Design\r
-ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB\r
-\r
-ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv" \r
-\r
+++ /dev/null
-#!/bin/sh\r
-################################################################################\r
-## ____ ____ \r
-## / /\/ / \r
-## /___/ \ / Vendor: Xilinx \r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : simulate_ncsim.sh\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\ \r
-##\r
-##\r
-## Script SIMULATE_NCSIM.SH\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-##***************************** Beginning of Script ***************************\r
- \r
-#Ensure the follwoing\r
-#The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,\r
-#UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.\r
-#Variables LMC_HOME and XILINX are set \r
-#Define the mapping for the work library in cds.lib file. DEFINE work ./work\r
-\r
-mkdir work\r
-##MGT Wrapper\r
-ncvhdl -RELAX -V93 -work work ../../../gtxvirtex6fee80_gtx.vhd;\r
-ncvhdl -RELAX -V93 -work work ../../../gtxvirtex6fee80.vhd;\r
-\r
-\r
- \r
-##Clock Modules \r
-ncvhdl -RELAX -V93 -work work ../../example_design/mgt_usrclk_source_mmcm.vhd;\r
-\r
-##Example Design modules\r
-ncvhdl -RELAX -V93 -work work ../../example_design/gtxvirtex6fee80_tx_sync.vhd;\r
-ncvhdl -RELAX -V93 -work work ../../example_design/gtxvirtex6fee80_rx_sync.vhd;\r
-ncvhdl -RELAX -V93 -work work ../../example_design/double_reset.vhd;\r
-ncvhdl -RELAX -V93 -work work ../../example_design/frame_gen.vhd;\r
-ncvhdl -RELAX -V93 -work work ../../example_design/frame_check.vhd;\r
-ncvhdl -RELAX -V93 -work work ../../example_design/gtxvirtex6fee80_top.vhd;\r
-\r
-ncvhdl -RELAX -V93 -work work ../demo_tb.vhd;\r
-\r
-##Other modules\r
-ncvhdl -RELAX -V93 -work work ../sim_reset_mgt_model.vhd;\r
-\r
-##Elaborate Design\r
-ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB\r
-\r
-ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv" \r
-\r
+++ /dev/null
-#!/bin/sh\r
-################################################################################\r
-## ____ ____ \r
-## / /\/ / \r
-## /___/ \ / Vendor: Xilinx \r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : simulate_vcs.sh\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\ \r
-##\r
-##\r
-## Script SIMULATE_VCS.SH\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## \r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-## \r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-## \r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-##***************************** Beginning of Script ***************************\r
-\r
-\r
-rm -rf simv* csrc DVEfiles AN.DB\r
-\r
-vhdlan \\r
- ../../../gtxvirtex6fee80_gtx.vhd \\r
- ../../../gtxvirtex6fee80.vhd \\r
- ../../example_design/mgt_usrclk_source_mmcm.vhd \\r
- ../../example_design/gtxvirtex6fee80_tx_sync.vhd \\r
- ../../example_design/gtxvirtex6fee80_rx_sync.vhd \\r
- ../../example_design/double_reset.vhd \\r
- ../../example_design/frame_gen.vhd \\r
- ../../example_design/frame_check.vhd \\r
- ../../example_design/gtxvirtex6fee80_top.vhd \\r
- ../demo_tb.vhd\r
-\r
-vcs +vcs+lic+wait \\r
- -debug \\r
- DEMO_TB\r
-./simv -ucli -i ucli_commands.key\r
-dve -vpd vcdplus.vpd -session vcs_session.tcl\r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____ \r
-## / /\/ / \r
-## /___/ \ / Vendor: Xilinx \r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : ucli_commands.key\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\ \r
-##\r
-##\r
-## Script UCLI_COMMANDS.KEY\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-## \r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-## \r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-## \r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-call {$vcdpluson}\r
-run\r
-call {$vcdplusclose}\r
-quit\r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____ \r
-## / /\/ / \r
-## /___/ \ / Vendor: Xilinx \r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : vcs_session.tcl\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\ \r
-##\r
-##\r
-##\r
-## Script VCS_SESSION.TCL\r
-## Generated by Xilinx Virtex-6 FPGA GTH Transceiver Wizard\r
-##\r
-## \r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-## \r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-## \r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
- gui_open_window Wave\r
- gui_sg_create gtxVirtex6FEE80_Group\r
- gui_list_add_group -id Wave.1 {gtxVirtex6FEE80_Group}\r
-\r
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{FRAME_CHECK_MODULE}} -divider\r
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:begin_r}\r
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:track_data_r}\r
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:data_error_detected_r}\r
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:start_of_packet_detected_r}\r
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:RX_DATA}\r
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:ERROR_COUNT}\r
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{GTX0_GTXVIRTEX6FEE80}} -divider\r
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - 8b10b Decoder}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCHARISK_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDISPERR_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXNOTINTABLE_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - Comma Detection and Alignment}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENMCOMMAALIGN_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPCOMMAALIGN_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Data Path interface}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDATA_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRECCLK_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESET_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXUSRCLK2_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCDRRESET_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXN_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXP_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Elastic Buffer and Phase Alignment Ports}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNDISABLE_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONENB_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONITOR_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNOVERRIDE_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNRESET_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPMAPHASEALIGN_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPMASETPHASE_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXSTATUS_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Loss-of-sync State Machine}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXLOSSOFSYNC_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX PLL Ports}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXRXRESET_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:MGTREFCLKRX_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PLLRXRESET_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPLLLKDET_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESETDONE_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Pipe Control for PCI Express}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PHYSTATUS_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - 8b10b Encoder Control Ports}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXCHARISK_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - GTX Ports}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTEST_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX Data Path interface}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDATA_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXOUTCLK_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESET_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXUSRCLK2_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX Driver and OOB signaling}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXN_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXP_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX Elastic Buffer and Phase Alignment Ports}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNDISABLE_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONENB_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONITOR_OUT}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNRESET_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXENPMAPHASEALIGN_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXPMASETPHASE_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX PLL Ports}} -divider
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTXRESET_IN}
- gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESETDONE_OUT}
-\r
-\r
- gui_zoom -window Wave.1 -full\r
-\r
+++ /dev/null
-###############################################################################\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-\r
-\r
-wcfg new\r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/begin_r\r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/track_data_r\r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/data_error_detected_r\r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/start_of_packet_detected_r\r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/RX_DATA\r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/ERROR_COUNT\r
-divider add "Receive Ports - 8b10b Decoder"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCHARISK_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDISPERR_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXNOTINTABLE_OUT
-divider add "Receive Ports - Comma Detection and Alignment"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENMCOMMAALIGN_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPCOMMAALIGN_IN
-divider add "Receive Ports - RX Data Path interface"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDATA_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRECCLK_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXUSRCLK2_IN
-divider add "Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCDRRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXN_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXP_IN
-divider add "Receive Ports - RX Elastic Buffer and Phase Alignment Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNDISABLE_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONENB_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONITOR_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNOVERRIDE_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPMAPHASEALIGN_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPMASETPHASE_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXSTATUS_OUT
-divider add "Receive Ports - RX Loss-of-sync State Machine"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXLOSSOFSYNC_OUT
-divider add "Receive Ports - RX PLL Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXRXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/MGTREFCLKRX_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PLLRXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPLLLKDET_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESETDONE_OUT
-divider add "Receive Ports - RX Pipe Control for PCI Express"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PHYSTATUS_OUT
-divider add "Transmit Ports - 8b10b Encoder Control Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXCHARISK_IN
-divider add "Transmit Ports - GTX Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTEST_IN
-divider add "Transmit Ports - TX Data Path interface"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDATA_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXOUTCLK_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXUSRCLK2_IN
-divider add "Transmit Ports - TX Driver and OOB signaling"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXN_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXP_OUT
-divider add "Transmit Ports - TX Elastic Buffer and Phase Alignment Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNDISABLE_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONENB_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONITOR_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXENPMAPHASEALIGN_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXPMASETPHASE_IN
-divider add "Transmit Ports - TX PLL Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESETDONE_OUT
-\r
-run 226 us\r
-quit\r
-\r
-\r
-\r
+++ /dev/null
-###############################################################################\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-onerror {resume}\r
-quietly WaveActivateNextPane {} 0\r
-add wave -noupdate -divider {FRAME CHECK MODULE gtx0_frame_check }\r
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/begin_r\r
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/track_data_r\r
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/data_error_detected_r\r
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/start_of_packet_detected_r\r
-add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/RX_DATA\r
-add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/ERROR_COUNT\r
-add wave -noupdate -divider {GTX0_GTXVIRTEX6FEE80 }\r
-add wave -noupdate -divider {Receive Ports - 8b10b Decoder }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCHARISK_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDISPERR_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXNOTINTABLE_OUT
-add wave -noupdate -divider {Receive Ports - Comma Detection and Alignment }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENMCOMMAALIGN_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPCOMMAALIGN_IN
-add wave -noupdate -divider {Receive Ports - RX Data Path interface }
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDATA_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRECCLK_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXUSRCLK2_IN
-add wave -noupdate -divider {Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCDRRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXN_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXP_IN
-add wave -noupdate -divider {Receive Ports - RX Elastic Buffer and Phase Alignment Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNDISABLE_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONENB_IN
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONITOR_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNOVERRIDE_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPMAPHASEALIGN_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPMASETPHASE_IN
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXSTATUS_OUT
-add wave -noupdate -divider {Receive Ports - RX Loss-of-sync State Machine }
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXLOSSOFSYNC_OUT
-add wave -noupdate -divider {Receive Ports - RX PLL Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXRXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/MGTREFCLKRX_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PLLRXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPLLLKDET_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESETDONE_OUT
-add wave -noupdate -divider {Receive Ports - RX Pipe Control for PCI Express }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PHYSTATUS_OUT
-add wave -noupdate -divider {Transmit Ports - 8b10b Encoder Control Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXCHARISK_IN
-add wave -noupdate -divider {Transmit Ports - GTX Ports }
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTEST_IN
-add wave -noupdate -divider {Transmit Ports - TX Data Path interface }
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDATA_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXOUTCLK_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXUSRCLK2_IN
-add wave -noupdate -divider {Transmit Ports - TX Driver and OOB signaling }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXN_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXP_OUT
-add wave -noupdate -divider {Transmit Ports - TX Elastic Buffer and Phase Alignment Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNDISABLE_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONENB_IN
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONITOR_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXENPMAPHASEALIGN_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXPMASETPHASE_IN
-add wave -noupdate -divider {Transmit Ports - TX PLL Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESETDONE_OUT
-\r
-TreeUpdate [SetDefaultTree]\r
-WaveRestoreCursors {{Cursor 1} {0 ps} 0}\r
-configure wave -namecolwidth 282\r
-configure wave -valuecolwidth 100\r
-configure wave -justifyvalue left\r
-configure wave -signalnamewidth 1\r
-configure wave -snapdistance 10\r
-configure wave -datasetprefix 0\r
-configure wave -rowmargin 4\r
-configure wave -childrowmargin 2\r
-configure wave -gridoffset 0\r
-configure wave -gridperiod 1\r
-configure wave -griddelta 40\r
-configure wave -timeline 0\r
-update\r
-WaveRestoreZoom {0 ps} {5236 ps}\r
+++ /dev/null
-\r
-###############################################################################\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
- window new WaveWindow -name "Waves for Virtex-6 GTX Wizard Example Design"\r
- waveform using "Waves for Virtex-6 GTX Wizard Example Design"\r
- \r
- waveform add -label FRAME_CHECK_MODULE -comment gtx0_frame_check\r
- waveform add -signals :gtxVirtex6FEE80_top_i:gtx0_frame_check:begin_r\r
- waveform add -signals :gtxVirtex6FEE80_top_i:gtx0_frame_check:track_data_r\r
- waveform add -siganls :gtxVirtex6FEE80_top_i:gtx0_frame_check:data_error_detected_r\r
- wavefrom add -siganls :gtxVirtex6FEE80_top_i:gtx0_frame_check:start_of_packet_detected_r\r
- waveform add -signals :gtxVirtex6FEE80_top_i:gtx0_frame_check:RX_DATA\r
- waveform add -signals :gtxVirtex6FEE80_top_i:gtx0_frame_check:ERROR_COUNT\r
- waveform add -label GTX0_GTXVIRTEX6FEE80 -comment GTX0_GTXVIRTEX6FEE80\r
- waveform add -label Receive_Ports_-_8b10b_Decoder -comment Receive_Ports_-_8b10b_Decoder
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCHARISK_OUT
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDISPERR_OUT
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXNOTINTABLE_OUT
- waveform add -label Receive_Ports_-_Comma_Detection_and_Alignment -comment Receive_Ports_-_Comma_Detection_and_Alignment
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENMCOMMAALIGN_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPCOMMAALIGN_IN
- waveform add -label Receive_Ports_-_RX_Data_Path_interface -comment Receive_Ports_-_RX_Data_Path_interface
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDATA_OUT
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRECCLK_OUT
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESET_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXUSRCLK2_IN
- waveform add -label Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR -comment Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCDRRESET_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXN_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXP_IN
- waveform add -label Receive_Ports_-_RX_Elastic_Buffer_and_Phase_Alignment_Ports -comment Receive_Ports_-_RX_Elastic_Buffer_and_Phase_Alignment_Ports
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNDISABLE_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONENB_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONITOR_OUT
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNOVERRIDE_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNRESET_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPMAPHASEALIGN_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPMASETPHASE_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXSTATUS_OUT
- waveform add -label Receive_Ports_-_RX_Loss-of-sync_State_Machine -comment Receive_Ports_-_RX_Loss-of-sync_State_Machine
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXLOSSOFSYNC_OUT
- waveform add -label Receive_Ports_-_RX_PLL_Ports -comment Receive_Ports_-_RX_PLL_Ports
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXRXRESET_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:MGTREFCLKRX_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PLLRXRESET_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPLLLKDET_OUT
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESETDONE_OUT
- waveform add -label Receive_Ports_-_RX_Pipe_Control_for_PCI_Express -comment Receive_Ports_-_RX_Pipe_Control_for_PCI_Express
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PHYSTATUS_OUT
- waveform add -label Transmit_Ports_-_8b10b_Encoder_Control_Ports -comment Transmit_Ports_-_8b10b_Encoder_Control_Ports
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXCHARISK_IN
- waveform add -label Transmit_Ports_-_GTX_Ports -comment Transmit_Ports_-_GTX_Ports
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTEST_IN
- waveform add -label Transmit_Ports_-_TX_Data_Path_interface -comment Transmit_Ports_-_TX_Data_Path_interface
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDATA_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXOUTCLK_OUT
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESET_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXUSRCLK2_IN
- waveform add -label Transmit_Ports_-_TX_Driver_and_OOB_signaling -comment Transmit_Ports_-_TX_Driver_and_OOB_signaling
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXN_OUT
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXP_OUT
- waveform add -label Transmit_Ports_-_TX_Elastic_Buffer_and_Phase_Alignment_Ports -comment Transmit_Ports_-_TX_Elastic_Buffer_and_Phase_Alignment_Ports
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNDISABLE_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONENB_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONITOR_OUT
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNRESET_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXENPMAPHASEALIGN_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXPMASETPHASE_IN
- waveform add -label Transmit_Ports_-_TX_PLL_Ports -comment Transmit_Ports_-_TX_PLL_Ports
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTXRESET_IN
- waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESETDONE_OUT
-\r
- console submit -using simulator -wait no "run 226 us"\r
-\r
+++ /dev/null
-################################################################################\r
-## ____ ____ \r
-## / /\/ / \r
-## /___/ \ / Vendor: Xilinx \r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : simulate_mti.do\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\ \r
-##\r
-##\r
-## Script SIMULATE_MTI.DO\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-##***************************** Beginning of Script ***************************\r
- \r
-## If MTI_LIBS is defined, map unisim and simprim directories using MTI_LIBS\r
-## This mode of mapping the unisims libraries is provided for backward \r
-## compatibility with previous wizard releases. If you don't set MTI_LIBS\r
-## the unisim libraries will be loaded from the paths set up by compxlib in\r
-## your modelsim.ini file\r
-\r
-set XILINX $env(XILINX)\r
-if [info exists env(MTI_LIBS)] { \r
- set MTI_LIBS $env(MTI_LIBS)\r
- vlib SECUREIP\r
- vlib SIMPRIM\r
- vmap SIMPRIM $MTI_LIBS/simprim\r
- vmap SECUREIP $MTI_LIBS/secureip\r
- \r
-}\r
- \r
-\r
-## Create and map work directory\r
-vlib work\r
-vmap work work\r
-\r
-vcom -93 -work work ../../implement/results/routed.vhd;\r
-\r
-vcom -93 -work work ../sim_reset_mgt_model.vhd;\r
-vcom -93 -work work ../demo_tb_imp.vhd;\r
-\r
-##Load Design\r
-vsim -t 1ps -L SECUREIP -L SIMPRIM -voptargs="+acc" -sdfmax DEMO_TB_IMP/gtxVirtex6FEE80_top_i=../../implement/results/routed.sdf +notimingchecks work.DEMO_TB_IMP\r
-\r
-##Run simulation\r
-run 226 us\r
-\r
-\r
-\r
+++ /dev/null
- Core name: Xilinx LogiCORE Virtex-6 GTX Transceiver Wizard
- Version: 1.12
- Release: 13.4
- Release Date: January 18, 2012
-
-
-================================================================================
-
-This document contains the following sections:
-
-1. Introduction
-2. New Features
-3. Supported Devices
-4. Resolved Issues
-5. Known Issues
-6. Technical Support
-7. Core Release History
-8. Legal Disclaimer
-
-================================================================================
-
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTX
-Transceiver Wizard v1.12 solution. For the latest core updates, see the product page at:
-
- http://www.xilinx.com/products/ipcenter/V6_GTX_Wizard.htm
-
-
-2. NEW FEATURES
-
-- ISE 13.4 software support
-- Auto Upgrade Support has been added. Older versions of the core- 1.4, 1.5, 16, 1.7,
- 1.8,1.9,1.10,1.11 can be upgraded to 1.12
-
-
-3. SUPPORTED DEVICES
-
-The following device families are supported by the core for this release.
-
-Virtex-6 XC CXT/LXT/SXT/HXT
-Virtex-6 XQ LXT/SXT
-Virtex-6 -1L XC LXT/SXT
-Virtex-6 -1L XQ LXT/SXT
-
-
-4. RESOLVED ISSUES
-
-Format for each entry:
-
- 1. Updates to SRIO gen2 settings
-
- Description: Attribute values for SRIO gen2 are updated based on the hw testing results
-
- Version(s) Fixed:
- CR 631978
-
-
-5. KNOWN ISSUES
-
-The most recent information, including known issues, workarounds, and
-resolutions for this version is provided in the IP Release Notes Guide
-located at
-
- www.xilinx.com/support/documentation/user_guides/xtp025.pdf
-
-
-6. TECHNICAL SUPPORT
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-
-7. CORE RELEASE HISTORY
-Date By Version Description
-================================================================================
-01/18/2012 Xilinx, Inc 1.12 ISE 13.4 support
-10/19/2011 Xilinx, Inc 1.11 ISE 13.3 support
-06/22/2011 Xilinx, Inc 1.10 ISE 13.2 support
-03/01/2011 Xilinx, Inc 1.9 ISE 13.1 support
-12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
-09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
-07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
-04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
-12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
-09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
-06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
-04/24/2009 Xilinx, Inc. 1.1 ISE 11.1 support
-================================================================================
-
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
-
+++ /dev/null
-################################################################################\r
-## ____ ____\r
-## / /\/ /\r
-## /___/ \ / Vendor: Xilinx\r
-## \ \ \/ Version : 1.12\r
-## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
-## / / Filename : gtx_attributes.ucf\r
-## /___/ /\ \r
-## \ \ / \ \r
-## \___\/\___\\r
-##\r
-##\r
-## GTX ATTRIBUTES \r
-## This file contains the attributes for the active GTX transceivers in the\r
-## design. If you would like to use this file in your design, please make\r
-## sure that the path to the GTX instance is correct.\r
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
-##\r
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
-##\r
-## This file contains confidential and proprietary information\r
-## of Xilinx, Inc. and is protected under U.S. and\r
-## international copyright and other intellectual property\r
-## laws.\r
-##\r
-## DISCLAIMER\r
-## This disclaimer is not a license and does not grant any\r
-## rights to the materials distributed herewith. Except as\r
-## otherwise provided in a valid license issued to you by\r
-## Xilinx, and to the maximum extent permitted by applicable\r
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
-## (2) Xilinx shall not be liable (whether in contract or tort,\r
-## including negligence, or under any other theory of\r
-## liability) for any loss or damage of any kind or nature\r
-## related to, arising under or in connection with these\r
-## materials, including for any direct, or any indirect,\r
-## special, incidental, or consequential loss or damage\r
-## (including loss of data, profits, goodwill, or any type of\r
-## loss or damage suffered as a result of any action brought\r
-## by a third party) even if such damage or loss was\r
-## reasonably foreseeable or Xilinx had been advised of the\r
-## possibility of the same.\r
-##\r
-## CRITICAL APPLICATIONS\r
-## Xilinx products are not designed or intended to be fail-\r
-## safe, or for use in any application requiring fail-safe\r
-## performance, such as life-support or safety devices or\r
-## systems, Class III medical devices, nuclear facilities,\r
-## applications related to the deployment of airbags, or any\r
-## other applications that could lead to death, personal\r
-## injury, or severe property or environmental damage\r
-## (individually and collectively, "Critical\r
-## Applications"). Customer assumes the sole risk and\r
-## liability of any use of Xilinx products in Critical\r
-## Applications, subject only to applicable laws and\r
-## regulations governing limitations on product liability.\r
-## \r
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
-## PART OF THIS FILE AT ALL TIMES.\r
-\r
-############################## Active GTX Attributes #######################\r
- \r
-##________________________ Attributes for GTX 0_____________________\r
- \r
-
-##--------------------------TX PLL----------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK_SOURCE = "RXPLL";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_OVERSAMPLE_MODE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_COM_CFG = 24'h21680a;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_CP_CFG = 8'h07;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_FB = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_OUT = 2;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_REF = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL45_FB = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_LKDET_CFG = 3'b111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK25_DIVIDER = 4;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_SATA = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_TDCC_CFG = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CAS_CLK_EN = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i POWER_SAVE = 10'b0000110100;
-
-##-----------------------TX Interface-------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_TXUSRCLK = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DATA_WIDTH = 10;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_USRCLK_CFG = 6'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_CTRL = "TXPLLREFCLK_DIV1";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_DLY = 10'b0000000000;
-
-##------------TX Buffering and Phase Alignment----------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_PMADATA_OPT = 1'b1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_TX_CFG = 20'h80082;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BUFFER_USE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BYTECLK_CFG = 6'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_EN_RATE_RESET_BUF = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_XCLK_SEL = "TXUSR";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_CTRINC = 4'b0100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_LPFINC = 4'b0110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_MONSEL = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_OVRDSETTING = 8'b10000000;
-
-##-----------------------TX Gearbox---------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEARBOX_ENDEC = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXGEARBOX_USE = "FALSE";
-
-##--------------TX Driver and OOB Signalling------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DRIVE_MODE = "DIRECT";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_ASSERT_DELAY = 3'b101;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_DEASSERT_DELAY = 3'b011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_HIZ = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_PD = "FALSE";
-
-##------------TX Pipe Control for PCI Express/SATA------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COM_BURST_VAL = 4'b1111;
-
-##----------------TX Attributes for PCI Express---------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_0 = 5'b11010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_1 = 5'b10000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_0 = 7'b1001110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_1 = 7'b1001001;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_2 = 7'b1000101;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_3 = 7'b1000010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_4 = 7'b1000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_0 = 7'b1000110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_1 = 7'b1000100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_2 = 7'b1000010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_3 = 7'b1000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_4 = 7'b1000000;
-
-##--------------------------RX PLL----------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_OVERSAMPLE_MODE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_COM_CFG = 24'h21680a;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_CP_CFG = 8'h07;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_FB = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_OUT = 2;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_REF = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL45_FB = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_LKDET_CFG = 3'b111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_CLK25_DIVIDER = 4;
-
-##-----------------------RX Interface-------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_RXUSRCLK = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DATA_WIDTH = 10;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_CTRL = "RXRECCLKPMA_DIV1";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_DLY = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXUSRCLK_DLY = 16'h0000;
-
-##--------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i AC_CAP_DIS = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CDR_PH_ADJ_TIME = 5'b10100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i OOBDETECT_THRESHOLD = 3'b011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CDR_SCAN = 27'h640404C;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RX_CFG = 25'h05ce008;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_GND = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_VTTRX = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_CDR = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_FR = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_PH = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DETECT_RX_CFG = 14'h1832;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_CTRL = 5'b00000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_OVRD = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CM_TRIM = 2'b01;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RXSYNC_CFG = 7'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CFG = 76'h0040000040000000003;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BGTEST_CFG = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BIAS_CFG = 17'h00000;
-
-##------------RX Decision Feedback Equalizer(DFE)-------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CAL_TIME = 5'b01100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CFG = 8'b00011011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_DFE = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_OFFSET = 8'h4C;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_SCANMODE = 2'b00;
-
-##-----------------------PRBS Detection-----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPRBSERR_LOOPBACK = 1'b0;
-
-##----------------Comma Detection and Alignment---------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i ALIGN_COMMA_WORD = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_10B_ENABLE = 10'b1111111100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_DOUBLE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_MCOMMA_DETECT = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_PCOMMA_DETECT = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_VALID_COMMA_ONLY = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_10B_VALUE = 10'b1010000011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_DETECT = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_10B_VALUE = 10'b0101111100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_DETECT = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DECODE_SEQ_MATCH = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_AUTO_WAIT = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_MODE = "OFF";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SHOW_REALIGN_COMMA = "TRUE";
-
-##---------------RX Loss-of-sync State Machine----------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_INVALID_INCR = 8;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_THRESHOLD = 256;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOSS_OF_SYNC_FSM = "TRUE";
-
-##-----------------------RX Gearbox---------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXGEARBOX_USE = "FALSE";
-
-##-----------RX Elastic Buffer and Phase alignment------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_BUFFER_USE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_BUF = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_MODE_RESET_BUF = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_RATE_RESET_BUF = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF2 = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_FIFO_ADDR_MODE = "FAST";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_HI_CNT = 4'b1000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_LO_CNT = 4'b0000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_XCLK_SEL = "RXUSR";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_CTRINC = 4'b1110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_EDGESET = 5'b00010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_LPFINC = 4'b1110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_MONSEL = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_OVRDSETTING = 8'b10000000;
-
-##----------------------Clock Correction----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_ADJ_LEN = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_DET_LEN = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_INSERT_IDLE_FLAG = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_KEEP_IDLE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MAX_LAT = 16;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MIN_LAT = 14;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_PRECEDENCE = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_REPEAT_WAIT = 0;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_1 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_2 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_3 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_4 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_ENABLE = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_1 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_2 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_3 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_4 = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_ENABLE = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_USE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_CORRECT_USE = "FALSE";
-
-##----------------------Channel Bonding----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_1_MAX_SKEW = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_2_MAX_SKEW = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_KEEP_ALIGN = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_1 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_2 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_3 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_4 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_1 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_2 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_3 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_4 = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_CFG = 5'b00000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_USE = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_LEN = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCI_EXPRESS_MODE = "FALSE";
-
-##-----------RX Attributes for PCI Express/SATA/SAS----------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MAX_COMSAS = 52;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MIN_COMSAS = 40;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_BURST_VAL = 3'b100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_IDLE_VAL = 3'b100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_BURST = 11;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_INIT = 34;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_WAKE = 11;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_BURST = 6;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_INIT = 19;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_WAKE = 6;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_FROM_P2 = 12'h03c;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_NON_P2 = 8'h19;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_RATE = 8'hff;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_TO_P2 = 10'h064;
-\r
-\r
-\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx\r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : gtxvirtex6fee80.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module GTXVIRTEX6FEE80 (a GTX Wrapper)\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
-\r
---***************************** Entity Declaration ****************************\r
-\r
-entity gtxVirtex6FEE80 is\r
-generic\r
-(\r
- -- Simulation attributes\r
- WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
-);\r
-port\r
-(\r
- \r
- --_________________________________________________________________________\r
- --_________________________________________________________________________\r
- --GTX0 (X0Y12)\r
- \r
- GTX0_DOUBLE_RESET_CLK_IN : in std_logic;\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GTX0_RXCHARISK_OUT : out std_logic;
- GTX0_RXDISPERR_OUT : out std_logic;
- GTX0_RXNOTINTABLE_OUT : out std_logic;
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GTX0_RXENMCOMMAALIGN_IN : in std_logic;
- GTX0_RXENPCOMMAALIGN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
- GTX0_RXRECCLK_OUT : out std_logic;
- GTX0_RXRESET_IN : in std_logic;
- GTX0_RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GTX0_RXCDRRESET_IN : in std_logic;
- GTX0_RXN_IN : in std_logic;
- GTX0_RXP_IN : in std_logic;
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
- GTX0_RXDLYALIGNMONENB_IN : in std_logic;
- GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
- GTX0_RXDLYALIGNRESET_IN : in std_logic;
- GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
- GTX0_RXPMASETPHASE_IN : in std_logic;
- GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTX0_GTXRXRESET_IN : in std_logic;
- GTX0_MGTREFCLKRX_IN : in std_logic;
- GTX0_PLLRXRESET_IN : in std_logic;
- GTX0_RXPLLLKDET_OUT : out std_logic;
- GTX0_RXRESETDONE_OUT : out std_logic;
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- GTX0_PHYSTATUS_OUT : out std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GTX0_TXCHARISK_IN : in std_logic;
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
- GTX0_TXOUTCLK_OUT : out std_logic;
- GTX0_TXRESET_IN : in std_logic;
- GTX0_TXUSRCLK2_IN : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTX0_TXN_OUT : out std_logic;
- GTX0_TXP_OUT : out std_logic;
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
- GTX0_TXDLYALIGNMONENB_IN : in std_logic;
- GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- GTX0_TXDLYALIGNRESET_IN : in std_logic;
- GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
- GTX0_TXPMASETPHASE_IN : in std_logic;
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTX0_GTXTXRESET_IN : in std_logic;
- GTX0_TXRESETDONE_OUT : out std_logic
-\r
- \r
-);\r
-\r
-\r
-end gtxVirtex6FEE80;\r
- \r
-architecture RTL of gtxVirtex6FEE80 is\r
-\r
- attribute CORE_GENERATION_INFO : string;\r
- attribute CORE_GENERATION_INFO of RTL : architecture is "gtxVirtex6FEE80,v6_gtxwizard_v1_12,{protocol_file=Start_from_scratch}";\r
-\r
---***************************** Signal Declarations *****************************\r
-\r
- -- ground and tied_to_vcc_i signals\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);\r
- signal tied_to_vcc_i : std_logic;\r
-\r
- signal gtx0_gtxtest_bit1 : std_logic;\r
- signal gtx0_gtxtest_done : std_logic;\r
- signal gtx0_gtxtest_i : std_logic_vector(12 downto 0);\r
- signal gtx0_txreset_i : std_logic;\r
- signal gtx0_rxreset_i : std_logic;\r
- signal gtx0_rxplllkdet_i : std_logic;\r
- \r
-\r
- \r
- signal gtx0_share_rxpll_i : std_logic_vector(1 downto 0);\r
- signal gtx0_mgtrefclkrx_i : std_logic_vector(1 downto 0);\r
- \r
---*************************** Component Declarations **************************\r
-component gtxVirtex6FEE80_gtx\r
-generic\r
-(\r
- -- Simulation attributes\r
- GTX_SIM_GTXRESET_SPEEDUP : integer := 0;\r
- \r
- -- Share RX PLL parameter\r
- GTX_TX_CLK_SOURCE : string := "TXPLL";\r
- -- Save power parameter\r
- GTX_POWER_SAVE : bit_vector := "0000000000"\r
-);\r
-port \r
-( \r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISK_OUT : out std_logic;
- RXDISPERR_OUT : out std_logic;
- RXNOTINTABLE_OUT : out std_logic;
- --------------- Receive Ports - Comma Detection and Alignment --------------
- RXENMCOMMAALIGN_IN : in std_logic;
- RXENPCOMMAALIGN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- RXDATA_OUT : out std_logic_vector(7 downto 0);
- RXRECCLK_OUT : out std_logic;
- RXRESET_IN : in std_logic;
- RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRRESET_IN : in std_logic;
- RXN_IN : in std_logic;
- RXP_IN : in std_logic;
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- RXDLYALIGNDISABLE_IN : in std_logic;
- RXDLYALIGNMONENB_IN : in std_logic;
- RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- RXDLYALIGNOVERRIDE_IN : in std_logic;
- RXDLYALIGNRESET_IN : in std_logic;
- RXENPMAPHASEALIGN_IN : in std_logic;
- RXPMASETPHASE_IN : in std_logic;
- RXSTATUS_OUT : out std_logic_vector(2 downto 0);
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTXRXRESET_IN : in std_logic;
- MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
- PLLRXRESET_IN : in std_logic;
- RXPLLLKDET_OUT : out std_logic;
- RXRESETDONE_OUT : out std_logic;
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- PHYSTATUS_OUT : out std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- TXCHARISK_IN : in std_logic;
- ------------------------- Transmit Ports - GTX Ports -----------------------
- GTXTEST_IN : in std_logic_vector(12 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- TXDATA_IN : in std_logic_vector(7 downto 0);
- TXOUTCLK_OUT : out std_logic;
- TXRESET_IN : in std_logic;
- TXUSRCLK2_IN : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- TXN_OUT : out std_logic;
- TXP_OUT : out std_logic;
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- TXDLYALIGNDISABLE_IN : in std_logic;
- TXDLYALIGNMONENB_IN : in std_logic;
- TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- TXDLYALIGNRESET_IN : in std_logic;
- TXENPMAPHASEALIGN_IN : in std_logic;
- TXPMASETPHASE_IN : in std_logic;
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTXTXRESET_IN : in std_logic;
- MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
- PLLTXRESET_IN : in std_logic;
- TXPLLLKDET_OUT : out std_logic;
- TXRESETDONE_OUT : out std_logic
-\r
-\r
-);\r
-end component;\r
-\r
-component DOUBLE_RESET\r
-port\r
-(\r
- CLK : in std_logic;\r
- PLLLKDET : in std_logic;\r
- GTXTEST_DONE : out std_logic;\r
- GTXTEST_BIT1 : out std_logic\r
-\r
-);\r
-end component;\r
-\r
---********************************* Main Body of Code**************************\r
-\r
-begin \r
-\r
- tied_to_ground_i <= '0';\r
- tied_to_ground_vec_i(63 downto 0) <= (others => '0');\r
- tied_to_vcc_i <= '1';\r
- \r
- gtx0_gtxtest_i <= b"10000000000" & gtx0_gtxtest_bit1 & '0';\r
- gtx0_txreset_i <= gtx0_gtxtest_done or GTX0_TXRESET_IN;\r
- gtx0_rxreset_i <= GTX0_RXRESET_IN;\r
- GTX0_RXPLLLKDET_OUT <= gtx0_rxplllkdet_i;\r
-\r
- \r
- gtx0_mgtrefclkrx_i <= (tied_to_ground_i & GTX0_MGTREFCLKRX_IN);
-\r
- \r
- --------------------------- GTX Instances ------------------------------- \r
-\r
-\r
- --_________________________________________________________________________\r
- --_________________________________________________________________________\r
- --GTX0 (X0Y12)\r
-\r
- gtx0_gtxVirtex6FEE80_i : gtxVirtex6FEE80_gtx\r
- generic map\r
- (\r
- -- Simulation attributes\r
- GTX_SIM_GTXRESET_SPEEDUP => WRAPPER_SIM_GTXRESET_SPEEDUP,\r
- \r
- -- Share RX PLL parameter\r
- GTX_TX_CLK_SOURCE => "RXPLL",\r
- -- Save power parameter\r
- GTX_POWER_SAVE => "0000110100"\r
- )\r
- port map\r
- (\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISK_OUT => GTX0_RXCHARISK_OUT,
- RXDISPERR_OUT => GTX0_RXDISPERR_OUT,
- RXNOTINTABLE_OUT => GTX0_RXNOTINTABLE_OUT,
- --------------- Receive Ports - Comma Detection and Alignment --------------
- RXENMCOMMAALIGN_IN => GTX0_RXENMCOMMAALIGN_IN,
- RXENPCOMMAALIGN_IN => GTX0_RXENPCOMMAALIGN_IN,
- ------------------- Receive Ports - RX Data Path interface -----------------
- RXDATA_OUT => GTX0_RXDATA_OUT,
- RXRECCLK_OUT => GTX0_RXRECCLK_OUT,
- RXRESET_IN => gtx0_rxreset_i,
- RXUSRCLK2_IN => GTX0_RXUSRCLK2_IN,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRRESET_IN => GTX0_RXCDRRESET_IN,
- RXN_IN => GTX0_RXN_IN,
- RXP_IN => GTX0_RXP_IN,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- RXDLYALIGNDISABLE_IN => GTX0_RXDLYALIGNDISABLE_IN,
- RXDLYALIGNMONENB_IN => GTX0_RXDLYALIGNMONENB_IN,
- RXDLYALIGNMONITOR_OUT => GTX0_RXDLYALIGNMONITOR_OUT,
- RXDLYALIGNOVERRIDE_IN => GTX0_RXDLYALIGNOVERRIDE_IN,
- RXDLYALIGNRESET_IN => GTX0_RXDLYALIGNRESET_IN,
- RXENPMAPHASEALIGN_IN => GTX0_RXENPMAPHASEALIGN_IN,
- RXPMASETPHASE_IN => GTX0_RXPMASETPHASE_IN,
- RXSTATUS_OUT => GTX0_RXSTATUS_OUT,
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- RXLOSSOFSYNC_OUT => GTX0_RXLOSSOFSYNC_OUT,
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTXRXRESET_IN => GTX0_GTXRXRESET_IN,
- MGTREFCLKRX_IN => gtx0_mgtrefclkrx_i,
- PLLRXRESET_IN => GTX0_PLLRXRESET_IN,
- RXPLLLKDET_OUT => gtx0_rxplllkdet_i,
- RXRESETDONE_OUT => GTX0_RXRESETDONE_OUT,
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- PHYSTATUS_OUT => GTX0_PHYSTATUS_OUT,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- TXCHARISK_IN => GTX0_TXCHARISK_IN,
- ------------------------- Transmit Ports - GTX Ports -----------------------
- GTXTEST_IN => gtx0_gtxtest_i,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- TXDATA_IN => GTX0_TXDATA_IN,
- TXOUTCLK_OUT => GTX0_TXOUTCLK_OUT,
- TXRESET_IN => gtx0_txreset_i,
- TXUSRCLK2_IN => GTX0_TXUSRCLK2_IN,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- TXN_OUT => GTX0_TXN_OUT,
- TXP_OUT => GTX0_TXP_OUT,
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- TXDLYALIGNDISABLE_IN => GTX0_TXDLYALIGNDISABLE_IN,
- TXDLYALIGNMONENB_IN => GTX0_TXDLYALIGNMONENB_IN,
- TXDLYALIGNMONITOR_OUT => GTX0_TXDLYALIGNMONITOR_OUT,
- TXDLYALIGNRESET_IN => GTX0_TXDLYALIGNRESET_IN,
- TXENPMAPHASEALIGN_IN => GTX0_TXENPMAPHASEALIGN_IN,
- TXPMASETPHASE_IN => GTX0_TXPMASETPHASE_IN,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTXTXRESET_IN => GTX0_GTXTXRESET_IN,
- MGTREFCLKTX_IN => gtx0_mgtrefclkrx_i,
- PLLTXRESET_IN => tied_to_ground_i,
- TXPLLLKDET_OUT => open,
- TXRESETDONE_OUT => GTX0_TXRESETDONE_OUT
-\r
- );\r
-\r
- \r
- \r
- gtx0_double_reset_i : DOUBLE_RESET\r
- port map\r
- (\r
- CLK => GTX0_DOUBLE_RESET_CLK_IN,\r
- PLLLKDET => gtx0_rxplllkdet_i,\r
- GTXTEST_DONE => gtx0_gtxtest_done,\r
- GTXTEST_BIT1 => gtx0_gtxtest_bit1\r
- );\r
-\r
- \r
-\r
- \r
-end RTL;\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx\r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : gtxvirtex6fee80_gtx.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module GTXVIRTEX6FEE80_GTX (a GTX Wrapper)\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***************************** Entity Declaration ****************************\r
-\r
-entity gtxVirtex6FEE80_gtx is\r
-generic\r
-(\r
- -- Simulation attributes\r
- GTX_SIM_GTXRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset\r
- \r
- -- Share RX PLL parameter\r
- GTX_TX_CLK_SOURCE : string := "TXPLL";\r
- -- Save power parameter\r
- GTX_POWER_SAVE : bit_vector := "0000000000"\r
-);\r
-port \r
-(\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISK_OUT : out std_logic;
- RXDISPERR_OUT : out std_logic;
- RXNOTINTABLE_OUT : out std_logic;
- --------------- Receive Ports - Comma Detection and Alignment --------------
- RXENMCOMMAALIGN_IN : in std_logic;
- RXENPCOMMAALIGN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- RXDATA_OUT : out std_logic_vector(7 downto 0);
- RXRECCLK_OUT : out std_logic;
- RXRESET_IN : in std_logic;
- RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- RXCDRRESET_IN : in std_logic;
- RXN_IN : in std_logic;
- RXP_IN : in std_logic;
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- RXDLYALIGNDISABLE_IN : in std_logic;
- RXDLYALIGNMONENB_IN : in std_logic;
- RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- RXDLYALIGNOVERRIDE_IN : in std_logic;
- RXDLYALIGNRESET_IN : in std_logic;
- RXENPMAPHASEALIGN_IN : in std_logic;
- RXPMASETPHASE_IN : in std_logic;
- RXSTATUS_OUT : out std_logic_vector(2 downto 0);
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTXRXRESET_IN : in std_logic;
- MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
- PLLRXRESET_IN : in std_logic;
- RXPLLLKDET_OUT : out std_logic;
- RXRESETDONE_OUT : out std_logic;
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- PHYSTATUS_OUT : out std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- TXCHARISK_IN : in std_logic;
- ------------------------- Transmit Ports - GTX Ports -----------------------
- GTXTEST_IN : in std_logic_vector(12 downto 0);
- ------------------ Transmit Ports - TX Data Path interface -----------------
- TXDATA_IN : in std_logic_vector(7 downto 0);
- TXOUTCLK_OUT : out std_logic;
- TXRESET_IN : in std_logic;
- TXUSRCLK2_IN : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- TXN_OUT : out std_logic;
- TXP_OUT : out std_logic;
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- TXDLYALIGNDISABLE_IN : in std_logic;
- TXDLYALIGNMONENB_IN : in std_logic;
- TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- TXDLYALIGNRESET_IN : in std_logic;
- TXENPMAPHASEALIGN_IN : in std_logic;
- TXPMASETPHASE_IN : in std_logic;
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTXTXRESET_IN : in std_logic;
- MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
- PLLTXRESET_IN : in std_logic;
- TXPLLLKDET_OUT : out std_logic;
- TXRESETDONE_OUT : out std_logic
-\r
-\r
-);\r
-\r
-\r
-end gtxVirtex6FEE80_gtx;\r
-\r
-architecture RTL of gtxVirtex6FEE80_gtx is\r
- \r
---**************************** Signal Declarations ****************************\r
-\r
- -- ground and tied_to_vcc_i signals\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);\r
- signal tied_to_vcc_i : std_logic;\r
-\r
-\r
-\r
- -- RX Datapath signals\r
- signal rxdata_i : std_logic_vector(31 downto 0); \r
- signal rxchariscomma_float_i : std_logic_vector(2 downto 0);\r
- signal rxcharisk_float_i : std_logic_vector(2 downto 0);\r
- signal rxdisperr_float_i : std_logic_vector(2 downto 0);\r
- signal rxnotintable_float_i : std_logic_vector(2 downto 0);\r
- signal rxrundisp_float_i : std_logic_vector(2 downto 0);\r
- \r
-\r
-\r
- -- TX Datapath signals\r
- signal txdata_i : std_logic_vector(31 downto 0);\r
- signal txkerr_float_i : std_logic_vector(2 downto 0);\r
- signal txrundisp_float_i : std_logic_vector(2 downto 0);\r
-\r
---******************************** Main Body of Code***************************\r
- \r
-begin \r
-\r
- --------------------------- Static signal Assignments --------------------- \r
-\r
- tied_to_ground_i <= '0';\r
- tied_to_ground_vec_i(63 downto 0) <= (others => '0');\r
- tied_to_vcc_i <= '1';\r
-\r
- ------------------- GTX Datapath byte mapping -----------------\r
-\r
- RXDATA_OUT <= rxdata_i(7 downto 0);\r
-\r
- txdata_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA_IN);\r
-\r
-\r
-\r
- ----------------------------- GTX Instance -------------------------- \r
-\r
- gtxe1_i :GTXE1\r
- generic map\r
- (\r
-\r
- --_______________________ Simulation-Only Attributes ___________________\r
-\r
- SIM_RECEIVER_DETECT_PASS => (TRUE),\r
- \r
- SIM_GTXRESET_SPEEDUP => (GTX_SIM_GTXRESET_SPEEDUP),\r
-\r
- SIM_TX_ELEC_IDLE_LEVEL => ("X"),\r
-\r
- SIM_VERSION => ("2.0"),\r
- SIM_TXREFCLK_SOURCE => ("000"),\r
- SIM_RXREFCLK_SOURCE => ("000"),\r
- \r
-
- ----------------------------TX PLL----------------------------
- TX_CLK_SOURCE => (GTX_TX_CLK_SOURCE),
- TX_OVERSAMPLE_MODE => (FALSE),
- TXPLL_COM_CFG => (x"21680a"),
- TXPLL_CP_CFG => (x"07"),
- TXPLL_DIVSEL_FB => (5),
- TXPLL_DIVSEL_OUT => (2),
- TXPLL_DIVSEL_REF => (1),
- TXPLL_DIVSEL45_FB => (5),
- TXPLL_LKDET_CFG => ("111"),
- TX_CLK25_DIVIDER => (4),
- TXPLL_SATA => ("00"),
- TX_TDCC_CFG => ("00"),
- PMA_CAS_CLK_EN => (FALSE),
- POWER_SAVE => (GTX_POWER_SAVE),
-
- -------------------------TX Interface-------------------------
- GEN_TXUSRCLK => (TRUE),
- TX_DATA_WIDTH => (10),
- TX_USRCLK_CFG => (x"00"),
- TXOUTCLK_CTRL => ("TXPLLREFCLK_DIV1"),
- TXOUTCLK_DLY => ("0000000000"),
-
- --------------TX Buffering and Phase Alignment----------------
- TX_PMADATA_OPT => ('1'),
- PMA_TX_CFG => (x"80082"),
- TX_BUFFER_USE => (FALSE),
- TX_BYTECLK_CFG => (x"00"),
- TX_EN_RATE_RESET_BUF => (TRUE),
- TX_XCLK_SEL => ("TXUSR"),
- TX_DLYALIGN_CTRINC => ("0100"),
- TX_DLYALIGN_LPFINC => ("0110"),
- TX_DLYALIGN_MONSEL => ("000"),
- TX_DLYALIGN_OVRDSETTING => ("10000000"),
-
- -------------------------TX Gearbox---------------------------
- GEARBOX_ENDEC => ("000"),
- TXGEARBOX_USE => (FALSE),
-
- ----------------TX Driver and OOB Signalling------------------
- TX_DRIVE_MODE => ("DIRECT"),
- TX_IDLE_ASSERT_DELAY => ("101"),
- TX_IDLE_DEASSERT_DELAY => ("011"),
- TXDRIVE_LOOPBACK_HIZ => (FALSE),
- TXDRIVE_LOOPBACK_PD => (FALSE),
-
- --------------TX Pipe Control for PCI Express/SATA------------
- COM_BURST_VAL => ("1111"),
-
- ------------------TX Attributes for PCI Express---------------
- TX_DEEMPH_0 => ("11010"),
- TX_DEEMPH_1 => ("10000"),
- TX_MARGIN_FULL_0 => ("1001110"),
- TX_MARGIN_FULL_1 => ("1001001"),
- TX_MARGIN_FULL_2 => ("1000101"),
- TX_MARGIN_FULL_3 => ("1000010"),
- TX_MARGIN_FULL_4 => ("1000000"),
- TX_MARGIN_LOW_0 => ("1000110"),
- TX_MARGIN_LOW_1 => ("1000100"),
- TX_MARGIN_LOW_2 => ("1000010"),
- TX_MARGIN_LOW_3 => ("1000000"),
- TX_MARGIN_LOW_4 => ("1000000"),
-
- ----------------------------RX PLL----------------------------
- RX_OVERSAMPLE_MODE => (FALSE),
- RXPLL_COM_CFG => (x"21680a"),
- RXPLL_CP_CFG => (x"07"),
- RXPLL_DIVSEL_FB => (5),
- RXPLL_DIVSEL_OUT => (2),
- RXPLL_DIVSEL_REF => (1),
- RXPLL_DIVSEL45_FB => (5),
- RXPLL_LKDET_CFG => ("111"),
- RX_CLK25_DIVIDER => (4),
-
- -------------------------RX Interface-------------------------
- GEN_RXUSRCLK => (TRUE),
- RX_DATA_WIDTH => (10),
- RXRECCLK_CTRL => ("RXRECCLKPMA_DIV1"),
- RXRECCLK_DLY => ("0000000000"),
- RXUSRCLK_DLY => (x"0000"),
-
- ----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
- AC_CAP_DIS => (TRUE),
- CDR_PH_ADJ_TIME => ("10100"),
- OOBDETECT_THRESHOLD => ("011"),
- PMA_CDR_SCAN => (x"640404C"),
- PMA_RX_CFG => (x"05ce008"),
- RCV_TERM_GND => (FALSE),
- RCV_TERM_VTTRX => (TRUE),
- RX_EN_IDLE_HOLD_CDR => (FALSE),
- RX_EN_IDLE_RESET_FR => (FALSE),
- RX_EN_IDLE_RESET_PH => (FALSE),
- TX_DETECT_RX_CFG => (x"1832"),
- TERMINATION_CTRL => ("00000"),
- TERMINATION_OVRD => (FALSE),
- CM_TRIM => ("01"),
- PMA_RXSYNC_CFG => (x"00"),
- PMA_CFG => (x"0040000040000000003"),
- BGTEST_CFG => ("00"),
- BIAS_CFG => (x"00000"),
-
- --------------RX Decision Feedback Equalizer(DFE)-------------
- DFE_CAL_TIME => ("01100"),
- DFE_CFG => ("00011011"),
- RX_EN_IDLE_HOLD_DFE => (TRUE),
- RX_EYE_OFFSET => (x"4C"),
- RX_EYE_SCANMODE => ("00"),
-
- -------------------------PRBS Detection-----------------------
- RXPRBSERR_LOOPBACK => ('0'),
-
- ------------------Comma Detection and Alignment---------------
- ALIGN_COMMA_WORD => (1),
- COMMA_10B_ENABLE => ("1111111100"),
- COMMA_DOUBLE => (FALSE),
- DEC_MCOMMA_DETECT => (FALSE),
- DEC_PCOMMA_DETECT => (FALSE),
- DEC_VALID_COMMA_ONLY => (FALSE),
- MCOMMA_10B_VALUE => ("1010000011"),
- MCOMMA_DETECT => (TRUE),
- PCOMMA_10B_VALUE => ("0101111100"),
- PCOMMA_DETECT => (TRUE),
- RX_DECODE_SEQ_MATCH => (TRUE),
- RX_SLIDE_AUTO_WAIT => (5),
- RX_SLIDE_MODE => ("OFF"),
- SHOW_REALIGN_COMMA => (TRUE),
-
- -----------------RX Loss-of-sync State Machine----------------
- RX_LOS_INVALID_INCR => (8),
- RX_LOS_THRESHOLD => (256),
- RX_LOSS_OF_SYNC_FSM => (TRUE),
-
- -------------------------RX Gearbox---------------------------
- RXGEARBOX_USE => (FALSE),
-
- -------------RX Elastic Buffer and Phase alignment------------
- RX_BUFFER_USE => (FALSE),
- RX_EN_IDLE_RESET_BUF => (FALSE),
- RX_EN_MODE_RESET_BUF => (TRUE),
- RX_EN_RATE_RESET_BUF => (TRUE),
- RX_EN_REALIGN_RESET_BUF => (FALSE),
- RX_EN_REALIGN_RESET_BUF2 => (FALSE),
- RX_FIFO_ADDR_MODE => ("FAST"),
- RX_IDLE_HI_CNT => ("1000"),
- RX_IDLE_LO_CNT => ("0000"),
- RX_XCLK_SEL => ("RXUSR"),
- RX_DLYALIGN_CTRINC => ("1110"),
- RX_DLYALIGN_EDGESET => ("00010"),
- RX_DLYALIGN_LPFINC => ("1110"),
- RX_DLYALIGN_MONSEL => ("000"),
- RX_DLYALIGN_OVRDSETTING => ("10000000"),
-
- ------------------------Clock Correction----------------------
- CLK_COR_ADJ_LEN => (1),
- CLK_COR_DET_LEN => (1),
- CLK_COR_INSERT_IDLE_FLAG => (FALSE),
- CLK_COR_KEEP_IDLE => (FALSE),
- CLK_COR_MAX_LAT => (16),
- CLK_COR_MIN_LAT => (14),
- CLK_COR_PRECEDENCE => (TRUE),
- CLK_COR_REPEAT_WAIT => (0),
- CLK_COR_SEQ_1_1 => ("0100000000"),
- CLK_COR_SEQ_1_2 => ("0100000000"),
- CLK_COR_SEQ_1_3 => ("0100000000"),
- CLK_COR_SEQ_1_4 => ("0100000000"),
- CLK_COR_SEQ_1_ENABLE => ("1111"),
- CLK_COR_SEQ_2_1 => ("0100000000"),
- CLK_COR_SEQ_2_2 => ("0100000000"),
- CLK_COR_SEQ_2_3 => ("0100000000"),
- CLK_COR_SEQ_2_4 => ("0100000000"),
- CLK_COR_SEQ_2_ENABLE => ("1111"),
- CLK_COR_SEQ_2_USE => (FALSE),
- CLK_CORRECT_USE => (FALSE),
-
- ------------------------Channel Bonding----------------------
- CHAN_BOND_1_MAX_SKEW => (1),
- CHAN_BOND_2_MAX_SKEW => (1),
- CHAN_BOND_KEEP_ALIGN => (FALSE),
- CHAN_BOND_SEQ_1_1 => ("0000000000"),
- CHAN_BOND_SEQ_1_2 => ("0000000000"),
- CHAN_BOND_SEQ_1_3 => ("0000000000"),
- CHAN_BOND_SEQ_1_4 => ("0000000000"),
- CHAN_BOND_SEQ_1_ENABLE => ("1111"),
- CHAN_BOND_SEQ_2_1 => ("0000000000"),
- CHAN_BOND_SEQ_2_2 => ("0000000000"),
- CHAN_BOND_SEQ_2_3 => ("0000000000"),
- CHAN_BOND_SEQ_2_4 => ("0000000000"),
- CHAN_BOND_SEQ_2_CFG => ("00000"),
- CHAN_BOND_SEQ_2_ENABLE => ("1111"),
- CHAN_BOND_SEQ_2_USE => (FALSE),
- CHAN_BOND_SEQ_LEN => (1),
- PCI_EXPRESS_MODE => (FALSE),
-
- -------------RX Attributes for PCI Express/SATA/SAS----------
- SAS_MAX_COMSAS => (52),
- SAS_MIN_COMSAS => (40),
- SATA_BURST_VAL => ("100"),
- SATA_IDLE_VAL => ("100"),
- SATA_MAX_BURST => (11),
- SATA_MAX_INIT => (34),
- SATA_MAX_WAKE => (11),
- SATA_MIN_BURST => (6),
- SATA_MIN_INIT => (19),
- SATA_MIN_WAKE => (6),
- TRANS_TIME_FROM_P2 => (x"03c"),
- TRANS_TIME_NON_P2 => (x"19"),
- TRANS_TIME_RATE => (x"ff"),
- TRANS_TIME_TO_P2 => (x"064")
-\r
-\r
- )\r
- port map\r
- (\r
- ------------------------ Loopback and Powerdown Ports ----------------------
- LOOPBACK => tied_to_ground_vec_i(2 downto 0),
- RXPOWERDOWN => "00",
- TXPOWERDOWN => "00",
- -------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
- RXDATAVALID => open,
- RXGEARBOXSLIP => tied_to_ground_i,
- RXHEADER => open,
- RXHEADERVALID => open,
- RXSTARTOFSEQ => open,
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- RXCHARISCOMMA => open,
- RXCHARISK(3 downto 1) => rxcharisk_float_i,
- RXCHARISK(0) => RXCHARISK_OUT,
- RXDEC8B10BUSE => tied_to_vcc_i,
- RXDISPERR(3 downto 1) => rxdisperr_float_i,
- RXDISPERR(0) => RXDISPERR_OUT,
- RXNOTINTABLE(3 downto 1) => rxnotintable_float_i,
- RXNOTINTABLE(0) => RXNOTINTABLE_OUT,
- RXRUNDISP => open,
- USRCODEERR => tied_to_ground_i,
- ------------------- Receive Ports - Channel Bonding Ports ------------------
- RXCHANBONDSEQ => open,
- RXCHBONDI => tied_to_ground_vec_i(3 downto 0),
- RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
- RXCHBONDMASTER => tied_to_ground_i,
- RXCHBONDO => open,
- RXCHBONDSLAVE => tied_to_ground_i,
- RXENCHANSYNC => tied_to_ground_i,
- ------------------- Receive Ports - Clock Correction Ports -----------------
- RXCLKCORCNT => open,
- --------------- Receive Ports - Comma Detection and Alignment --------------
- RXBYTEISALIGNED => open,
- RXBYTEREALIGN => open,
- RXCOMMADET => open,
- RXCOMMADETUSE => tied_to_vcc_i,
- RXENMCOMMAALIGN => RXENMCOMMAALIGN_IN,
- RXENPCOMMAALIGN => RXENPCOMMAALIGN_IN,
- RXSLIDE => tied_to_ground_i,
- ----------------------- Receive Ports - PRBS Detection ---------------------
- PRBSCNTRESET => tied_to_ground_i,
- RXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
- RXPRBSERR => open,
- ------------------- Receive Ports - RX Data Path interface -----------------
- RXDATA => rxdata_i,
- RXRECCLK => RXRECCLK_OUT,
- RXRECCLKPCS => open,
- RXRESET => RXRESET_IN,
- RXUSRCLK => tied_to_ground_i,
- RXUSRCLK2 => RXUSRCLK2_IN,
- ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
- DFECLKDLYADJ => tied_to_ground_vec_i(5 downto 0),
- DFECLKDLYADJMON => open,
- DFEDLYOVRD => tied_to_ground_i,
- DFEEYEDACMON => open,
- DFESENSCAL => open,
- DFETAP1 => tied_to_ground_vec_i(4 downto 0),
- DFETAP1MONITOR => open,
- DFETAP2 => tied_to_ground_vec_i(4 downto 0),
- DFETAP2MONITOR => open,
- DFETAP3 => tied_to_ground_vec_i(3 downto 0),
- DFETAP3MONITOR => open,
- DFETAP4 => tied_to_ground_vec_i(3 downto 0),
- DFETAP4MONITOR => open,
- DFETAPOVRD => tied_to_vcc_i,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GATERXELECIDLE => tied_to_vcc_i,
- IGNORESIGDET => tied_to_vcc_i,
- RXCDRRESET => RXCDRRESET_IN,
- RXELECIDLE => open,
- RXEQMIX => "0000000000",
- RXN => RXN_IN,
- RXP => RXP_IN,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- RXBUFRESET => tied_to_ground_i,
- RXBUFSTATUS => open,
- RXCHANISALIGNED => open,
- RXCHANREALIGN => open,
- RXDLYALIGNDISABLE => RXDLYALIGNDISABLE_IN,
- RXDLYALIGNMONENB => RXDLYALIGNMONENB_IN,
- RXDLYALIGNMONITOR => RXDLYALIGNMONITOR_OUT,
- RXDLYALIGNOVERRIDE => RXDLYALIGNOVERRIDE_IN,
- RXDLYALIGNRESET => RXDLYALIGNRESET_IN,
- RXDLYALIGNSWPPRECURB => tied_to_vcc_i,
- RXDLYALIGNUPDSW => tied_to_ground_i,
- RXENPMAPHASEALIGN => RXENPMAPHASEALIGN_IN,
- RXPMASETPHASE => RXPMASETPHASE_IN,
- RXSTATUS => RXSTATUS_OUT,
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- RXLOSSOFSYNC => RXLOSSOFSYNC_OUT,
- ---------------------- Receive Ports - RX Oversampling ---------------------
- RXENSAMPLEALIGN => tied_to_ground_i,
- RXOVERSAMPLEERR => open,
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GREFCLKRX => tied_to_ground_i,
- GTXRXRESET => GTXRXRESET_IN,
- MGTREFCLKRX => MGTREFCLKRX_IN,
- NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
- PERFCLKRX => tied_to_ground_i,
- PLLRXRESET => PLLRXRESET_IN,
- RXPLLLKDET => RXPLLLKDET_OUT,
- RXPLLLKDETEN => tied_to_vcc_i,
- RXPLLPOWERDOWN => tied_to_ground_i,
- RXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
- RXRATE => tied_to_ground_vec_i(1 downto 0),
- RXRATEDONE => open,
- RXRESETDONE => RXRESETDONE_OUT,
- SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- PHYSTATUS => PHYSTATUS_OUT,
- RXVALID => open,
- ----------------- Receive Ports - RX Polarity Control Ports ----------------
- RXPOLARITY => tied_to_ground_i,
- --------------------- Receive Ports - RX Ports for SATA --------------------
- COMINITDET => open,
- COMSASDET => open,
- COMWAKEDET => open,
- ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
- DADDR => tied_to_ground_vec_i(7 downto 0),
- DCLK => tied_to_ground_i,
- DEN => tied_to_ground_i,
- DI => tied_to_ground_vec_i(15 downto 0),
- DRDY => open,
- DRPDO => open,
- DWE => tied_to_ground_i,
- -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
- TXGEARBOXREADY => open,
- TXHEADER => tied_to_ground_vec_i(2 downto 0),
- TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
- TXSTARTSEQ => tied_to_ground_i,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- TXBYPASS8B10B => tied_to_ground_vec_i(3 downto 0),
- TXCHARDISPMODE => tied_to_ground_vec_i(3 downto 0),
- TXCHARDISPVAL => tied_to_ground_vec_i(3 downto 0),
- TXCHARISK(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
- TXCHARISK(0) => TXCHARISK_IN,
- TXENC8B10BUSE => tied_to_vcc_i,
- TXKERR => open,
- TXRUNDISP => open,
- ------------------------- Transmit Ports - GTX Ports -----------------------
- GTXTEST => GTXTEST_IN,
- MGTREFCLKFAB => open,
- TSTCLK0 => tied_to_ground_i,
- TSTCLK1 => tied_to_ground_i,
- TSTIN => "11111111111111111111",
- TSTOUT => open,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- TXDATA => txdata_i,
- TXOUTCLK => TXOUTCLK_OUT,
- TXOUTCLKPCS => open,
- TXRESET => TXRESET_IN,
- TXUSRCLK => tied_to_ground_i,
- TXUSRCLK2 => TXUSRCLK2_IN,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- TXBUFDIFFCTRL => "100",
- TXDIFFCTRL => "1000",
- TXINHIBIT => tied_to_ground_i,
- TXN => TXN_OUT,
- TXP => TXP_OUT,
- TXPOSTEMPHASIS => "00000",
- --------------- Transmit Ports - TX Driver and OOB signalling --------------
- TXPREEMPHASIS => "0000",
- ----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
- TXBUFSTATUS => open,
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- TXDLYALIGNDISABLE => TXDLYALIGNDISABLE_IN,
- TXDLYALIGNMONENB => TXDLYALIGNMONENB_IN,
- TXDLYALIGNMONITOR => TXDLYALIGNMONITOR_OUT,
- TXDLYALIGNOVERRIDE => tied_to_ground_i,
- TXDLYALIGNRESET => TXDLYALIGNRESET_IN,
- TXDLYALIGNUPDSW => tied_to_ground_i,
- TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_IN,
- TXPMASETPHASE => TXPMASETPHASE_IN,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GREFCLKTX => tied_to_ground_i,
- GTXTXRESET => GTXTXRESET_IN,
- MGTREFCLKTX => MGTREFCLKTX_IN,
- NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
- PERFCLKTX => tied_to_ground_i,
- PLLTXRESET => PLLTXRESET_IN,
- SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
- TXPLLLKDET => TXPLLLKDET_OUT,
- TXPLLLKDETEN => tied_to_vcc_i,
- TXPLLPOWERDOWN => tied_to_ground_i,
- TXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
- TXRATE => tied_to_ground_vec_i(1 downto 0),
- TXRATEDONE => open,
- TXRESETDONE => TXRESETDONE_OUT,
- --------------------- Transmit Ports - TX PRBS Generator -------------------
- TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
- TXPRBSFORCEERR => tied_to_ground_i,
- -------------------- Transmit Ports - TX Polarity Control ------------------
- TXPOLARITY => tied_to_ground_i,
- ----------------- Transmit Ports - TX Ports for PCI Express ----------------
- TXDEEMPH => tied_to_ground_i,
- TXDETECTRX => tied_to_ground_i,
- TXELECIDLE => tied_to_ground_i,
- TXMARGIN => tied_to_ground_vec_i(2 downto 0),
- TXPDOWNASYNCH => tied_to_ground_i,
- TXSWING => tied_to_ground_i,
- --------------------- Transmit Ports - TX Ports for SATA -------------------
- COMFINISH => open,
- TXCOMINIT => tied_to_ground_i,
- TXCOMSAS => tied_to_ground_i,
- TXCOMWAKE => tied_to_ground_i
-\r
- );\r
- \r
- end RTL;\r
-\r
-\r
- \r
+++ /dev/null
-------------------------------------------------------------------------------\r
--- ____ ____ \r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : gtxvirtex6fee80_rx_sync.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module gtxvirtex6fee80_rx_sync\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
-entity gtxvirtex6fee80_rx_sync is\r
-port\r
-(\r
- RXENPMAPHASEALIGN : out std_logic;\r
- RXPMASETPHASE : out std_logic;\r
- RXDLYALIGNDISABLE : out std_logic;\r
- RXDLYALIGNOVERRIDE : out std_logic;\r
- RXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-\r
-\r
-end gtxvirtex6fee80_rx_sync;\r
-\r
-architecture RTL of gtxvirtex6fee80_rx_sync is\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
-\r
---*******************************Register Declarations************************\r
-\r
- signal begin_r : std_logic;\r
- signal phase_align_r : std_logic;\r
- signal ready_r : std_logic;\r
- signal sync_counter_r : unsigned(5 downto 0);\r
- signal sync_done_count_r : unsigned(5 downto 0);\r
- signal align_reset_counter_r : unsigned(4 downto 0);\r
- signal wait_after_sync_r : std_logic;\r
- signal wait_before_setphase_counter_r : unsigned(5 downto 0);\r
- signal wait_before_setphase_r : std_logic;\r
- signal align_reset_r : std_logic;\r
- \r
---*******************************Wire Declarations****************************\r
- \r
- signal count_32_setphase_complete_r : std_logic;\r
- signal count_32_wait_complete_r : std_logic;\r
- signal count_align_reset_complete_r : std_logic;\r
- signal next_phase_align_c : std_logic;\r
- signal next_align_reset_c : std_logic;\r
- signal next_ready_c : std_logic;\r
- signal next_wait_after_sync_c : std_logic;\r
- signal next_wait_before_setphase_c : std_logic;\r
- signal sync_32_times_done_r : std_logic;\r
- \r
- attribute max_fanout:string; \r
- attribute max_fanout of ready_r : signal is "2";\r
-\r
-begin\r
---*******************************Main Body of Code****************************\r
-\r
- --________________________________ State machine __________________________ \r
- -- This state machine manages the phase alingment procedure of the GTX on the\r
- -- receive side. The module is held in reset till the usrclk source is stable\r
- -- and RXRESETDONE is asserted. In the case that a MMCM is used to generate \r
- -- rxusrclk, the mmcm_locked signal is used to indicate a stable usrclk source.\r
- -- Once RXRESETDONE and mmcm_locked are asserted, the state machine goes \r
- -- into the align_reset_r state where RXDLYALIGNRESET is asserted for 20 cycles. \r
- -- After this, it goes into the wait_before_setphase_r state for 32 cycles. \r
- -- After asserting RXENPMAPHASEALIGN and waiting 32 cycles, it enters the \r
- -- phase_align_r state where RXPMASETPHASE is asserted for 32 clock cycles. \r
- -- After the port is deasserted, the state machine goes into a wait state for\r
- -- 32 cycles. This procedure is repeated 32 times.\r
- \r
- -- State registers\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(RESET='1') then\r
- begin_r <= '1' after DLY;\r
- align_reset_r <= '0' after DLY;\r
- wait_before_setphase_r <= '0' after DLY;\r
- phase_align_r <= '0' after DLY;\r
- wait_after_sync_r <= '0' after DLY;\r
- ready_r <= '0' after DLY;\r
- else\r
- begin_r <= '0' after DLY;\r
- align_reset_r <= next_align_reset_c after DLY;\r
- wait_before_setphase_r <= next_wait_before_setphase_c after DLY;\r
- phase_align_r <= next_phase_align_c after DLY;\r
- wait_after_sync_r <= next_wait_after_sync_c after DLY;\r
- ready_r <= next_ready_c after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Next state logic\r
- next_align_reset_c <= begin_r or\r
- (align_reset_r and not count_align_reset_complete_r);\r
- \r
- next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or\r
- (wait_before_setphase_r and not count_32_wait_complete_r); \r
- \r
- next_phase_align_c <= (wait_before_setphase_r and count_32_wait_complete_r) or\r
- (phase_align_r and not count_32_setphase_complete_r) or\r
- (wait_after_sync_r and count_32_wait_complete_r and not sync_32_times_done_r);\r
- \r
- next_wait_after_sync_c <= (phase_align_r and count_32_setphase_complete_r) or\r
- (wait_after_sync_r and not count_32_wait_complete_r);\r
-\r
- next_ready_c <= (wait_after_sync_r and count_32_wait_complete_r and sync_32_times_done_r) or\r
- ready_r;\r
-\r
- --______ Counter for holding RXDLYALIGNRESET for 20 RXUSRCLK2 cycles ______\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (align_reset_r='0') then\r
- align_reset_counter_r <= (others=>'0') after DLY;\r
- else\r
- align_reset_counter_r <= align_reset_counter_r + 1 after DLY;\r
- end if;\r
- end if ;\r
- end process;\r
- \r
- count_align_reset_complete_r <= align_reset_counter_r(4)\r
- and align_reset_counter_r(2);\r
- \r
- --_______Counter for waiting 32 clock cycles before RXPMASETPHASE _________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if ((wait_before_setphase_r='0') and (wait_after_sync_r='0')) then\r
- wait_before_setphase_counter_r <= (others=>'0') after DLY;\r
- else\r
- wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- count_32_wait_complete_r <= wait_before_setphase_counter_r(5);\r
- \r
- --_______________ Counter for holding SYNC for SYNC_CYCLES ________________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (phase_align_r='0') then\r
- sync_counter_r <= (others=>'0') after DLY;\r
- else\r
- sync_counter_r <= sync_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- count_32_setphase_complete_r <= sync_counter_r(5);\r
-\r
- --__________ Counter for counting number of times sync is done ____________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (RESET='1') then\r
- sync_done_count_r <= (others=>'0') after DLY;\r
- elsif((count_32_wait_complete_r ='1') and (phase_align_r = '1')) then\r
- sync_done_count_r <= sync_done_count_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- sync_32_times_done_r <= sync_done_count_r(5);\r
-\r
- --_______________ Assign the phase align ports into the GTX _______________\r
-\r
- RXDLYALIGNRESET <= align_reset_r;\r
- RXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);\r
- RXPMASETPHASE <= phase_align_r;\r
- RXDLYALIGNDISABLE <= '1';\r
- RXDLYALIGNOVERRIDE <= '1';\r
-\r
- --_______________________ Assign the sync_done port _______________________\r
- \r
- SYNC_DONE <= ready_r;\r
- \r
- \r
-end RTL;\r
+++ /dev/null
-------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx\r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : gtxvirtex6fee80_top.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module gtxVirtex6FEE80_top\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***********************************Entity Declaration************************\r
-\r
-entity gtxVirtex6FEE80_top is\r
-generic\r
-(\r
- EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 1;\r
- EXAMPLE_LANE_WITH_START_CHAR : integer := 0; -- specifies lane with unique start frame ch\r
- EXAMPLE_WORDS_IN_BRAM : integer := 512; -- specifies amount of data in BRAM\r
- EXAMPLE_SIM_GTXRESET_SPEEDUP : integer := 1; -- simulation setting for GTX SecureIP model\r
- EXAMPLE_USE_CHIPSCOPE : integer := 1 -- Set to 1 to use Chipscope to drive resets\r
-);\r
-port\r
-(\r
- Q3_CLK0_MGTREFCLK_PAD_N_IN : in std_logic;\r
- Q3_CLK0_MGTREFCLK_PAD_P_IN : in std_logic;\r
- GTXTXRESET_IN : in std_logic;\r
- GTXRXRESET_IN : in std_logic;\r
- TRACK_DATA_OUT : out std_logic;\r
- RXN_IN : in std_logic;\r
- RXP_IN : in std_logic;\r
- TXN_OUT : out std_logic;\r
- TXP_OUT : out std_logic\r
- \r
-);\r
-\r
-\r
-end gtxVirtex6FEE80_top;\r
- \r
-architecture RTL of gtxVirtex6FEE80_top is\r
-\r
---**************************Component Declarations*****************************\r
-\r
-\r
-component gtxVirtex6FEE80 \r
-generic\r
-(\r
- -- Simulation attributes\r
- WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
-);\r
-port\r
-(\r
-\r
- --_________________________________________________________________________\r
- --_________________________________________________________________________\r
- --GTX0 (X0_Y12)\r
-\r
- GTX0_DOUBLE_RESET_CLK_IN : in std_logic;\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GTX0_RXCHARISK_OUT : out std_logic;
- GTX0_RXDISPERR_OUT : out std_logic;
- GTX0_RXNOTINTABLE_OUT : out std_logic;
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GTX0_RXENMCOMMAALIGN_IN : in std_logic;
- GTX0_RXENPCOMMAALIGN_IN : in std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
- GTX0_RXRECCLK_OUT : out std_logic;
- GTX0_RXRESET_IN : in std_logic;
- GTX0_RXUSRCLK2_IN : in std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GTX0_RXCDRRESET_IN : in std_logic;
- GTX0_RXN_IN : in std_logic;
- GTX0_RXP_IN : in std_logic;
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
- GTX0_RXDLYALIGNMONENB_IN : in std_logic;
- GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
- GTX0_RXDLYALIGNRESET_IN : in std_logic;
- GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
- GTX0_RXPMASETPHASE_IN : in std_logic;
- GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTX0_GTXRXRESET_IN : in std_logic;
- GTX0_MGTREFCLKRX_IN : in std_logic;
- GTX0_PLLRXRESET_IN : in std_logic;
- GTX0_RXPLLLKDET_OUT : out std_logic;
- GTX0_RXRESETDONE_OUT : out std_logic;
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- GTX0_PHYSTATUS_OUT : out std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GTX0_TXCHARISK_IN : in std_logic;
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
- GTX0_TXOUTCLK_OUT : out std_logic;
- GTX0_TXRESET_IN : in std_logic;
- GTX0_TXUSRCLK2_IN : in std_logic;
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTX0_TXN_OUT : out std_logic;
- GTX0_TXP_OUT : out std_logic;
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
- GTX0_TXDLYALIGNMONENB_IN : in std_logic;
- GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
- GTX0_TXDLYALIGNRESET_IN : in std_logic;
- GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
- GTX0_TXPMASETPHASE_IN : in std_logic;
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTX0_GTXTXRESET_IN : in std_logic;
- GTX0_TXRESETDONE_OUT : out std_logic
-\r
-\r
-);\r
-end component;\r
-\r
-component MGT_USRCLK_SOURCE \r
-generic\r
-(\r
- FREQUENCY_MODE : string := "LOW"; \r
- PERFORMANCE_MODE : string := "MAX_SPEED" \r
-);\r
-port\r
-(\r
- DIV1_OUT : out std_logic;\r
- DIV2_OUT : out std_logic;\r
- DCM_LOCKED_OUT : out std_logic;\r
- CLK_IN : in std_logic;\r
- DCM_RESET_IN : in std_logic\r
-\r
-);\r
-end component;\r
-\r
-component FRAME_GEN \r
-generic\r
-(\r
- WORDS_IN_BRAM : integer := 256;\r
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-); \r
-port\r
-(\r
- -- User Interface\r
- TX_DATA : out std_logic_vector(39 downto 0);\r
- TX_CHARISK : out std_logic_vector(3 downto 0); \r
-\r
- -- System Interface\r
- USER_CLK : in std_logic;\r
- SYSTEM_RESET : in std_logic\r
-); \r
-end component;\r
-\r
-component FRAME_CHECK \r
-generic\r
-(\r
- RX_DATA_WIDTH : integer := 16;\r
- RXCTRL_WIDTH : integer := 2;\r
- USE_COMMA : integer := 1;\r
- NONE_MSB_FIRST_DEC : integer := 0;\r
- COMMA_DOUBLE_DEC : integer := 0;\r
- CHANBOND_SEQ_LEN : integer := 1;\r
- WORDS_IN_BRAM : integer := 256;\r
- CONFIG_INDEPENDENT_LANES : integer := 0;\r
- START_OF_PACKET_CHAR : std_logic_vector(15 downto 0) ;\r
- COMMA_DOUBLE_CHAR : std_logic_vector(15 downto 0) := x"f628";\r
- MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
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- MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
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- MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
- MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
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- MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
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-);\r
-port\r
-(\r
- -- User Interface\r
- RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
- \r
- RXCTRL_IN : in std_logic_vector((RXCTRL_WIDTH-1) downto 0); \r
- RX_ENMCOMMA_ALIGN : out std_logic;\r
- RX_ENPCOMMA_ALIGN : out std_logic;\r
- \r
- RX_ENCHAN_SYNC : out std_logic; \r
- RX_CHANBOND_SEQ : in std_logic; \r
-\r
- -- Control Interface\r
- INC_IN : in std_logic; \r
- INC_OUT : out std_logic; \r
- PATTERN_MATCH_N : out std_logic;\r
- RESET_ON_ERROR : in std_logic; \r
- \r
- -- Error Monitoring\r
- ERROR_COUNT : out std_logic_vector(7 downto 0);\r
- \r
- -- Track Data\r
- TRACK_DATA : out std_logic;\r
- \r
- -- System Interface\r
- USER_CLK : in std_logic;\r
- SYSTEM_RESET : in std_logic\r
- \r
-);\r
-end component;\r
-\r
-component MGT_USRCLK_SOURCE_MMCM\r
-generic\r
-(\r
- MULT : real := 2.0;\r
- DIVIDE : integer := 2; \r
- CLK_PERIOD : real := 6.4; \r
- OUT0_DIVIDE : real := 2.0;\r
- OUT1_DIVIDE : integer := 2;\r
- OUT2_DIVIDE : integer := 2;\r
- OUT3_DIVIDE : integer := 2\r
-);\r
-port\r
-(\r
- CLKFBOUT : out std_logic; \r
- CLK0_OUT : out std_logic;\r
- CLK1_OUT : out std_logic;\r
- CLK2_OUT : out std_logic;\r
- CLK3_OUT : out std_logic;\r
- CLK_IN : in std_logic;\r
- MMCM_LOCKED_OUT : out std_logic;\r
- MMCM_RESET_IN : in std_logic\r
-);\r
-end component;\r
-\r
-component gtxVirtex6FEE80_tx_sync\r
-generic\r
-(\r
- -- Simulation attributes\r
- SIM_TXPMASETPHASE_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
-);\r
-port\r
-(\r
- TXENPMAPHASEALIGN : out std_logic;\r
- TXPMASETPHASE : out std_logic;\r
- TXDLYALIGNDISABLE : out std_logic;\r
- TXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-end component;\r
-\r
-component gtxVirtex6FEE80_rx_sync\r
-port\r
-(\r
- RXENPMAPHASEALIGN : out std_logic;\r
- RXPMASETPHASE : out std_logic;\r
- RXDLYALIGNDISABLE : out std_logic;\r
- RXDLYALIGNOVERRIDE : out std_logic;\r
- RXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-end component;\r
-\r
-\r
--- Chipscope modules\r
-attribute syn_black_box : boolean;\r
-attribute syn_noprune : boolean;\r
-\r
-\r
-component data_vio\r
-port\r
-(\r
- control : inout std_logic_vector(35 downto 0);\r
- clk : in std_logic;\r
- async_in : in std_logic_vector(31 downto 0);\r
- async_out : out std_logic_vector(31 downto 0);\r
- sync_in : in std_logic_vector(31 downto 0);\r
- sync_out : out std_logic_vector(31 downto 0)\r
-);\r
-end component;\r
-attribute syn_black_box of data_vio : component is TRUE;\r
-attribute syn_noprune of data_vio : component is TRUE;\r
-\r
-\r
-component icon\r
-port\r
-(\r
- control0 : inout std_logic_vector(35 downto 0);\r
- control1 : inout std_logic_vector(35 downto 0);\r
- control2 : inout std_logic_vector(35 downto 0);\r
- control3 : inout std_logic_vector(35 downto 0)\r
-);\r
-end component;\r
-attribute syn_black_box of icon : component is TRUE;\r
-attribute syn_noprune of icon : component is TRUE;\r
-\r
-\r
-component ila\r
-port\r
-(\r
- control : inout std_logic_vector(35 downto 0);\r
- clk : in std_logic;\r
- trig0 : in std_logic_vector(84 downto 0)\r
-);\r
-end component;\r
-\r
-\r
-attribute syn_black_box of ila : component is TRUE;\r
-attribute syn_noprune of ila : component is TRUE;\r
-\r
-\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
- \r
- attribute max_fanout : string; \r
-\r
---************************** Register Declarations ****************************\r
-\r
- signal gtx0_txresetdone_r : std_logic;\r
- signal gtx0_txresetdone_r2 : std_logic;\r
- signal gtx0_rxresetdone_i_r : std_logic;\r
- signal gtx0_rxresetdone_r : std_logic;\r
- signal gtx0_rxresetdone_r2 : std_logic;\r
- signal gtx0_rxresetdone_r3 : std_logic;\r
- attribute max_fanout of gtx0_rxresetdone_i_r : signal is "1";\r
- signal gtx0_rxdata_r : std_logic_vector(7 downto 0);\r
- signal gtx0_rxcharisk_r : std_logic_vector(0 downto 0); \r
-\r
-\r
---**************************** Wire Declarations ******************************\r
- -------------------------- MGT Wrapper Wires ------------------------------\r
- --________________________________________________________________________\r
- --________________________________________________________________________\r
- --GTX0 (X0Y12)\r
-\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- signal gtx0_rxcharisk_i : std_logic;
- signal gtx0_rxdisperr_i : std_logic;
- signal gtx0_rxnotintable_i : std_logic;
- --------------- Receive Ports - Comma Detection and Alignment --------------
- signal gtx0_rxenmcommaalign_i : std_logic;
- signal gtx0_rxenpcommaalign_i : std_logic;
- ------------------- Receive Ports - RX Data Path interface -----------------
- signal gtx0_rxdata_i : std_logic_vector(7 downto 0);
- signal gtx0_rxrecclk_i : std_logic;
- signal gtx0_rxreset_i : std_logic;
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- signal gtx0_rxcdrreset_i : std_logic;
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- signal gtx0_rxdlyaligndisable_i : std_logic;
- signal gtx0_rxdlyalignmonenb_i : std_logic;
- signal gtx0_rxdlyalignmonitor_i : std_logic_vector(7 downto 0);
- signal gtx0_rxdlyalignoverride_i : std_logic;
- signal gtx0_rxdlyalignreset_i : std_logic;
- signal gtx0_rxenpmaphasealign_i : std_logic;
- signal gtx0_rxpmasetphase_i : std_logic;
- signal gtx0_rxstatus_i : std_logic_vector(2 downto 0);
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- signal gtx0_rxlossofsync_i : std_logic_vector(1 downto 0);
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- signal gtx0_gtxrxreset_i : std_logic;
- signal gtx0_pllrxreset_i : std_logic;
- signal gtx0_rxplllkdet_i : std_logic;
- signal gtx0_rxresetdone_i : std_logic;
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- signal gtx0_phystatus_i : std_logic;
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- signal gtx0_txcharisk_i : std_logic;
- ------------------ Transmit Ports - TX Data Path interface -----------------
- signal gtx0_txdata_i : std_logic_vector(7 downto 0);
- signal gtx0_txoutclk_i : std_logic;
- signal gtx0_txreset_i : std_logic;
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- signal gtx0_txdlyaligndisable_i : std_logic;
- signal gtx0_txdlyalignmonenb_i : std_logic;
- signal gtx0_txdlyalignmonitor_i : std_logic_vector(7 downto 0);
- signal gtx0_txdlyalignreset_i : std_logic;
- signal gtx0_txenpmaphasealign_i : std_logic;
- signal gtx0_txpmasetphase_i : std_logic;
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- signal gtx0_gtxtxreset_i : std_logic;
- signal gtx0_txresetdone_i : std_logic;
-\r
-\r
-\r
-\r
- signal gtx0_tx_system_reset_c : std_logic;\r
- signal gtx0_rx_system_reset_c : std_logic;\r
- signal gtx0_double_reset_clk_i : std_logic;\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);\r
- signal tied_to_vcc_i : std_logic;\r
- signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);\r
- signal drp_clk_in_i : std_logic;\r
- \r
-\r
- ----------------------------- User Clocks ---------------------------------\r
-\r
- signal gtx0_txusrclk2_i : std_logic;
- signal gtx0_rxusrclk2_i : std_logic;
- signal txoutclk_mmcm0_locked_i : std_logic;
- signal txoutclk_mmcm0_reset_i : std_logic;
- signal gtx0_txoutclk_to_mmcm_i : std_logic;
-\r
-\r
- ----------------------------- Reference Clocks ----------------------------\r
- \r
- signal q3_clk0_refclk_i : std_logic;\r
- signal q3_clk0_refclk_i_bufg : std_logic;\r
-\r
- ----------------------- Frame check/gen Module Signals --------------------\r
- \r
- signal gtx0_matchn_i : std_logic;\r
- \r
- signal gtx0_txcharisk_float_i : std_logic_vector(2 downto 0);\r
- \r
- signal gtx0_txdata_float_i : std_logic_vector(31 downto 0);\r
- \r
- signal gtx0_track_data_i : std_logic;\r
- signal gtx0_block_sync_i : std_logic;\r
- signal gtx0_error_count_i : std_logic_vector(7 downto 0);\r
- signal gtx0_frame_check_reset_i : std_logic;\r
- signal gtx0_inc_in_i : std_logic;\r
- signal gtx0_inc_out_i : std_logic;\r
- signal gtx0_unscrambled_data_i : std_logic_vector(7 downto 0);\r
-\r
- signal reset_on_data_error_i : std_logic;\r
- signal track_data_out_i : std_logic;\r
- \r
- \r
- ------------------------- Sync Module Signals -----------------------------\r
-\r
- signal gtx0_rx_sync_done_i : std_logic;\r
- signal gtx0_reset_rxsync_c : std_logic;\r
-\r
-\r
- signal gtx0_tx_sync_done_i : std_logic;\r
- signal gtx0_reset_txsync_c : std_logic;\r
-\r
- ----------------------- Chipscope Signals ---------------------------------\r
-\r
- signal tx_data_vio_control_i : std_logic_vector(35 downto 0);
- signal rx_data_vio_control_i : std_logic_vector(35 downto 0);
- signal shared_vio_control_i : std_logic_vector(35 downto 0);
- signal ila_control_i : std_logic_vector(35 downto 0);
- signal tx_data_vio_async_in_i : std_logic_vector(31 downto 0);
- signal tx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
- signal tx_data_vio_async_out_i : std_logic_vector(31 downto 0);
- signal tx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
- signal rx_data_vio_async_in_i : std_logic_vector(31 downto 0);
- signal rx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
- signal rx_data_vio_async_out_i : std_logic_vector(31 downto 0);
- signal rx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
- signal shared_vio_in_i : std_logic_vector(31 downto 0);
- signal shared_vio_out_i : std_logic_vector(31 downto 0);
- signal ila_in_i : std_logic_vector(84 downto 0);
-
- signal gtx0_tx_data_vio_async_in_i : std_logic_vector(31 downto 0);
- signal gtx0_tx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
- signal gtx0_tx_data_vio_async_out_i : std_logic_vector(31 downto 0);
- signal gtx0_tx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
- signal gtx0_rx_data_vio_async_in_i : std_logic_vector(31 downto 0);
- signal gtx0_rx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
- signal gtx0_rx_data_vio_async_out_i : std_logic_vector(31 downto 0);
- signal gtx0_rx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
- signal gtx0_ila_in_i : std_logic_vector(84 downto 0);
-
-\r
- signal gtxtxreset_i : std_logic;\r
- signal gtxrxreset_i : std_logic;\r
-\r
- signal user_tx_reset_i : std_logic;\r
- signal user_rx_reset_i : std_logic;\r
- signal tx_vio_clk_i : std_logic;\r
- signal tx_vio_clk_mux_out_i : std_logic;\r
- signal rx_vio_ila_clk_i : std_logic;\r
- signal rx_vio_ila_clk_mux_out_i : std_logic;\r
-\r
- \r
---**************************** Main Body of Code *******************************\r
-begin\r
-\r
- -- Static signal Assigments\r
- tied_to_ground_i <= '0';\r
- tied_to_ground_vec_i <= x"0000000000000000";\r
- tied_to_vcc_i <= '1';\r
- tied_to_vcc_vec_i <= x"ff";\r
-\r
-\r
-\r
- \r
- \r
-\r
- -----------------------Dedicated GTX Reference Clock Inputs ---------------\r
- -- The dedicated reference clock inputs you selected in the GUI are implemented using\r
- -- IBUFDS_GTXE1 instances.\r
- --\r
- -- In the UCF file for this example design, you will see that each of\r
- -- these IBUFDS_GTXE1 instances has been LOCed to a particular set of pins. By LOCing to these\r
- -- locations, we tell the tools to use the dedicated input buffers to the GTX reference\r
- -- clock network, rather than general purpose IOs. To select other pins, consult the \r
- -- Implementation chapter of UG___, or rerun the wizard.\r
- --\r
- -- This network is the highest performace (lowest jitter) option for providing clocks\r
- -- to the GTX transceivers.\r
- \r
- q3_clk0_refclk_ibufds_i : IBUFDS_GTXE1\r
- port map\r
- (\r
- O => q3_clk0_refclk_i,\r
- ODIV2 => open,\r
- CEB => tied_to_ground_i,\r
- I => Q3_CLK0_MGTREFCLK_PAD_P_IN,\r
- IB => Q3_CLK0_MGTREFCLK_PAD_N_IN\r
- );\r
-\r
- \r
-\r
- q3_clk0_refclk_bufg_i : BUFG\r
- port map\r
- (\r
- I => q3_clk0_refclk_i,\r
- O => q3_clk0_refclk_i_bufg\r
- );\r
-\r
- -----------------------Clock Input to Double Reset Module------------------\r
- gtx0_double_reset_clk_i <= q3_clk0_refclk_i_bufg;\r
-\r
-\r
- ----------------------------------- User Clocks ---------------------------\r
- \r
- -- The clock resources in this section were added based on userclk source selections on\r
- -- the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks:\r
- -- * The userclk and userclk2 for each GTX datapath (TX and RX) must be phase aligned to \r
- -- avoid data errors in the fabric interface whenever the datapath is wider than 10 bits\r
- -- * To minimize clock resources, you can share clocks between GTXs. GTXs using the same frequency\r
- -- or multiples of the same frequency can be accomadated using MMCMs. Use caution when\r
- -- using RXRECCLK as a clock source, however - these clocks can typically only be shared if all\r
- -- the channels using the clock are receiving data from TX channels that share a reference clock \r
- -- source with each other.\r
-\r
- txoutclk_mmcm0_reset_i <= not gtx0_rxplllkdet_i;
- txoutclk_mmcm0_i : MGT_USRCLK_SOURCE_MMCM
- generic map
- (
- MULT => 15.0,
- DIVIDE => 1,
- CLK_PERIOD => 12.5,
- OUT0_DIVIDE => 6.0,
- OUT1_DIVIDE => 1,
- OUT2_DIVIDE => 1,
- OUT3_DIVIDE => 1
- )
- port map
- (
- CLKFBOUT => open,
- CLK0_OUT => gtx0_txusrclk2_i,
- CLK1_OUT => open,
- CLK2_OUT => open,
- CLK3_OUT => open,
- CLK_IN => gtx0_txoutclk_i,
- MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
- MMCM_RESET_IN => txoutclk_mmcm0_reset_i
- );
-
-
- rxrecclk_bufr1_i : BUFR
- generic map
- (
- BUFR_DIVIDE => "BYPASS"
- )
- port map
- (
- CE => '1',
- CLR => '0',
- I => gtx0_rxrecclk_i,
- O => gtx0_rxusrclk2_i
- );
-
-
-\r
-\r
- ----------------------------- The GTX Wrapper -----------------------------\r
- \r
- -- Use the instantiation template in the example directory to add the GTX wrapper to your design.\r
- -- In this example, the wrapper is wired up for basic operation with a frame generator and frame \r
- -- checker. The GTXs will reset, then attempt to align and transmit data. If channel bonding is \r
- -- enabled, bonding should occur after alignment.\r
-\r
-\r
- gtxVirtex6FEE80_i : gtxVirtex6FEE80\r
- generic map\r
- (\r
- WRAPPER_SIM_GTXRESET_SPEEDUP => EXAMPLE_SIM_GTXRESET_SPEEDUP\r
- )\r
- port map\r
- (\r
- \r
- \r
- \r
- \r
-\r
- --_____________________________________________________________________\r
- --_____________________________________________________________________\r
- --GTX0 (X0Y12)\r
- GTX0_DOUBLE_RESET_CLK_IN => gtx0_double_reset_clk_i,\r
- ----------------------- Receive Ports - 8b10b Decoder ----------------------
- GTX0_RXCHARISK_OUT => gtx0_rxcharisk_i,
- GTX0_RXDISPERR_OUT => gtx0_rxdisperr_i,
- GTX0_RXNOTINTABLE_OUT => gtx0_rxnotintable_i,
- --------------- Receive Ports - Comma Detection and Alignment --------------
- GTX0_RXENMCOMMAALIGN_IN => gtx0_rxenmcommaalign_i,
- GTX0_RXENPCOMMAALIGN_IN => gtx0_rxenpcommaalign_i,
- ------------------- Receive Ports - RX Data Path interface -----------------
- GTX0_RXDATA_OUT => gtx0_rxdata_i,
- GTX0_RXRECCLK_OUT => gtx0_rxrecclk_i,
- GTX0_RXRESET_IN => gtx0_rxreset_i,
- GTX0_RXUSRCLK2_IN => gtx0_rxusrclk2_i,
- ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
- GTX0_RXCDRRESET_IN => gtx0_rxcdrreset_i,
- GTX0_RXN_IN => RXN_IN,
- GTX0_RXP_IN => RXP_IN,
- -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
- GTX0_RXDLYALIGNDISABLE_IN => gtx0_rxdlyaligndisable_i,
- GTX0_RXDLYALIGNMONENB_IN => gtx0_rxdlyalignmonenb_i,
- GTX0_RXDLYALIGNMONITOR_OUT => gtx0_rxdlyalignmonitor_i,
- GTX0_RXDLYALIGNOVERRIDE_IN => gtx0_rxdlyalignoverride_i,
- GTX0_RXDLYALIGNRESET_IN => gtx0_rxdlyalignreset_i,
- GTX0_RXENPMAPHASEALIGN_IN => gtx0_rxenpmaphasealign_i,
- GTX0_RXPMASETPHASE_IN => gtx0_rxpmasetphase_i,
- GTX0_RXSTATUS_OUT => gtx0_rxstatus_i,
- --------------- Receive Ports - RX Loss-of-sync State Machine --------------
- GTX0_RXLOSSOFSYNC_OUT => gtx0_rxlossofsync_i,
- ------------------------ Receive Ports - RX PLL Ports ----------------------
- GTX0_GTXRXRESET_IN => gtx0_gtxrxreset_i,
- GTX0_MGTREFCLKRX_IN => q3_clk0_refclk_i,
- GTX0_PLLRXRESET_IN => gtx0_pllrxreset_i,
- GTX0_RXPLLLKDET_OUT => gtx0_rxplllkdet_i,
- GTX0_RXRESETDONE_OUT => gtx0_rxresetdone_i,
- -------------- Receive Ports - RX Pipe Control for PCI Express -------------
- GTX0_PHYSTATUS_OUT => gtx0_phystatus_i,
- ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
- GTX0_TXCHARISK_IN => gtx0_txcharisk_i,
- ------------------ Transmit Ports - TX Data Path interface -----------------
- GTX0_TXDATA_IN => gtx0_txdata_i,
- GTX0_TXOUTCLK_OUT => gtx0_txoutclk_i,
- GTX0_TXRESET_IN => gtx0_txreset_i,
- GTX0_TXUSRCLK2_IN => gtx0_txusrclk2_i,
- ---------------- Transmit Ports - TX Driver and OOB signaling --------------
- GTX0_TXN_OUT => TXN_OUT,
- GTX0_TXP_OUT => TXP_OUT,
- -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
- GTX0_TXDLYALIGNDISABLE_IN => gtx0_txdlyaligndisable_i,
- GTX0_TXDLYALIGNMONENB_IN => gtx0_txdlyalignmonenb_i,
- GTX0_TXDLYALIGNMONITOR_OUT => gtx0_txdlyalignmonitor_i,
- GTX0_TXDLYALIGNRESET_IN => gtx0_txdlyalignreset_i,
- GTX0_TXENPMAPHASEALIGN_IN => gtx0_txenpmaphasealign_i,
- GTX0_TXPMASETPHASE_IN => gtx0_txpmasetphase_i,
- ----------------------- Transmit Ports - TX PLL Ports ----------------------
- GTX0_GTXTXRESET_IN => gtx0_gtxtxreset_i,
- GTX0_TXRESETDONE_OUT => gtx0_txresetdone_i
-\r
-\r
- );\r
-\r
- -- Hold the TX in reset till the TX user clocks are stable\r
- gtx0_txreset_i <= not txoutclk_mmcm0_locked_i;\r
-\r
- -- Hold the RX in reset till the RX user clocks are stable\r
- \r
- gtx0_rxreset_i <= not gtx0_rxplllkdet_i;\r
-\r
-\r
-\r
- ------------------------------ TXSYNC module ------------------------------\r
- -- The TXSYNC module performs phase synchronization for all the active TX datapaths. It\r
- -- waits for the user clocks to be stable, then drives the phase align signals on each\r
- -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
- \r
- -- Include the TX_SYNC module in your own design to perform phase synchronization if\r
- -- your protocol bypasses the TX Buffers\r
-\r
- \r
- \r
- gtx0_reset_txsync_c <= not gtx0_txresetdone_r2; \r
-\r
- -- SIM_TXPMASETPHASE_SPEEDUP is a simulation only attribute and MUST be set to 0 \r
- -- during implementation \r
- gtx0_txsync_i : gtxVirtex6FEE80_tx_sync\r
- generic map\r
- (\r
- SIM_TXPMASETPHASE_SPEEDUP => EXAMPLE_SIM_GTXRESET_SPEEDUP\r
- )\r
- port map\r
- (\r
- TXENPMAPHASEALIGN => gtx0_txenpmaphasealign_i,\r
- TXPMASETPHASE => gtx0_txpmasetphase_i,\r
- TXDLYALIGNDISABLE => gtx0_txdlyaligndisable_i,\r
- TXDLYALIGNRESET => gtx0_txdlyalignreset_i,\r
- SYNC_DONE => gtx0_tx_sync_done_i,\r
- USER_CLK => gtx0_txusrclk2_i,\r
- RESET => gtx0_reset_txsync_c\r
- );\r
-\r
- ---------------------------- RXSYNC modules -------------------------------\r
- -- The RXSYNC module performs phase synchronization for all the active RX datapaths. It\r
- -- waits for the user clocks to be stable, then drives the RX phase align signals on each\r
- -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
- \r
- -- Include one RX_SYNC module per Buffer bypassed RX datapath in your own design. RX_SYNC modules\r
- -- can also be shared, but when sharing, make sure to hold the module in reset until all lanes have \r
- -- a stable clock\r
- \r
- \r
- gtx0_rxsync_i : gtxVirtex6FEE80_rx_sync\r
- port map\r
- (\r
- RXENPMAPHASEALIGN => gtx0_rxenpmaphasealign_i,\r
- RXPMASETPHASE => gtx0_rxpmasetphase_i,\r
- RXDLYALIGNDISABLE => gtx0_rxdlyaligndisable_i,\r
- RXDLYALIGNOVERRIDE => gtx0_rxdlyalignoverride_i,\r
- RXDLYALIGNRESET => gtx0_rxdlyalignreset_i,\r
- SYNC_DONE => gtx0_rx_sync_done_i,\r
- USER_CLK => gtx0_rxusrclk2_i,\r
- RESET => gtx0_reset_rxsync_c\r
- );\r
- \r
- gtx0_reset_rxsync_c <= '1' when (gtx0_rxresetdone_r3 = '0') else '0';\r
- \r
-\r
-\r
- -------------------------- User Module Resets -----------------------------\r
- -- All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules\r
- -- are held in reset till the RESETDONE goes high. \r
- -- The RESETDONE is registered a couple of times on USRCLK2 and connected \r
- -- to the reset of the modules\r
- \r
- process( gtx0_rxusrclk2_i)\r
- begin\r
- if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
- gtx0_rxresetdone_i_r <= gtx0_rxresetdone_i after DLY;\r
- end if; \r
- end process; \r
-\r
- process( gtx0_rxusrclk2_i,gtx0_rxresetdone_i_r)\r
- begin\r
- if(gtx0_rxresetdone_i_r = '0') then\r
- gtx0_rxresetdone_r <= '0' after DLY;\r
- gtx0_rxresetdone_r2 <= '0' after DLY;\r
- elsif(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
- gtx0_rxresetdone_r <= gtx0_rxresetdone_i_r after DLY;\r
- gtx0_rxresetdone_r2 <= gtx0_rxresetdone_r after DLY;\r
- end if;\r
- end process;\r
-\r
- process( gtx0_rxusrclk2_i)\r
- begin\r
- if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
- gtx0_rxresetdone_r3 <= gtx0_rxresetdone_r2 after DLY;\r
- end if; \r
- end process; \r
-\r
- process( gtx0_txusrclk2_i,gtx0_txresetdone_i)\r
- begin\r
- if(gtx0_txresetdone_i = '0') then\r
- gtx0_txresetdone_r <= '0' after DLY;\r
- gtx0_txresetdone_r2 <= '0' after DLY;\r
- elsif(gtx0_txusrclk2_i'event and gtx0_txusrclk2_i = '1') then\r
- gtx0_txresetdone_r <= gtx0_txresetdone_i after DLY;\r
- gtx0_txresetdone_r2 <= gtx0_txresetdone_r after DLY;\r
- end if;\r
- end process;\r
-\r
-\r
- ------------------------------ Frame Generators ---------------------------\r
- -- The example design uses Block RAM based frame generators to provide test\r
- -- data to the GTXs for transmission. By default the frame generators are \r
- -- loaded with an incrementing data sequence that includes commas/alignment\r
- -- characters for alignment. If your protocol uses channel bonding, the \r
- -- frame generator will also be preloaded with a channel bonding sequence.\r
- \r
- -- You can modify the data transmitted by changing the INIT values of the frame\r
- -- generator in this file. Pay careful attention to bit order and the spacing\r
- -- of your control and alignment characters.\r
-\r
- gtx0_frame_gen : FRAME_GEN\r
- generic map\r
- (\r
- WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM,\r
- MEM_00 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_01 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_02 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_03 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_04 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_05 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_06 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_07 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_08 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_09 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_0A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_0B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_0C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_0D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_0E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_0F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_10 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_11 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_12 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_13 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_14 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_15 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_16 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_17 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_18 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_19 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_1A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_1B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_1C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_1D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_1E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_1F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_20 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_21 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_22 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_23 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_24 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_25 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_26 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_27 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_28 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_29 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_2A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_2B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_2C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_2D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_2E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_2F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_30 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_31 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_32 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_33 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_34 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_35 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_36 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_37 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_38 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_39 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_3A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_3B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_3C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_3D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_3E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_3F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEMP_00 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_02 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_04 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_06 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_07 => x"0000000000000000000000000000000000000000000000000000000000000000"\r
- )\r
- port map\r
- (\r
- -- User Interface\r
- TX_DATA(39 downto 8) => gtx0_txdata_float_i,\r
- TX_DATA(7 downto 0) => gtx0_txdata_i,\r
- \r
- TX_CHARISK(3 downto 1) => gtx0_txcharisk_float_i,\r
- TX_CHARISK(0) => gtx0_txcharisk_i,\r
- -- System Interface\r
- USER_CLK => gtx0_txusrclk2_i,\r
- SYSTEM_RESET => gtx0_tx_system_reset_c\r
- );\r
- \r
-\r
-\r
- ---------------------------------- Frame Checkers -------------------------\r
- -- The example design uses Block RAM based frame checkers to verify incoming \r
- -- data. By default the frame generators are loaded with a data sequence that \r
- -- matches the outgoing sequence of the frame generators for the TX ports.\r
- \r
- -- You can modify the expected data sequence by changing the INIT values of the frame\r
- -- checkers in this file. Pay careful attention to bit order and the spacing\r
- -- of your control and alignment characters.\r
- \r
- -- When the frame checker receives data, it attempts to synchronise to the \r
- -- incoming pattern by looking for the first sequence in the pattern. Once it \r
- -- finds the first sequence, it increments through the sequence, and indicates an \r
- -- error whenever the next value received does not match the expected value.\r
-\r
- gtx0_frame_check_reset_i <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else gtx0_matchn_i;\r
-\r
- -- gtx0_frame_check0 is always connected to the lane with the start of char\r
- -- and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off\r
- gtx0_inc_in_i <= '0';\r
-\r
- process(gtx0_rxusrclk2_i)\r
- begin \r
- if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then\r
- gtx0_rxdata_r <= gtx0_rxdata_i after DLY;\r
- end if;\r
- end process;\r
-\r
- process(gtx0_rxusrclk2_i)\r
- begin \r
- if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then\r
- gtx0_rxcharisk_r(0) <= gtx0_rxcharisk_i after DLY;\r
- end if;\r
- end process;\r
- \r
-\r
- \r
- \r
- gtx0_frame_check : FRAME_CHECK\r
- generic map\r
- (\r
- RX_DATA_WIDTH => 8,\r
- RXCTRL_WIDTH => 1,\r
- USE_COMMA => 1,\r
- WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM,\r
- CONFIG_INDEPENDENT_LANES => 1,\r
- START_OF_PACKET_CHAR => x"02bc",\r
- MEM_00 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_01 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_02 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_03 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_04 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_05 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_06 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_07 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_08 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_09 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_0A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_0B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_0C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_0D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_0E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_0F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_10 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_11 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_12 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_13 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_14 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_15 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_16 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_17 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_18 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_19 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_1A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_1B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_1C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_1D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_1E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_1F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_20 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_21 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_22 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_23 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_24 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_25 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_26 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_27 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_28 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_29 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_2A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_2B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_2C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_2D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_2E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_2F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEM_30 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
- MEM_31 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
- MEM_32 => x"000000160000001500000014000000130000001200000011000000100000000f",
- MEM_33 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
- MEM_34 => x"000000260000002500000024000000230000002200000021000000200000001f",
- MEM_35 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
- MEM_36 => x"000000360000003500000034000000330000003200000031000000300000002f",
- MEM_37 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
- MEM_38 => x"000000460000004500000044000000430000004200000041000000400000003f",
- MEM_39 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
- MEM_3A => x"000000560000005500000054000000530000005200000051000000500000004f",
- MEM_3B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
- MEM_3C => x"000000660000006500000064000000630000006200000061000000600000005f",
- MEM_3D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
- MEM_3E => x"000000760000007500000074000000730000007200000071000000700000006f",
- MEM_3F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
- MEMP_00 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_02 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_04 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
- MEMP_06 => x"0000000000000000000000000000000000000000000000000000000000000100",
- MEMP_07 => x"0000000000000000000000000000000000000000000000000000000000000000"\r
- )\r
- port map\r
- (\r
- -- MGT Interface\r
- RX_DATA => gtx0_rxdata_r,\r
- RXCTRL_IN => gtx0_rxcharisk_r,\r
- RX_ENMCOMMA_ALIGN => gtx0_rxenmcommaalign_i,\r
- RX_ENPCOMMA_ALIGN => gtx0_rxenpcommaalign_i,\r
- RX_ENCHAN_SYNC => open,\r
- RX_CHANBOND_SEQ => tied_to_ground_i,\r
- -- Control Interface\r
- INC_IN => gtx0_inc_in_i,\r
- INC_OUT => gtx0_inc_out_i,\r
- PATTERN_MATCH_N => gtx0_matchn_i,\r
- RESET_ON_ERROR => gtx0_frame_check_reset_i,\r
- -- System Interface\r
- USER_CLK => gtx0_rxusrclk2_i,\r
- SYSTEM_RESET => gtx0_rx_system_reset_c,\r
- ERROR_COUNT => gtx0_error_count_i,\r
- TRACK_DATA => gtx0_track_data_i\r
- );\r
- \r
-\r
-\r
- TRACK_DATA_OUT <= track_data_out_i;\r
-\r
- track_data_out_i <= \r
- gtx0_track_data_i ;\r
-\r
-\r
-\r
- ----------------------------- Chipscope Connections -----------------------\r
- -- When the example design is run in hardware, it uses chipscope to allow the\r
- -- example design and GTX wrapper to be controlled and monitored. The \r
- -- EXAMPLE_USE_CHIPSCOPE parameter allows chipscope to be removed for simulation.\r
- \r
-chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate\r
- \r
- \r
- -- Shared VIO for all transievers \r
- shared_vio_i : data_vio\r
- port map\r
- (\r
- control => shared_vio_control_i,\r
- clk => tied_to_ground_i,\r
- async_in => shared_vio_in_i,\r
- async_out => shared_vio_out_i,\r
- sync_in => tied_to_ground_vec_i(31 downto 0),\r
- sync_out => open\r
- );\r
- \r
- -- ICON for all VIOs \r
- i_icon : icon\r
- port map\r
- (\r
- control0 => shared_vio_control_i,\r
- control1 => tx_data_vio_control_i,\r
- control2 => rx_data_vio_control_i,\r
- control3 => ila_control_i\r
- );\r
-\r
- \r
- -- TX VIO \r
- tx_data_vio_i : data_vio\r
- port map\r
- (\r
- control => tx_data_vio_control_i,\r
- clk => gtx0_txusrclk2_i,\r
- async_in => tx_data_vio_async_in_i,\r
- async_out => tx_data_vio_async_out_i,\r
- sync_in => tx_data_vio_sync_in_i,\r
- sync_out => tx_data_vio_sync_out_i\r
- );\r
- \r
- -- RX VIO \r
- rx_data_vio_i : data_vio\r
- port map\r
- (\r
- control => rx_data_vio_control_i,\r
- clk => gtx0_rxusrclk2_i,\r
- async_in => rx_data_vio_async_in_i,\r
- async_out => rx_data_vio_async_out_i,\r
- sync_in => rx_data_vio_sync_in_i,\r
- sync_out => rx_data_vio_sync_out_i\r
- );\r
- \r
- -- RX ILA\r
- ila_i : ila\r
- port map\r
- (\r
- control => ila_control_i,\r
- clk => gtx0_rxusrclk2_i,\r
- trig0 => ila_in_i\r
- );\r
-\r
-\r
-\r
- -- assign resets for frame_gen modules\r
- gtx0_tx_system_reset_c <= not gtx0_tx_sync_done_i or user_tx_reset_i;\r
- -- assign resets for frame_check modules\r
- gtx0_rx_system_reset_c <= not gtx0_rx_sync_done_i or user_rx_reset_i;\r
-\r
- gtx0_gtxtxreset_i <= gtxtxreset_i or gtxrxreset_i;\r
- gtx0_gtxrxreset_i <= gtxtxreset_i or gtxrxreset_i;\r
-
- -- Shared VIO Outputs
- gtxtxreset_i <= shared_vio_out_i(31);
- gtxrxreset_i <= shared_vio_out_i(30);
- user_tx_reset_i <= shared_vio_out_i(29);
- user_rx_reset_i <= shared_vio_out_i(28);
-
- -- Shared VIO Inputs
- shared_vio_in_i(31 downto 0) <= "00000000000000000000000000000000";
-
- -- Chipscope connections on GTX 0
- gtx0_tx_data_vio_async_in_i(31) <= '0';
- gtx0_tx_data_vio_async_in_i(30) <= gtx0_txresetdone_i;
- gtx0_tx_data_vio_async_in_i(29 downto 22) <= gtx0_txdlyalignmonitor_i;
- gtx0_tx_data_vio_async_in_i(21 downto 0) <= "0000000000000000000000";
- gtx0_tx_data_vio_sync_in_i(31 downto 0) <= "00000000000000000000000000000000";
- gtx0_txdlyalignmonenb_i <= tx_data_vio_async_out_i(30);
- gtx0_rx_data_vio_async_in_i(31) <= gtx0_rxplllkdet_i;
- gtx0_rx_data_vio_async_in_i(30) <= gtx0_rxresetdone_i;
- gtx0_rx_data_vio_async_in_i(29 downto 22) <= gtx0_rxdlyalignmonitor_i;
- gtx0_rx_data_vio_async_in_i(21 downto 0) <= "0000000000000000000000";
- gtx0_rx_data_vio_sync_in_i(31 downto 0) <= "00000000000000000000000000000000";
- gtx0_pllrxreset_i <= rx_data_vio_async_out_i(31);
- gtx0_rxcdrreset_i <= rx_data_vio_async_out_i(30);
- gtx0_ila_in_i(84) <= gtx0_rxcharisk_i;
- gtx0_ila_in_i(83) <= gtx0_rxdisperr_i;
- gtx0_ila_in_i(82) <= gtx0_rxnotintable_i;
- gtx0_ila_in_i(81 downto 74) <= gtx0_rxdata_i;
- gtx0_ila_in_i(73 downto 71) <= gtx0_rxstatus_i;
- gtx0_ila_in_i(70 downto 69) <= gtx0_rxlossofsync_i;
- gtx0_ila_in_i(68) <= gtx0_phystatus_i;
- gtx0_ila_in_i(67 downto 60) <= gtx0_error_count_i;
- gtx0_ila_in_i(59 downto 0) <= "000000000000000000000000000000000000000000000000000000000000";
-\r
-\r
-\r
- tx_data_vio_async_in_i <= gtx0_tx_data_vio_async_in_i;
-\r
-\r
- tx_data_vio_sync_in_i <= gtx0_tx_data_vio_sync_in_i;
-\r
- rx_data_vio_async_in_i <= gtx0_rx_data_vio_async_in_i;
-\r
-\r
- rx_data_vio_sync_in_i <= gtx0_rx_data_vio_sync_in_i;
-\r
-\r
- ila_in_i <= gtx0_ila_in_i;
-\r
-\r
-end generate chipscope;\r
-\r
-\r
-no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate\r
-\r
- -- If Chipscope is not being used, drive GTX reset signal\r
- -- from the top level ports\r
- gtx0_gtxtxreset_i <= GTXTXRESET_IN;\r
- gtx0_gtxrxreset_i <= GTXRXRESET_IN;\r
-\r
- -- assign resets for frame_gen modules\r
- gtx0_tx_system_reset_c <= not gtx0_tx_sync_done_i;\r
- -- assign resets for frame_check modules\r
- gtx0_rx_system_reset_c <= not gtx0_rx_sync_done_i;\r
-\r
- gtxtxreset_i <= tied_to_ground_i;
- gtxrxreset_i <= tied_to_ground_i;
- user_tx_reset_i <= tied_to_ground_i;
- user_rx_reset_i <= tied_to_ground_i;
- gtx0_txdlyalignmonenb_i <= tied_to_ground_i;
- gtx0_pllrxreset_i <= tied_to_ground_i;
- gtx0_rxcdrreset_i <= tied_to_ground_i;
-\r
-\r
-\r
-end generate no_chipscope;\r
-\r
-\r
-end RTL;\r
-\r
-\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor: Xilinx\r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
--- / / Filename : gtxvirtex6fee80_tx_sync.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\\r
---\r
---\r
--- Module gtxvirtex6fee80_tx_sync\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
-entity gtxvirtex6fee80_tx_sync is\r
-generic\r
-(\r
- SIM_TXPMASETPHASE_SPEEDUP : integer:=0\r
-); \r
-port\r
-(\r
- TXENPMAPHASEALIGN : out std_logic;\r
- TXPMASETPHASE : out std_logic;\r
- TXDLYALIGNDISABLE : out std_logic;\r
- TXDLYALIGNRESET : out std_logic;\r
- SYNC_DONE : out std_logic;\r
- USER_CLK : in std_logic;\r
- RESET : in std_logic\r
-);\r
-\r
-\r
-end gtxvirtex6fee80_tx_sync;\r
-\r
-architecture RTL of gtxvirtex6fee80_tx_sync is\r
---***********************************Parameter Declarations********************\r
-\r
- constant DLY : time := 1 ns;\r
-\r
---*******************************Register Declarations************************\r
-\r
- signal begin_r : std_logic;\r
- signal phase_align_r : std_logic;\r
- signal ready_r : std_logic;\r
- signal sync_counter_r : unsigned(15 downto 0);\r
- signal wait_before_setphase_counter_r : unsigned(5 downto 0);\r
- signal align_reset_counter_r : unsigned(4 downto 0);\r
- signal wait_before_setphase_r : std_logic;\r
- signal align_reset_r : std_logic;\r
- \r
---*******************************Wire Declarations****************************\r
- \r
- signal count_setphase_complete_r : std_logic;\r
- signal count_32_complete_r : std_logic;\r
- signal count_align_reset_complete_r : std_logic;\r
- signal next_phase_align_c : std_logic;\r
- signal next_ready_c : std_logic;\r
- signal next_wait_before_setphase_c : std_logic;\r
- signal next_align_reset_c : std_logic;\r
-\r
-begin\r
---*******************************Main Body of Code****************************\r
-\r
- --________________________________ State machine __________________________ \r
- -- This state machine manages the TX phase alignment procedure of the GTX.\r
- -- The module is held in reset till TXRESETDONE is asserted. Once TXRESETDONE \r
- -- is asserted, the state machine goes into the align_reset_r state, asserting\r
- -- TXDLYALIGNRESET for 20 TXUSRCLK2 cycles. After this, it goes into the \r
- -- wait_before_setphase_r state for 32 cycles. After asserting TXENPMAPHASEALIGN and \r
- -- waiting 32 cycles, it goes into the phase_align_r state where the last \r
- -- part of the alignment procedure is completed. This involves asserting \r
- -- TXPMASETPHASE for 8192 (TXPLL_DIVSEL_OUT=1), 16384 (TXPLL_DIVSEL_OUT=2), \r
- -- or 32768 (TXPLL_DIVSEL_OUT=4) clock cycles. After completion of the phase \r
- -- alignment procedure, TXDLYALIGNDISABLE is deasserted.\r
- \r
- -- State registers\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if(RESET='1') then\r
- begin_r <= '1' after DLY;\r
- align_reset_r <= '0' after DLY;\r
- wait_before_setphase_r <= '0' after DLY;\r
- phase_align_r <= '0' after DLY;\r
- ready_r <= '0' after DLY;\r
- else\r
- begin_r <= '0' after DLY;\r
- align_reset_r <= next_align_reset_c after DLY;\r
- wait_before_setphase_r <= next_wait_before_setphase_c after DLY;\r
- phase_align_r <= next_phase_align_c after DLY;\r
- ready_r <= next_ready_c after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- -- Next state logic\r
- next_align_reset_c <= begin_r or \r
- (align_reset_r and not count_align_reset_complete_r);\r
- \r
- next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or \r
- (wait_before_setphase_r and not count_32_complete_r);\r
- \r
- next_phase_align_c <= (wait_before_setphase_r and count_32_complete_r) or\r
- (phase_align_r and not count_setphase_complete_r);\r
- \r
- next_ready_c <= (phase_align_r and count_setphase_complete_r) or\r
- ready_r;\r
-\r
- --______ Counter for holding TXDLYALIGNRESET for 20 TXUSRCLK2 cycles ______\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (align_reset_r='0') then\r
- align_reset_counter_r <= (others=>'0') after DLY;\r
- else\r
- align_reset_counter_r <= align_reset_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
- \r
- count_align_reset_complete_r <= align_reset_counter_r(4) \r
- and align_reset_counter_r(2);\r
-\r
- --______ Counter for waiting 32 clock cycles before TXPMASETPHASE _________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (wait_before_setphase_r='0') then\r
- wait_before_setphase_counter_r <= (others=>'0') after DLY;\r
- else\r
- wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
- count_32_complete_r <= wait_before_setphase_counter_r(5);\r
-\r
- --_______________ Counter for holding SYNC for SYNC_CYCLES ________________\r
- process( USER_CLK )\r
- begin\r
- if(USER_CLK'event and USER_CLK = '1') then\r
- if (phase_align_r='0') then\r
- sync_counter_r <= (others=>'0') after DLY;\r
- else\r
- sync_counter_r <= sync_counter_r + 1 after DLY;\r
- end if;\r
- end if;\r
- end process;\r
-\r
-fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=1) generate\r
- -- 64 cycles of setphase for simulation\r
- count_setphase_complete_r <= sync_counter_r(6);\r
-end generate fast_simulation;\r
-\r
-no_fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=0) generate\r
- -- 16384 cycles of setphase for output divider of 2\r
- count_setphase_complete_r <= sync_counter_r(14);\r
-end generate no_fast_simulation;\r
-\r
- --_______________ Assign the phase align ports into the GTX _______________\r
-\r
- TXDLYALIGNRESET <= '0';\r
- TXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);\r
- TXPMASETPHASE <= phase_align_r;\r
- TXDLYALIGNDISABLE <= '1';\r
-\r
- --_______________________ Assign the sync_done port _______________________\r
- \r
- SYNC_DONE <= ready_r;\r
- \r
- \r
-end RTL;\r
+++ /dev/null
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-XILINX-XDM V1.5e
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+++ /dev/null
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\7fM4d<2we;4>50;3xL7e33td<5<4?:0yK6f2<ug=2>7>51zJ1g1=zf>386=4>{I0`0>{i?0>1<7?tH3a7?xh01<0;6<uG2b68yk1>>3:1=vF=c59~j2?0290:wE<l4:
\7fm3<>=83;pD?m;;|l4=<<728qC>n:4}o5:e?6=9rB9o95rn6;a>5<6sA8h86sa78a94?7|@;i?7p`89e83>4}O:j>0qc96e;295~N5k=1vb:7i:182
\7fM4d<2we;l>50;3xL7e33td<m<4?:0yK6f2<ug=j>7>51zJ1g1=zf>k86=4>{I0`0>{i?h>1<7?tH3a7?xh0i<0;6<uG2b68yk1f>3:1=vF=c59~j2g0290:wE<l4:
\7fm3d>=83;pD?m;;|l4e<<728qC>n:4}o5be?6=9rB9o95rn6ca>5<6sA8h86sa7`a94?7|@;i?7p`8ae83>4}O:j>0qc9ne;295~N5k=1vb:oi:182
\7fM4d<2we;o>50;3xL7e33td<n<4?:0yK6f2<ug=i>7>51zJ1g1=zf>h86=4>{I0`0>{i?k>1<7?tH3a7?xh0j<0;6<uG2b68yk1e>3:1=vF=c59~j2d0290:wE<l4:
\7fm3g>=83;pD?m;;|l4f<<728qC>n:4}o5ae?6=9rB9o95rn6`a>5<6sA8h86sa7ca94?7|@;i?7p`8be83>4}O:j>0qc9me;295~N5k=1vb:li:182
\7fM4d<2we;n>50;3xL7e33td<o<4?:0yK56?<@8937E<l4:
\7f~yxFGKr2o;7?643g5b0{GHKq;qMN_{|BC
\ No newline at end of file
+++ /dev/null
-NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;\r
-TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;\r
-#Update Constraints\r
-NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;\r
-NET "U0/iSHIFT_OUT" TIG ;\r
-TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;\r
-TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;\r
-TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;\r
-TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- Copyright (c) 2014 Xilinx, Inc.\r
--- All Rights Reserved\r
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor : Xilinx\r
--- \ \ \/ Version : 14.7\r
--- \ \ Application: XILINX CORE Generator\r
--- / / Filename : icon0.vhd\r
--- /___/ /\ Timestamp : Tue Nov 25 11:13:40 W. Europe Standard Time 2014\r
--- \ \ / \\r
--- \___\/\___\\r
---\r
--- Design Name: VHDL Synthesis Wrapper\r
--------------------------------------------------------------------------------\r
--- This wrapper is used to integrate with Project Navigator and PlanAhead\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-ENTITY icon0 IS\r
- port (\r
- CONTROL0: inout std_logic_vector(35 downto 0);\r
- CONTROL1: inout std_logic_vector(35 downto 0);\r
- CONTROL2: inout std_logic_vector(35 downto 0);\r
- CONTROL3: inout std_logic_vector(35 downto 0);\r
- CONTROL4: inout std_logic_vector(35 downto 0));\r
-END icon0;\r
-\r
-ARCHITECTURE icon0_a OF icon0 IS\r
-BEGIN\r
-\r
-END icon0_a;\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- Copyright (c) 2014 Xilinx, Inc.\r
--- All Rights Reserved\r
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor : Xilinx\r
--- \ \ \/ Version : 14.7\r
--- \ \ Application: Xilinx CORE Generator\r
--- / / Filename : icon0.vho\r
--- /___/ /\ Timestamp : Tue Nov 25 11:13:40 W. Europe Standard Time 2014\r
--- \ \ / \\r
--- \___\/\___\\r
---\r
--- Design Name: ISE Instantiation template\r
--- Component Identifier: xilinx.com:ip:chipscope_icon:1.06.a\r
--------------------------------------------------------------------------------\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-component icon0\r
- PORT (\r
- CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- CONTROL2 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- CONTROL3 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- CONTROL4 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));\r
-\r
-end component;\r
-\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-\r
-your_instance_name : icon0\r
- port map (\r
- CONTROL0 => CONTROL0,\r
- CONTROL1 => CONTROL1,\r
- CONTROL2 => CONTROL2,\r
- CONTROL3 => CONTROL3,\r
- CONTROL4 => CONTROL4);\r
-\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Tue Nov 25 10:12:59 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Structural\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a\r
-# END Select\r
-# BEGIN Parameters\r
-CSET component_name=icon0\r
-CSET constraint_type=embedded\r
-CSET enable_jtag_bufg=true\r
-CSET example_design=false\r
-CSET number_control_ports=5\r
-CSET use_ext_bscan=false\r
-CSET use_softbscan=false\r
-CSET use_unused_bscan=false\r
-CSET user_scan_chain=USER1\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2013-10-13T14:12:40Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: e48a616b\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="icon0.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="icon0.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- </file>
- <file xil_pn:name="icon0.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|icon0|icon0_a" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="icon0.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/icon0" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="icon0" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-25T11:13:50" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="21555AEE3F8341188AED62B4D711BFDF" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings>
- <binding xil_pn:location="/icon0" xil_pn:name="icon0.ucf"/>
- </bindings>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-The following files were generated for 'icon0' in directory\r
-D:\Xilinx_proj\Panda\Xilinx\FrontEndElectronics\FEE_V2_ADC32board_SODA2\ipcore_dir\\r
-\r
-XCO file generator:\r
- Generate an XCO file for compatibility with legacy flows.\r
-\r
- * icon0.xco\r
-\r
-Creates an implementation netlist:\r
- Creates an implementation netlist for the IP.\r
-\r
- * icon0.ngc\r
- * icon0.ucf\r
- * icon0.vhd\r
- * icon0.vho\r
-\r
-Creates an HDL instantiation template:\r
- Creates an HDL instantiation template for the IP.\r
-\r
- * icon0.vho\r
-\r
-IP Symbol Generator:\r
- Generate an IP symbol based on the current project options'.\r
-\r
- * icon0.asy\r
-\r
-SYM file generator:\r
- Generate a SYM file for compatibility with legacy flows\r
-\r
- * icon0.sym\r
-\r
-Generate ISE metadata:\r
- Create a metadata file for use when including this core in ISE designs\r
-\r
- * icon0_xmdf.tcl\r
-\r
-Generate ISE subproject:\r
- Create an ISE subproject for use when including this core in ISE designs\r
-\r
- * _xmsgs/pn_parser.xmsgs\r
- * icon0.gise\r
- * icon0.xise\r
-\r
-Deliver Readme:\r
- Readme file for the IP.\r
-\r
- * icon0_readme.txt\r
-\r
-Generate FLIST file:\r
- Text file listing all of the output files produced when a customized core was\r
- generated in the CORE Generator.\r
-\r
- * icon0_flist.txt\r
-\r
-Please see the Xilinx CORE Generator online help for further details on\r
-generated files and how to use them.\r
-\r
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$c`e
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\ No newline at end of file
+++ /dev/null
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 ila128
-RECTANGLE Normal 32 32 288 704
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName control[35:0]
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Wide 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName trig0[127:0]
-PINATTR Polarity IN
-\r
+++ /dev/null
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\7f5{GHYqvLM
\ No newline at end of file
+++ /dev/null
--------------------------------------------------------------------------------\r
--- Copyright (c) 2012 Xilinx, Inc.\r
--- All Rights Reserved\r
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor : Xilinx\r
--- \ \ \/ Version : 13.3\r
--- \ \ Application: XILINX CORE Generator\r
--- / / Filename : ila128.vhd\r
--- /___/ /\ Timestamp : Thu Jul 19 13:26:41 W. Europe Daylight Time 2012\r
--- \ \ / \\r
--- \___\/\___\\r
---\r
--- Design Name: VHDL Synthesis Wrapper\r
--------------------------------------------------------------------------------\r
--- This wrapper is used to integrate with Project Navigator and PlanAhead\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-ENTITY ila128 IS\r
- port (\r
- CONTROL: inout std_logic_vector(35 downto 0);\r
- CLK: in std_logic;\r
- TRIG0: in std_logic_vector(127 downto 0));\r
-END ila128;\r
-\r
-ARCHITECTURE ila128_a OF ila128 IS\r
-BEGIN\r
-\r
-END ila128_a;\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- Copyright (c) 2012 Xilinx, Inc.\r
--- All Rights Reserved\r
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor : Xilinx\r
--- \ \ \/ Version : 13.3\r
--- \ \ Application: Xilinx CORE Generator\r
--- / / Filename : ila128.vho\r
--- /___/ /\ Timestamp : Thu Jul 19 13:26:41 W. Europe Daylight Time 2012\r
--- \ \ / \\r
--- \___\/\___\\r
---\r
--- Design Name: ISE Instantiation template\r
--- Component Identifier: xilinx.com:ip:chipscope_ila:1.05.a\r
--------------------------------------------------------------------------------\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-component ila128\r
- PORT (\r
- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- CLK : IN STD_LOGIC;\r
- TRIG0 : IN STD_LOGIC_VECTOR(127 DOWNTO 0));\r
-\r
-end component;\r
-\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-\r
-your_instance_name : ila128\r
- port map (\r
- CONTROL => CONTROL,\r
- CLK => CLK,\r
- TRIG0 => TRIG0);\r
-\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 13.3\r
-# Date: Thu Jul 19 11:24:45 2012\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Structural\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a\r
-# END Select\r
-# BEGIN Parameters\r
-CSET check_bramcount=false\r
-CSET component_name=ila128\r
-CSET constraint_type=embedded\r
-CSET counter_width_1=Disabled\r
-CSET counter_width_10=Disabled\r
-CSET counter_width_11=Disabled\r
-CSET counter_width_12=Disabled\r
-CSET counter_width_13=Disabled\r
-CSET counter_width_14=Disabled\r
-CSET counter_width_15=Disabled\r
-CSET counter_width_16=Disabled\r
-CSET counter_width_2=Disabled\r
-CSET counter_width_3=Disabled\r
-CSET counter_width_4=Disabled\r
-CSET counter_width_5=Disabled\r
-CSET counter_width_6=Disabled\r
-CSET counter_width_7=Disabled\r
-CSET counter_width_8=Disabled\r
-CSET counter_width_9=Disabled\r
-CSET data_port_width=0\r
-CSET data_same_as_trigger=true\r
-CSET disable_save_keep=false\r
-CSET enable_storage_qualification=true\r
-CSET enable_trigger_output_port=false\r
-CSET example_design=false\r
-CSET exclude_from_data_storage_1=false\r
-CSET exclude_from_data_storage_10=false\r
-CSET exclude_from_data_storage_11=false\r
-CSET exclude_from_data_storage_12=false\r
-CSET exclude_from_data_storage_13=false\r
-CSET exclude_from_data_storage_14=false\r
-CSET exclude_from_data_storage_15=false\r
-CSET exclude_from_data_storage_16=false\r
-CSET exclude_from_data_storage_2=false\r
-CSET exclude_from_data_storage_3=false\r
-CSET exclude_from_data_storage_4=false\r
-CSET exclude_from_data_storage_5=false\r
-CSET exclude_from_data_storage_6=false\r
-CSET exclude_from_data_storage_7=false\r
-CSET exclude_from_data_storage_8=false\r
-CSET exclude_from_data_storage_9=false\r
-CSET match_type_1=basic_with_edges\r
-CSET match_type_10=basic_with_edges\r
-CSET match_type_11=basic_with_edges\r
-CSET match_type_12=basic_with_edges\r
-CSET match_type_13=basic_with_edges\r
-CSET match_type_14=basic_with_edges\r
-CSET match_type_15=basic_with_edges\r
-CSET match_type_16=basic_with_edges\r
-CSET match_type_2=basic_with_edges\r
-CSET match_type_3=basic_with_edges\r
-CSET match_type_4=basic_with_edges\r
-CSET match_type_5=basic_with_edges\r
-CSET match_type_6=basic_with_edges\r
-CSET match_type_7=basic_with_edges\r
-CSET match_type_8=basic_with_edges\r
-CSET match_type_9=basic_with_edges\r
-CSET match_units_1=1\r
-CSET match_units_10=1\r
-CSET match_units_11=1\r
-CSET match_units_12=1\r
-CSET match_units_13=1\r
-CSET match_units_14=1\r
-CSET match_units_15=1\r
-CSET match_units_16=1\r
-CSET match_units_2=1\r
-CSET match_units_3=1\r
-CSET match_units_4=1\r
-CSET match_units_5=1\r
-CSET match_units_6=1\r
-CSET match_units_7=1\r
-CSET match_units_8=1\r
-CSET match_units_9=1\r
-CSET max_sequence_levels=1\r
-CSET number_of_trigger_ports=1\r
-CSET sample_data_depth=1024\r
-CSET sample_on=Rising\r
-CSET trigger_port_width_1=128\r
-CSET trigger_port_width_10=8\r
-CSET trigger_port_width_11=8\r
-CSET trigger_port_width_12=8\r
-CSET trigger_port_width_13=8\r
-CSET trigger_port_width_14=8\r
-CSET trigger_port_width_15=8\r
-CSET trigger_port_width_16=8\r
-CSET trigger_port_width_2=8\r
-CSET trigger_port_width_3=8\r
-CSET trigger_port_width_4=8\r
-CSET trigger_port_width_5=8\r
-CSET trigger_port_width_6=8\r
-CSET trigger_port_width_7=8\r
-CSET trigger_port_width_8=8\r
-CSET trigger_port_width_9=8\r
-CSET use_rpms=true\r
-# END Parameters\r
-GENERATE\r
-# CRC: 6cc4b31f\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="ila128.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="ila128.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ila128|ila128_a" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="ila128.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ila128" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="ila128" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-19T13:26:50" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1DE8ABD5641346EB8572BE2AB4C22B42" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-The following files were generated for 'ila128' in directory\r
-D:\Xilinx_proj\Panda\test_seradc\ipcore_dir\\r
-\r
-XCO file generator:\r
- Generate an XCO file for compatibility with legacy flows.\r
-\r
- * ila128.xco\r
-\r
-Creates an implementation netlist:\r
- Creates an implementation netlist for the IP.\r
-\r
- * ila128.cdc\r
- * ila128.ngc\r
- * ila128.vhd\r
- * ila128.vho\r
-\r
-Creates an HDL instantiation template:\r
- Creates an HDL instantiation template for the IP.\r
-\r
- * ila128.vho\r
-\r
-IP Symbol Generator:\r
- Generate an IP symbol based on the current project options'.\r
-\r
- * ila128.asy\r
-\r
-SYM file generator:\r
- Generate a SYM file for compatibility with legacy flows\r
-\r
- * ila128.sym\r
-\r
-Generate ISE metadata:\r
- Create a metadata file for use when including this core in ISE designs\r
-\r
- * ila128_xmdf.tcl\r
-\r
-Generate ISE subproject:\r
- Create an ISE subproject for use when including this core in ISE designs\r
-\r
- * _xmsgs/pn_parser.xmsgs\r
- * ila128.gise\r
- * ila128.xise\r
-\r
-Deliver Readme:\r
- Readme file for the IP.\r
-\r
- * ila128_readme.txt\r
-\r
-Generate FLIST file:\r
- Text file listing all of the output files produced when a customized core was\r
- generated in the CORE Generator.\r
-\r
- * ila128_flist.txt\r
-\r
-Please see the Xilinx CORE Generator online help for further details on\r
-generated files and how to use them.\r
-\r
+++ /dev/null
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 ila36
-RECTANGLE Normal 32 32 288 704
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName control[35:0]
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Wide 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName trig0[35:0]
-PINATTR Polarity IN
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
-\r
- <!-- -->\r
-\r
- <!-- For tool use only. Do not edit. -->\r
-\r
- <!-- -->\r
-\r
- <!-- ProjectNavigator created generated project file. -->\r
-\r
- <!-- For use in tracking generated file and other information -->\r
-\r
- <!-- allowing preservation of process status. -->\r
-\r
- <!-- -->\r
-\r
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
-\r
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
-\r
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ila36.xise"/>\r
-\r
- <files xmlns="http://www.xilinx.com/XMLSchema">\r
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="ila36.asy" xil_pn:origination="imported"/>\r
- <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ila36.sym" xil_pn:origination="imported"/>\r
- <file xil_pn:fileType="FILE_VHO" xil_pn:name="ila36.vho" xil_pn:origination="imported"/>\r
- </files>\r
-\r
- <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
- <transform xil_pn:end_ts="1343040841" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1343040841">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="9113925850006466910" xil_pn:start_ts="1383914820">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3435590971552100386" xil_pn:start_ts="1383914820">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1383914820">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3403158479962426638" xil_pn:start_ts="1383914820">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- </transforms>\r
-\r
-</generated_project>\r
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$80a
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\7fa<1>=8391<7>t$2;`>4c73A2i:6F7899'623=9:1b5:4?::kf0?6=3f9947>5;|`;02<72:0;6=u+38a95`6<@1h=7E678:&130<6;2c2;7>5;hg7>5<<g:836=44}c:72?6=;3:1<v*<9b82a5=O0k<0D567;%041?743`3<6=44id694?=h;;21<75rb966>5<4290;w)=6c;3f4>N?j?1C4564$356>45<a0=1<75fe583>>i4:10;66sm85694?5=83:p(>7l:0g3?M>e>2B3455+267956=n1>0;66gj4;29?j5503:17pl74283>6<729q/?4m51d28L=d13A2346*=74827>o>?3:17dk;:188k64?2900qo6;2;297?6=8r.85n4>e19K<g0<@1237)<85;30?l?02900eh:50;9l77>=831vn5:>:180>5<7s-92o7?j0:J;f3=O0120(?9::018m<1=831bi94?::m06=<722wi4;=50;194?6|,:3h6<k?;I:a2>N?011/>:;5129j=2<722cn87>5;n11<?6=3th3:?4?:283>5}#;0i1=h>4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44o20;>5<<uk2==7>53;294~"41j0:i=5G8c48L=>?3-8<97?<;h;4>5<<al>1<75`33:94?=zj1<;6=4<:183
\7f!5>k3;n<6F7b79K<=><,;=>6<=4i8594?=nm=0;66a<2983>>{e0<l1<7=50;2x 6?d28o;7E6m6:J;<==#:>?1=>5f9683>>ob<3:17b==8;29?xd?=l0;6>4?:1y'7<e=9l:0D5l9;I:;<>"5?<0:?6g67;29?lc32900c><7:188yg>2l3:1?7>50z&0=f<6m91C4o84H9:;?!40=3;87d78:188m`2=831d??650;9~f=3129086=4?{%1:g?7b82B3n;5G89:8 7122890e4950;9ja1<722e8>54?::
\7fa<1d=8391<7>t$2;`>4c73A2i:6F7899'623=9:1b5:4?::kf0?6=3f9947>5;|`;05<72:0;6=u+38a95`6<@1h=7E678:&130<6;2c2;7>5;hg7>5<<g:836=44}c5;1?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>3;6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm78`94?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0i;0;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo9n3;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f2g3290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;l;50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`4e3<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk=j;7>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb6c;>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e?1<1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl88683>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1?03:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:66:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::
\7fa3=g=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<4o4?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c5;g?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>2o6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm79g94?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd00o0;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo961;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f2?5290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;4=50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`4=1<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk=297>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb6;5>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e?0=1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl89983>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1>13:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:7n:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::
\7fa3<e=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<5i4?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c5:a?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>3m6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm7`294?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0i80;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo991;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f20d290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;:950;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`43`<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk=<j7>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb6:3>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e?1;1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl88383>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1?;3:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:6;:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::
\7fa334=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<:>4?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c550?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj><>6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm77494?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0>>0;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo998;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f20>290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;;o50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`42g<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk==h7>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb64f>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e??l1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl87183>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1093:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:9=:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::
\7fa325=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<;94?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c541?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>==6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm76:94?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0?00;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo98a;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f21e290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;:m50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`43a<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk<i57>54;294~"41j0:i?5G8c48L=>?3-8<97<4i8594?=njk0;66gj4;29?j5503:17pl9b`83>1<729q/?4m51d08L=d13A2346*=7481?l?02900eol50;9ja1<722e8>54?::
\7fa2g4=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th=n<4?:583>5}#;0i1=h<4H9`5?M>?02.9;84=;h;4>5<<akh1<75fe583>>i4:10;66sm6df94?2=83:p(>7l:0g1?M>e>2B3455+26796>o>?3:17dlm:188m`2=831d??650;9~f31129086=4?{%1:g?7b82B3n;5G89:8 7122890e4950;9ja1<722e8>54?::
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\ No newline at end of file
+++ /dev/null
--------------------------------------------------------------------------------\r
--- Copyright (c) 2012 Xilinx, Inc.\r
--- All Rights Reserved\r
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor : Xilinx\r
--- \ \ \/ Version : 13.3\r
--- \ \ Application: XILINX CORE Generator\r
--- / / Filename : ila36.vhd\r
--- /___/ /\ Timestamp : Thu Jul 19 13:23:10 W. Europe Daylight Time 2012\r
--- \ \ / \\r
--- \___\/\___\\r
---\r
--- Design Name: VHDL Synthesis Wrapper\r
--------------------------------------------------------------------------------\r
--- This wrapper is used to integrate with Project Navigator and PlanAhead\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-ENTITY ila36 IS\r
- port (\r
- CONTROL: inout std_logic_vector(35 downto 0);\r
- CLK: in std_logic;\r
- TRIG0: in std_logic_vector(35 downto 0));\r
-END ila36;\r
-\r
-ARCHITECTURE ila36_a OF ila36 IS\r
-BEGIN\r
-\r
-END ila36_a;\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- Copyright (c) 2012 Xilinx, Inc.\r
--- All Rights Reserved\r
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor : Xilinx\r
--- \ \ \/ Version : 13.3\r
--- \ \ Application: Xilinx CORE Generator\r
--- / / Filename : ila36.vho\r
--- /___/ /\ Timestamp : Thu Jul 19 13:23:10 W. Europe Daylight Time 2012\r
--- \ \ / \\r
--- \___\/\___\\r
---\r
--- Design Name: ISE Instantiation template\r
--- Component Identifier: xilinx.com:ip:chipscope_ila:1.05.a\r
--------------------------------------------------------------------------------\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-component ila36\r
- PORT (\r
- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- CLK : IN STD_LOGIC;\r
- TRIG0 : IN STD_LOGIC_VECTOR(35 DOWNTO 0));\r
-\r
-end component;\r
-\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-\r
-your_instance_name : ila36\r
- port map (\r
- CONTROL => CONTROL,\r
- CLK => CLK,\r
- TRIG0 => TRIG0);\r
-\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 13.3\r
-# Date: Thu Jul 19 11:21:13 2012\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Structural\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a\r
-# END Select\r
-# BEGIN Parameters\r
-CSET check_bramcount=false\r
-CSET component_name=ila36\r
-CSET constraint_type=embedded\r
-CSET counter_width_1=Disabled\r
-CSET counter_width_10=Disabled\r
-CSET counter_width_11=Disabled\r
-CSET counter_width_12=Disabled\r
-CSET counter_width_13=Disabled\r
-CSET counter_width_14=Disabled\r
-CSET counter_width_15=Disabled\r
-CSET counter_width_16=Disabled\r
-CSET counter_width_2=Disabled\r
-CSET counter_width_3=Disabled\r
-CSET counter_width_4=Disabled\r
-CSET counter_width_5=Disabled\r
-CSET counter_width_6=Disabled\r
-CSET counter_width_7=Disabled\r
-CSET counter_width_8=Disabled\r
-CSET counter_width_9=Disabled\r
-CSET data_port_width=0\r
-CSET data_same_as_trigger=true\r
-CSET disable_save_keep=false\r
-CSET enable_storage_qualification=true\r
-CSET enable_trigger_output_port=false\r
-CSET example_design=false\r
-CSET exclude_from_data_storage_1=false\r
-CSET exclude_from_data_storage_10=false\r
-CSET exclude_from_data_storage_11=false\r
-CSET exclude_from_data_storage_12=false\r
-CSET exclude_from_data_storage_13=false\r
-CSET exclude_from_data_storage_14=false\r
-CSET exclude_from_data_storage_15=false\r
-CSET exclude_from_data_storage_16=false\r
-CSET exclude_from_data_storage_2=false\r
-CSET exclude_from_data_storage_3=false\r
-CSET exclude_from_data_storage_4=false\r
-CSET exclude_from_data_storage_5=false\r
-CSET exclude_from_data_storage_6=false\r
-CSET exclude_from_data_storage_7=false\r
-CSET exclude_from_data_storage_8=false\r
-CSET exclude_from_data_storage_9=false\r
-CSET match_type_1=basic_with_edges\r
-CSET match_type_10=basic_with_edges\r
-CSET match_type_11=basic_with_edges\r
-CSET match_type_12=basic_with_edges\r
-CSET match_type_13=basic_with_edges\r
-CSET match_type_14=basic_with_edges\r
-CSET match_type_15=basic_with_edges\r
-CSET match_type_16=basic_with_edges\r
-CSET match_type_2=basic_with_edges\r
-CSET match_type_3=basic_with_edges\r
-CSET match_type_4=basic_with_edges\r
-CSET match_type_5=basic_with_edges\r
-CSET match_type_6=basic_with_edges\r
-CSET match_type_7=basic_with_edges\r
-CSET match_type_8=basic_with_edges\r
-CSET match_type_9=basic_with_edges\r
-CSET match_units_1=1\r
-CSET match_units_10=1\r
-CSET match_units_11=1\r
-CSET match_units_12=1\r
-CSET match_units_13=1\r
-CSET match_units_14=1\r
-CSET match_units_15=1\r
-CSET match_units_16=1\r
-CSET match_units_2=1\r
-CSET match_units_3=1\r
-CSET match_units_4=1\r
-CSET match_units_5=1\r
-CSET match_units_6=1\r
-CSET match_units_7=1\r
-CSET match_units_8=1\r
-CSET match_units_9=1\r
-CSET max_sequence_levels=1\r
-CSET number_of_trigger_ports=1\r
-CSET sample_data_depth=1024\r
-CSET sample_on=Rising\r
-CSET trigger_port_width_1=36\r
-CSET trigger_port_width_10=8\r
-CSET trigger_port_width_11=8\r
-CSET trigger_port_width_12=8\r
-CSET trigger_port_width_13=8\r
-CSET trigger_port_width_14=8\r
-CSET trigger_port_width_15=8\r
-CSET trigger_port_width_16=8\r
-CSET trigger_port_width_2=8\r
-CSET trigger_port_width_3=8\r
-CSET trigger_port_width_4=8\r
-CSET trigger_port_width_5=8\r
-CSET trigger_port_width_6=8\r
-CSET trigger_port_width_7=8\r
-CSET trigger_port_width_8=8\r
-CSET trigger_port_width_9=8\r
-CSET use_rpms=true\r
-# END Parameters\r
-GENERATE\r
-# CRC: d7d162a4\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="ila36.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="ila36.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ila36|ila36_a" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="ila36.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ila36" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="ila36" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-19T13:23:19" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BE66BF3D7764410AB7EAAD8952DDFFD8" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-The following files were generated for 'ila36' in directory\r
-D:\Xilinx_proj\Panda\test_seradc\ipcore_dir\\r
-\r
-XCO file generator:\r
- Generate an XCO file for compatibility with legacy flows.\r
-\r
- * ila36.xco\r
-\r
-Creates an implementation netlist:\r
- Creates an implementation netlist for the IP.\r
-\r
- * ila36.cdc\r
- * ila36.ngc\r
- * ila36.vhd\r
- * ila36.vho\r
-\r
-Creates an HDL instantiation template:\r
- Creates an HDL instantiation template for the IP.\r
-\r
- * ila36.vho\r
-\r
-IP Symbol Generator:\r
- Generate an IP symbol based on the current project options'.\r
-\r
- * ila36.asy\r
-\r
-SYM file generator:\r
- Generate a SYM file for compatibility with legacy flows\r
-\r
- * ila36.sym\r
-\r
-Generate ISE metadata:\r
- Create a metadata file for use when including this core in ISE designs\r
-\r
- * ila36_xmdf.tcl\r
-\r
-Generate ISE subproject:\r
- Create an ISE subproject for use when including this core in ISE designs\r
-\r
- * _xmsgs/pn_parser.xmsgs\r
- * ila36.gise\r
- * ila36.xise\r
-\r
-Deliver Readme:\r
- Readme file for the IP.\r
-\r
- * ila36_readme.txt\r
-\r
-Generate FLIST file:\r
- Text file listing all of the output files produced when a customized core was\r
- generated in the CORE Generator.\r
-\r
- * ila36_flist.txt\r
-\r
-Please see the Xilinx CORE Generator online help for further details on\r
-generated files and how to use them.\r
-\r
+++ /dev/null
-------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ / \r
--- /___/ \ / Vendor: Xilinx \r
--- \ \ \/ Version : 1.12\r
--- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
--- / / Filename : mgt_usrclk_source_mmcm.vhd\r
--- /___/ /\ \r
--- \ \ / \ \r
--- \___\/\___\ \r
---\r
---\r
--- Module MGT_USRCLK_SOURCE_MMCM (for use with Virtex-6 GTX Transceivers)\r
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
---
---
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-use ieee.std_logic_unsigned.all;\r
-library UNISIM;\r
-use UNISIM.VCOMPONENTS.ALL;\r
-\r
---***********************************Entity Declaration*******************************\r
-entity MGT_USRCLK_SOURCE_MMCM is\r
-generic\r
-(\r
- MULT : real := 2.0;\r
- DIVIDE : integer := 2; \r
- CLK_PERIOD : real := 6.4; \r
- OUT0_DIVIDE : real := 2.0;\r
- OUT1_DIVIDE : integer := 2;\r
- OUT2_DIVIDE : integer := 2;\r
- OUT3_DIVIDE : integer := 2\r
-);\r
-port\r
-(\r
- CLKFBOUT : out std_logic; \r
- CLK0_OUT : out std_logic;\r
- CLK1_OUT : out std_logic;\r
- CLK2_OUT : out std_logic;\r
- CLK3_OUT : out std_logic;\r
- CLK_IN : in std_logic;\r
- MMCM_LOCKED_OUT : out std_logic;\r
- MMCM_RESET_IN : in std_logic\r
-);\r
-\r
-\r
-end MGT_USRCLK_SOURCE_MMCM;\r
-\r
-architecture RTL of MGT_USRCLK_SOURCE_MMCM is\r
---*********************************Wire Declarations**********************************\r
-\r
- signal tied_to_ground_vec_i : std_logic_vector(15 downto 0);\r
- signal tied_to_ground_i : std_logic;\r
- signal tied_to_vcc_i : std_logic;\r
- signal clkout0_i : std_logic;\r
- signal clkout1_i : std_logic;\r
- signal clkout2_i : std_logic;\r
- signal clkout3_i : std_logic;\r
- signal clkfbout_i : std_logic;\r
- signal clkfbout_buf : std_logic;\r
-\r
-begin\r
-\r
---*********************************** Beginning of Code *******************************\r
-\r
- -- Static signal Assigments \r
- tied_to_ground_i <= '0';\r
- tied_to_ground_vec_i <= (others=>'0');\r
- tied_to_vcc_i <= '1';\r
-\r
- -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback\r
- -- for improved jitter performance, and to avoid consuming an additional BUFG\r
- mmcm_adv_i : MMCM_ADV\r
- generic map\r
- (\r
- COMPENSATION => "ZHOLD",\r
- CLKFBOUT_MULT_F => MULT,\r
- DIVCLK_DIVIDE => DIVIDE,\r
- CLKFBOUT_PHASE => 0.0,\r
- CLKIN1_PERIOD => CLK_PERIOD,\r
- CLKIN2_PERIOD => 10.0, -- Not used\r
- CLKOUT0_DIVIDE_F => OUT0_DIVIDE,\r
- CLKOUT0_PHASE => 0.0,\r
- CLKOUT1_DIVIDE => OUT1_DIVIDE,\r
- CLKOUT1_PHASE => 0.0,\r
- CLKOUT2_DIVIDE => OUT2_DIVIDE,\r
- CLKOUT2_PHASE => 0.0,\r
- CLKOUT3_DIVIDE => OUT3_DIVIDE,\r
- CLKOUT3_PHASE => 0.0,\r
- CLOCK_HOLD => TRUE \r
- )\r
- port map\r
- (\r
- CLKIN1 => CLK_IN,\r
- CLKIN2 => tied_to_ground_i,\r
- CLKINSEL => tied_to_vcc_i,\r
- CLKFBIN => clkfbout_buf,\r
- CLKOUT0 => clkout0_i,\r
- CLKOUT0B => open,\r
- CLKOUT1 => clkout1_i,\r
- CLKOUT1B => open,\r
- CLKOUT2 => clkout2_i,\r
- CLKOUT2B => open,\r
- CLKOUT3 => clkout3_i,\r
- CLKOUT3B => open,\r
- CLKOUT4 => open,\r
- CLKOUT5 => open,\r
- CLKOUT6 => open,\r
- CLKFBOUT => clkfbout_i,\r
- CLKFBOUTB => open,\r
- CLKFBSTOPPED => open,\r
- CLKINSTOPPED => open,\r
- DO => open,\r
- DRDY => open,\r
- DADDR => tied_to_ground_vec_i(6 downto 0),\r
- DCLK => tied_to_ground_i,\r
- DEN => tied_to_ground_i,\r
- DI => tied_to_ground_vec_i(15 downto 0),\r
- DWE => tied_to_ground_i,\r
- LOCKED => MMCM_LOCKED_OUT,\r
- PSCLK => tied_to_ground_i,\r
- PSEN => tied_to_ground_i, \r
- PSINCDEC => tied_to_ground_i, \r
- PSDONE => open, \r
- PWRDWN => tied_to_ground_i,\r
- RST => MMCM_RESET_IN \r
- );\r
- \r
- clkfb_bufg_i : BUFG \r
- port map\r
- (\r
- O => clkfbout_buf, \r
- I => clkfbout_i\r
- ); \r
- CLKFBOUT <= clkfbout_buf;\r
- \r
- clkout0_bufg_i : BUFG \r
- port map\r
- (\r
- O => CLK0_OUT, \r
- I => clkout0_i\r
- ); \r
-\r
-\r
- clkout1_bufg_i : BUFG \r
- port map\r
- (\r
- O => CLK1_OUT,\r
- I => clkout1_i\r
- );\r
- \r
- \r
- clkout2_bufg_i : BUFG \r
- port map\r
- (\r
- O => CLK2_OUT, \r
- I => clkout2_i\r
- ); \r
-\r
-\r
- clkout3_bufg_i : BUFG \r
- port map\r
- (\r
- O => CLK3_OUT,\r
- I => clkout3_i\r
- ); \r
- \r
-end RTL;\r
- \r
+++ /dev/null
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 sync_fifo_512x41
-RECTANGLE Normal 32 32 800 4064
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName din[40:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 464 32 464
-PIN 0 464 LEFT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Wide 832 272 800 272
-PIN 832 272 RIGHT 36
-PINATTR PinName dout[40:0]
-PINATTR Polarity OUT
-LINE Normal 832 304 800 304
-PIN 832 304 RIGHT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 832 496 800 496
-PIN 832 496 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
-\r
- <!-- -->\r
-\r
- <!-- For tool use only. Do not edit. -->\r
-\r
- <!-- -->\r
-\r
- <!-- ProjectNavigator created generated project file. -->\r
-\r
- <!-- For use in tracking generated file and other information -->\r
-\r
- <!-- allowing preservation of process status. -->\r
-\r
- <!-- -->\r
-\r
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
-\r
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
-\r
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sync_fifo_512x41.xise"/>\r
-\r
- <files xmlns="http://www.xilinx.com/XMLSchema">\r
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="sync_fifo_512x41.asy" xil_pn:origination="imported"/>\r
- <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="sync_fifo_512x41.sym" xil_pn:origination="imported"/>\r
- <file xil_pn:fileType="FILE_VHO" xil_pn:name="sync_fifo_512x41.vho" xil_pn:origination="imported"/>\r
- </files>\r
-\r
- <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
- <transform xil_pn:end_ts="1411385153" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1411385153">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="517927155140597448" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1475527042133781192" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2025323555865192840" xil_pn:start_ts="1418036842">\r
- <status xil_pn:value="SuccessfullyRun"/>\r
- <status xil_pn:value="ReadyToRun"/>\r
- </transform>\r
- </transforms>\r
-\r
-</generated_project>\r
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$5g;
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\7f9o>:181
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\7f96?:181
\7f[2?827?<94>2c9~w1>62909wS:71:?741<6:j1v
\7f96=:181
\7f[2?:27?<94>2e9~w1>42909wS:73:?741<6:l1v
\7f96;:181
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\7fm1<2=838pD9<=;|l6=0<72;qC8?<4}o7:2?6=:rB?>?5rn4;4>5<5sA>9>6sa58:94?4|@=897p`:9883>7}O<;80qc;6a;296~N3:;1vb87m:181
\7fM25:2we94m50;0xL1453td>5i4?:3yK074<ug?2i7>52zJ767=zf<3m6=4={I616>{i=h:1<7<tH501?xh2i80;6?uG4308yk3f:3:1>vF;239~j0g42909wE:=2:
\7fm1d2=838pD9<=;|l6e0<72;qC8?<4}o7b2?6=:rB?>?5rn4c4>5<5sA>9>6sa5`:94?4|@=897p`:a883>7}O<;80qc;na;296~N3:;1vb8om:181
\7fM25:2we9lm50;0xL1453td>mi4?:3yK074<ug?ji7>52zJ767=zf<km6=4={I616>{i=k:1<7<tH501?xh2j80;6?uG4308yk3e:3:1>vF;239~j0d42909wE:=2:
\7fm1g2=838pD9<=;|l6f0<72;qC8?<4}o7a2?6=:rB?>?5rn4`4>5<5sA>9>6sa5c:94?4|@=897p`:b883>7}O<;80qc;ma;296~N3:;1vb8lm:181
\7fM25:2we9om50;0xL1453td>ni4?:0yK074<ug?ii7>51zJ767=zf<hm6=4>{I616>{i=j:1<7?tH501?xh2k80;6<uG4308yk3d:3:1=vF;239~j0e42909wE:=2:
\7fm1f2=839pD9<=;|l6g0<72:qC8?<4}o7`2?6=:rB?>?5rn4a4>5<5sA>9>6sa5b:94?4|@=897p`:c883>7}O<;80qc;la;296~N3:;1vb8mm:181
\7fM25:2we9nm50;0xL1453td>oi4?:3yK074<ug?hi7>52zJ767=zf<im6=4={I616>{i=m:1<7<tH501?xh2l80;6?uG4308yk3c:3:1>vF;239~j0b42909wE:=2:
\7fm1a2=838pD9<=;|l6`0<72;qC8?<4}o7g2?6=:rB?>?5rn4f4>5<5sA>9>6sa5e:94?4|@=897p`:d883>7}O<;80qc;ka;296~N3:;1vb8jm:181
\7fM25:2we9im50;0xL1453td>hi4?:3yK074<ug?oi7>52zJ767=zf<nm6=4={I616>{i=l:1<7<tH501?xh2m80;6?uG4308yk3b:3:1>vF;239~j0c42909wE:=2:
\7fm1`2=838pD9<=;|l6a0<72;qC8?<4}o7f2?6=:rB?>?5rn4g4>5<5sA>9>6sa5d:94?4|@=897p`:e883>7}O<;80qc;ja;296~N3:;1vb8km:181
\7fM25:2we9hm50;0xL1453td>ii4?:3yK074<ug?ni7>52zJ767=zf<om6=4={I616>{i=o:1<7<tH501?xh2n80;6?uG4308yk3a:3:1>vF;239~j0`42909wE:=2:
\7fm1c2=838pD9<=;|l6b0<72;qC8?<4}o7e2?6=:rB?>?5rn4d4>5<5sA>9>6sa5g:94?4|@=897p`:f883>7}O<;80qc;ia;296~N3:;1vb8hm:181
\7fM25:2we9km50;0xL1453td>ji4?:3yK074<ug?mi7>52zJ767=zf<lm6=4={I616>{i>9:1<7<tH501?xh1880;6<uG4308yk07:3:1=vF;239~j364290:wE:=2:
\7fm252=83;pD9<=;|l540<728qC8?<4}o432?6=9rB?>?5rn724>5<6sA>9>6sa61:94?7|@=897p`90883>4}O<;80qc8?a;295~N3:;1vb;>m:182
\7fM25:2we:=m50;3xL1453td=<i4?:0yK074<ug<;i7>51zJ767=zf?:m6=4>{I616>{i>8:1<7?tH501?xh1980;6<uG4308yk06:3:1=vF;239~j374290:wE:=2:
\7fm242=83;pD9<=;|l550<728qC8?<4}o422?6=9rB?>?5rn734>5<6sA>9>6sa60:94?7|@=897p`91883>4}O<;80qc8>a;295~N3:;1vb;?m:182
\7fM25:2we:<m50;3xL1453td==i4?:0yK074<ug<:i7>51zJ767=zf?;m6=4>{I616>{i>;:1<7?tH501?xh1:80;6<uG4308yk05:3:1=vF;239~j344290:wE:=2:
\7fm272=83;pD9<=;|l560<728qC8?<4}o412?6=9rB?>?5rn704>5<6sA>9>6sa63:94?7|@=897p`92883>4}O<;80qc8=a;295~N3:;1vb;<m:182
\7fM25:2we:?m50;3xL1453td=>i4?:0yK074<ug<9i7>51zJ767=zf?8m6=4>{I616>{i>::1<7?tH501?xh1;80;6<uG4308yk04:3:1=vF;239~j354290:wE:=2:
\7fm262=83;pD9<=;|l570<728qC8?<4}o402?6=9rB?>?5rn714>5<6sA>9>6sa62:94?7|@=897p`93883>4}O<;80qc8<a;295~N3:;1vb;=m:182
\7fM25:2we:>m50;3xL1453td=?i4?:0yK074<ug<8i7>51zJ767=zf?9m6=4>{I616>{i>=:1<7?tH501?xh1<80;6<uG4308yk03:3:1=vF;239~j324290:wE:=2:
\7fm212=83;pD9<=;|l500<728qC8?<4}o472?6=9rB?>?5rn764>5<6sA>9>6sa65:94?7|@=897p`94883>4}O<;80qc8;a;295~N3:;1vb;:m:182
\7fM25:2we:9m50;3xL1453td=8i4?:0yK074<ug<?i7>51zJ767=zf?>m6=4>{I616>{i><:1<7?tH501?xh1=80;6<uG4308yk02:3:1=vF;239~j334290:wE:=2:
\7fm202=83;pD9<=;|l510<728qC8?<4}o462?6=9rB?>?5rn774>5<6sA>9>6sa64:94?7|@=897p`95883>4}O<;80qc8:a;295~N3:;1vb;;m:182
\7fM25:2we:8m50;0xL1453td88h4?:0yK074<ug9?j7>51zJ767=zutwKLNu82g84e5ge<;>vLMLt0|BCT~{GH
\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
---------------------------------------------------------------------------------\r
--- You must compile the wrapper file sync_fifo_512x41.vhd when simulating\r
--- the core, sync_fifo_512x41. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
--- The synthesis directives "translate_off/translate_on" specified\r
--- below are supported by Xilinx, Mentor Graphics and Synplicity\r
--- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
--- synthesis translate_off\r
-LIBRARY XilinxCoreLib;\r
--- synthesis translate_on\r
-ENTITY sync_fifo_512x41 IS\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(40 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END sync_fifo_512x41;\r
-\r
-ARCHITECTURE sync_fifo_512x41_a OF sync_fifo_512x41 IS\r
--- synthesis translate_off\r
-COMPONENT wrapped_sync_fifo_512x41\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(40 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
-\r
--- Configuration specification\r
- FOR ALL : wrapped_sync_fifo_512x41 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
- GENERIC MAP (\r
- c_add_ngc_constraint => 0,\r
- c_application_type_axis => 0,\r
- c_application_type_rach => 0,\r
- c_application_type_rdch => 0,\r
- c_application_type_wach => 0,\r
- c_application_type_wdch => 0,\r
- c_application_type_wrch => 0,\r
- c_axi_addr_width => 32,\r
- c_axi_aruser_width => 1,\r
- c_axi_awuser_width => 1,\r
- c_axi_buser_width => 1,\r
- c_axi_data_width => 64,\r
- c_axi_id_width => 4,\r
- c_axi_ruser_width => 1,\r
- c_axi_type => 0,\r
- c_axi_wuser_width => 1,\r
- c_axis_tdata_width => 64,\r
- c_axis_tdest_width => 4,\r
- c_axis_tid_width => 8,\r
- c_axis_tkeep_width => 4,\r
- c_axis_tstrb_width => 4,\r
- c_axis_tuser_width => 4,\r
- c_axis_type => 0,\r
- c_common_clock => 1,\r
- c_count_type => 0,\r
- c_data_count_width => 9,\r
- c_default_value => "BlankString",\r
- c_din_width => 41,\r
- c_din_width_axis => 1,\r
- c_din_width_rach => 32,\r
- c_din_width_rdch => 64,\r
- c_din_width_wach => 32,\r
- c_din_width_wdch => 64,\r
- c_din_width_wrch => 2,\r
- c_dout_rst_val => "0",\r
- c_dout_width => 41,\r
- c_enable_rlocs => 0,\r
- c_enable_rst_sync => 1,\r
- c_error_injection_type => 0,\r
- c_error_injection_type_axis => 0,\r
- c_error_injection_type_rach => 0,\r
- c_error_injection_type_rdch => 0,\r
- c_error_injection_type_wach => 0,\r
- c_error_injection_type_wdch => 0,\r
- c_error_injection_type_wrch => 0,\r
- c_family => "virtex6",\r
- c_full_flags_rst_val => 1,\r
- c_has_almost_empty => 0,\r
- c_has_almost_full => 0,\r
- c_has_axi_aruser => 0,\r
- c_has_axi_awuser => 0,\r
- c_has_axi_buser => 0,\r
- c_has_axi_rd_channel => 0,\r
- c_has_axi_ruser => 0,\r
- c_has_axi_wr_channel => 0,\r
- c_has_axi_wuser => 0,\r
- c_has_axis_tdata => 0,\r
- c_has_axis_tdest => 0,\r
- c_has_axis_tid => 0,\r
- c_has_axis_tkeep => 0,\r
- c_has_axis_tlast => 0,\r
- c_has_axis_tready => 1,\r
- c_has_axis_tstrb => 0,\r
- c_has_axis_tuser => 0,\r
- c_has_backup => 0,\r
- c_has_data_count => 0,\r
- c_has_data_counts_axis => 0,\r
- c_has_data_counts_rach => 0,\r
- c_has_data_counts_rdch => 0,\r
- c_has_data_counts_wach => 0,\r
- c_has_data_counts_wdch => 0,\r
- c_has_data_counts_wrch => 0,\r
- c_has_int_clk => 0,\r
- c_has_master_ce => 0,\r
- c_has_meminit_file => 0,\r
- c_has_overflow => 0,\r
- c_has_prog_flags_axis => 0,\r
- c_has_prog_flags_rach => 0,\r
- c_has_prog_flags_rdch => 0,\r
- c_has_prog_flags_wach => 0,\r
- c_has_prog_flags_wdch => 0,\r
- c_has_prog_flags_wrch => 0,\r
- c_has_rd_data_count => 0,\r
- c_has_rd_rst => 0,\r
- c_has_rst => 1,\r
- c_has_slave_ce => 0,\r
- c_has_srst => 0,\r
- c_has_underflow => 0,\r
- c_has_valid => 0,\r
- c_has_wr_ack => 0,\r
- c_has_wr_data_count => 0,\r
- c_has_wr_rst => 0,\r
- c_implementation_type => 0,\r
- c_implementation_type_axis => 1,\r
- c_implementation_type_rach => 1,\r
- c_implementation_type_rdch => 1,\r
- c_implementation_type_wach => 1,\r
- c_implementation_type_wdch => 1,\r
- c_implementation_type_wrch => 1,\r
- c_init_wr_pntr_val => 0,\r
- c_interface_type => 0,\r
- c_memory_type => 1,\r
- c_mif_file_name => "BlankString",\r
- c_msgon_val => 1,\r
- c_optimization_mode => 0,\r
- c_overflow_low => 0,\r
- c_preload_latency => 1,\r
- c_preload_regs => 0,\r
- c_prim_fifo_type => "512x72",\r
- c_prog_empty_thresh_assert_val => 2,\r
- c_prog_empty_thresh_assert_val_axis => 1022,\r
- c_prog_empty_thresh_assert_val_rach => 1022,\r
- c_prog_empty_thresh_assert_val_rdch => 1022,\r
- c_prog_empty_thresh_assert_val_wach => 1022,\r
- c_prog_empty_thresh_assert_val_wdch => 1022,\r
- c_prog_empty_thresh_assert_val_wrch => 1022,\r
- c_prog_empty_thresh_negate_val => 3,\r
- c_prog_empty_type => 0,\r
- c_prog_empty_type_axis => 0,\r
- c_prog_empty_type_rach => 0,\r
- c_prog_empty_type_rdch => 0,\r
- c_prog_empty_type_wach => 0,\r
- c_prog_empty_type_wdch => 0,\r
- c_prog_empty_type_wrch => 0,\r
- c_prog_full_thresh_assert_val => 510,\r
- c_prog_full_thresh_assert_val_axis => 1023,\r
- c_prog_full_thresh_assert_val_rach => 1023,\r
- c_prog_full_thresh_assert_val_rdch => 1023,\r
- c_prog_full_thresh_assert_val_wach => 1023,\r
- c_prog_full_thresh_assert_val_wdch => 1023,\r
- c_prog_full_thresh_assert_val_wrch => 1023,\r
- c_prog_full_thresh_negate_val => 509,\r
- c_prog_full_type => 0,\r
- c_prog_full_type_axis => 0,\r
- c_prog_full_type_rach => 0,\r
- c_prog_full_type_rdch => 0,\r
- c_prog_full_type_wach => 0,\r
- c_prog_full_type_wdch => 0,\r
- c_prog_full_type_wrch => 0,\r
- c_rach_type => 0,\r
- c_rd_data_count_width => 9,\r
- c_rd_depth => 512,\r
- c_rd_freq => 1,\r
- c_rd_pntr_width => 9,\r
- c_rdch_type => 0,\r
- c_reg_slice_mode_axis => 0,\r
- c_reg_slice_mode_rach => 0,\r
- c_reg_slice_mode_rdch => 0,\r
- c_reg_slice_mode_wach => 0,\r
- c_reg_slice_mode_wdch => 0,\r
- c_reg_slice_mode_wrch => 0,\r
- c_synchronizer_stage => 2,\r
- c_underflow_low => 0,\r
- c_use_common_overflow => 0,\r
- c_use_common_underflow => 0,\r
- c_use_default_settings => 0,\r
- c_use_dout_rst => 1,\r
- c_use_ecc => 0,\r
- c_use_ecc_axis => 0,\r
- c_use_ecc_rach => 0,\r
- c_use_ecc_rdch => 0,\r
- c_use_ecc_wach => 0,\r
- c_use_ecc_wdch => 0,\r
- c_use_ecc_wrch => 0,\r
- c_use_embedded_reg => 0,\r
- c_use_fifo16_flags => 0,\r
- c_use_fwft_data_count => 0,\r
- c_valid_low => 0,\r
- c_wach_type => 0,\r
- c_wdch_type => 0,\r
- c_wr_ack_low => 0,\r
- c_wr_data_count_width => 9,\r
- c_wr_depth => 512,\r
- c_wr_depth_axis => 1024,\r
- c_wr_depth_rach => 16,\r
- c_wr_depth_rdch => 1024,\r
- c_wr_depth_wach => 16,\r
- c_wr_depth_wdch => 1024,\r
- c_wr_depth_wrch => 16,\r
- c_wr_freq => 1,\r
- c_wr_pntr_width => 9,\r
- c_wr_pntr_width_axis => 10,\r
- c_wr_pntr_width_rach => 4,\r
- c_wr_pntr_width_rdch => 10,\r
- c_wr_pntr_width_wach => 4,\r
- c_wr_pntr_width_wdch => 10,\r
- c_wr_pntr_width_wrch => 4,\r
- c_wr_response_latency => 1,\r
- c_wrch_type => 0\r
- );\r
--- synthesis translate_on\r
-BEGIN\r
--- synthesis translate_off\r
-U0 : wrapped_sync_fifo_512x41\r
- PORT MAP (\r
- clk => clk,\r
- rst => rst,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty\r
- );\r
--- synthesis translate_on\r
-\r
-END sync_fifo_512x41_a;\r
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
-\r
---------------------------------------------------------------------------------\r
--- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
--- --\r
--- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
--- memory queue generator. Use it to generate resource and performance --\r
--- optimized FIFOs with common or independent read/write clock domains, --\r
--- and optional fixed or programmable full and empty flags and --\r
--- handshaking signals. Choose from a selection of memory resource --\r
--- types for implementation. Optional Hamming code based error --\r
--- detection and correction as well as error injection capability for --\r
--- system test help to insure data integrity. FIFO width and depth are --\r
--- parameterizable, and for native interface FIFOs, asymmetric read and --\r
--- write port widths are also supported. --\r
---------------------------------------------------------------------------------\r
-\r
--- Interfaces:\r
--- AXI4Stream_MASTER_M_AXIS\r
--- AXI4Stream_SLAVE_S_AXIS\r
--- AXI4_MASTER_M_AXI\r
--- AXI4_SLAVE_S_AXI\r
--- AXI4Lite_MASTER_M_AXI\r
--- AXI4Lite_SLAVE_S_AXI\r
--- master_aclk\r
--- slave_aclk\r
--- slave_aresetn\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-COMPONENT sync_fifo_512x41\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(40 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
-\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : sync_fifo_512x41\r
- PORT MAP (\r
- clk => clk,\r
- rst => rst,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty\r
- );\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
-\r
--- You must compile the wrapper file sync_fifo_512x41.vhd when simulating\r
--- the core, sync_fifo_512x41. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Fri Sep 19 14:11:57 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
-# END Select\r
-# BEGIN Parameters\r
-CSET add_ngc_constraint_axi=false\r
-CSET almost_empty_flag=false\r
-CSET almost_full_flag=false\r
-CSET aruser_width=1\r
-CSET awuser_width=1\r
-CSET axi_address_width=32\r
-CSET axi_data_width=64\r
-CSET axi_type=AXI4_Stream\r
-CSET axis_type=FIFO\r
-CSET buser_width=1\r
-CSET clock_enable_type=Slave_Interface_Clock_Enable\r
-CSET clock_type_axi=Common_Clock\r
-CSET component_name=sync_fifo_512x41\r
-CSET data_count=false\r
-CSET data_count_width=9\r
-CSET disable_timing_violations=false\r
-CSET disable_timing_violations_axi=false\r
-CSET dout_reset_value=0\r
-CSET empty_threshold_assert_value=2\r
-CSET empty_threshold_assert_value_axis=1022\r
-CSET empty_threshold_assert_value_rach=1022\r
-CSET empty_threshold_assert_value_rdch=1022\r
-CSET empty_threshold_assert_value_wach=1022\r
-CSET empty_threshold_assert_value_wdch=1022\r
-CSET empty_threshold_assert_value_wrch=1022\r
-CSET empty_threshold_negate_value=3\r
-CSET enable_aruser=false\r
-CSET enable_awuser=false\r
-CSET enable_buser=false\r
-CSET enable_common_overflow=false\r
-CSET enable_common_underflow=false\r
-CSET enable_data_counts_axis=false\r
-CSET enable_data_counts_rach=false\r
-CSET enable_data_counts_rdch=false\r
-CSET enable_data_counts_wach=false\r
-CSET enable_data_counts_wdch=false\r
-CSET enable_data_counts_wrch=false\r
-CSET enable_ecc=false\r
-CSET enable_ecc_axis=false\r
-CSET enable_ecc_rach=false\r
-CSET enable_ecc_rdch=false\r
-CSET enable_ecc_wach=false\r
-CSET enable_ecc_wdch=false\r
-CSET enable_ecc_wrch=false\r
-CSET enable_read_channel=false\r
-CSET enable_read_pointer_increment_by2=false\r
-CSET enable_reset_synchronization=true\r
-CSET enable_ruser=false\r
-CSET enable_tdata=false\r
-CSET enable_tdest=false\r
-CSET enable_tid=false\r
-CSET enable_tkeep=false\r
-CSET enable_tlast=false\r
-CSET enable_tready=true\r
-CSET enable_tstrobe=false\r
-CSET enable_tuser=false\r
-CSET enable_write_channel=false\r
-CSET enable_wuser=false\r
-CSET fifo_application_type_axis=Data_FIFO\r
-CSET fifo_application_type_rach=Data_FIFO\r
-CSET fifo_application_type_rdch=Data_FIFO\r
-CSET fifo_application_type_wach=Data_FIFO\r
-CSET fifo_application_type_wdch=Data_FIFO\r
-CSET fifo_application_type_wrch=Data_FIFO\r
-CSET fifo_implementation=Common_Clock_Block_RAM\r
-CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
-CSET full_flags_reset_value=1\r
-CSET full_threshold_assert_value=510\r
-CSET full_threshold_assert_value_axis=1023\r
-CSET full_threshold_assert_value_rach=1023\r
-CSET full_threshold_assert_value_rdch=1023\r
-CSET full_threshold_assert_value_wach=1023\r
-CSET full_threshold_assert_value_wdch=1023\r
-CSET full_threshold_assert_value_wrch=1023\r
-CSET full_threshold_negate_value=509\r
-CSET id_width=4\r
-CSET inject_dbit_error=false\r
-CSET inject_dbit_error_axis=false\r
-CSET inject_dbit_error_rach=false\r
-CSET inject_dbit_error_rdch=false\r
-CSET inject_dbit_error_wach=false\r
-CSET inject_dbit_error_wdch=false\r
-CSET inject_dbit_error_wrch=false\r
-CSET inject_sbit_error=false\r
-CSET inject_sbit_error_axis=false\r
-CSET inject_sbit_error_rach=false\r
-CSET inject_sbit_error_rdch=false\r
-CSET inject_sbit_error_wach=false\r
-CSET inject_sbit_error_wdch=false\r
-CSET inject_sbit_error_wrch=false\r
-CSET input_data_width=41\r
-CSET input_depth=512\r
-CSET input_depth_axis=1024\r
-CSET input_depth_rach=16\r
-CSET input_depth_rdch=1024\r
-CSET input_depth_wach=16\r
-CSET input_depth_wdch=1024\r
-CSET input_depth_wrch=16\r
-CSET interface_type=Native\r
-CSET output_data_width=41\r
-CSET output_depth=512\r
-CSET overflow_flag=false\r
-CSET overflow_flag_axi=false\r
-CSET overflow_sense=Active_High\r
-CSET overflow_sense_axi=Active_High\r
-CSET performance_options=Standard_FIFO\r
-CSET programmable_empty_type=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
-CSET programmable_full_type=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
-CSET rach_type=FIFO\r
-CSET rdch_type=FIFO\r
-CSET read_clock_frequency=1\r
-CSET read_data_count=false\r
-CSET read_data_count_width=9\r
-CSET register_slice_mode_axis=Fully_Registered\r
-CSET register_slice_mode_rach=Fully_Registered\r
-CSET register_slice_mode_rdch=Fully_Registered\r
-CSET register_slice_mode_wach=Fully_Registered\r
-CSET register_slice_mode_wdch=Fully_Registered\r
-CSET register_slice_mode_wrch=Fully_Registered\r
-CSET reset_pin=true\r
-CSET reset_type=Asynchronous_Reset\r
-CSET ruser_width=1\r
-CSET synchronization_stages=2\r
-CSET synchronization_stages_axi=2\r
-CSET tdata_width=64\r
-CSET tdest_width=4\r
-CSET tid_width=8\r
-CSET tkeep_width=4\r
-CSET tstrb_width=4\r
-CSET tuser_width=4\r
-CSET underflow_flag=false\r
-CSET underflow_flag_axi=false\r
-CSET underflow_sense=Active_High\r
-CSET underflow_sense_axi=Active_High\r
-CSET use_clock_enable=false\r
-CSET use_dout_reset=true\r
-CSET use_embedded_registers=false\r
-CSET use_extra_logic=false\r
-CSET valid_flag=false\r
-CSET valid_sense=Active_High\r
-CSET wach_type=FIFO\r
-CSET wdch_type=FIFO\r
-CSET wrch_type=FIFO\r
-CSET write_acknowledge_flag=false\r
-CSET write_acknowledge_sense=Active_High\r
-CSET write_clock_frequency=1\r
-CSET write_data_count=false\r
-CSET write_data_count_width=9\r
-CSET wuser_width=1\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2012-11-19T12:39:56Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: 2a3474ef\r
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\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
---------------------------------------------------------------------------------\r
--- You must compile the wrapper file sync_fifo_FWFT_512x36.vhd when simulating\r
--- the core, sync_fifo_FWFT_512x36. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
--- The synthesis directives "translate_off/translate_on" specified\r
--- below are supported by Xilinx, Mentor Graphics and Synplicity\r
--- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
--- synthesis translate_off\r
-LIBRARY XilinxCoreLib;\r
--- synthesis translate_on\r
-ENTITY sync_fifo_FWFT_512x36 IS\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END sync_fifo_FWFT_512x36;\r
-\r
-ARCHITECTURE sync_fifo_FWFT_512x36_a OF sync_fifo_FWFT_512x36 IS\r
--- synthesis translate_off\r
-COMPONENT wrapped_sync_fifo_FWFT_512x36\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
-\r
--- Configuration specification\r
- FOR ALL : wrapped_sync_fifo_FWFT_512x36 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
- GENERIC MAP (\r
- c_add_ngc_constraint => 0,\r
- c_application_type_axis => 0,\r
- c_application_type_rach => 0,\r
- c_application_type_rdch => 0,\r
- c_application_type_wach => 0,\r
- c_application_type_wdch => 0,\r
- c_application_type_wrch => 0,\r
- c_axi_addr_width => 32,\r
- c_axi_aruser_width => 1,\r
- c_axi_awuser_width => 1,\r
- c_axi_buser_width => 1,\r
- c_axi_data_width => 64,\r
- c_axi_id_width => 4,\r
- c_axi_ruser_width => 1,\r
- c_axi_type => 0,\r
- c_axi_wuser_width => 1,\r
- c_axis_tdata_width => 64,\r
- c_axis_tdest_width => 4,\r
- c_axis_tid_width => 8,\r
- c_axis_tkeep_width => 4,\r
- c_axis_tstrb_width => 4,\r
- c_axis_tuser_width => 4,\r
- c_axis_type => 0,\r
- c_common_clock => 1,\r
- c_count_type => 0,\r
- c_data_count_width => 10,\r
- c_default_value => "BlankString",\r
- c_din_width => 36,\r
- c_din_width_axis => 1,\r
- c_din_width_rach => 32,\r
- c_din_width_rdch => 64,\r
- c_din_width_wach => 32,\r
- c_din_width_wdch => 64,\r
- c_din_width_wrch => 2,\r
- c_dout_rst_val => "0",\r
- c_dout_width => 36,\r
- c_enable_rlocs => 0,\r
- c_enable_rst_sync => 1,\r
- c_error_injection_type => 0,\r
- c_error_injection_type_axis => 0,\r
- c_error_injection_type_rach => 0,\r
- c_error_injection_type_rdch => 0,\r
- c_error_injection_type_wach => 0,\r
- c_error_injection_type_wdch => 0,\r
- c_error_injection_type_wrch => 0,\r
- c_family => "virtex6",\r
- c_full_flags_rst_val => 1,\r
- c_has_almost_empty => 0,\r
- c_has_almost_full => 0,\r
- c_has_axi_aruser => 0,\r
- c_has_axi_awuser => 0,\r
- c_has_axi_buser => 0,\r
- c_has_axi_rd_channel => 0,\r
- c_has_axi_ruser => 0,\r
- c_has_axi_wr_channel => 0,\r
- c_has_axi_wuser => 0,\r
- c_has_axis_tdata => 0,\r
- c_has_axis_tdest => 0,\r
- c_has_axis_tid => 0,\r
- c_has_axis_tkeep => 0,\r
- c_has_axis_tlast => 0,\r
- c_has_axis_tready => 1,\r
- c_has_axis_tstrb => 0,\r
- c_has_axis_tuser => 0,\r
- c_has_backup => 0,\r
- c_has_data_count => 0,\r
- c_has_data_counts_axis => 0,\r
- c_has_data_counts_rach => 0,\r
- c_has_data_counts_rdch => 0,\r
- c_has_data_counts_wach => 0,\r
- c_has_data_counts_wdch => 0,\r
- c_has_data_counts_wrch => 0,\r
- c_has_int_clk => 0,\r
- c_has_master_ce => 0,\r
- c_has_meminit_file => 0,\r
- c_has_overflow => 0,\r
- c_has_prog_flags_axis => 0,\r
- c_has_prog_flags_rach => 0,\r
- c_has_prog_flags_rdch => 0,\r
- c_has_prog_flags_wach => 0,\r
- c_has_prog_flags_wdch => 0,\r
- c_has_prog_flags_wrch => 0,\r
- c_has_rd_data_count => 0,\r
- c_has_rd_rst => 0,\r
- c_has_rst => 1,\r
- c_has_slave_ce => 0,\r
- c_has_srst => 0,\r
- c_has_underflow => 0,\r
- c_has_valid => 0,\r
- c_has_wr_ack => 0,\r
- c_has_wr_data_count => 0,\r
- c_has_wr_rst => 0,\r
- c_implementation_type => 0,\r
- c_implementation_type_axis => 1,\r
- c_implementation_type_rach => 1,\r
- c_implementation_type_rdch => 1,\r
- c_implementation_type_wach => 1,\r
- c_implementation_type_wdch => 1,\r
- c_implementation_type_wrch => 1,\r
- c_init_wr_pntr_val => 0,\r
- c_interface_type => 0,\r
- c_memory_type => 1,\r
- c_mif_file_name => "BlankString",\r
- c_msgon_val => 1,\r
- c_optimization_mode => 0,\r
- c_overflow_low => 0,\r
- c_preload_latency => 0,\r
- c_preload_regs => 1,\r
- c_prim_fifo_type => "512x36",\r
- c_prog_empty_thresh_assert_val => 4,\r
- c_prog_empty_thresh_assert_val_axis => 1022,\r
- c_prog_empty_thresh_assert_val_rach => 1022,\r
- c_prog_empty_thresh_assert_val_rdch => 1022,\r
- c_prog_empty_thresh_assert_val_wach => 1022,\r
- c_prog_empty_thresh_assert_val_wdch => 1022,\r
- c_prog_empty_thresh_assert_val_wrch => 1022,\r
- c_prog_empty_thresh_negate_val => 5,\r
- c_prog_empty_type => 0,\r
- c_prog_empty_type_axis => 0,\r
- c_prog_empty_type_rach => 0,\r
- c_prog_empty_type_rdch => 0,\r
- c_prog_empty_type_wach => 0,\r
- c_prog_empty_type_wdch => 0,\r
- c_prog_empty_type_wrch => 0,\r
- c_prog_full_thresh_assert_val => 511,\r
- c_prog_full_thresh_assert_val_axis => 1023,\r
- c_prog_full_thresh_assert_val_rach => 1023,\r
- c_prog_full_thresh_assert_val_rdch => 1023,\r
- c_prog_full_thresh_assert_val_wach => 1023,\r
- c_prog_full_thresh_assert_val_wdch => 1023,\r
- c_prog_full_thresh_assert_val_wrch => 1023,\r
- c_prog_full_thresh_negate_val => 510,\r
- c_prog_full_type => 0,\r
- c_prog_full_type_axis => 0,\r
- c_prog_full_type_rach => 0,\r
- c_prog_full_type_rdch => 0,\r
- c_prog_full_type_wach => 0,\r
- c_prog_full_type_wdch => 0,\r
- c_prog_full_type_wrch => 0,\r
- c_rach_type => 0,\r
- c_rd_data_count_width => 10,\r
- c_rd_depth => 512,\r
- c_rd_freq => 1,\r
- c_rd_pntr_width => 9,\r
- c_rdch_type => 0,\r
- c_reg_slice_mode_axis => 0,\r
- c_reg_slice_mode_rach => 0,\r
- c_reg_slice_mode_rdch => 0,\r
- c_reg_slice_mode_wach => 0,\r
- c_reg_slice_mode_wdch => 0,\r
- c_reg_slice_mode_wrch => 0,\r
- c_synchronizer_stage => 2,\r
- c_underflow_low => 0,\r
- c_use_common_overflow => 0,\r
- c_use_common_underflow => 0,\r
- c_use_default_settings => 0,\r
- c_use_dout_rst => 1,\r
- c_use_ecc => 0,\r
- c_use_ecc_axis => 0,\r
- c_use_ecc_rach => 0,\r
- c_use_ecc_rdch => 0,\r
- c_use_ecc_wach => 0,\r
- c_use_ecc_wdch => 0,\r
- c_use_ecc_wrch => 0,\r
- c_use_embedded_reg => 0,\r
- c_use_fifo16_flags => 0,\r
- c_use_fwft_data_count => 1,\r
- c_valid_low => 0,\r
- c_wach_type => 0,\r
- c_wdch_type => 0,\r
- c_wr_ack_low => 0,\r
- c_wr_data_count_width => 10,\r
- c_wr_depth => 512,\r
- c_wr_depth_axis => 1024,\r
- c_wr_depth_rach => 16,\r
- c_wr_depth_rdch => 1024,\r
- c_wr_depth_wach => 16,\r
- c_wr_depth_wdch => 1024,\r
- c_wr_depth_wrch => 16,\r
- c_wr_freq => 1,\r
- c_wr_pntr_width => 9,\r
- c_wr_pntr_width_axis => 10,\r
- c_wr_pntr_width_rach => 4,\r
- c_wr_pntr_width_rdch => 10,\r
- c_wr_pntr_width_wach => 4,\r
- c_wr_pntr_width_wdch => 10,\r
- c_wr_pntr_width_wrch => 4,\r
- c_wr_response_latency => 1,\r
- c_wrch_type => 0\r
- );\r
--- synthesis translate_on\r
-BEGIN\r
--- synthesis translate_off\r
-U0 : wrapped_sync_fifo_FWFT_512x36\r
- PORT MAP (\r
- clk => clk,\r
- rst => rst,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty\r
- );\r
--- synthesis translate_on\r
-\r
-END sync_fifo_FWFT_512x36_a;\r
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
-\r
---------------------------------------------------------------------------------\r
--- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
--- --\r
--- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
--- memory queue generator. Use it to generate resource and performance --\r
--- optimized FIFOs with common or independent read/write clock domains, --\r
--- and optional fixed or programmable full and empty flags and --\r
--- handshaking signals. Choose from a selection of memory resource --\r
--- types for implementation. Optional Hamming code based error --\r
--- detection and correction as well as error injection capability for --\r
--- system test help to insure data integrity. FIFO width and depth are --\r
--- parameterizable, and for native interface FIFOs, asymmetric read and --\r
--- write port widths are also supported. --\r
---------------------------------------------------------------------------------\r
-\r
--- Interfaces:\r
--- AXI4Stream_MASTER_M_AXIS\r
--- AXI4Stream_SLAVE_S_AXIS\r
--- AXI4_MASTER_M_AXI\r
--- AXI4_SLAVE_S_AXI\r
--- AXI4Lite_MASTER_M_AXI\r
--- AXI4Lite_SLAVE_S_AXI\r
--- master_aclk\r
--- slave_aclk\r
--- slave_aresetn\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-COMPONENT sync_fifo_FWFT_512x36\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
-\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : sync_fifo_FWFT_512x36\r
- PORT MAP (\r
- clk => clk,\r
- rst => rst,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty\r
- );\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
-\r
--- You must compile the wrapper file sync_fifo_FWFT_512x36.vhd when simulating\r
--- the core, sync_fifo_FWFT_512x36. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Fri Sep 19 14:17:44 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
-# END Select\r
-# BEGIN Parameters\r
-CSET add_ngc_constraint_axi=false\r
-CSET almost_empty_flag=false\r
-CSET almost_full_flag=false\r
-CSET aruser_width=1\r
-CSET awuser_width=1\r
-CSET axi_address_width=32\r
-CSET axi_data_width=64\r
-CSET axi_type=AXI4_Stream\r
-CSET axis_type=FIFO\r
-CSET buser_width=1\r
-CSET clock_enable_type=Slave_Interface_Clock_Enable\r
-CSET clock_type_axi=Common_Clock\r
-CSET component_name=sync_fifo_FWFT_512x36\r
-CSET data_count=false\r
-CSET data_count_width=10\r
-CSET disable_timing_violations=false\r
-CSET disable_timing_violations_axi=false\r
-CSET dout_reset_value=0\r
-CSET empty_threshold_assert_value=4\r
-CSET empty_threshold_assert_value_axis=1022\r
-CSET empty_threshold_assert_value_rach=1022\r
-CSET empty_threshold_assert_value_rdch=1022\r
-CSET empty_threshold_assert_value_wach=1022\r
-CSET empty_threshold_assert_value_wdch=1022\r
-CSET empty_threshold_assert_value_wrch=1022\r
-CSET empty_threshold_negate_value=5\r
-CSET enable_aruser=false\r
-CSET enable_awuser=false\r
-CSET enable_buser=false\r
-CSET enable_common_overflow=false\r
-CSET enable_common_underflow=false\r
-CSET enable_data_counts_axis=false\r
-CSET enable_data_counts_rach=false\r
-CSET enable_data_counts_rdch=false\r
-CSET enable_data_counts_wach=false\r
-CSET enable_data_counts_wdch=false\r
-CSET enable_data_counts_wrch=false\r
-CSET enable_ecc=false\r
-CSET enable_ecc_axis=false\r
-CSET enable_ecc_rach=false\r
-CSET enable_ecc_rdch=false\r
-CSET enable_ecc_wach=false\r
-CSET enable_ecc_wdch=false\r
-CSET enable_ecc_wrch=false\r
-CSET enable_read_channel=false\r
-CSET enable_read_pointer_increment_by2=false\r
-CSET enable_reset_synchronization=true\r
-CSET enable_ruser=false\r
-CSET enable_tdata=false\r
-CSET enable_tdest=false\r
-CSET enable_tid=false\r
-CSET enable_tkeep=false\r
-CSET enable_tlast=false\r
-CSET enable_tready=true\r
-CSET enable_tstrobe=false\r
-CSET enable_tuser=false\r
-CSET enable_write_channel=false\r
-CSET enable_wuser=false\r
-CSET fifo_application_type_axis=Data_FIFO\r
-CSET fifo_application_type_rach=Data_FIFO\r
-CSET fifo_application_type_rdch=Data_FIFO\r
-CSET fifo_application_type_wach=Data_FIFO\r
-CSET fifo_application_type_wdch=Data_FIFO\r
-CSET fifo_application_type_wrch=Data_FIFO\r
-CSET fifo_implementation=Common_Clock_Block_RAM\r
-CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
-CSET full_flags_reset_value=1\r
-CSET full_threshold_assert_value=511\r
-CSET full_threshold_assert_value_axis=1023\r
-CSET full_threshold_assert_value_rach=1023\r
-CSET full_threshold_assert_value_rdch=1023\r
-CSET full_threshold_assert_value_wach=1023\r
-CSET full_threshold_assert_value_wdch=1023\r
-CSET full_threshold_assert_value_wrch=1023\r
-CSET full_threshold_negate_value=510\r
-CSET id_width=4\r
-CSET inject_dbit_error=false\r
-CSET inject_dbit_error_axis=false\r
-CSET inject_dbit_error_rach=false\r
-CSET inject_dbit_error_rdch=false\r
-CSET inject_dbit_error_wach=false\r
-CSET inject_dbit_error_wdch=false\r
-CSET inject_dbit_error_wrch=false\r
-CSET inject_sbit_error=false\r
-CSET inject_sbit_error_axis=false\r
-CSET inject_sbit_error_rach=false\r
-CSET inject_sbit_error_rdch=false\r
-CSET inject_sbit_error_wach=false\r
-CSET inject_sbit_error_wdch=false\r
-CSET inject_sbit_error_wrch=false\r
-CSET input_data_width=36\r
-CSET input_depth=512\r
-CSET input_depth_axis=1024\r
-CSET input_depth_rach=16\r
-CSET input_depth_rdch=1024\r
-CSET input_depth_wach=16\r
-CSET input_depth_wdch=1024\r
-CSET input_depth_wrch=16\r
-CSET interface_type=Native\r
-CSET output_data_width=36\r
-CSET output_depth=512\r
-CSET overflow_flag=false\r
-CSET overflow_flag_axi=false\r
-CSET overflow_sense=Active_High\r
-CSET overflow_sense_axi=Active_High\r
-CSET performance_options=First_Word_Fall_Through\r
-CSET programmable_empty_type=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
-CSET programmable_full_type=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
-CSET rach_type=FIFO\r
-CSET rdch_type=FIFO\r
-CSET read_clock_frequency=1\r
-CSET read_data_count=false\r
-CSET read_data_count_width=10\r
-CSET register_slice_mode_axis=Fully_Registered\r
-CSET register_slice_mode_rach=Fully_Registered\r
-CSET register_slice_mode_rdch=Fully_Registered\r
-CSET register_slice_mode_wach=Fully_Registered\r
-CSET register_slice_mode_wdch=Fully_Registered\r
-CSET register_slice_mode_wrch=Fully_Registered\r
-CSET reset_pin=true\r
-CSET reset_type=Asynchronous_Reset\r
-CSET ruser_width=1\r
-CSET synchronization_stages=2\r
-CSET synchronization_stages_axi=2\r
-CSET tdata_width=64\r
-CSET tdest_width=4\r
-CSET tid_width=8\r
-CSET tkeep_width=4\r
-CSET tstrb_width=4\r
-CSET tuser_width=4\r
-CSET underflow_flag=false\r
-CSET underflow_flag_axi=false\r
-CSET underflow_sense=Active_High\r
-CSET underflow_sense_axi=Active_High\r
-CSET use_clock_enable=false\r
-CSET use_dout_reset=true\r
-CSET use_embedded_registers=false\r
-CSET use_extra_logic=true\r
-CSET valid_flag=false\r
-CSET valid_sense=Active_High\r
-CSET wach_type=FIFO\r
-CSET wdch_type=FIFO\r
-CSET wrch_type=FIFO\r
-CSET write_acknowledge_flag=false\r
-CSET write_acknowledge_sense=Active_High\r
-CSET write_clock_frequency=1\r
-CSET write_data_count=false\r
-CSET write_data_count_width=10\r
-CSET wuser_width=1\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2012-11-19T12:39:56Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: c1caed69\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
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- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="sync_fifo_FWFT_512x36.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="sync_fifo_FWFT_512x36.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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- </file>
- </files>
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- <properties>
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- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="Implementation Top File" xil_pn:value="sync_fifo_FWFT_512x36.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sync_fifo_FWFT_512x36" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="sync_fifo_FWFT_512x36" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
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- <autoManagedFiles>
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- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 sync_fifo_progfull364_progempty128_512x36
-RECTANGLE Normal 32 32 800 4064
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName din[35:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 464 32 464
-PIN 0 464 LEFT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Normal 0 528 32 528
-PIN 0 528 LEFT 36
-PINATTR PinName prog_full
-PINATTR Polarity OUT
-LINE Wide 832 272 800 272
-PIN 832 272 RIGHT 36
-PINATTR PinName dout[35:0]
-PINATTR Polarity OUT
-LINE Normal 832 304 800 304
-PIN 832 304 RIGHT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 832 496 800 496
-PIN 832 496 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-LINE Normal 832 560 800 560
-PIN 832 560 RIGHT 36
-PINATTR PinName prog_empty
-PINATTR Polarity OUT
-\r
+++ /dev/null
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- <!-- -->\r
-\r
- <!-- For tool use only. Do not edit. -->\r
-\r
- <!-- -->\r
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- <!-- ProjectNavigator created generated project file. -->\r
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\7f>k50;0xZ6c<5=896;=4}r1g>5<5sW9o70:=2;41?xu4k3:1>vP<c:?767<1n2wx?o4?:3y]7g=:<;81:h5rs2c94?4|V:k019<=:7f8yv5>2909wS=6;<616?0d3ty847>52z\0<>;3:;0=n6s|d583>7}Yl=168?<51148yvb52909wSj=;<616?gc3tyo=7>52z\g5>;3:;0jn6s|d183>7}Yl9168?<5a`9~wf`=838pRnh4=501>d?<uzin6=4={_af?825:3k37p}lc;296~Xdk27?>?4n7:
\7fpgg<72;qUoo524309f3=z{jk1<7<t^bc891452k?0q~m6:181
\7f[e>34>9>7??4:
\7fpg=<72;qUo5524309f1=z{j=1<7<t^b5891452k90q~m9:181
\7f[e134>9>7l=;|q`1?6=:rTh963;238a5>{tk=0;6?uQc59>074=j91v
\7fn=50;0xZf5<5=896lh4}ra2>5<5sWi:70:=2;cf?xud83:1>vPl0:?767<f>2wxnk4?:3y]fc=:<;81===4}r`f>5<5sWhn70:=2;;`?xuel3:1>vPmd:?767<>i2wxnn4?:3y]ff=:<;81545rsc`94?4|Vkh019<=:8:8yvdf2909wSln;<616??03tyi57>52z\a=>;3:;02:6s|b983>7}Yj1168?<5a49~wad=838pRil4=501>d2<uznj6=4={_fb?825:3;;=6s|d883>7}Yl0168?<5a29~wa>=838pRi64=501>d4<uzn<6=4={_f4?825:3k:7p}k6;296~Xc>27?>?4n0:
\7fp`0<72;qUh8524309=c=z{jn1<7<t^bf8914520o0q~m=:181
\7f[e534>9>77k;|qa3?6=:rTi;63;238:1>{t:8o1<7=t^33f?825:38:j63;238165=z{<n1<7<t^4f891452==0q~;m:181
\7f[3e34>9>7::;|q6e?6=:rT>m63;23870>{t=00;6?uQ589>074=<:1v
\7f8650;0xZ0><5=8968>4}r74>5<5sW?<70:=2;6e?xu2>3:1>vP:6:?767<3m2wx984?:3y]10=:<;818i5rs4694?4|V<>019<=:5a8yv1b2909wS9j;<616?>13ty:;o4?:3y]52d<5=896<9j;|q;0?6=:rT3863;238;7>{t9>n1<7<t^05g?825:3;<o6s|16194?4|V8=870:=2;304>{t9>;1<7<t^052?825:3;9<6s|16294?4|V8=;70:=2;32a>{t9?l1<7<t^04e?825:3;:h6s|17g94?4|V8<n70:=2;32g>{t9?n1<7<t^04g?825:3;:n6s|17`94?4|V8<i70:=2;32e>{t9?k1<7<t^04b?825:3;956s|17;94?4|V8<270:=2;31<>{t9?21<7<t^04;?825:3;9i6s|17594?4|V8<<70:=2;313>{t9?<1<7<t^045?825:3;9:6s|17794?4|V8<>70:=2;311>{t9?>1<7<t^047?825:3;986s|17194?4|V8<870:=2;317>{t9?81<7<t^041?825:3;9>6s|17294?4|V8<;70:=2;315>{t9<l1<7<t^07e?825:3;:56s|14g94?4|V8?n70:=2;31`>{t9<n1<7<t^07g?825:3;;i6s|14a94?4|V8?h70:=2;33g>{t9<h1<7<t^07a?825:3;;n6s|14c94?4|V8?j70:=2;33e>{t9<31<7<t^07:?825:3;;56s|14:94?4|V8?370:=2;33<>{t9<=1<7<t^074?825:3;:;6s|16c94?4|V8=j70:=2;322>{t9>31<7<t^05:?825:3;9n6s|16:94?4|V8=370:=2;321>{t9>=1<7<t^054?825:3;:86s|16494?4|V8==70:=2;327>{t9>?1<7<t^056?825:3;:>6s|16694?4|V8=?70:=2;325>{t9?i1<7<t^04`?825:3;:<6s|17394?4|V8<:70:=2;33b>{t9<<1<7<t^075?825:3;;;6s|9383>16|5:kn6<6m;_;1?[45?2T9<i5Q21`8Z76f3W8;56P=099]651<V;:=7S<?5:\141=:<;81><;4=501>1d<5=8969o4=501>1?<5=896964=501>14<5=896;o4=501>3?<5=896;64=501>31<5=896;?4=501>6?234>9>7=64:?767<59?168?<5233891452;897S?<1:\27f=Y9==0R<:i;_364>X6=81U=8<4^070?[72<2T:985Q1208Z4543W;886P>349]560<V89<7S?<8:\27<=Y9:k0R<=m;_30`>X6;l1U=>h4^063?[7392T:8?5Q1518Z4233W;?96P>479]51><V8>27S?;a:\20g=Y9=i0R<:j;|
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\7fa61c=8391<7>t$310>6gd3A9jh6F<919j32<722c:i>4?::m2b2<722wi>9j50;194?6|,;986>ol;I1b`>N4191b;:4?::k2a6<722e:j:4?::
\7fa66e=83>1<7>t$310>4cc3A9jh6F<919j32<722c287>5;h011?6=3f;m;7>5;|`10f<72:0;6=u+22197de<@:ko7E=60:k43?6=3`;n?7>5;n3e3?6=3th9?o4?:583>5}#::91=hj4H2cg?M5>82c<;7>5;h;7>5<<a;8>6=44o0d4>5<<uk8?n7>53;294~"5;:08mn5G3`f8L6?73`=<6=44i0g0>5<<g8l<6=44}c00e?6=<3:1<v*=3282aa=O;hn0D>7?;h54>5<<a0>1<75f23794?=h9o=1<75rb36b>5<4290;w)<<3;1bg>N4im1C?4>4i6594?=n9l91<75`1g594?=zj;926=4;:183
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\7f5{GHYqvLM
\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
---------------------------------------------------------------------------------\r
--- You must compile the wrapper file sync_fifo_progfull364_progempty128_512x36.vhd when simulating\r
--- the core, sync_fifo_progfull364_progempty128_512x36. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
--- The synthesis directives "translate_off/translate_on" specified\r
--- below are supported by Xilinx, Mentor Graphics and Synplicity\r
--- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
--- synthesis translate_off\r
-LIBRARY XilinxCoreLib;\r
--- synthesis translate_on\r
-ENTITY sync_fifo_progfull364_progempty128_512x36 IS\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC;\r
- prog_full : OUT STD_LOGIC;\r
- prog_empty : OUT STD_LOGIC\r
- );\r
-END sync_fifo_progfull364_progempty128_512x36;\r
-\r
-ARCHITECTURE sync_fifo_progfull364_progempty128_512x36_a OF sync_fifo_progfull364_progempty128_512x36 IS\r
--- synthesis translate_off\r
-COMPONENT wrapped_sync_fifo_progfull364_progempty128_512x36\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC;\r
- prog_full : OUT STD_LOGIC;\r
- prog_empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
-\r
--- Configuration specification\r
- FOR ALL : wrapped_sync_fifo_progfull364_progempty128_512x36 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
- GENERIC MAP (\r
- c_add_ngc_constraint => 0,\r
- c_application_type_axis => 0,\r
- c_application_type_rach => 0,\r
- c_application_type_rdch => 0,\r
- c_application_type_wach => 0,\r
- c_application_type_wdch => 0,\r
- c_application_type_wrch => 0,\r
- c_axi_addr_width => 32,\r
- c_axi_aruser_width => 1,\r
- c_axi_awuser_width => 1,\r
- c_axi_buser_width => 1,\r
- c_axi_data_width => 64,\r
- c_axi_id_width => 4,\r
- c_axi_ruser_width => 1,\r
- c_axi_type => 0,\r
- c_axi_wuser_width => 1,\r
- c_axis_tdata_width => 64,\r
- c_axis_tdest_width => 4,\r
- c_axis_tid_width => 8,\r
- c_axis_tkeep_width => 4,\r
- c_axis_tstrb_width => 4,\r
- c_axis_tuser_width => 4,\r
- c_axis_type => 0,\r
- c_common_clock => 1,\r
- c_count_type => 0,\r
- c_data_count_width => 9,\r
- c_default_value => "BlankString",\r
- c_din_width => 36,\r
- c_din_width_axis => 1,\r
- c_din_width_rach => 32,\r
- c_din_width_rdch => 64,\r
- c_din_width_wach => 32,\r
- c_din_width_wdch => 64,\r
- c_din_width_wrch => 2,\r
- c_dout_rst_val => "0",\r
- c_dout_width => 36,\r
- c_enable_rlocs => 0,\r
- c_enable_rst_sync => 1,\r
- c_error_injection_type => 0,\r
- c_error_injection_type_axis => 0,\r
- c_error_injection_type_rach => 0,\r
- c_error_injection_type_rdch => 0,\r
- c_error_injection_type_wach => 0,\r
- c_error_injection_type_wdch => 0,\r
- c_error_injection_type_wrch => 0,\r
- c_family => "virtex6",\r
- c_full_flags_rst_val => 1,\r
- c_has_almost_empty => 0,\r
- c_has_almost_full => 0,\r
- c_has_axi_aruser => 0,\r
- c_has_axi_awuser => 0,\r
- c_has_axi_buser => 0,\r
- c_has_axi_rd_channel => 0,\r
- c_has_axi_ruser => 0,\r
- c_has_axi_wr_channel => 0,\r
- c_has_axi_wuser => 0,\r
- c_has_axis_tdata => 0,\r
- c_has_axis_tdest => 0,\r
- c_has_axis_tid => 0,\r
- c_has_axis_tkeep => 0,\r
- c_has_axis_tlast => 0,\r
- c_has_axis_tready => 1,\r
- c_has_axis_tstrb => 0,\r
- c_has_axis_tuser => 0,\r
- c_has_backup => 0,\r
- c_has_data_count => 0,\r
- c_has_data_counts_axis => 0,\r
- c_has_data_counts_rach => 0,\r
- c_has_data_counts_rdch => 0,\r
- c_has_data_counts_wach => 0,\r
- c_has_data_counts_wdch => 0,\r
- c_has_data_counts_wrch => 0,\r
- c_has_int_clk => 0,\r
- c_has_master_ce => 0,\r
- c_has_meminit_file => 0,\r
- c_has_overflow => 0,\r
- c_has_prog_flags_axis => 0,\r
- c_has_prog_flags_rach => 0,\r
- c_has_prog_flags_rdch => 0,\r
- c_has_prog_flags_wach => 0,\r
- c_has_prog_flags_wdch => 0,\r
- c_has_prog_flags_wrch => 0,\r
- c_has_rd_data_count => 0,\r
- c_has_rd_rst => 0,\r
- c_has_rst => 1,\r
- c_has_slave_ce => 0,\r
- c_has_srst => 0,\r
- c_has_underflow => 0,\r
- c_has_valid => 0,\r
- c_has_wr_ack => 0,\r
- c_has_wr_data_count => 0,\r
- c_has_wr_rst => 0,\r
- c_implementation_type => 0,\r
- c_implementation_type_axis => 1,\r
- c_implementation_type_rach => 1,\r
- c_implementation_type_rdch => 1,\r
- c_implementation_type_wach => 1,\r
- c_implementation_type_wdch => 1,\r
- c_implementation_type_wrch => 1,\r
- c_init_wr_pntr_val => 0,\r
- c_interface_type => 0,\r
- c_memory_type => 1,\r
- c_mif_file_name => "BlankString",\r
- c_msgon_val => 1,\r
- c_optimization_mode => 0,\r
- c_overflow_low => 0,\r
- c_preload_latency => 1,\r
- c_preload_regs => 0,\r
- c_prim_fifo_type => "512x36",\r
- c_prog_empty_thresh_assert_val => 128,\r
- c_prog_empty_thresh_assert_val_axis => 1022,\r
- c_prog_empty_thresh_assert_val_rach => 1022,\r
- c_prog_empty_thresh_assert_val_rdch => 1022,\r
- c_prog_empty_thresh_assert_val_wach => 1022,\r
- c_prog_empty_thresh_assert_val_wdch => 1022,\r
- c_prog_empty_thresh_assert_val_wrch => 1022,\r
- c_prog_empty_thresh_negate_val => 129,\r
- c_prog_empty_type => 1,\r
- c_prog_empty_type_axis => 0,\r
- c_prog_empty_type_rach => 0,\r
- c_prog_empty_type_rdch => 0,\r
- c_prog_empty_type_wach => 0,\r
- c_prog_empty_type_wdch => 0,\r
- c_prog_empty_type_wrch => 0,\r
- c_prog_full_thresh_assert_val => 364,\r
- c_prog_full_thresh_assert_val_axis => 1023,\r
- c_prog_full_thresh_assert_val_rach => 1023,\r
- c_prog_full_thresh_assert_val_rdch => 1023,\r
- c_prog_full_thresh_assert_val_wach => 1023,\r
- c_prog_full_thresh_assert_val_wdch => 1023,\r
- c_prog_full_thresh_assert_val_wrch => 1023,\r
- c_prog_full_thresh_negate_val => 363,\r
- c_prog_full_type => 1,\r
- c_prog_full_type_axis => 0,\r
- c_prog_full_type_rach => 0,\r
- c_prog_full_type_rdch => 0,\r
- c_prog_full_type_wach => 0,\r
- c_prog_full_type_wdch => 0,\r
- c_prog_full_type_wrch => 0,\r
- c_rach_type => 0,\r
- c_rd_data_count_width => 9,\r
- c_rd_depth => 512,\r
- c_rd_freq => 1,\r
- c_rd_pntr_width => 9,\r
- c_rdch_type => 0,\r
- c_reg_slice_mode_axis => 0,\r
- c_reg_slice_mode_rach => 0,\r
- c_reg_slice_mode_rdch => 0,\r
- c_reg_slice_mode_wach => 0,\r
- c_reg_slice_mode_wdch => 0,\r
- c_reg_slice_mode_wrch => 0,\r
- c_synchronizer_stage => 2,\r
- c_underflow_low => 0,\r
- c_use_common_overflow => 0,\r
- c_use_common_underflow => 0,\r
- c_use_default_settings => 0,\r
- c_use_dout_rst => 1,\r
- c_use_ecc => 0,\r
- c_use_ecc_axis => 0,\r
- c_use_ecc_rach => 0,\r
- c_use_ecc_rdch => 0,\r
- c_use_ecc_wach => 0,\r
- c_use_ecc_wdch => 0,\r
- c_use_ecc_wrch => 0,\r
- c_use_embedded_reg => 0,\r
- c_use_fifo16_flags => 0,\r
- c_use_fwft_data_count => 0,\r
- c_valid_low => 0,\r
- c_wach_type => 0,\r
- c_wdch_type => 0,\r
- c_wr_ack_low => 0,\r
- c_wr_data_count_width => 9,\r
- c_wr_depth => 512,\r
- c_wr_depth_axis => 1024,\r
- c_wr_depth_rach => 16,\r
- c_wr_depth_rdch => 1024,\r
- c_wr_depth_wach => 16,\r
- c_wr_depth_wdch => 1024,\r
- c_wr_depth_wrch => 16,\r
- c_wr_freq => 1,\r
- c_wr_pntr_width => 9,\r
- c_wr_pntr_width_axis => 10,\r
- c_wr_pntr_width_rach => 4,\r
- c_wr_pntr_width_rdch => 10,\r
- c_wr_pntr_width_wach => 4,\r
- c_wr_pntr_width_wdch => 10,\r
- c_wr_pntr_width_wrch => 4,\r
- c_wr_response_latency => 1,\r
- c_wrch_type => 0\r
- );\r
--- synthesis translate_on\r
-BEGIN\r
--- synthesis translate_off\r
-U0 : wrapped_sync_fifo_progfull364_progempty128_512x36\r
- PORT MAP (\r
- clk => clk,\r
- rst => rst,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty,\r
- prog_full => prog_full,\r
- prog_empty => prog_empty\r
- );\r
--- synthesis translate_on\r
-\r
-END sync_fifo_progfull364_progempty128_512x36_a;\r
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
-\r
---------------------------------------------------------------------------------\r
--- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
--- --\r
--- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
--- memory queue generator. Use it to generate resource and performance --\r
--- optimized FIFOs with common or independent read/write clock domains, --\r
--- and optional fixed or programmable full and empty flags and --\r
--- handshaking signals. Choose from a selection of memory resource --\r
--- types for implementation. Optional Hamming code based error --\r
--- detection and correction as well as error injection capability for --\r
--- system test help to insure data integrity. FIFO width and depth are --\r
--- parameterizable, and for native interface FIFOs, asymmetric read and --\r
--- write port widths are also supported. --\r
---------------------------------------------------------------------------------\r
-\r
--- Interfaces:\r
--- AXI4Stream_MASTER_M_AXIS\r
--- AXI4Stream_SLAVE_S_AXIS\r
--- AXI4_MASTER_M_AXI\r
--- AXI4_SLAVE_S_AXI\r
--- AXI4Lite_MASTER_M_AXI\r
--- AXI4Lite_SLAVE_S_AXI\r
--- master_aclk\r
--- slave_aclk\r
--- slave_aresetn\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-COMPONENT sync_fifo_progfull364_progempty128_512x36\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC;\r
- prog_full : OUT STD_LOGIC;\r
- prog_empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
-\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : sync_fifo_progfull364_progempty128_512x36\r
- PORT MAP (\r
- clk => clk,\r
- rst => rst,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty,\r
- prog_full => prog_full,\r
- prog_empty => prog_empty\r
- );\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
-\r
--- You must compile the wrapper file sync_fifo_progfull364_progempty128_512x36.vhd when simulating\r
--- the core, sync_fifo_progfull364_progempty128_512x36. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Mon Oct 20 06:54:50 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
-# END Select\r
-# BEGIN Parameters\r
-CSET add_ngc_constraint_axi=false\r
-CSET almost_empty_flag=false\r
-CSET almost_full_flag=false\r
-CSET aruser_width=1\r
-CSET awuser_width=1\r
-CSET axi_address_width=32\r
-CSET axi_data_width=64\r
-CSET axi_type=AXI4_Stream\r
-CSET axis_type=FIFO\r
-CSET buser_width=1\r
-CSET clock_enable_type=Slave_Interface_Clock_Enable\r
-CSET clock_type_axi=Common_Clock\r
-CSET component_name=sync_fifo_progfull364_progempty128_512x36\r
-CSET data_count=false\r
-CSET data_count_width=9\r
-CSET disable_timing_violations=false\r
-CSET disable_timing_violations_axi=false\r
-CSET dout_reset_value=0\r
-CSET empty_threshold_assert_value=128\r
-CSET empty_threshold_assert_value_axis=1022\r
-CSET empty_threshold_assert_value_rach=1022\r
-CSET empty_threshold_assert_value_rdch=1022\r
-CSET empty_threshold_assert_value_wach=1022\r
-CSET empty_threshold_assert_value_wdch=1022\r
-CSET empty_threshold_assert_value_wrch=1022\r
-CSET empty_threshold_negate_value=129\r
-CSET enable_aruser=false\r
-CSET enable_awuser=false\r
-CSET enable_buser=false\r
-CSET enable_common_overflow=false\r
-CSET enable_common_underflow=false\r
-CSET enable_data_counts_axis=false\r
-CSET enable_data_counts_rach=false\r
-CSET enable_data_counts_rdch=false\r
-CSET enable_data_counts_wach=false\r
-CSET enable_data_counts_wdch=false\r
-CSET enable_data_counts_wrch=false\r
-CSET enable_ecc=false\r
-CSET enable_ecc_axis=false\r
-CSET enable_ecc_rach=false\r
-CSET enable_ecc_rdch=false\r
-CSET enable_ecc_wach=false\r
-CSET enable_ecc_wdch=false\r
-CSET enable_ecc_wrch=false\r
-CSET enable_read_channel=false\r
-CSET enable_read_pointer_increment_by2=false\r
-CSET enable_reset_synchronization=true\r
-CSET enable_ruser=false\r
-CSET enable_tdata=false\r
-CSET enable_tdest=false\r
-CSET enable_tid=false\r
-CSET enable_tkeep=false\r
-CSET enable_tlast=false\r
-CSET enable_tready=true\r
-CSET enable_tstrobe=false\r
-CSET enable_tuser=false\r
-CSET enable_write_channel=false\r
-CSET enable_wuser=false\r
-CSET fifo_application_type_axis=Data_FIFO\r
-CSET fifo_application_type_rach=Data_FIFO\r
-CSET fifo_application_type_rdch=Data_FIFO\r
-CSET fifo_application_type_wach=Data_FIFO\r
-CSET fifo_application_type_wdch=Data_FIFO\r
-CSET fifo_application_type_wrch=Data_FIFO\r
-CSET fifo_implementation=Common_Clock_Block_RAM\r
-CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
-CSET full_flags_reset_value=1\r
-CSET full_threshold_assert_value=364\r
-CSET full_threshold_assert_value_axis=1023\r
-CSET full_threshold_assert_value_rach=1023\r
-CSET full_threshold_assert_value_rdch=1023\r
-CSET full_threshold_assert_value_wach=1023\r
-CSET full_threshold_assert_value_wdch=1023\r
-CSET full_threshold_assert_value_wrch=1023\r
-CSET full_threshold_negate_value=363\r
-CSET id_width=4\r
-CSET inject_dbit_error=false\r
-CSET inject_dbit_error_axis=false\r
-CSET inject_dbit_error_rach=false\r
-CSET inject_dbit_error_rdch=false\r
-CSET inject_dbit_error_wach=false\r
-CSET inject_dbit_error_wdch=false\r
-CSET inject_dbit_error_wrch=false\r
-CSET inject_sbit_error=false\r
-CSET inject_sbit_error_axis=false\r
-CSET inject_sbit_error_rach=false\r
-CSET inject_sbit_error_rdch=false\r
-CSET inject_sbit_error_wach=false\r
-CSET inject_sbit_error_wdch=false\r
-CSET inject_sbit_error_wrch=false\r
-CSET input_data_width=36\r
-CSET input_depth=512\r
-CSET input_depth_axis=1024\r
-CSET input_depth_rach=16\r
-CSET input_depth_rdch=1024\r
-CSET input_depth_wach=16\r
-CSET input_depth_wdch=1024\r
-CSET input_depth_wrch=16\r
-CSET interface_type=Native\r
-CSET output_data_width=36\r
-CSET output_depth=512\r
-CSET overflow_flag=false\r
-CSET overflow_flag_axi=false\r
-CSET overflow_sense=Active_High\r
-CSET overflow_sense_axi=Active_High\r
-CSET performance_options=Standard_FIFO\r
-CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant\r
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
-CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant\r
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
-CSET rach_type=FIFO\r
-CSET rdch_type=FIFO\r
-CSET read_clock_frequency=1\r
-CSET read_data_count=false\r
-CSET read_data_count_width=9\r
-CSET register_slice_mode_axis=Fully_Registered\r
-CSET register_slice_mode_rach=Fully_Registered\r
-CSET register_slice_mode_rdch=Fully_Registered\r
-CSET register_slice_mode_wach=Fully_Registered\r
-CSET register_slice_mode_wdch=Fully_Registered\r
-CSET register_slice_mode_wrch=Fully_Registered\r
-CSET reset_pin=true\r
-CSET reset_type=Asynchronous_Reset\r
-CSET ruser_width=1\r
-CSET synchronization_stages=2\r
-CSET synchronization_stages_axi=2\r
-CSET tdata_width=64\r
-CSET tdest_width=4\r
-CSET tid_width=8\r
-CSET tkeep_width=4\r
-CSET tstrb_width=4\r
-CSET tuser_width=4\r
-CSET underflow_flag=false\r
-CSET underflow_flag_axi=false\r
-CSET underflow_sense=Active_High\r
-CSET underflow_sense_axi=Active_High\r
-CSET use_clock_enable=false\r
-CSET use_dout_reset=true\r
-CSET use_embedded_registers=false\r
-CSET use_extra_logic=false\r
-CSET valid_flag=false\r
-CSET valid_sense=Active_High\r
-CSET wach_type=FIFO\r
-CSET wdch_type=FIFO\r
-CSET wrch_type=FIFO\r
-CSET write_acknowledge_flag=false\r
-CSET write_acknowledge_sense=Active_High\r
-CSET write_clock_frequency=1\r
-CSET write_data_count=false\r
-CSET write_data_count_width=9\r
-CSET wuser_width=1\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2012-11-19T12:39:56Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: 5a086950\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="sync_fifo_progfull364_progempty128_512x36.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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\7fM5>82we:h?50;3xL6?73td=i?4?:0yK7<6<ug<n?7>51zJ0=5=zf?o?6=4>{I1:4>{i>l?1<7?tH2;3?xh1m?0;6<uG3828yk0b?3:1=vF<919~j3c?290:wE=60:
\7fm2`?=83;pD>7?;|l5ad<728qC?4>4}o4ff?6=9rB85=5rn7g`>5<6sA92<6sa6df94?7|@:3;7p`9ed83>4}O;0:0qc8jf;295~N4191vb;h?:182
\7fM5>82we:k?50;3xL6?73td=j?4?:0yK7<6<ug<m?7>51zJ0=5=zf?l?6=4>{I1:4>{i>o?1<7?tH2;3?xh1n?0;6<uG3828yk0a?3:1=vF<919~j3`?290:wE=60:
\7fm2c?=83;pD>7?;|l5bd<728qC?4>4}o4ef?6=9rB85=5rn7d`>5<6sA92<6sa6gf94?7|@:3;7p`9fd83>4}O;0:0qc8if;295~N4191vb:>?:182
\7fM5>82we;=?50;3xL6?73td<<?4?:0yK7<6<ug=;?7>51zJ0=5=zf>:?6=4>{I1:4>{i?9?1<7?tH2;3?xh08?0;6<uG3828yk17?3:1=vF<919~j26?290:wE=60:
\7fm35?=83;pD>7?;|l44d<728qC?4>4}o53f?6=9rB85=5rn62`>5<6sA92<6sa71f94?7|@:3;7p`80d83>4}O;0:0qc9?f;295~N4191vb:??:182
\7fM5>82we;<?50;3xL6?73td<=?4?:0yK7<6<ug=:?7>51zJ0=5=zf>;?6=4>{I1:4>{i?8?1<7?tH2;3?xh09?0;6<uG3828yk16?3:1=vF<919~j27?290:wE=60:
\7fm34?=83;pD>7?;|l45d<728qC?4>4}o52f?6=9rB85=5rn63`>5<6sA92<6sa70f94?7|@:3;7p`81d83>4}O;0:0qc9>f;295~N4191vb:<?:182
\7fM5>82we;??50;3xL6?73td<>?4?:0yK7<6<ug=9?7>51zJ0=5=zf>8?6=4>{I1:4>{i?;?1<7?tH2;3?xh0:?0;6<uG3828yk15?3:1=vF<919~j24?290:wE=60:
\7fm37?=83;pD>7?;|l46d<728qC?4>4}o51f?6=9rB85=5rn60`>5<6sA92<6sa73f94?7|@:3;7p`82d83>4}O;0:0qc9=f;295~N4191vb:=?:182
\7fM5>82we;>?50;3xL6?73td<??4?:0yK7<6<ug=8?7>51zJ0=5=zf>9?6=4>{I1:4>{i?:?1<7?tH2;3?xh0;?0;6<uG3828yk14?3:1=vF<919~j25?290:wE=60:
\7fm36?=83;pD>7?;|l47d<728qC?4>4}o50f?6=9rB85=5rn61`>5<6sA92<6sa72f94?7|@:3;7p`83d83>7}O;0:0qc9<f;295~N4191vb::?:182
\7fM5>82we;9?50;3xL6?73td<8?4?:0yK7<6<ug=??7>51zJ0=5=zf;?86=4>{I1:4>{zutJKOv691;0f=db60owKLOu?}ABS
\7fxFG
\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
---------------------------------------------------------------------------------\r
--- You must compile the wrapper file sync_fifo_progfull504_progempty128_512x36.vhd when simulating\r
--- the core, sync_fifo_progfull504_progempty128_512x36. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
--- The synthesis directives "translate_off/translate_on" specified\r
--- below are supported by Xilinx, Mentor Graphics and Synplicity\r
--- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
--- synthesis translate_off\r
-LIBRARY XilinxCoreLib;\r
--- synthesis translate_on\r
-ENTITY sync_fifo_progfull504_progempty128_512x36 IS\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC;\r
- prog_full : OUT STD_LOGIC;\r
- prog_empty : OUT STD_LOGIC\r
- );\r
-END sync_fifo_progfull504_progempty128_512x36;\r
-\r
-ARCHITECTURE sync_fifo_progfull504_progempty128_512x36_a OF sync_fifo_progfull504_progempty128_512x36 IS\r
--- synthesis translate_off\r
-COMPONENT wrapped_sync_fifo_progfull504_progempty128_512x36\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC;\r
- prog_full : OUT STD_LOGIC;\r
- prog_empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
-\r
--- Configuration specification\r
- FOR ALL : wrapped_sync_fifo_progfull504_progempty128_512x36 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
- GENERIC MAP (\r
- c_add_ngc_constraint => 0,\r
- c_application_type_axis => 0,\r
- c_application_type_rach => 0,\r
- c_application_type_rdch => 0,\r
- c_application_type_wach => 0,\r
- c_application_type_wdch => 0,\r
- c_application_type_wrch => 0,\r
- c_axi_addr_width => 32,\r
- c_axi_aruser_width => 1,\r
- c_axi_awuser_width => 1,\r
- c_axi_buser_width => 1,\r
- c_axi_data_width => 64,\r
- c_axi_id_width => 4,\r
- c_axi_ruser_width => 1,\r
- c_axi_type => 0,\r
- c_axi_wuser_width => 1,\r
- c_axis_tdata_width => 64,\r
- c_axis_tdest_width => 4,\r
- c_axis_tid_width => 8,\r
- c_axis_tkeep_width => 4,\r
- c_axis_tstrb_width => 4,\r
- c_axis_tuser_width => 4,\r
- c_axis_type => 0,\r
- c_common_clock => 1,\r
- c_count_type => 0,\r
- c_data_count_width => 9,\r
- c_default_value => "BlankString",\r
- c_din_width => 36,\r
- c_din_width_axis => 1,\r
- c_din_width_rach => 32,\r
- c_din_width_rdch => 64,\r
- c_din_width_wach => 32,\r
- c_din_width_wdch => 64,\r
- c_din_width_wrch => 2,\r
- c_dout_rst_val => "0",\r
- c_dout_width => 36,\r
- c_enable_rlocs => 0,\r
- c_enable_rst_sync => 1,\r
- c_error_injection_type => 0,\r
- c_error_injection_type_axis => 0,\r
- c_error_injection_type_rach => 0,\r
- c_error_injection_type_rdch => 0,\r
- c_error_injection_type_wach => 0,\r
- c_error_injection_type_wdch => 0,\r
- c_error_injection_type_wrch => 0,\r
- c_family => "virtex6",\r
- c_full_flags_rst_val => 1,\r
- c_has_almost_empty => 0,\r
- c_has_almost_full => 0,\r
- c_has_axi_aruser => 0,\r
- c_has_axi_awuser => 0,\r
- c_has_axi_buser => 0,\r
- c_has_axi_rd_channel => 0,\r
- c_has_axi_ruser => 0,\r
- c_has_axi_wr_channel => 0,\r
- c_has_axi_wuser => 0,\r
- c_has_axis_tdata => 0,\r
- c_has_axis_tdest => 0,\r
- c_has_axis_tid => 0,\r
- c_has_axis_tkeep => 0,\r
- c_has_axis_tlast => 0,\r
- c_has_axis_tready => 1,\r
- c_has_axis_tstrb => 0,\r
- c_has_axis_tuser => 0,\r
- c_has_backup => 0,\r
- c_has_data_count => 0,\r
- c_has_data_counts_axis => 0,\r
- c_has_data_counts_rach => 0,\r
- c_has_data_counts_rdch => 0,\r
- c_has_data_counts_wach => 0,\r
- c_has_data_counts_wdch => 0,\r
- c_has_data_counts_wrch => 0,\r
- c_has_int_clk => 0,\r
- c_has_master_ce => 0,\r
- c_has_meminit_file => 0,\r
- c_has_overflow => 0,\r
- c_has_prog_flags_axis => 0,\r
- c_has_prog_flags_rach => 0,\r
- c_has_prog_flags_rdch => 0,\r
- c_has_prog_flags_wach => 0,\r
- c_has_prog_flags_wdch => 0,\r
- c_has_prog_flags_wrch => 0,\r
- c_has_rd_data_count => 0,\r
- c_has_rd_rst => 0,\r
- c_has_rst => 1,\r
- c_has_slave_ce => 0,\r
- c_has_srst => 0,\r
- c_has_underflow => 0,\r
- c_has_valid => 0,\r
- c_has_wr_ack => 0,\r
- c_has_wr_data_count => 0,\r
- c_has_wr_rst => 0,\r
- c_implementation_type => 0,\r
- c_implementation_type_axis => 1,\r
- c_implementation_type_rach => 1,\r
- c_implementation_type_rdch => 1,\r
- c_implementation_type_wach => 1,\r
- c_implementation_type_wdch => 1,\r
- c_implementation_type_wrch => 1,\r
- c_init_wr_pntr_val => 0,\r
- c_interface_type => 0,\r
- c_memory_type => 1,\r
- c_mif_file_name => "BlankString",\r
- c_msgon_val => 1,\r
- c_optimization_mode => 0,\r
- c_overflow_low => 0,\r
- c_preload_latency => 1,\r
- c_preload_regs => 0,\r
- c_prim_fifo_type => "512x36",\r
- c_prog_empty_thresh_assert_val => 128,\r
- c_prog_empty_thresh_assert_val_axis => 1022,\r
- c_prog_empty_thresh_assert_val_rach => 1022,\r
- c_prog_empty_thresh_assert_val_rdch => 1022,\r
- c_prog_empty_thresh_assert_val_wach => 1022,\r
- c_prog_empty_thresh_assert_val_wdch => 1022,\r
- c_prog_empty_thresh_assert_val_wrch => 1022,\r
- c_prog_empty_thresh_negate_val => 129,\r
- c_prog_empty_type => 1,\r
- c_prog_empty_type_axis => 0,\r
- c_prog_empty_type_rach => 0,\r
- c_prog_empty_type_rdch => 0,\r
- c_prog_empty_type_wach => 0,\r
- c_prog_empty_type_wdch => 0,\r
- c_prog_empty_type_wrch => 0,\r
- c_prog_full_thresh_assert_val => 504,\r
- c_prog_full_thresh_assert_val_axis => 1023,\r
- c_prog_full_thresh_assert_val_rach => 1023,\r
- c_prog_full_thresh_assert_val_rdch => 1023,\r
- c_prog_full_thresh_assert_val_wach => 1023,\r
- c_prog_full_thresh_assert_val_wdch => 1023,\r
- c_prog_full_thresh_assert_val_wrch => 1023,\r
- c_prog_full_thresh_negate_val => 503,\r
- c_prog_full_type => 1,\r
- c_prog_full_type_axis => 0,\r
- c_prog_full_type_rach => 0,\r
- c_prog_full_type_rdch => 0,\r
- c_prog_full_type_wach => 0,\r
- c_prog_full_type_wdch => 0,\r
- c_prog_full_type_wrch => 0,\r
- c_rach_type => 0,\r
- c_rd_data_count_width => 9,\r
- c_rd_depth => 512,\r
- c_rd_freq => 1,\r
- c_rd_pntr_width => 9,\r
- c_rdch_type => 0,\r
- c_reg_slice_mode_axis => 0,\r
- c_reg_slice_mode_rach => 0,\r
- c_reg_slice_mode_rdch => 0,\r
- c_reg_slice_mode_wach => 0,\r
- c_reg_slice_mode_wdch => 0,\r
- c_reg_slice_mode_wrch => 0,\r
- c_synchronizer_stage => 2,\r
- c_underflow_low => 0,\r
- c_use_common_overflow => 0,\r
- c_use_common_underflow => 0,\r
- c_use_default_settings => 0,\r
- c_use_dout_rst => 1,\r
- c_use_ecc => 0,\r
- c_use_ecc_axis => 0,\r
- c_use_ecc_rach => 0,\r
- c_use_ecc_rdch => 0,\r
- c_use_ecc_wach => 0,\r
- c_use_ecc_wdch => 0,\r
- c_use_ecc_wrch => 0,\r
- c_use_embedded_reg => 0,\r
- c_use_fifo16_flags => 0,\r
- c_use_fwft_data_count => 0,\r
- c_valid_low => 0,\r
- c_wach_type => 0,\r
- c_wdch_type => 0,\r
- c_wr_ack_low => 0,\r
- c_wr_data_count_width => 9,\r
- c_wr_depth => 512,\r
- c_wr_depth_axis => 1024,\r
- c_wr_depth_rach => 16,\r
- c_wr_depth_rdch => 1024,\r
- c_wr_depth_wach => 16,\r
- c_wr_depth_wdch => 1024,\r
- c_wr_depth_wrch => 16,\r
- c_wr_freq => 1,\r
- c_wr_pntr_width => 9,\r
- c_wr_pntr_width_axis => 10,\r
- c_wr_pntr_width_rach => 4,\r
- c_wr_pntr_width_rdch => 10,\r
- c_wr_pntr_width_wach => 4,\r
- c_wr_pntr_width_wdch => 10,\r
- c_wr_pntr_width_wrch => 4,\r
- c_wr_response_latency => 1,\r
- c_wrch_type => 0\r
- );\r
--- synthesis translate_on\r
-BEGIN\r
--- synthesis translate_off\r
-U0 : wrapped_sync_fifo_progfull504_progempty128_512x36\r
- PORT MAP (\r
- clk => clk,\r
- rst => rst,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty,\r
- prog_full => prog_full,\r
- prog_empty => prog_empty\r
- );\r
--- synthesis translate_on\r
-\r
-END sync_fifo_progfull504_progempty128_512x36_a;\r
+++ /dev/null
---------------------------------------------------------------------------------\r
--- This file is owned and controlled by Xilinx and must be used solely --\r
--- for design, simulation, implementation and creation of design files --\r
--- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
--- devices or technologies is expressly prohibited and immediately --\r
--- terminates your license. --\r
--- --\r
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
--- PARTICULAR PURPOSE. --\r
--- --\r
--- Xilinx products are not intended for use in life support appliances, --\r
--- devices, or systems. Use in such applications are expressly --\r
--- prohibited. --\r
--- --\r
--- (c) Copyright 1995-2014 Xilinx, Inc. --\r
--- All rights reserved. --\r
---------------------------------------------------------------------------------\r
-\r
---------------------------------------------------------------------------------\r
--- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
--- --\r
--- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
--- memory queue generator. Use it to generate resource and performance --\r
--- optimized FIFOs with common or independent read/write clock domains, --\r
--- and optional fixed or programmable full and empty flags and --\r
--- handshaking signals. Choose from a selection of memory resource --\r
--- types for implementation. Optional Hamming code based error --\r
--- detection and correction as well as error injection capability for --\r
--- system test help to insure data integrity. FIFO width and depth are --\r
--- parameterizable, and for native interface FIFOs, asymmetric read and --\r
--- write port widths are also supported. --\r
---------------------------------------------------------------------------------\r
-\r
--- Interfaces:\r
--- AXI4Stream_MASTER_M_AXIS\r
--- AXI4Stream_SLAVE_S_AXIS\r
--- AXI4_MASTER_M_AXI\r
--- AXI4_SLAVE_S_AXI\r
--- AXI4Lite_MASTER_M_AXI\r
--- AXI4Lite_SLAVE_S_AXI\r
--- master_aclk\r
--- slave_aclk\r
--- slave_aresetn\r
-\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-COMPONENT sync_fifo_progfull504_progempty128_512x36\r
- PORT (\r
- clk : IN STD_LOGIC;\r
- rst : IN STD_LOGIC;\r
- din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- wr_en : IN STD_LOGIC;\r
- rd_en : IN STD_LOGIC;\r
- dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- full : OUT STD_LOGIC;\r
- empty : OUT STD_LOGIC;\r
- prog_full : OUT STD_LOGIC;\r
- prog_empty : OUT STD_LOGIC\r
- );\r
-END COMPONENT;\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
-\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-your_instance_name : sync_fifo_progfull504_progempty128_512x36\r
- PORT MAP (\r
- clk => clk,\r
- rst => rst,\r
- din => din,\r
- wr_en => wr_en,\r
- rd_en => rd_en,\r
- dout => dout,\r
- full => full,\r
- empty => empty,\r
- prog_full => prog_full,\r
- prog_empty => prog_empty\r
- );\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
-\r
--- You must compile the wrapper file sync_fifo_progfull504_progempty128_512x36.vhd when simulating\r
--- the core, sync_fifo_progfull504_progempty128_512x36. When compiling the wrapper file, be sure to\r
--- reference the XilinxCoreLib VHDL simulation library. For detailed\r
--- instructions, please refer to the "CORE Generator Help".\r
-\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 14.7\r
-# Date: Mon Oct 20 06:51:31 2014\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Behavioral\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
-# END Select\r
-# BEGIN Parameters\r
-CSET add_ngc_constraint_axi=false\r
-CSET almost_empty_flag=false\r
-CSET almost_full_flag=false\r
-CSET aruser_width=1\r
-CSET awuser_width=1\r
-CSET axi_address_width=32\r
-CSET axi_data_width=64\r
-CSET axi_type=AXI4_Stream\r
-CSET axis_type=FIFO\r
-CSET buser_width=1\r
-CSET clock_enable_type=Slave_Interface_Clock_Enable\r
-CSET clock_type_axi=Common_Clock\r
-CSET component_name=sync_fifo_progfull504_progempty128_512x36\r
-CSET data_count=false\r
-CSET data_count_width=9\r
-CSET disable_timing_violations=false\r
-CSET disable_timing_violations_axi=false\r
-CSET dout_reset_value=0\r
-CSET empty_threshold_assert_value=128\r
-CSET empty_threshold_assert_value_axis=1022\r
-CSET empty_threshold_assert_value_rach=1022\r
-CSET empty_threshold_assert_value_rdch=1022\r
-CSET empty_threshold_assert_value_wach=1022\r
-CSET empty_threshold_assert_value_wdch=1022\r
-CSET empty_threshold_assert_value_wrch=1022\r
-CSET empty_threshold_negate_value=129\r
-CSET enable_aruser=false\r
-CSET enable_awuser=false\r
-CSET enable_buser=false\r
-CSET enable_common_overflow=false\r
-CSET enable_common_underflow=false\r
-CSET enable_data_counts_axis=false\r
-CSET enable_data_counts_rach=false\r
-CSET enable_data_counts_rdch=false\r
-CSET enable_data_counts_wach=false\r
-CSET enable_data_counts_wdch=false\r
-CSET enable_data_counts_wrch=false\r
-CSET enable_ecc=false\r
-CSET enable_ecc_axis=false\r
-CSET enable_ecc_rach=false\r
-CSET enable_ecc_rdch=false\r
-CSET enable_ecc_wach=false\r
-CSET enable_ecc_wdch=false\r
-CSET enable_ecc_wrch=false\r
-CSET enable_read_channel=false\r
-CSET enable_read_pointer_increment_by2=false\r
-CSET enable_reset_synchronization=true\r
-CSET enable_ruser=false\r
-CSET enable_tdata=false\r
-CSET enable_tdest=false\r
-CSET enable_tid=false\r
-CSET enable_tkeep=false\r
-CSET enable_tlast=false\r
-CSET enable_tready=true\r
-CSET enable_tstrobe=false\r
-CSET enable_tuser=false\r
-CSET enable_write_channel=false\r
-CSET enable_wuser=false\r
-CSET fifo_application_type_axis=Data_FIFO\r
-CSET fifo_application_type_rach=Data_FIFO\r
-CSET fifo_application_type_rdch=Data_FIFO\r
-CSET fifo_application_type_wach=Data_FIFO\r
-CSET fifo_application_type_wdch=Data_FIFO\r
-CSET fifo_application_type_wrch=Data_FIFO\r
-CSET fifo_implementation=Common_Clock_Block_RAM\r
-CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
-CSET full_flags_reset_value=1\r
-CSET full_threshold_assert_value=504\r
-CSET full_threshold_assert_value_axis=1023\r
-CSET full_threshold_assert_value_rach=1023\r
-CSET full_threshold_assert_value_rdch=1023\r
-CSET full_threshold_assert_value_wach=1023\r
-CSET full_threshold_assert_value_wdch=1023\r
-CSET full_threshold_assert_value_wrch=1023\r
-CSET full_threshold_negate_value=503\r
-CSET id_width=4\r
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-CSET inject_dbit_error_axis=false\r
-CSET inject_dbit_error_rach=false\r
-CSET inject_dbit_error_rdch=false\r
-CSET inject_dbit_error_wach=false\r
-CSET inject_dbit_error_wdch=false\r
-CSET inject_dbit_error_wrch=false\r
-CSET inject_sbit_error=false\r
-CSET inject_sbit_error_axis=false\r
-CSET inject_sbit_error_rach=false\r
-CSET inject_sbit_error_rdch=false\r
-CSET inject_sbit_error_wach=false\r
-CSET inject_sbit_error_wdch=false\r
-CSET inject_sbit_error_wrch=false\r
-CSET input_data_width=36\r
-CSET input_depth=512\r
-CSET input_depth_axis=1024\r
-CSET input_depth_rach=16\r
-CSET input_depth_rdch=1024\r
-CSET input_depth_wach=16\r
-CSET input_depth_wdch=1024\r
-CSET input_depth_wrch=16\r
-CSET interface_type=Native\r
-CSET output_data_width=36\r
-CSET output_depth=512\r
-CSET overflow_flag=false\r
-CSET overflow_flag_axi=false\r
-CSET overflow_sense=Active_High\r
-CSET overflow_sense_axi=Active_High\r
-CSET performance_options=Standard_FIFO\r
-CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant\r
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
-CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant\r
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
-CSET rach_type=FIFO\r
-CSET rdch_type=FIFO\r
-CSET read_clock_frequency=1\r
-CSET read_data_count=false\r
-CSET read_data_count_width=9\r
-CSET register_slice_mode_axis=Fully_Registered\r
-CSET register_slice_mode_rach=Fully_Registered\r
-CSET register_slice_mode_rdch=Fully_Registered\r
-CSET register_slice_mode_wach=Fully_Registered\r
-CSET register_slice_mode_wdch=Fully_Registered\r
-CSET register_slice_mode_wrch=Fully_Registered\r
-CSET reset_pin=true\r
-CSET reset_type=Asynchronous_Reset\r
-CSET ruser_width=1\r
-CSET synchronization_stages=2\r
-CSET synchronization_stages_axi=2\r
-CSET tdata_width=64\r
-CSET tdest_width=4\r
-CSET tid_width=8\r
-CSET tkeep_width=4\r
-CSET tstrb_width=4\r
-CSET tuser_width=4\r
-CSET underflow_flag=false\r
-CSET underflow_flag_axi=false\r
-CSET underflow_sense=Active_High\r
-CSET underflow_sense_axi=Active_High\r
-CSET use_clock_enable=false\r
-CSET use_dout_reset=true\r
-CSET use_embedded_registers=false\r
-CSET use_extra_logic=false\r
-CSET valid_flag=false\r
-CSET valid_sense=Active_High\r
-CSET wach_type=FIFO\r
-CSET wdch_type=FIFO\r
-CSET wrch_type=FIFO\r
-CSET write_acknowledge_flag=false\r
-CSET write_acknowledge_sense=Active_High\r
-CSET write_clock_frequency=1\r
-CSET write_data_count=false\r
-CSET write_data_count_width=9\r
-CSET wuser_width=1\r
-# END Parameters\r
-# BEGIN Extra information\r
-MISC pkg_timestamp=2012-11-19T12:39:56Z\r
-# END Extra information\r
-GENERATE\r
-# CRC: d742ac77\r
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\ No newline at end of file
+++ /dev/null
--------------------------------------------------------------------------------\r
--- Copyright (c) 2012 Xilinx, Inc.\r
--- All Rights Reserved\r
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor : Xilinx\r
--- \ \ \/ Version : 13.3\r
--- \ \ Application: XILINX CORE Generator\r
--- / / Filename : vio36.vhd\r
--- /___/ /\ Timestamp : Mon Jul 23 15:40:25 W. Europe Daylight Time 2012\r
--- \ \ / \\r
--- \___\/\___\\r
---\r
--- Design Name: VHDL Synthesis Wrapper\r
--------------------------------------------------------------------------------\r
--- This wrapper is used to integrate with Project Navigator and PlanAhead\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.ALL;\r
-ENTITY vio36 IS\r
- port (\r
- CONTROL: inout std_logic_vector(35 downto 0);\r
- ASYNC_OUT: out std_logic_vector(35 downto 0));\r
-END vio36;\r
-\r
-ARCHITECTURE vio36_a OF vio36 IS\r
-BEGIN\r
-\r
-END vio36_a;\r
+++ /dev/null
--------------------------------------------------------------------------------\r
--- Copyright (c) 2012 Xilinx, Inc.\r
--- All Rights Reserved\r
--------------------------------------------------------------------------------\r
--- ____ ____\r
--- / /\/ /\r
--- /___/ \ / Vendor : Xilinx\r
--- \ \ \/ Version : 13.3\r
--- \ \ Application: Xilinx CORE Generator\r
--- / / Filename : vio36.vho\r
--- /___/ /\ Timestamp : Mon Jul 23 15:40:25 W. Europe Daylight Time 2012\r
--- \ \ / \\r
--- \___\/\___\\r
---\r
--- Design Name: ISE Instantiation template\r
--- Component Identifier: xilinx.com:ip:chipscope_vio:1.05.a\r
--------------------------------------------------------------------------------\r
--- The following code must appear in the VHDL architecture header:\r
-\r
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
-component vio36\r
- PORT (\r
- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
- ASYNC_OUT : OUT STD_LOGIC_VECTOR(35 DOWNTO 0));\r
-\r
-end component;\r
-\r
--- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
--- The following code must appear in the VHDL architecture\r
--- body. Substitute your own instance name and net names.\r
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
-\r
-your_instance_name : vio36\r
- port map (\r
- CONTROL => CONTROL,\r
- ASYNC_OUT => ASYNC_OUT);\r
-\r
--- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+++ /dev/null
-##############################################################\r
-#\r
-# Xilinx Core Generator version 13.3\r
-# Date: Mon Jul 23 13:39:49 2012\r
-#\r
-##############################################################\r
-#\r
-# This file contains the customisation parameters for a\r
-# Xilinx CORE Generator IP GUI. It is strongly recommended\r
-# that you do not manually alter this file as it may cause\r
-# unexpected and unsupported behavior.\r
-#\r
-##############################################################\r
-#\r
-# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a\r
-#\r
-##############################################################\r
-#\r
-# BEGIN Project Options\r
-SET addpads = false\r
-SET asysymbol = true\r
-SET busformat = BusFormatAngleBracketNotRipped\r
-SET createndf = false\r
-SET designentry = VHDL\r
-SET device = xc6vlx130t\r
-SET devicefamily = virtex6\r
-SET flowvendor = Other\r
-SET formalverification = false\r
-SET foundationsym = false\r
-SET implementationfiletype = Ngc\r
-SET package = ff484\r
-SET removerpms = false\r
-SET simulationfiles = Structural\r
-SET speedgrade = -3\r
-SET verilogsim = false\r
-SET vhdlsim = true\r
-# END Project Options\r
-# BEGIN Select\r
-SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a\r
-# END Select\r
-# BEGIN Parameters\r
-CSET asynchronous_input_port_width=8\r
-CSET asynchronous_output_port_width=36\r
-CSET component_name=vio36\r
-CSET constraint_type=embedded\r
-CSET enable_asynchronous_input_port=false\r
-CSET enable_asynchronous_output_port=true\r
-CSET enable_synchronous_input_port=false\r
-CSET enable_synchronous_output_port=false\r
-CSET example_design=false\r
-CSET invert_clock_input=false\r
-CSET synchronous_input_port_width=8\r
-CSET synchronous_output_port_width=8\r
-# END Parameters\r
-GENERATE\r
-# CRC: f58807c1\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="vio36.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="vio36.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|vio36|vio36_a" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="vio36.vhd" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/vio36" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="vio36" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-23T15:40:35" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6A1216FFFD084649B921E416A2F662FE" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
+++ /dev/null
-The following files were generated for 'vio36' in directory\r
-D:\Xilinx_proj\Panda\Xilinx\FrontEndElectronics\FEE_test_ADC32\ipcore_dir\\r
-\r
-XCO file generator:\r
- Generate an XCO file for compatibility with legacy flows.\r
-\r
- * vio36.xco\r
-\r
-Creates an implementation netlist:\r
- Creates an implementation netlist for the IP.\r
-\r
- * vio36.cdc\r
- * vio36.ngc\r
- * vio36.vhd\r
- * vio36.vho\r
-\r
-Creates an HDL instantiation template:\r
- Creates an HDL instantiation template for the IP.\r
-\r
- * vio36.vho\r
-\r
-IP Symbol Generator:\r
- Generate an IP symbol based on the current project options'.\r
-\r
- * vio36.asy\r
-\r
-SYM file generator:\r
- Generate a SYM file for compatibility with legacy flows\r
-\r
- * vio36.sym\r
-\r
-Generate ISE metadata:\r
- Create a metadata file for use when including this core in ISE designs\r
-\r
- * vio36_xmdf.tcl\r
-\r
-Generate ISE subproject:\r
- Create an ISE subproject for use when including this core in ISE designs\r
-\r
- * _xmsgs/pn_parser.xmsgs\r
- * vio36.gise\r
- * vio36.xise\r
-\r
-Deliver Readme:\r
- Readme file for the IP.\r
-\r
- * vio36_readme.txt\r
-\r
-Generate FLIST file:\r
- Text file listing all of the output files produced when a customized core was\r
- generated in the CORE Generator.\r
-\r
- * vio36_flist.txt\r
-\r
-Please see the Xilinx CORE Generator online help for further details on\r
-generated files and how to use them.\r
-\r
+++ /dev/null
-<?xml version='1.0' encoding='utf-8'?>\r
-<!--This is an ISE project configuration file.-->\r
-<!--It holds project specific layout data for the projectmgr plugin.-->\r
-<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->\r
-<Project version="2" owner="projectmgr" name="FEE_ADC32board" >\r
- <!--This is an ISE project configuration file.-->\r
- <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >\r
- <ClosedNodes>\r
- <ClosedNodesVersion>2</ClosedNodesVersion>\r
- <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel1458_2 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
- <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel1458_3 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
- <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel1458_4 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
- <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_1 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
- <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_2 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
- <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_3 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
- <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_4 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
- </ClosedNodes>\r
- <SelectedItems>\r
- <SelectedItem>FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral (D:/Project/Panda/GIT/FEE_ADC32board/modules/FEE_ADCinput_module.vhd)</SelectedItem>\r
- </SelectedItems>\r
- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
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- <CurrentItem>FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral (D:/Project/Panda/GIT/FEE_ADC32board/modules/FEE_ADCinput_module.vhd)</CurrentItem>\r
- </ItemView>\r
- <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >\r
- <ClosedNodes>\r
- <ClosedNodesVersion>1</ClosedNodesVersion>\r
- <ClosedNode>Configure Target Device</ClosedNode>\r
- <ClosedNode>Design Utilities</ClosedNode>\r
- <ClosedNode>Implement Design</ClosedNode>\r
- <ClosedNode>Synthesize - XST</ClosedNode>\r
- <ClosedNode>User Constraints</ClosedNode>\r
- </ClosedNodes>\r
- <SelectedItems>\r
- <SelectedItem></SelectedItem>\r
- </SelectedItems>\r
- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
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- <CurrentItem></CurrentItem>\r
- </ItemView>\r
- <ItemView guiview="File" >\r
- <ClosedNodes>\r
- <ClosedNodesVersion>1</ClosedNodesVersion>\r
- </ClosedNodes>\r
- <SelectedItems/>\r
- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
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- <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>\r
- <CurrentItem>D:\Project\Panda\GIT\FEE_ADC32board\FEE_modules\blockmem.vhd</CurrentItem>\r
- </ItemView>\r
- <ItemView guiview="Library" >\r
- <ClosedNodes>\r
- <ClosedNodesVersion>1</ClosedNodesVersion>\r
- <ClosedNode>work</ClosedNode>\r
- </ClosedNodes>\r
- <SelectedItems/>\r
- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
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- <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>\r
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- <CurrentItem>work</CurrentItem>\r
- </ItemView>\r
- <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >\r
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- <ClosedNodesVersion>1</ClosedNodesVersion>\r
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- <SelectedItems>\r
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- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
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- <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002ba000000010000000100000000000000000000000064ffffffff000000810000000000000001000002ba0000000100000000</ViewHeaderState>\r
- <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>\r
- <CurrentItem/>\r
- </ItemView>\r
- <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_DECL" guiview="Process" >\r
- <ClosedNodes>\r
- <ClosedNodesVersion>1</ClosedNodesVersion>\r
- </ClosedNodes>\r
- <SelectedItems>\r
- <SelectedItem/>\r
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- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
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- <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>\r
- <CurrentView>Implementation</CurrentView>\r
-</Project>\r
+++ /dev/null
-<?xml version='1.0' encoding='UTF-8'?>
-<report-views version="2.0" >
- <header>
- <DateModified>2014-12-11T14:19:21</DateModified>
- <ModuleName>top</ModuleName>
- <SummaryTimeStamp>Unknown</SummaryTimeStamp>
- <SavedFilePath>D:/Project/Panda/GIT/FEE_ADC32board/project/iseconfig/FEE_adc32_module.xreport</SavedFilePath>
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- <DateInitialized>2014-12-11T14:19:21</DateInitialized>
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- <body>
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- <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
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- <toc-item title="Design Summary" target="Design Summary" />
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- <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
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- <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
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- </body>
-</report-views>
+++ /dev/null
-<?xml version='1.0' encoding='UTF-8'?>
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- <header>
- <DateModified>2014-12-11T14:50:59</DateModified>
- <ModuleName>top</ModuleName>
- <SummaryTimeStamp>Unknown</SummaryTimeStamp>
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- <EnableMessageFiltering>true</EnableMessageFiltering>
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- </view>
- <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lck" label="Back-annotate Pin Report" >
- <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
- <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
- </view>
- <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lpc" label="Locked Pin Constraints" >
- <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
- <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
- </view>
- <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/top_timesim.nlf" label="Post-Fit Simulation Model Report" />
- <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
- <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
- </viewgroup>
- </body>
-</report-views>
+++ /dev/null
-SODA_SOURCE (0xF355)
-++++++++++++++++++++
-WRITE_REG:
-
-BE00 soda_cmd_word_S
-BE01 --
-BE02 --
-BE03 CTRL_STATUS_register_i
-
-READ_REG:
-
-BE00 soda_cmd_word_S
-BE01 super_burst_nr_S
-BE02 calib_register_S
-BE03 CTRL_STATUS_register_i
-
-CONTROL(r/w):
-CTRL_STATUS_register_i[31] : soda_reset_S
-CTRL_STATUS_register_i[30] : soda_enable_S
-CTRL_STATUS_register_i[29] : dead_channel_S
-CTRL_STATUS_register_i[28:16] : --
-STATUS(read-only):
-CTRL_STATUS_register_i[15] : report_error_S
-CTRL_STATUS_register_i[14:2] : --
-CTRL_STATUS_register_i[1] : downstream_error_S
-CTRL_STATUS_register_i[0] : channel_timeout_status_S
-
-
-SODA_CLIENT (0xF356)
-++++++++++++++++++++
-WRITE_REG:
-
-BE00 LEDregister_i
-
-READ_REG:
-
-BE00 soda_cmd_word_S
-BE01 super_burst_nr_S
-BE02 LEDregister_i
-BE03 Debug_status
-BE04 Debug_RX_count
-BE05 Debug_TX_count
-BE06 Debug_SOS_count
-BE07 Debug_CMD_count
-
-
-Cu_TRB_SODA_HUB (0xF35B)
-++++++++++++++++++++++++++
-WRITE_REG:
-
-BE00 soda_cmd_word_S
-BE01 CTRL_STATUS_register_S(15 downto 0) channel1
-BE02 CTRL_STATUS_register_S(15 downto 0) channel2
-BE03 CTRL_STATUS_register_S(15 downto 0) channel3
-BE04 CTRL_STATUS_register_S(15 downto 0) channel4
-
-READ_REG:
-
-BE00 '0' & soda_cmd_word_S
-BE01 '0' & superburst_nr_S
-BE04 calib_register_S channel1
-BE05 calib_register_S channel2
-BE06 calib_register_S channel3
-BE07 calib_register_S channel4
-BE08 calib_register_S channel1
-BE09 calib_register_S channel2
-BE10 calib_register_S channel3
-BE11 calib_register_S channel4
-
-CONTROL(r/w):
-CTRL_STATUS_register_i[31] : soda_reset_S
-CTRL_STATUS_register_i[30] : soda_enable_S
-CTRL_STATUS_register_i[29] : dead_channel_S
-CTRL_STATUS_register_i[28:16] : --
-STATUS(read-only):
-CTRL_STATUS_register_i[15] : report_error_S
-CTRL_STATUS_register_i[14:2] : --
-CTRL_STATUS_register_i[1] : downstream_error_S
-CTRL_STATUS_register_i[0] : channel_timeout_status_S
-
-DEBUG_STATUS(31) <= send_link_reset_i when rising_edge(SYSCLK);
-DEBUG_STATUS(30) <= '0';
-DEBUG_STATUS(29) <= internal_make_link_reset_out when rising_edge(SYSCLK);
-DEBUG_STATUS(28) <= '0';
-DEBUG_STATUS(27) <= '0';
-DEBUG_STATUS(26) <= rx_allow;
-DEBUG_STATUS(25) <= tx_allow;
-DEBUG_STATUS(24:20) <= (others => '0');
-DEBUG_STATUS(19:16) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-DEBUG_STATUS(15:3) <= (others => '0');
-DEBUG_STATUS(2) <= CLK_EN;
-DEBUG_STATUS(1) <= CLEAR;
-DEBUG_STATUS(0) <= RESET;
-
--------------------------------------------------------------------
-constant K_IDLE : std_logic_vector(7 downto 0) := x"BC";
-constant D_IDLE0 : std_logic_vector(7 downto 0) := x"C5";
-constant D_IDLE1 : std_logic_vector(7 downto 0) := x"50";
-constant K_SOP : std_logic_vector(7 downto 0) := x"FB";
-constant K_EOP : std_logic_vector(7 downto 0) := x"FD";
-constant K_BGN : std_logic_vector(7 downto 0) := x"1C";
-constant K_REQ : std_logic_vector(7 downto 0) := x"7C";
-constant K_RST : std_logic_vector(7 downto 0) := x"FE";
-constant K_DLM : std_logic_vector(7 downto 0) := x"DC";
-
-
+++ /dev/null
-SODA_QUAD_SOURCE (0xF358)
-+++++++++++++++++++++++++
-WRITE_REG:
-
-BE00 soda_cmd_word_S
-BE01 CTRL_STATUS_register_i[0](15..0)
-BE02 CTRL_STATUS_register_i[1](15..0)
-BE03 CTRL_STATUS_register_i[2](15..0)
-BE04 CTRL_STATUS_register_i[3](15..0)
-
-READ_REG:
-
-BE00 soda_cmd_word_S
-BE01 super_burst_nr_S
-BE04 calib_register_S[0]
-BE05 calib_register_S[1]
-BE06 calib_register_S[2]
-BE07 calib_register_S[3]
-BE08 CTRL_STATUS_register_i[0]
-BE09 CTRL_STATUS_register_i[0]
-BE10 CTRL_STATUS_register_i[0]
-BE11 CTRL_STATUS_register_i[0]
-
-control(read & write):
-CTRL_STATUS_register_i[3..0] : LEDs
-CTRL_STATUS_register_i[8] : dead_channel
-CTRL_STATUS_register_i[15] : reset errors
-status(read-only):
-CTRL_STATUS_register_i[17] : timeout-error
-CTRL_STATUS_register_i[18] : downstream-error
-CTRL_STATUS_register_i[31] : report error
-
-
-SODA_CLIENT (0xF356)
-++++++++++++++++++++
-WRITE_REG:
-
-BE00 LEDregister_i
-
-READ_REG:
-
-BE00 soda_cmd_word_S
-BE01 super_burst_nr_S
-BE02 LEDregister_i
-BE03 Debug_status
-BE04 Debug_RX_count
-BE05 Debug_TX_count
-BE06 Debug_SOS_count
-BE07 Debug_CMD_count
-
-
-
-
-DEBUG_STATUS(31) <= send_link_reset_i when rising_edge(SYSCLK);
-DEBUG_STATUS(30) <= '0';
-DEBUG_STATUS(29) <= internal_make_link_reset_out when rising_edge(SYSCLK);
-DEBUG_STATUS(28) <= '0';
-DEBUG_STATUS(27) <= '0';
-DEBUG_STATUS(26) <= rx_allow;
-DEBUG_STATUS(25) <= tx_allow;
-DEBUG_STATUS(24:20) <= (others => '0');
-DEBUG_STATUS(19:16) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-DEBUG_STATUS(15:3) <= (others => '0');
-DEBUG_STATUS(2) <= CLK_EN;
-DEBUG_STATUS(1) <= CLEAR;
-DEBUG_STATUS(0) <= RESET;
-
-
-
-
+++ /dev/null
----------------
--- TOP LEVEL --
----------------
--- TAB=3 !!\r
-\r
-library ieee;
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;\r
-\r
-entity Cu_trb3_periph_soda_client is\r
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_INTERFACES : integer := 1
- );
- port(\r
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
- --serdes I/O - connect as you like, no real use
- CU_SERDES_TX : out std_logic_vector(3 downto 0);
- CU_SERDES_RX : in std_logic_vector(3 downto 0);
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );\r
-end Cu_trb3_periph_soda_client;\r
-\r
-architecture Cu_trb3_periph_soda_client_arch of Cu_trb3_periph_soda_client is\r
- -- Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
- --Clock / Reset
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
-
- signal clk_100_osc : std_logic;
- signal clk_200_osc : std_logic;
- signal time_counter : unsigned(31 downto 0);
-\r
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-\r
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-\r
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-\r
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-\r
- --Cu media interface
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
-
-
- --SODA
- signal soda_rx_full_clk : std_logic;
- signal soda_rx_half_clk : std_logic;
- signal soda_tx_full_clk : std_logic;
- signal soda_tx_half_clk : std_logic;
-
- signal soda_tx_dlm_S : std_logic;
- signal soda_tx_dlm_word_S : std_logic_vector(7 downto 0);
- signal soda_rx_dlm_S : std_logic;
- signal soda_rx_dlm_word_S : std_logic_vector(7 downto 0);
--- signal make_reset : std_logic;
- signal soda_tx_dlm_preview_S : std_logic; --PL!
- signal link_phase_S : std_logic; --PL!
--- signal rx_cdr_lol_S : std_logic;
--- signal link_locked_S : std_logic; --PL!
-
- -- SODA slow controll
- signal soda_ack : std_logic;
- signal soda_write : std_logic;
- signal soda_read : std_logic;
- signal soda_data_in : std_logic_vector(31 downto 0);
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0);
- signal soda_leds : std_logic_vector(3 downto 0);
-
- signal link_debug_in_S : std_logic_vector(31 downto 0);
- signal general_reset_i : std_logic := '1';
-\r
-begin\r
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-
- LED_RX <= (others => '0'); -- otherwise it is floating
- LED_TX <= (others => '0'); -- otherwise it is floating
- LED_LINKOK <= (others => '0'); -- otherwise it is floating
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, --clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_osc, --rx_half_clk, PL 111114, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
--------------------------------------------------------------------------
--- Clock Handling
--------------------------------------------------------------------------
-THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc,
- LOCK => pll_lock
- );
-\r
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
- TRB_MEDIA_AND_SODA_SYNC_UPLINK : Cu_trb_net16_soda_syncUP_ecp3_sfp
- port map(
- OSCCLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
-
- --Copper SFP Connection
- CU_RXD_P_IN => CU_SERDES_RX(0),
- CU_RXD_N_IN => CU_SERDES_RX(1),
- CU_TXD_P_OUT => CU_SERDES_TX(0),
- CU_TXD_N_OUT => CU_SERDES_TX(1),
- CU_PRSNT_N_IN => FPGA5_COMM(0),
- CU_LOS_IN => FPGA5_COMM(0),
- CU_TXDIS_OUT => FPGA5_COMM(2),
-
- -- sync clocks
- SYNC_RX_HALF_CLK_OUT => soda_rx_half_clk,
- SYNC_RX_FULL_CLK_OUT => soda_rx_full_clk,
- SYNC_TX_HALF_CLK_OUT => soda_tx_half_clk,
- SYNC_TX_FULL_CLK_OUT => soda_tx_full_clk,
-\r
- SYNC_RXD_P_IN => SERDES_ADDON_RX(4),
- SYNC_RXD_N_IN => SERDES_ADDON_RX(5),
- SYNC_TXD_P_OUT => SERDES_ADDON_TX(4),
- SYNC_TXD_N_OUT => SERDES_ADDON_TX(5),\r
- SYNC_TX_DLM_IN => soda_tx_dlm_S,
- SYNC_TX_DLM_WORD_IN => soda_tx_dlm_word_S,
- SYNC_RX_DLM_OUT => soda_rx_dlm_S,
- SYNC_RX_DLM_WORD_OUT => soda_rx_dlm_word_S,
- SYNC_PRSNT_N_IN => SFP_MOD0(3),
- SYNC_LOS_IN => SFP_LOS(3),
- SYNC_TXDIS_OUT => sfp_txdis_S(3),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => (others => '0')
- );
-
-
--------------------------------------------------------------------------
--- Endpoint
--------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
- --USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"45",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"9100b000",
- REGIO_INIT_ADDRESS => x"f35a",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 9, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 256,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 256
- )
- port map(
- CLK => clk_100_osc, --rx_half_clk, PL 111114
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out(0),
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in(0),
- MED_DATAREADY_IN => med_dataready_in(0),
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out(0),
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => '0',
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => open,
- LVL1_VALID_TIMING_TRG_OUT => open,
- LVL1_VALID_NOTIMING_TRG_OUT => open,
- LVL1_INVALID_TRG_OUT => open,
-
- LVL1_TRG_TYPE_OUT => open,
- LVL1_TRG_NUMBER_OUT => open,
- LVL1_TRG_CODE_OUT => open,
- LVL1_TRG_INFORMATION_OUT => open,
- LVL1_INT_TRG_NUMBER_OUT => open,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => open,
- TRG_TIMEOUT_DETECTED_OUT => open,
- TRG_SPURIOUS_TRG_OUT => open,
- TRG_MISSING_TMG_TRG_OUT => open,
- TRG_SPIKE_DETECTED_OUT => open,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => '1',
- FEE_TRG_STATUSBITS_IN => (others => '0'),
- FEE_DATA_IN => (others => '0'),
- FEE_DATA_WRITE_IN(0) => '0',
- FEE_DATA_FINISHED_IN(0) => '1',
- FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-\r
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 4, others => 0)
- )
- port map(
- CLK => clk_100_osc, --rx_half_clk, PL 111114
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_READ_ENABLE_OUT(2) => soda_read,
-
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_WRITE_ENABLE_OUT(2) => soda_write,
-
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+31 downto 2*32) => soda_data_in,
-
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_ADDR_OUT(2*16+3 downto 2*16) => soda_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+4) => open,
-
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32+8) => open,
- BUS_DATA_IN(2*32+31 downto 2*32) => soda_data_out,
-
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_DATAREADY_IN(2) => soda_ack,
-
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => soda_ack,
-
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
-
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => '0',
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
- port map(
- CLK_IN => clk_100_osc,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-\r
-\r
--- SFP_TXDIS(1) <= sfp_txdis_S(1);
- SFP_TXDIS <= sfp_txdis_S;\r
- \r
- -----------------------------------------------------------------------\r
- -- Since there is nomore trb on this link, link-phase does not need to\r
- -- be controlled. To avoid changing code, link-phase is faked here.\r
- -----------------------------------------------------------------------
- DUMMY_LINK_PHASE_PROC : process (soda_rx_full_clk)\r
- begin\r
- if rising_edge(soda_rx_full_clk) then\r
- if (reset_i='1') then\r
- link_phase_S <='0';\r
- elsif (link_phase_S='0') then
- link_phase_S <='1';
- else
- link_phase_S <='0';
- end if;\r
- end if;\r
- end process;
-
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------
-
- A_SODA_CLIENT : soda_client
- port map(
- SYSCLK => soda_rx_half_clk, --clk_100_osc,
- SODACLK => soda_rx_full_clk,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- RX_DLM_WORD_IN => soda_rx_dlm_word_S,
- RX_DLM_IN => soda_rx_dlm_S,
- TX_DLM_OUT => soda_tx_dlm_S,
- TX_DLM_WORD_OUT => soda_tx_dlm_word_S,
- TX_DLM_PREVIEW_OUT => soda_tx_dlm_preview_S,
- LINK_PHASE_IN => link_phase_S,
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds,
- LINK_DEBUG_IN => link_debug_in_S
- );
-
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-\r
- LED_ORANGE <= time_counter(26);
- LED_YELLOW <= time_counter(26);
- LED_GREEN <= time_counter(26);
- LED_RED <= time_counter(26);
----------------------------------------------------------------------------
--- DEBUG
----------------------------------------------------------------------------
- link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0);
- link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- blink : process (clk_100_osc)
- begin
- if rising_edge(clk_100_osc) then
- if (time_counter = x"FFFFFFFF") then
- time_counter <= x"00000000";
- else
- time_counter <= time_counter + 1;
- end if;
- end if;
- end process;
-
-end Cu_trb3_periph_soda_client_arch;
\ No newline at end of file
+++ /dev/null
----------------
--- TOP LEVEL --
----------------
--- TAB=3 !!\r
-\r
-library ieee;
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;\r
-\r
-entity Cu_trb3_periph_soda_hub is\r
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_INTERFACES : integer := 6 + 1
- );
- port(\r
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- --serdes I/O - connect as you like, no real use
- CU_SERDES_TX : out std_logic_vector(3 downto 0);
- CU_SERDES_RX : in std_logic_vector(3 downto 0);
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );\r
-end Cu_trb3_periph_soda_hub;\r
-\r
-architecture Cu_trb3_periph_soda_hub_arch of Cu_trb3_periph_soda_hub is\r
- -- Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
- --Clock / Reset
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal downlink_clear : std_logic;
- signal downlink_reset : std_logic;
- signal GSR_N : std_logic;
-
- signal clk_100_osc : std_logic;
- signal clk_200_osc : std_logic;
- signal time_counter : unsigned(31 downto 0);
-\r
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-\r
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-\r
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-\r
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-\r
- --Cu media interface
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
-
- signal sci2_ack : std_logic;
- signal sci2_nack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
-
-
- --SODA
- signal soda_rxup_full_clk : std_logic;
- signal soda_rxup_half_clk : std_logic;
- signal soda_txup_full_clk : std_logic;
- signal soda_txup_half_clk : std_logic;
-\r
- signal soda_txup_dlm_S : std_logic;
- signal soda_txup_dlm_word_S : std_logic_vector(7 downto 0);
- signal soda_rxup_dlm_S : std_logic;
- signal soda_rxup_dlm_word_S : std_logic_vector(7 downto 0);
- signal soda_txup_dlm_preview_S : std_logic;
- signal soda_uplink_phase_S : std_logic;
-\r
- --SODA downlink
- signal soda_rxdn_half_clk : t_HUB_BIT;
- signal soda_rxdn_full_clk : t_HUB_BIT;
- signal soda_txdn_half_clk : t_HUB_BIT;
- signal soda_txdn_full_clk : t_HUB_BIT;
-\r
- signal soda_txdn_dlm_S : t_HUB_BIT;
- signal soda_txdn_dlm_word_S : t_HUB_BYTE;
- signal soda_rxdn_dlm_S : t_HUB_BIT;
- signal soda_rxdn_dlm_word_S : t_HUB_BYTE;
- signal soda_txdn_dlm_preview_S : t_HUB_BIT;
- signal soda_dnlink_phase_S : t_HUB_BIT;
-
- -- SODA slow controll
- signal soda_ack : std_logic;
- signal soda_write : std_logic;
- signal soda_read : std_logic;
- signal soda_data_in : std_logic_vector(31 downto 0);
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0);
- signal soda_leds : std_logic_vector(3 downto 0);
-
- signal link_debug_in_S : std_logic_vector(31 downto 0);
- signal general_reset_i : std_logic := '1';
-\r
-begin\r
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-
- LED_RX <= (others => '0'); -- otherwise it is floating
- LED_TX <= (others => '0'); -- otherwise it is floating
- LED_LINKOK <= (others => '0'); -- otherwise it is floating
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, --clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_osc, --rx_half_clk, PL 111114, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
--------------------------------------------------------------------------
--- Clock Handling
--------------------------------------------------------------------------
-THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc,
- LOCK => pll_lock
- );
-\r
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
- TRB_MEDIA_AND_SODA_SYNC_UPLINK : Cu_trb_net16_soda_syncUP_ecp3_sfp
- port map(
- OSCCLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
-
- --Copper SFP Connection
- CU_RXD_P_IN => CU_SERDES_RX(0),
- CU_RXD_N_IN => CU_SERDES_RX(1),
- CU_TXD_P_OUT => CU_SERDES_TX(0),
- CU_TXD_N_OUT => CU_SERDES_TX(1),
- CU_PRSNT_N_IN => FPGA5_COMM(0),
- CU_LOS_IN => FPGA5_COMM(0),
- CU_TXDIS_OUT => FPGA5_COMM(2),
-
- -- sync clocks
- SYNC_RX_HALF_CLK_OUT => soda_rxup_half_clk,
- SYNC_RX_FULL_CLK_OUT => soda_rxup_full_clk,
- SYNC_TX_HALF_CLK_OUT => soda_txup_half_clk,
- SYNC_TX_FULL_CLK_OUT => soda_txup_full_clk,
-\r
- SYNC_RXD_P_IN => SERDES_ADDON_RX(4),
- SYNC_RXD_N_IN => SERDES_ADDON_RX(5),
- SYNC_TXD_P_OUT => SERDES_ADDON_TX(4),
- SYNC_TXD_N_OUT => SERDES_ADDON_TX(5),\r
- SYNC_TX_DLM_IN => soda_txup_dlm_S,
- SYNC_TX_DLM_WORD_IN => soda_txup_dlm_word_S,
- SYNC_RX_DLM_OUT => soda_rxup_dlm_S,
- SYNC_RX_DLM_WORD_OUT => soda_rxup_dlm_word_S,
- SYNC_PRSNT_N_IN => SFP_MOD0(3),
- SYNC_LOS_IN => SFP_LOS(3),
- SYNC_TXDIS_OUT => sfp_txdis_S(3),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => (others => '0')
- );
-
-
--------------------------------------------------------------------------
--- Endpoint
--------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
- --USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"45",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"9100b000",
- REGIO_INIT_ADDRESS => x"f35b",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 9, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 256,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 256
- )
- port map(
- CLK => clk_100_osc, --rx_half_clk, PL 111114
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out(0),
- MED_DATA_OUT => med_data_out(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_out(2 downto 0),
- MED_READ_IN => med_read_in(0),
- MED_DATAREADY_IN => med_dataready_in(0),
- MED_DATA_IN => med_data_in(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_in(2 downto 0),
- MED_READ_OUT => med_read_out(0),
- MED_STAT_OP_IN => med_stat_op(15 downto 0),
- MED_CTRL_OP_OUT => med_ctrl_op(15 downto 0),
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => '0',
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => open,
- LVL1_VALID_TIMING_TRG_OUT => open,
- LVL1_VALID_NOTIMING_TRG_OUT => open,
- LVL1_INVALID_TRG_OUT => open,
-
- LVL1_TRG_TYPE_OUT => open,
- LVL1_TRG_NUMBER_OUT => open,
- LVL1_TRG_CODE_OUT => open,
- LVL1_TRG_INFORMATION_OUT => open,
- LVL1_INT_TRG_NUMBER_OUT => open,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => open,
- TRG_TIMEOUT_DETECTED_OUT => open,
- TRG_SPURIOUS_TRG_OUT => open,
- TRG_MISSING_TMG_TRG_OUT => open,
- TRG_SPIKE_DETECTED_OUT => open,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => '1',
- FEE_TRG_STATUSBITS_IN => (others => '0'),
- FEE_DATA_IN => (others => '0'),
- FEE_DATA_WRITE_IN(0) => '0',
- FEE_DATA_FINISHED_IN(0) => '1',
- FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-\r
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 4, others => 0)
- )
- port map(
- CLK => clk_100_osc, --rx_half_clk, PL 111114
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_READ_ENABLE_OUT(2) => soda_read,
-
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_WRITE_ENABLE_OUT(2) => soda_write,
-
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+31 downto 2*32) => soda_data_in,
-
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_ADDR_OUT(2*16+3 downto 2*16) => soda_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+4) => open,
-
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32+8) => open,
- BUS_DATA_IN(2*32+31 downto 2*32) => soda_data_out,
-
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_DATAREADY_IN(2) => soda_ack,
-
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => soda_ack,
-
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
-
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => '0',
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
- port map(
- CLK_IN => clk_100_osc,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-\r
-\r
--- SFP_TXDIS(1) <= sfp_txdis_S(1);
- SFP_TXDIS <= sfp_txdis_S;\r
- \r
- -----------------------------------------------------------------------\r
- -- Since there is nomore trb on this link, link-phase does not need to\r
- -- be controlled. To avoid changing code, link-phase is faked here.\r
- -----------------------------------------------------------------------
- DUMMY_LINK_PHASE_PROC : process (soda_rxup_full_clk)\r
- begin\r
- if rising_edge(soda_rxup_full_clk) then\r
- if (reset_i='1') then\r
- soda_uplink_phase_S <='0';
- elsif (soda_uplink_phase_S='0') then
- soda_uplink_phase_S <='1';
- else
- soda_uplink_phase_S <='0';
- end if;\r
- end if;\r
- end process;
-
-
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------
-
- A_SODA_HUB : soda_hub
- port map(
- SYSCLK => soda_rxup_half_clk,
- SODACLK => soda_rxup_full_clk,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
-
- -- SINGLE DUBPLEX UP-LINK TO THE TOP
- RXUP_DLM_WORD_IN => soda_rxup_dlm_word_S,
- RXUP_DLM_IN => soda_rxup_dlm_S,
- TXUP_DLM_OUT => soda_txup_dlm_S,
- TXUP_DLM_WORD_OUT => soda_txup_dlm_word_S,
- TXUP_DLM_PREVIEW_OUT => soda_txup_dlm_preview_S,
- UPLINK_PHASE_IN => soda_uplink_phase_S,
- -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
- RXDN_DLM_WORD_IN => soda_rxdn_dlm_word_S,
- RXDN_DLM_IN => soda_rxdn_dlm_S,
- TXDN_DLM_OUT => soda_txdn_dlm_S,
- TXDN_DLM_WORD_OUT => soda_txdn_dlm_word_S,
- TXDN_DLM_PREVIEW_OUT => soda_txdn_dlm_preview_S,
- DNLINK_PHASE_IN => soda_dnlink_phase_S,
-
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds,
- LINK_DEBUG_IN => link_debug_in_S
- );
-\r
-
- downlink_reset <= reset_i; --'1' when (reset_i = '1' or uplink_ready_S = '0') else '0';
- downlink_clear <= clear_i; --'1' when (clear_i = '1' or uplink_ready_S = '0') else '0';
-
-
- THE_SODA_HUB_SYNC_DOWNLINK : soda_only_ecp3_sfp_4_sync_down
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_NO
- )
- port map(
- OSC_CLK => clk_200_osc,
- TX_DATACLK => soda_rxup_full_clk,
- SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
- RESET => downlink_reset,
- CLEAR => downlink_clear,
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
--- LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- RX_HALF_CLK_OUT(0) => soda_rxdn_half_clk(0),
- RX_HALF_CLK_OUT(1) => soda_rxdn_half_clk(1),
- RX_HALF_CLK_OUT(2) => soda_rxdn_half_clk(2),
- RX_HALF_CLK_OUT(3) => soda_rxdn_half_clk(3),
-
- RX_FULL_CLK_OUT(0) => soda_rxdn_full_clk(0), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(1) => soda_rxdn_full_clk(1), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(2) => soda_rxdn_full_clk(2), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(3) => soda_rxdn_full_clk(3), -- needed for sync replies i.e. calibration
-
- TX_HALF_CLK_OUT(0) => soda_txdn_half_clk(0),
- TX_HALF_CLK_OUT(1) => soda_txdn_half_clk(1),
- TX_HALF_CLK_OUT(2) => soda_txdn_half_clk(2),
- TX_HALF_CLK_OUT(3) => soda_txdn_half_clk(3),
-
- TX_FULL_CLK_OUT(0) => soda_txdn_full_clk(0),
- TX_FULL_CLK_OUT(1) => soda_txdn_full_clk(1),
- TX_FULL_CLK_OUT(2) => soda_txdn_full_clk(2),
- TX_FULL_CLK_OUT(3) => soda_txdn_full_clk(3),
-
- RX_DLM_OUT(0) => soda_rxdn_dlm_S(0),
- RX_DLM_OUT(1) => soda_rxdn_dlm_S(1),
- RX_DLM_OUT(2) => soda_rxdn_dlm_S(2),
- RX_DLM_OUT(3) => soda_rxdn_dlm_S(3),
-
- RX_DLM_WORD_OUT(0) => soda_rxdn_dlm_word_S(0),
- RX_DLM_WORD_OUT(1) => soda_rxdn_dlm_word_S(1),
- RX_DLM_WORD_OUT(2) => soda_rxdn_dlm_word_S(2),
- RX_DLM_WORD_OUT(3) => soda_rxdn_dlm_word_S(3),
-
- TX_DLM_IN(0) => soda_txdn_dlm_S(0),
- TX_DLM_IN(1) => soda_txdn_dlm_S(1),
- TX_DLM_IN(2) => soda_txdn_dlm_S(2),
- TX_DLM_IN(3) => soda_txdn_dlm_S(3),
-
- TX_DLM_WORD_IN(0) => soda_txdn_dlm_word_S(0),
- TX_DLM_WORD_IN(1) => soda_txdn_dlm_word_S(1),
- TX_DLM_WORD_IN(2) => soda_txdn_dlm_word_S(2),
- TX_DLM_WORD_IN(3) => soda_txdn_dlm_word_S(3),
-
- TX_DLM_PREVIEW_IN(0) => soda_txdn_dlm_preview_S(0), --PL!
- TX_DLM_PREVIEW_IN(1) => soda_txdn_dlm_preview_S(1), --PL!
- TX_DLM_PREVIEW_IN(2) => soda_txdn_dlm_preview_S(2), --PL!
- TX_DLM_PREVIEW_IN(3) => soda_txdn_dlm_preview_S(3), --PL!
-
- LINK_PHASE_OUT(0) => soda_dnlink_phase_S(0), --PL!
- LINK_PHASE_OUT(1) => soda_dnlink_phase_S(1), --PL!
- LINK_PHASE_OUT(2) => soda_dnlink_phase_S(2), --PL!
- LINK_PHASE_OUT(3) => soda_dnlink_phase_S(3), --PL!
-
- --SFP Connection
- SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0
- SD_RXD_P_IN(1) => SERDES_ADDON_RX(1),
- SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1
- SD_RXD_P_IN(3) => SERDES_ADDON_RX(11),
- SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2
- SD_RXD_N_IN(1) => SERDES_ADDON_RX(3),
- SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3
- SD_RXD_N_IN(3) => SERDES_ADDON_RX(7),
- SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0
- SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1),
- SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1
- SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11),
- SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2
- SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3),
- SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3
- SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7),
- SD_REFCLK_P_IN => (others => '0'),
- SD_REFCLK_N_IN => ('0','0','0','0'),
- SD_PRSNT_N_IN(0) => SFP_MOD0(1),
- SD_PRSNT_N_IN(1) => SFP_MOD0(6),
- SD_PRSNT_N_IN(2) => SFP_MOD0(2),
- SD_PRSNT_N_IN(3) => SFP_MOD0(4),
- SD_LOS_IN(0) => SFP_LOS(1),
- SD_LOS_IN(1) => SFP_LOS(6),
- SD_LOS_IN(2) => SFP_LOS(2),
- SD_LOS_IN(3) => SFP_LOS(4),
- SD_TXDIS_OUT(0) => sfp_txdis_S(1),
- SD_TXDIS_OUT(1) => sfp_txdis_S(6),
- SD_TXDIS_OUT(2) => sfp_txdis_S(2),
- SD_TXDIS_OUT(3) => sfp_txdis_S(4),
-
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
- SCI_NACK => sci2_nack
- );
-
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-\r
- LED_ORANGE <= time_counter(26);
- LED_YELLOW <= time_counter(26);
- LED_GREEN <= time_counter(26);
- LED_RED <= time_counter(26);
----------------------------------------------------------------------------
--- DEBUG
----------------------------------------------------------------------------
- link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0);
- link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- blink : process (clk_100_osc)
- begin
- if rising_edge(clk_100_osc) then
- if (time_counter = x"FFFFFFFF") then
- time_counter <= x"00000000";
- else
- time_counter <= time_counter + 1;
- end if;
- end if;
- end process;
-
-end Cu_trb3_periph_soda_hub_arch;
\ No newline at end of file
+++ /dev/null
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-
-entity Cu_trb_net16_soda_syncUP_ecp3_sfp is
- port(
- OSCCLK : in std_logic; -- 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- --Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
- --Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
-
- --Copper SFP Connection
- CU_RXD_P_IN : in std_logic;
- CU_RXD_N_IN : in std_logic;
- CU_TXD_P_OUT : out std_logic;
- CU_TXD_N_OUT : out std_logic;
- CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Fiber/sync SFP Connection
- SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- SYNC_TX_DLM_IN : in std_logic;
- SYNC_TX_DLM_WORD_IN : in std_logic_vector(7 downto 0);
- SYNC_RX_DLM_OUT : out std_logic;
- SYNC_RX_DLM_WORD_OUT : out std_logic_vector(7 downto 0);
- SYNC_RXD_P_IN : in std_logic;
- SYNC_RXD_N_IN : in std_logic;
- SYNC_TXD_P_OUT : out std_logic;
- SYNC_TXD_N_OUT : out std_logic;
- SYNC_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SYNC_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SYNC_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
-
- TX_READY_CH3 : out std_logic;
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
-end entity;
-
-architecture Cu_trb_net16_soda_syncUP_ecp3_sfp_arch of Cu_trb_net16_soda_syncUP_ecp3_sfp is
-
-
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of Cu_trb_net16_soda_syncUP_ecp3_sfp_arch : architecture is "media_interface_group";
- attribute syn_sharing : string;
- attribute syn_sharing of Cu_trb_net16_soda_syncUP_ecp3_sfp_arch : architecture is "off";
-
- component sfp_2_200_int
- port
- (
- hdinp_ch1, hdinn_ch1 : in std_logic;
- hdoutp_ch1, hdoutn_ch1 : out std_logic;
- sci_sel_ch1 : in std_logic;
- rxiclk_ch1 : in std_logic;
- txiclk_ch1 : in std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- tx_full_clk_ch1 : out std_logic;
- tx_half_clk_ch1 : out std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- txdata_ch1 : in std_logic_vector (15 downto 0);
- tx_k_ch1 : in std_logic_vector (1 downto 0);
- tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
- tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
- rxdata_ch1 : out std_logic_vector (15 downto 0);
- rx_k_ch1 : out std_logic_vector (1 downto 0);
- rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
- rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
- rx_serdes_rst_ch1_c : in std_logic;
- sb_felb_ch1_c : in std_logic;
- sb_felb_rst_ch1_c : in std_logic;
- tx_pcs_rst_ch1_c : in std_logic;
- tx_pwrup_ch1_c : in std_logic;
- rx_pcs_rst_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- rx_los_low_ch1_s : out std_logic;
- lsm_status_ch1_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- tx_div2_mode_ch1_c : in std_logic;
- rx_div2_mode_ch1_c : in std_logic;
-
- hdinp_ch3, hdinn_ch3 : in std_logic;
- hdoutp_ch3, hdoutn_ch3 : out std_logic;
- sci_sel_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- txdata_ch3 : in std_logic_vector (7 downto 0);
- tx_k_ch3 : in std_logic;
- tx_force_disp_ch3 : in std_logic;
- tx_disp_sel_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- rx_serdes_rst_ch3_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
- tx_pcs_rst_ch3_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pcs_rst_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
- tx_div2_mode_ch3_c : in std_logic;
- rx_div2_mode_ch3_c : in std_logic;
- ---- Miscillaneous ports
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- tx_sync_qd_c : in std_logic;
- rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
- serdes_rst_qd_c : in std_logic
- );
- end component;
-
- type t_sync_tx_proc_state is (cSEND_IDLE,cSEND_DLM); --,cFIFO_READ);
- signal sync_tx_proc_state : t_sync_tx_proc_state;
-
-
- signal refck2core : std_logic;
- -- signal clock : std_logic;
- --reset signals
- signal ffc_quad_rst : std_logic;
- signal ffc_lane_tx_rst : std_logic;
- signal ffc_lane_rx_rst : std_logic;
- --serdes connections
- signal tx_data : std_logic_vector(15 downto 0);
- signal tx_k : std_logic_vector(1 downto 0);
- signal rx_data : std_logic_vector(15 downto 0); -- delayed signals
- signal rx_k : std_logic_vector(1 downto 0); -- delayed signals
- signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP
- signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP
- signal link_ok : std_logic_vector(0 downto 0);
- signal link_error : std_logic_vector(8 downto 0);
- signal ff_txhalfclk : std_logic;
- signal ff_rxhalfclk : std_logic;
- signal ff_rxfullclk : std_logic;
- --rx fifo signals
- signal fifo_rx_rd_en : std_logic;
- signal fifo_rx_wr_en : std_logic;
- signal fifo_rx_reset : std_logic;
- signal fifo_rx_din : std_logic_vector(17 downto 0);
- signal fifo_rx_dout : std_logic_vector(17 downto 0);
- signal fifo_rx_full : std_logic;
- signal fifo_rx_empty : std_logic;
- --tx fifo signals
- signal fifo_tx_rd_en : std_logic;
- signal fifo_tx_wr_en : std_logic;
- signal fifo_tx_reset : std_logic;
- signal fifo_tx_din : std_logic_vector(17 downto 0);
- signal fifo_tx_dout : std_logic_vector(17 downto 0);
- signal fifo_tx_full : std_logic;
- signal fifo_tx_empty : std_logic;
- signal fifo_tx_almost_full : std_logic;
- --rx path
- signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal buf_med_dataready_out : std_logic;
- signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal last_rx : std_logic_vector(8 downto 0);
- signal last_fifo_rx_empty : std_logic;
- --tx path
- signal last_fifo_tx_empty : std_logic;
- --link status
- signal rx_k_q : std_logic_vector(1 downto 0);
-
- signal quad_rst : std_logic;
- signal lane_rst : std_logic;
- signal tx_allow : std_logic;
- signal rx_allow : std_logic;
- signal tx_allow_qtx : std_logic;
-
- signal rx_allow_q : std_logic; -- clock domain changed signal
- signal tx_allow_q : std_logic;
- signal swap_bytes : std_logic;
- signal buf_stat_debug : std_logic_vector(31 downto 0);
-
- -- status inputs from SFP
- signal sfp_prsnt_n : std_logic; -- synchronized input signals
- signal sfp_los : std_logic; -- synchronized input signals
-
- signal buf_STAT_OP : std_logic_vector(15 downto 0);
-
- signal led_counter : unsigned(16 downto 0);
- signal rx_led : std_logic;
- signal tx_led : std_logic;
-
-
- signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
- signal first_idle : std_logic; -- tag the first IDLE2 after data
-
- signal reset_word_cnt : unsigned(4 downto 0);
- signal make_trbnet_reset : std_logic;
- signal make_trbnet_reset_q : std_logic;
- signal send_reset_words : std_logic;
- signal send_reset_words_q : std_logic;
- signal send_reset_in : std_logic;
- signal send_reset_in_qtx : std_logic;
- signal reset_i : std_logic;
- signal reset_i_rx : std_logic;
- signal pwr_up : std_logic;
-
- signal clk_sys : std_logic;
- signal clk_tx : std_logic;
- signal clk_rx : std_logic;
- signal clk_rxref : std_logic;
- signal clk_txref : std_logic;
-
- -- Peter Schakel 3-dec-2014
-
- signal sci_timer : unsigned(12 downto 0) := (others => '0');
- signal reset_n : std_logic;
- signal trb_rx_serdes_rst : std_logic;
- signal trb_rx_cdr_lol : std_logic;
- signal trb_rx_los_low : std_logic;
- signal trb_rx_pcs_rst : std_logic;
- signal trb_tx_pcs_rst : std_logic;
- signal rst_qd : std_logic;
- signal rst_qd1 : std_logic;
- signal rst_qd3 : std_logic;
- signal link_OK_S : std_logic;
- signal trb_rx_fsm_state : std_logic_vector(3 downto 0);
- signal trb_tx_fsm_state : std_logic_vector(3 downto 0);
- signal sync_rx_fsm_state : std_logic_vector(3 downto 0);
- signal sync_tx_fsm_state : std_logic_vector(3 downto 0);
- signal clk_200_osc : std_logic;
- signal sync_rx_full_clk : std_logic;
- signal sync_rx_half_clk : std_logic;
- signal sync_tx_full_clk : std_logic;
- signal sync_tx_half_clk : std_logic;
-
- signal sync_tx_data : std_logic_vector(7 downto 0);
- signal sync_tx_k : std_logic;
- signal SYNC_TX_DLM_IN_S : std_logic;
- signal sync_rx_data : std_logic_vector(7 downto 0);
- signal sync_rx_k : std_logic;
- signal sync_rx_error : std_logic;
- signal sync_rx_serdes_rst : std_logic;
- signal sync_tx_pcs_rst : std_logic;
- signal sync_rx_pcs_rst : std_logic;
- signal sync_rx_los_low : std_logic;
- signal sync_lsm_status : std_logic;
- signal sync_rx_cdr_lol : std_logic;
- signal dlm_fifo_rd_en : std_logic;
- signal dlm_fifo_empty : std_logic;
- signal dlm_fifo_reading : std_logic;
- signal dlm_received_S : std_logic;
-
- signal syncfifo_din : std_logic_vector(17 downto 0);
- signal syncfifo_dout : std_logic_vector(17 downto 0);
-
- type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
- signal sci_state : sci_ctrl;
-
- signal sci_ch_i : std_logic_vector(3 downto 0);
- signal sci_qd_i : std_logic;
- signal sci_reg_i : std_logic;
- signal sci_addr_i : std_logic_vector(8 downto 0);
- signal sci_data_in_i : std_logic_vector(7 downto 0);
- signal sci_data_out_i : std_logic_vector(7 downto 0);
- signal sci_read_i : std_logic;
- signal sci_write_i : std_logic;
- signal sci_write_shift_i : std_logic_vector(2 downto 0);
- signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
- signal tx_pll_lol_qd_i : std_logic;
-
- signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
- signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
- signal sync_wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
- signal sync_tx_allow : std_logic;
- signal sync_rx_allow : std_logic;
- signal sync_tx_allow_q : std_logic;
- signal sync_rx_allow_q : std_logic;
- signal link_phase_S : std_logic; --PL!
- signal request_retr_i : std_logic;
- signal start_retr_i : std_logic;
- signal request_retr_position_i : std_logic_vector(7 downto 0);
- signal start_retr_position_i : std_logic_vector(7 downto 0);
- signal send_link_reset_i : std_logic;
- signal make_link_reset_i : std_logic;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
- attribute syn_keep of led_counter : signal is true;
- attribute syn_keep of send_reset_in : signal is true;
- attribute syn_keep of reset_i : signal is true;
- attribute syn_preserve of reset_i : signal is true;
- attribute syn_preserve of sci_ch_i : signal is true;--
- attribute syn_keep of sci_ch_i : signal is true;--
- attribute syn_preserve of sci_addr_i : signal is true;--
- attribute syn_keep of sci_addr_i : signal is true;--
- attribute syn_preserve of sci_data_in_i : signal is true;--
- attribute syn_keep of sci_data_in_i : signal is true;--
- attribute syn_preserve of sci_data_out_i : signal is true;--
- attribute syn_keep of sci_data_out_i : signal is true;--
- attribute syn_preserve of sci_read_i : signal is true;--
- attribute syn_keep of sci_read_i : signal is true;--
- attribute syn_preserve of sci_write_i : signal is true;--
- attribute syn_keep of sci_write_i : signal is true;--
- attribute syn_preserve of sci_write_shift_i : signal is true;--
- attribute syn_keep of sci_write_shift_i : signal is true;--
- attribute syn_preserve of sci_read_shift_i : signal is true;--
- attribute syn_keep of sci_read_shift_i : signal is true;--
- attribute syn_preserve of wa_position : signal is true;--
- attribute syn_keep of wa_position : signal is true;--
- attribute syn_preserve of wa_position_rx : signal is true;--
- attribute syn_keep of wa_position_rx : signal is true;--
-
-begin
-
-clk_200_osc <= OSCCLK;
-
-SYNC_RX_HALF_CLK_OUT <= sync_rx_half_clk;
-SYNC_RX_FULL_CLK_OUT <= sync_rx_full_clk;
-SYNC_TX_HALF_CLK_OUT <= sync_tx_half_clk;
-SYNC_TX_FULL_CLK_OUT <= sync_tx_full_clk;
---RX_CDR_LOL_OUT <= rx_cdr_lol;
-
-clk_sys <= SYSCLK;
-clk_tx <= SYSCLK;
-clk_rx <= ff_rxhalfclk;
-clk_rxref <= OSCCLK;
-clk_txref <= OSCCLK;
-
---sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!
-
---------------------------------------------------------------------------
--- Internal Lane Resets
---------------------------------------------------------------------------
- PROC_RESET : process(clk_sys)
- begin
- if rising_edge(clk_sys) then
- reset_i <= RESET;
- send_reset_in <= ctrl_op(15);
- pwr_up <= '1'; --not CTRL_OP(i*16+14);
- end if;
- end process;
-
---------------------------------------------------------------------------
--- Synchronizer stages
---------------------------------------------------------------------------
-
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
-THE_SFP_STATUS_SYNC: signal_sync
- generic map(
- DEPTH => 3,
- WIDTH => 2
- )
- port map(
- RESET => '0',
- D_IN(0) => sync_prsnt_n_in,
- D_IN(1) => sync_los_in,
- CLK0 => clk_sys,
- CLK1 => clk_sys,
- D_OUT(0) => sfp_prsnt_n,
- D_OUT(1) => sfp_los
- );
-
-
-THE_RX_K_SYNC: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 4
- )
- port map(
- RESET => reset_i,
- D_IN(1 downto 0) => comb_rx_k,
- D_IN(2) => send_reset_words,
- D_IN(3) => make_trbnet_reset,
- CLK0 => clk_rx, -- CHANGED
- CLK1 => clk_sys,
- D_OUT(1 downto 0) => rx_k_q,
- D_OUT(2) => send_reset_words_q,
- D_OUT(3) => make_trbnet_reset_q
- );
-
-THE_RX_DATA_DELAY: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 16
- )
- port map(
- RESET => reset_i,
- D_IN => comb_rx_data,
- CLK0 => clk_rx,
- CLK1 => clk_rx,
- D_OUT => rx_data
- );
-
-THE_RX_K_DELAY: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 2
- )
- port map(
- RESET => reset_i,
- D_IN => comb_rx_k,
- CLK0 => clk_rx,
- CLK1 => clk_rx,
- D_OUT => rx_k
- );
-
-THE_RX_RESET: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 1
- )
- port map(
- RESET => '0',
- D_IN(0) => reset_i,
- CLK0 => clk_rx,
- CLK1 => clk_rx,
- D_OUT(0) => reset_i_rx
- );
-
--- Delay for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 2
- )
- port map(
- RESET => reset_i,
- D_IN(0) => rx_allow,
- D_IN(1) => tx_allow,
- CLK0 => clk_sys,
- CLK1 => clk_sys,
- D_OUT(0) => rx_allow_q,
- D_OUT(1) => tx_allow_q
- );
-
-THE_TX_SYNC: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 2
- )
- port map(
- RESET => '0',
- D_IN(0) => send_reset_in,
- D_IN(1) => tx_allow,
- CLK0 => clk_tx,
- CLK1 => clk_tx,
- D_OUT(0) => send_reset_in_qtx,
- D_OUT(1) => tx_allow_qtx
- );
-
---THE_DLM_IN_DELAY: signal_sync
--- generic map(
--- DEPTH => 1,
--- WIDTH => 1
--- )
--- port map(
--- RESET => '0',
--- D_IN(0) => SYNC_TX_DLM_IN,
--- CLK0 => sync_rx_full_clk,
--- CLK1 => sync_rx_full_clk,
--- D_OUT(0) => SYNC_TX_DLM_IN_S
--- );
---------------------------------------------------------------------------
--- Main control state machine, startup control for SFP
---------------------------------------------------------------------------
-
-THE_SFP_LSM: trb_net16_lsm_sfp
- generic map (
- HIGHSPEED_STARTUP => c_YES
- )
- port map(
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear,
- SFP_MISSING_IN => sfp_prsnt_n,
- SFP_LOS_IN => sfp_los,
- SD_LINK_OK_IN => link_ok(0),
- SD_LOS_IN => link_error(8),
- SD_TXCLK_BAD_IN => link_error(5),
- SD_RXCLK_BAD_IN => link_error(4),
- SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
- SD_ALIGNMENT_IN => rx_k_q,
- SD_CV_IN => link_error(7 downto 6),
- FULL_RESET_OUT => quad_rst,
- LANE_RESET_OUT => lane_rst,
- TX_ALLOW_OUT => tx_allow,
- RX_ALLOW_OUT => rx_allow,
- SWAP_BYTES_OUT => swap_bytes,
- STAT_OP => buf_stat_op,
- CTRL_OP => ctrl_op,
- STAT_DEBUG => buf_stat_debug
- );
-
-SYNC_TXDIS_OUT <= quad_rst or reset_i;
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
-ffc_quad_rst <= quad_rst;
-ffc_lane_tx_rst <= lane_rst;
-
-
-ffc_lane_rx_rst <= lane_rst;
-
-
-
--- Instantiation of serdes module
-
- THE_SERDES: sfp_2_200_int
- port map(
- HDINP_CH1 => CU_RXD_P_IN,
- HDINN_CH1 => CU_RXD_N_IN,
- HDOUTP_CH1 => CU_TXD_P_OUT,
- HDOUTN_CH1 => CU_TXD_N_OUT,
- SCI_SEL_CH1 => sci_ch_i(1),
- RXICLK_CH1 => clk_rx,
- TXICLK_CH1 => clk_tx,
- RX_FULL_CLK_CH1 => ff_rxfullclk,
- RX_HALF_CLK_CH1 => ff_rxhalfclk,
- TX_FULL_CLK_CH1 => open,
- TX_HALF_CLK_CH1 => ff_txhalfclk,
- FPGA_RXREFCLK_CH1 => clk_rxref,
- TXDATA_CH1 => tx_data,
- TX_K_CH1 => tx_k,
- TX_FORCE_DISP_CH1 => tx_correct,
- TX_DISP_SEL_CH1 => "00",
- RXDATA_CH1 => comb_rx_data,
- RX_K_CH1 => comb_rx_k,
- RX_DISP_ERR_CH1 => open,
- RX_CV_ERR_CH1 => link_error(7 downto 6),
- RX_SERDES_RST_CH1_C => trb_rx_serdes_rst,
- SB_FELB_CH1_C => '0', --loopback enable
- SB_FELB_RST_CH1_C => '0', --loopback reset
- TX_PCS_RST_CH1_C => trb_tx_pcs_rst, --'1', --tx power up
- TX_PWRUP_CH1_C => '1', --tx power up
- RX_PCS_RST_CH1_C => trb_rx_pcs_rst, --'1', --rx power up
- RX_PWRUP_CH1_C => '1', --rx power up
- RX_LOS_LOW_CH1_S => trb_rx_los_low, --link_error(8),
- LSM_STATUS_CH1_S => link_ok(0),
- RX_CDR_LOL_CH1_S => trb_rx_cdr_lol, --link_error(4),
- TX_DIV2_MODE_CH1_C => '0', --full rate
- RX_DIV2_MODE_CH1_C => '0', --full rate
-
- HDINP_CH3 => SYNC_RXD_P_IN,
- HDINN_CH3 => SYNC_RXD_N_IN,
- HDOUTP_CH3 => SYNC_TXD_P_OUT,
- HDOUTN_CH3 => SYNC_TXD_N_OUT,
- SCI_SEL_CH3 => sci_ch_i(3),
- TXICLK_CH3 => sync_rx_full_clk,
- RX_FULL_CLK_CH3 => sync_rx_full_clk,
- RX_HALF_CLK_CH3 => sync_rx_half_clk,
- TX_FULL_CLK_CH3 => sync_tx_full_clk,
- TX_HALF_CLK_CH3 => sync_tx_half_clk,
- FPGA_RXREFCLK_CH3 => clk_200_osc,
- TXDATA_CH3 => sync_tx_data,
- TX_K_CH3 => sync_tx_k,
- TX_FORCE_DISP_CH3 => '0',
- TX_DISP_SEL_CH3 => '0',
- RXDATA_CH3 => sync_rx_data,
- RX_K_CH3 => sync_rx_k,
- RX_DISP_ERR_CH3 => open,
- RX_CV_ERR_CH3 => sync_rx_error,
- RX_SERDES_RST_CH3_C => sync_rx_serdes_rst,
- SB_FELB_CH3_C => '0', --loopback enable
- SB_FELB_RST_CH3_C => '0', --loopback reset
- TX_PCS_RST_CH3_C => sync_tx_pcs_rst,
- TX_PWRUP_CH3_C => '1',
- RX_PCS_RST_CH3_C => sync_rx_pcs_rst,
- RX_PWRUP_CH3_C => '1',
- RX_LOS_LOW_CH3_S => sync_rx_los_low,
- LSM_STATUS_CH3_S => sync_lsm_status,
- RX_CDR_LOL_CH3_S => sync_rx_cdr_lol,
- TX_DIV2_MODE_CH3_C => '0',
- RX_DIV2_MODE_CH3_C => '0',
-
- SCI_WRDATA => sci_data_in_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_RDDATA => sci_data_out_i,
- SCI_SEL_QUAD => sci_addr_i(8),
- SCI_RD => sci_read_i,
- SCI_WRN => sci_write_i,
- FPGA_TXREFCLK => clk_txref,
--- FPGA_TXREFCLK => rx_full_clk,
- TX_SERDES_RST_C => CLEAR,
- TX_PLL_LOL_QD_S => link_error(5),
- TX_SYNC_QD_C => '0',
- RST_QD_C => rst_qd,
- REFCLK2FPGA => open,
- SERDES_RST_QD_C => ffc_quad_rst
- );
-
--------------------------------------------------------------------------
--- RX Fifo & Data output
--------------------------------------------------------------------------
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
-generic map(
- USE_STATUS_FLAGS => c_NO
- )
-port map( read_clock_in => clk_sys,
- write_clock_in => clk_rx, -- CHANGED
- read_enable_in => fifo_rx_rd_en,
- write_enable_in => fifo_rx_wr_en,
- fifo_gsr_in => fifo_rx_reset,
- write_data_in => fifo_rx_din,
- read_data_out => fifo_rx_dout,
- full_out => fifo_rx_full,
- empty_out => fifo_rx_empty
- );
-
-fifo_rx_reset <= reset_i or not rx_allow_q;
-fifo_rx_rd_en <= not fifo_rx_empty;
-
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process
- begin
- wait until rising_edge(clk_rx); --CHANGED
- last_rx <= rx_k(1) & rx_data(15 downto 8);
- if( swap_bytes = '0' ) then
- fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
- fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
- else
- fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
- fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
- end if;
- end process THE_BYTE_SWAP_PROC;
-
-buf_med_data_out <= fifo_rx_dout(15 downto 0);
-buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
-buf_med_packet_num_out <= rx_counter;
-med_read_out <= tx_allow_q and not fifo_tx_almost_full;
-
-
-THE_CNT_RESET_PROC : process
- begin
- wait until rising_edge(clk_rx); --CHANGED
- if reset_i_rx = '1' then
- send_reset_words <= '0';
- make_trbnet_reset <= '0';
- reset_word_cnt <= (others => '0');
- else
- send_reset_words <= '0';
- make_trbnet_reset <= '0';
- if fifo_rx_din = "11" & x"FEFE" then
- if reset_word_cnt(4) = '0' then
- reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
- else
- send_reset_words <= '1';
- end if;
- else
- reset_word_cnt <= (others => '0');
- make_trbnet_reset <= reset_word_cnt(4);
- end if;
- end if;
- end process;
-
-
-THE_SYNC_PROC: process
- begin
- wait until rising_edge(clk_sys);
- med_dataready_out <= buf_med_dataready_out;
- med_data_out <= buf_med_data_out;
- med_packet_num_out <= buf_med_packet_num_out;
- if reset_i = '1' then
- med_dataready_out <= '0';
- end if;
- end process;
-
-
---rx packet counter
----------------------
-THE_RX_PACKETS_PROC: process( clk_sys )
- begin
- if( rising_edge(clk_sys) ) then
- last_fifo_rx_empty <= fifo_rx_empty;
- if reset_i = '1' or rx_allow_q = '0' then
- rx_counter <= c_H0;
- else
- if( buf_med_dataready_out = '1' ) then
- if( rx_counter = c_max_word_number ) then
- rx_counter <= (others => '0');
- else
- rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
- end if;
- end if;
- end if;
- end if;
- end process;
-
---TX Fifo & Data output to Serdes
----------------------
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map( read_clock_in => clk_tx,
- write_clock_in => clk_sys,
- read_enable_in => fifo_tx_rd_en,
- write_enable_in => fifo_tx_wr_en,
- fifo_gsr_in => fifo_tx_reset,
- write_data_in => fifo_tx_din,
- read_data_out => fifo_tx_dout,
- full_out => fifo_tx_full,
- empty_out => fifo_tx_empty,
- almost_full_out => fifo_tx_almost_full
- );
-
-fifo_tx_reset <= reset_i or not tx_allow_q;
-fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
-fifo_tx_rd_en <= tx_allow_qtx;
-
-
-THE_SERDES_INPUT_PROC: process( clk_tx )
- begin
- if( rising_edge(clk_tx) ) then
- last_fifo_tx_empty <= fifo_tx_empty;
- first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
- if send_reset_in = '1' then
- tx_data <= x"FEFE";
- tx_k <= "11";
- elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
- tx_data <= x"50bc";
- tx_k <= "01";
- tx_correct <= first_idle & '0';
- else
- tx_data <= fifo_tx_dout(15 downto 0);
- tx_k <= "00";
- tx_correct <= "00";
- end if;
- end if;
- end process THE_SERDES_INPUT_PROC;
-
-
-sync_rx_proc : process(sync_rx_full_clk)
-begin
- if rising_edge(sync_rx_full_clk) then
- SYNC_RX_DLM_OUT <= '0';
- if dlm_received_S='1' then
- dlm_received_S <= '0';
- SYNC_RX_DLM_OUT <= '1';
- SYNC_RX_DLM_WORD_OUT <= sync_rx_data;
- elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
- dlm_received_S <= '1';
- end if;
- end if;
-end process;
-
-sync_tx_fsm : process(sync_tx_full_clk)
-begin
- if rising_edge(sync_tx_full_clk) then
- case sync_tx_proc_state is
- when cSEND_IDLE =>
- if (SYNC_TX_DLM_IN='0') then
- sync_tx_proc_state <= cSEND_IDLE;
--- dlm_fifo_rd_en <= '0';
- sync_tx_data <= x"BC"; -- idle
- sync_tx_k <= '1';
- else
- sync_tx_proc_state <= cSEND_DLM;
--- dlm_fifo_rd_en <= '1';
- sync_tx_data <= x"DC"; -- dlm
- sync_tx_k <= '1';
- end if;
--- when cFIFO_READ =>
--- sync_tx_proc_state <= cSEND_DLM;
--- dlm_fifo_rd_en <= '0';
--- sync_tx_data <= x"DC"; -- dlm
--- sync_tx_k <= '1';
- when cSEND_DLM =>
- sync_tx_proc_state <= cSEND_IDLE;
--- dlm_fifo_rd_en <= '0';
- sync_tx_data <= SYNC_TX_DLM_WORD_IN; --syncfifo_dout(7 downto 0);
- sync_tx_k <= '0';
- when others =>
- sync_tx_proc_state <= cSEND_IDLE;
- dlm_fifo_rd_en <= '0';
- sync_tx_data <= x"BC"; -- idle
- sync_tx_k <= '1';
- end case;
- end if;
-end process;
-
-
---sync_tx_proc : process(sync_tx_full_clk)
---begin
- --if rising_edge(sync_tx_full_clk) then
- --if dlm_fifo_rd_en='1' then
- --dlm_fifo_rd_en <= '0';
- --sync_tx_data <= syncfifo_dout(7 downto 0);
- --sync_tx_k <= '0';
- --elsif (dlm_fifo_empty='0') and (dlm_fifo_reading='1') then
- --dlm_fifo_rd_en <= '1';
- --sync_tx_data <= x"DC";
- --sync_tx_k <= '1';
- --elsif dlm_fifo_empty='0' then
- --dlm_fifo_reading <= '1';
- --dlm_fifo_rd_en <= '0';
- --sync_tx_data <= x"BC"; -- idle
- --sync_tx_k <= '1';
- --else
- --dlm_fifo_reading <= '0';
- --dlm_fifo_rd_en <= '0';
- --sync_tx_data <= x"BC"; -- idle
- --sync_tx_k <= '1';
- --end if;
- --end if;
---end process;
-
-link_error(8) <= trb_rx_los_low; -- loss of signal
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock
-
-reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';
-
--------------------------------------------------
--- Reset FSM & Link states
--------------------------------------------------
-THE_RX_FSM1: rx_reset_fsm
- port map(
- RST_N => reset_n,
- RX_REFCLK => OSCCLK,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RX_SERDES_RST_CH_C => trb_rx_serdes_rst,
- RX_CDR_LOL_CH_S => trb_rx_cdr_lol,
- RX_LOS_LOW_CH_S => trb_rx_los_low,
- RX_PCS_RST_CH_C => trb_rx_pcs_rst,
- WA_POSITION => "0000",
- STATE_OUT => trb_rx_fsm_state
- );
-
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';
-
-THE_TX_FSM1: tx_reset_fsm
- port map(
- RST_N => reset_n,
- TX_REFCLK => OSCCLK,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RST_QD_C => rst_qd1,
- TX_PCS_RST_CH_C => trb_tx_pcs_rst,
- STATE_OUT => trb_tx_fsm_state --open
- );
-
-THE_RX_FSM3: rx_reset_fsm
- port map(
- RST_N => reset_n,
- RX_REFCLK => sync_rx_full_clk,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RX_SERDES_RST_CH_C => sync_rx_serdes_rst,
- RX_CDR_LOL_CH_S => sync_rx_cdr_lol,
- RX_LOS_LOW_CH_S => sync_rx_los_low,
- RX_PCS_RST_CH_C => sync_rx_pcs_rst,
- WA_POSITION => sync_wa_position_rx(11 downto 8),
- STATE_OUT => sync_rx_fsm_state
- );
-
-SYNC_WA_POSITION : process(sync_rx_full_clk) --??CLK)
-begin
- if rising_edge(sync_rx_full_clk) then
- sync_wa_position_rx <= wa_position;
- end if;
-end process;
-
-THE_TX_FSM3 : tx_reset_fsm
- port map(
- RST_N => reset_n,
- TX_REFCLK => OSCCLK,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RST_QD_C => rst_qd3,
- TX_PCS_RST_CH_C => sync_tx_pcs_rst,
- STATE_OUT => sync_tx_fsm_state
- );
-
---rst_qd <= '1' when (rst_qd1='1') or (rst_qd3='1') else '0';
-rst_qd <= RESET;
-
-TX_READY_CH3 <= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';
-
------------------------------------------------------------------------------------------------------
--- SCI --gives access to serdes config port from slow control and reads word alignment every ~ 40 us
------------------------------------------------------------------------------------------------------
-PROC_SCI_CTRL: process(clk_sys)
- variable cnt : integer range 0 to 4 := 0;
-begin
- if( rising_edge(clk_sys) ) then
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer <= sci_timer + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- elsif sci_timer(sci_timer'left) = '1' then
- sci_timer <= (others => '0');
- sci_state <= GET_WA;
- end if;
- when SCTRL =>
- if sci_reg_i = '1' then
- --// SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_DATA_OUT <= (others => '0');
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
- when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
- when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
- when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
- when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
- when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
- when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
- when GET_WA_FINISH =>
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
- end case;
-
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
- else
- SCI_NACK <= '0';
- end if;
- end if;
-end process PROC_SCI_CTRL;
-
-----------------------
---Generate LED signals
-----------------------
-LED_PROC : process( clk_sys )
- begin
- if rising_edge(clk_sys) then
- led_counter <= led_counter + to_unsigned(1,1);
- if buf_med_dataready_out = '1' then
- rx_led <= '1';
- elsif led_counter = 0 then
- rx_led <= '0';
- end if;
- if tx_k(0) = '0' then
- tx_led <= '1';
- elsif led_counter = 0 then
- tx_led <= '0';
- end if;
- end if;
- end process LED_PROC;
-
-
-stat_op(15) <= send_reset_words_q;
-stat_op(14) <= buf_stat_op(14);
-stat_op(13) <= make_trbnet_reset_q;
-stat_op(12) <= '0';
-stat_op(11) <= tx_led; --tx led
-stat_op(10) <= rx_led; --rx led
-stat_op(9 downto 0) <= buf_stat_op(9 downto 0);
-
--- Debug output
-stat_debug(15 downto 0) <= rx_data;
-stat_debug(17 downto 16) <= rx_k;
-stat_debug(19 downto 18) <= (others => '0');
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
-stat_debug(24) <= fifo_rx_rd_en;
-stat_debug(25) <= fifo_rx_wr_en;
-stat_debug(26) <= fifo_rx_reset;
-stat_debug(27) <= fifo_rx_empty;
-stat_debug(28) <= fifo_rx_full;
-stat_debug(29) <= last_rx(8);
-stat_debug(30) <= rx_allow_q;
-stat_debug(41 downto 31) <= (others => '0');
-stat_debug(42) <= clk_sys;
-stat_debug(43) <= clk_sys;
-stat_debug(59 downto 44) <= (others => '0');
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
-
-
-end Cu_trb_net16_soda_syncUP_ecp3_sfp_arch;
\ No newline at end of file
+++ /dev/null
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;\r
-use work.med_sync_define.all;
-
-entity Cu_trb_net16_soda_sync_ecp3_sfp is
- port(
- OSCCLK : in std_logic; -- 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- --Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
- --Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
-
- --Copper SFP Connection
- CU_RXD_P_IN : in std_logic;
- CU_RXD_N_IN : in std_logic;
- CU_TXD_P_OUT : out std_logic;
- CU_TXD_N_OUT : out std_logic;
- CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Fiber/sync SFP Connection
- SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- SYNC_DLM_IN : in std_logic;
- SYNC_DLM_WORD_IN : in std_logic_vector(7 downto 0);
- SYNC_DLM_OUT : out std_logic;
- SYNC_DLM_WORD_OUT : out std_logic_vector(7 downto 0);
- SYNC_RXD_P_IN : in std_logic;
- SYNC_RXD_N_IN : in std_logic;
- SYNC_TXD_P_OUT : out std_logic;
- SYNC_TXD_N_OUT : out std_logic;
- SYNC_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SYNC_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SYNC_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';\r
-\r
- TX_READY_CH3 : out std_logic;
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
-end entity;
-
-architecture Cu_trb_net16_soda_sync_ecp3_sfp_arch of Cu_trb_net16_soda_sync_ecp3_sfp is
-
-
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "media_interface_group";
- attribute syn_sharing : string;
- attribute syn_sharing of Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "off";
-
- component sfp_2_200_int
- port
- (
- hdinp_ch1, hdinn_ch1 : in std_logic;
- hdoutp_ch1, hdoutn_ch1 : out std_logic;
- sci_sel_ch1 : in std_logic;
- rxiclk_ch1 : in std_logic;
- txiclk_ch1 : in std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- tx_full_clk_ch1 : out std_logic;
- tx_half_clk_ch1 : out std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- txdata_ch1 : in std_logic_vector (15 downto 0);
- tx_k_ch1 : in std_logic_vector (1 downto 0);
- tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
- tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
- rxdata_ch1 : out std_logic_vector (15 downto 0);
- rx_k_ch1 : out std_logic_vector (1 downto 0);
- rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
- rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
- rx_serdes_rst_ch1_c : in std_logic;
- sb_felb_ch1_c : in std_logic;
- sb_felb_rst_ch1_c : in std_logic;
- tx_pcs_rst_ch1_c : in std_logic;
- tx_pwrup_ch1_c : in std_logic;
- rx_pcs_rst_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- rx_los_low_ch1_s : out std_logic;
- lsm_status_ch1_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- tx_div2_mode_ch1_c : in std_logic;
- rx_div2_mode_ch1_c : in std_logic;
-
- hdinp_ch3, hdinn_ch3 : in std_logic;
- hdoutp_ch3, hdoutn_ch3 : out std_logic;
- sci_sel_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- txdata_ch3 : in std_logic_vector (7 downto 0);
- tx_k_ch3 : in std_logic;
- tx_force_disp_ch3 : in std_logic;
- tx_disp_sel_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- rx_serdes_rst_ch3_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
- tx_pcs_rst_ch3_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pcs_rst_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
- tx_div2_mode_ch3_c : in std_logic;
- rx_div2_mode_ch3_c : in std_logic;
- ---- Miscillaneous ports
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- tx_sync_qd_c : in std_logic;
- rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
- serdes_rst_qd_c : in std_logic
- );
- end component;
-\r
- type t_sync_tx_proc_state is (cSEND_IDLE,cSEND_DLM,cFIFO_READ);
- signal sync_tx_proc_state : t_sync_tx_proc_state;
-\r
-
- signal refck2core : std_logic;
- -- signal clock : std_logic;
- --reset signals
- signal ffc_quad_rst : std_logic;
- signal ffc_lane_tx_rst : std_logic;
- signal ffc_lane_rx_rst : std_logic;
- --serdes connections
- signal tx_data : std_logic_vector(15 downto 0);
- signal tx_k : std_logic_vector(1 downto 0);
- signal rx_data : std_logic_vector(15 downto 0); -- delayed signals
- signal rx_k : std_logic_vector(1 downto 0); -- delayed signals
- signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP
- signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP
- signal link_ok : std_logic_vector(0 downto 0);
- signal link_error : std_logic_vector(8 downto 0);
- signal ff_txhalfclk : std_logic;
- signal ff_rxhalfclk : std_logic;
- signal ff_rxfullclk : std_logic;
- --rx fifo signals
- signal fifo_rx_rd_en : std_logic;
- signal fifo_rx_wr_en : std_logic;
- signal fifo_rx_reset : std_logic;
- signal fifo_rx_din : std_logic_vector(17 downto 0);
- signal fifo_rx_dout : std_logic_vector(17 downto 0);
- signal fifo_rx_full : std_logic;
- signal fifo_rx_empty : std_logic;
- --tx fifo signals
- signal fifo_tx_rd_en : std_logic;
- signal fifo_tx_wr_en : std_logic;
- signal fifo_tx_reset : std_logic;
- signal fifo_tx_din : std_logic_vector(17 downto 0);
- signal fifo_tx_dout : std_logic_vector(17 downto 0);
- signal fifo_tx_full : std_logic;
- signal fifo_tx_empty : std_logic;
- signal fifo_tx_almost_full : std_logic;
- --rx path
- signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal buf_med_dataready_out : std_logic;
- signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal last_rx : std_logic_vector(8 downto 0);
- signal last_fifo_rx_empty : std_logic;
- --tx path
- signal last_fifo_tx_empty : std_logic;
- --link status
- signal rx_k_q : std_logic_vector(1 downto 0);
-
- signal quad_rst : std_logic;
- signal lane_rst : std_logic;
- signal tx_allow : std_logic;
- signal rx_allow : std_logic;
- signal tx_allow_qtx : std_logic;
-
- signal rx_allow_q : std_logic; -- clock domain changed signal
- signal tx_allow_q : std_logic;
- signal swap_bytes : std_logic;
- signal buf_stat_debug : std_logic_vector(31 downto 0);
-
- -- status inputs from SFP
- signal sfp_prsnt_n : std_logic; -- synchronized input signals
- signal sfp_los : std_logic; -- synchronized input signals
-
- signal buf_STAT_OP : std_logic_vector(15 downto 0);
-
- signal led_counter : unsigned(16 downto 0);
- signal rx_led : std_logic;
- signal tx_led : std_logic;
-
-
- signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
- signal first_idle : std_logic; -- tag the first IDLE2 after data
-
- signal reset_word_cnt : unsigned(4 downto 0);
- signal make_trbnet_reset : std_logic;
- signal make_trbnet_reset_q : std_logic;
- signal send_reset_words : std_logic;
- signal send_reset_words_q : std_logic;
- signal send_reset_in : std_logic;
- signal send_reset_in_qtx : std_logic;
- signal reset_i : std_logic;
- signal reset_i_rx : std_logic;
- signal pwr_up : std_logic;
-
- signal clk_sys : std_logic;
- signal clk_tx : std_logic;
- signal clk_rx : std_logic;
- signal clk_rxref : std_logic;
- signal clk_txref : std_logic;
-
- -- Peter Schakel 3-dec-2014
-
- signal sci_timer : unsigned(12 downto 0) := (others => '0');
- signal reset_n : std_logic;
- signal trb_rx_serdes_rst : std_logic;
- signal trb_rx_cdr_lol : std_logic;
- signal trb_rx_los_low : std_logic;
- signal trb_rx_pcs_rst : std_logic;
- signal trb_tx_pcs_rst : std_logic;
- signal rst_qd : std_logic;
- signal rst_qd1 : std_logic;
- signal rst_qd3 : std_logic;
- signal link_OK_S : std_logic;
- signal trb_rx_fsm_state : std_logic_vector(3 downto 0);
- signal trb_tx_fsm_state : std_logic_vector(3 downto 0);
- signal sync_rx_fsm_state : std_logic_vector(3 downto 0);
- signal sync_tx_fsm_state : std_logic_vector(3 downto 0);
- signal clk_200_osc : std_logic;
- signal sync_rx_full_clk : std_logic;
- signal sync_rx_half_clk : std_logic;
- signal sync_tx_full_clk : std_logic;
- signal sync_tx_half_clk : std_logic;
-
- signal sync_tx_data : std_logic_vector(7 downto 0);
- signal sync_tx_k : std_logic;
- signal sync_dlm_in_S : std_logic;
- signal sync_rx_data : std_logic_vector(7 downto 0);
- signal sync_rx_k : std_logic;
- signal sync_rx_error : std_logic;
- signal sync_rx_serdes_rst : std_logic;
- signal sync_tx_pcs_rst : std_logic;
- signal sync_rx_pcs_rst : std_logic;
- signal sync_rx_los_low : std_logic;
- signal sync_lsm_status : std_logic;
- signal sync_rx_cdr_lol : std_logic;
- signal dlm_fifo_rd_en : std_logic;
- signal dlm_fifo_empty : std_logic;
- signal dlm_fifo_reading : std_logic;
- signal dlm_received_S : std_logic;
-
- signal syncfifo_din : std_logic_vector(17 downto 0);
- signal syncfifo_dout : std_logic_vector(17 downto 0);
-
- type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
- signal sci_state : sci_ctrl;\r
-
- signal sci_ch_i : std_logic_vector(3 downto 0);
- signal sci_qd_i : std_logic;
- signal sci_reg_i : std_logic;
- signal sci_addr_i : std_logic_vector(8 downto 0);
- signal sci_data_in_i : std_logic_vector(7 downto 0);
- signal sci_data_out_i : std_logic_vector(7 downto 0);
- signal sci_read_i : std_logic;
- signal sci_write_i : std_logic;
- signal sci_write_shift_i : std_logic_vector(2 downto 0);
- signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
- signal tx_pll_lol_qd_i : std_logic;
-\r
- signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
- signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
- signal sync_wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
- signal sync_tx_allow : std_logic;
- signal sync_rx_allow : std_logic;
- signal sync_tx_allow_q : std_logic;
- signal sync_rx_allow_q : std_logic;
- signal link_phase_S : std_logic; --PL!
- signal request_retr_i : std_logic;
- signal start_retr_i : std_logic;
- signal request_retr_position_i : std_logic_vector(7 downto 0);
- signal start_retr_position_i : std_logic_vector(7 downto 0);
- signal send_link_reset_i : std_logic;
- signal make_link_reset_i : std_logic;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
- attribute syn_keep of led_counter : signal is true;
- attribute syn_keep of send_reset_in : signal is true;
- attribute syn_keep of reset_i : signal is true;
- attribute syn_preserve of reset_i : signal is true;
- attribute syn_preserve of sci_ch_i : signal is true;--
- attribute syn_keep of sci_ch_i : signal is true;--
- attribute syn_preserve of sci_addr_i : signal is true;--
- attribute syn_keep of sci_addr_i : signal is true;--
- attribute syn_preserve of sci_data_in_i : signal is true;--
- attribute syn_keep of sci_data_in_i : signal is true;--
- attribute syn_preserve of sci_data_out_i : signal is true;--
- attribute syn_keep of sci_data_out_i : signal is true;--
- attribute syn_preserve of sci_read_i : signal is true;--
- attribute syn_keep of sci_read_i : signal is true;--
- attribute syn_preserve of sci_write_i : signal is true;--
- attribute syn_keep of sci_write_i : signal is true;--
- attribute syn_preserve of sci_write_shift_i : signal is true;--
- attribute syn_keep of sci_write_shift_i : signal is true;--
- attribute syn_preserve of sci_read_shift_i : signal is true;--
- attribute syn_keep of sci_read_shift_i : signal is true;--
- attribute syn_preserve of wa_position : signal is true;--
- attribute syn_keep of wa_position : signal is true;--
- attribute syn_preserve of wa_position_rx : signal is true;--
- attribute syn_keep of wa_position_rx : signal is true;--
-
-begin
-
-clk_200_osc <= OSCCLK;
-
-SYNC_RX_HALF_CLK_OUT <= sync_rx_half_clk;
-SYNC_RX_FULL_CLK_OUT <= sync_rx_full_clk;
-SYNC_TX_HALF_CLK_OUT <= sync_tx_half_clk;
-SYNC_TX_FULL_CLK_OUT <= sync_tx_full_clk;
---RX_CDR_LOL_OUT <= rx_cdr_lol;
-
-clk_sys <= SYSCLK;
-clk_tx <= SYSCLK;
-clk_rx <= ff_rxhalfclk;
-clk_rxref <= OSCCLK;
-clk_txref <= OSCCLK;
-
---sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!
-
---------------------------------------------------------------------------
--- Internal Lane Resets
---------------------------------------------------------------------------
- PROC_RESET : process(clk_sys)
- begin
- if rising_edge(clk_sys) then
- reset_i <= RESET;
- send_reset_in <= ctrl_op(15);
- pwr_up <= '1'; --not CTRL_OP(i*16+14);
- end if;
- end process;
-
---------------------------------------------------------------------------
--- Synchronizer stages
---------------------------------------------------------------------------
-
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
-THE_SFP_STATUS_SYNC: signal_sync
- generic map(
- DEPTH => 3,
- WIDTH => 2
- )
- port map(
- RESET => '0',
- D_IN(0) => sync_prsnt_n_in,
- D_IN(1) => sync_los_in,
- CLK0 => clk_sys,
- CLK1 => clk_sys,
- D_OUT(0) => sfp_prsnt_n,
- D_OUT(1) => sfp_los
- );
-
-
-THE_RX_K_SYNC: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 4
- )
- port map(
- RESET => reset_i,
- D_IN(1 downto 0) => comb_rx_k,
- D_IN(2) => send_reset_words,
- D_IN(3) => make_trbnet_reset,
- CLK0 => clk_rx, -- CHANGED
- CLK1 => clk_sys,
- D_OUT(1 downto 0) => rx_k_q,
- D_OUT(2) => send_reset_words_q,
- D_OUT(3) => make_trbnet_reset_q
- );
-
-THE_RX_DATA_DELAY: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 16
- )
- port map(
- RESET => reset_i,
- D_IN => comb_rx_data,
- CLK0 => clk_rx,
- CLK1 => clk_rx,
- D_OUT => rx_data
- );
-
-THE_RX_K_DELAY: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 2
- )
- port map(
- RESET => reset_i,
- D_IN => comb_rx_k,
- CLK0 => clk_rx,
- CLK1 => clk_rx,
- D_OUT => rx_k
- );
-
-THE_RX_RESET: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 1
- )
- port map(
- RESET => '0',
- D_IN(0) => reset_i,
- CLK0 => clk_rx,
- CLK1 => clk_rx,
- D_OUT(0) => reset_i_rx
- );
-
--- Delay for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 2
- )
- port map(
- RESET => reset_i,
- D_IN(0) => rx_allow,
- D_IN(1) => tx_allow,
- CLK0 => clk_sys,
- CLK1 => clk_sys,
- D_OUT(0) => rx_allow_q,
- D_OUT(1) => tx_allow_q
- );
-
-THE_TX_SYNC: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 2
- )
- port map(
- RESET => '0',
- D_IN(0) => send_reset_in,
- D_IN(1) => tx_allow,
- CLK0 => clk_tx,
- CLK1 => clk_tx,
- D_OUT(0) => send_reset_in_qtx,
- D_OUT(1) => tx_allow_qtx
- );
-
---THE_DLM_IN_DELAY: signal_sync
--- generic map(
--- DEPTH => 1,
--- WIDTH => 1
--- )
--- port map(
--- RESET => '0',
--- D_IN(0) => SYNC_DLM_IN,
--- CLK0 => sync_rx_full_clk,
--- CLK1 => sync_rx_full_clk,
--- D_OUT(0) => sync_dlm_in_S
--- );
---------------------------------------------------------------------------
--- Main control state machine, startup control for SFP
---------------------------------------------------------------------------
-
-THE_SFP_LSM: trb_net16_lsm_sfp
- generic map (
- HIGHSPEED_STARTUP => c_YES
- )
- port map(
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear,
- SFP_MISSING_IN => sfp_prsnt_n,
- SFP_LOS_IN => sfp_los,
- SD_LINK_OK_IN => link_ok(0),
- SD_LOS_IN => link_error(8),
- SD_TXCLK_BAD_IN => link_error(5),
- SD_RXCLK_BAD_IN => link_error(4),
- SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
- SD_ALIGNMENT_IN => rx_k_q,
- SD_CV_IN => link_error(7 downto 6),
- FULL_RESET_OUT => quad_rst,
- LANE_RESET_OUT => lane_rst,
- TX_ALLOW_OUT => tx_allow,
- RX_ALLOW_OUT => rx_allow,
- SWAP_BYTES_OUT => swap_bytes,
- STAT_OP => buf_stat_op,
- CTRL_OP => ctrl_op,
- STAT_DEBUG => buf_stat_debug
- );
-
-SYNC_TXDIS_OUT <= quad_rst or reset_i;
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
-ffc_quad_rst <= quad_rst;
-ffc_lane_tx_rst <= lane_rst;
-
-
-ffc_lane_rx_rst <= lane_rst;
-
-
-
--- Instantiation of serdes module
-
- THE_SERDES: sfp_2_200_int
- port map(
- HDINP_CH1 => CU_RXD_P_IN,
- HDINN_CH1 => CU_RXD_N_IN,
- HDOUTP_CH1 => CU_TXD_P_OUT,
- HDOUTN_CH1 => CU_TXD_N_OUT,
- SCI_SEL_CH1 => sci_ch_i(1),
- RXICLK_CH1 => clk_rx,
- TXICLK_CH1 => clk_tx,
- RX_FULL_CLK_CH1 => ff_rxfullclk,
- RX_HALF_CLK_CH1 => ff_rxhalfclk,
- TX_FULL_CLK_CH1 => open,
- TX_HALF_CLK_CH1 => ff_txhalfclk,
- FPGA_RXREFCLK_CH1 => clk_rxref,
- TXDATA_CH1 => tx_data,
- TX_K_CH1 => tx_k,
- TX_FORCE_DISP_CH1 => tx_correct,
- TX_DISP_SEL_CH1 => "00",
- RXDATA_CH1 => comb_rx_data,
- RX_K_CH1 => comb_rx_k,
- RX_DISP_ERR_CH1 => open,
- RX_CV_ERR_CH1 => link_error(7 downto 6),
- RX_SERDES_RST_CH1_C => trb_rx_serdes_rst,
- SB_FELB_CH1_C => '0', --loopback enable
- SB_FELB_RST_CH1_C => '0', --loopback reset
- TX_PCS_RST_CH1_C => trb_tx_pcs_rst, --'1', --tx power up
- TX_PWRUP_CH1_C => '1', --tx power up
- RX_PCS_RST_CH1_C => trb_rx_pcs_rst, --'1', --rx power up
- RX_PWRUP_CH1_C => '1', --rx power up
- RX_LOS_LOW_CH1_S => trb_rx_los_low, --link_error(8),
- LSM_STATUS_CH1_S => link_ok(0),
- RX_CDR_LOL_CH1_S => trb_rx_cdr_lol, --link_error(4),
- TX_DIV2_MODE_CH1_C => '0', --full rate
- RX_DIV2_MODE_CH1_C => '0', --full rate
-
- HDINP_CH3 => SYNC_RXD_P_IN,
- HDINN_CH3 => SYNC_RXD_N_IN,
- HDOUTP_CH3 => SYNC_TXD_P_OUT,
- HDOUTN_CH3 => SYNC_TXD_N_OUT,
- SCI_SEL_CH3 => sci_ch_i(3),
- TXICLK_CH3 => sync_rx_full_clk,
- RX_FULL_CLK_CH3 => sync_rx_full_clk,
- RX_HALF_CLK_CH3 => sync_rx_half_clk,
- TX_FULL_CLK_CH3 => sync_tx_full_clk,
- TX_HALF_CLK_CH3 => sync_tx_half_clk,
- FPGA_RXREFCLK_CH3 => clk_200_osc,
- TXDATA_CH3 => sync_tx_data,
- TX_K_CH3 => sync_tx_k,
- TX_FORCE_DISP_CH3 => '0',
- TX_DISP_SEL_CH3 => '0',
- RXDATA_CH3 => sync_rx_data,
- RX_K_CH3 => sync_rx_k,
- RX_DISP_ERR_CH3 => open,
- RX_CV_ERR_CH3 => sync_rx_error,
- RX_SERDES_RST_CH3_C => sync_rx_serdes_rst,
- SB_FELB_CH3_C => '0', --loopback enable
- SB_FELB_RST_CH3_C => '0', --loopback reset
- TX_PCS_RST_CH3_C => sync_tx_pcs_rst,
- TX_PWRUP_CH3_C => '1',
- RX_PCS_RST_CH3_C => sync_rx_pcs_rst,
- RX_PWRUP_CH3_C => '1',
- RX_LOS_LOW_CH3_S => sync_rx_los_low,
- LSM_STATUS_CH3_S => sync_lsm_status,
- RX_CDR_LOL_CH3_S => sync_rx_cdr_lol,
- TX_DIV2_MODE_CH3_C => '0',
- RX_DIV2_MODE_CH3_C => '0',
-
- SCI_WRDATA => sci_data_in_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_RDDATA => sci_data_out_i,
- SCI_SEL_QUAD => sci_addr_i(8),
- SCI_RD => sci_read_i,
- SCI_WRN => sci_write_i,
- FPGA_TXREFCLK => clk_txref,
--- FPGA_TXREFCLK => rx_full_clk,
- TX_SERDES_RST_C => CLEAR,
- TX_PLL_LOL_QD_S => link_error(5),
- TX_SYNC_QD_C => '0',
- RST_QD_C => rst_qd,
- REFCLK2FPGA => open,
- SERDES_RST_QD_C => ffc_quad_rst
- );
-
--------------------------------------------------------------------------
--- RX Fifo & Data output
--------------------------------------------------------------------------
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
-generic map(
- USE_STATUS_FLAGS => c_NO
- )
-port map( read_clock_in => clk_sys,
- write_clock_in => clk_rx, -- CHANGED
- read_enable_in => fifo_rx_rd_en,
- write_enable_in => fifo_rx_wr_en,
- fifo_gsr_in => fifo_rx_reset,
- write_data_in => fifo_rx_din,
- read_data_out => fifo_rx_dout,
- full_out => fifo_rx_full,
- empty_out => fifo_rx_empty
- );
-
-fifo_rx_reset <= reset_i or not rx_allow_q;
-fifo_rx_rd_en <= not fifo_rx_empty;
-
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process
- begin
- wait until rising_edge(clk_rx); --CHANGED
- last_rx <= rx_k(1) & rx_data(15 downto 8);
- if( swap_bytes = '0' ) then
- fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
- fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
- else
- fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
- fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
- end if;
- end process THE_BYTE_SWAP_PROC;
-
-buf_med_data_out <= fifo_rx_dout(15 downto 0);
-buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
-buf_med_packet_num_out <= rx_counter;
-med_read_out <= tx_allow_q and not fifo_tx_almost_full;
-
-
-THE_CNT_RESET_PROC : process
- begin
- wait until rising_edge(clk_rx); --CHANGED
- if reset_i_rx = '1' then
- send_reset_words <= '0';
- make_trbnet_reset <= '0';
- reset_word_cnt <= (others => '0');
- else
- send_reset_words <= '0';
- make_trbnet_reset <= '0';
- if fifo_rx_din = "11" & x"FEFE" then
- if reset_word_cnt(4) = '0' then
- reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
- else
- send_reset_words <= '1';
- end if;
- else
- reset_word_cnt <= (others => '0');
- make_trbnet_reset <= reset_word_cnt(4);
- end if;
- end if;
- end process;
-
-
-THE_SYNC_PROC: process
- begin
- wait until rising_edge(clk_sys);
- med_dataready_out <= buf_med_dataready_out;
- med_data_out <= buf_med_data_out;
- med_packet_num_out <= buf_med_packet_num_out;
- if reset_i = '1' then
- med_dataready_out <= '0';
- end if;
- end process;
-
-
---rx packet counter
----------------------
-THE_RX_PACKETS_PROC: process( clk_sys )
- begin
- if( rising_edge(clk_sys) ) then
- last_fifo_rx_empty <= fifo_rx_empty;
- if reset_i = '1' or rx_allow_q = '0' then
- rx_counter <= c_H0;
- else
- if( buf_med_dataready_out = '1' ) then
- if( rx_counter = c_max_word_number ) then
- rx_counter <= (others => '0');
- else
- rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
- end if;
- end if;
- end if;
- end if;
- end process;
-
---TX Fifo & Data output to Serdes
----------------------
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map( read_clock_in => clk_tx,
- write_clock_in => clk_sys,
- read_enable_in => fifo_tx_rd_en,
- write_enable_in => fifo_tx_wr_en,
- fifo_gsr_in => fifo_tx_reset,
- write_data_in => fifo_tx_din,
- read_data_out => fifo_tx_dout,
- full_out => fifo_tx_full,
- empty_out => fifo_tx_empty,
- almost_full_out => fifo_tx_almost_full
- );
-
-fifo_tx_reset <= reset_i or not tx_allow_q;
-fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
-fifo_tx_rd_en <= tx_allow_qtx;
-
-
-THE_SERDES_INPUT_PROC: process( clk_tx )
- begin
- if( rising_edge(clk_tx) ) then
- last_fifo_tx_empty <= fifo_tx_empty;
- first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
- if send_reset_in = '1' then
- tx_data <= x"FEFE";
- tx_k <= "11";
- elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
- tx_data <= x"50bc";
- tx_k <= "01";
- tx_correct <= first_idle & '0';
- else
- tx_data <= fifo_tx_dout(15 downto 0);
- tx_k <= "00";
- tx_correct <= "00";
- end if;
- end if;
- end process THE_SERDES_INPUT_PROC;
-
-
--- map 8-bit dlm on 18-bit fifo
-syncfifo_din(7 downto 0) <= SYNC_DLM_WORD_IN;
-syncfifo_din(17 downto 8) <= (others => '0');
---SYNC_DLM_word_S <= syncfifo_dout(7 downto 0);
-
-SYNC_DLM_tx: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map(
- read_clock_in => sync_tx_full_clk,
- write_clock_in => sync_rx_full_clk,
- read_enable_in => dlm_fifo_rd_en,
- write_enable_in => SYNC_DLM_IN, --sync_dlm_in_S,
- fifo_gsr_in => reset,
- write_data_in => syncfifo_din,
- read_data_out => syncfifo_dout,
- full_out => open,
- empty_out => dlm_fifo_empty
- );
-
-sync_rx_proc : process(sync_rx_full_clk)
-begin
- if rising_edge(sync_rx_full_clk) then
- SYNC_DLM_OUT <= '0';
- if dlm_received_S='1' then
- dlm_received_S <= '0';
- SYNC_DLM_OUT <= '1';
- SYNC_DLM_WORD_OUT <= sync_rx_data;
- elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
- dlm_received_S <= '1';
- end if;
- end if;
-end process;
-
-sync_tx_fsm : process(sync_tx_full_clk)
-begin
- if rising_edge(sync_tx_full_clk) then\r
- case sync_tx_proc_state is\r
- when cSEND_IDLE =>
- if (dlm_fifo_empty='1') then
- sync_tx_proc_state <= cSEND_IDLE;
- dlm_fifo_rd_en <= '0';
- sync_tx_data <= x"BC"; -- idle
- sync_tx_k <= '1';\r
- else\r
- sync_tx_proc_state <= cFIFO_READ;
- dlm_fifo_rd_en <= '1';
- sync_tx_data <= x"BC"; -- dlm
- sync_tx_k <= '1';
- end if;
- when cFIFO_READ =>
- sync_tx_proc_state <= cSEND_DLM;
- dlm_fifo_rd_en <= '0';
- sync_tx_data <= x"DC"; -- dlm
- sync_tx_k <= '1';
- when cSEND_DLM =>
- sync_tx_proc_state <= cSEND_IDLE;
- dlm_fifo_rd_en <= '0';
- sync_tx_data <= syncfifo_dout(7 downto 0);
- sync_tx_k <= '0';
- when others =>\r
- sync_tx_proc_state <= cSEND_IDLE;
- dlm_fifo_rd_en <= '0';
- sync_tx_data <= x"BC"; -- idle
- sync_tx_k <= '1';
- end case;\r
- end if;\r
-end process;\r
- \r
- \r
---sync_tx_proc : process(sync_tx_full_clk)
---begin
- --if rising_edge(sync_tx_full_clk) then
- --if dlm_fifo_rd_en='1' then
- --dlm_fifo_rd_en <= '0';
- --sync_tx_data <= syncfifo_dout(7 downto 0);
- --sync_tx_k <= '0';
- --elsif (dlm_fifo_empty='0') and (dlm_fifo_reading='1') then
- --dlm_fifo_rd_en <= '1';
- --sync_tx_data <= x"DC";
- --sync_tx_k <= '1';
- --elsif dlm_fifo_empty='0' then
- --dlm_fifo_reading <= '1';
- --dlm_fifo_rd_en <= '0';
- --sync_tx_data <= x"BC"; -- idle
- --sync_tx_k <= '1';
- --else
- --dlm_fifo_reading <= '0';
- --dlm_fifo_rd_en <= '0';
- --sync_tx_data <= x"BC"; -- idle
- --sync_tx_k <= '1';
- --end if;
- --end if;
---end process;
-\r
-link_error(8) <= trb_rx_los_low; -- loss of signal
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock
-
-reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';
-
--------------------------------------------------
--- Reset FSM & Link states
--------------------------------------------------
-THE_RX_FSM1: rx_reset_fsm
- port map(
- RST_N => reset_n,
- RX_REFCLK => OSCCLK,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RX_SERDES_RST_CH_C => trb_rx_serdes_rst,
- RX_CDR_LOL_CH_S => trb_rx_cdr_lol,
- RX_LOS_LOW_CH_S => trb_rx_los_low,
- RX_PCS_RST_CH_C => trb_rx_pcs_rst,
- WA_POSITION => "0000",
- STATE_OUT => trb_rx_fsm_state
- );
-
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';
-\r
-THE_TX_FSM1: tx_reset_fsm
- port map(
- RST_N => reset_n,
- TX_REFCLK => OSCCLK,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RST_QD_C => rst_qd1,
- TX_PCS_RST_CH_C => trb_tx_pcs_rst,
- STATE_OUT => trb_tx_fsm_state --open
- );
-
-THE_RX_FSM3: rx_reset_fsm
- port map(
- RST_N => reset_n,
- RX_REFCLK => sync_rx_full_clk,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RX_SERDES_RST_CH_C => sync_rx_serdes_rst,
- RX_CDR_LOL_CH_S => sync_rx_cdr_lol,
- RX_LOS_LOW_CH_S => sync_rx_los_low,
- RX_PCS_RST_CH_C => sync_rx_pcs_rst,
- WA_POSITION => sync_wa_position_rx(11 downto 8),
- STATE_OUT => sync_rx_fsm_state
- );\r
-\r
-SYNC_WA_POSITION : process(sync_rx_full_clk) --??CLK)
-begin
- if rising_edge(sync_rx_full_clk) then
- sync_wa_position_rx <= wa_position;
- end if;
-end process;
-
-THE_TX_FSM3 : tx_reset_fsm
- port map(
- RST_N => reset_n,
- TX_REFCLK => OSCCLK,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RST_QD_C => rst_qd3,
- TX_PCS_RST_CH_C => sync_tx_pcs_rst,
- STATE_OUT => sync_tx_fsm_state
- );
-\r
---rst_qd <= '1' when (rst_qd1='1') or (rst_qd3='1') else '0';
-rst_qd <= RESET;
-\r
-TX_READY_CH3 <= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';
-\r
------------------------------------------------------------------------------------------------------
--- SCI --gives access to serdes config port from slow control and reads word alignment every ~ 40 us
------------------------------------------------------------------------------------------------------
-PROC_SCI_CTRL: process(clk_sys)
- variable cnt : integer range 0 to 4 := 0;
-begin
- if( rising_edge(clk_sys) ) then
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer <= sci_timer + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- elsif sci_timer(sci_timer'left) = '1' then
- sci_timer <= (others => '0');
- sci_state <= GET_WA;
- end if;
- when SCTRL =>
- if sci_reg_i = '1' then
- --// SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_DATA_OUT <= (others => '0');
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
- when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
- when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
- when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
- when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
- when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
- when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
- when GET_WA_FINISH =>
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
- end case;
-
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
- else
- SCI_NACK <= '0';
- end if;
- end if;
-end process PROC_SCI_CTRL;
-
-----------------------
---Generate LED signals
-----------------------
-LED_PROC : process( clk_sys )
- begin
- if rising_edge(clk_sys) then
- led_counter <= led_counter + to_unsigned(1,1);
- if buf_med_dataready_out = '1' then
- rx_led <= '1';
- elsif led_counter = 0 then
- rx_led <= '0';
- end if;
- if tx_k(0) = '0' then
- tx_led <= '1';
- elsif led_counter = 0 then
- tx_led <= '0';
- end if;
- end if;
- end process LED_PROC;
-
-
-stat_op(15) <= send_reset_words_q;
-stat_op(14) <= buf_stat_op(14);
-stat_op(13) <= make_trbnet_reset_q;
-stat_op(12) <= '0';
-stat_op(11) <= tx_led; --tx led
-stat_op(10) <= rx_led; --rx led
-stat_op(9 downto 0) <= buf_stat_op(9 downto 0);
-
--- Debug output
-stat_debug(15 downto 0) <= rx_data;
-stat_debug(17 downto 16) <= rx_k;
-stat_debug(19 downto 18) <= (others => '0');
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
-stat_debug(24) <= fifo_rx_rd_en;
-stat_debug(25) <= fifo_rx_wr_en;
-stat_debug(26) <= fifo_rx_reset;
-stat_debug(27) <= fifo_rx_empty;
-stat_debug(28) <= fifo_rx_full;
-stat_debug(29) <= last_rx(8);
-stat_debug(30) <= rx_allow_q;
-stat_debug(41 downto 31) <= (others => '0');
-stat_debug(42) <= clk_sys;
-stat_debug(43) <= clk_sys;
-stat_debug(59 downto 44) <= (others => '0');
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
-
-
-end Cu_trb_net16_soda_sync_ecp3_sfp_arch;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
--- use work.trb_net_std.all;
--- use work.trb_net_components.all;
--- use work.trb_net16_hub_func.all;
--- use work.trb3_components.all;
--- use work.med_sync_define.all;
--- use work.version.all;
-use work.soda_components.all;
-
-
-entity TB_soda_chain is
-end entity;
-
-architecture TestBench of TB_soda_chain is
-
- -- Clock period definitions
- constant sysclk_period: time:= 10ns;
- constant sodaclk_period: time:= 5ns;
-
-
---Inputs
- signal rst_S : std_logic;
- signal sys_clk_S : std_logic;
- signal soda_clk_S : std_logic;
- signal enable_S : std_logic := '0';
- signal SOB_S : std_logic := '0';
- signal src_dnstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
- signal src_dnstream_dlm_valid_S : std_logic;
- signal src_upstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
- signal src_upstream_dlm_valid_S : std_logic;
-
- signal hub_dnstream_dlm_word_S : t_HUB_WORD;
- signal hub_dnstream_dlm_valid_S : t_HUB_BIT;
- signal hub_upstream_dlm_word_S : t_HUB_WORD;
- signal hub_upstream_dlm_valid_S : t_HUB_BIT;
-
- --SODA
- signal soda_ack : std_logic;
- signal soda_write : std_logic := '0';
- signal soda_read : std_logic := '0';
- signal soda_data_in : std_logic_vector(31 downto 0) := (others => '0');
- signal soda_src_data_out : std_logic_vector(31 downto 0);
- signal soda_hub_data_out : std_logic_vector(31 downto 0);
- signal soda_clt_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0) := (others => '0');
- signal soda_leds : std_logic_vector(3 downto 0);
-begin
-
- THE_SOB_SOURCE : soda_start_of_burst_faker
- port map(
- SYSCLK => sys_clk_S,
- RESET => rst_S,
- SODA_BURST_PULSE_OUT => SOB_S
- );
-
-
- THE_SODA_SOURCE : soda_source
- port map(
- SYSCLK => sys_clk_S,
- SODACLK => soda_clk_S,
- RESET => rst_S,
- CLEAR => '0',
- CLK_EN => '1',
- --Internal Connection
- SODA_BURST_PULSE_IN => SOB_S,
- RX_DLM_WORD_IN => src_upstream_dlm_word_S,
- RX_DLM_IN => src_upstream_dlm_valid_S,
- TX_DLM_OUT => src_dnstream_dlm_valid_S,
- TX_DLM_WORD_OUT => src_dnstream_dlm_word_S,
-
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_src_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds
- );
-
- A_SODA_HUB : soda_hub
- port map(
- SYSCLK => sys_clk_S,
- SODACLK => soda_clk_S,
- RESET => rst_S,
- CLEAR => '0',
- CLK_EN => '1',
- --Internal Connection
- RXTOP_DLM_WORD_IN => src_dnstream_dlm_word_S,
- RXTOP_DLM_IN => src_dnstream_dlm_valid_S,
- TXTOP_DLM_OUT => src_upstream_dlm_valid_S,
- TXTOP_DLM_WORD_OUT => src_upstream_dlm_word_S,
-
- RXBTM_DLM_WORD_IN => hub_upstream_dlm_word_S,
- RXBTM_DLM_IN => hub_upstream_dlm_valid_S,
- TXBTM_DLM_OUT => hub_dnstream_dlm_valid_S,
- TXBTM_DLM_WORD_OUT => hub_dnstream_dlm_word_S,
-
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_hub_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- STAT => open
- );
-
- channel : for i in c_HUB_CHILDREN-1 downto 0 generate
-
- A_SODA_CLIENT : soda_client
- port map(
- SYSCLK => sys_clk_S,
- SODACLK => soda_clk_S,
- RESET => rst_S,
- CLEAR => '0',
- CLK_EN => '1',
- --Internal Connection
- RX_DLM_WORD_IN => hub_dnstream_dlm_word_S(i),
- RX_DLM_IN => hub_dnstream_dlm_valid_S(i),
- TX_DLM_OUT => hub_upstream_dlm_valid_S(i),
- TX_DLM_WORD_OUT => hub_upstream_dlm_word_S(i),
-
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_clt_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => open,
- LINK_DEBUG_IN => (others => '0')
- );
-
- end generate;
-
-
-------------------------------------------------------------------------------------------------------------
- -- SODA command packet
-------------------------------------------------------------------------------------------------------------
- cmd_proc :process
- begin
- wait for 2us;
- soda_addr <= "0000";
- soda_data_in <= x"08000000"; -- soda_reset
- soda_write <= '1';
- wait for sysclk_period;
- soda_write <= '0';
- wait for sysclk_period;
- soda_addr <= "0000";
- soda_data_in <= x"00000000"; -- soda_reset
- soda_write <= '1';
- wait for sysclk_period;
- soda_write <= '0';
-------------------------------------------------------------------------------------------------------------
- wait for 2us;
- soda_addr <= "0100";
- soda_data_in <= x"FFFFFFFD"; --
- soda_write <= '1';
- wait for sysclk_period;
- soda_write <= '0';
-------------------------------------------------------------------------------------------------------------
- wait for 700us;
- soda_addr <= "0000";
- soda_data_in <= x"40000000"; -- time_calibration
- soda_write <= '1';
- wait for sysclk_period;
- soda_write <= '0';
-------------------------------------------------------------------------------------------------------------
- wait for 700us;
- soda_addr <= "0100";
- soda_data_in <= x"FFFFFFFE"; -- time_calibration
- soda_write <= '1';
- wait for sysclk_period;
- soda_write <= '0';
-------------------------------------------------------------------------------------------------------------
- wait for 100us;
- soda_addr <= "1001";
- soda_read <= '1';
- wait for sysclk_period;
- soda_read <= '0';
- end process;
-
-------------------------------------------------------------------------------------------------------------
- -- Clock process definitions
-------------------------------------------------------------------------------------------------------------
- sysclk_proc :process
- begin
- sys_clk_S <= '0';
- wait for sysclk_period/2;
- sys_clk_S <= '1';
- wait for sysclk_period/2;
- end process;
-
- sodaclk_proc :process
- begin
- soda_clk_S <= '0';
- wait for sodaclk_period/2;
- soda_clk_S <= '1';
- wait for sodaclk_period/2;
- end process;
-
-
-------------------------------------------------------------------------------------------------------------
--- reset process
-------------------------------------------------------------------------------------------------------------
- reset_proc: process
- begin
- rst_S <= '1';
- wait for sysclk_period * 5;
- rst_S <= '0';
- wait;
- end process;
-
-end TestBench;
-
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
--- use work.trb_net_std.all;
--- use work.trb_net_components.all;
--- use work.trb_net16_hub_func.all;
--- use work.trb3_components.all;
--- use work.med_sync_define.all;
--- use work.version.all;
-use work.soda_components.all;
-
-
-entity TB_soda_source_child is
-end entity;
-\r
-architecture TestBench of TB_soda_source_child is\r
-\r
- -- Clock period definitions
- constant clk_period: time:= 4ns;
-\r
-\r
---Inputs
- signal rst_S : std_logic;
- signal clk_S : std_logic;
- signal enable_S : std_logic := '0';
- signal SOB_S : std_logic := '0';
- signal src_dnstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');\r
- signal src_dnstream_dlm_valid_S : std_logic;\r
- signal src_upstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');\r
- signal src_upstream_dlm_valid_S : std_logic;\r
-
- --SODA
- signal soda_ack : std_logic;
- signal soda_write : std_logic := '0';
- signal soda_read : std_logic := '0';
- signal soda_data_in : std_logic_vector(31 downto 0) := (others => '0');
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0) := (others => '0');
- signal soda_leds : std_logic_vector(3 downto 0);\r
-begin\r
-\r
- THE_SODA_SOURCE : soda_source
- port map(
- SYSCLK => clk_S,
- RESET => rst_S,
- CLEAR => '0',
- CLK_EN => '1',
- --Internal Connection
- SODA_BURST_PULSE_IN => SOB_S,
- RX_DLM_WORD_IN => src_upstream_dlm_word_S,
- RX_DLM_IN => src_upstream_dlm_valid_S,
- TX_DLM_OUT => src_dnstream_dlm_valid_S,
- TX_DLM_WORD_OUT => src_dnstream_dlm_word_S,
-
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,\r
- LEDS_OUT => soda_leds,
- TEST_LINE => open,\r
- STAT => open
- );
-
-
- A_SODA_CLIENT : soda_client
- port map(
- SYSCLK => clk_S,
- RESET => rst_S,
- CLEAR => '0',
- CLK_EN => '1',
- --Internal Connection
- RX_DLM_WORD_IN => src_dnstream_dlm_word_S,
- RX_DLM_IN => src_dnstream_dlm_valid_S,
- TX_DLM_OUT => src_upstream_dlm_valid_S,
- TX_DLM_WORD_OUT => src_upstream_dlm_word_S,
-
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,\r
- STAT => open
- );
-
-------------------------------------------------------------------------------------------------------------
- -- SODA command packet
-------------------------------------------------------------------------------------------------------------
- cmd_proc :process
- begin
-wait for 2us;
- soda_addr <= "0000";
- soda_data_in <= x"08000000"; -- soda_reset
- soda_write <= '1';
-wait for clk_period;
- soda_write <= '0';
-wait for 700us;
- soda_data_in <= x"40000000"; -- time_calibration
- soda_write <= '1';
-wait for clk_period;
- soda_write <= '0';
-
- end process;
-
-------------------------------------------------------------------------------------------------------------
- -- Clock process definitions
-------------------------------------------------------------------------------------------------------------
-clk_proc :process
- begin
- clk_S <= '0';
- wait for clk_period/2;
- clk_S <= '1';
- wait for clk_period/2;
- end process;
-
--- reset process
-reset_proc: process
- begin
- rst_S <= '1';
- wait for clk_period * 5;
- rst_S <= '0';
- wait;
- end process;
-\r
-burst_proc :process
- begin
- SOB_S <= '0';
- wait for 2.35us;
- SOB_S <= '1';
- wait for 50ns;
- end process;
-
-\r
-end TestBench;\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_4_sync_downstream" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 19 11:41:24.218" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_4_sync_downstream.lpc" type="lpc" modified="2015 02 19 11:41:22.000"/>
- <File name="serdes_4_sync_downstream.pp" type="pp" modified="2015 02 19 11:41:22.000"/>
- <File name="serdes_4_sync_downstream.sym" type="sym" modified="2015 02 19 11:41:22.000"/>
- <File name="serdes_4_sync_downstream.tft" type="tft" modified="2015 02 19 11:41:22.000"/>
- <File name="serdes_4_sync_downstream.txt" type="pcs_module" modified="2015 02 19 11:41:22.000"/>
- <File name="serdes_4_sync_downstream.vhd" type="top_level_vhdl" modified="2015 02 19 11:41:22.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_4_sync_hub_downstream" module="serdes_4_sync_hub_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 08 13:39:53.561" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_4_sync_hub_downstream.lpc" type="lpc" modified="2014 05 08 13:39:51.000"/>
- <File name="serdes_4_sync_hub_downstream.pp" type="pp" modified="2014 05 08 13:39:51.000"/>
- <File name="serdes_4_sync_hub_downstream.sym" type="sym" modified="2014 05 08 13:39:51.000"/>
- <File name="serdes_4_sync_hub_downstream.tft" type="tft" modified="2014 05 08 13:39:51.000"/>
- <File name="serdes_4_sync_hub_downstream.txt" type="pcs_module" modified="2014 05 08 13:39:51.000"/>
- <File name="serdes_4_sync_hub_downstream.vhd" type="top_level_vhdl" modified="2014 05 08 13:39:51.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_4_sync_hub_downstream
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=05/08/2014
-Time=13:39:51
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=RXTX
-_mode1=RXTX
-_mode2=RXTX
-_mode3=RXTX
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=G8B10B
-_tx_protocol1=G8B10B
-_tx_protocol2=G8B10B
-_tx_protocol3=G8B10B
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=DISABLED
-_tx_fifo1=DISABLED
-_tx_fifo2=DISABLED
-_tx_fifo3=DISABLED
-_tx_ficlk_rate0=200
-_tx_ficlk_rate1=200
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=INTERNAL
-_pll_rxsrc2=INTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2
-_rx_datarange2=2
-_rx_datarange3=2
-_rx_protocol0=G8B10B
-_rx_protocol1=G8B10B
-_rx_protocol2=G8B10B
-_rx_protocol3=G8B10B
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=200
-_rxrefclk_rate1=200
-_rxrefclk_rate2=200
-_rxrefclk_rate3=200
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=DISABLED
-_rx_fifo1=DISABLED
-_rx_fifo2=DISABLED
-_rx_fifo3=DISABLED
-_rx_ficlk_rate0=200
-_rx_ficlk_rate1=200
-_rx_ficlk_rate2=200
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=DC
-_rx_dcc2=DC
-_rx_dcc3=DC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=00
-_k01=00
-_k02=00
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00011100
-_byten02=00011100
-_byten03=00011100
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_4_sync_hub_downstream.pp=pp
-serdes_4_sync_hub_downstream.tft=tft
-serdes_4_sync_hub_downstream.txt=pcs_module
-serdes_4_sync_hub_downstream.sym=sym
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "serdes_4_sync_hub_downstream.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_CORE";
--- CH2_CDR_SRC : String := "REFCLK_CORE";
--- CH3_CDR_SRC : String := "REFCLK_CORE";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_4_sync_hub_downstream is
- GENERIC (USER_CONFIG_FILE : String := "serdes_4_sync_hub_downstream.txt");
- port (
-------------------
--- CH0 --
- hdinp_ch0, hdinn_ch0 : in std_logic;
- hdoutp_ch0, hdoutn_ch0 : out std_logic;
- sci_sel_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- txdata_ch0 : in std_logic_vector (7 downto 0);
- tx_k_ch0 : in std_logic;
- tx_force_disp_ch0 : in std_logic;
- tx_disp_sel_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- rx_serdes_rst_ch0_c : in std_logic;
- sb_felb_ch0_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- tx_pcs_rst_ch0_c : in std_logic;
- tx_pwrup_ch0_c : in std_logic;
- rx_pcs_rst_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
- tx_div2_mode_ch0_c : in std_logic;
- rx_div2_mode_ch0_c : in std_logic;
--- CH1 --
- hdinp_ch1, hdinn_ch1 : in std_logic;
- hdoutp_ch1, hdoutn_ch1 : out std_logic;
- sci_sel_ch1 : in std_logic;
- txiclk_ch1 : in std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- tx_full_clk_ch1 : out std_logic;
- tx_half_clk_ch1 : out std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- txdata_ch1 : in std_logic_vector (7 downto 0);
- tx_k_ch1 : in std_logic;
- tx_force_disp_ch1 : in std_logic;
- tx_disp_sel_ch1 : in std_logic;
- rxdata_ch1 : out std_logic_vector (7 downto 0);
- rx_k_ch1 : out std_logic;
- rx_disp_err_ch1 : out std_logic;
- rx_cv_err_ch1 : out std_logic;
- rx_serdes_rst_ch1_c : in std_logic;
- sb_felb_ch1_c : in std_logic;
- sb_felb_rst_ch1_c : in std_logic;
- tx_pcs_rst_ch1_c : in std_logic;
- tx_pwrup_ch1_c : in std_logic;
- rx_pcs_rst_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- rx_los_low_ch1_s : out std_logic;
- lsm_status_ch1_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- tx_div2_mode_ch1_c : in std_logic;
- rx_div2_mode_ch1_c : in std_logic;
--- CH2 --
- hdinp_ch2, hdinn_ch2 : in std_logic;
- hdoutp_ch2, hdoutn_ch2 : out std_logic;
- sci_sel_ch2 : in std_logic;
- txiclk_ch2 : in std_logic;
- rx_full_clk_ch2 : out std_logic;
- rx_half_clk_ch2 : out std_logic;
- tx_full_clk_ch2 : out std_logic;
- tx_half_clk_ch2 : out std_logic;
- fpga_rxrefclk_ch2 : in std_logic;
- txdata_ch2 : in std_logic_vector (7 downto 0);
- tx_k_ch2 : in std_logic;
- tx_force_disp_ch2 : in std_logic;
- tx_disp_sel_ch2 : in std_logic;
- rxdata_ch2 : out std_logic_vector (7 downto 0);
- rx_k_ch2 : out std_logic;
- rx_disp_err_ch2 : out std_logic;
- rx_cv_err_ch2 : out std_logic;
- rx_serdes_rst_ch2_c : in std_logic;
- sb_felb_ch2_c : in std_logic;
- sb_felb_rst_ch2_c : in std_logic;
- tx_pcs_rst_ch2_c : in std_logic;
- tx_pwrup_ch2_c : in std_logic;
- rx_pcs_rst_ch2_c : in std_logic;
- rx_pwrup_ch2_c : in std_logic;
- rx_los_low_ch2_s : out std_logic;
- lsm_status_ch2_s : out std_logic;
- rx_cdr_lol_ch2_s : out std_logic;
- tx_div2_mode_ch2_c : in std_logic;
- rx_div2_mode_ch2_c : in std_logic;
--- CH3 --
- hdinp_ch3, hdinn_ch3 : in std_logic;
- hdoutp_ch3, hdoutn_ch3 : out std_logic;
- sci_sel_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- txdata_ch3 : in std_logic_vector (7 downto 0);
- tx_k_ch3 : in std_logic;
- tx_force_disp_ch3 : in std_logic;
- tx_disp_sel_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- rx_serdes_rst_ch3_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
- tx_pcs_rst_ch3_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pcs_rst_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
- tx_div2_mode_ch3_c : in std_logic;
- rx_div2_mode_ch3_c : in std_logic;
----- Miscillaneous ports
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- tx_sync_qd_c : in std_logic;
- rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end serdes_4_sync_hub_downstream;
-
-
-architecture serdes_4_sync_hub_downstream_arch of serdes_4_sync_hub_downstream is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH0_CDR_SRC: string;
- attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH1_CDR_SRC: string;
- attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH2_CDR_SRC: string;
- attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH3_CDR_SRC: string;
- attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch0_sig : std_logic;
-signal tx_full_clk_ch1_sig : std_logic;
-signal tx_full_clk_ch2_sig : std_logic;
-signal tx_full_clk_ch3_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- refclk2fpga <= refclk2fpga_sig;
- rx_los_low_ch0_s <= rx_los_low_ch0_sig;
- rx_los_low_ch1_s <= rx_los_low_ch1_sig;
- rx_los_low_ch2_s <= rx_los_low_ch2_sig;
- rx_los_low_ch3_s <= rx_los_low_ch3_sig;
- rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
- rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
- rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
- rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
- tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
- tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
- tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH0_CDR_SRC => "REFCLK_CORE",
- CH1_CDR_SRC => "REFCLK_CORE",
- CH2_CDR_SRC => "REFCLK_CORE",
- CH3_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => hdoutp_ch0,
- HDOUTN0 => hdoutn_ch0,
- HDINP0 => hdinp_ch0,
- HDINN0 => hdinn_ch0,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => sci_sel_ch0,
- SCIENCH0 => fpsc_vhi,
- FF_RXI_CLK_0 => fpsc_vlo,
- FF_TXI_CLK_0 => txiclk_ch0,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => rx_full_clk_ch0,
- FF_RX_H_CLK_0 => rx_half_clk_ch0,
- FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
- FF_TX_H_CLK_0 => tx_half_clk_ch0,
- FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
- FF_TX_D_0_0 => txdata_ch0(0),
- FF_TX_D_0_1 => txdata_ch0(1),
- FF_TX_D_0_2 => txdata_ch0(2),
- FF_TX_D_0_3 => txdata_ch0(3),
- FF_TX_D_0_4 => txdata_ch0(4),
- FF_TX_D_0_5 => txdata_ch0(5),
- FF_TX_D_0_6 => txdata_ch0(6),
- FF_TX_D_0_7 => txdata_ch0(7),
- FF_TX_D_0_8 => tx_k_ch0,
- FF_TX_D_0_9 => tx_force_disp_ch0,
- FF_TX_D_0_10 => tx_disp_sel_ch0,
- FF_TX_D_0_11 => fpsc_vlo,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => rxdata_ch0(0),
- FF_RX_D_0_1 => rxdata_ch0(1),
- FF_RX_D_0_2 => rxdata_ch0(2),
- FF_RX_D_0_3 => rxdata_ch0(3),
- FF_RX_D_0_4 => rxdata_ch0(4),
- FF_RX_D_0_5 => rxdata_ch0(5),
- FF_RX_D_0_6 => rxdata_ch0(6),
- FF_RX_D_0_7 => rxdata_ch0(7),
- FF_RX_D_0_8 => rx_k_ch0,
- FF_RX_D_0_9 => rx_disp_err_ch0,
- FF_RX_D_0_10 => rx_cv_err_ch0,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => rx_serdes_rst_ch0_c,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
- FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
- FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
- FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
- FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
- FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
-
------ CH1 -----
- HDOUTP1 => hdoutp_ch1,
- HDOUTN1 => hdoutn_ch1,
- HDINP1 => hdinp_ch1,
- HDINN1 => hdinn_ch1,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => sci_sel_ch1,
- SCIENCH1 => fpsc_vhi,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => txiclk_ch1,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => rx_full_clk_ch1,
- FF_RX_H_CLK_1 => rx_half_clk_ch1,
- FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
- FF_TX_H_CLK_1 => tx_half_clk_ch1,
- FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
- FF_TX_D_1_0 => txdata_ch1(0),
- FF_TX_D_1_1 => txdata_ch1(1),
- FF_TX_D_1_2 => txdata_ch1(2),
- FF_TX_D_1_3 => txdata_ch1(3),
- FF_TX_D_1_4 => txdata_ch1(4),
- FF_TX_D_1_5 => txdata_ch1(5),
- FF_TX_D_1_6 => txdata_ch1(6),
- FF_TX_D_1_7 => txdata_ch1(7),
- FF_TX_D_1_8 => tx_k_ch1,
- FF_TX_D_1_9 => tx_force_disp_ch1,
- FF_TX_D_1_10 => tx_disp_sel_ch1,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => rxdata_ch1(0),
- FF_RX_D_1_1 => rxdata_ch1(1),
- FF_RX_D_1_2 => rxdata_ch1(2),
- FF_RX_D_1_3 => rxdata_ch1(3),
- FF_RX_D_1_4 => rxdata_ch1(4),
- FF_RX_D_1_5 => rxdata_ch1(5),
- FF_RX_D_1_6 => rxdata_ch1(6),
- FF_RX_D_1_7 => rxdata_ch1(7),
- FF_RX_D_1_8 => rx_k_ch1,
- FF_RX_D_1_9 => rx_disp_err_ch1,
- FF_RX_D_1_10 => rx_cv_err_ch1,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => rx_serdes_rst_ch1_c,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
- FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
- FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
- FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
- FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
- FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
-
------ CH2 -----
- HDOUTP2 => hdoutp_ch2,
- HDOUTN2 => hdoutn_ch2,
- HDINP2 => hdinp_ch2,
- HDINN2 => hdinn_ch2,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => sci_sel_ch2,
- SCIENCH2 => fpsc_vhi,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => txiclk_ch2,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => rx_full_clk_ch2,
- FF_RX_H_CLK_2 => rx_half_clk_ch2,
- FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
- FF_TX_H_CLK_2 => tx_half_clk_ch2,
- FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
- FF_TX_D_2_0 => txdata_ch2(0),
- FF_TX_D_2_1 => txdata_ch2(1),
- FF_TX_D_2_2 => txdata_ch2(2),
- FF_TX_D_2_3 => txdata_ch2(3),
- FF_TX_D_2_4 => txdata_ch2(4),
- FF_TX_D_2_5 => txdata_ch2(5),
- FF_TX_D_2_6 => txdata_ch2(6),
- FF_TX_D_2_7 => txdata_ch2(7),
- FF_TX_D_2_8 => tx_k_ch2,
- FF_TX_D_2_9 => tx_force_disp_ch2,
- FF_TX_D_2_10 => tx_disp_sel_ch2,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => rxdata_ch2(0),
- FF_RX_D_2_1 => rxdata_ch2(1),
- FF_RX_D_2_2 => rxdata_ch2(2),
- FF_RX_D_2_3 => rxdata_ch2(3),
- FF_RX_D_2_4 => rxdata_ch2(4),
- FF_RX_D_2_5 => rxdata_ch2(5),
- FF_RX_D_2_6 => rxdata_ch2(6),
- FF_RX_D_2_7 => rxdata_ch2(7),
- FF_RX_D_2_8 => rx_k_ch2,
- FF_RX_D_2_9 => rx_disp_err_ch2,
- FF_RX_D_2_10 => rx_cv_err_ch2,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => rx_serdes_rst_ch2_c,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
- FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
- FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
- FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
- FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
- FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
-
------ CH3 -----
- HDOUTP3 => hdoutp_ch3,
- HDOUTN3 => hdoutn_ch3,
- HDINP3 => hdinp_ch3,
- HDINN3 => hdinn_ch3,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => sci_sel_ch3,
- SCIENCH3 => fpsc_vhi,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => txiclk_ch3,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => rx_full_clk_ch3,
- FF_RX_H_CLK_3 => rx_half_clk_ch3,
- FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
- FF_TX_H_CLK_3 => tx_half_clk_ch3,
- FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
- FF_TX_D_3_0 => txdata_ch3(0),
- FF_TX_D_3_1 => txdata_ch3(1),
- FF_TX_D_3_2 => txdata_ch3(2),
- FF_TX_D_3_3 => txdata_ch3(3),
- FF_TX_D_3_4 => txdata_ch3(4),
- FF_TX_D_3_5 => txdata_ch3(5),
- FF_TX_D_3_6 => txdata_ch3(6),
- FF_TX_D_3_7 => txdata_ch3(7),
- FF_TX_D_3_8 => tx_k_ch3,
- FF_TX_D_3_9 => tx_force_disp_ch3,
- FF_TX_D_3_10 => tx_disp_sel_ch3,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => rxdata_ch3(0),
- FF_RX_D_3_1 => rxdata_ch3(1),
- FF_RX_D_3_2 => rxdata_ch3(2),
- FF_RX_D_3_3 => rxdata_ch3(3),
- FF_RX_D_3_4 => rxdata_ch3(4),
- FF_RX_D_3_5 => rxdata_ch3(5),
- FF_RX_D_3_6 => rxdata_ch3(6),
- FF_RX_D_3_7 => rxdata_ch3(7),
- FF_RX_D_3_8 => rx_k_ch3,
- FF_RX_D_3_9 => rx_disp_err_ch3,
- FF_RX_D_3_10 => rx_cv_err_ch3,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => rx_serdes_rst_ch3_c,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
- FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
- FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
- FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
- FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
- FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
-
------ Auxilliary ----
- SCIWDATA7 => sci_wrdata(7),
- SCIWDATA6 => sci_wrdata(6),
- SCIWDATA5 => sci_wrdata(5),
- SCIWDATA4 => sci_wrdata(4),
- SCIWDATA3 => sci_wrdata(3),
- SCIWDATA2 => sci_wrdata(2),
- SCIWDATA1 => sci_wrdata(1),
- SCIWDATA0 => sci_wrdata(0),
- SCIADDR5 => sci_addr(5),
- SCIADDR4 => sci_addr(4),
- SCIADDR3 => sci_addr(3),
- SCIADDR2 => sci_addr(2),
- SCIADDR1 => sci_addr(1),
- SCIADDR0 => sci_addr(0),
- SCIRDATA7 => sci_rddata(7),
- SCIRDATA6 => sci_rddata(6),
- SCIRDATA5 => sci_rddata(5),
- SCIRDATA4 => sci_rddata(4),
- SCIRDATA3 => sci_rddata(3),
- SCIRDATA2 => sci_rddata(2),
- SCIRDATA1 => sci_rddata(1),
- SCIRDATA0 => sci_rddata(0),
- SCIENAUX => fpsc_vhi,
- SCISELAUX => sci_sel_quad,
- SCIRD => sci_rd,
- SCIWSTN => sci_wrn,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => tx_sync_qd_c,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
-
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end serdes_4_sync_hub_downstream_arch ;
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 27 11:44:02.265" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.pp" type="pp" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.sym" type="sym" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.tft" type="tft" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 08 27 11:44:00.000"/>
- <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 08 27 11:44:00.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_sync_upstream
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=08/27/2014
-Time=11:44:00
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=RXTX
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=DISABLED
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=G8B10B
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=DISABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
-_tx_ficlk_rate0=200
-_tx_ficlk_rate1=200
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=2
-_rx_protocol0=DISABLED
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=G8B10B
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=200
-_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=200
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=DISABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=DISABLED
-_rx_ficlk_rate0=200
-_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=DC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=00
-_k02=00
-_k03=01
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00000000
-_byten02=00000000
-_byten03=00011100
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_sync_upstream.pp=pp
-serdes_sync_upstream.tft=tft
-serdes_sync_upstream.txt=pcs_module
-serdes_sync_upstream.sym=sym
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "serdes_sync_upstream.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_CORE";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_sync_upstream is
- GENERIC (USER_CONFIG_FILE : String := "serdes_sync_upstream.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
--- CH2 --
--- CH3 --
- hdinp_ch3, hdinn_ch3 : in std_logic;
- hdoutp_ch3, hdoutn_ch3 : out std_logic;
- sci_sel_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- txdata_ch3 : in std_logic_vector (7 downto 0);
- tx_k_ch3 : in std_logic;
- tx_force_disp_ch3 : in std_logic;
- tx_disp_sel_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- rx_serdes_rst_ch3_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
- tx_pcs_rst_ch3_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pcs_rst_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
- tx_div2_mode_ch3_c : in std_logic;
- rx_div2_mode_ch3_c : in std_logic;
----- Miscillaneous ports
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end serdes_sync_upstream;
-
-
-architecture serdes_sync_upstream_arch of serdes_sync_upstream is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH3_CDR_SRC: string;
- attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch3_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- refclk2fpga <= refclk2fpga_sig;
- rx_los_low_ch3_s <= rx_los_low_ch3_sig;
- rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH3_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => open,
- HDOUTN0 => open,
- HDINP0 => fpsc_vlo,
- HDINN0 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => fpsc_vlo,
- FF_TXI_CLK_0 => fpsc_vlo,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => open,
- FF_RX_H_CLK_0 => open,
- FF_TX_F_CLK_0 => open,
- FF_TX_H_CLK_0 => open,
- FFC_CK_CORE_RX_0 => fpsc_vlo,
- FF_TX_D_0_0 => fpsc_vlo,
- FF_TX_D_0_1 => fpsc_vlo,
- FF_TX_D_0_2 => fpsc_vlo,
- FF_TX_D_0_3 => fpsc_vlo,
- FF_TX_D_0_4 => fpsc_vlo,
- FF_TX_D_0_5 => fpsc_vlo,
- FF_TX_D_0_6 => fpsc_vlo,
- FF_TX_D_0_7 => fpsc_vlo,
- FF_TX_D_0_8 => fpsc_vlo,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => fpsc_vlo,
- FF_TX_D_0_11 => fpsc_vlo,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => open,
- FF_RX_D_0_1 => open,
- FF_RX_D_0_2 => open,
- FF_RX_D_0_3 => open,
- FF_RX_D_0_4 => open,
- FF_RX_D_0_5 => open,
- FF_RX_D_0_6 => open,
- FF_RX_D_0_7 => open,
- FF_RX_D_0_8 => open,
- FF_RX_D_0_9 => open,
- FF_RX_D_0_10 => open,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => fpsc_vlo,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => fpsc_vlo,
- FFC_TXPWDNB_0 => fpsc_vlo,
- FFC_LANE_RX_RST_0 => fpsc_vlo,
- FFC_RXPWDNB_0 => fpsc_vlo,
- FFS_RLOS_LO_0 => open,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => open,
- HDOUTN1 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_TX_F_CLK_1 => open,
- FF_TX_H_CLK_1 => open,
- FFC_CK_CORE_RX_1 => fpsc_vlo,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => fpsc_vlo,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => hdoutp_ch3,
- HDOUTN3 => hdoutn_ch3,
- HDINP3 => hdinp_ch3,
- HDINN3 => hdinn_ch3,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => sci_sel_ch3,
- SCIENCH3 => fpsc_vhi,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => txiclk_ch3,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => rx_full_clk_ch3,
- FF_RX_H_CLK_3 => rx_half_clk_ch3,
- FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
- FF_TX_H_CLK_3 => tx_half_clk_ch3,
- FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
- FF_TX_D_3_0 => txdata_ch3(0),
- FF_TX_D_3_1 => txdata_ch3(1),
- FF_TX_D_3_2 => txdata_ch3(2),
- FF_TX_D_3_3 => txdata_ch3(3),
- FF_TX_D_3_4 => txdata_ch3(4),
- FF_TX_D_3_5 => txdata_ch3(5),
- FF_TX_D_3_6 => txdata_ch3(6),
- FF_TX_D_3_7 => txdata_ch3(7),
- FF_TX_D_3_8 => tx_k_ch3,
- FF_TX_D_3_9 => tx_force_disp_ch3,
- FF_TX_D_3_10 => tx_disp_sel_ch3,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => rxdata_ch3(0),
- FF_RX_D_3_1 => rxdata_ch3(1),
- FF_RX_D_3_2 => rxdata_ch3(2),
- FF_RX_D_3_3 => rxdata_ch3(3),
- FF_RX_D_3_4 => rxdata_ch3(4),
- FF_RX_D_3_5 => rxdata_ch3(5),
- FF_RX_D_3_6 => rxdata_ch3(6),
- FF_RX_D_3_7 => rxdata_ch3(7),
- FF_RX_D_3_8 => rx_k_ch3,
- FF_RX_D_3_9 => rx_disp_err_ch3,
- FF_RX_D_3_10 => rx_cv_err_ch3,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => rx_serdes_rst_ch3_c,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
- FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
- FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
- FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
- FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
- FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
-
------ Auxilliary ----
- SCIWDATA7 => sci_wrdata(7),
- SCIWDATA6 => sci_wrdata(6),
- SCIWDATA5 => sci_wrdata(5),
- SCIWDATA4 => sci_wrdata(4),
- SCIWDATA3 => sci_wrdata(3),
- SCIWDATA2 => sci_wrdata(2),
- SCIWDATA1 => sci_wrdata(1),
- SCIWDATA0 => sci_wrdata(0),
- SCIADDR5 => sci_addr(5),
- SCIADDR4 => sci_addr(4),
- SCIADDR3 => sci_addr(3),
- SCIADDR2 => sci_addr(2),
- SCIADDR1 => sci_addr(1),
- SCIADDR0 => sci_addr(0),
- SCIRDATA7 => sci_rddata(7),
- SCIRDATA6 => sci_rddata(6),
- SCIRDATA5 => sci_rddata(5),
- SCIRDATA4 => sci_rddata(4),
- SCIRDATA3 => sci_rddata(3),
- SCIRDATA2 => sci_rddata(2),
- SCIRDATA1 => sci_rddata(1),
- SCIRDATA0 => sci_rddata(0),
- SCIENAUX => fpsc_vhi,
- SCISELAUX => sci_sel_quad,
- SCIRD => sci_rd,
- SCIWSTN => sci_wrn,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
-
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end serdes_sync_upstream_arch ;
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_source_downstream" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 03 02 17:24:32.835" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_sync_source_downstream.lpc" type="lpc" modified="2015 03 02 17:24:29.000"/>
- <File name="serdes_sync_source_downstream.pp" type="pp" modified="2015 03 02 17:24:29.000"/>
- <File name="serdes_sync_source_downstream.sym" type="sym" modified="2015 03 02 17:24:30.000"/>
- <File name="serdes_sync_source_downstream.tft" type="tft" modified="2015 03 02 17:24:29.000"/>
- <File name="serdes_sync_source_downstream.txt" type="pcs_module" modified="2015 03 02 17:24:29.000"/>
- <File name="serdes_sync_source_downstream.vhd" type="top_level_vhdl" modified="2015 03 02 17:24:29.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.2
-ModuleName=serdes_sync_source_downstream
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=03/02/2015
-Time=17:24:29
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=RXTX
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=G8B10B
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=DISABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=200
-_tx_ficlk_rate1=200
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=2.5
-_rx_protocol0=G8B10B
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=200
-_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=250.0
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
-_rx_ficlk_rate0=200
-_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=250.0
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=AC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=00
-_k02=00
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00000000
-_byten02=00000000
-_byten03=00000000
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_sync_source_downstream.pp=pp
-serdes_sync_source_downstream.tft=tft
-serdes_sync_source_downstream.txt=pcs_module
-serdes_sync_source_downstream.sym=sym
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL "G8B10B"
-CH0_MODE "RXTX"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH0_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH0_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH0_RX_DATA_RATE "FULL"
-CH0_TX_DATA_RATE "FULL"
-CH0_TX_DATA_WIDTH "8"
-CH0_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "DISABLED"
-CH0_RX_FIFO "ENABLED"
-CH0_TDRV "0"
-#CH0_TX_FICLK_RATE 200
-#CH0_RXREFCLK_RATE "200"
-#CH0_RX_FICLK_RATE 200
-CH0_TX_PRE "DISABLED"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLED"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "DC"
-CH0_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "DISABLED"
-CH0_RX_SB "DISABLED"
-CH0_TX_8B10B "ENABLED"
-CH0_RX_8B10B "ENABLED"
-CH0_COMMA_A "1100000101"
-CH0_COMMA_B "0011111010"
-CH0_COMMA_M "1111111100"
-CH0_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH0_CTC "DISABLED"
-CH0_CC_MATCH4 "0100011100"
-CH0_CC_MATCH_MODE "1"
-CH0_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH0_SSLB "DISABLED"
-CH0_SPLBPORTS "DISABLED"
-CH0_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "serdes_sync_source_downstream.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_sync_source_downstream is
- GENERIC (USER_CONFIG_FILE : String := "serdes_sync_source_downstream.txt");
- port (
-------------------
--- CH0 --
- hdinp_ch0, hdinn_ch0 : in std_logic;
- hdoutp_ch0, hdoutn_ch0 : out std_logic;
- sci_sel_ch0 : in std_logic;
- rxiclk_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- txdata_ch0 : in std_logic_vector (7 downto 0);
- tx_k_ch0 : in std_logic;
- tx_force_disp_ch0 : in std_logic;
- tx_disp_sel_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- rx_serdes_rst_ch0_c : in std_logic;
- sb_felb_ch0_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- tx_pcs_rst_ch0_c : in std_logic;
- tx_pwrup_ch0_c : in std_logic;
- rx_pcs_rst_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
- tx_div2_mode_ch0_c : in std_logic;
- rx_div2_mode_ch0_c : in std_logic;
--- CH1 --
--- CH2 --
--- CH3 --
----- Miscillaneous ports
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end serdes_sync_source_downstream;
-
-
-architecture serdes_sync_source_downstream_arch of serdes_sync_source_downstream is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH0_CDR_SRC: string;
- attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch0_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- refclk2fpga <= refclk2fpga_sig;
- rx_los_low_ch0_s <= rx_los_low_ch0_sig;
- rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH0_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => hdoutp_ch0,
- HDOUTN0 => hdoutn_ch0,
- HDINP0 => hdinp_ch0,
- HDINN0 => hdinn_ch0,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => sci_sel_ch0,
- SCIENCH0 => fpsc_vhi,
- FF_RXI_CLK_0 => rxiclk_ch0,
- FF_TXI_CLK_0 => txiclk_ch0,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => rx_full_clk_ch0,
- FF_RX_H_CLK_0 => rx_half_clk_ch0,
- FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
- FF_TX_H_CLK_0 => tx_half_clk_ch0,
- FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
- FF_TX_D_0_0 => txdata_ch0(0),
- FF_TX_D_0_1 => txdata_ch0(1),
- FF_TX_D_0_2 => txdata_ch0(2),
- FF_TX_D_0_3 => txdata_ch0(3),
- FF_TX_D_0_4 => txdata_ch0(4),
- FF_TX_D_0_5 => txdata_ch0(5),
- FF_TX_D_0_6 => txdata_ch0(6),
- FF_TX_D_0_7 => txdata_ch0(7),
- FF_TX_D_0_8 => tx_k_ch0,
- FF_TX_D_0_9 => tx_force_disp_ch0,
- FF_TX_D_0_10 => tx_disp_sel_ch0,
- FF_TX_D_0_11 => fpsc_vlo,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => rxdata_ch0(0),
- FF_RX_D_0_1 => rxdata_ch0(1),
- FF_RX_D_0_2 => rxdata_ch0(2),
- FF_RX_D_0_3 => rxdata_ch0(3),
- FF_RX_D_0_4 => rxdata_ch0(4),
- FF_RX_D_0_5 => rxdata_ch0(5),
- FF_RX_D_0_6 => rxdata_ch0(6),
- FF_RX_D_0_7 => rxdata_ch0(7),
- FF_RX_D_0_8 => rx_k_ch0,
- FF_RX_D_0_9 => rx_disp_err_ch0,
- FF_RX_D_0_10 => rx_cv_err_ch0,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => rx_serdes_rst_ch0_c,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
- FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
- FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
- FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
- FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
- FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
-
------ CH1 -----
- HDOUTP1 => open,
- HDOUTN1 => open,
- HDINP1 => fpsc_vlo,
- HDINN1 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => fpsc_vlo,
- SCIENCH1 => fpsc_vlo,
- FF_RXI_CLK_1 => fpsc_vlo,
- FF_TXI_CLK_1 => fpsc_vlo,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => open,
- FF_RX_H_CLK_1 => open,
- FF_TX_F_CLK_1 => open,
- FF_TX_H_CLK_1 => open,
- FFC_CK_CORE_RX_1 => fpsc_vlo,
- FF_TX_D_1_0 => fpsc_vlo,
- FF_TX_D_1_1 => fpsc_vlo,
- FF_TX_D_1_2 => fpsc_vlo,
- FF_TX_D_1_3 => fpsc_vlo,
- FF_TX_D_1_4 => fpsc_vlo,
- FF_TX_D_1_5 => fpsc_vlo,
- FF_TX_D_1_6 => fpsc_vlo,
- FF_TX_D_1_7 => fpsc_vlo,
- FF_TX_D_1_8 => fpsc_vlo,
- FF_TX_D_1_9 => fpsc_vlo,
- FF_TX_D_1_10 => fpsc_vlo,
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => fpsc_vlo,
- FF_TX_D_1_13 => fpsc_vlo,
- FF_TX_D_1_14 => fpsc_vlo,
- FF_TX_D_1_15 => fpsc_vlo,
- FF_TX_D_1_16 => fpsc_vlo,
- FF_TX_D_1_17 => fpsc_vlo,
- FF_TX_D_1_18 => fpsc_vlo,
- FF_TX_D_1_19 => fpsc_vlo,
- FF_TX_D_1_20 => fpsc_vlo,
- FF_TX_D_1_21 => fpsc_vlo,
- FF_TX_D_1_22 => fpsc_vlo,
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => open,
- FF_RX_D_1_1 => open,
- FF_RX_D_1_2 => open,
- FF_RX_D_1_3 => open,
- FF_RX_D_1_4 => open,
- FF_RX_D_1_5 => open,
- FF_RX_D_1_6 => open,
- FF_RX_D_1_7 => open,
- FF_RX_D_1_8 => open,
- FF_RX_D_1_9 => open,
- FF_RX_D_1_10 => open,
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => open,
- FF_RX_D_1_13 => open,
- FF_RX_D_1_14 => open,
- FF_RX_D_1_15 => open,
- FF_RX_D_1_16 => open,
- FF_RX_D_1_17 => open,
- FF_RX_D_1_18 => open,
- FF_RX_D_1_19 => open,
- FF_RX_D_1_20 => open,
- FF_RX_D_1_21 => open,
- FF_RX_D_1_22 => open,
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => fpsc_vlo,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => fpsc_vlo,
- FFC_PFIFO_CLR_1 => fpsc_vlo,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => fpsc_vlo,
- FFC_TXPWDNB_1 => fpsc_vlo,
- FFC_LANE_RX_RST_1 => fpsc_vlo,
- FFC_RXPWDNB_1 => fpsc_vlo,
- FFS_RLOS_LO_1 => open,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => open,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => open,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => fpsc_vlo,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => open,
- HDOUTN3 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_TX_F_CLK_3 => open,
- FF_TX_H_CLK_3 => open,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
- SCIWDATA7 => sci_wrdata(7),
- SCIWDATA6 => sci_wrdata(6),
- SCIWDATA5 => sci_wrdata(5),
- SCIWDATA4 => sci_wrdata(4),
- SCIWDATA3 => sci_wrdata(3),
- SCIWDATA2 => sci_wrdata(2),
- SCIWDATA1 => sci_wrdata(1),
- SCIWDATA0 => sci_wrdata(0),
- SCIADDR5 => sci_addr(5),
- SCIADDR4 => sci_addr(4),
- SCIADDR3 => sci_addr(3),
- SCIADDR2 => sci_addr(2),
- SCIADDR1 => sci_addr(1),
- SCIADDR0 => sci_addr(0),
- SCIRDATA7 => sci_rddata(7),
- SCIRDATA6 => sci_rddata(6),
- SCIRDATA5 => sci_rddata(5),
- SCIRDATA4 => sci_rddata(4),
- SCIRDATA3 => sci_rddata(3),
- SCIRDATA2 => sci_rddata(2),
- SCIRDATA1 => sci_rddata(1),
- SCIRDATA0 => sci_rddata(0),
- SCIENAUX => fpsc_vhi,
- SCISELAUX => sci_sel_quad,
- SCIRD => sci_rd,
- SCIWSTN => sci_wrn,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
-
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end serdes_sync_source_downstream_arch ;
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 03 04 13:04:52.349" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_sync_upstream.lpc" type="lpc" modified="2015 03 04 13:04:49.000"/>
- <File name="serdes_sync_upstream.pp" type="pp" modified="2015 03 04 13:04:49.000"/>
- <File name="serdes_sync_upstream.sym" type="sym" modified="2015 03 04 13:04:49.000"/>
- <File name="serdes_sync_upstream.tft" type="tft" modified="2015 03 04 13:04:49.000"/>
- <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2015 03 04 13:04:49.000"/>
- <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2015 03 04 13:04:49.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH3_PROTOCOL "G8B10B"
-CH0_MODE "DISABLED"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "RXTX"
-CH3_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH3_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH3_RX_DATA_RATE "FULL"
-CH3_TX_DATA_RATE "FULL"
-CH3_TX_DATA_WIDTH "8"
-CH3_RX_DATA_WIDTH "8"
-CH3_TX_FIFO "DISABLED"
-CH3_RX_FIFO "DISABLED"
-CH3_TDRV "0"
-#CH3_TX_FICLK_RATE 200
-#CH3_RXREFCLK_RATE "200"
-#CH3_RX_FICLK_RATE 200
-CH3_TX_PRE "DISABLED"
-CH3_RTERM_TX "50"
-CH3_RX_EQ "DISABLED"
-CH3_RTERM_RX "50"
-CH3_RX_DCC "DC"
-CH3_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH3_TX_SB "DISABLED"
-CH3_RX_SB "DISABLED"
-CH3_TX_8B10B "ENABLED"
-CH3_RX_8B10B "ENABLED"
-CH3_COMMA_A "1100000101"
-CH3_COMMA_B "0011111010"
-CH3_COMMA_M "1111111100"
-CH3_RXWA "ENABLED"
-CH3_ILSM "ENABLED"
-CH3_CTC "DISABLED"
-CH3_CC_MATCH4 "0000000000"
-CH3_CC_MATCH_MODE "1"
-CH3_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH3_SSLB "DISABLED"
-CH3_SPLBPORTS "DISABLED"
-CH3_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="sfp_1_125_int" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 11 26 14:19:29.243" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="sfp_1_125_int.lpc" type="lpc" modified="2014 11 26 14:19:25.000"/>
- <File name="sfp_1_125_int.pp" type="pp" modified="2014 11 26 14:19:25.000"/>
- <File name="sfp_1_125_int.sym" type="sym" modified="2014 11 26 14:19:25.000"/>
- <File name="sfp_1_125_int.tft" type="tft" modified="2014 11 26 14:19:25.000"/>
- <File name="sfp_1_125_int.txt" type="pcs_module" modified="2014 11 26 14:19:25.000"/>
- <File name="sfp_1_125_int.vhd" type="top_level_vhdl" modified="2014 11 26 14:19:25.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.2
-ModuleName=sfp_1_125_int
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=11/26/2014
-Time=14:19:25
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=RXTX
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2.5
-_pll_txsrc=INTERNAL
-_refclk_mult=20X
-_refclk_rate=125.0
-_tx_protocol0=DISABLED
-_tx_protocol1=G8B10B
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=16
-_tx_data_width1=16
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=125.0
-_tx_ficlk_rate1=125.0
-_tx_ficlk_rate2=250.0
-_tx_ficlk_rate3=250.0
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=INTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2.5
-_rx_datarange2=2
-_rx_datarange3=2
-_rx_protocol0=DISABLED
-_rx_protocol1=G8B10B
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=100
-_rxrefclk_rate1=125.0
-_rxrefclk_rate2=100
-_rxrefclk_rate3=100
-_rx_data_width0=16
-_rx_data_width1=16
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
-_rx_ficlk_rate0=100
-_rx_ficlk_rate1=125.0
-_rx_ficlk_rate2=200
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=DC
-_rx_dcc2=AC
-_rx_dcc3=AC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=2
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=01
-_k02=00
-_k03=00
-_k10=01
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00011100
-_byten02=00000000
-_byten03=00000000
-_byten10=00011100
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=1
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=ENABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=auto
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-sfp_1_125_int.pp=pp
-sfp_1_125_int.tft=tft
-sfp_1_125_int.txt=pcs_module
-sfp_1_125_int.sym=sym
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH1_PROTOCOL "G8B10B"
-CH0_MODE "DISABLED"
-CH1_MODE "RXTX"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH1_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH1_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "20X"
-#REFCLK_RATE 125.0
-CH1_RX_DATA_RATE "FULL"
-CH1_TX_DATA_RATE "FULL"
-CH1_TX_DATA_WIDTH "16"
-CH1_RX_DATA_WIDTH "16"
-CH1_TX_FIFO "ENABLED"
-CH1_RX_FIFO "ENABLED"
-CH1_TDRV "0"
-#CH1_TX_FICLK_RATE 125.0
-#CH1_RXREFCLK_RATE "125.0"
-#CH1_RX_FICLK_RATE 125.0
-CH1_TX_PRE "DISABLED"
-CH1_RTERM_TX "50"
-CH1_RX_EQ "DISABLED"
-CH1_RTERM_RX "50"
-CH1_RX_DCC "DC"
-CH1_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH1_TX_SB "DISABLED"
-CH1_RX_SB "DISABLED"
-CH1_TX_8B10B "ENABLED"
-CH1_RX_8B10B "ENABLED"
-CH1_COMMA_A "1100000101"
-CH1_COMMA_B "0011111010"
-CH1_COMMA_M "1111111100"
-CH1_RXWA "ENABLED"
-CH1_ILSM "ENABLED"
-CH1_CTC "DISABLED"
-CH1_CC_MATCH4 "0100011100"
-CH1_CC_MATCH_MODE "1"
-CH1_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH1_SSLB "DISABLED"
-CH1_SPLBPORTS "DISABLED"
-CH1_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "sfp_1_125_int.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_CORE";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
---THIS MODULE IS INSTANTIATED PER RX CHANNEL
---Reset Sequence Generator
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity sfp_1_125_intrx_reset_sm is
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rx_serdes_rst_ch_c: out std_logic;
- rx_cdr_lol_ch_s : in std_logic;
- rx_los_low_ch_s : in std_logic;
- rx_pcs_rst_ch_c : out std_logic
-);
-end sfp_1_125_intrx_reset_sm ;
-
-architecture rx_reset_sm_arch of sfp_1_125_intrx_reset_sm is
-
-type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
-
-signal cs: statetype; -- current state of lsm
-signal ns: statetype; -- next state of lsm
-attribute syn_encoding : string;
-attribute syn_encoding of cs : signal is "safe";
-attribute syn_encoding of ns : signal is "safe";
-
-signal tx_pll_lol_qd_s_int: std_logic;
-signal rx_los_low_int: std_logic;
-signal plol_los_int: std_logic;
-signal rx_lol_los : std_logic;
-signal rx_lol_los_int: std_logic;
-signal rx_lol_los_del: std_logic;
-signal rx_pcs_rst_ch_c_int: std_logic;
-signal rx_serdes_rst_ch_c_int: std_logic;
-
-signal reset_timer1: std_logic;
-signal reset_timer2: std_logic;
-
-signal counter1: std_logic_vector(1 downto 0);
-signal TIMER1: std_logic;
-
-signal counter2: std_logic_vector(18 downto 0);
-signal TIMER2 : std_logic;
-signal rstn_m1: std_logic;
-signal rstn_m2: std_logic;
-signal sync_rst_n: std_logic;
-begin
-
-process (refclkdiv2, rst_n)
-begin
- if rst_n = '0' then
- rstn_m1 <= '0';
- rstn_m2 <= '0';
- else if rising_edge(refclkdiv2) then
- rstn_m1 <= '1';
- rstn_m2 <= rstn_m1;
- end if;
- end if;
-end process;
-
- sync_rst_n <= rstn_m2;
-
-rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
-
-process(refclkdiv2, sync_rst_n)
-begin
- if sync_rst_n = '0' then
- cs <= WAIT_FOR_PLOL;
- rx_lol_los_int <= '1';
- rx_lol_los_del <= '1';
- tx_pll_lol_qd_s_int <= '1';
- rx_pcs_rst_ch_c <= '1';
- rx_serdes_rst_ch_c <= '0';
- rx_los_low_int <= '1';
- else if rising_edge(refclkdiv2) then
- cs <= ns;
- rx_lol_los_del <= rx_lol_los;
- rx_lol_los_int <= rx_lol_los_del;
- tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
- rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
- rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
- rx_los_low_int <= rx_los_low_ch_s;
- end if;
- end if;
-end process;
-
---TIMER1 = 3NS;
---Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
---A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
-
-process(refclkdiv2, reset_timer1)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer1 = '1' then
- counter1 <= "00";
- TIMER1 <= '0';
- else
- if counter1(1) = '1' then
- TIMER1 <='1';
- else
- TIMER1 <='0';
- counter1 <= counter1 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
---TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
---An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-
-process(refclkdiv2, reset_timer2)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer2 = '1' then
- counter2 <= "0000000000000000000";
- TIMER2 <= '0';
- else
- if counter2(count_index) = '1' then
- TIMER2 <='1';
- else
- TIMER2 <='0';
- counter2 <= counter2 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-
-process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
-begin
- reset_timer1 <= '0';
- reset_timer2 <= '0';
-
- case cs is
- when WAIT_FOR_PLOL =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal
- ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next
- else
- ns <= RX_SERDES_RESET;
- end if;
-
- when RX_SERDES_RESET =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '1';
- reset_timer1 <= '1';
- ns <= WAIT_FOR_TIMER1;
-
-
- when WAIT_FOR_TIMER1 =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '1';
- if TIMER1 = '1' then
- ns <= CHECK_LOL_LOS;
- else
- ns <= WAIT_FOR_TIMER1;
- end if;
-
- when CHECK_LOL_LOS =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- reset_timer2 <= '1';
- ns <= WAIT_FOR_TIMER2;
-
- when WAIT_FOR_TIMER2 =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES
- if TIMER2 = '1' then
- if rx_lol_los_int = '1' then
- ns <= WAIT_FOR_PLOL;
- else
- ns <= NORMAL;
- end if;
- else
- ns <= WAIT_FOR_TIMER2;
- end if;
- else
- ns <= CHECK_LOL_LOS; --RESET TIMER2
- end if;
-
- when NORMAL =>
- rx_pcs_rst_ch_c_int <= '0';
- rx_serdes_rst_ch_c_int <= '0';
- if rx_lol_los_int = '1' then
- ns <= WAIT_FOR_PLOL;
- else
- ns <= NORMAL;
- end if;
-
- when others =>
- ns <= WAIT_FOR_PLOL;
-
- end case;
-
-end process;
-
-
-end rx_reset_sm_arch;
-
---THIS MODULE IS INSTANTIATED PER TX QUAD
---TX Reset Sequence state machine--
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity sfp_1_125_inttx_reset_sm is
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rst_qd_c : out std_logic;
- tx_pcs_rst_ch_c : out std_logic
- );
-end sfp_1_125_inttx_reset_sm;
-
-architecture tx_reset_sm_arch of sfp_1_125_inttx_reset_sm is
-
-type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
-
-signal cs: statetype; -- current state of lsm
-signal ns: statetype; -- next state of lsm
-attribute syn_encoding : string;
-attribute syn_encoding of cs : signal is "safe";
-attribute syn_encoding of ns : signal is "safe";
-
-signal tx_pll_lol_qd_s_int : std_logic;
-signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0);
-signal rst_qd_c_int : std_logic;
-
-signal reset_timer1: std_logic;
-signal reset_timer2: std_logic;
-
-signal counter1: std_logic_vector(2 downto 0);
-signal TIMER1: std_logic;
-
-signal counter2: std_logic_vector(18 downto 0);
-signal TIMER2: std_logic;
-
-signal rstn_m1: std_logic;
-signal rstn_m2: std_logic;
-signal sync_rst_n: std_logic;
-begin
-
-process (refclkdiv2, rst_n)
-begin
- if rst_n = '0' then
- rstn_m1 <= '0';
- rstn_m2 <= '0';
- else if rising_edge(refclkdiv2) then
- rstn_m1 <= '1';
- rstn_m2 <= rstn_m1;
- end if;
- end if;
-end process;
-
- sync_rst_n <= rstn_m2;
-process (refclkdiv2, sync_rst_n)
-begin
- if sync_rst_n = '0' then
- cs <= QUAD_RESET;
- tx_pll_lol_qd_s_int <= '1';
- tx_pcs_rst_ch_c <= '1';
- rst_qd_c <= '1';
- else if rising_edge(refclkdiv2) then
- cs <= ns;
- tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
- tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
- rst_qd_c <= rst_qd_c_int;
- end if;
- end if;
-end process;
---TIMER1 = 20ns;
---Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
--- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
-
-
-process (refclkdiv2, reset_timer1)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer1 = '1' then
- counter1 <= "000";
- TIMER1 <= '0';
- else
- if counter1(2) = '1' then
- TIMER1 <= '1';
- else
- TIMER1 <='0';
- counter1 <= counter1 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-
---TIMER2 = 1,400,000 UI;
---WORST CASE CYCLES is with smallest multipier factor.
--- This would be with X8 clock multiplier in DIV2 mode
--- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
--- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
--- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-
-
-process(refclkdiv2, reset_timer2)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer2 = '1' then
- counter2 <= "0000000000000000000";
- TIMER2 <= '0';
- else
- if counter2(count_index) = '1' then
- TIMER2 <='1';
- else
- TIMER2 <='0';
- counter2 <= counter2 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
-begin
-
- reset_timer1 <= '0';
- reset_timer2 <= '0';
-
- case cs is
-
- when QUAD_RESET =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '1';
- reset_timer1 <= '1';
- ns <= WAIT_FOR_TIMER1;
-
- when WAIT_FOR_TIMER1 =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '1';
- if TIMER1 = '1' then
- ns <= CHECK_PLOL;
- else
- ns <= WAIT_FOR_TIMER1;
- end if;
-
- when CHECK_PLOL =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '0';
- reset_timer2 <= '1';
- ns <= WAIT_FOR_TIMER2;
-
- when WAIT_FOR_TIMER2 =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '0';
- if TIMER2 = '1' then
- if tx_pll_lol_qd_s_int = '1' then
- ns <= QUAD_RESET;
- else
- ns <= NORMAL;
- end if;
- else
- ns <= WAIT_FOR_TIMER2;
- end if;
-
- when NORMAL =>
- tx_pcs_rst_ch_c_int <= "0000";
- rst_qd_c_int <= '0';
- if tx_pll_lol_qd_s_int = '1' then
- ns <= QUAD_RESET;
- else
- ns <= NORMAL;
- end if;
-
- when others =>
- ns <= QUAD_RESET;
-
- end case;
-
-end process;
-
-end tx_reset_sm_arch;
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity sfp_1_125_int is
- GENERIC (USER_CONFIG_FILE : String := "sfp_1_125_int.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
- hdinp_ch1, hdinn_ch1 : in std_logic;
- hdoutp_ch1, hdoutn_ch1 : out std_logic;
- sci_sel_ch1 : in std_logic;
- rxiclk_ch1 : in std_logic;
- txiclk_ch1 : in std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- tx_full_clk_ch1 : out std_logic;
- tx_half_clk_ch1 : out std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- txdata_ch1 : in std_logic_vector (15 downto 0);
- tx_k_ch1 : in std_logic_vector (1 downto 0);
- tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
- tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
- rxdata_ch1 : out std_logic_vector (15 downto 0);
- rx_k_ch1 : out std_logic_vector (1 downto 0);
- rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
- rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
- sb_felb_ch1_c : in std_logic;
- sb_felb_rst_ch1_c : in std_logic;
- tx_pwrup_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- rx_los_low_ch1_s : out std_logic;
- lsm_status_ch1_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- tx_div2_mode_ch1_c : in std_logic;
- rx_div2_mode_ch1_c : in std_logic;
--- CH2 --
--- CH3 --
----- Miscillaneous ports
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- refclk2fpga : out std_logic;
- rst_n : in std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end sfp_1_125_int;
-
-
-architecture sfp_1_125_int_arch of sfp_1_125_int is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-component sfp_1_125_intrx_reset_sm
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rx_serdes_rst_ch_c: out std_logic;
- rx_cdr_lol_ch_s : in std_logic;
- rx_los_low_ch_s : in std_logic;
- rx_pcs_rst_ch_c : out std_logic
-);
-end component ;
-
-component sfp_1_125_inttx_reset_sm
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rst_qd_c : out std_logic;
- tx_pcs_rst_ch_c : out std_logic
- );
-end component;
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH1_CDR_SRC: string;
- attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "125.0";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch1_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-signal rx_serdes_rst_ch1_c : std_logic;
-signal rx_pcs_rst_ch1_c : std_logic;
-
--- reset sequence for rx
-signal refclkdiv2_rx_ch1 : std_logic;
-
-signal refclkdiv2_tx_ch : std_logic;
-signal tx_pcs_rst_ch_c : std_logic;
-signal rst_qd_c : std_logic;
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- refclk2fpga <= refclk2fpga_sig;
- rx_los_low_ch1_s <= rx_los_low_ch1_sig;
- rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH1_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => open,
- HDOUTN0 => open,
- HDINP0 => fpsc_vlo,
- HDINN0 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => fpsc_vlo,
- FF_TXI_CLK_0 => fpsc_vlo,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => open,
- FF_RX_H_CLK_0 => open,
- FF_TX_F_CLK_0 => open,
- FF_TX_H_CLK_0 => open,
- FFC_CK_CORE_RX_0 => fpsc_vlo,
- FF_TX_D_0_0 => fpsc_vlo,
- FF_TX_D_0_1 => fpsc_vlo,
- FF_TX_D_0_2 => fpsc_vlo,
- FF_TX_D_0_3 => fpsc_vlo,
- FF_TX_D_0_4 => fpsc_vlo,
- FF_TX_D_0_5 => fpsc_vlo,
- FF_TX_D_0_6 => fpsc_vlo,
- FF_TX_D_0_7 => fpsc_vlo,
- FF_TX_D_0_8 => fpsc_vlo,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => fpsc_vlo,
- FF_TX_D_0_11 => fpsc_vlo,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => open,
- FF_RX_D_0_1 => open,
- FF_RX_D_0_2 => open,
- FF_RX_D_0_3 => open,
- FF_RX_D_0_4 => open,
- FF_RX_D_0_5 => open,
- FF_RX_D_0_6 => open,
- FF_RX_D_0_7 => open,
- FF_RX_D_0_8 => open,
- FF_RX_D_0_9 => open,
- FF_RX_D_0_10 => open,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => fpsc_vlo,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => fpsc_vlo,
- FFC_TXPWDNB_0 => fpsc_vlo,
- FFC_LANE_RX_RST_0 => fpsc_vlo,
- FFC_RXPWDNB_0 => fpsc_vlo,
- FFS_RLOS_LO_0 => open,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => hdoutp_ch1,
- HDOUTN1 => hdoutn_ch1,
- HDINP1 => hdinp_ch1,
- HDINN1 => hdinn_ch1,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => sci_sel_ch1,
- SCIENCH1 => fpsc_vhi,
- FF_RXI_CLK_1 => rxiclk_ch1,
- FF_TXI_CLK_1 => txiclk_ch1,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => rx_full_clk_ch1,
- FF_RX_H_CLK_1 => rx_half_clk_ch1,
- FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
- FF_TX_H_CLK_1 => tx_half_clk_ch1,
- FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
- FF_TX_D_1_0 => txdata_ch1(0),
- FF_TX_D_1_1 => txdata_ch1(1),
- FF_TX_D_1_2 => txdata_ch1(2),
- FF_TX_D_1_3 => txdata_ch1(3),
- FF_TX_D_1_4 => txdata_ch1(4),
- FF_TX_D_1_5 => txdata_ch1(5),
- FF_TX_D_1_6 => txdata_ch1(6),
- FF_TX_D_1_7 => txdata_ch1(7),
- FF_TX_D_1_8 => tx_k_ch1(0),
- FF_TX_D_1_9 => tx_force_disp_ch1(0),
- FF_TX_D_1_10 => tx_disp_sel_ch1(0),
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => txdata_ch1(8),
- FF_TX_D_1_13 => txdata_ch1(9),
- FF_TX_D_1_14 => txdata_ch1(10),
- FF_TX_D_1_15 => txdata_ch1(11),
- FF_TX_D_1_16 => txdata_ch1(12),
- FF_TX_D_1_17 => txdata_ch1(13),
- FF_TX_D_1_18 => txdata_ch1(14),
- FF_TX_D_1_19 => txdata_ch1(15),
- FF_TX_D_1_20 => tx_k_ch1(1),
- FF_TX_D_1_21 => tx_force_disp_ch1(1),
- FF_TX_D_1_22 => tx_disp_sel_ch1(1),
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => rxdata_ch1(0),
- FF_RX_D_1_1 => rxdata_ch1(1),
- FF_RX_D_1_2 => rxdata_ch1(2),
- FF_RX_D_1_3 => rxdata_ch1(3),
- FF_RX_D_1_4 => rxdata_ch1(4),
- FF_RX_D_1_5 => rxdata_ch1(5),
- FF_RX_D_1_6 => rxdata_ch1(6),
- FF_RX_D_1_7 => rxdata_ch1(7),
- FF_RX_D_1_8 => rx_k_ch1(0),
- FF_RX_D_1_9 => rx_disp_err_ch1(0),
- FF_RX_D_1_10 => rx_cv_err_ch1(0),
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => rxdata_ch1(8),
- FF_RX_D_1_13 => rxdata_ch1(9),
- FF_RX_D_1_14 => rxdata_ch1(10),
- FF_RX_D_1_15 => rxdata_ch1(11),
- FF_RX_D_1_16 => rxdata_ch1(12),
- FF_RX_D_1_17 => rxdata_ch1(13),
- FF_RX_D_1_18 => rxdata_ch1(14),
- FF_RX_D_1_19 => rxdata_ch1(15),
- FF_RX_D_1_20 => rx_k_ch1(1),
- FF_RX_D_1_21 => rx_disp_err_ch1(1),
- FF_RX_D_1_22 => rx_cv_err_ch1(1),
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => rx_serdes_rst_ch1_c,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
- FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => tx_pcs_rst_ch_c,
- FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
- FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
- FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
- FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => open,
- HDOUTN3 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_TX_F_CLK_3 => open,
- FF_TX_H_CLK_3 => open,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
- SCIWDATA7 => sci_wrdata(7),
- SCIWDATA6 => sci_wrdata(6),
- SCIWDATA5 => sci_wrdata(5),
- SCIWDATA4 => sci_wrdata(4),
- SCIWDATA3 => sci_wrdata(3),
- SCIWDATA2 => sci_wrdata(2),
- SCIWDATA1 => sci_wrdata(1),
- SCIWDATA0 => sci_wrdata(0),
- SCIADDR5 => sci_addr(5),
- SCIADDR4 => sci_addr(4),
- SCIADDR3 => sci_addr(3),
- SCIADDR2 => sci_addr(2),
- SCIADDR1 => sci_addr(1),
- SCIADDR0 => sci_addr(0),
- SCIRDATA7 => sci_rddata(7),
- SCIRDATA6 => sci_rddata(6),
- SCIRDATA5 => sci_rddata(5),
- SCIRDATA4 => sci_rddata(4),
- SCIRDATA3 => sci_rddata(3),
- SCIRDATA2 => sci_rddata(2),
- SCIRDATA1 => sci_rddata(1),
- SCIRDATA0 => sci_rddata(0),
- SCIENAUX => fpsc_vhi,
- SCISELAUX => sci_sel_quad,
- SCIRD => sci_rd,
- SCIWSTN => sci_wrn,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
--- reset sequence for rx
-
- P2 : PROCESS(fpga_rxrefclk_ch1, rst_n)
- BEGIN
- IF (rst_n = '0') THEN
- refclkdiv2_rx_ch1 <= '0';
- ELSIF (fpga_rxrefclk_ch1'event and fpga_rxrefclk_ch1 = '1') THEN
- refclkdiv2_rx_ch1 <= not refclkdiv2_rx_ch1;
- END IF;
- END PROCESS;
-
-rx_reset_sm_ch1 : sfp_1_125_intrx_reset_sm
---synopsys translate_off
- generic map (count_index => 4)
---synopsys translate_on
-port map (
- refclkdiv2 => refclkdiv2_rx_ch1,
- rst_n => rst_n,
- rx_cdr_lol_ch_s => rx_cdr_lol_ch1_sig,
- rx_los_low_ch_s => rx_los_low_ch1_sig,
- tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
- rx_pcs_rst_ch_c => rx_pcs_rst_ch1_c,
- rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c);
-
-
-
-
- P5 : PROCESS(fpga_txrefclk, rst_n)
- BEGIN
- IF (rst_n = '0') THEN
- refclkdiv2_tx_ch <= '0';
- ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
- refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
- END IF;
- END PROCESS;
-
--- reset sequence for tx
-tx_reset_sm_ch : sfp_1_125_inttx_reset_sm
---synopsys translate_off
- generic map (count_index => 4)
---synopsys translate_on
-port map (
- rst_n => rst_n,
- refclkdiv2 => refclkdiv2_tx_ch,
- tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
- rst_qd_c => rst_qd_c,
- tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
- );
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end sfp_1_125_int_arch ;
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="sfp_1_200_int" module="sfp_1_200_int" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 11 09:38:27.437" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="sfp_1_200_int.lpc" type="lpc" modified="2015 02 11 09:38:25.000"/>
- <File name="sfp_1_200_int.pp" type="pp" modified="2015 02 11 09:38:25.000"/>
- <File name="sfp_1_200_int.sym" type="sym" modified="2015 02 11 09:38:25.000"/>
- <File name="sfp_1_200_int.tft" type="tft" modified="2015 02 11 09:38:25.000"/>
- <File name="sfp_1_200_int.txt" type="pcs_module" modified="2015 02 11 09:38:25.000"/>
- <File name="sfp_1_200_int.vhd" type="top_level_vhdl" modified="2015 02 11 09:38:25.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.2
-ModuleName=sfp_1_200_int
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=02/11/2015
-Time=09:38:25
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=RXTX
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=DISABLED
-_tx_protocol1=G8B10B
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=16
-_tx_data_width1=16
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
-_tx_ficlk_rate0=100
-_tx_ficlk_rate1=100
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=INTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2
-_rx_datarange2=2
-_rx_datarange3=2
-_rx_protocol0=DISABLED
-_rx_protocol1=G8B10B
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=200
-_rxrefclk_rate1=200
-_rxrefclk_rate2=200
-_rxrefclk_rate3=200
-_rx_data_width0=16
-_rx_data_width1=16
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=DISABLED
-_rx_ficlk_rate0=100
-_rx_ficlk_rate1=100
-_rx_ficlk_rate2=200
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=DC
-_rx_dcc2=AC
-_rx_dcc3=DC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=2
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=01
-_k02=00
-_k03=00
-_k10=01
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00011100
-_byten02=00000000
-_byten03=00000000
-_byten10=00011100
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=1
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=ENABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-sfp_1_200_int.pp=pp
-sfp_1_200_int.tft=tft
-sfp_1_200_int.txt=pcs_module
-sfp_1_200_int.sym=sym
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH1_PROTOCOL "G8B10B"
-CH0_MODE "DISABLED"
-CH1_MODE "RXTX"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH1_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH1_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH1_RX_DATA_RATE "FULL"
-CH1_TX_DATA_RATE "FULL"
-CH1_TX_DATA_WIDTH "16"
-CH1_RX_DATA_WIDTH "16"
-CH1_TX_FIFO "ENABLED"
-CH1_RX_FIFO "ENABLED"
-CH1_TDRV "0"
-#CH1_TX_FICLK_RATE 100
-#CH1_RXREFCLK_RATE "200"
-#CH1_RX_FICLK_RATE 100
-CH1_TX_PRE "DISABLED"
-CH1_RTERM_TX "50"
-CH1_RX_EQ "DISABLED"
-CH1_RTERM_RX "50"
-CH1_RX_DCC "DC"
-CH1_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH1_TX_SB "DISABLED"
-CH1_RX_SB "DISABLED"
-CH1_TX_8B10B "ENABLED"
-CH1_RX_8B10B "ENABLED"
-CH1_COMMA_A "1100000101"
-CH1_COMMA_B "0011111010"
-CH1_COMMA_M "1111111100"
-CH1_RXWA "ENABLED"
-CH1_ILSM "ENABLED"
-CH1_CTC "DISABLED"
-CH1_CC_MATCH4 "0100011100"
-CH1_CC_MATCH_MODE "1"
-CH1_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH1_SSLB "DISABLED"
-CH1_SPLBPORTS "DISABLED"
-CH1_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "sfp_1_200_int.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_CORE";
--- CH1_CDR_SRC : String := "REFCLK_CORE";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_CORE";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
---THIS MODULE IS INSTANTIATED PER RX CHANNEL
---Reset Sequence Generator
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity sfp_1_200_intrx_reset_sm is
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rx_serdes_rst_ch_c: out std_logic;
- rx_cdr_lol_ch_s : in std_logic;
- rx_los_low_ch_s : in std_logic;
- rx_pcs_rst_ch_c : out std_logic
-);
-end sfp_1_200_intrx_reset_sm ;
-
-architecture rx_reset_sm_arch of sfp_1_200_intrx_reset_sm is
-
-type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
-
-signal cs: statetype; -- current state of lsm
-signal ns: statetype; -- next state of lsm
-attribute syn_encoding : string;
-attribute syn_encoding of cs : signal is "safe";
-attribute syn_encoding of ns : signal is "safe";
-
-signal tx_pll_lol_qd_s_int: std_logic;
-signal rx_los_low_int: std_logic;
-signal plol_los_int: std_logic;
-signal rx_lol_los : std_logic;
-signal rx_lol_los_int: std_logic;
-signal rx_lol_los_del: std_logic;
-signal rx_pcs_rst_ch_c_int: std_logic;
-signal rx_serdes_rst_ch_c_int: std_logic;
-
-signal reset_timer1: std_logic;
-signal reset_timer2: std_logic;
-
-signal counter1: std_logic_vector(1 downto 0);
-signal TIMER1: std_logic;
-
-signal counter2: std_logic_vector(18 downto 0);
-signal TIMER2 : std_logic;
-signal rstn_m1: std_logic;
-signal rstn_m2: std_logic;
-signal sync_rst_n: std_logic;
-begin
-
-process (refclkdiv2, rst_n)
-begin
- if rst_n = '0' then
- rstn_m1 <= '0';
- rstn_m2 <= '0';
- else if rising_edge(refclkdiv2) then
- rstn_m1 <= '1';
- rstn_m2 <= rstn_m1;
- end if;
- end if;
-end process;
-
- sync_rst_n <= rstn_m2;
-
-rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
-
-process(refclkdiv2, sync_rst_n)
-begin
- if sync_rst_n = '0' then
- cs <= WAIT_FOR_PLOL;
- rx_lol_los_int <= '1';
- rx_lol_los_del <= '1';
- tx_pll_lol_qd_s_int <= '1';
- rx_pcs_rst_ch_c <= '1';
- rx_serdes_rst_ch_c <= '0';
- rx_los_low_int <= '1';
- else if rising_edge(refclkdiv2) then
- cs <= ns;
- rx_lol_los_del <= rx_lol_los;
- rx_lol_los_int <= rx_lol_los_del;
- tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
- rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
- rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
- rx_los_low_int <= rx_los_low_ch_s;
- end if;
- end if;
-end process;
-
---TIMER1 = 3NS;
---Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
---A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
-
-process(refclkdiv2, reset_timer1)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer1 = '1' then
- counter1 <= "00";
- TIMER1 <= '0';
- else
- if counter1(1) = '1' then
- TIMER1 <='1';
- else
- TIMER1 <='0';
- counter1 <= counter1 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
---TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
---An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-
-process(refclkdiv2, reset_timer2)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer2 = '1' then
- counter2 <= "0000000000000000000";
- TIMER2 <= '0';
- else
- if counter2(count_index) = '1' then
- TIMER2 <='1';
- else
- TIMER2 <='0';
- counter2 <= counter2 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-
-process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
-begin
- reset_timer1 <= '0';
- reset_timer2 <= '0';
-
- case cs is
- when WAIT_FOR_PLOL =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal
- ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next
- else
- ns <= RX_SERDES_RESET;
- end if;
-
- when RX_SERDES_RESET =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '1';
- reset_timer1 <= '1';
- ns <= WAIT_FOR_TIMER1;
-
-
- when WAIT_FOR_TIMER1 =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '1';
- if TIMER1 = '1' then
- ns <= CHECK_LOL_LOS;
- else
- ns <= WAIT_FOR_TIMER1;
- end if;
-
- when CHECK_LOL_LOS =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- reset_timer2 <= '1';
- ns <= WAIT_FOR_TIMER2;
-
- when WAIT_FOR_TIMER2 =>
- rx_pcs_rst_ch_c_int <= '1';
- rx_serdes_rst_ch_c_int <= '0';
- if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES
- if TIMER2 = '1' then
- if rx_lol_los_int = '1' then
- ns <= WAIT_FOR_PLOL;
- else
- ns <= NORMAL;
- end if;
- else
- ns <= WAIT_FOR_TIMER2;
- end if;
- else
- ns <= CHECK_LOL_LOS; --RESET TIMER2
- end if;
-
- when NORMAL =>
- rx_pcs_rst_ch_c_int <= '0';
- rx_serdes_rst_ch_c_int <= '0';
- if rx_lol_los_int = '1' then
- ns <= WAIT_FOR_PLOL;
- else
- ns <= NORMAL;
- end if;
-
- when others =>
- ns <= WAIT_FOR_PLOL;
-
- end case;
-
-end process;
-
-
-end rx_reset_sm_arch;
-
---THIS MODULE IS INSTANTIATED PER TX QUAD
---TX Reset Sequence state machine--
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity sfp_1_200_inttx_reset_sm is
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rst_qd_c : out std_logic;
- tx_pcs_rst_ch_c : out std_logic
- );
-end sfp_1_200_inttx_reset_sm;
-
-architecture tx_reset_sm_arch of sfp_1_200_inttx_reset_sm is
-
-type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
-
-signal cs: statetype; -- current state of lsm
-signal ns: statetype; -- next state of lsm
-attribute syn_encoding : string;
-attribute syn_encoding of cs : signal is "safe";
-attribute syn_encoding of ns : signal is "safe";
-
-signal tx_pll_lol_qd_s_int : std_logic;
-signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0);
-signal rst_qd_c_int : std_logic;
-
-signal reset_timer1: std_logic;
-signal reset_timer2: std_logic;
-
-signal counter1: std_logic_vector(2 downto 0);
-signal TIMER1: std_logic;
-
-signal counter2: std_logic_vector(18 downto 0);
-signal TIMER2: std_logic;
-
-signal rstn_m1: std_logic;
-signal rstn_m2: std_logic;
-signal sync_rst_n: std_logic;
-begin
-
-process (refclkdiv2, rst_n)
-begin
- if rst_n = '0' then
- rstn_m1 <= '0';
- rstn_m2 <= '0';
- else if rising_edge(refclkdiv2) then
- rstn_m1 <= '1';
- rstn_m2 <= rstn_m1;
- end if;
- end if;
-end process;
-
- sync_rst_n <= rstn_m2;
-process (refclkdiv2, sync_rst_n)
-begin
- if sync_rst_n = '0' then
- cs <= QUAD_RESET;
- tx_pll_lol_qd_s_int <= '1';
- tx_pcs_rst_ch_c <= '1';
- rst_qd_c <= '1';
- else if rising_edge(refclkdiv2) then
- cs <= ns;
- tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
- tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
- rst_qd_c <= rst_qd_c_int;
- end if;
- end if;
-end process;
---TIMER1 = 20ns;
---Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
--- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
-
-
-process (refclkdiv2, reset_timer1)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer1 = '1' then
- counter1 <= "000";
- TIMER1 <= '0';
- else
- if counter1(2) = '1' then
- TIMER1 <= '1';
- else
- TIMER1 <='0';
- counter1 <= counter1 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-
---TIMER2 = 1,400,000 UI;
---WORST CASE CYCLES is with smallest multipier factor.
--- This would be with X8 clock multiplier in DIV2 mode
--- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
--- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
--- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-
-
-process(refclkdiv2, reset_timer2)
-begin
- if rising_edge(refclkdiv2) then
- if reset_timer2 = '1' then
- counter2 <= "0000000000000000000";
- TIMER2 <= '0';
- else
- if counter2(count_index) = '1' then
- TIMER2 <='1';
- else
- TIMER2 <='0';
- counter2 <= counter2 + 1 ;
- end if;
- end if;
- end if;
-end process;
-
-process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
-begin
-
- reset_timer1 <= '0';
- reset_timer2 <= '0';
-
- case cs is
-
- when QUAD_RESET =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '1';
- reset_timer1 <= '1';
- ns <= WAIT_FOR_TIMER1;
-
- when WAIT_FOR_TIMER1 =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '1';
- if TIMER1 = '1' then
- ns <= CHECK_PLOL;
- else
- ns <= WAIT_FOR_TIMER1;
- end if;
-
- when CHECK_PLOL =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '0';
- reset_timer2 <= '1';
- ns <= WAIT_FOR_TIMER2;
-
- when WAIT_FOR_TIMER2 =>
- tx_pcs_rst_ch_c_int <= "1111";
- rst_qd_c_int <= '0';
- if TIMER2 = '1' then
- if tx_pll_lol_qd_s_int = '1' then
- ns <= QUAD_RESET;
- else
- ns <= NORMAL;
- end if;
- else
- ns <= WAIT_FOR_TIMER2;
- end if;
-
- when NORMAL =>
- tx_pcs_rst_ch_c_int <= "0000";
- rst_qd_c_int <= '0';
- if tx_pll_lol_qd_s_int = '1' then
- ns <= QUAD_RESET;
- else
- ns <= NORMAL;
- end if;
-
- when others =>
- ns <= QUAD_RESET;
-
- end case;
-
-end process;
-
-end tx_reset_sm_arch;
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity sfp_1_200_int is
- GENERIC (USER_CONFIG_FILE : String := "sfp_1_200_int.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
- hdinp_ch1, hdinn_ch1 : in std_logic;
- hdoutp_ch1, hdoutn_ch1 : out std_logic;
- sci_sel_ch1 : in std_logic;
- rxiclk_ch1 : in std_logic;
- txiclk_ch1 : in std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- tx_full_clk_ch1 : out std_logic;
- tx_half_clk_ch1 : out std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- txdata_ch1 : in std_logic_vector (15 downto 0);
- tx_k_ch1 : in std_logic_vector (1 downto 0);
- tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
- tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
- rxdata_ch1 : out std_logic_vector (15 downto 0);
- rx_k_ch1 : out std_logic_vector (1 downto 0);
- rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
- rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
- sb_felb_ch1_c : in std_logic;
- sb_felb_rst_ch1_c : in std_logic;
- tx_pwrup_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- rx_los_low_ch1_s : out std_logic;
- lsm_status_ch1_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- tx_div2_mode_ch1_c : in std_logic;
- rx_div2_mode_ch1_c : in std_logic;
--- CH2 --
--- CH3 --
----- Miscillaneous ports
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- refclk2fpga : out std_logic;
- rst_n : in std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end sfp_1_200_int;
-
-
-architecture sfp_1_200_int_arch of sfp_1_200_int is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-component sfp_1_200_intrx_reset_sm
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rx_serdes_rst_ch_c: out std_logic;
- rx_cdr_lol_ch_s : in std_logic;
- rx_los_low_ch_s : in std_logic;
- rx_pcs_rst_ch_c : out std_logic
-);
-end component ;
-
-component sfp_1_200_inttx_reset_sm
-generic (count_index: integer :=18);
-port (
- rst_n : in std_logic;
- refclkdiv2 : in std_logic;
- tx_pll_lol_qd_s : in std_logic;
- rst_qd_c : out std_logic;
- tx_pcs_rst_ch_c : out std_logic
- );
-end component;
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH1_CDR_SRC: string;
- attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch1_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-signal rx_serdes_rst_ch1_c : std_logic;
-signal rx_pcs_rst_ch1_c : std_logic;
-
--- reset sequence for rx
-signal refclkdiv2_rx_ch1 : std_logic;
-
-signal refclkdiv2_tx_ch : std_logic;
-signal tx_pcs_rst_ch_c : std_logic;
-signal rst_qd_c : std_logic;
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- refclk2fpga <= refclk2fpga_sig;
- rx_los_low_ch1_s <= rx_los_low_ch1_sig;
- rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH1_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => open,
- HDOUTN0 => open,
- HDINP0 => fpsc_vlo,
- HDINN0 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => fpsc_vlo,
- FF_TXI_CLK_0 => fpsc_vlo,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => open,
- FF_RX_H_CLK_0 => open,
- FF_TX_F_CLK_0 => open,
- FF_TX_H_CLK_0 => open,
- FFC_CK_CORE_RX_0 => fpsc_vlo,
- FF_TX_D_0_0 => fpsc_vlo,
- FF_TX_D_0_1 => fpsc_vlo,
- FF_TX_D_0_2 => fpsc_vlo,
- FF_TX_D_0_3 => fpsc_vlo,
- FF_TX_D_0_4 => fpsc_vlo,
- FF_TX_D_0_5 => fpsc_vlo,
- FF_TX_D_0_6 => fpsc_vlo,
- FF_TX_D_0_7 => fpsc_vlo,
- FF_TX_D_0_8 => fpsc_vlo,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => fpsc_vlo,
- FF_TX_D_0_11 => fpsc_vlo,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => open,
- FF_RX_D_0_1 => open,
- FF_RX_D_0_2 => open,
- FF_RX_D_0_3 => open,
- FF_RX_D_0_4 => open,
- FF_RX_D_0_5 => open,
- FF_RX_D_0_6 => open,
- FF_RX_D_0_7 => open,
- FF_RX_D_0_8 => open,
- FF_RX_D_0_9 => open,
- FF_RX_D_0_10 => open,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => fpsc_vlo,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => fpsc_vlo,
- FFC_TXPWDNB_0 => fpsc_vlo,
- FFC_LANE_RX_RST_0 => fpsc_vlo,
- FFC_RXPWDNB_0 => fpsc_vlo,
- FFS_RLOS_LO_0 => open,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => hdoutp_ch1,
- HDOUTN1 => hdoutn_ch1,
- HDINP1 => hdinp_ch1,
- HDINN1 => hdinn_ch1,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => sci_sel_ch1,
- SCIENCH1 => fpsc_vhi,
- FF_RXI_CLK_1 => rxiclk_ch1,
- FF_TXI_CLK_1 => txiclk_ch1,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => rx_full_clk_ch1,
- FF_RX_H_CLK_1 => rx_half_clk_ch1,
- FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
- FF_TX_H_CLK_1 => tx_half_clk_ch1,
- FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
- FF_TX_D_1_0 => txdata_ch1(0),
- FF_TX_D_1_1 => txdata_ch1(1),
- FF_TX_D_1_2 => txdata_ch1(2),
- FF_TX_D_1_3 => txdata_ch1(3),
- FF_TX_D_1_4 => txdata_ch1(4),
- FF_TX_D_1_5 => txdata_ch1(5),
- FF_TX_D_1_6 => txdata_ch1(6),
- FF_TX_D_1_7 => txdata_ch1(7),
- FF_TX_D_1_8 => tx_k_ch1(0),
- FF_TX_D_1_9 => tx_force_disp_ch1(0),
- FF_TX_D_1_10 => tx_disp_sel_ch1(0),
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => txdata_ch1(8),
- FF_TX_D_1_13 => txdata_ch1(9),
- FF_TX_D_1_14 => txdata_ch1(10),
- FF_TX_D_1_15 => txdata_ch1(11),
- FF_TX_D_1_16 => txdata_ch1(12),
- FF_TX_D_1_17 => txdata_ch1(13),
- FF_TX_D_1_18 => txdata_ch1(14),
- FF_TX_D_1_19 => txdata_ch1(15),
- FF_TX_D_1_20 => tx_k_ch1(1),
- FF_TX_D_1_21 => tx_force_disp_ch1(1),
- FF_TX_D_1_22 => tx_disp_sel_ch1(1),
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => rxdata_ch1(0),
- FF_RX_D_1_1 => rxdata_ch1(1),
- FF_RX_D_1_2 => rxdata_ch1(2),
- FF_RX_D_1_3 => rxdata_ch1(3),
- FF_RX_D_1_4 => rxdata_ch1(4),
- FF_RX_D_1_5 => rxdata_ch1(5),
- FF_RX_D_1_6 => rxdata_ch1(6),
- FF_RX_D_1_7 => rxdata_ch1(7),
- FF_RX_D_1_8 => rx_k_ch1(0),
- FF_RX_D_1_9 => rx_disp_err_ch1(0),
- FF_RX_D_1_10 => rx_cv_err_ch1(0),
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => rxdata_ch1(8),
- FF_RX_D_1_13 => rxdata_ch1(9),
- FF_RX_D_1_14 => rxdata_ch1(10),
- FF_RX_D_1_15 => rxdata_ch1(11),
- FF_RX_D_1_16 => rxdata_ch1(12),
- FF_RX_D_1_17 => rxdata_ch1(13),
- FF_RX_D_1_18 => rxdata_ch1(14),
- FF_RX_D_1_19 => rxdata_ch1(15),
- FF_RX_D_1_20 => rx_k_ch1(1),
- FF_RX_D_1_21 => rx_disp_err_ch1(1),
- FF_RX_D_1_22 => rx_cv_err_ch1(1),
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => rx_serdes_rst_ch1_c,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
- FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => tx_pcs_rst_ch_c,
- FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
- FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
- FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
- FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => open,
- HDOUTN3 => open,
- HDINP3 => fpsc_vlo,
- HDINN3 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => fpsc_vlo,
- SCIENCH3 => fpsc_vlo,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => fpsc_vlo,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => open,
- FF_RX_H_CLK_3 => open,
- FF_TX_F_CLK_3 => open,
- FF_TX_H_CLK_3 => open,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
- FF_TX_D_3_0 => fpsc_vlo,
- FF_TX_D_3_1 => fpsc_vlo,
- FF_TX_D_3_2 => fpsc_vlo,
- FF_TX_D_3_3 => fpsc_vlo,
- FF_TX_D_3_4 => fpsc_vlo,
- FF_TX_D_3_5 => fpsc_vlo,
- FF_TX_D_3_6 => fpsc_vlo,
- FF_TX_D_3_7 => fpsc_vlo,
- FF_TX_D_3_8 => fpsc_vlo,
- FF_TX_D_3_9 => fpsc_vlo,
- FF_TX_D_3_10 => fpsc_vlo,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => open,
- FF_RX_D_3_1 => open,
- FF_RX_D_3_2 => open,
- FF_RX_D_3_3 => open,
- FF_RX_D_3_4 => open,
- FF_RX_D_3_5 => open,
- FF_RX_D_3_6 => open,
- FF_RX_D_3_7 => open,
- FF_RX_D_3_8 => open,
- FF_RX_D_3_9 => open,
- FF_RX_D_3_10 => open,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => fpsc_vlo,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => fpsc_vlo,
- FFC_PFIFO_CLR_3 => fpsc_vlo,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => fpsc_vlo,
- FFC_TXPWDNB_3 => fpsc_vlo,
- FFC_LANE_RX_RST_3 => fpsc_vlo,
- FFC_RXPWDNB_3 => fpsc_vlo,
- FFS_RLOS_LO_3 => open,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => open,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => open,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => fpsc_vlo,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
- SCIWDATA7 => sci_wrdata(7),
- SCIWDATA6 => sci_wrdata(6),
- SCIWDATA5 => sci_wrdata(5),
- SCIWDATA4 => sci_wrdata(4),
- SCIWDATA3 => sci_wrdata(3),
- SCIWDATA2 => sci_wrdata(2),
- SCIWDATA1 => sci_wrdata(1),
- SCIWDATA0 => sci_wrdata(0),
- SCIADDR5 => sci_addr(5),
- SCIADDR4 => sci_addr(4),
- SCIADDR3 => sci_addr(3),
- SCIADDR2 => sci_addr(2),
- SCIADDR1 => sci_addr(1),
- SCIADDR0 => sci_addr(0),
- SCIRDATA7 => sci_rddata(7),
- SCIRDATA6 => sci_rddata(6),
- SCIRDATA5 => sci_rddata(5),
- SCIRDATA4 => sci_rddata(4),
- SCIRDATA3 => sci_rddata(3),
- SCIRDATA2 => sci_rddata(2),
- SCIRDATA1 => sci_rddata(1),
- SCIRDATA0 => sci_rddata(0),
- SCIENAUX => fpsc_vhi,
- SCISELAUX => sci_sel_quad,
- SCIRD => sci_rd,
- SCIWSTN => sci_wrn,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => fpsc_vlo,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
--- reset sequence for rx
-
- P2 : PROCESS(fpga_rxrefclk_ch1, rst_n)
- BEGIN
- IF (rst_n = '0') THEN
- refclkdiv2_rx_ch1 <= '0';
- ELSIF (fpga_rxrefclk_ch1'event and fpga_rxrefclk_ch1 = '1') THEN
- refclkdiv2_rx_ch1 <= not refclkdiv2_rx_ch1;
- END IF;
- END PROCESS;
-
-rx_reset_sm_ch1 : sfp_1_200_intrx_reset_sm
---synopsys translate_off
- generic map (count_index => 4)
---synopsys translate_on
-port map (
- refclkdiv2 => refclkdiv2_rx_ch1,
- rst_n => rst_n,
- rx_cdr_lol_ch_s => rx_cdr_lol_ch1_sig,
- rx_los_low_ch_s => rx_los_low_ch1_sig,
- tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
- rx_pcs_rst_ch_c => rx_pcs_rst_ch1_c,
- rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c);
-
-
-
-
- P5 : PROCESS(fpga_txrefclk, rst_n)
- BEGIN
- IF (rst_n = '0') THEN
- refclkdiv2_tx_ch <= '0';
- ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
- refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
- END IF;
- END PROCESS;
-
--- reset sequence for tx
-tx_reset_sm_ch : sfp_1_200_inttx_reset_sm
---synopsys translate_off
- generic map (count_index => 4)
---synopsys translate_on
-port map (
- rst_n => rst_n,
- refclkdiv2 => refclkdiv2_tx_ch,
- tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
- rst_qd_c => rst_qd_c,
- tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
- );
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end sfp_1_200_int_arch ;
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="sfp_2_200_int" module="sfp_2_200_int" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 12 10 11:11:13.056" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="sfp_2_200_int.lpc" type="lpc" modified="2014 12 10 11:10:10.000"/>
- <File name="sfp_2_200_int.pp" type="pp" modified="2014 12 10 11:10:10.000"/>
- <File name="sfp_2_200_int.sym" type="sym" modified="2014 12 10 11:10:10.000"/>
- <File name="sfp_2_200_int.tft" type="tft" modified="2014 12 10 11:10:10.000"/>
- <File name="sfp_2_200_int.txt" type="pcs_module" modified="2014 12 10 11:10:10.000"/>
- <File name="sfp_2_200_int.vhd" type="top_level_vhdl" modified="2014 12 10 11:10:10.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.2
-ModuleName=sfp_2_200_int
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/10/2014
-Time=11:10:10
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=RXTX
-_mode2=DISABLED
-_mode3=RXTX
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=DISABLED
-_tx_protocol1=G8B10B
-_tx_protocol2=DISABLED
-_tx_protocol3=G8B10B
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=16
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
-_tx_ficlk_rate0=200
-_tx_ficlk_rate1=100
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=EXTERNAL
-_pll_rxsrc1=INTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2.5
-_rx_datarange1=2
-_rx_datarange2=2.5
-_rx_datarange3=2
-_rx_protocol0=DISABLED
-_rx_protocol1=G8B10B
-_rx_protocol2=DISABLED
-_rx_protocol3=G8B10B
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=250.0
-_rxrefclk_rate1=200
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=200
-_rx_data_width0=8
-_rx_data_width1=16
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=DISABLED
-_rx_ficlk_rate0=250.0
-_rx_ficlk_rate1=100
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=AC
-_rx_dcc1=DC
-_rx_dcc2=AC
-_rx_dcc3=DC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=00
-_k01=01
-_k02=00
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00000000
-_byten01=00011100
-_byten02=00000000
-_byten03=00000000
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-sfp_2_200_int.pp=pp
-sfp_2_200_int.tft=tft
-sfp_2_200_int.txt=pcs_module
-sfp_2_200_int.sym=sym
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH1_PROTOCOL "G8B10B"
-CH3_PROTOCOL "G8B10B"
-CH0_MODE "DISABLED"
-CH1_MODE "RXTX"
-CH2_MODE "DISABLED"
-CH3_MODE "RXTX"
-CH1_CDR_SRC "REFCLK_CORE"
-CH3_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH1_RX_DATARATE_RANGE "MEDHIGH"
-CH3_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH1_RX_DATA_RATE "FULL"
-CH3_RX_DATA_RATE "FULL"
-CH1_TX_DATA_RATE "FULL"
-CH3_TX_DATA_RATE "FULL"
-CH1_TX_DATA_WIDTH "16"
-CH3_TX_DATA_WIDTH "8"
-CH1_RX_DATA_WIDTH "16"
-CH3_RX_DATA_WIDTH "8"
-CH1_TX_FIFO "ENABLED"
-CH3_TX_FIFO "DISABLED"
-CH1_RX_FIFO "ENABLED"
-CH3_RX_FIFO "DISABLED"
-CH1_TDRV "0"
-CH3_TDRV "0"
-#CH1_TX_FICLK_RATE 100
-#CH3_TX_FICLK_RATE 200
-#CH1_RXREFCLK_RATE "200"
-#CH3_RXREFCLK_RATE "200"
-#CH1_RX_FICLK_RATE 100
-#CH3_RX_FICLK_RATE 200
-CH1_TX_PRE "DISABLED"
-CH3_TX_PRE "DISABLED"
-CH1_RTERM_TX "50"
-CH3_RTERM_TX "50"
-CH1_RX_EQ "DISABLED"
-CH3_RX_EQ "DISABLED"
-CH1_RTERM_RX "50"
-CH3_RTERM_RX "50"
-CH1_RX_DCC "DC"
-CH3_RX_DCC "DC"
-CH1_LOS_THRESHOLD_LO "2"
-CH3_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH1_TX_SB "DISABLED"
-CH3_TX_SB "DISABLED"
-CH1_RX_SB "DISABLED"
-CH3_RX_SB "DISABLED"
-CH1_TX_8B10B "ENABLED"
-CH3_TX_8B10B "ENABLED"
-CH1_RX_8B10B "ENABLED"
-CH3_RX_8B10B "ENABLED"
-CH1_COMMA_A "1100000101"
-CH3_COMMA_A "1100000101"
-CH1_COMMA_B "0011111010"
-CH3_COMMA_B "0011111010"
-CH1_COMMA_M "1111111100"
-CH3_COMMA_M "1111111100"
-CH1_RXWA "ENABLED"
-CH3_RXWA "ENABLED"
-CH1_ILSM "ENABLED"
-CH3_ILSM "ENABLED"
-CH1_CTC "DISABLED"
-CH3_CTC "DISABLED"
-CH1_CC_MATCH4 "0100011100"
-CH3_CC_MATCH4 "0000000000"
-CH1_CC_MATCH_MODE "1"
-CH3_CC_MATCH_MODE "1"
-CH1_CC_MIN_IPG "3"
-CH3_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH1_SSLB "DISABLED"
-CH3_SSLB "DISABLED"
-CH1_SPLBPORTS "DISABLED"
-CH3_SPLBPORTS "DISABLED"
-CH1_PCSLBPORTS "DISABLED"
-CH3_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-
-
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
--- CONFIG_FILE : String := "sfp_2_200_int.txt";
--- QUAD_MODE : String := "SINGLE";
--- CH0_CDR_SRC : String := "REFCLK_EXT";
--- CH1_CDR_SRC : String := "REFCLK_CORE";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_CORE";
--- PLL_SRC : String := "REFCLK_CORE"
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String;
- CH1_CDR_SRC : String;
- CH2_CDR_SRC : String;
- CH3_CDR_SRC : String;
- PLL_SRC : String
- );
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
-
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
- CONFIG_FILE => CONFIG_FILE,
- QUAD_MODE => QUAD_MODE,
- CH0_CDR_SRC => CH0_CDR_SRC,
- CH1_CDR_SRC => CH1_CDR_SRC,
- CH2_CDR_SRC => CH2_CDR_SRC,
- CH3_CDR_SRC => CH3_CDR_SRC,
- PLL_SRC => PLL_SRC
- )
-port map (
- HDINN0 => HDINN0,
- HDINN1 => HDINN1,
- HDINN2 => HDINN2,
- HDINN3 => HDINN3,
- HDINP0 => HDINP0,
- HDINP1 => HDINP1,
- HDINP2 => HDINP2,
- HDINP3 => HDINP3,
- REFCLKN => REFCLKN,
- REFCLKP => REFCLKP,
- CIN11 => CIN11,
- CIN10 => CIN10,
- CIN9 => CIN9,
- CIN8 => CIN8,
- CIN7 => CIN7,
- CIN6 => CIN6,
- CIN5 => CIN5,
- CIN4 => CIN4,
- CIN3 => CIN3,
- CIN2 => CIN2,
- CIN1 => CIN1,
- CIN0 => CIN0,
- CYAWSTN => CYAWSTN,
- FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
- FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
- FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
- FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
- FF_RXI_CLK_3 => FF_RXI_CLK_3,
- FF_RXI_CLK_2 => FF_RXI_CLK_2,
- FF_RXI_CLK_1 => FF_RXI_CLK_1,
- FF_RXI_CLK_0 => FF_RXI_CLK_0,
- FF_TX_D_0_0 => FF_TX_D_0_0,
- FF_TX_D_0_1 => FF_TX_D_0_1,
- FF_TX_D_0_2 => FF_TX_D_0_2,
- FF_TX_D_0_3 => FF_TX_D_0_3,
- FF_TX_D_0_4 => FF_TX_D_0_4,
- FF_TX_D_0_5 => FF_TX_D_0_5,
- FF_TX_D_0_6 => FF_TX_D_0_6,
- FF_TX_D_0_7 => FF_TX_D_0_7,
- FF_TX_D_0_8 => FF_TX_D_0_8,
- FF_TX_D_0_9 => FF_TX_D_0_9,
- FF_TX_D_0_10 => FF_TX_D_0_10,
- FF_TX_D_0_11 => FF_TX_D_0_11,
- FF_TX_D_0_12 => FF_TX_D_0_12,
- FF_TX_D_0_13 => FF_TX_D_0_13,
- FF_TX_D_0_14 => FF_TX_D_0_14,
- FF_TX_D_0_15 => FF_TX_D_0_15,
- FF_TX_D_0_16 => FF_TX_D_0_16,
- FF_TX_D_0_17 => FF_TX_D_0_17,
- FF_TX_D_0_18 => FF_TX_D_0_18,
- FF_TX_D_0_19 => FF_TX_D_0_19,
- FF_TX_D_0_20 => FF_TX_D_0_20,
- FF_TX_D_0_21 => FF_TX_D_0_21,
- FF_TX_D_0_22 => FF_TX_D_0_22,
- FF_TX_D_0_23 => FF_TX_D_0_23,
- FF_TX_D_1_0 => FF_TX_D_1_0,
- FF_TX_D_1_1 => FF_TX_D_1_1,
- FF_TX_D_1_2 => FF_TX_D_1_2,
- FF_TX_D_1_3 => FF_TX_D_1_3,
- FF_TX_D_1_4 => FF_TX_D_1_4,
- FF_TX_D_1_5 => FF_TX_D_1_5,
- FF_TX_D_1_6 => FF_TX_D_1_6,
- FF_TX_D_1_7 => FF_TX_D_1_7,
- FF_TX_D_1_8 => FF_TX_D_1_8,
- FF_TX_D_1_9 => FF_TX_D_1_9,
- FF_TX_D_1_10 => FF_TX_D_1_10,
- FF_TX_D_1_11 => FF_TX_D_1_11,
- FF_TX_D_1_12 => FF_TX_D_1_12,
- FF_TX_D_1_13 => FF_TX_D_1_13,
- FF_TX_D_1_14 => FF_TX_D_1_14,
- FF_TX_D_1_15 => FF_TX_D_1_15,
- FF_TX_D_1_16 => FF_TX_D_1_16,
- FF_TX_D_1_17 => FF_TX_D_1_17,
- FF_TX_D_1_18 => FF_TX_D_1_18,
- FF_TX_D_1_19 => FF_TX_D_1_19,
- FF_TX_D_1_20 => FF_TX_D_1_20,
- FF_TX_D_1_21 => FF_TX_D_1_21,
- FF_TX_D_1_22 => FF_TX_D_1_22,
- FF_TX_D_1_23 => FF_TX_D_1_23,
- FF_TX_D_2_0 => FF_TX_D_2_0,
- FF_TX_D_2_1 => FF_TX_D_2_1,
- FF_TX_D_2_2 => FF_TX_D_2_2,
- FF_TX_D_2_3 => FF_TX_D_2_3,
- FF_TX_D_2_4 => FF_TX_D_2_4,
- FF_TX_D_2_5 => FF_TX_D_2_5,
- FF_TX_D_2_6 => FF_TX_D_2_6,
- FF_TX_D_2_7 => FF_TX_D_2_7,
- FF_TX_D_2_8 => FF_TX_D_2_8,
- FF_TX_D_2_9 => FF_TX_D_2_9,
- FF_TX_D_2_10 => FF_TX_D_2_10,
- FF_TX_D_2_11 => FF_TX_D_2_11,
- FF_TX_D_2_12 => FF_TX_D_2_12,
- FF_TX_D_2_13 => FF_TX_D_2_13,
- FF_TX_D_2_14 => FF_TX_D_2_14,
- FF_TX_D_2_15 => FF_TX_D_2_15,
- FF_TX_D_2_16 => FF_TX_D_2_16,
- FF_TX_D_2_17 => FF_TX_D_2_17,
- FF_TX_D_2_18 => FF_TX_D_2_18,
- FF_TX_D_2_19 => FF_TX_D_2_19,
- FF_TX_D_2_20 => FF_TX_D_2_20,
- FF_TX_D_2_21 => FF_TX_D_2_21,
- FF_TX_D_2_22 => FF_TX_D_2_22,
- FF_TX_D_2_23 => FF_TX_D_2_23,
- FF_TX_D_3_0 => FF_TX_D_3_0,
- FF_TX_D_3_1 => FF_TX_D_3_1,
- FF_TX_D_3_2 => FF_TX_D_3_2,
- FF_TX_D_3_3 => FF_TX_D_3_3,
- FF_TX_D_3_4 => FF_TX_D_3_4,
- FF_TX_D_3_5 => FF_TX_D_3_5,
- FF_TX_D_3_6 => FF_TX_D_3_6,
- FF_TX_D_3_7 => FF_TX_D_3_7,
- FF_TX_D_3_8 => FF_TX_D_3_8,
- FF_TX_D_3_9 => FF_TX_D_3_9,
- FF_TX_D_3_10 => FF_TX_D_3_10,
- FF_TX_D_3_11 => FF_TX_D_3_11,
- FF_TX_D_3_12 => FF_TX_D_3_12,
- FF_TX_D_3_13 => FF_TX_D_3_13,
- FF_TX_D_3_14 => FF_TX_D_3_14,
- FF_TX_D_3_15 => FF_TX_D_3_15,
- FF_TX_D_3_16 => FF_TX_D_3_16,
- FF_TX_D_3_17 => FF_TX_D_3_17,
- FF_TX_D_3_18 => FF_TX_D_3_18,
- FF_TX_D_3_19 => FF_TX_D_3_19,
- FF_TX_D_3_20 => FF_TX_D_3_20,
- FF_TX_D_3_21 => FF_TX_D_3_21,
- FF_TX_D_3_22 => FF_TX_D_3_22,
- FF_TX_D_3_23 => FF_TX_D_3_23,
- FF_TXI_CLK_0 => FF_TXI_CLK_0,
- FF_TXI_CLK_1 => FF_TXI_CLK_1,
- FF_TXI_CLK_2 => FF_TXI_CLK_2,
- FF_TXI_CLK_3 => FF_TXI_CLK_3,
- FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
- FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
- FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
- FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
- FFC_CK_CORE_TX => FFC_CK_CORE_TX,
- FFC_EI_EN_0 => FFC_EI_EN_0,
- FFC_EI_EN_1 => FFC_EI_EN_1,
- FFC_EI_EN_2 => FFC_EI_EN_2,
- FFC_EI_EN_3 => FFC_EI_EN_3,
- FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
- FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
- FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
- FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
- FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
- FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
- FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
- FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
- FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
- FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
- FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
- FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
- FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
- FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
- FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
- FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
- FFC_MACRO_RST => FFC_MACRO_RST,
- FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
- FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
- FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
- FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
- FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
- FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
- FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
- FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
- FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
- FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
- FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
- FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
- FFC_QUAD_RST => FFC_QUAD_RST,
- FFC_RRST_0 => FFC_RRST_0,
- FFC_RRST_1 => FFC_RRST_1,
- FFC_RRST_2 => FFC_RRST_2,
- FFC_RRST_3 => FFC_RRST_3,
- FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
- FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
- FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
- FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
- FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
- FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
- FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
- FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
- FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
- FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
- FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
- FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
- FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
- FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
- FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
- FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
- FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
- FFC_TRST => FFC_TRST,
- FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
- FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
- FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
- FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
- FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
- FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
- FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
- FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
- FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
- FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
- FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
- FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
- FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
- FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
- FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
- FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
- FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
- FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
- FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
- FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
- LDR_CORE2TX_0 => LDR_CORE2TX_0,
- LDR_CORE2TX_1 => LDR_CORE2TX_1,
- LDR_CORE2TX_2 => LDR_CORE2TX_2,
- LDR_CORE2TX_3 => LDR_CORE2TX_3,
- FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
- FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
- FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
- FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
- PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
- PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
- PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
- PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
- PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
- PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
- PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
- PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
- PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
- PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
- PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
- PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
- PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
- PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
- PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
- PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
- PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
- PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
- PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
- PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
- SCIADDR0 => SCIADDR0,
- SCIADDR1 => SCIADDR1,
- SCIADDR2 => SCIADDR2,
- SCIADDR3 => SCIADDR3,
- SCIADDR4 => SCIADDR4,
- SCIADDR5 => SCIADDR5,
- SCIENAUX => SCIENAUX,
- SCIENCH0 => SCIENCH0,
- SCIENCH1 => SCIENCH1,
- SCIENCH2 => SCIENCH2,
- SCIENCH3 => SCIENCH3,
- SCIRD => SCIRD,
- SCISELAUX => SCISELAUX,
- SCISELCH0 => SCISELCH0,
- SCISELCH1 => SCISELCH1,
- SCISELCH2 => SCISELCH2,
- SCISELCH3 => SCISELCH3,
- SCIWDATA0 => SCIWDATA0,
- SCIWDATA1 => SCIWDATA1,
- SCIWDATA2 => SCIWDATA2,
- SCIWDATA3 => SCIWDATA3,
- SCIWDATA4 => SCIWDATA4,
- SCIWDATA5 => SCIWDATA5,
- SCIWDATA6 => SCIWDATA6,
- SCIWDATA7 => SCIWDATA7,
- SCIWSTN => SCIWSTN,
- HDOUTN0 => HDOUTN0,
- HDOUTN1 => HDOUTN1,
- HDOUTN2 => HDOUTN2,
- HDOUTN3 => HDOUTN3,
- HDOUTP0 => HDOUTP0,
- HDOUTP1 => HDOUTP1,
- HDOUTP2 => HDOUTP2,
- HDOUTP3 => HDOUTP3,
- COUT19 => COUT19,
- COUT18 => COUT18,
- COUT17 => COUT17,
- COUT16 => COUT16,
- COUT15 => COUT15,
- COUT14 => COUT14,
- COUT13 => COUT13,
- COUT12 => COUT12,
- COUT11 => COUT11,
- COUT10 => COUT10,
- COUT9 => COUT9,
- COUT8 => COUT8,
- COUT7 => COUT7,
- COUT6 => COUT6,
- COUT5 => COUT5,
- COUT4 => COUT4,
- COUT3 => COUT3,
- COUT2 => COUT2,
- COUT1 => COUT1,
- COUT0 => COUT0,
- FF_RX_D_0_0 => FF_RX_D_0_0,
- FF_RX_D_0_1 => FF_RX_D_0_1,
- FF_RX_D_0_2 => FF_RX_D_0_2,
- FF_RX_D_0_3 => FF_RX_D_0_3,
- FF_RX_D_0_4 => FF_RX_D_0_4,
- FF_RX_D_0_5 => FF_RX_D_0_5,
- FF_RX_D_0_6 => FF_RX_D_0_6,
- FF_RX_D_0_7 => FF_RX_D_0_7,
- FF_RX_D_0_8 => FF_RX_D_0_8,
- FF_RX_D_0_9 => FF_RX_D_0_9,
- FF_RX_D_0_10 => FF_RX_D_0_10,
- FF_RX_D_0_11 => FF_RX_D_0_11,
- FF_RX_D_0_12 => FF_RX_D_0_12,
- FF_RX_D_0_13 => FF_RX_D_0_13,
- FF_RX_D_0_14 => FF_RX_D_0_14,
- FF_RX_D_0_15 => FF_RX_D_0_15,
- FF_RX_D_0_16 => FF_RX_D_0_16,
- FF_RX_D_0_17 => FF_RX_D_0_17,
- FF_RX_D_0_18 => FF_RX_D_0_18,
- FF_RX_D_0_19 => FF_RX_D_0_19,
- FF_RX_D_0_20 => FF_RX_D_0_20,
- FF_RX_D_0_21 => FF_RX_D_0_21,
- FF_RX_D_0_22 => FF_RX_D_0_22,
- FF_RX_D_0_23 => FF_RX_D_0_23,
- FF_RX_D_1_0 => FF_RX_D_1_0,
- FF_RX_D_1_1 => FF_RX_D_1_1,
- FF_RX_D_1_2 => FF_RX_D_1_2,
- FF_RX_D_1_3 => FF_RX_D_1_3,
- FF_RX_D_1_4 => FF_RX_D_1_4,
- FF_RX_D_1_5 => FF_RX_D_1_5,
- FF_RX_D_1_6 => FF_RX_D_1_6,
- FF_RX_D_1_7 => FF_RX_D_1_7,
- FF_RX_D_1_8 => FF_RX_D_1_8,
- FF_RX_D_1_9 => FF_RX_D_1_9,
- FF_RX_D_1_10 => FF_RX_D_1_10,
- FF_RX_D_1_11 => FF_RX_D_1_11,
- FF_RX_D_1_12 => FF_RX_D_1_12,
- FF_RX_D_1_13 => FF_RX_D_1_13,
- FF_RX_D_1_14 => FF_RX_D_1_14,
- FF_RX_D_1_15 => FF_RX_D_1_15,
- FF_RX_D_1_16 => FF_RX_D_1_16,
- FF_RX_D_1_17 => FF_RX_D_1_17,
- FF_RX_D_1_18 => FF_RX_D_1_18,
- FF_RX_D_1_19 => FF_RX_D_1_19,
- FF_RX_D_1_20 => FF_RX_D_1_20,
- FF_RX_D_1_21 => FF_RX_D_1_21,
- FF_RX_D_1_22 => FF_RX_D_1_22,
- FF_RX_D_1_23 => FF_RX_D_1_23,
- FF_RX_D_2_0 => FF_RX_D_2_0,
- FF_RX_D_2_1 => FF_RX_D_2_1,
- FF_RX_D_2_2 => FF_RX_D_2_2,
- FF_RX_D_2_3 => FF_RX_D_2_3,
- FF_RX_D_2_4 => FF_RX_D_2_4,
- FF_RX_D_2_5 => FF_RX_D_2_5,
- FF_RX_D_2_6 => FF_RX_D_2_6,
- FF_RX_D_2_7 => FF_RX_D_2_7,
- FF_RX_D_2_8 => FF_RX_D_2_8,
- FF_RX_D_2_9 => FF_RX_D_2_9,
- FF_RX_D_2_10 => FF_RX_D_2_10,
- FF_RX_D_2_11 => FF_RX_D_2_11,
- FF_RX_D_2_12 => FF_RX_D_2_12,
- FF_RX_D_2_13 => FF_RX_D_2_13,
- FF_RX_D_2_14 => FF_RX_D_2_14,
- FF_RX_D_2_15 => FF_RX_D_2_15,
- FF_RX_D_2_16 => FF_RX_D_2_16,
- FF_RX_D_2_17 => FF_RX_D_2_17,
- FF_RX_D_2_18 => FF_RX_D_2_18,
- FF_RX_D_2_19 => FF_RX_D_2_19,
- FF_RX_D_2_20 => FF_RX_D_2_20,
- FF_RX_D_2_21 => FF_RX_D_2_21,
- FF_RX_D_2_22 => FF_RX_D_2_22,
- FF_RX_D_2_23 => FF_RX_D_2_23,
- FF_RX_D_3_0 => FF_RX_D_3_0,
- FF_RX_D_3_1 => FF_RX_D_3_1,
- FF_RX_D_3_2 => FF_RX_D_3_2,
- FF_RX_D_3_3 => FF_RX_D_3_3,
- FF_RX_D_3_4 => FF_RX_D_3_4,
- FF_RX_D_3_5 => FF_RX_D_3_5,
- FF_RX_D_3_6 => FF_RX_D_3_6,
- FF_RX_D_3_7 => FF_RX_D_3_7,
- FF_RX_D_3_8 => FF_RX_D_3_8,
- FF_RX_D_3_9 => FF_RX_D_3_9,
- FF_RX_D_3_10 => FF_RX_D_3_10,
- FF_RX_D_3_11 => FF_RX_D_3_11,
- FF_RX_D_3_12 => FF_RX_D_3_12,
- FF_RX_D_3_13 => FF_RX_D_3_13,
- FF_RX_D_3_14 => FF_RX_D_3_14,
- FF_RX_D_3_15 => FF_RX_D_3_15,
- FF_RX_D_3_16 => FF_RX_D_3_16,
- FF_RX_D_3_17 => FF_RX_D_3_17,
- FF_RX_D_3_18 => FF_RX_D_3_18,
- FF_RX_D_3_19 => FF_RX_D_3_19,
- FF_RX_D_3_20 => FF_RX_D_3_20,
- FF_RX_D_3_21 => FF_RX_D_3_21,
- FF_RX_D_3_22 => FF_RX_D_3_22,
- FF_RX_D_3_23 => FF_RX_D_3_23,
- FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
- FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
- FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
- FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
- FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
- FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
- FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
- FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
- FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
- FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
- FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
- FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
- FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
- FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
- FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
- FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
- FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
- FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
- FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
- FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
- FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
- FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
- FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
- FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
- FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
- FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
- FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
- FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
- FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
- FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
- FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
- FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
- FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
- FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
- FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
- FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
- FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
- FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
- FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
- FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
- FFS_PLOL => FFS_PLOL,
- FFS_RLOL_0 => FFS_RLOL_0,
- FFS_RLOL_1 => FFS_RLOL_1,
- FFS_RLOL_2 => FFS_RLOL_2,
- FFS_RLOL_3 => FFS_RLOL_3,
- FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
- FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
- FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
- FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
- FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
- FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
- FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
- FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
- FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
- FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
- FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
- FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
- FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
- FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
- FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
- FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
- PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
- PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
- PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
- PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
- PCIE_RXVALID_0 => PCIE_RXVALID_0,
- PCIE_RXVALID_1 => PCIE_RXVALID_1,
- PCIE_RXVALID_2 => PCIE_RXVALID_2,
- PCIE_RXVALID_3 => PCIE_RXVALID_3,
- FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
- FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
- FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
- FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
- FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
- FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
- FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
- FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
- LDR_RX2CORE_0 => LDR_RX2CORE_0,
- LDR_RX2CORE_1 => LDR_RX2CORE_1,
- LDR_RX2CORE_2 => LDR_RX2CORE_2,
- LDR_RX2CORE_3 => LDR_RX2CORE_3,
- REFCK2CORE => REFCK2CORE,
- SCIINT => SCIINT,
- SCIRDATA0 => SCIRDATA0,
- SCIRDATA1 => SCIRDATA1,
- SCIRDATA2 => SCIRDATA2,
- SCIRDATA3 => SCIRDATA3,
- SCIRDATA4 => SCIRDATA4,
- SCIRDATA5 => SCIRDATA5,
- SCIRDATA6 => SCIRDATA6,
- SCIRDATA7 => SCIRDATA7,
- REFCLK_FROM_NQ => REFCLK_FROM_NQ,
- REFCLK_TO_NQ => REFCLK_TO_NQ
- );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity sfp_2_200_int is
- GENERIC (USER_CONFIG_FILE : String := "sfp_2_200_int.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
- hdinp_ch1, hdinn_ch1 : in std_logic;
- hdoutp_ch1, hdoutn_ch1 : out std_logic;
- sci_sel_ch1 : in std_logic;
- rxiclk_ch1 : in std_logic;
- txiclk_ch1 : in std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- tx_full_clk_ch1 : out std_logic;
- tx_half_clk_ch1 : out std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- txdata_ch1 : in std_logic_vector (15 downto 0);
- tx_k_ch1 : in std_logic_vector (1 downto 0);
- tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
- tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
- rxdata_ch1 : out std_logic_vector (15 downto 0);
- rx_k_ch1 : out std_logic_vector (1 downto 0);
- rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
- rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
- rx_serdes_rst_ch1_c : in std_logic;
- sb_felb_ch1_c : in std_logic;
- sb_felb_rst_ch1_c : in std_logic;
- tx_pcs_rst_ch1_c : in std_logic;
- tx_pwrup_ch1_c : in std_logic;
- rx_pcs_rst_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- rx_los_low_ch1_s : out std_logic;
- lsm_status_ch1_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- tx_div2_mode_ch1_c : in std_logic;
- rx_div2_mode_ch1_c : in std_logic;
--- CH2 --
--- CH3 --
- hdinp_ch3, hdinn_ch3 : in std_logic;
- hdoutp_ch3, hdoutn_ch3 : out std_logic;
- sci_sel_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- txdata_ch3 : in std_logic_vector (7 downto 0);
- tx_k_ch3 : in std_logic;
- tx_force_disp_ch3 : in std_logic;
- tx_disp_sel_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- rx_serdes_rst_ch3_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
- tx_pcs_rst_ch3_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pcs_rst_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
- tx_div2_mode_ch3_c : in std_logic;
- rx_div2_mode_ch3_c : in std_logic;
----- Miscillaneous ports
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- tx_sync_qd_c : in std_logic;
- rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
- serdes_rst_qd_c : in std_logic);
-
-end sfp_2_200_int;
-
-
-architecture sfp_2_200_int_arch of sfp_2_200_int is
-
-component VLO
-port (
- Z : out std_logic);
-end component;
-
-component VHI
-port (
- Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
- CONFIG_FILE : String;
- QUAD_MODE : String;
- CH0_CDR_SRC : String := "REFCLK_EXT";
- CH1_CDR_SRC : String := "REFCLK_EXT";
- CH2_CDR_SRC : String := "REFCLK_EXT";
- CH3_CDR_SRC : String := "REFCLK_EXT";
- PLL_SRC : String
- );
---synopsys translate_on
-port (
- HDINN0 : in std_logic;
- HDINN1 : in std_logic;
- HDINN2 : in std_logic;
- HDINN3 : in std_logic;
- HDINP0 : in std_logic;
- HDINP1 : in std_logic;
- HDINP2 : in std_logic;
- HDINP3 : in std_logic;
- REFCLKN : in std_logic;
- REFCLKP : in std_logic;
- CIN0 : in std_logic;
- CIN1 : in std_logic;
- CIN2 : in std_logic;
- CIN3 : in std_logic;
- CIN4 : in std_logic;
- CIN5 : in std_logic;
- CIN6 : in std_logic;
- CIN7 : in std_logic;
- CIN8 : in std_logic;
- CIN9 : in std_logic;
- CIN10 : in std_logic;
- CIN11 : in std_logic;
- CYAWSTN : in std_logic;
- FF_EBRD_CLK_0 : in std_logic;
- FF_EBRD_CLK_1 : in std_logic;
- FF_EBRD_CLK_2 : in std_logic;
- FF_EBRD_CLK_3 : in std_logic;
- FF_RXI_CLK_0 : in std_logic;
- FF_RXI_CLK_1 : in std_logic;
- FF_RXI_CLK_2 : in std_logic;
- FF_RXI_CLK_3 : in std_logic;
- FF_TX_D_0_0 : in std_logic;
- FF_TX_D_0_1 : in std_logic;
- FF_TX_D_0_2 : in std_logic;
- FF_TX_D_0_3 : in std_logic;
- FF_TX_D_0_4 : in std_logic;
- FF_TX_D_0_5 : in std_logic;
- FF_TX_D_0_6 : in std_logic;
- FF_TX_D_0_7 : in std_logic;
- FF_TX_D_0_8 : in std_logic;
- FF_TX_D_0_9 : in std_logic;
- FF_TX_D_0_10 : in std_logic;
- FF_TX_D_0_11 : in std_logic;
- FF_TX_D_0_12 : in std_logic;
- FF_TX_D_0_13 : in std_logic;
- FF_TX_D_0_14 : in std_logic;
- FF_TX_D_0_15 : in std_logic;
- FF_TX_D_0_16 : in std_logic;
- FF_TX_D_0_17 : in std_logic;
- FF_TX_D_0_18 : in std_logic;
- FF_TX_D_0_19 : in std_logic;
- FF_TX_D_0_20 : in std_logic;
- FF_TX_D_0_21 : in std_logic;
- FF_TX_D_0_22 : in std_logic;
- FF_TX_D_0_23 : in std_logic;
- FF_TX_D_1_0 : in std_logic;
- FF_TX_D_1_1 : in std_logic;
- FF_TX_D_1_2 : in std_logic;
- FF_TX_D_1_3 : in std_logic;
- FF_TX_D_1_4 : in std_logic;
- FF_TX_D_1_5 : in std_logic;
- FF_TX_D_1_6 : in std_logic;
- FF_TX_D_1_7 : in std_logic;
- FF_TX_D_1_8 : in std_logic;
- FF_TX_D_1_9 : in std_logic;
- FF_TX_D_1_10 : in std_logic;
- FF_TX_D_1_11 : in std_logic;
- FF_TX_D_1_12 : in std_logic;
- FF_TX_D_1_13 : in std_logic;
- FF_TX_D_1_14 : in std_logic;
- FF_TX_D_1_15 : in std_logic;
- FF_TX_D_1_16 : in std_logic;
- FF_TX_D_1_17 : in std_logic;
- FF_TX_D_1_18 : in std_logic;
- FF_TX_D_1_19 : in std_logic;
- FF_TX_D_1_20 : in std_logic;
- FF_TX_D_1_21 : in std_logic;
- FF_TX_D_1_22 : in std_logic;
- FF_TX_D_1_23 : in std_logic;
- FF_TX_D_2_0 : in std_logic;
- FF_TX_D_2_1 : in std_logic;
- FF_TX_D_2_2 : in std_logic;
- FF_TX_D_2_3 : in std_logic;
- FF_TX_D_2_4 : in std_logic;
- FF_TX_D_2_5 : in std_logic;
- FF_TX_D_2_6 : in std_logic;
- FF_TX_D_2_7 : in std_logic;
- FF_TX_D_2_8 : in std_logic;
- FF_TX_D_2_9 : in std_logic;
- FF_TX_D_2_10 : in std_logic;
- FF_TX_D_2_11 : in std_logic;
- FF_TX_D_2_12 : in std_logic;
- FF_TX_D_2_13 : in std_logic;
- FF_TX_D_2_14 : in std_logic;
- FF_TX_D_2_15 : in std_logic;
- FF_TX_D_2_16 : in std_logic;
- FF_TX_D_2_17 : in std_logic;
- FF_TX_D_2_18 : in std_logic;
- FF_TX_D_2_19 : in std_logic;
- FF_TX_D_2_20 : in std_logic;
- FF_TX_D_2_21 : in std_logic;
- FF_TX_D_2_22 : in std_logic;
- FF_TX_D_2_23 : in std_logic;
- FF_TX_D_3_0 : in std_logic;
- FF_TX_D_3_1 : in std_logic;
- FF_TX_D_3_2 : in std_logic;
- FF_TX_D_3_3 : in std_logic;
- FF_TX_D_3_4 : in std_logic;
- FF_TX_D_3_5 : in std_logic;
- FF_TX_D_3_6 : in std_logic;
- FF_TX_D_3_7 : in std_logic;
- FF_TX_D_3_8 : in std_logic;
- FF_TX_D_3_9 : in std_logic;
- FF_TX_D_3_10 : in std_logic;
- FF_TX_D_3_11 : in std_logic;
- FF_TX_D_3_12 : in std_logic;
- FF_TX_D_3_13 : in std_logic;
- FF_TX_D_3_14 : in std_logic;
- FF_TX_D_3_15 : in std_logic;
- FF_TX_D_3_16 : in std_logic;
- FF_TX_D_3_17 : in std_logic;
- FF_TX_D_3_18 : in std_logic;
- FF_TX_D_3_19 : in std_logic;
- FF_TX_D_3_20 : in std_logic;
- FF_TX_D_3_21 : in std_logic;
- FF_TX_D_3_22 : in std_logic;
- FF_TX_D_3_23 : in std_logic;
- FF_TXI_CLK_0 : in std_logic;
- FF_TXI_CLK_1 : in std_logic;
- FF_TXI_CLK_2 : in std_logic;
- FF_TXI_CLK_3 : in std_logic;
- FFC_CK_CORE_RX_0 : in std_logic;
- FFC_CK_CORE_RX_1 : in std_logic;
- FFC_CK_CORE_RX_2 : in std_logic;
- FFC_CK_CORE_RX_3 : in std_logic;
- FFC_CK_CORE_TX : in std_logic;
- FFC_EI_EN_0 : in std_logic;
- FFC_EI_EN_1 : in std_logic;
- FFC_EI_EN_2 : in std_logic;
- FFC_EI_EN_3 : in std_logic;
- FFC_ENABLE_CGALIGN_0 : in std_logic;
- FFC_ENABLE_CGALIGN_1 : in std_logic;
- FFC_ENABLE_CGALIGN_2 : in std_logic;
- FFC_ENABLE_CGALIGN_3 : in std_logic;
- FFC_FB_LOOPBACK_0 : in std_logic;
- FFC_FB_LOOPBACK_1 : in std_logic;
- FFC_FB_LOOPBACK_2 : in std_logic;
- FFC_FB_LOOPBACK_3 : in std_logic;
- FFC_LANE_RX_RST_0 : in std_logic;
- FFC_LANE_RX_RST_1 : in std_logic;
- FFC_LANE_RX_RST_2 : in std_logic;
- FFC_LANE_RX_RST_3 : in std_logic;
- FFC_LANE_TX_RST_0 : in std_logic;
- FFC_LANE_TX_RST_1 : in std_logic;
- FFC_LANE_TX_RST_2 : in std_logic;
- FFC_LANE_TX_RST_3 : in std_logic;
- FFC_MACRO_RST : in std_logic;
- FFC_PCI_DET_EN_0 : in std_logic;
- FFC_PCI_DET_EN_1 : in std_logic;
- FFC_PCI_DET_EN_2 : in std_logic;
- FFC_PCI_DET_EN_3 : in std_logic;
- FFC_PCIE_CT_0 : in std_logic;
- FFC_PCIE_CT_1 : in std_logic;
- FFC_PCIE_CT_2 : in std_logic;
- FFC_PCIE_CT_3 : in std_logic;
- FFC_PFIFO_CLR_0 : in std_logic;
- FFC_PFIFO_CLR_1 : in std_logic;
- FFC_PFIFO_CLR_2 : in std_logic;
- FFC_PFIFO_CLR_3 : in std_logic;
- FFC_QUAD_RST : in std_logic;
- FFC_RRST_0 : in std_logic;
- FFC_RRST_1 : in std_logic;
- FFC_RRST_2 : in std_logic;
- FFC_RRST_3 : in std_logic;
- FFC_RXPWDNB_0 : in std_logic;
- FFC_RXPWDNB_1 : in std_logic;
- FFC_RXPWDNB_2 : in std_logic;
- FFC_RXPWDNB_3 : in std_logic;
- FFC_SB_INV_RX_0 : in std_logic;
- FFC_SB_INV_RX_1 : in std_logic;
- FFC_SB_INV_RX_2 : in std_logic;
- FFC_SB_INV_RX_3 : in std_logic;
- FFC_SB_PFIFO_LP_0 : in std_logic;
- FFC_SB_PFIFO_LP_1 : in std_logic;
- FFC_SB_PFIFO_LP_2 : in std_logic;
- FFC_SB_PFIFO_LP_3 : in std_logic;
- FFC_SIGNAL_DETECT_0 : in std_logic;
- FFC_SIGNAL_DETECT_1 : in std_logic;
- FFC_SIGNAL_DETECT_2 : in std_logic;
- FFC_SIGNAL_DETECT_3 : in std_logic;
- FFC_SYNC_TOGGLE : in std_logic;
- FFC_TRST : in std_logic;
- FFC_TXPWDNB_0 : in std_logic;
- FFC_TXPWDNB_1 : in std_logic;
- FFC_TXPWDNB_2 : in std_logic;
- FFC_TXPWDNB_3 : in std_logic;
- FFC_RATE_MODE_RX_0 : in std_logic;
- FFC_RATE_MODE_RX_1 : in std_logic;
- FFC_RATE_MODE_RX_2 : in std_logic;
- FFC_RATE_MODE_RX_3 : in std_logic;
- FFC_RATE_MODE_TX_0 : in std_logic;
- FFC_RATE_MODE_TX_1 : in std_logic;
- FFC_RATE_MODE_TX_2 : in std_logic;
- FFC_RATE_MODE_TX_3 : in std_logic;
- FFC_DIV11_MODE_RX_0 : in std_logic;
- FFC_DIV11_MODE_RX_1 : in std_logic;
- FFC_DIV11_MODE_RX_2 : in std_logic;
- FFC_DIV11_MODE_RX_3 : in std_logic;
- FFC_DIV11_MODE_TX_0 : in std_logic;
- FFC_DIV11_MODE_TX_1 : in std_logic;
- FFC_DIV11_MODE_TX_2 : in std_logic;
- FFC_DIV11_MODE_TX_3 : in std_logic;
- LDR_CORE2TX_0 : in std_logic;
- LDR_CORE2TX_1 : in std_logic;
- LDR_CORE2TX_2 : in std_logic;
- LDR_CORE2TX_3 : in std_logic;
- FFC_LDR_CORE2TX_EN_0 : in std_logic;
- FFC_LDR_CORE2TX_EN_1 : in std_logic;
- FFC_LDR_CORE2TX_EN_2 : in std_logic;
- FFC_LDR_CORE2TX_EN_3 : in std_logic;
- PCIE_POWERDOWN_0_0 : in std_logic;
- PCIE_POWERDOWN_0_1 : in std_logic;
- PCIE_POWERDOWN_1_0 : in std_logic;
- PCIE_POWERDOWN_1_1 : in std_logic;
- PCIE_POWERDOWN_2_0 : in std_logic;
- PCIE_POWERDOWN_2_1 : in std_logic;
- PCIE_POWERDOWN_3_0 : in std_logic;
- PCIE_POWERDOWN_3_1 : in std_logic;
- PCIE_RXPOLARITY_0 : in std_logic;
- PCIE_RXPOLARITY_1 : in std_logic;
- PCIE_RXPOLARITY_2 : in std_logic;
- PCIE_RXPOLARITY_3 : in std_logic;
- PCIE_TXCOMPLIANCE_0 : in std_logic;
- PCIE_TXCOMPLIANCE_1 : in std_logic;
- PCIE_TXCOMPLIANCE_2 : in std_logic;
- PCIE_TXCOMPLIANCE_3 : in std_logic;
- PCIE_TXDETRX_PR2TLB_0 : in std_logic;
- PCIE_TXDETRX_PR2TLB_1 : in std_logic;
- PCIE_TXDETRX_PR2TLB_2 : in std_logic;
- PCIE_TXDETRX_PR2TLB_3 : in std_logic;
- SCIADDR0 : in std_logic;
- SCIADDR1 : in std_logic;
- SCIADDR2 : in std_logic;
- SCIADDR3 : in std_logic;
- SCIADDR4 : in std_logic;
- SCIADDR5 : in std_logic;
- SCIENAUX : in std_logic;
- SCIENCH0 : in std_logic;
- SCIENCH1 : in std_logic;
- SCIENCH2 : in std_logic;
- SCIENCH3 : in std_logic;
- SCIRD : in std_logic;
- SCISELAUX : in std_logic;
- SCISELCH0 : in std_logic;
- SCISELCH1 : in std_logic;
- SCISELCH2 : in std_logic;
- SCISELCH3 : in std_logic;
- SCIWDATA0 : in std_logic;
- SCIWDATA1 : in std_logic;
- SCIWDATA2 : in std_logic;
- SCIWDATA3 : in std_logic;
- SCIWDATA4 : in std_logic;
- SCIWDATA5 : in std_logic;
- SCIWDATA6 : in std_logic;
- SCIWDATA7 : in std_logic;
- SCIWSTN : in std_logic;
- REFCLK_FROM_NQ : in std_logic;
- HDOUTN0 : out std_logic;
- HDOUTN1 : out std_logic;
- HDOUTN2 : out std_logic;
- HDOUTN3 : out std_logic;
- HDOUTP0 : out std_logic;
- HDOUTP1 : out std_logic;
- HDOUTP2 : out std_logic;
- HDOUTP3 : out std_logic;
- COUT0 : out std_logic;
- COUT1 : out std_logic;
- COUT2 : out std_logic;
- COUT3 : out std_logic;
- COUT4 : out std_logic;
- COUT5 : out std_logic;
- COUT6 : out std_logic;
- COUT7 : out std_logic;
- COUT8 : out std_logic;
- COUT9 : out std_logic;
- COUT10 : out std_logic;
- COUT11 : out std_logic;
- COUT12 : out std_logic;
- COUT13 : out std_logic;
- COUT14 : out std_logic;
- COUT15 : out std_logic;
- COUT16 : out std_logic;
- COUT17 : out std_logic;
- COUT18 : out std_logic;
- COUT19 : out std_logic;
- FF_RX_D_0_0 : out std_logic;
- FF_RX_D_0_1 : out std_logic;
- FF_RX_D_0_2 : out std_logic;
- FF_RX_D_0_3 : out std_logic;
- FF_RX_D_0_4 : out std_logic;
- FF_RX_D_0_5 : out std_logic;
- FF_RX_D_0_6 : out std_logic;
- FF_RX_D_0_7 : out std_logic;
- FF_RX_D_0_8 : out std_logic;
- FF_RX_D_0_9 : out std_logic;
- FF_RX_D_0_10 : out std_logic;
- FF_RX_D_0_11 : out std_logic;
- FF_RX_D_0_12 : out std_logic;
- FF_RX_D_0_13 : out std_logic;
- FF_RX_D_0_14 : out std_logic;
- FF_RX_D_0_15 : out std_logic;
- FF_RX_D_0_16 : out std_logic;
- FF_RX_D_0_17 : out std_logic;
- FF_RX_D_0_18 : out std_logic;
- FF_RX_D_0_19 : out std_logic;
- FF_RX_D_0_20 : out std_logic;
- FF_RX_D_0_21 : out std_logic;
- FF_RX_D_0_22 : out std_logic;
- FF_RX_D_0_23 : out std_logic;
- FF_RX_D_1_0 : out std_logic;
- FF_RX_D_1_1 : out std_logic;
- FF_RX_D_1_2 : out std_logic;
- FF_RX_D_1_3 : out std_logic;
- FF_RX_D_1_4 : out std_logic;
- FF_RX_D_1_5 : out std_logic;
- FF_RX_D_1_6 : out std_logic;
- FF_RX_D_1_7 : out std_logic;
- FF_RX_D_1_8 : out std_logic;
- FF_RX_D_1_9 : out std_logic;
- FF_RX_D_1_10 : out std_logic;
- FF_RX_D_1_11 : out std_logic;
- FF_RX_D_1_12 : out std_logic;
- FF_RX_D_1_13 : out std_logic;
- FF_RX_D_1_14 : out std_logic;
- FF_RX_D_1_15 : out std_logic;
- FF_RX_D_1_16 : out std_logic;
- FF_RX_D_1_17 : out std_logic;
- FF_RX_D_1_18 : out std_logic;
- FF_RX_D_1_19 : out std_logic;
- FF_RX_D_1_20 : out std_logic;
- FF_RX_D_1_21 : out std_logic;
- FF_RX_D_1_22 : out std_logic;
- FF_RX_D_1_23 : out std_logic;
- FF_RX_D_2_0 : out std_logic;
- FF_RX_D_2_1 : out std_logic;
- FF_RX_D_2_2 : out std_logic;
- FF_RX_D_2_3 : out std_logic;
- FF_RX_D_2_4 : out std_logic;
- FF_RX_D_2_5 : out std_logic;
- FF_RX_D_2_6 : out std_logic;
- FF_RX_D_2_7 : out std_logic;
- FF_RX_D_2_8 : out std_logic;
- FF_RX_D_2_9 : out std_logic;
- FF_RX_D_2_10 : out std_logic;
- FF_RX_D_2_11 : out std_logic;
- FF_RX_D_2_12 : out std_logic;
- FF_RX_D_2_13 : out std_logic;
- FF_RX_D_2_14 : out std_logic;
- FF_RX_D_2_15 : out std_logic;
- FF_RX_D_2_16 : out std_logic;
- FF_RX_D_2_17 : out std_logic;
- FF_RX_D_2_18 : out std_logic;
- FF_RX_D_2_19 : out std_logic;
- FF_RX_D_2_20 : out std_logic;
- FF_RX_D_2_21 : out std_logic;
- FF_RX_D_2_22 : out std_logic;
- FF_RX_D_2_23 : out std_logic;
- FF_RX_D_3_0 : out std_logic;
- FF_RX_D_3_1 : out std_logic;
- FF_RX_D_3_2 : out std_logic;
- FF_RX_D_3_3 : out std_logic;
- FF_RX_D_3_4 : out std_logic;
- FF_RX_D_3_5 : out std_logic;
- FF_RX_D_3_6 : out std_logic;
- FF_RX_D_3_7 : out std_logic;
- FF_RX_D_3_8 : out std_logic;
- FF_RX_D_3_9 : out std_logic;
- FF_RX_D_3_10 : out std_logic;
- FF_RX_D_3_11 : out std_logic;
- FF_RX_D_3_12 : out std_logic;
- FF_RX_D_3_13 : out std_logic;
- FF_RX_D_3_14 : out std_logic;
- FF_RX_D_3_15 : out std_logic;
- FF_RX_D_3_16 : out std_logic;
- FF_RX_D_3_17 : out std_logic;
- FF_RX_D_3_18 : out std_logic;
- FF_RX_D_3_19 : out std_logic;
- FF_RX_D_3_20 : out std_logic;
- FF_RX_D_3_21 : out std_logic;
- FF_RX_D_3_22 : out std_logic;
- FF_RX_D_3_23 : out std_logic;
- FF_RX_F_CLK_0 : out std_logic;
- FF_RX_F_CLK_1 : out std_logic;
- FF_RX_F_CLK_2 : out std_logic;
- FF_RX_F_CLK_3 : out std_logic;
- FF_RX_H_CLK_0 : out std_logic;
- FF_RX_H_CLK_1 : out std_logic;
- FF_RX_H_CLK_2 : out std_logic;
- FF_RX_H_CLK_3 : out std_logic;
- FF_TX_F_CLK_0 : out std_logic;
- FF_TX_F_CLK_1 : out std_logic;
- FF_TX_F_CLK_2 : out std_logic;
- FF_TX_F_CLK_3 : out std_logic;
- FF_TX_H_CLK_0 : out std_logic;
- FF_TX_H_CLK_1 : out std_logic;
- FF_TX_H_CLK_2 : out std_logic;
- FF_TX_H_CLK_3 : out std_logic;
- FFS_CC_OVERRUN_0 : out std_logic;
- FFS_CC_OVERRUN_1 : out std_logic;
- FFS_CC_OVERRUN_2 : out std_logic;
- FFS_CC_OVERRUN_3 : out std_logic;
- FFS_CC_UNDERRUN_0 : out std_logic;
- FFS_CC_UNDERRUN_1 : out std_logic;
- FFS_CC_UNDERRUN_2 : out std_logic;
- FFS_CC_UNDERRUN_3 : out std_logic;
- FFS_LS_SYNC_STATUS_0 : out std_logic;
- FFS_LS_SYNC_STATUS_1 : out std_logic;
- FFS_LS_SYNC_STATUS_2 : out std_logic;
- FFS_LS_SYNC_STATUS_3 : out std_logic;
- FFS_CDR_TRAIN_DONE_0 : out std_logic;
- FFS_CDR_TRAIN_DONE_1 : out std_logic;
- FFS_CDR_TRAIN_DONE_2 : out std_logic;
- FFS_CDR_TRAIN_DONE_3 : out std_logic;
- FFS_PCIE_CON_0 : out std_logic;
- FFS_PCIE_CON_1 : out std_logic;
- FFS_PCIE_CON_2 : out std_logic;
- FFS_PCIE_CON_3 : out std_logic;
- FFS_PCIE_DONE_0 : out std_logic;
- FFS_PCIE_DONE_1 : out std_logic;
- FFS_PCIE_DONE_2 : out std_logic;
- FFS_PCIE_DONE_3 : out std_logic;
- FFS_PLOL : out std_logic;
- FFS_RLOL_0 : out std_logic;
- FFS_RLOL_1 : out std_logic;
- FFS_RLOL_2 : out std_logic;
- FFS_RLOL_3 : out std_logic;
- FFS_RLOS_HI_0 : out std_logic;
- FFS_RLOS_HI_1 : out std_logic;
- FFS_RLOS_HI_2 : out std_logic;
- FFS_RLOS_HI_3 : out std_logic;
- FFS_RLOS_LO_0 : out std_logic;
- FFS_RLOS_LO_1 : out std_logic;
- FFS_RLOS_LO_2 : out std_logic;
- FFS_RLOS_LO_3 : out std_logic;
- FFS_RXFBFIFO_ERROR_0 : out std_logic;
- FFS_RXFBFIFO_ERROR_1 : out std_logic;
- FFS_RXFBFIFO_ERROR_2 : out std_logic;
- FFS_RXFBFIFO_ERROR_3 : out std_logic;
- FFS_TXFBFIFO_ERROR_0 : out std_logic;
- FFS_TXFBFIFO_ERROR_1 : out std_logic;
- FFS_TXFBFIFO_ERROR_2 : out std_logic;
- FFS_TXFBFIFO_ERROR_3 : out std_logic;
- PCIE_PHYSTATUS_0 : out std_logic;
- PCIE_PHYSTATUS_1 : out std_logic;
- PCIE_PHYSTATUS_2 : out std_logic;
- PCIE_PHYSTATUS_3 : out std_logic;
- PCIE_RXVALID_0 : out std_logic;
- PCIE_RXVALID_1 : out std_logic;
- PCIE_RXVALID_2 : out std_logic;
- PCIE_RXVALID_3 : out std_logic;
- FFS_SKP_ADDED_0 : out std_logic;
- FFS_SKP_ADDED_1 : out std_logic;
- FFS_SKP_ADDED_2 : out std_logic;
- FFS_SKP_ADDED_3 : out std_logic;
- FFS_SKP_DELETED_0 : out std_logic;
- FFS_SKP_DELETED_1 : out std_logic;
- FFS_SKP_DELETED_2 : out std_logic;
- FFS_SKP_DELETED_3 : out std_logic;
- LDR_RX2CORE_0 : out std_logic;
- LDR_RX2CORE_1 : out std_logic;
- LDR_RX2CORE_2 : out std_logic;
- LDR_RX2CORE_3 : out std_logic;
- REFCK2CORE : out std_logic;
- SCIINT : out std_logic;
- SCIRDATA0 : out std_logic;
- SCIRDATA1 : out std_logic;
- SCIRDATA2 : out std_logic;
- SCIRDATA3 : out std_logic;
- SCIRDATA4 : out std_logic;
- SCIRDATA5 : out std_logic;
- SCIRDATA6 : out std_logic;
- SCIRDATA7 : out std_logic;
- REFCLK_TO_NQ : out std_logic
-);
-end component;
- attribute CONFIG_FILE: string;
- attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
- attribute QUAD_MODE: string;
- attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
- attribute PLL_SRC: string;
- attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH1_CDR_SRC: string;
- attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH3_CDR_SRC: string;
- attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
- attribute black_box_pad_pin: string;
- attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch1_sig : std_logic;
-signal tx_full_clk_ch3_sig : std_logic;
-
-signal refclk2fpga_sig : std_logic;
-signal tx_pll_lol_qd_sig : std_logic;
-signal rx_los_low_ch0_sig : std_logic;
-signal rx_los_low_ch1_sig : std_logic;
-signal rx_los_low_ch2_sig : std_logic;
-signal rx_los_low_ch3_sig : std_logic;
-signal rx_cdr_lol_ch0_sig : std_logic;
-signal rx_cdr_lol_ch1_sig : std_logic;
-signal rx_cdr_lol_ch2_sig : std_logic;
-signal rx_cdr_lol_ch3_sig : std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
- refclk2fpga <= refclk2fpga_sig;
- rx_los_low_ch1_s <= rx_los_low_ch1_sig;
- rx_los_low_ch3_s <= rx_los_low_ch3_sig;
- rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
- rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
- tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
- tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
- generic map (CONFIG_FILE => USER_CONFIG_FILE,
- QUAD_MODE => "SINGLE",
- CH1_CDR_SRC => "REFCLK_CORE",
- CH3_CDR_SRC => "REFCLK_CORE",
- PLL_SRC => "REFCLK_CORE"
- )
---synopsys translate_on
-port map (
- REFCLKP => fpsc_vlo,
- REFCLKN => fpsc_vlo,
-
------ CH0 -----
- HDOUTP0 => open,
- HDOUTN0 => open,
- HDINP0 => fpsc_vlo,
- HDINN0 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
- PCIE_RXPOLARITY_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_0 => fpsc_vlo,
- PCIE_POWERDOWN_0_1 => fpsc_vlo,
- PCIE_RXVALID_0 => open,
- PCIE_PHYSTATUS_0 => open,
- SCISELCH0 => fpsc_vlo,
- SCIENCH0 => fpsc_vlo,
- FF_RXI_CLK_0 => fpsc_vlo,
- FF_TXI_CLK_0 => fpsc_vlo,
- FF_EBRD_CLK_0 => fpsc_vlo,
- FF_RX_F_CLK_0 => open,
- FF_RX_H_CLK_0 => open,
- FF_TX_F_CLK_0 => open,
- FF_TX_H_CLK_0 => open,
- FFC_CK_CORE_RX_0 => fpsc_vlo,
- FF_TX_D_0_0 => fpsc_vlo,
- FF_TX_D_0_1 => fpsc_vlo,
- FF_TX_D_0_2 => fpsc_vlo,
- FF_TX_D_0_3 => fpsc_vlo,
- FF_TX_D_0_4 => fpsc_vlo,
- FF_TX_D_0_5 => fpsc_vlo,
- FF_TX_D_0_6 => fpsc_vlo,
- FF_TX_D_0_7 => fpsc_vlo,
- FF_TX_D_0_8 => fpsc_vlo,
- FF_TX_D_0_9 => fpsc_vlo,
- FF_TX_D_0_10 => fpsc_vlo,
- FF_TX_D_0_11 => fpsc_vlo,
- FF_TX_D_0_12 => fpsc_vlo,
- FF_TX_D_0_13 => fpsc_vlo,
- FF_TX_D_0_14 => fpsc_vlo,
- FF_TX_D_0_15 => fpsc_vlo,
- FF_TX_D_0_16 => fpsc_vlo,
- FF_TX_D_0_17 => fpsc_vlo,
- FF_TX_D_0_18 => fpsc_vlo,
- FF_TX_D_0_19 => fpsc_vlo,
- FF_TX_D_0_20 => fpsc_vlo,
- FF_TX_D_0_21 => fpsc_vlo,
- FF_TX_D_0_22 => fpsc_vlo,
- FF_TX_D_0_23 => fpsc_vlo,
- FF_RX_D_0_0 => open,
- FF_RX_D_0_1 => open,
- FF_RX_D_0_2 => open,
- FF_RX_D_0_3 => open,
- FF_RX_D_0_4 => open,
- FF_RX_D_0_5 => open,
- FF_RX_D_0_6 => open,
- FF_RX_D_0_7 => open,
- FF_RX_D_0_8 => open,
- FF_RX_D_0_9 => open,
- FF_RX_D_0_10 => open,
- FF_RX_D_0_11 => open,
- FF_RX_D_0_12 => open,
- FF_RX_D_0_13 => open,
- FF_RX_D_0_14 => open,
- FF_RX_D_0_15 => open,
- FF_RX_D_0_16 => open,
- FF_RX_D_0_17 => open,
- FF_RX_D_0_18 => open,
- FF_RX_D_0_19 => open,
- FF_RX_D_0_20 => open,
- FF_RX_D_0_21 => open,
- FF_RX_D_0_22 => open,
- FF_RX_D_0_23 => open,
-
- FFC_RRST_0 => fpsc_vlo,
- FFC_SIGNAL_DETECT_0 => fpsc_vlo,
- FFC_SB_PFIFO_LP_0 => fpsc_vlo,
- FFC_PFIFO_CLR_0 => fpsc_vlo,
- FFC_SB_INV_RX_0 => fpsc_vlo,
- FFC_PCIE_CT_0 => fpsc_vlo,
- FFC_PCI_DET_EN_0 => fpsc_vlo,
- FFC_FB_LOOPBACK_0 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
- FFC_EI_EN_0 => fpsc_vlo,
- FFC_LANE_TX_RST_0 => fpsc_vlo,
- FFC_TXPWDNB_0 => fpsc_vlo,
- FFC_LANE_RX_RST_0 => fpsc_vlo,
- FFC_RXPWDNB_0 => fpsc_vlo,
- FFS_RLOS_LO_0 => open,
- FFS_RLOS_HI_0 => open,
- FFS_PCIE_CON_0 => open,
- FFS_PCIE_DONE_0 => open,
- FFS_LS_SYNC_STATUS_0 => open,
- FFS_CC_OVERRUN_0 => open,
- FFS_CC_UNDERRUN_0 => open,
- FFS_SKP_ADDED_0 => open,
- FFS_SKP_DELETED_0 => open,
- FFS_RLOL_0 => open,
- FFS_RXFBFIFO_ERROR_0 => open,
- FFS_TXFBFIFO_ERROR_0 => open,
- LDR_CORE2TX_0 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
- LDR_RX2CORE_0 => open,
- FFS_CDR_TRAIN_DONE_0 => open,
- FFC_DIV11_MODE_TX_0 => fpsc_vlo,
- FFC_RATE_MODE_TX_0 => fpsc_vlo,
- FFC_DIV11_MODE_RX_0 => fpsc_vlo,
- FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
- HDOUTP1 => hdoutp_ch1,
- HDOUTN1 => hdoutn_ch1,
- HDINP1 => hdinp_ch1,
- HDINN1 => hdinn_ch1,
- PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
- PCIE_RXPOLARITY_1 => fpsc_vlo,
- PCIE_POWERDOWN_1_0 => fpsc_vlo,
- PCIE_POWERDOWN_1_1 => fpsc_vlo,
- PCIE_RXVALID_1 => open,
- PCIE_PHYSTATUS_1 => open,
- SCISELCH1 => sci_sel_ch1,
- SCIENCH1 => fpsc_vhi,
- FF_RXI_CLK_1 => rxiclk_ch1,
- FF_TXI_CLK_1 => txiclk_ch1,
- FF_EBRD_CLK_1 => fpsc_vlo,
- FF_RX_F_CLK_1 => rx_full_clk_ch1,
- FF_RX_H_CLK_1 => rx_half_clk_ch1,
- FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
- FF_TX_H_CLK_1 => tx_half_clk_ch1,
- FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
- FF_TX_D_1_0 => txdata_ch1(0),
- FF_TX_D_1_1 => txdata_ch1(1),
- FF_TX_D_1_2 => txdata_ch1(2),
- FF_TX_D_1_3 => txdata_ch1(3),
- FF_TX_D_1_4 => txdata_ch1(4),
- FF_TX_D_1_5 => txdata_ch1(5),
- FF_TX_D_1_6 => txdata_ch1(6),
- FF_TX_D_1_7 => txdata_ch1(7),
- FF_TX_D_1_8 => tx_k_ch1(0),
- FF_TX_D_1_9 => tx_force_disp_ch1(0),
- FF_TX_D_1_10 => tx_disp_sel_ch1(0),
- FF_TX_D_1_11 => fpsc_vlo,
- FF_TX_D_1_12 => txdata_ch1(8),
- FF_TX_D_1_13 => txdata_ch1(9),
- FF_TX_D_1_14 => txdata_ch1(10),
- FF_TX_D_1_15 => txdata_ch1(11),
- FF_TX_D_1_16 => txdata_ch1(12),
- FF_TX_D_1_17 => txdata_ch1(13),
- FF_TX_D_1_18 => txdata_ch1(14),
- FF_TX_D_1_19 => txdata_ch1(15),
- FF_TX_D_1_20 => tx_k_ch1(1),
- FF_TX_D_1_21 => tx_force_disp_ch1(1),
- FF_TX_D_1_22 => tx_disp_sel_ch1(1),
- FF_TX_D_1_23 => fpsc_vlo,
- FF_RX_D_1_0 => rxdata_ch1(0),
- FF_RX_D_1_1 => rxdata_ch1(1),
- FF_RX_D_1_2 => rxdata_ch1(2),
- FF_RX_D_1_3 => rxdata_ch1(3),
- FF_RX_D_1_4 => rxdata_ch1(4),
- FF_RX_D_1_5 => rxdata_ch1(5),
- FF_RX_D_1_6 => rxdata_ch1(6),
- FF_RX_D_1_7 => rxdata_ch1(7),
- FF_RX_D_1_8 => rx_k_ch1(0),
- FF_RX_D_1_9 => rx_disp_err_ch1(0),
- FF_RX_D_1_10 => rx_cv_err_ch1(0),
- FF_RX_D_1_11 => open,
- FF_RX_D_1_12 => rxdata_ch1(8),
- FF_RX_D_1_13 => rxdata_ch1(9),
- FF_RX_D_1_14 => rxdata_ch1(10),
- FF_RX_D_1_15 => rxdata_ch1(11),
- FF_RX_D_1_16 => rxdata_ch1(12),
- FF_RX_D_1_17 => rxdata_ch1(13),
- FF_RX_D_1_18 => rxdata_ch1(14),
- FF_RX_D_1_19 => rxdata_ch1(15),
- FF_RX_D_1_20 => rx_k_ch1(1),
- FF_RX_D_1_21 => rx_disp_err_ch1(1),
- FF_RX_D_1_22 => rx_cv_err_ch1(1),
- FF_RX_D_1_23 => open,
-
- FFC_RRST_1 => rx_serdes_rst_ch1_c,
- FFC_SIGNAL_DETECT_1 => fpsc_vlo,
- FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
- FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
- FFC_SB_INV_RX_1 => fpsc_vlo,
- FFC_PCIE_CT_1 => fpsc_vlo,
- FFC_PCI_DET_EN_1 => fpsc_vlo,
- FFC_FB_LOOPBACK_1 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
- FFC_EI_EN_1 => fpsc_vlo,
- FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
- FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
- FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
- FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
- FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
- FFS_RLOS_HI_1 => open,
- FFS_PCIE_CON_1 => open,
- FFS_PCIE_DONE_1 => open,
- FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
- FFS_CC_OVERRUN_1 => open,
- FFS_CC_UNDERRUN_1 => open,
- FFS_SKP_ADDED_1 => open,
- FFS_SKP_DELETED_1 => open,
- FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
- FFS_RXFBFIFO_ERROR_1 => open,
- FFS_TXFBFIFO_ERROR_1 => open,
- LDR_CORE2TX_1 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
- LDR_RX2CORE_1 => open,
- FFS_CDR_TRAIN_DONE_1 => open,
- FFC_DIV11_MODE_TX_1 => fpsc_vlo,
- FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
- FFC_DIV11_MODE_RX_1 => fpsc_vlo,
- FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
-
------ CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
- PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
- PCIE_RXPOLARITY_2 => fpsc_vlo,
- PCIE_POWERDOWN_2_0 => fpsc_vlo,
- PCIE_POWERDOWN_2_1 => fpsc_vlo,
- PCIE_RXVALID_2 => open,
- PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
- FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
- FF_TX_D_2_11 => fpsc_vlo,
- FF_TX_D_2_12 => fpsc_vlo,
- FF_TX_D_2_13 => fpsc_vlo,
- FF_TX_D_2_14 => fpsc_vlo,
- FF_TX_D_2_15 => fpsc_vlo,
- FF_TX_D_2_16 => fpsc_vlo,
- FF_TX_D_2_17 => fpsc_vlo,
- FF_TX_D_2_18 => fpsc_vlo,
- FF_TX_D_2_19 => fpsc_vlo,
- FF_TX_D_2_20 => fpsc_vlo,
- FF_TX_D_2_21 => fpsc_vlo,
- FF_TX_D_2_22 => fpsc_vlo,
- FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
- FF_RX_D_2_11 => open,
- FF_RX_D_2_12 => open,
- FF_RX_D_2_13 => open,
- FF_RX_D_2_14 => open,
- FF_RX_D_2_15 => open,
- FF_RX_D_2_16 => open,
- FF_RX_D_2_17 => open,
- FF_RX_D_2_18 => open,
- FF_RX_D_2_19 => open,
- FF_RX_D_2_20 => open,
- FF_RX_D_2_21 => open,
- FF_RX_D_2_22 => open,
- FF_RX_D_2_23 => open,
-
- FFC_RRST_2 => fpsc_vlo,
- FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
- FFC_SB_INV_RX_2 => fpsc_vlo,
- FFC_PCIE_CT_2 => fpsc_vlo,
- FFC_PCI_DET_EN_2 => fpsc_vlo,
- FFC_FB_LOOPBACK_2 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
- FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
- FFS_RLOS_HI_2 => open,
- FFS_PCIE_CON_2 => open,
- FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
- FFS_CC_OVERRUN_2 => open,
- FFS_CC_UNDERRUN_2 => open,
- FFS_SKP_ADDED_2 => open,
- FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
- FFS_RXFBFIFO_ERROR_2 => open,
- FFS_TXFBFIFO_ERROR_2 => open,
- LDR_CORE2TX_2 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
- LDR_RX2CORE_2 => open,
- FFS_CDR_TRAIN_DONE_2 => open,
- FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
- FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
- HDOUTP3 => hdoutp_ch3,
- HDOUTN3 => hdoutn_ch3,
- HDINP3 => hdinp_ch3,
- HDINN3 => hdinn_ch3,
- PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
- PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
- PCIE_RXPOLARITY_3 => fpsc_vlo,
- PCIE_POWERDOWN_3_0 => fpsc_vlo,
- PCIE_POWERDOWN_3_1 => fpsc_vlo,
- PCIE_RXVALID_3 => open,
- PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => sci_sel_ch3,
- SCIENCH3 => fpsc_vhi,
- FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => txiclk_ch3,
- FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => rx_full_clk_ch3,
- FF_RX_H_CLK_3 => rx_half_clk_ch3,
- FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
- FF_TX_H_CLK_3 => tx_half_clk_ch3,
- FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
- FF_TX_D_3_0 => txdata_ch3(0),
- FF_TX_D_3_1 => txdata_ch3(1),
- FF_TX_D_3_2 => txdata_ch3(2),
- FF_TX_D_3_3 => txdata_ch3(3),
- FF_TX_D_3_4 => txdata_ch3(4),
- FF_TX_D_3_5 => txdata_ch3(5),
- FF_TX_D_3_6 => txdata_ch3(6),
- FF_TX_D_3_7 => txdata_ch3(7),
- FF_TX_D_3_8 => tx_k_ch3,
- FF_TX_D_3_9 => tx_force_disp_ch3,
- FF_TX_D_3_10 => tx_disp_sel_ch3,
- FF_TX_D_3_11 => fpsc_vlo,
- FF_TX_D_3_12 => fpsc_vlo,
- FF_TX_D_3_13 => fpsc_vlo,
- FF_TX_D_3_14 => fpsc_vlo,
- FF_TX_D_3_15 => fpsc_vlo,
- FF_TX_D_3_16 => fpsc_vlo,
- FF_TX_D_3_17 => fpsc_vlo,
- FF_TX_D_3_18 => fpsc_vlo,
- FF_TX_D_3_19 => fpsc_vlo,
- FF_TX_D_3_20 => fpsc_vlo,
- FF_TX_D_3_21 => fpsc_vlo,
- FF_TX_D_3_22 => fpsc_vlo,
- FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => rxdata_ch3(0),
- FF_RX_D_3_1 => rxdata_ch3(1),
- FF_RX_D_3_2 => rxdata_ch3(2),
- FF_RX_D_3_3 => rxdata_ch3(3),
- FF_RX_D_3_4 => rxdata_ch3(4),
- FF_RX_D_3_5 => rxdata_ch3(5),
- FF_RX_D_3_6 => rxdata_ch3(6),
- FF_RX_D_3_7 => rxdata_ch3(7),
- FF_RX_D_3_8 => rx_k_ch3,
- FF_RX_D_3_9 => rx_disp_err_ch3,
- FF_RX_D_3_10 => rx_cv_err_ch3,
- FF_RX_D_3_11 => open,
- FF_RX_D_3_12 => open,
- FF_RX_D_3_13 => open,
- FF_RX_D_3_14 => open,
- FF_RX_D_3_15 => open,
- FF_RX_D_3_16 => open,
- FF_RX_D_3_17 => open,
- FF_RX_D_3_18 => open,
- FF_RX_D_3_19 => open,
- FF_RX_D_3_20 => open,
- FF_RX_D_3_21 => open,
- FF_RX_D_3_22 => open,
- FF_RX_D_3_23 => open,
-
- FFC_RRST_3 => rx_serdes_rst_ch3_c,
- FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
- FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
- FFC_SB_INV_RX_3 => fpsc_vlo,
- FFC_PCIE_CT_3 => fpsc_vlo,
- FFC_PCI_DET_EN_3 => fpsc_vlo,
- FFC_FB_LOOPBACK_3 => fpsc_vlo,
- FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
- FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
- FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
- FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
- FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
- FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
- FFS_RLOS_HI_3 => open,
- FFS_PCIE_CON_3 => open,
- FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
- FFS_CC_OVERRUN_3 => open,
- FFS_CC_UNDERRUN_3 => open,
- FFS_SKP_ADDED_3 => open,
- FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
- FFS_RXFBFIFO_ERROR_3 => open,
- FFS_TXFBFIFO_ERROR_3 => open,
- LDR_CORE2TX_3 => fpsc_vlo,
- FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
- LDR_RX2CORE_3 => open,
- FFS_CDR_TRAIN_DONE_3 => open,
- FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
- FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
-
------ Auxilliary ----
- SCIWDATA7 => sci_wrdata(7),
- SCIWDATA6 => sci_wrdata(6),
- SCIWDATA5 => sci_wrdata(5),
- SCIWDATA4 => sci_wrdata(4),
- SCIWDATA3 => sci_wrdata(3),
- SCIWDATA2 => sci_wrdata(2),
- SCIWDATA1 => sci_wrdata(1),
- SCIWDATA0 => sci_wrdata(0),
- SCIADDR5 => sci_addr(5),
- SCIADDR4 => sci_addr(4),
- SCIADDR3 => sci_addr(3),
- SCIADDR2 => sci_addr(2),
- SCIADDR1 => sci_addr(1),
- SCIADDR0 => sci_addr(0),
- SCIRDATA7 => sci_rddata(7),
- SCIRDATA6 => sci_rddata(6),
- SCIRDATA5 => sci_rddata(5),
- SCIRDATA4 => sci_rddata(4),
- SCIRDATA3 => sci_rddata(3),
- SCIRDATA2 => sci_rddata(2),
- SCIRDATA1 => sci_rddata(1),
- SCIRDATA0 => sci_rddata(0),
- SCIENAUX => fpsc_vhi,
- SCISELAUX => sci_sel_quad,
- SCIRD => sci_rd,
- SCIWSTN => sci_wrn,
- CYAWSTN => fpsc_vlo,
- SCIINT => open,
- FFC_CK_CORE_TX => fpga_txrefclk,
- FFC_MACRO_RST => serdes_rst_qd_c,
- FFC_QUAD_RST => rst_qd_c,
- FFC_TRST => tx_serdes_rst_c,
- FFS_PLOL => tx_pll_lol_qd_sig,
- FFC_SYNC_TOGGLE => tx_sync_qd_c,
- REFCK2CORE => refclk2fpga_sig,
- CIN0 => fpsc_vlo,
- CIN1 => fpsc_vlo,
- CIN2 => fpsc_vlo,
- CIN3 => fpsc_vlo,
- CIN4 => fpsc_vlo,
- CIN5 => fpsc_vlo,
- CIN6 => fpsc_vlo,
- CIN7 => fpsc_vlo,
- CIN8 => fpsc_vlo,
- CIN9 => fpsc_vlo,
- CIN10 => fpsc_vlo,
- CIN11 => fpsc_vlo,
- COUT0 => open,
- COUT1 => open,
- COUT2 => open,
- COUT3 => open,
- COUT4 => open,
- COUT5 => open,
- COUT6 => open,
- COUT7 => open,
- COUT8 => open,
- COUT9 => open,
- COUT10 => open,
- COUT11 => open,
- COUT12 => open,
- COUT13 => open,
- COUT14 => open,
- COUT15 => open,
- COUT16 => open,
- COUT17 => open,
- COUT18 => open,
- COUT19 => open,
- REFCLK_FROM_NQ => refclk_from_nq,
- REFCLK_TO_NQ => open);
-
-
-
-
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
- file_open (open_status, config, USER_CONFIG_FILE, read_mode);
- IF (open_status = name_error) THEN
- report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
- severity ERROR;
- END IF;
- wait;
-END PROCESS;
---synopsys translate_on
-end sfp_2_200_int_arch ;
+++ /dev/null
---4 channel Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_4_soda is
- generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave
- port(
- OSC_CLK : in std_logic; -- 200 MHz reference clock
- TX_DATACLK : in std_logic; -- 200 MHz data clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
--- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
-
- --Sync operation
- RX_DLM_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
- RX_DLM_WORD_OUT : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
- TX_DLM_WORD_IN : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
- LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
-
- --SFP Connection
- SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0'\r
- );
-end entity;
-
-
-architecture med_ecp3_sfp_4_soda_arch of med_ecp3_sfp_4_soda is
-
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of med_ecp3_sfp_4_soda_arch : architecture is "media_downlink_group";
- attribute syn_sharing : string;
- attribute syn_sharing of med_ecp3_sfp_4_soda_arch : architecture is "off";
-
-
-
-signal clk_200_osc : std_logic;
-signal clk_200_txdata : std_logic;
-signal rx_full_clk : std_logic_vector(3 downto 0);
-signal rx_half_clk : std_logic_vector(3 downto 0);
-signal tx_full_clk : std_logic_vector(3 downto 0);
-signal tx_half_clk : std_logic_vector(3 downto 0);
-\r
-type t_tx_state is (cRESET,cSEND_IDLE,cSEND_DLM);
-type t_tx_proc_state is array(c_HUB_CHILDREN-1 downto 0) of t_tx_state;
-signal tx_proc_state : t_tx_proc_state;
-
-signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
-signal tx_k : std_logic_vector(3 downto 0);
-signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
-signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0);
-
-signal rst_n : t_HUB_BIT;
-signal rst : t_HUB_BIT; -- PL!
-signal rx_serdes_rst : t_HUB_BIT;
-signal tx_serdes_rst : std_logic;
-signal tx_pcs_rst : t_HUB_BIT;
-signal rx_pcs_rst : t_HUB_BIT;
-signal rst_qd : t_HUB_BIT;
-signal rst_down_quad : std_logic;
-signal serdes_rst_qd : t_HUB_BIT;
-signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad
-signal sd_los_i : t_HUB_BIT; --PL!
-\r
-signal dlm_received_S : t_HUB_BIT;
-\r
-
-signal rx_los_low : t_HUB_BIT;
-signal lsm_status : t_HUB_BIT;
-signal rx_cdr_lol : t_HUB_BIT;
-signal tx_pll_lol : t_HUB_BIT;
-signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad
-
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
-signal sci_data_in_i : std_logic_vector(7 downto 0);
-signal sci_data_out_i : std_logic_vector(7 downto 0);
-signal sci_read_i : std_logic;
-signal sci_write_i : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
-signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal tx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal link_phase_S : t_HUB_BIT; --std_logic_vector(3 downto 0); --PL!
-signal request_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal start_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal request_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
-signal start_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
-signal send_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal make_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0);
-
-signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0');
-
-signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
-signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
-
-signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_reg : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state : sci_ctrl;
-signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0');
-
--- fix signal names for constraining
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_useioff : boolean;
-
-attribute syn_useioff of sd_los_i : signal is false; -- do not use an IOFF for this signal
-\r
-attribute syn_preserve of sci_ch_i : signal is true;
-attribute syn_keep of sci_ch_i : signal is true;
-attribute syn_preserve of sci_qd_i : signal is true;
-attribute syn_keep of sci_qd_i : signal is true;
-attribute syn_preserve of sci_reg_i : signal is true;
-attribute syn_keep of sci_reg_i : signal is true;
-attribute syn_preserve of sci_addr_i : signal is true;
-attribute syn_keep of sci_addr_i : signal is true;
-attribute syn_preserve of sci_data_in_i : signal is true;
-attribute syn_keep of sci_data_in_i : signal is true;
-attribute syn_preserve of sci_data_out_i : signal is true;
-attribute syn_keep of sci_data_out_i : signal is true;
-attribute syn_preserve of sci_read_i : signal is true;
-attribute syn_keep of sci_read_i : signal is true;
-attribute syn_preserve of sci_write_i : signal is true;
-attribute syn_keep of sci_write_i : signal is true;
-attribute syn_preserve of sci_write_shift_i : signal is true;
-attribute syn_keep of sci_write_shift_i : signal is true;
-attribute syn_preserve of sci_read_shift_i : signal is true;
-attribute syn_keep of sci_read_shift_i : signal is true;
-
-begin
-
-
---SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-
-clk_200_osc <= OSC_CLK; -- This external clock is oscillator/pll generated !!!
-clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!!
-
-
-gen_clocks : for i in 0 to 3 generate
-
- rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i));
- rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i));
-
- RX_HALF_CLK_OUT(i) <= rx_half_clk(i);
- RX_FULL_CLK_OUT(i) <= rx_full_clk(i);
- TX_HALF_CLK_OUT(i) <= tx_half_clk(i);
- TX_FULL_CLK_OUT(i) <= tx_full_clk(i);
-
--- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master
--- clk_200_i(i) <= rx_full_clk(i);
--- end generate;
-
--- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i(i) <= clk_200_txdata;
--- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!!
--- end generate;
-end generate;
-
--------------------------------------------------
--- Serdes
--------------------------------------------------
-THE_SERDES : entity work.serdes_4_sync_downstream
- port map(
- -- CHANNEL0 --
- hdinp_ch0 => SD_RXD_P_IN(0),
- hdinn_ch0 => SD_RXD_N_IN(0),
- hdoutp_ch0 => SD_TXD_P_OUT(0),
- hdoutn_ch0 => SD_TXD_N_OUT(0),
- rxiclk_ch0 => clk_200_txdata,
- sci_sel_ch0 => sci_ch_i(0),
- txiclk_ch0 => clk_200_txdata,
- rx_full_clk_ch0 => rx_full_clk(0),
- rx_half_clk_ch0 => rx_half_clk(0),
- tx_full_clk_ch0 => tx_full_clk(0),
- tx_half_clk_ch0 => tx_half_clk(0),
- fpga_rxrefclk_ch0 => clk_200_osc,
- txdata_ch0 => tx_data(0),
- tx_k_ch0 => tx_k(0),
- tx_force_disp_ch0 => '0',
- tx_disp_sel_ch0 => '0',
- rxdata_ch0 => rx_data(0),
- rx_k_ch0 => rx_k(0),
- rx_disp_err_ch0 => open,
- rx_cv_err_ch0 => rx_error(0),
- rx_serdes_rst_ch0_c => rx_serdes_rst(0),
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pcs_rst_ch0_c => tx_pcs_rst(0),
- tx_pwrup_ch0_c => '1',
- rx_pcs_rst_ch0_c => rx_pcs_rst(0),
- rx_pwrup_ch0_c => '1',
- rx_los_low_ch0_s => rx_los_low(0),
- lsm_status_ch0_s => lsm_status(0),
- rx_cdr_lol_ch0_s => rx_cdr_lol(0),
- tx_div2_mode_ch0_c => '0',
- rx_div2_mode_ch0_c => '0',
- -- CHANNEL1 --
- hdinp_ch1 => SD_RXD_P_IN(1),
- hdinn_ch1 => SD_RXD_N_IN(1),
- hdoutp_ch1 => SD_TXD_P_OUT(1),
- hdoutn_ch1 => SD_TXD_N_OUT(1),
- rxiclk_ch1 => clk_200_txdata,
- sci_sel_ch1 => sci_ch_i(1),
- txiclk_ch1 => clk_200_txdata,
- rx_full_clk_ch1 => rx_full_clk(1),
- rx_half_clk_ch1 => rx_half_clk(1),
- tx_full_clk_ch1 => tx_full_clk(1),
- tx_half_clk_ch1 => tx_half_clk(1),
- fpga_rxrefclk_ch1 => clk_200_osc,
- txdata_ch1 => tx_data(1),
- tx_k_ch1 => tx_k(1),
- tx_force_disp_ch1 => '0',
- tx_disp_sel_ch1 => '0',
- rxdata_ch1 => rx_data(1),
- rx_k_ch1 => rx_k(1),
- rx_disp_err_ch1 => open,
- rx_cv_err_ch1 => rx_error(1),
- rx_serdes_rst_ch1_c => rx_serdes_rst(1),
- sb_felb_ch1_c => '0',
- sb_felb_rst_ch1_c => '0',
- tx_pcs_rst_ch1_c => tx_pcs_rst(1),
- tx_pwrup_ch1_c => '1',
- rx_pcs_rst_ch1_c => rx_pcs_rst(1),
- rx_pwrup_ch1_c => '1',
- rx_los_low_ch1_s => rx_los_low(1),
- lsm_status_ch1_s => lsm_status(1),
- rx_cdr_lol_ch1_s => rx_cdr_lol(1),
- tx_div2_mode_ch1_c => '0',
- rx_div2_mode_ch1_c => '0',
- -- CHANNEL2 --
- hdinp_ch2 => SD_RXD_P_IN(2),
- hdinn_ch2 => SD_RXD_N_IN(2),
- hdoutp_ch2 => SD_TXD_P_OUT(2),
- hdoutn_ch2 => SD_TXD_N_OUT(2),
- rxiclk_ch2 => clk_200_txdata,
- sci_sel_ch2 => sci_ch_i(2),
- txiclk_ch2 => clk_200_txdata,
- rx_full_clk_ch2 => rx_full_clk(2),
- rx_half_clk_ch2 => rx_half_clk(2),
- tx_full_clk_ch2 => tx_full_clk(2),
- tx_half_clk_ch2 => tx_half_clk(2),
- fpga_rxrefclk_ch2 => clk_200_osc,
- txdata_ch2 => tx_data(2),
- tx_k_ch2 => tx_k(2),
- tx_force_disp_ch2 => '0',
- tx_disp_sel_ch2 => '0',
- rxdata_ch2 => rx_data(2),
- rx_k_ch2 => rx_k(2),
- rx_disp_err_ch2 => open,
- rx_cv_err_ch2 => rx_error(2),
- rx_serdes_rst_ch2_c => rx_serdes_rst(2),
- sb_felb_ch2_c => '0',
- sb_felb_rst_ch2_c => '0',
- tx_pcs_rst_ch2_c => tx_pcs_rst(2),
- tx_pwrup_ch2_c => '1',
- rx_pcs_rst_ch2_c => rx_pcs_rst(2),
- rx_pwrup_ch2_c => '1',
- rx_los_low_ch2_s => rx_los_low(2),
- lsm_status_ch2_s => lsm_status(2),
- rx_cdr_lol_ch2_s => rx_cdr_lol(2),
- tx_div2_mode_ch2_c => '0',
- rx_div2_mode_ch2_c => '0',
- -- CHANNEL3 --
- hdinp_ch3 => SD_RXD_P_IN(3),
- hdinn_ch3 => SD_RXD_N_IN(3),
- hdoutp_ch3 => SD_TXD_P_OUT(3),
- hdoutn_ch3 => SD_TXD_N_OUT(3),
- rxiclk_ch3 => clk_200_txdata,
- sci_sel_ch3 => sci_ch_i(3),
- txiclk_ch3 => clk_200_txdata,
- rx_full_clk_ch3 => rx_full_clk(3),
- rx_half_clk_ch3 => rx_half_clk(3),
- tx_full_clk_ch3 => tx_full_clk(3),
- tx_half_clk_ch3 => tx_half_clk(3),
- fpga_rxrefclk_ch3 => clk_200_osc,
- txdata_ch3 => tx_data(3),
- tx_k_ch3 => tx_k(3),
- tx_force_disp_ch3 => '0',
- tx_disp_sel_ch3 => '0',
- rxdata_ch3 => rx_data(3),
- rx_k_ch3 => rx_k(3),
- rx_disp_err_ch3 => open,
- rx_cv_err_ch3 => rx_error(3),
- rx_serdes_rst_ch3_c => rx_serdes_rst(3),
- sb_felb_ch3_c => '0',
- sb_felb_rst_ch3_c => '0',
- tx_pcs_rst_ch3_c => tx_pcs_rst(3),
- tx_pwrup_ch3_c => '1',
- rx_pcs_rst_ch3_c => rx_pcs_rst(3),
- rx_pwrup_ch3_c => '1',
- rx_los_low_ch3_s => rx_los_low(3),
- lsm_status_ch3_s => lsm_status(3),
- rx_cdr_lol_ch3_s => rx_cdr_lol(3),
- tx_div2_mode_ch3_c => '0',
- rx_div2_mode_ch3_c => '0',
- -- COMMON --
- sci_wrdata => sci_data_in_i,
- sci_rddata => sci_data_out_i,
- sci_addr => sci_addr_i(5 downto 0),
- sci_sel_quad => sci_qd_i,
- sci_rd => sci_read_i,
- sci_wrn => sci_write_i,
-
- fpga_txrefclk => clk_200_txdata,
- tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906
- tx_pll_lol_qd_s => tx_pll_lol_quad,
- tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols
- rst_qd_c => rst_down_quad,
- serdes_rst_qd_c => serdes_rst_down_quad
- );
-
--------------------------
--- combined quad reset --
--------------------------
---rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
-rst_down_quad <= RESET; -- PL: 18/06/14
---serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
-serdes_rst_down_quad <= '0'; -- PL: 23/06/14
-
-generated_logic : for i in 0 to 3 generate
-
--- SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready
- SD_TXDIS_OUT(i) <= '0'; --not rx_allow_q(i); --slave only switches on when RX is ready
-
- tx_pll_lol(i) <= tx_pll_lol_quad;
-
- -------------------------------------------------
- -- Reset FSM & Link states
- -------------------------------------------------
- THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n(i),
- RX_REFCLK => rx_full_clk(i),
- TX_PLL_LOL_QD_S => tx_pll_lol(i),
- RX_SERDES_RST_CH_C => rx_serdes_rst(i),
- RX_CDR_LOL_CH_S => rx_cdr_lol(i),
- RX_LOS_LOW_CH_S => rx_los_low(i),
- RX_PCS_RST_CH_C => rx_pcs_rst(i),
- WA_POSITION => wa_position_rx(i),
- STATE_OUT => rx_fsm_state(i)
- );
-
- THE_TX_RESET_FSM : tx_reset_fsm
- port map(
- RST_N => rst_n(i),
- TX_REFCLK => clk_200_txdata,
- TX_PLL_LOL_QD_S => tx_pll_lol(i),
- RST_QD_C => rst_qd(i),
- TX_PCS_RST_CH_C => tx_pcs_rst(i),
- STATE_OUT => tx_fsm_state(i)
- );
-
-
- -- Master does not do bit-locking
- wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
-
-
- PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i))
- begin
- if rising_edge(clk_200_txdata) then -- clk_200_txdata ??
- if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
- rx_allow(i) <= '1';
- tx_allow(i) <= '1';
- else
- rx_allow(i) <= '0';
- tx_allow(i) <= '1';
- end if;
- end if;
- end process;
-
- rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK);
- tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
-
-
- PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i))
- begin
- if rising_edge(clk_200_txdata) then
- if got_link_ready_i(i) = '1' then
- if start_timer(i)(start_timer'left) = '0' then
- start_timer(i) <= start_timer(i) + 1;
- end if;
- else
- start_timer(i) <= (others => '0');
- end if;
- end if;
- end process;
- -------------------------------------------------
- -- TX Data
- -------------------------------------------------
- the_tx_fsm : process(clk_200_txdata)
- begin
- if rising_edge(clk_200_txdata) then
- if (RESET='1') then\r
- tx_proc_state(i) <= cRESET;
- tx_data(i) <= x"00"; -- idle
- tx_k(i) <= '0'; \r
- link_phase_S(i) <= c_PHASE_L;
- else
- link_phase_S(i) <= not(link_phase_S(i));
- case tx_proc_state(i) is
- when cSEND_IDLE =>
- if (TX_DLM_IN(i)='0') then
- tx_proc_state(i) <= cSEND_IDLE;
- tx_data(i) <= x"BC"; -- idle
- tx_k(i) <= '1';
- else
- tx_proc_state(i) <= cSEND_DLM;
- tx_data(i) <= x"DC"; -- dlm
- tx_k(i) <= '1';
- end if;
- when cSEND_DLM =>
- tx_proc_state(i) <= cSEND_IDLE;
- tx_data(i) <= TX_DLM_WORD_IN(i);
- tx_k(i) <= '0';
- when others =>
- tx_proc_state(i) <= cSEND_IDLE;
- tx_data(i) <= x"BC"; -- idle
- tx_k(i) <= '1';
- end case;
- end if;\r
- end if;
- end process;
--- THE_TX : soda_tx_control
--- port map(
--- CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i),
--- CLK_100 => SYSCLK,
--- RESET_IN => rst(i), --CLEAR, PL!
---
--- TX_DATA_IN => (others => '0'), -- MED_DATA_IN(i),
--- TX_PACKET_NUMBER_IN => (others => '0'), -- MED_PACKET_NUM_IN(i),
--- TX_WRITE_IN => '0', -- MED_DATAREADY_IN(i),
--- TX_READ_OUT => open, -- MED_READ_OUT(i),
---
--- TX_DATA_OUT => tx_data(i),
--- TX_K_OUT => tx_k(i),
---
--- REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO
--- REQUEST_POSITION_IN => request_retr_position_i(i), --TODO
---
--- START_RETRANSMIT_IN => start_retr_i(i), --TODO
--- START_POSITION_IN => request_retr_position_i(i), --TODO
---
--- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i),
--- SEND_DLM => TX_DLM_IN(i),
--- SEND_DLM_WORD => TX_DLM_WORD_IN(i),
---
--- SEND_LINK_RESET_IN => '0', --CTRL_OP(i)(15),
--- TX_ALLOW_IN => tx_allow(i),
--- RX_ALLOW_IN => rx_allow(i),
--- LINK_PHASE_OUT => link_phase_S(i), --PL!
---
--- DEBUG_OUT => debug_tx_control_i(i),
--- STAT_REG_OUT => stat_tx_control_i(i)
--- );
-
- LINK_PHASE_OUT(i) <= link_phase_S(i); --PL!\r
- \r
-
- -------------------------------------------------
- -- RX Data
- -------------------------------------------------\r
- the_rx_proc : process(clk_200_txdata)
- begin
- if rising_edge(clk_200_txdata) then
- RX_DLM_OUT(i) <= '0';
- if dlm_received_S(i)='1' then
- dlm_received_S(i) <= '0';
- RX_DLM_OUT(i) <= '1';
- RX_DLM_WORD_OUT(i) <= rx_data(i);
- elsif (rx_data(i)=x"DC") and (rx_k(i)='1') then
- dlm_received_S(i) <= '1';
- end if;
- end if;
- end process;
--- THE_RX_CONTROL : rx_control
--- port map(
--- CLK_200 => clk_200_txdata, --clk_200_i(i), --PL!
--- CLK_100 => SYSCLK,
--- RESET_IN => rst(i), --CLEAR, PL!
---
--- RX_DATA_OUT => open, -- MED_DATA_OUT(i),
--- RX_PACKET_NUMBER_OUT => open, -- MED_PACKET_NUM_OUT(i),
--- RX_WRITE_OUT => open, -- MED_DATAREADY_OUT(i),
--- RX_READ_IN => '0', -- MED_READ_IN(i),
---
--- RX_DATA_IN => rx_data(i),
--- RX_K_IN => rx_k(i),
---
--- REQUEST_RETRANSMIT_OUT => request_retr_i(i),
--- REQUEST_POSITION_OUT => request_retr_position_i(i),
---
--- START_RETRANSMIT_OUT => start_retr_i(i),
--- START_POSITION_OUT => start_retr_position_i(i),
---
--- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
--- RX_DLM => RX_DLM_OUT(i),
--- RX_DLM_WORD => RX_DLM_WORD_OUT(i),
---
--- SEND_LINK_RESET_OUT => send_link_reset_i(i),
--- MAKE_RESET_OUT => make_link_reset_i(i),
--- RX_ALLOW_IN => rx_allow(i),
--- GOT_LINK_READY => got_link_ready_i(i),
---
--- DEBUG_OUT => debug_rx_control_i(i),
--- STAT_REG_OUT => stat_rx_control_i(i)
--- );
-
- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); --PL! 200115
-
-end generate;
-
--------------------------------------------------
--- SCI
--------------------------------------------------
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process
-variable cnt : integer range 0 to 4 := 0;
-begin
-wait until rising_edge(SYSCLK);
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer(0) <= sci_timer(0) + 1;
- sci_timer(1) <= sci_timer(1) + 1;
- sci_timer(2) <= sci_timer(2) + 1;
- sci_timer(3) <= sci_timer(3) + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- else
- if sci_timer(0)(sci_timer'left) = '1' then
- sci_timer(0) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(1)(sci_timer'left) = '1' then
- sci_timer(1) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(2)(sci_timer'left) = '1' then
- sci_timer(2) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(3)(sci_timer'left) = '1' then
- sci_timer(3) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- end if;
-when SCTRL =>
- if sci_reg_i = '1' then
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
-when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
-when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
-when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
-when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
-when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
-when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
-when GET_WA_FINISH =>
--- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- wa_position(cnt) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
-end case;
-
-if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
-else
- SCI_NACK <= '0';
-end if;
-
-end process;
-
-
-
-end med_ecp3_sfp_4_soda_arch;
\ No newline at end of file
+++ /dev/null
---4 channel Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_4_sync_down is
- generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave
- port(
- OSC_CLK : in std_logic; -- 200 MHz reference clock
- TX_DATACLK : in std_logic; -- 200 MHz data clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- --Internal Connection TX
- MED_DATA_IN : in t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in t_HUB_NUM; --std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
- MED_READ_OUT : out std_logic_vector(3 downto 0) := (others => '0');
- --Internal Connection RX
- MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0');
- MED_READ_IN : in std_logic_vector(3 downto 0);
- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
-
- --Sync operation
- RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
- RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
- TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
- LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
-
- --SFP Connection
- SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
- -- Status and control port
--- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
--- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
- STAT_OP : out std_logic_vector (63 downto 0);
- CTRL_OP : in std_logic_vector (63 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
-end entity;
-
-
-architecture med_ecp3_sfp_4_sync_down_arch of med_ecp3_sfp_4_sync_down is
-
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of med_ecp3_sfp_4_sync_down_arch : architecture is "media_downlink_group";
- attribute syn_sharing : string;
- attribute syn_sharing of med_ecp3_sfp_4_sync_down_arch : architecture is "off";
- attribute syn_hier : string;\r
- attribute syn_hier of med_ecp3_sfp_4_sync_down_arch : architecture is "hard";\r
-
-signal clk_200_osc : std_logic;
-signal clk_200_txdata : std_logic;
-signal clk_200_rxdn : std_logic_vector(3 downto 0);
-signal clk_200_i : std_logic_vector(3 downto 0);
-signal rx_full_clk : std_logic_vector(3 downto 0);
-signal rx_half_clk : std_logic_vector(3 downto 0);
-signal tx_full_clk : std_logic_vector(3 downto 0);
-signal tx_half_clk : std_logic_vector(3 downto 0);
-
-signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
-signal tx_k : std_logic_vector(3 downto 0);
-signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
-signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0);
-
-signal rst_n : t_HUB_BIT;
-signal rst : t_HUB_BIT; -- PL!
-signal rx_serdes_rst : t_HUB_BIT;
-signal tx_serdes_rst : std_logic;
-signal tx_pcs_rst : t_HUB_BIT;
-signal rx_pcs_rst : t_HUB_BIT;
-signal rst_qd : t_HUB_BIT;
-signal rst_down_quad : std_logic;
-signal serdes_rst_qd : t_HUB_BIT;
-signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad
-signal sd_los_i : t_HUB_BIT; --PL!
-
-signal rx_los_low : t_HUB_BIT;
-signal lsm_status : t_HUB_BIT;
-signal rx_cdr_lol : t_HUB_BIT;
-signal tx_pll_lol : t_HUB_BIT;
-signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad
-
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
-signal sci_data_in_i : std_logic_vector(7 downto 0);
-signal sci_data_out_i : std_logic_vector(7 downto 0);
-signal sci_read_i : std_logic;
-signal sci_write_i : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
-signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal tx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal link_phase_S : t_HUB_BIT; --std_logic_vector(3 downto 0); --PL!
-signal request_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal start_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal request_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
-signal start_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
-signal send_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal make_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0);
-
-signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0');
-signal watchdog_timer : t_HUB_TIMER21 := (others => (others => '0')); --unsigned(20 downto 0) := (others => '0');
-signal watchdog_trigger : t_HUB_BIT := (others => '0'); --std_logic_vector(3 downto 0) := (others => '0');
-
-signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
-signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
-
-signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_reg : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state : sci_ctrl;
-signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0');
-\r
--- fix signal names for constraining
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_useioff : boolean;
-
-attribute syn_useioff of sd_los_i : signal is false; -- do not use an IOFF for this signal
-\r
-attribute syn_preserve of sci_ch_i : signal is true;
-attribute syn_keep of sci_ch_i : signal is true;
-attribute syn_preserve of sci_qd_i : signal is true;
-attribute syn_keep of sci_qd_i : signal is true;
-attribute syn_preserve of sci_reg_i : signal is true;
-attribute syn_keep of sci_reg_i : signal is true;
-attribute syn_preserve of sci_addr_i : signal is true;
-attribute syn_keep of sci_addr_i : signal is true;
-attribute syn_preserve of sci_data_in_i : signal is true;
-attribute syn_keep of sci_data_in_i : signal is true;
-attribute syn_preserve of sci_data_out_i : signal is true;
-attribute syn_keep of sci_data_out_i : signal is true;
-attribute syn_preserve of sci_read_i : signal is true;
-attribute syn_keep of sci_read_i : signal is true;
-attribute syn_preserve of sci_write_i : signal is true;
-attribute syn_keep of sci_write_i : signal is true;
-attribute syn_preserve of sci_write_shift_i : signal is true;
-attribute syn_keep of sci_write_shift_i : signal is true;
-attribute syn_preserve of sci_read_shift_i : signal is true;
-attribute syn_keep of sci_read_shift_i : signal is true;
-
-begin
-
-
---SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-
-clk_200_osc <= OSC_CLK; -- This external clock is oscillator/pll generated !!!
-clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!!
-
-
-gen_clocks : for i in 0 to 3 generate
-
- rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
- rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
-
- RX_HALF_CLK_OUT(i) <= rx_half_clk(i);
- RX_FULL_CLK_OUT(i) <= rx_full_clk(i);
- TX_HALF_CLK_OUT(i) <= tx_half_clk(i);
- TX_FULL_CLK_OUT(i) <= tx_full_clk(i);
-
--- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master
--- clk_200_i(i) <= rx_full_clk(i);
--- end generate;
-
--- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i(i) <= clk_200_txdata;
--- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!!
--- end generate;
-end generate;
-
--------------------------------------------------
--- Serdes
--------------------------------------------------
-THE_SERDES : entity work.serdes_4_sync_downstream
- port map(
- -- CHANNEL0 --
- hdinp_ch0 => SD_RXD_P_IN(0),
- hdinn_ch0 => SD_RXD_N_IN(0),
- hdoutp_ch0 => SD_TXD_P_OUT(0),
- hdoutn_ch0 => SD_TXD_N_OUT(0),
- rxiclk_ch0 => clk_200_txdata, --clk_200_i(0),
- sci_sel_ch0 => sci_ch_i(0),
- txiclk_ch0 => clk_200_txdata,
- rx_full_clk_ch0 => rx_full_clk(0),
- rx_half_clk_ch0 => rx_half_clk(0),
- tx_full_clk_ch0 => tx_full_clk(0),
- tx_half_clk_ch0 => tx_half_clk(0),
- fpga_rxrefclk_ch0 => clk_200_osc,
- txdata_ch0 => tx_data(0),
- tx_k_ch0 => tx_k(0),
- tx_force_disp_ch0 => '0',
- tx_disp_sel_ch0 => '0',
- rxdata_ch0 => rx_data(0),
- rx_k_ch0 => rx_k(0),
- rx_disp_err_ch0 => open,
- rx_cv_err_ch0 => rx_error(0),
- rx_serdes_rst_ch0_c => rx_serdes_rst(0),
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pcs_rst_ch0_c => tx_pcs_rst(0),
- tx_pwrup_ch0_c => '1',
- rx_pcs_rst_ch0_c => rx_pcs_rst(0),
- rx_pwrup_ch0_c => '1',
- rx_los_low_ch0_s => rx_los_low(0),
- lsm_status_ch0_s => lsm_status(0),
- rx_cdr_lol_ch0_s => rx_cdr_lol(0),
- tx_div2_mode_ch0_c => '0',
- rx_div2_mode_ch0_c => '0',
- -- CHANNEL1 --
- hdinp_ch1 => SD_RXD_P_IN(1),
- hdinn_ch1 => SD_RXD_N_IN(1),
- hdoutp_ch1 => SD_TXD_P_OUT(1),
- hdoutn_ch1 => SD_TXD_N_OUT(1),
- rxiclk_ch1 => clk_200_txdata, --clk_200_i(1),
- sci_sel_ch1 => sci_ch_i(1),
- txiclk_ch1 => clk_200_txdata,
- rx_full_clk_ch1 => rx_full_clk(1),
- rx_half_clk_ch1 => rx_half_clk(1),
- tx_full_clk_ch1 => tx_full_clk(1),
- tx_half_clk_ch1 => tx_half_clk(1),
- fpga_rxrefclk_ch1 => clk_200_osc,
- txdata_ch1 => tx_data(1),
- tx_k_ch1 => tx_k(1),
- tx_force_disp_ch1 => '0',
- tx_disp_sel_ch1 => '0',
- rxdata_ch1 => rx_data(1),
- rx_k_ch1 => rx_k(1),
- rx_disp_err_ch1 => open,
- rx_cv_err_ch1 => rx_error(1),
- rx_serdes_rst_ch1_c => rx_serdes_rst(1),
- sb_felb_ch1_c => '0',
- sb_felb_rst_ch1_c => '0',
- tx_pcs_rst_ch1_c => tx_pcs_rst(1),
- tx_pwrup_ch1_c => '1',
- rx_pcs_rst_ch1_c => rx_pcs_rst(1),
- rx_pwrup_ch1_c => '1',
- rx_los_low_ch1_s => rx_los_low(1),
- lsm_status_ch1_s => lsm_status(1),
- rx_cdr_lol_ch1_s => rx_cdr_lol(1),
- tx_div2_mode_ch1_c => '0',
- rx_div2_mode_ch1_c => '0',
- -- CHANNEL2 --
- hdinp_ch2 => SD_RXD_P_IN(2),
- hdinn_ch2 => SD_RXD_N_IN(2),
- hdoutp_ch2 => SD_TXD_P_OUT(2),
- hdoutn_ch2 => SD_TXD_N_OUT(2),
- rxiclk_ch2 => clk_200_txdata, --clk_200_i(2),
- sci_sel_ch2 => sci_ch_i(2),
- txiclk_ch2 => clk_200_txdata,
- rx_full_clk_ch2 => rx_full_clk(2),
- rx_half_clk_ch2 => rx_half_clk(2),
- tx_full_clk_ch2 => tx_full_clk(2),
- tx_half_clk_ch2 => tx_half_clk(2),
- fpga_rxrefclk_ch2 => clk_200_osc,
- txdata_ch2 => tx_data(2),
- tx_k_ch2 => tx_k(2),
- tx_force_disp_ch2 => '0',
- tx_disp_sel_ch2 => '0',
- rxdata_ch2 => rx_data(2),
- rx_k_ch2 => rx_k(2),
- rx_disp_err_ch2 => open,
- rx_cv_err_ch2 => rx_error(2),
- rx_serdes_rst_ch2_c => rx_serdes_rst(2),
- sb_felb_ch2_c => '0',
- sb_felb_rst_ch2_c => '0',
- tx_pcs_rst_ch2_c => tx_pcs_rst(2),
- tx_pwrup_ch2_c => '1',
- rx_pcs_rst_ch2_c => rx_pcs_rst(2),
- rx_pwrup_ch2_c => '1',
- rx_los_low_ch2_s => rx_los_low(2),
- lsm_status_ch2_s => lsm_status(2),
- rx_cdr_lol_ch2_s => rx_cdr_lol(2),
- tx_div2_mode_ch2_c => '0',
- rx_div2_mode_ch2_c => '0',
- -- CHANNEL3 --
- hdinp_ch3 => SD_RXD_P_IN(3),
- hdinn_ch3 => SD_RXD_N_IN(3),
- hdoutp_ch3 => SD_TXD_P_OUT(3),
- hdoutn_ch3 => SD_TXD_N_OUT(3),
- rxiclk_ch3 => clk_200_txdata, --clk_200_i(3),
- sci_sel_ch3 => sci_ch_i(3),
- txiclk_ch3 => clk_200_txdata,
- rx_full_clk_ch3 => rx_full_clk(3),
- rx_half_clk_ch3 => rx_half_clk(3),
- tx_full_clk_ch3 => tx_full_clk(3),
- tx_half_clk_ch3 => tx_half_clk(3),
- fpga_rxrefclk_ch3 => clk_200_osc,
- txdata_ch3 => tx_data(3),
- tx_k_ch3 => tx_k(3),
- tx_force_disp_ch3 => '0',
- tx_disp_sel_ch3 => '0',
- rxdata_ch3 => rx_data(3),
- rx_k_ch3 => rx_k(3),
- rx_disp_err_ch3 => open,
- rx_cv_err_ch3 => rx_error(3),
- rx_serdes_rst_ch3_c => rx_serdes_rst(3),
- sb_felb_ch3_c => '0',
- sb_felb_rst_ch3_c => '0',
- tx_pcs_rst_ch3_c => tx_pcs_rst(3),
- tx_pwrup_ch3_c => '1',
- rx_pcs_rst_ch3_c => rx_pcs_rst(3),
- rx_pwrup_ch3_c => '1',
- rx_los_low_ch3_s => rx_los_low(3),
- lsm_status_ch3_s => lsm_status(3),
- rx_cdr_lol_ch3_s => rx_cdr_lol(3),
- tx_div2_mode_ch3_c => '0',
- rx_div2_mode_ch3_c => '0',
- -- COMMON --
- sci_wrdata => sci_data_in_i,
- sci_rddata => sci_data_out_i,
- sci_addr => sci_addr_i(5 downto 0),
- sci_sel_quad => sci_qd_i,
- sci_rd => sci_read_i,
- sci_wrn => sci_write_i,
-
- fpga_txrefclk => clk_200_txdata,
- tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906
- tx_pll_lol_qd_s => tx_pll_lol_quad,
- tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols
- rst_qd_c => rst_down_quad,
- serdes_rst_qd_c => serdes_rst_down_quad
- );
-
--------------------------
--- combined quad reset --
--------------------------
---rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
-rst_down_quad <= RESET; -- PL: 18/06/14
---serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
-serdes_rst_down_quad <= '0'; -- PL: 23/06/14
-
-generated_logic : for i in 0 to 3 generate
-
- SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready
-
- tx_pll_lol(i) <= tx_pll_lol_quad;
-
- -------------------------------------------------
- -- Reset FSM & Link states
- -------------------------------------------------
- THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n(i),
- RX_REFCLK => rx_full_clk(i),
- TX_PLL_LOL_QD_S => tx_pll_lol(i),
- RX_SERDES_RST_CH_C => rx_serdes_rst(i),
- RX_CDR_LOL_CH_S => rx_cdr_lol(i),
- RX_LOS_LOW_CH_S => rx_los_low(i),
- RX_PCS_RST_CH_C => rx_pcs_rst(i),
- WA_POSITION => wa_position_rx(i),
- STATE_OUT => rx_fsm_state(i)
- );
-
- THE_TX_FSM : tx_reset_fsm
- port map(
- RST_N => rst_n(i),
- TX_REFCLK => clk_200_txdata,
- TX_PLL_LOL_QD_S => tx_pll_lol(i),
- RST_QD_C => rst_qd(i),
- TX_PCS_RST_CH_C => tx_pcs_rst(i),
- STATE_OUT => tx_fsm_state(i)
- );
-
-
- -- Master does not do bit-locking
- wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
-
-
- PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i))
- begin
- if rising_edge(clk_200_txdata) then -- clk_200_txdata ??
- if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
- rx_allow(i) <= '1';
- tx_allow(i) <= '1';
- else
- rx_allow(i) <= '0';
- tx_allow(i) <= '1';
- end if;
- end if;
- end process;
-
- rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK);
- tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
-
-
- PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i))
- begin
- if rising_edge(clk_200_txdata) then
- if got_link_ready_i(i) = '1' then
- watchdog_timer(i) <= (others => '0');
- if start_timer(i)(start_timer'left) = '0' then
- start_timer(i) <= start_timer(i) + 1;
--- start_timer(i)(start_timer'left downto 0) <= start_timer(i)(start_timer'left downto 0) + 1;
- end if;
- else
- start_timer(i) <= (others => '0');
- if ((watchdog_timer(i)(watchdog_timer(i)'left) = '1') and (watchdog_timer(i)(watchdog_timer(i)'left - 1) = '1')) then
- watchdog_trigger(i) <= '1';
- else
- watchdog_trigger(i) <= '0';
- end if;
- if watchdog_trigger(i) = '0' then
- watchdog_timer(i) <= watchdog_timer(i) + 1;
- else
- watchdog_timer(i) <= (others => '0');
- end if;
- end if;
- end if;
- end process;
- -------------------------------------------------
- -- TX Data
- -------------------------------------------------
- THE_TX : soda_tx_control
- port map(
- CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i),
- CLK_100 => SYSCLK,
- RESET_IN => rst(i), --CLEAR, PL!
-
- TX_DATA_IN => MED_DATA_IN(i),
- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN(i),
- TX_WRITE_IN => MED_DATAREADY_IN(i),
- TX_READ_OUT => MED_READ_OUT(i),
-
- TX_DATA_OUT => tx_data(i),
- TX_K_OUT => tx_k(i),
-
- REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO
- REQUEST_POSITION_IN => request_retr_position_i(i), --TODO
-
- START_RETRANSMIT_IN => start_retr_i(i), --TODO
- START_POSITION_IN => request_retr_position_i(i), --TODO
-
- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i),
- SEND_DLM => TX_DLM(i),
- SEND_DLM_WORD => TX_DLM_WORD(i),
-
- SEND_LINK_RESET_IN => CTRL_OP(i*16 + 15), --CTRL_OP(i)(15),
- TX_ALLOW_IN => tx_allow(i),
- RX_ALLOW_IN => rx_allow(i),
- LINK_PHASE_OUT => link_phase_S(i), --PL!
-
- DEBUG_OUT => debug_tx_control_i(i),
- STAT_REG_OUT => stat_tx_control_i(i)
- );
-
- LINK_PHASE_OUT(i) <= link_phase_S(i); --PL!
- -------------------------------------------------
- -- RX Data
- -------------------------------------------------
- THE_RX_CONTROL : rx_control
- port map(
- CLK_200 => clk_200_txdata, --clk_200_i(i), --PL!
- CLK_100 => SYSCLK,
- RESET_IN => rst(i), --CLEAR, PL!
-
- RX_DATA_OUT => MED_DATA_OUT(i),
- RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT(i),
- RX_WRITE_OUT => MED_DATAREADY_OUT(i),
- RX_READ_IN => MED_READ_IN(i),
-
- RX_DATA_IN => rx_data(i),
- RX_K_IN => rx_k(i),
-
- REQUEST_RETRANSMIT_OUT => request_retr_i(i),
- REQUEST_POSITION_OUT => request_retr_position_i(i),
-
- START_RETRANSMIT_OUT => start_retr_i(i),
- START_POSITION_OUT => start_retr_position_i(i),
-
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
- RX_DLM => RX_DLM(i),
- RX_DLM_WORD => RX_DLM_WORD(i),
-
- SEND_LINK_RESET_OUT => send_link_reset_i(i),
- MAKE_RESET_OUT => make_link_reset_i(i),
- RX_ALLOW_IN => rx_allow(i),
- GOT_LINK_READY => got_link_ready_i(i),
-
- DEBUG_OUT => debug_rx_control_i(i),
- STAT_REG_OUT => stat_rx_control_i(i)
- );
-
- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(clk_200_txdata);\r
-\r
-end generate;
-
--------------------------------------------------
--- SCI
--------------------------------------------------
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process
-variable cnt : integer range 0 to 4 := 0;
-begin
-wait until rising_edge(SYSCLK);\r
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer(0) <= sci_timer(0) + 1;
- sci_timer(1) <= sci_timer(1) + 1;
- sci_timer(2) <= sci_timer(2) + 1;
- sci_timer(3) <= sci_timer(3) + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- else
- if sci_timer(0)(sci_timer'left) = '1' then
- sci_timer(0) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(1)(sci_timer'left) = '1' then
- sci_timer(1) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(2)(sci_timer'left) = '1' then
- sci_timer(2) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(3)(sci_timer'left) = '1' then
- sci_timer(3) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- end if;
-when SCTRL =>
- if sci_reg_i = '1' then
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
-when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
-when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
-when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
-when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
-when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
-when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
-when GET_WA_FINISH =>
--- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- wa_position(cnt) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
-end case;
-
-if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
-else
- SCI_NACK <= '0';
-end if;
-
-end process;
-
-
-
-
- STAT_DEBUG <= (others => '0'); --debug_reg;
-
- generated_status : for i in 0 to 3 generate
- STAT_OP(i*16 + 15) <= send_link_reset_i(i) when rising_edge(SYSCLK);\r
- STAT_OP(i*16 + 14) <= '0';\r
- STAT_OP(i*16 + 13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset\r
- STAT_OP(i*16 + 12) <= '0';\r
- STAT_OP(i*16 + 11) <= '0';\r
- STAT_OP(i*16 + 10) <= rx_allow(i);\r
- STAT_OP(i*16 + 9) <= tx_allow(i);\r
- STAT_OP(i*16 + 8) <= got_link_ready_i(i) when rising_edge(rx_half_clk(i));\r
- STAT_OP(i*16 + 7) <= send_link_reset_i(i);\r
- STAT_OP(i*16 + 6) <= make_link_reset_i(i);\r
- STAT_OP(i*16 + 5) <= request_retr_i(i);\r
- STAT_OP(i*16 + 4) <= start_retr_i(i);\r
- STAT_OP(i*16 + 3 downto i*16) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";\r
- end generate;
-
-end med_ecp3_sfp_4_sync_down_arch;
+++ /dev/null
---4 channel Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_4_sync_down_EP is
- generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave
- port(
- OSC_CLK : in std_logic; -- 200 MHz reference clock
- TX_DATACLK : in std_logic; -- 200 MHz data clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
-
- --Sync operation
- RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
- RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
- TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
- LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
-
- --SFP Connection
- SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
- -- Status and control port
--- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
--- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
-end entity;
-
-
-architecture med_ecp3_sfp_4_sync_down_EP_arch of med_ecp3_sfp_4_sync_down_EP is
-
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of med_ecp3_sfp_4_sync_down_EP_arch : architecture is "media_downlink_group";
- attribute syn_sharing : string;
- attribute syn_sharing of med_ecp3_sfp_4_sync_down_EP_arch : architecture is "off";
-
-
-
-signal clk_200_osc : std_logic;
-signal clk_200_txdata : std_logic;
---signal clk_200_rxdn : std_logic_vector(3 downto 0);
---signal clk_200_i : std_logic_vector(3 downto 0);
-signal rx_full_clk : std_logic_vector(3 downto 0);
-signal rx_half_clk : std_logic_vector(3 downto 0);
-signal tx_full_clk : std_logic_vector(3 downto 0);
-signal tx_half_clk : std_logic_vector(3 downto 0);
-
-signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
-signal tx_k : std_logic_vector(3 downto 0);
-signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
-signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0);
-
-signal rst_n : t_HUB_BIT;
-signal rst : t_HUB_BIT; -- PL!
-signal rx_serdes_rst : t_HUB_BIT;
-signal tx_serdes_rst : std_logic := '0';
-signal tx_pcs_rst : t_HUB_BIT;
-signal rx_pcs_rst : t_HUB_BIT;
-signal rst_qd : t_HUB_BIT;
-signal rst_down_quad : std_logic;
---signal serdes_rst_qd : t_HUB_BIT;
-signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad
-signal sd_los_i : t_HUB_BIT; --PL!
-
-signal rx_los_low : t_HUB_BIT;
-signal lsm_status : t_HUB_BIT;
-signal rx_cdr_lol : t_HUB_BIT;
-signal tx_pll_lol : t_HUB_BIT;
-signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad
-
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
-signal sci_data_in_i : std_logic_vector(7 downto 0);
-signal sci_data_out_i : std_logic_vector(7 downto 0);
-signal sci_read_i : std_logic;
-signal sci_write_i : std_logic;
---signal sci_write_shift_i : std_logic_vector(2 downto 0);
---signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
-signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal tx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal link_phase_S : t_HUB_BIT; --std_logic_vector(3 downto 0); --PL!
-signal request_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal start_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal request_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
-signal start_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
-signal send_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal make_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0);
-
-signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0');
-signal watchdog_timer : t_HUB_TIMER21 := (others => (others => '0')); --unsigned(20 downto 0) := (others => '0');
-signal watchdog_trigger : t_HUB_BIT := (others => '0'); --std_logic_vector(3 downto 0) := (others => '0');
-
-signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
-signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
-
-signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_reg : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state : sci_ctrl;
-signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0');
-
-begin
-
-
---SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-
-clk_200_osc <= OSC_CLK; -- This external clock is oscillator/pll generated !!!
-clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!!
-
-
-gen_clocks : for i in 0 to 3 generate
-
- rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
- rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
-
- RX_HALF_CLK_OUT(i) <= rx_half_clk(i);
- RX_FULL_CLK_OUT(i) <= rx_full_clk(i);
- TX_HALF_CLK_OUT(i) <= tx_half_clk(i);
- TX_FULL_CLK_OUT(i) <= tx_full_clk(i);
-
--- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master
--- clk_200_i(i) <= rx_full_clk(i);
--- end generate;
-
--- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i(i) <= clk_200_txdata;
--- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!!
--- end generate;
-end generate;
-
--------------------------------------------------
--- Serdes
--------------------------------------------------
-THE_SERDES : entity work.serdes_4_sync_downstream
- port map(
- -- CHANNEL0 --
- hdinp_ch0 => SD_RXD_P_IN(0),
- hdinn_ch0 => SD_RXD_N_IN(0),
- hdoutp_ch0 => SD_TXD_P_OUT(0),
- hdoutn_ch0 => SD_TXD_N_OUT(0),
- rxiclk_ch0 => clk_200_txdata, --clk_200_i(0),
- sci_sel_ch0 => sci_ch_i(0),
- txiclk_ch0 => clk_200_txdata,
- rx_full_clk_ch0 => rx_full_clk(0),
- rx_half_clk_ch0 => rx_half_clk(0),
- tx_full_clk_ch0 => tx_full_clk(0),
- tx_half_clk_ch0 => tx_half_clk(0),
- fpga_rxrefclk_ch0 => clk_200_osc,
- txdata_ch0 => tx_data(0),
- tx_k_ch0 => tx_k(0),
- tx_force_disp_ch0 => '0',
- tx_disp_sel_ch0 => '0',
- rxdata_ch0 => rx_data(0),
- rx_k_ch0 => rx_k(0),
- rx_disp_err_ch0 => open,
- rx_cv_err_ch0 => rx_error(0),
- rx_serdes_rst_ch0_c => rx_serdes_rst(0),
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pcs_rst_ch0_c => tx_pcs_rst(0),
- tx_pwrup_ch0_c => '1',
- rx_pcs_rst_ch0_c => rx_pcs_rst(0),
- rx_pwrup_ch0_c => '1',
- rx_los_low_ch0_s => rx_los_low(0),
- lsm_status_ch0_s => lsm_status(0),
- rx_cdr_lol_ch0_s => rx_cdr_lol(0),
- tx_div2_mode_ch0_c => '0',
- rx_div2_mode_ch0_c => '0',
- -- CHANNEL1 --
- hdinp_ch1 => SD_RXD_P_IN(1),
- hdinn_ch1 => SD_RXD_N_IN(1),
- hdoutp_ch1 => SD_TXD_P_OUT(1),
- hdoutn_ch1 => SD_TXD_N_OUT(1),
- rxiclk_ch1 => clk_200_txdata, --clk_200_i(1),
- sci_sel_ch1 => sci_ch_i(1),
- txiclk_ch1 => clk_200_txdata,
- rx_full_clk_ch1 => rx_full_clk(1),
- rx_half_clk_ch1 => rx_half_clk(1),
- tx_full_clk_ch1 => tx_full_clk(1),
- tx_half_clk_ch1 => tx_half_clk(1),
- fpga_rxrefclk_ch1 => clk_200_osc,
- txdata_ch1 => tx_data(1),
- tx_k_ch1 => tx_k(1),
- tx_force_disp_ch1 => '0',
- tx_disp_sel_ch1 => '0',
- rxdata_ch1 => rx_data(1),
- rx_k_ch1 => rx_k(1),
- rx_disp_err_ch1 => open,
- rx_cv_err_ch1 => rx_error(1),
- rx_serdes_rst_ch1_c => rx_serdes_rst(1),
- sb_felb_ch1_c => '0',
- sb_felb_rst_ch1_c => '0',
- tx_pcs_rst_ch1_c => tx_pcs_rst(1),
- tx_pwrup_ch1_c => '1',
- rx_pcs_rst_ch1_c => rx_pcs_rst(1),
- rx_pwrup_ch1_c => '1',
- rx_los_low_ch1_s => rx_los_low(1),
- lsm_status_ch1_s => lsm_status(1),
- rx_cdr_lol_ch1_s => rx_cdr_lol(1),
- tx_div2_mode_ch1_c => '0',
- rx_div2_mode_ch1_c => '0',
- -- CHANNEL2 --
- hdinp_ch2 => SD_RXD_P_IN(2),
- hdinn_ch2 => SD_RXD_N_IN(2),
- hdoutp_ch2 => SD_TXD_P_OUT(2),
- hdoutn_ch2 => SD_TXD_N_OUT(2),
- rxiclk_ch2 => clk_200_txdata, --clk_200_i(2),
- sci_sel_ch2 => sci_ch_i(2),
- txiclk_ch2 => clk_200_txdata,
- rx_full_clk_ch2 => rx_full_clk(2),
- rx_half_clk_ch2 => rx_half_clk(2),
- tx_full_clk_ch2 => tx_full_clk(2),
- tx_half_clk_ch2 => tx_half_clk(2),
- fpga_rxrefclk_ch2 => clk_200_osc,
- txdata_ch2 => tx_data(2),
- tx_k_ch2 => tx_k(2),
- tx_force_disp_ch2 => '0',
- tx_disp_sel_ch2 => '0',
- rxdata_ch2 => rx_data(2),
- rx_k_ch2 => rx_k(2),
- rx_disp_err_ch2 => open,
- rx_cv_err_ch2 => rx_error(2),
- rx_serdes_rst_ch2_c => rx_serdes_rst(2),
- sb_felb_ch2_c => '0',
- sb_felb_rst_ch2_c => '0',
- tx_pcs_rst_ch2_c => tx_pcs_rst(2),
- tx_pwrup_ch2_c => '1',
- rx_pcs_rst_ch2_c => rx_pcs_rst(2),
- rx_pwrup_ch2_c => '1',
- rx_los_low_ch2_s => rx_los_low(2),
- lsm_status_ch2_s => lsm_status(2),
- rx_cdr_lol_ch2_s => rx_cdr_lol(2),
- tx_div2_mode_ch2_c => '0',
- rx_div2_mode_ch2_c => '0',
- -- CHANNEL3 --
- hdinp_ch3 => SD_RXD_P_IN(3),
- hdinn_ch3 => SD_RXD_N_IN(3),
- hdoutp_ch3 => SD_TXD_P_OUT(3),
- hdoutn_ch3 => SD_TXD_N_OUT(3),
- rxiclk_ch3 => clk_200_txdata, --clk_200_i(3),
- sci_sel_ch3 => sci_ch_i(3),
- txiclk_ch3 => clk_200_txdata,
- rx_full_clk_ch3 => rx_full_clk(3),
- rx_half_clk_ch3 => rx_half_clk(3),
- tx_full_clk_ch3 => tx_full_clk(3),
- tx_half_clk_ch3 => tx_half_clk(3),
- fpga_rxrefclk_ch3 => clk_200_osc,
- txdata_ch3 => tx_data(3),
- tx_k_ch3 => tx_k(3),
- tx_force_disp_ch3 => '0',
- tx_disp_sel_ch3 => '0',
- rxdata_ch3 => rx_data(3),
- rx_k_ch3 => rx_k(3),
- rx_disp_err_ch3 => open,
- rx_cv_err_ch3 => rx_error(3),
- rx_serdes_rst_ch3_c => rx_serdes_rst(3),
- sb_felb_ch3_c => '0',
- sb_felb_rst_ch3_c => '0',
- tx_pcs_rst_ch3_c => tx_pcs_rst(3),
- tx_pwrup_ch3_c => '1',
- rx_pcs_rst_ch3_c => rx_pcs_rst(3),
- rx_pwrup_ch3_c => '1',
- rx_los_low_ch3_s => rx_los_low(3),
- lsm_status_ch3_s => lsm_status(3),
- rx_cdr_lol_ch3_s => rx_cdr_lol(3),
- tx_div2_mode_ch3_c => '0',
- rx_div2_mode_ch3_c => '0',
- -- COMMON --
- sci_wrdata => sci_data_in_i,
- sci_rddata => sci_data_out_i,
- sci_addr => sci_addr_i(5 downto 0),
- sci_sel_quad => sci_qd_i,
- sci_rd => sci_read_i,
- sci_wrn => sci_write_i,
-
- fpga_txrefclk => clk_200_txdata, --clk_200_osc, --clk_200_i(0),
- tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906
- tx_pll_lol_qd_s => tx_pll_lol_quad,
- tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols
- rst_qd_c => rst_down_quad, -- jemig wat is Oscar toch gasfjkl[glk
- serdes_rst_qd_c => serdes_rst_down_quad
- );
-
--------------------------
--- combined quad reset --
--------------------------
---rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
-rst_down_quad <= RESET; -- PL: 18/06/14
---serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
-serdes_rst_down_quad <= '0'; -- PL: 23/06/14
-
-generated_logic : for i in 0 to 3 generate
-
- SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready
-
- tx_pll_lol(i) <= tx_pll_lol_quad;
-
- -------------------------------------------------
- -- Reset FSM & Link states
- -------------------------------------------------
- THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n(i),
- RX_REFCLK => rx_full_clk(i), --clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn
- TX_PLL_LOL_QD_S => tx_pll_lol(i),
- RX_SERDES_RST_CH_C => rx_serdes_rst(i),
- RX_CDR_LOL_CH_S => rx_cdr_lol(i),
- RX_LOS_LOW_CH_S => rx_los_low(i),
- RX_PCS_RST_CH_C => rx_pcs_rst(i),
- WA_POSITION => wa_position_rx(i),
- STATE_OUT => rx_fsm_state(i)
- );
-
- THE_TX_FSM : tx_reset_fsm
- port map(
- RST_N => rst_n(i),
- TX_REFCLK => clk_200_txdata, --clk_200_osc,
- TX_PLL_LOL_QD_S => tx_pll_lol(i),
- RST_QD_C => rst_qd(i),
- TX_PCS_RST_CH_C => tx_pcs_rst(i),
- STATE_OUT => tx_fsm_state(i)
- );
-
-
- -- Master does not do bit-locking
- wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
-
-
- PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i))
- begin
- if rising_edge(clk_200_txdata) then -- clk_200_txdata ??
- if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
- rx_allow(i) <= '1';
- tx_allow(i) <= '1';
- else
- rx_allow(i) <= '0';
- tx_allow(i) <= '1';
- end if;
- end if;
- end process;
-
- rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK);
- tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
-
-
- PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i))
- begin
- if rising_edge(clk_200_txdata) then
- if got_link_ready_i(i) = '1' then
- watchdog_timer(i) <= (others => '0');
- if start_timer(i)(start_timer'left) = '0' then
- start_timer(i) <= start_timer(i) + 1;
--- start_timer(i)(start_timer'left downto 0) <= start_timer(i)(start_timer'left downto 0) + 1;
- end if;
- else
- start_timer(i) <= (others => '0');
- if ((watchdog_timer(i)(watchdog_timer(i)'left) = '1') and (watchdog_timer(i)(watchdog_timer(i)'left - 1) = '1')) then
- watchdog_trigger(i) <= '1';
- else
- watchdog_trigger(i) <= '0';
- end if;
- if watchdog_trigger(i) = '0' then
- watchdog_timer(i) <= watchdog_timer(i) + 1;
- else
- watchdog_timer(i) <= (others => '0');
- end if;
- end if;
- end if;
- end process;
- -------------------------------------------------
- -- TX Data
- -------------------------------------------------
- THE_TX : soda_tx_control
- port map(
- CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i),
- CLK_100 => SYSCLK,
- RESET_IN => rst(i), --CLEAR, PL!
-
- TX_DATA_IN => (others => '0'), -- MED_DATA_IN(i),
- TX_PACKET_NUMBER_IN => (others => '0'), -- MED_PACKET_NUM_IN(i),
- TX_WRITE_IN => '0', -- MED_DATAREADY_IN(i),
- TX_READ_OUT => open, -- MED_READ_OUT(i),
-
- TX_DATA_OUT => tx_data(i),
- TX_K_OUT => tx_k(i),
-
- REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO
- REQUEST_POSITION_IN => request_retr_position_i(i), --TODO
-
- START_RETRANSMIT_IN => start_retr_i(i), --TODO
- START_POSITION_IN => request_retr_position_i(i), --TODO
-
- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i),
- SEND_DLM => TX_DLM(i),
- SEND_DLM_WORD => TX_DLM_WORD(i),
-
- SEND_LINK_RESET_IN => '0', --CTRL_OP(i)(15),
- TX_ALLOW_IN => tx_allow(i),
- RX_ALLOW_IN => rx_allow(i),
- LINK_PHASE_OUT => link_phase_S(i), --PL!
-
- DEBUG_OUT => debug_tx_control_i(i),
- STAT_REG_OUT => stat_tx_control_i(i)
- );
-
- LINK_PHASE_OUT(i) <= link_phase_S(i); --PL!
- -------------------------------------------------
- -- RX Data
- -------------------------------------------------
- THE_RX_CONTROL : rx_control
- port map(
- CLK_200 => clk_200_txdata, --clk_200_i(i), --PL!
- CLK_100 => SYSCLK,
- RESET_IN => rst(i), --CLEAR, PL!
-
- RX_DATA_OUT => open, -- MED_DATA_OUT(i),
- RX_PACKET_NUMBER_OUT => open, -- MED_PACKET_NUM_OUT(i),
- RX_WRITE_OUT => open, -- MED_DATAREADY_OUT(i),
- RX_READ_IN => '0', -- MED_READ_IN(i),
-
- RX_DATA_IN => rx_data(i),
- RX_K_IN => rx_k(i),
-
- REQUEST_RETRANSMIT_OUT => request_retr_i(i),
- REQUEST_POSITION_OUT => request_retr_position_i(i),
-
- START_RETRANSMIT_OUT => start_retr_i(i),
- START_POSITION_OUT => start_retr_position_i(i),
-
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
- RX_DLM => RX_DLM(i),
- RX_DLM_WORD => RX_DLM_WORD(i),
-
- SEND_LINK_RESET_OUT => send_link_reset_i(i),
- MAKE_RESET_OUT => make_link_reset_i(i),
- RX_ALLOW_IN => rx_allow(i),
- GOT_LINK_READY => got_link_ready_i(i),
-
- DEBUG_OUT => debug_rx_control_i(i),
- STAT_REG_OUT => stat_rx_control_i(i)
- );
-
- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL!
-
-end generate;
-
--------------------------------------------------
--- SCI
--------------------------------------------------
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process
-variable cnt : integer range 0 to 4 := 0;
-begin
-wait until rising_edge(SYSCLK);
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer(0) <= sci_timer(0) + 1;
- sci_timer(1) <= sci_timer(1) + 1;
- sci_timer(2) <= sci_timer(2) + 1;
- sci_timer(3) <= sci_timer(3) + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- else
- if sci_timer(0)(sci_timer'left) = '1' then
- sci_timer(0) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(1)(sci_timer'left) = '1' then
- sci_timer(1) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(2)(sci_timer'left) = '1' then
- sci_timer(2) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(3)(sci_timer'left) = '1' then
- sci_timer(3) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- end if;
-when SCTRL =>
- if sci_reg_i = '1' then
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
-when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
-when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
-when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
-when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
-when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
-when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
-when GET_WA_FINISH =>
--- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- wa_position(cnt) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
-end case;
-
-if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
-else
- SCI_NACK <= '0';
-end if;
-
-end process;
-
-
--- -------------------------------------------------
--- -- Debug Registers
--- -------------------------------------------------
--- debug_reg(3 downto 0) <= rx_fsm_state;
--- debug_reg(4) <= rx_k;
--- debug_reg(5) <= rx_error;
--- debug_reg(6) <= rx_los_low;
--- debug_reg(7) <= rx_cdr_lol;
---
--- debug_reg(8) <= tx_k;
--- debug_reg(9) <= tx_pll_lol;
--- debug_reg(10) <= lsm_status;
--- debug_reg(11) <= make_link_reset_i;
--- debug_reg(15 downto 12) <= tx_fsm_state;
--- -- debug_reg(31 downto 24) <= tx_data;
---
--- debug_reg(16) <= '0';
--- debug_reg(17) <= tx_allow;
--- debug_reg(18) <= RESET;
--- debug_reg(19) <= CLEAR;
--- debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
---
--- debug_reg(35 downto 32) <= wa_position(3 downto 0);
--- debug_reg(36) <= debug_tx_control_i(6);
--- debug_reg(39 downto 37) <= "000";
--- debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
-
-
- STAT_DEBUG <= (others => '0'); --debug_reg;
-
--- generated_status : for i in 0 to 3 generate
- -- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
- -- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL!
-
--- STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK);
--- STAT_OP(i)(14) <= '0';
--- STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset
--- STAT_OP(i)(12) <= '0';
--- STAT_OP(i)(11) <= '0';
--- STAT_OP(i)(10) <= rx_allow(i);
--- STAT_OP(i)(9) <= tx_allow(i);
--- STAT_OP(i)(8) <= got_link_ready_i(i);
--- STAT_OP(i)(7) <= send_link_reset_i(i);
--- STAT_OP(i)(6) <= make_link_reset_i(i);
--- STAT_OP(i)(5) <= request_retr_i(i);
--- STAT_OP(i)(4) <= start_retr_i(i);
--- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";
--- end generate;
-
-end med_ecp3_sfp_4_sync_down_EP_arch;
\ No newline at end of file
+++ /dev/null
---Media interface for Lattice ECP3 using PCS at 2GHz\r
-\r
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.med_sync_define.all;\r
-use work.soda_components.all;\r
-\r
-entity med_ecp3_sfp_sync_down is\r
- generic( SERDES_NUM : integer range 0 to 3 := 0;\r
- IS_SYNC_SLAVE : integer := c_NO); --select slave mode\r
- port(\r
- OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock\r
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- --Internal Connection TX\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic := '0';\r
- --Internal Connection RX\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');\r
- MED_DATAREADY_OUT : out std_logic := '0';\r
- MED_READ_IN : in std_logic;\r
- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz\r
- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz\r
- TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz\r
- TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz\r
-\r
- --Sync operation\r
- RX_DLM : out std_logic := '0';\r
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";\r
- TX_DLM : in std_logic := '0';\r
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";\r
- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!\r
- LINK_PHASE_OUT : out std_logic := '0'; --PL!\r
-\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic; --not used\r
- SD_REFCLK_N_IN : in std_logic; --not used\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable\r
- --Control Interface\r
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
- SCI_READ : in std_logic := '0';\r
- SCI_WRITE : in std_logic := '0';\r
- SCI_ACK : out std_logic := '0';\r
- SCI_NACK : out std_logic := '0';\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')\r
- );\r
-end entity;\r
-\r
-\r
-architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is\r
-\r
- -- Placer Directives\r
- attribute HGROUP : string;\r
- -- for whole architecture\r
- attribute HGROUP of med_ecp3_sfp_sync_down_arch : architecture is "media_downlink_group";\r
- attribute syn_sharing : string;\r
- attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off";\r
-\r
-\r
-component DCS\r
--- synthesis translate_off\r
-generic\r
-(\r
- DCSMODE : string :="POS"\r
-);\r
--- synthesis translate_on\r
-port (\r
- CLK0 :in std_logic ;\r
- CLK1 :in std_logic ;\r
- SEL :in std_logic ;\r
- DCSOUT :out std_logic) ;\r
-end component;\r
-\r
-\r
---signal clk_200_i : std_logic;\r
---signal clk_200_internal : std_logic;\r
-signal clk_200_osc : std_logic;\r
-signal clk_100_osc : std_logic;\r
-signal rx_full_clk_ch0 : std_logic;\r
-signal rx_half_clk_ch0 : std_logic;\r
-signal tx_full_clk_ch0 : std_logic;\r
-signal tx_half_clk_ch0 : std_logic;\r
-\r
-signal tx_data : std_logic_vector(7 downto 0);\r
-signal tx_k : std_logic;\r
-signal rx_data : std_logic_vector(7 downto 0);\r
-signal rx_k : std_logic;\r
-signal rx_error : std_logic;\r
-signal rx_dlm_S : std_logic; --PL!
-\r
-signal rst_n : std_logic;\r
-signal rst : std_logic; -- PL!\r
-signal rx_serdes_rst : std_logic;\r
-signal tx_serdes_rst : std_logic;\r
-signal tx_pcs_rst : std_logic;\r
-signal rx_pcs_rst : std_logic;\r
-signal rst_qd : std_logic;\r
-signal serdes_rst_qd : std_logic;\r
-signal sd_los_i : std_logic; --PL!\r
-\r
-signal rx_los_low : std_logic;\r
-signal lsm_status : std_logic;\r
-signal rx_cdr_lol : std_logic;\r
-signal tx_pll_lol : std_logic;\r
-\r
-signal sci_ch_i : std_logic_vector(3 downto 0);\r
-signal sci_qd_i : std_logic;\r
-signal sci_reg_i : std_logic;\r
-signal sci_addr_i : std_logic_vector(8 downto 0);\r
-signal sci_data_in_i : std_logic_vector(7 downto 0);\r
-signal sci_data_out_i : std_logic_vector(7 downto 0);\r
-signal sci_read_i : std_logic;\r
-signal sci_write_i : std_logic;\r
-signal sci_write_shift_i : std_logic_vector(2 downto 0);\r
-signal sci_read_shift_i : std_logic_vector(2 downto 0);\r
-\r
--- fix signal names for constraining\r
-attribute syn_preserve : boolean;--\r
-attribute syn_keep : boolean;--\r
-attribute syn_preserve of sci_ch_i : signal is true;--\r
-attribute syn_keep of sci_ch_i : signal is true;--\r
-attribute syn_preserve of sci_qd_i : signal is true;--\r
-attribute syn_keep of sci_qd_i : signal is true;--\r
-attribute syn_preserve of sci_reg_i : signal is true;--\r
-attribute syn_keep of sci_reg_i : signal is true;--\r
-attribute syn_preserve of sci_addr_i : signal is true;--\r
-attribute syn_keep of sci_addr_i : signal is true;--\r
-attribute syn_preserve of sci_data_in_i : signal is true;--\r
-attribute syn_keep of sci_data_in_i : signal is true;--\r
-attribute syn_preserve of sci_data_out_i : signal is true;--\r
-attribute syn_keep of sci_data_out_i : signal is true;--\r
-attribute syn_preserve of sci_read_i : signal is true;--\r
-attribute syn_keep of sci_read_i : signal is true;--\r
-attribute syn_preserve of sci_write_i : signal is true;--\r
-attribute syn_keep of sci_write_i : signal is true;--\r
-attribute syn_preserve of sci_write_shift_i : signal is true;--\r
-attribute syn_keep of sci_write_shift_i : signal is true;--\r
-attribute syn_preserve of sci_read_shift_i : signal is true;--\r
-attribute syn_keep of sci_read_shift_i : signal is true;--\r
-\r
-signal buf_med_dataready_out : std_logic;\r
-\r
-signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";\r
-signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";\r
-signal tx_allow : std_logic;\r
-signal rx_allow : std_logic;\r
-signal tx_allow_q : std_logic;\r
-signal rx_allow_q : std_logic;\r
-signal link_phase_S : std_logic; --PL!\r
-signal request_retr_i : std_logic;\r
-signal start_retr_i : std_logic;\r
-signal request_retr_position_i : std_logic_vector(7 downto 0);\r
-signal start_retr_position_i : std_logic_vector(7 downto 0);\r
-signal send_link_reset_i : std_logic;\r
-signal make_link_reset_i : std_logic;\r
-signal got_link_ready_i : std_logic;\r
-signal internal_make_link_reset_out : std_logic;\r
-\r
-attribute syn_preserve of wa_position : signal is true;--\r
-attribute syn_keep of wa_position : signal is true;--\r
-attribute syn_preserve of wa_position_rx : signal is true;--\r
-attribute syn_keep of wa_position_rx : signal is true;--\r
-\r
-signal stat_rx_control_i : std_logic_vector(31 downto 0);\r
-signal stat_tx_control_i : std_logic_vector(31 downto 0);\r
-signal debug_rx_control_i : std_logic_vector(31 downto 0);\r
-signal debug_tx_control_i : std_logic_vector(31 downto 0);\r
-signal rx_fsm_state : std_logic_vector(3 downto 0);\r
-signal tx_fsm_state : std_logic_vector(3 downto 0);\r
-signal debug_reg : std_logic_vector(63 downto 0);\r
-\r
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);\r
-signal sci_state : sci_ctrl;\r
-signal sci_timer : unsigned(12 downto 0) := (others => '0');\r
-signal start_timer : unsigned(18 downto 0) := (others => '0');\r
---signal watchdog_timer : unsigned(20 downto 0) := (others => '0');\r
---signal watchdog_trigger : std_logic :='0';\r
-
-signal led_dlm, last_led_dlm : std_logic;\r
-signal led_ok : std_logic;\r
-signal led_tx, last_led_tx : std_logic;\r
-signal led_rx, last_led_rx : std_logic;\r
-signal timer : unsigned(20 downto 0);\r
-\r
-begin\r
-\r
-clk_200_osc <= OSCCLK; \r
-clk_100_osc <= SYSCLK; \r
- \r
-RX_HALF_CLK_OUT <= rx_half_clk_ch0;\r
-RX_FULL_CLK_OUT <= rx_full_clk_ch0;\r
-TX_HALF_CLK_OUT <= tx_half_clk_ch0;\r
-TX_FULL_CLK_OUT <= tx_full_clk_ch0;\r
-\r
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready\r
-\r
-\r
---rst_n <= not CLEAR; PL!\r
---rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger);\r
---rst <= (CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger);\r
-rst_n <= not(CLEAR or internal_make_link_reset_out);\r
-rst <= (CLEAR or internal_make_link_reset_out);\r
-\r
-------------------------------------------------- \r
--- Serdes\r
-------------------------------------------------- \r
-THE_SERDES : entity work.serdes_sync_source_downstream\r
- port map(\r
- hdinp_ch0 => SD_RXD_P_IN,\r
- hdinn_ch0 => SD_RXD_N_IN,\r
- hdoutp_ch0 => SD_TXD_P_OUT,\r
- hdoutn_ch0 => SD_TXD_N_OUT,\r
- rxiclk_ch0 => tx_full_clk_ch0, -- read fifo is no longer present! PL!\r
- txiclk_ch0 => tx_full_clk_ch0,\r
- rx_full_clk_ch0 => rx_full_clk_ch0,\r
- rx_half_clk_ch0 => rx_half_clk_ch0,\r
- tx_full_clk_ch0 => tx_full_clk_ch0,\r
- tx_half_clk_ch0 => tx_half_clk_ch0,\r
- fpga_rxrefclk_ch0 => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT\r
- txdata_ch0 => tx_data,\r
- tx_k_ch0 => tx_k,\r
- tx_force_disp_ch0 => '0',\r
- tx_disp_sel_ch0 => '0',\r
- rxdata_ch0 => rx_data,\r
- rx_k_ch0 => rx_k,\r
- rx_disp_err_ch0 => open,\r
- rx_cv_err_ch0 => rx_error,\r
- rx_serdes_rst_ch0_c => rx_serdes_rst,\r
- sb_felb_ch0_c => '0',\r
- sb_felb_rst_ch0_c => '0',\r
- tx_pcs_rst_ch0_c => tx_pcs_rst,\r
- tx_pwrup_ch0_c => '1',\r
- rx_pcs_rst_ch0_c => rx_pcs_rst,\r
- rx_pwrup_ch0_c => '1',\r
- rx_los_low_ch0_s => rx_los_low,\r
- lsm_status_ch0_s => lsm_status,\r
- rx_cdr_lol_ch0_s => rx_cdr_lol,\r
- tx_div2_mode_ch0_c => '0',\r
- rx_div2_mode_ch0_c => '0',\r
- refclk2fpga => open, --refclk2core_S,\r
- \r
- SCI_WRDATA => sci_data_in_i,\r
- SCI_RDDATA => sci_data_out_i,\r
- SCI_ADDR => sci_addr_i(5 downto 0),\r
- SCI_SEL_QUAD => sci_qd_i,\r
- SCI_SEL_CH0 => sci_ch_i(0),\r
- SCI_RD => sci_read_i,\r
- SCI_WRN => sci_write_i,\r
- \r
- fpga_txrefclk => clk_200_osc, -- REF CLK MUST ALWAYS BE PRESENT\r
- tx_serdes_rst_c => '0', --tx_serdes_rst,\r
- tx_pll_lol_qd_s => tx_pll_lol,\r
- rst_qd_c => rst_qd,\r
- serdes_rst_qd_c => serdes_rst_qd\r
-\r
- );\r
-\r
- \r
-------------------------------------------------- \r
--- Reset FSM & Link states\r
-------------------------------------------------- \r
-THE_RX_FSM : rx_reset_fsm\r
- port map(\r
- RST_N => rst_n,\r
- RX_REFCLK => clk_200_osc, --rx_full_clk_ch0,\r
- TX_PLL_LOL_QD_S => tx_pll_lol,\r
- RX_SERDES_RST_CH_C => rx_serdes_rst,\r
- RX_CDR_LOL_CH_S => rx_cdr_lol,\r
- RX_LOS_LOW_CH_S => rx_los_low,\r
- RX_PCS_RST_CH_C => rx_pcs_rst,\r
- WA_POSITION => wa_position_rx(3 downto 0),\r
- STATE_OUT => rx_fsm_state\r
- );\r
- \r
-THE_TX_FSM : tx_reset_fsm\r
- port map(\r
- RST_N => rst_n,\r
- TX_REFCLK => clk_200_osc,\r
- TX_PLL_LOL_QD_S => tx_pll_lol,\r
- RST_QD_C => rst_qd,\r
- TX_PCS_RST_CH_C => tx_pcs_rst,\r
- STATE_OUT => tx_fsm_state\r
- );\r
-\r
--- Master does not do bit-locking \r
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";\r
-\r
-\r
---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable\r
-PROC_ALLOW : process begin\r
- wait until rising_edge(clk_200_osc); --clk_200_i);\r
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then\r
- rx_allow <= '1';\r
- else\r
- rx_allow <= '0';\r
- end if;\r
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then\r
- tx_allow <= '1';\r
- else\r
- tx_allow <= '0';\r
- end if;\r
-end process;\r
-\r
-rx_allow_q <= rx_allow when rising_edge(clk_100_osc);\r
-tx_allow_q <= tx_allow when rising_edge(clk_100_osc);\r
-\r
-\r
--- start_timer begins when the rx-link is ready; i.e.: there is a working link.\r
--- If you are a SLAVE, you can then start transmitting right away. -- if you are a MASTER, you wait for the start_timer MSB to go high.\r
--- This gives a slave on the other side time to start-up\r
--- if the rx-link is NOT ready, the watchdog_timer starts. It should be longer than start_timer and will cause a hanging link to reset\r
-PROC_START_TIMER : process(clk_200_osc) --clk_200_i)\r
-begin\r
- if rising_edge(clk_200_osc) then\r
- if got_link_ready_i = '1' then\r
- if start_timer(start_timer'left) = '0' then\r
- start_timer <= start_timer + 1;\r
- end if; \r
- else\r
- start_timer <= (others => '0');\r
- end if;\r
- end if;\r
-end process;\r
-\r
-------------------------------------------------- \r
--- TX Data\r
-------------------------------------------------- \r
-THE_TX : soda_tx_control\r
- port map(\r
- CLK_200 => clk_200_osc,\r
- CLK_100 => clk_100_osc,\r
- RESET_IN => rst, --CLEAR, PL!\r
-\r
- TX_DATA_IN => MED_DATA_IN,\r
- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,\r
- TX_WRITE_IN => MED_DATAREADY_IN,\r
- TX_READ_OUT => MED_READ_OUT,\r
-\r
- TX_DATA_OUT => tx_data,\r
- TX_K_OUT => tx_k,\r
-\r
- REQUEST_RETRANSMIT_IN => request_retr_i, --TODO\r
- REQUEST_POSITION_IN => request_retr_position_i, --TODO\r
-\r
- START_RETRANSMIT_IN => start_retr_i, --TODO\r
- START_POSITION_IN => start_retr_position_i, --TODO\r
-\r
- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN,\r
- SEND_DLM => TX_DLM,\r
- SEND_DLM_WORD => TX_DLM_WORD,\r
-\r
- SEND_LINK_RESET_IN => CTRL_OP(15),\r
- TX_ALLOW_IN => tx_allow,\r
- RX_ALLOW_IN => rx_allow,\r
- LINK_PHASE_OUT => link_phase_S, --PL!\r
-\r
- DEBUG_OUT => debug_tx_control_i,\r
- STAT_REG_OUT => stat_tx_control_i\r
-); \r
-\r
-LINK_PHASE_OUT <= link_phase_S; --PL!\r
-------------------------------------------------- \r
--- RX Data\r
-------------------------------------------------- \r
-THE_RX_CONTROL : rx_control\r
- port map(\r
- CLK_200 => tx_full_clk_ch0, --rx_full_clk_ch0, PL! 270814\r
- CLK_100 => clk_100_osc,\r
- RESET_IN => rst, --CLEAR, PL!\r
-\r
- RX_DATA_OUT => MED_DATA_OUT,\r
- RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,\r
- RX_WRITE_OUT => buf_med_dataready_out,\r
- RX_READ_IN => MED_READ_IN,\r
-\r
- RX_DATA_IN => rx_data,\r
- RX_K_IN => rx_k,\r
-\r
- REQUEST_RETRANSMIT_OUT => request_retr_i,\r
- REQUEST_POSITION_OUT => request_retr_position_i,\r
-\r
- START_RETRANSMIT_OUT => start_retr_i,\r
- START_POSITION_OUT => start_retr_position_i,\r
-\r
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM\r
- RX_DLM => rx_dlm_S, --RX_DLM,\r
- RX_DLM_WORD => RX_DLM_WORD,\r
- \r
- SEND_LINK_RESET_OUT => send_link_reset_i,\r
- MAKE_RESET_OUT => make_link_reset_i,\r
- RX_ALLOW_IN => rx_allow,\r
- GOT_LINK_READY => got_link_ready_i,\r
-\r
- DEBUG_OUT => debug_rx_control_i,\r
- STAT_REG_OUT => stat_rx_control_i\r
- ); \r
- \r
-RX_DLM <= rx_dlm_S; --!PL 16032015\r
-MED_DATAREADY_OUT <= buf_med_dataready_out; \r
- \r
-------------------------------------------------- \r
--- SCI\r
-------------------------------------------------- \r
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us\r
-PROC_SCI_CTRL: process \r
- variable cnt : integer range 0 to 4 := 0;\r
-begin\r
- wait until rising_edge(clk_100_osc);\r
- SCI_ACK <= '0';\r
- case sci_state is\r
- when IDLE =>\r
- sci_ch_i <= x"0";\r
- sci_qd_i <= '0';\r
- sci_reg_i <= '0';\r
- sci_read_i <= '0';\r
- sci_write_i <= '0';\r
- sci_timer <= sci_timer + 1;\r
- if SCI_READ = '1' or SCI_WRITE = '1' then\r
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
- sci_addr_i <= SCI_ADDR;\r
- sci_data_in_i <= SCI_DATA_IN;\r
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
- sci_state <= SCTRL;\r
- elsif sci_timer(sci_timer'left) = '1' then\r
- sci_timer <= (others => '0');\r
- sci_state <= GET_WA;\r
- end if; \r
- when SCTRL =>\r
- if sci_reg_i = '1' then\r
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));\r
- SCI_ACK <= '1';\r
- sci_write_i <= '0';\r
- sci_read_i <= '0';\r
- sci_state <= IDLE;\r
- else\r
- sci_state <= SCTRL_WAIT;\r
- end if;\r
- when SCTRL_WAIT =>\r
- sci_state <= SCTRL_WAIT2;\r
- when SCTRL_WAIT2 =>\r
- sci_state <= SCTRL_FINISH;\r
- when SCTRL_FINISH =>\r
- SCI_DATA_OUT <= sci_data_out_i;\r
- SCI_ACK <= '1';\r
- sci_write_i <= '0';\r
- sci_read_i <= '0';\r
- sci_state <= IDLE;\r
- \r
- when GET_WA =>\r
- if cnt = 4 then\r
- cnt := 0;\r
- sci_state <= IDLE;\r
- else\r
- sci_state <= GET_WA_WAIT;\r
- sci_addr_i <= '0' & x"22";\r
- sci_ch_i <= x"0";\r
- sci_ch_i(cnt) <= '1';\r
- sci_read_i <= '1';\r
- end if;\r
- when GET_WA_WAIT =>\r
- sci_state <= GET_WA_WAIT2;\r
- when GET_WA_WAIT2 =>\r
- sci_state <= GET_WA_FINISH;\r
- when GET_WA_FINISH =>\r
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);\r
- sci_state <= GET_WA; \r
- cnt := cnt + 1;\r
- end case;\r
- \r
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then\r
- SCI_NACK <= '1';\r
- else\r
- SCI_NACK <= '0';\r
- end if;\r
- \r
-end process;\r
-\r
-------------------------------------------------- \r
--- Generate LED signals\r
-------------------------------------------------- \r
-led_ok <= rx_allow and tx_allow when rising_edge(clk_100_osc); \r
-led_rx <= (buf_med_dataready_out or led_rx) and not timer(20) when rising_edge(clk_100_osc);\r
-led_tx <= (MED_DATAREADY_IN or led_tx or sd_los_i) and not timer(20) when rising_edge(clk_100_osc);\r
-led_dlm <= (led_dlm or rx_dlm_S) and not timer(20) when rising_edge(clk_100_osc);\r
-\r
-ROC_TIMER : process begin\r
- wait until rising_edge(clk_100_osc);\r
- timer <= timer + 1 ;\r
- if timer(20) = '1' then\r
- timer <= (others => '0');\r
- last_led_rx <= led_rx ;\r
- last_led_tx <= led_tx;\r
- last_led_dlm <= led_dlm;\r
- end if;\r
-end process;\r
-\r
-\r
-------------------------------------------------- \r
--- Debug Registers\r
-------------------------------------------------- \r
-debug_reg(3 downto 0) <= rx_fsm_state;\r
-debug_reg(4) <= rx_k;\r
-debug_reg(5) <= rx_error;\r
-debug_reg(6) <= rx_los_low;\r
-debug_reg(7) <= rx_cdr_lol;\r
-\r
-debug_reg(8) <= tx_k;\r
-debug_reg(9) <= tx_pll_lol;\r
-debug_reg(10) <= lsm_status;\r
-debug_reg(11) <= make_link_reset_i;\r
-debug_reg(15 downto 12) <= tx_fsm_state;\r
--- debug_reg(31 downto 24) <= tx_data; \r
-\r
-debug_reg(16) <= '0';\r
-debug_reg(17) <= tx_allow;\r
-debug_reg(18) <= RESET;\r
-debug_reg(19) <= CLEAR;\r
-debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);\r
-\r
-debug_reg(35 downto 32) <= wa_position(3 downto 0);\r
-debug_reg(36) <= debug_tx_control_i(6);\r
-debug_reg(39 downto 37) <= "000";\r
-debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);\r
-\r
- \r
-STAT_DEBUG <= debug_reg;\r
-\r
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';\r
-sd_los_i <= SD_LOS_IN when rising_edge(clk_100_osc); -- PL!\r
-\r
-STAT_OP(15) <= send_link_reset_i when rising_edge(clk_100_osc);\r
-STAT_OP(14) <= '0';\r
-STAT_OP(13) <= internal_make_link_reset_out when rising_edge(clk_100_osc); --make trbnet reset\r
-STAT_OP(12) <= led_dlm or last_led_dlm;\r
-STAT_OP(11) <= led_tx or last_led_tx;\r
-STAT_OP(10) <= led_rx or last_led_rx;\r
-STAT_OP(9) <= led_ok;\r
---STAT_OP(8 downto 4) <= (others => '0');\r
-STAT_OP(8) <= got_link_ready_i;\r
-STAT_OP(7) <= send_link_reset_i;\r
-STAT_OP(6) <= make_link_reset_i;\r
-STAT_OP(5) <= request_retr_i;\r
-STAT_OP(4) <= start_retr_i;\r
-STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";\r
-\r
-end med_ecp3_sfp_sync_down_arch;\r
+++ /dev/null
---Media interface for Lattice ECP3 using PCS at 2GHz\r
--- TAB=3\r
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.med_sync_define.all;\r
-use work.soda_components.all;\r
-\r
-entity med_ecp3_sfp_sync_up is\r
- generic( SERDES_NUM : integer range 0 to 3 := 0;\r
- IS_SYNC_SLAVE : integer := c_YES); --select slave mode\r
- port(\r
- OSCCLK : in std_logic; -- 200 MHz reference clock\r
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- --Internal Connection TX\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic := '0';\r
- --Internal Connection RX\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');\r
- MED_DATAREADY_OUT : out std_logic := '0';\r
- MED_READ_IN : in std_logic;\r
- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz\r
- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz\r
- TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz\r
- TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz\r
- RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014\r
-\r
- --Sync operation\r
- RX_DLM : out std_logic := '0';\r
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";\r
- TX_DLM : in std_logic := '0';\r
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";\r
- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!\r
- LINK_PHASE_OUT : out std_logic := '0'; --PL!\r
- LINK_READY_OUT : out std_logic := '0'; --PL!\r
-\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic; --not used\r
- SD_REFCLK_N_IN : in std_logic; --not used\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable\r
- --Control Interface\r
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
- SCI_READ : in std_logic := '0';\r
- SCI_WRITE : in std_logic := '0';\r
- SCI_ACK : out std_logic := '0';\r
- SCI_NACK : out std_logic := '0';\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')\r
- );\r
-end entity;\r
-\r
-\r
-architecture med_ecp3_sfp_sync_up_arch of med_ecp3_sfp_sync_up is\r
-\r
--- Placer Directives\r
-attribute HGROUP : string;\r
--- for whole architecture\r
-attribute HGROUP of med_ecp3_sfp_sync_up_arch : architecture is "media_uplink_group";\r
-attribute syn_sharing : string;\r
-attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off";\r
-\r
-\r
-component DCS\r
--- synthesis translate_off\r
-generic(\r
-DSCMODE : string :="POS"\r
-);\r
--- synthesis translate_on\r
-port (\r
-CLK0 :in std_logic ;\r
-CLK1 :in std_logic ;\r
-SEL :in std_logic ;\r
-DCSOUT :out std_logic) ;\r
-end component;\r
-\r
-\r
-signal clk_200_osc : std_logic;\r
-signal rx_full_clk : std_logic;\r
-signal rx_half_clk : std_logic;\r
-signal tx_full_clk : std_logic;\r
-signal tx_half_clk : std_logic;\r
-\r
-signal tx_data : std_logic_vector(7 downto 0);\r
-signal tx_k : std_logic;\r
-signal rx_data : std_logic_vector(7 downto 0);\r
-signal rx_k : std_logic;\r
-signal rx_error : std_logic;\r
-\r
-signal rst_n : std_logic;\r
-signal rst : std_logic; -- PL!\r
-signal rx_serdes_rst : std_logic;\r
-signal tx_serdes_rst : std_logic;\r
-signal tx_pcs_rst : std_logic;\r
-signal rx_pcs_rst : std_logic;\r
-signal rst_qd : std_logic;\r
-signal serdes_rst_qd : std_logic;\r
-signal sd_los_i : std_logic; --PL!\r
-\r
-signal rx_los_low : std_logic;\r
-signal lsm_status : std_logic;\r
-signal rx_cdr_lol : std_logic;\r
-signal tx_pll_lol : std_logic;\r
-\r
-signal sci_ch_i : std_logic_vector(3 downto 0);\r
-signal sci_qd_i : std_logic;\r
-signal sci_reg_i : std_logic;\r
-signal sci_addr_i : std_logic_vector(8 downto 0);\r
-signal sci_data_in_i : std_logic_vector(7 downto 0);\r
-signal sci_data_out_i : std_logic_vector(7 downto 0);\r
-signal sci_read_i : std_logic;\r
-signal sci_write_i : std_logic;\r
-signal sci_write_shift_i : std_logic_vector(2 downto 0);\r
-signal sci_read_shift_i : std_logic_vector(2 downto 0);\r
-\r
--- fix signal names for constraining\r
-attribute syn_preserve : boolean;\r
-attribute syn_keep : boolean;\r
-attribute syn_useioff : boolean;\r
-\r
-attribute syn_useioff of sd_los_i : signal is false; -- do not use an IOFF for this signal\r
-\r
-attribute syn_preserve of sci_ch_i : signal is true;\r
-attribute syn_keep of sci_ch_i : signal is true;\r
-attribute syn_preserve of sci_qd_i : signal is true;\r
-attribute syn_keep of sci_qd_i : signal is true;\r
-attribute syn_preserve of sci_reg_i : signal is true;\r
-attribute syn_keep of sci_reg_i : signal is true;\r
-attribute syn_preserve of sci_addr_i : signal is true;\r
-attribute syn_keep of sci_addr_i : signal is true;\r
-attribute syn_preserve of sci_data_in_i : signal is true;\r
-attribute syn_keep of sci_data_in_i : signal is true;\r
-attribute syn_preserve of sci_data_out_i : signal is true;\r
-attribute syn_keep of sci_data_out_i : signal is true;\r
-attribute syn_preserve of sci_read_i : signal is true;\r
-attribute syn_keep of sci_read_i : signal is true;\r
-attribute syn_preserve of sci_write_i : signal is true;\r
-attribute syn_keep of sci_write_i : signal is true;\r
-attribute syn_preserve of sci_write_shift_i : signal is true;\r
-attribute syn_keep of sci_write_shift_i : signal is true;\r
-attribute syn_preserve of sci_read_shift_i : signal is true;\r
-attribute syn_keep of sci_read_shift_i : signal is true;\r
-\r
-signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";\r
-signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";\r
-signal tx_allow : std_logic;\r
-signal rx_allow : std_logic;\r
-signal tx_allow_q : std_logic;\r
-signal rx_allow_q : std_logic;\r
-signal link_phase_S : std_logic; --PL!\r
-signal request_retr_i : std_logic;\r
-signal start_retr_i : std_logic;\r
-signal request_retr_position_i : std_logic_vector(7 downto 0);\r
-signal start_retr_position_i : std_logic_vector(7 downto 0);\r
-signal send_link_reset_i : std_logic;\r
-signal make_link_reset_i : std_logic;\r
-signal got_link_ready_i : std_logic;\r
-signal internal_make_link_reset_out : std_logic;\r
-\r
-attribute syn_preserve of wa_position : signal is true;\r
-attribute syn_keep of wa_position : signal is true;\r
-attribute syn_preserve of wa_position_rx : signal is true;\r
-attribute syn_keep of wa_position_rx : signal is true;\r
-\r
-signal stat_rx_control_i : std_logic_vector(31 downto 0);\r
-signal stat_tx_control_i : std_logic_vector(31 downto 0);\r
-signal debug_rx_control_i : std_logic_vector(31 downto 0);\r
-signal debug_tx_control_i : std_logic_vector(31 downto 0);\r
-signal rx_fsm_state : std_logic_vector(3 downto 0);\r
-signal tx_fsm_state : std_logic_vector(3 downto 0);\r
-signal debug_reg : std_logic_vector(63 downto 0);\r
-\r
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);\r
-signal sci_state : sci_ctrl;\r
-signal sci_timer : unsigned(12 downto 0) := (others => '0');\r
-signal start_timer : unsigned(18 downto 0) := (others => '0');\r
-signal watchdog_timer : unsigned(20 downto 0) := (others => '0');\r
-signal watchdog_trigger : std_logic :='0';\r
-\r
-begin\r
-\r
-clk_200_osc <= OSCCLK;\r
-\r
-RX_HALF_CLK_OUT <= rx_half_clk;\r
-RX_FULL_CLK_OUT <= rx_full_clk;\r
-TX_HALF_CLK_OUT <= tx_half_clk;\r
-TX_FULL_CLK_OUT <= tx_full_clk;\r
-RX_CDR_LOL_OUT <= rx_cdr_lol; -- !PL14082014\r
-\r
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready\r
-\r
-LINK_READY_OUT <= got_link_ready_i when rising_edge(rx_half_clk);\r
-\r
-\r
---rst_n <= not CLEAR; PL!\r
-rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);\r
-rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);\r
-\r
-\r
---gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate\r
--- clk_200_i <= rx_full_clk;\r
---end generate;\r
-\r
---gen_master_clock : if IS_SYNC_SLAVE = c_NO generate\r
--- clk_200_i <= clk_200_internal;\r
---end generate;\r
-\r
-\r
-------------------------------------------------- \r
--- Serdes\r
-------------------------------------------------- \r
-THE_SERDES : entity work.serdes_sync_upstream\r
- port map(\r
- hdinp_ch3 => SD_RXD_P_IN,\r
- hdinn_ch3 => SD_RXD_N_IN,\r
- hdoutp_ch3 => SD_TXD_P_OUT,\r
- hdoutn_ch3 => SD_TXD_N_OUT,\r
- txiclk_ch3 => rx_full_clk,\r
- rx_full_clk_ch3 => rx_full_clk,\r
- rx_half_clk_ch3 => rx_half_clk,\r
- tx_full_clk_ch3 => tx_full_clk,\r
- tx_half_clk_ch3 => tx_half_clk,\r
- fpga_rxrefclk_ch3 => clk_200_osc,\r
- txdata_ch3 => tx_data,\r
- tx_k_ch3 => tx_k,\r
- tx_force_disp_ch3 => '0',\r
- tx_disp_sel_ch3 => '0',\r
- rxdata_ch3 => rx_data,\r
- rx_k_ch3 => rx_k,\r
- rx_disp_err_ch3 => open,\r
- rx_cv_err_ch3 => rx_error,\r
- rx_serdes_rst_ch3_c => rx_serdes_rst,\r
- sb_felb_ch3_c => '0',\r
- sb_felb_rst_ch3_c => '0',\r
- tx_pcs_rst_ch3_c => tx_pcs_rst,\r
- tx_pwrup_ch3_c => '1',\r
- rx_pcs_rst_ch3_c => rx_pcs_rst,\r
- rx_pwrup_ch3_c => '1',\r
- rx_los_low_ch3_s => rx_los_low,\r
- lsm_status_ch3_s => lsm_status,\r
- rx_cdr_lol_ch3_s => rx_cdr_lol,\r
- tx_div2_mode_ch3_c => '0',\r
- rx_div2_mode_ch3_c => '0',\r
- \r
- SCI_WRDATA => sci_data_in_i,\r
- SCI_RDDATA => sci_data_out_i,\r
- SCI_ADDR => sci_addr_i(5 downto 0),\r
- SCI_SEL_QUAD => sci_qd_i,\r
- SCI_SEL_ch3 => sci_ch_i(3),\r
- SCI_RD => sci_read_i,\r
- SCI_WRN => sci_write_i,\r
- \r
- fpga_txrefclk => rx_full_clk, --clk_200_osc,\r
- tx_serdes_rst_c => tx_serdes_rst,\r
- tx_pll_lol_qd_s => tx_pll_lol,\r
- rst_qd_c => rst_qd,\r
- serdes_rst_qd_c => serdes_rst_qd\r
-\r
- );\r
-\r
-------------------------------------------------- \r
--- Reset FSM & Link states\r
-------------------------------------------------- \r
-THE_RX_FSM : rx_reset_fsm\r
- port map(\r
- RST_N => rst_n,\r
- RX_REFCLK => clk_200_osc, -- allways running PL!\r
- TX_PLL_LOL_QD_S => tx_pll_lol,\r
- RX_SERDES_RST_CH_C => rx_serdes_rst,\r
- RX_CDR_LOL_CH_S => rx_cdr_lol,\r
- RX_LOS_LOW_CH_S => rx_los_low,\r
- RX_PCS_RST_CH_C => rx_pcs_rst,\r
- WA_POSITION => wa_position_rx(15 downto 12),\r
- STATE_OUT => rx_fsm_state\r
- );\r
- \r
-THE_TX_FSM : tx_reset_fsm\r
- port map(\r
- RST_N => rst_n,\r
- TX_REFCLK => clk_200_osc, -- allways running PL! 18-06 was clk_200_i\r
- TX_PLL_LOL_QD_S => tx_pll_lol,\r
- RST_QD_C => rst_qd,\r
- TX_PCS_RST_CH_C => tx_pcs_rst,\r
- STATE_OUT => tx_fsm_state\r
- );\r
-\r
--- Master does not do bit-locking \r
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";\r
-\r
-\r
---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable\r
-PROC_ALLOW : process begin\r
- wait until rising_edge(rx_full_clk); --clk_200_osc); --clk_200_i);\r
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then\r
- rx_allow <= '1';\r
- else\r
- rx_allow <= '0';\r
- end if;\r
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then\r
- tx_allow <= '1';\r
- else\r
- tx_allow <= '0';\r
- end if;\r
-end process;\r
-\r
-rx_allow_q <= rx_allow when rising_edge(rx_half_clk); --SYSCLK);\r
-tx_allow_q <= tx_allow when rising_edge(rx_half_clk); --SYSCLK);\r
-\r
-\r
-PROC_START_TIMER : process(rx_full_clk) --clk_200_osc) --clk_200_i)\r
-begin\r
- if rising_edge(rx_full_clk) then --clk_200_osc) then\r
- if got_link_ready_i = '1' then\r
- watchdog_timer <= (others => '0');\r
- if start_timer(start_timer'left) = '0' then\r
- start_timer <= start_timer + 1;\r
- end if; \r
- else\r
- start_timer <= (others => '0');\r
- if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then\r
- watchdog_trigger <= '1';\r
- else \r
- watchdog_trigger <= '0';\r
- end if;\r
- if watchdog_trigger = '0' then\r
- watchdog_timer <= watchdog_timer + 1;\r
- else \r
- watchdog_timer <= (others => '0');\r
- end if;\r
- end if;\r
- end if;\r
-end process;\r
-------------------------------------------------- \r
--- TX Data\r
-------------------------------------------------- \r
-THE_TX : soda_tx_control\r
- port map(\r
- CLK_200 => rx_full_clk, --clk_200_osc, --clk_200_i,\r
- CLK_100 => rx_half_clk, --SYSCLK,\r
- RESET_IN => rst, --CLEAR, PL!\r
-\r
- TX_DATA_IN => MED_DATA_IN,\r
- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,\r
- TX_WRITE_IN => MED_DATAREADY_IN,\r
- TX_READ_OUT => MED_READ_OUT,\r
-\r
- TX_DATA_OUT => tx_data,\r
- TX_K_OUT => tx_k,\r
-\r
- REQUEST_RETRANSMIT_IN => request_retr_i, --TODO\r
- REQUEST_POSITION_IN => request_retr_position_i, --TODO\r
-\r
- START_RETRANSMIT_IN => start_retr_i, --TODO\r
- START_POSITION_IN => request_retr_position_i, --TODO\r
-\r
- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN,\r
- SEND_DLM => TX_DLM,\r
- SEND_DLM_WORD => TX_DLM_WORD,\r
-\r
- SEND_LINK_RESET_IN => CTRL_OP(15),\r
- TX_ALLOW_IN => tx_allow,\r
- RX_ALLOW_IN => rx_allow,\r
- LINK_PHASE_OUT => link_phase_S, --PL!\r
-\r
- DEBUG_OUT => debug_tx_control_i,\r
- STAT_REG_OUT => stat_tx_control_i\r
-); \r
-\r
-LINK_PHASE_OUT <= link_phase_S; --PL!\r
-------------------------------------------------- \r
--- RX Data\r
-------------------------------------------------- \r
-THE_RX_CONTROL : rx_control\r
- port map(\r
- CLK_200 => rx_full_clk,\r
- CLK_100 => rx_half_clk,\r
- RESET_IN => rst,\r
-\r
- RX_DATA_OUT => MED_DATA_OUT,\r
- RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,\r
- RX_WRITE_OUT => MED_DATAREADY_OUT,\r
- RX_READ_IN => MED_READ_IN,\r
-\r
- RX_DATA_IN => rx_data,\r
- RX_K_IN => rx_k,\r
-\r
- REQUEST_RETRANSMIT_OUT => request_retr_i,\r
- REQUEST_POSITION_OUT => request_retr_position_i,\r
-\r
- START_RETRANSMIT_OUT => start_retr_i,\r
- START_POSITION_OUT => start_retr_position_i,\r
-\r
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM\r
- RX_DLM => RX_DLM,\r
- RX_DLM_WORD => RX_DLM_WORD,\r
- \r
- SEND_LINK_RESET_OUT => send_link_reset_i,\r
- MAKE_RESET_OUT => make_link_reset_i,\r
- RX_ALLOW_IN => rx_allow,\r
- GOT_LINK_READY => got_link_ready_i,\r
-\r
- DEBUG_OUT => debug_rx_control_i,\r
- STAT_REG_OUT => stat_rx_control_i\r
- ); \r
- \r
- \r
- \r
-------------------------------------------------- \r
--- SCI\r
-------------------------------------------------- \r
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us\r
-PROC_SCI_CTRL: process \r
- variable cnt : integer range 0 to 4 := 0;\r
-begin\r
- wait until rising_edge(rx_half_clk); --SYSCLK);\r
- SCI_ACK <= '0';\r
- case sci_state is\r
- when IDLE =>\r
- sci_ch_i <= x"0";\r
- sci_qd_i <= '0';\r
- sci_reg_i <= '0';\r
- sci_read_i <= '0';\r
- sci_write_i <= '0';\r
- sci_timer <= sci_timer + 1;\r
- if SCI_READ = '1' or SCI_WRITE = '1' then\r
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
- sci_addr_i <= SCI_ADDR;\r
- sci_data_in_i <= SCI_DATA_IN;\r
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
- sci_state <= SCTRL;\r
- elsif sci_timer(sci_timer'left) = '1' then\r
- sci_timer <= (others => '0');\r
- sci_state <= GET_WA;\r
- end if; \r
- when SCTRL =>\r
- if sci_reg_i = '1' then\r
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));\r
- SCI_ACK <= '1';\r
- sci_write_i <= '0';\r
- sci_read_i <= '0';\r
- sci_state <= IDLE;\r
- else\r
- sci_state <= SCTRL_WAIT;\r
- end if;\r
- when SCTRL_WAIT =>\r
- sci_state <= SCTRL_WAIT2;\r
- when SCTRL_WAIT2 =>\r
- sci_state <= SCTRL_FINISH;\r
- when SCTRL_FINISH =>\r
- SCI_DATA_OUT <= sci_data_out_i;\r
- SCI_ACK <= '1';\r
- sci_write_i <= '0';\r
- sci_read_i <= '0';\r
- sci_state <= IDLE;\r
- \r
- when GET_WA =>\r
- if cnt = 4 then\r
- cnt := 0;\r
- sci_state <= IDLE;\r
- else\r
- sci_state <= GET_WA_WAIT;\r
- sci_addr_i <= '0' & x"22";\r
- sci_ch_i <= x"0";\r
- sci_ch_i(cnt) <= '1';\r
- sci_read_i <= '1';\r
- end if;\r
- when GET_WA_WAIT =>\r
- sci_state <= GET_WA_WAIT2;\r
- when GET_WA_WAIT2 =>\r
- sci_state <= GET_WA_FINISH;\r
- when GET_WA_FINISH =>\r
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);\r
- sci_state <= GET_WA; \r
- cnt := cnt + 1;\r
- end case;\r
- \r
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then\r
- SCI_NACK <= '1';\r
- else\r
- SCI_NACK <= '0';\r
- end if;\r
- \r
-end process;\r
-\r
-\r
-------------------------------------------------- \r
--- Debug Registers\r
-------------------------------------------------- \r
-debug_reg(3 downto 0) <= rx_fsm_state;\r
-debug_reg(4) <= rx_k;\r
-debug_reg(5) <= rx_error;\r
-debug_reg(6) <= rx_los_low;\r
-debug_reg(7) <= rx_cdr_lol;\r
-\r
-debug_reg(8) <= tx_k;\r
-debug_reg(9) <= tx_pll_lol;\r
-debug_reg(10) <= lsm_status;\r
-debug_reg(11) <= make_link_reset_i;\r
-debug_reg(15 downto 12) <= tx_fsm_state;\r
--- debug_reg(31 downto 24) <= tx_data; \r
-\r
-debug_reg(16) <= '0';\r
-debug_reg(17) <= tx_allow;\r
-debug_reg(18) <= RESET;\r
-debug_reg(19) <= CLEAR;\r
-debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);\r
-\r
-debug_reg(35 downto 32) <= wa_position(3 downto 0);\r
-debug_reg(36) <= debug_tx_control_i(6);\r
-debug_reg(39 downto 37) <= "000";\r
-debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);\r
-\r
- \r
-STAT_DEBUG <= debug_reg;\r
-\r
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';\r
-sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!\r
-\r
-STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);\r
-STAT_OP(14) <= '0';\r
-STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset\r
-STAT_OP(12) <= tx_pll_lol; --'0';\r
-STAT_OP(11) <= rx_cdr_lol; --'0';\r
-STAT_OP(10) <= rx_allow;\r
-STAT_OP(9) <= tx_allow;\r
---STAT_OP(8 downto 4) <= (others => '0');\r
-STAT_OP(8) <= got_link_ready_i when rising_edge(rx_half_clk);\r
-STAT_OP(7) <= send_link_reset_i;\r
-STAT_OP(6) <= make_link_reset_i;\r
-STAT_OP(5) <= request_retr_i;\r
-STAT_OP(4) <= start_retr_i;\r
-STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";\r
-end med_ecp3_sfp_sync_up_arch;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.soda_components.all;
-
-entity soda_4source is
- port(
- SYSCLK : in std_logic; -- fabric clock
- SODACLK : in std_logic;
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
-
- SODA_BURST_PULSE_IN : in std_logic := '0'; --
- SODA_CYCLE_IN : in std_logic := '0'; --
- -- MULTIPLE DUPLEX DOWN-LINKS
- RX_DLM_IN : in t_HUB_BIT;
- RX_DLM_WORD_IN : in t_HUB_BYTE;
- TX_DLM_OUT : out t_HUB_BIT;
- TX_DLM_WORD_OUT : out t_HUB_BYTE;
- TX_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL!
- LINK_PHASE_IN : in t_HUB_BIT; --PL!
-
- SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
- SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
- SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
- SODA_READ_IN : in std_logic := '0';
- SODA_WRITE_IN : in std_logic := '0';
- SODA_ACK_OUT : out std_logic := '0';
- LEDS_OUT : out std_logic_vector(3 downto 0);
- LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
- );
-end soda_4source;
-
-architecture Behavioral of soda_4source is
-
- --SODA
- signal trb_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
- signal trb_cmd_strobe_S : std_logic := '0'; -- for commands sent over trbnet
- signal trb_cmd_strobe_sodaclk_S : std_logic := '0'; -- for commands sent over trbnet
- signal trb_cmd_pending_S : std_logic := '0';
- signal trb_send_cmd_S : std_logic := '0';
- signal soda_cmd_window_S : std_logic := '0';
- signal soda_cmd_pending_S : std_logic := '0';
- signal start_of_superburst_S : std_logic := '0';
- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
- signal soda_reset_S : std_logic;
- signal soda_enable_S : std_logic;
--- signal soda_40mhz_cycle_S : std_logic := '0';
-
--- Signals
- type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
- signal CURRENT_STATE, NEXT_STATE: STATES;
-
- signal last_packet_sent_S : t_PACKET_TYPE_SENT;
- signal expected_reply_S : t_HUB_BYTE_ARRAY;
- signal reply_data_valid_S : t_HUB_BIT_ARRAY := (others => '0');
- signal reply_OK_S : t_HUB_BIT_ARRAY := (others => '0');
- signal send_start_calibration_S : t_HUB_BIT_ARRAY := (others => '0');
- signal start_calibration_S : t_HUB_BIT_ARRAY := (others => '0');
- signal calib_data_valid_S : t_HUB_BIT_ARRAY := (others => '0');
- signal calibration_time_S : t_HUB_WORD_ARRAY := (others => (others => '0'));
--- signal calib_register_s : t_HUB_LWORD_ARRAY := (others => (others => '0'));
- signal reply_timeout_error_S : t_HUB_BIT_ARRAY := (others => '0');
- signal channel_timeout_status_S : t_HUB_BIT_ARRAY := (others => '0');
- signal downstream_error_S : t_HUB_BIT_ARRAY := (others => '0');
- signal report_error_S : t_HUB_BIT_ARRAY;
-
- --signal common_reply_timeout_error_S : std_logic;
- signal common_timeout_status_S : std_logic;
- signal common_downstream_error_S : std_logic;
- signal common_report_error_S : std_logic;
-
- signal dead_channel_S : t_HUB_BIT_ARRAY := (others => '0');
-
- signal COMMON_CTRL_STATUS_register_S: std_logic_vector(31 downto 0);
- signal CTRL_STATUS_register_S : t_HUB_LWORD_ARRAY; -- := (others => (others => '0'));
-
- signal TXstart_of_superburst_S : t_HUB_BIT_ARRAY := (others => '0');
- signal TXsuper_burst_nr_S : t_HUB_LWORD_ARRAY; -- from super-burst-nr-generator
- signal TXsoda_cmd_valid_S : t_HUB_BIT_ARRAY;
- signal TXsoda_cmd_window_S : t_HUB_BIT_ARRAY;
- signal TXsoda_cmd_word_S : t_HUB_LWORD_ARRAY;
-
--- slave bus signals
- signal bus_ack_x : std_logic;
- signal bus_ack : std_logic;
- signal store_wr_x : std_logic;
- signal store_wr : std_logic;
- signal store_rd_x : std_logic;
- signal store_rd : std_logic;
- signal buf_bus_data_out : std_logic_vector(31 downto 0) := (others => '0');
-
--- debug
--- signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0');
--- signal debug_rx_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
--- signal debug_tx_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
--- signal debug_SOS_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
--- signal debug_cmd_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
-
-begin
-
- superburst_gen : soda_superburst_generator
- generic map(BURST_COUNT => 16)
- port map(
- SODACLK => SODACLK,
- RESET => soda_reset_S,
- ENABLE => soda_enable_S,
- SODA_BURST_PULSE_IN => SODA_BURST_PULSE_IN,
- START_OF_SUPERBURST_OUT => start_of_superburst_S,
- SUPER_BURST_NR_OUT => super_burst_nr_S,
- SODA_CMD_WINDOW_OUT => soda_cmd_window_S
- );
-
- channel :for i in c_HUB_CHILDREN-1 downto 0 generate
-
- TXsoda_cmd_valid_S(i) <= trb_cmd_strobe_S; --trb_cmd_valid_S;
- TXsoda_cmd_window_S(i) <= soda_cmd_window_S;
- TXstart_of_superburst_S(i) <= start_of_superburst_S;
- TXsoda_cmd_word_S(i) <= '0' & trb_cmd_word_S;
- TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S;
-
- start_calibration_S(i) <= send_start_calibration_S(i);
-
- packet_builder : soda_packet_builder
- port map(
- SODACLK => SODACLK,
- RESET => RESET,
- --Internal Connection
- LINK_PHASE_IN => LINK_PHASE_IN(i), --link_phase_S, PL!
- SODA_CYCLE_IN => SODA_CYCLE_IN,
- SODA_CMD_WINDOW_IN => TXsoda_cmd_window_S(i),
- SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i),
- START_OF_SUPERBURST => TXstart_of_superburst_S(i),
- SUPER_BURST_NR_IN => TXsuper_burst_nr_S(i)(30 downto 0),
- SODA_CMD_WORD_IN => TXsoda_cmd_word_S(i)(30 downto 0),
- EXPECTED_REPLY_OUT => expected_reply_S(i),
- SEND_TIME_CAL_OUT => send_start_calibration_S(i),
- TX_DLM_PREVIEW_OUT => TX_DLM_PREVIEW_OUT(i),
- TX_DLM_OUT => TX_DLM_OUT(i),
- TX_DLM_WORD_OUT => TX_DLM_WORD_OUT(i)
- );
-
- hub_reply_handler : soda_reply_handler
- port map(
- SODACLK => SODACLK,
- RESET => RESET,
- CLEAR => '0',
- CLK_EN => '1',
- EXPECTED_REPLY_IN => expected_reply_S(i),
- RX_DLM_IN => RX_DLM_IN(i),
- RX_DLM_WORD_IN => RX_DLM_WORD_IN(i),
- REPLY_VALID_OUT => reply_data_valid_S(i),
- REPLY_OK_OUT => reply_OK_S(i)
- );
-
- hub_calibration_timer : soda_calibration_timer
- port map(
- SODACLK => SODACLK,
- RESET => soda_reset_S, --RESET,
- CLEAR => '0',
- CLK_EN => '1',
- --Internal Connection
- START_CALIBRATION => start_calibration_S(i),
- END_CALIBRATION => reply_data_valid_S(i),
- VALID_OUT => calib_data_valid_S(i),
- CALIB_TIME_OUT => calibration_time_S(i),
- TIMEOUT_ERROR => reply_timeout_error_S(i)
- );
-
- sodahub_calib_timeout_proc : process(SODACLK)
- begin
- if rising_edge(SODACLK) then
- if( RESET = '1' ) then
- downstream_error_S(i) <= '0';
- channel_timeout_status_S(i) <= '0';
- report_error_S(i) <= '0';
- elsif (soda_reset_S = '1') then -- check if slowcontrol wants to reset errors
- channel_timeout_status_S(i) <= '0';
- downstream_error_S(i) <= '0'; -- set CALIBRATION_TIMEOUT_ERROR status-bit
- report_error_S(i) <= '0'; -- reset REPORT_ERROR status-bit
- elsif (reply_data_valid_S(i) = '1') then -- the reply was correct
- channel_timeout_status_S(i) <= '0';
- if (reply_OK_S(i) = '1') then
- downstream_error_S(i) <= '0';
- report_error_S(i) <= '0'; -- reset REPORT_ERROR status-bit
- elsif (dead_channel_S(i) = '0') then
- downstream_error_S(i) <= '1';
- report_error_S(i) <= '1'; -- set REPORT_ERROR status-bit
- else
- downstream_error_S(i) <= '1';
- report_error_S(i) <= '0'; -- reset REPORT_ERROR status-bit
- end if;
- elsif (reply_timeout_error_S(i) = '1') then --and (reply_OK_S(i) = '1')) then
- if (dead_channel_S(i) = '0') then
- channel_timeout_status_S(i) <= '1';
- report_error_S(i) <= '1'; -- set REPORT_ERROR status-bit
- else
- channel_timeout_status_S(i) <= '1';
- report_error_S(i) <= '0'; -- reset REPORT_ERROR status-bit
- end if;
- end if;
- end if;
- end process;
-
- ---------------------------------------------------------
- -- Control bits --
- ---------------------------------------------------------
- dead_channel_S(i) <= CTRL_STATUS_register_S(i)(29); -- slow-control can declare a channel dead
- ---------------------------------------------------------
- -- Status bits --
- ---------------------------------------------------------
- CTRL_STATUS_SYNC: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 3
- )
- port map(
- RESET => RESET,
- D_IN(0) => report_error_S(i),
- D_IN(1) => downstream_error_S(i),
- D_IN(2) => channel_timeout_status_S(i),
- CLK0 => SYSCLK,
- CLK1 => SODACLK,
- D_OUT(0) => CTRL_STATUS_register_S(i)(15),
- D_OUT(1) => CTRL_STATUS_register_S(i)(1),
- D_OUT(2) => CTRL_STATUS_register_S(i)(0)
- );\r
- \r
- --CTRL_STATUS_register_S(i)(15) <= report_error_S(i);
- CTRL_STATUS_register_S(i)(14 downto 2) <= (others => '0');
- --CTRL_STATUS_register_S(i)(1) <= downstream_error_S(i);
- --CTRL_STATUS_register_S(i)(0) <= channel_timeout_status_S(i);
-
- end generate;
-
- soda_reset_S <= (RESET or COMMON_CTRL_STATUS_register_S(31));
- soda_enable_S <= COMMON_CTRL_STATUS_register_S(30);
- common_downstream_error_S <= '1' when ((downstream_error_S(0)='1') or (downstream_error_S(1)='1') or (downstream_error_S(2)='1') or (downstream_error_S(3)='1'))
- else '0';
- common_report_error_S <= '1' when ((report_error_S(0)='1') or (report_error_S(1)='1') or (report_error_S(2)='1') or (report_error_S(3)='1'))
- else '0';\r
- common_timeout_status_S <= '1' when ((channel_timeout_status_S(0)='1') or (channel_timeout_status_S(1)='1') or (channel_timeout_status_S(2)='1')) or ((channel_timeout_status_S(3)='1'))
- else '0';
- COMMON_CTRL_STATUS_register_S(15) <= common_report_error_S;
- COMMON_CTRL_STATUS_register_S(14 downto 2) <= (others => '0');
- COMMON_CTRL_STATUS_register_S(1) <= common_downstream_error_S;
- COMMON_CTRL_STATUS_register_S(0) <= common_timeout_status_S;
-\r
----------------------------------------------------------
--- RegIO Statemachine
----------------------------------------------------------
- STATE_MEM: process( SYSCLK)
- begin
- if( rising_edge(SYSCLK) ) then
- if( RESET = '1' ) then
- CURRENT_STATE <= SLEEP;
- bus_ack <= '0';
- store_wr <= '0';
- store_rd <= '0';
- else
- CURRENT_STATE <= NEXT_STATE;
- bus_ack <= bus_ack_x;
- store_wr <= store_wr_x;
- store_rd <= store_rd_x;
- end if;
- end if;
- end process STATE_MEM;
-
--- Transition matrix
- TRANSFORM: process(CURRENT_STATE, SODA_READ_IN, SODA_WRITE_IN )
- begin
- NEXT_STATE <= SLEEP;
- bus_ack_x <= '0';
- store_wr_x <= '0';
- store_rd_x <= '0';
- case CURRENT_STATE is
- when SLEEP =>
- if ( (SODA_READ_IN = '1') ) then
- NEXT_STATE <= RD_RDY;
- store_rd_x <= '1';
- elsif( (SODA_WRITE_IN = '1') ) then
- NEXT_STATE <= WR_RDY;
- store_wr_x <= '1';
- else
- NEXT_STATE <= SLEEP;
- end if;
- when RD_RDY =>
- NEXT_STATE <= RD_ACK;
- when WR_RDY =>
- NEXT_STATE <= WR_ACK;
- when RD_ACK =>
- if( SODA_READ_IN = '0' ) then
- NEXT_STATE <= DONE;
- bus_ack_x <= '1';
- else
- NEXT_STATE <= RD_ACK;
- bus_ack_x <= '1';
- end if;
- when WR_ACK =>
- if( SODA_WRITE_IN = '0' ) then
- NEXT_STATE <= DONE;
- bus_ack_x <= '1';
- else
- NEXT_STATE <= WR_ACK;
- bus_ack_x <= '1';
- end if;
- when DONE =>
- NEXT_STATE <= SLEEP;
- when others =>
- NEXT_STATE <= SLEEP;
- end case;
-end process TRANSFORM;
-
-
-soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse
- port map(
- IN_CLK => SYSCLK,
- OUT_CLK => SODACLK,
- CLK_EN => '1',
- SIGNAL_IN => trb_cmd_strobe_S,
- PULSE_OUT => trb_cmd_strobe_sodaclk_S
- );
-
----------------------------------------------------------
--- data handling --
----------------------------------------------------------
--- For sim purposes the CLIENT gets addresses 11XX
--- register write
- THE_WRITE_REG_PROC: process( SYSCLK )
- begin
- if( rising_edge(SYSCLK) ) then
- if ( RESET = '1' ) then
- trb_cmd_strobe_S <= '0';
- trb_cmd_word_S <= (others => '0');
- COMMON_CTRL_STATUS_register_S(31 downto 16) <= (30 => '1', others => '0'); -- enable soda by default
- CTRL_STATUS_register_S(0)(31 downto 16) <= (others => '0');
- CTRL_STATUS_register_S(1)(31 downto 16) <= (others => '0');
- CTRL_STATUS_register_S(2)(31 downto 16) <= (others => '0');
- CTRL_STATUS_register_S(3)(31 downto 16) <= (others => '0');
- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0000") ) then
- trb_cmd_strobe_S <= '1';
- trb_cmd_word_S <= SODA_DATA_IN(30 downto 0);
- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0011") ) then
- trb_cmd_strobe_S <= '0';
- COMMON_CTRL_STATUS_register_S(31 downto 16) <= SODA_DATA_IN(31 downto 16); -- use only the 16 lower bits for control
- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0100") ) then
- trb_cmd_strobe_S <= '0';
- CTRL_STATUS_register_S(0)(31 downto 16) <= SODA_DATA_IN(31 downto 16); -- use only the 16 lower bits for control
- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0101") ) then
- trb_cmd_strobe_S <= '0';
- CTRL_STATUS_register_S(1)(31 downto 16) <= SODA_DATA_IN(31 downto 16); -- use only the 16 lower bits for control
- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0110") ) then
- trb_cmd_strobe_S <= '0';
- CTRL_STATUS_register_S(2)(31 downto 16) <= SODA_DATA_IN(31 downto 16); -- use only the 16 lower bits for control
- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0111") ) then
- trb_cmd_strobe_S <= '0';
- CTRL_STATUS_register_S(3)(31 downto 16) <= SODA_DATA_IN(31 downto 16); -- use only the 16 lower bits for control
- else
- trb_cmd_strobe_S <= '0';
- end if;
- end if;
- end process THE_WRITE_REG_PROC;
-
-
--- register read
- THE_READ_REG_PROC: process( SYSCLK )
- begin
- if( rising_edge(SYSCLK) ) then
- if ( RESET = '1' ) then
- buf_bus_data_out <= (others => '0');
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0000") ) then
- buf_bus_data_out <= '0' & trb_cmd_word_S;
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0001") ) then
- buf_bus_data_out <= '0' & super_burst_nr_S;
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
- buf_bus_data_out <= COMMON_CTRL_STATUS_register_S;
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then
- buf_bus_data_out <= CTRL_STATUS_register_S(0);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then
- buf_bus_data_out <= CTRL_STATUS_register_S(1);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then
- buf_bus_data_out <= CTRL_STATUS_register_S(2);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0111") ) then
- buf_bus_data_out <= CTRL_STATUS_register_S(3);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "1000") ) then
- buf_bus_data_out <= x"0000" & calibration_time_S(0);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "1001") ) then
- buf_bus_data_out <= x"0000" & calibration_time_S(1);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "1010") ) then
- buf_bus_data_out <= x"0000" & calibration_time_S(2);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "1011") ) then
- buf_bus_data_out <= x"0000" & calibration_time_S(3);
- end if;
- end if;
- end process THE_READ_REG_PROC;
-
- LEDS_OUT <= (others => '0'); --LEDregister_i(3 downto 0);
-
- SODA_DATA_OUT <= buf_bus_data_out;
- SODA_ACK_OUT <= bus_ack;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-################################################################################
-#### This file contains constraints from Synplicity SDC files that have been
-#### translated into Synopsys FPGA Design Constraints (FDC).
-#### Translated FDC output file:
-#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-#### client SDC files to the translation:
-#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-################################################################################
-
-
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/code/soda_hub_synconstraints.fdc
-# Written on Tue May 20 15:36:03 2014
-# by Synplify Pro, I-2013.09L FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
-
-################################################################################
-#### The following Synplicity constraints from file:
-#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-#### are disabled and have not been translated.
-##############################################################################
-# FDC constraints translated from Synplify Legacy Timing & Design Constraints
-##############################################################################
-
-set_rtl_ff_names {}
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable
-define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable
-define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable
-define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable
-###==== END Collections
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -add
-create_clock -name {THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch1} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch1} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch2} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch2} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
-###==== END Clocks
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
-
-
-
-
-
-
-
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.soda_components.all;
-
-entity soda_start_of_burst_faker is
- generic(
- CLOCK_PERIOD : natural range 1 to 20 := cSODA_CLOCK_PERIOD; -- clock-period in ns
- BURST_PERIOD : natural := cBURST_PERIOD -- burst-period in ns
- );
- port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- SODA_BURST_PULSE_OUT : out std_logic := '0'
- );
-end soda_start_of_burst_faker;
-
-architecture Behavioral of soda_start_of_burst_faker is
-
- constant cCLOCKS_PER_BURST : std_logic_vector(15 downto 0) := conv_std_logic_vector((BURST_PERIOD / CLOCK_PERIOD) - 1, 16);
-
- signal burst_counter_S : std_logic_vector(15 downto 0) := (others => '0'); -- from super-burst-nr-generator
-
-
-begin
-
- burst_pulse_edge_proc : process(SYSCLK)
- begin
- if rising_edge(SYSCLK) then
- if (RESET='1') then
- burst_counter_S <= cCLOCKS_PER_BURST;
- SODA_BURST_PULSE_OUT <= '0';
- elsif (burst_counter_S=0) then
- burst_counter_S <= cCLOCKS_PER_BURST;
- SODA_BURST_PULSE_OUT <= '1';
- else
- burst_counter_S <= burst_counter_S - 1;
- SODA_BURST_PULSE_OUT <= '0';
- end if;
- end if;
- end process;
-
-
-end Behavioral;
+++ /dev/null
-################################################################################
-#### This file contains constraints from Synplicity SDC files that have been
-#### translated into Synopsys FPGA Design Constraints (FDC).
-#### Translated FDC output file:
-#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-#### client SDC files to the translation:
-#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-################################################################################
-
-
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-# Written on Wed Dec 18 11:52:15 2013
-# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
-
-################################################################################
-#### The following Synplicity constraints from file:
-#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-#### are disabled and have not been translated.
-##############################################################################
-# FDC constraints translated from Synplify Legacy Timing & Design Constraints
-##############################################################################
-
-set_rtl_ff_names {}
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable
-define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable
-define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable
-define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable
-###==== END Collections
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0}
-create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5}
-create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5}
-create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0}
-create_clock -name {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5}\r
-\r
-
-#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} -period {10.0} -waveform {0 5.0}
-#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} -period {5.0} -waveform {0 2.5}
-set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} }
-set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} }
-###==== END Clocks
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.soda_components.all;
-
-entity soda_clockscaler is
- port(
- CLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLOCK_ENABLE_OUT : out std_logic := '0';
- CLOCK_OUT : out std_logic := '0'
- );
-end soda_clockscaler;
-
-architecture Behavioral of soda_clockscaler is
-
- signal counter_S : std_logic_vector(24 downto 0) := (others => '0'); -- from super-burst-nr-generator
- signal clock_out_S : std_logic := '0';
-
-begin
-\r
- CLOCK_OUT <= clock_out_S;\r
-
- pulse_edge_proc : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET='1') then
- counter_S <= (others => '1');
- CLOCK_ENABLE_OUT <= '0';\r
- clock_out_S <= '0';
- elsif (counter_S=0) then
- counter_S <= (others => '1');
- CLOCK_ENABLE_OUT <= '1';\r
- clock_out_S <= not(clock_out_S);
- else
- counter_S <= counter_S - 1;
- CLOCK_ENABLE_OUT <= '0';
- end if;
- end if;
- end process;
-
-
-end Behavioral;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.soda_components.all;
-
-entity soda_cmd_handler is
- port(
- SODACLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
--- CLEAR : in std_logic; -- asynchronous reset
--- CLK_EN : in std_logic;
- --Internal Connection
- START_OF_SUPERBURST_IN : in std_logic := '0';
- SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');
- SODA_CMD_VALID_IN : out std_logic := '0';
- SODA_CMD_WORD_IN : out std_logic_vector(30 downto 0) := (others => '0');
--- EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- CRC_VALID_OUT : out std_logic := '0';
- CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- RX_DLM_IN : in std_logic;
- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0')
- );
-end soda_cmd_handler;
-
-architecture Behavioral of soda_cmd_handler is
-
- signal soda_pkt_word_S : std_logic_vector(31 downto 0) := (others => '0');
- signal soda_pkt_valid_S : std_logic := '0';
-
- type packet_state_type is ( c_RST, c_IDLE, c_ERROR,
- c_SODA_PKT1, c_SODA_PKT2, c_SODA_PKT3, c_SODA_PKT4,
- c_SODA_PKT5, c_SODA_PKT6, c_SODA_PKT7, c_SODA_PKT8
- );
- signal packet_state_S : packet_state_type := c_IDLE;
-
-begin
-
- packet_fsm_proc : process(SODACLK)
- begin
- if rising_edge(SODACLK) then
- if (RESET='1') then
- packet_state_S <= c_RST;
- else
- case packet_state_S is
- when c_RST =>
- if (RX_DLM_IN='1') then -- received K28.7 #1
- packet_state_S <= c_SODA_PKT1;
- else
- packet_state_S <= c_IDLE;
- end if;
- when c_IDLE =>
- if (RX_DLM_IN='1') then -- received K28.7 #1
- packet_state_S <= c_SODA_PKT1;
- else
- packet_state_S <= c_IDLE;
- end if;
- when c_SODA_PKT1 =>
- if (RX_DLM_IN='0') then -- possibly received data-byte
- packet_state_S <= c_SODA_PKT2;
- else
- packet_state_S <= c_ERROR;
- end if;
- when c_SODA_PKT2 =>
- if (RX_DLM_IN='1') then -- received K28.7 #2
- packet_state_S <= c_SODA_PKT3;
- else
- packet_state_S <= c_ERROR;
- end if;
- when c_SODA_PKT3 =>
- if (RX_DLM_IN='0') then -- possibly received data-byte
- packet_state_S <= c_SODA_PKT4;
- else
- packet_state_S <= c_ERROR;
- end if;
- when c_SODA_PKT4 =>
- if (RX_DLM_IN='1') then -- received K28.7 #3
- packet_state_S <= c_SODA_PKT5;
- else
- packet_state_S <= c_ERROR;
- end if;
- when c_SODA_PKT5 =>
- if (RX_DLM_IN='0') then -- possibly received data-byte
- packet_state_S <= c_SODA_PKT6;
- else
- packet_state_S <= c_ERROR;
- end if;
- when c_SODA_PKT6 =>
- if (RX_DLM_IN='1') then -- received K28.7 #4
- packet_state_S <= c_SODA_PKT7;
- else
- packet_state_S <= c_ERROR;
- -- else do nothing
- end if;
- when c_SODA_PKT7 =>
- if (RX_DLM_IN='1') then
- packet_state_S <= c_ERROR; -- if there's an unexpected K28.7 there's too much data
- else
- packet_state_S <= c_SODA_PKT8;
- end if;
- when c_SODA_PKT8 =>
- if (RX_DLM_IN='1') then -- received K28.7 #4+1... must be another packet coming in....
- packet_state_S <= c_SODA_PKT1;
- else
- packet_state_S <= c_IDLE;
- end if;
- when c_ERROR =>
- packet_state_S <= c_IDLE; -- TODO: Insert ERROR_HANDLER
- when others =>
- packet_state_S <= c_IDLE;
- end case;
- end if;
- end if;
- end process;
-
- soda_packet_collector_proc : process(SODACLK, packet_state_S)
- begin
- if rising_edge(SODACLK) then
- case packet_state_S is
- when c_RST =>
- START_OF_SUPERBURST_OUT <= '0';
- SODA_CMD_VALID_OUT <= '0';
- soda_pkt_valid_S <= '0';
- soda_pkt_word_S <= (others=>'0');
- when c_IDLE =>
- START_OF_SUPERBURST_OUT <= '0';
- SODA_CMD_VALID_OUT <= '0';
- soda_pkt_valid_S <= '0';
- soda_pkt_word_S <= (others=>'0');
- when c_SODA_PKT1 =>
- START_OF_SUPERBURST_OUT <= '0';
- SODA_CMD_VALID_OUT <= '0';
- soda_pkt_word_S(31 downto 24) <= RX_DLM_WORD_IN;
- when c_SODA_PKT2 =>
- -- do nothing -- disregard K28.7
- when c_SODA_PKT3 =>
- soda_pkt_word_S(23 downto 16) <= RX_DLM_WORD_IN;
- when c_SODA_PKT4 =>
- -- do nothing -- disregard K28.7
- when c_SODA_PKT5 =>
- soda_pkt_word_S(15 downto 8) <= RX_DLM_WORD_IN;
- when c_SODA_PKT6 =>
- -- do nothing -- disregard K28.7
- when c_SODA_PKT7 =>
- soda_pkt_word_S(7 downto 0) <= RX_DLM_WORD_IN; -- get transmitted CRC
- when c_SODA_PKT8 =>
- soda_pkt_valid_S <= '1';
- if (soda_pkt_word_S(31)= '1') then
- START_OF_SUPERBURST_OUT <= '1';
- SUPER_BURST_NR_OUT <= soda_pkt_word_S(30 downto 0);
- else
- SODA_CMD_VALID_OUT <= '1';
- SODA_CMD_WORD_OUT <= soda_pkt_word_S(30 downto 0);
- end if;
- when others =>
- START_OF_SUPERBURST_OUT <= '0';
- soda_pkt_valid_S <= '0';
- soda_pkt_word_S <= (others=>'0');
- SODA_CMD_VALID_OUT <= '0';
- SODA_CMD_WORD_OUT <= (others=>'0');
- end case;
-
- end if;
- end process;
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.soda_components.all;
-
-entity soda_cmd_window_generator is
- generic( CLOCK_PERIOD : natural range 1 to 20 := cSODA_CLOCK_PERIOD; -- clock-period in ns
- COMMAND_WINDOS_SIZE : natural range 1 to 65335 := cSODA_COMMAND_WINDOS_SIZE -- command window size in ns \r
- );
- port(
- SODACLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- START_OF_SUPERBURST_IN : in std_logic := '0'; --
- SODA_CMD_WINDOW_OUT : out std_logic := '0'
- );
-end soda_cmd_window_generator;
-
-architecture Behavioral of soda_cmd_window_generator is
-
-
- signal window_delay_counter_S : std_logic_vector(7 downto 0) := (others => '0'); --
- signal window_size_counter_S : std_logic_vector(15 downto 0) := (others => '0'); --
-
-
-begin
-
-
- soda_cmd_window_proc : process(SODACLK)
- begin
- if rising_edge(SODACLK) then
- if (RESET='1') then
- window_delay_counter_S <= (others => '0');
- window_size_counter_S <= (others => '0');
- SODA_CMD_WINDOW_OUT <= '0';
- elsif (START_OF_SUPERBURST_IN = '1') then\r
- window_delay_counter_S <= cWINDOW_delay;\r
- elsif (window_delay_counter_S > 0) then\r
- window_delay_counter_S <= window_delay_counter_S -1;\r
- end if;\r
- \r
- if (window_delay_counter_S = 1) then\r
- window_size_counter_S <= cCLOCKS_PER_WINDOW;\r
- elsif (window_size_counter_S > 0) then\r
- SODA_CMD_WINDOW_OUT <= '1';\r
- window_size_counter_S <= window_size_counter_S - 1;\r
- else\r
- SODA_CMD_WINDOW_OUT <= '0';\r
- end if;
-
- end if;
- end process;
-
-end Behavioral;
+++ /dev/null
-################################################################################
-#### This file contains constraints from Synplicity SDC files that have been
-#### translated into Synopsys FPGA Design Constraints (FDC).
-#### Translated FDC output file:
-#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-#### client SDC files to the translation:
-#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-################################################################################
-
-
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/code/soda_hub_synconstraints.fdc
-# Written on Tue May 20 15:36:03 2014
-# by Synplify Pro, I-2013.09L FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
-
-################################################################################
-#### The following Synplicity constraints from file:
-#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-#### are disabled and have not been translated.
-##############################################################################
-# FDC constraints translated from Synplify Legacy Timing & Design Constraints
-##############################################################################
-
-set_rtl_ff_names {}
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable
-define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable
-define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable
-define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable
-###==== END Collections
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -add
-create_clock -name {THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch1} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch1} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch2} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch2} -period {5.0} -waveform {0 2.5} -add
-create_clock -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
-###==== END Clocks
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
-
-
-
-
-
-
-
+++ /dev/null
---4 channel Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity soda_only_ecp3_sfp_4_sync_down is
- generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave
- port(
- OSC_CLK : in std_logic; -- 200 MHz reference clock
- TX_DATACLK : in std_logic; -- 200 MHz data clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
--- LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
- TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
- TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
-
- --Sync operation
- RX_DLM_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
- RX_DLM_WORD_OUT : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0');
- TX_DLM_WORD_IN : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0');
- TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
- LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL!
-
- --SFP Connection
- SD_RXD_P_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_RXD_N_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_TXD_P_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_TXD_N_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0);
- SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used
- SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used
- SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0'\r
- );
-end entity;
-
-
-architecture soda_only_ecp3_sfp_4_sync_down_arch of soda_only_ecp3_sfp_4_sync_down is
-
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of soda_only_ecp3_sfp_4_sync_down_arch : architecture is "media_downlink_group";
- attribute syn_sharing : string;
- attribute syn_sharing of soda_only_ecp3_sfp_4_sync_down_arch : architecture is "off";
-
-
-
-signal clk_200_osc : std_logic;
-signal clk_200_txdata : std_logic;
-signal rx_full_clk : std_logic_vector(3 downto 0);
-signal rx_half_clk : std_logic_vector(3 downto 0);
-signal tx_full_clk : std_logic_vector(3 downto 0);
-signal tx_half_clk : std_logic_vector(3 downto 0);
-
-type t_tx_state is (cRESET,cSEND_IDLE,cSEND_DLM);
-type t_tx_proc_state is array(c_HUB_CHILDREN-1 downto 0) of t_tx_state;
-signal tx_proc_state : t_tx_proc_state;
-
-signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
-signal tx_k : std_logic_vector(3 downto 0);
-signal rx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0);
-signal rx_k : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0);
-
-signal rst_n : t_HUB_BIT;
-signal rst : t_HUB_BIT; -- PL!
-signal rx_serdes_rst : t_HUB_BIT;
-signal tx_serdes_rst : std_logic;
-signal tx_pcs_rst : t_HUB_BIT;
-signal rx_pcs_rst : t_HUB_BIT;
-signal rst_qd : t_HUB_BIT;
-signal rst_down_quad : std_logic;
-signal serdes_rst_qd : t_HUB_BIT;
-signal serdes_rst_down_quad : std_logic; -- combined serdes reset for whole quad
-signal sd_los_i : t_HUB_BIT; --PL!
-\r
-signal dlm_received_S : t_HUB_BIT;
-\r
-
-signal rx_los_low : t_HUB_BIT;
-signal lsm_status : t_HUB_BIT;
-signal rx_cdr_lol : t_HUB_BIT;
-signal tx_pll_lol : t_HUB_BIT;
-signal tx_pll_lol_quad : std_logic; -- combined Loss-Of-Lock for whole quad
-
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
-signal sci_data_in_i : std_logic_vector(7 downto 0);
-signal sci_data_out_i : std_logic_vector(7 downto 0);
-signal sci_read_i : std_logic;
-signal sci_write_i : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
-signal wa_position : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx : t_HUB_NIBL := (others => (others => '1')); --std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_allow : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal tx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal rx_allow_q : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal link_phase_S : t_HUB_BIT; --std_logic_vector(3 downto 0); --PL!
-signal request_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal start_retr_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal request_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
-signal start_retr_position_i : t_HUB_BYTE; --std_logic_vector(7 downto 0);
-signal send_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal make_link_reset_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal got_link_ready_i : t_HUB_BIT; --std_logic_vector(3 downto 0);
-signal internal_make_link_reset_out : t_HUB_BIT; --std_logic_vector(3 downto 0);
-
-signal start_timer : t_HUB_TIMER19 := (others => (others => '0')); --unsigned(18 downto 0) := (others => '0');
-
-signal rx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
-signal tx_fsm_state : t_HUB_NIBL; --std_logic_vector(3 downto 0);
-
-signal stat_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal stat_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_rx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_tx_control_i : t_HUB_LWORD; --std_logic_vector(31 downto 0);
-signal debug_reg : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state : sci_ctrl;
-signal sci_timer : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0) := (others => '0');
-\r
--- fix signal names for constraining
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_useioff : boolean;
-
-attribute syn_useioff of sd_los_i : signal is false; -- do not use an IOFF for this signal
-\r
-attribute syn_preserve of sci_ch_i : signal is true;
-attribute syn_keep of sci_ch_i : signal is true;
-attribute syn_preserve of sci_qd_i : signal is true;
-attribute syn_keep of sci_qd_i : signal is true;
-attribute syn_preserve of sci_reg_i : signal is true;
-attribute syn_keep of sci_reg_i : signal is true;
-attribute syn_preserve of sci_addr_i : signal is true;
-attribute syn_keep of sci_addr_i : signal is true;
-attribute syn_preserve of sci_data_in_i : signal is true;
-attribute syn_keep of sci_data_in_i : signal is true;
-attribute syn_preserve of sci_data_out_i : signal is true;
-attribute syn_keep of sci_data_out_i : signal is true;
-attribute syn_preserve of sci_read_i : signal is true;
-attribute syn_keep of sci_read_i : signal is true;
-attribute syn_preserve of sci_write_i : signal is true;
-attribute syn_keep of sci_write_i : signal is true;
-attribute syn_preserve of sci_write_shift_i : signal is true;
-attribute syn_keep of sci_write_shift_i : signal is true;
-attribute syn_preserve of sci_read_shift_i : signal is true;
-attribute syn_keep of sci_read_shift_i : signal is true;
-
-begin
-
-
---SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-
-clk_200_osc <= OSC_CLK; -- This external clock is oscillator/pll generated !!!
-clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!!
-
-
-gen_clocks : for i in 0 to 3 generate
-
- rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i));
- rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i));
-
- RX_HALF_CLK_OUT(i) <= rx_half_clk(i);
- RX_FULL_CLK_OUT(i) <= rx_full_clk(i);
- TX_HALF_CLK_OUT(i) <= tx_half_clk(i);
- TX_FULL_CLK_OUT(i) <= tx_full_clk(i);
-
--- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master
--- clk_200_i(i) <= rx_full_clk(i);
--- end generate;
-
--- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i(i) <= clk_200_txdata;
--- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!!
--- end generate;
-end generate;
-
--------------------------------------------------
--- Serdes
--------------------------------------------------
-THE_SERDES : entity work.serdes_4_sync_downstream
- port map(
- -- CHANNEL0 --
- hdinp_ch0 => SD_RXD_P_IN(0),
- hdinn_ch0 => SD_RXD_N_IN(0),
- hdoutp_ch0 => SD_TXD_P_OUT(0),
- hdoutn_ch0 => SD_TXD_N_OUT(0),
- rxiclk_ch0 => clk_200_txdata,
- sci_sel_ch0 => sci_ch_i(0),
- txiclk_ch0 => clk_200_txdata,
- rx_full_clk_ch0 => rx_full_clk(0),
- rx_half_clk_ch0 => rx_half_clk(0),
- tx_full_clk_ch0 => tx_full_clk(0),
- tx_half_clk_ch0 => tx_half_clk(0),
- fpga_rxrefclk_ch0 => clk_200_osc,
- txdata_ch0 => tx_data(0),
- tx_k_ch0 => tx_k(0),
- tx_force_disp_ch0 => '0',
- tx_disp_sel_ch0 => '0',
- rxdata_ch0 => rx_data(0),
- rx_k_ch0 => rx_k(0),
- rx_disp_err_ch0 => open,
- rx_cv_err_ch0 => rx_error(0),
- rx_serdes_rst_ch0_c => rx_serdes_rst(0),
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pcs_rst_ch0_c => tx_pcs_rst(0),
- tx_pwrup_ch0_c => '1',
- rx_pcs_rst_ch0_c => rx_pcs_rst(0),
- rx_pwrup_ch0_c => '1',
- rx_los_low_ch0_s => rx_los_low(0),
- lsm_status_ch0_s => lsm_status(0),
- rx_cdr_lol_ch0_s => rx_cdr_lol(0),
- tx_div2_mode_ch0_c => '0',
- rx_div2_mode_ch0_c => '0',
- -- CHANNEL1 --
- hdinp_ch1 => SD_RXD_P_IN(1),
- hdinn_ch1 => SD_RXD_N_IN(1),
- hdoutp_ch1 => SD_TXD_P_OUT(1),
- hdoutn_ch1 => SD_TXD_N_OUT(1),
- rxiclk_ch1 => clk_200_txdata,
- sci_sel_ch1 => sci_ch_i(1),
- txiclk_ch1 => clk_200_txdata,
- rx_full_clk_ch1 => rx_full_clk(1),
- rx_half_clk_ch1 => rx_half_clk(1),
- tx_full_clk_ch1 => tx_full_clk(1),
- tx_half_clk_ch1 => tx_half_clk(1),
- fpga_rxrefclk_ch1 => clk_200_osc,
- txdata_ch1 => tx_data(1),
- tx_k_ch1 => tx_k(1),
- tx_force_disp_ch1 => '0',
- tx_disp_sel_ch1 => '0',
- rxdata_ch1 => rx_data(1),
- rx_k_ch1 => rx_k(1),
- rx_disp_err_ch1 => open,
- rx_cv_err_ch1 => rx_error(1),
- rx_serdes_rst_ch1_c => rx_serdes_rst(1),
- sb_felb_ch1_c => '0',
- sb_felb_rst_ch1_c => '0',
- tx_pcs_rst_ch1_c => tx_pcs_rst(1),
- tx_pwrup_ch1_c => '1',
- rx_pcs_rst_ch1_c => rx_pcs_rst(1),
- rx_pwrup_ch1_c => '1',
- rx_los_low_ch1_s => rx_los_low(1),
- lsm_status_ch1_s => lsm_status(1),
- rx_cdr_lol_ch1_s => rx_cdr_lol(1),
- tx_div2_mode_ch1_c => '0',
- rx_div2_mode_ch1_c => '0',
- -- CHANNEL2 --
- hdinp_ch2 => SD_RXD_P_IN(2),
- hdinn_ch2 => SD_RXD_N_IN(2),
- hdoutp_ch2 => SD_TXD_P_OUT(2),
- hdoutn_ch2 => SD_TXD_N_OUT(2),
- rxiclk_ch2 => clk_200_txdata,
- sci_sel_ch2 => sci_ch_i(2),
- txiclk_ch2 => clk_200_txdata,
- rx_full_clk_ch2 => rx_full_clk(2),
- rx_half_clk_ch2 => rx_half_clk(2),
- tx_full_clk_ch2 => tx_full_clk(2),
- tx_half_clk_ch2 => tx_half_clk(2),
- fpga_rxrefclk_ch2 => clk_200_osc,
- txdata_ch2 => tx_data(2),
- tx_k_ch2 => tx_k(2),
- tx_force_disp_ch2 => '0',
- tx_disp_sel_ch2 => '0',
- rxdata_ch2 => rx_data(2),
- rx_k_ch2 => rx_k(2),
- rx_disp_err_ch2 => open,
- rx_cv_err_ch2 => rx_error(2),
- rx_serdes_rst_ch2_c => rx_serdes_rst(2),
- sb_felb_ch2_c => '0',
- sb_felb_rst_ch2_c => '0',
- tx_pcs_rst_ch2_c => tx_pcs_rst(2),
- tx_pwrup_ch2_c => '1',
- rx_pcs_rst_ch2_c => rx_pcs_rst(2),
- rx_pwrup_ch2_c => '1',
- rx_los_low_ch2_s => rx_los_low(2),
- lsm_status_ch2_s => lsm_status(2),
- rx_cdr_lol_ch2_s => rx_cdr_lol(2),
- tx_div2_mode_ch2_c => '0',
- rx_div2_mode_ch2_c => '0',
- -- CHANNEL3 --
- hdinp_ch3 => SD_RXD_P_IN(3),
- hdinn_ch3 => SD_RXD_N_IN(3),
- hdoutp_ch3 => SD_TXD_P_OUT(3),
- hdoutn_ch3 => SD_TXD_N_OUT(3),
- rxiclk_ch3 => clk_200_txdata,
- sci_sel_ch3 => sci_ch_i(3),
- txiclk_ch3 => clk_200_txdata,
- rx_full_clk_ch3 => rx_full_clk(3),
- rx_half_clk_ch3 => rx_half_clk(3),
- tx_full_clk_ch3 => tx_full_clk(3),
- tx_half_clk_ch3 => tx_half_clk(3),
- fpga_rxrefclk_ch3 => clk_200_osc,
- txdata_ch3 => tx_data(3),
- tx_k_ch3 => tx_k(3),
- tx_force_disp_ch3 => '0',
- tx_disp_sel_ch3 => '0',
- rxdata_ch3 => rx_data(3),
- rx_k_ch3 => rx_k(3),
- rx_disp_err_ch3 => open,
- rx_cv_err_ch3 => rx_error(3),
- rx_serdes_rst_ch3_c => rx_serdes_rst(3),
- sb_felb_ch3_c => '0',
- sb_felb_rst_ch3_c => '0',
- tx_pcs_rst_ch3_c => tx_pcs_rst(3),
- tx_pwrup_ch3_c => '1',
- rx_pcs_rst_ch3_c => rx_pcs_rst(3),
- rx_pwrup_ch3_c => '1',
- rx_los_low_ch3_s => rx_los_low(3),
- lsm_status_ch3_s => lsm_status(3),
- rx_cdr_lol_ch3_s => rx_cdr_lol(3),
- tx_div2_mode_ch3_c => '0',
- rx_div2_mode_ch3_c => '0',
- -- COMMON --
- sci_wrdata => sci_data_in_i,
- sci_rddata => sci_data_out_i,
- sci_addr => sci_addr_i(5 downto 0),
- sci_sel_quad => sci_qd_i,
- sci_rd => sci_read_i,
- sci_wrn => sci_write_i,
-
- fpga_txrefclk => clk_200_txdata,
- tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906
- tx_pll_lol_qd_s => tx_pll_lol_quad,
- tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols
- rst_qd_c => rst_down_quad,
- serdes_rst_qd_c => serdes_rst_down_quad
- );
-
--------------------------
--- combined quad reset --
--------------------------
---rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
-rst_down_quad <= RESET; -- PL: 18/06/14
---serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
-serdes_rst_down_quad <= '0'; -- PL: 23/06/14
-
-generated_logic : for i in 0 to 3 generate
-
--- SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready
- SD_TXDIS_OUT(i) <= '0'; --not rx_allow_q(i); --slave only switches on when RX is ready
-
- tx_pll_lol(i) <= tx_pll_lol_quad;
-
- -------------------------------------------------
- -- Reset FSM & Link states
- -------------------------------------------------
- THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n(i),
- RX_REFCLK => rx_full_clk(i),
- TX_PLL_LOL_QD_S => tx_pll_lol(i),
- RX_SERDES_RST_CH_C => rx_serdes_rst(i),
- RX_CDR_LOL_CH_S => rx_cdr_lol(i),
- RX_LOS_LOW_CH_S => rx_los_low(i),
- RX_PCS_RST_CH_C => rx_pcs_rst(i),
- WA_POSITION => wa_position_rx(i),
- STATE_OUT => rx_fsm_state(i)
- );
-
- THE_TX_RESET_FSM : tx_reset_fsm
- port map(
- RST_N => rst_n(i),
- TX_REFCLK => clk_200_txdata,
- TX_PLL_LOL_QD_S => tx_pll_lol(i),
- RST_QD_C => rst_qd(i),
- TX_PCS_RST_CH_C => tx_pcs_rst(i),
- STATE_OUT => tx_fsm_state(i)
- );
-
-
- -- Master does not do bit-locking
- wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
-
-
- PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i))
- begin
- if rising_edge(clk_200_txdata) then -- clk_200_txdata ??
- if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
- rx_allow(i) <= '1';
- tx_allow(i) <= '1';
- else
- rx_allow(i) <= '0';
- tx_allow(i) <= '1';
- end if;
- end if;
- end process;
-
- rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK);
- tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
-
-
- PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i))
- begin
- if rising_edge(clk_200_txdata) then
- if got_link_ready_i(i) = '1' then
- if start_timer(i)(start_timer'left) = '0' then
- start_timer(i) <= start_timer(i) + 1;
- end if;
- else
- start_timer(i) <= (others => '0');
- end if;
- end if;
- end process;
- -------------------------------------------------
- -- TX Data
- -------------------------------------------------
- the_tx_fsm : process(clk_200_txdata)
- begin
- if rising_edge(clk_200_txdata) then
- if (RESET='1') then\r
- tx_proc_state(i) <= cRESET;
- tx_data(i) <= x"00"; -- idle
- tx_k(i) <= '0'; \r
- link_phase_S(i) <= c_PHASE_L;
- else
- link_phase_S(i) <= not(link_phase_S(i));
- case tx_proc_state(i) is
- when cSEND_IDLE =>
- if (TX_DLM_IN(i)='0') then
- tx_proc_state(i) <= cSEND_IDLE;
- tx_data(i) <= x"BC"; -- idle
- tx_k(i) <= '1';
- else
- tx_proc_state(i) <= cSEND_DLM;
- tx_data(i) <= x"DC"; -- dlm
- tx_k(i) <= '1';
- end if;
- when cSEND_DLM =>
- tx_proc_state(i) <= cSEND_IDLE;
- tx_data(i) <= TX_DLM_WORD_IN(i);
- tx_k(i) <= '0';
- when others =>
- tx_proc_state(i) <= cSEND_IDLE;
- tx_data(i) <= x"BC"; -- idle
- tx_k(i) <= '1';
- end case;
- end if;\r
- end if;
- end process;
--- THE_TX : soda_tx_control
--- port map(
--- CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i),
--- CLK_100 => SYSCLK,
--- RESET_IN => rst(i), --CLEAR, PL!
---
--- TX_DATA_IN => (others => '0'), -- MED_DATA_IN(i),
--- TX_PACKET_NUMBER_IN => (others => '0'), -- MED_PACKET_NUM_IN(i),
--- TX_WRITE_IN => '0', -- MED_DATAREADY_IN(i),
--- TX_READ_OUT => open, -- MED_READ_OUT(i),
---
--- TX_DATA_OUT => tx_data(i),
--- TX_K_OUT => tx_k(i),
---
--- REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO
--- REQUEST_POSITION_IN => request_retr_position_i(i), --TODO
---
--- START_RETRANSMIT_IN => start_retr_i(i), --TODO
--- START_POSITION_IN => request_retr_position_i(i), --TODO
---
--- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i),
--- SEND_DLM => TX_DLM_IN(i),
--- SEND_DLM_WORD => TX_DLM_WORD_IN(i),
---
--- SEND_LINK_RESET_IN => '0', --CTRL_OP(i)(15),
--- TX_ALLOW_IN => tx_allow(i),
--- RX_ALLOW_IN => rx_allow(i),
--- LINK_PHASE_OUT => link_phase_S(i), --PL!
---
--- DEBUG_OUT => debug_tx_control_i(i),
--- STAT_REG_OUT => stat_tx_control_i(i)
--- );
-
- LINK_PHASE_OUT(i) <= link_phase_S(i); --PL!\r
- \r
-
- -------------------------------------------------
- -- RX Data
- -------------------------------------------------\r
- the_rx_proc : process(clk_200_txdata)
- begin
- if rising_edge(clk_200_txdata) then
- RX_DLM_OUT(i) <= '0';
- if dlm_received_S(i)='1' then
- dlm_received_S(i) <= '0';
- RX_DLM_OUT(i) <= '1';
- RX_DLM_WORD_OUT(i) <= rx_data(i);
- elsif (rx_data(i)=x"DC") and (rx_k(i)='1') then
- dlm_received_S(i) <= '1';
- end if;
- end if;
- end process;
--- THE_RX_CONTROL : rx_control
--- port map(
--- CLK_200 => clk_200_txdata, --clk_200_i(i), --PL!
--- CLK_100 => SYSCLK,
--- RESET_IN => rst(i), --CLEAR, PL!
---
--- RX_DATA_OUT => open, -- MED_DATA_OUT(i),
--- RX_PACKET_NUMBER_OUT => open, -- MED_PACKET_NUM_OUT(i),
--- RX_WRITE_OUT => open, -- MED_DATAREADY_OUT(i),
--- RX_READ_IN => '0', -- MED_READ_IN(i),
---
--- RX_DATA_IN => rx_data(i),
--- RX_K_IN => rx_k(i),
---
--- REQUEST_RETRANSMIT_OUT => request_retr_i(i),
--- REQUEST_POSITION_OUT => request_retr_position_i(i),
---
--- START_RETRANSMIT_OUT => start_retr_i(i),
--- START_POSITION_OUT => start_retr_position_i(i),
---
--- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
--- RX_DLM => RX_DLM_OUT(i),
--- RX_DLM_WORD => RX_DLM_WORD_OUT(i),
---
--- SEND_LINK_RESET_OUT => send_link_reset_i(i),
--- MAKE_RESET_OUT => make_link_reset_i(i),
--- RX_ALLOW_IN => rx_allow(i),
--- GOT_LINK_READY => got_link_ready_i(i),
---
--- DEBUG_OUT => debug_rx_control_i(i),
--- STAT_REG_OUT => stat_rx_control_i(i)
--- );
-
- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); --PL! 200115
-
-end generate;
-
--------------------------------------------------
--- SCI
--------------------------------------------------
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process
-variable cnt : integer range 0 to 4 := 0;
-begin
-wait until rising_edge(SYSCLK);\r
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer(0) <= sci_timer(0) + 1;
- sci_timer(1) <= sci_timer(1) + 1;
- sci_timer(2) <= sci_timer(2) + 1;
- sci_timer(3) <= sci_timer(3) + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- else
- if sci_timer(0)(sci_timer'left) = '1' then
- sci_timer(0) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(1)(sci_timer'left) = '1' then
- sci_timer(1) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(2)(sci_timer'left) = '1' then
- sci_timer(2) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- if sci_timer(3)(sci_timer'left) = '1' then
- sci_timer(3) <= (others => '0');
- sci_state <= GET_WA;
- end if;
- end if;
-when SCTRL =>
- if sci_reg_i = '1' then
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
-when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
-when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
-when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
-when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
-when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
-when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
-when GET_WA_FINISH =>
--- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- wa_position(cnt) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
-end case;
-
-if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
-else
- SCI_NACK <= '0';
-end if;
-
-end process;
-
-
-
-end soda_only_ecp3_sfp_4_sync_down_arch;
+++ /dev/null
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity soda_only_ecp3_sfp_sync_up is
- generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_YES); --select slave mode
- port(
- OSCCLK : in std_logic; -- 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
-
- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014
-
- --Sync operation
- RX_DLM : out std_logic := '0';
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
- TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!
- LINK_PHASE_OUT : out std_logic := '0'; --PL!
- LINK_READY_OUT : out std_logic := '0'; --PL!
-
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0'
- );
-end entity;
-
-
-architecture soda_only_ecp3_sfp_sync_up_arch of soda_only_ecp3_sfp_sync_up is
-
--- Placer Directives
-attribute HGROUP : string;
--- for whole architecture
-attribute HGROUP of soda_only_ecp3_sfp_sync_up_arch : architecture is "media_uplink_group";
-attribute syn_sharing : string;
-attribute syn_sharing of soda_only_ecp3_sfp_sync_up_arch : architecture is "off";
-
-
-component DCS
--- synthesis translate_off
-generic
-(
- DCSMODE : string :="POS"
-);
--- synthesis translate_on
-port (
-CLK0 :in std_logic ;
-CLK1 :in std_logic ;
-SEL :in std_logic ;
-DCSOUT :out std_logic) ;
-end component;
-
-
---signal clk_200_i : std_logic;
---signal clk_200_internal : std_logic;
-signal clk_200_osc : std_logic;
-signal rx_full_clk : std_logic;
-signal rx_half_clk : std_logic;
-signal tx_full_clk : std_logic;
-signal tx_half_clk : std_logic;
-
-signal tx_data : std_logic_vector(7 downto 0);
-signal tx_k : std_logic;
-signal rx_data : std_logic_vector(7 downto 0);
-signal rx_k : std_logic;
-signal rx_error : std_logic;
-
-signal rst_n : std_logic;
-signal rst : std_logic; -- PL!
-signal rx_serdes_rst : std_logic;
-signal tx_serdes_rst : std_logic;
-signal tx_pcs_rst : std_logic;
-signal rx_pcs_rst : std_logic;
-signal rst_qd : std_logic;
-signal serdes_rst_qd : std_logic;
-signal sd_los_i : std_logic; --PL!
-
-signal rx_los_low : std_logic;
-signal lsm_status : std_logic;
-signal rx_cdr_lol : std_logic;
-signal tx_pll_lol : std_logic;
-
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
-signal sci_data_in_i : std_logic_vector(7 downto 0);
-signal sci_data_out_i : std_logic_vector(7 downto 0);
-signal sci_read_i : std_logic;
-signal sci_write_i : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
--- fix signal names for constraining
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_preserve of sci_ch_i : signal is true;
-attribute syn_keep of sci_ch_i : signal is true;
-attribute syn_preserve of sci_qd_i : signal is true;
-attribute syn_keep of sci_qd_i : signal is true;
-attribute syn_preserve of sci_reg_i : signal is true;
-attribute syn_keep of sci_reg_i : signal is true;
-attribute syn_preserve of sci_addr_i : signal is true;
-attribute syn_keep of sci_addr_i : signal is true;
-attribute syn_preserve of sci_data_in_i : signal is true;
-attribute syn_keep of sci_data_in_i : signal is true;
-attribute syn_preserve of sci_data_out_i : signal is true;
-attribute syn_keep of sci_data_out_i : signal is true;
-attribute syn_preserve of sci_read_i : signal is true;
-attribute syn_keep of sci_read_i : signal is true;
-attribute syn_preserve of sci_write_i : signal is true;
-attribute syn_keep of sci_write_i : signal is true;
-attribute syn_preserve of sci_write_shift_i : signal is true;
-attribute syn_keep of sci_write_shift_i : signal is true;
-attribute syn_preserve of sci_read_shift_i : signal is true;
-attribute syn_keep of sci_read_shift_i : signal is true;
-
-signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow : std_logic;
-signal rx_allow : std_logic;
-signal tx_allow_q : std_logic;
-signal rx_allow_q : std_logic;
-signal link_phase_S : std_logic; --PL!
-signal request_retr_i : std_logic;
-signal start_retr_i : std_logic;
-signal request_retr_position_i : std_logic_vector(7 downto 0);
-signal start_retr_position_i : std_logic_vector(7 downto 0);
-signal send_link_reset_i : std_logic;
-signal make_link_reset_i : std_logic;
-signal got_link_ready_i : std_logic;
-signal internal_make_link_reset_out : std_logic;
-
-attribute syn_preserve of wa_position : signal is true;
-attribute syn_keep of wa_position : signal is true;
-attribute syn_preserve of wa_position_rx : signal is true;
-attribute syn_keep of wa_position_rx : signal is true;
-
-signal stat_rx_control_i : std_logic_vector(31 downto 0);
-signal stat_tx_control_i : std_logic_vector(31 downto 0);
-signal debug_rx_control_i : std_logic_vector(31 downto 0);
-signal debug_tx_control_i : std_logic_vector(31 downto 0);
-signal rx_fsm_state : std_logic_vector(3 downto 0);
-signal tx_fsm_state : std_logic_vector(3 downto 0);
-signal debug_reg : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state : sci_ctrl;
-signal sci_timer : unsigned(12 downto 0) := (others => '0');
-signal start_timer : unsigned(18 downto 0) := (others => '0');
-signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
-signal watchdog_trigger : std_logic :='0';
-
-begin
-
-clk_200_osc <= OSCCLK;
-
-RX_HALF_CLK_OUT <= rx_half_clk;
-RX_FULL_CLK_OUT <= rx_full_clk;
-TX_HALF_CLK_OUT <= tx_half_clk;
-TX_FULL_CLK_OUT <= tx_full_clk;
-RX_CDR_LOL_OUT <= rx_cdr_lol; -- !PL14082014
-
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-
-LINK_READY_OUT <= got_link_ready_i;
-
-
---rst_n <= not CLEAR; PL!
-rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-
-
---gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
--- clk_200_i <= rx_full_clk;
---end generate;
-
---gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i <= clk_200_internal;
---end generate;
-
-
--------------------------------------------------
--- Serdes
--------------------------------------------------
-THE_SERDES : sfp_2_200_int
- port map(
- hdinp_ch3 => SD_RXD_P_IN,
- hdinn_ch3 => SD_RXD_N_IN,
- hdoutp_ch3 => SD_TXD_P_OUT,
- hdoutn_ch3 => SD_TXD_N_OUT,
- txiclk_ch3 => rx_full_clk,
- rx_full_clk_ch3 => rx_full_clk,
- rx_half_clk_ch3 => rx_half_clk,
- tx_full_clk_ch3 => tx_full_clk,
- tx_half_clk_ch3 => tx_half_clk,
- fpga_rxrefclk_ch3 => clk_200_osc,
- txdata_ch3 => tx_data,
- tx_k_ch3 => tx_k,
- tx_force_disp_ch3 => '0',
- tx_disp_sel_ch3 => '0',
- rxdata_ch3 => rx_data,
- rx_k_ch3 => rx_k,
- rx_disp_err_ch3 => open,
- rx_cv_err_ch3 => rx_error,
- rx_serdes_rst_ch3_c => rx_serdes_rst,
- sb_felb_ch3_c => '0',
- sb_felb_rst_ch3_c => '0',
- tx_pcs_rst_ch3_c => tx_pcs_rst,
- tx_pwrup_ch3_c => '1',
- rx_pcs_rst_ch3_c => rx_pcs_rst,
- rx_pwrup_ch3_c => '1',
- rx_los_low_ch3_s => rx_los_low,
- lsm_status_ch3_s => lsm_status,
- rx_cdr_lol_ch3_s => rx_cdr_lol,
- tx_div2_mode_ch3_c => '0',
- rx_div2_mode_ch3_c => '0',
-
- SCI_WRDATA => sci_data_in_i,
- SCI_RDDATA => sci_data_out_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_SEL_QUAD => sci_qd_i,
- SCI_SEL_ch3 => sci_ch_i(0),
- SCI_RD => sci_read_i,
- SCI_WRN => sci_write_i,
-
- fpga_txrefclk => rx_full_clk,
- tx_serdes_rst_c => tx_serdes_rst,
- tx_pll_lol_qd_s => tx_pll_lol,
- rst_qd_c => rst_qd,
- serdes_rst_qd_c => serdes_rst_qd
-
- );
-
--------------------------------------------------
--- Reset FSM & Link states
--------------------------------------------------
-THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n,
- RX_REFCLK => clk_200_osc, -- allways running PL!
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RX_SERDES_RST_CH_C => rx_serdes_rst,
- RX_CDR_LOL_CH_S => rx_cdr_lol,
- RX_LOS_LOW_CH_S => rx_los_low,
- RX_PCS_RST_CH_C => rx_pcs_rst,
- WA_POSITION => wa_position_rx(3 downto 0),
- STATE_OUT => rx_fsm_state
- );
-
-THE_TX_FSM : tx_reset_fsm
- port map(
- RST_N => rst_n,
- TX_REFCLK => clk_200_osc, -- allways running PL! 18-06 was clk_200_i
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RST_QD_C => rst_qd,
- TX_PCS_RST_CH_C => tx_pcs_rst,
- STATE_OUT => tx_fsm_state
- );
-
--- Master does not do bit-locking
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
-
-
---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
-PROC_ALLOW : process begin
- wait until rising_edge(rx_full_clk); --clk_200_osc); --clk_200_i);
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
- rx_allow <= '1';
- else
- rx_allow <= '0';
- end if;
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
- tx_allow <= '1';
- else
- tx_allow <= '0';
- end if;
-end process;
-
-rx_allow_q <= rx_allow when rising_edge(rx_half_clk); --SYSCLK);
-tx_allow_q <= tx_allow when rising_edge(rx_half_clk); --SYSCLK);
-
-
-PROC_START_TIMER : process(rx_full_clk) --clk_200_osc) --clk_200_i)
-begin
- if rising_edge(rx_full_clk) then --clk_200_osc) then
- if got_link_ready_i = '1' then
- watchdog_timer <= (others => '0');
- if start_timer(start_timer'left) = '0' then
- start_timer <= start_timer + 1;
- end if;
- else
- start_timer <= (others => '0');
- if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then
- watchdog_trigger <= '1';
- else
- watchdog_trigger <= '0';
- end if;
- if watchdog_trigger = '0' then
- watchdog_timer <= watchdog_timer + 1;
- else
- watchdog_timer <= (others => '0');
- end if;
- end if;
- end if;
-end process;
--------------------------------------------------
--- TX Data
--------------------------------------------------
-THE_TX : soda_tx_control
- port map(
- CLK_200 => rx_full_clk, --clk_200_osc, --clk_200_i,
- CLK_100 => rx_half_clk, --SYSCLK,
- RESET_IN => rst, --CLEAR, PL!
-
- TX_DATA_IN => (others => '0'), --MED_DATA_IN,
- TX_PACKET_NUMBER_IN => (others => '0'), --MED_PACKET_NUM_IN,
- TX_WRITE_IN => '0', --MED_DATAREADY_IN,
- TX_READ_OUT => open, --MED_READ_OUT,
-
- TX_DATA_OUT => tx_data,
- TX_K_OUT => tx_k,
-
- REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
- REQUEST_POSITION_IN => request_retr_position_i, --TODO
-
- START_RETRANSMIT_IN => start_retr_i, --TODO
- START_POSITION_IN => request_retr_position_i, --TODO
-
- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN,
- SEND_DLM => TX_DLM,
- SEND_DLM_WORD => TX_DLM_WORD,
-
- SEND_LINK_RESET_IN => '0', --CTRL_OP(15),
- TX_ALLOW_IN => tx_allow,
- RX_ALLOW_IN => rx_allow,
- LINK_PHASE_OUT => link_phase_S, --PL!
-
- DEBUG_OUT => debug_tx_control_i,
- STAT_REG_OUT => stat_tx_control_i
-);
-
-LINK_PHASE_OUT <= link_phase_S; --PL!
--------------------------------------------------
--- RX Data
--------------------------------------------------
-THE_RX_CONTROL : rx_control
- port map(
- CLK_200 => rx_full_clk, --clk_200_i, PL!
- CLK_100 => rx_half_clk, --SYSCLK,
- RESET_IN => rst, --CLEAR, PL!
-
- RX_DATA_OUT => open, --MED_DATA_OUT,
- RX_PACKET_NUMBER_OUT => open, --MED_PACKET_NUM_OUT,
- RX_WRITE_OUT => open, --MED_DATAREADY_OUT,
- RX_READ_IN => '0', --MED_READ_IN,
-
- RX_DATA_IN => rx_data,
- RX_K_IN => rx_k,
-
- REQUEST_RETRANSMIT_OUT => request_retr_i,
- REQUEST_POSITION_OUT => request_retr_position_i,
-
- START_RETRANSMIT_OUT => start_retr_i,
- START_POSITION_OUT => start_retr_position_i,
-
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
- RX_DLM => RX_DLM,
- RX_DLM_WORD => RX_DLM_WORD,
-
- SEND_LINK_RESET_OUT => send_link_reset_i,
- MAKE_RESET_OUT => make_link_reset_i,
- RX_ALLOW_IN => rx_allow,
- GOT_LINK_READY => got_link_ready_i,
-
- DEBUG_OUT => debug_rx_control_i,
- STAT_REG_OUT => stat_rx_control_i
- );
-
-
-
--------------------------------------------------
--- SCI
--------------------------------------------------
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process
- variable cnt : integer range 0 to 4 := 0;
-begin
- wait until rising_edge(rx_half_clk); --SYSCLK);
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer <= sci_timer + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- elsif sci_timer(sci_timer'left) = '1' then
- sci_timer <= (others => '0');
- sci_state <= GET_WA;
- end if;
- when SCTRL =>
- if sci_reg_i = '1' then
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
- when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
- when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
- when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
- when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
- when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
- when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
- when GET_WA_FINISH =>
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
- end case;
-
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
- else
- SCI_NACK <= '0';
- end if;
-
-end process;
-
-
--------------------------------------------------
--- Debug Registers
--------------------------------------------------
-debug_reg(3 downto 0) <= rx_fsm_state;
-debug_reg(4) <= rx_k;
-debug_reg(5) <= rx_error;
-debug_reg(6) <= rx_los_low;
-debug_reg(7) <= rx_cdr_lol;
-
-debug_reg(8) <= tx_k;
-debug_reg(9) <= tx_pll_lol;
-debug_reg(10) <= lsm_status;
-debug_reg(11) <= make_link_reset_i;
-debug_reg(15 downto 12) <= tx_fsm_state;
--- debug_reg(31 downto 24) <= tx_data;
-
-debug_reg(16) <= '0';
-debug_reg(17) <= tx_allow;
-debug_reg(18) <= RESET;
-debug_reg(19) <= CLEAR;
-debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
-
-debug_reg(35 downto 32) <= wa_position(3 downto 0);
-debug_reg(36) <= debug_tx_control_i(6);
-debug_reg(39 downto 37) <= "000";
-debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
-
-
---STAT_DEBUG <= debug_reg;
-
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
-sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!
-
- --STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
- --STAT_OP(14) <= '0';
- --STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset
- --STAT_OP(12) <= tx_pll_lol; --'0';
- --STAT_OP(11) <= rx_cdr_lol; --'0';
- --STAT_OP(10) <= rx_allow;
- --STAT_OP(9) <= tx_allow;
- --STAT_OP(8 downto 4) <= (others => '0');
- --STAT_OP(8) <= got_link_ready_i;
- --STAT_OP(7) <= send_link_reset_i;
- --STAT_OP(6) <= make_link_reset_i;
- --STAT_OP(5) <= request_retr_i;
- --STAT_OP(4) <= start_retr_i;
- --STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-end soda_only_ecp3_sfp_sync_up_arch;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; \r
-use work.soda_components.all;
-
-entity soda_reply_handler is
- port(
- SODACLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0');
- RX_DLM_IN : in std_logic := '0';
- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
- REPLY_VALID_OUT : out std_logic := '0';
- REPLY_OK_OUT : out std_logic := '0'
- );
-end soda_reply_handler;
-
-architecture Behavioral of soda_reply_handler is
-
- type packet_state_type is ( c_RST, c_IDLE, c_ERROR, c_REPLY, c_DONE);
- signal reply_recv_state_S : packet_state_type := c_IDLE;
-
-begin
-
- reply_fsm_proc : process(SODACLK)
- begin
- if rising_edge(SODACLK) then\r
- if (RESET='1') then
- REPLY_VALID_OUT <= '0';
- REPLY_OK_OUT <= '0';
- reply_recv_state_S <= c_IDLE;
- else
- REPLY_VALID_OUT <= '0';
- case reply_recv_state_S is\r
- when c_IDLE =>\r
- if (RX_DLM_IN='1') then
- reply_recv_state_S <= c_REPLY;
- REPLY_VALID_OUT <= '1';
- if (EXPECTED_REPLY_IN = RX_DLM_WORD_IN) then
- REPLY_OK_OUT <= '1';
- else
- REPLY_OK_OUT <= '0';
- end if;\r
- end if;
- when c_REPLY =>
- REPLY_VALID_OUT <= '0';
- REPLY_OK_OUT <= '0';
- if (RX_DLM_IN='0') then\r
- reply_recv_state_S <= c_IDLE;
- else
- reply_recv_state_S <= c_ERROR;\r
- end if;
- when c_ERROR =>
- reply_recv_state_S <= c_IDLE;
- REPLY_OK_OUT <= '0';
- REPLY_OK_OUT <= '0';
- when others =>
- reply_recv_state_S <= c_IDLE;
- REPLY_OK_OUT <= '0';
- end case;
- end if;\r
- end if;
- end process;
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
-#define_clock {p:CLK_PCLK_LEFT} -freq 200
-
-#define_clock {n:gen_200_PLL.THE_MAIN_PLL.CLKOP} -name {n:gen_200_PLL.THE_MAIN_PLL.CLKOP} -freq 100
-#define_clock {n:gen_200_PLL.THE_MAIN_PLL.CLKOK} -name {n:gen_200_PLL.THE_MAIN_PLL.CLKOK} -freq 200
-\r
-# Just to stop the nagging:\r
-define_clock {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -name {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -freq 100
-define_clock {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -name {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -freq 200
-\r
-#define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200.THE_SERDES.rx_half_clk_ch1} -freq 100
-#define_clock {n:clk_raw_internal} -name {nn:clk_raw_internal} -freq 200
+++ /dev/null
-################################################################################
-#### This file contains constraints from Synplicity SDC files that have been
-#### translated into Synopsys FPGA Design Constraints (FDC).
-#### Translated FDC output file:
-#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-#### client SDC files to the translation:
-#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-################################################################################
-
-
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-# Written on Wed Dec 18 11:52:15 2013
-# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
-
-################################################################################
-#### The following Synplicity constraints from file:
-#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-#### are disabled and have not been translated.
-##############################################################################
-# FDC constraints translated from Synplify Legacy Timing & Design Constraints
-##############################################################################
-
-set_rtl_ff_names {}
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable
-define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable
-define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable
-define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable
-###==== END Collections
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0}
-create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5}
-create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5}
-create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0}
-create_clock -name {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5}\r
-\r
-
-#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} -period {10.0} -waveform {0 5.0}
-#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} -period {5.0} -waveform {0 2.5}
-set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} }
-set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} }
-###==== END Clocks
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
+++ /dev/null
-
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/soda_source/soda_source_synconstraints.fdc
-# Written on Tue Dec 3 18:26:37 2013
-# by Synplify Pro, G-2012.09L-1 FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-###==== END Collections
-
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock -name {rx_clk_half} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10}
-create_clock -name {rx_clk_full} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5}
-
-#create_clock -name {clk_sys_internal} {n:gen_200_PLL\.THE_MAIN_PLL.CLKOP} -period {10}
-#create_clock -name {serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} -period {10}
-#create_clock -name {serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} -period {5}
-#set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_0} -group { {c:serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} }
-#set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_1} -group { {c:serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} }
-#set_clock_groups -derive -asynchronous -name {raw_internal} -group { {c:clk_raw_internal} }
-#set_clock_groups -derive -asynchronous -name {sys_internal} -group { {c:clk_sys_internal} }
-###==== END Clocks
-
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
-
+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.med_sync_define.all;\r
-use work.soda_components.all;\r
-\r
-entity soda_tx_control is\r
- port(\r
- CLK_200 : in std_logic;\r
- CLK_100 : in std_logic;\r
- RESET_IN : in std_logic;\r
-\r
- TX_DATA_IN : in std_logic_vector(15 downto 0);\r
- TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);\r
- TX_WRITE_IN : in std_logic;\r
- TX_READ_OUT : out std_logic;\r
-\r
- TX_DATA_OUT : out std_logic_vector( 7 downto 0);\r
- TX_K_OUT : out std_logic;\r
-\r
- REQUEST_RETRANSMIT_IN : in std_logic := '0';\r
- REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');\r
-\r
- START_RETRANSMIT_IN : in std_logic := '0';\r
- START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');\r
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM\r
- TX_DLM_PREVIEW_IN : in std_logic := '0';\r
- SEND_DLM : in std_logic := '0';\r
- SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0');\r
- \r
- SEND_LINK_RESET_IN : in std_logic := '0';\r
- TX_ALLOW_IN : in std_logic := '0';\r
- RX_ALLOW_IN : in std_logic := '0';\r
- LINK_PHASE_OUT : out std_logic := '0';\r
-\r
- DEBUG_OUT : out std_logic_vector(31 downto 0);\r
- STAT_REG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-end entity;\r
-\r
-\r
-\r
-architecture arch of soda_tx_control is\r
-\r
- attribute syn_hier : string;\r
- attribute syn_hier of arch : architecture is "hard";\r
-\r
- type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H,\r
- SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H,\r
- SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H); -- gk 05.10.10\r
- signal current_state : state_t;\r
- \r
- type ram_t is array(0 to 255) of std_logic_vector(17 downto 0);\r
- signal ram : ram_t;\r
-\r
- signal link_phase_S : std_logic := '0';\r
-\r
- signal ram_write : std_logic := '0';\r
- signal ram_write_addr : unsigned(7 downto 0) := (others => '0');\r
- signal ram_read : std_logic := '0';\r
- signal ram_read_addr : unsigned(7 downto 0) := (others => '0');\r
- signal ram_dout : std_logic_vector(17 downto 0);\r
- signal next_ram_dout : std_logic_vector(17 downto 0);\r
- signal ram_fill_level : unsigned(7 downto 0);\r
- signal ram_empty : std_logic;\r
- signal ram_afull : std_logic;\r
-\r
- signal request_position_q : std_logic_vector( 7 downto 0);\r
- signal restart_position_q : std_logic_vector( 7 downto 0);\r
- signal request_position_i : std_logic_vector( 7 downto 0);\r
- signal restart_position_i : std_logic_vector( 7 downto 0);\r
- signal make_request_i : std_logic;\r
- signal make_restart_i : std_logic;\r
- signal load_read_pointer_i : std_logic;\r
--- signal SEND_DLM : std_logic;\r
- signal send_dlm_word_S : std_logic_vector( 7 downto 0); --PL!\r
- signal send_dlm_i : std_logic;\r
- signal start_retransmit_i : std_logic;\r
- signal request_retransmit_i : std_logic;\r
-\r
- signal buf_tx_read_out : std_logic;\r
- signal tx_data_200 : std_logic_vector(17 downto 0);\r
- signal tx_allow_qtx : std_logic;\r
- signal rx_allow_qtx : std_logic;\r
- signal tx_allow_q : std_logic;\r
- signal send_link_reset_qtx : std_logic;\r
- signal ct_fifo_empty : std_logic;\r
- signal ct_fifo_write : std_logic := '0';\r
- signal ct_fifo_read : std_logic := '0';\r
- signal ct_fifo_full : std_logic;\r
- signal ct_fifo_afull : std_logic;\r
- signal ct_fifo_reset : std_logic;\r
- signal last_ct_fifo_empty : std_logic;\r
- signal last_ct_fifo_read : std_logic;\r
- signal debug_sending_dlm : std_logic;\r
-\r
- -- gk 05.10.10\r
- signal save_sop : std_logic;\r
- signal save_eop : std_logic;\r
- signal load_sop : std_logic;\r
- signal load_eop : std_logic;\r
- signal crc_reset : std_logic;\r
- signal crc_q : std_logic_vector(7 downto 0);\r
- signal crc_en : std_logic;\r
- signal crc_data : std_logic_vector(7 downto 0);\r
-\r
-begin\r
-\r
-----------------------------------------------------------------------\r
--- Clock Domain Transfer\r
-----------------------------------------------------------------------\r
--- gk 05.10.10\r
- THE_CT_FIFO : lattice_ecp3_fifo_18x16_dualport_oreg\r
- port map(\r
- Data(15 downto 0) => TX_DATA_IN,\r
- Data(16) => save_sop,\r
- Data(17) => save_eop,\r
- WrClock => CLK_100,\r
- RdClock => CLK_200,\r
- WrEn => ct_fifo_write,\r
- RdEn => ct_fifo_read,\r
- Reset => ct_fifo_reset,\r
- RPReset => ct_fifo_reset,\r
- Q(17 downto 0) => tx_data_200,\r
- Empty => ct_fifo_empty,\r
- Full => ct_fifo_full,\r
- AlmostFull => ct_fifo_afull\r
- );\r
-\r
- THE_RD_PROC : process(CLK_100)\r
- begin\r
- if rising_edge(CLK_100) then\r
- buf_tx_read_out <= tx_allow_q and not ct_fifo_afull ;\r
- end if;\r
- end process;\r
-\r
- ct_fifo_reset <= not tx_allow_qtx;\r
- TX_READ_OUT <= buf_tx_read_out;\r
-\r
- ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN;\r
- ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;\r
- \r
- last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_200);\r
- last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_200);\r
- \r
- save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0';\r
- save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0';\r
-\r
-----------------------------------------------------------------------\r
--- RAM\r
-----------------------------------------------------------------------\r
-\r
-\r
- THE_RAM_WR_PROC : process(CLK_200, RESET_IN)\r
- begin\r
- if RESET_IN = '1' then\r
- ram_write <= '0';\r
- elsif rising_edge(CLK_200) then\r
- ram_write <= last_ct_fifo_read and not last_ct_fifo_empty;\r
- end if;\r
- end process;\r
-\r
---RAM\r
- THE_RAM_PROC : process(CLK_200)\r
- begin\r
- if rising_edge(CLK_200) then\r
- if ram_write = '1' then\r
- ram((to_integer(ram_write_addr))) <= tx_data_200;\r
- end if;\r
- next_ram_dout <= ram(to_integer(ram_read_addr));\r
- ram_dout <= next_ram_dout;\r
- end if;\r
- end process;\r
-\r
---RAM read pointer\r
- THE_READ_CNT : process(CLK_200, RESET_IN)\r
- begin\r
- if RESET_IN = '1' then\r
- ram_read_addr <= (others => '0');\r
- elsif rising_edge(CLK_200) then\r
- if tx_allow_qtx = '0' then\r
- ram_read_addr <= (others => '0');\r
- elsif load_read_pointer_i = '1' then\r
- ram_read_addr <= unsigned(restart_position_i);\r
- elsif ram_read = '1' then\r
- ram_read_addr <= ram_read_addr + to_unsigned(1,1);\r
- end if;\r
- end if;\r
- end process;\r
-\r
---RAM write pointer\r
- THE_WRITE_CNT : process(CLK_200, RESET_IN)\r
- begin\r
- if RESET_IN = '1' then\r
- ram_write_addr <= (others => '0');\r
- elsif rising_edge(CLK_200) then\r
- if tx_allow_qtx = '0' then\r
- ram_write_addr <= (others => '0');\r
- elsif ram_write = '1' then\r
- ram_write_addr <= ram_write_addr + to_unsigned(1,1);\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
---RAM fill level counter\r
- THE_FILL_CNT : process(CLK_200, RESET_IN)\r
- begin\r
- if RESET_IN = '1' then\r
- ram_fill_level <= (others => '0');\r
- elsif rising_edge(CLK_200) then\r
- if tx_allow_qtx = '0' then\r
- ram_fill_level <= (others => '0');\r
- else\r
- ram_fill_level <= ram_write_addr - ram_read_addr;\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
---RAM empty\r
--- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN;\r
- ram_empty <= '1' when (ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0';\r
- ram_afull <= '1' when ram_fill_level >= 4 else '0';\r
-\r
-\r
-\r
-----------------------------------------------------------------------\r
--- TX control state machine\r
-----------------------------------------------------------------------\r
-\r
- THE_DATA_CONTROL_FSM : process(CLK_200, RESET_IN)\r
- begin\r
- if rising_edge(CLK_200) then\r
- TX_K_OUT <= '0';\r
- debug_sending_dlm <= '0';\r
- case current_state is\r
- when SEND_IDLE_L =>\r
- TX_DATA_OUT <= K_IDLE;\r
- TX_K_OUT <= '1';\r
- current_state <= SEND_IDLE_H;\r
-\r
- when SEND_IDLE_H =>\r
- if rx_allow_qtx = '1' then\r
- TX_DATA_OUT <= D_IDLE1;\r
- else\r
- TX_DATA_OUT <= D_IDLE0;\r
- end if;\r
-\r
- when SEND_DATA_L =>\r
- TX_DATA_OUT <= ram_dout(7 downto 0);\r
- load_sop <= ram_dout(16);\r
- load_eop <= ram_dout(17);\r
- current_state <= SEND_DATA_H;\r
-\r
- when SEND_DATA_H =>\r
- TX_DATA_OUT <= ram_dout(15 downto 8);\r
-\r
- when SEND_CHKSUM_L =>\r
- TX_DATA_OUT <= K_EOP;\r
- TX_K_OUT <= '1';\r
- load_sop <= '0';\r
- load_eop <= '0';\r
- current_state <= SEND_CHKSUM_H;\r
-\r
- when SEND_CHKSUM_H =>\r
- TX_DATA_OUT <= crc_q;\r
-\r
- when SEND_START_L =>\r
- TX_DATA_OUT <= K_BGN;\r
- TX_K_OUT <= '1';\r
- current_state <= SEND_START_H;\r
-\r
- when SEND_START_H =>\r
- TX_DATA_OUT <= std_logic_vector(ram_read_addr);\r
-\r
- when SEND_REQUEST_L =>\r
- TX_DATA_OUT <= K_REQ;\r
- TX_K_OUT <= '1';\r
- current_state <= SEND_REQUEST_H;\r
-\r
- when SEND_DLM_L =>\r
- TX_DATA_OUT <= K_DLM;\r
- TX_K_OUT <= '1';\r
- current_state <= SEND_DLM_H;\r
- debug_sending_dlm <= '1';\r
- send_dlm_word_S <= SEND_DLM_WORD; --PL!\r
- \r
- when SEND_DLM_H =>\r
- TX_DATA_OUT <= send_dlm_word_S; --SEND_DLM_WORD;\r
- debug_sending_dlm <= '1';\r
- \r
- when SEND_REQUEST_H =>\r
- TX_DATA_OUT <= request_position_i;\r
-\r
- when SEND_RESET =>\r
- TX_DATA_OUT <= K_RST;\r
- TX_K_OUT <= '1';\r
- if send_link_reset_qtx = '0' then\r
- current_state <= SEND_IDLE_L;\r
- end if;\r
-\r
- when others =>\r
- current_state <= SEND_IDLE_L;\r
- end case;\r
-\r
- if current_state = SEND_START_H or current_state = SEND_IDLE_H or\r
- current_state = SEND_DATA_H or current_state = SEND_DLM_H or\r
- current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H\r
- then\r
- link_phase_S <= c_PHASE_L; \r
- if tx_allow_qtx = '0' then\r
- current_state <= SEND_IDLE_L;\r
- elsif send_link_reset_qtx = '1' then\r
- current_state <= SEND_RESET;\r
- elsif make_request_i = '1' then\r
- current_state <= SEND_REQUEST_L;\r
- elsif make_restart_i = '1' then\r
- current_state <= SEND_START_L;\r
- -- elsif send_dlm_i = '1' then\r
- elsif (TX_DLM_PREVIEW_IN='1') then --PL!\r
- current_state <= SEND_DLM_L;\r
- elsif ram_empty = '0' then\r
- current_state <= SEND_DATA_L;\r
- else\r
- current_state <= SEND_IDLE_L;\r
- end if;\r
- else\r
- link_phase_S <= c_PHASE_H;\r
- end if;\r
- end if;\r
---------------------------\r
---async because of oreg.--\r
---------------------------\r
- if (current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or\r
- current_state = SEND_DLM_H or current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H) and\r
- ram_empty = '0' and tx_allow_qtx = '1' and send_link_reset_qtx = '0' and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' then\r
- ram_read <= '1';\r
- else \r
- ram_read <= '0';\r
- end if;\r
- \r
- if RESET_IN = '1' then\r
- ram_read <= '0';\r
- end if;\r
-end process;\r
-\r
-LINK_PHASE_OUT <= link_phase_S;\r
-----------------------------------------------------------------------\r
---\r
-----------------------------------------------------------------------\r
-\r
-tx_allow_qtx <= TX_ALLOW_IN when rising_edge(CLK_200);\r
-rx_allow_qtx <= RX_ALLOW_IN when rising_edge(CLK_200);\r
-\r
-send_link_reset_qtx <= SEND_LINK_RESET_IN when rising_edge(CLK_200);\r
-tx_allow_q <= tx_allow_qtx when rising_edge(CLK_100);\r
-\r
- THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync\r
- port map(\r
- CLK_A_IN => CLK_100,\r
- RESET_A_IN => RESET_IN,\r
- PULSE_A_IN => REQUEST_RETRANSMIT_IN,\r
- CLK_B_IN => CLK_200,\r
- RESET_B_IN => RESET_IN,\r
- PULSE_B_OUT => request_retransmit_i\r
- );\r
-\r
- THE_RETRANSMIT_PULSE_SYNC_2 : pulse_sync\r
- port map(\r
- CLK_A_IN => CLK_100,\r
- RESET_A_IN => RESET_IN,\r
- PULSE_A_IN => START_RETRANSMIT_IN,\r
- CLK_B_IN => CLK_200,\r
- RESET_B_IN => RESET_IN,\r
- PULSE_B_OUT => start_retransmit_i\r
- );\r
-\r
--- THE_RETRANSMIT_PULSE_SYNC_3 : pulse_sync\r
--- port map(\r
--- CLK_A_IN => CLK_100,\r
--- RESET_A_IN => RESET_IN,\r
--- PULSE_A_IN => SEND_DLM,\r
--- CLK_B_IN => CLK_200,\r
--- RESET_B_IN => RESET_IN,\r
--- PULSE_B_OUT => SEND_DLM\r
--- ); \r
--- SEND_DLM <= SEND_DLM;\r
- \r
- THE_POSITION_REG : process(CLK_100)\r
- begin\r
- if rising_edge(CLK_100) then\r
- if REQUEST_RETRANSMIT_IN = '1' then\r
- request_position_q <= REQUEST_POSITION_IN;\r
- end if;\r
- if START_RETRANSMIT_IN = '1' then\r
- restart_position_q <= START_POSITION_IN;\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
---Store Request Retransmit position\r
- THE_STORE_REQUEST_PROC : process(CLK_200, RESET_IN)\r
- begin\r
- if RESET_IN = '1' then\r
- make_request_i <= '0';\r
- request_position_i <= (others => '0');\r
- elsif rising_edge(CLK_200) then\r
- if tx_allow_qtx = '0' then\r
- make_request_i <= '0';\r
- request_position_i <= (others => '0');\r
- elsif request_retransmit_i = '1' then\r
- make_request_i <= '1';\r
- request_position_i <= request_position_q;\r
- elsif current_state = SEND_REQUEST_L then\r
- make_request_i <= '0';\r
- elsif current_state = SEND_REQUEST_H then\r
- request_position_i <= (others => '0');\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
---Store Restart position\r
- THE_STORE_RESTART_PROC : process(CLK_200, RESET_IN)\r
- begin\r
- if RESET_IN = '1' then\r
- make_restart_i <= '0';\r
- restart_position_i <= (others => '0');\r
- elsif rising_edge(CLK_200) then\r
- if tx_allow_qtx = '0' then\r
- make_restart_i <= '0';\r
- restart_position_i <= (others => '0');\r
- elsif start_retransmit_i = '1' then\r
- make_restart_i <= '1';\r
- restart_position_i <= restart_position_q;\r
- elsif current_state = SEND_START_L then\r
- make_restart_i <= '0';\r
- elsif current_state = SEND_START_H then\r
- restart_position_i <= (others => '0');\r
- end if;\r
- end if;\r
- end process;\r
-\r
---Store DLM position\r
- THE_STORE_DLM_PROC : process(CLK_200, RESET_IN)\r
- begin\r
- if RESET_IN = '1' then\r
- send_dlm_i <= '0';\r
- elsif rising_edge(CLK_200) then\r
- if tx_allow_qtx = '0' then\r
- send_dlm_i <= '0';\r
- elsif SEND_DLM = '1' then\r
- send_dlm_i <= '1';\r
--- elsif current_state = SEND_DLM_L then -- PL!\r
- else\r
- send_dlm_i <= '0';\r
- end if;\r
- end if;\r
- end process; \r
- \r
- load_read_pointer_i <= '1' when current_state = SEND_START_L else '0';\r
-\r
- -- gk 05.10.10\r
- crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0';\r
- crc_en <= '1' when ((current_state = SEND_DATA_L) or (current_state = SEND_DATA_H)) else '0';\r
- crc_data <= ram_dout(15 downto 8) when (current_state = SEND_DATA_H) else ram_dout(7 downto 0);\r
-\r
- -- gk 05.10.10\r
- CRC_CALC : trb_net_CRC8\r
- port map(\r
- CLK => CLK_200,\r
- RESET => crc_reset,\r
- CLK_EN => crc_en,\r
- DATA_IN => crc_data,\r
- CRC_OUT => crc_q,\r
- CRC_match => open\r
- );\r
-\r
-\r
-----------------------------------------------------------------------\r
--- Debug\r
-----------------------------------------------------------------------\r
- DEBUG_OUT(0) <= ram_read;\r
- DEBUG_OUT(1) <= ct_fifo_write;\r
- DEBUG_OUT(2) <= ct_fifo_read;\r
- DEBUG_OUT(3) <= tx_allow_qtx;\r
- DEBUG_OUT(4) <= ram_empty;\r
- DEBUG_OUT(5) <= ram_afull;\r
- DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200);\r
- DEBUG_OUT(31 downto 7) <= (others => '0');\r
-\r
- process(CLK_100)\r
- begin\r
- if rising_edge(CLK_100) then\r
- STAT_REG_OUT(7 downto 0) <= std_logic_vector(ram_fill_level);\r
- STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr);\r
- STAT_REG_OUT(16) <= ram_afull;\r
- STAT_REG_OUT(17) <= ram_empty;\r
- STAT_REG_OUT(18) <= tx_allow_qtx;\r
- STAT_REG_OUT(19) <= TX_ALLOW_IN;\r
- STAT_REG_OUT(20) <= make_restart_i;\r
- STAT_REG_OUT(21) <= make_request_i;\r
- STAT_REG_OUT(22) <= load_eop;\r
- STAT_REG_OUT(31 downto 23) <= (others => '0');\r
- end if;\r
- end process;\r
-\r
-\r
-\r
-\r
-end architecture;
\ No newline at end of file
+++ /dev/null
----------------
--- TOP LEVEL --
----------------
--- TAB=3 !!
--- 24/11/2014
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_ep_soda4source is \r
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_TRB_INTERFACES : integer := 1
- );
- port (
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- \r
- --serdes I/O - connect as you like, no real use
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
-
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;\r
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0) := (others => '0')
- );\r
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
--- attribute syn_useioff of LED_LINKOK : signal is false;
--- attribute syn_useioff of LED_TX : signal is false;
--- attribute syn_useioff of LED_RX : signal is false;
--- attribute syn_useioff of SFP_MOD0 : signal is false;
--- attribute syn_useioff of SFP_TXDIS : signal is false;
--- attribute syn_useioff of SFP_LOS : signal is false;
- attribute syn_useioff of TEST_LINE : signal is false;
- --important signals _with_ IO-FF
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
-end trb3_periph_EP_soda4source;
-
-architecture trb3_periph_EP_soda4source_arch of trb3_periph_EP_soda4source is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
- --Clock / Reset
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic := '1';
- signal reset_i : std_logic := '1';
- signal GSR_N : std_logic := '0';
-
- signal clk_100_osc : std_logic;
- signal clk_200_osc : std_logic;
- signal time_counter_S : std_logic_vector(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector(NUM_TRB_INTERFACES*64-1 downto 0);
--- signal med_ctrl_debug : std_logic_vector(NUM_TRB_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector(NUM_TRB_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector(NUM_TRB_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
--- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
--- signal my_address : std_logic_vector(15 downto 0);
- signal regio_addr_out : std_logic_vector(15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector(31 downto 0);
- signal regio_data_in : std_logic_vector(31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
--- SCI for the uplink
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
--- SCI for the downlink
- signal sci2_ack : std_logic;
- signal sci2_nack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
-
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
-
- --SODA
- signal soda_ack : std_logic;
- signal soda_nack : std_logic;
- signal soda_write : std_logic;
- signal soda_read : std_logic;
- signal soda_data_in : std_logic_vector(31 downto 0);
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0);
- signal soda_leds : std_logic_vector(3 downto 0);
-
- --SODA downlink
- signal rx_half_clk : t_HUB_BIT;
- signal rx_full_clk : t_HUB_BIT;
- signal tx_half_clk : t_HUB_BIT;
- signal tx_full_clk : t_HUB_BIT;
-
- signal tx_dlm_i : t_HUB_BIT;
- signal rx_dlm_i : t_HUB_BIT;
- signal tx_dlm_word : t_HUB_BYTE;
- signal rx_dlm_word : t_HUB_BYTE;
- signal tx_dlm_preview_S : t_HUB_BIT; --PL!
- signal link_phase_S : t_HUB_BIT; --PL!
-
- signal link_debug_in_S : std_logic_vector(31 downto 0);
-
- --SODA
- signal SOB_S : std_logic := '0';
- signal soda_40mhz_cycle_S : std_logic := '0';
-
- -- fix signal names for constraining
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- attribute syn_preserve of rx_full_clk : signal is true;
- attribute syn_keep of rx_full_clk : signal is true;
- attribute syn_preserve of rx_half_clk : signal is true;
- attribute syn_keep of rx_half_clk : signal is true;
- attribute syn_preserve of tx_full_clk : signal is true;
- attribute syn_keep of tx_full_clk : signal is true;
- attribute syn_preserve of tx_half_clk : signal is true;
- attribute syn_keep of tx_half_clk : signal is true;
- attribute syn_preserve of clk_100_osc : signal is true;
- attribute syn_keep of clk_100_osc : signal is true;
- attribute syn_preserve of clk_200_osc : signal is true;
- attribute syn_keep of clk_200_osc : signal is true;
- attribute syn_preserve of tx_dlm_i : signal is true;
- attribute syn_keep of tx_dlm_i : signal is true;
- attribute syn_preserve of rx_dlm_i : signal is true;
- attribute syn_keep of rx_dlm_i : signal is true;
- attribute syn_preserve of soda_40mhz_cycle_S : signal is true;
- attribute syn_keep of soda_40mhz_cycle_S : signal is true;
-
-\r
-begin
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc,
- LOCK => pll_lock
- );
-end generate;
-
--- GSR_N <= pll_lock;
-\r
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => '0', --med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
-THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
- USE_125_MHZ => USE_125_MHZ,
- USE_CTC => c_NO,
- USE_SLAVE => SYNC_MODE
- )
- port map(
- CLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- REFCLK2CORE_OUT => open,
- CLK_RX_HALF_OUT => open,
- CLK_RX_FULL_OUT => open,
-
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(4),
- SD_RXD_N_IN => SERDES_ADDON_RX(5),
- SD_TXD_P_OUT => SERDES_ADDON_TX(4),
- SD_TXD_N_OUT => SERDES_ADDON_TX(5),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => FPGA5_COMM(0),
- SD_LOS_IN => FPGA5_COMM(0),
- SD_TXDIS_OUT => FPGA5_COMM(2),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => (others => '0')
- );
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
--- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"45",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"9100b000",
- REGIO_INIT_ADDRESS => x"f358",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 9, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 256,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 256
- )
- port map(
- CLK => clk_100_osc,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out(0),
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in(0),
- MED_DATAREADY_IN => med_dataready_in(0),
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out(0),
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => '0',
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => open,
- LVL1_VALID_TIMING_TRG_OUT => open,
- LVL1_VALID_NOTIMING_TRG_OUT => open,
- LVL1_INVALID_TRG_OUT => open,
-
- LVL1_TRG_TYPE_OUT => open,
- LVL1_TRG_NUMBER_OUT => open,
- LVL1_TRG_CODE_OUT => open,
- LVL1_TRG_INFORMATION_OUT => open,
- LVL1_INT_TRG_NUMBER_OUT => open,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => open,
- TRG_TIMEOUT_DETECTED_OUT => open,
- TRG_SPURIOUS_TRG_OUT => open,
- TRG_MISSING_TMG_TRG_OUT => open,
- TRG_SPIKE_DETECTED_OUT => open,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => '1',
- FEE_TRG_STATUSBITS_IN => (others => '0'),
- FEE_DATA_IN => (others => '0'),
- FEE_DATA_WRITE_IN(0) => '0',
- FEE_DATA_FINISHED_IN(0) => '1',
- FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
- )
- port map(
- CLK => clk_100_osc,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_READ_ENABLE_OUT(2) => sci2_read,
- BUS_READ_ENABLE_OUT(3) => soda_read,
-
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_WRITE_ENABLE_OUT(2) => sci2_write,
- BUS_WRITE_ENABLE_OUT(3) => soda_write,
-
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
- BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
- BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
-
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
- BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
-
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_TIMEOUT_OUT(3) => open,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32+8) => open,
- BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
- BUS_DATA_IN(2*32+31 downto 2*32+8) => open,
- BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
-
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_DATAREADY_IN(2) => sci2_ack,
- BUS_DATAREADY_IN(3) => soda_ack,
-
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => sci2_ack,
- BUS_WRITE_ACK_IN(3) => soda_ack,
-
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(3) => '0',
-
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => '0',
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
- port map(
- CLK_IN => clk_100_osc,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-\r
----------------------------------------------------------------------------
--- The synchronous quad-downlink interface for Soda
----------------------------------------------------------------------------
-
-MED_ECP3_SODA_QUAD_SOURCE : med_ecp3_sfp_4_soda
- generic map(
- SERDES_NUM => 0, --number of serdes (for trb) in quad
- IS_SYNC_SLAVE => c_NO
- )
- port map(
- OSC_CLK => clk_200_osc,
- TX_DATACLK => clk_200_osc,
- SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
- RESET => reset_i,
- CLEAR => clear_i,
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
--- LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- RX_HALF_CLK_OUT(0) => rx_half_clk(0),
- RX_HALF_CLK_OUT(1) => rx_half_clk(1),
- RX_HALF_CLK_OUT(2) => rx_half_clk(2),
- RX_HALF_CLK_OUT(3) => rx_half_clk(3),
-
- RX_FULL_CLK_OUT(0) => rx_full_clk(0), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(1) => rx_full_clk(1), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(2) => rx_full_clk(2), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(3) => rx_full_clk(3), -- needed for sync replies i.e. calibration
-
- TX_HALF_CLK_OUT(0) => tx_half_clk(0),
- TX_HALF_CLK_OUT(1) => tx_half_clk(1),
- TX_HALF_CLK_OUT(2) => tx_half_clk(2),
- TX_HALF_CLK_OUT(3) => tx_half_clk(3),
-
- TX_FULL_CLK_OUT(0) => tx_full_clk(0),
- TX_FULL_CLK_OUT(1) => tx_full_clk(1),
- TX_FULL_CLK_OUT(2) => tx_full_clk(2),
- TX_FULL_CLK_OUT(3) => tx_full_clk(3),
-
- RX_DLM_OUT(0) => rx_dlm_i(0),
- RX_DLM_OUT(1) => rx_dlm_i(1),
- RX_DLM_OUT(2) => rx_dlm_i(2),
- RX_DLM_OUT(3) => rx_dlm_i(3),
-
- RX_DLM_WORD_OUT(0) => rx_dlm_word(0),
- RX_DLM_WORD_OUT(1) => rx_dlm_word(1),
- RX_DLM_WORD_OUT(2) => rx_dlm_word(2),
- RX_DLM_WORD_OUT(3) => rx_dlm_word(3),
-
- TX_DLM_IN(0) => tx_dlm_i(0),
- TX_DLM_IN(1) => tx_dlm_i(1),
- TX_DLM_IN(2) => tx_dlm_i(2),
- TX_DLM_IN(3) => tx_dlm_i(3),
-
- TX_DLM_WORD_IN(0) => tx_dlm_word(0),
- TX_DLM_WORD_IN(1) => tx_dlm_word(1),
- TX_DLM_WORD_IN(2) => tx_dlm_word(2),
- TX_DLM_WORD_IN(3) => tx_dlm_word(3),
-
- TX_DLM_PREVIEW_IN(0) => tx_dlm_preview_S(0), --PL!
- TX_DLM_PREVIEW_IN(1) => tx_dlm_preview_S(1), --PL!
- TX_DLM_PREVIEW_IN(2) => tx_dlm_preview_S(2), --PL!
- TX_DLM_PREVIEW_IN(3) => tx_dlm_preview_S(3), --PL!
-
- LINK_PHASE_OUT(0) => link_phase_S(0), --PL!
- LINK_PHASE_OUT(1) => link_phase_S(1), --PL!
- LINK_PHASE_OUT(2) => link_phase_S(2), --PL!
- LINK_PHASE_OUT(3) => link_phase_S(3), --PL!
-
- --SFP Connection
- SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0
- SD_RXD_P_IN(1) => SERDES_ADDON_RX(1),
- SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1
- SD_RXD_P_IN(3) => SERDES_ADDON_RX(11),
- SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2
- SD_RXD_N_IN(1) => SERDES_ADDON_RX(3),
- SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3
- SD_RXD_N_IN(3) => SERDES_ADDON_RX(7),
- SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0
- SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1),
- SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1
- SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11),
- SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2
- SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3),
- SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3
- SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7),
- SD_REFCLK_P_IN => (others => '0'),
- SD_REFCLK_N_IN => ('0','0','0','0'),
- SD_PRSNT_N_IN(0) => SFP_MOD0(1),
- SD_PRSNT_N_IN(1) => SFP_MOD0(6),
- SD_PRSNT_N_IN(2) => SFP_MOD0(2),
- SD_PRSNT_N_IN(3) => SFP_MOD0(4),
- SD_LOS_IN(0) => SFP_LOS(1),
- SD_LOS_IN(1) => SFP_LOS(6),
- SD_LOS_IN(2) => SFP_LOS(2),
- SD_LOS_IN(3) => SFP_LOS(4),
- SD_TXDIS_OUT(0) => sfp_txdis_S(1),
- SD_TXDIS_OUT(1) => sfp_txdis_S(6),
- SD_TXDIS_OUT(2) => sfp_txdis_S(2),
- SD_TXDIS_OUT(3) => sfp_txdis_S(4),
-
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
- SCI_NACK => sci2_nack--,
-
- --Status and control port
--- STAT_OP(0) => med_stat_op(15 downto 0), --med_stat_op(1*16+15 downto 1*16),
--- CTRL_OP(0) => med_ctrl_op(15 downto 0), --med_ctrl_op(0*16+15 downto 0*16),
--- STAT_DEBUG => open,
--- CTRL_DEBUG => (others => '0')
- );
-
-
-
- SFP_TXDIS <= sfp_txdis_S;
--- SFP_TXDIS(1) <= sfp_txdis_S(1);
-
----------------------------------------------------------------------------
--- Burst- and 40MHz cycle generator
----------------------------------------------------------------------------
-
-THE_SOB_SOURCE : soda_start_of_burst_control
- generic map(
- CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns
- CYCLE_PERIOD => cSODA_CYCLE_PERIOD, -- cycle-period in ns
- BURST_PERIOD => cBURST_PERIOD -- burst-period in ns
- )
- port map(
- SODA_CLK => clk_200_osc,
- RESET => reset_i,
- SODA_BURST_PULSE_OUT => SOB_S,
- SODA_40MHZ_CYCLE_OUT => soda_40mhz_cycle_S
- );
-
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------
-
- THE_SODA_QUAD_SOURCE : soda_4source
- port map(
- SYSCLK => clk_100_osc,
- SODACLK => clk_200_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
-
- SODA_BURST_PULSE_IN => SOB_S,
- SODA_CYCLE_IN => soda_40mhz_cycle_S,
- -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
- RX_DLM_IN => rx_dlm_i,
- RX_DLM_WORD_IN => rx_dlm_word,
- TX_DLM_OUT => tx_dlm_i,
- TX_DLM_WORD_OUT => tx_dlm_word,
- TX_DLM_PREVIEW_OUT => tx_dlm_preview_S,
- LINK_PHASE_IN => link_phase_S,
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds,
- LINK_DEBUG_IN => link_debug_in_S
- );
-
-
- LED_ORANGE <= time_counter_S(27);
- LED_YELLOW <= time_counter_S(26);
- LED_GREEN <= time_counter_S(25);
- LED_RED <= time_counter_S(24);
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- blink_L : process (clk_200_osc)
- begin
- if rising_edge(clk_200_osc) then
- if (time_counter_S(15 downto 0) = x"FFFF") then
- time_counter_S(15 downto 0) <= x"0000";\r
- else
- time_counter_S(15 downto 0) <= time_counter_S(15 downto 0) + 1;
- end if;
- end if;
- end process;
-\r
- blink_H : process (clk_200_osc, time_counter_S)
- begin
- if (rising_edge(clk_200_osc) and (time_counter_S(15 downto 0) = x"FFFF"))then
- if ((time_counter_S(31 downto 16) = x"FFFF") and (time_counter_S(15 downto 0) = x"FFFF")) then
- time_counter_S(31 downto 16) <= x"0000";
- else
- time_counter_S(31 downto 16) <= time_counter_S(31 downto 16) + 1;
- end if;
- end if;
- end process;
-
-
- TEST_LINE(15 downto 3) <= time_counter_S(31 downto 19); --(others => '0'); -- otherwise it is floating
-
- TEST_LINE(2) <= '1';
- TEST_LINE(1) <= '1';
- TEST_LINE(0) <= '1';
--- TEST_LINE(7 downto 0) <= (others => '1'); -- otherwise it is floating
--- TEST_LINE(15 downto 8) <= (others => '0'); -- otherwise it is floating
-
-end trb3_periph_EP_soda4source_arch;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_EP_hub is
- generic(
- SYNC_MODE : integer range 0 to 1 := c_YES; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_TRB_INTERFACES : integer := 1
- );
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
- --serdes I/O - connect as you like, no real use
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
-
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- --SFP_MOD1 : inout std_logic_vector(6 downto 1);
- --SFP_MOD2 : inout std_logic_vector(6 downto 1);
- --SFP_RATESEL : out std_logic_vector(6 downto 1);
- --SFP_TXFAULT : in std_logic_vector(6 downto 1);
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
-
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
-
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of LED_LINKOK : signal is false;
- attribute syn_useioff of LED_TX : signal is false;
- attribute syn_useioff of LED_RX : signal is false;
- attribute syn_useioff of SFP_MOD0 : signal is false;
- attribute syn_useioff of SFP_TXDIS : signal is false;
- attribute syn_useioff of SFP_LOS : signal is false;
- attribute syn_useioff of TEST_LINE : signal is false;
-
- --important signals _with_ IO-FF
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_EP_hub_arch of trb3_periph_EP_hub is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-
- --Clock / Reset
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal downlink_clear : std_logic;
- signal downlink_reset : std_logic;
- signal GSR_N : std_logic;
- signal clk_100_osc : std_logic;
- signal clk_200_osc : std_logic;
- signal time_counter : unsigned(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_TRB_INTERFACES*64-1 downto 0);
--- signal med_ctrl_debug : std_logic_vector (NUM_TRB_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_TRB_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_TRB_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
--- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
--- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
--- SCI for the uplink
- signal sci1_ack : std_logic;
- signal sci1_nack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
--- SCI for the downlink
- signal sci2_ack : std_logic;
- signal sci2_nack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
-
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
-
- --SODA
- signal soda_ack : std_logic;
- signal soda_nack : std_logic;
- signal soda_write : std_logic;
- signal soda_read : std_logic;
- signal soda_data_in : std_logic_vector(31 downto 0);
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0);
- signal soda_leds : std_logic_vector(3 downto 0);
-
- --SODA uplink
- signal rxup_half_clk : std_logic;
- signal rxup_full_clk : std_logic;
- signal txup_half_clk : std_logic;
- signal txup_full_clk : std_logic;
-
- signal rx_cdr_lol_S : std_logic;
- signal txup_dlm_i : std_logic;
- signal rxup_dlm_i : std_logic;
- signal txup_dlm_word : std_logic_vector(7 downto 0);
- signal rxup_dlm_word : std_logic_vector(7 downto 0);
- signal txup_dlm_preview_S : std_logic; --PL!
- signal uplink_phase_S : std_logic; --PL!
- signal uplink_ready_S : std_logic; --PL!
-
- --SODA downlink
- signal rxdn_half_clk : t_HUB_BIT;
- signal rxdn_full_clk : t_HUB_BIT;
- signal txdn_half_clk : t_HUB_BIT;
- signal txdn_full_clk : t_HUB_BIT;
-
- signal txdn_dlm_i : t_HUB_BIT;
- signal rxdn_dlm_i : t_HUB_BIT;
- signal txdn_dlm_word : t_HUB_BYTE;
- signal rxdn_dlm_word : t_HUB_BYTE;
- signal txdn_dlm_preview_S : t_HUB_BIT; --PL!
- signal dnlink_phase_S : t_HUB_BIT; --PL!
-
- signal link_debug_in_S : std_logic_vector(31 downto 0);
-
- --SODA
- signal SOB_S : std_logic := '0';
- -- fix signal names for constraining
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- attribute syn_preserve of clk_100_osc : signal is true;
- attribute syn_keep of clk_100_osc : signal is true;
- attribute syn_preserve of clk_200_osc : signal is true;
- attribute syn_keep of clk_200_osc : signal is true;
-
- attribute syn_preserve of rxup_full_clk : signal is true;
- attribute syn_keep of rxup_full_clk : signal is true;
- attribute syn_preserve of rxup_half_clk : signal is true;
- attribute syn_keep of rxup_half_clk : signal is true;
- attribute syn_preserve of txup_full_clk : signal is true;
- attribute syn_keep of txup_full_clk : signal is true;
- attribute syn_preserve of txup_half_clk : signal is true;
- attribute syn_keep of txup_half_clk : signal is true;
- attribute syn_preserve of txup_dlm_i : signal is true;
- attribute syn_keep of txup_dlm_i : signal is true;
- attribute syn_preserve of rxup_dlm_i : signal is true;
- attribute syn_keep of rxup_dlm_i : signal is true;
-
- attribute syn_preserve of rxdn_full_clk : signal is true;
- attribute syn_keep of rxdn_full_clk : signal is true;
- attribute syn_preserve of rxdn_half_clk : signal is true;
- attribute syn_keep of rxdn_half_clk : signal is true;
- attribute syn_preserve of txdn_full_clk : signal is true;
- attribute syn_keep of txdn_full_clk : signal is true;
- attribute syn_preserve of txdn_half_clk : signal is true;
- attribute syn_keep of txdn_half_clk : signal is true;
- attribute syn_preserve of txdn_dlm_i : signal is true;
- attribute syn_keep of txdn_dlm_i : signal is true;
- attribute syn_preserve of rxdn_dlm_i : signal is true;
- attribute syn_keep of rxdn_dlm_i : signal is true;
-
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
---gen_200_PLL : if USE_125_MHZ = c_NO generate
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc,
- LOCK => pll_lock
- );
---end generate;
-
---gen_125 : if USE_125_MHZ = c_YES generate
--- clk_100_osc <= CLK_GPLL_LEFT;
--- clk_200_osc <= CLK_GPLL_LEFT;
---end generate;
-
-
-
----------------------------------------------------------------------------
--- The synchronous interface for Soda and trb_endpoint
----------------------------------------------------------------------------
-
-THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_YES
- )
- port map(
- OSCCLK => clk_200_osc,
- SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_sync_down.vhd
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- RX_HALF_CLK_OUT => rxup_half_clk,
- RX_FULL_CLK_OUT => rxup_full_clk,
- TX_HALF_CLK_OUT => txup_half_clk,
- TX_FULL_CLK_OUT => txup_full_clk,
- RX_CDR_LOL_OUT => rx_cdr_lol_S, -- !PL 14082014
-
- RX_DLM => rxup_dlm_i,
- RX_DLM_WORD => rxup_dlm_word,
- TX_DLM => txup_dlm_i,
- TX_DLM_WORD => txup_dlm_word,
- TX_DLM_PREVIEW_IN => txup_dlm_preview_S, --PL!
- LINK_PHASE_OUT => uplink_phase_S, --PL!
- LINK_READY_OUT => uplink_ready_S, --PL!
- --SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting
- SD_RXD_P_IN => SERDES_ADDON_RX(4),
- SD_RXD_N_IN => SERDES_ADDON_RX(5),
- SD_TXD_P_OUT => SERDES_ADDON_TX(4),
- SD_TXD_N_OUT => SERDES_ADDON_TX(5),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(3), -- = A3, was 1 = B0
- SD_LOS_IN => SFP_LOS(3),
- SD_TXDIS_OUT => sfp_txdis_S(3), --SFP_TXDIS(3), this signal is now used to release downlinks
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- SCI_NACK => sci1_nack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-\r
-
- SFP_TXDIS <= sfp_txdis_S;
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
--- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"45",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"9100b000",
- REGIO_INIT_ADDRESS => x"f359",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 9, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 256,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 256
- )
- port map(
- CLK => clk_100_osc,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out(0),
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in(0),
- MED_DATAREADY_IN => med_dataready_in(0),
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out(0),
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => '0',
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => open,
- LVL1_VALID_TIMING_TRG_OUT => open,
- LVL1_VALID_NOTIMING_TRG_OUT => open,
- LVL1_INVALID_TRG_OUT => open,
-
- LVL1_TRG_TYPE_OUT => open,
- LVL1_TRG_NUMBER_OUT => open,
- LVL1_TRG_CODE_OUT => open,
- LVL1_TRG_INFORMATION_OUT => open,
- LVL1_INT_TRG_NUMBER_OUT => open,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => open,
- TRG_TIMEOUT_DETECTED_OUT => open,
- TRG_SPURIOUS_TRG_OUT => open,
- TRG_MISSING_TMG_TRG_OUT => open,
- TRG_SPIKE_DETECTED_OUT => open,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => '1',
- FEE_TRG_STATUSBITS_IN => (others => '0'),
- FEE_DATA_IN => (others => '0'),
- FEE_DATA_WRITE_IN(0) => '0',
- FEE_DATA_FINISHED_IN(0) => '1',
- FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
- )
- port map(
- CLK => clk_100_osc,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_READ_ENABLE_OUT(2) => sci2_read,
- BUS_READ_ENABLE_OUT(3) => soda_read,
-
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_WRITE_ENABLE_OUT(2) => sci2_write,
- BUS_WRITE_ENABLE_OUT(3) => soda_write,
-
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
- BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
- BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
-
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
- BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
-
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_TIMEOUT_OUT(3) => open,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32+8) => open,
- BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
- BUS_DATA_IN(2*32+31 downto 2*32+8) => open,
- BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
-
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_DATAREADY_IN(2) => sci2_ack,
- BUS_DATAREADY_IN(3) => soda_ack,
-
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => sci2_ack,
- BUS_WRITE_ACK_IN(3) => soda_ack,
-
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(3) => '0',
-
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => '0',
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
- port map(
- CLK_IN => clk_100_osc,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
-
----------------------------------------------------------------------------
--- The synchronous quad-downlink interface for Soda
----------------------------------------------------------------------------
-
- THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down_EP
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_NO
- )
- port map(
- OSC_CLK => clk_200_osc,
- TX_DATACLK => rxup_full_clk,
- SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
- RESET => downlink_reset,
- CLEAR => downlink_clear,
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- RX_HALF_CLK_OUT(0) => rxdn_half_clk(0),
- RX_HALF_CLK_OUT(1) => rxdn_half_clk(1),
- RX_HALF_CLK_OUT(2) => rxdn_half_clk(2),
- RX_HALF_CLK_OUT(3) => rxdn_half_clk(3),
-
- RX_FULL_CLK_OUT(0) => rxdn_full_clk(0), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(1) => rxdn_full_clk(1), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(2) => rxdn_full_clk(2), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(3) => rxdn_full_clk(3), -- needed for sync replies i.e. calibration
-
- TX_HALF_CLK_OUT(0) => txdn_half_clk(0),
- TX_HALF_CLK_OUT(1) => txdn_half_clk(1),
- TX_HALF_CLK_OUT(2) => txdn_half_clk(2),
- TX_HALF_CLK_OUT(3) => txdn_half_clk(3),
-
- TX_FULL_CLK_OUT(0) => txdn_full_clk(0),
- TX_FULL_CLK_OUT(1) => txdn_full_clk(1),
- TX_FULL_CLK_OUT(2) => txdn_full_clk(2),
- TX_FULL_CLK_OUT(3) => txdn_full_clk(3),
-
- RX_DLM(0) => rxdn_dlm_i(0),
- RX_DLM(1) => rxdn_dlm_i(1),
- RX_DLM(2) => rxdn_dlm_i(2),
- RX_DLM(3) => rxdn_dlm_i(3),
-
- RX_DLM_WORD(0) => rxdn_dlm_word(0),
- RX_DLM_WORD(1) => rxdn_dlm_word(1),
- RX_DLM_WORD(2) => rxdn_dlm_word(2),
- RX_DLM_WORD(3) => rxdn_dlm_word(3),
-
- TX_DLM(0) => txdn_dlm_i(0),
- TX_DLM(1) => txdn_dlm_i(1),
- TX_DLM(2) => txdn_dlm_i(2),
- TX_DLM(3) => txdn_dlm_i(3),
-
- TX_DLM_WORD(0) => txdn_dlm_word(0),
- TX_DLM_WORD(1) => txdn_dlm_word(1),
- TX_DLM_WORD(2) => txdn_dlm_word(2),
- TX_DLM_WORD(3) => txdn_dlm_word(3),
-
- TX_DLM_PREVIEW_IN(0) => txdn_dlm_preview_S(0), --PL!
- TX_DLM_PREVIEW_IN(1) => txdn_dlm_preview_S(1), --PL!
- TX_DLM_PREVIEW_IN(2) => txdn_dlm_preview_S(2), --PL!
- TX_DLM_PREVIEW_IN(3) => txdn_dlm_preview_S(3), --PL!
-
- LINK_PHASE_OUT(0) => dnlink_phase_S(0), --PL!
- LINK_PHASE_OUT(1) => dnlink_phase_S(1), --PL!
- LINK_PHASE_OUT(2) => dnlink_phase_S(2), --PL!
- LINK_PHASE_OUT(3) => dnlink_phase_S(3), --PL!
-
- --SFP Connection
- SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0
- SD_RXD_P_IN(1) => SERDES_ADDON_RX(1),
- SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1
- SD_RXD_P_IN(3) => SERDES_ADDON_RX(11),
- SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2
- SD_RXD_N_IN(1) => SERDES_ADDON_RX(3),
- SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3
- SD_RXD_N_IN(3) => SERDES_ADDON_RX(7),
- SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0
- SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1),
- SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1
- SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11),
- SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2
- SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3),
- SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3
- SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7),
- SD_REFCLK_P_IN => (others => '0'),
- SD_REFCLK_N_IN => ('0','0','0','0'),
- SD_PRSNT_N_IN(0) => SFP_MOD0(1),
- SD_PRSNT_N_IN(1) => SFP_MOD0(6),
- SD_PRSNT_N_IN(2) => SFP_MOD0(2),
- SD_PRSNT_N_IN(3) => SFP_MOD0(4),
- SD_LOS_IN(0) => SFP_LOS(1),
- SD_LOS_IN(1) => SFP_LOS(6),
- SD_LOS_IN(2) => SFP_LOS(2),
- SD_LOS_IN(3) => SFP_LOS(4),
- SD_TXDIS_OUT(0) => sfp_txdis_S(1),
- SD_TXDIS_OUT(1) => sfp_txdis_S(6),
- SD_TXDIS_OUT(2) => sfp_txdis_S(2),
- SD_TXDIS_OUT(3) => sfp_txdis_S(4),
-
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
- SCI_NACK => sci2_nack,
-
- --Status and control port
--- STAT_OP(0) => med_stat_op(15 downto 0), --med_stat_op(1*16+15 downto 1*16),
--- CTRL_OP(0) => med_ctrl_op(15 downto 0), --med_ctrl_op(0*16+15 downto 0*16),
-
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-
-
-
- SFP_TXDIS <= sfp_txdis_S;
--- SFP_TXDIS(1) <= sfp_txdis_S(1);
-
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------
-
-THE_SOB_SOURCE : soda_start_of_burst_faker
- generic map(
- CLOCK_PERIOD => cSYS_CLOCK_PERIOD, -- clock-period in ns
- BURST_PERIOD => cBURST_PERIOD -- burst-period in ns
- )
- port map(
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- SODA_BURST_PULSE_OUT => SOB_S
- );
-
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------
-
- A_SODA_HUB : soda_hub
- port map(
- SYSCLK => rxup_half_clk,
- SODACLK => rxup_full_clk,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
-
- -- SINGLE DUBPLEX UP-LINK TO THE TOP
- RXUP_DLM_WORD_IN => rxup_dlm_word,
- RXUP_DLM_IN => rxup_dlm_i,
- TXUP_DLM_OUT => txup_dlm_i,
- TXUP_DLM_WORD_OUT => txup_dlm_word,
- TXUP_DLM_PREVIEW_OUT => txup_dlm_preview_S,
- UPLINK_PHASE_IN => uplink_phase_S,
- -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
- RXDN_DLM_WORD_IN => rxdn_dlm_word,
- RXDN_DLM_IN => rxdn_dlm_i,
- TXDN_DLM_OUT => txdn_dlm_i,
- TXDN_DLM_WORD_OUT => txdn_dlm_word,
- TXDN_DLM_PREVIEW_OUT => txdn_dlm_preview_S,
- DNLINK_PHASE_IN => dnlink_phase_S,
-
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds,
- LINK_DEBUG_IN => link_debug_in_S
- );
-
-
- downlink_reset <= '1' when (reset_i = '1' or uplink_ready_S = '0') else '0';
- downlink_clear <= '1' when (clear_i = '1' or uplink_ready_S = '0') else '0';
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);
- LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);
- LED_GREEN <= med_stat_op(12); --tx_pll_lol
- LED_RED <= med_stat_op(11); --rx_cdr_lol
-
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------
--- TEST_LINE(15 downto 0) <= (others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- process
- begin
- wait until rising_edge(clk_100_osc);
- time_counter <= time_counter + 1;
- end process;
-
-
-end trb3_periph_EP_hub_arch;
\ No newline at end of file
+++ /dev/null
----------------
--- TOP LEVEL --
----------------
--- TAB=3 !!
--- 24/11/2014
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodaclient is
- generic(
- SYNC_MODE : integer range 0 to 1 := c_YES; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_INTERFACES : integer := 1
- );
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
- --Trigger
- --TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
- --TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
- --Serdes Clocks - do not use
- --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
- --CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
-
- --serdes I/O - connect as you like, no real use
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
-
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- --SFP_MOD1 : inout std_logic_vector(6 downto 1);
- --SFP_MOD2 : inout std_logic_vector(6 downto 1);
- --SFP_RATESEL : out std_logic_vector(6 downto 1);
- --SFP_TXFAULT : in std_logic_vector(6 downto 1);
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
-
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
-
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of LED_LINKOK : signal is false;
- attribute syn_useioff of LED_TX : signal is false;
- attribute syn_useioff of LED_RX : signal is false;
- attribute syn_useioff of SFP_MOD0 : signal is false;
- attribute syn_useioff of SFP_TXDIS : signal is false;
- attribute syn_useioff of SFP_LOS : signal is false;
- attribute syn_useioff of TEST_LINE : signal is false;
-
- --important signals _with_ IO-FF
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
- --Clock / Reset
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR : std_logic;
- signal GSR_N : std_logic;
-\r
- signal clk_100_osc : std_logic;
- signal clk_200_osc : std_logic;
- signal rx_full_clk : std_logic;
- signal rx_half_clk : std_logic;
- signal tx_full_clk : std_logic;
- signal tx_half_clk : std_logic;
- signal time_counter, time_counter2 : unsigned(31 downto 0);
- \r
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- --media interface
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sci1_nack : std_logic;
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
-
-
- --SODA
- signal tx_dlm_i : std_logic;
- signal rx_dlm_i : std_logic;
- signal tx_dlm_word : std_logic_vector(7 downto 0);
- signal rx_dlm_word : std_logic_vector(7 downto 0);
- signal make_reset : std_logic;
- signal tx_dlm_preview_S : std_logic; --PL!
- signal link_phase_S : std_logic; --PL!
- signal rx_cdr_lol_S : std_logic;
- signal link_locked_S : std_logic; --PL!
-
- -- SODA slow controll
- signal soda_ack : std_logic;
--- signal soda_nack : std_logic;
- signal soda_write : std_logic;
- signal soda_read : std_logic;
- signal soda_data_in : std_logic_vector(31 downto 0);
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0);
- signal soda_leds : std_logic_vector(3 downto 0);
-
- signal link_debug_in_S : std_logic_vector(31 downto 0);
- signal general_reset_i : std_logic := '1';
-
- signal soda_counter_i : unsigned(3 downto 0);
- -- fix signal names for constraining
- attribute syn_preserve of rx_full_clk : signal is true;
- attribute syn_keep of rx_full_clk : signal is true;
- attribute syn_preserve of rx_half_clk : signal is true;
- attribute syn_keep of rx_half_clk : signal is true;
- attribute syn_preserve of clk_100_osc : signal is true;
- attribute syn_keep of clk_100_osc : signal is true;
- attribute syn_preserve of clk_200_osc : signal is true;
- attribute syn_keep of clk_200_osc : signal is true;
- attribute syn_preserve of tx_dlm_i : signal is true;
- attribute syn_keep of tx_dlm_i : signal is true;
- attribute syn_preserve of rx_dlm_i : signal is true;
- attribute syn_keep of rx_dlm_i : signal is true;
- attribute syn_keep of GSR : signal is true;
- attribute syn_preserve of GSR : signal is true;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- attribute syn_keep of soda_counter_i : signal is true;
- attribute syn_preserve of soda_counter_i : signal is true;
-
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-
- LED_RX <= (others => '0'); -- otherwise it is floating
- LED_TX <= (others => '0'); -- otherwise it is floating
- LED_LINKOK <= (others => '0'); -- otherwise it is floating
-
- GSR_N <= pll_lock;\r
- GSR <= not(pll_lock);
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => rx_half_clk, --clk_100_osc, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', --general_reset_i, --'0', -- general reset signal (SYSCLK) --peter schakel
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
- process(rx_half_clk)
- begin
- if rising_edge(rx_half_clk) then
- general_reset_i <= not SFP_LOS(1);
- end if;
- end process;
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
---gen_200_PLL : if USE_125_MHZ = c_NO generate
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,\r
- RESET => '0',
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc,
- LOCK => pll_lock
- );
---end generate;
-
---gen_125 : if USE_125_MHZ = c_YES generate
--- clk_100_osc <= CLK_GPLL_LEFT;
--- clk_raw_internal <= CLK_GPLL_LEFT;
---end generate;
-
---gen_sync_clocks : if SYNC_MODE = c_YES generate
--- clk_sys_i <= clk_100_osc;
--- clk_soda_i <= soda_rx_clock_full;
--- clk_200_i <= soda_rx_clock_full;
---end generate;
-
---gen_local_clocks : if SYNC_MODE = c_NO generate
--- clk_sys_i <= clk_100_osc;
--- clk_soda_i <= clk_raw_internal;
--- clk_200_i <= clk_raw_internal;
---end generate;
-
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
--- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"45",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"9100b000",
- REGIO_INIT_ADDRESS => x"f356",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 9, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 256,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 256
- )
- port map(
- CLK => rx_half_clk, --clk_100_osc,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out(0),
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in(0),
- MED_DATAREADY_IN => med_dataready_in(0),
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out(0),
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => '0',
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => open,
- LVL1_VALID_TIMING_TRG_OUT => open,
- LVL1_VALID_NOTIMING_TRG_OUT => open,
- LVL1_INVALID_TRG_OUT => open,
-
- LVL1_TRG_TYPE_OUT => open,
- LVL1_TRG_NUMBER_OUT => open,
- LVL1_TRG_CODE_OUT => open,
- LVL1_TRG_INFORMATION_OUT => open,
- LVL1_INT_TRG_NUMBER_OUT => open,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => open,
- TRG_TIMEOUT_DETECTED_OUT => open,
- TRG_SPURIOUS_TRG_OUT => open,
- TRG_MISSING_TMG_TRG_OUT => open,
- TRG_SPIKE_DETECTED_OUT => open,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => '1',
- FEE_TRG_STATUSBITS_IN => (others => '0'),
- FEE_DATA_IN => (others => '0'),
- FEE_DATA_WRITE_IN(0) => '0',
- FEE_DATA_FINISHED_IN(0) => '1',
- FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => (others => '0'), --common_stat_reg, --0x00 because it is floating
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 4, others => 0)
- )
- port map(
- CLK => rx_half_clk, --clk_100_osc,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_READ_ENABLE_OUT(2) => soda_read,
-
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_WRITE_ENABLE_OUT(2) => soda_write,
-
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+31 downto 2*32) => soda_data_in,
-
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_ADDR_OUT(2*16+3 downto 2*16) => soda_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+4) => open,
-
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32+8) => open,
- BUS_DATA_IN(2*32+31 downto 2*32) => soda_data_out,
-
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_DATAREADY_IN(2) => soda_ack,
-
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => soda_ack,
-
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
-
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => '0',
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
- port map(
- CLK_IN => clk_100_osc, --rx_half_clk,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
-
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------
-
-THE_SYNC_LINK : med_ecp3_sfp_sync_up
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- IS_SYNC_SLAVE => c_YES
- )
- port map(
- OSCCLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- RX_HALF_CLK_OUT => rx_half_clk, --soda_rx_clock_half,
- RX_FULL_CLK_OUT => rx_full_clk, --soda_rx_clock_full,
- TX_HALF_CLK_OUT => tx_half_clk,
- TX_FULL_CLK_OUT => tx_full_clk,
- RX_CDR_LOL_OUT => rx_cdr_lol_S,
-
- RX_DLM => rx_dlm_i,
- RX_DLM_WORD => rx_dlm_word,
- TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,
- TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
- LINK_PHASE_OUT => link_phase_S, --PL!
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(4), --(0),
- SD_RXD_N_IN => SERDES_ADDON_RX(5), --(1),
- SD_TXD_P_OUT => SERDES_ADDON_TX(4), --(0),
- SD_TXD_N_OUT => SERDES_ADDON_TX(5), --(1),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(3), --(1),
- SD_LOS_IN => SFP_LOS(3), --(1),
- SD_TXDIS_OUT => sfp_txdis_S(3), --(1), --SFP_TXDIS(1),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- SCI_NACK => sci1_nack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );\r
-\r
-
--- SFP_TXDIS(1) <= sfp_txdis_S(1);
- SFP_TXDIS <= sfp_txdis_S;
-
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------
-
- A_SODA_CLIENT : soda_client
- port map(
- SYSCLK => rx_half_clk, --clk_100_osc,
- SODACLK => rx_full_clk,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- RX_DLM_WORD_IN => rx_dlm_word,
- RX_DLM_IN => rx_dlm_i,
- TX_DLM_OUT => tx_dlm_i,
- TX_DLM_WORD_OUT => tx_dlm_word,
- TX_DLM_PREVIEW_OUT => tx_dlm_preview_S,
- LINK_PHASE_IN => link_phase_S,
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds,
- LINK_DEBUG_IN => link_debug_in_S
- );
-
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_ORANGE <= '0'; --reset_i; --med_stat_op(8);
- LED_YELLOW <= '1'; --clear_i; --med_stat_op(10);
- LED_GREEN <= pll_lock; --tx_pll_lol
- LED_RED <= time_counter(26); --rx_cdr_lol
--- LED_ORANGE <= not reset_i when rising_edge(clk_100_osc);
--- LED_YELLOW <= soda_leds(0); --'1';
--- LED_GREEN <= not med_stat_op(9);
--- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
--- LED_ORANGE <= soda_leds(0);
--- LED_YELLOW <= soda_leds(1);
--- LED_GREEN <= soda_leds(2);
--- LED_RED <= soda_leds(3);
-
----------------------------------------------------------------------------
--- DEBUG
----------------------------------------------------------------------------
- link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0);
- link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- blink : process (clk_100_osc)
- begin
- if rising_edge(clk_100_osc) then
- if (time_counter = x"FFFFFFFF") then
- time_counter <= x"00000000";
- else
- time_counter <= time_counter + 1;
- end if;
- end if;
- end process;\r
-
- process(rx_full_clk) --soda_rx_clock_full) --clk_soda_i)
- begin
- if rising_edge(rx_full_clk) then
- soda_counter_i <= soda_counter_i+1;
- end if;
- end process;
-
-
-end trb3_periph_sodaclient_arch;
+++ /dev/null
----------------\r
--- TOP LEVEL --\r
----------------\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.trb_net16_hub_func.all;\r
-use work.trb3_components.all; \r
-use work.soda_components.all;\r
-use work.med_sync_define.all;\r
-use work.version.all;\r
-\r
-entity trb3_periph_sodahub is\r
- generic(\r
--- SYNC_MODE : integer range 0 to 1 := c_YES; --use the RX clock for internal logic and transmission. Should be NO for soda tests!\r
- USE_125_MHZ : integer := c_NO;\r
- CLOCK_FREQUENCY : integer := 100;\r
- NUM_INTERFACES : integer := 6 + 1 -- This is the number of SERDES's in use: 1 copper trb-upstream + 6 to ADDONboard\r
- );\r
- port(\r
- --Clocks \r
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz\r
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA\r
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!\r
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!\r
-\r
-\r
- --serdes I/O - connect as you like, no real use\r
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);\r
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);\r
-\r
- --Inter-FPGA Communication\r
- FPGA5_COMM : inout std_logic_vector(11 downto 0);\r
- --Bit 0/1 input, serial link RX active\r
- --Bit 2/3 output, serial link TX active\r
- --others yet undefined\r
- --Connection to AddOn\r
- LED_LINKOK : out std_logic_vector(6 downto 1);\r
- LED_RX : out std_logic_vector(6 downto 1);\r
- LED_TX : out std_logic_vector(6 downto 1);\r
- SFP_MOD0 : in std_logic_vector(6 downto 1);\r
- SFP_TXDIS : out std_logic_vector(6 downto 1);\r
- SFP_LOS : in std_logic_vector(6 downto 1);\r
- SFP_MOD1 : inout std_logic_vector(6 downto 1); --H!\r
- SFP_MOD2 : inout std_logic_vector(6 downto 1); --H!\r
- --SFP_RATESEL : out std_logic_vector(6 downto 1);\r
- --SFP_TXFAULT : in std_logic_vector(6 downto 1);\r
-\r
- --Flash ROM & Reboot\r
- FLASH_CLK : out std_logic;\r
- FLASH_CS : out std_logic;\r
- FLASH_DIN : out std_logic;\r
- FLASH_DOUT : in std_logic;\r
- PROGRAMN : out std_logic; --reboot FPGA\r
-\r
- --Misc\r
- TEMPSENS : inout std_logic; --Temperature Sensor\r
- CODE_LINE : in std_logic_vector(1 downto 0);\r
- LED_GREEN : out std_logic;\r
- LED_ORANGE : out std_logic;\r
- LED_RED : out std_logic;\r
- LED_YELLOW : out std_logic;\r
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads\r
-\r
- --Test Connectors\r
- TEST_LINE : out std_logic_vector(15 downto 0)\r
- );\r
- \r
- attribute syn_useioff : boolean;\r
- --no IO-FF for LEDs relaxes timing constraints\r
- attribute syn_useioff of SFP_LOS : signal is false;\r
- attribute syn_useioff of SFP_TXDIS : signal is false;\r
- attribute syn_useioff of SFP_MOD0 : signal is false;\r
- attribute syn_useioff of LED_RX : signal is false;\r
- attribute syn_useioff of LED_TX : signal is false;\r
- attribute syn_useioff of LED_LINKOK : signal is false;\r
-\r
-\r
- end entity trb3_periph_sodahub;\r
-\r
-\r
-architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is\r
- --Constants\r
- constant REGIO_NUM_STAT_REGS : integer := 2; --0; H!\r
- constant REGIO_NUM_CTRL_REGS : integer := 2;\r
-\r
-\r
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa\r
-\r
- --Clock / Reset\r
- -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL\r
--- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL\r
- -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL\r
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.\r
- signal clear_i : std_logic;\r
- signal reset_i : std_logic;\r
- signal downlink_clear : std_logic;\r
- signal downlink_reset : std_logic;\r
- signal GSR_N : std_logic;\r
- attribute syn_keep of GSR_N : signal is true;\r
- attribute syn_preserve of GSR_N : signal is true;\r
- signal clk_100_osc : std_logic;\r
--- signal clk_raw_internal : std_logic;\r
- signal clk_200_osc : std_logic;\r
-\r
- signal rxup_half_clk : std_logic;\r
- signal rxup_full_clk : std_logic;\r
- signal txup_half_clk : std_logic;\r
- signal txup_full_clk : std_logic;\r
- signal rx_cdr_lol_S : std_logic;\r
-\r
- signal rxdn_half_clk : t_HUB_BIT;\r
- signal rxdn_full_clk : t_HUB_BIT;\r
- signal txdn_half_clk : t_HUB_BIT;\r
- signal txdn_full_clk : t_HUB_BIT;\r
-\r
- signal time_counter : unsigned(31 downto 0);\r
- --Media Interface\r
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');\r
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');\r
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');\r
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');\r
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
-\r
- --Slow Control channel\r
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);\r
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);\r
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);\r
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);\r
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);\r
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);\r
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);\r
-\r
- --RegIO\r
- signal my_address : std_logic_vector (15 downto 0);\r
- signal regio_addr_out : std_logic_vector (15 downto 0);\r
- signal regio_read_enable_out : std_logic;\r
- signal regio_write_enable_out : std_logic;\r
- signal regio_data_out : std_logic_vector (31 downto 0);\r
- signal regio_data_in : std_logic_vector (31 downto 0);\r
- signal regio_dataready_in : std_logic;\r
- signal regio_no_more_data_in : std_logic;\r
- signal regio_write_ack_in : std_logic;\r
- signal regio_unknown_addr_in : std_logic;\r
- signal regio_timeout_out : std_logic;\r
-\r
- --Timer\r
- signal global_time : std_logic_vector(31 downto 0);\r
- signal local_time : std_logic_vector(7 downto 0);\r
- signal time_since_last_trg : std_logic_vector(31 downto 0);\r
- signal timer_ticks : std_logic_vector(1 downto 0);\r
-\r
- --Flash\r
- signal spimem_read_en : std_logic;\r
- signal spimem_write_en : std_logic;\r
- signal spimem_data_in : std_logic_vector(31 downto 0);\r
- signal spimem_addr : std_logic_vector(8 downto 0);\r
- signal spimem_data_out : std_logic_vector(31 downto 0);\r
- signal spimem_dataready_out : std_logic;\r
- signal spimem_no_more_data_out : std_logic;\r
- signal spimem_unknown_addr_out : std_logic;\r
- signal spimem_write_ack_out : std_logic;\r
-\r
- --media interface\r
- signal sci1_ack : std_logic;\r
- signal sci1_write : std_logic;\r
- signal sci1_read : std_logic;\r
- signal sci1_data_in : std_logic_vector(7 downto 0);\r
- signal sci1_data_out : std_logic_vector(7 downto 0);\r
- signal sci1_addr : std_logic_vector(8 downto 0); \r
- signal sci1_nack : std_logic;\r
- \r
- signal sci2_ack : std_logic;\r
- signal sci2_nack : std_logic;\r
- signal sci2_write : std_logic;\r
- signal sci2_read : std_logic;\r
- signal sci2_data_in : std_logic_vector(7 downto 0);\r
- signal sci2_data_out : std_logic_vector(7 downto 0);\r
- signal sci2_addr : std_logic_vector(8 downto 0); \r
-\r
- signal sfp_mod0_B : t_QUAD_BIT := (others => '0');\r
- signal sfp_los_B : t_QUAD_BIT := (others => '0');\r
- signal sfp_txdis_B : t_QUAD_BIT := (others => '0');\r
-\r
-\r
- --SODA\r
- signal make_reset : std_logic;\r
-\r
- --SODA uplink\r
- signal txup_dlm_i : std_logic;\r
- signal rxup_dlm_i : std_logic;\r
- signal txup_dlm_word : std_logic_vector(7 downto 0);\r
- signal rxup_dlm_word : std_logic_vector(7 downto 0);\r
- signal txup_dlm_preview_S : std_logic; --PL!\r
- signal uplink_phase_S : std_logic; --PL!\r
- signal uplink_ready_S : std_logic; --PL!\r
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1'); \r
-\r
- --SODA downlink\r
- signal txdn_dlm_i : t_HUB_BIT;\r
- signal rxdn_dlm_i : t_HUB_BIT;\r
- signal txdn_dlm_word : t_HUB_BYTE;\r
- signal rxdn_dlm_word : t_HUB_BYTE;\r
- signal txdn_dlm_preview_S : t_HUB_BIT; --PL!\r
- signal dnlink_phase_S : t_HUB_BIT; --PL!\r
-\r
- -- SODA slow controll\r
- signal soda_ack : std_logic;\r
--- signal soda_nack : std_logic;\r
- signal soda_write : std_logic;\r
- signal soda_read : std_logic;\r
- signal soda_data_in : std_logic_vector(31 downto 0);\r
- signal soda_data_out : std_logic_vector(31 downto 0);\r
- signal soda_addr : std_logic_vector(3 downto 0); \r
- signal soda_leds : std_logic_vector(3 downto 0); \r
-\r
- signal link_debug_in_S : std_logic_vector(31 downto 0);\r
- signal general_reset_i : std_logic := '1';\r
- \r
--- signal soda_counter_i : unsigned(31 downto 0);\r
- \r
-\r
--- attribute syn_keep of soda_counter_i : signal is true;\r
- -- fix signal names for constraining\r
- attribute syn_preserve of clk_100_osc : signal is true;\r
- attribute syn_keep of clk_100_osc : signal is true;\r
--- attribute syn_preserve of clk_raw_internal : signal is true;\r
--- attribute syn_keep of clk_raw_internal : signal is true;\r
--- attribute syn_preserve of clk_soda_i : signal is true;\r
--- attribute syn_keep of clk_soda_i : signal is true;\r
- attribute syn_preserve of txup_dlm_i : signal is true;\r
- attribute syn_keep of txup_dlm_i : signal is true;\r
- attribute syn_preserve of rxup_dlm_i : signal is true;\r
- attribute syn_keep of rxup_dlm_i : signal is true;\r
- attribute syn_preserve of txdn_dlm_i : signal is true;\r
- attribute syn_keep of txdn_dlm_i : signal is true;\r
- attribute syn_preserve of rxdn_dlm_i : signal is true;\r
- attribute syn_keep of rxdn_dlm_i : signal is true;\r
-\r
- \r
-begin\r
----------------------------------------------------------------------------\r
--- Reset Generation\r
----------------------------------------------------------------------------\r
-\r
-\r
- TEST_LINE <= (others => '0'); -- otherwise it is floating\r
--- LED_RX <= (others => '0'); -- otherwise it is floating\r
--- LED_TX <= (others => '0'); -- otherwise it is floating\r
--- LED_LINKOK <= (others => '0'); -- otherwise it is floating\r
- \r
- GSR_N <= pll_lock;\r
-\r
-\r
- THE_RESET_HANDLER : trb_net_reset_handler\r
- generic map(\r
- RESET_DELAY => x"FEEE"\r
- )\r
- port map(\r
- CLEAR_IN => '0', -- reset input (high active, async)\r
- CLEAR_N_IN => '1', -- reset input (low active, async)\r
- CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!\r
- SYSCLK_IN => rxup_half_clk, --clk_100_osc, -- PLL/DLL remastered clock\r
- PLL_LOCKED_IN => GSR_N, --pll_lock, -- master PLL lock signal (async) !PL 14082014\r
- RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel\r
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)\r
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!\r
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)\r
- DEBUG_OUT => open\r
- ); \r
-\r
--- process(clk_100_osc) \r
--- begin\r
--- if rising_edge(clk_100_osc) then\r
--- general_reset_i <= not SFP_LOS(1);\r
--- end if;\r
--- end process;\r
- \r
----------------------------------------------------------------------------\r
--- Clock Handling\r
----------------------------------------------------------------------------\r
---gen_200_PLL : if USE_125_MHZ = c_NO generate\r
- THE_MAIN_PLL : pll_in200_out100\r
- port map(\r
- CLK => CLK_GPLL_RIGHT,\r
- RESET => '0',\r
- CLKOP => clk_100_osc,\r
- CLKOK => clk_200_osc,\r
- LOCK => pll_lock\r
- );\r
---end generate; \r
-\r
---gen_125 : if USE_125_MHZ = c_YES generate\r
--- clk_100_osc <= CLK_GPLL_LEFT;\r
--- clk_raw_internal <= CLK_GPLL_LEFT;\r
---end generate; \r
-\r
---gen_sync_clocks : if SYNC_MODE = c_YES generate\r
--- clk_soda_i <= rxup_full_clk;\r
---end generate;\r
-\r
---gen_local_clocks : if SYNC_MODE = c_NO generate\r
--- clk_soda_i <= clk_raw_internal;\r
---end generate;\r
-\r
-\r
----------------------------------------------------------------------------\r
--- Bus Handler\r
----------------------------------------------------------------------------\r
- THE_BUS_HANDLER : trb_net16_regio_bus_handler\r
- generic map(\r
- PORT_NUMBER => 4,\r
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),\r
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)\r
- )\r
- port map(\r
- CLK => rxup_half_clk, --clk_100_osc, --clk_sys_i,\r
- RESET => reset_i,\r
-\r
- DAT_ADDR_IN => regio_addr_out,\r
- DAT_DATA_IN => regio_data_out,\r
- DAT_DATA_OUT => regio_data_in,\r
- DAT_READ_ENABLE_IN => regio_read_enable_out,\r
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,\r
- DAT_TIMEOUT_IN => regio_timeout_out,\r
- DAT_DATAREADY_OUT => regio_dataready_in,\r
- DAT_WRITE_ACK_OUT => regio_write_ack_in,\r
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,\r
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,\r
-\r
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,\r
- BUS_READ_ENABLE_OUT(1) => sci1_read,\r
- BUS_READ_ENABLE_OUT(2) => sci2_read,\r
- BUS_READ_ENABLE_OUT(3) => soda_read,\r
-\r
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,\r
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,\r
- BUS_WRITE_ENABLE_OUT(2) => sci2_write,\r
- BUS_WRITE_ENABLE_OUT(3) => soda_write,\r
-\r
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,\r
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,\r
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,\r
- BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,\r
- BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,\r
- BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,\r
- \r
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,\r
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,\r
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,\r
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,\r
- BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,\r
- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,\r
- BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,\r
- BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,\r
- \r
- BUS_TIMEOUT_OUT(0) => open,\r
- BUS_TIMEOUT_OUT(1) => open,\r
- BUS_TIMEOUT_OUT(2) => open,\r
- BUS_TIMEOUT_OUT(3) => open,\r
-\r
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,\r
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,\r
- BUS_DATA_IN(1*32+31 downto 1*32+8) => (others => '0'),\r
- BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,\r
- BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'),\r
- BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,\r
-\r
- BUS_DATAREADY_IN(0) => spimem_dataready_out,\r
- BUS_DATAREADY_IN(1) => sci1_ack,\r
- BUS_DATAREADY_IN(2) => sci2_ack,\r
- BUS_DATAREADY_IN(3) => soda_ack,\r
-\r
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,\r
- BUS_WRITE_ACK_IN(1) => sci1_ack,\r
- BUS_WRITE_ACK_IN(2) => sci2_ack,\r
- BUS_WRITE_ACK_IN(3) => soda_ack,\r
-\r
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,\r
- BUS_NO_MORE_DATA_IN(1) => '0',\r
- BUS_NO_MORE_DATA_IN(2) => '0',\r
- BUS_NO_MORE_DATA_IN(3) => '0',\r
- \r
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,\r
- BUS_UNKNOWN_ADDR_IN(1) => '0',\r
- BUS_UNKNOWN_ADDR_IN(2) => sci2_nack,\r
- BUS_UNKNOWN_ADDR_IN(3) => '0',\r
-\r
- STAT_DEBUG => open\r
- );\r
-\r
----------------------------------------------------------------------------\r
--- SPI / Flash\r
----------------------------------------------------------------------------\r
-\r
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch\r
- port map(\r
- CLK_IN => rxup_half_clk, --clk_100_osc,\r
- RESET_IN => reset_i,\r
- \r
- BUS_ADDR_IN => spimem_addr,\r
- BUS_READ_IN => spimem_read_en,\r
- BUS_WRITE_IN => spimem_write_en,\r
- BUS_DATAREADY_OUT => spimem_dataready_out,\r
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,\r
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,\r
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,\r
- BUS_DATA_IN => spimem_data_in,\r
- BUS_DATA_OUT => spimem_data_out,\r
- \r
- DO_REBOOT_IN => common_ctrl_reg(15), \r
- PROGRAMN => PROGRAMN,\r
- \r
- SPI_CS_OUT => FLASH_CS,\r
- SPI_SCK_OUT => FLASH_CLK,\r
- SPI_SDO_OUT => FLASH_DIN,\r
- SPI_SDI_IN => FLASH_DOUT\r
- );\r
-\r
- \r
-\r
----------------------------------------------------------------------------\r
--- The synchronous interface for Soda tests\r
---------------------------------------------------------------------------- \r
-\r
-THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up\r
- generic map(\r
- SERDES_NUM => 0, --number of serdes in quad\r
- IS_SYNC_SLAVE => c_YES\r
- )\r
- port map(\r
- OSCCLK => clk_200_osc,\r
- SYSCLK => rxup_half_clk, --clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_sync_down.vhd\r
- RESET => reset_i,\r
- CLEAR => clear_i,\r
- --Internal Connection for TrbNet data -> not used a.t.m.\r
- MED_DATA_IN => med_data_out(15 downto 0),\r
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),\r
- MED_DATAREADY_IN => med_dataready_out(0),\r
- MED_READ_OUT => med_read_in(0),\r
- MED_DATA_OUT => med_data_in(15 downto 0),\r
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),\r
- MED_DATAREADY_OUT => med_dataready_in(0),\r
- MED_READ_IN => med_read_out(0),\r
- RX_HALF_CLK_OUT => rxup_half_clk,\r
- RX_FULL_CLK_OUT => rxup_full_clk,\r
- TX_HALF_CLK_OUT => txup_half_clk,\r
- TX_FULL_CLK_OUT => txup_full_clk,\r
- RX_CDR_LOL_OUT => rx_cdr_lol_S, -- !PL 14082014 \r
-\r
- RX_DLM => rxup_dlm_i,\r
- RX_DLM_WORD => rxup_dlm_word,\r
- TX_DLM => txup_dlm_i,\r
- TX_DLM_WORD => txup_dlm_word,\r
- TX_DLM_PREVIEW_IN => txup_dlm_preview_S, --PL!\r
- LINK_PHASE_OUT => uplink_phase_S, --PL!\r
- LINK_READY_OUT => uplink_ready_S, --PL!\r
- --SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting\r
- SD_RXD_P_IN => SERDES_ADDON_RX(4),\r
- SD_RXD_N_IN => SERDES_ADDON_RX(5),\r
- SD_TXD_P_OUT => SERDES_ADDON_TX(4),\r
- SD_TXD_N_OUT => SERDES_ADDON_TX(5),\r
- SD_REFCLK_P_IN => '0',\r
- SD_REFCLK_N_IN => '0',\r
- SD_PRSNT_N_IN => SFP_MOD0(3), -- = A3, was 1 = B0\r
- SD_LOS_IN => SFP_LOS(3),\r
- SD_TXDIS_OUT => sfp_txdis_S(3), --SFP_TXDIS(3), this signal is now used to release downlinks\r
-\r
- SCI_DATA_IN => sci1_data_in,\r
- SCI_DATA_OUT => sci1_data_out,\r
- SCI_ADDR => sci1_addr,\r
- SCI_READ => sci1_read,\r
- SCI_WRITE => sci1_write,\r
- SCI_ACK => sci1_ack, \r
- SCI_NACK => sci1_nack,\r
- -- Status and control port\r
- STAT_OP => med_stat_op(15 downto 0),\r
- CTRL_OP => med_ctrl_op(15 downto 0),\r
- STAT_DEBUG => open,\r
- CTRL_DEBUG => (others => '0')\r
- ); \r
-\r
- SFP_TXDIS <= sfp_txdis_S;\r
- \r
----------------------------------------------------------------------------\r
--- The Soda Central \r
---------------------------------------------------------------------------- \r
-\r
- A_SODA_HUB : soda_hub\r
- port map(\r
- SYSCLK => rxup_half_clk,\r
- SODACLK => rxup_full_clk,\r
- RESET => reset_i,\r
- CLEAR => clear_i,\r
- CLK_EN => '1',\r
-\r
- -- SINGLE DUBPLEX UP-LINK TO THE TOP\r
- RXUP_DLM_WORD_IN => rxup_dlm_word,\r
- RXUP_DLM_IN => rxup_dlm_i,\r
- TXUP_DLM_OUT => txup_dlm_i, \r
- TXUP_DLM_WORD_OUT => txup_dlm_word,\r
- TXUP_DLM_PREVIEW_OUT => txup_dlm_preview_S,\r
- UPLINK_PHASE_IN => uplink_phase_S,\r
- -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM\r
- RXDN_DLM_WORD_IN => rxdn_dlm_word,\r
- RXDN_DLM_IN => rxdn_dlm_i,\r
- TXDN_DLM_OUT => txdn_dlm_i, \r
- TXDN_DLM_WORD_OUT => txdn_dlm_word,\r
- TXDN_DLM_PREVIEW_OUT => txdn_dlm_preview_S,\r
- DNLINK_PHASE_IN => dnlink_phase_S, \r
-\r
- SODA_DATA_IN => soda_data_in,\r
- SODA_DATA_OUT => soda_data_out,\r
- SODA_ADDR_IN => soda_addr,\r
- SODA_READ_IN => soda_read,\r
- SODA_WRITE_IN => soda_write,\r
- SODA_ACK_OUT => soda_ack,\r
- LEDS_OUT => soda_leds,\r
- LINK_DEBUG_IN => link_debug_in_S\r
- );\r
-\r
-\r
- downlink_reset <= '1' when (reset_i = '1' or uplink_ready_S = '0') else '0';\r
- downlink_clear <= '1' when (clear_i = '1' or uplink_ready_S = '0') else '0';\r
-\r
- \r
- THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down\r
- generic map(\r
- SERDES_NUM => 0, --number of serdes in quad\r
- IS_SYNC_SLAVE => c_NO\r
- )\r
- port map(\r
- OSC_CLK => clk_200_osc,\r
- TX_DATACLK => rxup_full_clk,\r
- SYSCLK => rxup_half_clk, --clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd\r
- RESET => downlink_reset,\r
- CLEAR => downlink_clear,\r
- ---------------------------------------------------------------------------------------------------------------------------------------------------------\r
- LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.\r
- ---------------------------------------------------------------------------------------------------------------------------------------------------------\r
--- MED_DATA_IN(0*16+15 downto 0*16) => med_data_out(1*16+15 downto 1*16),\r
- MED_DATA_IN(0) => med_data_out(1*16+15 downto 1*16),\r
- MED_DATA_IN(1) => med_data_out(6*16+15 downto 6*16),\r
- MED_DATA_IN(2) => med_data_out(4*16+15 downto 4*16),\r
- MED_DATA_IN(3) => med_data_out(2*16+15 downto 2*16),\r
-\r
--- MED_PACKET_NUM_IN(0*3+2 downto 0*3) => med_packet_num_out(1*3+2 downto 1*3),\r
- MED_PACKET_NUM_IN(0) => med_packet_num_out(1*3+2 downto 1*3),\r
- MED_PACKET_NUM_IN(1) => med_packet_num_out(6*3+2 downto 6*3),\r
- MED_PACKET_NUM_IN(2) => med_packet_num_out(2*3+2 downto 2*3),\r
- MED_PACKET_NUM_IN(3) => med_packet_num_out(4*3+2 downto 4*3),\r
-\r
- MED_DATAREADY_IN(0) => med_dataready_out(1),\r
- MED_DATAREADY_IN(1) => med_dataready_out(6),\r
- MED_DATAREADY_IN(2) => med_dataready_out(2),\r
- MED_DATAREADY_IN(3) => med_dataready_out(4),\r
-\r
- MED_READ_OUT(0) => med_read_in(1),\r
- MED_READ_OUT(1) => med_read_in(6),\r
- MED_READ_OUT(2) => med_read_in(2),\r
- MED_READ_OUT(3) => med_read_in(4),\r
-\r
--- MED_DATA_OUT(0*16+15 downto 0*16) => med_data_in(1*16+15 downto 1*16),\r
- MED_DATA_OUT(0) => med_data_in(1*16+15 downto 1*16),\r
- MED_DATA_OUT(1) => med_data_in(6*16+15 downto 6*16),\r
- MED_DATA_OUT(2) => med_data_in(2*16+15 downto 2*16),\r
- MED_DATA_OUT(3) => med_data_in(4*16+15 downto 4*16),\r
-\r
--- MED_PACKET_NUM_OUT(0*3+2 downto 0*3) => med_packet_num_in(1*3+2 downto 1*3),\r
- MED_PACKET_NUM_OUT(0) => med_packet_num_in(1*3+2 downto 1*3),\r
- MED_PACKET_NUM_OUT(1) => med_packet_num_in(6*3+2 downto 6*3),\r
- MED_PACKET_NUM_OUT(2) => med_packet_num_in(2*3+2 downto 2*3),\r
- MED_PACKET_NUM_OUT(3) => med_packet_num_in(4*3+2 downto 4*3),\r
-\r
- MED_DATAREADY_OUT(0) => med_dataready_in(1),\r
- MED_DATAREADY_OUT(1) => med_dataready_in(6),\r
- MED_DATAREADY_OUT(2) => med_dataready_in(2),\r
- MED_DATAREADY_OUT(3) => med_dataready_in(4),\r
-\r
- MED_READ_IN(0) => med_read_out(1),\r
- MED_READ_IN(1) => med_read_out(6),\r
- MED_READ_IN(2) => med_read_out(2),\r
- MED_READ_IN(3) => med_read_out(4),\r
-\r
- RX_HALF_CLK_OUT(0) => rxdn_half_clk(0),\r
- RX_HALF_CLK_OUT(1) => rxdn_half_clk(1),\r
- RX_HALF_CLK_OUT(2) => rxdn_half_clk(2),\r
- RX_HALF_CLK_OUT(3) => rxdn_half_clk(3),\r
-\r
- RX_FULL_CLK_OUT(0) => rxdn_full_clk(0), -- needed for sync replies i.e. calibration\r
- RX_FULL_CLK_OUT(1) => rxdn_full_clk(1), -- needed for sync replies i.e. calibration\r
- RX_FULL_CLK_OUT(2) => rxdn_full_clk(2), -- needed for sync replies i.e. calibration\r
- RX_FULL_CLK_OUT(3) => rxdn_full_clk(3), -- needed for sync replies i.e. calibration\r
-\r
- TX_HALF_CLK_OUT(0) => txdn_half_clk(0),\r
- TX_HALF_CLK_OUT(1) => txdn_half_clk(1),\r
- TX_HALF_CLK_OUT(2) => txdn_half_clk(2),\r
- TX_HALF_CLK_OUT(3) => txdn_half_clk(3),\r
-\r
- TX_FULL_CLK_OUT(0) => txdn_full_clk(0),\r
- TX_FULL_CLK_OUT(1) => txdn_full_clk(1),\r
- TX_FULL_CLK_OUT(2) => txdn_full_clk(2),\r
- TX_FULL_CLK_OUT(3) => txdn_full_clk(3),\r
-\r
- RX_DLM(0) => rxdn_dlm_i(0),\r
- RX_DLM(1) => rxdn_dlm_i(1),\r
- RX_DLM(2) => rxdn_dlm_i(2),\r
- RX_DLM(3) => rxdn_dlm_i(3),\r
- \r
- RX_DLM_WORD(0) => rxdn_dlm_word(0),\r
- RX_DLM_WORD(1) => rxdn_dlm_word(1),\r
- RX_DLM_WORD(2) => rxdn_dlm_word(2),\r
- RX_DLM_WORD(3) => rxdn_dlm_word(3),\r
- \r
- TX_DLM(0) => txdn_dlm_i(0),\r
- TX_DLM(1) => txdn_dlm_i(1),\r
- TX_DLM(2) => txdn_dlm_i(2),\r
- TX_DLM(3) => txdn_dlm_i(3),\r
- \r
- TX_DLM_WORD(0) => txdn_dlm_word(0),\r
- TX_DLM_WORD(1) => txdn_dlm_word(1),\r
- TX_DLM_WORD(2) => txdn_dlm_word(2),\r
- TX_DLM_WORD(3) => txdn_dlm_word(3),\r
-\r
- TX_DLM_PREVIEW_IN(0) => txdn_dlm_preview_S(0), --PL!\r
- TX_DLM_PREVIEW_IN(1) => txdn_dlm_preview_S(1), --PL!\r
- TX_DLM_PREVIEW_IN(2) => txdn_dlm_preview_S(2), --PL!\r
- TX_DLM_PREVIEW_IN(3) => txdn_dlm_preview_S(3), --PL!\r
-\r
- LINK_PHASE_OUT(0) => dnlink_phase_S(0), --PL!\r
- LINK_PHASE_OUT(1) => dnlink_phase_S(1), --PL!\r
- LINK_PHASE_OUT(2) => dnlink_phase_S(2), --PL!\r
- LINK_PHASE_OUT(3) => dnlink_phase_S(3), --PL!\r
-\r
- --SFP Connection\r
- SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0\r
- SD_RXD_P_IN(1) => SERDES_ADDON_RX(1),\r
- SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1\r
- SD_RXD_P_IN(3) => SERDES_ADDON_RX(11), \r
- SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2\r
- SD_RXD_N_IN(1) => SERDES_ADDON_RX(3),\r
- SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3\r
- SD_RXD_N_IN(3) => SERDES_ADDON_RX(7),\r
- SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0\r
- SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1),\r
- SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1\r
- SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11),\r
- SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2\r
- SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3),\r
- SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3\r
- SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7),\r
- SD_REFCLK_P_IN => (others => '0'),\r
- SD_REFCLK_N_IN => ('0','0','0','0'),\r
- SD_PRSNT_N_IN(0) => SFP_MOD0(1),\r
- SD_PRSNT_N_IN(1) => SFP_MOD0(6),\r
- SD_PRSNT_N_IN(2) => SFP_MOD0(2),\r
- SD_PRSNT_N_IN(3) => SFP_MOD0(4),\r
- SD_LOS_IN(0) => SFP_LOS(1),\r
- SD_LOS_IN(1) => SFP_LOS(6),\r
- SD_LOS_IN(2) => SFP_LOS(2),\r
- SD_LOS_IN(3) => SFP_LOS(4),\r
- SD_TXDIS_OUT(0) => sfp_txdis_S(1),\r
- SD_TXDIS_OUT(1) => sfp_txdis_S(6),\r
- SD_TXDIS_OUT(2) => sfp_txdis_S(2),\r
- SD_TXDIS_OUT(3) => sfp_txdis_S(4),\r
-\r
- SCI_DATA_IN => sci2_data_in,\r
- SCI_DATA_OUT => sci2_data_out,\r
- SCI_ADDR => sci2_addr,\r
- SCI_READ => sci2_read,\r
- SCI_WRITE => sci2_write,\r
- SCI_ACK => sci2_ack, \r
- SCI_NACK => sci2_nack,\r
-\r
- --Status and control port\r
- STAT_OP(15 downto 0) => med_stat_op(1*16+15 downto 1*16),\r
- STAT_OP(31 downto 16) => med_stat_op(6*16+15 downto 6*16),\r
- STAT_OP(47 downto 32) => med_stat_op(2*16+15 downto 2*16),\r
- STAT_OP(63 downto 48) => med_stat_op(4*16+15 downto 4*16),\r
-\r
- CTRL_OP(15 downto 0) => med_ctrl_op(1*16+15 downto 1*16),\r
- CTRL_OP(31 downto 16) => med_ctrl_op(6*16+15 downto 6*16),\r
- CTRL_OP(47 downto 32) => med_ctrl_op(2*16+15 downto 2*16),\r
- CTRL_OP(63 downto 48) => med_ctrl_op(4*16+15 downto 4*16),\r
-\r
- STAT_DEBUG => open,\r
- CTRL_DEBUG => (others => '0')\r
- );\r
-\r
-\r
----------------------------------------------------------------------------\r
--- TRB-Hub\r
----------------------------------------------------------------------------\r
- med_stat_op(3*16+15 downto 3*16) <= x"0007"; -- !PL telling the hub that this port is inactive 08192014\r
- med_stat_op(5*16+15 downto 5*16) <= x"0007"; -- !PL telling the hub that this port is inactive 08192014\r
-\r
- TRB_HUB : trb_net16_hub_base\r
- generic map (\r
- HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),\r
- IBUF_SECURE_MODE => c_YES,\r
- MII_NUMBER => 7,\r
- MII_IS_UPLINK => (0 => 1, others => 0),\r
- MII_IS_DOWNLINK => (0 => 0, others => 1),\r
- MII_IS_UPLINK_ONLY => (0 => 1, others => 0),\r
- INT_NUMBER => 0,\r
- -- INT_CHANNELS => (0,1,3,3,3,3,3,3),\r
- USE_ONEWIRE => c_YES,\r
- COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),\r
- HARDWARE_VERSION => x"91003200",\r
- INIT_ENDPOINT_ID => x"0000",\r
- INIT_ADDRESS => x"F357",\r
- USE_VAR_ENDPOINT_ID => c_YES,\r
- BROADCAST_SPECIAL_ADDR => x"45",\r
- CLOCK_FREQUENCY => CLOCK_FREQUENCY\r
- )\r
- port map (\r
- CLK => rxup_half_clk, --clk_100_osc,\r
- RESET => reset_i,\r
- CLK_EN => '1',\r
-\r
- --Media interfacces\r
- MED_DATAREADY_OUT(7*1-1 downto 0) => med_dataready_out,\r
- MED_DATA_OUT(7*16-1 downto 0) => med_data_out,\r
- MED_PACKET_NUM_OUT(7*3-1 downto 0) => med_packet_num_out,\r
- MED_READ_IN(7*1-1 downto 0) => med_read_in,\r
- MED_DATAREADY_IN(7*1-1 downto 0) => med_dataready_in,\r
- MED_DATA_IN(7*16-1 downto 0) => med_data_in,\r
- MED_PACKET_NUM_IN(7*3-1 downto 0) => med_packet_num_in,\r
- MED_READ_OUT(7*1-1 downto 0) => med_read_out,\r
- MED_STAT_OP(7*16-1 downto 0) => med_stat_op,\r
- MED_CTRL_OP(7*16-1 downto 0) => med_ctrl_op,\r
-\r
- COMMON_STAT_REGS => common_stat_reg,\r
- COMMON_CTRL_REGS => common_ctrl_reg,\r
- MY_ADDRESS_OUT => my_address,\r
- --REGIO INTERFACE\r
- REGIO_ADDR_OUT => regio_addr_out,\r
- REGIO_READ_ENABLE_OUT => regio_read_enable_out,\r
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,\r
- REGIO_DATA_OUT => regio_data_out,\r
- REGIO_DATA_IN => regio_data_in,\r
- REGIO_DATAREADY_IN => regio_dataready_in,\r
- REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,\r
- REGIO_WRITE_ACK_IN => regio_write_ack_in,\r
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,\r
- REGIO_TIMEOUT_OUT => regio_timeout_out,\r
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,\r
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),\r
- ONEWIRE => TEMPSENS,\r
- ONEWIRE_MONITOR_OUT => open,\r
- --Status ports (for debugging)\r
- MPLEX_CTRL => (others => '0'),\r
- CTRL_DEBUG => (others => '0'),\r
- STAT_DEBUG => open\r
- );\r
-\r
----------------------------------------------------------------------------\r
--- LED\r
----------------------------------------------------------------------------\r
--- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);\r
--- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);\r
--- LED_GREEN <= med_stat_op(12); --tx_pll_lol\r
--- LED_RED <= med_stat_op(11); --rx_cdr_lol\r
- LED_ORANGE <= SFP_LOS(1); --'1' when (time_counter(26)='0') else '0';
- LED_YELLOW <= SFP_LOS(2); --'1' when (time_counter(26)='0') else '0';
- LED_GREEN <= SFP_LOS(3); --time_counter(26);
- LED_RED <= SFP_LOS(4); --time_counter(26);
- \r
----------------------------------------------------------------------------
--- GREEN LED under sfp
----------------------------------------------------------------------------
- LED_LINKOK(1) <= SFP_LOS(1);
- LED_LINKOK(2) <= SFP_LOS(2);
- LED_LINKOK(3) <= SFP_LOS(3);
- LED_LINKOK(4) <= SFP_LOS(4);
- LED_LINKOK(5) <= SFP_LOS(5);
- LED_LINKOK(6) <= SFP_LOS(6);
-
- LED_RX(1) <= '1' when (med_stat_op(10)='0') else '0'; -- rx_allow
- LED_RX(2) <= '1';
- LED_RX(3) <= '1';
- LED_RX(4) <= '1';
- LED_RX(5) <= '1';
- LED_RX(6) <= '1';
-
- LED_TX(1) <= '1' when (med_stat_op(9)='0') else '0'; -- tx_allow
- LED_TX(2) <= '1';
- LED_TX(3) <= '1';
- LED_TX(4) <= '1';
- LED_TX(5) <= '1';
- LED_TX(6) <= '1';
-\r
----------------------------------------------------------------------------\r
--- DEBUG\r
---------------------------------------------------------------------------- \r
- link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0);\r
- link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0');\r
----------------------------------------------------------------------------\r
--- Test Circuits\r
----------------------------------------------------------------------------\r
-\r
-\r
- blink : process (clk_200_osc)
- begin
- if rising_edge(clk_200_osc) then
- if (time_counter = x"FFFFFFFF") then
- time_counter <= x"00000000";
- else
- time_counter <= time_counter + 1;
- end if;
- end if;
- end process;\r
-\r
-\r
-end trb3_periph_sodahub_arch;
\ No newline at end of file
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodasource is
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_INTERFACES : integer := 2
- );
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
- --serdes I/O - connect as you like, no real use
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
-
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
-
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
-
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of LED_LINKOK : signal is false;
- attribute syn_useioff of LED_TX : signal is false;
- attribute syn_useioff of LED_RX : signal is false;
- attribute syn_useioff of SFP_MOD0 : signal is false;
- attribute syn_useioff of SFP_TXDIS : signal is false;
- attribute syn_useioff of SFP_LOS : signal is false;
- attribute syn_useioff of TEST_LINE : signal is false;
-
- --important signals _with_ IO-FF
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-
- --Clock / Reset
- -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- signal clk_100_osc : std_logic;
- signal clk_200_osc : std_logic;
--- signal rx_clock_half : std_logic;
--- signal rx_clock_full : std_logic;
--- signal clk_tdc : std_logic;
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sci2_ack : std_logic;
- signal sci2_nack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
-
- --SODA
- signal soda_ack : std_logic;
- signal soda_write : std_logic;
- signal soda_read : std_logic;
- signal soda_data_in : std_logic_vector(31 downto 0);
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0);
- signal soda_leds : std_logic_vector(3 downto 0);
-
-
- --TDC
- signal hit_in_i : std_logic_vector(63 downto 0);
-
- signal soda_rx_clock_half : std_logic;
- signal soda_rx_clock_full : std_logic;
- signal soda_tx_clock_half : std_logic;
- signal soda_tx_clock_full : std_logic;
- signal tx_dlm_i : std_logic;
- signal rx_dlm_i : std_logic;
- signal tx_dlm_word : std_logic_vector(7 downto 0);
- signal rx_dlm_word : std_logic_vector(7 downto 0);
- signal tx_dlm_preview_S : std_logic; --PL!
- signal link_phase_S : std_logic; --PL!
-
- --SODA
- signal SOB_S : std_logic := '0';
- signal soda_40mhz_cycle_S : std_logic := '0';
- -- fix signal names for constraining
- attribute syn_preserve of soda_rx_clock_full : signal is true;
- attribute syn_keep of soda_rx_clock_full : signal is true;
- attribute syn_preserve of soda_rx_clock_half : signal is true;
- attribute syn_keep of soda_rx_clock_half : signal is true;
- attribute syn_preserve of soda_tx_clock_full : signal is true;
- attribute syn_keep of soda_tx_clock_full : signal is true;
- attribute syn_preserve of soda_tx_clock_half : signal is true;
- attribute syn_keep of soda_tx_clock_half : signal is true;
- attribute syn_preserve of clk_100_osc : signal is true;
- attribute syn_keep of clk_100_osc : signal is true;
- attribute syn_preserve of clk_200_osc : signal is true;
- attribute syn_keep of clk_200_osc : signal is true;
- attribute syn_preserve of tx_dlm_i : signal is true;
- attribute syn_keep of tx_dlm_i : signal is true;
- attribute syn_preserve of rx_dlm_i : signal is true;
- attribute syn_keep of rx_dlm_i : signal is true;
- attribute syn_preserve of soda_40mhz_cycle_S : signal is true;
- attribute syn_keep of soda_40mhz_cycle_S : signal is true;
-
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- RESET => '0',\r
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc,
- LOCK => pll_lock
- );
-end generate;
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
- USE_125_MHZ => USE_125_MHZ,
- USE_CTC => c_NO,
- USE_SLAVE => SYNC_MODE
- )
- port map(
- CLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- REFCLK2CORE_OUT => open,
- CLK_RX_HALF_OUT => open, --rx_clock_half,
- CLK_RX_FULL_OUT => open, --rx_clock_full,
-
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(2),
- SD_RXD_N_IN => SERDES_ADDON_RX(3),
- SD_TXD_P_OUT => SERDES_ADDON_TX(2),
- SD_TXD_N_OUT => SERDES_ADDON_TX(3),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => FPGA5_COMM(0),
- SD_LOS_IN => FPGA5_COMM(0),
- SD_TXDIS_OUT => FPGA5_COMM(2),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),\r
- CTRL_DEBUG => (others => '0')
- );
-
-
----------------------------------------------------------------------------
--- Hub
----------------------------------------------------------------------------
-
-THE_HUB : trb_net16_hub_base
- generic map (
- HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),
- IBUF_SECURE_MODE => c_YES,
- MII_NUMBER => NUM_INTERFACES,
- MII_IS_UPLINK => (0 => 1, others => 0),
- MII_IS_DOWNLINK => (0 => 0, others => 1),
- MII_IS_UPLINK_ONLY=> (0 => 1, others => 0),
- INT_NUMBER => 0,
- USE_ONEWIRE => c_YES,
- COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
--- COMPILE_TIME => VERSION_NUMBER_TIME,
- HARDWARE_VERSION => x"91003200",
- INIT_ENDPOINT_ID => x"0000",
- INIT_ADDRESS => x"F355",
- USE_VAR_ENDPOINT_ID => c_YES,
- BROADCAST_SPECIAL_ADDR => x"45",
- CLOCK_FREQUENCY => CLOCK_FREQUENCY
- )
- port map (
- CLK => clk_100_osc, --clk_sys_i, PL! 30062014
- RESET => reset_i,
- CLK_EN => '1',
-
- --Media interfacces
- MED_DATAREADY_OUT(NUM_INTERFACES*1-1 downto 0) => med_dataready_out,
- MED_DATA_OUT(NUM_INTERFACES*16-1 downto 0) => med_data_out,
- MED_PACKET_NUM_OUT(NUM_INTERFACES*3-1 downto 0) => med_packet_num_out,
- MED_READ_IN(NUM_INTERFACES*1-1 downto 0) => med_read_in,
- MED_DATAREADY_IN(NUM_INTERFACES*1-1 downto 0) => med_dataready_in,
- MED_DATA_IN(NUM_INTERFACES*16-1 downto 0) => med_data_in,
- MED_PACKET_NUM_IN(NUM_INTERFACES*3-1 downto 0) => med_packet_num_in,
- MED_READ_OUT(NUM_INTERFACES*1-1 downto 0) => med_read_out,
- MED_STAT_OP(NUM_INTERFACES*16-1 downto 0) => med_stat_op,
- MED_CTRL_OP(NUM_INTERFACES*16-1 downto 0) => med_ctrl_op,
-
- COMMON_STAT_REGS => common_stat_reg,
- COMMON_CTRL_REGS => common_ctrl_reg,
- MY_ADDRESS_OUT => open,
- --REGIO INTERFACE
- REGIO_ADDR_OUT => regio_addr_out,
- REGIO_READ_ENABLE_OUT => regio_read_enable_out,
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
- REGIO_DATA_OUT => regio_data_out,
- REGIO_DATA_IN => regio_data_in,
- REGIO_DATAREADY_IN => regio_dataready_in,
- REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
- REGIO_WRITE_ACK_IN => regio_write_ack_in,
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- REGIO_TIMEOUT_OUT => regio_timeout_out,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
- ONEWIRE => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
- --Status ports (for debugging)
- MPLEX_CTRL => (others => '0'),
- CTRL_DEBUG => (others => '0'),
- STAT_DEBUG => open
- );
-
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
- )
- port map(
- CLK => clk_100_osc,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_READ_ENABLE_OUT(2) => sci2_read,
- BUS_READ_ENABLE_OUT(3) => soda_read,
-
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_WRITE_ENABLE_OUT(2) => sci2_write,
- BUS_WRITE_ENABLE_OUT(3) => soda_write,
-
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
- BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
- BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
-
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
- BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
-
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_TIMEOUT_OUT(3) => open,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32+8) => (others => '0'),
- BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
- BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'),
- BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
-
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_DATAREADY_IN(2) => sci2_ack,
- BUS_DATAREADY_IN(3) => soda_ack,
-
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => sci2_ack,
- BUS_WRITE_ACK_IN(3) => soda_ack,
-
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(3) => '0',
-
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => sci2_nack,
- BUS_UNKNOWN_ADDR_IN(3) => '0',
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
- port map(
- CLK_IN => clk_100_osc,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
-
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------
-
-THE_SYNC_LINK : med_ecp3_sfp_sync_down
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_NO
- )
- port map(
- OSCCLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => med_data_out(31 downto 16),
- MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),
- MED_DATAREADY_IN => med_dataready_out(1),
- MED_READ_OUT => med_read_in(1),
- MED_DATA_OUT => med_data_in(31 downto 16),
- MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
- MED_DATAREADY_OUT => med_dataready_in(1),
- MED_READ_IN => med_read_out(1),
- RX_HALF_CLK_OUT => soda_rx_clock_half,
- RX_FULL_CLK_OUT => soda_rx_clock_full,
- TX_HALF_CLK_OUT => soda_tx_clock_half,
- TX_FULL_CLK_OUT => soda_tx_clock_full,
-
- RX_DLM => rx_dlm_i,
- RX_DLM_WORD => rx_dlm_word,
- TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,
- TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
- LINK_PHASE_OUT => link_phase_S, --PL!
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(0),
- SD_RXD_N_IN => SERDES_ADDON_RX(1),
- SD_TXD_P_OUT => SERDES_ADDON_TX(0),
- SD_TXD_N_OUT => SERDES_ADDON_TX(1),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),
-
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
- SCI_NACK => sci2_nack,
- -- Status and control port
- STAT_OP => med_stat_op(31 downto 16),
- CTRL_OP => med_ctrl_op(31 downto 16),
- STAT_DEBUG => med_stat_debug(63 downto 0),\r
- CTRL_DEBUG => (others => '0')
- );
-\r
--- THE_SYNC_LINK : med_ecp3_sfp_sync\r
--- generic map(\r
--- SERDES_NUM => 0, --number of serdes in quad\r
--- IS_SYNC_SLAVE => c_NO\r
--- )\r
--- port map(\r
--- CLK => clk_200_osc,\r
--- SYSCLK => clk_100_osc,\r
--- RESET => reset_i,\r
--- CLEAR => clear_i,\r
--- --Internal Connection for TrbNet data -> not used a.t.m.\r
--- MED_DATA_IN => med_data_out(31 downto 16),\r
--- MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),\r
--- MED_DATAREADY_IN => med_dataready_out(1),\r
--- MED_READ_OUT => med_read_in(1),\r
--- MED_DATA_OUT => med_data_in(31 downto 16),\r
--- MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),\r
--- MED_DATAREADY_OUT => med_dataready_in(1),\r
--- MED_READ_IN => med_read_out(1),\r
--- CLK_RX_HALF_OUT => soda_rx_clock_half,\r
--- CLK_RX_FULL_OUT => soda_rx_clock_full,\r
--- -- TX_HALF_CLK_OUT => soda_tx_clock_half,\r
--- -- TX_FULL_CLK_OUT => soda_tx_clock_full,\r
--- \r
--- RX_DLM => rx_dlm_i,\r
--- RX_DLM_WORD => rx_dlm_word,\r
--- TX_DLM => tx_dlm_i,\r
--- TX_DLM_WORD => tx_dlm_word,\r
--- -- TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!\r
--- -- LINK_PHASE_OUT => link_phase_S, --PL!\r
--- --SFP Connection\r
--- SD_RXD_P_IN => SERDES_ADDON_RX(0),\r
--- SD_RXD_N_IN => SERDES_ADDON_RX(1),\r
--- SD_TXD_P_OUT => SERDES_ADDON_TX(0),\r
--- SD_TXD_N_OUT => SERDES_ADDON_TX(1),\r
--- SD_REFCLK_P_IN => '0',\r
--- SD_REFCLK_N_IN => '0',\r
--- SD_PRSNT_N_IN => SFP_MOD0(1),\r
--- SD_LOS_IN => SFP_LOS(1),\r
--- SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),\r
--- \r
--- SCI_DATA_IN => sci2_data_in,\r
--- SCI_DATA_OUT => sci2_data_out,\r
--- SCI_ADDR => sci2_addr,\r
--- SCI_READ => sci2_read,\r
--- SCI_WRITE => sci2_write,\r
--- SCI_ACK => sci2_ack, \r
--- SCI_NACK => sci2_nack,\r
--- -- Status and control port\r
--- STAT_OP => med_stat_op(31 downto 16),\r
--- CTRL_OP => med_ctrl_op(31 downto 16),\r
--- STAT_DEBUG => med_stat_debug(63 downto 0),\r
--- CTRL_DEBUG => (others => '0')\r
--- ); \r
- \r
- SFP_TXDIS(1) <= sfp_txdis_S(1);\r
-\r
- \r
----------------------------------------------------------------------------\r
--- Burst- and 40MHz cycle generator\r
---------------------------------------------------------------------------- \r
-\r
-THE_SOB_SOURCE : soda_start_of_burst_control\r
- generic map(\r
- CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns\r
- CYCLE_PERIOD => cSODA_CYCLE_PERIOD, -- cycle-period in ns\r
- BURST_PERIOD => cBURST_PERIOD -- burst-period in ns\r
- )\r
- port map(\r
- SODA_CLK => clk_200_osc,\r
- RESET => reset_i,\r
- SODA_BURST_PULSE_OUT => SOB_S,\r
- SODA_40MHZ_CYCLE_OUT => soda_40mhz_cycle_S\r
- );\r
-\r
----------------------------------------------------------------------------\r
--- The Soda Central\r
---------------------------------------------------------------------------- \r
- \r
-THE_SODA_SOURCE : soda_source\r
- port map(\r
- SYSCLK => soda_tx_clock_half, --clk_100_osc, --clk_sys_i, PL! 30062014\r
- SODACLK => soda_tx_clock_full, --clk_200_osc, -- PL! 30062014\r
- RESET => reset_i,\r
-\r
- SODA_BURST_PULSE_IN => SOB_S,\r
- SODA_CYCLE_IN => soda_40mhz_cycle_S,\r
-\r
- RX_DLM_WORD_IN => rx_dlm_word,\r
- RX_DLM_IN => rx_dlm_i,\r
- TX_DLM_OUT => tx_dlm_i, \r
- TX_DLM_WORD_OUT => tx_dlm_word,\r
- TX_DLM_PREVIEW_OUT => tx_dlm_preview_S,\r
- LINK_PHASE_IN => link_phase_S,\r
- SODA_DATA_IN => soda_data_in,\r
- SODA_DATA_OUT => soda_data_out,\r
- SODA_ADDR_IN => soda_addr,\r
- SODA_READ_IN => soda_read,\r
- SODA_WRITE_IN => soda_write,\r
- SODA_ACK_OUT => soda_ack,\r
- LEDS_OUT => soda_leds\r
- );\r
-\r
----------------------------------------------------------------------------\r
--- LED\r
----------------------------------------------------------------------------\r
--- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);\r
--- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);\r
--- LED_GREEN <= med_stat_op(12); --tx_pll_lol\r
--- LED_RED <= med_stat_op(11); --rx_cdr_lol\r
- LED_ORANGE <= '1' when (med_stat_op(26)='0') else '0';\r
- LED_YELLOW <= '1' when (med_stat_op(26)='0') else '0';\r
- LED_GREEN <= med_stat_op(11);\r
- LED_RED <= med_stat_op(10);\r
- \r
-\r
----------------------------------------------------------------------------\r
--- GREEN LED under sfp\r
---------------------------------------------------------------------------- \r
- LED_LINKOK(1) <= not med_stat_op(9);\r
- LED_LINKOK(2) <= SFP_LOS(2);\r
- LED_LINKOK(3) <= SFP_LOS(3);\r
- LED_LINKOK(4) <= SFP_LOS(4);\r
- LED_LINKOK(5) <= SFP_LOS(5);\r
- LED_LINKOK(6) <= SFP_LOS(6);\r
-\r
- LED_RX(1) <= not (med_stat_op(11) or med_stat_op(10));\r
- LED_RX(2) <= '1';\r
- LED_RX(3) <= '1';\r
- LED_RX(4) <= '1';\r
- LED_RX(5) <= '1';\r
- LED_RX(6) <= '1';\r
- \r
- LED_TX(1) <= not med_stat_op(12);\r
- LED_TX(2) <= '1';\r
- LED_TX(3) <= '1';\r
- LED_TX(4) <= '1';\r
- LED_TX(5) <= '1';\r
- LED_TX(6) <= '1';\r
-\r
--- STAT_OP(12) <= led_dlm or last_led_dlm;\r
--- STAT_OP(11) <= led_tx or last_led_tx;\r
--- STAT_OP(10) <= led_rx or last_led_rx;\r
--- STAT_OP(9) <= led_ok; \r
-
----------------------------------------------------------------------------\r
--- Test Connector\r
---------------------------------------------------------------------------- \r
- TEST_LINE(13 downto 0) <= med_stat_debug(13 downto 0);\r
- TEST_LINE(14) <= soda_rx_clock_half;\r
- TEST_LINE(15) <= soda_tx_clock_half;\r
-\r
-end trb3_periph_sodasource_arch;
\ No newline at end of file
+++ /dev/null
---Media interface for Lattice ECP3 using PCS at 2GHz\r
-\r
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.med_sync_define.all;\r
-\r
-entity trb_net16_med_1_2sync_3_ecp3_sfp is\r
- port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
- REFCLK2CORE_OUT : out std_logic;\r
- CLK_RX_HALF_OUT : out std_logic;\r
- CLK_RX_FULL_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic; -- SFP disable\r
- --Control Interface\r
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
- SCI_READ : in std_logic := '0';\r
- SCI_WRITE : in std_logic := '0';\r
- SCI_ACK : out std_logic := '0';\r
- SCI_NACK : out std_logic := '0';\r
- -- SODA serdes channel\r
- SODA_RXD_P_IN : in std_logic;\r
- SODA_RXD_N_IN : in std_logic;\r
- SODA_TXD_P_OUT : out std_logic;\r
- SODA_TXD_N_OUT : out std_logic;\r
- SODA_DLM_IN : in std_logic;\r
- SODA_DLM_WORD_IN : in std_logic_vector(7 downto 0);\r
- SODA_DLM_OUT : out std_logic;\r
- SODA_DLM_WORD_OUT : out std_logic_vector(7 downto 0);\r
- SODA_CLOCK_OUT : out std_logic; -- 200MHz\r
- \r
- -- Connection to addon interface \r
- DOUT_TXD_P_OUT : out std_logic;\r
- DOUT_TXD_N_OUT : out std_logic;\r
- SFP_MOD0_5 : in std_logic;\r
- SFP_MOD0_3 : in std_logic; \r
- SFP_LOS_5 : in std_logic; \r
- SFP_LOS_3 : in std_logic;\r
- TX_READY_CH3 : out std_logic;\r
- TX_DATA_CH3 : in std_logic_vector(7 downto 0);\r
- TX_K_CH3 : in std_logic;\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end entity;\r
-\r
-architecture trb_net16_med_1_2sync_3_ecp3_sfp_arch of trb_net16_med_1_2sync_3_ecp3_sfp is\r
-\r
-\r
- -- Placer Directives\r
- attribute HGROUP : string;\r
- -- for whole architecture\r
- attribute HGROUP of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "media_interface_group";\r
- attribute syn_sharing : string;\r
- attribute syn_sharing of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "off";\r
-\r
- --OJK 29-nov-2013\r
- component sfp_1_3_200_int\r
- port(\r
- hdinp_ch1 : IN std_logic;
- hdinn_ch1 : IN std_logic;
- sci_sel_ch1 : IN std_logic;
- rxiclk_ch1 : IN std_logic;
- txiclk_ch1 : IN std_logic;
- fpga_rxrefclk_ch1 : IN std_logic;
- txdata_ch1 : IN std_logic_vector(15 downto 0);
- tx_k_ch1 : IN std_logic_vector(1 downto 0);
- tx_force_disp_ch1 : IN std_logic_vector(1 downto 0);
- tx_disp_sel_ch1 : IN std_logic_vector(1 downto 0);
- sb_felb_ch1_c : IN std_logic;
- sb_felb_rst_ch1_c : IN std_logic;
- tx_pwrup_ch1_c : IN std_logic;
- rx_pwrup_ch1_c : IN std_logic;
- tx_div2_mode_ch1_c : IN std_logic;
- rx_div2_mode_ch1_c : IN std_logic;
- sci_sel_ch3 : IN std_logic;
- txiclk_ch3 : IN std_logic;
- fpga_rxrefclk_ch3 : IN std_logic;
- txdata_ch3 : IN std_logic_vector(7 downto 0);
- tx_k_ch3 : IN std_logic;
- tx_force_disp_ch3 : IN std_logic;
- tx_disp_sel_ch3 : IN std_logic;
- tx_pwrup_ch3_c : IN std_logic;
- tx_div2_mode_ch3_c : IN std_logic;
- sci_wrdata : IN std_logic_vector(7 downto 0);
- sci_addr : IN std_logic_vector(5 downto 0);
- sci_sel_quad : IN std_logic;
- sci_rd : IN std_logic;
- sci_wrn : IN std_logic;
- fpga_txrefclk : IN std_logic;
- tx_serdes_rst_c : IN std_logic;
- tx_sync_qd_c : IN std_logic;
- rst_n : IN std_logic;
- serdes_rst_qd_c : IN std_logic;
- hdoutp_ch1 : OUT std_logic;
- hdoutn_ch1 : OUT std_logic;
- rx_full_clk_ch1 : OUT std_logic;
- rx_half_clk_ch1 : OUT std_logic;
- tx_full_clk_ch1 : OUT std_logic;
- tx_half_clk_ch1 : OUT std_logic;
- rxdata_ch1 : OUT std_logic_vector(15 downto 0);
- rx_k_ch1 : OUT std_logic_vector(1 downto 0);
- rx_disp_err_ch1 : OUT std_logic_vector(1 downto 0);
- rx_cv_err_ch1 : OUT std_logic_vector(1 downto 0);
- rx_los_low_ch1_s : OUT std_logic;
- lsm_status_ch1_s : OUT std_logic;
- rx_cdr_lol_ch1_s : OUT std_logic;
- hdoutp_ch3 : OUT std_logic;
- hdoutn_ch3 : OUT std_logic;
- tx_full_clk_ch3 : OUT std_logic;
- tx_half_clk_ch3 : OUT std_logic;
- sci_rddata : OUT std_logic_vector(7 downto 0);
- tx_pll_lol_qd_s : OUT std_logic;
- refclk2fpga : OUT std_logic\r
- );\r
- end component;\r
- \r
--- Peter Schakel 02-12-14\r
-component sfp_1_2sync_3_200_int is\r
- port (\r
-------------------\r
--- CH0 --\r
--- CH1 --\r
- hdinp_ch1, hdinn_ch1 : in std_logic;\r
- hdoutp_ch1, hdoutn_ch1 : out std_logic;\r
- sci_sel_ch1 : in std_logic;\r
- rxiclk_ch1 : in std_logic;\r
- txiclk_ch1 : in std_logic;\r
- rx_full_clk_ch1 : out std_logic;\r
- rx_half_clk_ch1 : out std_logic;\r
- tx_full_clk_ch1 : out std_logic;\r
- tx_half_clk_ch1 : out std_logic;\r
- fpga_rxrefclk_ch1 : in std_logic;\r
- txdata_ch1 : in std_logic_vector (15 downto 0);\r
- tx_k_ch1 : in std_logic_vector (1 downto 0);\r
- tx_force_disp_ch1 : in std_logic_vector (1 downto 0);\r
- tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);\r
- rxdata_ch1 : out std_logic_vector (15 downto 0);\r
- rx_k_ch1 : out std_logic_vector (1 downto 0);\r
- rx_disp_err_ch1 : out std_logic_vector (1 downto 0);\r
- rx_cv_err_ch1 : out std_logic_vector (1 downto 0);\r
- rx_serdes_rst_ch1_c : in std_logic;\r
- sb_felb_ch1_c : in std_logic;\r
- sb_felb_rst_ch1_c : in std_logic;\r
- tx_pcs_rst_ch1_c : in std_logic;\r
- tx_pwrup_ch1_c : in std_logic;\r
- rx_pcs_rst_ch1_c : in std_logic;\r
- rx_pwrup_ch1_c : in std_logic;\r
- rx_los_low_ch1_s : out std_logic;\r
- lsm_status_ch1_s : out std_logic;\r
- rx_cdr_lol_ch1_s : out std_logic;\r
- tx_div2_mode_ch1_c : in std_logic;\r
- rx_div2_mode_ch1_c : in std_logic;\r
--- CH2 --\r
- hdinp_ch2, hdinn_ch2 : in std_logic;\r
- hdoutp_ch2, hdoutn_ch2 : out std_logic;\r
- sci_sel_ch2 : in std_logic;\r
- rxiclk_ch2 : in std_logic;\r
- txiclk_ch2 : in std_logic;\r
- rx_full_clk_ch2 : out std_logic;\r
- rx_half_clk_ch2 : out std_logic;\r
- tx_full_clk_ch2 : out std_logic;\r
- tx_half_clk_ch2 : out std_logic;\r
- fpga_rxrefclk_ch2 : in std_logic;\r
- txdata_ch2 : in std_logic_vector (7 downto 0);\r
- tx_k_ch2 : in std_logic;\r
- tx_force_disp_ch2 : in std_logic;\r
- tx_disp_sel_ch2 : in std_logic;\r
- rxdata_ch2 : out std_logic_vector (7 downto 0);\r
- rx_k_ch2 : out std_logic;\r
- rx_disp_err_ch2 : out std_logic;\r
- rx_cv_err_ch2 : out std_logic;\r
- rx_serdes_rst_ch2_c : in std_logic;\r
- sb_felb_ch2_c : in std_logic;\r
- sb_felb_rst_ch2_c : in std_logic;\r
- tx_pcs_rst_ch2_c : in std_logic;\r
- tx_pwrup_ch2_c : in std_logic;\r
- rx_pcs_rst_ch2_c : in std_logic;\r
- rx_pwrup_ch2_c : in std_logic;\r
- rx_los_low_ch2_s : out std_logic;\r
- lsm_status_ch2_s : out std_logic;\r
- rx_cdr_lol_ch2_s : out std_logic;\r
- tx_div2_mode_ch2_c : in std_logic;\r
- rx_div2_mode_ch2_c : in std_logic;\r
--- CH3 --\r
- hdoutp_ch3, hdoutn_ch3 : out std_logic;\r
- sci_sel_ch3 : in std_logic;\r
- txiclk_ch3 : in std_logic;\r
- tx_full_clk_ch3 : out std_logic;\r
- tx_half_clk_ch3 : out std_logic;\r
- txdata_ch3 : in std_logic_vector (7 downto 0);\r
- tx_k_ch3 : in std_logic;\r
- tx_force_disp_ch3 : in std_logic;\r
- tx_disp_sel_ch3 : in std_logic;\r
- tx_pcs_rst_ch3_c : in std_logic;\r
- tx_pwrup_ch3_c : in std_logic;\r
- tx_div2_mode_ch3_c : in std_logic;\r
----- Miscillaneous ports\r
- sci_wrdata : in std_logic_vector (7 downto 0);\r
- sci_addr : in std_logic_vector (5 downto 0);\r
- sci_rddata : out std_logic_vector (7 downto 0);\r
- sci_sel_quad : in std_logic;\r
- sci_rd : in std_logic;\r
- sci_wrn : in std_logic;\r
- fpga_txrefclk : in std_logic;\r
- tx_serdes_rst_c : in std_logic;\r
- tx_pll_lol_qd_s : out std_logic;\r
- tx_sync_qd_c : in std_logic;\r
- rst_qd_c : in std_logic;\r
- serdes_rst_qd_c : in std_logic);\r
-\r
-end component;\r
-\r
- \r
- \r
- signal refck2core : std_logic;\r
--- signal clock : std_logic;\r
- --reset signals\r
- signal ffc_quad_rst : std_logic;\r
- signal ffc_lane_tx_rst : std_logic;\r
- signal ffc_lane_rx_rst : std_logic;\r
- --serdes connections\r
- signal tx_data : std_logic_vector(15 downto 0);\r
- signal tx_k : std_logic_vector(1 downto 0);\r
- signal rx_data : std_logic_vector(15 downto 0); -- delayed signals\r
- signal rx_k : std_logic_vector(1 downto 0); -- delayed signals\r
- signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP\r
- signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP\r
- signal link_ok : std_logic_vector(1 downto 0); -- OJK 02-dec-2013: Changed width from 1 bit to 2 bits\r
- signal link_error : std_logic_vector(10 downto 0);-- OJK 02-dec-2013: Changed width from 10 bits to 11 bits\r
- signal ff_txhalfclk : std_logic;\r
- signal ff_rxhalfclk : std_logic;\r
- signal ff_rxfullclk : std_logic;\r
- --rx fifo signals\r
- signal fifo_rx_rd_en : std_logic;\r
- signal fifo_rx_wr_en : std_logic;\r
- signal fifo_rx_reset : std_logic;\r
- signal fifo_rx_din : std_logic_vector(17 downto 0);\r
- signal fifo_rx_dout : std_logic_vector(17 downto 0);\r
- signal fifo_rx_full : std_logic;\r
- signal fifo_rx_empty : std_logic;\r
- --tx fifo signals\r
- signal fifo_tx_rd_en : std_logic;\r
- signal fifo_tx_wr_en : std_logic;\r
- signal fifo_tx_reset : std_logic;\r
- signal fifo_tx_din : std_logic_vector(17 downto 0);\r
- signal fifo_tx_dout : std_logic_vector(17 downto 0);\r
- signal fifo_tx_full : std_logic;\r
- signal fifo_tx_empty : std_logic;\r
- signal fifo_tx_almost_full : std_logic;\r
- --rx path\r
- signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- signal buf_med_dataready_out : std_logic;\r
- signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- signal last_rx : std_logic_vector(8 downto 0);\r
- signal last_fifo_rx_empty : std_logic;\r
- --tx path\r
- signal last_fifo_tx_empty : std_logic;\r
- --link status\r
- signal rx_k_q : std_logic_vector(1 downto 0);\r
-\r
- signal quad_rst : std_logic;\r
- signal lane_rst : std_logic;\r
- signal tx_allow : std_logic;\r
- signal rx_allow : std_logic;\r
- signal tx_allow_qtx : std_logic;\r
-\r
- signal rx_allow_q : std_logic; -- clock domain changed signal\r
- signal tx_allow_q : std_logic;\r
- signal swap_bytes : std_logic;\r
- signal buf_stat_debug : std_logic_vector(31 downto 0);\r
-\r
- -- status inputs from SFP\r
- signal sfp_prsnt_n : std_logic; -- synchronized input signals\r
- signal sfp_los : std_logic; -- synchronized input signals\r
-\r
- signal buf_STAT_OP : std_logic_vector(15 downto 0);\r
-\r
- signal led_counter : unsigned(16 downto 0);\r
- signal rx_led : std_logic;\r
- signal tx_led : std_logic;\r
-\r
-\r
- signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion\r
- signal first_idle : std_logic; -- tag the first IDLE2 after data\r
-\r
- signal reset_word_cnt : unsigned(4 downto 0);\r
- signal make_trbnet_reset : std_logic;\r
- signal make_trbnet_reset_q : std_logic;\r
- signal send_reset_words : std_logic;\r
- signal send_reset_words_q : std_logic;\r
- signal send_reset_in : std_logic;\r
- signal send_reset_in_qtx : std_logic;\r
- signal reset_i : std_logic;\r
- signal reset_i_rx : std_logic;\r
- signal pwr_up : std_logic;\r
- signal clear_n : std_logic;\r
-\r
- signal clk_sys : std_logic;\r
- signal clk_tx : std_logic;\r
- signal clk_rx : std_logic;\r
- signal clk_rxref : std_logic;\r
- signal clk_txref : std_logic;\r
-\r
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);\r
-signal sci_state : sci_ctrl;\r
- signal sci_ch_i : std_logic_vector(3 downto 0);\r
- signal sci_qd_i : std_logic;\r
- signal sci_reg_i : std_logic;\r
- signal sci_addr_i : std_logic_vector(8 downto 0);\r
- signal sci_data_in_i : std_logic_vector(7 downto 0);\r
- signal sci_data_out_i : std_logic_vector(7 downto 0);\r
- signal sci_read_i : std_logic;\r
- signal sci_write_i : std_logic;\r
--- signal sci_write_shift_i : std_logic_vector(2 downto 0);\r
--- signal sci_read_shift_i : std_logic_vector(2 downto 0); \r
- \r
- --OJK 13-dec-2013\r
- signal cnt : integer range 0 to 10000;\r
- signal tx_pll_lol_qd_i : std_logic;\r
- -- Peter Schakel 3-dec-2014\r
- \r
- signal sci_timer : unsigned(12 downto 0) := (others => '0');\r
- signal reset_n : std_logic;\r
- signal trb_rx_serdes_rst : std_logic;\r
- signal trb_rx_cdr_lol : std_logic;\r
- signal trb_rx_los_low : std_logic;\r
- signal trb_rx_pcs_rst : std_logic;\r
- signal trb_tx_pcs_rst : std_logic;\r
- signal rst_qd : std_logic;\r
- signal link_OK_S : std_logic;\r
- signal trb_rx_fsm_state : std_logic_vector(3 downto 0);\r
- \r
- signal sync_clk_rx_full : std_logic;\r
- signal sync_clk_rx_half : std_logic;\r
- signal sync_clk_tx_full : std_logic;\r
- signal sync_clk_tx_half : std_logic;\r
- signal sync_tx_k : std_logic;\r
- signal sync_tx_data : std_logic_vector(7 downto 0);\r
-\r
- signal syncfifo_din : std_logic_vector(17 downto 0);\r
- signal syncfifo_dout : std_logic_vector(17 downto 0);\r
- \r
- signal sync_rx_k : std_logic;\r
- signal sync_rx_data : std_logic_vector(7 downto 0);\r
- signal sync_rx_serdes_rst : std_logic;\r
- signal sync_rx_cdr_lol : std_logic;\r
- signal sync_tx_pcs_rst : std_logic;\r
- signal sync_rx_pcs_rst : std_logic;\r
- signal sync_rx_los_low : std_logic;\r
- signal sync_lsm_status : std_logic;\r
- signal SD_tx_pcs_rst : std_logic;\r
- signal DLM_fifo_rd_en : std_logic;\r
- signal DLM_fifo_empty : std_logic;\r
- signal DLM_fifo_reading : std_logic := '0'; \r
- signal SODA_dlm_word_S : std_logic_vector(7 downto 0);\r
- signal DLM_received_S : std_logic;\r
- signal sync_wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";\r
- signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";\r
- signal sync_rx_fsm_state : std_logic_vector(3 downto 0);\r
- signal sync_tx_fsm_state : std_logic_vector(3 downto 0);\r
- signal CH3_tx_fsm_state : std_logic_vector(3 downto 0);\r
-\r
- signal CLKdiv100_S : std_logic;\r
- signal sync_clk_rx_fulldiv100_S : std_logic;\r
- \r
- attribute syn_keep : boolean;\r
- attribute syn_preserve : boolean;\r
- attribute syn_keep of led_counter : signal is true;\r
- attribute syn_keep of send_reset_in : signal is true;\r
- attribute syn_keep of reset_i : signal is true;\r
- attribute syn_preserve of reset_i : signal is true;\r
-\r
-begin\r
-\r
---------------------------------------------------------------------------\r
--- Select proper clock configuration\r
---------------------------------------------------------------------------\r
- clk_sys <= SYSCLK;\r
- clk_tx <= SYSCLK;\r
- clk_rx <= ff_rxhalfclk;\r
- clk_rxref <= CLK;\r
- clk_txref <= CLK;\r
-\r
-\r
-\r
-\r
---------------------------------------------------------------------------\r
--- Internal Lane Resets\r
---------------------------------------------------------------------------\r
- clear_n <= not clear;\r
-\r
-\r
- PROC_RESET : process(clk_sys)\r
- begin\r
- if rising_edge(clk_sys) then\r
- reset_i <= RESET;\r
- send_reset_in <= ctrl_op(15);\r
- pwr_up <= '1'; --not CTRL_OP(i*16+14);\r
- end if;\r
- end process;\r
-\r
---------------------------------------------------------------------------\r
--- Synchronizer stages\r
---------------------------------------------------------------------------\r
-\r
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)\r
-THE_SFP_STATUS_SYNC: signal_sync\r
- generic map(\r
- DEPTH => 3,\r
- WIDTH => 2\r
- )\r
- port map(\r
- RESET => '0',\r
- D_IN(0) => sd_prsnt_n_in,\r
- D_IN(1) => sd_los_in,\r
- CLK0 => clk_sys,\r
- CLK1 => clk_sys,\r
- D_OUT(0) => sfp_prsnt_n,\r
- D_OUT(1) => sfp_los\r
- );\r
-\r
-\r
-THE_RX_K_SYNC: signal_sync\r
- generic map(\r
- DEPTH => 1,\r
- WIDTH => 4\r
- )\r
- port map(\r
- RESET => reset_i,\r
- D_IN(1 downto 0) => comb_rx_k,\r
- D_IN(2) => send_reset_words,\r
- D_IN(3) => make_trbnet_reset,\r
- CLK0 => clk_rx, -- CHANGED\r
- CLK1 => clk_sys,\r
- D_OUT(1 downto 0) => rx_k_q,\r
- D_OUT(2) => send_reset_words_q,\r
- D_OUT(3) => make_trbnet_reset_q\r
- );\r
-\r
-THE_RX_DATA_DELAY: signal_sync\r
- generic map(\r
- DEPTH => 2,\r
- WIDTH => 16\r
- )\r
- port map(\r
- RESET => reset_i,\r
- D_IN => comb_rx_data,\r
- CLK0 => clk_rx,\r
- CLK1 => clk_rx,\r
- D_OUT => rx_data\r
- );\r
-\r
-THE_RX_K_DELAY: signal_sync\r
- generic map(\r
- DEPTH => 2,\r
- WIDTH => 2\r
- )\r
- port map(\r
- RESET => reset_i,\r
- D_IN => comb_rx_k,\r
- CLK0 => clk_rx,\r
- CLK1 => clk_rx,\r
- D_OUT => rx_k\r
- );\r
-\r
-THE_RX_RESET: signal_sync\r
- generic map(\r
- DEPTH => 1,\r
- WIDTH => 1\r
- )\r
- port map(\r
- RESET => '0',\r
- D_IN(0) => reset_i,\r
- CLK0 => clk_rx,\r
- CLK1 => clk_rx,\r
- D_OUT(0) => reset_i_rx\r
- );\r
-\r
--- Delay for ALLOW signals\r
-THE_RX_ALLOW_SYNC: signal_sync\r
- generic map(\r
- DEPTH => 2,\r
- WIDTH => 2\r
- )\r
- port map(\r
- RESET => reset_i,\r
- D_IN(0) => rx_allow,\r
- D_IN(1) => tx_allow,\r
- CLK0 => clk_sys,\r
- CLK1 => clk_sys,\r
- D_OUT(0) => rx_allow_q,\r
- D_OUT(1) => tx_allow_q\r
- );\r
-\r
-THE_TX_SYNC: signal_sync\r
- generic map(\r
- DEPTH => 1,\r
- WIDTH => 2\r
- )\r
- port map(\r
- RESET => '0',\r
- D_IN(0) => send_reset_in,\r
- D_IN(1) => tx_allow,\r
- CLK0 => clk_tx,\r
- CLK1 => clk_tx,\r
- D_OUT(0) => send_reset_in_qtx,\r
- D_OUT(1) => tx_allow_qtx\r
- );\r
-\r
-\r
---------------------------------------------------------------------------\r
--- Main control state machine, startup control for SFP\r
---------------------------------------------------------------------------\r
-\r
-THE_SFP_LSM: trb_net16_lsm_sfp\r
- generic map (\r
- HIGHSPEED_STARTUP => c_YES\r
- )\r
- port map(\r
- SYSCLK => clk_sys,\r
- RESET => reset_i,\r
- CLEAR => clear,\r
- SFP_MISSING_IN => sfp_prsnt_n,\r
- SFP_LOS_IN => sfp_los,\r
- SD_LINK_OK_IN => link_OK_S, --// ?? link_ok(0),\r
- SD_LOS_IN => link_error(8),\r
- SD_TXCLK_BAD_IN => link_error(5),\r
- SD_RXCLK_BAD_IN => link_error(4),\r
- SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope\r
- SD_ALIGNMENT_IN => rx_k_q,\r
- SD_CV_IN => link_error(7 downto 6),\r
- FULL_RESET_OUT => quad_rst,\r
- LANE_RESET_OUT => lane_rst,\r
- TX_ALLOW_OUT => tx_allow,\r
- RX_ALLOW_OUT => rx_allow,\r
- SWAP_BYTES_OUT => swap_bytes,\r
- STAT_OP => buf_stat_op,\r
- CTRL_OP => ctrl_op,\r
- STAT_DEBUG => buf_stat_debug\r
- );\r
-\r
-sd_txdis_out <= quad_rst or reset_i;\r
-\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
-\r
-ffc_quad_rst <= quad_rst;\r
-ffc_lane_tx_rst <= lane_rst;\r
-\r
-\r
-ffc_lane_rx_rst <= lane_rst;\r
-\r
--- SerDes clock output to FPGA fabric\r
-REFCLK2CORE_OUT <= ff_rxhalfclk;\r
-CLK_RX_HALF_OUT <= ff_rxhalfclk;\r
-CLK_RX_FULL_OUT <= ff_rxfullclk;\r
-\r
-THE_SERDES: sfp_1_2sync_3_200_int port map(\r
-------------------\r
--- CH0 --\r
--- CH1 --\r
- hdinp_ch1 => sd_rxd_p_in, \r
- hdinn_ch1 => sd_rxd_n_in, \r
- hdoutp_ch1 => sd_txd_p_out, \r
- hdoutn_ch1 => sd_txd_n_out, \r
-\r
- sci_sel_ch1 => sci_ch_i(1),\r
- rxiclk_ch1 => clk_rx, \r
- txiclk_ch1 => clk_tx, \r
- rx_full_clk_ch1 => ff_rxfullclk, \r
- rx_half_clk_ch1 => ff_rxhalfclk, \r
- tx_full_clk_ch1 => open, \r
- tx_half_clk_ch1 => ff_txhalfclk, \r
- fpga_rxrefclk_ch1 => clk_rxref, \r
- txdata_ch1 => tx_data, \r
- tx_k_ch1 => tx_k, \r
- tx_force_disp_ch1 => tx_correct, \r
- tx_disp_sel_ch1 => "00", \r
- rxdata_ch1 => comb_rx_data, \r
- rx_k_ch1 => comb_rx_k, \r
- rx_disp_err_ch1 => open, \r
- rx_cv_err_ch1 => link_error(7 downto 6),\r
- rx_serdes_rst_ch1_c => trb_rx_serdes_rst,\r
- sb_felb_ch1_c => '0', \r
- sb_felb_rst_ch1_c => '0', \r
- tx_pcs_rst_ch1_c => trb_tx_pcs_rst,\r
- tx_pwrup_ch1_c => '1', \r
- rx_pcs_rst_ch1_c => trb_rx_pcs_rst,\r
- rx_pwrup_ch1_c => '1', \r
- rx_los_low_ch1_s => trb_rx_los_low, -- link_error(8), \r
- lsm_status_ch1_s => link_ok(0), \r
- rx_cdr_lol_ch1_s => trb_rx_cdr_lol, -- link_error(4), \r
- tx_div2_mode_ch1_c => '0', \r
- rx_div2_mode_ch1_c => '0',\r
-\r
--- CH2 --\r
- hdinp_ch2 => SODA_RXD_P_IN,\r
- hdinn_ch2 => SODA_RXD_N_IN,\r
- hdoutp_ch2 => SODA_TXD_P_OUT,\r
- hdoutn_ch2 => SODA_TXD_N_OUT,\r
- sci_sel_ch2 => sci_ch_i(2),\r
- rxiclk_ch2 => sync_clk_rx_full, -- ?? CLK,\r
- txiclk_ch2 => sync_clk_tx_full, -- ??CLK, --????? clk_txref\r
- rx_full_clk_ch2 => sync_clk_rx_full,\r
- rx_half_clk_ch2 => sync_clk_rx_half,\r
- tx_full_clk_ch2 => sync_clk_tx_full,\r
- tx_half_clk_ch2 => sync_clk_tx_half,\r
- fpga_rxrefclk_ch2 => CLK,\r
- txdata_ch2 => sync_tx_data,\r
- tx_k_ch2 => sync_tx_k,\r
- tx_force_disp_ch2 => '0',\r
- tx_disp_sel_ch2 => '0',\r
- rxdata_ch2 => sync_rx_data,\r
- rx_k_ch2 => sync_rx_k,\r
- rx_disp_err_ch2 => open,\r
- rx_cv_err_ch2 => open,\r
- rx_serdes_rst_ch2_c => sync_rx_serdes_rst,\r
- sb_felb_ch2_c => '0',\r
- sb_felb_rst_ch2_c => '0',\r
- tx_pcs_rst_ch2_c => sync_tx_pcs_rst,\r
- tx_pwrup_ch2_c => '1',\r
- rx_pcs_rst_ch2_c => sync_rx_pcs_rst,\r
- rx_pwrup_ch2_c => '1',\r
- rx_los_low_ch2_s => sync_rx_los_low,\r
- lsm_status_ch2_s => sync_lsm_status,\r
- rx_cdr_lol_ch2_s => sync_rx_cdr_lol,\r
- tx_div2_mode_ch2_c => '0',\r
- rx_div2_mode_ch2_c => '0',\r
- \r
--- CH3 --\r
- hdoutp_ch3 => DOUT_TXD_P_OUT, \r
- hdoutn_ch3 => DOUT_TXD_N_OUT, \r
- sci_sel_ch3 => '0', --disable access to channel 3 registers\r
- txiclk_ch3 => clk_tx, \r
- tx_full_clk_ch3 => open, \r
- tx_half_clk_ch3 => open, \r
---//???? fpga_rxrefclk_ch3 => clk_rxref, \r
- txdata_ch3 => tx_data_ch3, \r
- tx_k_ch3 => tx_k_ch3,\r
- tx_force_disp_ch3 => '0', \r
- tx_disp_sel_ch3 => '0', \r
- tx_pcs_rst_ch3_c => SD_tx_pcs_rst,\r
- tx_pwrup_ch3_c => '1', \r
- tx_div2_mode_ch3_c => '1', \r
-\r
----- Miscillaneous ports\r
- sci_wrdata => sci_data_in_i,\r
- sci_addr => sci_addr_i(5 downto 0),\r
- sci_rddata => sci_data_out_i,\r
- sci_sel_quad => sci_qd_i,\r
- sci_rd => sci_read_i,\r
- sci_wrn => sci_write_i,\r
- fpga_txrefclk => clk_txref, \r
- tx_serdes_rst_c => CLEAR, \r
- tx_pll_lol_qd_s => tx_pll_lol_qd_i, \r
- tx_sync_qd_c => '0', -- Multiple channel transmit synchronization is not needed?\r
---// refclk2fpga => open, -- Not needed?\r
- rst_qd_c => rst_qd,\r
---//?? rst_n => '1', \r
- serdes_rst_qd_c => ffc_quad_rst \r
- );\r
-\r
- syncfifo_din(7 downto 0) <= SODA_DLM_WORD_IN;\r
- syncfifo_din(17 downto 8) <= (others => '0');\r
- SODA_dlm_word_S <= syncfifo_dout(7 downto 0);\r
- \r
-sync_DLM_tx: trb_net_fifo_16bit_bram_dualport\r
-generic map(\r
- USE_STATUS_FLAGS => c_NO\r
- )\r
-port map( read_clock_in => sync_clk_tx_full,\r
- write_clock_in => sync_clk_rx_full, \r
- read_enable_in => DLM_fifo_rd_en,\r
- write_enable_in => SODA_DLM_IN,\r
- fifo_gsr_in => reset,\r
- write_data_in => syncfifo_din,\r
- read_data_out => syncfifo_dout,\r
- full_out => open,\r
- empty_out => DLM_fifo_empty\r
- );\r
-\r
-process(sync_clk_rx_full)\r
-begin\r
- if rising_edge(sync_clk_rx_full) then\r
- SODA_DLM_OUT <= '0';\r
- if DLM_received_S='1' then\r
- DLM_received_S <= '0';\r
- SODA_DLM_OUT <= '1';\r
- SODA_DLM_WORD_OUT <= sync_rx_data;\r
- elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then\r
- DLM_received_S <= '1';\r
- end if;\r
- end if;\r
-end process; \r
-\r
-process(sync_clk_tx_full)\r
-begin\r
- if rising_edge(sync_clk_tx_full) then\r
- if DLM_fifo_rd_en='1' then\r
- DLM_fifo_rd_en <= '0';\r
- sync_tx_data <= SODA_dlm_word_S;\r
- sync_tx_k <= '0';\r
- elsif (DLM_fifo_empty='0') and (DLM_fifo_reading='1') then\r
- DLM_fifo_rd_en <= '1';\r
- sync_tx_data <= x"DC";\r
- sync_tx_k <= '1';\r
- elsif DLM_fifo_empty='0' then\r
- DLM_fifo_reading <= '1';\r
- DLM_fifo_rd_en <= '0';\r
- sync_tx_data <= x"BC"; -- idle\r
- sync_tx_k <= '1'; \r
- else\r
- DLM_fifo_reading <= '0';\r
- DLM_fifo_rd_en <= '0';\r
- sync_tx_data <= x"BC"; -- idle\r
- sync_tx_k <= '1';\r
- end if;\r
- end if;\r
-end process; \r
-SODA_CLOCK_OUT <= sync_clk_rx_full;\r
-\r
-\r
-link_error(8) <= trb_rx_los_low; -- loss of signal\r
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock \r
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock\r
-\r
-reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';\r
-\r
-------------------------------------------------- \r
--- Reset FSM & Link states\r
-------------------------------------------------- \r
-THE_RX_FSM1: rx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- RX_REFCLK => CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RX_SERDES_RST_CH_C => trb_rx_serdes_rst,\r
- RX_CDR_LOL_CH_S => trb_rx_cdr_lol,\r
- RX_LOS_LOW_CH_S => trb_rx_los_low,\r
- RX_PCS_RST_CH_C => trb_rx_pcs_rst,\r
- WA_POSITION => "0000",\r
- STATE_OUT => trb_rx_fsm_state\r
- );\r
-\r
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';\r
-THE_TX_FSM1: tx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- TX_REFCLK => CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RST_QD_C => rst_qd,\r
- TX_PCS_RST_CH_C => trb_tx_pcs_rst,\r
- STATE_OUT => open\r
- );\r
-\r
-THE_RX_FSM2: rx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- RX_REFCLK => sync_clk_rx_full, --??CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RX_SERDES_RST_CH_C => sync_rx_serdes_rst,\r
- RX_CDR_LOL_CH_S => sync_rx_cdr_lol,\r
- RX_LOS_LOW_CH_S => sync_rx_los_low,\r
- RX_PCS_RST_CH_C => sync_rx_pcs_rst,\r
- WA_POSITION => sync_wa_position_rx(11 downto 8),\r
- STATE_OUT => sync_rx_fsm_state\r
- );\r
-SYNC_WA_POSITION : process(sync_clk_rx_full) --??CLK)\r
-begin\r
- if rising_edge(sync_clk_rx_full) then\r
- sync_wa_position_rx <= wa_position;\r
- end if;\r
-end process;\r
- \r
-THE_TX_FSM2: tx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- TX_REFCLK => CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RST_QD_C => open, --??\r
- TX_PCS_RST_CH_C => sync_tx_pcs_rst,\r
- STATE_OUT => sync_tx_fsm_state\r
- );\r
- \r
-THE_TX_FSM3 : tx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- TX_REFCLK => CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RST_QD_C => open, --??\r
- TX_PCS_RST_CH_C => SD_tx_pcs_rst,\r
- STATE_OUT => CH3_tx_fsm_state\r
- );\r
-TX_READY_CH3 <= '1' when (CH3_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';\r
- \r
- \r
--------------------------------------------------------------------------\r
--- RX Fifo & Data output\r
--------------------------------------------------------------------------\r
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport\r
-generic map(\r
- USE_STATUS_FLAGS => c_NO\r
- )\r
-port map( read_clock_in => clk_sys,\r
- write_clock_in => clk_rx, -- CHANGED\r
- read_enable_in => fifo_rx_rd_en,\r
- write_enable_in => fifo_rx_wr_en,\r
- fifo_gsr_in => fifo_rx_reset,\r
- write_data_in => fifo_rx_din,\r
- read_data_out => fifo_rx_dout,\r
- full_out => fifo_rx_full,\r
- empty_out => fifo_rx_empty\r
- );\r
-\r
-fifo_rx_reset <= reset_i or not rx_allow_q;\r
-fifo_rx_rd_en <= not fifo_rx_empty;\r
-\r
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path\r
-THE_BYTE_SWAP_PROC: process(clk_rx)\r
- begin\r
- if rising_edge(clk_rx) then\r
- last_rx <= rx_k(1) & rx_data(15 downto 8);\r
- if( swap_bytes = '0' ) then\r
- fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);\r
- fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);\r
- else\r
- fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);\r
- fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);\r
- end if;\r
- end if;\r
- end process THE_BYTE_SWAP_PROC;\r
-\r
-buf_med_data_out <= fifo_rx_dout(15 downto 0);\r
-buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;\r
-buf_med_packet_num_out <= rx_counter;\r
-med_read_out <= tx_allow_q and not fifo_tx_almost_full;\r
-\r
-\r
-THE_CNT_RESET_PROC : process(clk_rx)\r
- begin\r
- if rising_edge(clk_rx) then\r
- if reset_i_rx = '1' then\r
- send_reset_words <= '0';\r
- make_trbnet_reset <= '0';\r
- reset_word_cnt <= (others => '0');\r
- else\r
- send_reset_words <= '0';\r
- make_trbnet_reset <= '0';\r
- if fifo_rx_din = "11" & x"FEFE" then\r
- if reset_word_cnt(4) = '0' then\r
- reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);\r
- else\r
- send_reset_words <= '1';\r
- end if;\r
- else\r
- reset_word_cnt <= (others => '0');\r
- make_trbnet_reset <= reset_word_cnt(4);\r
- end if;\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
-THE_SYNC_PROC: process(clk_rx)\r
- begin\r
- if rising_edge(clk_rx) then\r
- med_dataready_out <= buf_med_dataready_out;\r
- med_data_out <= buf_med_data_out;\r
- med_packet_num_out <= buf_med_packet_num_out;\r
- if reset_i = '1' then\r
- med_dataready_out <= '0';\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
---rx packet counter\r
----------------------\r
-THE_RX_PACKETS_PROC: process( clk_sys )\r
- begin\r
- if( rising_edge(clk_sys) ) then\r
- last_fifo_rx_empty <= fifo_rx_empty;\r
- if reset_i = '1' or rx_allow_q = '0' then\r
- rx_counter <= c_H0;\r
- else\r
- if( buf_med_dataready_out = '1' ) then\r
- if( rx_counter = c_max_word_number ) then\r
- rx_counter <= (others => '0');\r
- else\r
- rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));\r
- end if;\r
- end if;\r
- end if;\r
- end if;\r
- end process;\r
-\r
---TX Fifo & Data output to Serdes\r
----------------------\r
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport\r
- generic map(\r
- USE_STATUS_FLAGS => c_NO\r
- )\r
- port map( read_clock_in => clk_tx,\r
- write_clock_in => clk_sys,\r
- read_enable_in => fifo_tx_rd_en,\r
- write_enable_in => fifo_tx_wr_en,\r
- fifo_gsr_in => fifo_tx_reset,\r
- write_data_in => fifo_tx_din,\r
- read_data_out => fifo_tx_dout,\r
- full_out => fifo_tx_full,\r
- empty_out => fifo_tx_empty,\r
- almost_full_out => fifo_tx_almost_full\r
- );\r
-\r
-fifo_tx_reset <= reset_i or not tx_allow_q;\r
-fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;\r
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;\r
-fifo_tx_rd_en <= tx_allow_qtx;\r
-\r
-\r
-THE_SERDES_INPUT_PROC: process( clk_tx )\r
- begin\r
- if( rising_edge(clk_tx) ) then\r
- last_fifo_tx_empty <= fifo_tx_empty;\r
- first_idle <= not last_fifo_tx_empty and fifo_tx_empty;\r
- if send_reset_in = '1' then\r
- tx_data <= x"FEFE";\r
- tx_k <= "11";\r
- elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then\r
- tx_data <= x"50bc";\r
- tx_k <= "01";\r
- tx_correct <= first_idle & '0';\r
- else\r
- tx_data <= fifo_tx_dout(15 downto 0);\r
- tx_k <= "00";\r
- tx_correct <= "00";\r
- end if;\r
- end if;\r
- end process THE_SERDES_INPUT_PROC;\r
-\r
-------------------------------------------------- \r
--- SCI\r
-------------------------------------------------- \r
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us\r
-PROC_SCI_CTRL: process(clk_sys)\r
- variable cnt : integer range 0 to 4 := 0;\r
-begin\r
- if( rising_edge(clk_sys) ) then\r
- SCI_ACK <= '0';\r
- case sci_state is\r
- when IDLE =>\r
- sci_ch_i <= x"0";\r
- sci_qd_i <= '0';\r
- sci_reg_i <= '0';\r
- sci_read_i <= '0';\r
- sci_write_i <= '0';\r
- sci_timer <= sci_timer + 1;\r
- if SCI_READ = '1' or SCI_WRITE = '1' then\r
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
- sci_addr_i <= SCI_ADDR;\r
- sci_data_in_i <= SCI_DATA_IN;\r
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
- sci_state <= SCTRL;\r
- elsif sci_timer(sci_timer'left) = '1' then\r
- sci_timer <= (others => '0');\r
- sci_state <= GET_WA;\r
- end if; \r
- when SCTRL =>\r
- if sci_reg_i = '1' then\r
---// SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));\r
- SCI_DATA_OUT <= (others => '0');\r
- SCI_ACK <= '1';\r
- sci_write_i <= '0';\r
- sci_read_i <= '0';\r
- sci_state <= IDLE;\r
- else\r
- sci_state <= SCTRL_WAIT;\r
- end if;\r
- when SCTRL_WAIT =>\r
- sci_state <= SCTRL_WAIT2;\r
- when SCTRL_WAIT2 =>\r
- sci_state <= SCTRL_FINISH;\r
- when SCTRL_FINISH =>\r
- SCI_DATA_OUT <= sci_data_out_i;\r
- SCI_ACK <= '1';\r
- sci_write_i <= '0';\r
- sci_read_i <= '0';\r
- sci_state <= IDLE;\r
- \r
- when GET_WA =>\r
- if cnt = 4 then\r
- cnt := 0;\r
- sci_state <= IDLE;\r
- else\r
- sci_state <= GET_WA_WAIT;\r
- sci_addr_i <= '0' & x"22";\r
- sci_ch_i <= x"0";\r
- sci_ch_i(cnt) <= '1';\r
- sci_read_i <= '1';\r
- end if;\r
- when GET_WA_WAIT =>\r
- sci_state <= GET_WA_WAIT2;\r
- when GET_WA_WAIT2 =>\r
- sci_state <= GET_WA_FINISH;\r
- when GET_WA_FINISH =>\r
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);\r
- sci_state <= GET_WA; \r
- cnt := cnt + 1;\r
- end case;\r
- \r
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then\r
- SCI_NACK <= '1';\r
- else\r
- SCI_NACK <= '0';\r
- end if;\r
- end if;\r
-end process;\r
- \r
- \r
-\r
---Generate LED signals\r
-----------------------\r
-process( clk_sys )\r
- begin\r
- if rising_edge(clk_sys) then\r
- led_counter <= led_counter + to_unsigned(1,1);\r
-\r
- if buf_med_dataready_out = '1' then\r
- rx_led <= '1';\r
- elsif led_counter = 0 then\r
- rx_led <= '0';\r
- end if;\r
-\r
- if tx_k(0) = '0' then\r
- tx_led <= '1';\r
- elsif led_counter = 0 then\r
- tx_led <= '0';\r
- end if;\r
-\r
- end if;\r
- end process;\r
-\r
-stat_op(15) <= send_reset_words_q;\r
-stat_op(14) <= buf_stat_op(14);\r
-stat_op(13) <= make_trbnet_reset_q;\r
-stat_op(12) <= '0';\r
-stat_op(11) <= tx_led; --tx led\r
-stat_op(10) <= rx_led; --rx led\r
-stat_op(9 downto 0) <= buf_stat_op(9 downto 0);\r
-\r
--- Debug output\r
-stat_debug(15 downto 0) <= rx_data;\r
-stat_debug(17 downto 16) <= rx_k;\r
-stat_debug(19 downto 18) <= (others => '0');\r
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);\r
-stat_debug(24) <= fifo_rx_rd_en;\r
-stat_debug(25) <= fifo_rx_wr_en;\r
-stat_debug(26) <= fifo_rx_reset;\r
-stat_debug(27) <= fifo_rx_empty;\r
-stat_debug(28) <= fifo_rx_full;\r
-stat_debug(29) <= last_rx(8);\r
-stat_debug(30) <= rx_allow_q;\r
-stat_debug(41 downto 31) <= (others => '0');\r
-stat_debug(42) <= clk_sys;\r
-stat_debug(43) <= clk_sys;\r
-stat_debug(59 downto 44) <= (others => '0');\r
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);\r
-\r
---stat_debug(3 downto 0) <= buf_stat_debug(3 downto 0); -- state_bits\r
---stat_debug(4) <= buf_stat_debug(4); -- alignme\r
---stat_debug(5) <= sfp_prsnt_n;\r
---stat_debug(6) <= tx_k(0);\r
---stat_debug(7) <= tx_k(1);\r
---stat_debug(8) <= rx_k_q(0);\r
---stat_debug(9) <= rx_k_q(1);\r
---stat_debug(18 downto 10) <= link_error;\r
---stat_debug(19) <= '0';\r
---stat_debug(20) <= link_ok(0);\r
---stat_debug(38 downto 21) <= fifo_rx_din;\r
---stat_debug(39) <= swap_bytes;\r
---stat_debug(40) <= buf_stat_debug(7); -- sfp_missing_in\r
---stat_debug(41) <= buf_stat_debug(8); -- sfp_los_in\r
---stat_debug(42) <= buf_stat_debug(6); -- resync\r
---stat_debug(59 downto 43) <= (others => '0');\r
---stat_debug(63 downto 60) <= link_error(3 downto 0);\r
-\r
-CLKdiv100_process: process(CLK)\r
-variable counter_V : integer range 0 to 99 := 0;\r
-begin\r
- if (rising_edge(CLK)) then \r
- if counter_V<49 then -- 99 for 125MHz\r
- counter_V := counter_V+1;\r
- else\r
- counter_V := 0;\r
- CLKdiv100_S <= not CLKdiv100_S;\r
- end if;\r
- end if;\r
-end process;\r
-sync_clk_rx_fulldiv100_process: process(sync_clk_rx_full)\r
-variable counter_V : integer range 0 to 99 := 0;\r
-begin\r
- if (rising_edge(sync_clk_rx_full)) then \r
- if counter_V<49 then -- 99 for 125MHz\r
- counter_V := counter_V+1;\r
- else\r
- counter_V := 0;\r
- sync_clk_rx_fulldiv100_S <= not sync_clk_rx_fulldiv100_S;\r
- end if;\r
- end if;\r
-end process;\r
-\r
-end architecture;\r
+++ /dev/null
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;\r
-use work.med_sync_define.all;
-
-entity Cu_trb_net16_soda_sync_ecp3_sfp is
- port(
- OSCCLK : in std_logic; -- 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- --Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
- --Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
-
- --Copper SFP Connection
- CU_RXD_P_IN : in std_logic;
- CU_RXD_N_IN : in std_logic;
- CU_TXD_P_OUT : out std_logic;
- CU_TXD_N_OUT : out std_logic;
- CU_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- CU_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- CU_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Fiber/sync SFP Connection
- SYNC_RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- SYNC_RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- SYNC_TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- SYNC_TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- SYNC_DLM_IN : in std_logic;
- SYNC_DLM_WORD_IN : in std_logic_vector(7 downto 0);
- SYNC_DLM_OUT : out std_logic;
- SYNC_DLM_WORD_OUT : out std_logic_vector(7 downto 0);
- SYNC_RXD_P_IN : in std_logic;
- SYNC_RXD_N_IN : in std_logic;
- SYNC_TXD_P_OUT : out std_logic;
- SYNC_TXD_N_OUT : out std_logic;
- SYNC_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SYNC_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SYNC_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';\r
-\r
- TX_READY_CH3 : out std_logic;
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
-end entity;
-
-architecture Cu_trb_net16_soda_sync_ecp3_sfp_arch of Cu_trb_net16_soda_sync_ecp3_sfp is
-
-
- -- Placer Directives
- attribute HGROUP : string;
- -- for whole architecture
- attribute HGROUP of Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "media_interface_group";
- attribute syn_sharing : string;
- attribute syn_sharing of Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "off";
-
- component sfp_2_200_int
- port
- (
- hdinp_ch1, hdinn_ch1 : in std_logic;
- hdoutp_ch1, hdoutn_ch1 : out std_logic;
- sci_sel_ch1 : in std_logic;
- rxiclk_ch1 : in std_logic;
- txiclk_ch1 : in std_logic;
- rx_full_clk_ch1 : out std_logic;
- rx_half_clk_ch1 : out std_logic;
- tx_full_clk_ch1 : out std_logic;
- tx_half_clk_ch1 : out std_logic;
- fpga_rxrefclk_ch1 : in std_logic;
- txdata_ch1 : in std_logic_vector (15 downto 0);
- tx_k_ch1 : in std_logic_vector (1 downto 0);
- tx_force_disp_ch1 : in std_logic_vector (1 downto 0);
- tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);
- rxdata_ch1 : out std_logic_vector (15 downto 0);
- rx_k_ch1 : out std_logic_vector (1 downto 0);
- rx_disp_err_ch1 : out std_logic_vector (1 downto 0);
- rx_cv_err_ch1 : out std_logic_vector (1 downto 0);
- rx_serdes_rst_ch1_c : in std_logic;
- sb_felb_ch1_c : in std_logic;
- sb_felb_rst_ch1_c : in std_logic;
- tx_pcs_rst_ch1_c : in std_logic;
- tx_pwrup_ch1_c : in std_logic;
- rx_pcs_rst_ch1_c : in std_logic;
- rx_pwrup_ch1_c : in std_logic;
- rx_los_low_ch1_s : out std_logic;
- lsm_status_ch1_s : out std_logic;
- rx_cdr_lol_ch1_s : out std_logic;
- tx_div2_mode_ch1_c : in std_logic;
- rx_div2_mode_ch1_c : in std_logic;
-
- hdinp_ch3, hdinn_ch3 : in std_logic;
- hdoutp_ch3, hdoutn_ch3 : out std_logic;
- sci_sel_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- txdata_ch3 : in std_logic_vector (7 downto 0);
- tx_k_ch3 : in std_logic;
- tx_force_disp_ch3 : in std_logic;
- tx_disp_sel_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- rx_serdes_rst_ch3_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
- tx_pcs_rst_ch3_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pcs_rst_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
- tx_div2_mode_ch3_c : in std_logic;
- rx_div2_mode_ch3_c : in std_logic;
- ---- Miscillaneous ports
- sci_wrdata : in std_logic_vector (7 downto 0);
- sci_addr : in std_logic_vector (5 downto 0);
- sci_rddata : out std_logic_vector (7 downto 0);
- sci_sel_quad : in std_logic;
- sci_rd : in std_logic;
- sci_wrn : in std_logic;
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- tx_sync_qd_c : in std_logic;
- rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
- serdes_rst_qd_c : in std_logic
- );
- end component;
-
- signal refck2core : std_logic;
- -- signal clock : std_logic;
- --reset signals
- signal ffc_quad_rst : std_logic;
- signal ffc_lane_tx_rst : std_logic;
- signal ffc_lane_rx_rst : std_logic;
- --serdes connections
- signal tx_data : std_logic_vector(15 downto 0);
- signal tx_k : std_logic_vector(1 downto 0);
- signal rx_data : std_logic_vector(15 downto 0); -- delayed signals
- signal rx_k : std_logic_vector(1 downto 0); -- delayed signals
- signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP
- signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP
- signal link_ok : std_logic_vector(0 downto 0);
- signal link_error : std_logic_vector(8 downto 0);
- signal ff_txhalfclk : std_logic;
- signal ff_rxhalfclk : std_logic;
- signal ff_rxfullclk : std_logic;
- --rx fifo signals
- signal fifo_rx_rd_en : std_logic;
- signal fifo_rx_wr_en : std_logic;
- signal fifo_rx_reset : std_logic;
- signal fifo_rx_din : std_logic_vector(17 downto 0);
- signal fifo_rx_dout : std_logic_vector(17 downto 0);
- signal fifo_rx_full : std_logic;
- signal fifo_rx_empty : std_logic;
- --tx fifo signals
- signal fifo_tx_rd_en : std_logic;
- signal fifo_tx_wr_en : std_logic;
- signal fifo_tx_reset : std_logic;
- signal fifo_tx_din : std_logic_vector(17 downto 0);
- signal fifo_tx_dout : std_logic_vector(17 downto 0);
- signal fifo_tx_full : std_logic;
- signal fifo_tx_empty : std_logic;
- signal fifo_tx_almost_full : std_logic;
- --rx path
- signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal buf_med_dataready_out : std_logic;
- signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal last_rx : std_logic_vector(8 downto 0);
- signal last_fifo_rx_empty : std_logic;
- --tx path
- signal last_fifo_tx_empty : std_logic;
- --link status
- signal rx_k_q : std_logic_vector(1 downto 0);
-
- signal quad_rst : std_logic;
- signal lane_rst : std_logic;
- signal tx_allow : std_logic;
- signal rx_allow : std_logic;
- signal tx_allow_qtx : std_logic;
-
- signal rx_allow_q : std_logic; -- clock domain changed signal
- signal tx_allow_q : std_logic;
- signal swap_bytes : std_logic;
- signal buf_stat_debug : std_logic_vector(31 downto 0);
-
- -- status inputs from SFP
- signal sfp_prsnt_n : std_logic; -- synchronized input signals
- signal sfp_los : std_logic; -- synchronized input signals
-
- signal buf_STAT_OP : std_logic_vector(15 downto 0);
-
- signal led_counter : unsigned(16 downto 0);
- signal rx_led : std_logic;
- signal tx_led : std_logic;
-
-
- signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
- signal first_idle : std_logic; -- tag the first IDLE2 after data
-
- signal reset_word_cnt : unsigned(4 downto 0);
- signal make_trbnet_reset : std_logic;
- signal make_trbnet_reset_q : std_logic;
- signal send_reset_words : std_logic;
- signal send_reset_words_q : std_logic;
- signal send_reset_in : std_logic;
- signal send_reset_in_qtx : std_logic;
- signal reset_i : std_logic;
- signal reset_i_rx : std_logic;
- signal pwr_up : std_logic;
-
- signal clk_sys : std_logic;
- signal clk_tx : std_logic;
- signal clk_rx : std_logic;
- signal clk_rxref : std_logic;
- signal clk_txref : std_logic;
-
- -- Peter Schakel 3-dec-2014
-
- signal sci_timer : unsigned(12 downto 0) := (others => '0');
- signal reset_n : std_logic;
- signal trb_rx_serdes_rst : std_logic;
- signal trb_rx_cdr_lol : std_logic;
- signal trb_rx_los_low : std_logic;
- signal trb_rx_pcs_rst : std_logic;
- signal trb_tx_pcs_rst : std_logic;
- signal rst_qd : std_logic;
- signal rst_qd1 : std_logic;
- signal rst_qd3 : std_logic;
- signal link_OK_S : std_logic;
- signal trb_rx_fsm_state : std_logic_vector(3 downto 0);
- signal trb_tx_fsm_state : std_logic_vector(3 downto 0);
- signal sync_rx_fsm_state : std_logic_vector(3 downto 0);
- signal sync_tx_fsm_state : std_logic_vector(3 downto 0);
- signal clk_200_osc : std_logic;
- signal sync_rx_full_clk : std_logic;
- signal sync_rx_half_clk : std_logic;
- signal sync_tx_full_clk : std_logic;
- signal sync_tx_half_clk : std_logic;
-
- signal sync_tx_data : std_logic_vector(7 downto 0);
- signal sync_tx_k : std_logic;
- signal sync_rx_data : std_logic_vector(7 downto 0);
- signal sync_rx_k : std_logic;
- signal sync_rx_error : std_logic;
- signal sync_rx_serdes_rst : std_logic;
- signal sync_tx_pcs_rst : std_logic;
- signal sync_rx_pcs_rst : std_logic;
- signal sync_rx_los_low : std_logic;
- signal sync_lsm_status : std_logic;
- signal sync_rx_cdr_lol : std_logic;
- signal dlm_fifo_rd_en : std_logic;
- signal dlm_fifo_empty : std_logic;
- signal dlm_fifo_reading : std_logic;
- signal dlm_received_S : std_logic;
-
- signal syncfifo_din : std_logic_vector(17 downto 0);
- signal syncfifo_dout : std_logic_vector(17 downto 0);
-
- type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
- signal sci_state : sci_ctrl;\r
-
- signal sci_ch_i : std_logic_vector(3 downto 0);
- signal sci_qd_i : std_logic;
- signal sci_reg_i : std_logic;
- signal sci_addr_i : std_logic_vector(8 downto 0);
- signal sci_data_in_i : std_logic_vector(7 downto 0);
- signal sci_data_out_i : std_logic_vector(7 downto 0);
- signal sci_read_i : std_logic;
- signal sci_write_i : std_logic;
- signal sci_write_shift_i : std_logic_vector(2 downto 0);
- signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
- signal tx_pll_lol_qd_i : std_logic;
-\r
- signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
- signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
- signal sync_wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
- signal sync_tx_allow : std_logic;
- signal sync_rx_allow : std_logic;
- signal sync_tx_allow_q : std_logic;
- signal sync_rx_allow_q : std_logic;
- signal link_phase_S : std_logic; --PL!
- signal request_retr_i : std_logic;
- signal start_retr_i : std_logic;
- signal request_retr_position_i : std_logic_vector(7 downto 0);
- signal start_retr_position_i : std_logic_vector(7 downto 0);
- signal send_link_reset_i : std_logic;
- signal make_link_reset_i : std_logic;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
- attribute syn_keep of led_counter : signal is true;
- attribute syn_keep of send_reset_in : signal is true;
- attribute syn_keep of reset_i : signal is true;
- attribute syn_preserve of reset_i : signal is true;
- attribute syn_preserve of sci_ch_i : signal is true;--
- attribute syn_keep of sci_ch_i : signal is true;--
- attribute syn_preserve of sci_addr_i : signal is true;--
- attribute syn_keep of sci_addr_i : signal is true;--
- attribute syn_preserve of sci_data_in_i : signal is true;--
- attribute syn_keep of sci_data_in_i : signal is true;--
- attribute syn_preserve of sci_data_out_i : signal is true;--
- attribute syn_keep of sci_data_out_i : signal is true;--
- attribute syn_preserve of sci_read_i : signal is true;--
- attribute syn_keep of sci_read_i : signal is true;--
- attribute syn_preserve of sci_write_i : signal is true;--
- attribute syn_keep of sci_write_i : signal is true;--
- attribute syn_preserve of sci_write_shift_i : signal is true;--
- attribute syn_keep of sci_write_shift_i : signal is true;--
- attribute syn_preserve of sci_read_shift_i : signal is true;--
- attribute syn_keep of sci_read_shift_i : signal is true;--
- attribute syn_preserve of wa_position : signal is true;--
- attribute syn_keep of wa_position : signal is true;--
- attribute syn_preserve of wa_position_rx : signal is true;--
- attribute syn_keep of wa_position_rx : signal is true;--
-
-begin
-
-clk_200_osc <= OSCCLK;
-
-SYNC_RX_HALF_CLK_OUT <= sync_rx_half_clk;
-SYNC_RX_FULL_CLK_OUT <= sync_rx_full_clk;
-SYNC_TX_HALF_CLK_OUT <= sync_tx_half_clk;
-SYNC_TX_FULL_CLK_OUT <= sync_tx_full_clk;
---RX_CDR_LOL_OUT <= rx_cdr_lol;
-
-clk_sys <= SYSCLK;
-clk_tx <= SYSCLK;
-clk_rx <= ff_rxhalfclk;
-clk_rxref <= OSCCLK;
-clk_txref <= OSCCLK;
-
---sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!
-
---------------------------------------------------------------------------
--- Internal Lane Resets
---------------------------------------------------------------------------
- PROC_RESET : process(clk_sys)
- begin
- if rising_edge(clk_sys) then
- reset_i <= RESET;
- send_reset_in <= ctrl_op(15);
- pwr_up <= '1'; --not CTRL_OP(i*16+14);
- end if;
- end process;
-
---------------------------------------------------------------------------
--- Synchronizer stages
---------------------------------------------------------------------------
-
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
-THE_SFP_STATUS_SYNC: signal_sync
- generic map(
- DEPTH => 3,
- WIDTH => 2
- )
- port map(
- RESET => '0',
- D_IN(0) => sync_prsnt_n_in,
- D_IN(1) => sync_los_in,
- CLK0 => clk_sys,
- CLK1 => clk_sys,
- D_OUT(0) => sfp_prsnt_n,
- D_OUT(1) => sfp_los
- );
-
-
-THE_RX_K_SYNC: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 4
- )
- port map(
- RESET => reset_i,
- D_IN(1 downto 0) => comb_rx_k,
- D_IN(2) => send_reset_words,
- D_IN(3) => make_trbnet_reset,
- CLK0 => clk_rx, -- CHANGED
- CLK1 => clk_sys,
- D_OUT(1 downto 0) => rx_k_q,
- D_OUT(2) => send_reset_words_q,
- D_OUT(3) => make_trbnet_reset_q
- );
-
-THE_RX_DATA_DELAY: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 16
- )
- port map(
- RESET => reset_i,
- D_IN => comb_rx_data,
- CLK0 => clk_rx,
- CLK1 => clk_rx,
- D_OUT => rx_data
- );
-
-THE_RX_K_DELAY: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 2
- )
- port map(
- RESET => reset_i,
- D_IN => comb_rx_k,
- CLK0 => clk_rx,
- CLK1 => clk_rx,
- D_OUT => rx_k
- );
-
-THE_RX_RESET: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 1
- )
- port map(
- RESET => '0',
- D_IN(0) => reset_i,
- CLK0 => clk_rx,
- CLK1 => clk_rx,
- D_OUT(0) => reset_i_rx
- );
-
--- Delay for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 2
- )
- port map(
- RESET => reset_i,
- D_IN(0) => rx_allow,
- D_IN(1) => tx_allow,
- CLK0 => clk_sys,
- CLK1 => clk_sys,
- D_OUT(0) => rx_allow_q,
- D_OUT(1) => tx_allow_q
- );
-
-THE_TX_SYNC: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 2
- )
- port map(
- RESET => '0',
- D_IN(0) => send_reset_in,
- D_IN(1) => tx_allow,
- CLK0 => clk_tx,
- CLK1 => clk_tx,
- D_OUT(0) => send_reset_in_qtx,
- D_OUT(1) => tx_allow_qtx
- );
-
-
---------------------------------------------------------------------------
--- Main control state machine, startup control for SFP
---------------------------------------------------------------------------
-
-THE_SFP_LSM: trb_net16_lsm_sfp
- generic map (
- HIGHSPEED_STARTUP => c_YES
- )
- port map(
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear,
- SFP_MISSING_IN => sfp_prsnt_n,
- SFP_LOS_IN => sfp_los,
- SD_LINK_OK_IN => link_ok(0),
- SD_LOS_IN => link_error(8),
- SD_TXCLK_BAD_IN => link_error(5),
- SD_RXCLK_BAD_IN => link_error(4),
- SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
- SD_ALIGNMENT_IN => rx_k_q,
- SD_CV_IN => link_error(7 downto 6),
- FULL_RESET_OUT => quad_rst,
- LANE_RESET_OUT => lane_rst,
- TX_ALLOW_OUT => tx_allow,
- RX_ALLOW_OUT => rx_allow,
- SWAP_BYTES_OUT => swap_bytes,
- STAT_OP => buf_stat_op,
- CTRL_OP => ctrl_op,
- STAT_DEBUG => buf_stat_debug
- );
-
-SYNC_TXDIS_OUT <= quad_rst or reset_i;
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
-ffc_quad_rst <= quad_rst;
-ffc_lane_tx_rst <= lane_rst;
-
-
-ffc_lane_rx_rst <= lane_rst;
-
-
-
--- Instantiation of serdes module
-
- THE_SERDES: sfp_2_200_int
- port map(
- HDINP_CH1 => CU_RXD_P_IN,
- HDINN_CH1 => CU_RXD_N_IN,
- HDOUTP_CH1 => CU_TXD_P_OUT,
- HDOUTN_CH1 => CU_TXD_N_OUT,
- SCI_SEL_CH1 => sci_ch_i(1),
- RXICLK_CH1 => clk_rx,
- TXICLK_CH1 => clk_tx,
- RX_FULL_CLK_CH1 => ff_rxfullclk,
- RX_HALF_CLK_CH1 => ff_rxhalfclk,
- TX_FULL_CLK_CH1 => open,
- TX_HALF_CLK_CH1 => ff_txhalfclk,
- FPGA_RXREFCLK_CH1 => clk_rxref,
- TXDATA_CH1 => tx_data,
- TX_K_CH1 => tx_k,
- TX_FORCE_DISP_CH1 => tx_correct,
- TX_DISP_SEL_CH1 => "00",
- RXDATA_CH1 => comb_rx_data,
- RX_K_CH1 => comb_rx_k,
- RX_DISP_ERR_CH1 => open,
- RX_CV_ERR_CH1 => link_error(7 downto 6),
- RX_SERDES_RST_CH1_C => trb_rx_serdes_rst,
- SB_FELB_CH1_C => '0', --loopback enable
- SB_FELB_RST_CH1_C => '0', --loopback reset
- TX_PCS_RST_CH1_C => trb_tx_pcs_rst, --'1', --tx power up
- TX_PWRUP_CH1_C => '1', --tx power up
- RX_PCS_RST_CH1_C => trb_rx_pcs_rst, --'1', --rx power up
- RX_PWRUP_CH1_C => '1', --rx power up
- RX_LOS_LOW_CH1_S => trb_rx_los_low, --link_error(8),
- LSM_STATUS_CH1_S => link_ok(0),
- RX_CDR_LOL_CH1_S => trb_rx_cdr_lol, --link_error(4),
- TX_DIV2_MODE_CH1_C => '0', --full rate
- RX_DIV2_MODE_CH1_C => '0', --full rate
-
- HDINP_CH3 => SYNC_RXD_P_IN,
- HDINN_CH3 => SYNC_RXD_N_IN,
- HDOUTP_CH3 => SYNC_TXD_P_OUT,
- HDOUTN_CH3 => SYNC_TXD_N_OUT,
- SCI_SEL_CH3 => sci_ch_i(3),
- TXICLK_CH3 => sync_rx_full_clk,
- RX_FULL_CLK_CH3 => sync_rx_full_clk,
- RX_HALF_CLK_CH3 => sync_rx_half_clk,
- TX_FULL_CLK_CH3 => sync_tx_full_clk,
- TX_HALF_CLK_CH3 => sync_tx_half_clk,
- FPGA_RXREFCLK_CH3 => clk_200_osc,
- TXDATA_CH3 => sync_tx_data,
- TX_K_CH3 => sync_tx_k,
- TX_FORCE_DISP_CH3 => '0',
- TX_DISP_SEL_CH3 => '0',
- RXDATA_CH3 => sync_rx_data,
- RX_K_CH3 => sync_rx_k,
- RX_DISP_ERR_CH3 => open,
- RX_CV_ERR_CH3 => sync_rx_error,
- RX_SERDES_RST_CH3_C => sync_rx_serdes_rst,
- SB_FELB_CH3_C => '0', --loopback enable
- SB_FELB_RST_CH3_C => '0', --loopback reset
- TX_PCS_RST_CH3_C => sync_tx_pcs_rst,
- TX_PWRUP_CH3_C => '1',
- RX_PCS_RST_CH3_C => sync_rx_pcs_rst,
- RX_PWRUP_CH3_C => '1',
- RX_LOS_LOW_CH3_S => sync_rx_los_low,
- LSM_STATUS_CH3_S => sync_lsm_status,
- RX_CDR_LOL_CH3_S => sync_rx_cdr_lol,
- TX_DIV2_MODE_CH3_C => '0',
- RX_DIV2_MODE_CH3_C => '0',
-
- SCI_WRDATA => sci_data_in_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_RDDATA => sci_data_out_i,
- SCI_SEL_QUAD => sci_addr_i(8),
- SCI_RD => sci_read_i,
- SCI_WRN => sci_write_i,
- FPGA_TXREFCLK => clk_txref,
--- FPGA_TXREFCLK => rx_full_clk,
- TX_SERDES_RST_C => CLEAR,
- TX_PLL_LOL_QD_S => link_error(5),
- TX_SYNC_QD_C => '0',
- RST_QD_C => rst_qd,
- REFCLK2FPGA => open,
- SERDES_RST_QD_C => ffc_quad_rst
- );
-
--------------------------------------------------------------------------
--- RX Fifo & Data output
--------------------------------------------------------------------------
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
-generic map(
- USE_STATUS_FLAGS => c_NO
- )
-port map( read_clock_in => clk_sys,
- write_clock_in => clk_rx, -- CHANGED
- read_enable_in => fifo_rx_rd_en,
- write_enable_in => fifo_rx_wr_en,
- fifo_gsr_in => fifo_rx_reset,
- write_data_in => fifo_rx_din,
- read_data_out => fifo_rx_dout,
- full_out => fifo_rx_full,
- empty_out => fifo_rx_empty
- );
-
-fifo_rx_reset <= reset_i or not rx_allow_q;
-fifo_rx_rd_en <= not fifo_rx_empty;
-
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process
- begin
- wait until rising_edge(clk_rx); --CHANGED
- last_rx <= rx_k(1) & rx_data(15 downto 8);
- if( swap_bytes = '0' ) then
- fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
- fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
- else
- fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
- fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
- end if;
- end process THE_BYTE_SWAP_PROC;
-
-buf_med_data_out <= fifo_rx_dout(15 downto 0);
-buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
-buf_med_packet_num_out <= rx_counter;
-med_read_out <= tx_allow_q and not fifo_tx_almost_full;
-
-
-THE_CNT_RESET_PROC : process
- begin
- wait until rising_edge(clk_rx); --CHANGED
- if reset_i_rx = '1' then
- send_reset_words <= '0';
- make_trbnet_reset <= '0';
- reset_word_cnt <= (others => '0');
- else
- send_reset_words <= '0';
- make_trbnet_reset <= '0';
- if fifo_rx_din = "11" & x"FEFE" then
- if reset_word_cnt(4) = '0' then
- reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
- else
- send_reset_words <= '1';
- end if;
- else
- reset_word_cnt <= (others => '0');
- make_trbnet_reset <= reset_word_cnt(4);
- end if;
- end if;
- end process;
-
-
-THE_SYNC_PROC: process
- begin
- wait until rising_edge(clk_sys);
- med_dataready_out <= buf_med_dataready_out;
- med_data_out <= buf_med_data_out;
- med_packet_num_out <= buf_med_packet_num_out;
- if reset_i = '1' then
- med_dataready_out <= '0';
- end if;
- end process;
-
-
---rx packet counter
----------------------
-THE_RX_PACKETS_PROC: process( clk_sys )
- begin
- if( rising_edge(clk_sys) ) then
- last_fifo_rx_empty <= fifo_rx_empty;
- if reset_i = '1' or rx_allow_q = '0' then
- rx_counter <= c_H0;
- else
- if( buf_med_dataready_out = '1' ) then
- if( rx_counter = c_max_word_number ) then
- rx_counter <= (others => '0');
- else
- rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
- end if;
- end if;
- end if;
- end if;
- end process;
-
---TX Fifo & Data output to Serdes
----------------------
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map( read_clock_in => clk_tx,
- write_clock_in => clk_sys,
- read_enable_in => fifo_tx_rd_en,
- write_enable_in => fifo_tx_wr_en,
- fifo_gsr_in => fifo_tx_reset,
- write_data_in => fifo_tx_din,
- read_data_out => fifo_tx_dout,
- full_out => fifo_tx_full,
- empty_out => fifo_tx_empty,
- almost_full_out => fifo_tx_almost_full
- );
-
-fifo_tx_reset <= reset_i or not tx_allow_q;
-fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
-fifo_tx_rd_en <= tx_allow_qtx;
-
-
-THE_SERDES_INPUT_PROC: process( clk_tx )
- begin
- if( rising_edge(clk_tx) ) then
- last_fifo_tx_empty <= fifo_tx_empty;
- first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
- if send_reset_in = '1' then
- tx_data <= x"FEFE";
- tx_k <= "11";
- elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
- tx_data <= x"50bc";
- tx_k <= "01";
- tx_correct <= first_idle & '0';
- else
- tx_data <= fifo_tx_dout(15 downto 0);
- tx_k <= "00";
- tx_correct <= "00";
- end if;
- end if;
- end process THE_SERDES_INPUT_PROC;
-
-
--- map 8-bit dlm on 18-bit fifo
-syncfifo_din(7 downto 0) <= SYNC_dlm_WORD_IN;
-syncfifo_din(17 downto 8) <= (others => '0');
---sync_dlm_word_S <= syncfifo_dout(7 downto 0);
-
-sync_dlm_tx: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map(
- read_clock_in => sync_tx_full_clk,
- write_clock_in => sync_rx_full_clk,
- read_enable_in => dlm_fifo_rd_en,
- write_enable_in => SYNC_dlm_IN,
- fifo_gsr_in => reset,
- write_data_in => syncfifo_din,
- read_data_out => syncfifo_dout,
- full_out => open,
- empty_out => dlm_fifo_empty
- );
-
-sync_rx_proc : process(sync_rx_full_clk)
-begin
- if rising_edge(sync_rx_full_clk) then
- SYNC_DLM_OUT <= '0';
- if dlm_received_S='1' then
- dlm_received_S <= '0';
- SYNC_DLM_OUT <= '1';
- SYNC_dlm_WORD_OUT <= sync_rx_data;
- elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
- dlm_received_S <= '1';
- end if;
- end if;
-end process;
-
-sync_tx_proc : process(sync_tx_full_clk)
-begin
- if rising_edge(sync_tx_full_clk) then
- if dlm_fifo_rd_en='1' then
- dlm_fifo_rd_en <= '0';
- sync_tx_data <= syncfifo_dout(7 downto 0);
- sync_tx_k <= '0';
- elsif (dlm_fifo_empty='0') and (dlm_fifo_reading='1') then
- dlm_fifo_rd_en <= '1';
- sync_tx_data <= x"DC";
- sync_tx_k <= '1';
- elsif dlm_fifo_empty='0' then
- dlm_fifo_reading <= '1';
- dlm_fifo_rd_en <= '0';
- sync_tx_data <= x"BC"; -- idle
- sync_tx_k <= '1';
- else
- dlm_fifo_reading <= '0';
- dlm_fifo_rd_en <= '0';
- sync_tx_data <= x"BC"; -- idle
- sync_tx_k <= '1';
- end if;
- end if;
-end process;
-\r
-link_error(8) <= trb_rx_los_low; -- loss of signal
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock
-
-reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';
-
--------------------------------------------------
--- Reset FSM & Link states
--------------------------------------------------
-THE_RX_FSM1: rx_reset_fsm
- port map(
- RST_N => reset_n,
- RX_REFCLK => OSCCLK,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RX_SERDES_RST_CH_C => trb_rx_serdes_rst,
- RX_CDR_LOL_CH_S => trb_rx_cdr_lol,
- RX_LOS_LOW_CH_S => trb_rx_los_low,
- RX_PCS_RST_CH_C => trb_rx_pcs_rst,
- WA_POSITION => "0000",
- STATE_OUT => trb_rx_fsm_state
- );
-
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';
-\r
-THE_TX_FSM1: tx_reset_fsm
- port map(
- RST_N => reset_n,
- TX_REFCLK => OSCCLK,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RST_QD_C => rst_qd1,
- TX_PCS_RST_CH_C => trb_tx_pcs_rst,
- STATE_OUT => trb_tx_fsm_state --open
- );
-
-THE_RX_FSM3: rx_reset_fsm
- port map(
- RST_N => reset_n,
- RX_REFCLK => sync_rx_full_clk,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RX_SERDES_RST_CH_C => sync_rx_serdes_rst,
- RX_CDR_LOL_CH_S => sync_rx_cdr_lol,
- RX_LOS_LOW_CH_S => sync_rx_los_low,
- RX_PCS_RST_CH_C => sync_rx_pcs_rst,
- WA_POSITION => sync_wa_position_rx(11 downto 8),
- STATE_OUT => sync_rx_fsm_state
- );\r
-\r
-SYNC_WA_POSITION : process(sync_rx_full_clk) --??CLK)
-begin
- if rising_edge(sync_rx_full_clk) then
- sync_wa_position_rx <= wa_position;
- end if;
-end process;
-
-THE_TX_FSM3 : tx_reset_fsm
- port map(
- RST_N => reset_n,
- TX_REFCLK => OSCCLK,
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
- RST_QD_C => rst_qd3,
- TX_PCS_RST_CH_C => sync_tx_pcs_rst,
- STATE_OUT => sync_tx_fsm_state
- );
-\r
---rst_qd <= '1' when (rst_qd1='1') or (rst_qd3='1') else '0';
-rst_qd <= RESET;
-\r
-TX_READY_CH3 <= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';
-\r
------------------------------------------------------------------------------------------------------
--- SCI --gives access to serdes config port from slow control and reads word alignment every ~ 40 us
------------------------------------------------------------------------------------------------------
-PROC_SCI_CTRL: process(clk_sys)
- variable cnt : integer range 0 to 4 := 0;
-begin
- if( rising_edge(clk_sys) ) then
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer <= sci_timer + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- elsif sci_timer(sci_timer'left) = '1' then
- sci_timer <= (others => '0');
- sci_state <= GET_WA;
- end if;
- when SCTRL =>
- if sci_reg_i = '1' then
- --// SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_DATA_OUT <= (others => '0');
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
- when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
- when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
- when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
- when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
- when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
- when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
- when GET_WA_FINISH =>
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
- end case;
-
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
- else
- SCI_NACK <= '0';
- end if;
- end if;
-end process PROC_SCI_CTRL;
-
-----------------------
---Generate LED signals
-----------------------
-LED_PROC : process( clk_sys )
- begin
- if rising_edge(clk_sys) then
- led_counter <= led_counter + to_unsigned(1,1);
- if buf_med_dataready_out = '1' then
- rx_led <= '1';
- elsif led_counter = 0 then
- rx_led <= '0';
- end if;
- if tx_k(0) = '0' then
- tx_led <= '1';
- elsif led_counter = 0 then
- tx_led <= '0';
- end if;
- end if;
- end process LED_PROC;
-
-
-stat_op(15) <= send_reset_words_q;
-stat_op(14) <= buf_stat_op(14);
-stat_op(13) <= make_trbnet_reset_q;
-stat_op(12) <= '0';
-stat_op(11) <= tx_led; --tx led
-stat_op(10) <= rx_led; --rx led
-stat_op(9 downto 0) <= buf_stat_op(9 downto 0);
-
--- Debug output
-stat_debug(15 downto 0) <= rx_data;
-stat_debug(17 downto 16) <= rx_k;
-stat_debug(19 downto 18) <= (others => '0');
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
-stat_debug(24) <= fifo_rx_rd_en;
-stat_debug(25) <= fifo_rx_wr_en;
-stat_debug(26) <= fifo_rx_reset;
-stat_debug(27) <= fifo_rx_empty;
-stat_debug(28) <= fifo_rx_full;
-stat_debug(29) <= last_rx(8);
-stat_debug(30) <= rx_allow_q;
-stat_debug(41 downto 31) <= (others => '0');
-stat_debug(42) <= clk_sys;
-stat_debug(43) <= clk_sys;
-stat_debug(59 downto 44) <= (others => '0');
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
-
-
-end Cu_trb_net16_soda_sync_ecp3_sfp_arch;
\ No newline at end of file
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-library work;
-use work.trb_net_std.all;
-
-
---this implementation uses IBM-CRC-16, i.e. x16 + x15 + x2 + 1
-
-
-entity trb_net_CRC is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- CRC_OUT : out std_logic_vector(15 downto 0);
- CRC_match : out std_logic
- );
-end entity;
-
-
-architecture trb_net_CRC_arch of trb_net_CRC is
-signal D,C, next_CRC_OUT, CRC : std_logic_vector(15 downto 0) := x"0000";
-
-begin
- D <= DATA_IN;
- C <= CRC;
- CRC_OUT <= CRC;
- CRC_match <= not or_all(CRC);
-
- next_CRC_OUT(0) <= D(15) xor D(13) xor D(12) xor D(11) xor D(10) xor D(9) xor
- D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor
- D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor
- C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor
- C(9) xor C(10) xor C(11) xor C(12) xor C(13) xor C(15);
- next_CRC_OUT(1) <= D(14) xor D(13) xor D(12) xor D(11) xor D(10) xor D(9) xor
- D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor
- D(2) xor D(1) xor C(1) xor C(2) xor C(3) xor C(4) xor
- C(5) xor C(6) xor C(7) xor C(8) xor C(9) xor C(10) xor
- C(11) xor C(12) xor C(13) xor C(14);
- next_CRC_OUT(2) <= D(14) xor D(1) xor D(0) xor C(0) xor C(1) xor C(14);
- next_CRC_OUT(3) <= D(15) xor D(2) xor D(1) xor C(1) xor C(2) xor C(15);
- next_CRC_OUT(4) <= D(3) xor D(2) xor C(2) xor C(3);
- next_CRC_OUT(5) <= D(4) xor D(3) xor C(3) xor C(4);
- next_CRC_OUT(6) <= D(5) xor D(4) xor C(4) xor C(5);
- next_CRC_OUT(7) <= D(6) xor D(5) xor C(5) xor C(6);
- next_CRC_OUT(8) <= D(7) xor D(6) xor C(6) xor C(7);
- next_CRC_OUT(9) <= D(8) xor D(7) xor C(7) xor C(8);
- next_CRC_OUT(10) <= D(9) xor D(8) xor C(8) xor C(9);
- next_CRC_OUT(11) <= D(10) xor D(9) xor C(9) xor C(10);
- next_CRC_OUT(12) <= D(11) xor D(10) xor C(10) xor C(11);
- next_CRC_OUT(13) <= D(12) xor D(11) xor C(11) xor C(12);
- next_CRC_OUT(14) <= D(13) xor D(12) xor C(12) xor C(13);
- next_CRC_OUT(15) <= D(15) xor D(14) xor D(12) xor D(11) xor D(10) xor D(9) xor
- D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor
- D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor
- C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor
- C(9) xor C(10) xor C(11) xor C(12) xor C(14) xor C(15);
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- CRC <= (others => '0');
- elsif CLK_EN = '1' then
- CRC <= next_CRC_OUT;
- end if;
- end if;
- end process;
-
-end architecture;
-
+++ /dev/null
--------------------------------------------------------------------------------
--- Copyright (C) 2009 OutputLogic.com
--- This source file may be used and distributed without restriction
--- provided that this copyright statement is not removed from the file
--- and that any derivative work contains the original copyright notice
--- and the associated disclaimer.
---
--- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
--- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
--- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--------------------------------------------------------------------------------
--- CRC module for data(7:0)
--- lfsr(7:0)=1+x^4+x^5+x^8;
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net_CRC8 is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- DATA_IN : in std_logic_vector(7 downto 0);
- CRC_OUT : out std_logic_vector(7 downto 0);
- CRC_match : out std_logic
- );
-end entity;
-
-architecture imp_crc of trb_net_CRC8 is
-
- signal lfsr_q: std_logic_vector (7 downto 0);
- signal lfsr_c: std_logic_vector (7 downto 0);
-
- begin
-
- CRC_OUT <= lfsr_q;
- CRC_match <= not or_all(lfsr_c);
-
- lfsr_c(0) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor data_in(0) xor data_in(3) xor data_in(4) xor data_in(6);
- lfsr_c(1) <= lfsr_q(1) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor data_in(1) xor data_in(4) xor data_in(5) xor data_in(7);
- lfsr_c(2) <= lfsr_q(2) xor lfsr_q(5) xor lfsr_q(6) xor data_in(2) xor data_in(5) xor data_in(6);
- lfsr_c(3) <= lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(3) xor data_in(6) xor data_in(7);
- lfsr_c(4) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(0) xor data_in(3) xor data_in(6) xor data_in(7);
- lfsr_c(5) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(0) xor data_in(1) xor data_in(3) xor data_in(6) xor data_in(7);
- lfsr_c(6) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(7) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(7);
- lfsr_c(7) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor data_in(2) xor data_in(3) xor data_in(5);
-
-
- process (CLK) begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- lfsr_q <= b"00000000";
- elsif (CLK_EN = '1') then
- lfsr_q <= lfsr_c;
- end if;
- end if;
- end process;
-end architecture imp_crc;
\ No newline at end of file
+++ /dev/null
-The place for all IP cores used for Soda.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="ctsc" device="LFE3-150EA-8FN672C" default_implementation="ctsc">
- <Options/>
- <Implementation title="ctsc" dir="ctsc" description="ctsc" synthesis="synplify" default_strategy="Strategy1">
- <Options def_top="Cu_trb3_periph_soda_client" top="Cu_trb3_periph_soda_client"/>
- <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_client.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_2_200_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_2_200_int.lpc" type="LPC_Module" type_short="LPC">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_2_200_int.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
- <Source name="code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/Cu_trb3_periph_soda_client.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="Cu_trb3_periph_soda_client"/>
- </Source>
- <Source name="ctsc.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- <Source name="ctsc.rvl" type="Reveal" type_short="Reveal">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="ctsc1.sty"/>
-</BaliProject>
+++ /dev/null
-rvl_alias "soda_rx_full_clk" "trb_media_and_soda_sync_uplink/sync_rx_full_clk_out";
-BLOCK RESETPATHS;
-BLOCK ASYNCPATHS;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
-DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
-LOCATE COMP "FPGA5_COMM_10" SITE "V10";
-LOCATE COMP "FPGA5_COMM_11" SITE "W10";
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-#GSR_NET NET "GSR_N";
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "TRB_MEDIA_AND_SODA_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ;
-MULTICYCLE FROM CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ;
-#MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 50 ns;
-
-BLOCK JTAGPATHS ;
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-
-FREQUENCY NET "soda_rx_full_clk" 200.000000 MHz ;
-FREQUENCY NET "soda_rx_half_clk" 100.000000 MHz ;
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="ctsh" device="LFE3-150EA-8FN672C" default_implementation="ctsh">
- <Options/>
- <Implementation title="ctsh" dir="ctsh" description="ctsh" synthesis="synplify" default_strategy="Strategy1">
- <Options def_top="Cu_trb3_periph_soda_hub" top="Cu_trb3_periph_soda_hub"/>
- <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_hub.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_2_200_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_2_200_int.lpc" type="LPC_Module" type_short="LPC">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_2_200_int.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_4_sync_downstream.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_4_sync_downstream.lpc" type="LPC_Module" type_short="LPC">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_4_sync_downstream.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
- <Source name="code/soda_only_ecp3_sfp_4_sync_down.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/Cu_trb3_periph_soda_hub.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="Cu_trb3_periph_soda_hub"/>
- </Source>
- <Source name="ctsh.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- <Source name="ctsh.rvl" type="Reveal" type_short="Reveal">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="ctsh1.sty"/>
-</BaliProject>
+++ /dev/null
-rvl_alias "soda_rxup_full_clk" "trb_media_and_soda_sync_uplink/sync_rx_full_clk_out";
-BLOCK RESETPATHS;
-BLOCK ASYNCPATHS;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;\r
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
-DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
-LOCATE COMP "FPGA5_COMM_10" SITE "V10";
-LOCATE COMP "FPGA5_COMM_11" SITE "W10";
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE_0" SITE "A5" ;
-LOCATE COMP "TEST_LINE_1" SITE "A6" ;
-LOCATE COMP "TEST_LINE_2" SITE "G8" ;
-LOCATE COMP "TEST_LINE_3" SITE "F9" ;
-LOCATE COMP "TEST_LINE_4" SITE "D9" ;
-LOCATE COMP "TEST_LINE_5" SITE "D10" ;
-LOCATE COMP "TEST_LINE_6" SITE "F10" ;
-LOCATE COMP "TEST_LINE_7" SITE "E10" ;
-LOCATE COMP "TEST_LINE_8" SITE "A8" ;
-LOCATE COMP "TEST_LINE_9" SITE "B8" ;
-LOCATE COMP "TEST_LINE_10" SITE "G10" ;
-LOCATE COMP "TEST_LINE_11" SITE "G9" ;
-LOCATE COMP "TEST_LINE_12" SITE "C9" ;
-LOCATE COMP "TEST_LINE_13" SITE "C10" ;
-LOCATE COMP "TEST_LINE_14" SITE "H10" ;
-LOCATE COMP "TEST_LINE_15" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1
-LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3
-LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5
-LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7
-LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15
-LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17
-LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21
-LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23
-LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25
-LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27
-LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35
-LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
-LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2
-LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4
-LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6
-LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8
-LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
-LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18
-LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22
-LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24
-LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26
-LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28
-LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36
-LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38
-LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169
-LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171
-LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173
-LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175
-LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183
-LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185
-LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170
-LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172
-LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174
-LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176
-LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184
-LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE_1" SITE "AA20" ;
-LOCATE COMP "CODE_LINE_0" SITE "Y21" ;
-IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-#GSR_NET NET "GSR_N";
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "TRB_MEDIA_AND_SODA_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SODA_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ;
-MULTICYCLE FROM CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ;
-#MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 50 ns;
-
-BLOCK JTAGPATHS ;
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-
-FREQUENCY NET "soda_rxup_full_clk" 200.000000 MHz ;
-FREQUENCY NET "soda_rxup_half_clk" 100.000000 MHz ;
-FREQUENCY NET "soda_rxdn_full_clk" 200.000000 MHz ;
-FREQUENCY NET "soda_rxdn_half_clk" 100.000000 MHz ;
-#FREQUENCY NET "soda_tx_full_clk" 200.000000 MHz ;
-#FREQUENCY NET "soda_tx_half_clk" 100.000000 MHz ;
\ No newline at end of file
--- /dev/null
+create_clock -period 12.500 -name SGMIICLK_P -waveform {0.000 6.250} [get_ports SGMIICLK_Q0_P]
+#create_clock -period 12.500 -name SGMIICLK_N -waveform {0.000 6.250} [get_ports SGMIICLK_Q0_N]
+create_clock -period 5.000 -name SMA_MGT_REFCLK_P -waveform {0.000 2.500} [get_ports SMA_MGT_REFCLK_P]
+#create_clock -period 5 -name SMA_MGT_REFCLK_N -waveform {0 2.5} [get_ports SMA_MGT_REFCLK_N]
+create_clock -period 4.000 -name Q3_CLK0_MGTREFCLK_P_IPAD -waveform {0.000 2.000} [get_ports Q3_CLK0_MGTREFCLK_P_IPAD]
+#create_clock -period 4.000 -name Q3_CLK0_MGTREFCLK_N_IPAD -waveform {0.000 2.000} [get_ports Q3_CLK0_MGTREFCLK_N_IPAD]
+
+create_clock -period 5.000 -name USER_SMA_CLOCK_P -waveform {0.000 2.500} [get_ports USER_SMA_CLOCK_P]
+set_clock_latency -clock [get_clocks USER_SMA_CLOCK_P] -rise -source -late 1.000 [get_ports SMA_MGT_REFCLK_P]
+
+
+
+
+# GTX_SODAinput
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
+#create_clock -period 5.000 -name GT0_GTREFCLK0_IN [get_pins -hier -filter name=~*gt0_GTX_SODAinput_i*gtxe2_i*GTREFCLK0]
+
+# GTX_dualSODA
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_dualSODA_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_dualSODA_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_dualSODA_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_dualSODA_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt1_GTX_dualSODA_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt1_GTX_dualSODA_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt1_GTX_dualSODA_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt1_GTX_dualSODA_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#create_clock -period 5.000 -name GT0_GTREFCLK0_IN [get_pins -hier -filter name=~*gt0_GTX_dualSODA_i*gtxe2_i*GTREFCLK0]
+#create_clock -period 5.000 -name GT1_GTREFCLK0_IN [get_pins -hier -filter name=~*gt1_GTX_dualSODA_i*gtxe2_i*GTREFCLK0]
+
+# GTX_trb3_2gb
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#create_clock -period 8.000 -name GT0_GTREFCLK0_IN [get_pins -hier -filter name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*GTREFCLK0]
+
+
+
+# rename some clocks:
+#create_generated_clock -name clk_200_i [get_pins THE_MAIN_PLL/U0/mmcm_adv_inst/CLKOUT0]
+#create_generated_clock -name clk_100_i [get_pins THE_MAIN_PLL/U0/mmcm_adv_inst/CLKOUT1]
+#create_generated_clock -name clk_80_i [get_pins THE_MAIN_PLL/U0/mmcm_adv_inst/CLKOUT2]
+# or ???????
+#create_generated_clock -name clk_200_i [get_pins THE_MAIN_PLL/U0/clkout1_buf/O]
+#create_generated_clock -name clk_100_i [get_pins THE_MAIN_PLL/U0/clkout2_buf/O]
+#create_generated_clock -name clk_80_i [get_pins THE_MAIN_PLL/U0/clkout3_buf/O]
+create_generated_clock -name clk_200_i [get_pins THE_MAIN_PLL/inst/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clk_100_i [get_pins THE_MAIN_PLL/inst/mmcm_adv_inst/CLKOUT1]
+create_generated_clock -name clk_80_i [get_pins THE_MAIN_PLL/inst/mmcm_adv_inst/CLKOUT2]
+
+
+
+#create_generated_clock -name clk_rx200_0_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_0/clock100to200_1/U0/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clk_rx200_0_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_0/clock100to200_1/inst/mmcm_adv_inst/CLKOUT0]
+#create_generated_clock -name clk_rx200_1_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_1/clock100to200_1/U0/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clk_rx200_1_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT0]
+#//create_generated_clock -name clk_rx200_2_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_2/clock100to200_1/U0/mmcm_adv_inst/CLKOUT0]
+#//create_generated_clock -name clk_rx200_3_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_3/clock100to200_1/U0/mmcm_adv_inst/CLKOUT0]
+#create_generated_clock -name clk_tx200 [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/clock100to200a/U0/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clk_tx200 [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/clock100to200a/inst/mmcm_adv_inst/CLKOUT0]
+
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/clk_out]
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/clkout1_buf/O]
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/clkout1_buf/I]
+
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/U0/plle2_adv_inst/CLKOUT0]
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/U0/clkout1_buf/O]
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/U0/clk_out1]
+
+
+#THE_DATAOUTPUT/GTX_dataoutput_support_i/GTX_dataoutput_init_i/U0/GTX_dataoutput_i/gt0_GTX_dataoutput_i/gtxe2_i/TXUSRCLK2
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_dataoutput_i*gtxe2_i*TXUSRCLK2]] -to [get_clocks -include_generated_clocks clk_80_i]
+
+####################### GT reference clock constraints #########################
+
+# TRBnet fifo clocks asynchronous to system clock:
+create_clock -period 8.000 -name GT0_GTREFCLK0_IN [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*GTREFCLK0]
+create_clock -period 8.000 [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]
+create_clock -period 10.000 [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]] -to [get_clocks -include_generated_clocks clk_80_i]
+
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]] -to [get_clocks -include_generated_clocks clk_100_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]] -to [get_clocks -include_generated_clocks clk_100_i]
+
+# system clocks asynchronous to ease timing:
+set_false_path -from [get_clocks -include_generated_clocks clk_200_i] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks clk_200_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks clk_100_i]
+
+# SODA serdes clocks asynchronous to system clocks:
+set_false_path -from [get_clocks -include_generated_clocks clk_tx200] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_tx200] -to [get_clocks -include_generated_clocks clk_100_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks clk_tx200]
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks clk_tx200]
+
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_0_i] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_1_i] -to [get_clocks -include_generated_clocks clk_80_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_2_i] -to [get_clocks -include_generated_clocks clk_80_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_3_i] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_0_i] -to [get_clocks -include_generated_clocks clk_100_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_1_i] -to [get_clocks -include_generated_clocks clk_100_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_2_i] -to [get_clocks -include_generated_clocks clk_100_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_3_i] -to [get_clocks -include_generated_clocks clk_100_i]
+
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_2_i] -to [get_clocks -include_generated_clocks clk_SODA200_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_3_i] -to [get_clocks -include_generated_clocks clk_SODA200_i]
+
+
+
+set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt0_rxresetdone_r3_reg]
+set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt1_rxresetdone_r3_reg]
+#//set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt2_rxresetdone_r3_reg]
+#//set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt3_rxresetdone_r3_reg]
+set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt0_txfsmresetdone_r2_reg]
+set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt1_txfsmresetdone_r2_reg]
+#//set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt2_txfsmresetdone_r2_reg]
+#//set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt3_txfsmresetdone_r2_reg]
+
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_r*/CLR}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_r*/CLR}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_r*/D}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_r*/D}]
+
+# SODA_input GTX constraints
+#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}]
+#set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells GTX_SODAinput_support_i/GTX_SODAinput_init_i/U0/GTX_SODAinput_i/gt0_GTX_SODAinput_i/gtxe2_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks clk_100_i]
+
+
+# no critical timing for external ports:
+set_false_path -to [get_ports {fmc_led[0]}]
+set_false_path -to [get_ports {fmc_led[1]}]
+set_false_path -to [get_ports {fmc_led[2]}]
+set_false_path -to [get_ports {fmc_led[3]}]
+
+set_false_path -from [get_ports {fmc_sfp_los[0]}]
+set_false_path -from [get_ports {fmc_sfp_los[1]}]
+set_false_path -from [get_ports {fmc_sfp_los[2]}]
+set_false_path -from [get_ports {fmc_sfp_los[3]}]
+
+set_false_path -to [get_ports {fmc_sfp_tx_disable[0]}]
+set_false_path -to [get_ports {fmc_sfp_tx_disable[1]}]
+set_false_path -to [get_ports {fmc_sfp_tx_disable[2]}]
+set_false_path -to [get_ports {fmc_sfp_tx_disable[3]}]
+
+set_false_path -to [get_ports XADC_GPIO_0]
+set_false_path -to [get_ports XADC_GPIO_1]
+set_false_path -to [get_ports XADC_GPIO_2]
+set_false_path -to [get_ports XADC_GPIO_3]
+
+
+
+create_generated_clock -name clk_160div3_i [get_pins THE_MAIN_PLL/inst/mmcm_adv_inst/CLKOUT3]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_dataoutput_i*gtxe2_i*TXUSRCLK2]] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_200_i] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks clk_200_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks clk_100_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_tx200] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks clk_tx200]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_0_i] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_1_i] -to [get_clocks -include_generated_clocks clk_160div3_i]
+
+set_property BITSTREAM.CONFIG.CONFIGRATE 12 [current_design]
+set_property CONFIG_MODE BPI16 [current_design]
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2015.3 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="10" Path="P:/soda/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/DataConcentrator_KC705.xpr">
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+ <Option Name="BoardPart" Val=""/>
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+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
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+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="async_fifo_512x99_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_512x99" Description="Vivado Implementation Defaults" SynthRun="async_fifo_512x99_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="async_fifo_nn_4096x103_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_4096x103" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_4096x103_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="async_fifo_nn_4096x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_4096x36" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_4096x36_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
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+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
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+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
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+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="async_fifo_nn_thfull_FWFT_2048x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_thfull_FWFT_2048x36" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_thfull_FWFT_2048x36_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
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+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="async_fifo_nn_thfull_FWFT_512x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_thfull_FWFT_512x36" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_thfull_FWFT_512x36_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="clock100to200_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="clock100to200" Description="Vivado Implementation Defaults" SynthRun="clock100to200_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
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+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="fifo_18x512_oreg_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_18x512_oreg" Description="Vivado Implementation Defaults" SynthRun="fifo_18x512_oreg_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
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+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="fifo_36x16k_oreg_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_36x16k_oreg" Description="Vivado Implementation Defaults" SynthRun="fifo_36x16k_oreg_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
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+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="fifo_36x32k_oreg_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_36x32k_oreg" Description="Vivado Implementation Defaults" SynthRun="fifo_36x32k_oreg_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
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+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="fifo_36x512_oreg_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_36x512_oreg" Description="Vivado Implementation Defaults" SynthRun="fifo_36x512_oreg_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
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+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="pll_in200_out200_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pll_in200_out200" Description="Vivado Implementation Defaults" SynthRun="pll_in200_out200_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
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+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="sync_fifo_512x41_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="sync_fifo_512x41" Description="Vivado Implementation Defaults" SynthRun="sync_fifo_512x41_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="xilinx_fifo_18x16_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x16" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x16_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="xilinx_fifo_18x1k_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x1k" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x1k_synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
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+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="xilinx_fifo_18x1k_datacount_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x1k_datacount" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x1k_datacount_synth_1" IncludeInArchive="true">
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+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="xilinx_fifo_18x32_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x32" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x32_synth_1" IncludeInArchive="true">
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+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
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+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="xilinx_fifo_18x64_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x64" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x64_synth_1" IncludeInArchive="true">
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+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="xilinx_fifo_19x16_obuf_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_19x16_obuf" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_19x16_obuf_synth_1" IncludeInArchive="true">
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+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ <Run Id="xilinx_fifo_dualport_18x1k_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_dualport_18x1k" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_dualport_18x1k_synth_1" IncludeInArchive="true">
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+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
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+ </Run>
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+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
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+ </Run>
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+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
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+ <Step Id="phys_opt_design"/>
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+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
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+ <Step Id="opt_design"/>
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+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ </Run>
+ </Runs>
+</Project>
--- /dev/null
+set_property PACKAGE_PIN Y20 [get_ports SFP_TX_DISABLE]
+set_property IOSTANDARD LVCMOS25 [get_ports SFP_TX_DISABLE]
+
+set_property PACKAGE_PIN Y23 [get_ports USER_SMA_GPIO_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_GPIO_P]
+set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_P]
+set_property PACKAGE_PIN Y24 [get_ports USER_SMA_GPIO_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_GPIO_N]
+set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_N]
+
+#set_property PACKAGE_PIN Y21 [get_ports SDIO_SDWP]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_SDWP]
+#set_property PACKAGE_PIN AA21 [get_ports SDIO_SDDET]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_SDDET]
+#set_property PACKAGE_PIN AB22 [get_ports SDIO_CMD_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_CMD_LS]
+#set_property PACKAGE_PIN AB23 [get_ports SDIO_CLK_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_CLK_LS]
+#set_property PACKAGE_PIN AA22 [get_ports SDIO_DAT2_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_DAT2_LS]
+#set_property PACKAGE_PIN AA23 [get_ports SDIO_DAT1_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_DAT1_LS]
+#set_property PACKAGE_PIN AC20 [get_ports SDIO_DAT0_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_DAT0_LS]
+#set_property PACKAGE_PIN AC21 [get_ports SDIO_CD_DAT3_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_CD_DAT3_LS]
+#set_property PACKAGE_PIN AA20 [get_ports FMC_LPC_LA12_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA12_P]
+#set_property PACKAGE_PIN AB20 [get_ports FMC_LPC_LA12_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA12_N]
+#set_property PACKAGE_PIN AB24 [get_ports FMC_LPC_LA13_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA13_P]
+#set_property PACKAGE_PIN AC25 [get_ports FMC_LPC_LA13_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA13_N]
+#set_property PACKAGE_PIN AC22 [get_ports FMC_LPC_LA16_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA16_P]
+#set_property PACKAGE_PIN AD22 [get_ports FMC_LPC_LA16_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA16_N]
+#set_property PACKAGE_PIN AC24 [get_ports FMC_LPC_LA15_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA15_P]
+#set_property PACKAGE_PIN AD24 [get_ports FMC_LPC_LA15_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA15_N]
+#set_property PACKAGE_PIN AD21 [get_ports FMC_LPC_LA14_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA14_P]
+#set_property PACKAGE_PIN AE21 [get_ports FMC_LPC_LA14_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA14_N]
+#set_property PACKAGE_PIN AE23 [get_ports FMC_LPC_LA01_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA01_CC_P]
+#set_property PACKAGE_PIN AF23 [get_ports FMC_LPC_LA01_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA01_CC_N]
+#set_property PACKAGE_PIN AD23 [get_ports FMC_LPC_LA00_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA00_CC_P]
+#set_property PACKAGE_PIN AE24 [get_ports FMC_LPC_LA00_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA00_CC_N]
+#set_property PACKAGE_PIN AF22 [get_ports FMC_LPC_CLK0_M2C_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK0_M2C_P]
+#set_property PACKAGE_PIN AG23 [get_ports FMC_LPC_CLK0_M2C_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK0_M2C_N]
+#set_property PACKAGE_PIN AG24 [get_ports SI5326_INT_ALM_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SI5326_INT_ALM_LS]
+#set_property PACKAGE_PIN AH24 [get_ports HDMI_INT]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_INT]
+#set_property PACKAGE_PIN AJ24 [get_ports FMC_LPC_LA10_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA10_P]
+#set_property PACKAGE_PIN AK25 [get_ports FMC_LPC_LA10_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA10_N]
+#set_property PACKAGE_PIN AE25 [get_ports FMC_LPC_LA11_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA11_P]
+#set_property PACKAGE_PIN AF25 [get_ports FMC_LPC_LA11_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA11_N]
+#set_property PACKAGE_PIN AK23 [get_ports FMC_LPC_LA09_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA09_P]
+#set_property PACKAGE_PIN AK24 [get_ports FMC_LPC_LA09_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA09_N]
+#set_property PACKAGE_PIN AG25 [get_ports FMC_LPC_LA07_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA07_P]
+#set_property PACKAGE_PIN AH25 [get_ports FMC_LPC_LA07_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA07_N]
+#set_property PACKAGE_PIN AF20 [get_ports FMC_LPC_LA02_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA02_P]
+#set_property PACKAGE_PIN AF21 [get_ports FMC_LPC_LA02_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA02_N]
+#set_property PACKAGE_PIN AG22 [get_ports FMC_LPC_LA05_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA05_P]
+#set_property PACKAGE_PIN AH22 [get_ports FMC_LPC_LA05_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA05_N]
+#set_property PACKAGE_PIN AJ22 [get_ports FMC_LPC_LA08_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA08_P]
+#set_property PACKAGE_PIN AJ23 [get_ports FMC_LPC_LA08_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA08_N]
+#set_property PACKAGE_PIN AG20 [get_ports FMC_LPC_LA03_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA03_P]
+#set_property PACKAGE_PIN AH20 [get_ports FMC_LPC_LA03_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA03_N]
+#set_property PACKAGE_PIN AH21 [get_ports FMC_LPC_LA04_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA04_P]
+#set_property PACKAGE_PIN AJ21 [get_ports FMC_LPC_LA04_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA04_N]
+#set_property PACKAGE_PIN AK20 [get_ports FMC_LPC_LA06_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA06_P]
+#set_property PACKAGE_PIN AK21 [get_ports FMC_LPC_LA06_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA06_N]
+#set_property PACKAGE_PIN AE20 [get_ports SI5326_RST_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SI5326_RST_LS]
+#set_property PACKAGE_PIN Y25 [get_ports ROTARY_INCB]
+#set_property IOSTANDARD LVCMOS25 [get_ports ROTARY_INCB]
+#set_property PACKAGE_PIN Y26 [get_ports ROTARY_INCA]
+#set_property IOSTANDARD LVCMOS25 [get_ports ROTARY_INCA]
+#set_property PACKAGE_PIN AA26 [get_ports ROTARY_PUSH]
+#set_property IOSTANDARD LVCMOS25 [get_ports ROTARY_PUSH]
+set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_P]
+set_property PACKAGE_PIN W28 [get_ports REC_CLOCK_C_N]
+set_property PACKAGE_PIN W27 [get_ports REC_CLOCK_C_P]
+set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N]
+#set_property PACKAGE_PIN Y28 [get_ports GPIO_DIP_SW3]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW3]
+#set_property PACKAGE_PIN AA28 [get_ports GPIO_DIP_SW2]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW2]
+#set_property PACKAGE_PIN W29 [get_ports GPIO_DIP_SW1]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW1]
+#set_property PACKAGE_PIN Y29 [get_ports GPIO_DIP_SW0]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW0]
+set_property PACKAGE_PIN AA27 [get_ports XADC_GPIO_3]
+set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3]
+set_property PACKAGE_PIN AB28 [get_ports XADC_GPIO_2]
+set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2]
+set_property PACKAGE_PIN AA25 [get_ports XADC_GPIO_1]
+set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1]
+set_property PACKAGE_PIN AB25 [get_ports XADC_GPIO_0]
+set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0]
+#set_property PACKAGE_PIN AC29 [get_ports FMC_LPC_LA33_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA33_P]
+#set_property PACKAGE_PIN AC30 [get_ports FMC_LPC_LA33_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA33_N]
+#set_property PACKAGE_PIN Y30 [get_ports FMC_LPC_LA32_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA32_P]
+#set_property PACKAGE_PIN AA30 [get_ports FMC_LPC_LA32_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA32_N]
+#set_property PACKAGE_PIN AD29 [get_ports FMC_LPC_LA31_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA31_P]
+#set_property PACKAGE_PIN AE29 [get_ports FMC_LPC_LA31_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA31_N]
+#set_property PACKAGE_PIN AB29 [get_ports FMC_LPC_LA30_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA30_P]
+#set_property PACKAGE_PIN AB30 [get_ports FMC_LPC_LA30_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA30_N]
+#set_property PACKAGE_PIN AD27 [get_ports FMC_LPC_LA18_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA18_CC_P]
+#set_property PACKAGE_PIN AD28 [get_ports FMC_LPC_LA18_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA18_CC_N]
+#set_property PACKAGE_PIN AB27 [get_ports FMC_LPC_LA17_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA17_CC_P]
+#set_property PACKAGE_PIN AC27 [get_ports FMC_LPC_LA17_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA17_CC_N]
+#set_property PACKAGE_PIN AG29 [get_ports FMC_LPC_CLK1_M2C_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK1_M2C_P]
+#set_property PACKAGE_PIN AH29 [get_ports FMC_LPC_CLK1_M2C_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK1_M2C_N]
+#set_property PACKAGE_PIN AE28 [get_ports FMC_LPC_LA29_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA29_P]
+#set_property PACKAGE_PIN AF28 [get_ports FMC_LPC_LA29_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA29_N]
+#set_property PACKAGE_PIN AK29 [get_ports FMC_LPC_LA26_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA26_P]
+#set_property PACKAGE_PIN AK30 [get_ports FMC_LPC_LA26_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA26_N]
+#set_property PACKAGE_PIN AE30 [get_ports FMC_LPC_LA28_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA28_P]
+#set_property PACKAGE_PIN AF30 [get_ports FMC_LPC_LA28_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA28_N]
+#set_property PACKAGE_PIN AJ28 [get_ports FMC_LPC_LA27_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA27_P]
+#set_property PACKAGE_PIN AJ29 [get_ports FMC_LPC_LA27_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA27_N]
+#set_property PACKAGE_PIN AG30 [get_ports FMC_LPC_LA24_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA24_P]
+#set_property PACKAGE_PIN AH30 [get_ports FMC_LPC_LA24_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA24_N]
+#set_property PACKAGE_PIN AC26 [get_ports FMC_LPC_LA25_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA25_P]
+#set_property PACKAGE_PIN AD26 [get_ports FMC_LPC_LA25_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA25_N]
+#set_property PACKAGE_PIN AJ27 [get_ports FMC_LPC_LA22_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA22_P]
+#set_property PACKAGE_PIN AK28 [get_ports FMC_LPC_LA22_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA22_N]
+#set_property PACKAGE_PIN AG27 [get_ports FMC_LPC_LA21_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA21_P]
+#set_property PACKAGE_PIN AG28 [get_ports FMC_LPC_LA21_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA21_N]
+#set_property PACKAGE_PIN AH26 [get_ports FMC_LPC_LA23_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA23_P]
+#set_property PACKAGE_PIN AH27 [get_ports FMC_LPC_LA23_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA23_N]
+#set_property PACKAGE_PIN AF26 [get_ports FMC_LPC_LA20_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA20_P]
+#set_property PACKAGE_PIN AF27 [get_ports FMC_LPC_LA20_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA20_N]
+#set_property PACKAGE_PIN AJ26 [get_ports FMC_LPC_LA19_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA19_P]
+#set_property PACKAGE_PIN AK26 [get_ports FMC_LPC_LA19_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA19_N]
+#set_property PACKAGE_PIN AE26 [get_ports GPIO_LED_4_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_4_LS]
+#set_property PACKAGE_PIN R19 [get_ports PHY_RXD4]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD4]
+#set_property PACKAGE_PIN P24 [get_ports FLASH_D0]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D0]
+#set_property PACKAGE_PIN R25 [get_ports FLASH_D1]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D1]
+#set_property PACKAGE_PIN R20 [get_ports FLASH_D2]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D2]
+#set_property PACKAGE_PIN R21 [get_ports FLASH_D3]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D3]
+#set_property PACKAGE_PIN R23 [get_ports PHY_MDC]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_MDC]
+#set_property PACKAGE_PIN R24 [get_ports FPGA_EMCCLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports FPGA_EMCCLK]
+#set_property PACKAGE_PIN T20 [get_ports FLASH_D4]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D4]
+#set_property PACKAGE_PIN T21 [get_ports FLASH_D5]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D5]
+#set_property PACKAGE_PIN T22 [get_ports FLASH_D6]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D6]
+#set_property PACKAGE_PIN T23 [get_ports FLASH_D7]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D7]
+#set_property PACKAGE_PIN U19 [get_ports FPGA_FCS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FPGA_FCS]
+#set_property PACKAGE_PIN U20 [get_ports FLASH_D8]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D8]
+#set_property PACKAGE_PIN P29 [get_ports FLASH_D9]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D9]
+#set_property PACKAGE_PIN R29 [get_ports FLASH_D10]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D10]
+#set_property PACKAGE_PIN P27 [get_ports FLASH_D11]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D11]
+#set_property PACKAGE_PIN P28 [get_ports FLASH_D12]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D12]
+#set_property PACKAGE_PIN R30 [get_ports PHY_CRS]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_CRS]
+#set_property PACKAGE_PIN T30 [get_ports FLASH_D13]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D13]
+#set_property PACKAGE_PIN P26 [get_ports FLASH_D14]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D14]
+#set_property PACKAGE_PIN R26 [get_ports FLASH_D15]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D15]
+#set_property PACKAGE_PIN R28 [get_ports PHY_RXCTL_RXDV]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXCTL_RXDV]
+#set_property PACKAGE_PIN T28 [get_ports PHY_RXD7]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD7]
+#set_property PACKAGE_PIN T26 [get_ports PHY_RXD6]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD6]
+#set_property PACKAGE_PIN T27 [get_ports PHY_RXD5]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD5]
+#set_property PACKAGE_PIN U27 [get_ports PHY_RXCLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXCLK]
+#set_property PACKAGE_PIN U28 [get_ports PHY_RXD3]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD3]
+#set_property PACKAGE_PIN T25 [get_ports PHY_RXD2]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD2]
+#set_property PACKAGE_PIN U25 [get_ports PHY_RXD1]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD1]
+#set_property PACKAGE_PIN U29 [get_ports FLASH_WAIT]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_WAIT]
+#set_property PACKAGE_PIN U30 [get_ports PHY_RXD0]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD0]
+#set_property PACKAGE_PIN V26 [get_ports PHY_RXER]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXER]
+#set_property PACKAGE_PIN V27 [get_ports FLASH_A15]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A15]
+#set_property PACKAGE_PIN V29 [get_ports FLASH_A14]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A14]
+#set_property PACKAGE_PIN V30 [get_ports FLASH_A13]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A13]
+#set_property PACKAGE_PIN V25 [get_ports FLASH_A12]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A12]
+#set_property PACKAGE_PIN W26 [get_ports FLASH_A11]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A11]
+#set_property PACKAGE_PIN V19 [get_ports FLASH_A10]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A10]
+#set_property PACKAGE_PIN V20 [get_ports FLASH_A9]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A9]
+#set_property PACKAGE_PIN W23 [get_ports FLASH_A8]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A8]
+#set_property PACKAGE_PIN W24 [get_ports FLASH_A7]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A7]
+#set_property PACKAGE_PIN U22 [get_ports SM_FAN_TACH]
+#set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_TACH]
+#set_property PACKAGE_PIN U23 [get_ports FLASH_A6]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A6]
+#set_property PACKAGE_PIN V21 [get_ports FLASH_A5]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A5]
+#set_property PACKAGE_PIN V22 [get_ports FLASH_A4]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A4]
+#set_property PACKAGE_PIN U24 [get_ports FLASH_A3]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A3]
+#set_property PACKAGE_PIN V24 [get_ports FLASH_A2]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A2]
+#set_property PACKAGE_PIN W21 [get_ports FLASH_A1]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A1]
+#set_property PACKAGE_PIN W22 [get_ports FLASH_A0]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A0]
+#set_property PACKAGE_PIN W19 [get_ports PHY_COL]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_COL]
+#set_property PACKAGE_PIN M19 [get_ports USB_TX]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_TX]
+#set_property PACKAGE_PIN J23 [get_ports XADC_VAUX0P_R]
+#set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0P_R]
+#set_property PACKAGE_PIN J24 [get_ports XADC_VAUX0N_R]
+#set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0N_R]
+#set_property PACKAGE_PIN L22 [get_ports XADC_VAUX8P_R]
+#set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8P_R]
+#set_property PACKAGE_PIN L23 [get_ports XADC_VAUX8N_R]
+#set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8N_R]
+#set_property PACKAGE_PIN K23 [get_ports USB_RTS]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_RTS]
+#set_property PACKAGE_PIN K24 [get_ports USB_RX]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_RX]
+#set_property PACKAGE_PIN L21 [get_ports IIC_SDA_MAIN]
+#set_property IOSTANDARD LVCMOS25 [get_ports IIC_SDA_MAIN]
+#set_property PACKAGE_PIN K21 [get_ports IIC_SCL_MAIN]
+#set_property IOSTANDARD LVCMOS25 [get_ports IIC_SCL_MAIN]
+#set_property PACKAGE_PIN J21 [get_ports PHY_MDIO]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_MDIO]
+#set_property PACKAGE_PIN J22 [get_ports FMC_LPC_PRSNT_M2C_B_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_PRSNT_M2C_B_LS]
+#set_property PACKAGE_PIN M20 [get_ports FMC_HPC_PRSNT_M2C_B_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_PRSNT_M2C_B_LS]
+#set_property PACKAGE_PIN L20 [get_ports PHY_RESET]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RESET]
+#set_property PACKAGE_PIN J29 [get_ports FMC_HPC_PG_M2C_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_PG_M2C_LS]
+#set_property PACKAGE_PIN H29 [get_ports FMC_C2M_PG_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_C2M_PG_LS]
+#set_property PACKAGE_PIN J27 [get_ports FMC_VADJ_ON_B_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_VADJ_ON_B_LS]
+#set_property PACKAGE_PIN J28 [get_ports PHY_TXD7]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD7]
+#set_property PACKAGE_PIN L30 [get_ports PHY_TXD6]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD6]
+#set_property PACKAGE_PIN K30 [get_ports PHY_TXC_GTXCLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXC_GTXCLK]
+#set_property PACKAGE_PIN K26 [get_ports PHY_TXD5]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD5]
+#set_property PACKAGE_PIN J26 [get_ports PHY_TXD4]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD4]
+#set_property PACKAGE_PIN L26 [get_ports SM_FAN_PWM]
+#set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_PWM]
+#set_property PACKAGE_PIN L27 [get_ports USB_CTS]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_CTS]
+set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_P]
+set_property PACKAGE_PIN K25 [get_ports USER_SMA_CLOCK_N]
+set_property PACKAGE_PIN L25 [get_ports USER_SMA_CLOCK_P]
+set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_N]
+#set_property PACKAGE_PIN K28 [get_ports USER_CLOCK_P]
+#set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_P]
+#set_property PACKAGE_PIN K29 [get_ports USER_CLOCK_N]
+#set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_N]
+#set_property PACKAGE_PIN M28 [get_ports PHY_TXCLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXCLK]
+#set_property PACKAGE_PIN L28 [get_ports PHY_TXD3]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD3]
+#set_property PACKAGE_PIN M29 [get_ports PHY_TXD2]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD2]
+#set_property PACKAGE_PIN M30 [get_ports FLASH_ADV_B]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_ADV_B]
+#set_property PACKAGE_PIN N27 [get_ports PHY_TXD0]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD0]
+#set_property PACKAGE_PIN M27 [get_ports PHY_TXCTL_TXEN]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXCTL_TXEN]
+#set_property PACKAGE_PIN N29 [get_ports PHY_TXER]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXER]
+#set_property PACKAGE_PIN N30 [get_ports PHY_INT]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_INT]
+#set_property PACKAGE_PIN N25 [get_ports PHY_TXD1]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD1]
+#set_property PACKAGE_PIN N26 [get_ports FLASH_A23]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A23]
+#set_property PACKAGE_PIN N19 [get_ports FLASH_A22]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A22]
+#set_property PACKAGE_PIN N20 [get_ports FLASH_A21]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A21]
+#set_property PACKAGE_PIN N21 [get_ports FLASH_A20]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A20]
+#set_property PACKAGE_PIN N22 [get_ports FLASH_A19]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A19]
+#set_property PACKAGE_PIN P23 [get_ports IIC_MUX_RESET_B]
+#set_property IOSTANDARD LVCMOS25 [get_ports IIC_MUX_RESET_B]
+#set_property PACKAGE_PIN N24 [get_ports FLASH_A18]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A18]
+#set_property PACKAGE_PIN P21 [get_ports FLASH_A17]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A17]
+#set_property PACKAGE_PIN P22 [get_ports FLASH_A16]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A16]
+#set_property PACKAGE_PIN M24 [get_ports FLASH_OE_B]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_OE_B]
+#set_property PACKAGE_PIN M25 [get_ports FLASH_FWE_B]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_FWE_B]
+#set_property PACKAGE_PIN M22 [get_ports FLASH_A25]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A25]
+#set_property PACKAGE_PIN M23 [get_ports FLASH_A24]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A24]
+set_property PACKAGE_PIN P19 [get_ports SFP_LOS_LS]
+set_property IOSTANDARD LVCMOS25 [get_ports SFP_LOS_LS]
+#set_property PACKAGE_PIN F23 [get_ports PCIE_WAKE_B_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports PCIE_WAKE_B_LS]
+#set_property PACKAGE_PIN B23 [get_ports HDMI_R_D0]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D0]
+#set_property PACKAGE_PIN A23 [get_ports HDMI_R_D1]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D1]
+#set_property PACKAGE_PIN E23 [get_ports HDMI_R_D2]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D2]
+#set_property PACKAGE_PIN D23 [get_ports HDMI_R_D3]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D3]
+#set_property PACKAGE_PIN F25 [get_ports HDMI_R_D4]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D4]
+#set_property PACKAGE_PIN E25 [get_ports HDMI_R_D5]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D5]
+#set_property PACKAGE_PIN E24 [get_ports HDMI_R_D6]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D6]
+#set_property PACKAGE_PIN D24 [get_ports HDMI_R_D7]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D7]
+#set_property PACKAGE_PIN F26 [get_ports HDMI_R_D8]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D8]
+#set_property PACKAGE_PIN E26 [get_ports HDMI_R_D9]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D9]
+#set_property PACKAGE_PIN G23 [get_ports HDMI_R_D10]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D10]
+#set_property PACKAGE_PIN G24 [get_ports HDMI_R_D11]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D11]
+#set_property PACKAGE_PIN B27 [get_ports FMC_HPC_LA16_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_P]
+#set_property PACKAGE_PIN A27 [get_ports FMC_HPC_LA16_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_N]
+#set_property PACKAGE_PIN C24 [get_ports FMC_HPC_LA15_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_P]
+#set_property PACKAGE_PIN B24 [get_ports FMC_HPC_LA15_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_N]
+#set_property PACKAGE_PIN B28 [get_ports FMC_HPC_LA14_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_P]
+#set_property PACKAGE_PIN A28 [get_ports FMC_HPC_LA14_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_N]
+#set_property PACKAGE_PIN A25 [get_ports FMC_HPC_LA13_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_P]
+#set_property PACKAGE_PIN A26 [get_ports FMC_HPC_LA13_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_N]
+#set_property PACKAGE_PIN D26 [get_ports FMC_HPC_LA01_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_P]
+#set_property PACKAGE_PIN C26 [get_ports FMC_HPC_LA01_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_N]
+#set_property PACKAGE_PIN C25 [get_ports FMC_HPC_LA00_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_P]
+#set_property PACKAGE_PIN B25 [get_ports FMC_HPC_LA00_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_N]
+#set_property PACKAGE_PIN D27 [get_ports FMC_HPC_CLK0_M2C_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK0_M2C_P]
+#set_property PACKAGE_PIN C27 [get_ports FMC_HPC_CLK0_M2C_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK0_M2C_N]
+#set_property PACKAGE_PIN E28 [get_ports FMC_HPC_LA07_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_P]
+#set_property PACKAGE_PIN D28 [get_ports FMC_HPC_LA07_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_N]
+#set_property PACKAGE_PIN C29 [get_ports FMC_HPC_LA12_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_P]
+#set_property PACKAGE_PIN B29 [get_ports FMC_HPC_LA12_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_N]
+#set_property PACKAGE_PIN D29 [get_ports FMC_HPC_LA10_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_P]
+#set_property PACKAGE_PIN C30 [get_ports FMC_HPC_LA10_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_N]
+#set_property PACKAGE_PIN B30 [get_ports FMC_HPC_LA09_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_P]
+#set_property PACKAGE_PIN A30 [get_ports FMC_HPC_LA09_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_N]
+#set_property PACKAGE_PIN E29 [get_ports FMC_HPC_LA08_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_P]
+#set_property PACKAGE_PIN E30 [get_ports FMC_HPC_LA08_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_N]
+#set_property PACKAGE_PIN H24 [get_ports FMC_HPC_LA02_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_P]
+#set_property PACKAGE_PIN H25 [get_ports FMC_HPC_LA02_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_N]
+#set_property PACKAGE_PIN G28 [get_ports FMC_HPC_LA04_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_P]
+#set_property PACKAGE_PIN F28 [get_ports FMC_HPC_LA04_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_N]
+#set_property PACKAGE_PIN G27 [get_ports FMC_HPC_LA11_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_P]
+#set_property PACKAGE_PIN F27 [get_ports FMC_HPC_LA11_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_N]
+#set_property PACKAGE_PIN G29 [get_ports FMC_HPC_LA05_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_P]
+#set_property PACKAGE_PIN F30 [get_ports FMC_HPC_LA05_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_N]
+#set_property PACKAGE_PIN H26 [get_ports FMC_HPC_LA03_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_P]
+#set_property PACKAGE_PIN H27 [get_ports FMC_HPC_LA03_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_N]
+#set_property PACKAGE_PIN H30 [get_ports FMC_HPC_LA06_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_P]
+#set_property PACKAGE_PIN G30 [get_ports FMC_HPC_LA06_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_N]
+#set_property PACKAGE_PIN G25 [get_ports PCIE_PERST_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports PCIE_PERST_LS]
+#set_property PACKAGE_PIN G19 [get_ports GPIO_LED_5_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_5_LS]
+#set_property PACKAGE_PIN K18 [get_ports HDMI_R_CLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_CLK]
+#set_property PACKAGE_PIN J18 [get_ports HDMI_R_HSYNC]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_HSYNC]
+#set_property PACKAGE_PIN H20 [get_ports HDMI_R_VSYNC]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_VSYNC]
+#set_property PACKAGE_PIN G20 [get_ports HDMI_SPDIF_OUT_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_SPDIF_OUT_LS]
+#set_property PACKAGE_PIN J17 [get_ports HDMI_R_SPDIF]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_SPDIF]
+#set_property PACKAGE_PIN H17 [get_ports HDMI_R_DE]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_DE]
+#set_property PACKAGE_PIN J19 [get_ports HDMI_R_D12]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D12]
+#set_property PACKAGE_PIN H19 [get_ports HDMI_R_D13]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D13]
+#set_property PACKAGE_PIN L17 [get_ports HDMI_R_D14]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D14]
+#set_property PACKAGE_PIN L18 [get_ports HDMI_R_D15]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D15]
+#set_property PACKAGE_PIN K19 [get_ports HDMI_R_D16]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D16]
+#set_property PACKAGE_PIN K20 [get_ports HDMI_R_D17]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D17]
+#set_property PACKAGE_PIN H21 [get_ports FMC_HPC_LA33_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_P]
+#set_property PACKAGE_PIN H22 [get_ports FMC_HPC_LA33_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_N]
+#set_property PACKAGE_PIN D21 [get_ports FMC_HPC_LA32_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_P]
+#set_property PACKAGE_PIN C21 [get_ports FMC_HPC_LA32_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_N]
+#set_property PACKAGE_PIN G22 [get_ports FMC_HPC_LA31_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_P]
+#set_property PACKAGE_PIN F22 [get_ports FMC_HPC_LA31_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_N]
+#set_property PACKAGE_PIN D22 [get_ports FMC_HPC_LA30_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_P]
+#set_property PACKAGE_PIN C22 [get_ports FMC_HPC_LA30_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_N]
+#set_property PACKAGE_PIN F21 [get_ports FMC_HPC_LA18_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_P]
+#set_property PACKAGE_PIN E21 [get_ports FMC_HPC_LA18_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_N]
+#set_property PACKAGE_PIN F20 [get_ports FMC_HPC_LA17_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_P]
+#set_property PACKAGE_PIN E20 [get_ports FMC_HPC_LA17_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_N]
+#set_property PACKAGE_PIN D17 [get_ports FMC_HPC_CLK1_M2C_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK1_M2C_P]
+#set_property PACKAGE_PIN D18 [get_ports FMC_HPC_CLK1_M2C_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK1_M2C_N]
+#set_property PACKAGE_PIN E19 [get_ports FMC_HPC_LA20_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_P]
+#set_property PACKAGE_PIN D19 [get_ports FMC_HPC_LA20_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_N]
+#set_property PACKAGE_PIN D16 [get_ports FMC_HPC_LA28_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_P]
+#set_property PACKAGE_PIN C16 [get_ports FMC_HPC_LA28_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_N]
+#set_property PACKAGE_PIN G18 [get_ports FMC_HPC_LA19_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_P]
+#set_property PACKAGE_PIN F18 [get_ports FMC_HPC_LA19_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_N]
+#set_property PACKAGE_PIN C17 [get_ports FMC_HPC_LA29_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_P]
+#set_property PACKAGE_PIN B17 [get_ports FMC_HPC_LA29_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_N]
+#set_property PACKAGE_PIN G17 [get_ports FMC_HPC_LA25_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_P]
+#set_property PACKAGE_PIN F17 [get_ports FMC_HPC_LA25_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_N]
+#set_property PACKAGE_PIN C20 [get_ports FMC_HPC_LA22_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_P]
+#set_property PACKAGE_PIN B20 [get_ports FMC_HPC_LA22_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_N]
+#set_property PACKAGE_PIN A16 [get_ports FMC_HPC_LA24_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_P]
+#set_property PACKAGE_PIN A17 [get_ports FMC_HPC_LA24_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_N]
+#set_property PACKAGE_PIN A20 [get_ports FMC_HPC_LA21_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_P]
+#set_property PACKAGE_PIN A21 [get_ports FMC_HPC_LA21_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_N]
+#set_property PACKAGE_PIN B18 [get_ports FMC_HPC_LA26_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_P]
+#set_property PACKAGE_PIN A18 [get_ports FMC_HPC_LA26_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_N]
+#set_property PACKAGE_PIN B22 [get_ports FMC_HPC_LA23_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_P]
+#set_property PACKAGE_PIN A22 [get_ports FMC_HPC_LA23_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_N]
+#set_property PACKAGE_PIN C19 [get_ports FMC_HPC_LA27_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_P]
+#set_property PACKAGE_PIN B19 [get_ports FMC_HPC_LA27_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_N]
+#set_property PACKAGE_PIN E18 [get_ports GPIO_LED_6_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_6_LS]
+set_property PACKAGE_PIN G12 [get_ports GPIO_SW_C]
+set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_C]
+#set_property PACKAGE_PIN L16 [get_ports FMC_HPC_HA13_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA13_P]
+#set_property PACKAGE_PIN K16 [get_ports FMC_HPC_HA13_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA13_N]
+#set_property PACKAGE_PIN L15 [get_ports FMC_HPC_HA16_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA16_P]
+#set_property PACKAGE_PIN K15 [get_ports FMC_HPC_HA16_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA16_N]
+#set_property PACKAGE_PIN L12 [get_ports FMC_HPC_HA23_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA23_P]
+#set_property PACKAGE_PIN L13 [get_ports FMC_HPC_HA23_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA23_N]
+#set_property PACKAGE_PIN K13 [get_ports FMC_HPC_HA20_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA20_P]
+#set_property PACKAGE_PIN J13 [get_ports FMC_HPC_HA20_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA20_N]
+#set_property PACKAGE_PIN K14 [get_ports FMC_HPC_HA18_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA18_P]
+#set_property PACKAGE_PIN J14 [get_ports FMC_HPC_HA18_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA18_N]
+#set_property PACKAGE_PIN L11 [get_ports FMC_HPC_HA22_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA22_P]
+#set_property PACKAGE_PIN K11 [get_ports FMC_HPC_HA22_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA22_N]
+#set_property PACKAGE_PIN H15 [get_ports FMC_HPC_HA15_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA15_P]
+#set_property PACKAGE_PIN G15 [get_ports FMC_HPC_HA15_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA15_N]
+#set_property PACKAGE_PIN J11 [get_ports FMC_HPC_HA21_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA21_P]
+#set_property PACKAGE_PIN J12 [get_ports FMC_HPC_HA21_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA21_N]
+#set_property PACKAGE_PIN J16 [get_ports FMC_HPC_HA14_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA14_P]
+#set_property PACKAGE_PIN H16 [get_ports FMC_HPC_HA14_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA14_N]
+#set_property PACKAGE_PIN H11 [get_ports FMC_HPC_HA19_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA19_P]
+#set_property PACKAGE_PIN H12 [get_ports FMC_HPC_HA19_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA19_N]
+#set_property PACKAGE_PIN H14 [get_ports FMC_HPC_HA01_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA01_CC_P]
+#set_property PACKAGE_PIN G14 [get_ports FMC_HPC_HA01_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA01_CC_N]
+#set_property PACKAGE_PIN G13 [get_ports FMC_HPC_HA17_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA17_CC_P]
+#set_property PACKAGE_PIN F13 [get_ports FMC_HPC_HA17_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA17_CC_N]
+#set_property PACKAGE_PIN D12 [get_ports FMC_HPC_HA00_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA00_CC_P]
+#set_property PACKAGE_PIN D13 [get_ports FMC_HPC_HA00_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA00_CC_N]
+#set_property PACKAGE_PIN F12 [get_ports FMC_HPC_HA09_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA09_P]
+#set_property PACKAGE_PIN E13 [get_ports FMC_HPC_HA09_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA09_N]
+#set_property PACKAGE_PIN C12 [get_ports FMC_HPC_HA03_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA03_P]
+#set_property PACKAGE_PIN B12 [get_ports FMC_HPC_HA03_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA03_N]
+#set_property PACKAGE_PIN F11 [get_ports FMC_HPC_HA04_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA04_P]
+#set_property PACKAGE_PIN E11 [get_ports FMC_HPC_HA04_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA04_N]
+#set_property PACKAGE_PIN A11 [get_ports FMC_HPC_HA10_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA10_P]
+#set_property PACKAGE_PIN A12 [get_ports FMC_HPC_HA10_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA10_N]
+#set_property PACKAGE_PIN D11 [get_ports FMC_HPC_HA02_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA02_P]
+#set_property PACKAGE_PIN C11 [get_ports FMC_HPC_HA02_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA02_N]
+#set_property PACKAGE_PIN F15 [get_ports FMC_HPC_HA05_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA05_P]
+#set_property PACKAGE_PIN E16 [get_ports FMC_HPC_HA05_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA05_N]
+#set_property PACKAGE_PIN E14 [get_ports FMC_HPC_HA08_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA08_P]
+#set_property PACKAGE_PIN E15 [get_ports FMC_HPC_HA08_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA08_N]
+#set_property PACKAGE_PIN D14 [get_ports FMC_HPC_HA06_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA06_P]
+#set_property PACKAGE_PIN C14 [get_ports FMC_HPC_HA06_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA06_N]
+#set_property PACKAGE_PIN B13 [get_ports FMC_HPC_HA11_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA11_P]
+#set_property PACKAGE_PIN A13 [get_ports FMC_HPC_HA11_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA11_N]
+#set_property PACKAGE_PIN C15 [get_ports FMC_HPC_HA12_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA12_P]
+#set_property PACKAGE_PIN B15 [get_ports FMC_HPC_HA12_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA12_N]
+#set_property PACKAGE_PIN B14 [get_ports FMC_HPC_HA07_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA07_P]
+#set_property PACKAGE_PIN A15 [get_ports FMC_HPC_HA07_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA07_N]
+#set_property PACKAGE_PIN F16 [get_ports GPIO_LED_7_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_7_LS]
+#set_property PACKAGE_PIN Y14 [get_ports PMBUS_DATA_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_DATA_LS]
+#set_property PACKAGE_PIN AK16 [get_ports DDR3_D24]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D24]
+#set_property PACKAGE_PIN AK15 [get_ports DDR3_D31]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D31]
+#set_property PACKAGE_PIN AG15 [get_ports DDR3_D26]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D26]
+#set_property PACKAGE_PIN AH15 [get_ports DDR3_D30]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D30]
+#set_property PACKAGE_PIN AH16 [get_ports DDR3_DQS3_P]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS3_P]
+#set_property PACKAGE_PIN AJ16 [get_ports DDR3_DQS3_N]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS3_N]
+#set_property PACKAGE_PIN AF15 [get_ports DDR3_D27]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D27]
+#set_property PACKAGE_PIN AG14 [get_ports DDR3_D29]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D29]
+#set_property PACKAGE_PIN AH17 [get_ports DDR3_D28]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D28]
+#set_property PACKAGE_PIN AJ17 [get_ports DDR3_D25]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D25]
+#set_property PACKAGE_PIN AE16 [get_ports DDR3_DM3]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3]
+#set_property PACKAGE_PIN AF16 [get_ports VTTVREF]
+#set_property PACKAGE_PIN AJ19 [get_ports DDR3_D21]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D21]
+#set_property PACKAGE_PIN AK19 [get_ports DDR3_D17]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D17]
+#set_property PACKAGE_PIN AG19 [get_ports DDR3_D16]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D16]
+#set_property PACKAGE_PIN AH19 [get_ports DDR3_D20]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D20]
+#set_property PACKAGE_PIN AJ18 [get_ports DDR3_DQS2_P]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS2_P]
+#set_property PACKAGE_PIN AK18 [get_ports DDR3_DQS2_N]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS2_N]
+#set_property PACKAGE_PIN AD19 [get_ports DDR3_D23]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D23]
+#set_property PACKAGE_PIN AE19 [get_ports DDR3_D22]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D22]
+#set_property PACKAGE_PIN AF18 [get_ports DDR3_D19]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D19]
+#set_property PACKAGE_PIN AG18 [get_ports DDR3_D18]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D18]
+#set_property PACKAGE_PIN AF17 [get_ports DDR3_DM2]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2]
+#set_property PACKAGE_PIN AG17 [get_ports PMBUS_CLK_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_CLK_LS]
+#set_property PACKAGE_PIN AD18 [get_ports DDR3_D15]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D15]
+#set_property PACKAGE_PIN AE18 [get_ports DDR3_D14]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D14]
+#set_property PACKAGE_PIN AD17 [get_ports DDR3_D11]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D11]
+#set_property PACKAGE_PIN AD16 [get_ports DDR3_D9]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D9]
+#set_property PACKAGE_PIN Y19 [get_ports DDR3_DQS1_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P]
+#set_property PACKAGE_PIN Y18 [get_ports DDR3_DQS1_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N]
+#set_property PACKAGE_PIN AA18 [get_ports DDR3_D12]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D12]
+#set_property PACKAGE_PIN AB18 [get_ports DDR3_D13]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D13]
+#set_property PACKAGE_PIN AB19 [get_ports DDR3_D8]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D8]
+#set_property PACKAGE_PIN AC19 [get_ports DDR3_D10]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D10]
+#set_property PACKAGE_PIN AB17 [get_ports DDR3_DM1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1]
+#set_property PACKAGE_PIN AC17 [get_ports 7N700]
+#set_property PACKAGE_PIN AE15 [get_ports DDR3_D6]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D6]
+#set_property PACKAGE_PIN AE14 [get_ports VTTVREF]
+#set_property PACKAGE_PIN AA15 [get_ports DDR3_D0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
+#set_property PACKAGE_PIN AB15 [get_ports DDR3_D5]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D5]
+#set_property PACKAGE_PIN AC16 [get_ports DDR3_DQS0_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_P]
+#set_property PACKAGE_PIN AC15 [get_ports DDR3_DQS0_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_N]
+#set_property PACKAGE_PIN AC14 [get_ports DDR3_D2]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
+#set_property PACKAGE_PIN AD14 [get_ports DDR3_D3]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
+#set_property PACKAGE_PIN AA17 [get_ports DDR3_D4]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
+#set_property PACKAGE_PIN AA16 [get_ports DDR3_D1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
+#set_property PACKAGE_PIN Y16 [get_ports DDR3_DM0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0]
+#set_property PACKAGE_PIN Y15 [get_ports DDR3_D7]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D7]
+#set_property PACKAGE_PIN AB14 [get_ports PMBUS_ALERT_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_ALERT_LS]
+#set_property PACKAGE_PIN Y13 [get_ports VRN_33]
+#set_property IOSTANDARD SSTL15 [get_ports VRN_33]
+set_property PACKAGE_PIN AA12 [get_ports GPIO_SW_N]
+set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_N]
+set_property PACKAGE_PIN AB12 [get_ports GPIO_SW_S]
+set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_S]
+#set_property PACKAGE_PIN AA8 [get_ports GPIO_LED_1_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_1_LS]
+#set_property PACKAGE_PIN AB8 [get_ports GPIO_LED_0_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0_LS]
+#set_property PACKAGE_PIN AB9 [get_ports GPIO_LED_3_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_3_LS]
+#set_property PACKAGE_PIN AC9 [get_ports GPIO_LED_2_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_2_LS]
+#set_property PACKAGE_PIN Y11 [get_ports LCD_RS_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_RS_LS]
+#set_property PACKAGE_PIN Y10 [get_ports LCD_DB7_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB7_LS]
+#set_property PACKAGE_PIN AA11 [get_ports LCD_DB6_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB6_LS]
+#set_property PACKAGE_PIN AA10 [get_ports LCD_DB5_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB5_LS]
+#set_property PACKAGE_PIN AA13 [get_ports LCD_DB4_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB4_LS]
+#set_property PACKAGE_PIN AB13 [get_ports LCD_RW_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_RW_LS]
+#set_property PACKAGE_PIN AB10 [get_ports LCD_E_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_E_LS]
+#set_property PACKAGE_PIN AC10 [get_ports DDR3_ODT1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
+#set_property PACKAGE_PIN AD8 [get_ports DDR3_ODT0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0]
+#set_property PACKAGE_PIN AE8 [get_ports DDR3_S1_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
+#set_property PACKAGE_PIN AC12 [get_ports DDR3_S0_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B]
+#set_property PACKAGE_PIN AC11 [get_ports DDR3_CAS_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B]
+#set_property PACKAGE_PIN AD9 [get_ports DDR3_RAS_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B]
+#set_property PACKAGE_PIN AE9 [get_ports DDR3_WE_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]
+#set_property PACKAGE_PIN AE11 [get_ports DDR3_CLK1_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]
+#set_property PACKAGE_PIN AF11 [get_ports DDR3_CLK1_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N]
+set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
+set_property PACKAGE_PIN AD11 [get_ports SYSCLK_N]
+set_property PACKAGE_PIN AD12 [get_ports SYSCLK_P]
+set_property IOSTANDARD LVDS [get_ports SYSCLK_N]
+#set_property PACKAGE_PIN AG10 [get_ports DDR3_CLK0_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P]
+#set_property PACKAGE_PIN AH10 [get_ports DDR3_CLK0_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N]
+#set_property PACKAGE_PIN AE10 [get_ports DDR3_CKE1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
+#set_property PACKAGE_PIN AF10 [get_ports DDR3_CKE0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0]
+#set_property PACKAGE_PIN AJ9 [get_ports DDR3_TEMP_EVENT]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_TEMP_EVENT]
+#set_property PACKAGE_PIN AK9 [get_ports DDR3_BA2]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
+#set_property PACKAGE_PIN AG9 [get_ports DDR3_BA1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
+#set_property PACKAGE_PIN AH9 [get_ports DDR3_BA0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
+#set_property PACKAGE_PIN AK11 [get_ports DDR3_A15]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
+#set_property PACKAGE_PIN AK10 [get_ports DDR3_A14]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
+#set_property PACKAGE_PIN AH11 [get_ports DDR3_A13]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
+#set_property PACKAGE_PIN AJ11 [get_ports DDR3_A12]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
+#set_property PACKAGE_PIN AE13 [get_ports DDR3_A11]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
+#set_property PACKAGE_PIN AF13 [get_ports DDR3_A10]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
+#set_property PACKAGE_PIN AK14 [get_ports DDR3_A9]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
+#set_property PACKAGE_PIN AK13 [get_ports DDR3_A8]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
+#set_property PACKAGE_PIN AH14 [get_ports DDR3_A7]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
+#set_property PACKAGE_PIN AJ14 [get_ports DDR3_A6]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
+#set_property PACKAGE_PIN AJ13 [get_ports DDR3_A5]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A5]
+#set_property PACKAGE_PIN AJ12 [get_ports DDR3_A4]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A4]
+#set_property PACKAGE_PIN AF12 [get_ports DDR3_A3]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A3]
+#set_property PACKAGE_PIN AG12 [get_ports DDR3_A2]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A2]
+#set_property PACKAGE_PIN AG13 [get_ports DDR3_A1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A1]
+#set_property PACKAGE_PIN AH12 [get_ports DDR3_A0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A0]
+#set_property PACKAGE_PIN AD13 [get_ports VRP_33]
+set_property PACKAGE_PIN AC6 [get_ports GPIO_SW_W]
+set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_W]
+#set_property PACKAGE_PIN AD4 [get_ports DDR3_D63]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
+#set_property PACKAGE_PIN AD3 [get_ports DDR3_D57]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
+#set_property PACKAGE_PIN AC2 [get_ports DDR3_D62]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
+#set_property PACKAGE_PIN AC1 [get_ports DDR3_D56]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
+#set_property PACKAGE_PIN AD2 [get_ports DDR3_DQS7_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
+#set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS7_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
+#set_property PACKAGE_PIN AC5 [get_ports DDR3_D59]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
+#set_property PACKAGE_PIN AC4 [get_ports DDR3_D58]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
+#set_property PACKAGE_PIN AD6 [get_ports DDR3_D61]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
+#set_property PACKAGE_PIN AE6 [get_ports DDR3_D60]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
+#set_property PACKAGE_PIN AC7 [get_ports DDR3_DM7]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
+#set_property PACKAGE_PIN AD7 [get_ports VTTVREF]
+#set_property PACKAGE_PIN AF3 [get_ports DDR3_D52]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
+#set_property PACKAGE_PIN AF2 [get_ports DDR3_D49]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
+#set_property PACKAGE_PIN AE1 [get_ports DDR3_D54]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D54]
+#set_property PACKAGE_PIN AF1 [get_ports DDR3_D48]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D48]
+#set_property PACKAGE_PIN AG4 [get_ports DDR3_DQS6_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_P]
+#set_property PACKAGE_PIN AG3 [get_ports DDR3_DQS6_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_N]
+#set_property PACKAGE_PIN AE4 [get_ports DDR3_D50]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D50]
+#set_property PACKAGE_PIN AE3 [get_ports DDR3_D51]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D51]
+#set_property PACKAGE_PIN AE5 [get_ports DDR3_D55]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
+#set_property PACKAGE_PIN AF5 [get_ports DDR3_D53]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D53]
+#set_property PACKAGE_PIN AF6 [get_ports DDR3_DM6]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6]
+set_property PACKAGE_PIN AG5 [get_ports GPIO_SW_E]
+set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_E]
+#set_property PACKAGE_PIN AH4 [get_ports DDR3_D44]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D44]
+#set_property PACKAGE_PIN AJ4 [get_ports DDR3_D45]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D45]
+#set_property PACKAGE_PIN AH6 [get_ports DDR3_D41]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D41]
+#set_property PACKAGE_PIN AH5 [get_ports DDR3_D40]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D40]
+#set_property PACKAGE_PIN AG2 [get_ports DDR3_DQS5_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P]
+#set_property PACKAGE_PIN AH1 [get_ports DDR3_DQS5_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N]
+#set_property PACKAGE_PIN AH2 [get_ports DDR3_D43]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D43]
+#set_property PACKAGE_PIN AJ2 [get_ports DDR3_D42]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D42]
+#set_property PACKAGE_PIN AJ1 [get_ports DDR3_D47]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D47]
+#set_property PACKAGE_PIN AK1 [get_ports DDR3_D46]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D46]
+#set_property PACKAGE_PIN AJ3 [get_ports DDR3_DM5]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5]
+#set_property PACKAGE_PIN AK3 [get_ports DDR3_RESET_B]
+#set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B]
+#set_property PACKAGE_PIN AF8 [get_ports DDR3_D36]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D36]
+#set_property PACKAGE_PIN AG8 [get_ports VTTVREF]
+#set_property PACKAGE_PIN AF7 [get_ports DDR3_D35]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D35]
+#set_property PACKAGE_PIN AG7 [get_ports DDR3_D34]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D34]
+#set_property PACKAGE_PIN AH7 [get_ports DDR3_DQS4_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P]
+#set_property PACKAGE_PIN AJ7 [get_ports DDR3_DQS4_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N]
+#set_property PACKAGE_PIN AJ6 [get_ports DDR3_D39]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D39]
+#set_property PACKAGE_PIN AK6 [get_ports DDR3_D33]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D33]
+#set_property PACKAGE_PIN AJ8 [get_ports DDR3_D38]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D38]
+#set_property PACKAGE_PIN AK8 [get_ports DDR3_D32]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D32]
+#set_property PACKAGE_PIN AK5 [get_ports DDR3_DM4]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM4]
+#set_property PACKAGE_PIN AK4 [get_ports DDR3_D37]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D37]
+#set_property PACKAGE_PIN AB7 [get_ports CPU_RESET]
+#set_property IOSTANDARD LVCMOS15 [get_ports CPU_RESET]
+#set_property PACKAGE_PIN T2 [get_ports PCIE_TX4_P]
+#set_property PACKAGE_PIN V6 [get_ports PCIE_RX4_P]
+#set_property PACKAGE_PIN T1 [get_ports PCIE_TX4_N]
+#set_property PACKAGE_PIN V5 [get_ports PCIE_RX4_N]
+#set_property PACKAGE_PIN U4 [get_ports PCIE_TX5_P]
+#set_property PACKAGE_PIN W4 [get_ports PCIE_RX5_P]
+#set_property PACKAGE_PIN U3 [get_ports PCIE_TX5_N]
+#set_property PACKAGE_PIN R8 [get_ports 9N302]
+#set_property PACKAGE_PIN W3 [get_ports PCIE_RX5_N]
+#set_property PACKAGE_PIN R7 [get_ports 9N301]
+#set_property PACKAGE_PIN W8 [get_ports 9N173]
+#set_property PACKAGE_PIN U7 [get_ports PCIE_CLK_QO_N]
+#set_property PACKAGE_PIN U8 [get_ports PCIE_CLK_QO_P]
+#set_property PACKAGE_PIN V2 [get_ports PCIE_TX6_P]
+#set_property PACKAGE_PIN Y6 [get_ports PCIE_RX6_P]
+#set_property PACKAGE_PIN V1 [get_ports PCIE_TX6_N]
+#set_property PACKAGE_PIN Y5 [get_ports PCIE_RX6_N]
+#set_property PACKAGE_PIN Y2 [get_ports PCIE_TX7_P]
+#set_property PACKAGE_PIN AA4 [get_ports PCIE_RX7_P]
+#set_property PACKAGE_PIN Y1 [get_ports PCIE_TX7_N]
+#set_property PACKAGE_PIN AA3 [get_ports PCIE_RX7_N]
+#set_property PACKAGE_PIN L4 [get_ports PCIE_TX0_P]
+#set_property PACKAGE_PIN M6 [get_ports PCIE_RX0_P]
+#set_property PACKAGE_PIN L3 [get_ports PCIE_TX0_N]
+#set_property PACKAGE_PIN M5 [get_ports PCIE_RX0_N]
+#set_property PACKAGE_PIN M2 [get_ports PCIE_TX1_P]
+#set_property PACKAGE_PIN P6 [get_ports PCIE_RX1_P]
+#set_property PACKAGE_PIN M1 [get_ports PCIE_TX1_N]
+#set_property PACKAGE_PIN L8 [get_ports SI5326_OUT_C_P]
+#set_property PACKAGE_PIN P5 [get_ports PCIE_RX1_N]
+#set_property PACKAGE_PIN L7 [get_ports SI5326_OUT_C_N]
+#set_property PACKAGE_PIN N7 [get_ports FMC_LPC_GBTCLK0_M2C_C_N]
+#set_property PACKAGE_PIN N8 [get_ports FMC_LPC_GBTCLK0_M2C_C_P]
+#set_property PACKAGE_PIN N4 [get_ports PCIE_TX2_P]
+#set_property PACKAGE_PIN R4 [get_ports PCIE_RX2_P]
+#set_property PACKAGE_PIN N3 [get_ports PCIE_TX2_N]
+#set_property PACKAGE_PIN R3 [get_ports PCIE_RX2_N]
+#set_property PACKAGE_PIN P2 [get_ports PCIE_TX3_P]
+#set_property PACKAGE_PIN T6 [get_ports PCIE_RX3_P]
+#set_property PACKAGE_PIN P1 [get_ports PCIE_TX3_N]
+#set_property PACKAGE_PIN T5 [get_ports PCIE_RX3_N]
+#set_property PACKAGE_PIN F2 [get_ports FMC_LPC_DP0_C2M_P]
+#set_property PACKAGE_PIN F6 [get_ports FMC_LPC_DP0_M2C_P]
+#set_property PACKAGE_PIN F1 [get_ports FMC_LPC_DP0_C2M_N]
+#set_property PACKAGE_PIN F5 [get_ports FMC_LPC_DP0_M2C_N]
+set_property PACKAGE_PIN G3 [get_ports SFP_RX_N]
+set_property PACKAGE_PIN H2 [get_ports SFP_TX_P]
+set_property PACKAGE_PIN H1 [get_ports SFP_TX_N]
+set_property PACKAGE_PIN G4 [get_ports SFP_RX_P]
+#set_property IOSTANDARD LVDS_25 [get_ports SGMIICLK_Q0_P]
+set_property PACKAGE_PIN G7 [get_ports SGMIICLK_Q0_N]
+set_property PACKAGE_PIN G8 [get_ports SGMIICLK_Q0_P]
+set_property PACKAGE_PIN J7 [get_ports SMA_MGT_REFCLK_N]
+set_property PACKAGE_PIN J8 [get_ports SMA_MGT_REFCLK_P]
+#set_property PACKAGE_PIN J4 [get_ports SGMII_TX_P]
+#set_property PACKAGE_PIN H6 [get_ports SGMII_RX_P]
+#set_property PACKAGE_PIN J3 [get_ports SGMII_TX_N]
+#set_property PACKAGE_PIN H5 [get_ports SGMII_RX_N]
+#set_property PACKAGE_PIN K2 [get_ports SMA_MGT_TX_P]
+#set_property PACKAGE_PIN K6 [get_ports SMA_MGT_RX_P]
+#set_property PACKAGE_PIN K1 [get_ports SMA_MGT_TX_N]
+#set_property PACKAGE_PIN K5 [get_ports SMA_MGT_RX_N]
+#set_property PACKAGE_PIN A4 [get_ports FMC_HPC_DP3_C2M_P]
+#set_property PACKAGE_PIN A8 [get_ports FMC_HPC_DP3_M2C_P]
+#set_property PACKAGE_PIN A3 [get_ports FMC_HPC_DP3_C2M_N]
+#set_property PACKAGE_PIN A7 [get_ports FMC_HPC_DP3_M2C_N]
+#set_property PACKAGE_PIN B2 [get_ports FMC_HPC_DP2_C2M_P]
+#set_property PACKAGE_PIN B6 [get_ports FMC_HPC_DP2_M2C_P]
+#set_property PACKAGE_PIN B1 [get_ports FMC_HPC_DP2_C2M_N]
+#set_property PACKAGE_PIN C8 [get_ports FMC_HPC_GBTCLK0_M2C_C_P]
+#set_property PACKAGE_PIN B5 [get_ports FMC_HPC_DP2_M2C_N]
+#set_property PACKAGE_PIN C7 [get_ports FMC_HPC_GBTCLK0_M2C_C_N]
+#set_property PACKAGE_PIN E7 [get_ports FMC_HPC_GBTCLK1_M2C_C_N]
+#set_property PACKAGE_PIN E8 [get_ports FMC_HPC_GBTCLK1_M2C_C_P]
+#set_property PACKAGE_PIN C4 [get_ports FMC_HPC_DP1_C2M_P]
+#set_property PACKAGE_PIN D6 [get_ports FMC_HPC_DP1_M2C_P]
+#set_property PACKAGE_PIN C3 [get_ports FMC_HPC_DP1_C2M_N]
+#set_property PACKAGE_PIN D5 [get_ports FMC_HPC_DP1_M2C_N]
+#set_property PACKAGE_PIN D2 [get_ports FMC_HPC_DP0_C2M_P]
+#set_property PACKAGE_PIN E4 [get_ports FMC_HPC_DP0_M2C_P]
+#set_property PACKAGE_PIN D1 [get_ports FMC_HPC_DP0_C2M_N]
+#set_property PACKAGE_PIN E3 [get_ports FMC_HPC_DP0_M2C_N]
+
+set_property PACKAGE_PIN F20 [get_ports {fmc_sfp_tx_disable[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_disable[0]}]
+set_property PACKAGE_PIN A26 [get_ports {fmc_sfp_tx_disable[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_disable[1]}]
+set_property PACKAGE_PIN D29 [get_ports {fmc_sfp_tx_disable[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_disable[2]}]
+set_property PACKAGE_PIN G30 [get_ports {fmc_sfp_tx_disable[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_disable[3]}]
+
+set_property PACKAGE_PIN F18 [get_ports {fmc_led[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_led[0]}]
+set_property PACKAGE_PIN G18 [get_ports {fmc_led[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_led[1]}]
+set_property PACKAGE_PIN E21 [get_ports {fmc_led[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_led[2]}]
+set_property PACKAGE_PIN F21 [get_ports {fmc_led[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_led[3]}]
+
+set_property PACKAGE_PIN A28 [get_ports {fmc_sfp_los[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_los[0]}]
+set_property PACKAGE_PIN G27 [get_ports {fmc_sfp_los[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_los[1]}]
+set_property PACKAGE_PIN D28 [get_ports {fmc_sfp_los[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_los[2]}]
+set_property PACKAGE_PIN G28 [get_ports {fmc_sfp_los[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_los[3]}]
+
+set_property PACKAGE_PIN E20 [get_ports {fmc_sfp_tx_fault[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_fault[0]}]
+set_property PACKAGE_PIN B28 [get_ports {fmc_sfp_tx_fault[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_fault[1]}]
+set_property PACKAGE_PIN C30 [get_ports {fmc_sfp_tx_fault[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_fault[2]}]
+set_property PACKAGE_PIN E28 [get_ports {fmc_sfp_tx_fault[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_fault[3]}]
+
+set_property PACKAGE_PIN C24 [get_ports {fmc_sfp_rate_sel[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_rate_sel[0]}]
+set_property PACKAGE_PIN F27 [get_ports {fmc_sfp_rate_sel[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_rate_sel[1]}]
+set_property PACKAGE_PIN E29 [get_ports {fmc_sfp_rate_sel[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_rate_sel[2]}]
+set_property PACKAGE_PIN F28 [get_ports {fmc_sfp_rate_sel[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_rate_sel[3]}]
+
+set_property PACKAGE_PIN B24 [get_ports {fmc_sfp_mod_def0[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_mod_def0[0]}]
+set_property PACKAGE_PIN C29 [get_ports {fmc_sfp_mod_def0[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_mod_def0[1]}]
+set_property PACKAGE_PIN E30 [get_ports {fmc_sfp_mod_def0[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_mod_def0[2]}]
+set_property PACKAGE_PIN G29 [get_ports {fmc_sfp_mod_def0[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_mod_def0[3]}]
+
+set_property PACKAGE_PIN H24 [get_ports {fmc_user_switch[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_user_switch[0]}]
+set_property PACKAGE_PIN H25 [get_ports {fmc_user_switch[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_user_switch[1]}]
+set_property PACKAGE_PIN H26 [get_ports {fmc_user_switch[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_user_switch[2]}]
+set_property PACKAGE_PIN H27 [get_ports {fmc_user_switch[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_user_switch[3]}]
+
+set_property PACKAGE_PIN E4 [get_ports X0Y12_RX_P_IPAD]
+set_property PACKAGE_PIN E3 [get_ports X0Y12_RX_N_IPAD]
+set_property PACKAGE_PIN D1 [get_ports X0Y12_TX_N_OPAD]
+set_property PACKAGE_PIN D2 [get_ports X0Y12_TX_P_OPAD]
+set_property PACKAGE_PIN D5 [get_ports X0Y13_RX_N_IPAD]
+set_property PACKAGE_PIN D6 [get_ports X0Y13_RX_P_IPAD]
+set_property PACKAGE_PIN C3 [get_ports X0Y13_TX_N_OPAD]
+set_property PACKAGE_PIN C4 [get_ports X0Y13_TX_P_OPAD]
+set_property PACKAGE_PIN B5 [get_ports X0Y14_RX_N_IPAD]
+set_property PACKAGE_PIN B6 [get_ports X0Y14_RX_P_IPAD]
+set_property PACKAGE_PIN B1 [get_ports X0Y14_TX_N_OPAD]
+set_property PACKAGE_PIN B2 [get_ports X0Y14_TX_P_OPAD]
+set_property PACKAGE_PIN A4 [get_ports X0Y15_TX_P_OPAD]
+set_property PACKAGE_PIN A7 [get_ports X0Y15_RX_N_IPAD]
+set_property PACKAGE_PIN A8 [get_ports X0Y15_RX_P_IPAD]
+set_property PACKAGE_PIN A3 [get_ports X0Y15_TX_N_OPAD]
+
+set_property PACKAGE_PIN C8 [get_ports Q3_CLK0_MGTREFCLK_P_IPAD]
+set_property PACKAGE_PIN C7 [get_ports Q3_CLK0_MGTREFCLK_N_IPAD]
+#set_property PACKAGE_PIN E7 [get_ports Q3_CLK1_MGTREFCLK_N_IPAD]
+#set_property PACKAGE_PIN E8 [get_ports Q3_CLK1_MGTREFCLK_P_IPAD]
+
+
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.soda_components.all;
+use work.version.all;
+use work.panda_package.all;
+USE work.CN_package.all;
+
+
+entity trb3_kc705_data_concentrator is
+ port(
+ --Clocks
+
+ SYSCLK_P : in std_logic; --200MHz
+ SYSCLK_N : in std_logic; --200MHz
+
+ --Serdes
+ SGMIICLK_Q0_P : in std_logic; -- reverence clock for onboard sfp
+ SGMIICLK_Q0_N : in std_logic;
+ SFP_TX_P : out std_logic;
+ SFP_TX_N : out std_logic;
+ SFP_RX_P : in std_logic;
+ SFP_RX_N : in std_logic;
+ SFP_TX_DISABLE : out std_logic;
+ SFP_LOS_LS : in std_logic;
+
+ --Quad SFP on FMC module
+ fmc_led : out std_logic_vector(3 downto 0);
+ fmc_user_switch : inout std_logic_vector(3 downto 0);
+ fmc_sfp_los : in std_logic_vector(3 downto 0);
+ fmc_sfp_tx_fault : in std_logic_vector(3 downto 0);
+ fmc_sfp_tx_disable : out std_logic_vector(3 downto 0);
+ fmc_sfp_rate_sel : out std_logic_vector(3 downto 0);
+ fmc_sfp_mod_def0 : in std_logic_vector(3 downto 0); -- or out???
+ X0Y12_RX_P_IPAD : in std_logic;
+ X0Y12_RX_N_IPAD : in std_logic;
+ X0Y13_RX_P_IPAD : in std_logic;
+ X0Y13_RX_N_IPAD : in std_logic;
+ X0Y14_RX_P_IPAD : in std_logic;
+ X0Y14_RX_N_IPAD : in std_logic;
+ X0Y15_RX_P_IPAD : in std_logic;
+ X0Y15_RX_N_IPAD : in std_logic;
+ Q3_CLK0_MGTREFCLK_P_IPAD : in std_logic;
+ Q3_CLK0_MGTREFCLK_N_IPAD : in std_logic;
+-- Q3_CLK1_MGTREFCLK_P_IPAD : in std_logic;
+-- Q3_CLK1_MGTREFCLK_N_IPAD : in std_logic;
+ X0Y12_TX_P_OPAD : out std_logic;
+ X0Y12_TX_N_OPAD : out std_logic;
+ X0Y13_TX_P_OPAD : out std_logic;
+ X0Y13_TX_N_OPAD : out std_logic;
+ X0Y14_TX_P_OPAD : out std_logic;
+ X0Y14_TX_N_OPAD : out std_logic;
+ X0Y15_TX_P_OPAD : out std_logic;
+ X0Y15_TX_N_OPAD : out std_logic;
+ SMA_MGT_REFCLK_P : in std_logic; -- sma reference clock input for MGTREFCLK1P_117
+ SMA_MGT_REFCLK_N : in std_logic; -- sma reference clock input for MGTREFCLK1N_117
+ USER_SMA_CLOCK_P : out std_logic; -- sma clock output
+ USER_SMA_CLOCK_N : out std_logic; -- sma clock output
+ REC_CLOCK_C_P : out std_logic; -- clock output to jitter cleaner
+ REC_CLOCK_C_N : out std_logic; -- clock output to jitter cleaner
+ USER_SMA_GPIO_P : out std_logic;
+ USER_SMA_GPIO_N : out std_logic;
+
+ GPIO_SW_N : in std_logic;
+ GPIO_SW_S : in std_logic;
+ GPIO_SW_C : in std_logic;
+ GPIO_SW_W : in std_logic;
+ GPIO_SW_E : in std_logic;
+ XADC_GPIO_0 : out std_logic;
+ XADC_GPIO_1 : out std_logic;
+ XADC_GPIO_2 : out std_logic;
+ XADC_GPIO_3 : out std_logic
+ );
+end entity;
+
+architecture trb3_kc705_data_concentrator of trb3_kc705_data_concentrator is
+
+ constant EXTERNAL_SODA : boolean := true;
+
+
+
+component pll_in200_out200_160_100_80 is
+port
+ (-- Clock in ports
+ clk_in1_p : in std_logic;
+ clk_in1_n : in std_logic;
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ clk_out3 : out std_logic;
+ clk_out4 : out std_logic;
+ -- Status and control signals
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+component pll_in200_out200 is
+port
+ (-- Clock in ports
+ clk_in1 : in std_logic;
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ -- Status and control signals
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+component jittercleaner_200M is
+port
+ (
+ clk_in : in std_logic;
+ clk_out : out std_logic;
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+component trb_net16_med_sync_gtx2_kintex7_sfp is
+ port(
+ CLK : in std_logic; -- SerDes clock
+ SYSCLK : in std_logic; -- fabric clock
+ SODA_clock : in std_logic; --//try
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ disable_GTX_reset : in std_logic;
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ REFCLK2CORE_OUT : out std_logic;
+ CLK_RX_HALF_OUT : out std_logic;
+ CLK_RX_FULL_OUT : out std_logic;
+ --SFP Connection
+ SODA_RXD_P_IN : in std_logic;
+ SODA_RXD_N_IN : in std_logic;
+ SODA_TXD_P_OUT : out std_logic;
+ SODA_TXD_N_OUT : out std_logic;
+ SODA_REFCLK_P_IN : in std_logic;
+ SODA_REFCLK_N_IN : in std_logic;
+ SODA_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SODA_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SODA_TXDIS_OUT : out std_logic; -- SFP disable
+ SODA_DLM_IN : in std_logic;
+ SODA_DLM_WORD_IN : in std_logic_vector(7 downto 0);
+ SODA_DLM_OUT : out std_logic;
+ SODA_DLM_WORD_OUT : out std_logic_vector(7 downto 0);
+ SODA_CLOCK_OUT : out std_logic; -- 200MHz
+ SODA_LOCKED_OUT : out std_logic;
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+end component;
+
+component GTX_dataoutputwrapper is
+ port (
+ sysClk : in std_logic;
+ refClk_P : in std_logic;
+ refClk_N : in std_logic;
+ clock_out : out std_logic;
+ clock_rec : out std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ kchar_in : in std_logic_vector(1 downto 0);
+ data_out : out std_logic_vector(15 downto 0);
+ kchar_out : out std_logic_vector(1 downto 0);
+ G0_txP : out std_logic;
+ G0_txN : out std_logic;
+ G0_rxP : in std_logic;
+ G0_rxN : in std_logic;
+ G0_LOS : in std_logic;
+ tx_locked : out std_logic;
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+ );
+end component;
+
+component dataconversion_for_serdes16 is
+ port (
+ DATA_CLK : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
+ TX_READY : in std_logic;
+ SFP_MOD0 : in std_logic;
+ SFP_LOS : in std_logic;
+ TX_ALLOWED : in std_logic;
+ TX_DATA : out std_logic_vector(15 downto 0);
+ TX_K : out std_logic_vector(1 downto 0);
+ DATA_IN_ALLOWED : out std_logic;
+ DATA_IN : in std_logic_vector(63 downto 0);
+ DATA_IN_WRITE : in std_logic;
+ DATA_IN_FIRST : in std_logic;
+ DATA_IN_LAST : in std_logic;
+ DATA_IN_ERROR : in std_logic);
+end component;
+
+component DC_module_TRB3 is
+ generic (
+ NROFFIBERS : natural := NROFFIBERS;
+ NROFADCS : natural := NROFFEEADCS*NROFFEEFPGAS;
+ ADCBITS : natural := ADCBITS;
+ ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY;
+ MAX_DIVIDERSCALEBITS : natural := 12;
+ MAX_LUTSIZEBITS : natural := 9;
+ MAX_LUTSCALEBITS : natural := 14;
+ MUXINFIFOSIZE : natural := 10;
+ TRANSFERFIFOSIZE : natural := 12;
+ CF_FRACTIONBIT : natural := 11;
+ PANDAPACKETBUFFERBITS : natural := 13;
+ ADCINDEXSHIFT : natural := 1;
+ ENERGYSCALINGBITS : natural := 13;
+ COMBINEPULSESMEMSIZE : natural := 10;
+ COMBINETIMEDIFFERENCE : natural := 5000;
+ SYSTEM_ID : std_logic_vector(15 downto 0) := x"5555";
+ DOPRECLUSTERING : boolean := DOPRECLUSTERING;
+ XYPAD_BITSIZE : natural := 8;
+ CLUSTERBITS : natural := 8;
+ MAXCLUSTERSBITS : natural := 5;
+ PARALLELBUILDS : natural := 2;
+ MINIMUMENERGYBITS : natural := 8;
+ SKIPSINGLEHITCLUSTERS : boolean := FALSE
+ );
+ port (
+ slowcontrol_clock : in std_logic;
+ packet_in_clock : in std_logic;
+ MUX_clock : in std_logic;
+ packet_out_clock : in std_logic;
+ SODA_clock : in std_logic;
+ reset : in std_logic;
+
+-- Slave bus
+ BUS_READ_IN : in std_logic;
+ BUS_WRITE_IN : in std_logic;
+ BUS_BUSY_OUT : out std_logic;
+ BUS_ACK_OUT : out std_logic;
+ BUS_ADDR_IN : in std_logic_vector(1 downto 0);
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+
+-- fiber interface signals:
+ fiber_txlocked : in std_logic_vector(0 to NROFFIBERS-1);
+ fiber_rxlocked : in std_logic_vector(0 to NROFFIBERS-1);
+ reset_fibers : out std_logic;
+ fiber_data32write : out std_logic_vector(0 to NROFFIBERS-1);
+ fiber_data32out : out array_fiber32bits_type;
+ fiber_data32fifofull : in std_logic_vector(0 to NROFFIBERS-1);
+ fiber_data32read : out std_logic_vector(0 to NROFFIBERS-1);
+ fiber_data32present : in std_logic_vector(0 to NROFFIBERS-1);
+ fiber_data32in : in array_fiber32bits_type;
+ fiber_rxerror : in std_logic_vector(0 to NROFFIBERS-1);
+
+-- SODA signals
+ superburst_number : in std_logic_vector(30 downto 0);
+ superburst_update : in std_logic;
+ SODA_enable : out std_logic;
+ EnableExternalSODA : out std_logic;
+
+-- 64 bits data output
+ data_out_allowed : in std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_error : out std_logic;
+ no_packet_limit : out std_logic;
+
+-- testpoints
+ testword0 : out std_logic_vector (35 downto 0) := (others => '0');
+ testword0clock : out std_logic := '0';
+ testword1 : out std_logic_vector (35 downto 0) := (others => '0');
+ testword2 : out std_logic_vector (35 downto 0) := (others => '0')
+
+ );
+end component;
+
+component serdesQuadBufLayerMUX is
+ port (
+ refClk : in std_logic;
+ refClk_P : in std_logic := '0';
+ refClk_N : in std_logic := '1';
+ sysClk : in std_logic;
+ reset : in std_logic;
+ reset_fibers : in std_logic;
+ clk_SODA200 : in std_logic;
+ txAsyncClk : in std_logic;
+ rxAsyncClk : in std_logic;
+ txpll_clocks : out std_logic_vector(3 downto 0);
+
+ G0_txAsyncData : in std_logic_vector (31 downto 0);
+ G0_txAsyncDataWrite : in std_logic;
+ G0_txAsyncFifoFull : out std_logic;
+ G0_rxAsyncData : out std_logic_vector (31 downto 0);
+ G0_rxAsyncDataRead : in std_logic;
+ G0_rxAsyncDataOverflow : out std_logic;
+ G0_rxAsyncDataPresent : out std_logic;
+ G0_txLocked : out std_logic;
+ G0_rxLocked : out std_logic;
+ G0_error : out std_logic;
+ G0_TX_DLM : in std_logic;
+ G0_TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ G0_RX_DLM : out std_logic;
+ G0_RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ G0_LOS : in std_logic;
+ G0_txP : out std_logic;
+ G0_txN : out std_logic;
+ G0_rxP : in std_logic;
+ G0_rxN : in std_logic;
+
+ G1_txAsyncData : in std_logic_vector (31 downto 0);
+ G1_txAsyncDataWrite : in std_logic;
+ G1_txAsyncFifoFull : out std_logic;
+ G1_rxAsyncData : out std_logic_vector (31 downto 0);
+ G1_rxAsyncDataRead : in std_logic;
+ G1_rxAsyncDataOverflow : out std_logic;
+ G1_rxAsyncDataPresent : out std_logic;
+ G1_txLocked : out std_logic;
+ G1_rxLocked : out std_logic;
+ G1_error : out std_logic;
+ G1_TX_DLM : in std_logic;
+ G1_TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ G1_RX_DLM : out std_logic;
+ G1_RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ G1_LOS : in std_logic;
+ G1_txP : out std_logic;
+ G1_txN : out std_logic;
+ G1_rxP : in std_logic;
+ G1_rxN : in std_logic;
+
+ G2_txAsyncData : in std_logic_vector (31 downto 0);
+ G2_txAsyncDataWrite : in std_logic;
+ G2_txAsyncFifoFull : out std_logic;
+ G2_rxAsyncData : out std_logic_vector (31 downto 0);
+ G2_rxAsyncDataRead : in std_logic;
+ G2_rxAsyncDataOverflow : out std_logic;
+ G2_rxAsyncDataPresent : out std_logic;
+ G2_txLocked : out std_logic;
+ G2_rxLocked : out std_logic;
+ G2_error : out std_logic;
+ G2_TX_DLM : in std_logic;
+ G2_TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ G2_RX_DLM : out std_logic;
+ G2_RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ G2_LOS : in std_logic;
+ G2_txP : out std_logic;
+ G2_txN : out std_logic;
+ G2_rxP : in std_logic;
+ G2_rxN : in std_logic;
+
+ G3_txAsyncData : in std_logic_vector (31 downto 0);
+ G3_txAsyncDataWrite : in std_logic;
+ G3_txAsyncFifoFull : out std_logic;
+ G3_rxAsyncData : out std_logic_vector (31 downto 0);
+ G3_rxAsyncDataRead : in std_logic;
+ G3_rxAsyncDataOverflow : out std_logic;
+ G3_rxAsyncDataPresent : out std_logic;
+ G3_txLocked : out std_logic;
+ G3_rxLocked : out std_logic;
+ G3_error : out std_logic;
+ G3_TX_DLM : in std_logic;
+ G3_TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ G3_RX_DLM : out std_logic;
+ G3_RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ G3_LOS : in std_logic;
+ G3_txP : out std_logic;
+ G3_txN : out std_logic;
+ G3_rxP : in std_logic;
+ G3_rxN : in std_logic;
+
+ LEDs_link_ok : out std_logic_vector(0 to 3);
+ LEDs_rx : out std_logic_vector(0 to 3);
+ LEDs_tx : out std_logic_vector(0 to 3);
+ GT0_QPLLOUTCLK_IN : in std_logic := '0';
+ GT0_QPLLOUTREFCLK_IN : in std_logic := '0';
+
+ testPin : out std_logic_vector(3 downto 0);
+ testword0 : out std_logic_vector (35 downto 0) := (others => '0');
+ testword0clock : out std_logic := '0'
+ );
+end component;
+
+component DC_SODAserdesWrapper is
+ port (
+ refClk : in std_logic;
+ refClk_P : in std_logic;
+ refClk_N : in std_logic;
+ sysClk : in std_logic;
+ asyncclk : in std_logic;
+ gtpReset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ txData : in std_logic_vector (7 downto 0);
+ txCharIsK : in std_logic;
+ txP : out std_logic;
+ txN : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxData : out std_logic_vector (7 downto 0);
+ rxCharIsK : out std_logic;
+ rxNotInTable : out std_logic;
+ rxP : in std_logic;
+ rxN : in std_logic;
+ rxUsrClk : out std_logic;
+ rxUsrClkdiv2 : out std_logic;
+ rxLocked : out std_logic;
+
+ GT0_QPLLOUTCLK_OUT : out std_logic := '0';
+ GT0_QPLLOUTREFCLK_OUT : out std_logic := '0';
+ resetDone : out std_logic
+ );
+end component;
+
+component DC_SODA_clockcrossing is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ DLM_in : in std_logic;
+ DLM_WORD_in : in std_logic_vector(7 downto 0);
+ DLM_out : out std_logic;
+ DLM_WORD_out : out std_logic_vector(7 downto 0);
+ error : out std_logic
+ );
+end component;
+
+component sync_bit is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+end component;
+
+component CN_checkdata is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_error : in std_logic;
+ data_in_write : in std_logic;
+ dataerror : out std_logic;
+ timeerror : out std_logic;
+ waveerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+--Constants
+ constant REGIO_NUM_STAT_REGS : integer := 2;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+ attribute keep : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ --Clock / Reset
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal clk_80_i : std_logic;
+ signal clk_160div3_i : std_logic;
+ signal USER_SMA_CLOCK_S : std_logic;
+
+
+ signal txpll_clocks_S : std_logic_vector(3 downto 0);
+
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clk_SODA200_i : std_logic;
+--// signal clk_SODA200_jitter_i : std_logic;
+ signal SD_LOS_S : std_logic;
+ signal SD_TXDIS_S : std_logic;
+
+
+
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+ --Media Interface
+ signal med_stat_op : std_logic_vector (1*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_data_out : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_in : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_in : std_logic;
+
+ --LVL1 channel
+ signal trg_data_valid_i : std_logic;
+ signal trg_timing_valid_i : std_logic;
+ signal trg_notiming_valid_i : std_logic;
+ signal trg_invalid_i : std_logic;
+ signal trg_type_i : std_logic_vector(3 downto 0);
+ signal trg_number_i : std_logic_vector(15 downto 0);
+ signal trg_code_i : std_logic_vector(7 downto 0);
+ signal trg_information_i : std_logic_vector(23 downto 0);
+ signal trg_int_number_i : std_logic_vector(15 downto 0);
+ signal trg_multiple_trg_i : std_logic;
+ signal trg_timeout_detected_i: std_logic;
+ signal trg_spurious_trg_i : std_logic;
+ signal trg_missing_tmg_trg_i : std_logic;
+ signal trg_spike_detected_i : std_logic;
+
+ --Data channel
+ signal fee_almost_full_i : std_logic;
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0) := (others => '0');
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_data_in : std_logic_vector(31 downto 0);
+ signal spictrl_addr : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spictrl_ack : std_logic;
+ signal spictrl_busy : std_logic;
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(5 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_ack : std_logic;
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ signal DLM_to_bottom_S : t_HUB_BIT;
+ signal DLM_WORD_to_bottom_S : t_HUB_BYTE;
+ signal DLM_from_bottom_S : t_HUB_BIT;
+ signal DLM_WORD_from_bottom_S : t_HUB_BYTE;
+
+ signal DLM_hub2uplink_S : std_logic;
+ signal DLM_WORD_hub2uplink_S : std_logic_vector(7 downto 0) := (others => '0');
+ signal DLM_source2hub_S : std_logic;
+ signal DLM_WORD_source2hub_S : std_logic_vector(7 downto 0) := (others => '0');
+
+ signal SODA_burst_pulse_S : std_logic;
+ signal soda_40mhz_cycle_S : std_logic;
+
+ signal EnableExternalSODA_S : std_logic;
+ signal EnableExternalSODAsync_S : std_logic;
+
+ signal dataout_data_S : std_logic_vector(15 downto 0);
+ signal dataout_charisK_S : std_logic_vector(1 downto 0);
+ signal dataout_clock_S : std_logic;
+ signal dataout_tx_locked_S : std_logic;
+
+ signal dataout_rec_data_S : std_logic_vector(15 downto 0);
+ signal dataout_rec_charisK_S : std_logic_vector(1 downto 0);
+ signal dataout_clock_rec_S : std_logic;
+ signal dataout_allowed_rec_S : std_logic;
+ signal dataout_allowed_S : std_logic;
+
+ signal data64b_muxed_allowed : std_logic := '1';
+ signal data64b_muxed : std_logic_vector(63 downto 0);
+ signal data64b_muxed_write : std_logic;
+ signal data64b_muxed_first : std_logic;
+ signal data64b_muxed_last : std_logic;
+ signal data64b_muxed_error : std_logic;
+ signal data64b_muxed_error_S : std_logic;
+ signal data64b_muxed_allowed0_S: std_logic := '1';
+ signal data64b_muxed_allowed_S: std_logic := '1';
+ signal data64b_muxed_busy_S : std_logic;
+ signal no_packet_limit_S : std_logic;
+
+ signal data64_S : std_logic_vector(63 downto 0);
+ signal data64_write_S : std_logic;
+ signal data64_first_S : std_logic;
+ signal data64_last_S : std_logic;
+ signal data64_allowed_S : std_logic;
+ signal data64_error_S : std_logic;
+
+ signal data64b_count : std_logic_vector(15 downto 0);
+
+ --FPGA Test
+ signal time_counter : unsigned(31 downto 0);
+
+ --TDC component
+ component TDC
+ generic (
+ CHANNEL_NUMBER : integer range 0 to 64);
+ port (
+ RESET : in std_logic;
+ CLK_TDC : in std_logic;
+ CLK_READOUT : in std_logic;
+ HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0);
+ TRIGGER_IN : in std_logic;
+ TRIGGER_WIN_IN : in std_logic_vector(31 downto 0);
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ TRB_WR_CLK_OUT : out std_logic;
+ DATA_VALID_OUT : out std_logic;
+ DATA_FINISHED_OUT : out std_logic;
+ READY_OUT : out std_logic;
+ TDC_DEBUG_00 : out std_logic_vector(31 downto 0));
+ end component;
+
+ -- data_concentrator
+
+ signal SODA_clock_selected_S : std_logic;
+ signal PACKETIN_clock : std_logic;
+ signal MUX_clock : std_logic;
+ signal PACKETOUT_clock : std_logic;
+ signal dc_read_en : std_logic := '0';
+ signal dc_write_en : std_logic := '0';
+ signal dc_busy : std_logic := '0';
+ signal dc_ack : std_logic := '0';
+ signal dc_addr : std_logic_vector(1 downto 0);
+ signal dc_data_in : std_logic_vector(31 downto 0);
+ signal dc_data_out : std_logic_vector(31 downto 0);
+
+ -- soda hub
+ signal soda_read_en : std_logic;
+ signal soda_write_en : std_logic;
+ signal soda_ack : std_logic;
+ signal soda_addr : std_logic_vector(3 downto 0);
+ signal soda_data_in : std_logic_vector(31 downto 0);
+ signal soda_data_out : std_logic_vector(31 downto 0);
+
+ -- soda source
+ signal sodasrc_read_en : std_logic;
+ signal sodasrc_write_en : std_logic;
+ signal sodasrc_ack : std_logic;
+ signal sodasrc_addr : std_logic_vector(3 downto 0);
+ signal sodasrc_data_in : std_logic_vector(31 downto 0);
+ signal sodasrc_data_out : std_logic_vector(31 downto 0);
+
+ -- external SODA
+
+ signal DLM_from_uplink_S : std_logic;
+ signal DLM_WORD_from_uplink_S : std_logic_vector(7 downto 0);
+ signal DLM_to_uplink_S : std_logic;
+ signal DLM_WORD_to_uplink_S : std_logic_vector(7 downto 0);
+ signal SODA_IN_rxUsrClk_S : std_logic;
+ signal SODA_IN_rxLocked_S : std_logic;
+ signal jittercleaner_reset_S : std_logic;
+ signal jittercleaner_locked_S : std_logic;
+ signal jittercleaner_clock_in_S : std_logic;
+ signal jittercleaner_clock_out_S : std_logic;
+ signal jittercleaner_clock_out0_S : std_logic;
+ signal SODA_reset_S : std_logic;
+
+ -- fibers
+ signal q3_clk0_gtrefclk_S : std_logic;
+ signal q2_clk1_gtrefclk_S : std_logic;
+ attribute syn_noclockbuf : boolean;
+ attribute syn_noclockbuf of q3_clk0_gtrefclk_S : signal is true;
+ attribute syn_noclockbuf of q2_clk1_gtrefclk_S : signal is true;
+ signal gt0_qplloutclk_S : std_logic;
+ signal gt0_qplloutrefclk_S : std_logic;
+ signal reset_SODAclock_S : std_logic;
+ signal reset_fibers_S : std_logic;
+ signal reset_fee_S : std_logic;
+
+ signal fiber_txlocked_S : std_logic_vector(0 to NROFFIBERS-1);
+ signal fiber_rxlocked_S : std_logic_vector(0 to NROFFIBERS-1);
+ signal superburst_update_S : std_logic;
+ signal superburst_number_S : std_logic_vector(30 downto 0);
+ signal fiber_data32write_S : std_logic_vector(0 to NROFFIBERS-1);
+ signal fiber_data32out_S : array_fiber32bits_type;
+ signal fiber_data32fifofull_S : std_logic_vector(0 to NROFFIBERS-1);
+ signal fiber_data32read_S : std_logic_vector(0 to NROFFIBERS-1);
+ signal fiber_data32present_S : std_logic_vector(0 to NROFFIBERS-1);
+ signal fiber_data32in_S : array_fiber32bits_type;
+ signal fiber_rxerror_S : std_logic_vector(0 to NROFFIBERS-1);
+
+ -- LEDs
+ signal LEDs_link_ok_i : std_logic_vector(0 to 3);
+ signal LEDs_rx_i : std_logic_vector(0 to 3);
+ signal LEDs_tx_i : std_logic_vector(0 to 3);
+
+
+ signal testword0clock_i : std_logic;
+ attribute syn_keep of testword0clock_i : signal is true;
+ attribute syn_preserve of testword0clock_i : signal is true;
+
+ attribute syn_keep of clk_100_i : signal is true;
+ attribute syn_keep of clk_200_i : signal is true;
+
+ attribute syn_keep of clk_80_i : signal is true;
+ attribute syn_keep of clk_SODA200_i : signal is true;
+
+ attribute syn_preserve of clk_100_i : signal is true;
+ attribute syn_preserve of clk_200_i : signal is true;
+ attribute syn_preserve of clk_80_i : signal is true;
+ attribute syn_preserve of clk_SODA200_i : signal is true;
+
+ signal data64b_dataerror : std_logic;
+ signal data64b_timeerror : std_logic;
+ signal data64b_waveerror : std_logic;
+
+ signal dumadr0 : std_logic_vector(5*16-1 downto 0);
+ type debug_superbursts_type is array(7 downto 0) of std_logic_vector(7 downto 0);
+ signal debug_nextsuperburst_S : std_logic := '0';
+ signal debug_counter_S : integer := 0;
+ signal debug_superburst_error_S : std_logic := '0';
+ signal debug_emptypacket_S : std_logic := '0';
+ signal debug_superburst_S : std_logic_vector(30 downto 0);
+ signal debug_superbursts_S : debug_superbursts_type := (others => (others => '0'));
+ signal debug_nrofbytes_S : std_logic_vector(15 downto 0);
+
+ signal debug_clkdiv2_1 : std_logic;
+ signal debug_clkdiv2_2 : std_logic;
+ signal debug_clkdiv2_3 : std_logic;
+ signal debug_clkdiv2_4 : std_logic;
+
+ signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');
+
+attribute mark_debug : string;
+-- attribute mark_debug of dataout_data_S : signal is "true";
+-- attribute mark_debug of dataout_charisK_S : signal is "true";
+-- attribute mark_debug of dataout_tx_locked_S : signal is "true";
+-- attribute mark_debug of data64b_muxed_allowed : signal is "true";
+-- attribute mark_debug of data64b_muxed : signal is "true";
+-- attribute mark_debug of data64b_muxed_write : signal is "true";
+-- attribute mark_debug of data64b_muxed_first : signal is "true";
+-- attribute mark_debug of data64b_muxed_last : signal is "true";
+-- attribute mark_debug of data64b_muxed_error : signal is "true";
+-- attribute mark_debug of data64b_dataerror : signal is "true";
+-- attribute mark_debug of data64b_timeerror : signal is "true";
+-- attribute mark_debug of data64b_waveerror : signal is "true";
+-- attribute mark_debug of data64b_count : signal is "true";
+-- attribute mark_debug of dataout_tx_locked_S : signal is "true";
+-- attribute mark_debug of dataout_data_S : signal is "true";
+-- attribute mark_debug of dataout_charisK_S : signal is "true";
+-- attribute mark_debug of dataout_rec_data_S : signal is "true";
+-- attribute mark_debug of dataout_rec_charisK_S : signal is "true";
+
+-- attribute mark_debug of data64b_muxed : signal is "true";
+-- attribute mark_debug of data64b_muxed_write : signal is "true";
+-- attribute mark_debug of data64b_muxed_first : signal is "true";
+-- attribute mark_debug of data64b_muxed_last : signal is "true";
+-- attribute mark_debug of data64b_muxed_busy_S : signal is "true";
+-- attribute mark_debug of data64_S : signal is "true";
+-- attribute mark_debug of data64_write_S : signal is "true";
+-- attribute mark_debug of data64_first_S : signal is "true";
+-- attribute mark_debug of data64_last_S : signal is "true";
+-- attribute mark_debug of data64_allowed_S : signal is "true";
+--attribute mark_debug of data64_error_S : signal is "true";
+
+
+attribute mark_debug of fiber_data32out_S : signal is "true";
+attribute mark_debug of fiber_data32write_S : signal is "true";
+attribute mark_debug of fiber_data32fifofull_S : signal is "true";
+attribute mark_debug of fiber_data32in_S : signal is "true";
+attribute mark_debug of fiber_data32read_S : signal is "true";
+attribute mark_debug of fiber_data32present_S : signal is "true";
+
+
+
+begin
+
+
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+GSR_N <= pll_lock;
+SFP_TX_DISABLE <= not SD_TXDIS_S;
+
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => GPIO_SW_C, -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+
+THE_MAIN_PLL : pll_in200_out200_160_100_80 port map(
+ clk_in1_p => SYSCLK_P,
+ clk_in1_n => SYSCLK_N,
+ clk_out1 => clk_200_i,
+ clk_out2 => clk_100_i,
+ clk_out3 => clk_80_i,
+ clk_out4 => clk_160div3_i,
+ reset => '0',
+ locked => pll_lock);
+
+BUF_sma_clock_inst : OBUFDS
+ generic map(
+ IOSTANDARD => "LVDS_25")
+ port map(
+ O => USER_SMA_CLOCK_P,
+ OB => USER_SMA_CLOCK_N,
+ I => USER_SMA_CLOCK_S);
+
+BUF_jittercleanerclock_inst : OBUFDS -- reference clock for jitter cleaner
+ generic map(
+ IOSTANDARD => "LVDS_25")
+ port map(
+ O => REC_CLOCK_C_P,
+ OB => REC_CLOCK_C_N,
+ I => clk_200_i);
+
+
+PACKETIN_clock <= clk_160div3_i; -- clk_80_i;
+MUX_clock <= clk_80_i; --clk_100_i;
+PACKETOUT_clock <= clk_80_i;
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+THE_MEDIA_UPLINK : trb_net16_med_sync_gtx2_kintex7_sfp
+ port map(
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ SODA_clock => clk_SODA200_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ disable_GTX_reset => '0',
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ CLK_RX_HALF_OUT => open,
+ CLK_RX_FULL_OUT => open,
+ --SFP Connection
+ SODA_RXD_P_IN => SFP_RX_P,
+ SODA_RXD_N_IN => SFP_RX_N,
+ SODA_TXD_P_OUT => SFP_TX_P,
+ SODA_TXD_N_OUT => SFP_TX_N,
+ SODA_REFCLK_P_IN => SGMIICLK_Q0_P,
+ SODA_REFCLK_N_IN => SGMIICLK_Q0_N,
+ SODA_PRSNT_N_IN => SD_LOS_S,
+ SODA_LOS_IN => SD_LOS_S,
+ SODA_TXDIS_OUT => SD_TXDIS_S,
+ SODA_DLM_IN => DLM_to_uplink_S,
+ SODA_DLM_WORD_IN => DLM_WORD_to_uplink_S,
+ SODA_DLM_OUT => DLM_from_uplink_S,
+ SODA_DLM_WORD_OUT => DLM_WORD_from_uplink_S,
+ SODA_CLOCK_OUT => SODA_IN_rxUsrClk_S, -- 200MHz
+ SODA_LOCKED_OUT => SODA_IN_rxLocked_S,
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0')
+ );
+process(clk_100_i)
+begin
+ if (rising_edge(clk_100_i)) then
+ SD_LOS_S <= SFP_LOS_LS;
+ end if;
+end process;
+
+
+THE_DATAOUTPUT: GTX_dataoutputwrapper port map(
+ sysClk => clk_100_i,
+ refClk_P => q2_clk1_gtrefclk_S,
+ refClk_N => q3_clk0_gtrefclk_S,
+ clock_out => dataout_clock_S,
+ clock_rec => dataout_clock_rec_S,
+ reset => reset_i,
+ data_in => dataout_data_S,
+ kchar_in => dataout_charisK_S,
+ data_out => dataout_rec_data_S,
+ kchar_out => dataout_rec_charisK_S,
+ G0_txP => X0Y14_TX_P_OPAD,
+ G0_txN => X0Y14_TX_N_OPAD,
+ G0_rxP => X0Y14_RX_P_IPAD,
+ G0_rxN => X0Y14_RX_N_IPAD,
+ G0_LOS => fmc_sfp_los(2),
+ tx_locked => dataout_tx_locked_S,
+ GT0_QPLLOUTCLK_IN => gt0_qplloutclk_S,
+ GT0_QPLLOUTREFCLK_IN => gt0_qplloutrefclk_S
+ );
+
+process(dataout_clock_rec_S)
+begin
+ if (rising_edge(dataout_clock_rec_S)) then
+ if ((dataout_rec_data_S(15 downto 8)=x"3C") and (dataout_rec_charisK_S(1)='1')) or
+ ((dataout_rec_data_S(7 downto 0)=x"3C") and (dataout_rec_charisK_S(0)='1')) then
+ dataout_allowed_rec_S <= '0';
+ else
+ dataout_allowed_rec_S <= '1';
+ end if;
+ end if;
+end process;
+sync_dataout_allowed: sync_bit port map(
+ clock => dataout_clock_S,
+ data_in => dataout_allowed_rec_S,
+ data_out => dataout_allowed_S);
+
+THE_DATACONVERSION : dataconversion_for_serdes16
+ port map (
+ DATA_CLK => PACKETOUT_clock,
+ CLK => dataout_clock_S,
+ RESET => reset_i,
+ TX_READY => dataout_tx_locked_S,
+ SFP_MOD0 => '0',
+ SFP_LOS => '0', --//fmc_sfp_los(2),
+ TX_ALLOWED => dataout_allowed_S,
+ TX_DATA => dataout_data_S,
+ TX_K => dataout_charisK_S,
+ DATA_IN_ALLOWED => data64_allowed_S, -- data64b_muxed_allowed,
+ DATA_IN => data64_S, -- data64b_muxed,
+ DATA_IN_WRITE => data64_write_S, -- data64b_muxed_write,
+ DATA_IN_FIRST => data64_first_S, -- data64b_muxed_first,
+ DATA_IN_LAST => data64_last_S, -- data64b_muxed_last,
+ DATA_IN_ERROR => data64_error_S -- data64b_muxed_error
+ );
+
+data64b_muxed_allowed <= data64_allowed_S;
+data64_S <= data64b_muxed;
+data64_first_S <= data64b_muxed_first;
+data64_last_S <= data64b_muxed_last;
+data64_write_S <= data64b_muxed_write;
+data64_error_S <= data64b_muxed_error;
+
+
+data64b_muxed_allowed_S <= '1' when (data64b_muxed_allowed='1') and (data64b_muxed_allowed0_S='1') else '0';
+
+THE_CHECK : CN_checkdata port map(
+ clock => PACKETOUT_clock,
+ reset => '0',
+ data_in => data64b_muxed,
+ data_in_first => data64b_muxed_first,
+ data_in_last => data64b_muxed_last,
+ data_in_error => data64b_muxed_error,
+ data_in_write => data64b_muxed_write,
+ dataerror => data64b_dataerror,
+ timeerror => data64b_timeerror,
+ waveerror => data64b_waveerror,
+ testword0 => open);
+
+
+process(PACKETOUT_clock)
+constant MINCLOCKSBETWEENPACKETS : integer := ADCCLOCKFREQUENCY/500000; -- 2048;
+variable counting : boolean := FALSE;
+variable counterpacket : integer range 0 to 65535 := 0;
+variable counterwait : integer range 0 to 65535 := 0;
+begin
+ if (rising_edge(PACKETOUT_clock)) then
+ data64b_muxed_error_S <= '0';
+ if (data64b_muxed_write='1') and (data64b_muxed_last='1') then
+ data64b_muxed_allowed0_S <= '0';
+ counterwait := counterpacket;
+ elsif (counterwait<MINCLOCKSBETWEENPACKETS) and (no_packet_limit_S='0') then
+ data64b_muxed_allowed0_S <= '0';
+ counterwait := counterwait+1;
+ else
+ data64b_muxed_allowed0_S <= data64b_muxed_allowed;
+ end if;
+ if (data64b_muxed_write='1') and (data64b_muxed_first='1') then
+ counting := TRUE;
+ counterpacket := 0;
+ elsif (data64b_muxed_write='1') and (data64b_muxed_last='1') then
+ counting := FALSE;
+ else
+ if (counting) and (counterpacket<65535) then
+ counterpacket := counterpacket+1;
+ end if;
+ end if;
+ if (data64b_muxed_write='1') then
+ if (data64b_muxed_first='1') and (data64b_muxed_last='1') then
+ data64b_muxed_error_S <= '1';
+ elsif data64b_muxed_first='1' then
+ if data64b_muxed_busy_S='1' then
+ data64b_muxed_error_S <= '1';
+ end if;
+ data64b_muxed_busy_S <= '1';
+ elsif data64b_muxed_last='1' then
+ if data64b_muxed_busy_S='0' then
+ data64b_muxed_error_S <= '1';
+ end if;
+ data64b_muxed_busy_S <= '0';
+ else
+ end if;
+ end if;
+ end if;
+end process;
+
+process(PACKETOUT_clock)
+begin
+ if (rising_edge(PACKETOUT_clock)) then
+ debug_nextsuperburst_S <= '0';
+ debug_superburst_error_S <= '0';
+ if data64b_muxed_write='1' then
+ if data64b_muxed_first='1' then
+ debug_counter_S <= 0;
+ if data64b_muxed(47 downto 32) = conv_std_logic_vector(16,16) then
+ debug_emptypacket_S <= '1';
+ else
+ debug_emptypacket_S <= '0';
+ end if;
+ debug_nrofbytes_S <= data64b_muxed(47 downto 32);
+ elsif debug_counter_S=0 then
+ if data64b_muxed(63)='0' then -- pulse data
+ if (debug_superburst_S+1) /= data64b_muxed(30 downto 0) then
+ debug_superburst_error_S <= '1';
+ end if;
+ debug_nextsuperburst_S <= '1';
+ debug_superburst_S <= data64b_muxed(30 downto 0);
+ for i in 1 to 7 loop
+ debug_superbursts_S(i) <= debug_superbursts_S(i-1);
+ end loop;
+ debug_superbursts_S(0) <= data64b_muxed(7 downto 0);
+ end if;
+ if data64b_muxed_last='1' then
+ if debug_nrofbytes_S /= conv_std_logic_vector((debug_counter_S+2)*8,16) then
+ debug_superburst_error_S <= '1';
+ end if;
+ end if;
+ debug_counter_S <= debug_counter_S+1;
+ elsif data64b_muxed_last='1' then
+ if debug_nrofbytes_S /= conv_std_logic_vector((debug_counter_S+2)*8,16) then
+ debug_superburst_error_S <= '1';
+ end if;
+ debug_counter_S <= debug_counter_S+1;
+ else
+ debug_counter_S <= debug_counter_S+1;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"45",
+ REGIO_COMPILE_TIME => conv_std_logic_vector(VERSION_NUMBER_TIME, 32),
+ REGIO_HARDWARE_VERSION => x"91000001",
+ REGIO_USE_1WIRE_INTERFACE => c_NO, --c_YES,c_NO,c_MONITOR
+ REGIO_INIT_ADDRESS => x"f310",
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => 100,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => 13, --13
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out, -- open, --
+ MED_DATA_OUT => med_data_out, -- open, --
+ MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out, -- open, --
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => '0',
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_OUT => trg_invalid_i,
+
+ LVL1_TRG_TYPE_OUT => trg_type_i,
+ LVL1_TRG_NUMBER_OUT => trg_number_i,
+ LVL1_TRG_CODE_OUT => trg_code_i,
+ LVL1_TRG_INFORMATION_OUT => trg_information_i,
+ LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
+ TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+ TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
+ TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
+ TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN(0) => '0',
+ FEE_TRG_STATUSBITS_IN => (others => '0'),
+ FEE_DATA_IN => (others => '0'),
+ FEE_DATA_WRITE_IN(0) => '0',
+ FEE_DATA_FINISHED_IN(0) => '0',
+ FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => (others => '0'), --CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => open, -- TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"e000", 3 => x"e100", 4 => x"e200", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 2, 3 => 4, 4 => 4, others => 0)
+-- PORT_MASK_ENABLE => 0
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_READ_ENABLE_OUT(2) => dc_read_en,
+ BUS_READ_ENABLE_OUT(3) => soda_read_en,
+ BUS_READ_ENABLE_OUT(4) => sodasrc_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_WRITE_ENABLE_OUT(2) => dc_write_en,
+ BUS_WRITE_ENABLE_OUT(3) => soda_write_en,
+ BUS_WRITE_ENABLE_OUT(4) => sodasrc_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => dc_data_in,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
+ BUS_DATA_OUT(4*32+31 downto 4*32) => sodasrc_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => dumadr0(0*16+15 downto 0*16+1),
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => dumadr0(1*16+15 downto 1*16+6),
+ BUS_ADDR_OUT(2*16+1 downto 2*16) => dc_addr,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+2) => dumadr0(2*16+15 downto 2*16+2),
+ BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
+ BUS_ADDR_OUT(3*16+15 downto 3*16+4) => dumadr0(3*16+15 downto 3*16+4),
+ BUS_ADDR_OUT(4*16+3 downto 4*16) => sodasrc_addr,
+ BUS_ADDR_OUT(4*16+15 downto 4*16+4) => dumadr0(4*16+15 downto 4*16+4),
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATA_IN(2*32+31 downto 2*32) => dc_data_out,
+ BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
+ BUS_DATA_IN(4*32+31 downto 4*32) => sodasrc_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_DATAREADY_IN(2) => dc_ack,
+ BUS_DATAREADY_IN(3) => soda_ack,
+ BUS_DATAREADY_IN(4) => sodasrc_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(2) => dc_ack,
+ BUS_WRITE_ACK_IN(3) => soda_ack,
+ BUS_WRITE_ACK_IN(4) => sodasrc_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(2) => dc_busy,
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_NO_MORE_DATA_IN(4) => '0',
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => '0',
+ BUS_UNKNOWN_ADDR_IN(4) => '0',
+ BUS_TIMEOUT_OUT => open,
+ -- BUS_TIMEOUT_OUT(0) => open,
+ -- BUS_TIMEOUT_OUT(1) => open,
+ -- BUS_TIMEOUT_OUT(2) => open,
+ -- BUS_TIMEOUT_OUT(3) => open,
+ -- BUS_TIMEOUT_OUT(4) => open,
+
+ --Bus Handler (SPI CTRL)
+ --Bus Handler (SPI Memory)
+ --Bus Handler (test port)
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+ THE_SPI_MASTER : spi_master
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => spictrl_addr,
+ BUS_DATA_IN => spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => open, -- FLASH_CS,
+ SPI_SDI_IN => '0', -- FLASH_DOUT,
+ SPI_SDO_OUT => open, -- FLASH_DIN,
+ SPI_SCK_OUT => open, -- FLASH_CLK,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+-- data memory for SPI accesses
+ THE_SPI_MEMORY : spi_databus_memory
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+ THE_FPGA_REBOOT : fpga_reboot
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ DO_REBOOT => common_ctrl_reg(15),
+ PROGRAMN => open -- PROGRAMN
+ );
+
+THE_DATACONCENTRATOR: DC_module_TRB3 port map(
+ slowcontrol_clock => clk_100_i,
+ packet_in_clock => PACKETIN_clock,
+ MUX_clock => MUX_clock,
+ packet_out_clock => PACKETOUT_clock,
+ SODA_clock => clk_SODA200_i,
+ reset => reset_i,
+
+-- Slave bus
+ BUS_READ_IN => dc_read_en,
+ BUS_WRITE_IN => dc_write_en,
+ BUS_BUSY_OUT => dc_busy,
+ BUS_ACK_OUT => dc_ack,
+ BUS_ADDR_IN => dc_addr,
+ BUS_DATA_IN => dc_data_in,
+ BUS_DATA_OUT => dc_data_out,
+
+-- fiber interface signals:
+ fiber_txlocked => fiber_txlocked_S,
+ fiber_rxlocked => fiber_rxlocked_S,
+ reset_fibers => reset_fibers_S,
+ fiber_data32write => fiber_data32write_S,
+ fiber_data32out => fiber_data32out_S,
+ fiber_data32fifofull => fiber_data32fifofull_S,
+ fiber_data32read => fiber_data32read_S,
+ fiber_data32present => fiber_data32present_S,
+ fiber_data32in => fiber_data32in_S,
+ fiber_rxerror => fiber_rxerror_S,
+
+-- SODA signals
+ superburst_number => superburst_number_S,
+ superburst_update => superburst_update_S,
+ SODA_enable => open,
+ EnableExternalSODA => EnableExternalSODA_S,
+
+-- 64 bits data output
+ data_out_allowed => data64b_muxed_allowed_S,
+ data_out => data64b_muxed,
+ data_out_write => data64b_muxed_write,
+ data_out_first => data64b_muxed_first,
+ data_out_last => data64b_muxed_last,
+ data_out_error => data64b_muxed_error,
+ no_packet_limit => no_packet_limit_S,
+
+-- testpoints
+ testword0 => open,
+ testword0clock => open,
+ testword1 => open,
+ testword2 => open
+ );
+
+sync_reset_SODA_clock: sync_bit port map(
+ clock => clk_SODA200_i,
+ data_in => reset_i,
+ data_out => reset_SODAclock_S);
+
+soda_packet_handler1 : soda_packet_handler port map(
+ SODACLK => clk_SODA200_i,
+ RESET => reset_SODAclock_S,
+ CLEAR => '0',
+ CLK_EN => '1',
+ --Internal Connection
+ START_OF_SUPERBURST_OUT => superburst_update_S,
+ SUPER_BURST_NR_OUT => superburst_number_S,
+ START_OF_CALIBRATION_OUT => open,
+ SODA_CMD_VALID_OUT => open,
+ SODA_CMD_WORD_OUT => open,
+ RX_DLM_IN => DLM_to_bottom_S(0),
+ RX_DLM_WORD_IN => DLM_WORD_to_bottom_S(0)
+);
+
+reset_fee_S <= '1' when (reset_i='1') or (SODA_IN_rxLocked_S='0') else '0';
+
+THE_FEE_SERDES: serdesQuadBufLayerMUX port map(
+ refClk => txpll_clocks_S(0), --//clk_SODA200_i,
+ refClk_P => q2_clk1_gtrefclk_S,
+ refClk_N => q3_clk0_gtrefclk_S,
+ sysClk => clk_100_i,
+ reset => reset_fee_S,
+ reset_fibers => reset_fibers_S,
+ clk_SODA200 => clk_SODA200_i,
+ txAsyncClk => clk_100_i, -- slowcontrol_clock
+ rxAsyncClk => PACKETIN_clock,
+ txpll_clocks => txpll_clocks_S,
+
+ G0_txAsyncData => fiber_data32out_S(0),
+ G0_txAsyncDataWrite => fiber_data32write_S(0),
+ G0_txAsyncFifoFull => fiber_data32fifofull_S(0),
+ G0_rxAsyncData => fiber_data32in_S(0),
+ G0_rxAsyncDataRead => fiber_data32read_S(0),
+ G0_rxAsyncDataOverflow => open,
+ G0_rxAsyncDataPresent => fiber_data32present_S(0),
+ G0_txLocked => fiber_txlocked_S(0),
+ G0_rxLocked => fiber_rxlocked_S(0),
+ G0_error => fiber_rxerror_S(0),
+
+ G0_TX_DLM => DLM_to_bottom_S(0),
+ G0_TX_DLM_WORD => DLM_WORD_to_bottom_S(0),
+ G0_RX_DLM => DLM_from_bottom_S(0),
+ G0_RX_DLM_WORD => DLM_WORD_from_bottom_S(0),
+ G0_LOS => fmc_sfp_los(3),
+ G0_txP => X0Y12_TX_P_OPAD,
+ G0_txN => X0Y12_TX_N_OPAD,
+ G0_rxP => X0Y12_RX_P_IPAD,
+ G0_rxN => X0Y12_RX_N_IPAD,
+
+ G1_txAsyncData => fiber_data32out_S(1),
+ G1_txAsyncDataWrite => fiber_data32write_S(1),
+ G1_txAsyncFifoFull => fiber_data32fifofull_S(1),
+ G1_rxAsyncData => fiber_data32in_S(1),
+ G1_rxAsyncDataRead => fiber_data32read_S(1),
+ G1_rxAsyncDataOverflow => open,
+ G1_rxAsyncDataPresent => fiber_data32present_S(1),
+ G1_txLocked => fiber_txlocked_S(1),
+ G1_rxLocked => fiber_rxlocked_S(1),
+ G1_error => fiber_rxerror_S(1),
+ G1_TX_DLM => DLM_to_bottom_S(1),
+ G1_TX_DLM_WORD => DLM_WORD_to_bottom_S(1),
+ G1_RX_DLM => DLM_from_bottom_S(1),
+ G1_RX_DLM_WORD => DLM_WORD_from_bottom_S(1),
+ G1_LOS => fmc_sfp_los(2),
+ G1_txP => X0Y13_TX_P_OPAD,
+ G1_txN => X0Y13_TX_N_OPAD,
+ G1_rxP => X0Y13_RX_P_IPAD,
+ G1_rxN => X0Y13_RX_N_IPAD,
+
+ G2_txAsyncData => fiber_data32out_S(2),
+ G2_txAsyncDataWrite => fiber_data32write_S(2),
+ G2_txAsyncFifoFull => fiber_data32fifofull_S(2),
+ G2_rxAsyncData => fiber_data32in_S(2),
+ G2_rxAsyncDataRead => fiber_data32read_S(2),
+ G2_rxAsyncDataOverflow => open,
+ G2_rxAsyncDataPresent => fiber_data32present_S(2),
+ G2_txLocked => fiber_txlocked_S(2),
+ G2_rxLocked => fiber_rxlocked_S(2),
+ G2_error => fiber_rxerror_S(2),
+ G2_TX_DLM => DLM_to_bottom_S(2),
+ G2_TX_DLM_WORD => DLM_WORD_to_bottom_S(2),
+ G2_RX_DLM => DLM_from_bottom_S(2),
+ G2_RX_DLM_WORD => DLM_WORD_from_bottom_S(2),
+ G2_LOS => fmc_sfp_los(1),
+ G2_txP => open, -- X0Y14_TX_P_OPAD,
+ G2_txN => open, -- X0Y14_TX_N_OPAD,
+ G2_rxP => '0', -- X0Y14_RX_P_IPAD,
+ G2_rxN => '0', -- X0Y14_RX_N_IPAD,
+
+ G3_txAsyncData => fiber_data32out_S(3),
+ G3_txAsyncDataWrite => fiber_data32write_S(3),
+ G3_txAsyncFifoFull => fiber_data32fifofull_S(3),
+ G3_rxAsyncData => fiber_data32in_S(3),
+ G3_rxAsyncDataRead => fiber_data32read_S(3),
+ G3_rxAsyncDataOverflow => open,
+ G3_rxAsyncDataPresent => fiber_data32present_S(3),
+ G3_txLocked => fiber_txlocked_S(3),
+ G3_rxLocked => fiber_rxlocked_S(3),
+ G3_error => fiber_rxerror_S(3),
+ G3_TX_DLM => DLM_to_bottom_S(3),
+ G3_TX_DLM_WORD => DLM_WORD_to_bottom_S(3),
+ G3_RX_DLM => DLM_from_bottom_S(3),
+ G3_RX_DLM_WORD => DLM_WORD_from_bottom_S(3),
+ G3_LOS => fmc_sfp_los(0),
+ G3_txP => open, -- X0Y15_TX_P_OPAD,
+ G3_txN => open, -- X0Y15_TX_N_OPAD,
+ G3_rxP => '0', -- X0Y15_RX_P_IPAD,
+ G3_rxN => '0', -- X0Y15_RX_N_IPAD,
+
+ LEDs_link_ok => open,
+ LEDs_rx => open,
+ LEDs_tx => open,
+ GT0_QPLLOUTCLK_IN => gt0_qplloutclk_S,
+ GT0_QPLLOUTREFCLK_IN => gt0_qplloutrefclk_S,
+
+ testPin => open,
+ testword0 => open,
+ testword0clock => open
+ );
+
+ibufds_instq2_clk1 : IBUFDS_GTE2 port map(
+ O => q2_clk1_gtrefclk_S,
+ ODIV2 => open,
+ CEB => '0',
+ I => SMA_MGT_REFCLK_P,
+ IB => SMA_MGT_REFCLK_N);
+
+ibufds_instq3_clk0 : IBUFDS_GTE2 port map(
+ O => q3_clk0_gtrefclk_S,
+ ODIV2 => open,
+ CEB => '0',
+ I => Q3_CLK0_MGTREFCLK_P_IPAD,
+ IB => Q3_CLK0_MGTREFCLK_N_IPAD);
+
+
+THE_SODA_INPUT: DC_SODAserdesWrapper port map(
+ refClk => '0',
+ refClk_P => q2_clk1_gtrefclk_S,
+ refClk_N => q3_clk0_gtrefclk_S,
+ sysClk => clk_100_i,
+ asyncclk => clk_100_i,
+ gtpReset => reset_i, -- SODA_reset_S,
+ disable_GTX_reset => '0',
+
+ txData => (others => '0'),
+ txCharIsK => '0',
+ txP => X0Y15_TX_P_OPAD,
+ txN => X0Y15_TX_N_OPAD,
+ txUsrClk => open,
+ txLocked => open,
+
+ rxData => open,
+ rxCharIsK => open,
+ rxNotInTable => open,
+ rxP => X0Y15_RX_P_IPAD,
+ rxN => X0Y15_RX_N_IPAD,
+ rxUsrClk => open,
+ rxUsrClkdiv2 => open,
+ rxLocked => open,
+ GT0_QPLLOUTCLK_OUT => gt0_qplloutclk_S,
+ GT0_QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_S,
+ resetDone => open
+ );
+
+
+
+fmc_led(0) <= fmc_sfp_los(3);
+fmc_led(1) <= fmc_sfp_los(2);
+fmc_led(2) <= fmc_sfp_los(1);
+fmc_led(3) <= fmc_sfp_los(0);
+
+THE_SODA_HUB: soda_hub
+ port map(
+ SYSCLK => clk_100_i,
+ SODACLK => clk_SODA200_i,
+ RESET => SODA_reset_S,
+ CLEAR => '0',
+ CLK_EN => '1',
+
+ -- SINGLE DUBPLEX UP-LINK TO THE TOP
+ RXUP_DLM_IN => DLM_hub2uplink_S,
+ RXUP_DLM_WORD_IN => DLM_WORD_hub2uplink_S,
+ TXUP_DLM_OUT => DLM_to_uplink_S,
+ TXUP_DLM_WORD_OUT => DLM_WORD_to_uplink_S,
+ TXUP_DLM_PREVIEW_OUT => open,
+ UPLINK_PHASE_IN => c_PHASE_H,
+
+ -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
+ RXDN_DLM_IN => DLM_from_bottom_S,
+ RXDN_DLM_WORD_IN => DLM_WORD_from_bottom_S,
+ TXDN_DLM_OUT => DLM_to_bottom_S,
+ TXDN_DLM_WORD_OUT => DLM_WORD_to_bottom_S,
+ TXDN_DLM_PREVIEW_OUT => open,
+ DNLINK_PHASE_IN => (others => c_PHASE_H),
+
+ SODA_DATA_IN => soda_data_in,
+ SODA_DATA_OUT => soda_data_out,
+ SODA_ADDR_IN => soda_addr,
+ SODA_READ_IN => soda_read_en,
+ SODA_WRITE_IN => soda_write_en,
+ SODA_ACK_OUT => soda_ack,
+ LEDS_OUT => open,
+ LINK_DEBUG_IN => (others => '0')
+ );
+
+THE_JITTERCLEANER1: jittercleaner_200M port map(
+ clk_in => jittercleaner_clock_in_S,
+ clk_out => jittercleaner_clock_out0_S,
+ reset => jittercleaner_reset_S,
+ locked => open);
+THE_JITTERCLEANER2: pll_in200_out200 port map(
+ clk_in1 => jittercleaner_clock_out0_S,
+ clk_out1 => jittercleaner_clock_out_S,
+ reset => jittercleaner_reset_S,
+ locked => jittercleaner_locked_S);
+
+-- THE_JITTERCLEANER: jittercleaner_200M port map(
+ -- clk_in => jittercleaner_clock_in_S,
+ -- clk_out => jittercleaner_clock_out_S,
+ -- reset => jittercleaner_reset_S,
+ -- locked => jittercleaner_locked_S);
+-- THE_JITTERCLEANER: BUFG
+ -- port map
+ -- (O => jittercleaner_clock_out_S,
+ -- I => jittercleaner_clock_in_S);
+-- jittercleaner_locked_S <= '1';
+
+gen_externalsoda: if EXTERNAL_SODA=true generate
+ process(clk_SODA200_i)
+ begin
+ if rising_edge(clk_SODA200_i) then
+ DLM_hub2uplink_S <= '0';
+ if DLM_from_uplink_S='1' then
+ DLM_hub2uplink_S <= '1';
+ DLM_WORD_hub2uplink_S <= DLM_WORD_from_uplink_S;
+ end if;
+ end if;
+ end process;
+ USER_SMA_CLOCK_S <= clk_SODA200_i;
+ clk_SODA200_i <= jittercleaner_clock_out_S; -- clk_200_i; --//try SODA_IN_rxUsrClk_S; --// jittercleaner_clock_out_S;
+ jittercleaner_reset_S <= not SODA_IN_rxLocked_S;
+ SODA_reset_S <= not jittercleaner_locked_S;
+ jittercleaner_clock_in_S <= SODA_IN_rxUsrClk_S; -- clk_200_i; --//try ;
+end generate;
+
+gen_internalsoda: if EXTERNAL_SODA=false generate
+ DLM_hub2uplink_S <= DLM_source2hub_S;
+ DLM_WORD_hub2uplink_S <= DLM_WORD_source2hub_S;
+ clk_SODA200_i <= txpll_clocks_S(0);
+ USER_SMA_CLOCK_S <= clk_200_i;
+ SODA_reset_S <= reset_i;
+ jittercleaner_reset_S <= reset_i;
+ jittercleaner_clock_in_S <= clk_200_i;
+end generate;
+
+
+SMA_GPIO_output : OBUFDS
+ generic map(
+ IOSTANDARD => "LVDS_25")
+ port map(
+ O => USER_SMA_GPIO_P,
+ OB => USER_SMA_GPIO_N,
+ I => superburst_update_S);
+---------------------------------------------------------------------------
+-- The Soda Central
+---------------------------------------------------------------------------
+soda_source1: soda_source
+ port map(
+ SYSCLK => clk_100_i,
+ SODACLK => clk_SODA200_i,
+ RESET => reset_i,
+ --Internal Connection
+ SODA_BURST_PULSE_IN => SODA_burst_pulse_S,
+ SODA_CYCLE_IN => soda_40mhz_cycle_S,
+
+ RX_DLM_WORD_IN => DLM_WORD_to_uplink_S,
+ RX_DLM_IN => DLM_to_uplink_S,
+ TX_DLM_OUT => DLM_source2hub_S,
+ TX_DLM_WORD_OUT => DLM_WORD_source2hub_S,
+
+ TX_DLM_PREVIEW_OUT => open,
+ LINK_PHASE_IN => c_PHASE_H,
+
+ SODA_DATA_IN => sodasrc_data_in,
+ SODA_DATA_OUT => sodasrc_data_out,
+ SODA_ADDR_IN => sodasrc_addr,
+ SODA_READ_IN => sodasrc_read_en,
+ SODA_WRITE_IN => sodasrc_write_en,
+ SODA_ACK_OUT => sodasrc_ack,
+
+ LEDS_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- Burst- and 40MHz cycle generator
+---------------------------------------------------------------------------
+THE_SOB_SOURCE : soda_start_of_burst_control
+ generic map(
+ CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns
+ CYCLE_PERIOD => cSODA_CYCLE_PERIOD, -- cycle-period in ns
+ BURST_PERIOD => cBURST_PERIOD -- burst-period in ns
+ )
+ port map(
+ SODA_CLK => clk_SODA200_i,
+ RESET => reset_i,
+ SODA_BURST_PULSE_OUT => SODA_burst_pulse_S,
+ SODA_40MHZ_CYCLE_OUT => soda_40mhz_cycle_S
+ );
+
+XADC_GPIO_0 <= DLM_hub2uplink_S; -- debug_clkdiv2_1;
+XADC_GPIO_1 <= DLM_to_bottom_S(0); --debug_clkdiv2_2;
+XADC_GPIO_2 <= debug_clkdiv2_3;
+XADC_GPIO_3 <= debug_clkdiv2_4;
+
+process(clk_SODA200_i)
+ begin
+ if rising_edge(clk_SODA200_i) then
+ debug_clkdiv2_1 <= not debug_clkdiv2_1;
+ end if;
+end process;
+process(clk_200_i)
+ begin
+ if rising_edge(clk_200_i) then
+ debug_clkdiv2_2 <= not debug_clkdiv2_2;
+ end if;
+end process;
+process(USER_SMA_CLOCK_S)
+ begin
+ if rising_edge(USER_SMA_CLOCK_S) then
+ debug_clkdiv2_3 <= not debug_clkdiv2_3;
+ end if;
+end process;
+process(SODA_IN_rxUsrClk_S)
+ begin
+ if rising_edge(SODA_IN_rxUsrClk_S) then
+ debug_clkdiv2_4 <= not debug_clkdiv2_4;
+ end if;
+end process;
+
+
+-- LED_LINKOK(1) <= not LEDs_link_ok_i(0);
+-- LED_LINKOK(6) <= not LEDs_link_ok_i(1);
+-- LED_LINKOK(2) <= not LEDs_link_ok_i(2);
+-- LED_LINKOK(4) <= not LEDs_link_ok_i(3);
+-- LED_LINKOK(3) <= '1';
+-- LED_LINKOK(5) <= '1';
+
+-- LED_RX(1) <= not LEDs_rx_i(0);
+-- LED_RX(6) <= not LEDs_rx_i(1);
+-- LED_RX(2) <= not LEDs_rx_i(2);
+-- LED_RX(4) <= not LEDs_rx_i(3);
+-- LED_RX(3) <= '1';
+-- LED_RX(5) <= '1';
+
+-- LED_TX(1) <= not LEDs_tx_i(0);
+-- LED_TX(6) <= not LEDs_tx_i(1);
+-- LED_TX(2) <= not LEDs_tx_i(2);
+-- LED_TX(4) <= not LEDs_tx_i(3);
+-- LED_TX(3) <= '1';
+-- LED_TX(5) <= '1';
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+-- LED_GREEN <= not med_stat_op(9);
+-- LED_ORANGE <= not med_stat_op(10);
+-- LED_RED <= not time_counter(26);
+-- LED_YELLOW <= not med_stat_op(11);
+
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------
+ --TEST_LINE(7 downto 0) <= med_data_in(7 downto 0);
+ --TEST_LINE(8) <= med_dataready_in;
+ --TEST_LINE(9) <= med_dataready_out;
+ --TEST_LINE(10) <= stat_reg_strobe(0);
+ --TEST_LINE(15 downto 11) <= (others => '0');
+
+
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ fmc_user_switch <= (others => 'Z');
+-- fmc_sfp_tx_fault
+ fmc_sfp_tx_disable <= (others => '0');
+ fmc_sfp_rate_sel <= (others => '0');
+-- fmc_sfp_mod_def0 <= (others => '0');
+-- Q3_CLK0_MGTREFCLK_P_IPAD : in std_logic;
+-- Q3_CLK0_MGTREFCLK_N_IPAD : in std_logic;
+
+process(PACKETOUT_clock)
+ begin
+ if rising_edge(PACKETOUT_clock) then
+ if data64b_muxed_write='1' then
+ if data64b_muxed_first='1' then
+ data64b_count <= (others => '0');
+ else
+ data64b_count <= data64b_count+1;
+ end if;
+ end if;
+ end if;
+end process;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 07-03-2016
+-- Module Name: CN_checkcluster
+-- Description: Checks cluster packets for errors
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_checkcluster
+-- Checks cluster packets for errors in hitdata, time consistancy
+-- It can check packets with or without the first Panda header word that contains the last packet bit, packet number and packet size,
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word0: (depending on headerword0)
+-- bit63 = last-packet flag
+-- bit62..48 = packet number
+-- bit47..32 = data size in bytes
+-- bit31..0 = Not used (same as HADES)
+-- 64bits word1:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- for cluster data
+-- 64bits word2, clusterresults
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..30 = diameter
+-- bit29..20 = Y position, multiplied by 2
+-- bit19..10 = X position, multiplied by 2
+-- bit9..0 = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+
+--
+-- Library
+--
+--
+-- Inputs:
+-- clock : clock for data input
+-- reset : reset
+-- headerword0 : '0' : no Panda header word expected, '1' : Panda header word expected with last packet bit, packet number and packet size
+-- data_in : 64bits data
+-- data_in_first : indicates that 64bits data is first in packet
+-- data_in_last : indicates that 64bits data is last in packet
+-- data_in_error : indicates that 64bits data ontains an error
+-- data_in_write : write signal for 64bits data
+--
+--
+-- Outputs:
+-- dataerror : error in data: wrong header, missing first or last bit, superburst number error or time error
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity CN_checkcluster is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ headerword0 : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_error : in std_logic;
+ data_in_write : in std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end CN_checkcluster;
+
+
+architecture behaviour of CN_checkcluster is
+
+signal data_in_busy_S : std_logic := '0';
+signal dataerror1_S : std_logic := '0';
+signal dataerror2_S : std_logic := '0';
+signal wave_S : std_logic := '0';
+signal prev_time_S : std_logic_vector(23 downto 0) := (others => '0');
+signal superburst_S : std_logic_vector(30 downto 0) := (others => '0');
+signal prev_superburst_S : std_logic_vector(30 downto 0) := (others => '0');
+signal packetsize_S : integer range 0 to 65535 := 0;
+signal data_in_count_S : integer range 0 to 65535 := 0;
+signal prev_data_S : std_logic_vector(63 downto 0) := (others => '0');
+
+signal data_in_second_S : std_logic := '0';
+signal newcluster_S : std_logic := '0';
+signal last_received_S : std_logic := '1';
+signal hits_index_S : integer range 0 to 1023 := 0;
+signal nrofhits_S : integer range 0 to 1023 := 0;
+
+begin
+
+dataerror <= '1' when ((dataerror1_S='1') or (dataerror2_S='1')) and (prev_superburst_S>1) else '0';
+
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ dataerror1_S <= '0';
+ if reset='1' then
+ data_in_busy_S <= '0';
+ else
+ if (data_in_write='1') then
+ if (data_in_first='1') and (data_in_last='1') and (headerword0='1') then
+ dataerror1_S <= '1';
+ elsif (data_in_first='1') and (data_in_last='1') and (headerword0='0') then
+ data_in_busy_S <= '0';
+ elsif data_in_first='1' then
+ if data_in_busy_S='1' then
+ dataerror1_S <= '1';
+ end if;
+ data_in_busy_S <= '1';
+ elsif data_in_last='1' then
+ if data_in_busy_S='0' then
+ dataerror1_S <= '1';
+ end if;
+ data_in_busy_S <= '0';
+ else
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0);
+begin
+ if (rising_edge(clock)) then
+ dataerror2_S <= '0';
+ if reset='1' then
+ newcluster_S <= '0';
+ last_received_S <= '1';
+ data_in_second_S <= '0';
+ prev_superburst_S <= (others => '0');
+ else
+ if (data_in_write='1') then
+ if prev_data_S=data_in then
+ dataerror2_S <= '1';
+ end if;
+ prev_data_S <= data_in;
+ if (data_in_first='1') or (data_in_second_S='1') then
+ if (headerword0='1') and (data_in_second_S='0') then
+ data_in_count_S <= 1;
+ if data_in(63)='0' then
+ dataerror2_S <= '1';
+ end if;
+ packetsize_S <= conv_integer(unsigned(data_in(47 downto 32)));
+ if data_in(31 downto 0)/=x"00000000" then
+ dataerror2_S <= '1';
+ end if;
+ if last_received_S='0' then
+ dataerror2_S <= '1';
+ end if;
+ if data_in_last='1' then
+ dataerror2_S <= '1';
+ newcluster_S <= '0';
+ last_received_S <= '1';
+ data_in_second_S <= '0';
+ else
+ newcluster_S <= '1';
+ last_received_S <= '0';
+ data_in_second_S <= '1';
+ end if;
+ else
+ if (headerword0='1') then
+ data_in_count_S <= data_in_count_S+1;
+ else
+ data_in_count_S <= 1;
+ end if;
+ data_in_second_S <= '0';
+ if last_received_S='0' then
+ dataerror2_S <= '1';
+ end if;
+ if superburst_S+1/=data_in(30 downto 0) then
+ dataerror2_S <= '1';
+ end if;
+ superburst_S <= data_in(30 downto 0);
+ if data_in_last='1' then -- empty superburst
+ newcluster_S <= '0';
+ last_received_S <= '1';
+ if (headerword0='1') and (packetsize_S/=(data_in_count_S+1)*8) then
+ dataerror2_S <= '1';
+ end if;
+ else
+ newcluster_S <= '1';
+ last_received_S <= '0';
+ end if;
+ end if;
+ else
+ if (data_in_last='1') then
+ if (headerword0='1') and (packetsize_S/=(data_in_count_S+1)*8) then
+ dataerror2_S <= '1';
+ end if;
+ end if;
+ data_in_count_S <= data_in_count_S+1;
+ if newcluster_S='1' then
+ if last_received_S='1' then
+ dataerror2_S <= '1';
+ end if;
+ newcluster_S <= '0';
+ nrofhits_S <= conv_integer(unsigned(data_in(9 downto 0)));
+ if conv_integer(unsigned(data_in(9 downto 0)))>0 then
+ end if;
+ hits_index_S <= 0;
+ if data_in_last='1' then
+ last_received_S <= '1';
+ end if;
+ if (prev_superburst_S>superburst_S) or ((prev_superburst_S=superburst_S) and (prev_time_S>data_in(63 downto 40))) then
+ dataerror2_S <= '1';
+ end if;
+ prev_superburst_S <= superburst_S;
+ prev_time_S <= data_in(63 downto 40);
+ else
+ if (data_in_last='1') and (hits_index_S+1/=nrofhits_S) then
+ dataerror2_S <= '1';
+ end if;
+ if (last_received_S='1') and (hits_index_S+1/=nrofhits_S) then
+ dataerror2_S <= '1';
+ end if;
+ if hits_index_S>=nrofhits_S-1 then
+ newcluster_S <= '1';
+ end if;
+ hits_index_S <= hits_index_S+1;
+ if data_in_last='1' then
+ last_received_S <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 07-03-2016
+-- Module Name: CN_checkdata
+-- Description: Checks data packets for errors
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_checkdata
+-- Checks data packets for errors in hitdata, time consistancy or waveforms.
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word1:
+-- bit63 = last-packet flag
+-- bit62..48 = packet number
+-- bit47..32 = data size in bytes
+-- bit31..0 = Not used (same as HADES)
+-- 64bits word2:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- for pulse data
+-- 64bits word3 and further, for each pulse:
+-- bit63..51 = offset in respect to superburst
+-- bit52..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- for wave data
+-- 64bits word3:
+-- bit63..56 = status byte
+-- bit55..40 = adc channel
+-- bit39..32 = number of samples in wave
+-- bit15..0 = timestamp in respect to superburst of the first sample in the waveform
+-- 64bits word4 and further :
+-- bit63..48 = next_adcsample(15:0)
+-- bit47..32 = next_adcsample(15:0)
+-- bit31..16 = next_adcsample(15:0)
+-- bit15..0 = next_adcsample(15:0)
+--
+-- Library
+--
+--
+-- Inputs:
+-- clock : clock for data input
+-- reset : reset
+-- data_in : 64bits data
+-- data_in_first : indicates that 64bits data is first in packet
+-- data_in_last : indicates that 64bits data is last in packet
+-- data_in_error : indicates that 64bits data ontains an error
+-- data_in_write : write signal for 64bits data
+--
+--
+-- Outputs:
+-- dataerror : error in data: wrong header, missing first or last bit
+-- timeerror : superburst number error or time error
+-- waveerror : error in waveform
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity CN_checkdata is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_error : in std_logic;
+ data_in_write : in std_logic;
+ dataerror : out std_logic;
+ timeerror : out std_logic;
+ waveerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end CN_checkdata;
+
+
+architecture behaviour of CN_checkdata is
+
+signal data_in_busy_S : std_logic;
+signal dataerror1_S : std_logic;
+signal dataerror2_S : std_logic;
+signal timeerror1_S : std_logic;
+signal timeerror2_S : std_logic;
+signal timeerror3_S : std_logic;
+signal waveerror1_S : std_logic;
+signal superbursterror_S : std_logic;
+signal wave_S : std_logic;
+signal data_prev_S : std_logic_vector(63 downto 0) := (others => '0');
+signal time_S : std_logic_vector(23 downto 0);
+signal superburst_S : std_logic_vector(30 downto 0);
+signal prev_superburst_S : std_logic_vector(30 downto 0);
+signal prev_wavetime_S : std_logic_vector(15 downto 0);
+signal wavesuperburst_S : std_logic_vector(30 downto 0);
+signal prev_wavesuperburst_S: std_logic_vector(30 downto 0);
+signal packetsize_S : integer range 0 to 65535;
+signal data_in_count_S : integer range 0 to 65535;
+
+begin
+
+dataerror <= '1' when ((dataerror1_S='1') or (dataerror2_S='1')) and (prev_superburst_S>1) else '0';
+timeerror <= '1' when ((timeerror1_S='1') or (timeerror2_S='1') or (timeerror3_S='1')) and (prev_superburst_S>1) else '0';
+waveerror <= waveerror1_S;
+
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ dataerror1_S <= '0';
+ if reset='1' then
+ data_in_busy_S <= '0';
+ else
+ if (data_in_write='1') then
+ if (data_in_first='1') and (data_in_last='1') then
+ dataerror1_S <= '1';
+ elsif data_in_first='1' then
+ if data_in_busy_S='1' then
+ dataerror1_S <= '1';
+ end if;
+ data_in_busy_S <= '1';
+ elsif data_in_last='1' then
+ if data_in_busy_S='0' then
+ dataerror1_S <= '1';
+ end if;
+ data_in_busy_S <= '0';
+ else
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0);
+begin
+ if (rising_edge(clock)) then
+ dataerror2_S <= '0';
+ timeerror1_S <= '0';
+ timeerror2_S <= '0';
+ timeerror3_S <= '0';
+ waveerror1_S <= '0';
+ superbursterror_S <= '0';
+ if reset='1' then
+ prev_superburst_S <= (others => '0');
+ prev_wavesuperburst_S <= (others => '0');
+ else
+ if (data_in_write='1') then
+ if data_prev_S=data_in then
+ dataerror2_S <= '1';
+ end if;
+ data_prev_S <= data_in;
+ if data_in_first='1' then
+ data_in_count_S<=1;
+ if data_in(63)='0' then
+ dataerror2_S <= '1';
+ end if;
+ packetsize_S <= conv_integer(unsigned(data_in(47 downto 32)));
+ if data_in(31 downto 0)/=x"00000000" then
+ dataerror2_S <= '1';
+ end if;
+ else
+ if data_in_last='1' then
+ if packetsize_S/=(data_in_count_S+1)*8 then
+ dataerror2_S <= '1';
+ end if;
+ end if;
+ if data_in_count_S=1 then
+ if data_in(47 downto 32)/=x"5555" then
+ dataerror2_S <= '1';
+ end if;
+ superburst_S <= data_in(30 downto 0);
+ if data_in(63)='1' then
+ wave_S <= '1';
+ wavesuperburst_S <= data_in(30 downto 0);
+ else
+ wave_S <= '0';
+ prev_superburst_V := prev_superburst_S+1;
+ if data_in(30 downto 0)/=prev_superburst_V then
+ timeerror1_S <= '1';
+ end if;
+ if data_in(30 downto 0)<prev_superburst_S then
+ superbursterror_S <= '1';
+ end if;
+ prev_superburst_S <= data_in(30 downto 0);
+ time_S <= (others => '0');
+ end if;
+ elsif (data_in_count_S=2) and (wave_S='1') then
+ if data_in(39 downto 32)<x"02" then
+ waveerror1_S <= '1';
+ end if;
+ if (wavesuperburst_S<prev_wavesuperburst_S) then
+ timeerror3_S <= '1';
+ elsif (wavesuperburst_S=prev_wavesuperburst_S) then
+ if data_in(15 downto 0)<prev_wavetime_S then
+ timeerror3_S <= '1';
+ end if;
+ end if;
+ data_in_count_S <= 3;
+ prev_wavetime_S <= data_in(15 downto 0);
+ prev_wavesuperburst_S <= wavesuperburst_S;
+ else
+ if wave_S='1' then
+ else
+ if data_in(63 downto 40) < time_S(23 downto 0) then
+ timeerror2_S <= '1';
+ end if;
+ time_S <= data_in(63 downto 40);
+ end if;
+ end if;
+ data_in_count_S <= data_in_count_S+1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+testword0(63 downto 0) <= data_in;
+testword0(64) <= data_in_first;
+testword0(65) <= data_in_last;
+testword0(66) <= data_in_write;
+testword0(67) <= wave_S;
+testword0(68) <= data_in_busy_S;
+testword0(69) <= dataerror1_S;
+testword0(70) <= dataerror2_S;
+testword0(71) <= timeerror1_S;
+testword0(72) <= timeerror2_S;
+testword0(73) <= timeerror3_S;
+testword0(74) <= waveerror1_S;
+testword0(75) <= '1' when prev_superburst_S>1 else '0';
+
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 31-01-2012
+-- Module Name: CN_cluster_XY_LUT
+-- Description: Look Up Table for XY position and on-edge indication
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- CN_cluster_XY_LUT
+-- Look Up Table to translate ADC channel number to X and Y position of the crystal.
+-- Contains also bit that indicates if the crystal is on the edge of the region.
+--
+-- generics
+--
+-- inputs
+-- clock : clock
+-- write_enable : write to memory
+-- write_address : address to write to
+-- data_in : data to write into memory
+-- read_address : address to read from
+--
+-- outputs
+-- data_out : data from memory
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+entity CN_cluster_XY_LUT is
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(15 downto 0);
+ data_in : in std_logic_vector(16 downto 0);
+ read_address : in std_logic_vector(15 downto 0);
+ data_out : out std_logic_vector(16 downto 0)
+ );
+end CN_cluster_XY_LUT;
+
+architecture behavioral of CN_cluster_XY_LUT is
+ type mem_type is array (0 to 2**16-1) of std_logic;
+ signal mem_S : mem_type := (others => '1');
+-- type mem_type is array (0 to 2**16-1) of std_logic_vector (16 downto 0);
+-- signal mem_S : mem_type :=
+--('1'&x"0000",'1'&x"0001",'1'&x"0002",'1'&x"0003",'1'&x"0004",'1'&x"0005",'1'&x"0006",'1'&x"0007",'1'&x"0008",'1'&x"0009",'1'&x"000A",'1'&x"000B",'1'&x"000C",'1'&x"000D",'1'&x"000E",'1'&x"000F",
+--'1'&x"0010",'1'&x"0011",'1'&x"0012",'1'&x"0013",'1'&x"0014",'1'&x"0015",'1'&x"0016",'1'&x"0017",'1'&x"0018",'1'&x"0019",'1'&x"001A",'1'&x"001B",'1'&x"001C",'1'&x"001D",'1'&x"001E",'1'&x"001F",
+--'1'&x"0020",'1'&x"0021",'1'&x"0022",'1'&x"0023",'1'&x"0024",'1'&x"0025",'1'&x"0026",'1'&x"0027",'1'&x"0028",'1'&x"0029",'1'&x"002A",'1'&x"002B",'1'&x"002C",'1'&x"002D",'1'&x"002E",'1'&x"002F",
+--'1'&x"0030",'1'&x"0031",'1'&x"0032",'1'&x"0033",'1'&x"0034",'1'&x"0035",'1'&x"0036",'1'&x"0037",'1'&x"0038",'1'&x"0039",'1'&x"003A",'1'&x"003B",'1'&x"003C",'1'&x"003D",'1'&x"003E",'1'&x"003F",
+--'1'&x"0040",'1'&x"0041",'1'&x"0042",'1'&x"0043",'1'&x"0044",'1'&x"0045",'1'&x"0046",'1'&x"0047",'1'&x"0048",'1'&x"0049",'1'&x"004A",'1'&x"004B",'1'&x"004C",'1'&x"004D",'1'&x"004E",'1'&x"004F",
+--'1'&x"0050",'1'&x"0051",'1'&x"0052",'1'&x"0053",'1'&x"0054",'1'&x"0055",'1'&x"0056",'1'&x"0057",'1'&x"0058",'1'&x"0059",'1'&x"005A",'1'&x"005B",'1'&x"005C",'1'&x"005D",'1'&x"005E",'1'&x"005F",
+--'1'&x"0060",'1'&x"0061",'1'&x"0062",'1'&x"0063",'1'&x"0064",'1'&x"0065",'1'&x"0066",'1'&x"0067",'1'&x"0068",'1'&x"0069",'1'&x"006A",'1'&x"006B",'1'&x"006C",'1'&x"006D",'1'&x"006E",'1'&x"006F",
+--'1'&x"0070",'1'&x"0071",'1'&x"0072",'1'&x"0073",'1'&x"0074",'1'&x"0075",'1'&x"0076",'1'&x"0077",'1'&x"0078",'1'&x"0079",'1'&x"007A",'1'&x"007B",'1'&x"007C",'1'&x"007D",'1'&x"007E",'1'&x"007F",
+--'1'&x"0080",'1'&x"0081",'1'&x"0082",'1'&x"0083",'1'&x"0084",'1'&x"0085",'1'&x"0086",'1'&x"0087",'1'&x"0088",'1'&x"0089",'1'&x"008A",'1'&x"008B",'1'&x"008C",'1'&x"008D",'1'&x"008E",'1'&x"008F",
+--'1'&x"0090",'1'&x"0091",'1'&x"0092",'1'&x"0093",'1'&x"0094",'1'&x"0095",'1'&x"0096",'1'&x"0097",'1'&x"0098",'1'&x"0099",'1'&x"009A",'1'&x"009B",'1'&x"009C",'1'&x"009D",'1'&x"009E",'1'&x"009F",
+--'1'&x"00A0",'1'&x"00A1",'1'&x"00A2",'1'&x"00A3",'1'&x"00A4",'1'&x"00A5",'1'&x"00A6",'1'&x"00A7",'1'&x"00A8",'1'&x"00A9",'1'&x"00AA",'1'&x"00AB",'1'&x"00AC",'1'&x"00AD",'1'&x"00AE",'1'&x"00AF",
+--'1'&x"00B0",'1'&x"00B1",'1'&x"00B2",'1'&x"00B3",'1'&x"00B4",'1'&x"00B5",'1'&x"00B6",'1'&x"00B7",'1'&x"00B8",'1'&x"00B9",'1'&x"00BA",'1'&x"00BB",'1'&x"00BC",'1'&x"00BD",'1'&x"00BE",'1'&x"00BF",
+--'1'&x"00C0",'1'&x"00C1",'1'&x"00C2",'1'&x"00C3",'1'&x"00C4",'1'&x"00C5",'1'&x"00C6",'1'&x"00C7",'1'&x"00C8",'1'&x"00C9",'1'&x"00CA",'1'&x"00CB",'1'&x"00CC",'1'&x"00CD",'1'&x"00CE",'1'&x"00CF",
+--'1'&x"00D0",'1'&x"00D1",'1'&x"00D2",'1'&x"00D3",'1'&x"00D4",'1'&x"00D5",'1'&x"00D6",'1'&x"00D7",'1'&x"00D8",'1'&x"00D9",'1'&x"00DA",'1'&x"00DB",'1'&x"00DC",'1'&x"00DD",'1'&x"00DE",'1'&x"00DF",
+--'1'&x"00E0",'1'&x"00E1",'1'&x"00E2",'1'&x"00E3",'1'&x"00E4",'1'&x"00E5",'1'&x"00E6",'1'&x"00E7",'1'&x"00E8",'1'&x"00E9",'1'&x"00EA",'1'&x"00EB",'1'&x"00EC",'1'&x"00ED",'1'&x"00EE",'1'&x"00EF",
+--'1'&x"00F0",'1'&x"00F1",'1'&x"00F2",'1'&x"00F3",'1'&x"00F4",'1'&x"00F5",'1'&x"00F6",'1'&x"00F7",'1'&x"00F8",'1'&x"00F9",'1'&x"00FA",'1'&x"00FB",'1'&x"00FC",'1'&x"00FD",'1'&x"00FE",'1'&x"00FF",
+--'1'&x"0100",'1'&x"0101",'1'&x"0102",'1'&x"0103",'1'&x"0104",'1'&x"0105",'1'&x"0106",'1'&x"0107",'1'&x"0108",'1'&x"0109",'1'&x"010A",'1'&x"010B",'1'&x"010C",'1'&x"010D",'1'&x"010E",'1'&x"010F",
+--'1'&x"0110",'1'&x"0111",'1'&x"0112",'1'&x"0113",'1'&x"0114",'1'&x"0115",'1'&x"0116",'1'&x"0117",'1'&x"0118",'1'&x"0119",'1'&x"011A",'1'&x"011B",'1'&x"011C",'1'&x"011D",'1'&x"011E",'1'&x"011F",
+--'1'&x"0120",'1'&x"0121",'1'&x"0122",'1'&x"0123",'1'&x"0124",'1'&x"0125",'1'&x"0126",'1'&x"0127",'1'&x"0128",'1'&x"0129",'1'&x"012A",'1'&x"012B",'1'&x"012C",'1'&x"012D",'1'&x"012E",'1'&x"012F",
+--'1'&x"0130",'1'&x"0131",'1'&x"0132",'1'&x"0133",'1'&x"0134",'1'&x"0135",'1'&x"0136",'1'&x"0137",'1'&x"0138",'1'&x"0139",'1'&x"013A",'1'&x"013B",'1'&x"013C",'1'&x"013D",'1'&x"013E",'1'&x"013F",
+--'1'&x"0140",'1'&x"0141",'1'&x"0142",'1'&x"0143",'1'&x"0144",'1'&x"0145",'1'&x"0146",'1'&x"0147",'1'&x"0148",'1'&x"0149",'1'&x"014A",'1'&x"014B",'1'&x"014C",'1'&x"014D",'1'&x"014E",'1'&x"014F",
+--'1'&x"0150",'1'&x"0151",'1'&x"0152",'1'&x"0153",'1'&x"0154",'1'&x"0155",'1'&x"0156",'1'&x"0157",'1'&x"0158",'1'&x"0159",'1'&x"015A",'1'&x"015B",'1'&x"015C",'1'&x"015D",'1'&x"015E",'1'&x"015F",
+--'1'&x"0160",'1'&x"0161",'1'&x"0162",'1'&x"0163",'1'&x"0164",'1'&x"0165",'1'&x"0166",'1'&x"0167",'1'&x"0168",'1'&x"0169",'1'&x"016A",'1'&x"016B",'1'&x"016C",'1'&x"016D",'1'&x"016E",'1'&x"016F",
+--'1'&x"0170",'1'&x"0171",'1'&x"0172",'1'&x"0173",'1'&x"0174",'1'&x"0175",'1'&x"0176",'1'&x"0177",'1'&x"0178",'1'&x"0179",'1'&x"017A",'1'&x"017B",'1'&x"017C",'1'&x"017D",'1'&x"017E",'1'&x"017F",
+--'1'&x"0180",'1'&x"0181",'1'&x"0182",'1'&x"0183",'1'&x"0184",'1'&x"0185",'1'&x"0186",'1'&x"0187",'1'&x"0188",'1'&x"0189",'1'&x"018A",'1'&x"018B",'1'&x"018C",'1'&x"018D",'1'&x"018E",'1'&x"018F",
+--'1'&x"0190",'1'&x"0191",'1'&x"0192",'1'&x"0193",'1'&x"0194",'1'&x"0195",'1'&x"0196",'1'&x"0197",'1'&x"0198",'1'&x"0199",'1'&x"019A",'1'&x"019B",'1'&x"019C",'1'&x"019D",'1'&x"019E",'1'&x"019F",
+--'1'&x"01A0",'1'&x"01A1",'1'&x"01A2",'1'&x"01A3",'1'&x"01A4",'1'&x"01A5",'1'&x"01A6",'1'&x"01A7",'1'&x"01A8",'1'&x"01A9",'1'&x"01AA",'1'&x"01AB",'1'&x"01AC",'1'&x"01AD",'1'&x"01AE",'1'&x"01AF",
+--'1'&x"01B0",'1'&x"01B1",'1'&x"01B2",'1'&x"01B3",'1'&x"01B4",'1'&x"01B5",'1'&x"01B6",'1'&x"01B7",'1'&x"01B8",'1'&x"01B9",'1'&x"01BA",'1'&x"01BB",'1'&x"01BC",'1'&x"01BD",'1'&x"01BE",'1'&x"01BF",
+--'1'&x"01C0",'1'&x"01C1",'1'&x"01C2",'1'&x"01C3",'1'&x"01C4",'1'&x"01C5",'1'&x"01C6",'1'&x"01C7",'1'&x"01C8",'1'&x"01C9",'1'&x"01CA",'1'&x"01CB",'1'&x"01CC",'1'&x"01CD",'1'&x"01CE",'1'&x"01CF",
+--'1'&x"01D0",'1'&x"01D1",'1'&x"01D2",'1'&x"01D3",'1'&x"01D4",'1'&x"01D5",'1'&x"01D6",'1'&x"01D7",'1'&x"01D8",'1'&x"01D9",'1'&x"01DA",'1'&x"01DB",'1'&x"01DC",'1'&x"01DD",'1'&x"01DE",'1'&x"01DF",
+--'1'&x"01E0",'1'&x"01E1",'1'&x"01E2",'1'&x"01E3",'1'&x"01E4",'1'&x"01E5",'1'&x"01E6",'1'&x"01E7",'1'&x"01E8",'1'&x"01E9",'1'&x"01EA",'1'&x"01EB",'1'&x"01EC",'1'&x"01ED",'1'&x"01EE",'1'&x"01EF",
+--'1'&x"01F0",'1'&x"01F1",'1'&x"01F2",'1'&x"01F3",'1'&x"01F4",'1'&x"01F5",'1'&x"01F6",'1'&x"01F7",'1'&x"01F8",'1'&x"01F9",'1'&x"01FA",'1'&x"01FB",'1'&x"01FC",'1'&x"01FD",'1'&x"01FE",'1'&x"01FF",
+--'1'&x"0200",'1'&x"0201",'1'&x"0202",'1'&x"0203",'1'&x"0204",'1'&x"0205",'1'&x"0206",'1'&x"0207",'1'&x"0208",'1'&x"0209",'1'&x"020A",'1'&x"020B",'1'&x"020C",'1'&x"020D",'1'&x"020E",'1'&x"020F",
+--'1'&x"0210",'1'&x"0211",'1'&x"0212",'1'&x"0213",'1'&x"0214",'1'&x"0215",'1'&x"0216",'1'&x"0217",'1'&x"0218",'1'&x"0219",'1'&x"021A",'1'&x"021B",'1'&x"021C",'1'&x"021D",'1'&x"021E",'1'&x"021F",
+--'1'&x"0220",'1'&x"0221",'1'&x"0222",'1'&x"0223",'1'&x"0224",'1'&x"0225",'1'&x"0226",'1'&x"0227",'1'&x"0228",'1'&x"0229",'1'&x"022A",'1'&x"022B",'1'&x"022C",'1'&x"022D",'1'&x"022E",'1'&x"022F",
+--'1'&x"0230",'1'&x"0231",'1'&x"0232",'1'&x"0233",'1'&x"0234",'1'&x"0235",'1'&x"0236",'1'&x"0237",'1'&x"0238",'1'&x"0239",'1'&x"023A",'1'&x"023B",'1'&x"023C",'1'&x"023D",'1'&x"023E",'1'&x"023F",
+--'1'&x"0240",'1'&x"0241",'1'&x"0242",'1'&x"0243",'1'&x"0244",'1'&x"0245",'1'&x"0246",'1'&x"0247",'1'&x"0248",'1'&x"0249",'1'&x"024A",'1'&x"024B",'1'&x"024C",'1'&x"024D",'1'&x"024E",'1'&x"024F",
+--'1'&x"0250",'1'&x"0251",'1'&x"0252",'1'&x"0253",'1'&x"0254",'1'&x"0255",'1'&x"0256",'1'&x"0257",'1'&x"0258",'1'&x"0259",'1'&x"025A",'1'&x"025B",'1'&x"025C",'1'&x"025D",'1'&x"025E",'1'&x"025F",
+--'1'&x"0260",'1'&x"0261",'1'&x"0262",'1'&x"0263",'1'&x"0264",'1'&x"0265",'1'&x"0266",'1'&x"0267",'1'&x"0268",'1'&x"0269",'1'&x"026A",'1'&x"026B",'1'&x"026C",'1'&x"026D",'1'&x"026E",'1'&x"026F",
+--'1'&x"0270",'1'&x"0271",'1'&x"0272",'1'&x"0273",'1'&x"0274",'1'&x"0275",'1'&x"0276",'1'&x"0277",'1'&x"0278",'1'&x"0279",'1'&x"027A",'1'&x"027B",'1'&x"027C",'1'&x"027D",'1'&x"027E",'1'&x"027F",
+--'1'&x"0280",'1'&x"0281",'1'&x"0282",'1'&x"0283",'1'&x"0284",'1'&x"0285",'1'&x"0286",'1'&x"0287",'1'&x"0288",'1'&x"0289",'1'&x"028A",'1'&x"028B",'1'&x"028C",'1'&x"028D",'1'&x"028E",'1'&x"028F",
+--'1'&x"0290",'1'&x"0291",'1'&x"0292",'1'&x"0293",'1'&x"0294",'1'&x"0295",'1'&x"0296",'1'&x"0297",'1'&x"0298",'1'&x"0299",'1'&x"029A",'1'&x"029B",'1'&x"029C",'1'&x"029D",'1'&x"029E",'1'&x"029F",
+--'1'&x"02A0",'1'&x"02A1",'1'&x"02A2",'1'&x"02A3",'1'&x"02A4",'1'&x"02A5",'1'&x"02A6",'1'&x"02A7",'1'&x"02A8",'1'&x"02A9",'1'&x"02AA",'1'&x"02AB",'1'&x"02AC",'1'&x"02AD",'1'&x"02AE",'1'&x"02AF",
+--'1'&x"02B0",'1'&x"02B1",'1'&x"02B2",'1'&x"02B3",'1'&x"02B4",'1'&x"02B5",'1'&x"02B6",'1'&x"02B7",'1'&x"02B8",'1'&x"02B9",'1'&x"02BA",'1'&x"02BB",'1'&x"02BC",'1'&x"02BD",'1'&x"02BE",'1'&x"02BF",
+--'1'&x"02C0",'1'&x"02C1",'1'&x"02C2",'1'&x"02C3",'1'&x"02C4",'1'&x"02C5",'1'&x"02C6",'1'&x"02C7",'1'&x"02C8",'1'&x"02C9",'1'&x"02CA",'1'&x"02CB",'1'&x"02CC",'1'&x"02CD",'1'&x"02CE",'1'&x"02CF",
+--'1'&x"02D0",'1'&x"02D1",'1'&x"02D2",'1'&x"02D3",'1'&x"02D4",'1'&x"02D5",'1'&x"02D6",'1'&x"02D7",'1'&x"02D8",'1'&x"02D9",'1'&x"02DA",'1'&x"02DB",'1'&x"02DC",'1'&x"02DD",'1'&x"02DE",'1'&x"02DF",
+--'1'&x"02E0",'1'&x"02E1",'1'&x"02E2",'1'&x"02E3",'1'&x"02E4",'1'&x"02E5",'1'&x"02E6",'1'&x"02E7",'1'&x"02E8",'1'&x"02E9",'1'&x"02EA",'1'&x"02EB",'1'&x"02EC",'1'&x"02ED",'1'&x"02EE",'1'&x"02EF",
+--'1'&x"02F0",'1'&x"02F1",'1'&x"02F2",'1'&x"02F3",'1'&x"02F4",'1'&x"02F5",'1'&x"02F6",'1'&x"02F7",'1'&x"02F8",'1'&x"02F9",'1'&x"02FA",'1'&x"02FB",'1'&x"02FC",'1'&x"02FD",'1'&x"02FE",'1'&x"02FF",
+--'1'&x"0300",'1'&x"0301",'1'&x"0302",'1'&x"0303",'1'&x"0304",'1'&x"0305",'1'&x"0306",'1'&x"0307",'1'&x"0308",'1'&x"0309",'1'&x"030A",'1'&x"030B",'1'&x"030C",'1'&x"030D",'1'&x"030E",'1'&x"030F",
+--'1'&x"0310",'1'&x"0311",'1'&x"0312",'1'&x"0313",'1'&x"0314",'1'&x"0315",'1'&x"0316",'1'&x"0317",'1'&x"0318",'1'&x"0319",'1'&x"031A",'1'&x"031B",'1'&x"031C",'1'&x"031D",'1'&x"031E",'1'&x"031F",
+--'1'&x"0320",'1'&x"0321",'1'&x"0322",'1'&x"0323",'1'&x"0324",'1'&x"0325",'1'&x"0326",'1'&x"0327",'1'&x"0328",'1'&x"0329",'1'&x"032A",'1'&x"032B",'1'&x"032C",'1'&x"032D",'1'&x"032E",'1'&x"032F",
+--'1'&x"0330",'1'&x"0331",'1'&x"0332",'1'&x"0333",'1'&x"0334",'1'&x"0335",'1'&x"0336",'1'&x"0337",'1'&x"0338",'1'&x"0339",'1'&x"033A",'1'&x"033B",'1'&x"033C",'1'&x"033D",'1'&x"033E",'1'&x"033F",
+--'1'&x"0340",'1'&x"0341",'1'&x"0342",'1'&x"0343",'1'&x"0344",'1'&x"0345",'1'&x"0346",'1'&x"0347",'1'&x"0348",'1'&x"0349",'1'&x"034A",'1'&x"034B",'1'&x"034C",'1'&x"034D",'1'&x"034E",'1'&x"034F",
+--'1'&x"0350",'1'&x"0351",'1'&x"0352",'1'&x"0353",'1'&x"0354",'1'&x"0355",'1'&x"0356",'1'&x"0357",'1'&x"0358",'1'&x"0359",'1'&x"035A",'1'&x"035B",'1'&x"035C",'1'&x"035D",'1'&x"035E",'1'&x"035F",
+--'1'&x"0360",'1'&x"0361",'1'&x"0362",'1'&x"0363",'1'&x"0364",'1'&x"0365",'1'&x"0366",'1'&x"0367",'1'&x"0368",'1'&x"0369",'1'&x"036A",'1'&x"036B",'1'&x"036C",'1'&x"036D",'1'&x"036E",'1'&x"036F",
+--'1'&x"0370",'1'&x"0371",'1'&x"0372",'1'&x"0373",'1'&x"0374",'1'&x"0375",'1'&x"0376",'1'&x"0377",'1'&x"0378",'1'&x"0379",'1'&x"037A",'1'&x"037B",'1'&x"037C",'1'&x"037D",'1'&x"037E",'1'&x"037F",
+--'1'&x"0380",'1'&x"0381",'1'&x"0382",'1'&x"0383",'1'&x"0384",'1'&x"0385",'1'&x"0386",'1'&x"0387",'1'&x"0388",'1'&x"0389",'1'&x"038A",'1'&x"038B",'1'&x"038C",'1'&x"038D",'1'&x"038E",'1'&x"038F",
+--'1'&x"0390",'1'&x"0391",'1'&x"0392",'1'&x"0393",'1'&x"0394",'1'&x"0395",'1'&x"0396",'1'&x"0397",'1'&x"0398",'1'&x"0399",'1'&x"039A",'1'&x"039B",'1'&x"039C",'1'&x"039D",'1'&x"039E",'1'&x"039F",
+--'1'&x"03A0",'1'&x"03A1",'1'&x"03A2",'1'&x"03A3",'1'&x"03A4",'1'&x"03A5",'1'&x"03A6",'1'&x"03A7",'1'&x"03A8",'1'&x"03A9",'1'&x"03AA",'1'&x"03AB",'1'&x"03AC",'1'&x"03AD",'1'&x"03AE",'1'&x"03AF",
+--'1'&x"03B0",'1'&x"03B1",'1'&x"03B2",'1'&x"03B3",'1'&x"03B4",'1'&x"03B5",'1'&x"03B6",'1'&x"03B7",'1'&x"03B8",'1'&x"03B9",'1'&x"03BA",'1'&x"03BB",'1'&x"03BC",'1'&x"03BD",'1'&x"03BE",'1'&x"03BF",
+--'1'&x"03C0",'1'&x"03C1",'1'&x"03C2",'1'&x"03C3",'1'&x"03C4",'1'&x"03C5",'1'&x"03C6",'1'&x"03C7",'1'&x"03C8",'1'&x"03C9",'1'&x"03CA",'1'&x"03CB",'1'&x"03CC",'1'&x"03CD",'1'&x"03CE",'1'&x"03CF",
+--'1'&x"03D0",'1'&x"03D1",'1'&x"03D2",'1'&x"03D3",'1'&x"03D4",'1'&x"03D5",'1'&x"03D6",'1'&x"03D7",'1'&x"03D8",'1'&x"03D9",'1'&x"03DA",'1'&x"03DB",'1'&x"03DC",'1'&x"03DD",'1'&x"03DE",'1'&x"03DF",
+--'1'&x"03E0",'1'&x"03E1",'1'&x"03E2",'1'&x"03E3",'1'&x"03E4",'1'&x"03E5",'1'&x"03E6",'1'&x"03E7",'1'&x"03E8",'1'&x"03E9",'1'&x"03EA",'1'&x"03EB",'1'&x"03EC",'1'&x"03ED",'1'&x"03EE",'1'&x"03EF",
+--'1'&x"03F0",'1'&x"03F1",'1'&x"03F2",'1'&x"03F3",'1'&x"03F4",'1'&x"03F5",'1'&x"03F6",'1'&x"03F7",'1'&x"03F8",'1'&x"03F9",'1'&x"03FA",'1'&x"03FB",'1'&x"03FC",'1'&x"03FD",'1'&x"03FE",'1'&x"03FF",
+--'1'&x"0400",'1'&x"0401",'1'&x"0402",'1'&x"0403",'1'&x"0404",'1'&x"0405",'1'&x"0406",'1'&x"0407",'1'&x"0408",'1'&x"0409",'1'&x"040A",'1'&x"040B",'1'&x"040C",'1'&x"040D",'1'&x"040E",'1'&x"040F",
+--'1'&x"0410",'1'&x"0411",'1'&x"0412",'1'&x"0413",'1'&x"0414",'1'&x"0415",'1'&x"0416",'1'&x"0417",'1'&x"0418",'1'&x"0419",'1'&x"041A",'1'&x"041B",'1'&x"041C",'1'&x"041D",'1'&x"041E",'1'&x"041F",
+--'1'&x"0420",'1'&x"0421",'1'&x"0422",'1'&x"0423",'1'&x"0424",'1'&x"0425",'1'&x"0426",'1'&x"0427",'1'&x"0428",'1'&x"0429",'1'&x"042A",'1'&x"042B",'1'&x"042C",'1'&x"042D",'1'&x"042E",'1'&x"042F",
+--'1'&x"0430",'1'&x"0431",'1'&x"0432",'1'&x"0433",'1'&x"0434",'1'&x"0435",'1'&x"0436",'1'&x"0437",'1'&x"0438",'1'&x"0439",'1'&x"043A",'1'&x"043B",'1'&x"043C",'1'&x"043D",'1'&x"043E",'1'&x"043F",
+--'1'&x"0440",'1'&x"0441",'1'&x"0442",'1'&x"0443",'1'&x"0444",'1'&x"0445",'1'&x"0446",'1'&x"0447",'1'&x"0448",'1'&x"0449",'1'&x"044A",'1'&x"044B",'1'&x"044C",'1'&x"044D",'1'&x"044E",'1'&x"044F",
+--'1'&x"0450",'1'&x"0451",'1'&x"0452",'1'&x"0453",'1'&x"0454",'1'&x"0455",'1'&x"0456",'1'&x"0457",'1'&x"0458",'1'&x"0459",'1'&x"045A",'1'&x"045B",'1'&x"045C",'1'&x"045D",'1'&x"045E",'1'&x"045F",
+--'1'&x"0460",'1'&x"0461",'1'&x"0462",'1'&x"0463",'1'&x"0464",'1'&x"0465",'1'&x"0466",'1'&x"0467",'1'&x"0468",'1'&x"0469",'1'&x"046A",'1'&x"046B",'1'&x"046C",'1'&x"046D",'1'&x"046E",'1'&x"046F",
+--'1'&x"0470",'1'&x"0471",'1'&x"0472",'1'&x"0473",'1'&x"0474",'1'&x"0475",'1'&x"0476",'1'&x"0477",'1'&x"0478",'1'&x"0479",'1'&x"047A",'1'&x"047B",'1'&x"047C",'1'&x"047D",'1'&x"047E",'1'&x"047F",
+--'1'&x"0480",'1'&x"0481",'1'&x"0482",'1'&x"0483",'1'&x"0484",'1'&x"0485",'1'&x"0486",'1'&x"0487",'1'&x"0488",'1'&x"0489",'1'&x"048A",'1'&x"048B",'1'&x"048C",'1'&x"048D",'1'&x"048E",'1'&x"048F",
+--'1'&x"0490",'1'&x"0491",'1'&x"0492",'1'&x"0493",'1'&x"0494",'1'&x"0495",'1'&x"0496",'1'&x"0497",'1'&x"0498",'1'&x"0499",'1'&x"049A",'1'&x"049B",'1'&x"049C",'1'&x"049D",'1'&x"049E",'1'&x"049F",
+--'1'&x"04A0",'1'&x"04A1",'1'&x"04A2",'1'&x"04A3",'1'&x"04A4",'1'&x"04A5",'1'&x"04A6",'1'&x"04A7",'1'&x"04A8",'1'&x"04A9",'1'&x"04AA",'1'&x"04AB",'1'&x"04AC",'1'&x"04AD",'1'&x"04AE",'1'&x"04AF",
+--'1'&x"04B0",'1'&x"04B1",'1'&x"04B2",'1'&x"04B3",'1'&x"04B4",'1'&x"04B5",'1'&x"04B6",'1'&x"04B7",'1'&x"04B8",'1'&x"04B9",'1'&x"04BA",'1'&x"04BB",'1'&x"04BC",'1'&x"04BD",'1'&x"04BE",'1'&x"04BF",
+--'1'&x"04C0",'1'&x"04C1",'1'&x"04C2",'1'&x"04C3",'1'&x"04C4",'1'&x"04C5",'1'&x"04C6",'1'&x"04C7",'1'&x"04C8",'1'&x"04C9",'1'&x"04CA",'1'&x"04CB",'1'&x"04CC",'1'&x"04CD",'1'&x"04CE",'1'&x"04CF",
+--'1'&x"04D0",'1'&x"04D1",'1'&x"04D2",'1'&x"04D3",'1'&x"04D4",'1'&x"04D5",'1'&x"04D6",'1'&x"04D7",'1'&x"04D8",'1'&x"04D9",'1'&x"04DA",'1'&x"04DB",'1'&x"04DC",'1'&x"04DD",'1'&x"04DE",'1'&x"04DF",
+--'1'&x"04E0",'1'&x"04E1",'1'&x"04E2",'1'&x"04E3",'1'&x"04E4",'1'&x"04E5",'1'&x"04E6",'1'&x"04E7",'1'&x"04E8",'1'&x"04E9",'1'&x"04EA",'1'&x"04EB",'1'&x"04EC",'1'&x"04ED",'1'&x"04EE",'1'&x"04EF",
+--'1'&x"04F0",'1'&x"04F1",'1'&x"04F2",'1'&x"04F3",'1'&x"04F4",'1'&x"04F5",'1'&x"04F6",'1'&x"04F7",'1'&x"04F8",'1'&x"04F9",'1'&x"04FA",'1'&x"04FB",'1'&x"04FC",'1'&x"04FD",'1'&x"04FE",'1'&x"04FF",
+--'1'&x"0500",'1'&x"0501",'1'&x"0502",'1'&x"0503",'1'&x"0504",'1'&x"0505",'1'&x"0506",'1'&x"0507",'1'&x"0508",'1'&x"0509",'1'&x"050A",'1'&x"050B",'1'&x"050C",'1'&x"050D",'1'&x"050E",'1'&x"050F",
+--'1'&x"0510",'1'&x"0511",'1'&x"0512",'1'&x"0513",'1'&x"0514",'1'&x"0515",'1'&x"0516",'1'&x"0517",'1'&x"0518",'1'&x"0519",'1'&x"051A",'1'&x"051B",'1'&x"051C",'1'&x"051D",'1'&x"051E",'1'&x"051F",
+--'1'&x"0520",'1'&x"0521",'1'&x"0522",'1'&x"0523",'1'&x"0524",'1'&x"0525",'1'&x"0526",'1'&x"0527",'1'&x"0528",'1'&x"0529",'1'&x"052A",'1'&x"052B",'1'&x"052C",'1'&x"052D",'1'&x"052E",'1'&x"052F",
+--'1'&x"0530",'1'&x"0531",'1'&x"0532",'1'&x"0533",'1'&x"0534",'1'&x"0535",'1'&x"0536",'1'&x"0537",'1'&x"0538",'1'&x"0539",'1'&x"053A",'1'&x"053B",'1'&x"053C",'1'&x"053D",'1'&x"053E",'1'&x"053F",
+--'1'&x"0540",'1'&x"0541",'1'&x"0542",'1'&x"0543",'1'&x"0544",'1'&x"0545",'1'&x"0546",'1'&x"0547",'1'&x"0548",'1'&x"0549",'1'&x"054A",'1'&x"054B",'1'&x"054C",'1'&x"054D",'1'&x"054E",'1'&x"054F",
+--'1'&x"0550",'1'&x"0551",'1'&x"0552",'1'&x"0553",'1'&x"0554",'1'&x"0555",'1'&x"0556",'1'&x"0557",'1'&x"0558",'1'&x"0559",'1'&x"055A",'1'&x"055B",'1'&x"055C",'1'&x"055D",'1'&x"055E",'1'&x"055F",
+--'1'&x"0560",'1'&x"0561",'1'&x"0562",'1'&x"0563",'1'&x"0564",'1'&x"0565",'1'&x"0566",'1'&x"0567",'1'&x"0568",'1'&x"0569",'1'&x"056A",'1'&x"056B",'1'&x"056C",'1'&x"056D",'1'&x"056E",'1'&x"056F",
+--'1'&x"0570",'1'&x"0571",'1'&x"0572",'1'&x"0573",'1'&x"0574",'1'&x"0575",'1'&x"0576",'1'&x"0577",'1'&x"0578",'1'&x"0579",'1'&x"057A",'1'&x"057B",'1'&x"057C",'1'&x"057D",'1'&x"057E",'1'&x"057F",
+--'1'&x"0580",'1'&x"0581",'1'&x"0582",'1'&x"0583",'1'&x"0584",'1'&x"0585",'1'&x"0586",'1'&x"0587",'1'&x"0588",'1'&x"0589",'1'&x"058A",'1'&x"058B",'1'&x"058C",'1'&x"058D",'1'&x"058E",'1'&x"058F",
+--'1'&x"0590",'1'&x"0591",'1'&x"0592",'1'&x"0593",'1'&x"0594",'1'&x"0595",'1'&x"0596",'1'&x"0597",'1'&x"0598",'1'&x"0599",'1'&x"059A",'1'&x"059B",'1'&x"059C",'1'&x"059D",'1'&x"059E",'1'&x"059F",
+--'1'&x"05A0",'1'&x"05A1",'1'&x"05A2",'1'&x"05A3",'1'&x"05A4",'1'&x"05A5",'1'&x"05A6",'1'&x"05A7",'1'&x"05A8",'1'&x"05A9",'1'&x"05AA",'1'&x"05AB",'1'&x"05AC",'1'&x"05AD",'1'&x"05AE",'1'&x"05AF",
+--'1'&x"05B0",'1'&x"05B1",'1'&x"05B2",'1'&x"05B3",'1'&x"05B4",'1'&x"05B5",'1'&x"05B6",'1'&x"05B7",'1'&x"05B8",'1'&x"05B9",'1'&x"05BA",'1'&x"05BB",'1'&x"05BC",'1'&x"05BD",'1'&x"05BE",'1'&x"05BF",
+--'1'&x"05C0",'1'&x"05C1",'1'&x"05C2",'1'&x"05C3",'1'&x"05C4",'1'&x"05C5",'1'&x"05C6",'1'&x"05C7",'1'&x"05C8",'1'&x"05C9",'1'&x"05CA",'1'&x"05CB",'1'&x"05CC",'1'&x"05CD",'1'&x"05CE",'1'&x"05CF",
+--'1'&x"05D0",'1'&x"05D1",'1'&x"05D2",'1'&x"05D3",'1'&x"05D4",'1'&x"05D5",'1'&x"05D6",'1'&x"05D7",'1'&x"05D8",'1'&x"05D9",'1'&x"05DA",'1'&x"05DB",'1'&x"05DC",'1'&x"05DD",'1'&x"05DE",'1'&x"05DF",
+--'1'&x"05E0",'1'&x"05E1",'1'&x"05E2",'1'&x"05E3",'1'&x"05E4",'1'&x"05E5",'1'&x"05E6",'1'&x"05E7",'1'&x"05E8",'1'&x"05E9",'1'&x"05EA",'1'&x"05EB",'1'&x"05EC",'1'&x"05ED",'1'&x"05EE",'1'&x"05EF",
+--'1'&x"05F0",'1'&x"05F1",'1'&x"05F2",'1'&x"05F3",'1'&x"05F4",'1'&x"05F5",'1'&x"05F6",'1'&x"05F7",'1'&x"05F8",'1'&x"05F9",'1'&x"05FA",'1'&x"05FB",'1'&x"05FC",'1'&x"05FD",'1'&x"05FE",'1'&x"05FF",
+--'1'&x"0600",'1'&x"0601",'1'&x"0602",'1'&x"0603",'1'&x"0604",'1'&x"0605",'1'&x"0606",'1'&x"0607",'1'&x"0608",'1'&x"0609",'1'&x"060A",'1'&x"060B",'1'&x"060C",'1'&x"060D",'1'&x"060E",'1'&x"060F",
+--'1'&x"0610",'1'&x"0611",'1'&x"0612",'1'&x"0613",'1'&x"0614",'1'&x"0615",'1'&x"0616",'1'&x"0617",'1'&x"0618",'1'&x"0619",'1'&x"061A",'1'&x"061B",'1'&x"061C",'1'&x"061D",'1'&x"061E",'1'&x"061F",
+--'1'&x"0620",'1'&x"0621",'1'&x"0622",'1'&x"0623",'1'&x"0624",'1'&x"0625",'1'&x"0626",'1'&x"0627",'1'&x"0628",'1'&x"0629",'1'&x"062A",'1'&x"062B",'1'&x"062C",'1'&x"062D",'1'&x"062E",'1'&x"062F",
+--'1'&x"0630",'1'&x"0631",'1'&x"0632",'1'&x"0633",'1'&x"0634",'1'&x"0635",'1'&x"0636",'1'&x"0637",'1'&x"0638",'1'&x"0639",'1'&x"063A",'1'&x"063B",'1'&x"063C",'1'&x"063D",'1'&x"063E",'1'&x"063F",
+--'1'&x"0640",'1'&x"0641",'1'&x"0642",'1'&x"0643",'1'&x"0644",'1'&x"0645",'1'&x"0646",'1'&x"0647",'1'&x"0648",'1'&x"0649",'1'&x"064A",'1'&x"064B",'1'&x"064C",'1'&x"064D",'1'&x"064E",'1'&x"064F",
+--'1'&x"0650",'1'&x"0651",'1'&x"0652",'1'&x"0653",'1'&x"0654",'1'&x"0655",'1'&x"0656",'1'&x"0657",'1'&x"0658",'1'&x"0659",'1'&x"065A",'1'&x"065B",'1'&x"065C",'1'&x"065D",'1'&x"065E",'1'&x"065F",
+--'1'&x"0660",'1'&x"0661",'1'&x"0662",'1'&x"0663",'1'&x"0664",'1'&x"0665",'1'&x"0666",'1'&x"0667",'1'&x"0668",'1'&x"0669",'1'&x"066A",'1'&x"066B",'1'&x"066C",'1'&x"066D",'1'&x"066E",'1'&x"066F",
+--'1'&x"0670",'1'&x"0671",'1'&x"0672",'1'&x"0673",'1'&x"0674",'1'&x"0675",'1'&x"0676",'1'&x"0677",'1'&x"0678",'1'&x"0679",'1'&x"067A",'1'&x"067B",'1'&x"067C",'1'&x"067D",'1'&x"067E",'1'&x"067F",
+--'1'&x"0680",'1'&x"0681",'1'&x"0682",'1'&x"0683",'1'&x"0684",'1'&x"0685",'1'&x"0686",'1'&x"0687",'1'&x"0688",'1'&x"0689",'1'&x"068A",'1'&x"068B",'1'&x"068C",'1'&x"068D",'1'&x"068E",'1'&x"068F",
+--'1'&x"0690",'1'&x"0691",'1'&x"0692",'1'&x"0693",'1'&x"0694",'1'&x"0695",'1'&x"0696",'1'&x"0697",'1'&x"0698",'1'&x"0699",'1'&x"069A",'1'&x"069B",'1'&x"069C",'1'&x"069D",'1'&x"069E",'1'&x"069F",
+--'1'&x"06A0",'1'&x"06A1",'1'&x"06A2",'1'&x"06A3",'1'&x"06A4",'1'&x"06A5",'1'&x"06A6",'1'&x"06A7",'1'&x"06A8",'1'&x"06A9",'1'&x"06AA",'1'&x"06AB",'1'&x"06AC",'1'&x"06AD",'1'&x"06AE",'1'&x"06AF",
+--'1'&x"06B0",'1'&x"06B1",'1'&x"06B2",'1'&x"06B3",'1'&x"06B4",'1'&x"06B5",'1'&x"06B6",'1'&x"06B7",'1'&x"06B8",'1'&x"06B9",'1'&x"06BA",'1'&x"06BB",'1'&x"06BC",'1'&x"06BD",'1'&x"06BE",'1'&x"06BF",
+--'1'&x"06C0",'1'&x"06C1",'1'&x"06C2",'1'&x"06C3",'1'&x"06C4",'1'&x"06C5",'1'&x"06C6",'1'&x"06C7",'1'&x"06C8",'1'&x"06C9",'1'&x"06CA",'1'&x"06CB",'1'&x"06CC",'1'&x"06CD",'1'&x"06CE",'1'&x"06CF",
+--'1'&x"06D0",'1'&x"06D1",'1'&x"06D2",'1'&x"06D3",'1'&x"06D4",'1'&x"06D5",'1'&x"06D6",'1'&x"06D7",'1'&x"06D8",'1'&x"06D9",'1'&x"06DA",'1'&x"06DB",'1'&x"06DC",'1'&x"06DD",'1'&x"06DE",'1'&x"06DF",
+--'1'&x"06E0",'1'&x"06E1",'1'&x"06E2",'1'&x"06E3",'1'&x"06E4",'1'&x"06E5",'1'&x"06E6",'1'&x"06E7",'1'&x"06E8",'1'&x"06E9",'1'&x"06EA",'1'&x"06EB",'1'&x"06EC",'1'&x"06ED",'1'&x"06EE",'1'&x"06EF",
+--'1'&x"06F0",'1'&x"06F1",'1'&x"06F2",'1'&x"06F3",'1'&x"06F4",'1'&x"06F5",'1'&x"06F6",'1'&x"06F7",'1'&x"06F8",'1'&x"06F9",'1'&x"06FA",'1'&x"06FB",'1'&x"06FC",'1'&x"06FD",'1'&x"06FE",'1'&x"06FF",
+--'1'&x"0700",'1'&x"0701",'1'&x"0702",'1'&x"0703",'1'&x"0704",'1'&x"0705",'1'&x"0706",'1'&x"0707",'1'&x"0708",'1'&x"0709",'1'&x"070A",'1'&x"070B",'1'&x"070C",'1'&x"070D",'1'&x"070E",'1'&x"070F",
+--'1'&x"0710",'1'&x"0711",'1'&x"0712",'1'&x"0713",'1'&x"0714",'1'&x"0715",'1'&x"0716",'1'&x"0717",'1'&x"0718",'1'&x"0719",'1'&x"071A",'1'&x"071B",'1'&x"071C",'1'&x"071D",'1'&x"071E",'1'&x"071F",
+--'1'&x"0720",'1'&x"0721",'1'&x"0722",'1'&x"0723",'1'&x"0724",'1'&x"0725",'1'&x"0726",'1'&x"0727",'1'&x"0728",'1'&x"0729",'1'&x"072A",'1'&x"072B",'1'&x"072C",'1'&x"072D",'1'&x"072E",'1'&x"072F",
+--'1'&x"0730",'1'&x"0731",'1'&x"0732",'1'&x"0733",'1'&x"0734",'1'&x"0735",'1'&x"0736",'1'&x"0737",'1'&x"0738",'1'&x"0739",'1'&x"073A",'1'&x"073B",'1'&x"073C",'1'&x"073D",'1'&x"073E",'1'&x"073F",
+--'1'&x"0740",'1'&x"0741",'1'&x"0742",'1'&x"0743",'1'&x"0744",'1'&x"0745",'1'&x"0746",'1'&x"0747",'1'&x"0748",'1'&x"0749",'1'&x"074A",'1'&x"074B",'1'&x"074C",'1'&x"074D",'1'&x"074E",'1'&x"074F",
+--'1'&x"0750",'1'&x"0751",'1'&x"0752",'1'&x"0753",'1'&x"0754",'1'&x"0755",'1'&x"0756",'1'&x"0757",'1'&x"0758",'1'&x"0759",'1'&x"075A",'1'&x"075B",'1'&x"075C",'1'&x"075D",'1'&x"075E",'1'&x"075F",
+--'1'&x"0760",'1'&x"0761",'1'&x"0762",'1'&x"0763",'1'&x"0764",'1'&x"0765",'1'&x"0766",'1'&x"0767",'1'&x"0768",'1'&x"0769",'1'&x"076A",'1'&x"076B",'1'&x"076C",'1'&x"076D",'1'&x"076E",'1'&x"076F",
+--'1'&x"0770",'1'&x"0771",'1'&x"0772",'1'&x"0773",'1'&x"0774",'1'&x"0775",'1'&x"0776",'1'&x"0777",'1'&x"0778",'1'&x"0779",'1'&x"077A",'1'&x"077B",'1'&x"077C",'1'&x"077D",'1'&x"077E",'1'&x"077F",
+--'1'&x"0780",'1'&x"0781",'1'&x"0782",'1'&x"0783",'1'&x"0784",'1'&x"0785",'1'&x"0786",'1'&x"0787",'1'&x"0788",'1'&x"0789",'1'&x"078A",'1'&x"078B",'1'&x"078C",'1'&x"078D",'1'&x"078E",'1'&x"078F",
+--'1'&x"0790",'1'&x"0791",'1'&x"0792",'1'&x"0793",'1'&x"0794",'1'&x"0795",'1'&x"0796",'1'&x"0797",'1'&x"0798",'1'&x"0799",'1'&x"079A",'1'&x"079B",'1'&x"079C",'1'&x"079D",'1'&x"079E",'1'&x"079F",
+--'1'&x"07A0",'1'&x"07A1",'1'&x"07A2",'1'&x"07A3",'1'&x"07A4",'1'&x"07A5",'1'&x"07A6",'1'&x"07A7",'1'&x"07A8",'1'&x"07A9",'1'&x"07AA",'1'&x"07AB",'1'&x"07AC",'1'&x"07AD",'1'&x"07AE",'1'&x"07AF",
+--'1'&x"07B0",'1'&x"07B1",'1'&x"07B2",'1'&x"07B3",'1'&x"07B4",'1'&x"07B5",'1'&x"07B6",'1'&x"07B7",'1'&x"07B8",'1'&x"07B9",'1'&x"07BA",'1'&x"07BB",'1'&x"07BC",'1'&x"07BD",'1'&x"07BE",'1'&x"07BF",
+--'1'&x"07C0",'1'&x"07C1",'1'&x"07C2",'1'&x"07C3",'1'&x"07C4",'1'&x"07C5",'1'&x"07C6",'1'&x"07C7",'1'&x"07C8",'1'&x"07C9",'1'&x"07CA",'1'&x"07CB",'1'&x"07CC",'1'&x"07CD",'1'&x"07CE",'1'&x"07CF",
+--'1'&x"07D0",'1'&x"07D1",'1'&x"07D2",'1'&x"07D3",'1'&x"07D4",'1'&x"07D5",'1'&x"07D6",'1'&x"07D7",'1'&x"07D8",'1'&x"07D9",'1'&x"07DA",'1'&x"07DB",'1'&x"07DC",'1'&x"07DD",'1'&x"07DE",'1'&x"07DF",
+--'1'&x"07E0",'1'&x"07E1",'1'&x"07E2",'1'&x"07E3",'1'&x"07E4",'1'&x"07E5",'1'&x"07E6",'1'&x"07E7",'1'&x"07E8",'1'&x"07E9",'1'&x"07EA",'1'&x"07EB",'1'&x"07EC",'1'&x"07ED",'1'&x"07EE",'1'&x"07EF",
+--'1'&x"07F0",'1'&x"07F1",'1'&x"07F2",'1'&x"07F3",'1'&x"07F4",'1'&x"07F5",'1'&x"07F6",'1'&x"07F7",'1'&x"07F8",'1'&x"07F9",'1'&x"07FA",'1'&x"07FB",'1'&x"07FC",'1'&x"07FD",'1'&x"07FE",'1'&x"07FF",
+--'1'&x"0800",'1'&x"0801",'1'&x"0802",'1'&x"0803",'1'&x"0804",'1'&x"0805",'1'&x"0806",'1'&x"0807",'1'&x"0808",'1'&x"0809",'1'&x"080A",'1'&x"080B",'1'&x"080C",'1'&x"080D",'1'&x"080E",'1'&x"080F",
+--'1'&x"0810",'1'&x"0811",'1'&x"0812",'1'&x"0813",'1'&x"0814",'1'&x"0815",'1'&x"0816",'1'&x"0817",'1'&x"0818",'1'&x"0819",'1'&x"081A",'1'&x"081B",'1'&x"081C",'1'&x"081D",'1'&x"081E",'1'&x"081F",
+--'1'&x"0820",'1'&x"0821",'1'&x"0822",'1'&x"0823",'1'&x"0824",'1'&x"0825",'1'&x"0826",'1'&x"0827",'1'&x"0828",'1'&x"0829",'1'&x"082A",'1'&x"082B",'1'&x"082C",'1'&x"082D",'1'&x"082E",'1'&x"082F",
+--'1'&x"0830",'1'&x"0831",'1'&x"0832",'1'&x"0833",'1'&x"0834",'1'&x"0835",'1'&x"0836",'1'&x"0837",'1'&x"0838",'1'&x"0839",'1'&x"083A",'1'&x"083B",'1'&x"083C",'1'&x"083D",'1'&x"083E",'1'&x"083F",
+--'1'&x"0840",'1'&x"0841",'1'&x"0842",'1'&x"0843",'1'&x"0844",'1'&x"0845",'1'&x"0846",'1'&x"0847",'1'&x"0848",'1'&x"0849",'1'&x"084A",'1'&x"084B",'1'&x"084C",'1'&x"084D",'1'&x"084E",'1'&x"084F",
+--'1'&x"0850",'1'&x"0851",'1'&x"0852",'1'&x"0853",'1'&x"0854",'1'&x"0855",'1'&x"0856",'1'&x"0857",'1'&x"0858",'1'&x"0859",'1'&x"085A",'1'&x"085B",'1'&x"085C",'1'&x"085D",'1'&x"085E",'1'&x"085F",
+--'1'&x"0860",'1'&x"0861",'1'&x"0862",'1'&x"0863",'1'&x"0864",'1'&x"0865",'1'&x"0866",'1'&x"0867",'1'&x"0868",'1'&x"0869",'1'&x"086A",'1'&x"086B",'1'&x"086C",'1'&x"086D",'1'&x"086E",'1'&x"086F",
+--'1'&x"0870",'1'&x"0871",'1'&x"0872",'1'&x"0873",'1'&x"0874",'1'&x"0875",'1'&x"0876",'1'&x"0877",'1'&x"0878",'1'&x"0879",'1'&x"087A",'1'&x"087B",'1'&x"087C",'1'&x"087D",'1'&x"087E",'1'&x"087F",
+--'1'&x"0880",'1'&x"0881",'1'&x"0882",'1'&x"0883",'1'&x"0884",'1'&x"0885",'1'&x"0886",'1'&x"0887",'1'&x"0888",'1'&x"0889",'1'&x"088A",'1'&x"088B",'1'&x"088C",'1'&x"088D",'1'&x"088E",'1'&x"088F",
+--'1'&x"0890",'1'&x"0891",'1'&x"0892",'1'&x"0893",'1'&x"0894",'1'&x"0895",'1'&x"0896",'1'&x"0897",'1'&x"0898",'1'&x"0899",'1'&x"089A",'1'&x"089B",'1'&x"089C",'1'&x"089D",'1'&x"089E",'1'&x"089F",
+--'1'&x"08A0",'1'&x"08A1",'1'&x"08A2",'1'&x"08A3",'1'&x"08A4",'1'&x"08A5",'1'&x"08A6",'1'&x"08A7",'1'&x"08A8",'1'&x"08A9",'1'&x"08AA",'1'&x"08AB",'1'&x"08AC",'1'&x"08AD",'1'&x"08AE",'1'&x"08AF",
+--'1'&x"08B0",'1'&x"08B1",'1'&x"08B2",'1'&x"08B3",'1'&x"08B4",'1'&x"08B5",'1'&x"08B6",'1'&x"08B7",'1'&x"08B8",'1'&x"08B9",'1'&x"08BA",'1'&x"08BB",'1'&x"08BC",'1'&x"08BD",'1'&x"08BE",'1'&x"08BF",
+--'1'&x"08C0",'1'&x"08C1",'1'&x"08C2",'1'&x"08C3",'1'&x"08C4",'1'&x"08C5",'1'&x"08C6",'1'&x"08C7",'1'&x"08C8",'1'&x"08C9",'1'&x"08CA",'1'&x"08CB",'1'&x"08CC",'1'&x"08CD",'1'&x"08CE",'1'&x"08CF",
+--'1'&x"08D0",'1'&x"08D1",'1'&x"08D2",'1'&x"08D3",'1'&x"08D4",'1'&x"08D5",'1'&x"08D6",'1'&x"08D7",'1'&x"08D8",'1'&x"08D9",'1'&x"08DA",'1'&x"08DB",'1'&x"08DC",'1'&x"08DD",'1'&x"08DE",'1'&x"08DF",
+--'1'&x"08E0",'1'&x"08E1",'1'&x"08E2",'1'&x"08E3",'1'&x"08E4",'1'&x"08E5",'1'&x"08E6",'1'&x"08E7",'1'&x"08E8",'1'&x"08E9",'1'&x"08EA",'1'&x"08EB",'1'&x"08EC",'1'&x"08ED",'1'&x"08EE",'1'&x"08EF",
+--'1'&x"08F0",'1'&x"08F1",'1'&x"08F2",'1'&x"08F3",'1'&x"08F4",'1'&x"08F5",'1'&x"08F6",'1'&x"08F7",'1'&x"08F8",'1'&x"08F9",'1'&x"08FA",'1'&x"08FB",'1'&x"08FC",'1'&x"08FD",'1'&x"08FE",'1'&x"08FF",
+--'1'&x"0900",'1'&x"0901",'1'&x"0902",'1'&x"0903",'1'&x"0904",'1'&x"0905",'1'&x"0906",'1'&x"0907",'1'&x"0908",'1'&x"0909",'1'&x"090A",'1'&x"090B",'1'&x"090C",'1'&x"090D",'1'&x"090E",'1'&x"090F",
+--'1'&x"0910",'1'&x"0911",'1'&x"0912",'1'&x"0913",'1'&x"0914",'1'&x"0915",'1'&x"0916",'1'&x"0917",'1'&x"0918",'1'&x"0919",'1'&x"091A",'1'&x"091B",'1'&x"091C",'1'&x"091D",'1'&x"091E",'1'&x"091F",
+--'1'&x"0920",'1'&x"0921",'1'&x"0922",'1'&x"0923",'1'&x"0924",'1'&x"0925",'1'&x"0926",'1'&x"0927",'1'&x"0928",'1'&x"0929",'1'&x"092A",'1'&x"092B",'1'&x"092C",'1'&x"092D",'1'&x"092E",'1'&x"092F",
+--'1'&x"0930",'1'&x"0931",'1'&x"0932",'1'&x"0933",'1'&x"0934",'1'&x"0935",'1'&x"0936",'1'&x"0937",'1'&x"0938",'1'&x"0939",'1'&x"093A",'1'&x"093B",'1'&x"093C",'1'&x"093D",'1'&x"093E",'1'&x"093F",
+--'1'&x"0940",'1'&x"0941",'1'&x"0942",'1'&x"0943",'1'&x"0944",'1'&x"0945",'1'&x"0946",'1'&x"0947",'1'&x"0948",'1'&x"0949",'1'&x"094A",'1'&x"094B",'1'&x"094C",'1'&x"094D",'1'&x"094E",'1'&x"094F",
+--'1'&x"0950",'1'&x"0951",'1'&x"0952",'1'&x"0953",'1'&x"0954",'1'&x"0955",'1'&x"0956",'1'&x"0957",'1'&x"0958",'1'&x"0959",'1'&x"095A",'1'&x"095B",'1'&x"095C",'1'&x"095D",'1'&x"095E",'1'&x"095F",
+--'1'&x"0960",'1'&x"0961",'1'&x"0962",'1'&x"0963",'1'&x"0964",'1'&x"0965",'1'&x"0966",'1'&x"0967",'1'&x"0968",'1'&x"0969",'1'&x"096A",'1'&x"096B",'1'&x"096C",'1'&x"096D",'1'&x"096E",'1'&x"096F",
+--'1'&x"0970",'1'&x"0971",'1'&x"0972",'1'&x"0973",'1'&x"0974",'1'&x"0975",'1'&x"0976",'1'&x"0977",'1'&x"0978",'1'&x"0979",'1'&x"097A",'1'&x"097B",'1'&x"097C",'1'&x"097D",'1'&x"097E",'1'&x"097F",
+--'1'&x"0980",'1'&x"0981",'1'&x"0982",'1'&x"0983",'1'&x"0984",'1'&x"0985",'1'&x"0986",'1'&x"0987",'1'&x"0988",'1'&x"0989",'1'&x"098A",'1'&x"098B",'1'&x"098C",'1'&x"098D",'1'&x"098E",'1'&x"098F",
+--'1'&x"0990",'1'&x"0991",'1'&x"0992",'1'&x"0993",'1'&x"0994",'1'&x"0995",'1'&x"0996",'1'&x"0997",'1'&x"0998",'1'&x"0999",'1'&x"099A",'1'&x"099B",'1'&x"099C",'1'&x"099D",'1'&x"099E",'1'&x"099F",
+--'1'&x"09A0",'1'&x"09A1",'1'&x"09A2",'1'&x"09A3",'1'&x"09A4",'1'&x"09A5",'1'&x"09A6",'1'&x"09A7",'1'&x"09A8",'1'&x"09A9",'1'&x"09AA",'1'&x"09AB",'1'&x"09AC",'1'&x"09AD",'1'&x"09AE",'1'&x"09AF",
+--'1'&x"09B0",'1'&x"09B1",'1'&x"09B2",'1'&x"09B3",'1'&x"09B4",'1'&x"09B5",'1'&x"09B6",'1'&x"09B7",'1'&x"09B8",'1'&x"09B9",'1'&x"09BA",'1'&x"09BB",'1'&x"09BC",'1'&x"09BD",'1'&x"09BE",'1'&x"09BF",
+--'1'&x"09C0",'1'&x"09C1",'1'&x"09C2",'1'&x"09C3",'1'&x"09C4",'1'&x"09C5",'1'&x"09C6",'1'&x"09C7",'1'&x"09C8",'1'&x"09C9",'1'&x"09CA",'1'&x"09CB",'1'&x"09CC",'1'&x"09CD",'1'&x"09CE",'1'&x"09CF",
+--'1'&x"09D0",'1'&x"09D1",'1'&x"09D2",'1'&x"09D3",'1'&x"09D4",'1'&x"09D5",'1'&x"09D6",'1'&x"09D7",'1'&x"09D8",'1'&x"09D9",'1'&x"09DA",'1'&x"09DB",'1'&x"09DC",'1'&x"09DD",'1'&x"09DE",'1'&x"09DF",
+--'1'&x"09E0",'1'&x"09E1",'1'&x"09E2",'1'&x"09E3",'1'&x"09E4",'1'&x"09E5",'1'&x"09E6",'1'&x"09E7",'1'&x"09E8",'1'&x"09E9",'1'&x"09EA",'1'&x"09EB",'1'&x"09EC",'1'&x"09ED",'1'&x"09EE",'1'&x"09EF",
+--'1'&x"09F0",'1'&x"09F1",'1'&x"09F2",'1'&x"09F3",'1'&x"09F4",'1'&x"09F5",'1'&x"09F6",'1'&x"09F7",'1'&x"09F8",'1'&x"09F9",'1'&x"09FA",'1'&x"09FB",'1'&x"09FC",'1'&x"09FD",'1'&x"09FE",'1'&x"09FF",
+--'1'&x"0A00",'1'&x"0A01",'1'&x"0A02",'1'&x"0A03",'1'&x"0A04",'1'&x"0A05",'1'&x"0A06",'1'&x"0A07",'1'&x"0A08",'1'&x"0A09",'1'&x"0A0A",'1'&x"0A0B",'1'&x"0A0C",'1'&x"0A0D",'1'&x"0A0E",'1'&x"0A0F",
+--'1'&x"0A10",'1'&x"0A11",'1'&x"0A12",'1'&x"0A13",'1'&x"0A14",'1'&x"0A15",'1'&x"0A16",'1'&x"0A17",'1'&x"0A18",'1'&x"0A19",'1'&x"0A1A",'1'&x"0A1B",'1'&x"0A1C",'1'&x"0A1D",'1'&x"0A1E",'1'&x"0A1F",
+--'1'&x"0A20",'1'&x"0A21",'1'&x"0A22",'1'&x"0A23",'1'&x"0A24",'1'&x"0A25",'1'&x"0A26",'1'&x"0A27",'1'&x"0A28",'1'&x"0A29",'1'&x"0A2A",'1'&x"0A2B",'1'&x"0A2C",'1'&x"0A2D",'1'&x"0A2E",'1'&x"0A2F",
+--'1'&x"0A30",'1'&x"0A31",'1'&x"0A32",'1'&x"0A33",'1'&x"0A34",'1'&x"0A35",'1'&x"0A36",'1'&x"0A37",'1'&x"0A38",'1'&x"0A39",'1'&x"0A3A",'1'&x"0A3B",'1'&x"0A3C",'1'&x"0A3D",'1'&x"0A3E",'1'&x"0A3F",
+--'1'&x"0A40",'1'&x"0A41",'1'&x"0A42",'1'&x"0A43",'1'&x"0A44",'1'&x"0A45",'1'&x"0A46",'1'&x"0A47",'1'&x"0A48",'1'&x"0A49",'1'&x"0A4A",'1'&x"0A4B",'1'&x"0A4C",'1'&x"0A4D",'1'&x"0A4E",'1'&x"0A4F",
+--'1'&x"0A50",'1'&x"0A51",'1'&x"0A52",'1'&x"0A53",'1'&x"0A54",'1'&x"0A55",'1'&x"0A56",'1'&x"0A57",'1'&x"0A58",'1'&x"0A59",'1'&x"0A5A",'1'&x"0A5B",'1'&x"0A5C",'1'&x"0A5D",'1'&x"0A5E",'1'&x"0A5F",
+--'1'&x"0A60",'1'&x"0A61",'1'&x"0A62",'1'&x"0A63",'1'&x"0A64",'1'&x"0A65",'1'&x"0A66",'1'&x"0A67",'1'&x"0A68",'1'&x"0A69",'1'&x"0A6A",'1'&x"0A6B",'1'&x"0A6C",'1'&x"0A6D",'1'&x"0A6E",'1'&x"0A6F",
+--'1'&x"0A70",'1'&x"0A71",'1'&x"0A72",'1'&x"0A73",'1'&x"0A74",'1'&x"0A75",'1'&x"0A76",'1'&x"0A77",'1'&x"0A78",'1'&x"0A79",'1'&x"0A7A",'1'&x"0A7B",'1'&x"0A7C",'1'&x"0A7D",'1'&x"0A7E",'1'&x"0A7F",
+--'1'&x"0A80",'1'&x"0A81",'1'&x"0A82",'1'&x"0A83",'1'&x"0A84",'1'&x"0A85",'1'&x"0A86",'1'&x"0A87",'1'&x"0A88",'1'&x"0A89",'1'&x"0A8A",'1'&x"0A8B",'1'&x"0A8C",'1'&x"0A8D",'1'&x"0A8E",'1'&x"0A8F",
+--'1'&x"0A90",'1'&x"0A91",'1'&x"0A92",'1'&x"0A93",'1'&x"0A94",'1'&x"0A95",'1'&x"0A96",'1'&x"0A97",'1'&x"0A98",'1'&x"0A99",'1'&x"0A9A",'1'&x"0A9B",'1'&x"0A9C",'1'&x"0A9D",'1'&x"0A9E",'1'&x"0A9F",
+--'1'&x"0AA0",'1'&x"0AA1",'1'&x"0AA2",'1'&x"0AA3",'1'&x"0AA4",'1'&x"0AA5",'1'&x"0AA6",'1'&x"0AA7",'1'&x"0AA8",'1'&x"0AA9",'1'&x"0AAA",'1'&x"0AAB",'1'&x"0AAC",'1'&x"0AAD",'1'&x"0AAE",'1'&x"0AAF",
+--'1'&x"0AB0",'1'&x"0AB1",'1'&x"0AB2",'1'&x"0AB3",'1'&x"0AB4",'1'&x"0AB5",'1'&x"0AB6",'1'&x"0AB7",'1'&x"0AB8",'1'&x"0AB9",'1'&x"0ABA",'1'&x"0ABB",'1'&x"0ABC",'1'&x"0ABD",'1'&x"0ABE",'1'&x"0ABF",
+--'1'&x"0AC0",'1'&x"0AC1",'1'&x"0AC2",'1'&x"0AC3",'1'&x"0AC4",'1'&x"0AC5",'1'&x"0AC6",'1'&x"0AC7",'1'&x"0AC8",'1'&x"0AC9",'1'&x"0ACA",'1'&x"0ACB",'1'&x"0ACC",'1'&x"0ACD",'1'&x"0ACE",'1'&x"0ACF",
+--'1'&x"0AD0",'1'&x"0AD1",'1'&x"0AD2",'1'&x"0AD3",'1'&x"0AD4",'1'&x"0AD5",'1'&x"0AD6",'1'&x"0AD7",'1'&x"0AD8",'1'&x"0AD9",'1'&x"0ADA",'1'&x"0ADB",'1'&x"0ADC",'1'&x"0ADD",'1'&x"0ADE",'1'&x"0ADF",
+--'1'&x"0AE0",'1'&x"0AE1",'1'&x"0AE2",'1'&x"0AE3",'1'&x"0AE4",'1'&x"0AE5",'1'&x"0AE6",'1'&x"0AE7",'1'&x"0AE8",'1'&x"0AE9",'1'&x"0AEA",'1'&x"0AEB",'1'&x"0AEC",'1'&x"0AED",'1'&x"0AEE",'1'&x"0AEF",
+--'1'&x"0AF0",'1'&x"0AF1",'1'&x"0AF2",'1'&x"0AF3",'1'&x"0AF4",'1'&x"0AF5",'1'&x"0AF6",'1'&x"0AF7",'1'&x"0AF8",'1'&x"0AF9",'1'&x"0AFA",'1'&x"0AFB",'1'&x"0AFC",'1'&x"0AFD",'1'&x"0AFE",'1'&x"0AFF",
+--'1'&x"0B00",'1'&x"0B01",'1'&x"0B02",'1'&x"0B03",'1'&x"0B04",'1'&x"0B05",'1'&x"0B06",'1'&x"0B07",'1'&x"0B08",'1'&x"0B09",'1'&x"0B0A",'1'&x"0B0B",'1'&x"0B0C",'1'&x"0B0D",'1'&x"0B0E",'1'&x"0B0F",
+--'1'&x"0B10",'1'&x"0B11",'1'&x"0B12",'1'&x"0B13",'1'&x"0B14",'1'&x"0B15",'1'&x"0B16",'1'&x"0B17",'1'&x"0B18",'1'&x"0B19",'1'&x"0B1A",'1'&x"0B1B",'1'&x"0B1C",'1'&x"0B1D",'1'&x"0B1E",'1'&x"0B1F",
+--'1'&x"0B20",'1'&x"0B21",'1'&x"0B22",'1'&x"0B23",'1'&x"0B24",'1'&x"0B25",'1'&x"0B26",'1'&x"0B27",'1'&x"0B28",'1'&x"0B29",'1'&x"0B2A",'1'&x"0B2B",'1'&x"0B2C",'1'&x"0B2D",'1'&x"0B2E",'1'&x"0B2F",
+--'1'&x"0B30",'1'&x"0B31",'1'&x"0B32",'1'&x"0B33",'1'&x"0B34",'1'&x"0B35",'1'&x"0B36",'1'&x"0B37",'1'&x"0B38",'1'&x"0B39",'1'&x"0B3A",'1'&x"0B3B",'1'&x"0B3C",'1'&x"0B3D",'1'&x"0B3E",'1'&x"0B3F",
+--'1'&x"0B40",'1'&x"0B41",'1'&x"0B42",'1'&x"0B43",'1'&x"0B44",'1'&x"0B45",'1'&x"0B46",'1'&x"0B47",'1'&x"0B48",'1'&x"0B49",'1'&x"0B4A",'1'&x"0B4B",'1'&x"0B4C",'1'&x"0B4D",'1'&x"0B4E",'1'&x"0B4F",
+--'1'&x"0B50",'1'&x"0B51",'1'&x"0B52",'1'&x"0B53",'1'&x"0B54",'1'&x"0B55",'1'&x"0B56",'1'&x"0B57",'1'&x"0B58",'1'&x"0B59",'1'&x"0B5A",'1'&x"0B5B",'1'&x"0B5C",'1'&x"0B5D",'1'&x"0B5E",'1'&x"0B5F",
+--'1'&x"0B60",'1'&x"0B61",'1'&x"0B62",'1'&x"0B63",'1'&x"0B64",'1'&x"0B65",'1'&x"0B66",'1'&x"0B67",'1'&x"0B68",'1'&x"0B69",'1'&x"0B6A",'1'&x"0B6B",'1'&x"0B6C",'1'&x"0B6D",'1'&x"0B6E",'1'&x"0B6F",
+--'1'&x"0B70",'1'&x"0B71",'1'&x"0B72",'1'&x"0B73",'1'&x"0B74",'1'&x"0B75",'1'&x"0B76",'1'&x"0B77",'1'&x"0B78",'1'&x"0B79",'1'&x"0B7A",'1'&x"0B7B",'1'&x"0B7C",'1'&x"0B7D",'1'&x"0B7E",'1'&x"0B7F",
+--'1'&x"0B80",'1'&x"0B81",'1'&x"0B82",'1'&x"0B83",'1'&x"0B84",'1'&x"0B85",'1'&x"0B86",'1'&x"0B87",'1'&x"0B88",'1'&x"0B89",'1'&x"0B8A",'1'&x"0B8B",'1'&x"0B8C",'1'&x"0B8D",'1'&x"0B8E",'1'&x"0B8F",
+--'1'&x"0B90",'1'&x"0B91",'1'&x"0B92",'1'&x"0B93",'1'&x"0B94",'1'&x"0B95",'1'&x"0B96",'1'&x"0B97",'1'&x"0B98",'1'&x"0B99",'1'&x"0B9A",'1'&x"0B9B",'1'&x"0B9C",'1'&x"0B9D",'1'&x"0B9E",'1'&x"0B9F",
+--'1'&x"0BA0",'1'&x"0BA1",'1'&x"0BA2",'1'&x"0BA3",'1'&x"0BA4",'1'&x"0BA5",'1'&x"0BA6",'1'&x"0BA7",'1'&x"0BA8",'1'&x"0BA9",'1'&x"0BAA",'1'&x"0BAB",'1'&x"0BAC",'1'&x"0BAD",'1'&x"0BAE",'1'&x"0BAF",
+--'1'&x"0BB0",'1'&x"0BB1",'1'&x"0BB2",'1'&x"0BB3",'1'&x"0BB4",'1'&x"0BB5",'1'&x"0BB6",'1'&x"0BB7",'1'&x"0BB8",'1'&x"0BB9",'1'&x"0BBA",'1'&x"0BBB",'1'&x"0BBC",'1'&x"0BBD",'1'&x"0BBE",'1'&x"0BBF",
+--'1'&x"0BC0",'1'&x"0BC1",'1'&x"0BC2",'1'&x"0BC3",'1'&x"0BC4",'1'&x"0BC5",'1'&x"0BC6",'1'&x"0BC7",'1'&x"0BC8",'1'&x"0BC9",'1'&x"0BCA",'1'&x"0BCB",'1'&x"0BCC",'1'&x"0BCD",'1'&x"0BCE",'1'&x"0BCF",
+--'1'&x"0BD0",'1'&x"0BD1",'1'&x"0BD2",'1'&x"0BD3",'1'&x"0BD4",'1'&x"0BD5",'1'&x"0BD6",'1'&x"0BD7",'1'&x"0BD8",'1'&x"0BD9",'1'&x"0BDA",'1'&x"0BDB",'1'&x"0BDC",'1'&x"0BDD",'1'&x"0BDE",'1'&x"0BDF",
+--'1'&x"0BE0",'1'&x"0BE1",'1'&x"0BE2",'1'&x"0BE3",'1'&x"0BE4",'1'&x"0BE5",'1'&x"0BE6",'1'&x"0BE7",'1'&x"0BE8",'1'&x"0BE9",'1'&x"0BEA",'1'&x"0BEB",'1'&x"0BEC",'1'&x"0BED",'1'&x"0BEE",'1'&x"0BEF",
+--'1'&x"0BF0",'1'&x"0BF1",'1'&x"0BF2",'1'&x"0BF3",'1'&x"0BF4",'1'&x"0BF5",'1'&x"0BF6",'1'&x"0BF7",'1'&x"0BF8",'1'&x"0BF9",'1'&x"0BFA",'1'&x"0BFB",'1'&x"0BFC",'1'&x"0BFD",'1'&x"0BFE",'1'&x"0BFF",
+--'1'&x"0C00",'1'&x"0C01",'1'&x"0C02",'1'&x"0C03",'1'&x"0C04",'1'&x"0C05",'1'&x"0C06",'1'&x"0C07",'1'&x"0C08",'1'&x"0C09",'1'&x"0C0A",'1'&x"0C0B",'1'&x"0C0C",'1'&x"0C0D",'1'&x"0C0E",'1'&x"0C0F",
+--'1'&x"0C10",'1'&x"0C11",'1'&x"0C12",'1'&x"0C13",'1'&x"0C14",'1'&x"0C15",'1'&x"0C16",'1'&x"0C17",'1'&x"0C18",'1'&x"0C19",'1'&x"0C1A",'1'&x"0C1B",'1'&x"0C1C",'1'&x"0C1D",'1'&x"0C1E",'1'&x"0C1F",
+--'1'&x"0C20",'1'&x"0C21",'1'&x"0C22",'1'&x"0C23",'1'&x"0C24",'1'&x"0C25",'1'&x"0C26",'1'&x"0C27",'1'&x"0C28",'1'&x"0C29",'1'&x"0C2A",'1'&x"0C2B",'1'&x"0C2C",'1'&x"0C2D",'1'&x"0C2E",'1'&x"0C2F",
+--'1'&x"0C30",'1'&x"0C31",'1'&x"0C32",'1'&x"0C33",'1'&x"0C34",'1'&x"0C35",'1'&x"0C36",'1'&x"0C37",'1'&x"0C38",'1'&x"0C39",'1'&x"0C3A",'1'&x"0C3B",'1'&x"0C3C",'1'&x"0C3D",'1'&x"0C3E",'1'&x"0C3F",
+--'1'&x"0C40",'1'&x"0C41",'1'&x"0C42",'1'&x"0C43",'1'&x"0C44",'1'&x"0C45",'1'&x"0C46",'1'&x"0C47",'1'&x"0C48",'1'&x"0C49",'1'&x"0C4A",'1'&x"0C4B",'1'&x"0C4C",'1'&x"0C4D",'1'&x"0C4E",'1'&x"0C4F",
+--'1'&x"0C50",'1'&x"0C51",'1'&x"0C52",'1'&x"0C53",'1'&x"0C54",'1'&x"0C55",'1'&x"0C56",'1'&x"0C57",'1'&x"0C58",'1'&x"0C59",'1'&x"0C5A",'1'&x"0C5B",'1'&x"0C5C",'1'&x"0C5D",'1'&x"0C5E",'1'&x"0C5F",
+--'1'&x"0C60",'1'&x"0C61",'1'&x"0C62",'1'&x"0C63",'1'&x"0C64",'1'&x"0C65",'1'&x"0C66",'1'&x"0C67",'1'&x"0C68",'1'&x"0C69",'1'&x"0C6A",'1'&x"0C6B",'1'&x"0C6C",'1'&x"0C6D",'1'&x"0C6E",'1'&x"0C6F",
+--'1'&x"0C70",'1'&x"0C71",'1'&x"0C72",'1'&x"0C73",'1'&x"0C74",'1'&x"0C75",'1'&x"0C76",'1'&x"0C77",'1'&x"0C78",'1'&x"0C79",'1'&x"0C7A",'1'&x"0C7B",'1'&x"0C7C",'1'&x"0C7D",'1'&x"0C7E",'1'&x"0C7F",
+--'1'&x"0C80",'1'&x"0C81",'1'&x"0C82",'1'&x"0C83",'1'&x"0C84",'1'&x"0C85",'1'&x"0C86",'1'&x"0C87",'1'&x"0C88",'1'&x"0C89",'1'&x"0C8A",'1'&x"0C8B",'1'&x"0C8C",'1'&x"0C8D",'1'&x"0C8E",'1'&x"0C8F",
+--'1'&x"0C90",'1'&x"0C91",'1'&x"0C92",'1'&x"0C93",'1'&x"0C94",'1'&x"0C95",'1'&x"0C96",'1'&x"0C97",'1'&x"0C98",'1'&x"0C99",'1'&x"0C9A",'1'&x"0C9B",'1'&x"0C9C",'1'&x"0C9D",'1'&x"0C9E",'1'&x"0C9F",
+--'1'&x"0CA0",'1'&x"0CA1",'1'&x"0CA2",'1'&x"0CA3",'1'&x"0CA4",'1'&x"0CA5",'1'&x"0CA6",'1'&x"0CA7",'1'&x"0CA8",'1'&x"0CA9",'1'&x"0CAA",'1'&x"0CAB",'1'&x"0CAC",'1'&x"0CAD",'1'&x"0CAE",'1'&x"0CAF",
+--'1'&x"0CB0",'1'&x"0CB1",'1'&x"0CB2",'1'&x"0CB3",'1'&x"0CB4",'1'&x"0CB5",'1'&x"0CB6",'1'&x"0CB7",'1'&x"0CB8",'1'&x"0CB9",'1'&x"0CBA",'1'&x"0CBB",'1'&x"0CBC",'1'&x"0CBD",'1'&x"0CBE",'1'&x"0CBF",
+--'1'&x"0CC0",'1'&x"0CC1",'1'&x"0CC2",'1'&x"0CC3",'1'&x"0CC4",'1'&x"0CC5",'1'&x"0CC6",'1'&x"0CC7",'1'&x"0CC8",'1'&x"0CC9",'1'&x"0CCA",'1'&x"0CCB",'1'&x"0CCC",'1'&x"0CCD",'1'&x"0CCE",'1'&x"0CCF",
+--'1'&x"0CD0",'1'&x"0CD1",'1'&x"0CD2",'1'&x"0CD3",'1'&x"0CD4",'1'&x"0CD5",'1'&x"0CD6",'1'&x"0CD7",'1'&x"0CD8",'1'&x"0CD9",'1'&x"0CDA",'1'&x"0CDB",'1'&x"0CDC",'1'&x"0CDD",'1'&x"0CDE",'1'&x"0CDF",
+--'1'&x"0CE0",'1'&x"0CE1",'1'&x"0CE2",'1'&x"0CE3",'1'&x"0CE4",'1'&x"0CE5",'1'&x"0CE6",'1'&x"0CE7",'1'&x"0CE8",'1'&x"0CE9",'1'&x"0CEA",'1'&x"0CEB",'1'&x"0CEC",'1'&x"0CED",'1'&x"0CEE",'1'&x"0CEF",
+--'1'&x"0CF0",'1'&x"0CF1",'1'&x"0CF2",'1'&x"0CF3",'1'&x"0CF4",'1'&x"0CF5",'1'&x"0CF6",'1'&x"0CF7",'1'&x"0CF8",'1'&x"0CF9",'1'&x"0CFA",'1'&x"0CFB",'1'&x"0CFC",'1'&x"0CFD",'1'&x"0CFE",'1'&x"0CFF",
+--'1'&x"0D00",'1'&x"0D01",'1'&x"0D02",'1'&x"0D03",'1'&x"0D04",'1'&x"0D05",'1'&x"0D06",'1'&x"0D07",'1'&x"0D08",'1'&x"0D09",'1'&x"0D0A",'1'&x"0D0B",'1'&x"0D0C",'1'&x"0D0D",'1'&x"0D0E",'1'&x"0D0F",
+--'1'&x"0D10",'1'&x"0D11",'1'&x"0D12",'1'&x"0D13",'1'&x"0D14",'1'&x"0D15",'1'&x"0D16",'1'&x"0D17",'1'&x"0D18",'1'&x"0D19",'1'&x"0D1A",'1'&x"0D1B",'1'&x"0D1C",'1'&x"0D1D",'1'&x"0D1E",'1'&x"0D1F",
+--'1'&x"0D20",'1'&x"0D21",'1'&x"0D22",'1'&x"0D23",'1'&x"0D24",'1'&x"0D25",'1'&x"0D26",'1'&x"0D27",'1'&x"0D28",'1'&x"0D29",'1'&x"0D2A",'1'&x"0D2B",'1'&x"0D2C",'1'&x"0D2D",'1'&x"0D2E",'1'&x"0D2F",
+--'1'&x"0D30",'1'&x"0D31",'1'&x"0D32",'1'&x"0D33",'1'&x"0D34",'1'&x"0D35",'1'&x"0D36",'1'&x"0D37",'1'&x"0D38",'1'&x"0D39",'1'&x"0D3A",'1'&x"0D3B",'1'&x"0D3C",'1'&x"0D3D",'1'&x"0D3E",'1'&x"0D3F",
+--'1'&x"0D40",'1'&x"0D41",'1'&x"0D42",'1'&x"0D43",'1'&x"0D44",'1'&x"0D45",'1'&x"0D46",'1'&x"0D47",'1'&x"0D48",'1'&x"0D49",'1'&x"0D4A",'1'&x"0D4B",'1'&x"0D4C",'1'&x"0D4D",'1'&x"0D4E",'1'&x"0D4F",
+--'1'&x"0D50",'1'&x"0D51",'1'&x"0D52",'1'&x"0D53",'1'&x"0D54",'1'&x"0D55",'1'&x"0D56",'1'&x"0D57",'1'&x"0D58",'1'&x"0D59",'1'&x"0D5A",'1'&x"0D5B",'1'&x"0D5C",'1'&x"0D5D",'1'&x"0D5E",'1'&x"0D5F",
+--'1'&x"0D60",'1'&x"0D61",'1'&x"0D62",'1'&x"0D63",'1'&x"0D64",'1'&x"0D65",'1'&x"0D66",'1'&x"0D67",'1'&x"0D68",'1'&x"0D69",'1'&x"0D6A",'1'&x"0D6B",'1'&x"0D6C",'1'&x"0D6D",'1'&x"0D6E",'1'&x"0D6F",
+--'1'&x"0D70",'1'&x"0D71",'1'&x"0D72",'1'&x"0D73",'1'&x"0D74",'1'&x"0D75",'1'&x"0D76",'1'&x"0D77",'1'&x"0D78",'1'&x"0D79",'1'&x"0D7A",'1'&x"0D7B",'1'&x"0D7C",'1'&x"0D7D",'1'&x"0D7E",'1'&x"0D7F",
+--'1'&x"0D80",'1'&x"0D81",'1'&x"0D82",'1'&x"0D83",'1'&x"0D84",'1'&x"0D85",'1'&x"0D86",'1'&x"0D87",'1'&x"0D88",'1'&x"0D89",'1'&x"0D8A",'1'&x"0D8B",'1'&x"0D8C",'1'&x"0D8D",'1'&x"0D8E",'1'&x"0D8F",
+--'1'&x"0D90",'1'&x"0D91",'1'&x"0D92",'1'&x"0D93",'1'&x"0D94",'1'&x"0D95",'1'&x"0D96",'1'&x"0D97",'1'&x"0D98",'1'&x"0D99",'1'&x"0D9A",'1'&x"0D9B",'1'&x"0D9C",'1'&x"0D9D",'1'&x"0D9E",'1'&x"0D9F",
+--'1'&x"0DA0",'1'&x"0DA1",'1'&x"0DA2",'1'&x"0DA3",'1'&x"0DA4",'1'&x"0DA5",'1'&x"0DA6",'1'&x"0DA7",'1'&x"0DA8",'1'&x"0DA9",'1'&x"0DAA",'1'&x"0DAB",'1'&x"0DAC",'1'&x"0DAD",'1'&x"0DAE",'1'&x"0DAF",
+--'1'&x"0DB0",'1'&x"0DB1",'1'&x"0DB2",'1'&x"0DB3",'1'&x"0DB4",'1'&x"0DB5",'1'&x"0DB6",'1'&x"0DB7",'1'&x"0DB8",'1'&x"0DB9",'1'&x"0DBA",'1'&x"0DBB",'1'&x"0DBC",'1'&x"0DBD",'1'&x"0DBE",'1'&x"0DBF",
+--'1'&x"0DC0",'1'&x"0DC1",'1'&x"0DC2",'1'&x"0DC3",'1'&x"0DC4",'1'&x"0DC5",'1'&x"0DC6",'1'&x"0DC7",'1'&x"0DC8",'1'&x"0DC9",'1'&x"0DCA",'1'&x"0DCB",'1'&x"0DCC",'1'&x"0DCD",'1'&x"0DCE",'1'&x"0DCF",
+--'1'&x"0DD0",'1'&x"0DD1",'1'&x"0DD2",'1'&x"0DD3",'1'&x"0DD4",'1'&x"0DD5",'1'&x"0DD6",'1'&x"0DD7",'1'&x"0DD8",'1'&x"0DD9",'1'&x"0DDA",'1'&x"0DDB",'1'&x"0DDC",'1'&x"0DDD",'1'&x"0DDE",'1'&x"0DDF",
+--'1'&x"0DE0",'1'&x"0DE1",'1'&x"0DE2",'1'&x"0DE3",'1'&x"0DE4",'1'&x"0DE5",'1'&x"0DE6",'1'&x"0DE7",'1'&x"0DE8",'1'&x"0DE9",'1'&x"0DEA",'1'&x"0DEB",'1'&x"0DEC",'1'&x"0DED",'1'&x"0DEE",'1'&x"0DEF",
+--'1'&x"0DF0",'1'&x"0DF1",'1'&x"0DF2",'1'&x"0DF3",'1'&x"0DF4",'1'&x"0DF5",'1'&x"0DF6",'1'&x"0DF7",'1'&x"0DF8",'1'&x"0DF9",'1'&x"0DFA",'1'&x"0DFB",'1'&x"0DFC",'1'&x"0DFD",'1'&x"0DFE",'1'&x"0DFF",
+--'1'&x"0E00",'1'&x"0E01",'1'&x"0E02",'1'&x"0E03",'1'&x"0E04",'1'&x"0E05",'1'&x"0E06",'1'&x"0E07",'1'&x"0E08",'1'&x"0E09",'1'&x"0E0A",'1'&x"0E0B",'1'&x"0E0C",'1'&x"0E0D",'1'&x"0E0E",'1'&x"0E0F",
+--'1'&x"0E10",'1'&x"0E11",'1'&x"0E12",'1'&x"0E13",'1'&x"0E14",'1'&x"0E15",'1'&x"0E16",'1'&x"0E17",'1'&x"0E18",'1'&x"0E19",'1'&x"0E1A",'1'&x"0E1B",'1'&x"0E1C",'1'&x"0E1D",'1'&x"0E1E",'1'&x"0E1F",
+--'1'&x"0E20",'1'&x"0E21",'1'&x"0E22",'1'&x"0E23",'1'&x"0E24",'1'&x"0E25",'1'&x"0E26",'1'&x"0E27",'1'&x"0E28",'1'&x"0E29",'1'&x"0E2A",'1'&x"0E2B",'1'&x"0E2C",'1'&x"0E2D",'1'&x"0E2E",'1'&x"0E2F",
+--'1'&x"0E30",'1'&x"0E31",'1'&x"0E32",'1'&x"0E33",'1'&x"0E34",'1'&x"0E35",'1'&x"0E36",'1'&x"0E37",'1'&x"0E38",'1'&x"0E39",'1'&x"0E3A",'1'&x"0E3B",'1'&x"0E3C",'1'&x"0E3D",'1'&x"0E3E",'1'&x"0E3F",
+--'1'&x"0E40",'1'&x"0E41",'1'&x"0E42",'1'&x"0E43",'1'&x"0E44",'1'&x"0E45",'1'&x"0E46",'1'&x"0E47",'1'&x"0E48",'1'&x"0E49",'1'&x"0E4A",'1'&x"0E4B",'1'&x"0E4C",'1'&x"0E4D",'1'&x"0E4E",'1'&x"0E4F",
+--'1'&x"0E50",'1'&x"0E51",'1'&x"0E52",'1'&x"0E53",'1'&x"0E54",'1'&x"0E55",'1'&x"0E56",'1'&x"0E57",'1'&x"0E58",'1'&x"0E59",'1'&x"0E5A",'1'&x"0E5B",'1'&x"0E5C",'1'&x"0E5D",'1'&x"0E5E",'1'&x"0E5F",
+--'1'&x"0E60",'1'&x"0E61",'1'&x"0E62",'1'&x"0E63",'1'&x"0E64",'1'&x"0E65",'1'&x"0E66",'1'&x"0E67",'1'&x"0E68",'1'&x"0E69",'1'&x"0E6A",'1'&x"0E6B",'1'&x"0E6C",'1'&x"0E6D",'1'&x"0E6E",'1'&x"0E6F",
+--'1'&x"0E70",'1'&x"0E71",'1'&x"0E72",'1'&x"0E73",'1'&x"0E74",'1'&x"0E75",'1'&x"0E76",'1'&x"0E77",'1'&x"0E78",'1'&x"0E79",'1'&x"0E7A",'1'&x"0E7B",'1'&x"0E7C",'1'&x"0E7D",'1'&x"0E7E",'1'&x"0E7F",
+--'1'&x"0E80",'1'&x"0E81",'1'&x"0E82",'1'&x"0E83",'1'&x"0E84",'1'&x"0E85",'1'&x"0E86",'1'&x"0E87",'1'&x"0E88",'1'&x"0E89",'1'&x"0E8A",'1'&x"0E8B",'1'&x"0E8C",'1'&x"0E8D",'1'&x"0E8E",'1'&x"0E8F",
+--'1'&x"0E90",'1'&x"0E91",'1'&x"0E92",'1'&x"0E93",'1'&x"0E94",'1'&x"0E95",'1'&x"0E96",'1'&x"0E97",'1'&x"0E98",'1'&x"0E99",'1'&x"0E9A",'1'&x"0E9B",'1'&x"0E9C",'1'&x"0E9D",'1'&x"0E9E",'1'&x"0E9F",
+--'1'&x"0EA0",'1'&x"0EA1",'1'&x"0EA2",'1'&x"0EA3",'1'&x"0EA4",'1'&x"0EA5",'1'&x"0EA6",'1'&x"0EA7",'1'&x"0EA8",'1'&x"0EA9",'1'&x"0EAA",'1'&x"0EAB",'1'&x"0EAC",'1'&x"0EAD",'1'&x"0EAE",'1'&x"0EAF",
+--'1'&x"0EB0",'1'&x"0EB1",'1'&x"0EB2",'1'&x"0EB3",'1'&x"0EB4",'1'&x"0EB5",'1'&x"0EB6",'1'&x"0EB7",'1'&x"0EB8",'1'&x"0EB9",'1'&x"0EBA",'1'&x"0EBB",'1'&x"0EBC",'1'&x"0EBD",'1'&x"0EBE",'1'&x"0EBF",
+--'1'&x"0EC0",'1'&x"0EC1",'1'&x"0EC2",'1'&x"0EC3",'1'&x"0EC4",'1'&x"0EC5",'1'&x"0EC6",'1'&x"0EC7",'1'&x"0EC8",'1'&x"0EC9",'1'&x"0ECA",'1'&x"0ECB",'1'&x"0ECC",'1'&x"0ECD",'1'&x"0ECE",'1'&x"0ECF",
+--'1'&x"0ED0",'1'&x"0ED1",'1'&x"0ED2",'1'&x"0ED3",'1'&x"0ED4",'1'&x"0ED5",'1'&x"0ED6",'1'&x"0ED7",'1'&x"0ED8",'1'&x"0ED9",'1'&x"0EDA",'1'&x"0EDB",'1'&x"0EDC",'1'&x"0EDD",'1'&x"0EDE",'1'&x"0EDF",
+--'1'&x"0EE0",'1'&x"0EE1",'1'&x"0EE2",'1'&x"0EE3",'1'&x"0EE4",'1'&x"0EE5",'1'&x"0EE6",'1'&x"0EE7",'1'&x"0EE8",'1'&x"0EE9",'1'&x"0EEA",'1'&x"0EEB",'1'&x"0EEC",'1'&x"0EED",'1'&x"0EEE",'1'&x"0EEF",
+--'1'&x"0EF0",'1'&x"0EF1",'1'&x"0EF2",'1'&x"0EF3",'1'&x"0EF4",'1'&x"0EF5",'1'&x"0EF6",'1'&x"0EF7",'1'&x"0EF8",'1'&x"0EF9",'1'&x"0EFA",'1'&x"0EFB",'1'&x"0EFC",'1'&x"0EFD",'1'&x"0EFE",'1'&x"0EFF",
+--'1'&x"0F00",'1'&x"0F01",'1'&x"0F02",'1'&x"0F03",'1'&x"0F04",'1'&x"0F05",'1'&x"0F06",'1'&x"0F07",'1'&x"0F08",'1'&x"0F09",'1'&x"0F0A",'1'&x"0F0B",'1'&x"0F0C",'1'&x"0F0D",'1'&x"0F0E",'1'&x"0F0F",
+--'1'&x"0F10",'1'&x"0F11",'1'&x"0F12",'1'&x"0F13",'1'&x"0F14",'1'&x"0F15",'1'&x"0F16",'1'&x"0F17",'1'&x"0F18",'1'&x"0F19",'1'&x"0F1A",'1'&x"0F1B",'1'&x"0F1C",'1'&x"0F1D",'1'&x"0F1E",'1'&x"0F1F",
+--'1'&x"0F20",'1'&x"0F21",'1'&x"0F22",'1'&x"0F23",'1'&x"0F24",'1'&x"0F25",'1'&x"0F26",'1'&x"0F27",'1'&x"0F28",'1'&x"0F29",'1'&x"0F2A",'1'&x"0F2B",'1'&x"0F2C",'1'&x"0F2D",'1'&x"0F2E",'1'&x"0F2F",
+--'1'&x"0F30",'1'&x"0F31",'1'&x"0F32",'1'&x"0F33",'1'&x"0F34",'1'&x"0F35",'1'&x"0F36",'1'&x"0F37",'1'&x"0F38",'1'&x"0F39",'1'&x"0F3A",'1'&x"0F3B",'1'&x"0F3C",'1'&x"0F3D",'1'&x"0F3E",'1'&x"0F3F",
+--'1'&x"0F40",'1'&x"0F41",'1'&x"0F42",'1'&x"0F43",'1'&x"0F44",'1'&x"0F45",'1'&x"0F46",'1'&x"0F47",'1'&x"0F48",'1'&x"0F49",'1'&x"0F4A",'1'&x"0F4B",'1'&x"0F4C",'1'&x"0F4D",'1'&x"0F4E",'1'&x"0F4F",
+--'1'&x"0F50",'1'&x"0F51",'1'&x"0F52",'1'&x"0F53",'1'&x"0F54",'1'&x"0F55",'1'&x"0F56",'1'&x"0F57",'1'&x"0F58",'1'&x"0F59",'1'&x"0F5A",'1'&x"0F5B",'1'&x"0F5C",'1'&x"0F5D",'1'&x"0F5E",'1'&x"0F5F",
+--'1'&x"0F60",'1'&x"0F61",'1'&x"0F62",'1'&x"0F63",'1'&x"0F64",'1'&x"0F65",'1'&x"0F66",'1'&x"0F67",'1'&x"0F68",'1'&x"0F69",'1'&x"0F6A",'1'&x"0F6B",'1'&x"0F6C",'1'&x"0F6D",'1'&x"0F6E",'1'&x"0F6F",
+--'1'&x"0F70",'1'&x"0F71",'1'&x"0F72",'1'&x"0F73",'1'&x"0F74",'1'&x"0F75",'1'&x"0F76",'1'&x"0F77",'1'&x"0F78",'1'&x"0F79",'1'&x"0F7A",'1'&x"0F7B",'1'&x"0F7C",'1'&x"0F7D",'1'&x"0F7E",'1'&x"0F7F",
+--'1'&x"0F80",'1'&x"0F81",'1'&x"0F82",'1'&x"0F83",'1'&x"0F84",'1'&x"0F85",'1'&x"0F86",'1'&x"0F87",'1'&x"0F88",'1'&x"0F89",'1'&x"0F8A",'1'&x"0F8B",'1'&x"0F8C",'1'&x"0F8D",'1'&x"0F8E",'1'&x"0F8F",
+--'1'&x"0F90",'1'&x"0F91",'1'&x"0F92",'1'&x"0F93",'1'&x"0F94",'1'&x"0F95",'1'&x"0F96",'1'&x"0F97",'1'&x"0F98",'1'&x"0F99",'1'&x"0F9A",'1'&x"0F9B",'1'&x"0F9C",'1'&x"0F9D",'1'&x"0F9E",'1'&x"0F9F",
+--'1'&x"0FA0",'1'&x"0FA1",'1'&x"0FA2",'1'&x"0FA3",'1'&x"0FA4",'1'&x"0FA5",'1'&x"0FA6",'1'&x"0FA7",'1'&x"0FA8",'1'&x"0FA9",'1'&x"0FAA",'1'&x"0FAB",'1'&x"0FAC",'1'&x"0FAD",'1'&x"0FAE",'1'&x"0FAF",
+--'1'&x"0FB0",'1'&x"0FB1",'1'&x"0FB2",'1'&x"0FB3",'1'&x"0FB4",'1'&x"0FB5",'1'&x"0FB6",'1'&x"0FB7",'1'&x"0FB8",'1'&x"0FB9",'1'&x"0FBA",'1'&x"0FBB",'1'&x"0FBC",'1'&x"0FBD",'1'&x"0FBE",'1'&x"0FBF",
+--'1'&x"0FC0",'1'&x"0FC1",'1'&x"0FC2",'1'&x"0FC3",'1'&x"0FC4",'1'&x"0FC5",'1'&x"0FC6",'1'&x"0FC7",'1'&x"0FC8",'1'&x"0FC9",'1'&x"0FCA",'1'&x"0FCB",'1'&x"0FCC",'1'&x"0FCD",'1'&x"0FCE",'1'&x"0FCF",
+--'1'&x"0FD0",'1'&x"0FD1",'1'&x"0FD2",'1'&x"0FD3",'1'&x"0FD4",'1'&x"0FD5",'1'&x"0FD6",'1'&x"0FD7",'1'&x"0FD8",'1'&x"0FD9",'1'&x"0FDA",'1'&x"0FDB",'1'&x"0FDC",'1'&x"0FDD",'1'&x"0FDE",'1'&x"0FDF",
+--'1'&x"0FE0",'1'&x"0FE1",'1'&x"0FE2",'1'&x"0FE3",'1'&x"0FE4",'1'&x"0FE5",'1'&x"0FE6",'1'&x"0FE7",'1'&x"0FE8",'1'&x"0FE9",'1'&x"0FEA",'1'&x"0FEB",'1'&x"0FEC",'1'&x"0FED",'1'&x"0FEE",'1'&x"0FEF",
+--'1'&x"0FF0",'1'&x"0FF1",'1'&x"0FF2",'1'&x"0FF3",'1'&x"0FF4",'1'&x"0FF5",'1'&x"0FF6",'1'&x"0FF7",'1'&x"0FF8",'1'&x"0FF9",'1'&x"0FFA",'1'&x"0FFB",'1'&x"0FFC",'1'&x"0FFD",'1'&x"0FFE",'1'&x"0FFF",
+--'1'&x"1000",'1'&x"1001",'1'&x"1002",'1'&x"1003",'1'&x"1004",'1'&x"1005",'1'&x"1006",'1'&x"1007",'1'&x"1008",'1'&x"1009",'1'&x"100A",'1'&x"100B",'1'&x"100C",'1'&x"100D",'1'&x"100E",'1'&x"100F",
+--'1'&x"1010",'1'&x"1011",'1'&x"1012",'1'&x"1013",'1'&x"1014",'1'&x"1015",'1'&x"1016",'1'&x"1017",'1'&x"1018",'1'&x"1019",'1'&x"101A",'1'&x"101B",'1'&x"101C",'1'&x"101D",'1'&x"101E",'1'&x"101F",
+--'1'&x"1020",'1'&x"1021",'1'&x"1022",'1'&x"1023",'1'&x"1024",'1'&x"1025",'1'&x"1026",'1'&x"1027",'1'&x"1028",'1'&x"1029",'1'&x"102A",'1'&x"102B",'1'&x"102C",'1'&x"102D",'1'&x"102E",'1'&x"102F",
+--'1'&x"1030",'1'&x"1031",'1'&x"1032",'1'&x"1033",'1'&x"1034",'1'&x"1035",'1'&x"1036",'1'&x"1037",'1'&x"1038",'1'&x"1039",'1'&x"103A",'1'&x"103B",'1'&x"103C",'1'&x"103D",'1'&x"103E",'1'&x"103F",
+--'1'&x"1040",'1'&x"1041",'1'&x"1042",'1'&x"1043",'1'&x"1044",'1'&x"1045",'1'&x"1046",'1'&x"1047",'1'&x"1048",'1'&x"1049",'1'&x"104A",'1'&x"104B",'1'&x"104C",'1'&x"104D",'1'&x"104E",'1'&x"104F",
+--'1'&x"1050",'1'&x"1051",'1'&x"1052",'1'&x"1053",'1'&x"1054",'1'&x"1055",'1'&x"1056",'1'&x"1057",'1'&x"1058",'1'&x"1059",'1'&x"105A",'1'&x"105B",'1'&x"105C",'1'&x"105D",'1'&x"105E",'1'&x"105F",
+--'1'&x"1060",'1'&x"1061",'1'&x"1062",'1'&x"1063",'1'&x"1064",'1'&x"1065",'1'&x"1066",'1'&x"1067",'1'&x"1068",'1'&x"1069",'1'&x"106A",'1'&x"106B",'1'&x"106C",'1'&x"106D",'1'&x"106E",'1'&x"106F",
+--'1'&x"1070",'1'&x"1071",'1'&x"1072",'1'&x"1073",'1'&x"1074",'1'&x"1075",'1'&x"1076",'1'&x"1077",'1'&x"1078",'1'&x"1079",'1'&x"107A",'1'&x"107B",'1'&x"107C",'1'&x"107D",'1'&x"107E",'1'&x"107F",
+--'1'&x"1080",'1'&x"1081",'1'&x"1082",'1'&x"1083",'1'&x"1084",'1'&x"1085",'1'&x"1086",'1'&x"1087",'1'&x"1088",'1'&x"1089",'1'&x"108A",'1'&x"108B",'1'&x"108C",'1'&x"108D",'1'&x"108E",'1'&x"108F",
+--'1'&x"1090",'1'&x"1091",'1'&x"1092",'1'&x"1093",'1'&x"1094",'1'&x"1095",'1'&x"1096",'1'&x"1097",'1'&x"1098",'1'&x"1099",'1'&x"109A",'1'&x"109B",'1'&x"109C",'1'&x"109D",'1'&x"109E",'1'&x"109F",
+--'1'&x"10A0",'1'&x"10A1",'1'&x"10A2",'1'&x"10A3",'1'&x"10A4",'1'&x"10A5",'1'&x"10A6",'1'&x"10A7",'1'&x"10A8",'1'&x"10A9",'1'&x"10AA",'1'&x"10AB",'1'&x"10AC",'1'&x"10AD",'1'&x"10AE",'1'&x"10AF",
+--'1'&x"10B0",'1'&x"10B1",'1'&x"10B2",'1'&x"10B3",'1'&x"10B4",'1'&x"10B5",'1'&x"10B6",'1'&x"10B7",'1'&x"10B8",'1'&x"10B9",'1'&x"10BA",'1'&x"10BB",'1'&x"10BC",'1'&x"10BD",'1'&x"10BE",'1'&x"10BF",
+--'1'&x"10C0",'1'&x"10C1",'1'&x"10C2",'1'&x"10C3",'1'&x"10C4",'1'&x"10C5",'1'&x"10C6",'1'&x"10C7",'1'&x"10C8",'1'&x"10C9",'1'&x"10CA",'1'&x"10CB",'1'&x"10CC",'1'&x"10CD",'1'&x"10CE",'1'&x"10CF",
+--'1'&x"10D0",'1'&x"10D1",'1'&x"10D2",'1'&x"10D3",'1'&x"10D4",'1'&x"10D5",'1'&x"10D6",'1'&x"10D7",'1'&x"10D8",'1'&x"10D9",'1'&x"10DA",'1'&x"10DB",'1'&x"10DC",'1'&x"10DD",'1'&x"10DE",'1'&x"10DF",
+--'1'&x"10E0",'1'&x"10E1",'1'&x"10E2",'1'&x"10E3",'1'&x"10E4",'1'&x"10E5",'1'&x"10E6",'1'&x"10E7",'1'&x"10E8",'1'&x"10E9",'1'&x"10EA",'1'&x"10EB",'1'&x"10EC",'1'&x"10ED",'1'&x"10EE",'1'&x"10EF",
+--'1'&x"10F0",'1'&x"10F1",'1'&x"10F2",'1'&x"10F3",'1'&x"10F4",'1'&x"10F5",'1'&x"10F6",'1'&x"10F7",'1'&x"10F8",'1'&x"10F9",'1'&x"10FA",'1'&x"10FB",'1'&x"10FC",'1'&x"10FD",'1'&x"10FE",'1'&x"10FF",
+--'1'&x"1100",'1'&x"1101",'1'&x"1102",'1'&x"1103",'1'&x"1104",'1'&x"1105",'1'&x"1106",'1'&x"1107",'1'&x"1108",'1'&x"1109",'1'&x"110A",'1'&x"110B",'1'&x"110C",'1'&x"110D",'1'&x"110E",'1'&x"110F",
+--'1'&x"1110",'1'&x"1111",'1'&x"1112",'1'&x"1113",'1'&x"1114",'1'&x"1115",'1'&x"1116",'1'&x"1117",'1'&x"1118",'1'&x"1119",'1'&x"111A",'1'&x"111B",'1'&x"111C",'1'&x"111D",'1'&x"111E",'1'&x"111F",
+--'1'&x"1120",'1'&x"1121",'1'&x"1122",'1'&x"1123",'1'&x"1124",'1'&x"1125",'1'&x"1126",'1'&x"1127",'1'&x"1128",'1'&x"1129",'1'&x"112A",'1'&x"112B",'1'&x"112C",'1'&x"112D",'1'&x"112E",'1'&x"112F",
+--'1'&x"1130",'1'&x"1131",'1'&x"1132",'1'&x"1133",'1'&x"1134",'1'&x"1135",'1'&x"1136",'1'&x"1137",'1'&x"1138",'1'&x"1139",'1'&x"113A",'1'&x"113B",'1'&x"113C",'1'&x"113D",'1'&x"113E",'1'&x"113F",
+--'1'&x"1140",'1'&x"1141",'1'&x"1142",'1'&x"1143",'1'&x"1144",'1'&x"1145",'1'&x"1146",'1'&x"1147",'1'&x"1148",'1'&x"1149",'1'&x"114A",'1'&x"114B",'1'&x"114C",'1'&x"114D",'1'&x"114E",'1'&x"114F",
+--'1'&x"1150",'1'&x"1151",'1'&x"1152",'1'&x"1153",'1'&x"1154",'1'&x"1155",'1'&x"1156",'1'&x"1157",'1'&x"1158",'1'&x"1159",'1'&x"115A",'1'&x"115B",'1'&x"115C",'1'&x"115D",'1'&x"115E",'1'&x"115F",
+--'1'&x"1160",'1'&x"1161",'1'&x"1162",'1'&x"1163",'1'&x"1164",'1'&x"1165",'1'&x"1166",'1'&x"1167",'1'&x"1168",'1'&x"1169",'1'&x"116A",'1'&x"116B",'1'&x"116C",'1'&x"116D",'1'&x"116E",'1'&x"116F",
+--'1'&x"1170",'1'&x"1171",'1'&x"1172",'1'&x"1173",'1'&x"1174",'1'&x"1175",'1'&x"1176",'1'&x"1177",'1'&x"1178",'1'&x"1179",'1'&x"117A",'1'&x"117B",'1'&x"117C",'1'&x"117D",'1'&x"117E",'1'&x"117F",
+--'1'&x"1180",'1'&x"1181",'1'&x"1182",'1'&x"1183",'1'&x"1184",'1'&x"1185",'1'&x"1186",'1'&x"1187",'1'&x"1188",'1'&x"1189",'1'&x"118A",'1'&x"118B",'1'&x"118C",'1'&x"118D",'1'&x"118E",'1'&x"118F",
+--'1'&x"1190",'1'&x"1191",'1'&x"1192",'1'&x"1193",'1'&x"1194",'1'&x"1195",'1'&x"1196",'1'&x"1197",'1'&x"1198",'1'&x"1199",'1'&x"119A",'1'&x"119B",'1'&x"119C",'1'&x"119D",'1'&x"119E",'1'&x"119F",
+--'1'&x"11A0",'1'&x"11A1",'1'&x"11A2",'1'&x"11A3",'1'&x"11A4",'1'&x"11A5",'1'&x"11A6",'1'&x"11A7",'1'&x"11A8",'1'&x"11A9",'1'&x"11AA",'1'&x"11AB",'1'&x"11AC",'1'&x"11AD",'1'&x"11AE",'1'&x"11AF",
+--'1'&x"11B0",'1'&x"11B1",'1'&x"11B2",'1'&x"11B3",'1'&x"11B4",'1'&x"11B5",'1'&x"11B6",'1'&x"11B7",'1'&x"11B8",'1'&x"11B9",'1'&x"11BA",'1'&x"11BB",'1'&x"11BC",'1'&x"11BD",'1'&x"11BE",'1'&x"11BF",
+--'1'&x"11C0",'1'&x"11C1",'1'&x"11C2",'1'&x"11C3",'1'&x"11C4",'1'&x"11C5",'1'&x"11C6",'1'&x"11C7",'1'&x"11C8",'1'&x"11C9",'1'&x"11CA",'1'&x"11CB",'1'&x"11CC",'1'&x"11CD",'1'&x"11CE",'1'&x"11CF",
+--'1'&x"11D0",'1'&x"11D1",'1'&x"11D2",'1'&x"11D3",'1'&x"11D4",'1'&x"11D5",'1'&x"11D6",'1'&x"11D7",'1'&x"11D8",'1'&x"11D9",'1'&x"11DA",'1'&x"11DB",'1'&x"11DC",'1'&x"11DD",'1'&x"11DE",'1'&x"11DF",
+--'1'&x"11E0",'1'&x"11E1",'1'&x"11E2",'1'&x"11E3",'1'&x"11E4",'1'&x"11E5",'1'&x"11E6",'1'&x"11E7",'1'&x"11E8",'1'&x"11E9",'1'&x"11EA",'1'&x"11EB",'1'&x"11EC",'1'&x"11ED",'1'&x"11EE",'1'&x"11EF",
+--'1'&x"11F0",'1'&x"11F1",'1'&x"11F2",'1'&x"11F3",'1'&x"11F4",'1'&x"11F5",'1'&x"11F6",'1'&x"11F7",'1'&x"11F8",'1'&x"11F9",'1'&x"11FA",'1'&x"11FB",'1'&x"11FC",'1'&x"11FD",'1'&x"11FE",'1'&x"11FF",
+--'1'&x"1200",'1'&x"1201",'1'&x"1202",'1'&x"1203",'1'&x"1204",'1'&x"1205",'1'&x"1206",'1'&x"1207",'1'&x"1208",'1'&x"1209",'1'&x"120A",'1'&x"120B",'1'&x"120C",'1'&x"120D",'1'&x"120E",'1'&x"120F",
+--'1'&x"1210",'1'&x"1211",'1'&x"1212",'1'&x"1213",'1'&x"1214",'1'&x"1215",'1'&x"1216",'1'&x"1217",'1'&x"1218",'1'&x"1219",'1'&x"121A",'1'&x"121B",'1'&x"121C",'1'&x"121D",'1'&x"121E",'1'&x"121F",
+--'1'&x"1220",'1'&x"1221",'1'&x"1222",'1'&x"1223",'1'&x"1224",'1'&x"1225",'1'&x"1226",'1'&x"1227",'1'&x"1228",'1'&x"1229",'1'&x"122A",'1'&x"122B",'1'&x"122C",'1'&x"122D",'1'&x"122E",'1'&x"122F",
+--'1'&x"1230",'1'&x"1231",'1'&x"1232",'1'&x"1233",'1'&x"1234",'1'&x"1235",'1'&x"1236",'1'&x"1237",'1'&x"1238",'1'&x"1239",'1'&x"123A",'1'&x"123B",'1'&x"123C",'1'&x"123D",'1'&x"123E",'1'&x"123F",
+--'1'&x"1240",'1'&x"1241",'1'&x"1242",'1'&x"1243",'1'&x"1244",'1'&x"1245",'1'&x"1246",'1'&x"1247",'1'&x"1248",'1'&x"1249",'1'&x"124A",'1'&x"124B",'1'&x"124C",'1'&x"124D",'1'&x"124E",'1'&x"124F",
+--'1'&x"1250",'1'&x"1251",'1'&x"1252",'1'&x"1253",'1'&x"1254",'1'&x"1255",'1'&x"1256",'1'&x"1257",'1'&x"1258",'1'&x"1259",'1'&x"125A",'1'&x"125B",'1'&x"125C",'1'&x"125D",'1'&x"125E",'1'&x"125F",
+--'1'&x"1260",'1'&x"1261",'1'&x"1262",'1'&x"1263",'1'&x"1264",'1'&x"1265",'1'&x"1266",'1'&x"1267",'1'&x"1268",'1'&x"1269",'1'&x"126A",'1'&x"126B",'1'&x"126C",'1'&x"126D",'1'&x"126E",'1'&x"126F",
+--'1'&x"1270",'1'&x"1271",'1'&x"1272",'1'&x"1273",'1'&x"1274",'1'&x"1275",'1'&x"1276",'1'&x"1277",'1'&x"1278",'1'&x"1279",'1'&x"127A",'1'&x"127B",'1'&x"127C",'1'&x"127D",'1'&x"127E",'1'&x"127F",
+--'1'&x"1280",'1'&x"1281",'1'&x"1282",'1'&x"1283",'1'&x"1284",'1'&x"1285",'1'&x"1286",'1'&x"1287",'1'&x"1288",'1'&x"1289",'1'&x"128A",'1'&x"128B",'1'&x"128C",'1'&x"128D",'1'&x"128E",'1'&x"128F",
+--'1'&x"1290",'1'&x"1291",'1'&x"1292",'1'&x"1293",'1'&x"1294",'1'&x"1295",'1'&x"1296",'1'&x"1297",'1'&x"1298",'1'&x"1299",'1'&x"129A",'1'&x"129B",'1'&x"129C",'1'&x"129D",'1'&x"129E",'1'&x"129F",
+--'1'&x"12A0",'1'&x"12A1",'1'&x"12A2",'1'&x"12A3",'1'&x"12A4",'1'&x"12A5",'1'&x"12A6",'1'&x"12A7",'1'&x"12A8",'1'&x"12A9",'1'&x"12AA",'1'&x"12AB",'1'&x"12AC",'1'&x"12AD",'1'&x"12AE",'1'&x"12AF",
+--'1'&x"12B0",'1'&x"12B1",'1'&x"12B2",'1'&x"12B3",'1'&x"12B4",'1'&x"12B5",'1'&x"12B6",'1'&x"12B7",'1'&x"12B8",'1'&x"12B9",'1'&x"12BA",'1'&x"12BB",'1'&x"12BC",'1'&x"12BD",'1'&x"12BE",'1'&x"12BF",
+--'1'&x"12C0",'1'&x"12C1",'1'&x"12C2",'1'&x"12C3",'1'&x"12C4",'1'&x"12C5",'1'&x"12C6",'1'&x"12C7",'1'&x"12C8",'1'&x"12C9",'1'&x"12CA",'1'&x"12CB",'1'&x"12CC",'1'&x"12CD",'1'&x"12CE",'1'&x"12CF",
+--'1'&x"12D0",'1'&x"12D1",'1'&x"12D2",'1'&x"12D3",'1'&x"12D4",'1'&x"12D5",'1'&x"12D6",'1'&x"12D7",'1'&x"12D8",'1'&x"12D9",'1'&x"12DA",'1'&x"12DB",'1'&x"12DC",'1'&x"12DD",'1'&x"12DE",'1'&x"12DF",
+--'1'&x"12E0",'1'&x"12E1",'1'&x"12E2",'1'&x"12E3",'1'&x"12E4",'1'&x"12E5",'1'&x"12E6",'1'&x"12E7",'1'&x"12E8",'1'&x"12E9",'1'&x"12EA",'1'&x"12EB",'1'&x"12EC",'1'&x"12ED",'1'&x"12EE",'1'&x"12EF",
+--'1'&x"12F0",'1'&x"12F1",'1'&x"12F2",'1'&x"12F3",'1'&x"12F4",'1'&x"12F5",'1'&x"12F6",'1'&x"12F7",'1'&x"12F8",'1'&x"12F9",'1'&x"12FA",'1'&x"12FB",'1'&x"12FC",'1'&x"12FD",'1'&x"12FE",'1'&x"12FF",
+--'1'&x"1300",'1'&x"1301",'1'&x"1302",'1'&x"1303",'1'&x"1304",'1'&x"1305",'1'&x"1306",'1'&x"1307",'1'&x"1308",'1'&x"1309",'1'&x"130A",'1'&x"130B",'1'&x"130C",'1'&x"130D",'1'&x"130E",'1'&x"130F",
+--'1'&x"1310",'1'&x"1311",'1'&x"1312",'1'&x"1313",'1'&x"1314",'1'&x"1315",'1'&x"1316",'1'&x"1317",'1'&x"1318",'1'&x"1319",'1'&x"131A",'1'&x"131B",'1'&x"131C",'1'&x"131D",'1'&x"131E",'1'&x"131F",
+--'1'&x"1320",'1'&x"1321",'1'&x"1322",'1'&x"1323",'1'&x"1324",'1'&x"1325",'1'&x"1326",'1'&x"1327",'1'&x"1328",'1'&x"1329",'1'&x"132A",'1'&x"132B",'1'&x"132C",'1'&x"132D",'1'&x"132E",'1'&x"132F",
+--'1'&x"1330",'1'&x"1331",'1'&x"1332",'1'&x"1333",'1'&x"1334",'1'&x"1335",'1'&x"1336",'1'&x"1337",'1'&x"1338",'1'&x"1339",'1'&x"133A",'1'&x"133B",'1'&x"133C",'1'&x"133D",'1'&x"133E",'1'&x"133F",
+--'1'&x"1340",'1'&x"1341",'1'&x"1342",'1'&x"1343",'1'&x"1344",'1'&x"1345",'1'&x"1346",'1'&x"1347",'1'&x"1348",'1'&x"1349",'1'&x"134A",'1'&x"134B",'1'&x"134C",'1'&x"134D",'1'&x"134E",'1'&x"134F",
+--'1'&x"1350",'1'&x"1351",'1'&x"1352",'1'&x"1353",'1'&x"1354",'1'&x"1355",'1'&x"1356",'1'&x"1357",'1'&x"1358",'1'&x"1359",'1'&x"135A",'1'&x"135B",'1'&x"135C",'1'&x"135D",'1'&x"135E",'1'&x"135F",
+--'1'&x"1360",'1'&x"1361",'1'&x"1362",'1'&x"1363",'1'&x"1364",'1'&x"1365",'1'&x"1366",'1'&x"1367",'1'&x"1368",'1'&x"1369",'1'&x"136A",'1'&x"136B",'1'&x"136C",'1'&x"136D",'1'&x"136E",'1'&x"136F",
+--'1'&x"1370",'1'&x"1371",'1'&x"1372",'1'&x"1373",'1'&x"1374",'1'&x"1375",'1'&x"1376",'1'&x"1377",'1'&x"1378",'1'&x"1379",'1'&x"137A",'1'&x"137B",'1'&x"137C",'1'&x"137D",'1'&x"137E",'1'&x"137F",
+--'1'&x"1380",'1'&x"1381",'1'&x"1382",'1'&x"1383",'1'&x"1384",'1'&x"1385",'1'&x"1386",'1'&x"1387",'1'&x"1388",'1'&x"1389",'1'&x"138A",'1'&x"138B",'1'&x"138C",'1'&x"138D",'1'&x"138E",'1'&x"138F",
+--'1'&x"1390",'1'&x"1391",'1'&x"1392",'1'&x"1393",'1'&x"1394",'1'&x"1395",'1'&x"1396",'1'&x"1397",'1'&x"1398",'1'&x"1399",'1'&x"139A",'1'&x"139B",'1'&x"139C",'1'&x"139D",'1'&x"139E",'1'&x"139F",
+--'1'&x"13A0",'1'&x"13A1",'1'&x"13A2",'1'&x"13A3",'1'&x"13A4",'1'&x"13A5",'1'&x"13A6",'1'&x"13A7",'1'&x"13A8",'1'&x"13A9",'1'&x"13AA",'1'&x"13AB",'1'&x"13AC",'1'&x"13AD",'1'&x"13AE",'1'&x"13AF",
+--'1'&x"13B0",'1'&x"13B1",'1'&x"13B2",'1'&x"13B3",'1'&x"13B4",'1'&x"13B5",'1'&x"13B6",'1'&x"13B7",'1'&x"13B8",'1'&x"13B9",'1'&x"13BA",'1'&x"13BB",'1'&x"13BC",'1'&x"13BD",'1'&x"13BE",'1'&x"13BF",
+--'1'&x"13C0",'1'&x"13C1",'1'&x"13C2",'1'&x"13C3",'1'&x"13C4",'1'&x"13C5",'1'&x"13C6",'1'&x"13C7",'1'&x"13C8",'1'&x"13C9",'1'&x"13CA",'1'&x"13CB",'1'&x"13CC",'1'&x"13CD",'1'&x"13CE",'1'&x"13CF",
+--'1'&x"13D0",'1'&x"13D1",'1'&x"13D2",'1'&x"13D3",'1'&x"13D4",'1'&x"13D5",'1'&x"13D6",'1'&x"13D7",'1'&x"13D8",'1'&x"13D9",'1'&x"13DA",'1'&x"13DB",'1'&x"13DC",'1'&x"13DD",'1'&x"13DE",'1'&x"13DF",
+--'1'&x"13E0",'1'&x"13E1",'1'&x"13E2",'1'&x"13E3",'1'&x"13E4",'1'&x"13E5",'1'&x"13E6",'1'&x"13E7",'1'&x"13E8",'1'&x"13E9",'1'&x"13EA",'1'&x"13EB",'1'&x"13EC",'1'&x"13ED",'1'&x"13EE",'1'&x"13EF",
+--'1'&x"13F0",'1'&x"13F1",'1'&x"13F2",'1'&x"13F3",'1'&x"13F4",'1'&x"13F5",'1'&x"13F6",'1'&x"13F7",'1'&x"13F8",'1'&x"13F9",'1'&x"13FA",'1'&x"13FB",'1'&x"13FC",'1'&x"13FD",'1'&x"13FE",'1'&x"13FF",
+--'1'&x"1400",'1'&x"1401",'1'&x"1402",'1'&x"1403",'1'&x"1404",'1'&x"1405",'1'&x"1406",'1'&x"1407",'1'&x"1408",'1'&x"1409",'1'&x"140A",'1'&x"140B",'1'&x"140C",'1'&x"140D",'1'&x"140E",'1'&x"140F",
+--'1'&x"1410",'1'&x"1411",'1'&x"1412",'1'&x"1413",'1'&x"1414",'1'&x"1415",'1'&x"1416",'1'&x"1417",'1'&x"1418",'1'&x"1419",'1'&x"141A",'1'&x"141B",'1'&x"141C",'1'&x"141D",'1'&x"141E",'1'&x"141F",
+--'1'&x"1420",'1'&x"1421",'1'&x"1422",'1'&x"1423",'1'&x"1424",'1'&x"1425",'1'&x"1426",'1'&x"1427",'1'&x"1428",'1'&x"1429",'1'&x"142A",'1'&x"142B",'1'&x"142C",'1'&x"142D",'1'&x"142E",'1'&x"142F",
+--'1'&x"1430",'1'&x"1431",'1'&x"1432",'1'&x"1433",'1'&x"1434",'1'&x"1435",'1'&x"1436",'1'&x"1437",'1'&x"1438",'1'&x"1439",'1'&x"143A",'1'&x"143B",'1'&x"143C",'1'&x"143D",'1'&x"143E",'1'&x"143F",
+--'1'&x"1440",'1'&x"1441",'1'&x"1442",'1'&x"1443",'1'&x"1444",'1'&x"1445",'1'&x"1446",'1'&x"1447",'1'&x"1448",'1'&x"1449",'1'&x"144A",'1'&x"144B",'1'&x"144C",'1'&x"144D",'1'&x"144E",'1'&x"144F",
+--'1'&x"1450",'1'&x"1451",'1'&x"1452",'1'&x"1453",'1'&x"1454",'1'&x"1455",'1'&x"1456",'1'&x"1457",'1'&x"1458",'1'&x"1459",'1'&x"145A",'1'&x"145B",'1'&x"145C",'1'&x"145D",'1'&x"145E",'1'&x"145F",
+--'1'&x"1460",'1'&x"1461",'1'&x"1462",'1'&x"1463",'1'&x"1464",'1'&x"1465",'1'&x"1466",'1'&x"1467",'1'&x"1468",'1'&x"1469",'1'&x"146A",'1'&x"146B",'1'&x"146C",'1'&x"146D",'1'&x"146E",'1'&x"146F",
+--'1'&x"1470",'1'&x"1471",'1'&x"1472",'1'&x"1473",'1'&x"1474",'1'&x"1475",'1'&x"1476",'1'&x"1477",'1'&x"1478",'1'&x"1479",'1'&x"147A",'1'&x"147B",'1'&x"147C",'1'&x"147D",'1'&x"147E",'1'&x"147F",
+--'1'&x"1480",'1'&x"1481",'1'&x"1482",'1'&x"1483",'1'&x"1484",'1'&x"1485",'1'&x"1486",'1'&x"1487",'1'&x"1488",'1'&x"1489",'1'&x"148A",'1'&x"148B",'1'&x"148C",'1'&x"148D",'1'&x"148E",'1'&x"148F",
+--'1'&x"1490",'1'&x"1491",'1'&x"1492",'1'&x"1493",'1'&x"1494",'1'&x"1495",'1'&x"1496",'1'&x"1497",'1'&x"1498",'1'&x"1499",'1'&x"149A",'1'&x"149B",'1'&x"149C",'1'&x"149D",'1'&x"149E",'1'&x"149F",
+--'1'&x"14A0",'1'&x"14A1",'1'&x"14A2",'1'&x"14A3",'1'&x"14A4",'1'&x"14A5",'1'&x"14A6",'1'&x"14A7",'1'&x"14A8",'1'&x"14A9",'1'&x"14AA",'1'&x"14AB",'1'&x"14AC",'1'&x"14AD",'1'&x"14AE",'1'&x"14AF",
+--'1'&x"14B0",'1'&x"14B1",'1'&x"14B2",'1'&x"14B3",'1'&x"14B4",'1'&x"14B5",'1'&x"14B6",'1'&x"14B7",'1'&x"14B8",'1'&x"14B9",'1'&x"14BA",'1'&x"14BB",'1'&x"14BC",'1'&x"14BD",'1'&x"14BE",'1'&x"14BF",
+--'1'&x"14C0",'1'&x"14C1",'1'&x"14C2",'1'&x"14C3",'1'&x"14C4",'1'&x"14C5",'1'&x"14C6",'1'&x"14C7",'1'&x"14C8",'1'&x"14C9",'1'&x"14CA",'1'&x"14CB",'1'&x"14CC",'1'&x"14CD",'1'&x"14CE",'1'&x"14CF",
+--'1'&x"14D0",'1'&x"14D1",'1'&x"14D2",'1'&x"14D3",'1'&x"14D4",'1'&x"14D5",'1'&x"14D6",'1'&x"14D7",'1'&x"14D8",'1'&x"14D9",'1'&x"14DA",'1'&x"14DB",'1'&x"14DC",'1'&x"14DD",'1'&x"14DE",'1'&x"14DF",
+--'1'&x"14E0",'1'&x"14E1",'1'&x"14E2",'1'&x"14E3",'1'&x"14E4",'1'&x"14E5",'1'&x"14E6",'1'&x"14E7",'1'&x"14E8",'1'&x"14E9",'1'&x"14EA",'1'&x"14EB",'1'&x"14EC",'1'&x"14ED",'1'&x"14EE",'1'&x"14EF",
+--'1'&x"14F0",'1'&x"14F1",'1'&x"14F2",'1'&x"14F3",'1'&x"14F4",'1'&x"14F5",'1'&x"14F6",'1'&x"14F7",'1'&x"14F8",'1'&x"14F9",'1'&x"14FA",'1'&x"14FB",'1'&x"14FC",'1'&x"14FD",'1'&x"14FE",'1'&x"14FF",
+--'1'&x"1500",'1'&x"1501",'1'&x"1502",'1'&x"1503",'1'&x"1504",'1'&x"1505",'1'&x"1506",'1'&x"1507",'1'&x"1508",'1'&x"1509",'1'&x"150A",'1'&x"150B",'1'&x"150C",'1'&x"150D",'1'&x"150E",'1'&x"150F",
+--'1'&x"1510",'1'&x"1511",'1'&x"1512",'1'&x"1513",'1'&x"1514",'1'&x"1515",'1'&x"1516",'1'&x"1517",'1'&x"1518",'1'&x"1519",'1'&x"151A",'1'&x"151B",'1'&x"151C",'1'&x"151D",'1'&x"151E",'1'&x"151F",
+--'1'&x"1520",'1'&x"1521",'1'&x"1522",'1'&x"1523",'1'&x"1524",'1'&x"1525",'1'&x"1526",'1'&x"1527",'1'&x"1528",'1'&x"1529",'1'&x"152A",'1'&x"152B",'1'&x"152C",'1'&x"152D",'1'&x"152E",'1'&x"152F",
+--'1'&x"1530",'1'&x"1531",'1'&x"1532",'1'&x"1533",'1'&x"1534",'1'&x"1535",'1'&x"1536",'1'&x"1537",'1'&x"1538",'1'&x"1539",'1'&x"153A",'1'&x"153B",'1'&x"153C",'1'&x"153D",'1'&x"153E",'1'&x"153F",
+--'1'&x"1540",'1'&x"1541",'1'&x"1542",'1'&x"1543",'1'&x"1544",'1'&x"1545",'1'&x"1546",'1'&x"1547",'1'&x"1548",'1'&x"1549",'1'&x"154A",'1'&x"154B",'1'&x"154C",'1'&x"154D",'1'&x"154E",'1'&x"154F",
+--'1'&x"1550",'1'&x"1551",'1'&x"1552",'1'&x"1553",'1'&x"1554",'1'&x"1555",'1'&x"1556",'1'&x"1557",'1'&x"1558",'1'&x"1559",'1'&x"155A",'1'&x"155B",'1'&x"155C",'1'&x"155D",'1'&x"155E",'1'&x"155F",
+--'1'&x"1560",'1'&x"1561",'1'&x"1562",'1'&x"1563",'1'&x"1564",'1'&x"1565",'1'&x"1566",'1'&x"1567",'1'&x"1568",'1'&x"1569",'1'&x"156A",'1'&x"156B",'1'&x"156C",'1'&x"156D",'1'&x"156E",'1'&x"156F",
+--'1'&x"1570",'1'&x"1571",'1'&x"1572",'1'&x"1573",'1'&x"1574",'1'&x"1575",'1'&x"1576",'1'&x"1577",'1'&x"1578",'1'&x"1579",'1'&x"157A",'1'&x"157B",'1'&x"157C",'1'&x"157D",'1'&x"157E",'1'&x"157F",
+--'1'&x"1580",'1'&x"1581",'1'&x"1582",'1'&x"1583",'1'&x"1584",'1'&x"1585",'1'&x"1586",'1'&x"1587",'1'&x"1588",'1'&x"1589",'1'&x"158A",'1'&x"158B",'1'&x"158C",'1'&x"158D",'1'&x"158E",'1'&x"158F",
+--'1'&x"1590",'1'&x"1591",'1'&x"1592",'1'&x"1593",'1'&x"1594",'1'&x"1595",'1'&x"1596",'1'&x"1597",'1'&x"1598",'1'&x"1599",'1'&x"159A",'1'&x"159B",'1'&x"159C",'1'&x"159D",'1'&x"159E",'1'&x"159F",
+--'1'&x"15A0",'1'&x"15A1",'1'&x"15A2",'1'&x"15A3",'1'&x"15A4",'1'&x"15A5",'1'&x"15A6",'1'&x"15A7",'1'&x"15A8",'1'&x"15A9",'1'&x"15AA",'1'&x"15AB",'1'&x"15AC",'1'&x"15AD",'1'&x"15AE",'1'&x"15AF",
+--'1'&x"15B0",'1'&x"15B1",'1'&x"15B2",'1'&x"15B3",'1'&x"15B4",'1'&x"15B5",'1'&x"15B6",'1'&x"15B7",'1'&x"15B8",'1'&x"15B9",'1'&x"15BA",'1'&x"15BB",'1'&x"15BC",'1'&x"15BD",'1'&x"15BE",'1'&x"15BF",
+--'1'&x"15C0",'1'&x"15C1",'1'&x"15C2",'1'&x"15C3",'1'&x"15C4",'1'&x"15C5",'1'&x"15C6",'1'&x"15C7",'1'&x"15C8",'1'&x"15C9",'1'&x"15CA",'1'&x"15CB",'1'&x"15CC",'1'&x"15CD",'1'&x"15CE",'1'&x"15CF",
+--'1'&x"15D0",'1'&x"15D1",'1'&x"15D2",'1'&x"15D3",'1'&x"15D4",'1'&x"15D5",'1'&x"15D6",'1'&x"15D7",'1'&x"15D8",'1'&x"15D9",'1'&x"15DA",'1'&x"15DB",'1'&x"15DC",'1'&x"15DD",'1'&x"15DE",'1'&x"15DF",
+--'1'&x"15E0",'1'&x"15E1",'1'&x"15E2",'1'&x"15E3",'1'&x"15E4",'1'&x"15E5",'1'&x"15E6",'1'&x"15E7",'1'&x"15E8",'1'&x"15E9",'1'&x"15EA",'1'&x"15EB",'1'&x"15EC",'1'&x"15ED",'1'&x"15EE",'1'&x"15EF",
+--'1'&x"15F0",'1'&x"15F1",'1'&x"15F2",'1'&x"15F3",'1'&x"15F4",'1'&x"15F5",'1'&x"15F6",'1'&x"15F7",'1'&x"15F8",'1'&x"15F9",'1'&x"15FA",'1'&x"15FB",'1'&x"15FC",'1'&x"15FD",'1'&x"15FE",'1'&x"15FF",
+--'1'&x"1600",'1'&x"1601",'1'&x"1602",'1'&x"1603",'1'&x"1604",'1'&x"1605",'1'&x"1606",'1'&x"1607",'1'&x"1608",'1'&x"1609",'1'&x"160A",'1'&x"160B",'1'&x"160C",'1'&x"160D",'1'&x"160E",'1'&x"160F",
+--'1'&x"1610",'1'&x"1611",'1'&x"1612",'1'&x"1613",'1'&x"1614",'1'&x"1615",'1'&x"1616",'1'&x"1617",'1'&x"1618",'1'&x"1619",'1'&x"161A",'1'&x"161B",'1'&x"161C",'1'&x"161D",'1'&x"161E",'1'&x"161F",
+--'1'&x"1620",'1'&x"1621",'1'&x"1622",'1'&x"1623",'1'&x"1624",'1'&x"1625",'1'&x"1626",'1'&x"1627",'1'&x"1628",'1'&x"1629",'1'&x"162A",'1'&x"162B",'1'&x"162C",'1'&x"162D",'1'&x"162E",'1'&x"162F",
+--'1'&x"1630",'1'&x"1631",'1'&x"1632",'1'&x"1633",'1'&x"1634",'1'&x"1635",'1'&x"1636",'1'&x"1637",'1'&x"1638",'1'&x"1639",'1'&x"163A",'1'&x"163B",'1'&x"163C",'1'&x"163D",'1'&x"163E",'1'&x"163F",
+--'1'&x"1640",'1'&x"1641",'1'&x"1642",'1'&x"1643",'1'&x"1644",'1'&x"1645",'1'&x"1646",'1'&x"1647",'1'&x"1648",'1'&x"1649",'1'&x"164A",'1'&x"164B",'1'&x"164C",'1'&x"164D",'1'&x"164E",'1'&x"164F",
+--'1'&x"1650",'1'&x"1651",'1'&x"1652",'1'&x"1653",'1'&x"1654",'1'&x"1655",'1'&x"1656",'1'&x"1657",'1'&x"1658",'1'&x"1659",'1'&x"165A",'1'&x"165B",'1'&x"165C",'1'&x"165D",'1'&x"165E",'1'&x"165F",
+--'1'&x"1660",'1'&x"1661",'1'&x"1662",'1'&x"1663",'1'&x"1664",'1'&x"1665",'1'&x"1666",'1'&x"1667",'1'&x"1668",'1'&x"1669",'1'&x"166A",'1'&x"166B",'1'&x"166C",'1'&x"166D",'1'&x"166E",'1'&x"166F",
+--'1'&x"1670",'1'&x"1671",'1'&x"1672",'1'&x"1673",'1'&x"1674",'1'&x"1675",'1'&x"1676",'1'&x"1677",'1'&x"1678",'1'&x"1679",'1'&x"167A",'1'&x"167B",'1'&x"167C",'1'&x"167D",'1'&x"167E",'1'&x"167F",
+--'1'&x"1680",'1'&x"1681",'1'&x"1682",'1'&x"1683",'1'&x"1684",'1'&x"1685",'1'&x"1686",'1'&x"1687",'1'&x"1688",'1'&x"1689",'1'&x"168A",'1'&x"168B",'1'&x"168C",'1'&x"168D",'1'&x"168E",'1'&x"168F",
+--'1'&x"1690",'1'&x"1691",'1'&x"1692",'1'&x"1693",'1'&x"1694",'1'&x"1695",'1'&x"1696",'1'&x"1697",'1'&x"1698",'1'&x"1699",'1'&x"169A",'1'&x"169B",'1'&x"169C",'1'&x"169D",'1'&x"169E",'1'&x"169F",
+--'1'&x"16A0",'1'&x"16A1",'1'&x"16A2",'1'&x"16A3",'1'&x"16A4",'1'&x"16A5",'1'&x"16A6",'1'&x"16A7",'1'&x"16A8",'1'&x"16A9",'1'&x"16AA",'1'&x"16AB",'1'&x"16AC",'1'&x"16AD",'1'&x"16AE",'1'&x"16AF",
+--'1'&x"16B0",'1'&x"16B1",'1'&x"16B2",'1'&x"16B3",'1'&x"16B4",'1'&x"16B5",'1'&x"16B6",'1'&x"16B7",'1'&x"16B8",'1'&x"16B9",'1'&x"16BA",'1'&x"16BB",'1'&x"16BC",'1'&x"16BD",'1'&x"16BE",'1'&x"16BF",
+--'1'&x"16C0",'1'&x"16C1",'1'&x"16C2",'1'&x"16C3",'1'&x"16C4",'1'&x"16C5",'1'&x"16C6",'1'&x"16C7",'1'&x"16C8",'1'&x"16C9",'1'&x"16CA",'1'&x"16CB",'1'&x"16CC",'1'&x"16CD",'1'&x"16CE",'1'&x"16CF",
+--'1'&x"16D0",'1'&x"16D1",'1'&x"16D2",'1'&x"16D3",'1'&x"16D4",'1'&x"16D5",'1'&x"16D6",'1'&x"16D7",'1'&x"16D8",'1'&x"16D9",'1'&x"16DA",'1'&x"16DB",'1'&x"16DC",'1'&x"16DD",'1'&x"16DE",'1'&x"16DF",
+--'1'&x"16E0",'1'&x"16E1",'1'&x"16E2",'1'&x"16E3",'1'&x"16E4",'1'&x"16E5",'1'&x"16E6",'1'&x"16E7",'1'&x"16E8",'1'&x"16E9",'1'&x"16EA",'1'&x"16EB",'1'&x"16EC",'1'&x"16ED",'1'&x"16EE",'1'&x"16EF",
+--'1'&x"16F0",'1'&x"16F1",'1'&x"16F2",'1'&x"16F3",'1'&x"16F4",'1'&x"16F5",'1'&x"16F6",'1'&x"16F7",'1'&x"16F8",'1'&x"16F9",'1'&x"16FA",'1'&x"16FB",'1'&x"16FC",'1'&x"16FD",'1'&x"16FE",'1'&x"16FF",
+--'1'&x"1700",'1'&x"1701",'1'&x"1702",'1'&x"1703",'1'&x"1704",'1'&x"1705",'1'&x"1706",'1'&x"1707",'1'&x"1708",'1'&x"1709",'1'&x"170A",'1'&x"170B",'1'&x"170C",'1'&x"170D",'1'&x"170E",'1'&x"170F",
+--'1'&x"1710",'1'&x"1711",'1'&x"1712",'1'&x"1713",'1'&x"1714",'1'&x"1715",'1'&x"1716",'1'&x"1717",'1'&x"1718",'1'&x"1719",'1'&x"171A",'1'&x"171B",'1'&x"171C",'1'&x"171D",'1'&x"171E",'1'&x"171F",
+--'1'&x"1720",'1'&x"1721",'1'&x"1722",'1'&x"1723",'1'&x"1724",'1'&x"1725",'1'&x"1726",'1'&x"1727",'1'&x"1728",'1'&x"1729",'1'&x"172A",'1'&x"172B",'1'&x"172C",'1'&x"172D",'1'&x"172E",'1'&x"172F",
+--'1'&x"1730",'1'&x"1731",'1'&x"1732",'1'&x"1733",'1'&x"1734",'1'&x"1735",'1'&x"1736",'1'&x"1737",'1'&x"1738",'1'&x"1739",'1'&x"173A",'1'&x"173B",'1'&x"173C",'1'&x"173D",'1'&x"173E",'1'&x"173F",
+--'1'&x"1740",'1'&x"1741",'1'&x"1742",'1'&x"1743",'1'&x"1744",'1'&x"1745",'1'&x"1746",'1'&x"1747",'1'&x"1748",'1'&x"1749",'1'&x"174A",'1'&x"174B",'1'&x"174C",'1'&x"174D",'1'&x"174E",'1'&x"174F",
+--'1'&x"1750",'1'&x"1751",'1'&x"1752",'1'&x"1753",'1'&x"1754",'1'&x"1755",'1'&x"1756",'1'&x"1757",'1'&x"1758",'1'&x"1759",'1'&x"175A",'1'&x"175B",'1'&x"175C",'1'&x"175D",'1'&x"175E",'1'&x"175F",
+--'1'&x"1760",'1'&x"1761",'1'&x"1762",'1'&x"1763",'1'&x"1764",'1'&x"1765",'1'&x"1766",'1'&x"1767",'1'&x"1768",'1'&x"1769",'1'&x"176A",'1'&x"176B",'1'&x"176C",'1'&x"176D",'1'&x"176E",'1'&x"176F",
+--'1'&x"1770",'1'&x"1771",'1'&x"1772",'1'&x"1773",'1'&x"1774",'1'&x"1775",'1'&x"1776",'1'&x"1777",'1'&x"1778",'1'&x"1779",'1'&x"177A",'1'&x"177B",'1'&x"177C",'1'&x"177D",'1'&x"177E",'1'&x"177F",
+--'1'&x"1780",'1'&x"1781",'1'&x"1782",'1'&x"1783",'1'&x"1784",'1'&x"1785",'1'&x"1786",'1'&x"1787",'1'&x"1788",'1'&x"1789",'1'&x"178A",'1'&x"178B",'1'&x"178C",'1'&x"178D",'1'&x"178E",'1'&x"178F",
+--'1'&x"1790",'1'&x"1791",'1'&x"1792",'1'&x"1793",'1'&x"1794",'1'&x"1795",'1'&x"1796",'1'&x"1797",'1'&x"1798",'1'&x"1799",'1'&x"179A",'1'&x"179B",'1'&x"179C",'1'&x"179D",'1'&x"179E",'1'&x"179F",
+--'1'&x"17A0",'1'&x"17A1",'1'&x"17A2",'1'&x"17A3",'1'&x"17A4",'1'&x"17A5",'1'&x"17A6",'1'&x"17A7",'1'&x"17A8",'1'&x"17A9",'1'&x"17AA",'1'&x"17AB",'1'&x"17AC",'1'&x"17AD",'1'&x"17AE",'1'&x"17AF",
+--'1'&x"17B0",'1'&x"17B1",'1'&x"17B2",'1'&x"17B3",'1'&x"17B4",'1'&x"17B5",'1'&x"17B6",'1'&x"17B7",'1'&x"17B8",'1'&x"17B9",'1'&x"17BA",'1'&x"17BB",'1'&x"17BC",'1'&x"17BD",'1'&x"17BE",'1'&x"17BF",
+--'1'&x"17C0",'1'&x"17C1",'1'&x"17C2",'1'&x"17C3",'1'&x"17C4",'1'&x"17C5",'1'&x"17C6",'1'&x"17C7",'1'&x"17C8",'1'&x"17C9",'1'&x"17CA",'1'&x"17CB",'1'&x"17CC",'1'&x"17CD",'1'&x"17CE",'1'&x"17CF",
+--'1'&x"17D0",'1'&x"17D1",'1'&x"17D2",'1'&x"17D3",'1'&x"17D4",'1'&x"17D5",'1'&x"17D6",'1'&x"17D7",'1'&x"17D8",'1'&x"17D9",'1'&x"17DA",'1'&x"17DB",'1'&x"17DC",'1'&x"17DD",'1'&x"17DE",'1'&x"17DF",
+--'1'&x"17E0",'1'&x"17E1",'1'&x"17E2",'1'&x"17E3",'1'&x"17E4",'1'&x"17E5",'1'&x"17E6",'1'&x"17E7",'1'&x"17E8",'1'&x"17E9",'1'&x"17EA",'1'&x"17EB",'1'&x"17EC",'1'&x"17ED",'1'&x"17EE",'1'&x"17EF",
+--'1'&x"17F0",'1'&x"17F1",'1'&x"17F2",'1'&x"17F3",'1'&x"17F4",'1'&x"17F5",'1'&x"17F6",'1'&x"17F7",'1'&x"17F8",'1'&x"17F9",'1'&x"17FA",'1'&x"17FB",'1'&x"17FC",'1'&x"17FD",'1'&x"17FE",'1'&x"17FF",
+--'1'&x"1800",'1'&x"1801",'1'&x"1802",'1'&x"1803",'1'&x"1804",'1'&x"1805",'1'&x"1806",'1'&x"1807",'1'&x"1808",'1'&x"1809",'1'&x"180A",'1'&x"180B",'1'&x"180C",'1'&x"180D",'1'&x"180E",'1'&x"180F",
+--'1'&x"1810",'1'&x"1811",'1'&x"1812",'1'&x"1813",'1'&x"1814",'1'&x"1815",'1'&x"1816",'1'&x"1817",'1'&x"1818",'1'&x"1819",'1'&x"181A",'1'&x"181B",'1'&x"181C",'1'&x"181D",'1'&x"181E",'1'&x"181F",
+--'1'&x"1820",'1'&x"1821",'1'&x"1822",'1'&x"1823",'1'&x"1824",'1'&x"1825",'1'&x"1826",'1'&x"1827",'1'&x"1828",'1'&x"1829",'1'&x"182A",'1'&x"182B",'1'&x"182C",'1'&x"182D",'1'&x"182E",'1'&x"182F",
+--'1'&x"1830",'1'&x"1831",'1'&x"1832",'1'&x"1833",'1'&x"1834",'1'&x"1835",'1'&x"1836",'1'&x"1837",'1'&x"1838",'1'&x"1839",'1'&x"183A",'1'&x"183B",'1'&x"183C",'1'&x"183D",'1'&x"183E",'1'&x"183F",
+--'1'&x"1840",'1'&x"1841",'1'&x"1842",'1'&x"1843",'1'&x"1844",'1'&x"1845",'1'&x"1846",'1'&x"1847",'1'&x"1848",'1'&x"1849",'1'&x"184A",'1'&x"184B",'1'&x"184C",'1'&x"184D",'1'&x"184E",'1'&x"184F",
+--'1'&x"1850",'1'&x"1851",'1'&x"1852",'1'&x"1853",'1'&x"1854",'1'&x"1855",'1'&x"1856",'1'&x"1857",'1'&x"1858",'1'&x"1859",'1'&x"185A",'1'&x"185B",'1'&x"185C",'1'&x"185D",'1'&x"185E",'1'&x"185F",
+--'1'&x"1860",'1'&x"1861",'1'&x"1862",'1'&x"1863",'1'&x"1864",'1'&x"1865",'1'&x"1866",'1'&x"1867",'1'&x"1868",'1'&x"1869",'1'&x"186A",'1'&x"186B",'1'&x"186C",'1'&x"186D",'1'&x"186E",'1'&x"186F",
+--'1'&x"1870",'1'&x"1871",'1'&x"1872",'1'&x"1873",'1'&x"1874",'1'&x"1875",'1'&x"1876",'1'&x"1877",'1'&x"1878",'1'&x"1879",'1'&x"187A",'1'&x"187B",'1'&x"187C",'1'&x"187D",'1'&x"187E",'1'&x"187F",
+--'1'&x"1880",'1'&x"1881",'1'&x"1882",'1'&x"1883",'1'&x"1884",'1'&x"1885",'1'&x"1886",'1'&x"1887",'1'&x"1888",'1'&x"1889",'1'&x"188A",'1'&x"188B",'1'&x"188C",'1'&x"188D",'1'&x"188E",'1'&x"188F",
+--'1'&x"1890",'1'&x"1891",'1'&x"1892",'1'&x"1893",'1'&x"1894",'1'&x"1895",'1'&x"1896",'1'&x"1897",'1'&x"1898",'1'&x"1899",'1'&x"189A",'1'&x"189B",'1'&x"189C",'1'&x"189D",'1'&x"189E",'1'&x"189F",
+--'1'&x"18A0",'1'&x"18A1",'1'&x"18A2",'1'&x"18A3",'1'&x"18A4",'1'&x"18A5",'1'&x"18A6",'1'&x"18A7",'1'&x"18A8",'1'&x"18A9",'1'&x"18AA",'1'&x"18AB",'1'&x"18AC",'1'&x"18AD",'1'&x"18AE",'1'&x"18AF",
+--'1'&x"18B0",'1'&x"18B1",'1'&x"18B2",'1'&x"18B3",'1'&x"18B4",'1'&x"18B5",'1'&x"18B6",'1'&x"18B7",'1'&x"18B8",'1'&x"18B9",'1'&x"18BA",'1'&x"18BB",'1'&x"18BC",'1'&x"18BD",'1'&x"18BE",'1'&x"18BF",
+--'1'&x"18C0",'1'&x"18C1",'1'&x"18C2",'1'&x"18C3",'1'&x"18C4",'1'&x"18C5",'1'&x"18C6",'1'&x"18C7",'1'&x"18C8",'1'&x"18C9",'1'&x"18CA",'1'&x"18CB",'1'&x"18CC",'1'&x"18CD",'1'&x"18CE",'1'&x"18CF",
+--'1'&x"18D0",'1'&x"18D1",'1'&x"18D2",'1'&x"18D3",'1'&x"18D4",'1'&x"18D5",'1'&x"18D6",'1'&x"18D7",'1'&x"18D8",'1'&x"18D9",'1'&x"18DA",'1'&x"18DB",'1'&x"18DC",'1'&x"18DD",'1'&x"18DE",'1'&x"18DF",
+--'1'&x"18E0",'1'&x"18E1",'1'&x"18E2",'1'&x"18E3",'1'&x"18E4",'1'&x"18E5",'1'&x"18E6",'1'&x"18E7",'1'&x"18E8",'1'&x"18E9",'1'&x"18EA",'1'&x"18EB",'1'&x"18EC",'1'&x"18ED",'1'&x"18EE",'1'&x"18EF",
+--'1'&x"18F0",'1'&x"18F1",'1'&x"18F2",'1'&x"18F3",'1'&x"18F4",'1'&x"18F5",'1'&x"18F6",'1'&x"18F7",'1'&x"18F8",'1'&x"18F9",'1'&x"18FA",'1'&x"18FB",'1'&x"18FC",'1'&x"18FD",'1'&x"18FE",'1'&x"18FF",
+--'1'&x"1900",'1'&x"1901",'1'&x"1902",'1'&x"1903",'1'&x"1904",'1'&x"1905",'1'&x"1906",'1'&x"1907",'1'&x"1908",'1'&x"1909",'1'&x"190A",'1'&x"190B",'1'&x"190C",'1'&x"190D",'1'&x"190E",'1'&x"190F",
+--'1'&x"1910",'1'&x"1911",'1'&x"1912",'1'&x"1913",'1'&x"1914",'1'&x"1915",'1'&x"1916",'1'&x"1917",'1'&x"1918",'1'&x"1919",'1'&x"191A",'1'&x"191B",'1'&x"191C",'1'&x"191D",'1'&x"191E",'1'&x"191F",
+--'1'&x"1920",'1'&x"1921",'1'&x"1922",'1'&x"1923",'1'&x"1924",'1'&x"1925",'1'&x"1926",'1'&x"1927",'1'&x"1928",'1'&x"1929",'1'&x"192A",'1'&x"192B",'1'&x"192C",'1'&x"192D",'1'&x"192E",'1'&x"192F",
+--'1'&x"1930",'1'&x"1931",'1'&x"1932",'1'&x"1933",'1'&x"1934",'1'&x"1935",'1'&x"1936",'1'&x"1937",'1'&x"1938",'1'&x"1939",'1'&x"193A",'1'&x"193B",'1'&x"193C",'1'&x"193D",'1'&x"193E",'1'&x"193F",
+--'1'&x"1940",'1'&x"1941",'1'&x"1942",'1'&x"1943",'1'&x"1944",'1'&x"1945",'1'&x"1946",'1'&x"1947",'1'&x"1948",'1'&x"1949",'1'&x"194A",'1'&x"194B",'1'&x"194C",'1'&x"194D",'1'&x"194E",'1'&x"194F",
+--'1'&x"1950",'1'&x"1951",'1'&x"1952",'1'&x"1953",'1'&x"1954",'1'&x"1955",'1'&x"1956",'1'&x"1957",'1'&x"1958",'1'&x"1959",'1'&x"195A",'1'&x"195B",'1'&x"195C",'1'&x"195D",'1'&x"195E",'1'&x"195F",
+--'1'&x"1960",'1'&x"1961",'1'&x"1962",'1'&x"1963",'1'&x"1964",'1'&x"1965",'1'&x"1966",'1'&x"1967",'1'&x"1968",'1'&x"1969",'1'&x"196A",'1'&x"196B",'1'&x"196C",'1'&x"196D",'1'&x"196E",'1'&x"196F",
+--'1'&x"1970",'1'&x"1971",'1'&x"1972",'1'&x"1973",'1'&x"1974",'1'&x"1975",'1'&x"1976",'1'&x"1977",'1'&x"1978",'1'&x"1979",'1'&x"197A",'1'&x"197B",'1'&x"197C",'1'&x"197D",'1'&x"197E",'1'&x"197F",
+--'1'&x"1980",'1'&x"1981",'1'&x"1982",'1'&x"1983",'1'&x"1984",'1'&x"1985",'1'&x"1986",'1'&x"1987",'1'&x"1988",'1'&x"1989",'1'&x"198A",'1'&x"198B",'1'&x"198C",'1'&x"198D",'1'&x"198E",'1'&x"198F",
+--'1'&x"1990",'1'&x"1991",'1'&x"1992",'1'&x"1993",'1'&x"1994",'1'&x"1995",'1'&x"1996",'1'&x"1997",'1'&x"1998",'1'&x"1999",'1'&x"199A",'1'&x"199B",'1'&x"199C",'1'&x"199D",'1'&x"199E",'1'&x"199F",
+--'1'&x"19A0",'1'&x"19A1",'1'&x"19A2",'1'&x"19A3",'1'&x"19A4",'1'&x"19A5",'1'&x"19A6",'1'&x"19A7",'1'&x"19A8",'1'&x"19A9",'1'&x"19AA",'1'&x"19AB",'1'&x"19AC",'1'&x"19AD",'1'&x"19AE",'1'&x"19AF",
+--'1'&x"19B0",'1'&x"19B1",'1'&x"19B2",'1'&x"19B3",'1'&x"19B4",'1'&x"19B5",'1'&x"19B6",'1'&x"19B7",'1'&x"19B8",'1'&x"19B9",'1'&x"19BA",'1'&x"19BB",'1'&x"19BC",'1'&x"19BD",'1'&x"19BE",'1'&x"19BF",
+--'1'&x"19C0",'1'&x"19C1",'1'&x"19C2",'1'&x"19C3",'1'&x"19C4",'1'&x"19C5",'1'&x"19C6",'1'&x"19C7",'1'&x"19C8",'1'&x"19C9",'1'&x"19CA",'1'&x"19CB",'1'&x"19CC",'1'&x"19CD",'1'&x"19CE",'1'&x"19CF",
+--'1'&x"19D0",'1'&x"19D1",'1'&x"19D2",'1'&x"19D3",'1'&x"19D4",'1'&x"19D5",'1'&x"19D6",'1'&x"19D7",'1'&x"19D8",'1'&x"19D9",'1'&x"19DA",'1'&x"19DB",'1'&x"19DC",'1'&x"19DD",'1'&x"19DE",'1'&x"19DF",
+--'1'&x"19E0",'1'&x"19E1",'1'&x"19E2",'1'&x"19E3",'1'&x"19E4",'1'&x"19E5",'1'&x"19E6",'1'&x"19E7",'1'&x"19E8",'1'&x"19E9",'1'&x"19EA",'1'&x"19EB",'1'&x"19EC",'1'&x"19ED",'1'&x"19EE",'1'&x"19EF",
+--'1'&x"19F0",'1'&x"19F1",'1'&x"19F2",'1'&x"19F3",'1'&x"19F4",'1'&x"19F5",'1'&x"19F6",'1'&x"19F7",'1'&x"19F8",'1'&x"19F9",'1'&x"19FA",'1'&x"19FB",'1'&x"19FC",'1'&x"19FD",'1'&x"19FE",'1'&x"19FF",
+--'1'&x"1A00",'1'&x"1A01",'1'&x"1A02",'1'&x"1A03",'1'&x"1A04",'1'&x"1A05",'1'&x"1A06",'1'&x"1A07",'1'&x"1A08",'1'&x"1A09",'1'&x"1A0A",'1'&x"1A0B",'1'&x"1A0C",'1'&x"1A0D",'1'&x"1A0E",'1'&x"1A0F",
+--'1'&x"1A10",'1'&x"1A11",'1'&x"1A12",'1'&x"1A13",'1'&x"1A14",'1'&x"1A15",'1'&x"1A16",'1'&x"1A17",'1'&x"1A18",'1'&x"1A19",'1'&x"1A1A",'1'&x"1A1B",'1'&x"1A1C",'1'&x"1A1D",'1'&x"1A1E",'1'&x"1A1F",
+--'1'&x"1A20",'1'&x"1A21",'1'&x"1A22",'1'&x"1A23",'1'&x"1A24",'1'&x"1A25",'1'&x"1A26",'1'&x"1A27",'1'&x"1A28",'1'&x"1A29",'1'&x"1A2A",'1'&x"1A2B",'1'&x"1A2C",'1'&x"1A2D",'1'&x"1A2E",'1'&x"1A2F",
+--'1'&x"1A30",'1'&x"1A31",'1'&x"1A32",'1'&x"1A33",'1'&x"1A34",'1'&x"1A35",'1'&x"1A36",'1'&x"1A37",'1'&x"1A38",'1'&x"1A39",'1'&x"1A3A",'1'&x"1A3B",'1'&x"1A3C",'1'&x"1A3D",'1'&x"1A3E",'1'&x"1A3F",
+--'1'&x"1A40",'1'&x"1A41",'1'&x"1A42",'1'&x"1A43",'1'&x"1A44",'1'&x"1A45",'1'&x"1A46",'1'&x"1A47",'1'&x"1A48",'1'&x"1A49",'1'&x"1A4A",'1'&x"1A4B",'1'&x"1A4C",'1'&x"1A4D",'1'&x"1A4E",'1'&x"1A4F",
+--'1'&x"1A50",'1'&x"1A51",'1'&x"1A52",'1'&x"1A53",'1'&x"1A54",'1'&x"1A55",'1'&x"1A56",'1'&x"1A57",'1'&x"1A58",'1'&x"1A59",'1'&x"1A5A",'1'&x"1A5B",'1'&x"1A5C",'1'&x"1A5D",'1'&x"1A5E",'1'&x"1A5F",
+--'1'&x"1A60",'1'&x"1A61",'1'&x"1A62",'1'&x"1A63",'1'&x"1A64",'1'&x"1A65",'1'&x"1A66",'1'&x"1A67",'1'&x"1A68",'1'&x"1A69",'1'&x"1A6A",'1'&x"1A6B",'1'&x"1A6C",'1'&x"1A6D",'1'&x"1A6E",'1'&x"1A6F",
+--'1'&x"1A70",'1'&x"1A71",'1'&x"1A72",'1'&x"1A73",'1'&x"1A74",'1'&x"1A75",'1'&x"1A76",'1'&x"1A77",'1'&x"1A78",'1'&x"1A79",'1'&x"1A7A",'1'&x"1A7B",'1'&x"1A7C",'1'&x"1A7D",'1'&x"1A7E",'1'&x"1A7F",
+--'1'&x"1A80",'1'&x"1A81",'1'&x"1A82",'1'&x"1A83",'1'&x"1A84",'1'&x"1A85",'1'&x"1A86",'1'&x"1A87",'1'&x"1A88",'1'&x"1A89",'1'&x"1A8A",'1'&x"1A8B",'1'&x"1A8C",'1'&x"1A8D",'1'&x"1A8E",'1'&x"1A8F",
+--'1'&x"1A90",'1'&x"1A91",'1'&x"1A92",'1'&x"1A93",'1'&x"1A94",'1'&x"1A95",'1'&x"1A96",'1'&x"1A97",'1'&x"1A98",'1'&x"1A99",'1'&x"1A9A",'1'&x"1A9B",'1'&x"1A9C",'1'&x"1A9D",'1'&x"1A9E",'1'&x"1A9F",
+--'1'&x"1AA0",'1'&x"1AA1",'1'&x"1AA2",'1'&x"1AA3",'1'&x"1AA4",'1'&x"1AA5",'1'&x"1AA6",'1'&x"1AA7",'1'&x"1AA8",'1'&x"1AA9",'1'&x"1AAA",'1'&x"1AAB",'1'&x"1AAC",'1'&x"1AAD",'1'&x"1AAE",'1'&x"1AAF",
+--'1'&x"1AB0",'1'&x"1AB1",'1'&x"1AB2",'1'&x"1AB3",'1'&x"1AB4",'1'&x"1AB5",'1'&x"1AB6",'1'&x"1AB7",'1'&x"1AB8",'1'&x"1AB9",'1'&x"1ABA",'1'&x"1ABB",'1'&x"1ABC",'1'&x"1ABD",'1'&x"1ABE",'1'&x"1ABF",
+--'1'&x"1AC0",'1'&x"1AC1",'1'&x"1AC2",'1'&x"1AC3",'1'&x"1AC4",'1'&x"1AC5",'1'&x"1AC6",'1'&x"1AC7",'1'&x"1AC8",'1'&x"1AC9",'1'&x"1ACA",'1'&x"1ACB",'1'&x"1ACC",'1'&x"1ACD",'1'&x"1ACE",'1'&x"1ACF",
+--'1'&x"1AD0",'1'&x"1AD1",'1'&x"1AD2",'1'&x"1AD3",'1'&x"1AD4",'1'&x"1AD5",'1'&x"1AD6",'1'&x"1AD7",'1'&x"1AD8",'1'&x"1AD9",'1'&x"1ADA",'1'&x"1ADB",'1'&x"1ADC",'1'&x"1ADD",'1'&x"1ADE",'1'&x"1ADF",
+--'1'&x"1AE0",'1'&x"1AE1",'1'&x"1AE2",'1'&x"1AE3",'1'&x"1AE4",'1'&x"1AE5",'1'&x"1AE6",'1'&x"1AE7",'1'&x"1AE8",'1'&x"1AE9",'1'&x"1AEA",'1'&x"1AEB",'1'&x"1AEC",'1'&x"1AED",'1'&x"1AEE",'1'&x"1AEF",
+--'1'&x"1AF0",'1'&x"1AF1",'1'&x"1AF2",'1'&x"1AF3",'1'&x"1AF4",'1'&x"1AF5",'1'&x"1AF6",'1'&x"1AF7",'1'&x"1AF8",'1'&x"1AF9",'1'&x"1AFA",'1'&x"1AFB",'1'&x"1AFC",'1'&x"1AFD",'1'&x"1AFE",'1'&x"1AFF",
+--'1'&x"1B00",'1'&x"1B01",'1'&x"1B02",'1'&x"1B03",'1'&x"1B04",'1'&x"1B05",'1'&x"1B06",'1'&x"1B07",'1'&x"1B08",'1'&x"1B09",'1'&x"1B0A",'1'&x"1B0B",'1'&x"1B0C",'1'&x"1B0D",'1'&x"1B0E",'1'&x"1B0F",
+--'1'&x"1B10",'1'&x"1B11",'1'&x"1B12",'1'&x"1B13",'1'&x"1B14",'1'&x"1B15",'1'&x"1B16",'1'&x"1B17",'1'&x"1B18",'1'&x"1B19",'1'&x"1B1A",'1'&x"1B1B",'1'&x"1B1C",'1'&x"1B1D",'1'&x"1B1E",'1'&x"1B1F",
+--'1'&x"1B20",'1'&x"1B21",'1'&x"1B22",'1'&x"1B23",'1'&x"1B24",'1'&x"1B25",'1'&x"1B26",'1'&x"1B27",'1'&x"1B28",'1'&x"1B29",'1'&x"1B2A",'1'&x"1B2B",'1'&x"1B2C",'1'&x"1B2D",'1'&x"1B2E",'1'&x"1B2F",
+--'1'&x"1B30",'1'&x"1B31",'1'&x"1B32",'1'&x"1B33",'1'&x"1B34",'1'&x"1B35",'1'&x"1B36",'1'&x"1B37",'1'&x"1B38",'1'&x"1B39",'1'&x"1B3A",'1'&x"1B3B",'1'&x"1B3C",'1'&x"1B3D",'1'&x"1B3E",'1'&x"1B3F",
+--'1'&x"1B40",'1'&x"1B41",'1'&x"1B42",'1'&x"1B43",'1'&x"1B44",'1'&x"1B45",'1'&x"1B46",'1'&x"1B47",'1'&x"1B48",'1'&x"1B49",'1'&x"1B4A",'1'&x"1B4B",'1'&x"1B4C",'1'&x"1B4D",'1'&x"1B4E",'1'&x"1B4F",
+--'1'&x"1B50",'1'&x"1B51",'1'&x"1B52",'1'&x"1B53",'1'&x"1B54",'1'&x"1B55",'1'&x"1B56",'1'&x"1B57",'1'&x"1B58",'1'&x"1B59",'1'&x"1B5A",'1'&x"1B5B",'1'&x"1B5C",'1'&x"1B5D",'1'&x"1B5E",'1'&x"1B5F",
+--'1'&x"1B60",'1'&x"1B61",'1'&x"1B62",'1'&x"1B63",'1'&x"1B64",'1'&x"1B65",'1'&x"1B66",'1'&x"1B67",'1'&x"1B68",'1'&x"1B69",'1'&x"1B6A",'1'&x"1B6B",'1'&x"1B6C",'1'&x"1B6D",'1'&x"1B6E",'1'&x"1B6F",
+--'1'&x"1B70",'1'&x"1B71",'1'&x"1B72",'1'&x"1B73",'1'&x"1B74",'1'&x"1B75",'1'&x"1B76",'1'&x"1B77",'1'&x"1B78",'1'&x"1B79",'1'&x"1B7A",'1'&x"1B7B",'1'&x"1B7C",'1'&x"1B7D",'1'&x"1B7E",'1'&x"1B7F",
+--'1'&x"1B80",'1'&x"1B81",'1'&x"1B82",'1'&x"1B83",'1'&x"1B84",'1'&x"1B85",'1'&x"1B86",'1'&x"1B87",'1'&x"1B88",'1'&x"1B89",'1'&x"1B8A",'1'&x"1B8B",'1'&x"1B8C",'1'&x"1B8D",'1'&x"1B8E",'1'&x"1B8F",
+--'1'&x"1B90",'1'&x"1B91",'1'&x"1B92",'1'&x"1B93",'1'&x"1B94",'1'&x"1B95",'1'&x"1B96",'1'&x"1B97",'1'&x"1B98",'1'&x"1B99",'1'&x"1B9A",'1'&x"1B9B",'1'&x"1B9C",'1'&x"1B9D",'1'&x"1B9E",'1'&x"1B9F",
+--'1'&x"1BA0",'1'&x"1BA1",'1'&x"1BA2",'1'&x"1BA3",'1'&x"1BA4",'1'&x"1BA5",'1'&x"1BA6",'1'&x"1BA7",'1'&x"1BA8",'1'&x"1BA9",'1'&x"1BAA",'1'&x"1BAB",'1'&x"1BAC",'1'&x"1BAD",'1'&x"1BAE",'1'&x"1BAF",
+--'1'&x"1BB0",'1'&x"1BB1",'1'&x"1BB2",'1'&x"1BB3",'1'&x"1BB4",'1'&x"1BB5",'1'&x"1BB6",'1'&x"1BB7",'1'&x"1BB8",'1'&x"1BB9",'1'&x"1BBA",'1'&x"1BBB",'1'&x"1BBC",'1'&x"1BBD",'1'&x"1BBE",'1'&x"1BBF",
+--'1'&x"1BC0",'1'&x"1BC1",'1'&x"1BC2",'1'&x"1BC3",'1'&x"1BC4",'1'&x"1BC5",'1'&x"1BC6",'1'&x"1BC7",'1'&x"1BC8",'1'&x"1BC9",'1'&x"1BCA",'1'&x"1BCB",'1'&x"1BCC",'1'&x"1BCD",'1'&x"1BCE",'1'&x"1BCF",
+--'1'&x"1BD0",'1'&x"1BD1",'1'&x"1BD2",'1'&x"1BD3",'1'&x"1BD4",'1'&x"1BD5",'1'&x"1BD6",'1'&x"1BD7",'1'&x"1BD8",'1'&x"1BD9",'1'&x"1BDA",'1'&x"1BDB",'1'&x"1BDC",'1'&x"1BDD",'1'&x"1BDE",'1'&x"1BDF",
+--'1'&x"1BE0",'1'&x"1BE1",'1'&x"1BE2",'1'&x"1BE3",'1'&x"1BE4",'1'&x"1BE5",'1'&x"1BE6",'1'&x"1BE7",'1'&x"1BE8",'1'&x"1BE9",'1'&x"1BEA",'1'&x"1BEB",'1'&x"1BEC",'1'&x"1BED",'1'&x"1BEE",'1'&x"1BEF",
+--'1'&x"1BF0",'1'&x"1BF1",'1'&x"1BF2",'1'&x"1BF3",'1'&x"1BF4",'1'&x"1BF5",'1'&x"1BF6",'1'&x"1BF7",'1'&x"1BF8",'1'&x"1BF9",'1'&x"1BFA",'1'&x"1BFB",'1'&x"1BFC",'1'&x"1BFD",'1'&x"1BFE",'1'&x"1BFF",
+--'1'&x"1C00",'1'&x"1C01",'1'&x"1C02",'1'&x"1C03",'1'&x"1C04",'1'&x"1C05",'1'&x"1C06",'1'&x"1C07",'1'&x"1C08",'1'&x"1C09",'1'&x"1C0A",'1'&x"1C0B",'1'&x"1C0C",'1'&x"1C0D",'1'&x"1C0E",'1'&x"1C0F",
+--'1'&x"1C10",'1'&x"1C11",'1'&x"1C12",'1'&x"1C13",'1'&x"1C14",'1'&x"1C15",'1'&x"1C16",'1'&x"1C17",'1'&x"1C18",'1'&x"1C19",'1'&x"1C1A",'1'&x"1C1B",'1'&x"1C1C",'1'&x"1C1D",'1'&x"1C1E",'1'&x"1C1F",
+--'1'&x"1C20",'1'&x"1C21",'1'&x"1C22",'1'&x"1C23",'1'&x"1C24",'1'&x"1C25",'1'&x"1C26",'1'&x"1C27",'1'&x"1C28",'1'&x"1C29",'1'&x"1C2A",'1'&x"1C2B",'1'&x"1C2C",'1'&x"1C2D",'1'&x"1C2E",'1'&x"1C2F",
+--'1'&x"1C30",'1'&x"1C31",'1'&x"1C32",'1'&x"1C33",'1'&x"1C34",'1'&x"1C35",'1'&x"1C36",'1'&x"1C37",'1'&x"1C38",'1'&x"1C39",'1'&x"1C3A",'1'&x"1C3B",'1'&x"1C3C",'1'&x"1C3D",'1'&x"1C3E",'1'&x"1C3F",
+--'1'&x"1C40",'1'&x"1C41",'1'&x"1C42",'1'&x"1C43",'1'&x"1C44",'1'&x"1C45",'1'&x"1C46",'1'&x"1C47",'1'&x"1C48",'1'&x"1C49",'1'&x"1C4A",'1'&x"1C4B",'1'&x"1C4C",'1'&x"1C4D",'1'&x"1C4E",'1'&x"1C4F",
+--'1'&x"1C50",'1'&x"1C51",'1'&x"1C52",'1'&x"1C53",'1'&x"1C54",'1'&x"1C55",'1'&x"1C56",'1'&x"1C57",'1'&x"1C58",'1'&x"1C59",'1'&x"1C5A",'1'&x"1C5B",'1'&x"1C5C",'1'&x"1C5D",'1'&x"1C5E",'1'&x"1C5F",
+--'1'&x"1C60",'1'&x"1C61",'1'&x"1C62",'1'&x"1C63",'1'&x"1C64",'1'&x"1C65",'1'&x"1C66",'1'&x"1C67",'1'&x"1C68",'1'&x"1C69",'1'&x"1C6A",'1'&x"1C6B",'1'&x"1C6C",'1'&x"1C6D",'1'&x"1C6E",'1'&x"1C6F",
+--'1'&x"1C70",'1'&x"1C71",'1'&x"1C72",'1'&x"1C73",'1'&x"1C74",'1'&x"1C75",'1'&x"1C76",'1'&x"1C77",'1'&x"1C78",'1'&x"1C79",'1'&x"1C7A",'1'&x"1C7B",'1'&x"1C7C",'1'&x"1C7D",'1'&x"1C7E",'1'&x"1C7F",
+--'1'&x"1C80",'1'&x"1C81",'1'&x"1C82",'1'&x"1C83",'1'&x"1C84",'1'&x"1C85",'1'&x"1C86",'1'&x"1C87",'1'&x"1C88",'1'&x"1C89",'1'&x"1C8A",'1'&x"1C8B",'1'&x"1C8C",'1'&x"1C8D",'1'&x"1C8E",'1'&x"1C8F",
+--'1'&x"1C90",'1'&x"1C91",'1'&x"1C92",'1'&x"1C93",'1'&x"1C94",'1'&x"1C95",'1'&x"1C96",'1'&x"1C97",'1'&x"1C98",'1'&x"1C99",'1'&x"1C9A",'1'&x"1C9B",'1'&x"1C9C",'1'&x"1C9D",'1'&x"1C9E",'1'&x"1C9F",
+--'1'&x"1CA0",'1'&x"1CA1",'1'&x"1CA2",'1'&x"1CA3",'1'&x"1CA4",'1'&x"1CA5",'1'&x"1CA6",'1'&x"1CA7",'1'&x"1CA8",'1'&x"1CA9",'1'&x"1CAA",'1'&x"1CAB",'1'&x"1CAC",'1'&x"1CAD",'1'&x"1CAE",'1'&x"1CAF",
+--'1'&x"1CB0",'1'&x"1CB1",'1'&x"1CB2",'1'&x"1CB3",'1'&x"1CB4",'1'&x"1CB5",'1'&x"1CB6",'1'&x"1CB7",'1'&x"1CB8",'1'&x"1CB9",'1'&x"1CBA",'1'&x"1CBB",'1'&x"1CBC",'1'&x"1CBD",'1'&x"1CBE",'1'&x"1CBF",
+--'1'&x"1CC0",'1'&x"1CC1",'1'&x"1CC2",'1'&x"1CC3",'1'&x"1CC4",'1'&x"1CC5",'1'&x"1CC6",'1'&x"1CC7",'1'&x"1CC8",'1'&x"1CC9",'1'&x"1CCA",'1'&x"1CCB",'1'&x"1CCC",'1'&x"1CCD",'1'&x"1CCE",'1'&x"1CCF",
+--'1'&x"1CD0",'1'&x"1CD1",'1'&x"1CD2",'1'&x"1CD3",'1'&x"1CD4",'1'&x"1CD5",'1'&x"1CD6",'1'&x"1CD7",'1'&x"1CD8",'1'&x"1CD9",'1'&x"1CDA",'1'&x"1CDB",'1'&x"1CDC",'1'&x"1CDD",'1'&x"1CDE",'1'&x"1CDF",
+--'1'&x"1CE0",'1'&x"1CE1",'1'&x"1CE2",'1'&x"1CE3",'1'&x"1CE4",'1'&x"1CE5",'1'&x"1CE6",'1'&x"1CE7",'1'&x"1CE8",'1'&x"1CE9",'1'&x"1CEA",'1'&x"1CEB",'1'&x"1CEC",'1'&x"1CED",'1'&x"1CEE",'1'&x"1CEF",
+--'1'&x"1CF0",'1'&x"1CF1",'1'&x"1CF2",'1'&x"1CF3",'1'&x"1CF4",'1'&x"1CF5",'1'&x"1CF6",'1'&x"1CF7",'1'&x"1CF8",'1'&x"1CF9",'1'&x"1CFA",'1'&x"1CFB",'1'&x"1CFC",'1'&x"1CFD",'1'&x"1CFE",'1'&x"1CFF",
+--'1'&x"1D00",'1'&x"1D01",'1'&x"1D02",'1'&x"1D03",'1'&x"1D04",'1'&x"1D05",'1'&x"1D06",'1'&x"1D07",'1'&x"1D08",'1'&x"1D09",'1'&x"1D0A",'1'&x"1D0B",'1'&x"1D0C",'1'&x"1D0D",'1'&x"1D0E",'1'&x"1D0F",
+--'1'&x"1D10",'1'&x"1D11",'1'&x"1D12",'1'&x"1D13",'1'&x"1D14",'1'&x"1D15",'1'&x"1D16",'1'&x"1D17",'1'&x"1D18",'1'&x"1D19",'1'&x"1D1A",'1'&x"1D1B",'1'&x"1D1C",'1'&x"1D1D",'1'&x"1D1E",'1'&x"1D1F",
+--'1'&x"1D20",'1'&x"1D21",'1'&x"1D22",'1'&x"1D23",'1'&x"1D24",'1'&x"1D25",'1'&x"1D26",'1'&x"1D27",'1'&x"1D28",'1'&x"1D29",'1'&x"1D2A",'1'&x"1D2B",'1'&x"1D2C",'1'&x"1D2D",'1'&x"1D2E",'1'&x"1D2F",
+--'1'&x"1D30",'1'&x"1D31",'1'&x"1D32",'1'&x"1D33",'1'&x"1D34",'1'&x"1D35",'1'&x"1D36",'1'&x"1D37",'1'&x"1D38",'1'&x"1D39",'1'&x"1D3A",'1'&x"1D3B",'1'&x"1D3C",'1'&x"1D3D",'1'&x"1D3E",'1'&x"1D3F",
+--'1'&x"1D40",'1'&x"1D41",'1'&x"1D42",'1'&x"1D43",'1'&x"1D44",'1'&x"1D45",'1'&x"1D46",'1'&x"1D47",'1'&x"1D48",'1'&x"1D49",'1'&x"1D4A",'1'&x"1D4B",'1'&x"1D4C",'1'&x"1D4D",'1'&x"1D4E",'1'&x"1D4F",
+--'1'&x"1D50",'1'&x"1D51",'1'&x"1D52",'1'&x"1D53",'1'&x"1D54",'1'&x"1D55",'1'&x"1D56",'1'&x"1D57",'1'&x"1D58",'1'&x"1D59",'1'&x"1D5A",'1'&x"1D5B",'1'&x"1D5C",'1'&x"1D5D",'1'&x"1D5E",'1'&x"1D5F",
+--'1'&x"1D60",'1'&x"1D61",'1'&x"1D62",'1'&x"1D63",'1'&x"1D64",'1'&x"1D65",'1'&x"1D66",'1'&x"1D67",'1'&x"1D68",'1'&x"1D69",'1'&x"1D6A",'1'&x"1D6B",'1'&x"1D6C",'1'&x"1D6D",'1'&x"1D6E",'1'&x"1D6F",
+--'1'&x"1D70",'1'&x"1D71",'1'&x"1D72",'1'&x"1D73",'1'&x"1D74",'1'&x"1D75",'1'&x"1D76",'1'&x"1D77",'1'&x"1D78",'1'&x"1D79",'1'&x"1D7A",'1'&x"1D7B",'1'&x"1D7C",'1'&x"1D7D",'1'&x"1D7E",'1'&x"1D7F",
+--'1'&x"1D80",'1'&x"1D81",'1'&x"1D82",'1'&x"1D83",'1'&x"1D84",'1'&x"1D85",'1'&x"1D86",'1'&x"1D87",'1'&x"1D88",'1'&x"1D89",'1'&x"1D8A",'1'&x"1D8B",'1'&x"1D8C",'1'&x"1D8D",'1'&x"1D8E",'1'&x"1D8F",
+--'1'&x"1D90",'1'&x"1D91",'1'&x"1D92",'1'&x"1D93",'1'&x"1D94",'1'&x"1D95",'1'&x"1D96",'1'&x"1D97",'1'&x"1D98",'1'&x"1D99",'1'&x"1D9A",'1'&x"1D9B",'1'&x"1D9C",'1'&x"1D9D",'1'&x"1D9E",'1'&x"1D9F",
+--'1'&x"1DA0",'1'&x"1DA1",'1'&x"1DA2",'1'&x"1DA3",'1'&x"1DA4",'1'&x"1DA5",'1'&x"1DA6",'1'&x"1DA7",'1'&x"1DA8",'1'&x"1DA9",'1'&x"1DAA",'1'&x"1DAB",'1'&x"1DAC",'1'&x"1DAD",'1'&x"1DAE",'1'&x"1DAF",
+--'1'&x"1DB0",'1'&x"1DB1",'1'&x"1DB2",'1'&x"1DB3",'1'&x"1DB4",'1'&x"1DB5",'1'&x"1DB6",'1'&x"1DB7",'1'&x"1DB8",'1'&x"1DB9",'1'&x"1DBA",'1'&x"1DBB",'1'&x"1DBC",'1'&x"1DBD",'1'&x"1DBE",'1'&x"1DBF",
+--'1'&x"1DC0",'1'&x"1DC1",'1'&x"1DC2",'1'&x"1DC3",'1'&x"1DC4",'1'&x"1DC5",'1'&x"1DC6",'1'&x"1DC7",'1'&x"1DC8",'1'&x"1DC9",'1'&x"1DCA",'1'&x"1DCB",'1'&x"1DCC",'1'&x"1DCD",'1'&x"1DCE",'1'&x"1DCF",
+--'1'&x"1DD0",'1'&x"1DD1",'1'&x"1DD2",'1'&x"1DD3",'1'&x"1DD4",'1'&x"1DD5",'1'&x"1DD6",'1'&x"1DD7",'1'&x"1DD8",'1'&x"1DD9",'1'&x"1DDA",'1'&x"1DDB",'1'&x"1DDC",'1'&x"1DDD",'1'&x"1DDE",'1'&x"1DDF",
+--'1'&x"1DE0",'1'&x"1DE1",'1'&x"1DE2",'1'&x"1DE3",'1'&x"1DE4",'1'&x"1DE5",'1'&x"1DE6",'1'&x"1DE7",'1'&x"1DE8",'1'&x"1DE9",'1'&x"1DEA",'1'&x"1DEB",'1'&x"1DEC",'1'&x"1DED",'1'&x"1DEE",'1'&x"1DEF",
+--'1'&x"1DF0",'1'&x"1DF1",'1'&x"1DF2",'1'&x"1DF3",'1'&x"1DF4",'1'&x"1DF5",'1'&x"1DF6",'1'&x"1DF7",'1'&x"1DF8",'1'&x"1DF9",'1'&x"1DFA",'1'&x"1DFB",'1'&x"1DFC",'1'&x"1DFD",'1'&x"1DFE",'1'&x"1DFF",
+--'1'&x"1E00",'1'&x"1E01",'1'&x"1E02",'1'&x"1E03",'1'&x"1E04",'1'&x"1E05",'1'&x"1E06",'1'&x"1E07",'1'&x"1E08",'1'&x"1E09",'1'&x"1E0A",'1'&x"1E0B",'1'&x"1E0C",'1'&x"1E0D",'1'&x"1E0E",'1'&x"1E0F",
+--'1'&x"1E10",'1'&x"1E11",'1'&x"1E12",'1'&x"1E13",'1'&x"1E14",'1'&x"1E15",'1'&x"1E16",'1'&x"1E17",'1'&x"1E18",'1'&x"1E19",'1'&x"1E1A",'1'&x"1E1B",'1'&x"1E1C",'1'&x"1E1D",'1'&x"1E1E",'1'&x"1E1F",
+--'1'&x"1E20",'1'&x"1E21",'1'&x"1E22",'1'&x"1E23",'1'&x"1E24",'1'&x"1E25",'1'&x"1E26",'1'&x"1E27",'1'&x"1E28",'1'&x"1E29",'1'&x"1E2A",'1'&x"1E2B",'1'&x"1E2C",'1'&x"1E2D",'1'&x"1E2E",'1'&x"1E2F",
+--'1'&x"1E30",'1'&x"1E31",'1'&x"1E32",'1'&x"1E33",'1'&x"1E34",'1'&x"1E35",'1'&x"1E36",'1'&x"1E37",'1'&x"1E38",'1'&x"1E39",'1'&x"1E3A",'1'&x"1E3B",'1'&x"1E3C",'1'&x"1E3D",'1'&x"1E3E",'1'&x"1E3F",
+--'1'&x"1E40",'1'&x"1E41",'1'&x"1E42",'1'&x"1E43",'1'&x"1E44",'1'&x"1E45",'1'&x"1E46",'1'&x"1E47",'1'&x"1E48",'1'&x"1E49",'1'&x"1E4A",'1'&x"1E4B",'1'&x"1E4C",'1'&x"1E4D",'1'&x"1E4E",'1'&x"1E4F",
+--'1'&x"1E50",'1'&x"1E51",'1'&x"1E52",'1'&x"1E53",'1'&x"1E54",'1'&x"1E55",'1'&x"1E56",'1'&x"1E57",'1'&x"1E58",'1'&x"1E59",'1'&x"1E5A",'1'&x"1E5B",'1'&x"1E5C",'1'&x"1E5D",'1'&x"1E5E",'1'&x"1E5F",
+--'1'&x"1E60",'1'&x"1E61",'1'&x"1E62",'1'&x"1E63",'1'&x"1E64",'1'&x"1E65",'1'&x"1E66",'1'&x"1E67",'1'&x"1E68",'1'&x"1E69",'1'&x"1E6A",'1'&x"1E6B",'1'&x"1E6C",'1'&x"1E6D",'1'&x"1E6E",'1'&x"1E6F",
+--'1'&x"1E70",'1'&x"1E71",'1'&x"1E72",'1'&x"1E73",'1'&x"1E74",'1'&x"1E75",'1'&x"1E76",'1'&x"1E77",'1'&x"1E78",'1'&x"1E79",'1'&x"1E7A",'1'&x"1E7B",'1'&x"1E7C",'1'&x"1E7D",'1'&x"1E7E",'1'&x"1E7F",
+--'1'&x"1E80",'1'&x"1E81",'1'&x"1E82",'1'&x"1E83",'1'&x"1E84",'1'&x"1E85",'1'&x"1E86",'1'&x"1E87",'1'&x"1E88",'1'&x"1E89",'1'&x"1E8A",'1'&x"1E8B",'1'&x"1E8C",'1'&x"1E8D",'1'&x"1E8E",'1'&x"1E8F",
+--'1'&x"1E90",'1'&x"1E91",'1'&x"1E92",'1'&x"1E93",'1'&x"1E94",'1'&x"1E95",'1'&x"1E96",'1'&x"1E97",'1'&x"1E98",'1'&x"1E99",'1'&x"1E9A",'1'&x"1E9B",'1'&x"1E9C",'1'&x"1E9D",'1'&x"1E9E",'1'&x"1E9F",
+--'1'&x"1EA0",'1'&x"1EA1",'1'&x"1EA2",'1'&x"1EA3",'1'&x"1EA4",'1'&x"1EA5",'1'&x"1EA6",'1'&x"1EA7",'1'&x"1EA8",'1'&x"1EA9",'1'&x"1EAA",'1'&x"1EAB",'1'&x"1EAC",'1'&x"1EAD",'1'&x"1EAE",'1'&x"1EAF",
+--'1'&x"1EB0",'1'&x"1EB1",'1'&x"1EB2",'1'&x"1EB3",'1'&x"1EB4",'1'&x"1EB5",'1'&x"1EB6",'1'&x"1EB7",'1'&x"1EB8",'1'&x"1EB9",'1'&x"1EBA",'1'&x"1EBB",'1'&x"1EBC",'1'&x"1EBD",'1'&x"1EBE",'1'&x"1EBF",
+--'1'&x"1EC0",'1'&x"1EC1",'1'&x"1EC2",'1'&x"1EC3",'1'&x"1EC4",'1'&x"1EC5",'1'&x"1EC6",'1'&x"1EC7",'1'&x"1EC8",'1'&x"1EC9",'1'&x"1ECA",'1'&x"1ECB",'1'&x"1ECC",'1'&x"1ECD",'1'&x"1ECE",'1'&x"1ECF",
+--'1'&x"1ED0",'1'&x"1ED1",'1'&x"1ED2",'1'&x"1ED3",'1'&x"1ED4",'1'&x"1ED5",'1'&x"1ED6",'1'&x"1ED7",'1'&x"1ED8",'1'&x"1ED9",'1'&x"1EDA",'1'&x"1EDB",'1'&x"1EDC",'1'&x"1EDD",'1'&x"1EDE",'1'&x"1EDF",
+--'1'&x"1EE0",'1'&x"1EE1",'1'&x"1EE2",'1'&x"1EE3",'1'&x"1EE4",'1'&x"1EE5",'1'&x"1EE6",'1'&x"1EE7",'1'&x"1EE8",'1'&x"1EE9",'1'&x"1EEA",'1'&x"1EEB",'1'&x"1EEC",'1'&x"1EED",'1'&x"1EEE",'1'&x"1EEF",
+--'1'&x"1EF0",'1'&x"1EF1",'1'&x"1EF2",'1'&x"1EF3",'1'&x"1EF4",'1'&x"1EF5",'1'&x"1EF6",'1'&x"1EF7",'1'&x"1EF8",'1'&x"1EF9",'1'&x"1EFA",'1'&x"1EFB",'1'&x"1EFC",'1'&x"1EFD",'1'&x"1EFE",'1'&x"1EFF",
+--'1'&x"1F00",'1'&x"1F01",'1'&x"1F02",'1'&x"1F03",'1'&x"1F04",'1'&x"1F05",'1'&x"1F06",'1'&x"1F07",'1'&x"1F08",'1'&x"1F09",'1'&x"1F0A",'1'&x"1F0B",'1'&x"1F0C",'1'&x"1F0D",'1'&x"1F0E",'1'&x"1F0F",
+--'1'&x"1F10",'1'&x"1F11",'1'&x"1F12",'1'&x"1F13",'1'&x"1F14",'1'&x"1F15",'1'&x"1F16",'1'&x"1F17",'1'&x"1F18",'1'&x"1F19",'1'&x"1F1A",'1'&x"1F1B",'1'&x"1F1C",'1'&x"1F1D",'1'&x"1F1E",'1'&x"1F1F",
+--'1'&x"1F20",'1'&x"1F21",'1'&x"1F22",'1'&x"1F23",'1'&x"1F24",'1'&x"1F25",'1'&x"1F26",'1'&x"1F27",'1'&x"1F28",'1'&x"1F29",'1'&x"1F2A",'1'&x"1F2B",'1'&x"1F2C",'1'&x"1F2D",'1'&x"1F2E",'1'&x"1F2F",
+--'1'&x"1F30",'1'&x"1F31",'1'&x"1F32",'1'&x"1F33",'1'&x"1F34",'1'&x"1F35",'1'&x"1F36",'1'&x"1F37",'1'&x"1F38",'1'&x"1F39",'1'&x"1F3A",'1'&x"1F3B",'1'&x"1F3C",'1'&x"1F3D",'1'&x"1F3E",'1'&x"1F3F",
+--'1'&x"1F40",'1'&x"1F41",'1'&x"1F42",'1'&x"1F43",'1'&x"1F44",'1'&x"1F45",'1'&x"1F46",'1'&x"1F47",'1'&x"1F48",'1'&x"1F49",'1'&x"1F4A",'1'&x"1F4B",'1'&x"1F4C",'1'&x"1F4D",'1'&x"1F4E",'1'&x"1F4F",
+--'1'&x"1F50",'1'&x"1F51",'1'&x"1F52",'1'&x"1F53",'1'&x"1F54",'1'&x"1F55",'1'&x"1F56",'1'&x"1F57",'1'&x"1F58",'1'&x"1F59",'1'&x"1F5A",'1'&x"1F5B",'1'&x"1F5C",'1'&x"1F5D",'1'&x"1F5E",'1'&x"1F5F",
+--'1'&x"1F60",'1'&x"1F61",'1'&x"1F62",'1'&x"1F63",'1'&x"1F64",'1'&x"1F65",'1'&x"1F66",'1'&x"1F67",'1'&x"1F68",'1'&x"1F69",'1'&x"1F6A",'1'&x"1F6B",'1'&x"1F6C",'1'&x"1F6D",'1'&x"1F6E",'1'&x"1F6F",
+--'1'&x"1F70",'1'&x"1F71",'1'&x"1F72",'1'&x"1F73",'1'&x"1F74",'1'&x"1F75",'1'&x"1F76",'1'&x"1F77",'1'&x"1F78",'1'&x"1F79",'1'&x"1F7A",'1'&x"1F7B",'1'&x"1F7C",'1'&x"1F7D",'1'&x"1F7E",'1'&x"1F7F",
+--'1'&x"1F80",'1'&x"1F81",'1'&x"1F82",'1'&x"1F83",'1'&x"1F84",'1'&x"1F85",'1'&x"1F86",'1'&x"1F87",'1'&x"1F88",'1'&x"1F89",'1'&x"1F8A",'1'&x"1F8B",'1'&x"1F8C",'1'&x"1F8D",'1'&x"1F8E",'1'&x"1F8F",
+--'1'&x"1F90",'1'&x"1F91",'1'&x"1F92",'1'&x"1F93",'1'&x"1F94",'1'&x"1F95",'1'&x"1F96",'1'&x"1F97",'1'&x"1F98",'1'&x"1F99",'1'&x"1F9A",'1'&x"1F9B",'1'&x"1F9C",'1'&x"1F9D",'1'&x"1F9E",'1'&x"1F9F",
+--'1'&x"1FA0",'1'&x"1FA1",'1'&x"1FA2",'1'&x"1FA3",'1'&x"1FA4",'1'&x"1FA5",'1'&x"1FA6",'1'&x"1FA7",'1'&x"1FA8",'1'&x"1FA9",'1'&x"1FAA",'1'&x"1FAB",'1'&x"1FAC",'1'&x"1FAD",'1'&x"1FAE",'1'&x"1FAF",
+--'1'&x"1FB0",'1'&x"1FB1",'1'&x"1FB2",'1'&x"1FB3",'1'&x"1FB4",'1'&x"1FB5",'1'&x"1FB6",'1'&x"1FB7",'1'&x"1FB8",'1'&x"1FB9",'1'&x"1FBA",'1'&x"1FBB",'1'&x"1FBC",'1'&x"1FBD",'1'&x"1FBE",'1'&x"1FBF",
+--'1'&x"1FC0",'1'&x"1FC1",'1'&x"1FC2",'1'&x"1FC3",'1'&x"1FC4",'1'&x"1FC5",'1'&x"1FC6",'1'&x"1FC7",'1'&x"1FC8",'1'&x"1FC9",'1'&x"1FCA",'1'&x"1FCB",'1'&x"1FCC",'1'&x"1FCD",'1'&x"1FCE",'1'&x"1FCF",
+--'1'&x"1FD0",'1'&x"1FD1",'1'&x"1FD2",'1'&x"1FD3",'1'&x"1FD4",'1'&x"1FD5",'1'&x"1FD6",'1'&x"1FD7",'1'&x"1FD8",'1'&x"1FD9",'1'&x"1FDA",'1'&x"1FDB",'1'&x"1FDC",'1'&x"1FDD",'1'&x"1FDE",'1'&x"1FDF",
+--'1'&x"1FE0",'1'&x"1FE1",'1'&x"1FE2",'1'&x"1FE3",'1'&x"1FE4",'1'&x"1FE5",'1'&x"1FE6",'1'&x"1FE7",'1'&x"1FE8",'1'&x"1FE9",'1'&x"1FEA",'1'&x"1FEB",'1'&x"1FEC",'1'&x"1FED",'1'&x"1FEE",'1'&x"1FEF",
+--'1'&x"1FF0",'1'&x"1FF1",'1'&x"1FF2",'1'&x"1FF3",'1'&x"1FF4",'1'&x"1FF5",'1'&x"1FF6",'1'&x"1FF7",'1'&x"1FF8",'1'&x"1FF9",'1'&x"1FFA",'1'&x"1FFB",'1'&x"1FFC",'1'&x"1FFD",'1'&x"1FFE",'1'&x"1FFF",
+--'1'&x"2000",'1'&x"2001",'1'&x"2002",'1'&x"2003",'1'&x"2004",'1'&x"2005",'1'&x"2006",'1'&x"2007",'1'&x"2008",'1'&x"2009",'1'&x"200A",'1'&x"200B",'1'&x"200C",'1'&x"200D",'1'&x"200E",'1'&x"200F",
+--'1'&x"2010",'1'&x"2011",'1'&x"2012",'1'&x"2013",'1'&x"2014",'1'&x"2015",'1'&x"2016",'1'&x"2017",'1'&x"2018",'1'&x"2019",'1'&x"201A",'1'&x"201B",'1'&x"201C",'1'&x"201D",'1'&x"201E",'1'&x"201F",
+--'1'&x"2020",'1'&x"2021",'1'&x"2022",'1'&x"2023",'1'&x"2024",'1'&x"2025",'1'&x"2026",'1'&x"2027",'1'&x"2028",'1'&x"2029",'1'&x"202A",'1'&x"202B",'1'&x"202C",'1'&x"202D",'1'&x"202E",'1'&x"202F",
+--'1'&x"2030",'1'&x"2031",'1'&x"2032",'1'&x"2033",'1'&x"2034",'1'&x"2035",'1'&x"2036",'1'&x"2037",'1'&x"2038",'1'&x"2039",'1'&x"203A",'1'&x"203B",'1'&x"203C",'1'&x"203D",'1'&x"203E",'1'&x"203F",
+--'1'&x"2040",'1'&x"2041",'1'&x"2042",'1'&x"2043",'1'&x"2044",'1'&x"2045",'1'&x"2046",'1'&x"2047",'1'&x"2048",'1'&x"2049",'1'&x"204A",'1'&x"204B",'1'&x"204C",'1'&x"204D",'1'&x"204E",'1'&x"204F",
+--'1'&x"2050",'1'&x"2051",'1'&x"2052",'1'&x"2053",'1'&x"2054",'1'&x"2055",'1'&x"2056",'1'&x"2057",'1'&x"2058",'1'&x"2059",'1'&x"205A",'1'&x"205B",'1'&x"205C",'1'&x"205D",'1'&x"205E",'1'&x"205F",
+--'1'&x"2060",'1'&x"2061",'1'&x"2062",'1'&x"2063",'1'&x"2064",'1'&x"2065",'1'&x"2066",'1'&x"2067",'1'&x"2068",'1'&x"2069",'1'&x"206A",'1'&x"206B",'1'&x"206C",'1'&x"206D",'1'&x"206E",'1'&x"206F",
+--'1'&x"2070",'1'&x"2071",'1'&x"2072",'1'&x"2073",'1'&x"2074",'1'&x"2075",'1'&x"2076",'1'&x"2077",'1'&x"2078",'1'&x"2079",'1'&x"207A",'1'&x"207B",'1'&x"207C",'1'&x"207D",'1'&x"207E",'1'&x"207F",
+--'1'&x"2080",'1'&x"2081",'1'&x"2082",'1'&x"2083",'1'&x"2084",'1'&x"2085",'1'&x"2086",'1'&x"2087",'1'&x"2088",'1'&x"2089",'1'&x"208A",'1'&x"208B",'1'&x"208C",'1'&x"208D",'1'&x"208E",'1'&x"208F",
+--'1'&x"2090",'1'&x"2091",'1'&x"2092",'1'&x"2093",'1'&x"2094",'1'&x"2095",'1'&x"2096",'1'&x"2097",'1'&x"2098",'1'&x"2099",'1'&x"209A",'1'&x"209B",'1'&x"209C",'1'&x"209D",'1'&x"209E",'1'&x"209F",
+--'1'&x"20A0",'1'&x"20A1",'1'&x"20A2",'1'&x"20A3",'1'&x"20A4",'1'&x"20A5",'1'&x"20A6",'1'&x"20A7",'1'&x"20A8",'1'&x"20A9",'1'&x"20AA",'1'&x"20AB",'1'&x"20AC",'1'&x"20AD",'1'&x"20AE",'1'&x"20AF",
+--'1'&x"20B0",'1'&x"20B1",'1'&x"20B2",'1'&x"20B3",'1'&x"20B4",'1'&x"20B5",'1'&x"20B6",'1'&x"20B7",'1'&x"20B8",'1'&x"20B9",'1'&x"20BA",'1'&x"20BB",'1'&x"20BC",'1'&x"20BD",'1'&x"20BE",'1'&x"20BF",
+--'1'&x"20C0",'1'&x"20C1",'1'&x"20C2",'1'&x"20C3",'1'&x"20C4",'1'&x"20C5",'1'&x"20C6",'1'&x"20C7",'1'&x"20C8",'1'&x"20C9",'1'&x"20CA",'1'&x"20CB",'1'&x"20CC",'1'&x"20CD",'1'&x"20CE",'1'&x"20CF",
+--'1'&x"20D0",'1'&x"20D1",'1'&x"20D2",'1'&x"20D3",'1'&x"20D4",'1'&x"20D5",'1'&x"20D6",'1'&x"20D7",'1'&x"20D8",'1'&x"20D9",'1'&x"20DA",'1'&x"20DB",'1'&x"20DC",'1'&x"20DD",'1'&x"20DE",'1'&x"20DF",
+--'1'&x"20E0",'1'&x"20E1",'1'&x"20E2",'1'&x"20E3",'1'&x"20E4",'1'&x"20E5",'1'&x"20E6",'1'&x"20E7",'1'&x"20E8",'1'&x"20E9",'1'&x"20EA",'1'&x"20EB",'1'&x"20EC",'1'&x"20ED",'1'&x"20EE",'1'&x"20EF",
+--'1'&x"20F0",'1'&x"20F1",'1'&x"20F2",'1'&x"20F3",'1'&x"20F4",'1'&x"20F5",'1'&x"20F6",'1'&x"20F7",'1'&x"20F8",'1'&x"20F9",'1'&x"20FA",'1'&x"20FB",'1'&x"20FC",'1'&x"20FD",'1'&x"20FE",'1'&x"20FF",
+--'1'&x"2100",'1'&x"2101",'1'&x"2102",'1'&x"2103",'1'&x"2104",'1'&x"2105",'1'&x"2106",'1'&x"2107",'1'&x"2108",'1'&x"2109",'1'&x"210A",'1'&x"210B",'1'&x"210C",'1'&x"210D",'1'&x"210E",'1'&x"210F",
+--'1'&x"2110",'1'&x"2111",'1'&x"2112",'1'&x"2113",'1'&x"2114",'1'&x"2115",'1'&x"2116",'1'&x"2117",'1'&x"2118",'1'&x"2119",'1'&x"211A",'1'&x"211B",'1'&x"211C",'1'&x"211D",'1'&x"211E",'1'&x"211F",
+--'1'&x"2120",'1'&x"2121",'1'&x"2122",'1'&x"2123",'1'&x"2124",'1'&x"2125",'1'&x"2126",'1'&x"2127",'1'&x"2128",'1'&x"2129",'1'&x"212A",'1'&x"212B",'1'&x"212C",'1'&x"212D",'1'&x"212E",'1'&x"212F",
+--'1'&x"2130",'1'&x"2131",'1'&x"2132",'1'&x"2133",'1'&x"2134",'1'&x"2135",'1'&x"2136",'1'&x"2137",'1'&x"2138",'1'&x"2139",'1'&x"213A",'1'&x"213B",'1'&x"213C",'1'&x"213D",'1'&x"213E",'1'&x"213F",
+--'1'&x"2140",'1'&x"2141",'1'&x"2142",'1'&x"2143",'1'&x"2144",'1'&x"2145",'1'&x"2146",'1'&x"2147",'1'&x"2148",'1'&x"2149",'1'&x"214A",'1'&x"214B",'1'&x"214C",'1'&x"214D",'1'&x"214E",'1'&x"214F",
+--'1'&x"2150",'1'&x"2151",'1'&x"2152",'1'&x"2153",'1'&x"2154",'1'&x"2155",'1'&x"2156",'1'&x"2157",'1'&x"2158",'1'&x"2159",'1'&x"215A",'1'&x"215B",'1'&x"215C",'1'&x"215D",'1'&x"215E",'1'&x"215F",
+--'1'&x"2160",'1'&x"2161",'1'&x"2162",'1'&x"2163",'1'&x"2164",'1'&x"2165",'1'&x"2166",'1'&x"2167",'1'&x"2168",'1'&x"2169",'1'&x"216A",'1'&x"216B",'1'&x"216C",'1'&x"216D",'1'&x"216E",'1'&x"216F",
+--'1'&x"2170",'1'&x"2171",'1'&x"2172",'1'&x"2173",'1'&x"2174",'1'&x"2175",'1'&x"2176",'1'&x"2177",'1'&x"2178",'1'&x"2179",'1'&x"217A",'1'&x"217B",'1'&x"217C",'1'&x"217D",'1'&x"217E",'1'&x"217F",
+--'1'&x"2180",'1'&x"2181",'1'&x"2182",'1'&x"2183",'1'&x"2184",'1'&x"2185",'1'&x"2186",'1'&x"2187",'1'&x"2188",'1'&x"2189",'1'&x"218A",'1'&x"218B",'1'&x"218C",'1'&x"218D",'1'&x"218E",'1'&x"218F",
+--'1'&x"2190",'1'&x"2191",'1'&x"2192",'1'&x"2193",'1'&x"2194",'1'&x"2195",'1'&x"2196",'1'&x"2197",'1'&x"2198",'1'&x"2199",'1'&x"219A",'1'&x"219B",'1'&x"219C",'1'&x"219D",'1'&x"219E",'1'&x"219F",
+--'1'&x"21A0",'1'&x"21A1",'1'&x"21A2",'1'&x"21A3",'1'&x"21A4",'1'&x"21A5",'1'&x"21A6",'1'&x"21A7",'1'&x"21A8",'1'&x"21A9",'1'&x"21AA",'1'&x"21AB",'1'&x"21AC",'1'&x"21AD",'1'&x"21AE",'1'&x"21AF",
+--'1'&x"21B0",'1'&x"21B1",'1'&x"21B2",'1'&x"21B3",'1'&x"21B4",'1'&x"21B5",'1'&x"21B6",'1'&x"21B7",'1'&x"21B8",'1'&x"21B9",'1'&x"21BA",'1'&x"21BB",'1'&x"21BC",'1'&x"21BD",'1'&x"21BE",'1'&x"21BF",
+--'1'&x"21C0",'1'&x"21C1",'1'&x"21C2",'1'&x"21C3",'1'&x"21C4",'1'&x"21C5",'1'&x"21C6",'1'&x"21C7",'1'&x"21C8",'1'&x"21C9",'1'&x"21CA",'1'&x"21CB",'1'&x"21CC",'1'&x"21CD",'1'&x"21CE",'1'&x"21CF",
+--'1'&x"21D0",'1'&x"21D1",'1'&x"21D2",'1'&x"21D3",'1'&x"21D4",'1'&x"21D5",'1'&x"21D6",'1'&x"21D7",'1'&x"21D8",'1'&x"21D9",'1'&x"21DA",'1'&x"21DB",'1'&x"21DC",'1'&x"21DD",'1'&x"21DE",'1'&x"21DF",
+--'1'&x"21E0",'1'&x"21E1",'1'&x"21E2",'1'&x"21E3",'1'&x"21E4",'1'&x"21E5",'1'&x"21E6",'1'&x"21E7",'1'&x"21E8",'1'&x"21E9",'1'&x"21EA",'1'&x"21EB",'1'&x"21EC",'1'&x"21ED",'1'&x"21EE",'1'&x"21EF",
+--'1'&x"21F0",'1'&x"21F1",'1'&x"21F2",'1'&x"21F3",'1'&x"21F4",'1'&x"21F5",'1'&x"21F6",'1'&x"21F7",'1'&x"21F8",'1'&x"21F9",'1'&x"21FA",'1'&x"21FB",'1'&x"21FC",'1'&x"21FD",'1'&x"21FE",'1'&x"21FF",
+--'1'&x"2200",'1'&x"2201",'1'&x"2202",'1'&x"2203",'1'&x"2204",'1'&x"2205",'1'&x"2206",'1'&x"2207",'1'&x"2208",'1'&x"2209",'1'&x"220A",'1'&x"220B",'1'&x"220C",'1'&x"220D",'1'&x"220E",'1'&x"220F",
+--'1'&x"2210",'1'&x"2211",'1'&x"2212",'1'&x"2213",'1'&x"2214",'1'&x"2215",'1'&x"2216",'1'&x"2217",'1'&x"2218",'1'&x"2219",'1'&x"221A",'1'&x"221B",'1'&x"221C",'1'&x"221D",'1'&x"221E",'1'&x"221F",
+--'1'&x"2220",'1'&x"2221",'1'&x"2222",'1'&x"2223",'1'&x"2224",'1'&x"2225",'1'&x"2226",'1'&x"2227",'1'&x"2228",'1'&x"2229",'1'&x"222A",'1'&x"222B",'1'&x"222C",'1'&x"222D",'1'&x"222E",'1'&x"222F",
+--'1'&x"2230",'1'&x"2231",'1'&x"2232",'1'&x"2233",'1'&x"2234",'1'&x"2235",'1'&x"2236",'1'&x"2237",'1'&x"2238",'1'&x"2239",'1'&x"223A",'1'&x"223B",'1'&x"223C",'1'&x"223D",'1'&x"223E",'1'&x"223F",
+--'1'&x"2240",'1'&x"2241",'1'&x"2242",'1'&x"2243",'1'&x"2244",'1'&x"2245",'1'&x"2246",'1'&x"2247",'1'&x"2248",'1'&x"2249",'1'&x"224A",'1'&x"224B",'1'&x"224C",'1'&x"224D",'1'&x"224E",'1'&x"224F",
+--'1'&x"2250",'1'&x"2251",'1'&x"2252",'1'&x"2253",'1'&x"2254",'1'&x"2255",'1'&x"2256",'1'&x"2257",'1'&x"2258",'1'&x"2259",'1'&x"225A",'1'&x"225B",'1'&x"225C",'1'&x"225D",'1'&x"225E",'1'&x"225F",
+--'1'&x"2260",'1'&x"2261",'1'&x"2262",'1'&x"2263",'1'&x"2264",'1'&x"2265",'1'&x"2266",'1'&x"2267",'1'&x"2268",'1'&x"2269",'1'&x"226A",'1'&x"226B",'1'&x"226C",'1'&x"226D",'1'&x"226E",'1'&x"226F",
+--'1'&x"2270",'1'&x"2271",'1'&x"2272",'1'&x"2273",'1'&x"2274",'1'&x"2275",'1'&x"2276",'1'&x"2277",'1'&x"2278",'1'&x"2279",'1'&x"227A",'1'&x"227B",'1'&x"227C",'1'&x"227D",'1'&x"227E",'1'&x"227F",
+--'1'&x"2280",'1'&x"2281",'1'&x"2282",'1'&x"2283",'1'&x"2284",'1'&x"2285",'1'&x"2286",'1'&x"2287",'1'&x"2288",'1'&x"2289",'1'&x"228A",'1'&x"228B",'1'&x"228C",'1'&x"228D",'1'&x"228E",'1'&x"228F",
+--'1'&x"2290",'1'&x"2291",'1'&x"2292",'1'&x"2293",'1'&x"2294",'1'&x"2295",'1'&x"2296",'1'&x"2297",'1'&x"2298",'1'&x"2299",'1'&x"229A",'1'&x"229B",'1'&x"229C",'1'&x"229D",'1'&x"229E",'1'&x"229F",
+--'1'&x"22A0",'1'&x"22A1",'1'&x"22A2",'1'&x"22A3",'1'&x"22A4",'1'&x"22A5",'1'&x"22A6",'1'&x"22A7",'1'&x"22A8",'1'&x"22A9",'1'&x"22AA",'1'&x"22AB",'1'&x"22AC",'1'&x"22AD",'1'&x"22AE",'1'&x"22AF",
+--'1'&x"22B0",'1'&x"22B1",'1'&x"22B2",'1'&x"22B3",'1'&x"22B4",'1'&x"22B5",'1'&x"22B6",'1'&x"22B7",'1'&x"22B8",'1'&x"22B9",'1'&x"22BA",'1'&x"22BB",'1'&x"22BC",'1'&x"22BD",'1'&x"22BE",'1'&x"22BF",
+--'1'&x"22C0",'1'&x"22C1",'1'&x"22C2",'1'&x"22C3",'1'&x"22C4",'1'&x"22C5",'1'&x"22C6",'1'&x"22C7",'1'&x"22C8",'1'&x"22C9",'1'&x"22CA",'1'&x"22CB",'1'&x"22CC",'1'&x"22CD",'1'&x"22CE",'1'&x"22CF",
+--'1'&x"22D0",'1'&x"22D1",'1'&x"22D2",'1'&x"22D3",'1'&x"22D4",'1'&x"22D5",'1'&x"22D6",'1'&x"22D7",'1'&x"22D8",'1'&x"22D9",'1'&x"22DA",'1'&x"22DB",'1'&x"22DC",'1'&x"22DD",'1'&x"22DE",'1'&x"22DF",
+--'1'&x"22E0",'1'&x"22E1",'1'&x"22E2",'1'&x"22E3",'1'&x"22E4",'1'&x"22E5",'1'&x"22E6",'1'&x"22E7",'1'&x"22E8",'1'&x"22E9",'1'&x"22EA",'1'&x"22EB",'1'&x"22EC",'1'&x"22ED",'1'&x"22EE",'1'&x"22EF",
+--'1'&x"22F0",'1'&x"22F1",'1'&x"22F2",'1'&x"22F3",'1'&x"22F4",'1'&x"22F5",'1'&x"22F6",'1'&x"22F7",'1'&x"22F8",'1'&x"22F9",'1'&x"22FA",'1'&x"22FB",'1'&x"22FC",'1'&x"22FD",'1'&x"22FE",'1'&x"22FF",
+--'1'&x"2300",'1'&x"2301",'1'&x"2302",'1'&x"2303",'1'&x"2304",'1'&x"2305",'1'&x"2306",'1'&x"2307",'1'&x"2308",'1'&x"2309",'1'&x"230A",'1'&x"230B",'1'&x"230C",'1'&x"230D",'1'&x"230E",'1'&x"230F",
+--'1'&x"2310",'1'&x"2311",'1'&x"2312",'1'&x"2313",'1'&x"2314",'1'&x"2315",'1'&x"2316",'1'&x"2317",'1'&x"2318",'1'&x"2319",'1'&x"231A",'1'&x"231B",'1'&x"231C",'1'&x"231D",'1'&x"231E",'1'&x"231F",
+--'1'&x"2320",'1'&x"2321",'1'&x"2322",'1'&x"2323",'1'&x"2324",'1'&x"2325",'1'&x"2326",'1'&x"2327",'1'&x"2328",'1'&x"2329",'1'&x"232A",'1'&x"232B",'1'&x"232C",'1'&x"232D",'1'&x"232E",'1'&x"232F",
+--'1'&x"2330",'1'&x"2331",'1'&x"2332",'1'&x"2333",'1'&x"2334",'1'&x"2335",'1'&x"2336",'1'&x"2337",'1'&x"2338",'1'&x"2339",'1'&x"233A",'1'&x"233B",'1'&x"233C",'1'&x"233D",'1'&x"233E",'1'&x"233F",
+--'1'&x"2340",'1'&x"2341",'1'&x"2342",'1'&x"2343",'1'&x"2344",'1'&x"2345",'1'&x"2346",'1'&x"2347",'1'&x"2348",'1'&x"2349",'1'&x"234A",'1'&x"234B",'1'&x"234C",'1'&x"234D",'1'&x"234E",'1'&x"234F",
+--'1'&x"2350",'1'&x"2351",'1'&x"2352",'1'&x"2353",'1'&x"2354",'1'&x"2355",'1'&x"2356",'1'&x"2357",'1'&x"2358",'1'&x"2359",'1'&x"235A",'1'&x"235B",'1'&x"235C",'1'&x"235D",'1'&x"235E",'1'&x"235F",
+--'1'&x"2360",'1'&x"2361",'1'&x"2362",'1'&x"2363",'1'&x"2364",'1'&x"2365",'1'&x"2366",'1'&x"2367",'1'&x"2368",'1'&x"2369",'1'&x"236A",'1'&x"236B",'1'&x"236C",'1'&x"236D",'1'&x"236E",'1'&x"236F",
+--'1'&x"2370",'1'&x"2371",'1'&x"2372",'1'&x"2373",'1'&x"2374",'1'&x"2375",'1'&x"2376",'1'&x"2377",'1'&x"2378",'1'&x"2379",'1'&x"237A",'1'&x"237B",'1'&x"237C",'1'&x"237D",'1'&x"237E",'1'&x"237F",
+--'1'&x"2380",'1'&x"2381",'1'&x"2382",'1'&x"2383",'1'&x"2384",'1'&x"2385",'1'&x"2386",'1'&x"2387",'1'&x"2388",'1'&x"2389",'1'&x"238A",'1'&x"238B",'1'&x"238C",'1'&x"238D",'1'&x"238E",'1'&x"238F",
+--'1'&x"2390",'1'&x"2391",'1'&x"2392",'1'&x"2393",'1'&x"2394",'1'&x"2395",'1'&x"2396",'1'&x"2397",'1'&x"2398",'1'&x"2399",'1'&x"239A",'1'&x"239B",'1'&x"239C",'1'&x"239D",'1'&x"239E",'1'&x"239F",
+--'1'&x"23A0",'1'&x"23A1",'1'&x"23A2",'1'&x"23A3",'1'&x"23A4",'1'&x"23A5",'1'&x"23A6",'1'&x"23A7",'1'&x"23A8",'1'&x"23A9",'1'&x"23AA",'1'&x"23AB",'1'&x"23AC",'1'&x"23AD",'1'&x"23AE",'1'&x"23AF",
+--'1'&x"23B0",'1'&x"23B1",'1'&x"23B2",'1'&x"23B3",'1'&x"23B4",'1'&x"23B5",'1'&x"23B6",'1'&x"23B7",'1'&x"23B8",'1'&x"23B9",'1'&x"23BA",'1'&x"23BB",'1'&x"23BC",'1'&x"23BD",'1'&x"23BE",'1'&x"23BF",
+--'1'&x"23C0",'1'&x"23C1",'1'&x"23C2",'1'&x"23C3",'1'&x"23C4",'1'&x"23C5",'1'&x"23C6",'1'&x"23C7",'1'&x"23C8",'1'&x"23C9",'1'&x"23CA",'1'&x"23CB",'1'&x"23CC",'1'&x"23CD",'1'&x"23CE",'1'&x"23CF",
+--'1'&x"23D0",'1'&x"23D1",'1'&x"23D2",'1'&x"23D3",'1'&x"23D4",'1'&x"23D5",'1'&x"23D6",'1'&x"23D7",'1'&x"23D8",'1'&x"23D9",'1'&x"23DA",'1'&x"23DB",'1'&x"23DC",'1'&x"23DD",'1'&x"23DE",'1'&x"23DF",
+--'1'&x"23E0",'1'&x"23E1",'1'&x"23E2",'1'&x"23E3",'1'&x"23E4",'1'&x"23E5",'1'&x"23E6",'1'&x"23E7",'1'&x"23E8",'1'&x"23E9",'1'&x"23EA",'1'&x"23EB",'1'&x"23EC",'1'&x"23ED",'1'&x"23EE",'1'&x"23EF",
+--'1'&x"23F0",'1'&x"23F1",'1'&x"23F2",'1'&x"23F3",'1'&x"23F4",'1'&x"23F5",'1'&x"23F6",'1'&x"23F7",'1'&x"23F8",'1'&x"23F9",'1'&x"23FA",'1'&x"23FB",'1'&x"23FC",'1'&x"23FD",'1'&x"23FE",'1'&x"23FF",
+--'1'&x"2400",'1'&x"2401",'1'&x"2402",'1'&x"2403",'1'&x"2404",'1'&x"2405",'1'&x"2406",'1'&x"2407",'1'&x"2408",'1'&x"2409",'1'&x"240A",'1'&x"240B",'1'&x"240C",'1'&x"240D",'1'&x"240E",'1'&x"240F",
+--'1'&x"2410",'1'&x"2411",'1'&x"2412",'1'&x"2413",'1'&x"2414",'1'&x"2415",'1'&x"2416",'1'&x"2417",'1'&x"2418",'1'&x"2419",'1'&x"241A",'1'&x"241B",'1'&x"241C",'1'&x"241D",'1'&x"241E",'1'&x"241F",
+--'1'&x"2420",'1'&x"2421",'1'&x"2422",'1'&x"2423",'1'&x"2424",'1'&x"2425",'1'&x"2426",'1'&x"2427",'1'&x"2428",'1'&x"2429",'1'&x"242A",'1'&x"242B",'1'&x"242C",'1'&x"242D",'1'&x"242E",'1'&x"242F",
+--'1'&x"2430",'1'&x"2431",'1'&x"2432",'1'&x"2433",'1'&x"2434",'1'&x"2435",'1'&x"2436",'1'&x"2437",'1'&x"2438",'1'&x"2439",'1'&x"243A",'1'&x"243B",'1'&x"243C",'1'&x"243D",'1'&x"243E",'1'&x"243F",
+--'1'&x"2440",'1'&x"2441",'1'&x"2442",'1'&x"2443",'1'&x"2444",'1'&x"2445",'1'&x"2446",'1'&x"2447",'1'&x"2448",'1'&x"2449",'1'&x"244A",'1'&x"244B",'1'&x"244C",'1'&x"244D",'1'&x"244E",'1'&x"244F",
+--'1'&x"2450",'1'&x"2451",'1'&x"2452",'1'&x"2453",'1'&x"2454",'1'&x"2455",'1'&x"2456",'1'&x"2457",'1'&x"2458",'1'&x"2459",'1'&x"245A",'1'&x"245B",'1'&x"245C",'1'&x"245D",'1'&x"245E",'1'&x"245F",
+--'1'&x"2460",'1'&x"2461",'1'&x"2462",'1'&x"2463",'1'&x"2464",'1'&x"2465",'1'&x"2466",'1'&x"2467",'1'&x"2468",'1'&x"2469",'1'&x"246A",'1'&x"246B",'1'&x"246C",'1'&x"246D",'1'&x"246E",'1'&x"246F",
+--'1'&x"2470",'1'&x"2471",'1'&x"2472",'1'&x"2473",'1'&x"2474",'1'&x"2475",'1'&x"2476",'1'&x"2477",'1'&x"2478",'1'&x"2479",'1'&x"247A",'1'&x"247B",'1'&x"247C",'1'&x"247D",'1'&x"247E",'1'&x"247F",
+--'1'&x"2480",'1'&x"2481",'1'&x"2482",'1'&x"2483",'1'&x"2484",'1'&x"2485",'1'&x"2486",'1'&x"2487",'1'&x"2488",'1'&x"2489",'1'&x"248A",'1'&x"248B",'1'&x"248C",'1'&x"248D",'1'&x"248E",'1'&x"248F",
+--'1'&x"2490",'1'&x"2491",'1'&x"2492",'1'&x"2493",'1'&x"2494",'1'&x"2495",'1'&x"2496",'1'&x"2497",'1'&x"2498",'1'&x"2499",'1'&x"249A",'1'&x"249B",'1'&x"249C",'1'&x"249D",'1'&x"249E",'1'&x"249F",
+--'1'&x"24A0",'1'&x"24A1",'1'&x"24A2",'1'&x"24A3",'1'&x"24A4",'1'&x"24A5",'1'&x"24A6",'1'&x"24A7",'1'&x"24A8",'1'&x"24A9",'1'&x"24AA",'1'&x"24AB",'1'&x"24AC",'1'&x"24AD",'1'&x"24AE",'1'&x"24AF",
+--'1'&x"24B0",'1'&x"24B1",'1'&x"24B2",'1'&x"24B3",'1'&x"24B4",'1'&x"24B5",'1'&x"24B6",'1'&x"24B7",'1'&x"24B8",'1'&x"24B9",'1'&x"24BA",'1'&x"24BB",'1'&x"24BC",'1'&x"24BD",'1'&x"24BE",'1'&x"24BF",
+--'1'&x"24C0",'1'&x"24C1",'1'&x"24C2",'1'&x"24C3",'1'&x"24C4",'1'&x"24C5",'1'&x"24C6",'1'&x"24C7",'1'&x"24C8",'1'&x"24C9",'1'&x"24CA",'1'&x"24CB",'1'&x"24CC",'1'&x"24CD",'1'&x"24CE",'1'&x"24CF",
+--'1'&x"24D0",'1'&x"24D1",'1'&x"24D2",'1'&x"24D3",'1'&x"24D4",'1'&x"24D5",'1'&x"24D6",'1'&x"24D7",'1'&x"24D8",'1'&x"24D9",'1'&x"24DA",'1'&x"24DB",'1'&x"24DC",'1'&x"24DD",'1'&x"24DE",'1'&x"24DF",
+--'1'&x"24E0",'1'&x"24E1",'1'&x"24E2",'1'&x"24E3",'1'&x"24E4",'1'&x"24E5",'1'&x"24E6",'1'&x"24E7",'1'&x"24E8",'1'&x"24E9",'1'&x"24EA",'1'&x"24EB",'1'&x"24EC",'1'&x"24ED",'1'&x"24EE",'1'&x"24EF",
+--'1'&x"24F0",'1'&x"24F1",'1'&x"24F2",'1'&x"24F3",'1'&x"24F4",'1'&x"24F5",'1'&x"24F6",'1'&x"24F7",'1'&x"24F8",'1'&x"24F9",'1'&x"24FA",'1'&x"24FB",'1'&x"24FC",'1'&x"24FD",'1'&x"24FE",'1'&x"24FF",
+--'1'&x"2500",'1'&x"2501",'1'&x"2502",'1'&x"2503",'1'&x"2504",'1'&x"2505",'1'&x"2506",'1'&x"2507",'1'&x"2508",'1'&x"2509",'1'&x"250A",'1'&x"250B",'1'&x"250C",'1'&x"250D",'1'&x"250E",'1'&x"250F",
+--'1'&x"2510",'1'&x"2511",'1'&x"2512",'1'&x"2513",'1'&x"2514",'1'&x"2515",'1'&x"2516",'1'&x"2517",'1'&x"2518",'1'&x"2519",'1'&x"251A",'1'&x"251B",'1'&x"251C",'1'&x"251D",'1'&x"251E",'1'&x"251F",
+--'1'&x"2520",'1'&x"2521",'1'&x"2522",'1'&x"2523",'1'&x"2524",'1'&x"2525",'1'&x"2526",'1'&x"2527",'1'&x"2528",'1'&x"2529",'1'&x"252A",'1'&x"252B",'1'&x"252C",'1'&x"252D",'1'&x"252E",'1'&x"252F",
+--'1'&x"2530",'1'&x"2531",'1'&x"2532",'1'&x"2533",'1'&x"2534",'1'&x"2535",'1'&x"2536",'1'&x"2537",'1'&x"2538",'1'&x"2539",'1'&x"253A",'1'&x"253B",'1'&x"253C",'1'&x"253D",'1'&x"253E",'1'&x"253F",
+--'1'&x"2540",'1'&x"2541",'1'&x"2542",'1'&x"2543",'1'&x"2544",'1'&x"2545",'1'&x"2546",'1'&x"2547",'1'&x"2548",'1'&x"2549",'1'&x"254A",'1'&x"254B",'1'&x"254C",'1'&x"254D",'1'&x"254E",'1'&x"254F",
+--'1'&x"2550",'1'&x"2551",'1'&x"2552",'1'&x"2553",'1'&x"2554",'1'&x"2555",'1'&x"2556",'1'&x"2557",'1'&x"2558",'1'&x"2559",'1'&x"255A",'1'&x"255B",'1'&x"255C",'1'&x"255D",'1'&x"255E",'1'&x"255F",
+--'1'&x"2560",'1'&x"2561",'1'&x"2562",'1'&x"2563",'1'&x"2564",'1'&x"2565",'1'&x"2566",'1'&x"2567",'1'&x"2568",'1'&x"2569",'1'&x"256A",'1'&x"256B",'1'&x"256C",'1'&x"256D",'1'&x"256E",'1'&x"256F",
+--'1'&x"2570",'1'&x"2571",'1'&x"2572",'1'&x"2573",'1'&x"2574",'1'&x"2575",'1'&x"2576",'1'&x"2577",'1'&x"2578",'1'&x"2579",'1'&x"257A",'1'&x"257B",'1'&x"257C",'1'&x"257D",'1'&x"257E",'1'&x"257F",
+--'1'&x"2580",'1'&x"2581",'1'&x"2582",'1'&x"2583",'1'&x"2584",'1'&x"2585",'1'&x"2586",'1'&x"2587",'1'&x"2588",'1'&x"2589",'1'&x"258A",'1'&x"258B",'1'&x"258C",'1'&x"258D",'1'&x"258E",'1'&x"258F",
+--'1'&x"2590",'1'&x"2591",'1'&x"2592",'1'&x"2593",'1'&x"2594",'1'&x"2595",'1'&x"2596",'1'&x"2597",'1'&x"2598",'1'&x"2599",'1'&x"259A",'1'&x"259B",'1'&x"259C",'1'&x"259D",'1'&x"259E",'1'&x"259F",
+--'1'&x"25A0",'1'&x"25A1",'1'&x"25A2",'1'&x"25A3",'1'&x"25A4",'1'&x"25A5",'1'&x"25A6",'1'&x"25A7",'1'&x"25A8",'1'&x"25A9",'1'&x"25AA",'1'&x"25AB",'1'&x"25AC",'1'&x"25AD",'1'&x"25AE",'1'&x"25AF",
+--'1'&x"25B0",'1'&x"25B1",'1'&x"25B2",'1'&x"25B3",'1'&x"25B4",'1'&x"25B5",'1'&x"25B6",'1'&x"25B7",'1'&x"25B8",'1'&x"25B9",'1'&x"25BA",'1'&x"25BB",'1'&x"25BC",'1'&x"25BD",'1'&x"25BE",'1'&x"25BF",
+--'1'&x"25C0",'1'&x"25C1",'1'&x"25C2",'1'&x"25C3",'1'&x"25C4",'1'&x"25C5",'1'&x"25C6",'1'&x"25C7",'1'&x"25C8",'1'&x"25C9",'1'&x"25CA",'1'&x"25CB",'1'&x"25CC",'1'&x"25CD",'1'&x"25CE",'1'&x"25CF",
+--'1'&x"25D0",'1'&x"25D1",'1'&x"25D2",'1'&x"25D3",'1'&x"25D4",'1'&x"25D5",'1'&x"25D6",'1'&x"25D7",'1'&x"25D8",'1'&x"25D9",'1'&x"25DA",'1'&x"25DB",'1'&x"25DC",'1'&x"25DD",'1'&x"25DE",'1'&x"25DF",
+--'1'&x"25E0",'1'&x"25E1",'1'&x"25E2",'1'&x"25E3",'1'&x"25E4",'1'&x"25E5",'1'&x"25E6",'1'&x"25E7",'1'&x"25E8",'1'&x"25E9",'1'&x"25EA",'1'&x"25EB",'1'&x"25EC",'1'&x"25ED",'1'&x"25EE",'1'&x"25EF",
+--'1'&x"25F0",'1'&x"25F1",'1'&x"25F2",'1'&x"25F3",'1'&x"25F4",'1'&x"25F5",'1'&x"25F6",'1'&x"25F7",'1'&x"25F8",'1'&x"25F9",'1'&x"25FA",'1'&x"25FB",'1'&x"25FC",'1'&x"25FD",'1'&x"25FE",'1'&x"25FF",
+--'1'&x"2600",'1'&x"2601",'1'&x"2602",'1'&x"2603",'1'&x"2604",'1'&x"2605",'1'&x"2606",'1'&x"2607",'1'&x"2608",'1'&x"2609",'1'&x"260A",'1'&x"260B",'1'&x"260C",'1'&x"260D",'1'&x"260E",'1'&x"260F",
+--'1'&x"2610",'1'&x"2611",'1'&x"2612",'1'&x"2613",'1'&x"2614",'1'&x"2615",'1'&x"2616",'1'&x"2617",'1'&x"2618",'1'&x"2619",'1'&x"261A",'1'&x"261B",'1'&x"261C",'1'&x"261D",'1'&x"261E",'1'&x"261F",
+--'1'&x"2620",'1'&x"2621",'1'&x"2622",'1'&x"2623",'1'&x"2624",'1'&x"2625",'1'&x"2626",'1'&x"2627",'1'&x"2628",'1'&x"2629",'1'&x"262A",'1'&x"262B",'1'&x"262C",'1'&x"262D",'1'&x"262E",'1'&x"262F",
+--'1'&x"2630",'1'&x"2631",'1'&x"2632",'1'&x"2633",'1'&x"2634",'1'&x"2635",'1'&x"2636",'1'&x"2637",'1'&x"2638",'1'&x"2639",'1'&x"263A",'1'&x"263B",'1'&x"263C",'1'&x"263D",'1'&x"263E",'1'&x"263F",
+--'1'&x"2640",'1'&x"2641",'1'&x"2642",'1'&x"2643",'1'&x"2644",'1'&x"2645",'1'&x"2646",'1'&x"2647",'1'&x"2648",'1'&x"2649",'1'&x"264A",'1'&x"264B",'1'&x"264C",'1'&x"264D",'1'&x"264E",'1'&x"264F",
+--'1'&x"2650",'1'&x"2651",'1'&x"2652",'1'&x"2653",'1'&x"2654",'1'&x"2655",'1'&x"2656",'1'&x"2657",'1'&x"2658",'1'&x"2659",'1'&x"265A",'1'&x"265B",'1'&x"265C",'1'&x"265D",'1'&x"265E",'1'&x"265F",
+--'1'&x"2660",'1'&x"2661",'1'&x"2662",'1'&x"2663",'1'&x"2664",'1'&x"2665",'1'&x"2666",'1'&x"2667",'1'&x"2668",'1'&x"2669",'1'&x"266A",'1'&x"266B",'1'&x"266C",'1'&x"266D",'1'&x"266E",'1'&x"266F",
+--'1'&x"2670",'1'&x"2671",'1'&x"2672",'1'&x"2673",'1'&x"2674",'1'&x"2675",'1'&x"2676",'1'&x"2677",'1'&x"2678",'1'&x"2679",'1'&x"267A",'1'&x"267B",'1'&x"267C",'1'&x"267D",'1'&x"267E",'1'&x"267F",
+--'1'&x"2680",'1'&x"2681",'1'&x"2682",'1'&x"2683",'1'&x"2684",'1'&x"2685",'1'&x"2686",'1'&x"2687",'1'&x"2688",'1'&x"2689",'1'&x"268A",'1'&x"268B",'1'&x"268C",'1'&x"268D",'1'&x"268E",'1'&x"268F",
+--'1'&x"2690",'1'&x"2691",'1'&x"2692",'1'&x"2693",'1'&x"2694",'1'&x"2695",'1'&x"2696",'1'&x"2697",'1'&x"2698",'1'&x"2699",'1'&x"269A",'1'&x"269B",'1'&x"269C",'1'&x"269D",'1'&x"269E",'1'&x"269F",
+--'1'&x"26A0",'1'&x"26A1",'1'&x"26A2",'1'&x"26A3",'1'&x"26A4",'1'&x"26A5",'1'&x"26A6",'1'&x"26A7",'1'&x"26A8",'1'&x"26A9",'1'&x"26AA",'1'&x"26AB",'1'&x"26AC",'1'&x"26AD",'1'&x"26AE",'1'&x"26AF",
+--'1'&x"26B0",'1'&x"26B1",'1'&x"26B2",'1'&x"26B3",'1'&x"26B4",'1'&x"26B5",'1'&x"26B6",'1'&x"26B7",'1'&x"26B8",'1'&x"26B9",'1'&x"26BA",'1'&x"26BB",'1'&x"26BC",'1'&x"26BD",'1'&x"26BE",'1'&x"26BF",
+--'1'&x"26C0",'1'&x"26C1",'1'&x"26C2",'1'&x"26C3",'1'&x"26C4",'1'&x"26C5",'1'&x"26C6",'1'&x"26C7",'1'&x"26C8",'1'&x"26C9",'1'&x"26CA",'1'&x"26CB",'1'&x"26CC",'1'&x"26CD",'1'&x"26CE",'1'&x"26CF",
+--'1'&x"26D0",'1'&x"26D1",'1'&x"26D2",'1'&x"26D3",'1'&x"26D4",'1'&x"26D5",'1'&x"26D6",'1'&x"26D7",'1'&x"26D8",'1'&x"26D9",'1'&x"26DA",'1'&x"26DB",'1'&x"26DC",'1'&x"26DD",'1'&x"26DE",'1'&x"26DF",
+--'1'&x"26E0",'1'&x"26E1",'1'&x"26E2",'1'&x"26E3",'1'&x"26E4",'1'&x"26E5",'1'&x"26E6",'1'&x"26E7",'1'&x"26E8",'1'&x"26E9",'1'&x"26EA",'1'&x"26EB",'1'&x"26EC",'1'&x"26ED",'1'&x"26EE",'1'&x"26EF",
+--'1'&x"26F0",'1'&x"26F1",'1'&x"26F2",'1'&x"26F3",'1'&x"26F4",'1'&x"26F5",'1'&x"26F6",'1'&x"26F7",'1'&x"26F8",'1'&x"26F9",'1'&x"26FA",'1'&x"26FB",'1'&x"26FC",'1'&x"26FD",'1'&x"26FE",'1'&x"26FF",
+--'1'&x"2700",'1'&x"2701",'1'&x"2702",'1'&x"2703",'1'&x"2704",'1'&x"2705",'1'&x"2706",'1'&x"2707",'1'&x"2708",'1'&x"2709",'1'&x"270A",'1'&x"270B",'1'&x"270C",'1'&x"270D",'1'&x"270E",'1'&x"270F",
+--'1'&x"2710",'1'&x"2711",'1'&x"2712",'1'&x"2713",'1'&x"2714",'1'&x"2715",'1'&x"2716",'1'&x"2717",'1'&x"2718",'1'&x"2719",'1'&x"271A",'1'&x"271B",'1'&x"271C",'1'&x"271D",'1'&x"271E",'1'&x"271F",
+--'1'&x"2720",'1'&x"2721",'1'&x"2722",'1'&x"2723",'1'&x"2724",'1'&x"2725",'1'&x"2726",'1'&x"2727",'1'&x"2728",'1'&x"2729",'1'&x"272A",'1'&x"272B",'1'&x"272C",'1'&x"272D",'1'&x"272E",'1'&x"272F",
+--'1'&x"2730",'1'&x"2731",'1'&x"2732",'1'&x"2733",'1'&x"2734",'1'&x"2735",'1'&x"2736",'1'&x"2737",'1'&x"2738",'1'&x"2739",'1'&x"273A",'1'&x"273B",'1'&x"273C",'1'&x"273D",'1'&x"273E",'1'&x"273F",
+--'1'&x"2740",'1'&x"2741",'1'&x"2742",'1'&x"2743",'1'&x"2744",'1'&x"2745",'1'&x"2746",'1'&x"2747",'1'&x"2748",'1'&x"2749",'1'&x"274A",'1'&x"274B",'1'&x"274C",'1'&x"274D",'1'&x"274E",'1'&x"274F",
+--'1'&x"2750",'1'&x"2751",'1'&x"2752",'1'&x"2753",'1'&x"2754",'1'&x"2755",'1'&x"2756",'1'&x"2757",'1'&x"2758",'1'&x"2759",'1'&x"275A",'1'&x"275B",'1'&x"275C",'1'&x"275D",'1'&x"275E",'1'&x"275F",
+--'1'&x"2760",'1'&x"2761",'1'&x"2762",'1'&x"2763",'1'&x"2764",'1'&x"2765",'1'&x"2766",'1'&x"2767",'1'&x"2768",'1'&x"2769",'1'&x"276A",'1'&x"276B",'1'&x"276C",'1'&x"276D",'1'&x"276E",'1'&x"276F",
+--'1'&x"2770",'1'&x"2771",'1'&x"2772",'1'&x"2773",'1'&x"2774",'1'&x"2775",'1'&x"2776",'1'&x"2777",'1'&x"2778",'1'&x"2779",'1'&x"277A",'1'&x"277B",'1'&x"277C",'1'&x"277D",'1'&x"277E",'1'&x"277F",
+--'1'&x"2780",'1'&x"2781",'1'&x"2782",'1'&x"2783",'1'&x"2784",'1'&x"2785",'1'&x"2786",'1'&x"2787",'1'&x"2788",'1'&x"2789",'1'&x"278A",'1'&x"278B",'1'&x"278C",'1'&x"278D",'1'&x"278E",'1'&x"278F",
+--'1'&x"2790",'1'&x"2791",'1'&x"2792",'1'&x"2793",'1'&x"2794",'1'&x"2795",'1'&x"2796",'1'&x"2797",'1'&x"2798",'1'&x"2799",'1'&x"279A",'1'&x"279B",'1'&x"279C",'1'&x"279D",'1'&x"279E",'1'&x"279F",
+--'1'&x"27A0",'1'&x"27A1",'1'&x"27A2",'1'&x"27A3",'1'&x"27A4",'1'&x"27A5",'1'&x"27A6",'1'&x"27A7",'1'&x"27A8",'1'&x"27A9",'1'&x"27AA",'1'&x"27AB",'1'&x"27AC",'1'&x"27AD",'1'&x"27AE",'1'&x"27AF",
+--'1'&x"27B0",'1'&x"27B1",'1'&x"27B2",'1'&x"27B3",'1'&x"27B4",'1'&x"27B5",'1'&x"27B6",'1'&x"27B7",'1'&x"27B8",'1'&x"27B9",'1'&x"27BA",'1'&x"27BB",'1'&x"27BC",'1'&x"27BD",'1'&x"27BE",'1'&x"27BF",
+--'1'&x"27C0",'1'&x"27C1",'1'&x"27C2",'1'&x"27C3",'1'&x"27C4",'1'&x"27C5",'1'&x"27C6",'1'&x"27C7",'1'&x"27C8",'1'&x"27C9",'1'&x"27CA",'1'&x"27CB",'1'&x"27CC",'1'&x"27CD",'1'&x"27CE",'1'&x"27CF",
+--'1'&x"27D0",'1'&x"27D1",'1'&x"27D2",'1'&x"27D3",'1'&x"27D4",'1'&x"27D5",'1'&x"27D6",'1'&x"27D7",'1'&x"27D8",'1'&x"27D9",'1'&x"27DA",'1'&x"27DB",'1'&x"27DC",'1'&x"27DD",'1'&x"27DE",'1'&x"27DF",
+--'1'&x"27E0",'1'&x"27E1",'1'&x"27E2",'1'&x"27E3",'1'&x"27E4",'1'&x"27E5",'1'&x"27E6",'1'&x"27E7",'1'&x"27E8",'1'&x"27E9",'1'&x"27EA",'1'&x"27EB",'1'&x"27EC",'1'&x"27ED",'1'&x"27EE",'1'&x"27EF",
+--'1'&x"27F0",'1'&x"27F1",'1'&x"27F2",'1'&x"27F3",'1'&x"27F4",'1'&x"27F5",'1'&x"27F6",'1'&x"27F7",'1'&x"27F8",'1'&x"27F9",'1'&x"27FA",'1'&x"27FB",'1'&x"27FC",'1'&x"27FD",'1'&x"27FE",'1'&x"27FF",
+--'1'&x"2800",'1'&x"2801",'1'&x"2802",'1'&x"2803",'1'&x"2804",'1'&x"2805",'1'&x"2806",'1'&x"2807",'1'&x"2808",'1'&x"2809",'1'&x"280A",'1'&x"280B",'1'&x"280C",'1'&x"280D",'1'&x"280E",'1'&x"280F",
+--'1'&x"2810",'1'&x"2811",'1'&x"2812",'1'&x"2813",'1'&x"2814",'1'&x"2815",'1'&x"2816",'1'&x"2817",'1'&x"2818",'1'&x"2819",'1'&x"281A",'1'&x"281B",'1'&x"281C",'1'&x"281D",'1'&x"281E",'1'&x"281F",
+--'1'&x"2820",'1'&x"2821",'1'&x"2822",'1'&x"2823",'1'&x"2824",'1'&x"2825",'1'&x"2826",'1'&x"2827",'1'&x"2828",'1'&x"2829",'1'&x"282A",'1'&x"282B",'1'&x"282C",'1'&x"282D",'1'&x"282E",'1'&x"282F",
+--'1'&x"2830",'1'&x"2831",'1'&x"2832",'1'&x"2833",'1'&x"2834",'1'&x"2835",'1'&x"2836",'1'&x"2837",'1'&x"2838",'1'&x"2839",'1'&x"283A",'1'&x"283B",'1'&x"283C",'1'&x"283D",'1'&x"283E",'1'&x"283F",
+--'1'&x"2840",'1'&x"2841",'1'&x"2842",'1'&x"2843",'1'&x"2844",'1'&x"2845",'1'&x"2846",'1'&x"2847",'1'&x"2848",'1'&x"2849",'1'&x"284A",'1'&x"284B",'1'&x"284C",'1'&x"284D",'1'&x"284E",'1'&x"284F",
+--'1'&x"2850",'1'&x"2851",'1'&x"2852",'1'&x"2853",'1'&x"2854",'1'&x"2855",'1'&x"2856",'1'&x"2857",'1'&x"2858",'1'&x"2859",'1'&x"285A",'1'&x"285B",'1'&x"285C",'1'&x"285D",'1'&x"285E",'1'&x"285F",
+--'1'&x"2860",'1'&x"2861",'1'&x"2862",'1'&x"2863",'1'&x"2864",'1'&x"2865",'1'&x"2866",'1'&x"2867",'1'&x"2868",'1'&x"2869",'1'&x"286A",'1'&x"286B",'1'&x"286C",'1'&x"286D",'1'&x"286E",'1'&x"286F",
+--'1'&x"2870",'1'&x"2871",'1'&x"2872",'1'&x"2873",'1'&x"2874",'1'&x"2875",'1'&x"2876",'1'&x"2877",'1'&x"2878",'1'&x"2879",'1'&x"287A",'1'&x"287B",'1'&x"287C",'1'&x"287D",'1'&x"287E",'1'&x"287F",
+--'1'&x"2880",'1'&x"2881",'1'&x"2882",'1'&x"2883",'1'&x"2884",'1'&x"2885",'1'&x"2886",'1'&x"2887",'1'&x"2888",'1'&x"2889",'1'&x"288A",'1'&x"288B",'1'&x"288C",'1'&x"288D",'1'&x"288E",'1'&x"288F",
+--'1'&x"2890",'1'&x"2891",'1'&x"2892",'1'&x"2893",'1'&x"2894",'1'&x"2895",'1'&x"2896",'1'&x"2897",'1'&x"2898",'1'&x"2899",'1'&x"289A",'1'&x"289B",'1'&x"289C",'1'&x"289D",'1'&x"289E",'1'&x"289F",
+--'1'&x"28A0",'1'&x"28A1",'1'&x"28A2",'1'&x"28A3",'1'&x"28A4",'1'&x"28A5",'1'&x"28A6",'1'&x"28A7",'1'&x"28A8",'1'&x"28A9",'1'&x"28AA",'1'&x"28AB",'1'&x"28AC",'1'&x"28AD",'1'&x"28AE",'1'&x"28AF",
+--'1'&x"28B0",'1'&x"28B1",'1'&x"28B2",'1'&x"28B3",'1'&x"28B4",'1'&x"28B5",'1'&x"28B6",'1'&x"28B7",'1'&x"28B8",'1'&x"28B9",'1'&x"28BA",'1'&x"28BB",'1'&x"28BC",'1'&x"28BD",'1'&x"28BE",'1'&x"28BF",
+--'1'&x"28C0",'1'&x"28C1",'1'&x"28C2",'1'&x"28C3",'1'&x"28C4",'1'&x"28C5",'1'&x"28C6",'1'&x"28C7",'1'&x"28C8",'1'&x"28C9",'1'&x"28CA",'1'&x"28CB",'1'&x"28CC",'1'&x"28CD",'1'&x"28CE",'1'&x"28CF",
+--'1'&x"28D0",'1'&x"28D1",'1'&x"28D2",'1'&x"28D3",'1'&x"28D4",'1'&x"28D5",'1'&x"28D6",'1'&x"28D7",'1'&x"28D8",'1'&x"28D9",'1'&x"28DA",'1'&x"28DB",'1'&x"28DC",'1'&x"28DD",'1'&x"28DE",'1'&x"28DF",
+--'1'&x"28E0",'1'&x"28E1",'1'&x"28E2",'1'&x"28E3",'1'&x"28E4",'1'&x"28E5",'1'&x"28E6",'1'&x"28E7",'1'&x"28E8",'1'&x"28E9",'1'&x"28EA",'1'&x"28EB",'1'&x"28EC",'1'&x"28ED",'1'&x"28EE",'1'&x"28EF",
+--'1'&x"28F0",'1'&x"28F1",'1'&x"28F2",'1'&x"28F3",'1'&x"28F4",'1'&x"28F5",'1'&x"28F6",'1'&x"28F7",'1'&x"28F8",'1'&x"28F9",'1'&x"28FA",'1'&x"28FB",'1'&x"28FC",'1'&x"28FD",'1'&x"28FE",'1'&x"28FF",
+--'1'&x"2900",'1'&x"2901",'1'&x"2902",'1'&x"2903",'1'&x"2904",'1'&x"2905",'1'&x"2906",'1'&x"2907",'1'&x"2908",'1'&x"2909",'1'&x"290A",'1'&x"290B",'1'&x"290C",'1'&x"290D",'1'&x"290E",'1'&x"290F",
+--'1'&x"2910",'1'&x"2911",'1'&x"2912",'1'&x"2913",'1'&x"2914",'1'&x"2915",'1'&x"2916",'1'&x"2917",'1'&x"2918",'1'&x"2919",'1'&x"291A",'1'&x"291B",'1'&x"291C",'1'&x"291D",'1'&x"291E",'1'&x"291F",
+--'1'&x"2920",'1'&x"2921",'1'&x"2922",'1'&x"2923",'1'&x"2924",'1'&x"2925",'1'&x"2926",'1'&x"2927",'1'&x"2928",'1'&x"2929",'1'&x"292A",'1'&x"292B",'1'&x"292C",'1'&x"292D",'1'&x"292E",'1'&x"292F",
+--'1'&x"2930",'1'&x"2931",'1'&x"2932",'1'&x"2933",'1'&x"2934",'1'&x"2935",'1'&x"2936",'1'&x"2937",'1'&x"2938",'1'&x"2939",'1'&x"293A",'1'&x"293B",'1'&x"293C",'1'&x"293D",'1'&x"293E",'1'&x"293F",
+--'1'&x"2940",'1'&x"2941",'1'&x"2942",'1'&x"2943",'1'&x"2944",'1'&x"2945",'1'&x"2946",'1'&x"2947",'1'&x"2948",'1'&x"2949",'1'&x"294A",'1'&x"294B",'1'&x"294C",'1'&x"294D",'1'&x"294E",'1'&x"294F",
+--'1'&x"2950",'1'&x"2951",'1'&x"2952",'1'&x"2953",'1'&x"2954",'1'&x"2955",'1'&x"2956",'1'&x"2957",'1'&x"2958",'1'&x"2959",'1'&x"295A",'1'&x"295B",'1'&x"295C",'1'&x"295D",'1'&x"295E",'1'&x"295F",
+--'1'&x"2960",'1'&x"2961",'1'&x"2962",'1'&x"2963",'1'&x"2964",'1'&x"2965",'1'&x"2966",'1'&x"2967",'1'&x"2968",'1'&x"2969",'1'&x"296A",'1'&x"296B",'1'&x"296C",'1'&x"296D",'1'&x"296E",'1'&x"296F",
+--'1'&x"2970",'1'&x"2971",'1'&x"2972",'1'&x"2973",'1'&x"2974",'1'&x"2975",'1'&x"2976",'1'&x"2977",'1'&x"2978",'1'&x"2979",'1'&x"297A",'1'&x"297B",'1'&x"297C",'1'&x"297D",'1'&x"297E",'1'&x"297F",
+--'1'&x"2980",'1'&x"2981",'1'&x"2982",'1'&x"2983",'1'&x"2984",'1'&x"2985",'1'&x"2986",'1'&x"2987",'1'&x"2988",'1'&x"2989",'1'&x"298A",'1'&x"298B",'1'&x"298C",'1'&x"298D",'1'&x"298E",'1'&x"298F",
+--'1'&x"2990",'1'&x"2991",'1'&x"2992",'1'&x"2993",'1'&x"2994",'1'&x"2995",'1'&x"2996",'1'&x"2997",'1'&x"2998",'1'&x"2999",'1'&x"299A",'1'&x"299B",'1'&x"299C",'1'&x"299D",'1'&x"299E",'1'&x"299F",
+--'1'&x"29A0",'1'&x"29A1",'1'&x"29A2",'1'&x"29A3",'1'&x"29A4",'1'&x"29A5",'1'&x"29A6",'1'&x"29A7",'1'&x"29A8",'1'&x"29A9",'1'&x"29AA",'1'&x"29AB",'1'&x"29AC",'1'&x"29AD",'1'&x"29AE",'1'&x"29AF",
+--'1'&x"29B0",'1'&x"29B1",'1'&x"29B2",'1'&x"29B3",'1'&x"29B4",'1'&x"29B5",'1'&x"29B6",'1'&x"29B7",'1'&x"29B8",'1'&x"29B9",'1'&x"29BA",'1'&x"29BB",'1'&x"29BC",'1'&x"29BD",'1'&x"29BE",'1'&x"29BF",
+--'1'&x"29C0",'1'&x"29C1",'1'&x"29C2",'1'&x"29C3",'1'&x"29C4",'1'&x"29C5",'1'&x"29C6",'1'&x"29C7",'1'&x"29C8",'1'&x"29C9",'1'&x"29CA",'1'&x"29CB",'1'&x"29CC",'1'&x"29CD",'1'&x"29CE",'1'&x"29CF",
+--'1'&x"29D0",'1'&x"29D1",'1'&x"29D2",'1'&x"29D3",'1'&x"29D4",'1'&x"29D5",'1'&x"29D6",'1'&x"29D7",'1'&x"29D8",'1'&x"29D9",'1'&x"29DA",'1'&x"29DB",'1'&x"29DC",'1'&x"29DD",'1'&x"29DE",'1'&x"29DF",
+--'1'&x"29E0",'1'&x"29E1",'1'&x"29E2",'1'&x"29E3",'1'&x"29E4",'1'&x"29E5",'1'&x"29E6",'1'&x"29E7",'1'&x"29E8",'1'&x"29E9",'1'&x"29EA",'1'&x"29EB",'1'&x"29EC",'1'&x"29ED",'1'&x"29EE",'1'&x"29EF",
+--'1'&x"29F0",'1'&x"29F1",'1'&x"29F2",'1'&x"29F3",'1'&x"29F4",'1'&x"29F5",'1'&x"29F6",'1'&x"29F7",'1'&x"29F8",'1'&x"29F9",'1'&x"29FA",'1'&x"29FB",'1'&x"29FC",'1'&x"29FD",'1'&x"29FE",'1'&x"29FF",
+--'1'&x"2A00",'1'&x"2A01",'1'&x"2A02",'1'&x"2A03",'1'&x"2A04",'1'&x"2A05",'1'&x"2A06",'1'&x"2A07",'1'&x"2A08",'1'&x"2A09",'1'&x"2A0A",'1'&x"2A0B",'1'&x"2A0C",'1'&x"2A0D",'1'&x"2A0E",'1'&x"2A0F",
+--'1'&x"2A10",'1'&x"2A11",'1'&x"2A12",'1'&x"2A13",'1'&x"2A14",'1'&x"2A15",'1'&x"2A16",'1'&x"2A17",'1'&x"2A18",'1'&x"2A19",'1'&x"2A1A",'1'&x"2A1B",'1'&x"2A1C",'1'&x"2A1D",'1'&x"2A1E",'1'&x"2A1F",
+--'1'&x"2A20",'1'&x"2A21",'1'&x"2A22",'1'&x"2A23",'1'&x"2A24",'1'&x"2A25",'1'&x"2A26",'1'&x"2A27",'1'&x"2A28",'1'&x"2A29",'1'&x"2A2A",'1'&x"2A2B",'1'&x"2A2C",'1'&x"2A2D",'1'&x"2A2E",'1'&x"2A2F",
+--'1'&x"2A30",'1'&x"2A31",'1'&x"2A32",'1'&x"2A33",'1'&x"2A34",'1'&x"2A35",'1'&x"2A36",'1'&x"2A37",'1'&x"2A38",'1'&x"2A39",'1'&x"2A3A",'1'&x"2A3B",'1'&x"2A3C",'1'&x"2A3D",'1'&x"2A3E",'1'&x"2A3F",
+--'1'&x"2A40",'1'&x"2A41",'1'&x"2A42",'1'&x"2A43",'1'&x"2A44",'1'&x"2A45",'1'&x"2A46",'1'&x"2A47",'1'&x"2A48",'1'&x"2A49",'1'&x"2A4A",'1'&x"2A4B",'1'&x"2A4C",'1'&x"2A4D",'1'&x"2A4E",'1'&x"2A4F",
+--'1'&x"2A50",'1'&x"2A51",'1'&x"2A52",'1'&x"2A53",'1'&x"2A54",'1'&x"2A55",'1'&x"2A56",'1'&x"2A57",'1'&x"2A58",'1'&x"2A59",'1'&x"2A5A",'1'&x"2A5B",'1'&x"2A5C",'1'&x"2A5D",'1'&x"2A5E",'1'&x"2A5F",
+--'1'&x"2A60",'1'&x"2A61",'1'&x"2A62",'1'&x"2A63",'1'&x"2A64",'1'&x"2A65",'1'&x"2A66",'1'&x"2A67",'1'&x"2A68",'1'&x"2A69",'1'&x"2A6A",'1'&x"2A6B",'1'&x"2A6C",'1'&x"2A6D",'1'&x"2A6E",'1'&x"2A6F",
+--'1'&x"2A70",'1'&x"2A71",'1'&x"2A72",'1'&x"2A73",'1'&x"2A74",'1'&x"2A75",'1'&x"2A76",'1'&x"2A77",'1'&x"2A78",'1'&x"2A79",'1'&x"2A7A",'1'&x"2A7B",'1'&x"2A7C",'1'&x"2A7D",'1'&x"2A7E",'1'&x"2A7F",
+--'1'&x"2A80",'1'&x"2A81",'1'&x"2A82",'1'&x"2A83",'1'&x"2A84",'1'&x"2A85",'1'&x"2A86",'1'&x"2A87",'1'&x"2A88",'1'&x"2A89",'1'&x"2A8A",'1'&x"2A8B",'1'&x"2A8C",'1'&x"2A8D",'1'&x"2A8E",'1'&x"2A8F",
+--'1'&x"2A90",'1'&x"2A91",'1'&x"2A92",'1'&x"2A93",'1'&x"2A94",'1'&x"2A95",'1'&x"2A96",'1'&x"2A97",'1'&x"2A98",'1'&x"2A99",'1'&x"2A9A",'1'&x"2A9B",'1'&x"2A9C",'1'&x"2A9D",'1'&x"2A9E",'1'&x"2A9F",
+--'1'&x"2AA0",'1'&x"2AA1",'1'&x"2AA2",'1'&x"2AA3",'1'&x"2AA4",'1'&x"2AA5",'1'&x"2AA6",'1'&x"2AA7",'1'&x"2AA8",'1'&x"2AA9",'1'&x"2AAA",'1'&x"2AAB",'1'&x"2AAC",'1'&x"2AAD",'1'&x"2AAE",'1'&x"2AAF",
+--'1'&x"2AB0",'1'&x"2AB1",'1'&x"2AB2",'1'&x"2AB3",'1'&x"2AB4",'1'&x"2AB5",'1'&x"2AB6",'1'&x"2AB7",'1'&x"2AB8",'1'&x"2AB9",'1'&x"2ABA",'1'&x"2ABB",'1'&x"2ABC",'1'&x"2ABD",'1'&x"2ABE",'1'&x"2ABF",
+--'1'&x"2AC0",'1'&x"2AC1",'1'&x"2AC2",'1'&x"2AC3",'1'&x"2AC4",'1'&x"2AC5",'1'&x"2AC6",'1'&x"2AC7",'1'&x"2AC8",'1'&x"2AC9",'1'&x"2ACA",'1'&x"2ACB",'1'&x"2ACC",'1'&x"2ACD",'1'&x"2ACE",'1'&x"2ACF",
+--'1'&x"2AD0",'1'&x"2AD1",'1'&x"2AD2",'1'&x"2AD3",'1'&x"2AD4",'1'&x"2AD5",'1'&x"2AD6",'1'&x"2AD7",'1'&x"2AD8",'1'&x"2AD9",'1'&x"2ADA",'1'&x"2ADB",'1'&x"2ADC",'1'&x"2ADD",'1'&x"2ADE",'1'&x"2ADF",
+--'1'&x"2AE0",'1'&x"2AE1",'1'&x"2AE2",'1'&x"2AE3",'1'&x"2AE4",'1'&x"2AE5",'1'&x"2AE6",'1'&x"2AE7",'1'&x"2AE8",'1'&x"2AE9",'1'&x"2AEA",'1'&x"2AEB",'1'&x"2AEC",'1'&x"2AED",'1'&x"2AEE",'1'&x"2AEF",
+--'1'&x"2AF0",'1'&x"2AF1",'1'&x"2AF2",'1'&x"2AF3",'1'&x"2AF4",'1'&x"2AF5",'1'&x"2AF6",'1'&x"2AF7",'1'&x"2AF8",'1'&x"2AF9",'1'&x"2AFA",'1'&x"2AFB",'1'&x"2AFC",'1'&x"2AFD",'1'&x"2AFE",'1'&x"2AFF",
+--'1'&x"2B00",'1'&x"2B01",'1'&x"2B02",'1'&x"2B03",'1'&x"2B04",'1'&x"2B05",'1'&x"2B06",'1'&x"2B07",'1'&x"2B08",'1'&x"2B09",'1'&x"2B0A",'1'&x"2B0B",'1'&x"2B0C",'1'&x"2B0D",'1'&x"2B0E",'1'&x"2B0F",
+--'1'&x"2B10",'1'&x"2B11",'1'&x"2B12",'1'&x"2B13",'1'&x"2B14",'1'&x"2B15",'1'&x"2B16",'1'&x"2B17",'1'&x"2B18",'1'&x"2B19",'1'&x"2B1A",'1'&x"2B1B",'1'&x"2B1C",'1'&x"2B1D",'1'&x"2B1E",'1'&x"2B1F",
+--'1'&x"2B20",'1'&x"2B21",'1'&x"2B22",'1'&x"2B23",'1'&x"2B24",'1'&x"2B25",'1'&x"2B26",'1'&x"2B27",'1'&x"2B28",'1'&x"2B29",'1'&x"2B2A",'1'&x"2B2B",'1'&x"2B2C",'1'&x"2B2D",'1'&x"2B2E",'1'&x"2B2F",
+--'1'&x"2B30",'1'&x"2B31",'1'&x"2B32",'1'&x"2B33",'1'&x"2B34",'1'&x"2B35",'1'&x"2B36",'1'&x"2B37",'1'&x"2B38",'1'&x"2B39",'1'&x"2B3A",'1'&x"2B3B",'1'&x"2B3C",'1'&x"2B3D",'1'&x"2B3E",'1'&x"2B3F",
+--'1'&x"2B40",'1'&x"2B41",'1'&x"2B42",'1'&x"2B43",'1'&x"2B44",'1'&x"2B45",'1'&x"2B46",'1'&x"2B47",'1'&x"2B48",'1'&x"2B49",'1'&x"2B4A",'1'&x"2B4B",'1'&x"2B4C",'1'&x"2B4D",'1'&x"2B4E",'1'&x"2B4F",
+--'1'&x"2B50",'1'&x"2B51",'1'&x"2B52",'1'&x"2B53",'1'&x"2B54",'1'&x"2B55",'1'&x"2B56",'1'&x"2B57",'1'&x"2B58",'1'&x"2B59",'1'&x"2B5A",'1'&x"2B5B",'1'&x"2B5C",'1'&x"2B5D",'1'&x"2B5E",'1'&x"2B5F",
+--'1'&x"2B60",'1'&x"2B61",'1'&x"2B62",'1'&x"2B63",'1'&x"2B64",'1'&x"2B65",'1'&x"2B66",'1'&x"2B67",'1'&x"2B68",'1'&x"2B69",'1'&x"2B6A",'1'&x"2B6B",'1'&x"2B6C",'1'&x"2B6D",'1'&x"2B6E",'1'&x"2B6F",
+--'1'&x"2B70",'1'&x"2B71",'1'&x"2B72",'1'&x"2B73",'1'&x"2B74",'1'&x"2B75",'1'&x"2B76",'1'&x"2B77",'1'&x"2B78",'1'&x"2B79",'1'&x"2B7A",'1'&x"2B7B",'1'&x"2B7C",'1'&x"2B7D",'1'&x"2B7E",'1'&x"2B7F",
+--'1'&x"2B80",'1'&x"2B81",'1'&x"2B82",'1'&x"2B83",'1'&x"2B84",'1'&x"2B85",'1'&x"2B86",'1'&x"2B87",'1'&x"2B88",'1'&x"2B89",'1'&x"2B8A",'1'&x"2B8B",'1'&x"2B8C",'1'&x"2B8D",'1'&x"2B8E",'1'&x"2B8F",
+--'1'&x"2B90",'1'&x"2B91",'1'&x"2B92",'1'&x"2B93",'1'&x"2B94",'1'&x"2B95",'1'&x"2B96",'1'&x"2B97",'1'&x"2B98",'1'&x"2B99",'1'&x"2B9A",'1'&x"2B9B",'1'&x"2B9C",'1'&x"2B9D",'1'&x"2B9E",'1'&x"2B9F",
+--'1'&x"2BA0",'1'&x"2BA1",'1'&x"2BA2",'1'&x"2BA3",'1'&x"2BA4",'1'&x"2BA5",'1'&x"2BA6",'1'&x"2BA7",'1'&x"2BA8",'1'&x"2BA9",'1'&x"2BAA",'1'&x"2BAB",'1'&x"2BAC",'1'&x"2BAD",'1'&x"2BAE",'1'&x"2BAF",
+--'1'&x"2BB0",'1'&x"2BB1",'1'&x"2BB2",'1'&x"2BB3",'1'&x"2BB4",'1'&x"2BB5",'1'&x"2BB6",'1'&x"2BB7",'1'&x"2BB8",'1'&x"2BB9",'1'&x"2BBA",'1'&x"2BBB",'1'&x"2BBC",'1'&x"2BBD",'1'&x"2BBE",'1'&x"2BBF",
+--'1'&x"2BC0",'1'&x"2BC1",'1'&x"2BC2",'1'&x"2BC3",'1'&x"2BC4",'1'&x"2BC5",'1'&x"2BC6",'1'&x"2BC7",'1'&x"2BC8",'1'&x"2BC9",'1'&x"2BCA",'1'&x"2BCB",'1'&x"2BCC",'1'&x"2BCD",'1'&x"2BCE",'1'&x"2BCF",
+--'1'&x"2BD0",'1'&x"2BD1",'1'&x"2BD2",'1'&x"2BD3",'1'&x"2BD4",'1'&x"2BD5",'1'&x"2BD6",'1'&x"2BD7",'1'&x"2BD8",'1'&x"2BD9",'1'&x"2BDA",'1'&x"2BDB",'1'&x"2BDC",'1'&x"2BDD",'1'&x"2BDE",'1'&x"2BDF",
+--'1'&x"2BE0",'1'&x"2BE1",'1'&x"2BE2",'1'&x"2BE3",'1'&x"2BE4",'1'&x"2BE5",'1'&x"2BE6",'1'&x"2BE7",'1'&x"2BE8",'1'&x"2BE9",'1'&x"2BEA",'1'&x"2BEB",'1'&x"2BEC",'1'&x"2BED",'1'&x"2BEE",'1'&x"2BEF",
+--'1'&x"2BF0",'1'&x"2BF1",'1'&x"2BF2",'1'&x"2BF3",'1'&x"2BF4",'1'&x"2BF5",'1'&x"2BF6",'1'&x"2BF7",'1'&x"2BF8",'1'&x"2BF9",'1'&x"2BFA",'1'&x"2BFB",'1'&x"2BFC",'1'&x"2BFD",'1'&x"2BFE",'1'&x"2BFF",
+--'1'&x"2C00",'1'&x"2C01",'1'&x"2C02",'1'&x"2C03",'1'&x"2C04",'1'&x"2C05",'1'&x"2C06",'1'&x"2C07",'1'&x"2C08",'1'&x"2C09",'1'&x"2C0A",'1'&x"2C0B",'1'&x"2C0C",'1'&x"2C0D",'1'&x"2C0E",'1'&x"2C0F",
+--'1'&x"2C10",'1'&x"2C11",'1'&x"2C12",'1'&x"2C13",'1'&x"2C14",'1'&x"2C15",'1'&x"2C16",'1'&x"2C17",'1'&x"2C18",'1'&x"2C19",'1'&x"2C1A",'1'&x"2C1B",'1'&x"2C1C",'1'&x"2C1D",'1'&x"2C1E",'1'&x"2C1F",
+--'1'&x"2C20",'1'&x"2C21",'1'&x"2C22",'1'&x"2C23",'1'&x"2C24",'1'&x"2C25",'1'&x"2C26",'1'&x"2C27",'1'&x"2C28",'1'&x"2C29",'1'&x"2C2A",'1'&x"2C2B",'1'&x"2C2C",'1'&x"2C2D",'1'&x"2C2E",'1'&x"2C2F",
+--'1'&x"2C30",'1'&x"2C31",'1'&x"2C32",'1'&x"2C33",'1'&x"2C34",'1'&x"2C35",'1'&x"2C36",'1'&x"2C37",'1'&x"2C38",'1'&x"2C39",'1'&x"2C3A",'1'&x"2C3B",'1'&x"2C3C",'1'&x"2C3D",'1'&x"2C3E",'1'&x"2C3F",
+--'1'&x"2C40",'1'&x"2C41",'1'&x"2C42",'1'&x"2C43",'1'&x"2C44",'1'&x"2C45",'1'&x"2C46",'1'&x"2C47",'1'&x"2C48",'1'&x"2C49",'1'&x"2C4A",'1'&x"2C4B",'1'&x"2C4C",'1'&x"2C4D",'1'&x"2C4E",'1'&x"2C4F",
+--'1'&x"2C50",'1'&x"2C51",'1'&x"2C52",'1'&x"2C53",'1'&x"2C54",'1'&x"2C55",'1'&x"2C56",'1'&x"2C57",'1'&x"2C58",'1'&x"2C59",'1'&x"2C5A",'1'&x"2C5B",'1'&x"2C5C",'1'&x"2C5D",'1'&x"2C5E",'1'&x"2C5F",
+--'1'&x"2C60",'1'&x"2C61",'1'&x"2C62",'1'&x"2C63",'1'&x"2C64",'1'&x"2C65",'1'&x"2C66",'1'&x"2C67",'1'&x"2C68",'1'&x"2C69",'1'&x"2C6A",'1'&x"2C6B",'1'&x"2C6C",'1'&x"2C6D",'1'&x"2C6E",'1'&x"2C6F",
+--'1'&x"2C70",'1'&x"2C71",'1'&x"2C72",'1'&x"2C73",'1'&x"2C74",'1'&x"2C75",'1'&x"2C76",'1'&x"2C77",'1'&x"2C78",'1'&x"2C79",'1'&x"2C7A",'1'&x"2C7B",'1'&x"2C7C",'1'&x"2C7D",'1'&x"2C7E",'1'&x"2C7F",
+--'1'&x"2C80",'1'&x"2C81",'1'&x"2C82",'1'&x"2C83",'1'&x"2C84",'1'&x"2C85",'1'&x"2C86",'1'&x"2C87",'1'&x"2C88",'1'&x"2C89",'1'&x"2C8A",'1'&x"2C8B",'1'&x"2C8C",'1'&x"2C8D",'1'&x"2C8E",'1'&x"2C8F",
+--'1'&x"2C90",'1'&x"2C91",'1'&x"2C92",'1'&x"2C93",'1'&x"2C94",'1'&x"2C95",'1'&x"2C96",'1'&x"2C97",'1'&x"2C98",'1'&x"2C99",'1'&x"2C9A",'1'&x"2C9B",'1'&x"2C9C",'1'&x"2C9D",'1'&x"2C9E",'1'&x"2C9F",
+--'1'&x"2CA0",'1'&x"2CA1",'1'&x"2CA2",'1'&x"2CA3",'1'&x"2CA4",'1'&x"2CA5",'1'&x"2CA6",'1'&x"2CA7",'1'&x"2CA8",'1'&x"2CA9",'1'&x"2CAA",'1'&x"2CAB",'1'&x"2CAC",'1'&x"2CAD",'1'&x"2CAE",'1'&x"2CAF",
+--'1'&x"2CB0",'1'&x"2CB1",'1'&x"2CB2",'1'&x"2CB3",'1'&x"2CB4",'1'&x"2CB5",'1'&x"2CB6",'1'&x"2CB7",'1'&x"2CB8",'1'&x"2CB9",'1'&x"2CBA",'1'&x"2CBB",'1'&x"2CBC",'1'&x"2CBD",'1'&x"2CBE",'1'&x"2CBF",
+--'1'&x"2CC0",'1'&x"2CC1",'1'&x"2CC2",'1'&x"2CC3",'1'&x"2CC4",'1'&x"2CC5",'1'&x"2CC6",'1'&x"2CC7",'1'&x"2CC8",'1'&x"2CC9",'1'&x"2CCA",'1'&x"2CCB",'1'&x"2CCC",'1'&x"2CCD",'1'&x"2CCE",'1'&x"2CCF",
+--'1'&x"2CD0",'1'&x"2CD1",'1'&x"2CD2",'1'&x"2CD3",'1'&x"2CD4",'1'&x"2CD5",'1'&x"2CD6",'1'&x"2CD7",'1'&x"2CD8",'1'&x"2CD9",'1'&x"2CDA",'1'&x"2CDB",'1'&x"2CDC",'1'&x"2CDD",'1'&x"2CDE",'1'&x"2CDF",
+--'1'&x"2CE0",'1'&x"2CE1",'1'&x"2CE2",'1'&x"2CE3",'1'&x"2CE4",'1'&x"2CE5",'1'&x"2CE6",'1'&x"2CE7",'1'&x"2CE8",'1'&x"2CE9",'1'&x"2CEA",'1'&x"2CEB",'1'&x"2CEC",'1'&x"2CED",'1'&x"2CEE",'1'&x"2CEF",
+--'1'&x"2CF0",'1'&x"2CF1",'1'&x"2CF2",'1'&x"2CF3",'1'&x"2CF4",'1'&x"2CF5",'1'&x"2CF6",'1'&x"2CF7",'1'&x"2CF8",'1'&x"2CF9",'1'&x"2CFA",'1'&x"2CFB",'1'&x"2CFC",'1'&x"2CFD",'1'&x"2CFE",'1'&x"2CFF",
+--'1'&x"2D00",'1'&x"2D01",'1'&x"2D02",'1'&x"2D03",'1'&x"2D04",'1'&x"2D05",'1'&x"2D06",'1'&x"2D07",'1'&x"2D08",'1'&x"2D09",'1'&x"2D0A",'1'&x"2D0B",'1'&x"2D0C",'1'&x"2D0D",'1'&x"2D0E",'1'&x"2D0F",
+--'1'&x"2D10",'1'&x"2D11",'1'&x"2D12",'1'&x"2D13",'1'&x"2D14",'1'&x"2D15",'1'&x"2D16",'1'&x"2D17",'1'&x"2D18",'1'&x"2D19",'1'&x"2D1A",'1'&x"2D1B",'1'&x"2D1C",'1'&x"2D1D",'1'&x"2D1E",'1'&x"2D1F",
+--'1'&x"2D20",'1'&x"2D21",'1'&x"2D22",'1'&x"2D23",'1'&x"2D24",'1'&x"2D25",'1'&x"2D26",'1'&x"2D27",'1'&x"2D28",'1'&x"2D29",'1'&x"2D2A",'1'&x"2D2B",'1'&x"2D2C",'1'&x"2D2D",'1'&x"2D2E",'1'&x"2D2F",
+--'1'&x"2D30",'1'&x"2D31",'1'&x"2D32",'1'&x"2D33",'1'&x"2D34",'1'&x"2D35",'1'&x"2D36",'1'&x"2D37",'1'&x"2D38",'1'&x"2D39",'1'&x"2D3A",'1'&x"2D3B",'1'&x"2D3C",'1'&x"2D3D",'1'&x"2D3E",'1'&x"2D3F",
+--'1'&x"2D40",'1'&x"2D41",'1'&x"2D42",'1'&x"2D43",'1'&x"2D44",'1'&x"2D45",'1'&x"2D46",'1'&x"2D47",'1'&x"2D48",'1'&x"2D49",'1'&x"2D4A",'1'&x"2D4B",'1'&x"2D4C",'1'&x"2D4D",'1'&x"2D4E",'1'&x"2D4F",
+--'1'&x"2D50",'1'&x"2D51",'1'&x"2D52",'1'&x"2D53",'1'&x"2D54",'1'&x"2D55",'1'&x"2D56",'1'&x"2D57",'1'&x"2D58",'1'&x"2D59",'1'&x"2D5A",'1'&x"2D5B",'1'&x"2D5C",'1'&x"2D5D",'1'&x"2D5E",'1'&x"2D5F",
+--'1'&x"2D60",'1'&x"2D61",'1'&x"2D62",'1'&x"2D63",'1'&x"2D64",'1'&x"2D65",'1'&x"2D66",'1'&x"2D67",'1'&x"2D68",'1'&x"2D69",'1'&x"2D6A",'1'&x"2D6B",'1'&x"2D6C",'1'&x"2D6D",'1'&x"2D6E",'1'&x"2D6F",
+--'1'&x"2D70",'1'&x"2D71",'1'&x"2D72",'1'&x"2D73",'1'&x"2D74",'1'&x"2D75",'1'&x"2D76",'1'&x"2D77",'1'&x"2D78",'1'&x"2D79",'1'&x"2D7A",'1'&x"2D7B",'1'&x"2D7C",'1'&x"2D7D",'1'&x"2D7E",'1'&x"2D7F",
+--'1'&x"2D80",'1'&x"2D81",'1'&x"2D82",'1'&x"2D83",'1'&x"2D84",'1'&x"2D85",'1'&x"2D86",'1'&x"2D87",'1'&x"2D88",'1'&x"2D89",'1'&x"2D8A",'1'&x"2D8B",'1'&x"2D8C",'1'&x"2D8D",'1'&x"2D8E",'1'&x"2D8F",
+--'1'&x"2D90",'1'&x"2D91",'1'&x"2D92",'1'&x"2D93",'1'&x"2D94",'1'&x"2D95",'1'&x"2D96",'1'&x"2D97",'1'&x"2D98",'1'&x"2D99",'1'&x"2D9A",'1'&x"2D9B",'1'&x"2D9C",'1'&x"2D9D",'1'&x"2D9E",'1'&x"2D9F",
+--'1'&x"2DA0",'1'&x"2DA1",'1'&x"2DA2",'1'&x"2DA3",'1'&x"2DA4",'1'&x"2DA5",'1'&x"2DA6",'1'&x"2DA7",'1'&x"2DA8",'1'&x"2DA9",'1'&x"2DAA",'1'&x"2DAB",'1'&x"2DAC",'1'&x"2DAD",'1'&x"2DAE",'1'&x"2DAF",
+--'1'&x"2DB0",'1'&x"2DB1",'1'&x"2DB2",'1'&x"2DB3",'1'&x"2DB4",'1'&x"2DB5",'1'&x"2DB6",'1'&x"2DB7",'1'&x"2DB8",'1'&x"2DB9",'1'&x"2DBA",'1'&x"2DBB",'1'&x"2DBC",'1'&x"2DBD",'1'&x"2DBE",'1'&x"2DBF",
+--'1'&x"2DC0",'1'&x"2DC1",'1'&x"2DC2",'1'&x"2DC3",'1'&x"2DC4",'1'&x"2DC5",'1'&x"2DC6",'1'&x"2DC7",'1'&x"2DC8",'1'&x"2DC9",'1'&x"2DCA",'1'&x"2DCB",'1'&x"2DCC",'1'&x"2DCD",'1'&x"2DCE",'1'&x"2DCF",
+--'1'&x"2DD0",'1'&x"2DD1",'1'&x"2DD2",'1'&x"2DD3",'1'&x"2DD4",'1'&x"2DD5",'1'&x"2DD6",'1'&x"2DD7",'1'&x"2DD8",'1'&x"2DD9",'1'&x"2DDA",'1'&x"2DDB",'1'&x"2DDC",'1'&x"2DDD",'1'&x"2DDE",'1'&x"2DDF",
+--'1'&x"2DE0",'1'&x"2DE1",'1'&x"2DE2",'1'&x"2DE3",'1'&x"2DE4",'1'&x"2DE5",'1'&x"2DE6",'1'&x"2DE7",'1'&x"2DE8",'1'&x"2DE9",'1'&x"2DEA",'1'&x"2DEB",'1'&x"2DEC",'1'&x"2DED",'1'&x"2DEE",'1'&x"2DEF",
+--'1'&x"2DF0",'1'&x"2DF1",'1'&x"2DF2",'1'&x"2DF3",'1'&x"2DF4",'1'&x"2DF5",'1'&x"2DF6",'1'&x"2DF7",'1'&x"2DF8",'1'&x"2DF9",'1'&x"2DFA",'1'&x"2DFB",'1'&x"2DFC",'1'&x"2DFD",'1'&x"2DFE",'1'&x"2DFF",
+--'1'&x"2E00",'1'&x"2E01",'1'&x"2E02",'1'&x"2E03",'1'&x"2E04",'1'&x"2E05",'1'&x"2E06",'1'&x"2E07",'1'&x"2E08",'1'&x"2E09",'1'&x"2E0A",'1'&x"2E0B",'1'&x"2E0C",'1'&x"2E0D",'1'&x"2E0E",'1'&x"2E0F",
+--'1'&x"2E10",'1'&x"2E11",'1'&x"2E12",'1'&x"2E13",'1'&x"2E14",'1'&x"2E15",'1'&x"2E16",'1'&x"2E17",'1'&x"2E18",'1'&x"2E19",'1'&x"2E1A",'1'&x"2E1B",'1'&x"2E1C",'1'&x"2E1D",'1'&x"2E1E",'1'&x"2E1F",
+--'1'&x"2E20",'1'&x"2E21",'1'&x"2E22",'1'&x"2E23",'1'&x"2E24",'1'&x"2E25",'1'&x"2E26",'1'&x"2E27",'1'&x"2E28",'1'&x"2E29",'1'&x"2E2A",'1'&x"2E2B",'1'&x"2E2C",'1'&x"2E2D",'1'&x"2E2E",'1'&x"2E2F",
+--'1'&x"2E30",'1'&x"2E31",'1'&x"2E32",'1'&x"2E33",'1'&x"2E34",'1'&x"2E35",'1'&x"2E36",'1'&x"2E37",'1'&x"2E38",'1'&x"2E39",'1'&x"2E3A",'1'&x"2E3B",'1'&x"2E3C",'1'&x"2E3D",'1'&x"2E3E",'1'&x"2E3F",
+--'1'&x"2E40",'1'&x"2E41",'1'&x"2E42",'1'&x"2E43",'1'&x"2E44",'1'&x"2E45",'1'&x"2E46",'1'&x"2E47",'1'&x"2E48",'1'&x"2E49",'1'&x"2E4A",'1'&x"2E4B",'1'&x"2E4C",'1'&x"2E4D",'1'&x"2E4E",'1'&x"2E4F",
+--'1'&x"2E50",'1'&x"2E51",'1'&x"2E52",'1'&x"2E53",'1'&x"2E54",'1'&x"2E55",'1'&x"2E56",'1'&x"2E57",'1'&x"2E58",'1'&x"2E59",'1'&x"2E5A",'1'&x"2E5B",'1'&x"2E5C",'1'&x"2E5D",'1'&x"2E5E",'1'&x"2E5F",
+--'1'&x"2E60",'1'&x"2E61",'1'&x"2E62",'1'&x"2E63",'1'&x"2E64",'1'&x"2E65",'1'&x"2E66",'1'&x"2E67",'1'&x"2E68",'1'&x"2E69",'1'&x"2E6A",'1'&x"2E6B",'1'&x"2E6C",'1'&x"2E6D",'1'&x"2E6E",'1'&x"2E6F",
+--'1'&x"2E70",'1'&x"2E71",'1'&x"2E72",'1'&x"2E73",'1'&x"2E74",'1'&x"2E75",'1'&x"2E76",'1'&x"2E77",'1'&x"2E78",'1'&x"2E79",'1'&x"2E7A",'1'&x"2E7B",'1'&x"2E7C",'1'&x"2E7D",'1'&x"2E7E",'1'&x"2E7F",
+--'1'&x"2E80",'1'&x"2E81",'1'&x"2E82",'1'&x"2E83",'1'&x"2E84",'1'&x"2E85",'1'&x"2E86",'1'&x"2E87",'1'&x"2E88",'1'&x"2E89",'1'&x"2E8A",'1'&x"2E8B",'1'&x"2E8C",'1'&x"2E8D",'1'&x"2E8E",'1'&x"2E8F",
+--'1'&x"2E90",'1'&x"2E91",'1'&x"2E92",'1'&x"2E93",'1'&x"2E94",'1'&x"2E95",'1'&x"2E96",'1'&x"2E97",'1'&x"2E98",'1'&x"2E99",'1'&x"2E9A",'1'&x"2E9B",'1'&x"2E9C",'1'&x"2E9D",'1'&x"2E9E",'1'&x"2E9F",
+--'1'&x"2EA0",'1'&x"2EA1",'1'&x"2EA2",'1'&x"2EA3",'1'&x"2EA4",'1'&x"2EA5",'1'&x"2EA6",'1'&x"2EA7",'1'&x"2EA8",'1'&x"2EA9",'1'&x"2EAA",'1'&x"2EAB",'1'&x"2EAC",'1'&x"2EAD",'1'&x"2EAE",'1'&x"2EAF",
+--'1'&x"2EB0",'1'&x"2EB1",'1'&x"2EB2",'1'&x"2EB3",'1'&x"2EB4",'1'&x"2EB5",'1'&x"2EB6",'1'&x"2EB7",'1'&x"2EB8",'1'&x"2EB9",'1'&x"2EBA",'1'&x"2EBB",'1'&x"2EBC",'1'&x"2EBD",'1'&x"2EBE",'1'&x"2EBF",
+--'1'&x"2EC0",'1'&x"2EC1",'1'&x"2EC2",'1'&x"2EC3",'1'&x"2EC4",'1'&x"2EC5",'1'&x"2EC6",'1'&x"2EC7",'1'&x"2EC8",'1'&x"2EC9",'1'&x"2ECA",'1'&x"2ECB",'1'&x"2ECC",'1'&x"2ECD",'1'&x"2ECE",'1'&x"2ECF",
+--'1'&x"2ED0",'1'&x"2ED1",'1'&x"2ED2",'1'&x"2ED3",'1'&x"2ED4",'1'&x"2ED5",'1'&x"2ED6",'1'&x"2ED7",'1'&x"2ED8",'1'&x"2ED9",'1'&x"2EDA",'1'&x"2EDB",'1'&x"2EDC",'1'&x"2EDD",'1'&x"2EDE",'1'&x"2EDF",
+--'1'&x"2EE0",'1'&x"2EE1",'1'&x"2EE2",'1'&x"2EE3",'1'&x"2EE4",'1'&x"2EE5",'1'&x"2EE6",'1'&x"2EE7",'1'&x"2EE8",'1'&x"2EE9",'1'&x"2EEA",'1'&x"2EEB",'1'&x"2EEC",'1'&x"2EED",'1'&x"2EEE",'1'&x"2EEF",
+--'1'&x"2EF0",'1'&x"2EF1",'1'&x"2EF2",'1'&x"2EF3",'1'&x"2EF4",'1'&x"2EF5",'1'&x"2EF6",'1'&x"2EF7",'1'&x"2EF8",'1'&x"2EF9",'1'&x"2EFA",'1'&x"2EFB",'1'&x"2EFC",'1'&x"2EFD",'1'&x"2EFE",'1'&x"2EFF",
+--'1'&x"2F00",'1'&x"2F01",'1'&x"2F02",'1'&x"2F03",'1'&x"2F04",'1'&x"2F05",'1'&x"2F06",'1'&x"2F07",'1'&x"2F08",'1'&x"2F09",'1'&x"2F0A",'1'&x"2F0B",'1'&x"2F0C",'1'&x"2F0D",'1'&x"2F0E",'1'&x"2F0F",
+--'1'&x"2F10",'1'&x"2F11",'1'&x"2F12",'1'&x"2F13",'1'&x"2F14",'1'&x"2F15",'1'&x"2F16",'1'&x"2F17",'1'&x"2F18",'1'&x"2F19",'1'&x"2F1A",'1'&x"2F1B",'1'&x"2F1C",'1'&x"2F1D",'1'&x"2F1E",'1'&x"2F1F",
+--'1'&x"2F20",'1'&x"2F21",'1'&x"2F22",'1'&x"2F23",'1'&x"2F24",'1'&x"2F25",'1'&x"2F26",'1'&x"2F27",'1'&x"2F28",'1'&x"2F29",'1'&x"2F2A",'1'&x"2F2B",'1'&x"2F2C",'1'&x"2F2D",'1'&x"2F2E",'1'&x"2F2F",
+--'1'&x"2F30",'1'&x"2F31",'1'&x"2F32",'1'&x"2F33",'1'&x"2F34",'1'&x"2F35",'1'&x"2F36",'1'&x"2F37",'1'&x"2F38",'1'&x"2F39",'1'&x"2F3A",'1'&x"2F3B",'1'&x"2F3C",'1'&x"2F3D",'1'&x"2F3E",'1'&x"2F3F",
+--'1'&x"2F40",'1'&x"2F41",'1'&x"2F42",'1'&x"2F43",'1'&x"2F44",'1'&x"2F45",'1'&x"2F46",'1'&x"2F47",'1'&x"2F48",'1'&x"2F49",'1'&x"2F4A",'1'&x"2F4B",'1'&x"2F4C",'1'&x"2F4D",'1'&x"2F4E",'1'&x"2F4F",
+--'1'&x"2F50",'1'&x"2F51",'1'&x"2F52",'1'&x"2F53",'1'&x"2F54",'1'&x"2F55",'1'&x"2F56",'1'&x"2F57",'1'&x"2F58",'1'&x"2F59",'1'&x"2F5A",'1'&x"2F5B",'1'&x"2F5C",'1'&x"2F5D",'1'&x"2F5E",'1'&x"2F5F",
+--'1'&x"2F60",'1'&x"2F61",'1'&x"2F62",'1'&x"2F63",'1'&x"2F64",'1'&x"2F65",'1'&x"2F66",'1'&x"2F67",'1'&x"2F68",'1'&x"2F69",'1'&x"2F6A",'1'&x"2F6B",'1'&x"2F6C",'1'&x"2F6D",'1'&x"2F6E",'1'&x"2F6F",
+--'1'&x"2F70",'1'&x"2F71",'1'&x"2F72",'1'&x"2F73",'1'&x"2F74",'1'&x"2F75",'1'&x"2F76",'1'&x"2F77",'1'&x"2F78",'1'&x"2F79",'1'&x"2F7A",'1'&x"2F7B",'1'&x"2F7C",'1'&x"2F7D",'1'&x"2F7E",'1'&x"2F7F",
+--'1'&x"2F80",'1'&x"2F81",'1'&x"2F82",'1'&x"2F83",'1'&x"2F84",'1'&x"2F85",'1'&x"2F86",'1'&x"2F87",'1'&x"2F88",'1'&x"2F89",'1'&x"2F8A",'1'&x"2F8B",'1'&x"2F8C",'1'&x"2F8D",'1'&x"2F8E",'1'&x"2F8F",
+--'1'&x"2F90",'1'&x"2F91",'1'&x"2F92",'1'&x"2F93",'1'&x"2F94",'1'&x"2F95",'1'&x"2F96",'1'&x"2F97",'1'&x"2F98",'1'&x"2F99",'1'&x"2F9A",'1'&x"2F9B",'1'&x"2F9C",'1'&x"2F9D",'1'&x"2F9E",'1'&x"2F9F",
+--'1'&x"2FA0",'1'&x"2FA1",'1'&x"2FA2",'1'&x"2FA3",'1'&x"2FA4",'1'&x"2FA5",'1'&x"2FA6",'1'&x"2FA7",'1'&x"2FA8",'1'&x"2FA9",'1'&x"2FAA",'1'&x"2FAB",'1'&x"2FAC",'1'&x"2FAD",'1'&x"2FAE",'1'&x"2FAF",
+--'1'&x"2FB0",'1'&x"2FB1",'1'&x"2FB2",'1'&x"2FB3",'1'&x"2FB4",'1'&x"2FB5",'1'&x"2FB6",'1'&x"2FB7",'1'&x"2FB8",'1'&x"2FB9",'1'&x"2FBA",'1'&x"2FBB",'1'&x"2FBC",'1'&x"2FBD",'1'&x"2FBE",'1'&x"2FBF",
+--'1'&x"2FC0",'1'&x"2FC1",'1'&x"2FC2",'1'&x"2FC3",'1'&x"2FC4",'1'&x"2FC5",'1'&x"2FC6",'1'&x"2FC7",'1'&x"2FC8",'1'&x"2FC9",'1'&x"2FCA",'1'&x"2FCB",'1'&x"2FCC",'1'&x"2FCD",'1'&x"2FCE",'1'&x"2FCF",
+--'1'&x"2FD0",'1'&x"2FD1",'1'&x"2FD2",'1'&x"2FD3",'1'&x"2FD4",'1'&x"2FD5",'1'&x"2FD6",'1'&x"2FD7",'1'&x"2FD8",'1'&x"2FD9",'1'&x"2FDA",'1'&x"2FDB",'1'&x"2FDC",'1'&x"2FDD",'1'&x"2FDE",'1'&x"2FDF",
+--'1'&x"2FE0",'1'&x"2FE1",'1'&x"2FE2",'1'&x"2FE3",'1'&x"2FE4",'1'&x"2FE5",'1'&x"2FE6",'1'&x"2FE7",'1'&x"2FE8",'1'&x"2FE9",'1'&x"2FEA",'1'&x"2FEB",'1'&x"2FEC",'1'&x"2FED",'1'&x"2FEE",'1'&x"2FEF",
+--'1'&x"2FF0",'1'&x"2FF1",'1'&x"2FF2",'1'&x"2FF3",'1'&x"2FF4",'1'&x"2FF5",'1'&x"2FF6",'1'&x"2FF7",'1'&x"2FF8",'1'&x"2FF9",'1'&x"2FFA",'1'&x"2FFB",'1'&x"2FFC",'1'&x"2FFD",'1'&x"2FFE",'1'&x"2FFF",
+--'1'&x"3000",'1'&x"3001",'1'&x"3002",'1'&x"3003",'1'&x"3004",'1'&x"3005",'1'&x"3006",'1'&x"3007",'1'&x"3008",'1'&x"3009",'1'&x"300A",'1'&x"300B",'1'&x"300C",'1'&x"300D",'1'&x"300E",'1'&x"300F",
+--'1'&x"3010",'1'&x"3011",'1'&x"3012",'1'&x"3013",'1'&x"3014",'1'&x"3015",'1'&x"3016",'1'&x"3017",'1'&x"3018",'1'&x"3019",'1'&x"301A",'1'&x"301B",'1'&x"301C",'1'&x"301D",'1'&x"301E",'1'&x"301F",
+--'1'&x"3020",'1'&x"3021",'1'&x"3022",'1'&x"3023",'1'&x"3024",'1'&x"3025",'1'&x"3026",'1'&x"3027",'1'&x"3028",'1'&x"3029",'1'&x"302A",'1'&x"302B",'1'&x"302C",'1'&x"302D",'1'&x"302E",'1'&x"302F",
+--'1'&x"3030",'1'&x"3031",'1'&x"3032",'1'&x"3033",'1'&x"3034",'1'&x"3035",'1'&x"3036",'1'&x"3037",'1'&x"3038",'1'&x"3039",'1'&x"303A",'1'&x"303B",'1'&x"303C",'1'&x"303D",'1'&x"303E",'1'&x"303F",
+--'1'&x"3040",'1'&x"3041",'1'&x"3042",'1'&x"3043",'1'&x"3044",'1'&x"3045",'1'&x"3046",'1'&x"3047",'1'&x"3048",'1'&x"3049",'1'&x"304A",'1'&x"304B",'1'&x"304C",'1'&x"304D",'1'&x"304E",'1'&x"304F",
+--'1'&x"3050",'1'&x"3051",'1'&x"3052",'1'&x"3053",'1'&x"3054",'1'&x"3055",'1'&x"3056",'1'&x"3057",'1'&x"3058",'1'&x"3059",'1'&x"305A",'1'&x"305B",'1'&x"305C",'1'&x"305D",'1'&x"305E",'1'&x"305F",
+--'1'&x"3060",'1'&x"3061",'1'&x"3062",'1'&x"3063",'1'&x"3064",'1'&x"3065",'1'&x"3066",'1'&x"3067",'1'&x"3068",'1'&x"3069",'1'&x"306A",'1'&x"306B",'1'&x"306C",'1'&x"306D",'1'&x"306E",'1'&x"306F",
+--'1'&x"3070",'1'&x"3071",'1'&x"3072",'1'&x"3073",'1'&x"3074",'1'&x"3075",'1'&x"3076",'1'&x"3077",'1'&x"3078",'1'&x"3079",'1'&x"307A",'1'&x"307B",'1'&x"307C",'1'&x"307D",'1'&x"307E",'1'&x"307F",
+--'1'&x"3080",'1'&x"3081",'1'&x"3082",'1'&x"3083",'1'&x"3084",'1'&x"3085",'1'&x"3086",'1'&x"3087",'1'&x"3088",'1'&x"3089",'1'&x"308A",'1'&x"308B",'1'&x"308C",'1'&x"308D",'1'&x"308E",'1'&x"308F",
+--'1'&x"3090",'1'&x"3091",'1'&x"3092",'1'&x"3093",'1'&x"3094",'1'&x"3095",'1'&x"3096",'1'&x"3097",'1'&x"3098",'1'&x"3099",'1'&x"309A",'1'&x"309B",'1'&x"309C",'1'&x"309D",'1'&x"309E",'1'&x"309F",
+--'1'&x"30A0",'1'&x"30A1",'1'&x"30A2",'1'&x"30A3",'1'&x"30A4",'1'&x"30A5",'1'&x"30A6",'1'&x"30A7",'1'&x"30A8",'1'&x"30A9",'1'&x"30AA",'1'&x"30AB",'1'&x"30AC",'1'&x"30AD",'1'&x"30AE",'1'&x"30AF",
+--'1'&x"30B0",'1'&x"30B1",'1'&x"30B2",'1'&x"30B3",'1'&x"30B4",'1'&x"30B5",'1'&x"30B6",'1'&x"30B7",'1'&x"30B8",'1'&x"30B9",'1'&x"30BA",'1'&x"30BB",'1'&x"30BC",'1'&x"30BD",'1'&x"30BE",'1'&x"30BF",
+--'1'&x"30C0",'1'&x"30C1",'1'&x"30C2",'1'&x"30C3",'1'&x"30C4",'1'&x"30C5",'1'&x"30C6",'1'&x"30C7",'1'&x"30C8",'1'&x"30C9",'1'&x"30CA",'1'&x"30CB",'1'&x"30CC",'1'&x"30CD",'1'&x"30CE",'1'&x"30CF",
+--'1'&x"30D0",'1'&x"30D1",'1'&x"30D2",'1'&x"30D3",'1'&x"30D4",'1'&x"30D5",'1'&x"30D6",'1'&x"30D7",'1'&x"30D8",'1'&x"30D9",'1'&x"30DA",'1'&x"30DB",'1'&x"30DC",'1'&x"30DD",'1'&x"30DE",'1'&x"30DF",
+--'1'&x"30E0",'1'&x"30E1",'1'&x"30E2",'1'&x"30E3",'1'&x"30E4",'1'&x"30E5",'1'&x"30E6",'1'&x"30E7",'1'&x"30E8",'1'&x"30E9",'1'&x"30EA",'1'&x"30EB",'1'&x"30EC",'1'&x"30ED",'1'&x"30EE",'1'&x"30EF",
+--'1'&x"30F0",'1'&x"30F1",'1'&x"30F2",'1'&x"30F3",'1'&x"30F4",'1'&x"30F5",'1'&x"30F6",'1'&x"30F7",'1'&x"30F8",'1'&x"30F9",'1'&x"30FA",'1'&x"30FB",'1'&x"30FC",'1'&x"30FD",'1'&x"30FE",'1'&x"30FF",
+--'1'&x"3100",'1'&x"3101",'1'&x"3102",'1'&x"3103",'1'&x"3104",'1'&x"3105",'1'&x"3106",'1'&x"3107",'1'&x"3108",'1'&x"3109",'1'&x"310A",'1'&x"310B",'1'&x"310C",'1'&x"310D",'1'&x"310E",'1'&x"310F",
+--'1'&x"3110",'1'&x"3111",'1'&x"3112",'1'&x"3113",'1'&x"3114",'1'&x"3115",'1'&x"3116",'1'&x"3117",'1'&x"3118",'1'&x"3119",'1'&x"311A",'1'&x"311B",'1'&x"311C",'1'&x"311D",'1'&x"311E",'1'&x"311F",
+--'1'&x"3120",'1'&x"3121",'1'&x"3122",'1'&x"3123",'1'&x"3124",'1'&x"3125",'1'&x"3126",'1'&x"3127",'1'&x"3128",'1'&x"3129",'1'&x"312A",'1'&x"312B",'1'&x"312C",'1'&x"312D",'1'&x"312E",'1'&x"312F",
+--'1'&x"3130",'1'&x"3131",'1'&x"3132",'1'&x"3133",'1'&x"3134",'1'&x"3135",'1'&x"3136",'1'&x"3137",'1'&x"3138",'1'&x"3139",'1'&x"313A",'1'&x"313B",'1'&x"313C",'1'&x"313D",'1'&x"313E",'1'&x"313F",
+--'1'&x"3140",'1'&x"3141",'1'&x"3142",'1'&x"3143",'1'&x"3144",'1'&x"3145",'1'&x"3146",'1'&x"3147",'1'&x"3148",'1'&x"3149",'1'&x"314A",'1'&x"314B",'1'&x"314C",'1'&x"314D",'1'&x"314E",'1'&x"314F",
+--'1'&x"3150",'1'&x"3151",'1'&x"3152",'1'&x"3153",'1'&x"3154",'1'&x"3155",'1'&x"3156",'1'&x"3157",'1'&x"3158",'1'&x"3159",'1'&x"315A",'1'&x"315B",'1'&x"315C",'1'&x"315D",'1'&x"315E",'1'&x"315F",
+--'1'&x"3160",'1'&x"3161",'1'&x"3162",'1'&x"3163",'1'&x"3164",'1'&x"3165",'1'&x"3166",'1'&x"3167",'1'&x"3168",'1'&x"3169",'1'&x"316A",'1'&x"316B",'1'&x"316C",'1'&x"316D",'1'&x"316E",'1'&x"316F",
+--'1'&x"3170",'1'&x"3171",'1'&x"3172",'1'&x"3173",'1'&x"3174",'1'&x"3175",'1'&x"3176",'1'&x"3177",'1'&x"3178",'1'&x"3179",'1'&x"317A",'1'&x"317B",'1'&x"317C",'1'&x"317D",'1'&x"317E",'1'&x"317F",
+--'1'&x"3180",'1'&x"3181",'1'&x"3182",'1'&x"3183",'1'&x"3184",'1'&x"3185",'1'&x"3186",'1'&x"3187",'1'&x"3188",'1'&x"3189",'1'&x"318A",'1'&x"318B",'1'&x"318C",'1'&x"318D",'1'&x"318E",'1'&x"318F",
+--'1'&x"3190",'1'&x"3191",'1'&x"3192",'1'&x"3193",'1'&x"3194",'1'&x"3195",'1'&x"3196",'1'&x"3197",'1'&x"3198",'1'&x"3199",'1'&x"319A",'1'&x"319B",'1'&x"319C",'1'&x"319D",'1'&x"319E",'1'&x"319F",
+--'1'&x"31A0",'1'&x"31A1",'1'&x"31A2",'1'&x"31A3",'1'&x"31A4",'1'&x"31A5",'1'&x"31A6",'1'&x"31A7",'1'&x"31A8",'1'&x"31A9",'1'&x"31AA",'1'&x"31AB",'1'&x"31AC",'1'&x"31AD",'1'&x"31AE",'1'&x"31AF",
+--'1'&x"31B0",'1'&x"31B1",'1'&x"31B2",'1'&x"31B3",'1'&x"31B4",'1'&x"31B5",'1'&x"31B6",'1'&x"31B7",'1'&x"31B8",'1'&x"31B9",'1'&x"31BA",'1'&x"31BB",'1'&x"31BC",'1'&x"31BD",'1'&x"31BE",'1'&x"31BF",
+--'1'&x"31C0",'1'&x"31C1",'1'&x"31C2",'1'&x"31C3",'1'&x"31C4",'1'&x"31C5",'1'&x"31C6",'1'&x"31C7",'1'&x"31C8",'1'&x"31C9",'1'&x"31CA",'1'&x"31CB",'1'&x"31CC",'1'&x"31CD",'1'&x"31CE",'1'&x"31CF",
+--'1'&x"31D0",'1'&x"31D1",'1'&x"31D2",'1'&x"31D3",'1'&x"31D4",'1'&x"31D5",'1'&x"31D6",'1'&x"31D7",'1'&x"31D8",'1'&x"31D9",'1'&x"31DA",'1'&x"31DB",'1'&x"31DC",'1'&x"31DD",'1'&x"31DE",'1'&x"31DF",
+--'1'&x"31E0",'1'&x"31E1",'1'&x"31E2",'1'&x"31E3",'1'&x"31E4",'1'&x"31E5",'1'&x"31E6",'1'&x"31E7",'1'&x"31E8",'1'&x"31E9",'1'&x"31EA",'1'&x"31EB",'1'&x"31EC",'1'&x"31ED",'1'&x"31EE",'1'&x"31EF",
+--'1'&x"31F0",'1'&x"31F1",'1'&x"31F2",'1'&x"31F3",'1'&x"31F4",'1'&x"31F5",'1'&x"31F6",'1'&x"31F7",'1'&x"31F8",'1'&x"31F9",'1'&x"31FA",'1'&x"31FB",'1'&x"31FC",'1'&x"31FD",'1'&x"31FE",'1'&x"31FF",
+--'1'&x"3200",'1'&x"3201",'1'&x"3202",'1'&x"3203",'1'&x"3204",'1'&x"3205",'1'&x"3206",'1'&x"3207",'1'&x"3208",'1'&x"3209",'1'&x"320A",'1'&x"320B",'1'&x"320C",'1'&x"320D",'1'&x"320E",'1'&x"320F",
+--'1'&x"3210",'1'&x"3211",'1'&x"3212",'1'&x"3213",'1'&x"3214",'1'&x"3215",'1'&x"3216",'1'&x"3217",'1'&x"3218",'1'&x"3219",'1'&x"321A",'1'&x"321B",'1'&x"321C",'1'&x"321D",'1'&x"321E",'1'&x"321F",
+--'1'&x"3220",'1'&x"3221",'1'&x"3222",'1'&x"3223",'1'&x"3224",'1'&x"3225",'1'&x"3226",'1'&x"3227",'1'&x"3228",'1'&x"3229",'1'&x"322A",'1'&x"322B",'1'&x"322C",'1'&x"322D",'1'&x"322E",'1'&x"322F",
+--'1'&x"3230",'1'&x"3231",'1'&x"3232",'1'&x"3233",'1'&x"3234",'1'&x"3235",'1'&x"3236",'1'&x"3237",'1'&x"3238",'1'&x"3239",'1'&x"323A",'1'&x"323B",'1'&x"323C",'1'&x"323D",'1'&x"323E",'1'&x"323F",
+--'1'&x"3240",'1'&x"3241",'1'&x"3242",'1'&x"3243",'1'&x"3244",'1'&x"3245",'1'&x"3246",'1'&x"3247",'1'&x"3248",'1'&x"3249",'1'&x"324A",'1'&x"324B",'1'&x"324C",'1'&x"324D",'1'&x"324E",'1'&x"324F",
+--'1'&x"3250",'1'&x"3251",'1'&x"3252",'1'&x"3253",'1'&x"3254",'1'&x"3255",'1'&x"3256",'1'&x"3257",'1'&x"3258",'1'&x"3259",'1'&x"325A",'1'&x"325B",'1'&x"325C",'1'&x"325D",'1'&x"325E",'1'&x"325F",
+--'1'&x"3260",'1'&x"3261",'1'&x"3262",'1'&x"3263",'1'&x"3264",'1'&x"3265",'1'&x"3266",'1'&x"3267",'1'&x"3268",'1'&x"3269",'1'&x"326A",'1'&x"326B",'1'&x"326C",'1'&x"326D",'1'&x"326E",'1'&x"326F",
+--'1'&x"3270",'1'&x"3271",'1'&x"3272",'1'&x"3273",'1'&x"3274",'1'&x"3275",'1'&x"3276",'1'&x"3277",'1'&x"3278",'1'&x"3279",'1'&x"327A",'1'&x"327B",'1'&x"327C",'1'&x"327D",'1'&x"327E",'1'&x"327F",
+--'1'&x"3280",'1'&x"3281",'1'&x"3282",'1'&x"3283",'1'&x"3284",'1'&x"3285",'1'&x"3286",'1'&x"3287",'1'&x"3288",'1'&x"3289",'1'&x"328A",'1'&x"328B",'1'&x"328C",'1'&x"328D",'1'&x"328E",'1'&x"328F",
+--'1'&x"3290",'1'&x"3291",'1'&x"3292",'1'&x"3293",'1'&x"3294",'1'&x"3295",'1'&x"3296",'1'&x"3297",'1'&x"3298",'1'&x"3299",'1'&x"329A",'1'&x"329B",'1'&x"329C",'1'&x"329D",'1'&x"329E",'1'&x"329F",
+--'1'&x"32A0",'1'&x"32A1",'1'&x"32A2",'1'&x"32A3",'1'&x"32A4",'1'&x"32A5",'1'&x"32A6",'1'&x"32A7",'1'&x"32A8",'1'&x"32A9",'1'&x"32AA",'1'&x"32AB",'1'&x"32AC",'1'&x"32AD",'1'&x"32AE",'1'&x"32AF",
+--'1'&x"32B0",'1'&x"32B1",'1'&x"32B2",'1'&x"32B3",'1'&x"32B4",'1'&x"32B5",'1'&x"32B6",'1'&x"32B7",'1'&x"32B8",'1'&x"32B9",'1'&x"32BA",'1'&x"32BB",'1'&x"32BC",'1'&x"32BD",'1'&x"32BE",'1'&x"32BF",
+--'1'&x"32C0",'1'&x"32C1",'1'&x"32C2",'1'&x"32C3",'1'&x"32C4",'1'&x"32C5",'1'&x"32C6",'1'&x"32C7",'1'&x"32C8",'1'&x"32C9",'1'&x"32CA",'1'&x"32CB",'1'&x"32CC",'1'&x"32CD",'1'&x"32CE",'1'&x"32CF",
+--'1'&x"32D0",'1'&x"32D1",'1'&x"32D2",'1'&x"32D3",'1'&x"32D4",'1'&x"32D5",'1'&x"32D6",'1'&x"32D7",'1'&x"32D8",'1'&x"32D9",'1'&x"32DA",'1'&x"32DB",'1'&x"32DC",'1'&x"32DD",'1'&x"32DE",'1'&x"32DF",
+--'1'&x"32E0",'1'&x"32E1",'1'&x"32E2",'1'&x"32E3",'1'&x"32E4",'1'&x"32E5",'1'&x"32E6",'1'&x"32E7",'1'&x"32E8",'1'&x"32E9",'1'&x"32EA",'1'&x"32EB",'1'&x"32EC",'1'&x"32ED",'1'&x"32EE",'1'&x"32EF",
+--'1'&x"32F0",'1'&x"32F1",'1'&x"32F2",'1'&x"32F3",'1'&x"32F4",'1'&x"32F5",'1'&x"32F6",'1'&x"32F7",'1'&x"32F8",'1'&x"32F9",'1'&x"32FA",'1'&x"32FB",'1'&x"32FC",'1'&x"32FD",'1'&x"32FE",'1'&x"32FF",
+--'1'&x"3300",'1'&x"3301",'1'&x"3302",'1'&x"3303",'1'&x"3304",'1'&x"3305",'1'&x"3306",'1'&x"3307",'1'&x"3308",'1'&x"3309",'1'&x"330A",'1'&x"330B",'1'&x"330C",'1'&x"330D",'1'&x"330E",'1'&x"330F",
+--'1'&x"3310",'1'&x"3311",'1'&x"3312",'1'&x"3313",'1'&x"3314",'1'&x"3315",'1'&x"3316",'1'&x"3317",'1'&x"3318",'1'&x"3319",'1'&x"331A",'1'&x"331B",'1'&x"331C",'1'&x"331D",'1'&x"331E",'1'&x"331F",
+--'1'&x"3320",'1'&x"3321",'1'&x"3322",'1'&x"3323",'1'&x"3324",'1'&x"3325",'1'&x"3326",'1'&x"3327",'1'&x"3328",'1'&x"3329",'1'&x"332A",'1'&x"332B",'1'&x"332C",'1'&x"332D",'1'&x"332E",'1'&x"332F",
+--'1'&x"3330",'1'&x"3331",'1'&x"3332",'1'&x"3333",'1'&x"3334",'1'&x"3335",'1'&x"3336",'1'&x"3337",'1'&x"3338",'1'&x"3339",'1'&x"333A",'1'&x"333B",'1'&x"333C",'1'&x"333D",'1'&x"333E",'1'&x"333F",
+--'1'&x"3340",'1'&x"3341",'1'&x"3342",'1'&x"3343",'1'&x"3344",'1'&x"3345",'1'&x"3346",'1'&x"3347",'1'&x"3348",'1'&x"3349",'1'&x"334A",'1'&x"334B",'1'&x"334C",'1'&x"334D",'1'&x"334E",'1'&x"334F",
+--'1'&x"3350",'1'&x"3351",'1'&x"3352",'1'&x"3353",'1'&x"3354",'1'&x"3355",'1'&x"3356",'1'&x"3357",'1'&x"3358",'1'&x"3359",'1'&x"335A",'1'&x"335B",'1'&x"335C",'1'&x"335D",'1'&x"335E",'1'&x"335F",
+--'1'&x"3360",'1'&x"3361",'1'&x"3362",'1'&x"3363",'1'&x"3364",'1'&x"3365",'1'&x"3366",'1'&x"3367",'1'&x"3368",'1'&x"3369",'1'&x"336A",'1'&x"336B",'1'&x"336C",'1'&x"336D",'1'&x"336E",'1'&x"336F",
+--'1'&x"3370",'1'&x"3371",'1'&x"3372",'1'&x"3373",'1'&x"3374",'1'&x"3375",'1'&x"3376",'1'&x"3377",'1'&x"3378",'1'&x"3379",'1'&x"337A",'1'&x"337B",'1'&x"337C",'1'&x"337D",'1'&x"337E",'1'&x"337F",
+--'1'&x"3380",'1'&x"3381",'1'&x"3382",'1'&x"3383",'1'&x"3384",'1'&x"3385",'1'&x"3386",'1'&x"3387",'1'&x"3388",'1'&x"3389",'1'&x"338A",'1'&x"338B",'1'&x"338C",'1'&x"338D",'1'&x"338E",'1'&x"338F",
+--'1'&x"3390",'1'&x"3391",'1'&x"3392",'1'&x"3393",'1'&x"3394",'1'&x"3395",'1'&x"3396",'1'&x"3397",'1'&x"3398",'1'&x"3399",'1'&x"339A",'1'&x"339B",'1'&x"339C",'1'&x"339D",'1'&x"339E",'1'&x"339F",
+--'1'&x"33A0",'1'&x"33A1",'1'&x"33A2",'1'&x"33A3",'1'&x"33A4",'1'&x"33A5",'1'&x"33A6",'1'&x"33A7",'1'&x"33A8",'1'&x"33A9",'1'&x"33AA",'1'&x"33AB",'1'&x"33AC",'1'&x"33AD",'1'&x"33AE",'1'&x"33AF",
+--'1'&x"33B0",'1'&x"33B1",'1'&x"33B2",'1'&x"33B3",'1'&x"33B4",'1'&x"33B5",'1'&x"33B6",'1'&x"33B7",'1'&x"33B8",'1'&x"33B9",'1'&x"33BA",'1'&x"33BB",'1'&x"33BC",'1'&x"33BD",'1'&x"33BE",'1'&x"33BF",
+--'1'&x"33C0",'1'&x"33C1",'1'&x"33C2",'1'&x"33C3",'1'&x"33C4",'1'&x"33C5",'1'&x"33C6",'1'&x"33C7",'1'&x"33C8",'1'&x"33C9",'1'&x"33CA",'1'&x"33CB",'1'&x"33CC",'1'&x"33CD",'1'&x"33CE",'1'&x"33CF",
+--'1'&x"33D0",'1'&x"33D1",'1'&x"33D2",'1'&x"33D3",'1'&x"33D4",'1'&x"33D5",'1'&x"33D6",'1'&x"33D7",'1'&x"33D8",'1'&x"33D9",'1'&x"33DA",'1'&x"33DB",'1'&x"33DC",'1'&x"33DD",'1'&x"33DE",'1'&x"33DF",
+--'1'&x"33E0",'1'&x"33E1",'1'&x"33E2",'1'&x"33E3",'1'&x"33E4",'1'&x"33E5",'1'&x"33E6",'1'&x"33E7",'1'&x"33E8",'1'&x"33E9",'1'&x"33EA",'1'&x"33EB",'1'&x"33EC",'1'&x"33ED",'1'&x"33EE",'1'&x"33EF",
+--'1'&x"33F0",'1'&x"33F1",'1'&x"33F2",'1'&x"33F3",'1'&x"33F4",'1'&x"33F5",'1'&x"33F6",'1'&x"33F7",'1'&x"33F8",'1'&x"33F9",'1'&x"33FA",'1'&x"33FB",'1'&x"33FC",'1'&x"33FD",'1'&x"33FE",'1'&x"33FF",
+--'1'&x"3400",'1'&x"3401",'1'&x"3402",'1'&x"3403",'1'&x"3404",'1'&x"3405",'1'&x"3406",'1'&x"3407",'1'&x"3408",'1'&x"3409",'1'&x"340A",'1'&x"340B",'1'&x"340C",'1'&x"340D",'1'&x"340E",'1'&x"340F",
+--'1'&x"3410",'1'&x"3411",'1'&x"3412",'1'&x"3413",'1'&x"3414",'1'&x"3415",'1'&x"3416",'1'&x"3417",'1'&x"3418",'1'&x"3419",'1'&x"341A",'1'&x"341B",'1'&x"341C",'1'&x"341D",'1'&x"341E",'1'&x"341F",
+--'1'&x"3420",'1'&x"3421",'1'&x"3422",'1'&x"3423",'1'&x"3424",'1'&x"3425",'1'&x"3426",'1'&x"3427",'1'&x"3428",'1'&x"3429",'1'&x"342A",'1'&x"342B",'1'&x"342C",'1'&x"342D",'1'&x"342E",'1'&x"342F",
+--'1'&x"3430",'1'&x"3431",'1'&x"3432",'1'&x"3433",'1'&x"3434",'1'&x"3435",'1'&x"3436",'1'&x"3437",'1'&x"3438",'1'&x"3439",'1'&x"343A",'1'&x"343B",'1'&x"343C",'1'&x"343D",'1'&x"343E",'1'&x"343F",
+--'1'&x"3440",'1'&x"3441",'1'&x"3442",'1'&x"3443",'1'&x"3444",'1'&x"3445",'1'&x"3446",'1'&x"3447",'1'&x"3448",'1'&x"3449",'1'&x"344A",'1'&x"344B",'1'&x"344C",'1'&x"344D",'1'&x"344E",'1'&x"344F",
+--'1'&x"3450",'1'&x"3451",'1'&x"3452",'1'&x"3453",'1'&x"3454",'1'&x"3455",'1'&x"3456",'1'&x"3457",'1'&x"3458",'1'&x"3459",'1'&x"345A",'1'&x"345B",'1'&x"345C",'1'&x"345D",'1'&x"345E",'1'&x"345F",
+--'1'&x"3460",'1'&x"3461",'1'&x"3462",'1'&x"3463",'1'&x"3464",'1'&x"3465",'1'&x"3466",'1'&x"3467",'1'&x"3468",'1'&x"3469",'1'&x"346A",'1'&x"346B",'1'&x"346C",'1'&x"346D",'1'&x"346E",'1'&x"346F",
+--'1'&x"3470",'1'&x"3471",'1'&x"3472",'1'&x"3473",'1'&x"3474",'1'&x"3475",'1'&x"3476",'1'&x"3477",'1'&x"3478",'1'&x"3479",'1'&x"347A",'1'&x"347B",'1'&x"347C",'1'&x"347D",'1'&x"347E",'1'&x"347F",
+--'1'&x"3480",'1'&x"3481",'1'&x"3482",'1'&x"3483",'1'&x"3484",'1'&x"3485",'1'&x"3486",'1'&x"3487",'1'&x"3488",'1'&x"3489",'1'&x"348A",'1'&x"348B",'1'&x"348C",'1'&x"348D",'1'&x"348E",'1'&x"348F",
+--'1'&x"3490",'1'&x"3491",'1'&x"3492",'1'&x"3493",'1'&x"3494",'1'&x"3495",'1'&x"3496",'1'&x"3497",'1'&x"3498",'1'&x"3499",'1'&x"349A",'1'&x"349B",'1'&x"349C",'1'&x"349D",'1'&x"349E",'1'&x"349F",
+--'1'&x"34A0",'1'&x"34A1",'1'&x"34A2",'1'&x"34A3",'1'&x"34A4",'1'&x"34A5",'1'&x"34A6",'1'&x"34A7",'1'&x"34A8",'1'&x"34A9",'1'&x"34AA",'1'&x"34AB",'1'&x"34AC",'1'&x"34AD",'1'&x"34AE",'1'&x"34AF",
+--'1'&x"34B0",'1'&x"34B1",'1'&x"34B2",'1'&x"34B3",'1'&x"34B4",'1'&x"34B5",'1'&x"34B6",'1'&x"34B7",'1'&x"34B8",'1'&x"34B9",'1'&x"34BA",'1'&x"34BB",'1'&x"34BC",'1'&x"34BD",'1'&x"34BE",'1'&x"34BF",
+--'1'&x"34C0",'1'&x"34C1",'1'&x"34C2",'1'&x"34C3",'1'&x"34C4",'1'&x"34C5",'1'&x"34C6",'1'&x"34C7",'1'&x"34C8",'1'&x"34C9",'1'&x"34CA",'1'&x"34CB",'1'&x"34CC",'1'&x"34CD",'1'&x"34CE",'1'&x"34CF",
+--'1'&x"34D0",'1'&x"34D1",'1'&x"34D2",'1'&x"34D3",'1'&x"34D4",'1'&x"34D5",'1'&x"34D6",'1'&x"34D7",'1'&x"34D8",'1'&x"34D9",'1'&x"34DA",'1'&x"34DB",'1'&x"34DC",'1'&x"34DD",'1'&x"34DE",'1'&x"34DF",
+--'1'&x"34E0",'1'&x"34E1",'1'&x"34E2",'1'&x"34E3",'1'&x"34E4",'1'&x"34E5",'1'&x"34E6",'1'&x"34E7",'1'&x"34E8",'1'&x"34E9",'1'&x"34EA",'1'&x"34EB",'1'&x"34EC",'1'&x"34ED",'1'&x"34EE",'1'&x"34EF",
+--'1'&x"34F0",'1'&x"34F1",'1'&x"34F2",'1'&x"34F3",'1'&x"34F4",'1'&x"34F5",'1'&x"34F6",'1'&x"34F7",'1'&x"34F8",'1'&x"34F9",'1'&x"34FA",'1'&x"34FB",'1'&x"34FC",'1'&x"34FD",'1'&x"34FE",'1'&x"34FF",
+--'1'&x"3500",'1'&x"3501",'1'&x"3502",'1'&x"3503",'1'&x"3504",'1'&x"3505",'1'&x"3506",'1'&x"3507",'1'&x"3508",'1'&x"3509",'1'&x"350A",'1'&x"350B",'1'&x"350C",'1'&x"350D",'1'&x"350E",'1'&x"350F",
+--'1'&x"3510",'1'&x"3511",'1'&x"3512",'1'&x"3513",'1'&x"3514",'1'&x"3515",'1'&x"3516",'1'&x"3517",'1'&x"3518",'1'&x"3519",'1'&x"351A",'1'&x"351B",'1'&x"351C",'1'&x"351D",'1'&x"351E",'1'&x"351F",
+--'1'&x"3520",'1'&x"3521",'1'&x"3522",'1'&x"3523",'1'&x"3524",'1'&x"3525",'1'&x"3526",'1'&x"3527",'1'&x"3528",'1'&x"3529",'1'&x"352A",'1'&x"352B",'1'&x"352C",'1'&x"352D",'1'&x"352E",'1'&x"352F",
+--'1'&x"3530",'1'&x"3531",'1'&x"3532",'1'&x"3533",'1'&x"3534",'1'&x"3535",'1'&x"3536",'1'&x"3537",'1'&x"3538",'1'&x"3539",'1'&x"353A",'1'&x"353B",'1'&x"353C",'1'&x"353D",'1'&x"353E",'1'&x"353F",
+--'1'&x"3540",'1'&x"3541",'1'&x"3542",'1'&x"3543",'1'&x"3544",'1'&x"3545",'1'&x"3546",'1'&x"3547",'1'&x"3548",'1'&x"3549",'1'&x"354A",'1'&x"354B",'1'&x"354C",'1'&x"354D",'1'&x"354E",'1'&x"354F",
+--'1'&x"3550",'1'&x"3551",'1'&x"3552",'1'&x"3553",'1'&x"3554",'1'&x"3555",'1'&x"3556",'1'&x"3557",'1'&x"3558",'1'&x"3559",'1'&x"355A",'1'&x"355B",'1'&x"355C",'1'&x"355D",'1'&x"355E",'1'&x"355F",
+--'1'&x"3560",'1'&x"3561",'1'&x"3562",'1'&x"3563",'1'&x"3564",'1'&x"3565",'1'&x"3566",'1'&x"3567",'1'&x"3568",'1'&x"3569",'1'&x"356A",'1'&x"356B",'1'&x"356C",'1'&x"356D",'1'&x"356E",'1'&x"356F",
+--'1'&x"3570",'1'&x"3571",'1'&x"3572",'1'&x"3573",'1'&x"3574",'1'&x"3575",'1'&x"3576",'1'&x"3577",'1'&x"3578",'1'&x"3579",'1'&x"357A",'1'&x"357B",'1'&x"357C",'1'&x"357D",'1'&x"357E",'1'&x"357F",
+--'1'&x"3580",'1'&x"3581",'1'&x"3582",'1'&x"3583",'1'&x"3584",'1'&x"3585",'1'&x"3586",'1'&x"3587",'1'&x"3588",'1'&x"3589",'1'&x"358A",'1'&x"358B",'1'&x"358C",'1'&x"358D",'1'&x"358E",'1'&x"358F",
+--'1'&x"3590",'1'&x"3591",'1'&x"3592",'1'&x"3593",'1'&x"3594",'1'&x"3595",'1'&x"3596",'1'&x"3597",'1'&x"3598",'1'&x"3599",'1'&x"359A",'1'&x"359B",'1'&x"359C",'1'&x"359D",'1'&x"359E",'1'&x"359F",
+--'1'&x"35A0",'1'&x"35A1",'1'&x"35A2",'1'&x"35A3",'1'&x"35A4",'1'&x"35A5",'1'&x"35A6",'1'&x"35A7",'1'&x"35A8",'1'&x"35A9",'1'&x"35AA",'1'&x"35AB",'1'&x"35AC",'1'&x"35AD",'1'&x"35AE",'1'&x"35AF",
+--'1'&x"35B0",'1'&x"35B1",'1'&x"35B2",'1'&x"35B3",'1'&x"35B4",'1'&x"35B5",'1'&x"35B6",'1'&x"35B7",'1'&x"35B8",'1'&x"35B9",'1'&x"35BA",'1'&x"35BB",'1'&x"35BC",'1'&x"35BD",'1'&x"35BE",'1'&x"35BF",
+--'1'&x"35C0",'1'&x"35C1",'1'&x"35C2",'1'&x"35C3",'1'&x"35C4",'1'&x"35C5",'1'&x"35C6",'1'&x"35C7",'1'&x"35C8",'1'&x"35C9",'1'&x"35CA",'1'&x"35CB",'1'&x"35CC",'1'&x"35CD",'1'&x"35CE",'1'&x"35CF",
+--'1'&x"35D0",'1'&x"35D1",'1'&x"35D2",'1'&x"35D3",'1'&x"35D4",'1'&x"35D5",'1'&x"35D6",'1'&x"35D7",'1'&x"35D8",'1'&x"35D9",'1'&x"35DA",'1'&x"35DB",'1'&x"35DC",'1'&x"35DD",'1'&x"35DE",'1'&x"35DF",
+--'1'&x"35E0",'1'&x"35E1",'1'&x"35E2",'1'&x"35E3",'1'&x"35E4",'1'&x"35E5",'1'&x"35E6",'1'&x"35E7",'1'&x"35E8",'1'&x"35E9",'1'&x"35EA",'1'&x"35EB",'1'&x"35EC",'1'&x"35ED",'1'&x"35EE",'1'&x"35EF",
+--'1'&x"35F0",'1'&x"35F1",'1'&x"35F2",'1'&x"35F3",'1'&x"35F4",'1'&x"35F5",'1'&x"35F6",'1'&x"35F7",'1'&x"35F8",'1'&x"35F9",'1'&x"35FA",'1'&x"35FB",'1'&x"35FC",'1'&x"35FD",'1'&x"35FE",'1'&x"35FF",
+--'1'&x"3600",'1'&x"3601",'1'&x"3602",'1'&x"3603",'1'&x"3604",'1'&x"3605",'1'&x"3606",'1'&x"3607",'1'&x"3608",'1'&x"3609",'1'&x"360A",'1'&x"360B",'1'&x"360C",'1'&x"360D",'1'&x"360E",'1'&x"360F",
+--'1'&x"3610",'1'&x"3611",'1'&x"3612",'1'&x"3613",'1'&x"3614",'1'&x"3615",'1'&x"3616",'1'&x"3617",'1'&x"3618",'1'&x"3619",'1'&x"361A",'1'&x"361B",'1'&x"361C",'1'&x"361D",'1'&x"361E",'1'&x"361F",
+--'1'&x"3620",'1'&x"3621",'1'&x"3622",'1'&x"3623",'1'&x"3624",'1'&x"3625",'1'&x"3626",'1'&x"3627",'1'&x"3628",'1'&x"3629",'1'&x"362A",'1'&x"362B",'1'&x"362C",'1'&x"362D",'1'&x"362E",'1'&x"362F",
+--'1'&x"3630",'1'&x"3631",'1'&x"3632",'1'&x"3633",'1'&x"3634",'1'&x"3635",'1'&x"3636",'1'&x"3637",'1'&x"3638",'1'&x"3639",'1'&x"363A",'1'&x"363B",'1'&x"363C",'1'&x"363D",'1'&x"363E",'1'&x"363F",
+--'1'&x"3640",'1'&x"3641",'1'&x"3642",'1'&x"3643",'1'&x"3644",'1'&x"3645",'1'&x"3646",'1'&x"3647",'1'&x"3648",'1'&x"3649",'1'&x"364A",'1'&x"364B",'1'&x"364C",'1'&x"364D",'1'&x"364E",'1'&x"364F",
+--'1'&x"3650",'1'&x"3651",'1'&x"3652",'1'&x"3653",'1'&x"3654",'1'&x"3655",'1'&x"3656",'1'&x"3657",'1'&x"3658",'1'&x"3659",'1'&x"365A",'1'&x"365B",'1'&x"365C",'1'&x"365D",'1'&x"365E",'1'&x"365F",
+--'1'&x"3660",'1'&x"3661",'1'&x"3662",'1'&x"3663",'1'&x"3664",'1'&x"3665",'1'&x"3666",'1'&x"3667",'1'&x"3668",'1'&x"3669",'1'&x"366A",'1'&x"366B",'1'&x"366C",'1'&x"366D",'1'&x"366E",'1'&x"366F",
+--'1'&x"3670",'1'&x"3671",'1'&x"3672",'1'&x"3673",'1'&x"3674",'1'&x"3675",'1'&x"3676",'1'&x"3677",'1'&x"3678",'1'&x"3679",'1'&x"367A",'1'&x"367B",'1'&x"367C",'1'&x"367D",'1'&x"367E",'1'&x"367F",
+--'1'&x"3680",'1'&x"3681",'1'&x"3682",'1'&x"3683",'1'&x"3684",'1'&x"3685",'1'&x"3686",'1'&x"3687",'1'&x"3688",'1'&x"3689",'1'&x"368A",'1'&x"368B",'1'&x"368C",'1'&x"368D",'1'&x"368E",'1'&x"368F",
+--'1'&x"3690",'1'&x"3691",'1'&x"3692",'1'&x"3693",'1'&x"3694",'1'&x"3695",'1'&x"3696",'1'&x"3697",'1'&x"3698",'1'&x"3699",'1'&x"369A",'1'&x"369B",'1'&x"369C",'1'&x"369D",'1'&x"369E",'1'&x"369F",
+--'1'&x"36A0",'1'&x"36A1",'1'&x"36A2",'1'&x"36A3",'1'&x"36A4",'1'&x"36A5",'1'&x"36A6",'1'&x"36A7",'1'&x"36A8",'1'&x"36A9",'1'&x"36AA",'1'&x"36AB",'1'&x"36AC",'1'&x"36AD",'1'&x"36AE",'1'&x"36AF",
+--'1'&x"36B0",'1'&x"36B1",'1'&x"36B2",'1'&x"36B3",'1'&x"36B4",'1'&x"36B5",'1'&x"36B6",'1'&x"36B7",'1'&x"36B8",'1'&x"36B9",'1'&x"36BA",'1'&x"36BB",'1'&x"36BC",'1'&x"36BD",'1'&x"36BE",'1'&x"36BF",
+--'1'&x"36C0",'1'&x"36C1",'1'&x"36C2",'1'&x"36C3",'1'&x"36C4",'1'&x"36C5",'1'&x"36C6",'1'&x"36C7",'1'&x"36C8",'1'&x"36C9",'1'&x"36CA",'1'&x"36CB",'1'&x"36CC",'1'&x"36CD",'1'&x"36CE",'1'&x"36CF",
+--'1'&x"36D0",'1'&x"36D1",'1'&x"36D2",'1'&x"36D3",'1'&x"36D4",'1'&x"36D5",'1'&x"36D6",'1'&x"36D7",'1'&x"36D8",'1'&x"36D9",'1'&x"36DA",'1'&x"36DB",'1'&x"36DC",'1'&x"36DD",'1'&x"36DE",'1'&x"36DF",
+--'1'&x"36E0",'1'&x"36E1",'1'&x"36E2",'1'&x"36E3",'1'&x"36E4",'1'&x"36E5",'1'&x"36E6",'1'&x"36E7",'1'&x"36E8",'1'&x"36E9",'1'&x"36EA",'1'&x"36EB",'1'&x"36EC",'1'&x"36ED",'1'&x"36EE",'1'&x"36EF",
+--'1'&x"36F0",'1'&x"36F1",'1'&x"36F2",'1'&x"36F3",'1'&x"36F4",'1'&x"36F5",'1'&x"36F6",'1'&x"36F7",'1'&x"36F8",'1'&x"36F9",'1'&x"36FA",'1'&x"36FB",'1'&x"36FC",'1'&x"36FD",'1'&x"36FE",'1'&x"36FF",
+--'1'&x"3700",'1'&x"3701",'1'&x"3702",'1'&x"3703",'1'&x"3704",'1'&x"3705",'1'&x"3706",'1'&x"3707",'1'&x"3708",'1'&x"3709",'1'&x"370A",'1'&x"370B",'1'&x"370C",'1'&x"370D",'1'&x"370E",'1'&x"370F",
+--'1'&x"3710",'1'&x"3711",'1'&x"3712",'1'&x"3713",'1'&x"3714",'1'&x"3715",'1'&x"3716",'1'&x"3717",'1'&x"3718",'1'&x"3719",'1'&x"371A",'1'&x"371B",'1'&x"371C",'1'&x"371D",'1'&x"371E",'1'&x"371F",
+--'1'&x"3720",'1'&x"3721",'1'&x"3722",'1'&x"3723",'1'&x"3724",'1'&x"3725",'1'&x"3726",'1'&x"3727",'1'&x"3728",'1'&x"3729",'1'&x"372A",'1'&x"372B",'1'&x"372C",'1'&x"372D",'1'&x"372E",'1'&x"372F",
+--'1'&x"3730",'1'&x"3731",'1'&x"3732",'1'&x"3733",'1'&x"3734",'1'&x"3735",'1'&x"3736",'1'&x"3737",'1'&x"3738",'1'&x"3739",'1'&x"373A",'1'&x"373B",'1'&x"373C",'1'&x"373D",'1'&x"373E",'1'&x"373F",
+--'1'&x"3740",'1'&x"3741",'1'&x"3742",'1'&x"3743",'1'&x"3744",'1'&x"3745",'1'&x"3746",'1'&x"3747",'1'&x"3748",'1'&x"3749",'1'&x"374A",'1'&x"374B",'1'&x"374C",'1'&x"374D",'1'&x"374E",'1'&x"374F",
+--'1'&x"3750",'1'&x"3751",'1'&x"3752",'1'&x"3753",'1'&x"3754",'1'&x"3755",'1'&x"3756",'1'&x"3757",'1'&x"3758",'1'&x"3759",'1'&x"375A",'1'&x"375B",'1'&x"375C",'1'&x"375D",'1'&x"375E",'1'&x"375F",
+--'1'&x"3760",'1'&x"3761",'1'&x"3762",'1'&x"3763",'1'&x"3764",'1'&x"3765",'1'&x"3766",'1'&x"3767",'1'&x"3768",'1'&x"3769",'1'&x"376A",'1'&x"376B",'1'&x"376C",'1'&x"376D",'1'&x"376E",'1'&x"376F",
+--'1'&x"3770",'1'&x"3771",'1'&x"3772",'1'&x"3773",'1'&x"3774",'1'&x"3775",'1'&x"3776",'1'&x"3777",'1'&x"3778",'1'&x"3779",'1'&x"377A",'1'&x"377B",'1'&x"377C",'1'&x"377D",'1'&x"377E",'1'&x"377F",
+--'1'&x"3780",'1'&x"3781",'1'&x"3782",'1'&x"3783",'1'&x"3784",'1'&x"3785",'1'&x"3786",'1'&x"3787",'1'&x"3788",'1'&x"3789",'1'&x"378A",'1'&x"378B",'1'&x"378C",'1'&x"378D",'1'&x"378E",'1'&x"378F",
+--'1'&x"3790",'1'&x"3791",'1'&x"3792",'1'&x"3793",'1'&x"3794",'1'&x"3795",'1'&x"3796",'1'&x"3797",'1'&x"3798",'1'&x"3799",'1'&x"379A",'1'&x"379B",'1'&x"379C",'1'&x"379D",'1'&x"379E",'1'&x"379F",
+--'1'&x"37A0",'1'&x"37A1",'1'&x"37A2",'1'&x"37A3",'1'&x"37A4",'1'&x"37A5",'1'&x"37A6",'1'&x"37A7",'1'&x"37A8",'1'&x"37A9",'1'&x"37AA",'1'&x"37AB",'1'&x"37AC",'1'&x"37AD",'1'&x"37AE",'1'&x"37AF",
+--'1'&x"37B0",'1'&x"37B1",'1'&x"37B2",'1'&x"37B3",'1'&x"37B4",'1'&x"37B5",'1'&x"37B6",'1'&x"37B7",'1'&x"37B8",'1'&x"37B9",'1'&x"37BA",'1'&x"37BB",'1'&x"37BC",'1'&x"37BD",'1'&x"37BE",'1'&x"37BF",
+--'1'&x"37C0",'1'&x"37C1",'1'&x"37C2",'1'&x"37C3",'1'&x"37C4",'1'&x"37C5",'1'&x"37C6",'1'&x"37C7",'1'&x"37C8",'1'&x"37C9",'1'&x"37CA",'1'&x"37CB",'1'&x"37CC",'1'&x"37CD",'1'&x"37CE",'1'&x"37CF",
+--'1'&x"37D0",'1'&x"37D1",'1'&x"37D2",'1'&x"37D3",'1'&x"37D4",'1'&x"37D5",'1'&x"37D6",'1'&x"37D7",'1'&x"37D8",'1'&x"37D9",'1'&x"37DA",'1'&x"37DB",'1'&x"37DC",'1'&x"37DD",'1'&x"37DE",'1'&x"37DF",
+--'1'&x"37E0",'1'&x"37E1",'1'&x"37E2",'1'&x"37E3",'1'&x"37E4",'1'&x"37E5",'1'&x"37E6",'1'&x"37E7",'1'&x"37E8",'1'&x"37E9",'1'&x"37EA",'1'&x"37EB",'1'&x"37EC",'1'&x"37ED",'1'&x"37EE",'1'&x"37EF",
+--'1'&x"37F0",'1'&x"37F1",'1'&x"37F2",'1'&x"37F3",'1'&x"37F4",'1'&x"37F5",'1'&x"37F6",'1'&x"37F7",'1'&x"37F8",'1'&x"37F9",'1'&x"37FA",'1'&x"37FB",'1'&x"37FC",'1'&x"37FD",'1'&x"37FE",'1'&x"37FF",
+--'1'&x"3800",'1'&x"3801",'1'&x"3802",'1'&x"3803",'1'&x"3804",'1'&x"3805",'1'&x"3806",'1'&x"3807",'1'&x"3808",'1'&x"3809",'1'&x"380A",'1'&x"380B",'1'&x"380C",'1'&x"380D",'1'&x"380E",'1'&x"380F",
+--'1'&x"3810",'1'&x"3811",'1'&x"3812",'1'&x"3813",'1'&x"3814",'1'&x"3815",'1'&x"3816",'1'&x"3817",'1'&x"3818",'1'&x"3819",'1'&x"381A",'1'&x"381B",'1'&x"381C",'1'&x"381D",'1'&x"381E",'1'&x"381F",
+--'1'&x"3820",'1'&x"3821",'1'&x"3822",'1'&x"3823",'1'&x"3824",'1'&x"3825",'1'&x"3826",'1'&x"3827",'1'&x"3828",'1'&x"3829",'1'&x"382A",'1'&x"382B",'1'&x"382C",'1'&x"382D",'1'&x"382E",'1'&x"382F",
+--'1'&x"3830",'1'&x"3831",'1'&x"3832",'1'&x"3833",'1'&x"3834",'1'&x"3835",'1'&x"3836",'1'&x"3837",'1'&x"3838",'1'&x"3839",'1'&x"383A",'1'&x"383B",'1'&x"383C",'1'&x"383D",'1'&x"383E",'1'&x"383F",
+--'1'&x"3840",'1'&x"3841",'1'&x"3842",'1'&x"3843",'1'&x"3844",'1'&x"3845",'1'&x"3846",'1'&x"3847",'1'&x"3848",'1'&x"3849",'1'&x"384A",'1'&x"384B",'1'&x"384C",'1'&x"384D",'1'&x"384E",'1'&x"384F",
+--'1'&x"3850",'1'&x"3851",'1'&x"3852",'1'&x"3853",'1'&x"3854",'1'&x"3855",'1'&x"3856",'1'&x"3857",'1'&x"3858",'1'&x"3859",'1'&x"385A",'1'&x"385B",'1'&x"385C",'1'&x"385D",'1'&x"385E",'1'&x"385F",
+--'1'&x"3860",'1'&x"3861",'1'&x"3862",'1'&x"3863",'1'&x"3864",'1'&x"3865",'1'&x"3866",'1'&x"3867",'1'&x"3868",'1'&x"3869",'1'&x"386A",'1'&x"386B",'1'&x"386C",'1'&x"386D",'1'&x"386E",'1'&x"386F",
+--'1'&x"3870",'1'&x"3871",'1'&x"3872",'1'&x"3873",'1'&x"3874",'1'&x"3875",'1'&x"3876",'1'&x"3877",'1'&x"3878",'1'&x"3879",'1'&x"387A",'1'&x"387B",'1'&x"387C",'1'&x"387D",'1'&x"387E",'1'&x"387F",
+--'1'&x"3880",'1'&x"3881",'1'&x"3882",'1'&x"3883",'1'&x"3884",'1'&x"3885",'1'&x"3886",'1'&x"3887",'1'&x"3888",'1'&x"3889",'1'&x"388A",'1'&x"388B",'1'&x"388C",'1'&x"388D",'1'&x"388E",'1'&x"388F",
+--'1'&x"3890",'1'&x"3891",'1'&x"3892",'1'&x"3893",'1'&x"3894",'1'&x"3895",'1'&x"3896",'1'&x"3897",'1'&x"3898",'1'&x"3899",'1'&x"389A",'1'&x"389B",'1'&x"389C",'1'&x"389D",'1'&x"389E",'1'&x"389F",
+--'1'&x"38A0",'1'&x"38A1",'1'&x"38A2",'1'&x"38A3",'1'&x"38A4",'1'&x"38A5",'1'&x"38A6",'1'&x"38A7",'1'&x"38A8",'1'&x"38A9",'1'&x"38AA",'1'&x"38AB",'1'&x"38AC",'1'&x"38AD",'1'&x"38AE",'1'&x"38AF",
+--'1'&x"38B0",'1'&x"38B1",'1'&x"38B2",'1'&x"38B3",'1'&x"38B4",'1'&x"38B5",'1'&x"38B6",'1'&x"38B7",'1'&x"38B8",'1'&x"38B9",'1'&x"38BA",'1'&x"38BB",'1'&x"38BC",'1'&x"38BD",'1'&x"38BE",'1'&x"38BF",
+--'1'&x"38C0",'1'&x"38C1",'1'&x"38C2",'1'&x"38C3",'1'&x"38C4",'1'&x"38C5",'1'&x"38C6",'1'&x"38C7",'1'&x"38C8",'1'&x"38C9",'1'&x"38CA",'1'&x"38CB",'1'&x"38CC",'1'&x"38CD",'1'&x"38CE",'1'&x"38CF",
+--'1'&x"38D0",'1'&x"38D1",'1'&x"38D2",'1'&x"38D3",'1'&x"38D4",'1'&x"38D5",'1'&x"38D6",'1'&x"38D7",'1'&x"38D8",'1'&x"38D9",'1'&x"38DA",'1'&x"38DB",'1'&x"38DC",'1'&x"38DD",'1'&x"38DE",'1'&x"38DF",
+--'1'&x"38E0",'1'&x"38E1",'1'&x"38E2",'1'&x"38E3",'1'&x"38E4",'1'&x"38E5",'1'&x"38E6",'1'&x"38E7",'1'&x"38E8",'1'&x"38E9",'1'&x"38EA",'1'&x"38EB",'1'&x"38EC",'1'&x"38ED",'1'&x"38EE",'1'&x"38EF",
+--'1'&x"38F0",'1'&x"38F1",'1'&x"38F2",'1'&x"38F3",'1'&x"38F4",'1'&x"38F5",'1'&x"38F6",'1'&x"38F7",'1'&x"38F8",'1'&x"38F9",'1'&x"38FA",'1'&x"38FB",'1'&x"38FC",'1'&x"38FD",'1'&x"38FE",'1'&x"38FF",
+--'1'&x"3900",'1'&x"3901",'1'&x"3902",'1'&x"3903",'1'&x"3904",'1'&x"3905",'1'&x"3906",'1'&x"3907",'1'&x"3908",'1'&x"3909",'1'&x"390A",'1'&x"390B",'1'&x"390C",'1'&x"390D",'1'&x"390E",'1'&x"390F",
+--'1'&x"3910",'1'&x"3911",'1'&x"3912",'1'&x"3913",'1'&x"3914",'1'&x"3915",'1'&x"3916",'1'&x"3917",'1'&x"3918",'1'&x"3919",'1'&x"391A",'1'&x"391B",'1'&x"391C",'1'&x"391D",'1'&x"391E",'1'&x"391F",
+--'1'&x"3920",'1'&x"3921",'1'&x"3922",'1'&x"3923",'1'&x"3924",'1'&x"3925",'1'&x"3926",'1'&x"3927",'1'&x"3928",'1'&x"3929",'1'&x"392A",'1'&x"392B",'1'&x"392C",'1'&x"392D",'1'&x"392E",'1'&x"392F",
+--'1'&x"3930",'1'&x"3931",'1'&x"3932",'1'&x"3933",'1'&x"3934",'1'&x"3935",'1'&x"3936",'1'&x"3937",'1'&x"3938",'1'&x"3939",'1'&x"393A",'1'&x"393B",'1'&x"393C",'1'&x"393D",'1'&x"393E",'1'&x"393F",
+--'1'&x"3940",'1'&x"3941",'1'&x"3942",'1'&x"3943",'1'&x"3944",'1'&x"3945",'1'&x"3946",'1'&x"3947",'1'&x"3948",'1'&x"3949",'1'&x"394A",'1'&x"394B",'1'&x"394C",'1'&x"394D",'1'&x"394E",'1'&x"394F",
+--'1'&x"3950",'1'&x"3951",'1'&x"3952",'1'&x"3953",'1'&x"3954",'1'&x"3955",'1'&x"3956",'1'&x"3957",'1'&x"3958",'1'&x"3959",'1'&x"395A",'1'&x"395B",'1'&x"395C",'1'&x"395D",'1'&x"395E",'1'&x"395F",
+--'1'&x"3960",'1'&x"3961",'1'&x"3962",'1'&x"3963",'1'&x"3964",'1'&x"3965",'1'&x"3966",'1'&x"3967",'1'&x"3968",'1'&x"3969",'1'&x"396A",'1'&x"396B",'1'&x"396C",'1'&x"396D",'1'&x"396E",'1'&x"396F",
+--'1'&x"3970",'1'&x"3971",'1'&x"3972",'1'&x"3973",'1'&x"3974",'1'&x"3975",'1'&x"3976",'1'&x"3977",'1'&x"3978",'1'&x"3979",'1'&x"397A",'1'&x"397B",'1'&x"397C",'1'&x"397D",'1'&x"397E",'1'&x"397F",
+--'1'&x"3980",'1'&x"3981",'1'&x"3982",'1'&x"3983",'1'&x"3984",'1'&x"3985",'1'&x"3986",'1'&x"3987",'1'&x"3988",'1'&x"3989",'1'&x"398A",'1'&x"398B",'1'&x"398C",'1'&x"398D",'1'&x"398E",'1'&x"398F",
+--'1'&x"3990",'1'&x"3991",'1'&x"3992",'1'&x"3993",'1'&x"3994",'1'&x"3995",'1'&x"3996",'1'&x"3997",'1'&x"3998",'1'&x"3999",'1'&x"399A",'1'&x"399B",'1'&x"399C",'1'&x"399D",'1'&x"399E",'1'&x"399F",
+--'1'&x"39A0",'1'&x"39A1",'1'&x"39A2",'1'&x"39A3",'1'&x"39A4",'1'&x"39A5",'1'&x"39A6",'1'&x"39A7",'1'&x"39A8",'1'&x"39A9",'1'&x"39AA",'1'&x"39AB",'1'&x"39AC",'1'&x"39AD",'1'&x"39AE",'1'&x"39AF",
+--'1'&x"39B0",'1'&x"39B1",'1'&x"39B2",'1'&x"39B3",'1'&x"39B4",'1'&x"39B5",'1'&x"39B6",'1'&x"39B7",'1'&x"39B8",'1'&x"39B9",'1'&x"39BA",'1'&x"39BB",'1'&x"39BC",'1'&x"39BD",'1'&x"39BE",'1'&x"39BF",
+--'1'&x"39C0",'1'&x"39C1",'1'&x"39C2",'1'&x"39C3",'1'&x"39C4",'1'&x"39C5",'1'&x"39C6",'1'&x"39C7",'1'&x"39C8",'1'&x"39C9",'1'&x"39CA",'1'&x"39CB",'1'&x"39CC",'1'&x"39CD",'1'&x"39CE",'1'&x"39CF",
+--'1'&x"39D0",'1'&x"39D1",'1'&x"39D2",'1'&x"39D3",'1'&x"39D4",'1'&x"39D5",'1'&x"39D6",'1'&x"39D7",'1'&x"39D8",'1'&x"39D9",'1'&x"39DA",'1'&x"39DB",'1'&x"39DC",'1'&x"39DD",'1'&x"39DE",'1'&x"39DF",
+--'1'&x"39E0",'1'&x"39E1",'1'&x"39E2",'1'&x"39E3",'1'&x"39E4",'1'&x"39E5",'1'&x"39E6",'1'&x"39E7",'1'&x"39E8",'1'&x"39E9",'1'&x"39EA",'1'&x"39EB",'1'&x"39EC",'1'&x"39ED",'1'&x"39EE",'1'&x"39EF",
+--'1'&x"39F0",'1'&x"39F1",'1'&x"39F2",'1'&x"39F3",'1'&x"39F4",'1'&x"39F5",'1'&x"39F6",'1'&x"39F7",'1'&x"39F8",'1'&x"39F9",'1'&x"39FA",'1'&x"39FB",'1'&x"39FC",'1'&x"39FD",'1'&x"39FE",'1'&x"39FF",
+--'1'&x"3A00",'1'&x"3A01",'1'&x"3A02",'1'&x"3A03",'1'&x"3A04",'1'&x"3A05",'1'&x"3A06",'1'&x"3A07",'1'&x"3A08",'1'&x"3A09",'1'&x"3A0A",'1'&x"3A0B",'1'&x"3A0C",'1'&x"3A0D",'1'&x"3A0E",'1'&x"3A0F",
+--'1'&x"3A10",'1'&x"3A11",'1'&x"3A12",'1'&x"3A13",'1'&x"3A14",'1'&x"3A15",'1'&x"3A16",'1'&x"3A17",'1'&x"3A18",'1'&x"3A19",'1'&x"3A1A",'1'&x"3A1B",'1'&x"3A1C",'1'&x"3A1D",'1'&x"3A1E",'1'&x"3A1F",
+--'1'&x"3A20",'1'&x"3A21",'1'&x"3A22",'1'&x"3A23",'1'&x"3A24",'1'&x"3A25",'1'&x"3A26",'1'&x"3A27",'1'&x"3A28",'1'&x"3A29",'1'&x"3A2A",'1'&x"3A2B",'1'&x"3A2C",'1'&x"3A2D",'1'&x"3A2E",'1'&x"3A2F",
+--'1'&x"3A30",'1'&x"3A31",'1'&x"3A32",'1'&x"3A33",'1'&x"3A34",'1'&x"3A35",'1'&x"3A36",'1'&x"3A37",'1'&x"3A38",'1'&x"3A39",'1'&x"3A3A",'1'&x"3A3B",'1'&x"3A3C",'1'&x"3A3D",'1'&x"3A3E",'1'&x"3A3F",
+--'1'&x"3A40",'1'&x"3A41",'1'&x"3A42",'1'&x"3A43",'1'&x"3A44",'1'&x"3A45",'1'&x"3A46",'1'&x"3A47",'1'&x"3A48",'1'&x"3A49",'1'&x"3A4A",'1'&x"3A4B",'1'&x"3A4C",'1'&x"3A4D",'1'&x"3A4E",'1'&x"3A4F",
+--'1'&x"3A50",'1'&x"3A51",'1'&x"3A52",'1'&x"3A53",'1'&x"3A54",'1'&x"3A55",'1'&x"3A56",'1'&x"3A57",'1'&x"3A58",'1'&x"3A59",'1'&x"3A5A",'1'&x"3A5B",'1'&x"3A5C",'1'&x"3A5D",'1'&x"3A5E",'1'&x"3A5F",
+--'1'&x"3A60",'1'&x"3A61",'1'&x"3A62",'1'&x"3A63",'1'&x"3A64",'1'&x"3A65",'1'&x"3A66",'1'&x"3A67",'1'&x"3A68",'1'&x"3A69",'1'&x"3A6A",'1'&x"3A6B",'1'&x"3A6C",'1'&x"3A6D",'1'&x"3A6E",'1'&x"3A6F",
+--'1'&x"3A70",'1'&x"3A71",'1'&x"3A72",'1'&x"3A73",'1'&x"3A74",'1'&x"3A75",'1'&x"3A76",'1'&x"3A77",'1'&x"3A78",'1'&x"3A79",'1'&x"3A7A",'1'&x"3A7B",'1'&x"3A7C",'1'&x"3A7D",'1'&x"3A7E",'1'&x"3A7F",
+--'1'&x"3A80",'1'&x"3A81",'1'&x"3A82",'1'&x"3A83",'1'&x"3A84",'1'&x"3A85",'1'&x"3A86",'1'&x"3A87",'1'&x"3A88",'1'&x"3A89",'1'&x"3A8A",'1'&x"3A8B",'1'&x"3A8C",'1'&x"3A8D",'1'&x"3A8E",'1'&x"3A8F",
+--'1'&x"3A90",'1'&x"3A91",'1'&x"3A92",'1'&x"3A93",'1'&x"3A94",'1'&x"3A95",'1'&x"3A96",'1'&x"3A97",'1'&x"3A98",'1'&x"3A99",'1'&x"3A9A",'1'&x"3A9B",'1'&x"3A9C",'1'&x"3A9D",'1'&x"3A9E",'1'&x"3A9F",
+--'1'&x"3AA0",'1'&x"3AA1",'1'&x"3AA2",'1'&x"3AA3",'1'&x"3AA4",'1'&x"3AA5",'1'&x"3AA6",'1'&x"3AA7",'1'&x"3AA8",'1'&x"3AA9",'1'&x"3AAA",'1'&x"3AAB",'1'&x"3AAC",'1'&x"3AAD",'1'&x"3AAE",'1'&x"3AAF",
+--'1'&x"3AB0",'1'&x"3AB1",'1'&x"3AB2",'1'&x"3AB3",'1'&x"3AB4",'1'&x"3AB5",'1'&x"3AB6",'1'&x"3AB7",'1'&x"3AB8",'1'&x"3AB9",'1'&x"3ABA",'1'&x"3ABB",'1'&x"3ABC",'1'&x"3ABD",'1'&x"3ABE",'1'&x"3ABF",
+--'1'&x"3AC0",'1'&x"3AC1",'1'&x"3AC2",'1'&x"3AC3",'1'&x"3AC4",'1'&x"3AC5",'1'&x"3AC6",'1'&x"3AC7",'1'&x"3AC8",'1'&x"3AC9",'1'&x"3ACA",'1'&x"3ACB",'1'&x"3ACC",'1'&x"3ACD",'1'&x"3ACE",'1'&x"3ACF",
+--'1'&x"3AD0",'1'&x"3AD1",'1'&x"3AD2",'1'&x"3AD3",'1'&x"3AD4",'1'&x"3AD5",'1'&x"3AD6",'1'&x"3AD7",'1'&x"3AD8",'1'&x"3AD9",'1'&x"3ADA",'1'&x"3ADB",'1'&x"3ADC",'1'&x"3ADD",'1'&x"3ADE",'1'&x"3ADF",
+--'1'&x"3AE0",'1'&x"3AE1",'1'&x"3AE2",'1'&x"3AE3",'1'&x"3AE4",'1'&x"3AE5",'1'&x"3AE6",'1'&x"3AE7",'1'&x"3AE8",'1'&x"3AE9",'1'&x"3AEA",'1'&x"3AEB",'1'&x"3AEC",'1'&x"3AED",'1'&x"3AEE",'1'&x"3AEF",
+--'1'&x"3AF0",'1'&x"3AF1",'1'&x"3AF2",'1'&x"3AF3",'1'&x"3AF4",'1'&x"3AF5",'1'&x"3AF6",'1'&x"3AF7",'1'&x"3AF8",'1'&x"3AF9",'1'&x"3AFA",'1'&x"3AFB",'1'&x"3AFC",'1'&x"3AFD",'1'&x"3AFE",'1'&x"3AFF",
+--'1'&x"3B00",'1'&x"3B01",'1'&x"3B02",'1'&x"3B03",'1'&x"3B04",'1'&x"3B05",'1'&x"3B06",'1'&x"3B07",'1'&x"3B08",'1'&x"3B09",'1'&x"3B0A",'1'&x"3B0B",'1'&x"3B0C",'1'&x"3B0D",'1'&x"3B0E",'1'&x"3B0F",
+--'1'&x"3B10",'1'&x"3B11",'1'&x"3B12",'1'&x"3B13",'1'&x"3B14",'1'&x"3B15",'1'&x"3B16",'1'&x"3B17",'1'&x"3B18",'1'&x"3B19",'1'&x"3B1A",'1'&x"3B1B",'1'&x"3B1C",'1'&x"3B1D",'1'&x"3B1E",'1'&x"3B1F",
+--'1'&x"3B20",'1'&x"3B21",'1'&x"3B22",'1'&x"3B23",'1'&x"3B24",'1'&x"3B25",'1'&x"3B26",'1'&x"3B27",'1'&x"3B28",'1'&x"3B29",'1'&x"3B2A",'1'&x"3B2B",'1'&x"3B2C",'1'&x"3B2D",'1'&x"3B2E",'1'&x"3B2F",
+--'1'&x"3B30",'1'&x"3B31",'1'&x"3B32",'1'&x"3B33",'1'&x"3B34",'1'&x"3B35",'1'&x"3B36",'1'&x"3B37",'1'&x"3B38",'1'&x"3B39",'1'&x"3B3A",'1'&x"3B3B",'1'&x"3B3C",'1'&x"3B3D",'1'&x"3B3E",'1'&x"3B3F",
+--'1'&x"3B40",'1'&x"3B41",'1'&x"3B42",'1'&x"3B43",'1'&x"3B44",'1'&x"3B45",'1'&x"3B46",'1'&x"3B47",'1'&x"3B48",'1'&x"3B49",'1'&x"3B4A",'1'&x"3B4B",'1'&x"3B4C",'1'&x"3B4D",'1'&x"3B4E",'1'&x"3B4F",
+--'1'&x"3B50",'1'&x"3B51",'1'&x"3B52",'1'&x"3B53",'1'&x"3B54",'1'&x"3B55",'1'&x"3B56",'1'&x"3B57",'1'&x"3B58",'1'&x"3B59",'1'&x"3B5A",'1'&x"3B5B",'1'&x"3B5C",'1'&x"3B5D",'1'&x"3B5E",'1'&x"3B5F",
+--'1'&x"3B60",'1'&x"3B61",'1'&x"3B62",'1'&x"3B63",'1'&x"3B64",'1'&x"3B65",'1'&x"3B66",'1'&x"3B67",'1'&x"3B68",'1'&x"3B69",'1'&x"3B6A",'1'&x"3B6B",'1'&x"3B6C",'1'&x"3B6D",'1'&x"3B6E",'1'&x"3B6F",
+--'1'&x"3B70",'1'&x"3B71",'1'&x"3B72",'1'&x"3B73",'1'&x"3B74",'1'&x"3B75",'1'&x"3B76",'1'&x"3B77",'1'&x"3B78",'1'&x"3B79",'1'&x"3B7A",'1'&x"3B7B",'1'&x"3B7C",'1'&x"3B7D",'1'&x"3B7E",'1'&x"3B7F",
+--'1'&x"3B80",'1'&x"3B81",'1'&x"3B82",'1'&x"3B83",'1'&x"3B84",'1'&x"3B85",'1'&x"3B86",'1'&x"3B87",'1'&x"3B88",'1'&x"3B89",'1'&x"3B8A",'1'&x"3B8B",'1'&x"3B8C",'1'&x"3B8D",'1'&x"3B8E",'1'&x"3B8F",
+--'1'&x"3B90",'1'&x"3B91",'1'&x"3B92",'1'&x"3B93",'1'&x"3B94",'1'&x"3B95",'1'&x"3B96",'1'&x"3B97",'1'&x"3B98",'1'&x"3B99",'1'&x"3B9A",'1'&x"3B9B",'1'&x"3B9C",'1'&x"3B9D",'1'&x"3B9E",'1'&x"3B9F",
+--'1'&x"3BA0",'1'&x"3BA1",'1'&x"3BA2",'1'&x"3BA3",'1'&x"3BA4",'1'&x"3BA5",'1'&x"3BA6",'1'&x"3BA7",'1'&x"3BA8",'1'&x"3BA9",'1'&x"3BAA",'1'&x"3BAB",'1'&x"3BAC",'1'&x"3BAD",'1'&x"3BAE",'1'&x"3BAF",
+--'1'&x"3BB0",'1'&x"3BB1",'1'&x"3BB2",'1'&x"3BB3",'1'&x"3BB4",'1'&x"3BB5",'1'&x"3BB6",'1'&x"3BB7",'1'&x"3BB8",'1'&x"3BB9",'1'&x"3BBA",'1'&x"3BBB",'1'&x"3BBC",'1'&x"3BBD",'1'&x"3BBE",'1'&x"3BBF",
+--'1'&x"3BC0",'1'&x"3BC1",'1'&x"3BC2",'1'&x"3BC3",'1'&x"3BC4",'1'&x"3BC5",'1'&x"3BC6",'1'&x"3BC7",'1'&x"3BC8",'1'&x"3BC9",'1'&x"3BCA",'1'&x"3BCB",'1'&x"3BCC",'1'&x"3BCD",'1'&x"3BCE",'1'&x"3BCF",
+--'1'&x"3BD0",'1'&x"3BD1",'1'&x"3BD2",'1'&x"3BD3",'1'&x"3BD4",'1'&x"3BD5",'1'&x"3BD6",'1'&x"3BD7",'1'&x"3BD8",'1'&x"3BD9",'1'&x"3BDA",'1'&x"3BDB",'1'&x"3BDC",'1'&x"3BDD",'1'&x"3BDE",'1'&x"3BDF",
+--'1'&x"3BE0",'1'&x"3BE1",'1'&x"3BE2",'1'&x"3BE3",'1'&x"3BE4",'1'&x"3BE5",'1'&x"3BE6",'1'&x"3BE7",'1'&x"3BE8",'1'&x"3BE9",'1'&x"3BEA",'1'&x"3BEB",'1'&x"3BEC",'1'&x"3BED",'1'&x"3BEE",'1'&x"3BEF",
+--'1'&x"3BF0",'1'&x"3BF1",'1'&x"3BF2",'1'&x"3BF3",'1'&x"3BF4",'1'&x"3BF5",'1'&x"3BF6",'1'&x"3BF7",'1'&x"3BF8",'1'&x"3BF9",'1'&x"3BFA",'1'&x"3BFB",'1'&x"3BFC",'1'&x"3BFD",'1'&x"3BFE",'1'&x"3BFF",
+--'1'&x"3C00",'1'&x"3C01",'1'&x"3C02",'1'&x"3C03",'1'&x"3C04",'1'&x"3C05",'1'&x"3C06",'1'&x"3C07",'1'&x"3C08",'1'&x"3C09",'1'&x"3C0A",'1'&x"3C0B",'1'&x"3C0C",'1'&x"3C0D",'1'&x"3C0E",'1'&x"3C0F",
+--'1'&x"3C10",'1'&x"3C11",'1'&x"3C12",'1'&x"3C13",'1'&x"3C14",'1'&x"3C15",'1'&x"3C16",'1'&x"3C17",'1'&x"3C18",'1'&x"3C19",'1'&x"3C1A",'1'&x"3C1B",'1'&x"3C1C",'1'&x"3C1D",'1'&x"3C1E",'1'&x"3C1F",
+--'1'&x"3C20",'1'&x"3C21",'1'&x"3C22",'1'&x"3C23",'1'&x"3C24",'1'&x"3C25",'1'&x"3C26",'1'&x"3C27",'1'&x"3C28",'1'&x"3C29",'1'&x"3C2A",'1'&x"3C2B",'1'&x"3C2C",'1'&x"3C2D",'1'&x"3C2E",'1'&x"3C2F",
+--'1'&x"3C30",'1'&x"3C31",'1'&x"3C32",'1'&x"3C33",'1'&x"3C34",'1'&x"3C35",'1'&x"3C36",'1'&x"3C37",'1'&x"3C38",'1'&x"3C39",'1'&x"3C3A",'1'&x"3C3B",'1'&x"3C3C",'1'&x"3C3D",'1'&x"3C3E",'1'&x"3C3F",
+--'1'&x"3C40",'1'&x"3C41",'1'&x"3C42",'1'&x"3C43",'1'&x"3C44",'1'&x"3C45",'1'&x"3C46",'1'&x"3C47",'1'&x"3C48",'1'&x"3C49",'1'&x"3C4A",'1'&x"3C4B",'1'&x"3C4C",'1'&x"3C4D",'1'&x"3C4E",'1'&x"3C4F",
+--'1'&x"3C50",'1'&x"3C51",'1'&x"3C52",'1'&x"3C53",'1'&x"3C54",'1'&x"3C55",'1'&x"3C56",'1'&x"3C57",'1'&x"3C58",'1'&x"3C59",'1'&x"3C5A",'1'&x"3C5B",'1'&x"3C5C",'1'&x"3C5D",'1'&x"3C5E",'1'&x"3C5F",
+--'1'&x"3C60",'1'&x"3C61",'1'&x"3C62",'1'&x"3C63",'1'&x"3C64",'1'&x"3C65",'1'&x"3C66",'1'&x"3C67",'1'&x"3C68",'1'&x"3C69",'1'&x"3C6A",'1'&x"3C6B",'1'&x"3C6C",'1'&x"3C6D",'1'&x"3C6E",'1'&x"3C6F",
+--'1'&x"3C70",'1'&x"3C71",'1'&x"3C72",'1'&x"3C73",'1'&x"3C74",'1'&x"3C75",'1'&x"3C76",'1'&x"3C77",'1'&x"3C78",'1'&x"3C79",'1'&x"3C7A",'1'&x"3C7B",'1'&x"3C7C",'1'&x"3C7D",'1'&x"3C7E",'1'&x"3C7F",
+--'1'&x"3C80",'1'&x"3C81",'1'&x"3C82",'1'&x"3C83",'1'&x"3C84",'1'&x"3C85",'1'&x"3C86",'1'&x"3C87",'1'&x"3C88",'1'&x"3C89",'1'&x"3C8A",'1'&x"3C8B",'1'&x"3C8C",'1'&x"3C8D",'1'&x"3C8E",'1'&x"3C8F",
+--'1'&x"3C90",'1'&x"3C91",'1'&x"3C92",'1'&x"3C93",'1'&x"3C94",'1'&x"3C95",'1'&x"3C96",'1'&x"3C97",'1'&x"3C98",'1'&x"3C99",'1'&x"3C9A",'1'&x"3C9B",'1'&x"3C9C",'1'&x"3C9D",'1'&x"3C9E",'1'&x"3C9F",
+--'1'&x"3CA0",'1'&x"3CA1",'1'&x"3CA2",'1'&x"3CA3",'1'&x"3CA4",'1'&x"3CA5",'1'&x"3CA6",'1'&x"3CA7",'1'&x"3CA8",'1'&x"3CA9",'1'&x"3CAA",'1'&x"3CAB",'1'&x"3CAC",'1'&x"3CAD",'1'&x"3CAE",'1'&x"3CAF",
+--'1'&x"3CB0",'1'&x"3CB1",'1'&x"3CB2",'1'&x"3CB3",'1'&x"3CB4",'1'&x"3CB5",'1'&x"3CB6",'1'&x"3CB7",'1'&x"3CB8",'1'&x"3CB9",'1'&x"3CBA",'1'&x"3CBB",'1'&x"3CBC",'1'&x"3CBD",'1'&x"3CBE",'1'&x"3CBF",
+--'1'&x"3CC0",'1'&x"3CC1",'1'&x"3CC2",'1'&x"3CC3",'1'&x"3CC4",'1'&x"3CC5",'1'&x"3CC6",'1'&x"3CC7",'1'&x"3CC8",'1'&x"3CC9",'1'&x"3CCA",'1'&x"3CCB",'1'&x"3CCC",'1'&x"3CCD",'1'&x"3CCE",'1'&x"3CCF",
+--'1'&x"3CD0",'1'&x"3CD1",'1'&x"3CD2",'1'&x"3CD3",'1'&x"3CD4",'1'&x"3CD5",'1'&x"3CD6",'1'&x"3CD7",'1'&x"3CD8",'1'&x"3CD9",'1'&x"3CDA",'1'&x"3CDB",'1'&x"3CDC",'1'&x"3CDD",'1'&x"3CDE",'1'&x"3CDF",
+--'1'&x"3CE0",'1'&x"3CE1",'1'&x"3CE2",'1'&x"3CE3",'1'&x"3CE4",'1'&x"3CE5",'1'&x"3CE6",'1'&x"3CE7",'1'&x"3CE8",'1'&x"3CE9",'1'&x"3CEA",'1'&x"3CEB",'1'&x"3CEC",'1'&x"3CED",'1'&x"3CEE",'1'&x"3CEF",
+--'1'&x"3CF0",'1'&x"3CF1",'1'&x"3CF2",'1'&x"3CF3",'1'&x"3CF4",'1'&x"3CF5",'1'&x"3CF6",'1'&x"3CF7",'1'&x"3CF8",'1'&x"3CF9",'1'&x"3CFA",'1'&x"3CFB",'1'&x"3CFC",'1'&x"3CFD",'1'&x"3CFE",'1'&x"3CFF",
+--'1'&x"3D00",'1'&x"3D01",'1'&x"3D02",'1'&x"3D03",'1'&x"3D04",'1'&x"3D05",'1'&x"3D06",'1'&x"3D07",'1'&x"3D08",'1'&x"3D09",'1'&x"3D0A",'1'&x"3D0B",'1'&x"3D0C",'1'&x"3D0D",'1'&x"3D0E",'1'&x"3D0F",
+--'1'&x"3D10",'1'&x"3D11",'1'&x"3D12",'1'&x"3D13",'1'&x"3D14",'1'&x"3D15",'1'&x"3D16",'1'&x"3D17",'1'&x"3D18",'1'&x"3D19",'1'&x"3D1A",'1'&x"3D1B",'1'&x"3D1C",'1'&x"3D1D",'1'&x"3D1E",'1'&x"3D1F",
+--'1'&x"3D20",'1'&x"3D21",'1'&x"3D22",'1'&x"3D23",'1'&x"3D24",'1'&x"3D25",'1'&x"3D26",'1'&x"3D27",'1'&x"3D28",'1'&x"3D29",'1'&x"3D2A",'1'&x"3D2B",'1'&x"3D2C",'1'&x"3D2D",'1'&x"3D2E",'1'&x"3D2F",
+--'1'&x"3D30",'1'&x"3D31",'1'&x"3D32",'1'&x"3D33",'1'&x"3D34",'1'&x"3D35",'1'&x"3D36",'1'&x"3D37",'1'&x"3D38",'1'&x"3D39",'1'&x"3D3A",'1'&x"3D3B",'1'&x"3D3C",'1'&x"3D3D",'1'&x"3D3E",'1'&x"3D3F",
+--'1'&x"3D40",'1'&x"3D41",'1'&x"3D42",'1'&x"3D43",'1'&x"3D44",'1'&x"3D45",'1'&x"3D46",'1'&x"3D47",'1'&x"3D48",'1'&x"3D49",'1'&x"3D4A",'1'&x"3D4B",'1'&x"3D4C",'1'&x"3D4D",'1'&x"3D4E",'1'&x"3D4F",
+--'1'&x"3D50",'1'&x"3D51",'1'&x"3D52",'1'&x"3D53",'1'&x"3D54",'1'&x"3D55",'1'&x"3D56",'1'&x"3D57",'1'&x"3D58",'1'&x"3D59",'1'&x"3D5A",'1'&x"3D5B",'1'&x"3D5C",'1'&x"3D5D",'1'&x"3D5E",'1'&x"3D5F",
+--'1'&x"3D60",'1'&x"3D61",'1'&x"3D62",'1'&x"3D63",'1'&x"3D64",'1'&x"3D65",'1'&x"3D66",'1'&x"3D67",'1'&x"3D68",'1'&x"3D69",'1'&x"3D6A",'1'&x"3D6B",'1'&x"3D6C",'1'&x"3D6D",'1'&x"3D6E",'1'&x"3D6F",
+--'1'&x"3D70",'1'&x"3D71",'1'&x"3D72",'1'&x"3D73",'1'&x"3D74",'1'&x"3D75",'1'&x"3D76",'1'&x"3D77",'1'&x"3D78",'1'&x"3D79",'1'&x"3D7A",'1'&x"3D7B",'1'&x"3D7C",'1'&x"3D7D",'1'&x"3D7E",'1'&x"3D7F",
+--'1'&x"3D80",'1'&x"3D81",'1'&x"3D82",'1'&x"3D83",'1'&x"3D84",'1'&x"3D85",'1'&x"3D86",'1'&x"3D87",'1'&x"3D88",'1'&x"3D89",'1'&x"3D8A",'1'&x"3D8B",'1'&x"3D8C",'1'&x"3D8D",'1'&x"3D8E",'1'&x"3D8F",
+--'1'&x"3D90",'1'&x"3D91",'1'&x"3D92",'1'&x"3D93",'1'&x"3D94",'1'&x"3D95",'1'&x"3D96",'1'&x"3D97",'1'&x"3D98",'1'&x"3D99",'1'&x"3D9A",'1'&x"3D9B",'1'&x"3D9C",'1'&x"3D9D",'1'&x"3D9E",'1'&x"3D9F",
+--'1'&x"3DA0",'1'&x"3DA1",'1'&x"3DA2",'1'&x"3DA3",'1'&x"3DA4",'1'&x"3DA5",'1'&x"3DA6",'1'&x"3DA7",'1'&x"3DA8",'1'&x"3DA9",'1'&x"3DAA",'1'&x"3DAB",'1'&x"3DAC",'1'&x"3DAD",'1'&x"3DAE",'1'&x"3DAF",
+--'1'&x"3DB0",'1'&x"3DB1",'1'&x"3DB2",'1'&x"3DB3",'1'&x"3DB4",'1'&x"3DB5",'1'&x"3DB6",'1'&x"3DB7",'1'&x"3DB8",'1'&x"3DB9",'1'&x"3DBA",'1'&x"3DBB",'1'&x"3DBC",'1'&x"3DBD",'1'&x"3DBE",'1'&x"3DBF",
+--'1'&x"3DC0",'1'&x"3DC1",'1'&x"3DC2",'1'&x"3DC3",'1'&x"3DC4",'1'&x"3DC5",'1'&x"3DC6",'1'&x"3DC7",'1'&x"3DC8",'1'&x"3DC9",'1'&x"3DCA",'1'&x"3DCB",'1'&x"3DCC",'1'&x"3DCD",'1'&x"3DCE",'1'&x"3DCF",
+--'1'&x"3DD0",'1'&x"3DD1",'1'&x"3DD2",'1'&x"3DD3",'1'&x"3DD4",'1'&x"3DD5",'1'&x"3DD6",'1'&x"3DD7",'1'&x"3DD8",'1'&x"3DD9",'1'&x"3DDA",'1'&x"3DDB",'1'&x"3DDC",'1'&x"3DDD",'1'&x"3DDE",'1'&x"3DDF",
+--'1'&x"3DE0",'1'&x"3DE1",'1'&x"3DE2",'1'&x"3DE3",'1'&x"3DE4",'1'&x"3DE5",'1'&x"3DE6",'1'&x"3DE7",'1'&x"3DE8",'1'&x"3DE9",'1'&x"3DEA",'1'&x"3DEB",'1'&x"3DEC",'1'&x"3DED",'1'&x"3DEE",'1'&x"3DEF",
+--'1'&x"3DF0",'1'&x"3DF1",'1'&x"3DF2",'1'&x"3DF3",'1'&x"3DF4",'1'&x"3DF5",'1'&x"3DF6",'1'&x"3DF7",'1'&x"3DF8",'1'&x"3DF9",'1'&x"3DFA",'1'&x"3DFB",'1'&x"3DFC",'1'&x"3DFD",'1'&x"3DFE",'1'&x"3DFF",
+--'1'&x"3E00",'1'&x"3E01",'1'&x"3E02",'1'&x"3E03",'1'&x"3E04",'1'&x"3E05",'1'&x"3E06",'1'&x"3E07",'1'&x"3E08",'1'&x"3E09",'1'&x"3E0A",'1'&x"3E0B",'1'&x"3E0C",'1'&x"3E0D",'1'&x"3E0E",'1'&x"3E0F",
+--'1'&x"3E10",'1'&x"3E11",'1'&x"3E12",'1'&x"3E13",'1'&x"3E14",'1'&x"3E15",'1'&x"3E16",'1'&x"3E17",'1'&x"3E18",'1'&x"3E19",'1'&x"3E1A",'1'&x"3E1B",'1'&x"3E1C",'1'&x"3E1D",'1'&x"3E1E",'1'&x"3E1F",
+--'1'&x"3E20",'1'&x"3E21",'1'&x"3E22",'1'&x"3E23",'1'&x"3E24",'1'&x"3E25",'1'&x"3E26",'1'&x"3E27",'1'&x"3E28",'1'&x"3E29",'1'&x"3E2A",'1'&x"3E2B",'1'&x"3E2C",'1'&x"3E2D",'1'&x"3E2E",'1'&x"3E2F",
+--'1'&x"3E30",'1'&x"3E31",'1'&x"3E32",'1'&x"3E33",'1'&x"3E34",'1'&x"3E35",'1'&x"3E36",'1'&x"3E37",'1'&x"3E38",'1'&x"3E39",'1'&x"3E3A",'1'&x"3E3B",'1'&x"3E3C",'1'&x"3E3D",'1'&x"3E3E",'1'&x"3E3F",
+--'1'&x"3E40",'1'&x"3E41",'1'&x"3E42",'1'&x"3E43",'1'&x"3E44",'1'&x"3E45",'1'&x"3E46",'1'&x"3E47",'1'&x"3E48",'1'&x"3E49",'1'&x"3E4A",'1'&x"3E4B",'1'&x"3E4C",'1'&x"3E4D",'1'&x"3E4E",'1'&x"3E4F",
+--'1'&x"3E50",'1'&x"3E51",'1'&x"3E52",'1'&x"3E53",'1'&x"3E54",'1'&x"3E55",'1'&x"3E56",'1'&x"3E57",'1'&x"3E58",'1'&x"3E59",'1'&x"3E5A",'1'&x"3E5B",'1'&x"3E5C",'1'&x"3E5D",'1'&x"3E5E",'1'&x"3E5F",
+--'1'&x"3E60",'1'&x"3E61",'1'&x"3E62",'1'&x"3E63",'1'&x"3E64",'1'&x"3E65",'1'&x"3E66",'1'&x"3E67",'1'&x"3E68",'1'&x"3E69",'1'&x"3E6A",'1'&x"3E6B",'1'&x"3E6C",'1'&x"3E6D",'1'&x"3E6E",'1'&x"3E6F",
+--'1'&x"3E70",'1'&x"3E71",'1'&x"3E72",'1'&x"3E73",'1'&x"3E74",'1'&x"3E75",'1'&x"3E76",'1'&x"3E77",'1'&x"3E78",'1'&x"3E79",'1'&x"3E7A",'1'&x"3E7B",'1'&x"3E7C",'1'&x"3E7D",'1'&x"3E7E",'1'&x"3E7F",
+--'1'&x"3E80",'1'&x"3E81",'1'&x"3E82",'1'&x"3E83",'1'&x"3E84",'1'&x"3E85",'1'&x"3E86",'1'&x"3E87",'1'&x"3E88",'1'&x"3E89",'1'&x"3E8A",'1'&x"3E8B",'1'&x"3E8C",'1'&x"3E8D",'1'&x"3E8E",'1'&x"3E8F",
+--'1'&x"3E90",'1'&x"3E91",'1'&x"3E92",'1'&x"3E93",'1'&x"3E94",'1'&x"3E95",'1'&x"3E96",'1'&x"3E97",'1'&x"3E98",'1'&x"3E99",'1'&x"3E9A",'1'&x"3E9B",'1'&x"3E9C",'1'&x"3E9D",'1'&x"3E9E",'1'&x"3E9F",
+--'1'&x"3EA0",'1'&x"3EA1",'1'&x"3EA2",'1'&x"3EA3",'1'&x"3EA4",'1'&x"3EA5",'1'&x"3EA6",'1'&x"3EA7",'1'&x"3EA8",'1'&x"3EA9",'1'&x"3EAA",'1'&x"3EAB",'1'&x"3EAC",'1'&x"3EAD",'1'&x"3EAE",'1'&x"3EAF",
+--'1'&x"3EB0",'1'&x"3EB1",'1'&x"3EB2",'1'&x"3EB3",'1'&x"3EB4",'1'&x"3EB5",'1'&x"3EB6",'1'&x"3EB7",'1'&x"3EB8",'1'&x"3EB9",'1'&x"3EBA",'1'&x"3EBB",'1'&x"3EBC",'1'&x"3EBD",'1'&x"3EBE",'1'&x"3EBF",
+--'1'&x"3EC0",'1'&x"3EC1",'1'&x"3EC2",'1'&x"3EC3",'1'&x"3EC4",'1'&x"3EC5",'1'&x"3EC6",'1'&x"3EC7",'1'&x"3EC8",'1'&x"3EC9",'1'&x"3ECA",'1'&x"3ECB",'1'&x"3ECC",'1'&x"3ECD",'1'&x"3ECE",'1'&x"3ECF",
+--'1'&x"3ED0",'1'&x"3ED1",'1'&x"3ED2",'1'&x"3ED3",'1'&x"3ED4",'1'&x"3ED5",'1'&x"3ED6",'1'&x"3ED7",'1'&x"3ED8",'1'&x"3ED9",'1'&x"3EDA",'1'&x"3EDB",'1'&x"3EDC",'1'&x"3EDD",'1'&x"3EDE",'1'&x"3EDF",
+--'1'&x"3EE0",'1'&x"3EE1",'1'&x"3EE2",'1'&x"3EE3",'1'&x"3EE4",'1'&x"3EE5",'1'&x"3EE6",'1'&x"3EE7",'1'&x"3EE8",'1'&x"3EE9",'1'&x"3EEA",'1'&x"3EEB",'1'&x"3EEC",'1'&x"3EED",'1'&x"3EEE",'1'&x"3EEF",
+--'1'&x"3EF0",'1'&x"3EF1",'1'&x"3EF2",'1'&x"3EF3",'1'&x"3EF4",'1'&x"3EF5",'1'&x"3EF6",'1'&x"3EF7",'1'&x"3EF8",'1'&x"3EF9",'1'&x"3EFA",'1'&x"3EFB",'1'&x"3EFC",'1'&x"3EFD",'1'&x"3EFE",'1'&x"3EFF",
+--'1'&x"3F00",'1'&x"3F01",'1'&x"3F02",'1'&x"3F03",'1'&x"3F04",'1'&x"3F05",'1'&x"3F06",'1'&x"3F07",'1'&x"3F08",'1'&x"3F09",'1'&x"3F0A",'1'&x"3F0B",'1'&x"3F0C",'1'&x"3F0D",'1'&x"3F0E",'1'&x"3F0F",
+--'1'&x"3F10",'1'&x"3F11",'1'&x"3F12",'1'&x"3F13",'1'&x"3F14",'1'&x"3F15",'1'&x"3F16",'1'&x"3F17",'1'&x"3F18",'1'&x"3F19",'1'&x"3F1A",'1'&x"3F1B",'1'&x"3F1C",'1'&x"3F1D",'1'&x"3F1E",'1'&x"3F1F",
+--'1'&x"3F20",'1'&x"3F21",'1'&x"3F22",'1'&x"3F23",'1'&x"3F24",'1'&x"3F25",'1'&x"3F26",'1'&x"3F27",'1'&x"3F28",'1'&x"3F29",'1'&x"3F2A",'1'&x"3F2B",'1'&x"3F2C",'1'&x"3F2D",'1'&x"3F2E",'1'&x"3F2F",
+--'1'&x"3F30",'1'&x"3F31",'1'&x"3F32",'1'&x"3F33",'1'&x"3F34",'1'&x"3F35",'1'&x"3F36",'1'&x"3F37",'1'&x"3F38",'1'&x"3F39",'1'&x"3F3A",'1'&x"3F3B",'1'&x"3F3C",'1'&x"3F3D",'1'&x"3F3E",'1'&x"3F3F",
+--'1'&x"3F40",'1'&x"3F41",'1'&x"3F42",'1'&x"3F43",'1'&x"3F44",'1'&x"3F45",'1'&x"3F46",'1'&x"3F47",'1'&x"3F48",'1'&x"3F49",'1'&x"3F4A",'1'&x"3F4B",'1'&x"3F4C",'1'&x"3F4D",'1'&x"3F4E",'1'&x"3F4F",
+--'1'&x"3F50",'1'&x"3F51",'1'&x"3F52",'1'&x"3F53",'1'&x"3F54",'1'&x"3F55",'1'&x"3F56",'1'&x"3F57",'1'&x"3F58",'1'&x"3F59",'1'&x"3F5A",'1'&x"3F5B",'1'&x"3F5C",'1'&x"3F5D",'1'&x"3F5E",'1'&x"3F5F",
+--'1'&x"3F60",'1'&x"3F61",'1'&x"3F62",'1'&x"3F63",'1'&x"3F64",'1'&x"3F65",'1'&x"3F66",'1'&x"3F67",'1'&x"3F68",'1'&x"3F69",'1'&x"3F6A",'1'&x"3F6B",'1'&x"3F6C",'1'&x"3F6D",'1'&x"3F6E",'1'&x"3F6F",
+--'1'&x"3F70",'1'&x"3F71",'1'&x"3F72",'1'&x"3F73",'1'&x"3F74",'1'&x"3F75",'1'&x"3F76",'1'&x"3F77",'1'&x"3F78",'1'&x"3F79",'1'&x"3F7A",'1'&x"3F7B",'1'&x"3F7C",'1'&x"3F7D",'1'&x"3F7E",'1'&x"3F7F",
+--'1'&x"3F80",'1'&x"3F81",'1'&x"3F82",'1'&x"3F83",'1'&x"3F84",'1'&x"3F85",'1'&x"3F86",'1'&x"3F87",'1'&x"3F88",'1'&x"3F89",'1'&x"3F8A",'1'&x"3F8B",'1'&x"3F8C",'1'&x"3F8D",'1'&x"3F8E",'1'&x"3F8F",
+--'1'&x"3F90",'1'&x"3F91",'1'&x"3F92",'1'&x"3F93",'1'&x"3F94",'1'&x"3F95",'1'&x"3F96",'1'&x"3F97",'1'&x"3F98",'1'&x"3F99",'1'&x"3F9A",'1'&x"3F9B",'1'&x"3F9C",'1'&x"3F9D",'1'&x"3F9E",'1'&x"3F9F",
+--'1'&x"3FA0",'1'&x"3FA1",'1'&x"3FA2",'1'&x"3FA3",'1'&x"3FA4",'1'&x"3FA5",'1'&x"3FA6",'1'&x"3FA7",'1'&x"3FA8",'1'&x"3FA9",'1'&x"3FAA",'1'&x"3FAB",'1'&x"3FAC",'1'&x"3FAD",'1'&x"3FAE",'1'&x"3FAF",
+--'1'&x"3FB0",'1'&x"3FB1",'1'&x"3FB2",'1'&x"3FB3",'1'&x"3FB4",'1'&x"3FB5",'1'&x"3FB6",'1'&x"3FB7",'1'&x"3FB8",'1'&x"3FB9",'1'&x"3FBA",'1'&x"3FBB",'1'&x"3FBC",'1'&x"3FBD",'1'&x"3FBE",'1'&x"3FBF",
+--'1'&x"3FC0",'1'&x"3FC1",'1'&x"3FC2",'1'&x"3FC3",'1'&x"3FC4",'1'&x"3FC5",'1'&x"3FC6",'1'&x"3FC7",'1'&x"3FC8",'1'&x"3FC9",'1'&x"3FCA",'1'&x"3FCB",'1'&x"3FCC",'1'&x"3FCD",'1'&x"3FCE",'1'&x"3FCF",
+--'1'&x"3FD0",'1'&x"3FD1",'1'&x"3FD2",'1'&x"3FD3",'1'&x"3FD4",'1'&x"3FD5",'1'&x"3FD6",'1'&x"3FD7",'1'&x"3FD8",'1'&x"3FD9",'1'&x"3FDA",'1'&x"3FDB",'1'&x"3FDC",'1'&x"3FDD",'1'&x"3FDE",'1'&x"3FDF",
+--'1'&x"3FE0",'1'&x"3FE1",'1'&x"3FE2",'1'&x"3FE3",'1'&x"3FE4",'1'&x"3FE5",'1'&x"3FE6",'1'&x"3FE7",'1'&x"3FE8",'1'&x"3FE9",'1'&x"3FEA",'1'&x"3FEB",'1'&x"3FEC",'1'&x"3FED",'1'&x"3FEE",'1'&x"3FEF",
+--'1'&x"3FF0",'1'&x"3FF1",'1'&x"3FF2",'1'&x"3FF3",'1'&x"3FF4",'1'&x"3FF5",'1'&x"3FF6",'1'&x"3FF7",'1'&x"3FF8",'1'&x"3FF9",'1'&x"3FFA",'1'&x"3FFB",'1'&x"3FFC",'1'&x"3FFD",'1'&x"3FFE",'1'&x"3FFF",
+--'1'&x"4000",'1'&x"4001",'1'&x"4002",'1'&x"4003",'1'&x"4004",'1'&x"4005",'1'&x"4006",'1'&x"4007",'1'&x"4008",'1'&x"4009",'1'&x"400A",'1'&x"400B",'1'&x"400C",'1'&x"400D",'1'&x"400E",'1'&x"400F",
+--'1'&x"4010",'1'&x"4011",'1'&x"4012",'1'&x"4013",'1'&x"4014",'1'&x"4015",'1'&x"4016",'1'&x"4017",'1'&x"4018",'1'&x"4019",'1'&x"401A",'1'&x"401B",'1'&x"401C",'1'&x"401D",'1'&x"401E",'1'&x"401F",
+--'1'&x"4020",'1'&x"4021",'1'&x"4022",'1'&x"4023",'1'&x"4024",'1'&x"4025",'1'&x"4026",'1'&x"4027",'1'&x"4028",'1'&x"4029",'1'&x"402A",'1'&x"402B",'1'&x"402C",'1'&x"402D",'1'&x"402E",'1'&x"402F",
+--'1'&x"4030",'1'&x"4031",'1'&x"4032",'1'&x"4033",'1'&x"4034",'1'&x"4035",'1'&x"4036",'1'&x"4037",'1'&x"4038",'1'&x"4039",'1'&x"403A",'1'&x"403B",'1'&x"403C",'1'&x"403D",'1'&x"403E",'1'&x"403F",
+--'1'&x"4040",'1'&x"4041",'1'&x"4042",'1'&x"4043",'1'&x"4044",'1'&x"4045",'1'&x"4046",'1'&x"4047",'1'&x"4048",'1'&x"4049",'1'&x"404A",'1'&x"404B",'1'&x"404C",'1'&x"404D",'1'&x"404E",'1'&x"404F",
+--'1'&x"4050",'1'&x"4051",'1'&x"4052",'1'&x"4053",'1'&x"4054",'1'&x"4055",'1'&x"4056",'1'&x"4057",'1'&x"4058",'1'&x"4059",'1'&x"405A",'1'&x"405B",'1'&x"405C",'1'&x"405D",'1'&x"405E",'1'&x"405F",
+--'1'&x"4060",'1'&x"4061",'1'&x"4062",'1'&x"4063",'1'&x"4064",'1'&x"4065",'1'&x"4066",'1'&x"4067",'1'&x"4068",'1'&x"4069",'1'&x"406A",'1'&x"406B",'1'&x"406C",'1'&x"406D",'1'&x"406E",'1'&x"406F",
+--'1'&x"4070",'1'&x"4071",'1'&x"4072",'1'&x"4073",'1'&x"4074",'1'&x"4075",'1'&x"4076",'1'&x"4077",'1'&x"4078",'1'&x"4079",'1'&x"407A",'1'&x"407B",'1'&x"407C",'1'&x"407D",'1'&x"407E",'1'&x"407F",
+--'1'&x"4080",'1'&x"4081",'1'&x"4082",'1'&x"4083",'1'&x"4084",'1'&x"4085",'1'&x"4086",'1'&x"4087",'1'&x"4088",'1'&x"4089",'1'&x"408A",'1'&x"408B",'1'&x"408C",'1'&x"408D",'1'&x"408E",'1'&x"408F",
+--'1'&x"4090",'1'&x"4091",'1'&x"4092",'1'&x"4093",'1'&x"4094",'1'&x"4095",'1'&x"4096",'1'&x"4097",'1'&x"4098",'1'&x"4099",'1'&x"409A",'1'&x"409B",'1'&x"409C",'1'&x"409D",'1'&x"409E",'1'&x"409F",
+--'1'&x"40A0",'1'&x"40A1",'1'&x"40A2",'1'&x"40A3",'1'&x"40A4",'1'&x"40A5",'1'&x"40A6",'1'&x"40A7",'1'&x"40A8",'1'&x"40A9",'1'&x"40AA",'1'&x"40AB",'1'&x"40AC",'1'&x"40AD",'1'&x"40AE",'1'&x"40AF",
+--'1'&x"40B0",'1'&x"40B1",'1'&x"40B2",'1'&x"40B3",'1'&x"40B4",'1'&x"40B5",'1'&x"40B6",'1'&x"40B7",'1'&x"40B8",'1'&x"40B9",'1'&x"40BA",'1'&x"40BB",'1'&x"40BC",'1'&x"40BD",'1'&x"40BE",'1'&x"40BF",
+--'1'&x"40C0",'1'&x"40C1",'1'&x"40C2",'1'&x"40C3",'1'&x"40C4",'1'&x"40C5",'1'&x"40C6",'1'&x"40C7",'1'&x"40C8",'1'&x"40C9",'1'&x"40CA",'1'&x"40CB",'1'&x"40CC",'1'&x"40CD",'1'&x"40CE",'1'&x"40CF",
+--'1'&x"40D0",'1'&x"40D1",'1'&x"40D2",'1'&x"40D3",'1'&x"40D4",'1'&x"40D5",'1'&x"40D6",'1'&x"40D7",'1'&x"40D8",'1'&x"40D9",'1'&x"40DA",'1'&x"40DB",'1'&x"40DC",'1'&x"40DD",'1'&x"40DE",'1'&x"40DF",
+--'1'&x"40E0",'1'&x"40E1",'1'&x"40E2",'1'&x"40E3",'1'&x"40E4",'1'&x"40E5",'1'&x"40E6",'1'&x"40E7",'1'&x"40E8",'1'&x"40E9",'1'&x"40EA",'1'&x"40EB",'1'&x"40EC",'1'&x"40ED",'1'&x"40EE",'1'&x"40EF",
+--'1'&x"40F0",'1'&x"40F1",'1'&x"40F2",'1'&x"40F3",'1'&x"40F4",'1'&x"40F5",'1'&x"40F6",'1'&x"40F7",'1'&x"40F8",'1'&x"40F9",'1'&x"40FA",'1'&x"40FB",'1'&x"40FC",'1'&x"40FD",'1'&x"40FE",'1'&x"40FF",
+--'1'&x"4100",'1'&x"4101",'1'&x"4102",'1'&x"4103",'1'&x"4104",'1'&x"4105",'1'&x"4106",'1'&x"4107",'1'&x"4108",'1'&x"4109",'1'&x"410A",'1'&x"410B",'1'&x"410C",'1'&x"410D",'1'&x"410E",'1'&x"410F",
+--'1'&x"4110",'1'&x"4111",'1'&x"4112",'1'&x"4113",'1'&x"4114",'1'&x"4115",'1'&x"4116",'1'&x"4117",'1'&x"4118",'1'&x"4119",'1'&x"411A",'1'&x"411B",'1'&x"411C",'1'&x"411D",'1'&x"411E",'1'&x"411F",
+--'1'&x"4120",'1'&x"4121",'1'&x"4122",'1'&x"4123",'1'&x"4124",'1'&x"4125",'1'&x"4126",'1'&x"4127",'1'&x"4128",'1'&x"4129",'1'&x"412A",'1'&x"412B",'1'&x"412C",'1'&x"412D",'1'&x"412E",'1'&x"412F",
+--'1'&x"4130",'1'&x"4131",'1'&x"4132",'1'&x"4133",'1'&x"4134",'1'&x"4135",'1'&x"4136",'1'&x"4137",'1'&x"4138",'1'&x"4139",'1'&x"413A",'1'&x"413B",'1'&x"413C",'1'&x"413D",'1'&x"413E",'1'&x"413F",
+--'1'&x"4140",'1'&x"4141",'1'&x"4142",'1'&x"4143",'1'&x"4144",'1'&x"4145",'1'&x"4146",'1'&x"4147",'1'&x"4148",'1'&x"4149",'1'&x"414A",'1'&x"414B",'1'&x"414C",'1'&x"414D",'1'&x"414E",'1'&x"414F",
+--'1'&x"4150",'1'&x"4151",'1'&x"4152",'1'&x"4153",'1'&x"4154",'1'&x"4155",'1'&x"4156",'1'&x"4157",'1'&x"4158",'1'&x"4159",'1'&x"415A",'1'&x"415B",'1'&x"415C",'1'&x"415D",'1'&x"415E",'1'&x"415F",
+--'1'&x"4160",'1'&x"4161",'1'&x"4162",'1'&x"4163",'1'&x"4164",'1'&x"4165",'1'&x"4166",'1'&x"4167",'1'&x"4168",'1'&x"4169",'1'&x"416A",'1'&x"416B",'1'&x"416C",'1'&x"416D",'1'&x"416E",'1'&x"416F",
+--'1'&x"4170",'1'&x"4171",'1'&x"4172",'1'&x"4173",'1'&x"4174",'1'&x"4175",'1'&x"4176",'1'&x"4177",'1'&x"4178",'1'&x"4179",'1'&x"417A",'1'&x"417B",'1'&x"417C",'1'&x"417D",'1'&x"417E",'1'&x"417F",
+--'1'&x"4180",'1'&x"4181",'1'&x"4182",'1'&x"4183",'1'&x"4184",'1'&x"4185",'1'&x"4186",'1'&x"4187",'1'&x"4188",'1'&x"4189",'1'&x"418A",'1'&x"418B",'1'&x"418C",'1'&x"418D",'1'&x"418E",'1'&x"418F",
+--'1'&x"4190",'1'&x"4191",'1'&x"4192",'1'&x"4193",'1'&x"4194",'1'&x"4195",'1'&x"4196",'1'&x"4197",'1'&x"4198",'1'&x"4199",'1'&x"419A",'1'&x"419B",'1'&x"419C",'1'&x"419D",'1'&x"419E",'1'&x"419F",
+--'1'&x"41A0",'1'&x"41A1",'1'&x"41A2",'1'&x"41A3",'1'&x"41A4",'1'&x"41A5",'1'&x"41A6",'1'&x"41A7",'1'&x"41A8",'1'&x"41A9",'1'&x"41AA",'1'&x"41AB",'1'&x"41AC",'1'&x"41AD",'1'&x"41AE",'1'&x"41AF",
+--'1'&x"41B0",'1'&x"41B1",'1'&x"41B2",'1'&x"41B3",'1'&x"41B4",'1'&x"41B5",'1'&x"41B6",'1'&x"41B7",'1'&x"41B8",'1'&x"41B9",'1'&x"41BA",'1'&x"41BB",'1'&x"41BC",'1'&x"41BD",'1'&x"41BE",'1'&x"41BF",
+--'1'&x"41C0",'1'&x"41C1",'1'&x"41C2",'1'&x"41C3",'1'&x"41C4",'1'&x"41C5",'1'&x"41C6",'1'&x"41C7",'1'&x"41C8",'1'&x"41C9",'1'&x"41CA",'1'&x"41CB",'1'&x"41CC",'1'&x"41CD",'1'&x"41CE",'1'&x"41CF",
+--'1'&x"41D0",'1'&x"41D1",'1'&x"41D2",'1'&x"41D3",'1'&x"41D4",'1'&x"41D5",'1'&x"41D6",'1'&x"41D7",'1'&x"41D8",'1'&x"41D9",'1'&x"41DA",'1'&x"41DB",'1'&x"41DC",'1'&x"41DD",'1'&x"41DE",'1'&x"41DF",
+--'1'&x"41E0",'1'&x"41E1",'1'&x"41E2",'1'&x"41E3",'1'&x"41E4",'1'&x"41E5",'1'&x"41E6",'1'&x"41E7",'1'&x"41E8",'1'&x"41E9",'1'&x"41EA",'1'&x"41EB",'1'&x"41EC",'1'&x"41ED",'1'&x"41EE",'1'&x"41EF",
+--'1'&x"41F0",'1'&x"41F1",'1'&x"41F2",'1'&x"41F3",'1'&x"41F4",'1'&x"41F5",'1'&x"41F6",'1'&x"41F7",'1'&x"41F8",'1'&x"41F9",'1'&x"41FA",'1'&x"41FB",'1'&x"41FC",'1'&x"41FD",'1'&x"41FE",'1'&x"41FF",
+--'1'&x"4200",'1'&x"4201",'1'&x"4202",'1'&x"4203",'1'&x"4204",'1'&x"4205",'1'&x"4206",'1'&x"4207",'1'&x"4208",'1'&x"4209",'1'&x"420A",'1'&x"420B",'1'&x"420C",'1'&x"420D",'1'&x"420E",'1'&x"420F",
+--'1'&x"4210",'1'&x"4211",'1'&x"4212",'1'&x"4213",'1'&x"4214",'1'&x"4215",'1'&x"4216",'1'&x"4217",'1'&x"4218",'1'&x"4219",'1'&x"421A",'1'&x"421B",'1'&x"421C",'1'&x"421D",'1'&x"421E",'1'&x"421F",
+--'1'&x"4220",'1'&x"4221",'1'&x"4222",'1'&x"4223",'1'&x"4224",'1'&x"4225",'1'&x"4226",'1'&x"4227",'1'&x"4228",'1'&x"4229",'1'&x"422A",'1'&x"422B",'1'&x"422C",'1'&x"422D",'1'&x"422E",'1'&x"422F",
+--'1'&x"4230",'1'&x"4231",'1'&x"4232",'1'&x"4233",'1'&x"4234",'1'&x"4235",'1'&x"4236",'1'&x"4237",'1'&x"4238",'1'&x"4239",'1'&x"423A",'1'&x"423B",'1'&x"423C",'1'&x"423D",'1'&x"423E",'1'&x"423F",
+--'1'&x"4240",'1'&x"4241",'1'&x"4242",'1'&x"4243",'1'&x"4244",'1'&x"4245",'1'&x"4246",'1'&x"4247",'1'&x"4248",'1'&x"4249",'1'&x"424A",'1'&x"424B",'1'&x"424C",'1'&x"424D",'1'&x"424E",'1'&x"424F",
+--'1'&x"4250",'1'&x"4251",'1'&x"4252",'1'&x"4253",'1'&x"4254",'1'&x"4255",'1'&x"4256",'1'&x"4257",'1'&x"4258",'1'&x"4259",'1'&x"425A",'1'&x"425B",'1'&x"425C",'1'&x"425D",'1'&x"425E",'1'&x"425F",
+--'1'&x"4260",'1'&x"4261",'1'&x"4262",'1'&x"4263",'1'&x"4264",'1'&x"4265",'1'&x"4266",'1'&x"4267",'1'&x"4268",'1'&x"4269",'1'&x"426A",'1'&x"426B",'1'&x"426C",'1'&x"426D",'1'&x"426E",'1'&x"426F",
+--'1'&x"4270",'1'&x"4271",'1'&x"4272",'1'&x"4273",'1'&x"4274",'1'&x"4275",'1'&x"4276",'1'&x"4277",'1'&x"4278",'1'&x"4279",'1'&x"427A",'1'&x"427B",'1'&x"427C",'1'&x"427D",'1'&x"427E",'1'&x"427F",
+--'1'&x"4280",'1'&x"4281",'1'&x"4282",'1'&x"4283",'1'&x"4284",'1'&x"4285",'1'&x"4286",'1'&x"4287",'1'&x"4288",'1'&x"4289",'1'&x"428A",'1'&x"428B",'1'&x"428C",'1'&x"428D",'1'&x"428E",'1'&x"428F",
+--'1'&x"4290",'1'&x"4291",'1'&x"4292",'1'&x"4293",'1'&x"4294",'1'&x"4295",'1'&x"4296",'1'&x"4297",'1'&x"4298",'1'&x"4299",'1'&x"429A",'1'&x"429B",'1'&x"429C",'1'&x"429D",'1'&x"429E",'1'&x"429F",
+--'1'&x"42A0",'1'&x"42A1",'1'&x"42A2",'1'&x"42A3",'1'&x"42A4",'1'&x"42A5",'1'&x"42A6",'1'&x"42A7",'1'&x"42A8",'1'&x"42A9",'1'&x"42AA",'1'&x"42AB",'1'&x"42AC",'1'&x"42AD",'1'&x"42AE",'1'&x"42AF",
+--'1'&x"42B0",'1'&x"42B1",'1'&x"42B2",'1'&x"42B3",'1'&x"42B4",'1'&x"42B5",'1'&x"42B6",'1'&x"42B7",'1'&x"42B8",'1'&x"42B9",'1'&x"42BA",'1'&x"42BB",'1'&x"42BC",'1'&x"42BD",'1'&x"42BE",'1'&x"42BF",
+--'1'&x"42C0",'1'&x"42C1",'1'&x"42C2",'1'&x"42C3",'1'&x"42C4",'1'&x"42C5",'1'&x"42C6",'1'&x"42C7",'1'&x"42C8",'1'&x"42C9",'1'&x"42CA",'1'&x"42CB",'1'&x"42CC",'1'&x"42CD",'1'&x"42CE",'1'&x"42CF",
+--'1'&x"42D0",'1'&x"42D1",'1'&x"42D2",'1'&x"42D3",'1'&x"42D4",'1'&x"42D5",'1'&x"42D6",'1'&x"42D7",'1'&x"42D8",'1'&x"42D9",'1'&x"42DA",'1'&x"42DB",'1'&x"42DC",'1'&x"42DD",'1'&x"42DE",'1'&x"42DF",
+--'1'&x"42E0",'1'&x"42E1",'1'&x"42E2",'1'&x"42E3",'1'&x"42E4",'1'&x"42E5",'1'&x"42E6",'1'&x"42E7",'1'&x"42E8",'1'&x"42E9",'1'&x"42EA",'1'&x"42EB",'1'&x"42EC",'1'&x"42ED",'1'&x"42EE",'1'&x"42EF",
+--'1'&x"42F0",'1'&x"42F1",'1'&x"42F2",'1'&x"42F3",'1'&x"42F4",'1'&x"42F5",'1'&x"42F6",'1'&x"42F7",'1'&x"42F8",'1'&x"42F9",'1'&x"42FA",'1'&x"42FB",'1'&x"42FC",'1'&x"42FD",'1'&x"42FE",'1'&x"42FF",
+--'1'&x"4300",'1'&x"4301",'1'&x"4302",'1'&x"4303",'1'&x"4304",'1'&x"4305",'1'&x"4306",'1'&x"4307",'1'&x"4308",'1'&x"4309",'1'&x"430A",'1'&x"430B",'1'&x"430C",'1'&x"430D",'1'&x"430E",'1'&x"430F",
+--'1'&x"4310",'1'&x"4311",'1'&x"4312",'1'&x"4313",'1'&x"4314",'1'&x"4315",'1'&x"4316",'1'&x"4317",'1'&x"4318",'1'&x"4319",'1'&x"431A",'1'&x"431B",'1'&x"431C",'1'&x"431D",'1'&x"431E",'1'&x"431F",
+--'1'&x"4320",'1'&x"4321",'1'&x"4322",'1'&x"4323",'1'&x"4324",'1'&x"4325",'1'&x"4326",'1'&x"4327",'1'&x"4328",'1'&x"4329",'1'&x"432A",'1'&x"432B",'1'&x"432C",'1'&x"432D",'1'&x"432E",'1'&x"432F",
+--'1'&x"4330",'1'&x"4331",'1'&x"4332",'1'&x"4333",'1'&x"4334",'1'&x"4335",'1'&x"4336",'1'&x"4337",'1'&x"4338",'1'&x"4339",'1'&x"433A",'1'&x"433B",'1'&x"433C",'1'&x"433D",'1'&x"433E",'1'&x"433F",
+--'1'&x"4340",'1'&x"4341",'1'&x"4342",'1'&x"4343",'1'&x"4344",'1'&x"4345",'1'&x"4346",'1'&x"4347",'1'&x"4348",'1'&x"4349",'1'&x"434A",'1'&x"434B",'1'&x"434C",'1'&x"434D",'1'&x"434E",'1'&x"434F",
+--'1'&x"4350",'1'&x"4351",'1'&x"4352",'1'&x"4353",'1'&x"4354",'1'&x"4355",'1'&x"4356",'1'&x"4357",'1'&x"4358",'1'&x"4359",'1'&x"435A",'1'&x"435B",'1'&x"435C",'1'&x"435D",'1'&x"435E",'1'&x"435F",
+--'1'&x"4360",'1'&x"4361",'1'&x"4362",'1'&x"4363",'1'&x"4364",'1'&x"4365",'1'&x"4366",'1'&x"4367",'1'&x"4368",'1'&x"4369",'1'&x"436A",'1'&x"436B",'1'&x"436C",'1'&x"436D",'1'&x"436E",'1'&x"436F",
+--'1'&x"4370",'1'&x"4371",'1'&x"4372",'1'&x"4373",'1'&x"4374",'1'&x"4375",'1'&x"4376",'1'&x"4377",'1'&x"4378",'1'&x"4379",'1'&x"437A",'1'&x"437B",'1'&x"437C",'1'&x"437D",'1'&x"437E",'1'&x"437F",
+--'1'&x"4380",'1'&x"4381",'1'&x"4382",'1'&x"4383",'1'&x"4384",'1'&x"4385",'1'&x"4386",'1'&x"4387",'1'&x"4388",'1'&x"4389",'1'&x"438A",'1'&x"438B",'1'&x"438C",'1'&x"438D",'1'&x"438E",'1'&x"438F",
+--'1'&x"4390",'1'&x"4391",'1'&x"4392",'1'&x"4393",'1'&x"4394",'1'&x"4395",'1'&x"4396",'1'&x"4397",'1'&x"4398",'1'&x"4399",'1'&x"439A",'1'&x"439B",'1'&x"439C",'1'&x"439D",'1'&x"439E",'1'&x"439F",
+--'1'&x"43A0",'1'&x"43A1",'1'&x"43A2",'1'&x"43A3",'1'&x"43A4",'1'&x"43A5",'1'&x"43A6",'1'&x"43A7",'1'&x"43A8",'1'&x"43A9",'1'&x"43AA",'1'&x"43AB",'1'&x"43AC",'1'&x"43AD",'1'&x"43AE",'1'&x"43AF",
+--'1'&x"43B0",'1'&x"43B1",'1'&x"43B2",'1'&x"43B3",'1'&x"43B4",'1'&x"43B5",'1'&x"43B6",'1'&x"43B7",'1'&x"43B8",'1'&x"43B9",'1'&x"43BA",'1'&x"43BB",'1'&x"43BC",'1'&x"43BD",'1'&x"43BE",'1'&x"43BF",
+--'1'&x"43C0",'1'&x"43C1",'1'&x"43C2",'1'&x"43C3",'1'&x"43C4",'1'&x"43C5",'1'&x"43C6",'1'&x"43C7",'1'&x"43C8",'1'&x"43C9",'1'&x"43CA",'1'&x"43CB",'1'&x"43CC",'1'&x"43CD",'1'&x"43CE",'1'&x"43CF",
+--'1'&x"43D0",'1'&x"43D1",'1'&x"43D2",'1'&x"43D3",'1'&x"43D4",'1'&x"43D5",'1'&x"43D6",'1'&x"43D7",'1'&x"43D8",'1'&x"43D9",'1'&x"43DA",'1'&x"43DB",'1'&x"43DC",'1'&x"43DD",'1'&x"43DE",'1'&x"43DF",
+--'1'&x"43E0",'1'&x"43E1",'1'&x"43E2",'1'&x"43E3",'1'&x"43E4",'1'&x"43E5",'1'&x"43E6",'1'&x"43E7",'1'&x"43E8",'1'&x"43E9",'1'&x"43EA",'1'&x"43EB",'1'&x"43EC",'1'&x"43ED",'1'&x"43EE",'1'&x"43EF",
+--'1'&x"43F0",'1'&x"43F1",'1'&x"43F2",'1'&x"43F3",'1'&x"43F4",'1'&x"43F5",'1'&x"43F6",'1'&x"43F7",'1'&x"43F8",'1'&x"43F9",'1'&x"43FA",'1'&x"43FB",'1'&x"43FC",'1'&x"43FD",'1'&x"43FE",'1'&x"43FF",
+--'1'&x"4400",'1'&x"4401",'1'&x"4402",'1'&x"4403",'1'&x"4404",'1'&x"4405",'1'&x"4406",'1'&x"4407",'1'&x"4408",'1'&x"4409",'1'&x"440A",'1'&x"440B",'1'&x"440C",'1'&x"440D",'1'&x"440E",'1'&x"440F",
+--'1'&x"4410",'1'&x"4411",'1'&x"4412",'1'&x"4413",'1'&x"4414",'1'&x"4415",'1'&x"4416",'1'&x"4417",'1'&x"4418",'1'&x"4419",'1'&x"441A",'1'&x"441B",'1'&x"441C",'1'&x"441D",'1'&x"441E",'1'&x"441F",
+--'1'&x"4420",'1'&x"4421",'1'&x"4422",'1'&x"4423",'1'&x"4424",'1'&x"4425",'1'&x"4426",'1'&x"4427",'1'&x"4428",'1'&x"4429",'1'&x"442A",'1'&x"442B",'1'&x"442C",'1'&x"442D",'1'&x"442E",'1'&x"442F",
+--'1'&x"4430",'1'&x"4431",'1'&x"4432",'1'&x"4433",'1'&x"4434",'1'&x"4435",'1'&x"4436",'1'&x"4437",'1'&x"4438",'1'&x"4439",'1'&x"443A",'1'&x"443B",'1'&x"443C",'1'&x"443D",'1'&x"443E",'1'&x"443F",
+--'1'&x"4440",'1'&x"4441",'1'&x"4442",'1'&x"4443",'1'&x"4444",'1'&x"4445",'1'&x"4446",'1'&x"4447",'1'&x"4448",'1'&x"4449",'1'&x"444A",'1'&x"444B",'1'&x"444C",'1'&x"444D",'1'&x"444E",'1'&x"444F",
+--'1'&x"4450",'1'&x"4451",'1'&x"4452",'1'&x"4453",'1'&x"4454",'1'&x"4455",'1'&x"4456",'1'&x"4457",'1'&x"4458",'1'&x"4459",'1'&x"445A",'1'&x"445B",'1'&x"445C",'1'&x"445D",'1'&x"445E",'1'&x"445F",
+--'1'&x"4460",'1'&x"4461",'1'&x"4462",'1'&x"4463",'1'&x"4464",'1'&x"4465",'1'&x"4466",'1'&x"4467",'1'&x"4468",'1'&x"4469",'1'&x"446A",'1'&x"446B",'1'&x"446C",'1'&x"446D",'1'&x"446E",'1'&x"446F",
+--'1'&x"4470",'1'&x"4471",'1'&x"4472",'1'&x"4473",'1'&x"4474",'1'&x"4475",'1'&x"4476",'1'&x"4477",'1'&x"4478",'1'&x"4479",'1'&x"447A",'1'&x"447B",'1'&x"447C",'1'&x"447D",'1'&x"447E",'1'&x"447F",
+--'1'&x"4480",'1'&x"4481",'1'&x"4482",'1'&x"4483",'1'&x"4484",'1'&x"4485",'1'&x"4486",'1'&x"4487",'1'&x"4488",'1'&x"4489",'1'&x"448A",'1'&x"448B",'1'&x"448C",'1'&x"448D",'1'&x"448E",'1'&x"448F",
+--'1'&x"4490",'1'&x"4491",'1'&x"4492",'1'&x"4493",'1'&x"4494",'1'&x"4495",'1'&x"4496",'1'&x"4497",'1'&x"4498",'1'&x"4499",'1'&x"449A",'1'&x"449B",'1'&x"449C",'1'&x"449D",'1'&x"449E",'1'&x"449F",
+--'1'&x"44A0",'1'&x"44A1",'1'&x"44A2",'1'&x"44A3",'1'&x"44A4",'1'&x"44A5",'1'&x"44A6",'1'&x"44A7",'1'&x"44A8",'1'&x"44A9",'1'&x"44AA",'1'&x"44AB",'1'&x"44AC",'1'&x"44AD",'1'&x"44AE",'1'&x"44AF",
+--'1'&x"44B0",'1'&x"44B1",'1'&x"44B2",'1'&x"44B3",'1'&x"44B4",'1'&x"44B5",'1'&x"44B6",'1'&x"44B7",'1'&x"44B8",'1'&x"44B9",'1'&x"44BA",'1'&x"44BB",'1'&x"44BC",'1'&x"44BD",'1'&x"44BE",'1'&x"44BF",
+--'1'&x"44C0",'1'&x"44C1",'1'&x"44C2",'1'&x"44C3",'1'&x"44C4",'1'&x"44C5",'1'&x"44C6",'1'&x"44C7",'1'&x"44C8",'1'&x"44C9",'1'&x"44CA",'1'&x"44CB",'1'&x"44CC",'1'&x"44CD",'1'&x"44CE",'1'&x"44CF",
+--'1'&x"44D0",'1'&x"44D1",'1'&x"44D2",'1'&x"44D3",'1'&x"44D4",'1'&x"44D5",'1'&x"44D6",'1'&x"44D7",'1'&x"44D8",'1'&x"44D9",'1'&x"44DA",'1'&x"44DB",'1'&x"44DC",'1'&x"44DD",'1'&x"44DE",'1'&x"44DF",
+--'1'&x"44E0",'1'&x"44E1",'1'&x"44E2",'1'&x"44E3",'1'&x"44E4",'1'&x"44E5",'1'&x"44E6",'1'&x"44E7",'1'&x"44E8",'1'&x"44E9",'1'&x"44EA",'1'&x"44EB",'1'&x"44EC",'1'&x"44ED",'1'&x"44EE",'1'&x"44EF",
+--'1'&x"44F0",'1'&x"44F1",'1'&x"44F2",'1'&x"44F3",'1'&x"44F4",'1'&x"44F5",'1'&x"44F6",'1'&x"44F7",'1'&x"44F8",'1'&x"44F9",'1'&x"44FA",'1'&x"44FB",'1'&x"44FC",'1'&x"44FD",'1'&x"44FE",'1'&x"44FF",
+--'1'&x"4500",'1'&x"4501",'1'&x"4502",'1'&x"4503",'1'&x"4504",'1'&x"4505",'1'&x"4506",'1'&x"4507",'1'&x"4508",'1'&x"4509",'1'&x"450A",'1'&x"450B",'1'&x"450C",'1'&x"450D",'1'&x"450E",'1'&x"450F",
+--'1'&x"4510",'1'&x"4511",'1'&x"4512",'1'&x"4513",'1'&x"4514",'1'&x"4515",'1'&x"4516",'1'&x"4517",'1'&x"4518",'1'&x"4519",'1'&x"451A",'1'&x"451B",'1'&x"451C",'1'&x"451D",'1'&x"451E",'1'&x"451F",
+--'1'&x"4520",'1'&x"4521",'1'&x"4522",'1'&x"4523",'1'&x"4524",'1'&x"4525",'1'&x"4526",'1'&x"4527",'1'&x"4528",'1'&x"4529",'1'&x"452A",'1'&x"452B",'1'&x"452C",'1'&x"452D",'1'&x"452E",'1'&x"452F",
+--'1'&x"4530",'1'&x"4531",'1'&x"4532",'1'&x"4533",'1'&x"4534",'1'&x"4535",'1'&x"4536",'1'&x"4537",'1'&x"4538",'1'&x"4539",'1'&x"453A",'1'&x"453B",'1'&x"453C",'1'&x"453D",'1'&x"453E",'1'&x"453F",
+--'1'&x"4540",'1'&x"4541",'1'&x"4542",'1'&x"4543",'1'&x"4544",'1'&x"4545",'1'&x"4546",'1'&x"4547",'1'&x"4548",'1'&x"4549",'1'&x"454A",'1'&x"454B",'1'&x"454C",'1'&x"454D",'1'&x"454E",'1'&x"454F",
+--'1'&x"4550",'1'&x"4551",'1'&x"4552",'1'&x"4553",'1'&x"4554",'1'&x"4555",'1'&x"4556",'1'&x"4557",'1'&x"4558",'1'&x"4559",'1'&x"455A",'1'&x"455B",'1'&x"455C",'1'&x"455D",'1'&x"455E",'1'&x"455F",
+--'1'&x"4560",'1'&x"4561",'1'&x"4562",'1'&x"4563",'1'&x"4564",'1'&x"4565",'1'&x"4566",'1'&x"4567",'1'&x"4568",'1'&x"4569",'1'&x"456A",'1'&x"456B",'1'&x"456C",'1'&x"456D",'1'&x"456E",'1'&x"456F",
+--'1'&x"4570",'1'&x"4571",'1'&x"4572",'1'&x"4573",'1'&x"4574",'1'&x"4575",'1'&x"4576",'1'&x"4577",'1'&x"4578",'1'&x"4579",'1'&x"457A",'1'&x"457B",'1'&x"457C",'1'&x"457D",'1'&x"457E",'1'&x"457F",
+--'1'&x"4580",'1'&x"4581",'1'&x"4582",'1'&x"4583",'1'&x"4584",'1'&x"4585",'1'&x"4586",'1'&x"4587",'1'&x"4588",'1'&x"4589",'1'&x"458A",'1'&x"458B",'1'&x"458C",'1'&x"458D",'1'&x"458E",'1'&x"458F",
+--'1'&x"4590",'1'&x"4591",'1'&x"4592",'1'&x"4593",'1'&x"4594",'1'&x"4595",'1'&x"4596",'1'&x"4597",'1'&x"4598",'1'&x"4599",'1'&x"459A",'1'&x"459B",'1'&x"459C",'1'&x"459D",'1'&x"459E",'1'&x"459F",
+--'1'&x"45A0",'1'&x"45A1",'1'&x"45A2",'1'&x"45A3",'1'&x"45A4",'1'&x"45A5",'1'&x"45A6",'1'&x"45A7",'1'&x"45A8",'1'&x"45A9",'1'&x"45AA",'1'&x"45AB",'1'&x"45AC",'1'&x"45AD",'1'&x"45AE",'1'&x"45AF",
+--'1'&x"45B0",'1'&x"45B1",'1'&x"45B2",'1'&x"45B3",'1'&x"45B4",'1'&x"45B5",'1'&x"45B6",'1'&x"45B7",'1'&x"45B8",'1'&x"45B9",'1'&x"45BA",'1'&x"45BB",'1'&x"45BC",'1'&x"45BD",'1'&x"45BE",'1'&x"45BF",
+--'1'&x"45C0",'1'&x"45C1",'1'&x"45C2",'1'&x"45C3",'1'&x"45C4",'1'&x"45C5",'1'&x"45C6",'1'&x"45C7",'1'&x"45C8",'1'&x"45C9",'1'&x"45CA",'1'&x"45CB",'1'&x"45CC",'1'&x"45CD",'1'&x"45CE",'1'&x"45CF",
+--'1'&x"45D0",'1'&x"45D1",'1'&x"45D2",'1'&x"45D3",'1'&x"45D4",'1'&x"45D5",'1'&x"45D6",'1'&x"45D7",'1'&x"45D8",'1'&x"45D9",'1'&x"45DA",'1'&x"45DB",'1'&x"45DC",'1'&x"45DD",'1'&x"45DE",'1'&x"45DF",
+--'1'&x"45E0",'1'&x"45E1",'1'&x"45E2",'1'&x"45E3",'1'&x"45E4",'1'&x"45E5",'1'&x"45E6",'1'&x"45E7",'1'&x"45E8",'1'&x"45E9",'1'&x"45EA",'1'&x"45EB",'1'&x"45EC",'1'&x"45ED",'1'&x"45EE",'1'&x"45EF",
+--'1'&x"45F0",'1'&x"45F1",'1'&x"45F2",'1'&x"45F3",'1'&x"45F4",'1'&x"45F5",'1'&x"45F6",'1'&x"45F7",'1'&x"45F8",'1'&x"45F9",'1'&x"45FA",'1'&x"45FB",'1'&x"45FC",'1'&x"45FD",'1'&x"45FE",'1'&x"45FF",
+--'1'&x"4600",'1'&x"4601",'1'&x"4602",'1'&x"4603",'1'&x"4604",'1'&x"4605",'1'&x"4606",'1'&x"4607",'1'&x"4608",'1'&x"4609",'1'&x"460A",'1'&x"460B",'1'&x"460C",'1'&x"460D",'1'&x"460E",'1'&x"460F",
+--'1'&x"4610",'1'&x"4611",'1'&x"4612",'1'&x"4613",'1'&x"4614",'1'&x"4615",'1'&x"4616",'1'&x"4617",'1'&x"4618",'1'&x"4619",'1'&x"461A",'1'&x"461B",'1'&x"461C",'1'&x"461D",'1'&x"461E",'1'&x"461F",
+--'1'&x"4620",'1'&x"4621",'1'&x"4622",'1'&x"4623",'1'&x"4624",'1'&x"4625",'1'&x"4626",'1'&x"4627",'1'&x"4628",'1'&x"4629",'1'&x"462A",'1'&x"462B",'1'&x"462C",'1'&x"462D",'1'&x"462E",'1'&x"462F",
+--'1'&x"4630",'1'&x"4631",'1'&x"4632",'1'&x"4633",'1'&x"4634",'1'&x"4635",'1'&x"4636",'1'&x"4637",'1'&x"4638",'1'&x"4639",'1'&x"463A",'1'&x"463B",'1'&x"463C",'1'&x"463D",'1'&x"463E",'1'&x"463F",
+--'1'&x"4640",'1'&x"4641",'1'&x"4642",'1'&x"4643",'1'&x"4644",'1'&x"4645",'1'&x"4646",'1'&x"4647",'1'&x"4648",'1'&x"4649",'1'&x"464A",'1'&x"464B",'1'&x"464C",'1'&x"464D",'1'&x"464E",'1'&x"464F",
+--'1'&x"4650",'1'&x"4651",'1'&x"4652",'1'&x"4653",'1'&x"4654",'1'&x"4655",'1'&x"4656",'1'&x"4657",'1'&x"4658",'1'&x"4659",'1'&x"465A",'1'&x"465B",'1'&x"465C",'1'&x"465D",'1'&x"465E",'1'&x"465F",
+--'1'&x"4660",'1'&x"4661",'1'&x"4662",'1'&x"4663",'1'&x"4664",'1'&x"4665",'1'&x"4666",'1'&x"4667",'1'&x"4668",'1'&x"4669",'1'&x"466A",'1'&x"466B",'1'&x"466C",'1'&x"466D",'1'&x"466E",'1'&x"466F",
+--'1'&x"4670",'1'&x"4671",'1'&x"4672",'1'&x"4673",'1'&x"4674",'1'&x"4675",'1'&x"4676",'1'&x"4677",'1'&x"4678",'1'&x"4679",'1'&x"467A",'1'&x"467B",'1'&x"467C",'1'&x"467D",'1'&x"467E",'1'&x"467F",
+--'1'&x"4680",'1'&x"4681",'1'&x"4682",'1'&x"4683",'1'&x"4684",'1'&x"4685",'1'&x"4686",'1'&x"4687",'1'&x"4688",'1'&x"4689",'1'&x"468A",'1'&x"468B",'1'&x"468C",'1'&x"468D",'1'&x"468E",'1'&x"468F",
+--'1'&x"4690",'1'&x"4691",'1'&x"4692",'1'&x"4693",'1'&x"4694",'1'&x"4695",'1'&x"4696",'1'&x"4697",'1'&x"4698",'1'&x"4699",'1'&x"469A",'1'&x"469B",'1'&x"469C",'1'&x"469D",'1'&x"469E",'1'&x"469F",
+--'1'&x"46A0",'1'&x"46A1",'1'&x"46A2",'1'&x"46A3",'1'&x"46A4",'1'&x"46A5",'1'&x"46A6",'1'&x"46A7",'1'&x"46A8",'1'&x"46A9",'1'&x"46AA",'1'&x"46AB",'1'&x"46AC",'1'&x"46AD",'1'&x"46AE",'1'&x"46AF",
+--'1'&x"46B0",'1'&x"46B1",'1'&x"46B2",'1'&x"46B3",'1'&x"46B4",'1'&x"46B5",'1'&x"46B6",'1'&x"46B7",'1'&x"46B8",'1'&x"46B9",'1'&x"46BA",'1'&x"46BB",'1'&x"46BC",'1'&x"46BD",'1'&x"46BE",'1'&x"46BF",
+--'1'&x"46C0",'1'&x"46C1",'1'&x"46C2",'1'&x"46C3",'1'&x"46C4",'1'&x"46C5",'1'&x"46C6",'1'&x"46C7",'1'&x"46C8",'1'&x"46C9",'1'&x"46CA",'1'&x"46CB",'1'&x"46CC",'1'&x"46CD",'1'&x"46CE",'1'&x"46CF",
+--'1'&x"46D0",'1'&x"46D1",'1'&x"46D2",'1'&x"46D3",'1'&x"46D4",'1'&x"46D5",'1'&x"46D6",'1'&x"46D7",'1'&x"46D8",'1'&x"46D9",'1'&x"46DA",'1'&x"46DB",'1'&x"46DC",'1'&x"46DD",'1'&x"46DE",'1'&x"46DF",
+--'1'&x"46E0",'1'&x"46E1",'1'&x"46E2",'1'&x"46E3",'1'&x"46E4",'1'&x"46E5",'1'&x"46E6",'1'&x"46E7",'1'&x"46E8",'1'&x"46E9",'1'&x"46EA",'1'&x"46EB",'1'&x"46EC",'1'&x"46ED",'1'&x"46EE",'1'&x"46EF",
+--'1'&x"46F0",'1'&x"46F1",'1'&x"46F2",'1'&x"46F3",'1'&x"46F4",'1'&x"46F5",'1'&x"46F6",'1'&x"46F7",'1'&x"46F8",'1'&x"46F9",'1'&x"46FA",'1'&x"46FB",'1'&x"46FC",'1'&x"46FD",'1'&x"46FE",'1'&x"46FF",
+--'1'&x"4700",'1'&x"4701",'1'&x"4702",'1'&x"4703",'1'&x"4704",'1'&x"4705",'1'&x"4706",'1'&x"4707",'1'&x"4708",'1'&x"4709",'1'&x"470A",'1'&x"470B",'1'&x"470C",'1'&x"470D",'1'&x"470E",'1'&x"470F",
+--'1'&x"4710",'1'&x"4711",'1'&x"4712",'1'&x"4713",'1'&x"4714",'1'&x"4715",'1'&x"4716",'1'&x"4717",'1'&x"4718",'1'&x"4719",'1'&x"471A",'1'&x"471B",'1'&x"471C",'1'&x"471D",'1'&x"471E",'1'&x"471F",
+--'1'&x"4720",'1'&x"4721",'1'&x"4722",'1'&x"4723",'1'&x"4724",'1'&x"4725",'1'&x"4726",'1'&x"4727",'1'&x"4728",'1'&x"4729",'1'&x"472A",'1'&x"472B",'1'&x"472C",'1'&x"472D",'1'&x"472E",'1'&x"472F",
+--'1'&x"4730",'1'&x"4731",'1'&x"4732",'1'&x"4733",'1'&x"4734",'1'&x"4735",'1'&x"4736",'1'&x"4737",'1'&x"4738",'1'&x"4739",'1'&x"473A",'1'&x"473B",'1'&x"473C",'1'&x"473D",'1'&x"473E",'1'&x"473F",
+--'1'&x"4740",'1'&x"4741",'1'&x"4742",'1'&x"4743",'1'&x"4744",'1'&x"4745",'1'&x"4746",'1'&x"4747",'1'&x"4748",'1'&x"4749",'1'&x"474A",'1'&x"474B",'1'&x"474C",'1'&x"474D",'1'&x"474E",'1'&x"474F",
+--'1'&x"4750",'1'&x"4751",'1'&x"4752",'1'&x"4753",'1'&x"4754",'1'&x"4755",'1'&x"4756",'1'&x"4757",'1'&x"4758",'1'&x"4759",'1'&x"475A",'1'&x"475B",'1'&x"475C",'1'&x"475D",'1'&x"475E",'1'&x"475F",
+--'1'&x"4760",'1'&x"4761",'1'&x"4762",'1'&x"4763",'1'&x"4764",'1'&x"4765",'1'&x"4766",'1'&x"4767",'1'&x"4768",'1'&x"4769",'1'&x"476A",'1'&x"476B",'1'&x"476C",'1'&x"476D",'1'&x"476E",'1'&x"476F",
+--'1'&x"4770",'1'&x"4771",'1'&x"4772",'1'&x"4773",'1'&x"4774",'1'&x"4775",'1'&x"4776",'1'&x"4777",'1'&x"4778",'1'&x"4779",'1'&x"477A",'1'&x"477B",'1'&x"477C",'1'&x"477D",'1'&x"477E",'1'&x"477F",
+--'1'&x"4780",'1'&x"4781",'1'&x"4782",'1'&x"4783",'1'&x"4784",'1'&x"4785",'1'&x"4786",'1'&x"4787",'1'&x"4788",'1'&x"4789",'1'&x"478A",'1'&x"478B",'1'&x"478C",'1'&x"478D",'1'&x"478E",'1'&x"478F",
+--'1'&x"4790",'1'&x"4791",'1'&x"4792",'1'&x"4793",'1'&x"4794",'1'&x"4795",'1'&x"4796",'1'&x"4797",'1'&x"4798",'1'&x"4799",'1'&x"479A",'1'&x"479B",'1'&x"479C",'1'&x"479D",'1'&x"479E",'1'&x"479F",
+--'1'&x"47A0",'1'&x"47A1",'1'&x"47A2",'1'&x"47A3",'1'&x"47A4",'1'&x"47A5",'1'&x"47A6",'1'&x"47A7",'1'&x"47A8",'1'&x"47A9",'1'&x"47AA",'1'&x"47AB",'1'&x"47AC",'1'&x"47AD",'1'&x"47AE",'1'&x"47AF",
+--'1'&x"47B0",'1'&x"47B1",'1'&x"47B2",'1'&x"47B3",'1'&x"47B4",'1'&x"47B5",'1'&x"47B6",'1'&x"47B7",'1'&x"47B8",'1'&x"47B9",'1'&x"47BA",'1'&x"47BB",'1'&x"47BC",'1'&x"47BD",'1'&x"47BE",'1'&x"47BF",
+--'1'&x"47C0",'1'&x"47C1",'1'&x"47C2",'1'&x"47C3",'1'&x"47C4",'1'&x"47C5",'1'&x"47C6",'1'&x"47C7",'1'&x"47C8",'1'&x"47C9",'1'&x"47CA",'1'&x"47CB",'1'&x"47CC",'1'&x"47CD",'1'&x"47CE",'1'&x"47CF",
+--'1'&x"47D0",'1'&x"47D1",'1'&x"47D2",'1'&x"47D3",'1'&x"47D4",'1'&x"47D5",'1'&x"47D6",'1'&x"47D7",'1'&x"47D8",'1'&x"47D9",'1'&x"47DA",'1'&x"47DB",'1'&x"47DC",'1'&x"47DD",'1'&x"47DE",'1'&x"47DF",
+--'1'&x"47E0",'1'&x"47E1",'1'&x"47E2",'1'&x"47E3",'1'&x"47E4",'1'&x"47E5",'1'&x"47E6",'1'&x"47E7",'1'&x"47E8",'1'&x"47E9",'1'&x"47EA",'1'&x"47EB",'1'&x"47EC",'1'&x"47ED",'1'&x"47EE",'1'&x"47EF",
+--'1'&x"47F0",'1'&x"47F1",'1'&x"47F2",'1'&x"47F3",'1'&x"47F4",'1'&x"47F5",'1'&x"47F6",'1'&x"47F7",'1'&x"47F8",'1'&x"47F9",'1'&x"47FA",'1'&x"47FB",'1'&x"47FC",'1'&x"47FD",'1'&x"47FE",'1'&x"47FF",
+--'1'&x"4800",'1'&x"4801",'1'&x"4802",'1'&x"4803",'1'&x"4804",'1'&x"4805",'1'&x"4806",'1'&x"4807",'1'&x"4808",'1'&x"4809",'1'&x"480A",'1'&x"480B",'1'&x"480C",'1'&x"480D",'1'&x"480E",'1'&x"480F",
+--'1'&x"4810",'1'&x"4811",'1'&x"4812",'1'&x"4813",'1'&x"4814",'1'&x"4815",'1'&x"4816",'1'&x"4817",'1'&x"4818",'1'&x"4819",'1'&x"481A",'1'&x"481B",'1'&x"481C",'1'&x"481D",'1'&x"481E",'1'&x"481F",
+--'1'&x"4820",'1'&x"4821",'1'&x"4822",'1'&x"4823",'1'&x"4824",'1'&x"4825",'1'&x"4826",'1'&x"4827",'1'&x"4828",'1'&x"4829",'1'&x"482A",'1'&x"482B",'1'&x"482C",'1'&x"482D",'1'&x"482E",'1'&x"482F",
+--'1'&x"4830",'1'&x"4831",'1'&x"4832",'1'&x"4833",'1'&x"4834",'1'&x"4835",'1'&x"4836",'1'&x"4837",'1'&x"4838",'1'&x"4839",'1'&x"483A",'1'&x"483B",'1'&x"483C",'1'&x"483D",'1'&x"483E",'1'&x"483F",
+--'1'&x"4840",'1'&x"4841",'1'&x"4842",'1'&x"4843",'1'&x"4844",'1'&x"4845",'1'&x"4846",'1'&x"4847",'1'&x"4848",'1'&x"4849",'1'&x"484A",'1'&x"484B",'1'&x"484C",'1'&x"484D",'1'&x"484E",'1'&x"484F",
+--'1'&x"4850",'1'&x"4851",'1'&x"4852",'1'&x"4853",'1'&x"4854",'1'&x"4855",'1'&x"4856",'1'&x"4857",'1'&x"4858",'1'&x"4859",'1'&x"485A",'1'&x"485B",'1'&x"485C",'1'&x"485D",'1'&x"485E",'1'&x"485F",
+--'1'&x"4860",'1'&x"4861",'1'&x"4862",'1'&x"4863",'1'&x"4864",'1'&x"4865",'1'&x"4866",'1'&x"4867",'1'&x"4868",'1'&x"4869",'1'&x"486A",'1'&x"486B",'1'&x"486C",'1'&x"486D",'1'&x"486E",'1'&x"486F",
+--'1'&x"4870",'1'&x"4871",'1'&x"4872",'1'&x"4873",'1'&x"4874",'1'&x"4875",'1'&x"4876",'1'&x"4877",'1'&x"4878",'1'&x"4879",'1'&x"487A",'1'&x"487B",'1'&x"487C",'1'&x"487D",'1'&x"487E",'1'&x"487F",
+--'1'&x"4880",'1'&x"4881",'1'&x"4882",'1'&x"4883",'1'&x"4884",'1'&x"4885",'1'&x"4886",'1'&x"4887",'1'&x"4888",'1'&x"4889",'1'&x"488A",'1'&x"488B",'1'&x"488C",'1'&x"488D",'1'&x"488E",'1'&x"488F",
+--'1'&x"4890",'1'&x"4891",'1'&x"4892",'1'&x"4893",'1'&x"4894",'1'&x"4895",'1'&x"4896",'1'&x"4897",'1'&x"4898",'1'&x"4899",'1'&x"489A",'1'&x"489B",'1'&x"489C",'1'&x"489D",'1'&x"489E",'1'&x"489F",
+--'1'&x"48A0",'1'&x"48A1",'1'&x"48A2",'1'&x"48A3",'1'&x"48A4",'1'&x"48A5",'1'&x"48A6",'1'&x"48A7",'1'&x"48A8",'1'&x"48A9",'1'&x"48AA",'1'&x"48AB",'1'&x"48AC",'1'&x"48AD",'1'&x"48AE",'1'&x"48AF",
+--'1'&x"48B0",'1'&x"48B1",'1'&x"48B2",'1'&x"48B3",'1'&x"48B4",'1'&x"48B5",'1'&x"48B6",'1'&x"48B7",'1'&x"48B8",'1'&x"48B9",'1'&x"48BA",'1'&x"48BB",'1'&x"48BC",'1'&x"48BD",'1'&x"48BE",'1'&x"48BF",
+--'1'&x"48C0",'1'&x"48C1",'1'&x"48C2",'1'&x"48C3",'1'&x"48C4",'1'&x"48C5",'1'&x"48C6",'1'&x"48C7",'1'&x"48C8",'1'&x"48C9",'1'&x"48CA",'1'&x"48CB",'1'&x"48CC",'1'&x"48CD",'1'&x"48CE",'1'&x"48CF",
+--'1'&x"48D0",'1'&x"48D1",'1'&x"48D2",'1'&x"48D3",'1'&x"48D4",'1'&x"48D5",'1'&x"48D6",'1'&x"48D7",'1'&x"48D8",'1'&x"48D9",'1'&x"48DA",'1'&x"48DB",'1'&x"48DC",'1'&x"48DD",'1'&x"48DE",'1'&x"48DF",
+--'1'&x"48E0",'1'&x"48E1",'1'&x"48E2",'1'&x"48E3",'1'&x"48E4",'1'&x"48E5",'1'&x"48E6",'1'&x"48E7",'1'&x"48E8",'1'&x"48E9",'1'&x"48EA",'1'&x"48EB",'1'&x"48EC",'1'&x"48ED",'1'&x"48EE",'1'&x"48EF",
+--'1'&x"48F0",'1'&x"48F1",'1'&x"48F2",'1'&x"48F3",'1'&x"48F4",'1'&x"48F5",'1'&x"48F6",'1'&x"48F7",'1'&x"48F8",'1'&x"48F9",'1'&x"48FA",'1'&x"48FB",'1'&x"48FC",'1'&x"48FD",'1'&x"48FE",'1'&x"48FF",
+--'1'&x"4900",'1'&x"4901",'1'&x"4902",'1'&x"4903",'1'&x"4904",'1'&x"4905",'1'&x"4906",'1'&x"4907",'1'&x"4908",'1'&x"4909",'1'&x"490A",'1'&x"490B",'1'&x"490C",'1'&x"490D",'1'&x"490E",'1'&x"490F",
+--'1'&x"4910",'1'&x"4911",'1'&x"4912",'1'&x"4913",'1'&x"4914",'1'&x"4915",'1'&x"4916",'1'&x"4917",'1'&x"4918",'1'&x"4919",'1'&x"491A",'1'&x"491B",'1'&x"491C",'1'&x"491D",'1'&x"491E",'1'&x"491F",
+--'1'&x"4920",'1'&x"4921",'1'&x"4922",'1'&x"4923",'1'&x"4924",'1'&x"4925",'1'&x"4926",'1'&x"4927",'1'&x"4928",'1'&x"4929",'1'&x"492A",'1'&x"492B",'1'&x"492C",'1'&x"492D",'1'&x"492E",'1'&x"492F",
+--'1'&x"4930",'1'&x"4931",'1'&x"4932",'1'&x"4933",'1'&x"4934",'1'&x"4935",'1'&x"4936",'1'&x"4937",'1'&x"4938",'1'&x"4939",'1'&x"493A",'1'&x"493B",'1'&x"493C",'1'&x"493D",'1'&x"493E",'1'&x"493F",
+--'1'&x"4940",'1'&x"4941",'1'&x"4942",'1'&x"4943",'1'&x"4944",'1'&x"4945",'1'&x"4946",'1'&x"4947",'1'&x"4948",'1'&x"4949",'1'&x"494A",'1'&x"494B",'1'&x"494C",'1'&x"494D",'1'&x"494E",'1'&x"494F",
+--'1'&x"4950",'1'&x"4951",'1'&x"4952",'1'&x"4953",'1'&x"4954",'1'&x"4955",'1'&x"4956",'1'&x"4957",'1'&x"4958",'1'&x"4959",'1'&x"495A",'1'&x"495B",'1'&x"495C",'1'&x"495D",'1'&x"495E",'1'&x"495F",
+--'1'&x"4960",'1'&x"4961",'1'&x"4962",'1'&x"4963",'1'&x"4964",'1'&x"4965",'1'&x"4966",'1'&x"4967",'1'&x"4968",'1'&x"4969",'1'&x"496A",'1'&x"496B",'1'&x"496C",'1'&x"496D",'1'&x"496E",'1'&x"496F",
+--'1'&x"4970",'1'&x"4971",'1'&x"4972",'1'&x"4973",'1'&x"4974",'1'&x"4975",'1'&x"4976",'1'&x"4977",'1'&x"4978",'1'&x"4979",'1'&x"497A",'1'&x"497B",'1'&x"497C",'1'&x"497D",'1'&x"497E",'1'&x"497F",
+--'1'&x"4980",'1'&x"4981",'1'&x"4982",'1'&x"4983",'1'&x"4984",'1'&x"4985",'1'&x"4986",'1'&x"4987",'1'&x"4988",'1'&x"4989",'1'&x"498A",'1'&x"498B",'1'&x"498C",'1'&x"498D",'1'&x"498E",'1'&x"498F",
+--'1'&x"4990",'1'&x"4991",'1'&x"4992",'1'&x"4993",'1'&x"4994",'1'&x"4995",'1'&x"4996",'1'&x"4997",'1'&x"4998",'1'&x"4999",'1'&x"499A",'1'&x"499B",'1'&x"499C",'1'&x"499D",'1'&x"499E",'1'&x"499F",
+--'1'&x"49A0",'1'&x"49A1",'1'&x"49A2",'1'&x"49A3",'1'&x"49A4",'1'&x"49A5",'1'&x"49A6",'1'&x"49A7",'1'&x"49A8",'1'&x"49A9",'1'&x"49AA",'1'&x"49AB",'1'&x"49AC",'1'&x"49AD",'1'&x"49AE",'1'&x"49AF",
+--'1'&x"49B0",'1'&x"49B1",'1'&x"49B2",'1'&x"49B3",'1'&x"49B4",'1'&x"49B5",'1'&x"49B6",'1'&x"49B7",'1'&x"49B8",'1'&x"49B9",'1'&x"49BA",'1'&x"49BB",'1'&x"49BC",'1'&x"49BD",'1'&x"49BE",'1'&x"49BF",
+--'1'&x"49C0",'1'&x"49C1",'1'&x"49C2",'1'&x"49C3",'1'&x"49C4",'1'&x"49C5",'1'&x"49C6",'1'&x"49C7",'1'&x"49C8",'1'&x"49C9",'1'&x"49CA",'1'&x"49CB",'1'&x"49CC",'1'&x"49CD",'1'&x"49CE",'1'&x"49CF",
+--'1'&x"49D0",'1'&x"49D1",'1'&x"49D2",'1'&x"49D3",'1'&x"49D4",'1'&x"49D5",'1'&x"49D6",'1'&x"49D7",'1'&x"49D8",'1'&x"49D9",'1'&x"49DA",'1'&x"49DB",'1'&x"49DC",'1'&x"49DD",'1'&x"49DE",'1'&x"49DF",
+--'1'&x"49E0",'1'&x"49E1",'1'&x"49E2",'1'&x"49E3",'1'&x"49E4",'1'&x"49E5",'1'&x"49E6",'1'&x"49E7",'1'&x"49E8",'1'&x"49E9",'1'&x"49EA",'1'&x"49EB",'1'&x"49EC",'1'&x"49ED",'1'&x"49EE",'1'&x"49EF",
+--'1'&x"49F0",'1'&x"49F1",'1'&x"49F2",'1'&x"49F3",'1'&x"49F4",'1'&x"49F5",'1'&x"49F6",'1'&x"49F7",'1'&x"49F8",'1'&x"49F9",'1'&x"49FA",'1'&x"49FB",'1'&x"49FC",'1'&x"49FD",'1'&x"49FE",'1'&x"49FF",
+--'1'&x"4A00",'1'&x"4A01",'1'&x"4A02",'1'&x"4A03",'1'&x"4A04",'1'&x"4A05",'1'&x"4A06",'1'&x"4A07",'1'&x"4A08",'1'&x"4A09",'1'&x"4A0A",'1'&x"4A0B",'1'&x"4A0C",'1'&x"4A0D",'1'&x"4A0E",'1'&x"4A0F",
+--'1'&x"4A10",'1'&x"4A11",'1'&x"4A12",'1'&x"4A13",'1'&x"4A14",'1'&x"4A15",'1'&x"4A16",'1'&x"4A17",'1'&x"4A18",'1'&x"4A19",'1'&x"4A1A",'1'&x"4A1B",'1'&x"4A1C",'1'&x"4A1D",'1'&x"4A1E",'1'&x"4A1F",
+--'1'&x"4A20",'1'&x"4A21",'1'&x"4A22",'1'&x"4A23",'1'&x"4A24",'1'&x"4A25",'1'&x"4A26",'1'&x"4A27",'1'&x"4A28",'1'&x"4A29",'1'&x"4A2A",'1'&x"4A2B",'1'&x"4A2C",'1'&x"4A2D",'1'&x"4A2E",'1'&x"4A2F",
+--'1'&x"4A30",'1'&x"4A31",'1'&x"4A32",'1'&x"4A33",'1'&x"4A34",'1'&x"4A35",'1'&x"4A36",'1'&x"4A37",'1'&x"4A38",'1'&x"4A39",'1'&x"4A3A",'1'&x"4A3B",'1'&x"4A3C",'1'&x"4A3D",'1'&x"4A3E",'1'&x"4A3F",
+--'1'&x"4A40",'1'&x"4A41",'1'&x"4A42",'1'&x"4A43",'1'&x"4A44",'1'&x"4A45",'1'&x"4A46",'1'&x"4A47",'1'&x"4A48",'1'&x"4A49",'1'&x"4A4A",'1'&x"4A4B",'1'&x"4A4C",'1'&x"4A4D",'1'&x"4A4E",'1'&x"4A4F",
+--'1'&x"4A50",'1'&x"4A51",'1'&x"4A52",'1'&x"4A53",'1'&x"4A54",'1'&x"4A55",'1'&x"4A56",'1'&x"4A57",'1'&x"4A58",'1'&x"4A59",'1'&x"4A5A",'1'&x"4A5B",'1'&x"4A5C",'1'&x"4A5D",'1'&x"4A5E",'1'&x"4A5F",
+--'1'&x"4A60",'1'&x"4A61",'1'&x"4A62",'1'&x"4A63",'1'&x"4A64",'1'&x"4A65",'1'&x"4A66",'1'&x"4A67",'1'&x"4A68",'1'&x"4A69",'1'&x"4A6A",'1'&x"4A6B",'1'&x"4A6C",'1'&x"4A6D",'1'&x"4A6E",'1'&x"4A6F",
+--'1'&x"4A70",'1'&x"4A71",'1'&x"4A72",'1'&x"4A73",'1'&x"4A74",'1'&x"4A75",'1'&x"4A76",'1'&x"4A77",'1'&x"4A78",'1'&x"4A79",'1'&x"4A7A",'1'&x"4A7B",'1'&x"4A7C",'1'&x"4A7D",'1'&x"4A7E",'1'&x"4A7F",
+--'1'&x"4A80",'1'&x"4A81",'1'&x"4A82",'1'&x"4A83",'1'&x"4A84",'1'&x"4A85",'1'&x"4A86",'1'&x"4A87",'1'&x"4A88",'1'&x"4A89",'1'&x"4A8A",'1'&x"4A8B",'1'&x"4A8C",'1'&x"4A8D",'1'&x"4A8E",'1'&x"4A8F",
+--'1'&x"4A90",'1'&x"4A91",'1'&x"4A92",'1'&x"4A93",'1'&x"4A94",'1'&x"4A95",'1'&x"4A96",'1'&x"4A97",'1'&x"4A98",'1'&x"4A99",'1'&x"4A9A",'1'&x"4A9B",'1'&x"4A9C",'1'&x"4A9D",'1'&x"4A9E",'1'&x"4A9F",
+--'1'&x"4AA0",'1'&x"4AA1",'1'&x"4AA2",'1'&x"4AA3",'1'&x"4AA4",'1'&x"4AA5",'1'&x"4AA6",'1'&x"4AA7",'1'&x"4AA8",'1'&x"4AA9",'1'&x"4AAA",'1'&x"4AAB",'1'&x"4AAC",'1'&x"4AAD",'1'&x"4AAE",'1'&x"4AAF",
+--'1'&x"4AB0",'1'&x"4AB1",'1'&x"4AB2",'1'&x"4AB3",'1'&x"4AB4",'1'&x"4AB5",'1'&x"4AB6",'1'&x"4AB7",'1'&x"4AB8",'1'&x"4AB9",'1'&x"4ABA",'1'&x"4ABB",'1'&x"4ABC",'1'&x"4ABD",'1'&x"4ABE",'1'&x"4ABF",
+--'1'&x"4AC0",'1'&x"4AC1",'1'&x"4AC2",'1'&x"4AC3",'1'&x"4AC4",'1'&x"4AC5",'1'&x"4AC6",'1'&x"4AC7",'1'&x"4AC8",'1'&x"4AC9",'1'&x"4ACA",'1'&x"4ACB",'1'&x"4ACC",'1'&x"4ACD",'1'&x"4ACE",'1'&x"4ACF",
+--'1'&x"4AD0",'1'&x"4AD1",'1'&x"4AD2",'1'&x"4AD3",'1'&x"4AD4",'1'&x"4AD5",'1'&x"4AD6",'1'&x"4AD7",'1'&x"4AD8",'1'&x"4AD9",'1'&x"4ADA",'1'&x"4ADB",'1'&x"4ADC",'1'&x"4ADD",'1'&x"4ADE",'1'&x"4ADF",
+--'1'&x"4AE0",'1'&x"4AE1",'1'&x"4AE2",'1'&x"4AE3",'1'&x"4AE4",'1'&x"4AE5",'1'&x"4AE6",'1'&x"4AE7",'1'&x"4AE8",'1'&x"4AE9",'1'&x"4AEA",'1'&x"4AEB",'1'&x"4AEC",'1'&x"4AED",'1'&x"4AEE",'1'&x"4AEF",
+--'1'&x"4AF0",'1'&x"4AF1",'1'&x"4AF2",'1'&x"4AF3",'1'&x"4AF4",'1'&x"4AF5",'1'&x"4AF6",'1'&x"4AF7",'1'&x"4AF8",'1'&x"4AF9",'1'&x"4AFA",'1'&x"4AFB",'1'&x"4AFC",'1'&x"4AFD",'1'&x"4AFE",'1'&x"4AFF",
+--'1'&x"4B00",'1'&x"4B01",'1'&x"4B02",'1'&x"4B03",'1'&x"4B04",'1'&x"4B05",'1'&x"4B06",'1'&x"4B07",'1'&x"4B08",'1'&x"4B09",'1'&x"4B0A",'1'&x"4B0B",'1'&x"4B0C",'1'&x"4B0D",'1'&x"4B0E",'1'&x"4B0F",
+--'1'&x"4B10",'1'&x"4B11",'1'&x"4B12",'1'&x"4B13",'1'&x"4B14",'1'&x"4B15",'1'&x"4B16",'1'&x"4B17",'1'&x"4B18",'1'&x"4B19",'1'&x"4B1A",'1'&x"4B1B",'1'&x"4B1C",'1'&x"4B1D",'1'&x"4B1E",'1'&x"4B1F",
+--'1'&x"4B20",'1'&x"4B21",'1'&x"4B22",'1'&x"4B23",'1'&x"4B24",'1'&x"4B25",'1'&x"4B26",'1'&x"4B27",'1'&x"4B28",'1'&x"4B29",'1'&x"4B2A",'1'&x"4B2B",'1'&x"4B2C",'1'&x"4B2D",'1'&x"4B2E",'1'&x"4B2F",
+--'1'&x"4B30",'1'&x"4B31",'1'&x"4B32",'1'&x"4B33",'1'&x"4B34",'1'&x"4B35",'1'&x"4B36",'1'&x"4B37",'1'&x"4B38",'1'&x"4B39",'1'&x"4B3A",'1'&x"4B3B",'1'&x"4B3C",'1'&x"4B3D",'1'&x"4B3E",'1'&x"4B3F",
+--'1'&x"4B40",'1'&x"4B41",'1'&x"4B42",'1'&x"4B43",'1'&x"4B44",'1'&x"4B45",'1'&x"4B46",'1'&x"4B47",'1'&x"4B48",'1'&x"4B49",'1'&x"4B4A",'1'&x"4B4B",'1'&x"4B4C",'1'&x"4B4D",'1'&x"4B4E",'1'&x"4B4F",
+--'1'&x"4B50",'1'&x"4B51",'1'&x"4B52",'1'&x"4B53",'1'&x"4B54",'1'&x"4B55",'1'&x"4B56",'1'&x"4B57",'1'&x"4B58",'1'&x"4B59",'1'&x"4B5A",'1'&x"4B5B",'1'&x"4B5C",'1'&x"4B5D",'1'&x"4B5E",'1'&x"4B5F",
+--'1'&x"4B60",'1'&x"4B61",'1'&x"4B62",'1'&x"4B63",'1'&x"4B64",'1'&x"4B65",'1'&x"4B66",'1'&x"4B67",'1'&x"4B68",'1'&x"4B69",'1'&x"4B6A",'1'&x"4B6B",'1'&x"4B6C",'1'&x"4B6D",'1'&x"4B6E",'1'&x"4B6F",
+--'1'&x"4B70",'1'&x"4B71",'1'&x"4B72",'1'&x"4B73",'1'&x"4B74",'1'&x"4B75",'1'&x"4B76",'1'&x"4B77",'1'&x"4B78",'1'&x"4B79",'1'&x"4B7A",'1'&x"4B7B",'1'&x"4B7C",'1'&x"4B7D",'1'&x"4B7E",'1'&x"4B7F",
+--'1'&x"4B80",'1'&x"4B81",'1'&x"4B82",'1'&x"4B83",'1'&x"4B84",'1'&x"4B85",'1'&x"4B86",'1'&x"4B87",'1'&x"4B88",'1'&x"4B89",'1'&x"4B8A",'1'&x"4B8B",'1'&x"4B8C",'1'&x"4B8D",'1'&x"4B8E",'1'&x"4B8F",
+--'1'&x"4B90",'1'&x"4B91",'1'&x"4B92",'1'&x"4B93",'1'&x"4B94",'1'&x"4B95",'1'&x"4B96",'1'&x"4B97",'1'&x"4B98",'1'&x"4B99",'1'&x"4B9A",'1'&x"4B9B",'1'&x"4B9C",'1'&x"4B9D",'1'&x"4B9E",'1'&x"4B9F",
+--'1'&x"4BA0",'1'&x"4BA1",'1'&x"4BA2",'1'&x"4BA3",'1'&x"4BA4",'1'&x"4BA5",'1'&x"4BA6",'1'&x"4BA7",'1'&x"4BA8",'1'&x"4BA9",'1'&x"4BAA",'1'&x"4BAB",'1'&x"4BAC",'1'&x"4BAD",'1'&x"4BAE",'1'&x"4BAF",
+--'1'&x"4BB0",'1'&x"4BB1",'1'&x"4BB2",'1'&x"4BB3",'1'&x"4BB4",'1'&x"4BB5",'1'&x"4BB6",'1'&x"4BB7",'1'&x"4BB8",'1'&x"4BB9",'1'&x"4BBA",'1'&x"4BBB",'1'&x"4BBC",'1'&x"4BBD",'1'&x"4BBE",'1'&x"4BBF",
+--'1'&x"4BC0",'1'&x"4BC1",'1'&x"4BC2",'1'&x"4BC3",'1'&x"4BC4",'1'&x"4BC5",'1'&x"4BC6",'1'&x"4BC7",'1'&x"4BC8",'1'&x"4BC9",'1'&x"4BCA",'1'&x"4BCB",'1'&x"4BCC",'1'&x"4BCD",'1'&x"4BCE",'1'&x"4BCF",
+--'1'&x"4BD0",'1'&x"4BD1",'1'&x"4BD2",'1'&x"4BD3",'1'&x"4BD4",'1'&x"4BD5",'1'&x"4BD6",'1'&x"4BD7",'1'&x"4BD8",'1'&x"4BD9",'1'&x"4BDA",'1'&x"4BDB",'1'&x"4BDC",'1'&x"4BDD",'1'&x"4BDE",'1'&x"4BDF",
+--'1'&x"4BE0",'1'&x"4BE1",'1'&x"4BE2",'1'&x"4BE3",'1'&x"4BE4",'1'&x"4BE5",'1'&x"4BE6",'1'&x"4BE7",'1'&x"4BE8",'1'&x"4BE9",'1'&x"4BEA",'1'&x"4BEB",'1'&x"4BEC",'1'&x"4BED",'1'&x"4BEE",'1'&x"4BEF",
+--'1'&x"4BF0",'1'&x"4BF1",'1'&x"4BF2",'1'&x"4BF3",'1'&x"4BF4",'1'&x"4BF5",'1'&x"4BF6",'1'&x"4BF7",'1'&x"4BF8",'1'&x"4BF9",'1'&x"4BFA",'1'&x"4BFB",'1'&x"4BFC",'1'&x"4BFD",'1'&x"4BFE",'1'&x"4BFF",
+--'1'&x"4C00",'1'&x"4C01",'1'&x"4C02",'1'&x"4C03",'1'&x"4C04",'1'&x"4C05",'1'&x"4C06",'1'&x"4C07",'1'&x"4C08",'1'&x"4C09",'1'&x"4C0A",'1'&x"4C0B",'1'&x"4C0C",'1'&x"4C0D",'1'&x"4C0E",'1'&x"4C0F",
+--'1'&x"4C10",'1'&x"4C11",'1'&x"4C12",'1'&x"4C13",'1'&x"4C14",'1'&x"4C15",'1'&x"4C16",'1'&x"4C17",'1'&x"4C18",'1'&x"4C19",'1'&x"4C1A",'1'&x"4C1B",'1'&x"4C1C",'1'&x"4C1D",'1'&x"4C1E",'1'&x"4C1F",
+--'1'&x"4C20",'1'&x"4C21",'1'&x"4C22",'1'&x"4C23",'1'&x"4C24",'1'&x"4C25",'1'&x"4C26",'1'&x"4C27",'1'&x"4C28",'1'&x"4C29",'1'&x"4C2A",'1'&x"4C2B",'1'&x"4C2C",'1'&x"4C2D",'1'&x"4C2E",'1'&x"4C2F",
+--'1'&x"4C30",'1'&x"4C31",'1'&x"4C32",'1'&x"4C33",'1'&x"4C34",'1'&x"4C35",'1'&x"4C36",'1'&x"4C37",'1'&x"4C38",'1'&x"4C39",'1'&x"4C3A",'1'&x"4C3B",'1'&x"4C3C",'1'&x"4C3D",'1'&x"4C3E",'1'&x"4C3F",
+--'1'&x"4C40",'1'&x"4C41",'1'&x"4C42",'1'&x"4C43",'1'&x"4C44",'1'&x"4C45",'1'&x"4C46",'1'&x"4C47",'1'&x"4C48",'1'&x"4C49",'1'&x"4C4A",'1'&x"4C4B",'1'&x"4C4C",'1'&x"4C4D",'1'&x"4C4E",'1'&x"4C4F",
+--'1'&x"4C50",'1'&x"4C51",'1'&x"4C52",'1'&x"4C53",'1'&x"4C54",'1'&x"4C55",'1'&x"4C56",'1'&x"4C57",'1'&x"4C58",'1'&x"4C59",'1'&x"4C5A",'1'&x"4C5B",'1'&x"4C5C",'1'&x"4C5D",'1'&x"4C5E",'1'&x"4C5F",
+--'1'&x"4C60",'1'&x"4C61",'1'&x"4C62",'1'&x"4C63",'1'&x"4C64",'1'&x"4C65",'1'&x"4C66",'1'&x"4C67",'1'&x"4C68",'1'&x"4C69",'1'&x"4C6A",'1'&x"4C6B",'1'&x"4C6C",'1'&x"4C6D",'1'&x"4C6E",'1'&x"4C6F",
+--'1'&x"4C70",'1'&x"4C71",'1'&x"4C72",'1'&x"4C73",'1'&x"4C74",'1'&x"4C75",'1'&x"4C76",'1'&x"4C77",'1'&x"4C78",'1'&x"4C79",'1'&x"4C7A",'1'&x"4C7B",'1'&x"4C7C",'1'&x"4C7D",'1'&x"4C7E",'1'&x"4C7F",
+--'1'&x"4C80",'1'&x"4C81",'1'&x"4C82",'1'&x"4C83",'1'&x"4C84",'1'&x"4C85",'1'&x"4C86",'1'&x"4C87",'1'&x"4C88",'1'&x"4C89",'1'&x"4C8A",'1'&x"4C8B",'1'&x"4C8C",'1'&x"4C8D",'1'&x"4C8E",'1'&x"4C8F",
+--'1'&x"4C90",'1'&x"4C91",'1'&x"4C92",'1'&x"4C93",'1'&x"4C94",'1'&x"4C95",'1'&x"4C96",'1'&x"4C97",'1'&x"4C98",'1'&x"4C99",'1'&x"4C9A",'1'&x"4C9B",'1'&x"4C9C",'1'&x"4C9D",'1'&x"4C9E",'1'&x"4C9F",
+--'1'&x"4CA0",'1'&x"4CA1",'1'&x"4CA2",'1'&x"4CA3",'1'&x"4CA4",'1'&x"4CA5",'1'&x"4CA6",'1'&x"4CA7",'1'&x"4CA8",'1'&x"4CA9",'1'&x"4CAA",'1'&x"4CAB",'1'&x"4CAC",'1'&x"4CAD",'1'&x"4CAE",'1'&x"4CAF",
+--'1'&x"4CB0",'1'&x"4CB1",'1'&x"4CB2",'1'&x"4CB3",'1'&x"4CB4",'1'&x"4CB5",'1'&x"4CB6",'1'&x"4CB7",'1'&x"4CB8",'1'&x"4CB9",'1'&x"4CBA",'1'&x"4CBB",'1'&x"4CBC",'1'&x"4CBD",'1'&x"4CBE",'1'&x"4CBF",
+--'1'&x"4CC0",'1'&x"4CC1",'1'&x"4CC2",'1'&x"4CC3",'1'&x"4CC4",'1'&x"4CC5",'1'&x"4CC6",'1'&x"4CC7",'1'&x"4CC8",'1'&x"4CC9",'1'&x"4CCA",'1'&x"4CCB",'1'&x"4CCC",'1'&x"4CCD",'1'&x"4CCE",'1'&x"4CCF",
+--'1'&x"4CD0",'1'&x"4CD1",'1'&x"4CD2",'1'&x"4CD3",'1'&x"4CD4",'1'&x"4CD5",'1'&x"4CD6",'1'&x"4CD7",'1'&x"4CD8",'1'&x"4CD9",'1'&x"4CDA",'1'&x"4CDB",'1'&x"4CDC",'1'&x"4CDD",'1'&x"4CDE",'1'&x"4CDF",
+--'1'&x"4CE0",'1'&x"4CE1",'1'&x"4CE2",'1'&x"4CE3",'1'&x"4CE4",'1'&x"4CE5",'1'&x"4CE6",'1'&x"4CE7",'1'&x"4CE8",'1'&x"4CE9",'1'&x"4CEA",'1'&x"4CEB",'1'&x"4CEC",'1'&x"4CED",'1'&x"4CEE",'1'&x"4CEF",
+--'1'&x"4CF0",'1'&x"4CF1",'1'&x"4CF2",'1'&x"4CF3",'1'&x"4CF4",'1'&x"4CF5",'1'&x"4CF6",'1'&x"4CF7",'1'&x"4CF8",'1'&x"4CF9",'1'&x"4CFA",'1'&x"4CFB",'1'&x"4CFC",'1'&x"4CFD",'1'&x"4CFE",'1'&x"4CFF",
+--'1'&x"4D00",'1'&x"4D01",'1'&x"4D02",'1'&x"4D03",'1'&x"4D04",'1'&x"4D05",'1'&x"4D06",'1'&x"4D07",'1'&x"4D08",'1'&x"4D09",'1'&x"4D0A",'1'&x"4D0B",'1'&x"4D0C",'1'&x"4D0D",'1'&x"4D0E",'1'&x"4D0F",
+--'1'&x"4D10",'1'&x"4D11",'1'&x"4D12",'1'&x"4D13",'1'&x"4D14",'1'&x"4D15",'1'&x"4D16",'1'&x"4D17",'1'&x"4D18",'1'&x"4D19",'1'&x"4D1A",'1'&x"4D1B",'1'&x"4D1C",'1'&x"4D1D",'1'&x"4D1E",'1'&x"4D1F",
+--'1'&x"4D20",'1'&x"4D21",'1'&x"4D22",'1'&x"4D23",'1'&x"4D24",'1'&x"4D25",'1'&x"4D26",'1'&x"4D27",'1'&x"4D28",'1'&x"4D29",'1'&x"4D2A",'1'&x"4D2B",'1'&x"4D2C",'1'&x"4D2D",'1'&x"4D2E",'1'&x"4D2F",
+--'1'&x"4D30",'1'&x"4D31",'1'&x"4D32",'1'&x"4D33",'1'&x"4D34",'1'&x"4D35",'1'&x"4D36",'1'&x"4D37",'1'&x"4D38",'1'&x"4D39",'1'&x"4D3A",'1'&x"4D3B",'1'&x"4D3C",'1'&x"4D3D",'1'&x"4D3E",'1'&x"4D3F",
+--'1'&x"4D40",'1'&x"4D41",'1'&x"4D42",'1'&x"4D43",'1'&x"4D44",'1'&x"4D45",'1'&x"4D46",'1'&x"4D47",'1'&x"4D48",'1'&x"4D49",'1'&x"4D4A",'1'&x"4D4B",'1'&x"4D4C",'1'&x"4D4D",'1'&x"4D4E",'1'&x"4D4F",
+--'1'&x"4D50",'1'&x"4D51",'1'&x"4D52",'1'&x"4D53",'1'&x"4D54",'1'&x"4D55",'1'&x"4D56",'1'&x"4D57",'1'&x"4D58",'1'&x"4D59",'1'&x"4D5A",'1'&x"4D5B",'1'&x"4D5C",'1'&x"4D5D",'1'&x"4D5E",'1'&x"4D5F",
+--'1'&x"4D60",'1'&x"4D61",'1'&x"4D62",'1'&x"4D63",'1'&x"4D64",'1'&x"4D65",'1'&x"4D66",'1'&x"4D67",'1'&x"4D68",'1'&x"4D69",'1'&x"4D6A",'1'&x"4D6B",'1'&x"4D6C",'1'&x"4D6D",'1'&x"4D6E",'1'&x"4D6F",
+--'1'&x"4D70",'1'&x"4D71",'1'&x"4D72",'1'&x"4D73",'1'&x"4D74",'1'&x"4D75",'1'&x"4D76",'1'&x"4D77",'1'&x"4D78",'1'&x"4D79",'1'&x"4D7A",'1'&x"4D7B",'1'&x"4D7C",'1'&x"4D7D",'1'&x"4D7E",'1'&x"4D7F",
+--'1'&x"4D80",'1'&x"4D81",'1'&x"4D82",'1'&x"4D83",'1'&x"4D84",'1'&x"4D85",'1'&x"4D86",'1'&x"4D87",'1'&x"4D88",'1'&x"4D89",'1'&x"4D8A",'1'&x"4D8B",'1'&x"4D8C",'1'&x"4D8D",'1'&x"4D8E",'1'&x"4D8F",
+--'1'&x"4D90",'1'&x"4D91",'1'&x"4D92",'1'&x"4D93",'1'&x"4D94",'1'&x"4D95",'1'&x"4D96",'1'&x"4D97",'1'&x"4D98",'1'&x"4D99",'1'&x"4D9A",'1'&x"4D9B",'1'&x"4D9C",'1'&x"4D9D",'1'&x"4D9E",'1'&x"4D9F",
+--'1'&x"4DA0",'1'&x"4DA1",'1'&x"4DA2",'1'&x"4DA3",'1'&x"4DA4",'1'&x"4DA5",'1'&x"4DA6",'1'&x"4DA7",'1'&x"4DA8",'1'&x"4DA9",'1'&x"4DAA",'1'&x"4DAB",'1'&x"4DAC",'1'&x"4DAD",'1'&x"4DAE",'1'&x"4DAF",
+--'1'&x"4DB0",'1'&x"4DB1",'1'&x"4DB2",'1'&x"4DB3",'1'&x"4DB4",'1'&x"4DB5",'1'&x"4DB6",'1'&x"4DB7",'1'&x"4DB8",'1'&x"4DB9",'1'&x"4DBA",'1'&x"4DBB",'1'&x"4DBC",'1'&x"4DBD",'1'&x"4DBE",'1'&x"4DBF",
+--'1'&x"4DC0",'1'&x"4DC1",'1'&x"4DC2",'1'&x"4DC3",'1'&x"4DC4",'1'&x"4DC5",'1'&x"4DC6",'1'&x"4DC7",'1'&x"4DC8",'1'&x"4DC9",'1'&x"4DCA",'1'&x"4DCB",'1'&x"4DCC",'1'&x"4DCD",'1'&x"4DCE",'1'&x"4DCF",
+--'1'&x"4DD0",'1'&x"4DD1",'1'&x"4DD2",'1'&x"4DD3",'1'&x"4DD4",'1'&x"4DD5",'1'&x"4DD6",'1'&x"4DD7",'1'&x"4DD8",'1'&x"4DD9",'1'&x"4DDA",'1'&x"4DDB",'1'&x"4DDC",'1'&x"4DDD",'1'&x"4DDE",'1'&x"4DDF",
+--'1'&x"4DE0",'1'&x"4DE1",'1'&x"4DE2",'1'&x"4DE3",'1'&x"4DE4",'1'&x"4DE5",'1'&x"4DE6",'1'&x"4DE7",'1'&x"4DE8",'1'&x"4DE9",'1'&x"4DEA",'1'&x"4DEB",'1'&x"4DEC",'1'&x"4DED",'1'&x"4DEE",'1'&x"4DEF",
+--'1'&x"4DF0",'1'&x"4DF1",'1'&x"4DF2",'1'&x"4DF3",'1'&x"4DF4",'1'&x"4DF5",'1'&x"4DF6",'1'&x"4DF7",'1'&x"4DF8",'1'&x"4DF9",'1'&x"4DFA",'1'&x"4DFB",'1'&x"4DFC",'1'&x"4DFD",'1'&x"4DFE",'1'&x"4DFF",
+--'1'&x"4E00",'1'&x"4E01",'1'&x"4E02",'1'&x"4E03",'1'&x"4E04",'1'&x"4E05",'1'&x"4E06",'1'&x"4E07",'1'&x"4E08",'1'&x"4E09",'1'&x"4E0A",'1'&x"4E0B",'1'&x"4E0C",'1'&x"4E0D",'1'&x"4E0E",'1'&x"4E0F",
+--'1'&x"4E10",'1'&x"4E11",'1'&x"4E12",'1'&x"4E13",'1'&x"4E14",'1'&x"4E15",'1'&x"4E16",'1'&x"4E17",'1'&x"4E18",'1'&x"4E19",'1'&x"4E1A",'1'&x"4E1B",'1'&x"4E1C",'1'&x"4E1D",'1'&x"4E1E",'1'&x"4E1F",
+--'1'&x"4E20",'1'&x"4E21",'1'&x"4E22",'1'&x"4E23",'1'&x"4E24",'1'&x"4E25",'1'&x"4E26",'1'&x"4E27",'1'&x"4E28",'1'&x"4E29",'1'&x"4E2A",'1'&x"4E2B",'1'&x"4E2C",'1'&x"4E2D",'1'&x"4E2E",'1'&x"4E2F",
+--'1'&x"4E30",'1'&x"4E31",'1'&x"4E32",'1'&x"4E33",'1'&x"4E34",'1'&x"4E35",'1'&x"4E36",'1'&x"4E37",'1'&x"4E38",'1'&x"4E39",'1'&x"4E3A",'1'&x"4E3B",'1'&x"4E3C",'1'&x"4E3D",'1'&x"4E3E",'1'&x"4E3F",
+--'1'&x"4E40",'1'&x"4E41",'1'&x"4E42",'1'&x"4E43",'1'&x"4E44",'1'&x"4E45",'1'&x"4E46",'1'&x"4E47",'1'&x"4E48",'1'&x"4E49",'1'&x"4E4A",'1'&x"4E4B",'1'&x"4E4C",'1'&x"4E4D",'1'&x"4E4E",'1'&x"4E4F",
+--'1'&x"4E50",'1'&x"4E51",'1'&x"4E52",'1'&x"4E53",'1'&x"4E54",'1'&x"4E55",'1'&x"4E56",'1'&x"4E57",'1'&x"4E58",'1'&x"4E59",'1'&x"4E5A",'1'&x"4E5B",'1'&x"4E5C",'1'&x"4E5D",'1'&x"4E5E",'1'&x"4E5F",
+--'1'&x"4E60",'1'&x"4E61",'1'&x"4E62",'1'&x"4E63",'1'&x"4E64",'1'&x"4E65",'1'&x"4E66",'1'&x"4E67",'1'&x"4E68",'1'&x"4E69",'1'&x"4E6A",'1'&x"4E6B",'1'&x"4E6C",'1'&x"4E6D",'1'&x"4E6E",'1'&x"4E6F",
+--'1'&x"4E70",'1'&x"4E71",'1'&x"4E72",'1'&x"4E73",'1'&x"4E74",'1'&x"4E75",'1'&x"4E76",'1'&x"4E77",'1'&x"4E78",'1'&x"4E79",'1'&x"4E7A",'1'&x"4E7B",'1'&x"4E7C",'1'&x"4E7D",'1'&x"4E7E",'1'&x"4E7F",
+--'1'&x"4E80",'1'&x"4E81",'1'&x"4E82",'1'&x"4E83",'1'&x"4E84",'1'&x"4E85",'1'&x"4E86",'1'&x"4E87",'1'&x"4E88",'1'&x"4E89",'1'&x"4E8A",'1'&x"4E8B",'1'&x"4E8C",'1'&x"4E8D",'1'&x"4E8E",'1'&x"4E8F",
+--'1'&x"4E90",'1'&x"4E91",'1'&x"4E92",'1'&x"4E93",'1'&x"4E94",'1'&x"4E95",'1'&x"4E96",'1'&x"4E97",'1'&x"4E98",'1'&x"4E99",'1'&x"4E9A",'1'&x"4E9B",'1'&x"4E9C",'1'&x"4E9D",'1'&x"4E9E",'1'&x"4E9F",
+--'1'&x"4EA0",'1'&x"4EA1",'1'&x"4EA2",'1'&x"4EA3",'1'&x"4EA4",'1'&x"4EA5",'1'&x"4EA6",'1'&x"4EA7",'1'&x"4EA8",'1'&x"4EA9",'1'&x"4EAA",'1'&x"4EAB",'1'&x"4EAC",'1'&x"4EAD",'1'&x"4EAE",'1'&x"4EAF",
+--'1'&x"4EB0",'1'&x"4EB1",'1'&x"4EB2",'1'&x"4EB3",'1'&x"4EB4",'1'&x"4EB5",'1'&x"4EB6",'1'&x"4EB7",'1'&x"4EB8",'1'&x"4EB9",'1'&x"4EBA",'1'&x"4EBB",'1'&x"4EBC",'1'&x"4EBD",'1'&x"4EBE",'1'&x"4EBF",
+--'1'&x"4EC0",'1'&x"4EC1",'1'&x"4EC2",'1'&x"4EC3",'1'&x"4EC4",'1'&x"4EC5",'1'&x"4EC6",'1'&x"4EC7",'1'&x"4EC8",'1'&x"4EC9",'1'&x"4ECA",'1'&x"4ECB",'1'&x"4ECC",'1'&x"4ECD",'1'&x"4ECE",'1'&x"4ECF",
+--'1'&x"4ED0",'1'&x"4ED1",'1'&x"4ED2",'1'&x"4ED3",'1'&x"4ED4",'1'&x"4ED5",'1'&x"4ED6",'1'&x"4ED7",'1'&x"4ED8",'1'&x"4ED9",'1'&x"4EDA",'1'&x"4EDB",'1'&x"4EDC",'1'&x"4EDD",'1'&x"4EDE",'1'&x"4EDF",
+--'1'&x"4EE0",'1'&x"4EE1",'1'&x"4EE2",'1'&x"4EE3",'1'&x"4EE4",'1'&x"4EE5",'1'&x"4EE6",'1'&x"4EE7",'1'&x"4EE8",'1'&x"4EE9",'1'&x"4EEA",'1'&x"4EEB",'1'&x"4EEC",'1'&x"4EED",'1'&x"4EEE",'1'&x"4EEF",
+--'1'&x"4EF0",'1'&x"4EF1",'1'&x"4EF2",'1'&x"4EF3",'1'&x"4EF4",'1'&x"4EF5",'1'&x"4EF6",'1'&x"4EF7",'1'&x"4EF8",'1'&x"4EF9",'1'&x"4EFA",'1'&x"4EFB",'1'&x"4EFC",'1'&x"4EFD",'1'&x"4EFE",'1'&x"4EFF",
+--'1'&x"4F00",'1'&x"4F01",'1'&x"4F02",'1'&x"4F03",'1'&x"4F04",'1'&x"4F05",'1'&x"4F06",'1'&x"4F07",'1'&x"4F08",'1'&x"4F09",'1'&x"4F0A",'1'&x"4F0B",'1'&x"4F0C",'1'&x"4F0D",'1'&x"4F0E",'1'&x"4F0F",
+--'1'&x"4F10",'1'&x"4F11",'1'&x"4F12",'1'&x"4F13",'1'&x"4F14",'1'&x"4F15",'1'&x"4F16",'1'&x"4F17",'1'&x"4F18",'1'&x"4F19",'1'&x"4F1A",'1'&x"4F1B",'1'&x"4F1C",'1'&x"4F1D",'1'&x"4F1E",'1'&x"4F1F",
+--'1'&x"4F20",'1'&x"4F21",'1'&x"4F22",'1'&x"4F23",'1'&x"4F24",'1'&x"4F25",'1'&x"4F26",'1'&x"4F27",'1'&x"4F28",'1'&x"4F29",'1'&x"4F2A",'1'&x"4F2B",'1'&x"4F2C",'1'&x"4F2D",'1'&x"4F2E",'1'&x"4F2F",
+--'1'&x"4F30",'1'&x"4F31",'1'&x"4F32",'1'&x"4F33",'1'&x"4F34",'1'&x"4F35",'1'&x"4F36",'1'&x"4F37",'1'&x"4F38",'1'&x"4F39",'1'&x"4F3A",'1'&x"4F3B",'1'&x"4F3C",'1'&x"4F3D",'1'&x"4F3E",'1'&x"4F3F",
+--'1'&x"4F40",'1'&x"4F41",'1'&x"4F42",'1'&x"4F43",'1'&x"4F44",'1'&x"4F45",'1'&x"4F46",'1'&x"4F47",'1'&x"4F48",'1'&x"4F49",'1'&x"4F4A",'1'&x"4F4B",'1'&x"4F4C",'1'&x"4F4D",'1'&x"4F4E",'1'&x"4F4F",
+--'1'&x"4F50",'1'&x"4F51",'1'&x"4F52",'1'&x"4F53",'1'&x"4F54",'1'&x"4F55",'1'&x"4F56",'1'&x"4F57",'1'&x"4F58",'1'&x"4F59",'1'&x"4F5A",'1'&x"4F5B",'1'&x"4F5C",'1'&x"4F5D",'1'&x"4F5E",'1'&x"4F5F",
+--'1'&x"4F60",'1'&x"4F61",'1'&x"4F62",'1'&x"4F63",'1'&x"4F64",'1'&x"4F65",'1'&x"4F66",'1'&x"4F67",'1'&x"4F68",'1'&x"4F69",'1'&x"4F6A",'1'&x"4F6B",'1'&x"4F6C",'1'&x"4F6D",'1'&x"4F6E",'1'&x"4F6F",
+--'1'&x"4F70",'1'&x"4F71",'1'&x"4F72",'1'&x"4F73",'1'&x"4F74",'1'&x"4F75",'1'&x"4F76",'1'&x"4F77",'1'&x"4F78",'1'&x"4F79",'1'&x"4F7A",'1'&x"4F7B",'1'&x"4F7C",'1'&x"4F7D",'1'&x"4F7E",'1'&x"4F7F",
+--'1'&x"4F80",'1'&x"4F81",'1'&x"4F82",'1'&x"4F83",'1'&x"4F84",'1'&x"4F85",'1'&x"4F86",'1'&x"4F87",'1'&x"4F88",'1'&x"4F89",'1'&x"4F8A",'1'&x"4F8B",'1'&x"4F8C",'1'&x"4F8D",'1'&x"4F8E",'1'&x"4F8F",
+--'1'&x"4F90",'1'&x"4F91",'1'&x"4F92",'1'&x"4F93",'1'&x"4F94",'1'&x"4F95",'1'&x"4F96",'1'&x"4F97",'1'&x"4F98",'1'&x"4F99",'1'&x"4F9A",'1'&x"4F9B",'1'&x"4F9C",'1'&x"4F9D",'1'&x"4F9E",'1'&x"4F9F",
+--'1'&x"4FA0",'1'&x"4FA1",'1'&x"4FA2",'1'&x"4FA3",'1'&x"4FA4",'1'&x"4FA5",'1'&x"4FA6",'1'&x"4FA7",'1'&x"4FA8",'1'&x"4FA9",'1'&x"4FAA",'1'&x"4FAB",'1'&x"4FAC",'1'&x"4FAD",'1'&x"4FAE",'1'&x"4FAF",
+--'1'&x"4FB0",'1'&x"4FB1",'1'&x"4FB2",'1'&x"4FB3",'1'&x"4FB4",'1'&x"4FB5",'1'&x"4FB6",'1'&x"4FB7",'1'&x"4FB8",'1'&x"4FB9",'1'&x"4FBA",'1'&x"4FBB",'1'&x"4FBC",'1'&x"4FBD",'1'&x"4FBE",'1'&x"4FBF",
+--'1'&x"4FC0",'1'&x"4FC1",'1'&x"4FC2",'1'&x"4FC3",'1'&x"4FC4",'1'&x"4FC5",'1'&x"4FC6",'1'&x"4FC7",'1'&x"4FC8",'1'&x"4FC9",'1'&x"4FCA",'1'&x"4FCB",'1'&x"4FCC",'1'&x"4FCD",'1'&x"4FCE",'1'&x"4FCF",
+--'1'&x"4FD0",'1'&x"4FD1",'1'&x"4FD2",'1'&x"4FD3",'1'&x"4FD4",'1'&x"4FD5",'1'&x"4FD6",'1'&x"4FD7",'1'&x"4FD8",'1'&x"4FD9",'1'&x"4FDA",'1'&x"4FDB",'1'&x"4FDC",'1'&x"4FDD",'1'&x"4FDE",'1'&x"4FDF",
+--'1'&x"4FE0",'1'&x"4FE1",'1'&x"4FE2",'1'&x"4FE3",'1'&x"4FE4",'1'&x"4FE5",'1'&x"4FE6",'1'&x"4FE7",'1'&x"4FE8",'1'&x"4FE9",'1'&x"4FEA",'1'&x"4FEB",'1'&x"4FEC",'1'&x"4FED",'1'&x"4FEE",'1'&x"4FEF",
+--'1'&x"4FF0",'1'&x"4FF1",'1'&x"4FF2",'1'&x"4FF3",'1'&x"4FF4",'1'&x"4FF5",'1'&x"4FF6",'1'&x"4FF7",'1'&x"4FF8",'1'&x"4FF9",'1'&x"4FFA",'1'&x"4FFB",'1'&x"4FFC",'1'&x"4FFD",'1'&x"4FFE",'1'&x"4FFF",
+--'1'&x"5000",'1'&x"5001",'1'&x"5002",'1'&x"5003",'1'&x"5004",'1'&x"5005",'1'&x"5006",'1'&x"5007",'1'&x"5008",'1'&x"5009",'1'&x"500A",'1'&x"500B",'1'&x"500C",'1'&x"500D",'1'&x"500E",'1'&x"500F",
+--'1'&x"5010",'1'&x"5011",'1'&x"5012",'1'&x"5013",'1'&x"5014",'1'&x"5015",'1'&x"5016",'1'&x"5017",'1'&x"5018",'1'&x"5019",'1'&x"501A",'1'&x"501B",'1'&x"501C",'1'&x"501D",'1'&x"501E",'1'&x"501F",
+--'1'&x"5020",'1'&x"5021",'1'&x"5022",'1'&x"5023",'1'&x"5024",'1'&x"5025",'1'&x"5026",'1'&x"5027",'1'&x"5028",'1'&x"5029",'1'&x"502A",'1'&x"502B",'1'&x"502C",'1'&x"502D",'1'&x"502E",'1'&x"502F",
+--'1'&x"5030",'1'&x"5031",'1'&x"5032",'1'&x"5033",'1'&x"5034",'1'&x"5035",'1'&x"5036",'1'&x"5037",'1'&x"5038",'1'&x"5039",'1'&x"503A",'1'&x"503B",'1'&x"503C",'1'&x"503D",'1'&x"503E",'1'&x"503F",
+--'1'&x"5040",'1'&x"5041",'1'&x"5042",'1'&x"5043",'1'&x"5044",'1'&x"5045",'1'&x"5046",'1'&x"5047",'1'&x"5048",'1'&x"5049",'1'&x"504A",'1'&x"504B",'1'&x"504C",'1'&x"504D",'1'&x"504E",'1'&x"504F",
+--'1'&x"5050",'1'&x"5051",'1'&x"5052",'1'&x"5053",'1'&x"5054",'1'&x"5055",'1'&x"5056",'1'&x"5057",'1'&x"5058",'1'&x"5059",'1'&x"505A",'1'&x"505B",'1'&x"505C",'1'&x"505D",'1'&x"505E",'1'&x"505F",
+--'1'&x"5060",'1'&x"5061",'1'&x"5062",'1'&x"5063",'1'&x"5064",'1'&x"5065",'1'&x"5066",'1'&x"5067",'1'&x"5068",'1'&x"5069",'1'&x"506A",'1'&x"506B",'1'&x"506C",'1'&x"506D",'1'&x"506E",'1'&x"506F",
+--'1'&x"5070",'1'&x"5071",'1'&x"5072",'1'&x"5073",'1'&x"5074",'1'&x"5075",'1'&x"5076",'1'&x"5077",'1'&x"5078",'1'&x"5079",'1'&x"507A",'1'&x"507B",'1'&x"507C",'1'&x"507D",'1'&x"507E",'1'&x"507F",
+--'1'&x"5080",'1'&x"5081",'1'&x"5082",'1'&x"5083",'1'&x"5084",'1'&x"5085",'1'&x"5086",'1'&x"5087",'1'&x"5088",'1'&x"5089",'1'&x"508A",'1'&x"508B",'1'&x"508C",'1'&x"508D",'1'&x"508E",'1'&x"508F",
+--'1'&x"5090",'1'&x"5091",'1'&x"5092",'1'&x"5093",'1'&x"5094",'1'&x"5095",'1'&x"5096",'1'&x"5097",'1'&x"5098",'1'&x"5099",'1'&x"509A",'1'&x"509B",'1'&x"509C",'1'&x"509D",'1'&x"509E",'1'&x"509F",
+--'1'&x"50A0",'1'&x"50A1",'1'&x"50A2",'1'&x"50A3",'1'&x"50A4",'1'&x"50A5",'1'&x"50A6",'1'&x"50A7",'1'&x"50A8",'1'&x"50A9",'1'&x"50AA",'1'&x"50AB",'1'&x"50AC",'1'&x"50AD",'1'&x"50AE",'1'&x"50AF",
+--'1'&x"50B0",'1'&x"50B1",'1'&x"50B2",'1'&x"50B3",'1'&x"50B4",'1'&x"50B5",'1'&x"50B6",'1'&x"50B7",'1'&x"50B8",'1'&x"50B9",'1'&x"50BA",'1'&x"50BB",'1'&x"50BC",'1'&x"50BD",'1'&x"50BE",'1'&x"50BF",
+--'1'&x"50C0",'1'&x"50C1",'1'&x"50C2",'1'&x"50C3",'1'&x"50C4",'1'&x"50C5",'1'&x"50C6",'1'&x"50C7",'1'&x"50C8",'1'&x"50C9",'1'&x"50CA",'1'&x"50CB",'1'&x"50CC",'1'&x"50CD",'1'&x"50CE",'1'&x"50CF",
+--'1'&x"50D0",'1'&x"50D1",'1'&x"50D2",'1'&x"50D3",'1'&x"50D4",'1'&x"50D5",'1'&x"50D6",'1'&x"50D7",'1'&x"50D8",'1'&x"50D9",'1'&x"50DA",'1'&x"50DB",'1'&x"50DC",'1'&x"50DD",'1'&x"50DE",'1'&x"50DF",
+--'1'&x"50E0",'1'&x"50E1",'1'&x"50E2",'1'&x"50E3",'1'&x"50E4",'1'&x"50E5",'1'&x"50E6",'1'&x"50E7",'1'&x"50E8",'1'&x"50E9",'1'&x"50EA",'1'&x"50EB",'1'&x"50EC",'1'&x"50ED",'1'&x"50EE",'1'&x"50EF",
+--'1'&x"50F0",'1'&x"50F1",'1'&x"50F2",'1'&x"50F3",'1'&x"50F4",'1'&x"50F5",'1'&x"50F6",'1'&x"50F7",'1'&x"50F8",'1'&x"50F9",'1'&x"50FA",'1'&x"50FB",'1'&x"50FC",'1'&x"50FD",'1'&x"50FE",'1'&x"50FF",
+--'1'&x"5100",'1'&x"5101",'1'&x"5102",'1'&x"5103",'1'&x"5104",'1'&x"5105",'1'&x"5106",'1'&x"5107",'1'&x"5108",'1'&x"5109",'1'&x"510A",'1'&x"510B",'1'&x"510C",'1'&x"510D",'1'&x"510E",'1'&x"510F",
+--'1'&x"5110",'1'&x"5111",'1'&x"5112",'1'&x"5113",'1'&x"5114",'1'&x"5115",'1'&x"5116",'1'&x"5117",'1'&x"5118",'1'&x"5119",'1'&x"511A",'1'&x"511B",'1'&x"511C",'1'&x"511D",'1'&x"511E",'1'&x"511F",
+--'1'&x"5120",'1'&x"5121",'1'&x"5122",'1'&x"5123",'1'&x"5124",'1'&x"5125",'1'&x"5126",'1'&x"5127",'1'&x"5128",'1'&x"5129",'1'&x"512A",'1'&x"512B",'1'&x"512C",'1'&x"512D",'1'&x"512E",'1'&x"512F",
+--'1'&x"5130",'1'&x"5131",'1'&x"5132",'1'&x"5133",'1'&x"5134",'1'&x"5135",'1'&x"5136",'1'&x"5137",'1'&x"5138",'1'&x"5139",'1'&x"513A",'1'&x"513B",'1'&x"513C",'1'&x"513D",'1'&x"513E",'1'&x"513F",
+--'1'&x"5140",'1'&x"5141",'1'&x"5142",'1'&x"5143",'1'&x"5144",'1'&x"5145",'1'&x"5146",'1'&x"5147",'1'&x"5148",'1'&x"5149",'1'&x"514A",'1'&x"514B",'1'&x"514C",'1'&x"514D",'1'&x"514E",'1'&x"514F",
+--'1'&x"5150",'1'&x"5151",'1'&x"5152",'1'&x"5153",'1'&x"5154",'1'&x"5155",'1'&x"5156",'1'&x"5157",'1'&x"5158",'1'&x"5159",'1'&x"515A",'1'&x"515B",'1'&x"515C",'1'&x"515D",'1'&x"515E",'1'&x"515F",
+--'1'&x"5160",'1'&x"5161",'1'&x"5162",'1'&x"5163",'1'&x"5164",'1'&x"5165",'1'&x"5166",'1'&x"5167",'1'&x"5168",'1'&x"5169",'1'&x"516A",'1'&x"516B",'1'&x"516C",'1'&x"516D",'1'&x"516E",'1'&x"516F",
+--'1'&x"5170",'1'&x"5171",'1'&x"5172",'1'&x"5173",'1'&x"5174",'1'&x"5175",'1'&x"5176",'1'&x"5177",'1'&x"5178",'1'&x"5179",'1'&x"517A",'1'&x"517B",'1'&x"517C",'1'&x"517D",'1'&x"517E",'1'&x"517F",
+--'1'&x"5180",'1'&x"5181",'1'&x"5182",'1'&x"5183",'1'&x"5184",'1'&x"5185",'1'&x"5186",'1'&x"5187",'1'&x"5188",'1'&x"5189",'1'&x"518A",'1'&x"518B",'1'&x"518C",'1'&x"518D",'1'&x"518E",'1'&x"518F",
+--'1'&x"5190",'1'&x"5191",'1'&x"5192",'1'&x"5193",'1'&x"5194",'1'&x"5195",'1'&x"5196",'1'&x"5197",'1'&x"5198",'1'&x"5199",'1'&x"519A",'1'&x"519B",'1'&x"519C",'1'&x"519D",'1'&x"519E",'1'&x"519F",
+--'1'&x"51A0",'1'&x"51A1",'1'&x"51A2",'1'&x"51A3",'1'&x"51A4",'1'&x"51A5",'1'&x"51A6",'1'&x"51A7",'1'&x"51A8",'1'&x"51A9",'1'&x"51AA",'1'&x"51AB",'1'&x"51AC",'1'&x"51AD",'1'&x"51AE",'1'&x"51AF",
+--'1'&x"51B0",'1'&x"51B1",'1'&x"51B2",'1'&x"51B3",'1'&x"51B4",'1'&x"51B5",'1'&x"51B6",'1'&x"51B7",'1'&x"51B8",'1'&x"51B9",'1'&x"51BA",'1'&x"51BB",'1'&x"51BC",'1'&x"51BD",'1'&x"51BE",'1'&x"51BF",
+--'1'&x"51C0",'1'&x"51C1",'1'&x"51C2",'1'&x"51C3",'1'&x"51C4",'1'&x"51C5",'1'&x"51C6",'1'&x"51C7",'1'&x"51C8",'1'&x"51C9",'1'&x"51CA",'1'&x"51CB",'1'&x"51CC",'1'&x"51CD",'1'&x"51CE",'1'&x"51CF",
+--'1'&x"51D0",'1'&x"51D1",'1'&x"51D2",'1'&x"51D3",'1'&x"51D4",'1'&x"51D5",'1'&x"51D6",'1'&x"51D7",'1'&x"51D8",'1'&x"51D9",'1'&x"51DA",'1'&x"51DB",'1'&x"51DC",'1'&x"51DD",'1'&x"51DE",'1'&x"51DF",
+--'1'&x"51E0",'1'&x"51E1",'1'&x"51E2",'1'&x"51E3",'1'&x"51E4",'1'&x"51E5",'1'&x"51E6",'1'&x"51E7",'1'&x"51E8",'1'&x"51E9",'1'&x"51EA",'1'&x"51EB",'1'&x"51EC",'1'&x"51ED",'1'&x"51EE",'1'&x"51EF",
+--'1'&x"51F0",'1'&x"51F1",'1'&x"51F2",'1'&x"51F3",'1'&x"51F4",'1'&x"51F5",'1'&x"51F6",'1'&x"51F7",'1'&x"51F8",'1'&x"51F9",'1'&x"51FA",'1'&x"51FB",'1'&x"51FC",'1'&x"51FD",'1'&x"51FE",'1'&x"51FF",
+--'1'&x"5200",'1'&x"5201",'1'&x"5202",'1'&x"5203",'1'&x"5204",'1'&x"5205",'1'&x"5206",'1'&x"5207",'1'&x"5208",'1'&x"5209",'1'&x"520A",'1'&x"520B",'1'&x"520C",'1'&x"520D",'1'&x"520E",'1'&x"520F",
+--'1'&x"5210",'1'&x"5211",'1'&x"5212",'1'&x"5213",'1'&x"5214",'1'&x"5215",'1'&x"5216",'1'&x"5217",'1'&x"5218",'1'&x"5219",'1'&x"521A",'1'&x"521B",'1'&x"521C",'1'&x"521D",'1'&x"521E",'1'&x"521F",
+--'1'&x"5220",'1'&x"5221",'1'&x"5222",'1'&x"5223",'1'&x"5224",'1'&x"5225",'1'&x"5226",'1'&x"5227",'1'&x"5228",'1'&x"5229",'1'&x"522A",'1'&x"522B",'1'&x"522C",'1'&x"522D",'1'&x"522E",'1'&x"522F",
+--'1'&x"5230",'1'&x"5231",'1'&x"5232",'1'&x"5233",'1'&x"5234",'1'&x"5235",'1'&x"5236",'1'&x"5237",'1'&x"5238",'1'&x"5239",'1'&x"523A",'1'&x"523B",'1'&x"523C",'1'&x"523D",'1'&x"523E",'1'&x"523F",
+--'1'&x"5240",'1'&x"5241",'1'&x"5242",'1'&x"5243",'1'&x"5244",'1'&x"5245",'1'&x"5246",'1'&x"5247",'1'&x"5248",'1'&x"5249",'1'&x"524A",'1'&x"524B",'1'&x"524C",'1'&x"524D",'1'&x"524E",'1'&x"524F",
+--'1'&x"5250",'1'&x"5251",'1'&x"5252",'1'&x"5253",'1'&x"5254",'1'&x"5255",'1'&x"5256",'1'&x"5257",'1'&x"5258",'1'&x"5259",'1'&x"525A",'1'&x"525B",'1'&x"525C",'1'&x"525D",'1'&x"525E",'1'&x"525F",
+--'1'&x"5260",'1'&x"5261",'1'&x"5262",'1'&x"5263",'1'&x"5264",'1'&x"5265",'1'&x"5266",'1'&x"5267",'1'&x"5268",'1'&x"5269",'1'&x"526A",'1'&x"526B",'1'&x"526C",'1'&x"526D",'1'&x"526E",'1'&x"526F",
+--'1'&x"5270",'1'&x"5271",'1'&x"5272",'1'&x"5273",'1'&x"5274",'1'&x"5275",'1'&x"5276",'1'&x"5277",'1'&x"5278",'1'&x"5279",'1'&x"527A",'1'&x"527B",'1'&x"527C",'1'&x"527D",'1'&x"527E",'1'&x"527F",
+--'1'&x"5280",'1'&x"5281",'1'&x"5282",'1'&x"5283",'1'&x"5284",'1'&x"5285",'1'&x"5286",'1'&x"5287",'1'&x"5288",'1'&x"5289",'1'&x"528A",'1'&x"528B",'1'&x"528C",'1'&x"528D",'1'&x"528E",'1'&x"528F",
+--'1'&x"5290",'1'&x"5291",'1'&x"5292",'1'&x"5293",'1'&x"5294",'1'&x"5295",'1'&x"5296",'1'&x"5297",'1'&x"5298",'1'&x"5299",'1'&x"529A",'1'&x"529B",'1'&x"529C",'1'&x"529D",'1'&x"529E",'1'&x"529F",
+--'1'&x"52A0",'1'&x"52A1",'1'&x"52A2",'1'&x"52A3",'1'&x"52A4",'1'&x"52A5",'1'&x"52A6",'1'&x"52A7",'1'&x"52A8",'1'&x"52A9",'1'&x"52AA",'1'&x"52AB",'1'&x"52AC",'1'&x"52AD",'1'&x"52AE",'1'&x"52AF",
+--'1'&x"52B0",'1'&x"52B1",'1'&x"52B2",'1'&x"52B3",'1'&x"52B4",'1'&x"52B5",'1'&x"52B6",'1'&x"52B7",'1'&x"52B8",'1'&x"52B9",'1'&x"52BA",'1'&x"52BB",'1'&x"52BC",'1'&x"52BD",'1'&x"52BE",'1'&x"52BF",
+--'1'&x"52C0",'1'&x"52C1",'1'&x"52C2",'1'&x"52C3",'1'&x"52C4",'1'&x"52C5",'1'&x"52C6",'1'&x"52C7",'1'&x"52C8",'1'&x"52C9",'1'&x"52CA",'1'&x"52CB",'1'&x"52CC",'1'&x"52CD",'1'&x"52CE",'1'&x"52CF",
+--'1'&x"52D0",'1'&x"52D1",'1'&x"52D2",'1'&x"52D3",'1'&x"52D4",'1'&x"52D5",'1'&x"52D6",'1'&x"52D7",'1'&x"52D8",'1'&x"52D9",'1'&x"52DA",'1'&x"52DB",'1'&x"52DC",'1'&x"52DD",'1'&x"52DE",'1'&x"52DF",
+--'1'&x"52E0",'1'&x"52E1",'1'&x"52E2",'1'&x"52E3",'1'&x"52E4",'1'&x"52E5",'1'&x"52E6",'1'&x"52E7",'1'&x"52E8",'1'&x"52E9",'1'&x"52EA",'1'&x"52EB",'1'&x"52EC",'1'&x"52ED",'1'&x"52EE",'1'&x"52EF",
+--'1'&x"52F0",'1'&x"52F1",'1'&x"52F2",'1'&x"52F3",'1'&x"52F4",'1'&x"52F5",'1'&x"52F6",'1'&x"52F7",'1'&x"52F8",'1'&x"52F9",'1'&x"52FA",'1'&x"52FB",'1'&x"52FC",'1'&x"52FD",'1'&x"52FE",'1'&x"52FF",
+--'1'&x"5300",'1'&x"5301",'1'&x"5302",'1'&x"5303",'1'&x"5304",'1'&x"5305",'1'&x"5306",'1'&x"5307",'1'&x"5308",'1'&x"5309",'1'&x"530A",'1'&x"530B",'1'&x"530C",'1'&x"530D",'1'&x"530E",'1'&x"530F",
+--'1'&x"5310",'1'&x"5311",'1'&x"5312",'1'&x"5313",'1'&x"5314",'1'&x"5315",'1'&x"5316",'1'&x"5317",'1'&x"5318",'1'&x"5319",'1'&x"531A",'1'&x"531B",'1'&x"531C",'1'&x"531D",'1'&x"531E",'1'&x"531F",
+--'1'&x"5320",'1'&x"5321",'1'&x"5322",'1'&x"5323",'1'&x"5324",'1'&x"5325",'1'&x"5326",'1'&x"5327",'1'&x"5328",'1'&x"5329",'1'&x"532A",'1'&x"532B",'1'&x"532C",'1'&x"532D",'1'&x"532E",'1'&x"532F",
+--'1'&x"5330",'1'&x"5331",'1'&x"5332",'1'&x"5333",'1'&x"5334",'1'&x"5335",'1'&x"5336",'1'&x"5337",'1'&x"5338",'1'&x"5339",'1'&x"533A",'1'&x"533B",'1'&x"533C",'1'&x"533D",'1'&x"533E",'1'&x"533F",
+--'1'&x"5340",'1'&x"5341",'1'&x"5342",'1'&x"5343",'1'&x"5344",'1'&x"5345",'1'&x"5346",'1'&x"5347",'1'&x"5348",'1'&x"5349",'1'&x"534A",'1'&x"534B",'1'&x"534C",'1'&x"534D",'1'&x"534E",'1'&x"534F",
+--'1'&x"5350",'1'&x"5351",'1'&x"5352",'1'&x"5353",'1'&x"5354",'1'&x"5355",'1'&x"5356",'1'&x"5357",'1'&x"5358",'1'&x"5359",'1'&x"535A",'1'&x"535B",'1'&x"535C",'1'&x"535D",'1'&x"535E",'1'&x"535F",
+--'1'&x"5360",'1'&x"5361",'1'&x"5362",'1'&x"5363",'1'&x"5364",'1'&x"5365",'1'&x"5366",'1'&x"5367",'1'&x"5368",'1'&x"5369",'1'&x"536A",'1'&x"536B",'1'&x"536C",'1'&x"536D",'1'&x"536E",'1'&x"536F",
+--'1'&x"5370",'1'&x"5371",'1'&x"5372",'1'&x"5373",'1'&x"5374",'1'&x"5375",'1'&x"5376",'1'&x"5377",'1'&x"5378",'1'&x"5379",'1'&x"537A",'1'&x"537B",'1'&x"537C",'1'&x"537D",'1'&x"537E",'1'&x"537F",
+--'1'&x"5380",'1'&x"5381",'1'&x"5382",'1'&x"5383",'1'&x"5384",'1'&x"5385",'1'&x"5386",'1'&x"5387",'1'&x"5388",'1'&x"5389",'1'&x"538A",'1'&x"538B",'1'&x"538C",'1'&x"538D",'1'&x"538E",'1'&x"538F",
+--'1'&x"5390",'1'&x"5391",'1'&x"5392",'1'&x"5393",'1'&x"5394",'1'&x"5395",'1'&x"5396",'1'&x"5397",'1'&x"5398",'1'&x"5399",'1'&x"539A",'1'&x"539B",'1'&x"539C",'1'&x"539D",'1'&x"539E",'1'&x"539F",
+--'1'&x"53A0",'1'&x"53A1",'1'&x"53A2",'1'&x"53A3",'1'&x"53A4",'1'&x"53A5",'1'&x"53A6",'1'&x"53A7",'1'&x"53A8",'1'&x"53A9",'1'&x"53AA",'1'&x"53AB",'1'&x"53AC",'1'&x"53AD",'1'&x"53AE",'1'&x"53AF",
+--'1'&x"53B0",'1'&x"53B1",'1'&x"53B2",'1'&x"53B3",'1'&x"53B4",'1'&x"53B5",'1'&x"53B6",'1'&x"53B7",'1'&x"53B8",'1'&x"53B9",'1'&x"53BA",'1'&x"53BB",'1'&x"53BC",'1'&x"53BD",'1'&x"53BE",'1'&x"53BF",
+--'1'&x"53C0",'1'&x"53C1",'1'&x"53C2",'1'&x"53C3",'1'&x"53C4",'1'&x"53C5",'1'&x"53C6",'1'&x"53C7",'1'&x"53C8",'1'&x"53C9",'1'&x"53CA",'1'&x"53CB",'1'&x"53CC",'1'&x"53CD",'1'&x"53CE",'1'&x"53CF",
+--'1'&x"53D0",'1'&x"53D1",'1'&x"53D2",'1'&x"53D3",'1'&x"53D4",'1'&x"53D5",'1'&x"53D6",'1'&x"53D7",'1'&x"53D8",'1'&x"53D9",'1'&x"53DA",'1'&x"53DB",'1'&x"53DC",'1'&x"53DD",'1'&x"53DE",'1'&x"53DF",
+--'1'&x"53E0",'1'&x"53E1",'1'&x"53E2",'1'&x"53E3",'1'&x"53E4",'1'&x"53E5",'1'&x"53E6",'1'&x"53E7",'1'&x"53E8",'1'&x"53E9",'1'&x"53EA",'1'&x"53EB",'1'&x"53EC",'1'&x"53ED",'1'&x"53EE",'1'&x"53EF",
+--'1'&x"53F0",'1'&x"53F1",'1'&x"53F2",'1'&x"53F3",'1'&x"53F4",'1'&x"53F5",'1'&x"53F6",'1'&x"53F7",'1'&x"53F8",'1'&x"53F9",'1'&x"53FA",'1'&x"53FB",'1'&x"53FC",'1'&x"53FD",'1'&x"53FE",'1'&x"53FF",
+--'1'&x"5400",'1'&x"5401",'1'&x"5402",'1'&x"5403",'1'&x"5404",'1'&x"5405",'1'&x"5406",'1'&x"5407",'1'&x"5408",'1'&x"5409",'1'&x"540A",'1'&x"540B",'1'&x"540C",'1'&x"540D",'1'&x"540E",'1'&x"540F",
+--'1'&x"5410",'1'&x"5411",'1'&x"5412",'1'&x"5413",'1'&x"5414",'1'&x"5415",'1'&x"5416",'1'&x"5417",'1'&x"5418",'1'&x"5419",'1'&x"541A",'1'&x"541B",'1'&x"541C",'1'&x"541D",'1'&x"541E",'1'&x"541F",
+--'1'&x"5420",'1'&x"5421",'1'&x"5422",'1'&x"5423",'1'&x"5424",'1'&x"5425",'1'&x"5426",'1'&x"5427",'1'&x"5428",'1'&x"5429",'1'&x"542A",'1'&x"542B",'1'&x"542C",'1'&x"542D",'1'&x"542E",'1'&x"542F",
+--'1'&x"5430",'1'&x"5431",'1'&x"5432",'1'&x"5433",'1'&x"5434",'1'&x"5435",'1'&x"5436",'1'&x"5437",'1'&x"5438",'1'&x"5439",'1'&x"543A",'1'&x"543B",'1'&x"543C",'1'&x"543D",'1'&x"543E",'1'&x"543F",
+--'1'&x"5440",'1'&x"5441",'1'&x"5442",'1'&x"5443",'1'&x"5444",'1'&x"5445",'1'&x"5446",'1'&x"5447",'1'&x"5448",'1'&x"5449",'1'&x"544A",'1'&x"544B",'1'&x"544C",'1'&x"544D",'1'&x"544E",'1'&x"544F",
+--'1'&x"5450",'1'&x"5451",'1'&x"5452",'1'&x"5453",'1'&x"5454",'1'&x"5455",'1'&x"5456",'1'&x"5457",'1'&x"5458",'1'&x"5459",'1'&x"545A",'1'&x"545B",'1'&x"545C",'1'&x"545D",'1'&x"545E",'1'&x"545F",
+--'1'&x"5460",'1'&x"5461",'1'&x"5462",'1'&x"5463",'1'&x"5464",'1'&x"5465",'1'&x"5466",'1'&x"5467",'1'&x"5468",'1'&x"5469",'1'&x"546A",'1'&x"546B",'1'&x"546C",'1'&x"546D",'1'&x"546E",'1'&x"546F",
+--'1'&x"5470",'1'&x"5471",'1'&x"5472",'1'&x"5473",'1'&x"5474",'1'&x"5475",'1'&x"5476",'1'&x"5477",'1'&x"5478",'1'&x"5479",'1'&x"547A",'1'&x"547B",'1'&x"547C",'1'&x"547D",'1'&x"547E",'1'&x"547F",
+--'1'&x"5480",'1'&x"5481",'1'&x"5482",'1'&x"5483",'1'&x"5484",'1'&x"5485",'1'&x"5486",'1'&x"5487",'1'&x"5488",'1'&x"5489",'1'&x"548A",'1'&x"548B",'1'&x"548C",'1'&x"548D",'1'&x"548E",'1'&x"548F",
+--'1'&x"5490",'1'&x"5491",'1'&x"5492",'1'&x"5493",'1'&x"5494",'1'&x"5495",'1'&x"5496",'1'&x"5497",'1'&x"5498",'1'&x"5499",'1'&x"549A",'1'&x"549B",'1'&x"549C",'1'&x"549D",'1'&x"549E",'1'&x"549F",
+--'1'&x"54A0",'1'&x"54A1",'1'&x"54A2",'1'&x"54A3",'1'&x"54A4",'1'&x"54A5",'1'&x"54A6",'1'&x"54A7",'1'&x"54A8",'1'&x"54A9",'1'&x"54AA",'1'&x"54AB",'1'&x"54AC",'1'&x"54AD",'1'&x"54AE",'1'&x"54AF",
+--'1'&x"54B0",'1'&x"54B1",'1'&x"54B2",'1'&x"54B3",'1'&x"54B4",'1'&x"54B5",'1'&x"54B6",'1'&x"54B7",'1'&x"54B8",'1'&x"54B9",'1'&x"54BA",'1'&x"54BB",'1'&x"54BC",'1'&x"54BD",'1'&x"54BE",'1'&x"54BF",
+--'1'&x"54C0",'1'&x"54C1",'1'&x"54C2",'1'&x"54C3",'1'&x"54C4",'1'&x"54C5",'1'&x"54C6",'1'&x"54C7",'1'&x"54C8",'1'&x"54C9",'1'&x"54CA",'1'&x"54CB",'1'&x"54CC",'1'&x"54CD",'1'&x"54CE",'1'&x"54CF",
+--'1'&x"54D0",'1'&x"54D1",'1'&x"54D2",'1'&x"54D3",'1'&x"54D4",'1'&x"54D5",'1'&x"54D6",'1'&x"54D7",'1'&x"54D8",'1'&x"54D9",'1'&x"54DA",'1'&x"54DB",'1'&x"54DC",'1'&x"54DD",'1'&x"54DE",'1'&x"54DF",
+--'1'&x"54E0",'1'&x"54E1",'1'&x"54E2",'1'&x"54E3",'1'&x"54E4",'1'&x"54E5",'1'&x"54E6",'1'&x"54E7",'1'&x"54E8",'1'&x"54E9",'1'&x"54EA",'1'&x"54EB",'1'&x"54EC",'1'&x"54ED",'1'&x"54EE",'1'&x"54EF",
+--'1'&x"54F0",'1'&x"54F1",'1'&x"54F2",'1'&x"54F3",'1'&x"54F4",'1'&x"54F5",'1'&x"54F6",'1'&x"54F7",'1'&x"54F8",'1'&x"54F9",'1'&x"54FA",'1'&x"54FB",'1'&x"54FC",'1'&x"54FD",'1'&x"54FE",'1'&x"54FF",
+--'1'&x"5500",'1'&x"5501",'1'&x"5502",'1'&x"5503",'1'&x"5504",'1'&x"5505",'1'&x"5506",'1'&x"5507",'1'&x"5508",'1'&x"5509",'1'&x"550A",'1'&x"550B",'1'&x"550C",'1'&x"550D",'1'&x"550E",'1'&x"550F",
+--'1'&x"5510",'1'&x"5511",'1'&x"5512",'1'&x"5513",'1'&x"5514",'1'&x"5515",'1'&x"5516",'1'&x"5517",'1'&x"5518",'1'&x"5519",'1'&x"551A",'1'&x"551B",'1'&x"551C",'1'&x"551D",'1'&x"551E",'1'&x"551F",
+--'1'&x"5520",'1'&x"5521",'1'&x"5522",'1'&x"5523",'1'&x"5524",'1'&x"5525",'1'&x"5526",'1'&x"5527",'1'&x"5528",'1'&x"5529",'1'&x"552A",'1'&x"552B",'1'&x"552C",'1'&x"552D",'1'&x"552E",'1'&x"552F",
+--'1'&x"5530",'1'&x"5531",'1'&x"5532",'1'&x"5533",'1'&x"5534",'1'&x"5535",'1'&x"5536",'1'&x"5537",'1'&x"5538",'1'&x"5539",'1'&x"553A",'1'&x"553B",'1'&x"553C",'1'&x"553D",'1'&x"553E",'1'&x"553F",
+--'1'&x"5540",'1'&x"5541",'1'&x"5542",'1'&x"5543",'1'&x"5544",'1'&x"5545",'1'&x"5546",'1'&x"5547",'1'&x"5548",'1'&x"5549",'1'&x"554A",'1'&x"554B",'1'&x"554C",'1'&x"554D",'1'&x"554E",'1'&x"554F",
+--'1'&x"5550",'1'&x"5551",'1'&x"5552",'1'&x"5553",'1'&x"5554",'1'&x"5555",'1'&x"5556",'1'&x"5557",'1'&x"5558",'1'&x"5559",'1'&x"555A",'1'&x"555B",'1'&x"555C",'1'&x"555D",'1'&x"555E",'1'&x"555F",
+--'1'&x"5560",'1'&x"5561",'1'&x"5562",'1'&x"5563",'1'&x"5564",'1'&x"5565",'1'&x"5566",'1'&x"5567",'1'&x"5568",'1'&x"5569",'1'&x"556A",'1'&x"556B",'1'&x"556C",'1'&x"556D",'1'&x"556E",'1'&x"556F",
+--'1'&x"5570",'1'&x"5571",'1'&x"5572",'1'&x"5573",'1'&x"5574",'1'&x"5575",'1'&x"5576",'1'&x"5577",'1'&x"5578",'1'&x"5579",'1'&x"557A",'1'&x"557B",'1'&x"557C",'1'&x"557D",'1'&x"557E",'1'&x"557F",
+--'1'&x"5580",'1'&x"5581",'1'&x"5582",'1'&x"5583",'1'&x"5584",'1'&x"5585",'1'&x"5586",'1'&x"5587",'1'&x"5588",'1'&x"5589",'1'&x"558A",'1'&x"558B",'1'&x"558C",'1'&x"558D",'1'&x"558E",'1'&x"558F",
+--'1'&x"5590",'1'&x"5591",'1'&x"5592",'1'&x"5593",'1'&x"5594",'1'&x"5595",'1'&x"5596",'1'&x"5597",'1'&x"5598",'1'&x"5599",'1'&x"559A",'1'&x"559B",'1'&x"559C",'1'&x"559D",'1'&x"559E",'1'&x"559F",
+--'1'&x"55A0",'1'&x"55A1",'1'&x"55A2",'1'&x"55A3",'1'&x"55A4",'1'&x"55A5",'1'&x"55A6",'1'&x"55A7",'1'&x"55A8",'1'&x"55A9",'1'&x"55AA",'1'&x"55AB",'1'&x"55AC",'1'&x"55AD",'1'&x"55AE",'1'&x"55AF",
+--'1'&x"55B0",'1'&x"55B1",'1'&x"55B2",'1'&x"55B3",'1'&x"55B4",'1'&x"55B5",'1'&x"55B6",'1'&x"55B7",'1'&x"55B8",'1'&x"55B9",'1'&x"55BA",'1'&x"55BB",'1'&x"55BC",'1'&x"55BD",'1'&x"55BE",'1'&x"55BF",
+--'1'&x"55C0",'1'&x"55C1",'1'&x"55C2",'1'&x"55C3",'1'&x"55C4",'1'&x"55C5",'1'&x"55C6",'1'&x"55C7",'1'&x"55C8",'1'&x"55C9",'1'&x"55CA",'1'&x"55CB",'1'&x"55CC",'1'&x"55CD",'1'&x"55CE",'1'&x"55CF",
+--'1'&x"55D0",'1'&x"55D1",'1'&x"55D2",'1'&x"55D3",'1'&x"55D4",'1'&x"55D5",'1'&x"55D6",'1'&x"55D7",'1'&x"55D8",'1'&x"55D9",'1'&x"55DA",'1'&x"55DB",'1'&x"55DC",'1'&x"55DD",'1'&x"55DE",'1'&x"55DF",
+--'1'&x"55E0",'1'&x"55E1",'1'&x"55E2",'1'&x"55E3",'1'&x"55E4",'1'&x"55E5",'1'&x"55E6",'1'&x"55E7",'1'&x"55E8",'1'&x"55E9",'1'&x"55EA",'1'&x"55EB",'1'&x"55EC",'1'&x"55ED",'1'&x"55EE",'1'&x"55EF",
+--'1'&x"55F0",'1'&x"55F1",'1'&x"55F2",'1'&x"55F3",'1'&x"55F4",'1'&x"55F5",'1'&x"55F6",'1'&x"55F7",'1'&x"55F8",'1'&x"55F9",'1'&x"55FA",'1'&x"55FB",'1'&x"55FC",'1'&x"55FD",'1'&x"55FE",'1'&x"55FF",
+--'1'&x"5600",'1'&x"5601",'1'&x"5602",'1'&x"5603",'1'&x"5604",'1'&x"5605",'1'&x"5606",'1'&x"5607",'1'&x"5608",'1'&x"5609",'1'&x"560A",'1'&x"560B",'1'&x"560C",'1'&x"560D",'1'&x"560E",'1'&x"560F",
+--'1'&x"5610",'1'&x"5611",'1'&x"5612",'1'&x"5613",'1'&x"5614",'1'&x"5615",'1'&x"5616",'1'&x"5617",'1'&x"5618",'1'&x"5619",'1'&x"561A",'1'&x"561B",'1'&x"561C",'1'&x"561D",'1'&x"561E",'1'&x"561F",
+--'1'&x"5620",'1'&x"5621",'1'&x"5622",'1'&x"5623",'1'&x"5624",'1'&x"5625",'1'&x"5626",'1'&x"5627",'1'&x"5628",'1'&x"5629",'1'&x"562A",'1'&x"562B",'1'&x"562C",'1'&x"562D",'1'&x"562E",'1'&x"562F",
+--'1'&x"5630",'1'&x"5631",'1'&x"5632",'1'&x"5633",'1'&x"5634",'1'&x"5635",'1'&x"5636",'1'&x"5637",'1'&x"5638",'1'&x"5639",'1'&x"563A",'1'&x"563B",'1'&x"563C",'1'&x"563D",'1'&x"563E",'1'&x"563F",
+--'1'&x"5640",'1'&x"5641",'1'&x"5642",'1'&x"5643",'1'&x"5644",'1'&x"5645",'1'&x"5646",'1'&x"5647",'1'&x"5648",'1'&x"5649",'1'&x"564A",'1'&x"564B",'1'&x"564C",'1'&x"564D",'1'&x"564E",'1'&x"564F",
+--'1'&x"5650",'1'&x"5651",'1'&x"5652",'1'&x"5653",'1'&x"5654",'1'&x"5655",'1'&x"5656",'1'&x"5657",'1'&x"5658",'1'&x"5659",'1'&x"565A",'1'&x"565B",'1'&x"565C",'1'&x"565D",'1'&x"565E",'1'&x"565F",
+--'1'&x"5660",'1'&x"5661",'1'&x"5662",'1'&x"5663",'1'&x"5664",'1'&x"5665",'1'&x"5666",'1'&x"5667",'1'&x"5668",'1'&x"5669",'1'&x"566A",'1'&x"566B",'1'&x"566C",'1'&x"566D",'1'&x"566E",'1'&x"566F",
+--'1'&x"5670",'1'&x"5671",'1'&x"5672",'1'&x"5673",'1'&x"5674",'1'&x"5675",'1'&x"5676",'1'&x"5677",'1'&x"5678",'1'&x"5679",'1'&x"567A",'1'&x"567B",'1'&x"567C",'1'&x"567D",'1'&x"567E",'1'&x"567F",
+--'1'&x"5680",'1'&x"5681",'1'&x"5682",'1'&x"5683",'1'&x"5684",'1'&x"5685",'1'&x"5686",'1'&x"5687",'1'&x"5688",'1'&x"5689",'1'&x"568A",'1'&x"568B",'1'&x"568C",'1'&x"568D",'1'&x"568E",'1'&x"568F",
+--'1'&x"5690",'1'&x"5691",'1'&x"5692",'1'&x"5693",'1'&x"5694",'1'&x"5695",'1'&x"5696",'1'&x"5697",'1'&x"5698",'1'&x"5699",'1'&x"569A",'1'&x"569B",'1'&x"569C",'1'&x"569D",'1'&x"569E",'1'&x"569F",
+--'1'&x"56A0",'1'&x"56A1",'1'&x"56A2",'1'&x"56A3",'1'&x"56A4",'1'&x"56A5",'1'&x"56A6",'1'&x"56A7",'1'&x"56A8",'1'&x"56A9",'1'&x"56AA",'1'&x"56AB",'1'&x"56AC",'1'&x"56AD",'1'&x"56AE",'1'&x"56AF",
+--'1'&x"56B0",'1'&x"56B1",'1'&x"56B2",'1'&x"56B3",'1'&x"56B4",'1'&x"56B5",'1'&x"56B6",'1'&x"56B7",'1'&x"56B8",'1'&x"56B9",'1'&x"56BA",'1'&x"56BB",'1'&x"56BC",'1'&x"56BD",'1'&x"56BE",'1'&x"56BF",
+--'1'&x"56C0",'1'&x"56C1",'1'&x"56C2",'1'&x"56C3",'1'&x"56C4",'1'&x"56C5",'1'&x"56C6",'1'&x"56C7",'1'&x"56C8",'1'&x"56C9",'1'&x"56CA",'1'&x"56CB",'1'&x"56CC",'1'&x"56CD",'1'&x"56CE",'1'&x"56CF",
+--'1'&x"56D0",'1'&x"56D1",'1'&x"56D2",'1'&x"56D3",'1'&x"56D4",'1'&x"56D5",'1'&x"56D6",'1'&x"56D7",'1'&x"56D8",'1'&x"56D9",'1'&x"56DA",'1'&x"56DB",'1'&x"56DC",'1'&x"56DD",'1'&x"56DE",'1'&x"56DF",
+--'1'&x"56E0",'1'&x"56E1",'1'&x"56E2",'1'&x"56E3",'1'&x"56E4",'1'&x"56E5",'1'&x"56E6",'1'&x"56E7",'1'&x"56E8",'1'&x"56E9",'1'&x"56EA",'1'&x"56EB",'1'&x"56EC",'1'&x"56ED",'1'&x"56EE",'1'&x"56EF",
+--'1'&x"56F0",'1'&x"56F1",'1'&x"56F2",'1'&x"56F3",'1'&x"56F4",'1'&x"56F5",'1'&x"56F6",'1'&x"56F7",'1'&x"56F8",'1'&x"56F9",'1'&x"56FA",'1'&x"56FB",'1'&x"56FC",'1'&x"56FD",'1'&x"56FE",'1'&x"56FF",
+--'1'&x"5700",'1'&x"5701",'1'&x"5702",'1'&x"5703",'1'&x"5704",'1'&x"5705",'1'&x"5706",'1'&x"5707",'1'&x"5708",'1'&x"5709",'1'&x"570A",'1'&x"570B",'1'&x"570C",'1'&x"570D",'1'&x"570E",'1'&x"570F",
+--'1'&x"5710",'1'&x"5711",'1'&x"5712",'1'&x"5713",'1'&x"5714",'1'&x"5715",'1'&x"5716",'1'&x"5717",'1'&x"5718",'1'&x"5719",'1'&x"571A",'1'&x"571B",'1'&x"571C",'1'&x"571D",'1'&x"571E",'1'&x"571F",
+--'1'&x"5720",'1'&x"5721",'1'&x"5722",'1'&x"5723",'1'&x"5724",'1'&x"5725",'1'&x"5726",'1'&x"5727",'1'&x"5728",'1'&x"5729",'1'&x"572A",'1'&x"572B",'1'&x"572C",'1'&x"572D",'1'&x"572E",'1'&x"572F",
+--'1'&x"5730",'1'&x"5731",'1'&x"5732",'1'&x"5733",'1'&x"5734",'1'&x"5735",'1'&x"5736",'1'&x"5737",'1'&x"5738",'1'&x"5739",'1'&x"573A",'1'&x"573B",'1'&x"573C",'1'&x"573D",'1'&x"573E",'1'&x"573F",
+--'1'&x"5740",'1'&x"5741",'1'&x"5742",'1'&x"5743",'1'&x"5744",'1'&x"5745",'1'&x"5746",'1'&x"5747",'1'&x"5748",'1'&x"5749",'1'&x"574A",'1'&x"574B",'1'&x"574C",'1'&x"574D",'1'&x"574E",'1'&x"574F",
+--'1'&x"5750",'1'&x"5751",'1'&x"5752",'1'&x"5753",'1'&x"5754",'1'&x"5755",'1'&x"5756",'1'&x"5757",'1'&x"5758",'1'&x"5759",'1'&x"575A",'1'&x"575B",'1'&x"575C",'1'&x"575D",'1'&x"575E",'1'&x"575F",
+--'1'&x"5760",'1'&x"5761",'1'&x"5762",'1'&x"5763",'1'&x"5764",'1'&x"5765",'1'&x"5766",'1'&x"5767",'1'&x"5768",'1'&x"5769",'1'&x"576A",'1'&x"576B",'1'&x"576C",'1'&x"576D",'1'&x"576E",'1'&x"576F",
+--'1'&x"5770",'1'&x"5771",'1'&x"5772",'1'&x"5773",'1'&x"5774",'1'&x"5775",'1'&x"5776",'1'&x"5777",'1'&x"5778",'1'&x"5779",'1'&x"577A",'1'&x"577B",'1'&x"577C",'1'&x"577D",'1'&x"577E",'1'&x"577F",
+--'1'&x"5780",'1'&x"5781",'1'&x"5782",'1'&x"5783",'1'&x"5784",'1'&x"5785",'1'&x"5786",'1'&x"5787",'1'&x"5788",'1'&x"5789",'1'&x"578A",'1'&x"578B",'1'&x"578C",'1'&x"578D",'1'&x"578E",'1'&x"578F",
+--'1'&x"5790",'1'&x"5791",'1'&x"5792",'1'&x"5793",'1'&x"5794",'1'&x"5795",'1'&x"5796",'1'&x"5797",'1'&x"5798",'1'&x"5799",'1'&x"579A",'1'&x"579B",'1'&x"579C",'1'&x"579D",'1'&x"579E",'1'&x"579F",
+--'1'&x"57A0",'1'&x"57A1",'1'&x"57A2",'1'&x"57A3",'1'&x"57A4",'1'&x"57A5",'1'&x"57A6",'1'&x"57A7",'1'&x"57A8",'1'&x"57A9",'1'&x"57AA",'1'&x"57AB",'1'&x"57AC",'1'&x"57AD",'1'&x"57AE",'1'&x"57AF",
+--'1'&x"57B0",'1'&x"57B1",'1'&x"57B2",'1'&x"57B3",'1'&x"57B4",'1'&x"57B5",'1'&x"57B6",'1'&x"57B7",'1'&x"57B8",'1'&x"57B9",'1'&x"57BA",'1'&x"57BB",'1'&x"57BC",'1'&x"57BD",'1'&x"57BE",'1'&x"57BF",
+--'1'&x"57C0",'1'&x"57C1",'1'&x"57C2",'1'&x"57C3",'1'&x"57C4",'1'&x"57C5",'1'&x"57C6",'1'&x"57C7",'1'&x"57C8",'1'&x"57C9",'1'&x"57CA",'1'&x"57CB",'1'&x"57CC",'1'&x"57CD",'1'&x"57CE",'1'&x"57CF",
+--'1'&x"57D0",'1'&x"57D1",'1'&x"57D2",'1'&x"57D3",'1'&x"57D4",'1'&x"57D5",'1'&x"57D6",'1'&x"57D7",'1'&x"57D8",'1'&x"57D9",'1'&x"57DA",'1'&x"57DB",'1'&x"57DC",'1'&x"57DD",'1'&x"57DE",'1'&x"57DF",
+--'1'&x"57E0",'1'&x"57E1",'1'&x"57E2",'1'&x"57E3",'1'&x"57E4",'1'&x"57E5",'1'&x"57E6",'1'&x"57E7",'1'&x"57E8",'1'&x"57E9",'1'&x"57EA",'1'&x"57EB",'1'&x"57EC",'1'&x"57ED",'1'&x"57EE",'1'&x"57EF",
+--'1'&x"57F0",'1'&x"57F1",'1'&x"57F2",'1'&x"57F3",'1'&x"57F4",'1'&x"57F5",'1'&x"57F6",'1'&x"57F7",'1'&x"57F8",'1'&x"57F9",'1'&x"57FA",'1'&x"57FB",'1'&x"57FC",'1'&x"57FD",'1'&x"57FE",'1'&x"57FF",
+--'1'&x"5800",'1'&x"5801",'1'&x"5802",'1'&x"5803",'1'&x"5804",'1'&x"5805",'1'&x"5806",'1'&x"5807",'1'&x"5808",'1'&x"5809",'1'&x"580A",'1'&x"580B",'1'&x"580C",'1'&x"580D",'1'&x"580E",'1'&x"580F",
+--'1'&x"5810",'1'&x"5811",'1'&x"5812",'1'&x"5813",'1'&x"5814",'1'&x"5815",'1'&x"5816",'1'&x"5817",'1'&x"5818",'1'&x"5819",'1'&x"581A",'1'&x"581B",'1'&x"581C",'1'&x"581D",'1'&x"581E",'1'&x"581F",
+--'1'&x"5820",'1'&x"5821",'1'&x"5822",'1'&x"5823",'1'&x"5824",'1'&x"5825",'1'&x"5826",'1'&x"5827",'1'&x"5828",'1'&x"5829",'1'&x"582A",'1'&x"582B",'1'&x"582C",'1'&x"582D",'1'&x"582E",'1'&x"582F",
+--'1'&x"5830",'1'&x"5831",'1'&x"5832",'1'&x"5833",'1'&x"5834",'1'&x"5835",'1'&x"5836",'1'&x"5837",'1'&x"5838",'1'&x"5839",'1'&x"583A",'1'&x"583B",'1'&x"583C",'1'&x"583D",'1'&x"583E",'1'&x"583F",
+--'1'&x"5840",'1'&x"5841",'1'&x"5842",'1'&x"5843",'1'&x"5844",'1'&x"5845",'1'&x"5846",'1'&x"5847",'1'&x"5848",'1'&x"5849",'1'&x"584A",'1'&x"584B",'1'&x"584C",'1'&x"584D",'1'&x"584E",'1'&x"584F",
+--'1'&x"5850",'1'&x"5851",'1'&x"5852",'1'&x"5853",'1'&x"5854",'1'&x"5855",'1'&x"5856",'1'&x"5857",'1'&x"5858",'1'&x"5859",'1'&x"585A",'1'&x"585B",'1'&x"585C",'1'&x"585D",'1'&x"585E",'1'&x"585F",
+--'1'&x"5860",'1'&x"5861",'1'&x"5862",'1'&x"5863",'1'&x"5864",'1'&x"5865",'1'&x"5866",'1'&x"5867",'1'&x"5868",'1'&x"5869",'1'&x"586A",'1'&x"586B",'1'&x"586C",'1'&x"586D",'1'&x"586E",'1'&x"586F",
+--'1'&x"5870",'1'&x"5871",'1'&x"5872",'1'&x"5873",'1'&x"5874",'1'&x"5875",'1'&x"5876",'1'&x"5877",'1'&x"5878",'1'&x"5879",'1'&x"587A",'1'&x"587B",'1'&x"587C",'1'&x"587D",'1'&x"587E",'1'&x"587F",
+--'1'&x"5880",'1'&x"5881",'1'&x"5882",'1'&x"5883",'1'&x"5884",'1'&x"5885",'1'&x"5886",'1'&x"5887",'1'&x"5888",'1'&x"5889",'1'&x"588A",'1'&x"588B",'1'&x"588C",'1'&x"588D",'1'&x"588E",'1'&x"588F",
+--'1'&x"5890",'1'&x"5891",'1'&x"5892",'1'&x"5893",'1'&x"5894",'1'&x"5895",'1'&x"5896",'1'&x"5897",'1'&x"5898",'1'&x"5899",'1'&x"589A",'1'&x"589B",'1'&x"589C",'1'&x"589D",'1'&x"589E",'1'&x"589F",
+--'1'&x"58A0",'1'&x"58A1",'1'&x"58A2",'1'&x"58A3",'1'&x"58A4",'1'&x"58A5",'1'&x"58A6",'1'&x"58A7",'1'&x"58A8",'1'&x"58A9",'1'&x"58AA",'1'&x"58AB",'1'&x"58AC",'1'&x"58AD",'1'&x"58AE",'1'&x"58AF",
+--'1'&x"58B0",'1'&x"58B1",'1'&x"58B2",'1'&x"58B3",'1'&x"58B4",'1'&x"58B5",'1'&x"58B6",'1'&x"58B7",'1'&x"58B8",'1'&x"58B9",'1'&x"58BA",'1'&x"58BB",'1'&x"58BC",'1'&x"58BD",'1'&x"58BE",'1'&x"58BF",
+--'1'&x"58C0",'1'&x"58C1",'1'&x"58C2",'1'&x"58C3",'1'&x"58C4",'1'&x"58C5",'1'&x"58C6",'1'&x"58C7",'1'&x"58C8",'1'&x"58C9",'1'&x"58CA",'1'&x"58CB",'1'&x"58CC",'1'&x"58CD",'1'&x"58CE",'1'&x"58CF",
+--'1'&x"58D0",'1'&x"58D1",'1'&x"58D2",'1'&x"58D3",'1'&x"58D4",'1'&x"58D5",'1'&x"58D6",'1'&x"58D7",'1'&x"58D8",'1'&x"58D9",'1'&x"58DA",'1'&x"58DB",'1'&x"58DC",'1'&x"58DD",'1'&x"58DE",'1'&x"58DF",
+--'1'&x"58E0",'1'&x"58E1",'1'&x"58E2",'1'&x"58E3",'1'&x"58E4",'1'&x"58E5",'1'&x"58E6",'1'&x"58E7",'1'&x"58E8",'1'&x"58E9",'1'&x"58EA",'1'&x"58EB",'1'&x"58EC",'1'&x"58ED",'1'&x"58EE",'1'&x"58EF",
+--'1'&x"58F0",'1'&x"58F1",'1'&x"58F2",'1'&x"58F3",'1'&x"58F4",'1'&x"58F5",'1'&x"58F6",'1'&x"58F7",'1'&x"58F8",'1'&x"58F9",'1'&x"58FA",'1'&x"58FB",'1'&x"58FC",'1'&x"58FD",'1'&x"58FE",'1'&x"58FF",
+--'1'&x"5900",'1'&x"5901",'1'&x"5902",'1'&x"5903",'1'&x"5904",'1'&x"5905",'1'&x"5906",'1'&x"5907",'1'&x"5908",'1'&x"5909",'1'&x"590A",'1'&x"590B",'1'&x"590C",'1'&x"590D",'1'&x"590E",'1'&x"590F",
+--'1'&x"5910",'1'&x"5911",'1'&x"5912",'1'&x"5913",'1'&x"5914",'1'&x"5915",'1'&x"5916",'1'&x"5917",'1'&x"5918",'1'&x"5919",'1'&x"591A",'1'&x"591B",'1'&x"591C",'1'&x"591D",'1'&x"591E",'1'&x"591F",
+--'1'&x"5920",'1'&x"5921",'1'&x"5922",'1'&x"5923",'1'&x"5924",'1'&x"5925",'1'&x"5926",'1'&x"5927",'1'&x"5928",'1'&x"5929",'1'&x"592A",'1'&x"592B",'1'&x"592C",'1'&x"592D",'1'&x"592E",'1'&x"592F",
+--'1'&x"5930",'1'&x"5931",'1'&x"5932",'1'&x"5933",'1'&x"5934",'1'&x"5935",'1'&x"5936",'1'&x"5937",'1'&x"5938",'1'&x"5939",'1'&x"593A",'1'&x"593B",'1'&x"593C",'1'&x"593D",'1'&x"593E",'1'&x"593F",
+--'1'&x"5940",'1'&x"5941",'1'&x"5942",'1'&x"5943",'1'&x"5944",'1'&x"5945",'1'&x"5946",'1'&x"5947",'1'&x"5948",'1'&x"5949",'1'&x"594A",'1'&x"594B",'1'&x"594C",'1'&x"594D",'1'&x"594E",'1'&x"594F",
+--'1'&x"5950",'1'&x"5951",'1'&x"5952",'1'&x"5953",'1'&x"5954",'1'&x"5955",'1'&x"5956",'1'&x"5957",'1'&x"5958",'1'&x"5959",'1'&x"595A",'1'&x"595B",'1'&x"595C",'1'&x"595D",'1'&x"595E",'1'&x"595F",
+--'1'&x"5960",'1'&x"5961",'1'&x"5962",'1'&x"5963",'1'&x"5964",'1'&x"5965",'1'&x"5966",'1'&x"5967",'1'&x"5968",'1'&x"5969",'1'&x"596A",'1'&x"596B",'1'&x"596C",'1'&x"596D",'1'&x"596E",'1'&x"596F",
+--'1'&x"5970",'1'&x"5971",'1'&x"5972",'1'&x"5973",'1'&x"5974",'1'&x"5975",'1'&x"5976",'1'&x"5977",'1'&x"5978",'1'&x"5979",'1'&x"597A",'1'&x"597B",'1'&x"597C",'1'&x"597D",'1'&x"597E",'1'&x"597F",
+--'1'&x"5980",'1'&x"5981",'1'&x"5982",'1'&x"5983",'1'&x"5984",'1'&x"5985",'1'&x"5986",'1'&x"5987",'1'&x"5988",'1'&x"5989",'1'&x"598A",'1'&x"598B",'1'&x"598C",'1'&x"598D",'1'&x"598E",'1'&x"598F",
+--'1'&x"5990",'1'&x"5991",'1'&x"5992",'1'&x"5993",'1'&x"5994",'1'&x"5995",'1'&x"5996",'1'&x"5997",'1'&x"5998",'1'&x"5999",'1'&x"599A",'1'&x"599B",'1'&x"599C",'1'&x"599D",'1'&x"599E",'1'&x"599F",
+--'1'&x"59A0",'1'&x"59A1",'1'&x"59A2",'1'&x"59A3",'1'&x"59A4",'1'&x"59A5",'1'&x"59A6",'1'&x"59A7",'1'&x"59A8",'1'&x"59A9",'1'&x"59AA",'1'&x"59AB",'1'&x"59AC",'1'&x"59AD",'1'&x"59AE",'1'&x"59AF",
+--'1'&x"59B0",'1'&x"59B1",'1'&x"59B2",'1'&x"59B3",'1'&x"59B4",'1'&x"59B5",'1'&x"59B6",'1'&x"59B7",'1'&x"59B8",'1'&x"59B9",'1'&x"59BA",'1'&x"59BB",'1'&x"59BC",'1'&x"59BD",'1'&x"59BE",'1'&x"59BF",
+--'1'&x"59C0",'1'&x"59C1",'1'&x"59C2",'1'&x"59C3",'1'&x"59C4",'1'&x"59C5",'1'&x"59C6",'1'&x"59C7",'1'&x"59C8",'1'&x"59C9",'1'&x"59CA",'1'&x"59CB",'1'&x"59CC",'1'&x"59CD",'1'&x"59CE",'1'&x"59CF",
+--'1'&x"59D0",'1'&x"59D1",'1'&x"59D2",'1'&x"59D3",'1'&x"59D4",'1'&x"59D5",'1'&x"59D6",'1'&x"59D7",'1'&x"59D8",'1'&x"59D9",'1'&x"59DA",'1'&x"59DB",'1'&x"59DC",'1'&x"59DD",'1'&x"59DE",'1'&x"59DF",
+--'1'&x"59E0",'1'&x"59E1",'1'&x"59E2",'1'&x"59E3",'1'&x"59E4",'1'&x"59E5",'1'&x"59E6",'1'&x"59E7",'1'&x"59E8",'1'&x"59E9",'1'&x"59EA",'1'&x"59EB",'1'&x"59EC",'1'&x"59ED",'1'&x"59EE",'1'&x"59EF",
+--'1'&x"59F0",'1'&x"59F1",'1'&x"59F2",'1'&x"59F3",'1'&x"59F4",'1'&x"59F5",'1'&x"59F6",'1'&x"59F7",'1'&x"59F8",'1'&x"59F9",'1'&x"59FA",'1'&x"59FB",'1'&x"59FC",'1'&x"59FD",'1'&x"59FE",'1'&x"59FF",
+--'1'&x"5A00",'1'&x"5A01",'1'&x"5A02",'1'&x"5A03",'1'&x"5A04",'1'&x"5A05",'1'&x"5A06",'1'&x"5A07",'1'&x"5A08",'1'&x"5A09",'1'&x"5A0A",'1'&x"5A0B",'1'&x"5A0C",'1'&x"5A0D",'1'&x"5A0E",'1'&x"5A0F",
+--'1'&x"5A10",'1'&x"5A11",'1'&x"5A12",'1'&x"5A13",'1'&x"5A14",'1'&x"5A15",'1'&x"5A16",'1'&x"5A17",'1'&x"5A18",'1'&x"5A19",'1'&x"5A1A",'1'&x"5A1B",'1'&x"5A1C",'1'&x"5A1D",'1'&x"5A1E",'1'&x"5A1F",
+--'1'&x"5A20",'1'&x"5A21",'1'&x"5A22",'1'&x"5A23",'1'&x"5A24",'1'&x"5A25",'1'&x"5A26",'1'&x"5A27",'1'&x"5A28",'1'&x"5A29",'1'&x"5A2A",'1'&x"5A2B",'1'&x"5A2C",'1'&x"5A2D",'1'&x"5A2E",'1'&x"5A2F",
+--'1'&x"5A30",'1'&x"5A31",'1'&x"5A32",'1'&x"5A33",'1'&x"5A34",'1'&x"5A35",'1'&x"5A36",'1'&x"5A37",'1'&x"5A38",'1'&x"5A39",'1'&x"5A3A",'1'&x"5A3B",'1'&x"5A3C",'1'&x"5A3D",'1'&x"5A3E",'1'&x"5A3F",
+--'1'&x"5A40",'1'&x"5A41",'1'&x"5A42",'1'&x"5A43",'1'&x"5A44",'1'&x"5A45",'1'&x"5A46",'1'&x"5A47",'1'&x"5A48",'1'&x"5A49",'1'&x"5A4A",'1'&x"5A4B",'1'&x"5A4C",'1'&x"5A4D",'1'&x"5A4E",'1'&x"5A4F",
+--'1'&x"5A50",'1'&x"5A51",'1'&x"5A52",'1'&x"5A53",'1'&x"5A54",'1'&x"5A55",'1'&x"5A56",'1'&x"5A57",'1'&x"5A58",'1'&x"5A59",'1'&x"5A5A",'1'&x"5A5B",'1'&x"5A5C",'1'&x"5A5D",'1'&x"5A5E",'1'&x"5A5F",
+--'1'&x"5A60",'1'&x"5A61",'1'&x"5A62",'1'&x"5A63",'1'&x"5A64",'1'&x"5A65",'1'&x"5A66",'1'&x"5A67",'1'&x"5A68",'1'&x"5A69",'1'&x"5A6A",'1'&x"5A6B",'1'&x"5A6C",'1'&x"5A6D",'1'&x"5A6E",'1'&x"5A6F",
+--'1'&x"5A70",'1'&x"5A71",'1'&x"5A72",'1'&x"5A73",'1'&x"5A74",'1'&x"5A75",'1'&x"5A76",'1'&x"5A77",'1'&x"5A78",'1'&x"5A79",'1'&x"5A7A",'1'&x"5A7B",'1'&x"5A7C",'1'&x"5A7D",'1'&x"5A7E",'1'&x"5A7F",
+--'1'&x"5A80",'1'&x"5A81",'1'&x"5A82",'1'&x"5A83",'1'&x"5A84",'1'&x"5A85",'1'&x"5A86",'1'&x"5A87",'1'&x"5A88",'1'&x"5A89",'1'&x"5A8A",'1'&x"5A8B",'1'&x"5A8C",'1'&x"5A8D",'1'&x"5A8E",'1'&x"5A8F",
+--'1'&x"5A90",'1'&x"5A91",'1'&x"5A92",'1'&x"5A93",'1'&x"5A94",'1'&x"5A95",'1'&x"5A96",'1'&x"5A97",'1'&x"5A98",'1'&x"5A99",'1'&x"5A9A",'1'&x"5A9B",'1'&x"5A9C",'1'&x"5A9D",'1'&x"5A9E",'1'&x"5A9F",
+--'1'&x"5AA0",'1'&x"5AA1",'1'&x"5AA2",'1'&x"5AA3",'1'&x"5AA4",'1'&x"5AA5",'1'&x"5AA6",'1'&x"5AA7",'1'&x"5AA8",'1'&x"5AA9",'1'&x"5AAA",'1'&x"5AAB",'1'&x"5AAC",'1'&x"5AAD",'1'&x"5AAE",'1'&x"5AAF",
+--'1'&x"5AB0",'1'&x"5AB1",'1'&x"5AB2",'1'&x"5AB3",'1'&x"5AB4",'1'&x"5AB5",'1'&x"5AB6",'1'&x"5AB7",'1'&x"5AB8",'1'&x"5AB9",'1'&x"5ABA",'1'&x"5ABB",'1'&x"5ABC",'1'&x"5ABD",'1'&x"5ABE",'1'&x"5ABF",
+--'1'&x"5AC0",'1'&x"5AC1",'1'&x"5AC2",'1'&x"5AC3",'1'&x"5AC4",'1'&x"5AC5",'1'&x"5AC6",'1'&x"5AC7",'1'&x"5AC8",'1'&x"5AC9",'1'&x"5ACA",'1'&x"5ACB",'1'&x"5ACC",'1'&x"5ACD",'1'&x"5ACE",'1'&x"5ACF",
+--'1'&x"5AD0",'1'&x"5AD1",'1'&x"5AD2",'1'&x"5AD3",'1'&x"5AD4",'1'&x"5AD5",'1'&x"5AD6",'1'&x"5AD7",'1'&x"5AD8",'1'&x"5AD9",'1'&x"5ADA",'1'&x"5ADB",'1'&x"5ADC",'1'&x"5ADD",'1'&x"5ADE",'1'&x"5ADF",
+--'1'&x"5AE0",'1'&x"5AE1",'1'&x"5AE2",'1'&x"5AE3",'1'&x"5AE4",'1'&x"5AE5",'1'&x"5AE6",'1'&x"5AE7",'1'&x"5AE8",'1'&x"5AE9",'1'&x"5AEA",'1'&x"5AEB",'1'&x"5AEC",'1'&x"5AED",'1'&x"5AEE",'1'&x"5AEF",
+--'1'&x"5AF0",'1'&x"5AF1",'1'&x"5AF2",'1'&x"5AF3",'1'&x"5AF4",'1'&x"5AF5",'1'&x"5AF6",'1'&x"5AF7",'1'&x"5AF8",'1'&x"5AF9",'1'&x"5AFA",'1'&x"5AFB",'1'&x"5AFC",'1'&x"5AFD",'1'&x"5AFE",'1'&x"5AFF",
+--'1'&x"5B00",'1'&x"5B01",'1'&x"5B02",'1'&x"5B03",'1'&x"5B04",'1'&x"5B05",'1'&x"5B06",'1'&x"5B07",'1'&x"5B08",'1'&x"5B09",'1'&x"5B0A",'1'&x"5B0B",'1'&x"5B0C",'1'&x"5B0D",'1'&x"5B0E",'1'&x"5B0F",
+--'1'&x"5B10",'1'&x"5B11",'1'&x"5B12",'1'&x"5B13",'1'&x"5B14",'1'&x"5B15",'1'&x"5B16",'1'&x"5B17",'1'&x"5B18",'1'&x"5B19",'1'&x"5B1A",'1'&x"5B1B",'1'&x"5B1C",'1'&x"5B1D",'1'&x"5B1E",'1'&x"5B1F",
+--'1'&x"5B20",'1'&x"5B21",'1'&x"5B22",'1'&x"5B23",'1'&x"5B24",'1'&x"5B25",'1'&x"5B26",'1'&x"5B27",'1'&x"5B28",'1'&x"5B29",'1'&x"5B2A",'1'&x"5B2B",'1'&x"5B2C",'1'&x"5B2D",'1'&x"5B2E",'1'&x"5B2F",
+--'1'&x"5B30",'1'&x"5B31",'1'&x"5B32",'1'&x"5B33",'1'&x"5B34",'1'&x"5B35",'1'&x"5B36",'1'&x"5B37",'1'&x"5B38",'1'&x"5B39",'1'&x"5B3A",'1'&x"5B3B",'1'&x"5B3C",'1'&x"5B3D",'1'&x"5B3E",'1'&x"5B3F",
+--'1'&x"5B40",'1'&x"5B41",'1'&x"5B42",'1'&x"5B43",'1'&x"5B44",'1'&x"5B45",'1'&x"5B46",'1'&x"5B47",'1'&x"5B48",'1'&x"5B49",'1'&x"5B4A",'1'&x"5B4B",'1'&x"5B4C",'1'&x"5B4D",'1'&x"5B4E",'1'&x"5B4F",
+--'1'&x"5B50",'1'&x"5B51",'1'&x"5B52",'1'&x"5B53",'1'&x"5B54",'1'&x"5B55",'1'&x"5B56",'1'&x"5B57",'1'&x"5B58",'1'&x"5B59",'1'&x"5B5A",'1'&x"5B5B",'1'&x"5B5C",'1'&x"5B5D",'1'&x"5B5E",'1'&x"5B5F",
+--'1'&x"5B60",'1'&x"5B61",'1'&x"5B62",'1'&x"5B63",'1'&x"5B64",'1'&x"5B65",'1'&x"5B66",'1'&x"5B67",'1'&x"5B68",'1'&x"5B69",'1'&x"5B6A",'1'&x"5B6B",'1'&x"5B6C",'1'&x"5B6D",'1'&x"5B6E",'1'&x"5B6F",
+--'1'&x"5B70",'1'&x"5B71",'1'&x"5B72",'1'&x"5B73",'1'&x"5B74",'1'&x"5B75",'1'&x"5B76",'1'&x"5B77",'1'&x"5B78",'1'&x"5B79",'1'&x"5B7A",'1'&x"5B7B",'1'&x"5B7C",'1'&x"5B7D",'1'&x"5B7E",'1'&x"5B7F",
+--'1'&x"5B80",'1'&x"5B81",'1'&x"5B82",'1'&x"5B83",'1'&x"5B84",'1'&x"5B85",'1'&x"5B86",'1'&x"5B87",'1'&x"5B88",'1'&x"5B89",'1'&x"5B8A",'1'&x"5B8B",'1'&x"5B8C",'1'&x"5B8D",'1'&x"5B8E",'1'&x"5B8F",
+--'1'&x"5B90",'1'&x"5B91",'1'&x"5B92",'1'&x"5B93",'1'&x"5B94",'1'&x"5B95",'1'&x"5B96",'1'&x"5B97",'1'&x"5B98",'1'&x"5B99",'1'&x"5B9A",'1'&x"5B9B",'1'&x"5B9C",'1'&x"5B9D",'1'&x"5B9E",'1'&x"5B9F",
+--'1'&x"5BA0",'1'&x"5BA1",'1'&x"5BA2",'1'&x"5BA3",'1'&x"5BA4",'1'&x"5BA5",'1'&x"5BA6",'1'&x"5BA7",'1'&x"5BA8",'1'&x"5BA9",'1'&x"5BAA",'1'&x"5BAB",'1'&x"5BAC",'1'&x"5BAD",'1'&x"5BAE",'1'&x"5BAF",
+--'1'&x"5BB0",'1'&x"5BB1",'1'&x"5BB2",'1'&x"5BB3",'1'&x"5BB4",'1'&x"5BB5",'1'&x"5BB6",'1'&x"5BB7",'1'&x"5BB8",'1'&x"5BB9",'1'&x"5BBA",'1'&x"5BBB",'1'&x"5BBC",'1'&x"5BBD",'1'&x"5BBE",'1'&x"5BBF",
+--'1'&x"5BC0",'1'&x"5BC1",'1'&x"5BC2",'1'&x"5BC3",'1'&x"5BC4",'1'&x"5BC5",'1'&x"5BC6",'1'&x"5BC7",'1'&x"5BC8",'1'&x"5BC9",'1'&x"5BCA",'1'&x"5BCB",'1'&x"5BCC",'1'&x"5BCD",'1'&x"5BCE",'1'&x"5BCF",
+--'1'&x"5BD0",'1'&x"5BD1",'1'&x"5BD2",'1'&x"5BD3",'1'&x"5BD4",'1'&x"5BD5",'1'&x"5BD6",'1'&x"5BD7",'1'&x"5BD8",'1'&x"5BD9",'1'&x"5BDA",'1'&x"5BDB",'1'&x"5BDC",'1'&x"5BDD",'1'&x"5BDE",'1'&x"5BDF",
+--'1'&x"5BE0",'1'&x"5BE1",'1'&x"5BE2",'1'&x"5BE3",'1'&x"5BE4",'1'&x"5BE5",'1'&x"5BE6",'1'&x"5BE7",'1'&x"5BE8",'1'&x"5BE9",'1'&x"5BEA",'1'&x"5BEB",'1'&x"5BEC",'1'&x"5BED",'1'&x"5BEE",'1'&x"5BEF",
+--'1'&x"5BF0",'1'&x"5BF1",'1'&x"5BF2",'1'&x"5BF3",'1'&x"5BF4",'1'&x"5BF5",'1'&x"5BF6",'1'&x"5BF7",'1'&x"5BF8",'1'&x"5BF9",'1'&x"5BFA",'1'&x"5BFB",'1'&x"5BFC",'1'&x"5BFD",'1'&x"5BFE",'1'&x"5BFF",
+--'1'&x"5C00",'1'&x"5C01",'1'&x"5C02",'1'&x"5C03",'1'&x"5C04",'1'&x"5C05",'1'&x"5C06",'1'&x"5C07",'1'&x"5C08",'1'&x"5C09",'1'&x"5C0A",'1'&x"5C0B",'1'&x"5C0C",'1'&x"5C0D",'1'&x"5C0E",'1'&x"5C0F",
+--'1'&x"5C10",'1'&x"5C11",'1'&x"5C12",'1'&x"5C13",'1'&x"5C14",'1'&x"5C15",'1'&x"5C16",'1'&x"5C17",'1'&x"5C18",'1'&x"5C19",'1'&x"5C1A",'1'&x"5C1B",'1'&x"5C1C",'1'&x"5C1D",'1'&x"5C1E",'1'&x"5C1F",
+--'1'&x"5C20",'1'&x"5C21",'1'&x"5C22",'1'&x"5C23",'1'&x"5C24",'1'&x"5C25",'1'&x"5C26",'1'&x"5C27",'1'&x"5C28",'1'&x"5C29",'1'&x"5C2A",'1'&x"5C2B",'1'&x"5C2C",'1'&x"5C2D",'1'&x"5C2E",'1'&x"5C2F",
+--'1'&x"5C30",'1'&x"5C31",'1'&x"5C32",'1'&x"5C33",'1'&x"5C34",'1'&x"5C35",'1'&x"5C36",'1'&x"5C37",'1'&x"5C38",'1'&x"5C39",'1'&x"5C3A",'1'&x"5C3B",'1'&x"5C3C",'1'&x"5C3D",'1'&x"5C3E",'1'&x"5C3F",
+--'1'&x"5C40",'1'&x"5C41",'1'&x"5C42",'1'&x"5C43",'1'&x"5C44",'1'&x"5C45",'1'&x"5C46",'1'&x"5C47",'1'&x"5C48",'1'&x"5C49",'1'&x"5C4A",'1'&x"5C4B",'1'&x"5C4C",'1'&x"5C4D",'1'&x"5C4E",'1'&x"5C4F",
+--'1'&x"5C50",'1'&x"5C51",'1'&x"5C52",'1'&x"5C53",'1'&x"5C54",'1'&x"5C55",'1'&x"5C56",'1'&x"5C57",'1'&x"5C58",'1'&x"5C59",'1'&x"5C5A",'1'&x"5C5B",'1'&x"5C5C",'1'&x"5C5D",'1'&x"5C5E",'1'&x"5C5F",
+--'1'&x"5C60",'1'&x"5C61",'1'&x"5C62",'1'&x"5C63",'1'&x"5C64",'1'&x"5C65",'1'&x"5C66",'1'&x"5C67",'1'&x"5C68",'1'&x"5C69",'1'&x"5C6A",'1'&x"5C6B",'1'&x"5C6C",'1'&x"5C6D",'1'&x"5C6E",'1'&x"5C6F",
+--'1'&x"5C70",'1'&x"5C71",'1'&x"5C72",'1'&x"5C73",'1'&x"5C74",'1'&x"5C75",'1'&x"5C76",'1'&x"5C77",'1'&x"5C78",'1'&x"5C79",'1'&x"5C7A",'1'&x"5C7B",'1'&x"5C7C",'1'&x"5C7D",'1'&x"5C7E",'1'&x"5C7F",
+--'1'&x"5C80",'1'&x"5C81",'1'&x"5C82",'1'&x"5C83",'1'&x"5C84",'1'&x"5C85",'1'&x"5C86",'1'&x"5C87",'1'&x"5C88",'1'&x"5C89",'1'&x"5C8A",'1'&x"5C8B",'1'&x"5C8C",'1'&x"5C8D",'1'&x"5C8E",'1'&x"5C8F",
+--'1'&x"5C90",'1'&x"5C91",'1'&x"5C92",'1'&x"5C93",'1'&x"5C94",'1'&x"5C95",'1'&x"5C96",'1'&x"5C97",'1'&x"5C98",'1'&x"5C99",'1'&x"5C9A",'1'&x"5C9B",'1'&x"5C9C",'1'&x"5C9D",'1'&x"5C9E",'1'&x"5C9F",
+--'1'&x"5CA0",'1'&x"5CA1",'1'&x"5CA2",'1'&x"5CA3",'1'&x"5CA4",'1'&x"5CA5",'1'&x"5CA6",'1'&x"5CA7",'1'&x"5CA8",'1'&x"5CA9",'1'&x"5CAA",'1'&x"5CAB",'1'&x"5CAC",'1'&x"5CAD",'1'&x"5CAE",'1'&x"5CAF",
+--'1'&x"5CB0",'1'&x"5CB1",'1'&x"5CB2",'1'&x"5CB3",'1'&x"5CB4",'1'&x"5CB5",'1'&x"5CB6",'1'&x"5CB7",'1'&x"5CB8",'1'&x"5CB9",'1'&x"5CBA",'1'&x"5CBB",'1'&x"5CBC",'1'&x"5CBD",'1'&x"5CBE",'1'&x"5CBF",
+--'1'&x"5CC0",'1'&x"5CC1",'1'&x"5CC2",'1'&x"5CC3",'1'&x"5CC4",'1'&x"5CC5",'1'&x"5CC6",'1'&x"5CC7",'1'&x"5CC8",'1'&x"5CC9",'1'&x"5CCA",'1'&x"5CCB",'1'&x"5CCC",'1'&x"5CCD",'1'&x"5CCE",'1'&x"5CCF",
+--'1'&x"5CD0",'1'&x"5CD1",'1'&x"5CD2",'1'&x"5CD3",'1'&x"5CD4",'1'&x"5CD5",'1'&x"5CD6",'1'&x"5CD7",'1'&x"5CD8",'1'&x"5CD9",'1'&x"5CDA",'1'&x"5CDB",'1'&x"5CDC",'1'&x"5CDD",'1'&x"5CDE",'1'&x"5CDF",
+--'1'&x"5CE0",'1'&x"5CE1",'1'&x"5CE2",'1'&x"5CE3",'1'&x"5CE4",'1'&x"5CE5",'1'&x"5CE6",'1'&x"5CE7",'1'&x"5CE8",'1'&x"5CE9",'1'&x"5CEA",'1'&x"5CEB",'1'&x"5CEC",'1'&x"5CED",'1'&x"5CEE",'1'&x"5CEF",
+--'1'&x"5CF0",'1'&x"5CF1",'1'&x"5CF2",'1'&x"5CF3",'1'&x"5CF4",'1'&x"5CF5",'1'&x"5CF6",'1'&x"5CF7",'1'&x"5CF8",'1'&x"5CF9",'1'&x"5CFA",'1'&x"5CFB",'1'&x"5CFC",'1'&x"5CFD",'1'&x"5CFE",'1'&x"5CFF",
+--'1'&x"5D00",'1'&x"5D01",'1'&x"5D02",'1'&x"5D03",'1'&x"5D04",'1'&x"5D05",'1'&x"5D06",'1'&x"5D07",'1'&x"5D08",'1'&x"5D09",'1'&x"5D0A",'1'&x"5D0B",'1'&x"5D0C",'1'&x"5D0D",'1'&x"5D0E",'1'&x"5D0F",
+--'1'&x"5D10",'1'&x"5D11",'1'&x"5D12",'1'&x"5D13",'1'&x"5D14",'1'&x"5D15",'1'&x"5D16",'1'&x"5D17",'1'&x"5D18",'1'&x"5D19",'1'&x"5D1A",'1'&x"5D1B",'1'&x"5D1C",'1'&x"5D1D",'1'&x"5D1E",'1'&x"5D1F",
+--'1'&x"5D20",'1'&x"5D21",'1'&x"5D22",'1'&x"5D23",'1'&x"5D24",'1'&x"5D25",'1'&x"5D26",'1'&x"5D27",'1'&x"5D28",'1'&x"5D29",'1'&x"5D2A",'1'&x"5D2B",'1'&x"5D2C",'1'&x"5D2D",'1'&x"5D2E",'1'&x"5D2F",
+--'1'&x"5D30",'1'&x"5D31",'1'&x"5D32",'1'&x"5D33",'1'&x"5D34",'1'&x"5D35",'1'&x"5D36",'1'&x"5D37",'1'&x"5D38",'1'&x"5D39",'1'&x"5D3A",'1'&x"5D3B",'1'&x"5D3C",'1'&x"5D3D",'1'&x"5D3E",'1'&x"5D3F",
+--'1'&x"5D40",'1'&x"5D41",'1'&x"5D42",'1'&x"5D43",'1'&x"5D44",'1'&x"5D45",'1'&x"5D46",'1'&x"5D47",'1'&x"5D48",'1'&x"5D49",'1'&x"5D4A",'1'&x"5D4B",'1'&x"5D4C",'1'&x"5D4D",'1'&x"5D4E",'1'&x"5D4F",
+--'1'&x"5D50",'1'&x"5D51",'1'&x"5D52",'1'&x"5D53",'1'&x"5D54",'1'&x"5D55",'1'&x"5D56",'1'&x"5D57",'1'&x"5D58",'1'&x"5D59",'1'&x"5D5A",'1'&x"5D5B",'1'&x"5D5C",'1'&x"5D5D",'1'&x"5D5E",'1'&x"5D5F",
+--'1'&x"5D60",'1'&x"5D61",'1'&x"5D62",'1'&x"5D63",'1'&x"5D64",'1'&x"5D65",'1'&x"5D66",'1'&x"5D67",'1'&x"5D68",'1'&x"5D69",'1'&x"5D6A",'1'&x"5D6B",'1'&x"5D6C",'1'&x"5D6D",'1'&x"5D6E",'1'&x"5D6F",
+--'1'&x"5D70",'1'&x"5D71",'1'&x"5D72",'1'&x"5D73",'1'&x"5D74",'1'&x"5D75",'1'&x"5D76",'1'&x"5D77",'1'&x"5D78",'1'&x"5D79",'1'&x"5D7A",'1'&x"5D7B",'1'&x"5D7C",'1'&x"5D7D",'1'&x"5D7E",'1'&x"5D7F",
+--'1'&x"5D80",'1'&x"5D81",'1'&x"5D82",'1'&x"5D83",'1'&x"5D84",'1'&x"5D85",'1'&x"5D86",'1'&x"5D87",'1'&x"5D88",'1'&x"5D89",'1'&x"5D8A",'1'&x"5D8B",'1'&x"5D8C",'1'&x"5D8D",'1'&x"5D8E",'1'&x"5D8F",
+--'1'&x"5D90",'1'&x"5D91",'1'&x"5D92",'1'&x"5D93",'1'&x"5D94",'1'&x"5D95",'1'&x"5D96",'1'&x"5D97",'1'&x"5D98",'1'&x"5D99",'1'&x"5D9A",'1'&x"5D9B",'1'&x"5D9C",'1'&x"5D9D",'1'&x"5D9E",'1'&x"5D9F",
+--'1'&x"5DA0",'1'&x"5DA1",'1'&x"5DA2",'1'&x"5DA3",'1'&x"5DA4",'1'&x"5DA5",'1'&x"5DA6",'1'&x"5DA7",'1'&x"5DA8",'1'&x"5DA9",'1'&x"5DAA",'1'&x"5DAB",'1'&x"5DAC",'1'&x"5DAD",'1'&x"5DAE",'1'&x"5DAF",
+--'1'&x"5DB0",'1'&x"5DB1",'1'&x"5DB2",'1'&x"5DB3",'1'&x"5DB4",'1'&x"5DB5",'1'&x"5DB6",'1'&x"5DB7",'1'&x"5DB8",'1'&x"5DB9",'1'&x"5DBA",'1'&x"5DBB",'1'&x"5DBC",'1'&x"5DBD",'1'&x"5DBE",'1'&x"5DBF",
+--'1'&x"5DC0",'1'&x"5DC1",'1'&x"5DC2",'1'&x"5DC3",'1'&x"5DC4",'1'&x"5DC5",'1'&x"5DC6",'1'&x"5DC7",'1'&x"5DC8",'1'&x"5DC9",'1'&x"5DCA",'1'&x"5DCB",'1'&x"5DCC",'1'&x"5DCD",'1'&x"5DCE",'1'&x"5DCF",
+--'1'&x"5DD0",'1'&x"5DD1",'1'&x"5DD2",'1'&x"5DD3",'1'&x"5DD4",'1'&x"5DD5",'1'&x"5DD6",'1'&x"5DD7",'1'&x"5DD8",'1'&x"5DD9",'1'&x"5DDA",'1'&x"5DDB",'1'&x"5DDC",'1'&x"5DDD",'1'&x"5DDE",'1'&x"5DDF",
+--'1'&x"5DE0",'1'&x"5DE1",'1'&x"5DE2",'1'&x"5DE3",'1'&x"5DE4",'1'&x"5DE5",'1'&x"5DE6",'1'&x"5DE7",'1'&x"5DE8",'1'&x"5DE9",'1'&x"5DEA",'1'&x"5DEB",'1'&x"5DEC",'1'&x"5DED",'1'&x"5DEE",'1'&x"5DEF",
+--'1'&x"5DF0",'1'&x"5DF1",'1'&x"5DF2",'1'&x"5DF3",'1'&x"5DF4",'1'&x"5DF5",'1'&x"5DF6",'1'&x"5DF7",'1'&x"5DF8",'1'&x"5DF9",'1'&x"5DFA",'1'&x"5DFB",'1'&x"5DFC",'1'&x"5DFD",'1'&x"5DFE",'1'&x"5DFF",
+--'1'&x"5E00",'1'&x"5E01",'1'&x"5E02",'1'&x"5E03",'1'&x"5E04",'1'&x"5E05",'1'&x"5E06",'1'&x"5E07",'1'&x"5E08",'1'&x"5E09",'1'&x"5E0A",'1'&x"5E0B",'1'&x"5E0C",'1'&x"5E0D",'1'&x"5E0E",'1'&x"5E0F",
+--'1'&x"5E10",'1'&x"5E11",'1'&x"5E12",'1'&x"5E13",'1'&x"5E14",'1'&x"5E15",'1'&x"5E16",'1'&x"5E17",'1'&x"5E18",'1'&x"5E19",'1'&x"5E1A",'1'&x"5E1B",'1'&x"5E1C",'1'&x"5E1D",'1'&x"5E1E",'1'&x"5E1F",
+--'1'&x"5E20",'1'&x"5E21",'1'&x"5E22",'1'&x"5E23",'1'&x"5E24",'1'&x"5E25",'1'&x"5E26",'1'&x"5E27",'1'&x"5E28",'1'&x"5E29",'1'&x"5E2A",'1'&x"5E2B",'1'&x"5E2C",'1'&x"5E2D",'1'&x"5E2E",'1'&x"5E2F",
+--'1'&x"5E30",'1'&x"5E31",'1'&x"5E32",'1'&x"5E33",'1'&x"5E34",'1'&x"5E35",'1'&x"5E36",'1'&x"5E37",'1'&x"5E38",'1'&x"5E39",'1'&x"5E3A",'1'&x"5E3B",'1'&x"5E3C",'1'&x"5E3D",'1'&x"5E3E",'1'&x"5E3F",
+--'1'&x"5E40",'1'&x"5E41",'1'&x"5E42",'1'&x"5E43",'1'&x"5E44",'1'&x"5E45",'1'&x"5E46",'1'&x"5E47",'1'&x"5E48",'1'&x"5E49",'1'&x"5E4A",'1'&x"5E4B",'1'&x"5E4C",'1'&x"5E4D",'1'&x"5E4E",'1'&x"5E4F",
+--'1'&x"5E50",'1'&x"5E51",'1'&x"5E52",'1'&x"5E53",'1'&x"5E54",'1'&x"5E55",'1'&x"5E56",'1'&x"5E57",'1'&x"5E58",'1'&x"5E59",'1'&x"5E5A",'1'&x"5E5B",'1'&x"5E5C",'1'&x"5E5D",'1'&x"5E5E",'1'&x"5E5F",
+--'1'&x"5E60",'1'&x"5E61",'1'&x"5E62",'1'&x"5E63",'1'&x"5E64",'1'&x"5E65",'1'&x"5E66",'1'&x"5E67",'1'&x"5E68",'1'&x"5E69",'1'&x"5E6A",'1'&x"5E6B",'1'&x"5E6C",'1'&x"5E6D",'1'&x"5E6E",'1'&x"5E6F",
+--'1'&x"5E70",'1'&x"5E71",'1'&x"5E72",'1'&x"5E73",'1'&x"5E74",'1'&x"5E75",'1'&x"5E76",'1'&x"5E77",'1'&x"5E78",'1'&x"5E79",'1'&x"5E7A",'1'&x"5E7B",'1'&x"5E7C",'1'&x"5E7D",'1'&x"5E7E",'1'&x"5E7F",
+--'1'&x"5E80",'1'&x"5E81",'1'&x"5E82",'1'&x"5E83",'1'&x"5E84",'1'&x"5E85",'1'&x"5E86",'1'&x"5E87",'1'&x"5E88",'1'&x"5E89",'1'&x"5E8A",'1'&x"5E8B",'1'&x"5E8C",'1'&x"5E8D",'1'&x"5E8E",'1'&x"5E8F",
+--'1'&x"5E90",'1'&x"5E91",'1'&x"5E92",'1'&x"5E93",'1'&x"5E94",'1'&x"5E95",'1'&x"5E96",'1'&x"5E97",'1'&x"5E98",'1'&x"5E99",'1'&x"5E9A",'1'&x"5E9B",'1'&x"5E9C",'1'&x"5E9D",'1'&x"5E9E",'1'&x"5E9F",
+--'1'&x"5EA0",'1'&x"5EA1",'1'&x"5EA2",'1'&x"5EA3",'1'&x"5EA4",'1'&x"5EA5",'1'&x"5EA6",'1'&x"5EA7",'1'&x"5EA8",'1'&x"5EA9",'1'&x"5EAA",'1'&x"5EAB",'1'&x"5EAC",'1'&x"5EAD",'1'&x"5EAE",'1'&x"5EAF",
+--'1'&x"5EB0",'1'&x"5EB1",'1'&x"5EB2",'1'&x"5EB3",'1'&x"5EB4",'1'&x"5EB5",'1'&x"5EB6",'1'&x"5EB7",'1'&x"5EB8",'1'&x"5EB9",'1'&x"5EBA",'1'&x"5EBB",'1'&x"5EBC",'1'&x"5EBD",'1'&x"5EBE",'1'&x"5EBF",
+--'1'&x"5EC0",'1'&x"5EC1",'1'&x"5EC2",'1'&x"5EC3",'1'&x"5EC4",'1'&x"5EC5",'1'&x"5EC6",'1'&x"5EC7",'1'&x"5EC8",'1'&x"5EC9",'1'&x"5ECA",'1'&x"5ECB",'1'&x"5ECC",'1'&x"5ECD",'1'&x"5ECE",'1'&x"5ECF",
+--'1'&x"5ED0",'1'&x"5ED1",'1'&x"5ED2",'1'&x"5ED3",'1'&x"5ED4",'1'&x"5ED5",'1'&x"5ED6",'1'&x"5ED7",'1'&x"5ED8",'1'&x"5ED9",'1'&x"5EDA",'1'&x"5EDB",'1'&x"5EDC",'1'&x"5EDD",'1'&x"5EDE",'1'&x"5EDF",
+--'1'&x"5EE0",'1'&x"5EE1",'1'&x"5EE2",'1'&x"5EE3",'1'&x"5EE4",'1'&x"5EE5",'1'&x"5EE6",'1'&x"5EE7",'1'&x"5EE8",'1'&x"5EE9",'1'&x"5EEA",'1'&x"5EEB",'1'&x"5EEC",'1'&x"5EED",'1'&x"5EEE",'1'&x"5EEF",
+--'1'&x"5EF0",'1'&x"5EF1",'1'&x"5EF2",'1'&x"5EF3",'1'&x"5EF4",'1'&x"5EF5",'1'&x"5EF6",'1'&x"5EF7",'1'&x"5EF8",'1'&x"5EF9",'1'&x"5EFA",'1'&x"5EFB",'1'&x"5EFC",'1'&x"5EFD",'1'&x"5EFE",'1'&x"5EFF",
+--'1'&x"5F00",'1'&x"5F01",'1'&x"5F02",'1'&x"5F03",'1'&x"5F04",'1'&x"5F05",'1'&x"5F06",'1'&x"5F07",'1'&x"5F08",'1'&x"5F09",'1'&x"5F0A",'1'&x"5F0B",'1'&x"5F0C",'1'&x"5F0D",'1'&x"5F0E",'1'&x"5F0F",
+--'1'&x"5F10",'1'&x"5F11",'1'&x"5F12",'1'&x"5F13",'1'&x"5F14",'1'&x"5F15",'1'&x"5F16",'1'&x"5F17",'1'&x"5F18",'1'&x"5F19",'1'&x"5F1A",'1'&x"5F1B",'1'&x"5F1C",'1'&x"5F1D",'1'&x"5F1E",'1'&x"5F1F",
+--'1'&x"5F20",'1'&x"5F21",'1'&x"5F22",'1'&x"5F23",'1'&x"5F24",'1'&x"5F25",'1'&x"5F26",'1'&x"5F27",'1'&x"5F28",'1'&x"5F29",'1'&x"5F2A",'1'&x"5F2B",'1'&x"5F2C",'1'&x"5F2D",'1'&x"5F2E",'1'&x"5F2F",
+--'1'&x"5F30",'1'&x"5F31",'1'&x"5F32",'1'&x"5F33",'1'&x"5F34",'1'&x"5F35",'1'&x"5F36",'1'&x"5F37",'1'&x"5F38",'1'&x"5F39",'1'&x"5F3A",'1'&x"5F3B",'1'&x"5F3C",'1'&x"5F3D",'1'&x"5F3E",'1'&x"5F3F",
+--'1'&x"5F40",'1'&x"5F41",'1'&x"5F42",'1'&x"5F43",'1'&x"5F44",'1'&x"5F45",'1'&x"5F46",'1'&x"5F47",'1'&x"5F48",'1'&x"5F49",'1'&x"5F4A",'1'&x"5F4B",'1'&x"5F4C",'1'&x"5F4D",'1'&x"5F4E",'1'&x"5F4F",
+--'1'&x"5F50",'1'&x"5F51",'1'&x"5F52",'1'&x"5F53",'1'&x"5F54",'1'&x"5F55",'1'&x"5F56",'1'&x"5F57",'1'&x"5F58",'1'&x"5F59",'1'&x"5F5A",'1'&x"5F5B",'1'&x"5F5C",'1'&x"5F5D",'1'&x"5F5E",'1'&x"5F5F",
+--'1'&x"5F60",'1'&x"5F61",'1'&x"5F62",'1'&x"5F63",'1'&x"5F64",'1'&x"5F65",'1'&x"5F66",'1'&x"5F67",'1'&x"5F68",'1'&x"5F69",'1'&x"5F6A",'1'&x"5F6B",'1'&x"5F6C",'1'&x"5F6D",'1'&x"5F6E",'1'&x"5F6F",
+--'1'&x"5F70",'1'&x"5F71",'1'&x"5F72",'1'&x"5F73",'1'&x"5F74",'1'&x"5F75",'1'&x"5F76",'1'&x"5F77",'1'&x"5F78",'1'&x"5F79",'1'&x"5F7A",'1'&x"5F7B",'1'&x"5F7C",'1'&x"5F7D",'1'&x"5F7E",'1'&x"5F7F",
+--'1'&x"5F80",'1'&x"5F81",'1'&x"5F82",'1'&x"5F83",'1'&x"5F84",'1'&x"5F85",'1'&x"5F86",'1'&x"5F87",'1'&x"5F88",'1'&x"5F89",'1'&x"5F8A",'1'&x"5F8B",'1'&x"5F8C",'1'&x"5F8D",'1'&x"5F8E",'1'&x"5F8F",
+--'1'&x"5F90",'1'&x"5F91",'1'&x"5F92",'1'&x"5F93",'1'&x"5F94",'1'&x"5F95",'1'&x"5F96",'1'&x"5F97",'1'&x"5F98",'1'&x"5F99",'1'&x"5F9A",'1'&x"5F9B",'1'&x"5F9C",'1'&x"5F9D",'1'&x"5F9E",'1'&x"5F9F",
+--'1'&x"5FA0",'1'&x"5FA1",'1'&x"5FA2",'1'&x"5FA3",'1'&x"5FA4",'1'&x"5FA5",'1'&x"5FA6",'1'&x"5FA7",'1'&x"5FA8",'1'&x"5FA9",'1'&x"5FAA",'1'&x"5FAB",'1'&x"5FAC",'1'&x"5FAD",'1'&x"5FAE",'1'&x"5FAF",
+--'1'&x"5FB0",'1'&x"5FB1",'1'&x"5FB2",'1'&x"5FB3",'1'&x"5FB4",'1'&x"5FB5",'1'&x"5FB6",'1'&x"5FB7",'1'&x"5FB8",'1'&x"5FB9",'1'&x"5FBA",'1'&x"5FBB",'1'&x"5FBC",'1'&x"5FBD",'1'&x"5FBE",'1'&x"5FBF",
+--'1'&x"5FC0",'1'&x"5FC1",'1'&x"5FC2",'1'&x"5FC3",'1'&x"5FC4",'1'&x"5FC5",'1'&x"5FC6",'1'&x"5FC7",'1'&x"5FC8",'1'&x"5FC9",'1'&x"5FCA",'1'&x"5FCB",'1'&x"5FCC",'1'&x"5FCD",'1'&x"5FCE",'1'&x"5FCF",
+--'1'&x"5FD0",'1'&x"5FD1",'1'&x"5FD2",'1'&x"5FD3",'1'&x"5FD4",'1'&x"5FD5",'1'&x"5FD6",'1'&x"5FD7",'1'&x"5FD8",'1'&x"5FD9",'1'&x"5FDA",'1'&x"5FDB",'1'&x"5FDC",'1'&x"5FDD",'1'&x"5FDE",'1'&x"5FDF",
+--'1'&x"5FE0",'1'&x"5FE1",'1'&x"5FE2",'1'&x"5FE3",'1'&x"5FE4",'1'&x"5FE5",'1'&x"5FE6",'1'&x"5FE7",'1'&x"5FE8",'1'&x"5FE9",'1'&x"5FEA",'1'&x"5FEB",'1'&x"5FEC",'1'&x"5FED",'1'&x"5FEE",'1'&x"5FEF",
+--'1'&x"5FF0",'1'&x"5FF1",'1'&x"5FF2",'1'&x"5FF3",'1'&x"5FF4",'1'&x"5FF5",'1'&x"5FF6",'1'&x"5FF7",'1'&x"5FF8",'1'&x"5FF9",'1'&x"5FFA",'1'&x"5FFB",'1'&x"5FFC",'1'&x"5FFD",'1'&x"5FFE",'1'&x"5FFF",
+--'1'&x"6000",'1'&x"6001",'1'&x"6002",'1'&x"6003",'1'&x"6004",'1'&x"6005",'1'&x"6006",'1'&x"6007",'1'&x"6008",'1'&x"6009",'1'&x"600A",'1'&x"600B",'1'&x"600C",'1'&x"600D",'1'&x"600E",'1'&x"600F",
+--'1'&x"6010",'1'&x"6011",'1'&x"6012",'1'&x"6013",'1'&x"6014",'1'&x"6015",'1'&x"6016",'1'&x"6017",'1'&x"6018",'1'&x"6019",'1'&x"601A",'1'&x"601B",'1'&x"601C",'1'&x"601D",'1'&x"601E",'1'&x"601F",
+--'1'&x"6020",'1'&x"6021",'1'&x"6022",'1'&x"6023",'1'&x"6024",'1'&x"6025",'1'&x"6026",'1'&x"6027",'1'&x"6028",'1'&x"6029",'1'&x"602A",'1'&x"602B",'1'&x"602C",'1'&x"602D",'1'&x"602E",'1'&x"602F",
+--'1'&x"6030",'1'&x"6031",'1'&x"6032",'1'&x"6033",'1'&x"6034",'1'&x"6035",'1'&x"6036",'1'&x"6037",'1'&x"6038",'1'&x"6039",'1'&x"603A",'1'&x"603B",'1'&x"603C",'1'&x"603D",'1'&x"603E",'1'&x"603F",
+--'1'&x"6040",'1'&x"6041",'1'&x"6042",'1'&x"6043",'1'&x"6044",'1'&x"6045",'1'&x"6046",'1'&x"6047",'1'&x"6048",'1'&x"6049",'1'&x"604A",'1'&x"604B",'1'&x"604C",'1'&x"604D",'1'&x"604E",'1'&x"604F",
+--'1'&x"6050",'1'&x"6051",'1'&x"6052",'1'&x"6053",'1'&x"6054",'1'&x"6055",'1'&x"6056",'1'&x"6057",'1'&x"6058",'1'&x"6059",'1'&x"605A",'1'&x"605B",'1'&x"605C",'1'&x"605D",'1'&x"605E",'1'&x"605F",
+--'1'&x"6060",'1'&x"6061",'1'&x"6062",'1'&x"6063",'1'&x"6064",'1'&x"6065",'1'&x"6066",'1'&x"6067",'1'&x"6068",'1'&x"6069",'1'&x"606A",'1'&x"606B",'1'&x"606C",'1'&x"606D",'1'&x"606E",'1'&x"606F",
+--'1'&x"6070",'1'&x"6071",'1'&x"6072",'1'&x"6073",'1'&x"6074",'1'&x"6075",'1'&x"6076",'1'&x"6077",'1'&x"6078",'1'&x"6079",'1'&x"607A",'1'&x"607B",'1'&x"607C",'1'&x"607D",'1'&x"607E",'1'&x"607F",
+--'1'&x"6080",'1'&x"6081",'1'&x"6082",'1'&x"6083",'1'&x"6084",'1'&x"6085",'1'&x"6086",'1'&x"6087",'1'&x"6088",'1'&x"6089",'1'&x"608A",'1'&x"608B",'1'&x"608C",'1'&x"608D",'1'&x"608E",'1'&x"608F",
+--'1'&x"6090",'1'&x"6091",'1'&x"6092",'1'&x"6093",'1'&x"6094",'1'&x"6095",'1'&x"6096",'1'&x"6097",'1'&x"6098",'1'&x"6099",'1'&x"609A",'1'&x"609B",'1'&x"609C",'1'&x"609D",'1'&x"609E",'1'&x"609F",
+--'1'&x"60A0",'1'&x"60A1",'1'&x"60A2",'1'&x"60A3",'1'&x"60A4",'1'&x"60A5",'1'&x"60A6",'1'&x"60A7",'1'&x"60A8",'1'&x"60A9",'1'&x"60AA",'1'&x"60AB",'1'&x"60AC",'1'&x"60AD",'1'&x"60AE",'1'&x"60AF",
+--'1'&x"60B0",'1'&x"60B1",'1'&x"60B2",'1'&x"60B3",'1'&x"60B4",'1'&x"60B5",'1'&x"60B6",'1'&x"60B7",'1'&x"60B8",'1'&x"60B9",'1'&x"60BA",'1'&x"60BB",'1'&x"60BC",'1'&x"60BD",'1'&x"60BE",'1'&x"60BF",
+--'1'&x"60C0",'1'&x"60C1",'1'&x"60C2",'1'&x"60C3",'1'&x"60C4",'1'&x"60C5",'1'&x"60C6",'1'&x"60C7",'1'&x"60C8",'1'&x"60C9",'1'&x"60CA",'1'&x"60CB",'1'&x"60CC",'1'&x"60CD",'1'&x"60CE",'1'&x"60CF",
+--'1'&x"60D0",'1'&x"60D1",'1'&x"60D2",'1'&x"60D3",'1'&x"60D4",'1'&x"60D5",'1'&x"60D6",'1'&x"60D7",'1'&x"60D8",'1'&x"60D9",'1'&x"60DA",'1'&x"60DB",'1'&x"60DC",'1'&x"60DD",'1'&x"60DE",'1'&x"60DF",
+--'1'&x"60E0",'1'&x"60E1",'1'&x"60E2",'1'&x"60E3",'1'&x"60E4",'1'&x"60E5",'1'&x"60E6",'1'&x"60E7",'1'&x"60E8",'1'&x"60E9",'1'&x"60EA",'1'&x"60EB",'1'&x"60EC",'1'&x"60ED",'1'&x"60EE",'1'&x"60EF",
+--'1'&x"60F0",'1'&x"60F1",'1'&x"60F2",'1'&x"60F3",'1'&x"60F4",'1'&x"60F5",'1'&x"60F6",'1'&x"60F7",'1'&x"60F8",'1'&x"60F9",'1'&x"60FA",'1'&x"60FB",'1'&x"60FC",'1'&x"60FD",'1'&x"60FE",'1'&x"60FF",
+--'1'&x"6100",'1'&x"6101",'1'&x"6102",'1'&x"6103",'1'&x"6104",'1'&x"6105",'1'&x"6106",'1'&x"6107",'1'&x"6108",'1'&x"6109",'1'&x"610A",'1'&x"610B",'1'&x"610C",'1'&x"610D",'1'&x"610E",'1'&x"610F",
+--'1'&x"6110",'1'&x"6111",'1'&x"6112",'1'&x"6113",'1'&x"6114",'1'&x"6115",'1'&x"6116",'1'&x"6117",'1'&x"6118",'1'&x"6119",'1'&x"611A",'1'&x"611B",'1'&x"611C",'1'&x"611D",'1'&x"611E",'1'&x"611F",
+--'1'&x"6120",'1'&x"6121",'1'&x"6122",'1'&x"6123",'1'&x"6124",'1'&x"6125",'1'&x"6126",'1'&x"6127",'1'&x"6128",'1'&x"6129",'1'&x"612A",'1'&x"612B",'1'&x"612C",'1'&x"612D",'1'&x"612E",'1'&x"612F",
+--'1'&x"6130",'1'&x"6131",'1'&x"6132",'1'&x"6133",'1'&x"6134",'1'&x"6135",'1'&x"6136",'1'&x"6137",'1'&x"6138",'1'&x"6139",'1'&x"613A",'1'&x"613B",'1'&x"613C",'1'&x"613D",'1'&x"613E",'1'&x"613F",
+--'1'&x"6140",'1'&x"6141",'1'&x"6142",'1'&x"6143",'1'&x"6144",'1'&x"6145",'1'&x"6146",'1'&x"6147",'1'&x"6148",'1'&x"6149",'1'&x"614A",'1'&x"614B",'1'&x"614C",'1'&x"614D",'1'&x"614E",'1'&x"614F",
+--'1'&x"6150",'1'&x"6151",'1'&x"6152",'1'&x"6153",'1'&x"6154",'1'&x"6155",'1'&x"6156",'1'&x"6157",'1'&x"6158",'1'&x"6159",'1'&x"615A",'1'&x"615B",'1'&x"615C",'1'&x"615D",'1'&x"615E",'1'&x"615F",
+--'1'&x"6160",'1'&x"6161",'1'&x"6162",'1'&x"6163",'1'&x"6164",'1'&x"6165",'1'&x"6166",'1'&x"6167",'1'&x"6168",'1'&x"6169",'1'&x"616A",'1'&x"616B",'1'&x"616C",'1'&x"616D",'1'&x"616E",'1'&x"616F",
+--'1'&x"6170",'1'&x"6171",'1'&x"6172",'1'&x"6173",'1'&x"6174",'1'&x"6175",'1'&x"6176",'1'&x"6177",'1'&x"6178",'1'&x"6179",'1'&x"617A",'1'&x"617B",'1'&x"617C",'1'&x"617D",'1'&x"617E",'1'&x"617F",
+--'1'&x"6180",'1'&x"6181",'1'&x"6182",'1'&x"6183",'1'&x"6184",'1'&x"6185",'1'&x"6186",'1'&x"6187",'1'&x"6188",'1'&x"6189",'1'&x"618A",'1'&x"618B",'1'&x"618C",'1'&x"618D",'1'&x"618E",'1'&x"618F",
+--'1'&x"6190",'1'&x"6191",'1'&x"6192",'1'&x"6193",'1'&x"6194",'1'&x"6195",'1'&x"6196",'1'&x"6197",'1'&x"6198",'1'&x"6199",'1'&x"619A",'1'&x"619B",'1'&x"619C",'1'&x"619D",'1'&x"619E",'1'&x"619F",
+--'1'&x"61A0",'1'&x"61A1",'1'&x"61A2",'1'&x"61A3",'1'&x"61A4",'1'&x"61A5",'1'&x"61A6",'1'&x"61A7",'1'&x"61A8",'1'&x"61A9",'1'&x"61AA",'1'&x"61AB",'1'&x"61AC",'1'&x"61AD",'1'&x"61AE",'1'&x"61AF",
+--'1'&x"61B0",'1'&x"61B1",'1'&x"61B2",'1'&x"61B3",'1'&x"61B4",'1'&x"61B5",'1'&x"61B6",'1'&x"61B7",'1'&x"61B8",'1'&x"61B9",'1'&x"61BA",'1'&x"61BB",'1'&x"61BC",'1'&x"61BD",'1'&x"61BE",'1'&x"61BF",
+--'1'&x"61C0",'1'&x"61C1",'1'&x"61C2",'1'&x"61C3",'1'&x"61C4",'1'&x"61C5",'1'&x"61C6",'1'&x"61C7",'1'&x"61C8",'1'&x"61C9",'1'&x"61CA",'1'&x"61CB",'1'&x"61CC",'1'&x"61CD",'1'&x"61CE",'1'&x"61CF",
+--'1'&x"61D0",'1'&x"61D1",'1'&x"61D2",'1'&x"61D3",'1'&x"61D4",'1'&x"61D5",'1'&x"61D6",'1'&x"61D7",'1'&x"61D8",'1'&x"61D9",'1'&x"61DA",'1'&x"61DB",'1'&x"61DC",'1'&x"61DD",'1'&x"61DE",'1'&x"61DF",
+--'1'&x"61E0",'1'&x"61E1",'1'&x"61E2",'1'&x"61E3",'1'&x"61E4",'1'&x"61E5",'1'&x"61E6",'1'&x"61E7",'1'&x"61E8",'1'&x"61E9",'1'&x"61EA",'1'&x"61EB",'1'&x"61EC",'1'&x"61ED",'1'&x"61EE",'1'&x"61EF",
+--'1'&x"61F0",'1'&x"61F1",'1'&x"61F2",'1'&x"61F3",'1'&x"61F4",'1'&x"61F5",'1'&x"61F6",'1'&x"61F7",'1'&x"61F8",'1'&x"61F9",'1'&x"61FA",'1'&x"61FB",'1'&x"61FC",'1'&x"61FD",'1'&x"61FE",'1'&x"61FF",
+--'1'&x"6200",'1'&x"6201",'1'&x"6202",'1'&x"6203",'1'&x"6204",'1'&x"6205",'1'&x"6206",'1'&x"6207",'1'&x"6208",'1'&x"6209",'1'&x"620A",'1'&x"620B",'1'&x"620C",'1'&x"620D",'1'&x"620E",'1'&x"620F",
+--'1'&x"6210",'1'&x"6211",'1'&x"6212",'1'&x"6213",'1'&x"6214",'1'&x"6215",'1'&x"6216",'1'&x"6217",'1'&x"6218",'1'&x"6219",'1'&x"621A",'1'&x"621B",'1'&x"621C",'1'&x"621D",'1'&x"621E",'1'&x"621F",
+--'1'&x"6220",'1'&x"6221",'1'&x"6222",'1'&x"6223",'1'&x"6224",'1'&x"6225",'1'&x"6226",'1'&x"6227",'1'&x"6228",'1'&x"6229",'1'&x"622A",'1'&x"622B",'1'&x"622C",'1'&x"622D",'1'&x"622E",'1'&x"622F",
+--'1'&x"6230",'1'&x"6231",'1'&x"6232",'1'&x"6233",'1'&x"6234",'1'&x"6235",'1'&x"6236",'1'&x"6237",'1'&x"6238",'1'&x"6239",'1'&x"623A",'1'&x"623B",'1'&x"623C",'1'&x"623D",'1'&x"623E",'1'&x"623F",
+--'1'&x"6240",'1'&x"6241",'1'&x"6242",'1'&x"6243",'1'&x"6244",'1'&x"6245",'1'&x"6246",'1'&x"6247",'1'&x"6248",'1'&x"6249",'1'&x"624A",'1'&x"624B",'1'&x"624C",'1'&x"624D",'1'&x"624E",'1'&x"624F",
+--'1'&x"6250",'1'&x"6251",'1'&x"6252",'1'&x"6253",'1'&x"6254",'1'&x"6255",'1'&x"6256",'1'&x"6257",'1'&x"6258",'1'&x"6259",'1'&x"625A",'1'&x"625B",'1'&x"625C",'1'&x"625D",'1'&x"625E",'1'&x"625F",
+--'1'&x"6260",'1'&x"6261",'1'&x"6262",'1'&x"6263",'1'&x"6264",'1'&x"6265",'1'&x"6266",'1'&x"6267",'1'&x"6268",'1'&x"6269",'1'&x"626A",'1'&x"626B",'1'&x"626C",'1'&x"626D",'1'&x"626E",'1'&x"626F",
+--'1'&x"6270",'1'&x"6271",'1'&x"6272",'1'&x"6273",'1'&x"6274",'1'&x"6275",'1'&x"6276",'1'&x"6277",'1'&x"6278",'1'&x"6279",'1'&x"627A",'1'&x"627B",'1'&x"627C",'1'&x"627D",'1'&x"627E",'1'&x"627F",
+--'1'&x"6280",'1'&x"6281",'1'&x"6282",'1'&x"6283",'1'&x"6284",'1'&x"6285",'1'&x"6286",'1'&x"6287",'1'&x"6288",'1'&x"6289",'1'&x"628A",'1'&x"628B",'1'&x"628C",'1'&x"628D",'1'&x"628E",'1'&x"628F",
+--'1'&x"6290",'1'&x"6291",'1'&x"6292",'1'&x"6293",'1'&x"6294",'1'&x"6295",'1'&x"6296",'1'&x"6297",'1'&x"6298",'1'&x"6299",'1'&x"629A",'1'&x"629B",'1'&x"629C",'1'&x"629D",'1'&x"629E",'1'&x"629F",
+--'1'&x"62A0",'1'&x"62A1",'1'&x"62A2",'1'&x"62A3",'1'&x"62A4",'1'&x"62A5",'1'&x"62A6",'1'&x"62A7",'1'&x"62A8",'1'&x"62A9",'1'&x"62AA",'1'&x"62AB",'1'&x"62AC",'1'&x"62AD",'1'&x"62AE",'1'&x"62AF",
+--'1'&x"62B0",'1'&x"62B1",'1'&x"62B2",'1'&x"62B3",'1'&x"62B4",'1'&x"62B5",'1'&x"62B6",'1'&x"62B7",'1'&x"62B8",'1'&x"62B9",'1'&x"62BA",'1'&x"62BB",'1'&x"62BC",'1'&x"62BD",'1'&x"62BE",'1'&x"62BF",
+--'1'&x"62C0",'1'&x"62C1",'1'&x"62C2",'1'&x"62C3",'1'&x"62C4",'1'&x"62C5",'1'&x"62C6",'1'&x"62C7",'1'&x"62C8",'1'&x"62C9",'1'&x"62CA",'1'&x"62CB",'1'&x"62CC",'1'&x"62CD",'1'&x"62CE",'1'&x"62CF",
+--'1'&x"62D0",'1'&x"62D1",'1'&x"62D2",'1'&x"62D3",'1'&x"62D4",'1'&x"62D5",'1'&x"62D6",'1'&x"62D7",'1'&x"62D8",'1'&x"62D9",'1'&x"62DA",'1'&x"62DB",'1'&x"62DC",'1'&x"62DD",'1'&x"62DE",'1'&x"62DF",
+--'1'&x"62E0",'1'&x"62E1",'1'&x"62E2",'1'&x"62E3",'1'&x"62E4",'1'&x"62E5",'1'&x"62E6",'1'&x"62E7",'1'&x"62E8",'1'&x"62E9",'1'&x"62EA",'1'&x"62EB",'1'&x"62EC",'1'&x"62ED",'1'&x"62EE",'1'&x"62EF",
+--'1'&x"62F0",'1'&x"62F1",'1'&x"62F2",'1'&x"62F3",'1'&x"62F4",'1'&x"62F5",'1'&x"62F6",'1'&x"62F7",'1'&x"62F8",'1'&x"62F9",'1'&x"62FA",'1'&x"62FB",'1'&x"62FC",'1'&x"62FD",'1'&x"62FE",'1'&x"62FF",
+--'1'&x"6300",'1'&x"6301",'1'&x"6302",'1'&x"6303",'1'&x"6304",'1'&x"6305",'1'&x"6306",'1'&x"6307",'1'&x"6308",'1'&x"6309",'1'&x"630A",'1'&x"630B",'1'&x"630C",'1'&x"630D",'1'&x"630E",'1'&x"630F",
+--'1'&x"6310",'1'&x"6311",'1'&x"6312",'1'&x"6313",'1'&x"6314",'1'&x"6315",'1'&x"6316",'1'&x"6317",'1'&x"6318",'1'&x"6319",'1'&x"631A",'1'&x"631B",'1'&x"631C",'1'&x"631D",'1'&x"631E",'1'&x"631F",
+--'1'&x"6320",'1'&x"6321",'1'&x"6322",'1'&x"6323",'1'&x"6324",'1'&x"6325",'1'&x"6326",'1'&x"6327",'1'&x"6328",'1'&x"6329",'1'&x"632A",'1'&x"632B",'1'&x"632C",'1'&x"632D",'1'&x"632E",'1'&x"632F",
+--'1'&x"6330",'1'&x"6331",'1'&x"6332",'1'&x"6333",'1'&x"6334",'1'&x"6335",'1'&x"6336",'1'&x"6337",'1'&x"6338",'1'&x"6339",'1'&x"633A",'1'&x"633B",'1'&x"633C",'1'&x"633D",'1'&x"633E",'1'&x"633F",
+--'1'&x"6340",'1'&x"6341",'1'&x"6342",'1'&x"6343",'1'&x"6344",'1'&x"6345",'1'&x"6346",'1'&x"6347",'1'&x"6348",'1'&x"6349",'1'&x"634A",'1'&x"634B",'1'&x"634C",'1'&x"634D",'1'&x"634E",'1'&x"634F",
+--'1'&x"6350",'1'&x"6351",'1'&x"6352",'1'&x"6353",'1'&x"6354",'1'&x"6355",'1'&x"6356",'1'&x"6357",'1'&x"6358",'1'&x"6359",'1'&x"635A",'1'&x"635B",'1'&x"635C",'1'&x"635D",'1'&x"635E",'1'&x"635F",
+--'1'&x"6360",'1'&x"6361",'1'&x"6362",'1'&x"6363",'1'&x"6364",'1'&x"6365",'1'&x"6366",'1'&x"6367",'1'&x"6368",'1'&x"6369",'1'&x"636A",'1'&x"636B",'1'&x"636C",'1'&x"636D",'1'&x"636E",'1'&x"636F",
+--'1'&x"6370",'1'&x"6371",'1'&x"6372",'1'&x"6373",'1'&x"6374",'1'&x"6375",'1'&x"6376",'1'&x"6377",'1'&x"6378",'1'&x"6379",'1'&x"637A",'1'&x"637B",'1'&x"637C",'1'&x"637D",'1'&x"637E",'1'&x"637F",
+--'1'&x"6380",'1'&x"6381",'1'&x"6382",'1'&x"6383",'1'&x"6384",'1'&x"6385",'1'&x"6386",'1'&x"6387",'1'&x"6388",'1'&x"6389",'1'&x"638A",'1'&x"638B",'1'&x"638C",'1'&x"638D",'1'&x"638E",'1'&x"638F",
+--'1'&x"6390",'1'&x"6391",'1'&x"6392",'1'&x"6393",'1'&x"6394",'1'&x"6395",'1'&x"6396",'1'&x"6397",'1'&x"6398",'1'&x"6399",'1'&x"639A",'1'&x"639B",'1'&x"639C",'1'&x"639D",'1'&x"639E",'1'&x"639F",
+--'1'&x"63A0",'1'&x"63A1",'1'&x"63A2",'1'&x"63A3",'1'&x"63A4",'1'&x"63A5",'1'&x"63A6",'1'&x"63A7",'1'&x"63A8",'1'&x"63A9",'1'&x"63AA",'1'&x"63AB",'1'&x"63AC",'1'&x"63AD",'1'&x"63AE",'1'&x"63AF",
+--'1'&x"63B0",'1'&x"63B1",'1'&x"63B2",'1'&x"63B3",'1'&x"63B4",'1'&x"63B5",'1'&x"63B6",'1'&x"63B7",'1'&x"63B8",'1'&x"63B9",'1'&x"63BA",'1'&x"63BB",'1'&x"63BC",'1'&x"63BD",'1'&x"63BE",'1'&x"63BF",
+--'1'&x"63C0",'1'&x"63C1",'1'&x"63C2",'1'&x"63C3",'1'&x"63C4",'1'&x"63C5",'1'&x"63C6",'1'&x"63C7",'1'&x"63C8",'1'&x"63C9",'1'&x"63CA",'1'&x"63CB",'1'&x"63CC",'1'&x"63CD",'1'&x"63CE",'1'&x"63CF",
+--'1'&x"63D0",'1'&x"63D1",'1'&x"63D2",'1'&x"63D3",'1'&x"63D4",'1'&x"63D5",'1'&x"63D6",'1'&x"63D7",'1'&x"63D8",'1'&x"63D9",'1'&x"63DA",'1'&x"63DB",'1'&x"63DC",'1'&x"63DD",'1'&x"63DE",'1'&x"63DF",
+--'1'&x"63E0",'1'&x"63E1",'1'&x"63E2",'1'&x"63E3",'1'&x"63E4",'1'&x"63E5",'1'&x"63E6",'1'&x"63E7",'1'&x"63E8",'1'&x"63E9",'1'&x"63EA",'1'&x"63EB",'1'&x"63EC",'1'&x"63ED",'1'&x"63EE",'1'&x"63EF",
+--'1'&x"63F0",'1'&x"63F1",'1'&x"63F2",'1'&x"63F3",'1'&x"63F4",'1'&x"63F5",'1'&x"63F6",'1'&x"63F7",'1'&x"63F8",'1'&x"63F9",'1'&x"63FA",'1'&x"63FB",'1'&x"63FC",'1'&x"63FD",'1'&x"63FE",'1'&x"63FF",
+--'1'&x"6400",'1'&x"6401",'1'&x"6402",'1'&x"6403",'1'&x"6404",'1'&x"6405",'1'&x"6406",'1'&x"6407",'1'&x"6408",'1'&x"6409",'1'&x"640A",'1'&x"640B",'1'&x"640C",'1'&x"640D",'1'&x"640E",'1'&x"640F",
+--'1'&x"6410",'1'&x"6411",'1'&x"6412",'1'&x"6413",'1'&x"6414",'1'&x"6415",'1'&x"6416",'1'&x"6417",'1'&x"6418",'1'&x"6419",'1'&x"641A",'1'&x"641B",'1'&x"641C",'1'&x"641D",'1'&x"641E",'1'&x"641F",
+--'1'&x"6420",'1'&x"6421",'1'&x"6422",'1'&x"6423",'1'&x"6424",'1'&x"6425",'1'&x"6426",'1'&x"6427",'1'&x"6428",'1'&x"6429",'1'&x"642A",'1'&x"642B",'1'&x"642C",'1'&x"642D",'1'&x"642E",'1'&x"642F",
+--'1'&x"6430",'1'&x"6431",'1'&x"6432",'1'&x"6433",'1'&x"6434",'1'&x"6435",'1'&x"6436",'1'&x"6437",'1'&x"6438",'1'&x"6439",'1'&x"643A",'1'&x"643B",'1'&x"643C",'1'&x"643D",'1'&x"643E",'1'&x"643F",
+--'1'&x"6440",'1'&x"6441",'1'&x"6442",'1'&x"6443",'1'&x"6444",'1'&x"6445",'1'&x"6446",'1'&x"6447",'1'&x"6448",'1'&x"6449",'1'&x"644A",'1'&x"644B",'1'&x"644C",'1'&x"644D",'1'&x"644E",'1'&x"644F",
+--'1'&x"6450",'1'&x"6451",'1'&x"6452",'1'&x"6453",'1'&x"6454",'1'&x"6455",'1'&x"6456",'1'&x"6457",'1'&x"6458",'1'&x"6459",'1'&x"645A",'1'&x"645B",'1'&x"645C",'1'&x"645D",'1'&x"645E",'1'&x"645F",
+--'1'&x"6460",'1'&x"6461",'1'&x"6462",'1'&x"6463",'1'&x"6464",'1'&x"6465",'1'&x"6466",'1'&x"6467",'1'&x"6468",'1'&x"6469",'1'&x"646A",'1'&x"646B",'1'&x"646C",'1'&x"646D",'1'&x"646E",'1'&x"646F",
+--'1'&x"6470",'1'&x"6471",'1'&x"6472",'1'&x"6473",'1'&x"6474",'1'&x"6475",'1'&x"6476",'1'&x"6477",'1'&x"6478",'1'&x"6479",'1'&x"647A",'1'&x"647B",'1'&x"647C",'1'&x"647D",'1'&x"647E",'1'&x"647F",
+--'1'&x"6480",'1'&x"6481",'1'&x"6482",'1'&x"6483",'1'&x"6484",'1'&x"6485",'1'&x"6486",'1'&x"6487",'1'&x"6488",'1'&x"6489",'1'&x"648A",'1'&x"648B",'1'&x"648C",'1'&x"648D",'1'&x"648E",'1'&x"648F",
+--'1'&x"6490",'1'&x"6491",'1'&x"6492",'1'&x"6493",'1'&x"6494",'1'&x"6495",'1'&x"6496",'1'&x"6497",'1'&x"6498",'1'&x"6499",'1'&x"649A",'1'&x"649B",'1'&x"649C",'1'&x"649D",'1'&x"649E",'1'&x"649F",
+--'1'&x"64A0",'1'&x"64A1",'1'&x"64A2",'1'&x"64A3",'1'&x"64A4",'1'&x"64A5",'1'&x"64A6",'1'&x"64A7",'1'&x"64A8",'1'&x"64A9",'1'&x"64AA",'1'&x"64AB",'1'&x"64AC",'1'&x"64AD",'1'&x"64AE",'1'&x"64AF",
+--'1'&x"64B0",'1'&x"64B1",'1'&x"64B2",'1'&x"64B3",'1'&x"64B4",'1'&x"64B5",'1'&x"64B6",'1'&x"64B7",'1'&x"64B8",'1'&x"64B9",'1'&x"64BA",'1'&x"64BB",'1'&x"64BC",'1'&x"64BD",'1'&x"64BE",'1'&x"64BF",
+--'1'&x"64C0",'1'&x"64C1",'1'&x"64C2",'1'&x"64C3",'1'&x"64C4",'1'&x"64C5",'1'&x"64C6",'1'&x"64C7",'1'&x"64C8",'1'&x"64C9",'1'&x"64CA",'1'&x"64CB",'1'&x"64CC",'1'&x"64CD",'1'&x"64CE",'1'&x"64CF",
+--'1'&x"64D0",'1'&x"64D1",'1'&x"64D2",'1'&x"64D3",'1'&x"64D4",'1'&x"64D5",'1'&x"64D6",'1'&x"64D7",'1'&x"64D8",'1'&x"64D9",'1'&x"64DA",'1'&x"64DB",'1'&x"64DC",'1'&x"64DD",'1'&x"64DE",'1'&x"64DF",
+--'1'&x"64E0",'1'&x"64E1",'1'&x"64E2",'1'&x"64E3",'1'&x"64E4",'1'&x"64E5",'1'&x"64E6",'1'&x"64E7",'1'&x"64E8",'1'&x"64E9",'1'&x"64EA",'1'&x"64EB",'1'&x"64EC",'1'&x"64ED",'1'&x"64EE",'1'&x"64EF",
+--'1'&x"64F0",'1'&x"64F1",'1'&x"64F2",'1'&x"64F3",'1'&x"64F4",'1'&x"64F5",'1'&x"64F6",'1'&x"64F7",'1'&x"64F8",'1'&x"64F9",'1'&x"64FA",'1'&x"64FB",'1'&x"64FC",'1'&x"64FD",'1'&x"64FE",'1'&x"64FF",
+--'1'&x"6500",'1'&x"6501",'1'&x"6502",'1'&x"6503",'1'&x"6504",'1'&x"6505",'1'&x"6506",'1'&x"6507",'1'&x"6508",'1'&x"6509",'1'&x"650A",'1'&x"650B",'1'&x"650C",'1'&x"650D",'1'&x"650E",'1'&x"650F",
+--'1'&x"6510",'1'&x"6511",'1'&x"6512",'1'&x"6513",'1'&x"6514",'1'&x"6515",'1'&x"6516",'1'&x"6517",'1'&x"6518",'1'&x"6519",'1'&x"651A",'1'&x"651B",'1'&x"651C",'1'&x"651D",'1'&x"651E",'1'&x"651F",
+--'1'&x"6520",'1'&x"6521",'1'&x"6522",'1'&x"6523",'1'&x"6524",'1'&x"6525",'1'&x"6526",'1'&x"6527",'1'&x"6528",'1'&x"6529",'1'&x"652A",'1'&x"652B",'1'&x"652C",'1'&x"652D",'1'&x"652E",'1'&x"652F",
+--'1'&x"6530",'1'&x"6531",'1'&x"6532",'1'&x"6533",'1'&x"6534",'1'&x"6535",'1'&x"6536",'1'&x"6537",'1'&x"6538",'1'&x"6539",'1'&x"653A",'1'&x"653B",'1'&x"653C",'1'&x"653D",'1'&x"653E",'1'&x"653F",
+--'1'&x"6540",'1'&x"6541",'1'&x"6542",'1'&x"6543",'1'&x"6544",'1'&x"6545",'1'&x"6546",'1'&x"6547",'1'&x"6548",'1'&x"6549",'1'&x"654A",'1'&x"654B",'1'&x"654C",'1'&x"654D",'1'&x"654E",'1'&x"654F",
+--'1'&x"6550",'1'&x"6551",'1'&x"6552",'1'&x"6553",'1'&x"6554",'1'&x"6555",'1'&x"6556",'1'&x"6557",'1'&x"6558",'1'&x"6559",'1'&x"655A",'1'&x"655B",'1'&x"655C",'1'&x"655D",'1'&x"655E",'1'&x"655F",
+--'1'&x"6560",'1'&x"6561",'1'&x"6562",'1'&x"6563",'1'&x"6564",'1'&x"6565",'1'&x"6566",'1'&x"6567",'1'&x"6568",'1'&x"6569",'1'&x"656A",'1'&x"656B",'1'&x"656C",'1'&x"656D",'1'&x"656E",'1'&x"656F",
+--'1'&x"6570",'1'&x"6571",'1'&x"6572",'1'&x"6573",'1'&x"6574",'1'&x"6575",'1'&x"6576",'1'&x"6577",'1'&x"6578",'1'&x"6579",'1'&x"657A",'1'&x"657B",'1'&x"657C",'1'&x"657D",'1'&x"657E",'1'&x"657F",
+--'1'&x"6580",'1'&x"6581",'1'&x"6582",'1'&x"6583",'1'&x"6584",'1'&x"6585",'1'&x"6586",'1'&x"6587",'1'&x"6588",'1'&x"6589",'1'&x"658A",'1'&x"658B",'1'&x"658C",'1'&x"658D",'1'&x"658E",'1'&x"658F",
+--'1'&x"6590",'1'&x"6591",'1'&x"6592",'1'&x"6593",'1'&x"6594",'1'&x"6595",'1'&x"6596",'1'&x"6597",'1'&x"6598",'1'&x"6599",'1'&x"659A",'1'&x"659B",'1'&x"659C",'1'&x"659D",'1'&x"659E",'1'&x"659F",
+--'1'&x"65A0",'1'&x"65A1",'1'&x"65A2",'1'&x"65A3",'1'&x"65A4",'1'&x"65A5",'1'&x"65A6",'1'&x"65A7",'1'&x"65A8",'1'&x"65A9",'1'&x"65AA",'1'&x"65AB",'1'&x"65AC",'1'&x"65AD",'1'&x"65AE",'1'&x"65AF",
+--'1'&x"65B0",'1'&x"65B1",'1'&x"65B2",'1'&x"65B3",'1'&x"65B4",'1'&x"65B5",'1'&x"65B6",'1'&x"65B7",'1'&x"65B8",'1'&x"65B9",'1'&x"65BA",'1'&x"65BB",'1'&x"65BC",'1'&x"65BD",'1'&x"65BE",'1'&x"65BF",
+--'1'&x"65C0",'1'&x"65C1",'1'&x"65C2",'1'&x"65C3",'1'&x"65C4",'1'&x"65C5",'1'&x"65C6",'1'&x"65C7",'1'&x"65C8",'1'&x"65C9",'1'&x"65CA",'1'&x"65CB",'1'&x"65CC",'1'&x"65CD",'1'&x"65CE",'1'&x"65CF",
+--'1'&x"65D0",'1'&x"65D1",'1'&x"65D2",'1'&x"65D3",'1'&x"65D4",'1'&x"65D5",'1'&x"65D6",'1'&x"65D7",'1'&x"65D8",'1'&x"65D9",'1'&x"65DA",'1'&x"65DB",'1'&x"65DC",'1'&x"65DD",'1'&x"65DE",'1'&x"65DF",
+--'1'&x"65E0",'1'&x"65E1",'1'&x"65E2",'1'&x"65E3",'1'&x"65E4",'1'&x"65E5",'1'&x"65E6",'1'&x"65E7",'1'&x"65E8",'1'&x"65E9",'1'&x"65EA",'1'&x"65EB",'1'&x"65EC",'1'&x"65ED",'1'&x"65EE",'1'&x"65EF",
+--'1'&x"65F0",'1'&x"65F1",'1'&x"65F2",'1'&x"65F3",'1'&x"65F4",'1'&x"65F5",'1'&x"65F6",'1'&x"65F7",'1'&x"65F8",'1'&x"65F9",'1'&x"65FA",'1'&x"65FB",'1'&x"65FC",'1'&x"65FD",'1'&x"65FE",'1'&x"65FF",
+--'1'&x"6600",'1'&x"6601",'1'&x"6602",'1'&x"6603",'1'&x"6604",'1'&x"6605",'1'&x"6606",'1'&x"6607",'1'&x"6608",'1'&x"6609",'1'&x"660A",'1'&x"660B",'1'&x"660C",'1'&x"660D",'1'&x"660E",'1'&x"660F",
+--'1'&x"6610",'1'&x"6611",'1'&x"6612",'1'&x"6613",'1'&x"6614",'1'&x"6615",'1'&x"6616",'1'&x"6617",'1'&x"6618",'1'&x"6619",'1'&x"661A",'1'&x"661B",'1'&x"661C",'1'&x"661D",'1'&x"661E",'1'&x"661F",
+--'1'&x"6620",'1'&x"6621",'1'&x"6622",'1'&x"6623",'1'&x"6624",'1'&x"6625",'1'&x"6626",'1'&x"6627",'1'&x"6628",'1'&x"6629",'1'&x"662A",'1'&x"662B",'1'&x"662C",'1'&x"662D",'1'&x"662E",'1'&x"662F",
+--'1'&x"6630",'1'&x"6631",'1'&x"6632",'1'&x"6633",'1'&x"6634",'1'&x"6635",'1'&x"6636",'1'&x"6637",'1'&x"6638",'1'&x"6639",'1'&x"663A",'1'&x"663B",'1'&x"663C",'1'&x"663D",'1'&x"663E",'1'&x"663F",
+--'1'&x"6640",'1'&x"6641",'1'&x"6642",'1'&x"6643",'1'&x"6644",'1'&x"6645",'1'&x"6646",'1'&x"6647",'1'&x"6648",'1'&x"6649",'1'&x"664A",'1'&x"664B",'1'&x"664C",'1'&x"664D",'1'&x"664E",'1'&x"664F",
+--'1'&x"6650",'1'&x"6651",'1'&x"6652",'1'&x"6653",'1'&x"6654",'1'&x"6655",'1'&x"6656",'1'&x"6657",'1'&x"6658",'1'&x"6659",'1'&x"665A",'1'&x"665B",'1'&x"665C",'1'&x"665D",'1'&x"665E",'1'&x"665F",
+--'1'&x"6660",'1'&x"6661",'1'&x"6662",'1'&x"6663",'1'&x"6664",'1'&x"6665",'1'&x"6666",'1'&x"6667",'1'&x"6668",'1'&x"6669",'1'&x"666A",'1'&x"666B",'1'&x"666C",'1'&x"666D",'1'&x"666E",'1'&x"666F",
+--'1'&x"6670",'1'&x"6671",'1'&x"6672",'1'&x"6673",'1'&x"6674",'1'&x"6675",'1'&x"6676",'1'&x"6677",'1'&x"6678",'1'&x"6679",'1'&x"667A",'1'&x"667B",'1'&x"667C",'1'&x"667D",'1'&x"667E",'1'&x"667F",
+--'1'&x"6680",'1'&x"6681",'1'&x"6682",'1'&x"6683",'1'&x"6684",'1'&x"6685",'1'&x"6686",'1'&x"6687",'1'&x"6688",'1'&x"6689",'1'&x"668A",'1'&x"668B",'1'&x"668C",'1'&x"668D",'1'&x"668E",'1'&x"668F",
+--'1'&x"6690",'1'&x"6691",'1'&x"6692",'1'&x"6693",'1'&x"6694",'1'&x"6695",'1'&x"6696",'1'&x"6697",'1'&x"6698",'1'&x"6699",'1'&x"669A",'1'&x"669B",'1'&x"669C",'1'&x"669D",'1'&x"669E",'1'&x"669F",
+--'1'&x"66A0",'1'&x"66A1",'1'&x"66A2",'1'&x"66A3",'1'&x"66A4",'1'&x"66A5",'1'&x"66A6",'1'&x"66A7",'1'&x"66A8",'1'&x"66A9",'1'&x"66AA",'1'&x"66AB",'1'&x"66AC",'1'&x"66AD",'1'&x"66AE",'1'&x"66AF",
+--'1'&x"66B0",'1'&x"66B1",'1'&x"66B2",'1'&x"66B3",'1'&x"66B4",'1'&x"66B5",'1'&x"66B6",'1'&x"66B7",'1'&x"66B8",'1'&x"66B9",'1'&x"66BA",'1'&x"66BB",'1'&x"66BC",'1'&x"66BD",'1'&x"66BE",'1'&x"66BF",
+--'1'&x"66C0",'1'&x"66C1",'1'&x"66C2",'1'&x"66C3",'1'&x"66C4",'1'&x"66C5",'1'&x"66C6",'1'&x"66C7",'1'&x"66C8",'1'&x"66C9",'1'&x"66CA",'1'&x"66CB",'1'&x"66CC",'1'&x"66CD",'1'&x"66CE",'1'&x"66CF",
+--'1'&x"66D0",'1'&x"66D1",'1'&x"66D2",'1'&x"66D3",'1'&x"66D4",'1'&x"66D5",'1'&x"66D6",'1'&x"66D7",'1'&x"66D8",'1'&x"66D9",'1'&x"66DA",'1'&x"66DB",'1'&x"66DC",'1'&x"66DD",'1'&x"66DE",'1'&x"66DF",
+--'1'&x"66E0",'1'&x"66E1",'1'&x"66E2",'1'&x"66E3",'1'&x"66E4",'1'&x"66E5",'1'&x"66E6",'1'&x"66E7",'1'&x"66E8",'1'&x"66E9",'1'&x"66EA",'1'&x"66EB",'1'&x"66EC",'1'&x"66ED",'1'&x"66EE",'1'&x"66EF",
+--'1'&x"66F0",'1'&x"66F1",'1'&x"66F2",'1'&x"66F3",'1'&x"66F4",'1'&x"66F5",'1'&x"66F6",'1'&x"66F7",'1'&x"66F8",'1'&x"66F9",'1'&x"66FA",'1'&x"66FB",'1'&x"66FC",'1'&x"66FD",'1'&x"66FE",'1'&x"66FF",
+--'1'&x"6700",'1'&x"6701",'1'&x"6702",'1'&x"6703",'1'&x"6704",'1'&x"6705",'1'&x"6706",'1'&x"6707",'1'&x"6708",'1'&x"6709",'1'&x"670A",'1'&x"670B",'1'&x"670C",'1'&x"670D",'1'&x"670E",'1'&x"670F",
+--'1'&x"6710",'1'&x"6711",'1'&x"6712",'1'&x"6713",'1'&x"6714",'1'&x"6715",'1'&x"6716",'1'&x"6717",'1'&x"6718",'1'&x"6719",'1'&x"671A",'1'&x"671B",'1'&x"671C",'1'&x"671D",'1'&x"671E",'1'&x"671F",
+--'1'&x"6720",'1'&x"6721",'1'&x"6722",'1'&x"6723",'1'&x"6724",'1'&x"6725",'1'&x"6726",'1'&x"6727",'1'&x"6728",'1'&x"6729",'1'&x"672A",'1'&x"672B",'1'&x"672C",'1'&x"672D",'1'&x"672E",'1'&x"672F",
+--'1'&x"6730",'1'&x"6731",'1'&x"6732",'1'&x"6733",'1'&x"6734",'1'&x"6735",'1'&x"6736",'1'&x"6737",'1'&x"6738",'1'&x"6739",'1'&x"673A",'1'&x"673B",'1'&x"673C",'1'&x"673D",'1'&x"673E",'1'&x"673F",
+--'1'&x"6740",'1'&x"6741",'1'&x"6742",'1'&x"6743",'1'&x"6744",'1'&x"6745",'1'&x"6746",'1'&x"6747",'1'&x"6748",'1'&x"6749",'1'&x"674A",'1'&x"674B",'1'&x"674C",'1'&x"674D",'1'&x"674E",'1'&x"674F",
+--'1'&x"6750",'1'&x"6751",'1'&x"6752",'1'&x"6753",'1'&x"6754",'1'&x"6755",'1'&x"6756",'1'&x"6757",'1'&x"6758",'1'&x"6759",'1'&x"675A",'1'&x"675B",'1'&x"675C",'1'&x"675D",'1'&x"675E",'1'&x"675F",
+--'1'&x"6760",'1'&x"6761",'1'&x"6762",'1'&x"6763",'1'&x"6764",'1'&x"6765",'1'&x"6766",'1'&x"6767",'1'&x"6768",'1'&x"6769",'1'&x"676A",'1'&x"676B",'1'&x"676C",'1'&x"676D",'1'&x"676E",'1'&x"676F",
+--'1'&x"6770",'1'&x"6771",'1'&x"6772",'1'&x"6773",'1'&x"6774",'1'&x"6775",'1'&x"6776",'1'&x"6777",'1'&x"6778",'1'&x"6779",'1'&x"677A",'1'&x"677B",'1'&x"677C",'1'&x"677D",'1'&x"677E",'1'&x"677F",
+--'1'&x"6780",'1'&x"6781",'1'&x"6782",'1'&x"6783",'1'&x"6784",'1'&x"6785",'1'&x"6786",'1'&x"6787",'1'&x"6788",'1'&x"6789",'1'&x"678A",'1'&x"678B",'1'&x"678C",'1'&x"678D",'1'&x"678E",'1'&x"678F",
+--'1'&x"6790",'1'&x"6791",'1'&x"6792",'1'&x"6793",'1'&x"6794",'1'&x"6795",'1'&x"6796",'1'&x"6797",'1'&x"6798",'1'&x"6799",'1'&x"679A",'1'&x"679B",'1'&x"679C",'1'&x"679D",'1'&x"679E",'1'&x"679F",
+--'1'&x"67A0",'1'&x"67A1",'1'&x"67A2",'1'&x"67A3",'1'&x"67A4",'1'&x"67A5",'1'&x"67A6",'1'&x"67A7",'1'&x"67A8",'1'&x"67A9",'1'&x"67AA",'1'&x"67AB",'1'&x"67AC",'1'&x"67AD",'1'&x"67AE",'1'&x"67AF",
+--'1'&x"67B0",'1'&x"67B1",'1'&x"67B2",'1'&x"67B3",'1'&x"67B4",'1'&x"67B5",'1'&x"67B6",'1'&x"67B7",'1'&x"67B8",'1'&x"67B9",'1'&x"67BA",'1'&x"67BB",'1'&x"67BC",'1'&x"67BD",'1'&x"67BE",'1'&x"67BF",
+--'1'&x"67C0",'1'&x"67C1",'1'&x"67C2",'1'&x"67C3",'1'&x"67C4",'1'&x"67C5",'1'&x"67C6",'1'&x"67C7",'1'&x"67C8",'1'&x"67C9",'1'&x"67CA",'1'&x"67CB",'1'&x"67CC",'1'&x"67CD",'1'&x"67CE",'1'&x"67CF",
+--'1'&x"67D0",'1'&x"67D1",'1'&x"67D2",'1'&x"67D3",'1'&x"67D4",'1'&x"67D5",'1'&x"67D6",'1'&x"67D7",'1'&x"67D8",'1'&x"67D9",'1'&x"67DA",'1'&x"67DB",'1'&x"67DC",'1'&x"67DD",'1'&x"67DE",'1'&x"67DF",
+--'1'&x"67E0",'1'&x"67E1",'1'&x"67E2",'1'&x"67E3",'1'&x"67E4",'1'&x"67E5",'1'&x"67E6",'1'&x"67E7",'1'&x"67E8",'1'&x"67E9",'1'&x"67EA",'1'&x"67EB",'1'&x"67EC",'1'&x"67ED",'1'&x"67EE",'1'&x"67EF",
+--'1'&x"67F0",'1'&x"67F1",'1'&x"67F2",'1'&x"67F3",'1'&x"67F4",'1'&x"67F5",'1'&x"67F6",'1'&x"67F7",'1'&x"67F8",'1'&x"67F9",'1'&x"67FA",'1'&x"67FB",'1'&x"67FC",'1'&x"67FD",'1'&x"67FE",'1'&x"67FF",
+--'1'&x"6800",'1'&x"6801",'1'&x"6802",'1'&x"6803",'1'&x"6804",'1'&x"6805",'1'&x"6806",'1'&x"6807",'1'&x"6808",'1'&x"6809",'1'&x"680A",'1'&x"680B",'1'&x"680C",'1'&x"680D",'1'&x"680E",'1'&x"680F",
+--'1'&x"6810",'1'&x"6811",'1'&x"6812",'1'&x"6813",'1'&x"6814",'1'&x"6815",'1'&x"6816",'1'&x"6817",'1'&x"6818",'1'&x"6819",'1'&x"681A",'1'&x"681B",'1'&x"681C",'1'&x"681D",'1'&x"681E",'1'&x"681F",
+--'1'&x"6820",'1'&x"6821",'1'&x"6822",'1'&x"6823",'1'&x"6824",'1'&x"6825",'1'&x"6826",'1'&x"6827",'1'&x"6828",'1'&x"6829",'1'&x"682A",'1'&x"682B",'1'&x"682C",'1'&x"682D",'1'&x"682E",'1'&x"682F",
+--'1'&x"6830",'1'&x"6831",'1'&x"6832",'1'&x"6833",'1'&x"6834",'1'&x"6835",'1'&x"6836",'1'&x"6837",'1'&x"6838",'1'&x"6839",'1'&x"683A",'1'&x"683B",'1'&x"683C",'1'&x"683D",'1'&x"683E",'1'&x"683F",
+--'1'&x"6840",'1'&x"6841",'1'&x"6842",'1'&x"6843",'1'&x"6844",'1'&x"6845",'1'&x"6846",'1'&x"6847",'1'&x"6848",'1'&x"6849",'1'&x"684A",'1'&x"684B",'1'&x"684C",'1'&x"684D",'1'&x"684E",'1'&x"684F",
+--'1'&x"6850",'1'&x"6851",'1'&x"6852",'1'&x"6853",'1'&x"6854",'1'&x"6855",'1'&x"6856",'1'&x"6857",'1'&x"6858",'1'&x"6859",'1'&x"685A",'1'&x"685B",'1'&x"685C",'1'&x"685D",'1'&x"685E",'1'&x"685F",
+--'1'&x"6860",'1'&x"6861",'1'&x"6862",'1'&x"6863",'1'&x"6864",'1'&x"6865",'1'&x"6866",'1'&x"6867",'1'&x"6868",'1'&x"6869",'1'&x"686A",'1'&x"686B",'1'&x"686C",'1'&x"686D",'1'&x"686E",'1'&x"686F",
+--'1'&x"6870",'1'&x"6871",'1'&x"6872",'1'&x"6873",'1'&x"6874",'1'&x"6875",'1'&x"6876",'1'&x"6877",'1'&x"6878",'1'&x"6879",'1'&x"687A",'1'&x"687B",'1'&x"687C",'1'&x"687D",'1'&x"687E",'1'&x"687F",
+--'1'&x"6880",'1'&x"6881",'1'&x"6882",'1'&x"6883",'1'&x"6884",'1'&x"6885",'1'&x"6886",'1'&x"6887",'1'&x"6888",'1'&x"6889",'1'&x"688A",'1'&x"688B",'1'&x"688C",'1'&x"688D",'1'&x"688E",'1'&x"688F",
+--'1'&x"6890",'1'&x"6891",'1'&x"6892",'1'&x"6893",'1'&x"6894",'1'&x"6895",'1'&x"6896",'1'&x"6897",'1'&x"6898",'1'&x"6899",'1'&x"689A",'1'&x"689B",'1'&x"689C",'1'&x"689D",'1'&x"689E",'1'&x"689F",
+--'1'&x"68A0",'1'&x"68A1",'1'&x"68A2",'1'&x"68A3",'1'&x"68A4",'1'&x"68A5",'1'&x"68A6",'1'&x"68A7",'1'&x"68A8",'1'&x"68A9",'1'&x"68AA",'1'&x"68AB",'1'&x"68AC",'1'&x"68AD",'1'&x"68AE",'1'&x"68AF",
+--'1'&x"68B0",'1'&x"68B1",'1'&x"68B2",'1'&x"68B3",'1'&x"68B4",'1'&x"68B5",'1'&x"68B6",'1'&x"68B7",'1'&x"68B8",'1'&x"68B9",'1'&x"68BA",'1'&x"68BB",'1'&x"68BC",'1'&x"68BD",'1'&x"68BE",'1'&x"68BF",
+--'1'&x"68C0",'1'&x"68C1",'1'&x"68C2",'1'&x"68C3",'1'&x"68C4",'1'&x"68C5",'1'&x"68C6",'1'&x"68C7",'1'&x"68C8",'1'&x"68C9",'1'&x"68CA",'1'&x"68CB",'1'&x"68CC",'1'&x"68CD",'1'&x"68CE",'1'&x"68CF",
+--'1'&x"68D0",'1'&x"68D1",'1'&x"68D2",'1'&x"68D3",'1'&x"68D4",'1'&x"68D5",'1'&x"68D6",'1'&x"68D7",'1'&x"68D8",'1'&x"68D9",'1'&x"68DA",'1'&x"68DB",'1'&x"68DC",'1'&x"68DD",'1'&x"68DE",'1'&x"68DF",
+--'1'&x"68E0",'1'&x"68E1",'1'&x"68E2",'1'&x"68E3",'1'&x"68E4",'1'&x"68E5",'1'&x"68E6",'1'&x"68E7",'1'&x"68E8",'1'&x"68E9",'1'&x"68EA",'1'&x"68EB",'1'&x"68EC",'1'&x"68ED",'1'&x"68EE",'1'&x"68EF",
+--'1'&x"68F0",'1'&x"68F1",'1'&x"68F2",'1'&x"68F3",'1'&x"68F4",'1'&x"68F5",'1'&x"68F6",'1'&x"68F7",'1'&x"68F8",'1'&x"68F9",'1'&x"68FA",'1'&x"68FB",'1'&x"68FC",'1'&x"68FD",'1'&x"68FE",'1'&x"68FF",
+--'1'&x"6900",'1'&x"6901",'1'&x"6902",'1'&x"6903",'1'&x"6904",'1'&x"6905",'1'&x"6906",'1'&x"6907",'1'&x"6908",'1'&x"6909",'1'&x"690A",'1'&x"690B",'1'&x"690C",'1'&x"690D",'1'&x"690E",'1'&x"690F",
+--'1'&x"6910",'1'&x"6911",'1'&x"6912",'1'&x"6913",'1'&x"6914",'1'&x"6915",'1'&x"6916",'1'&x"6917",'1'&x"6918",'1'&x"6919",'1'&x"691A",'1'&x"691B",'1'&x"691C",'1'&x"691D",'1'&x"691E",'1'&x"691F",
+--'1'&x"6920",'1'&x"6921",'1'&x"6922",'1'&x"6923",'1'&x"6924",'1'&x"6925",'1'&x"6926",'1'&x"6927",'1'&x"6928",'1'&x"6929",'1'&x"692A",'1'&x"692B",'1'&x"692C",'1'&x"692D",'1'&x"692E",'1'&x"692F",
+--'1'&x"6930",'1'&x"6931",'1'&x"6932",'1'&x"6933",'1'&x"6934",'1'&x"6935",'1'&x"6936",'1'&x"6937",'1'&x"6938",'1'&x"6939",'1'&x"693A",'1'&x"693B",'1'&x"693C",'1'&x"693D",'1'&x"693E",'1'&x"693F",
+--'1'&x"6940",'1'&x"6941",'1'&x"6942",'1'&x"6943",'1'&x"6944",'1'&x"6945",'1'&x"6946",'1'&x"6947",'1'&x"6948",'1'&x"6949",'1'&x"694A",'1'&x"694B",'1'&x"694C",'1'&x"694D",'1'&x"694E",'1'&x"694F",
+--'1'&x"6950",'1'&x"6951",'1'&x"6952",'1'&x"6953",'1'&x"6954",'1'&x"6955",'1'&x"6956",'1'&x"6957",'1'&x"6958",'1'&x"6959",'1'&x"695A",'1'&x"695B",'1'&x"695C",'1'&x"695D",'1'&x"695E",'1'&x"695F",
+--'1'&x"6960",'1'&x"6961",'1'&x"6962",'1'&x"6963",'1'&x"6964",'1'&x"6965",'1'&x"6966",'1'&x"6967",'1'&x"6968",'1'&x"6969",'1'&x"696A",'1'&x"696B",'1'&x"696C",'1'&x"696D",'1'&x"696E",'1'&x"696F",
+--'1'&x"6970",'1'&x"6971",'1'&x"6972",'1'&x"6973",'1'&x"6974",'1'&x"6975",'1'&x"6976",'1'&x"6977",'1'&x"6978",'1'&x"6979",'1'&x"697A",'1'&x"697B",'1'&x"697C",'1'&x"697D",'1'&x"697E",'1'&x"697F",
+--'1'&x"6980",'1'&x"6981",'1'&x"6982",'1'&x"6983",'1'&x"6984",'1'&x"6985",'1'&x"6986",'1'&x"6987",'1'&x"6988",'1'&x"6989",'1'&x"698A",'1'&x"698B",'1'&x"698C",'1'&x"698D",'1'&x"698E",'1'&x"698F",
+--'1'&x"6990",'1'&x"6991",'1'&x"6992",'1'&x"6993",'1'&x"6994",'1'&x"6995",'1'&x"6996",'1'&x"6997",'1'&x"6998",'1'&x"6999",'1'&x"699A",'1'&x"699B",'1'&x"699C",'1'&x"699D",'1'&x"699E",'1'&x"699F",
+--'1'&x"69A0",'1'&x"69A1",'1'&x"69A2",'1'&x"69A3",'1'&x"69A4",'1'&x"69A5",'1'&x"69A6",'1'&x"69A7",'1'&x"69A8",'1'&x"69A9",'1'&x"69AA",'1'&x"69AB",'1'&x"69AC",'1'&x"69AD",'1'&x"69AE",'1'&x"69AF",
+--'1'&x"69B0",'1'&x"69B1",'1'&x"69B2",'1'&x"69B3",'1'&x"69B4",'1'&x"69B5",'1'&x"69B6",'1'&x"69B7",'1'&x"69B8",'1'&x"69B9",'1'&x"69BA",'1'&x"69BB",'1'&x"69BC",'1'&x"69BD",'1'&x"69BE",'1'&x"69BF",
+--'1'&x"69C0",'1'&x"69C1",'1'&x"69C2",'1'&x"69C3",'1'&x"69C4",'1'&x"69C5",'1'&x"69C6",'1'&x"69C7",'1'&x"69C8",'1'&x"69C9",'1'&x"69CA",'1'&x"69CB",'1'&x"69CC",'1'&x"69CD",'1'&x"69CE",'1'&x"69CF",
+--'1'&x"69D0",'1'&x"69D1",'1'&x"69D2",'1'&x"69D3",'1'&x"69D4",'1'&x"69D5",'1'&x"69D6",'1'&x"69D7",'1'&x"69D8",'1'&x"69D9",'1'&x"69DA",'1'&x"69DB",'1'&x"69DC",'1'&x"69DD",'1'&x"69DE",'1'&x"69DF",
+--'1'&x"69E0",'1'&x"69E1",'1'&x"69E2",'1'&x"69E3",'1'&x"69E4",'1'&x"69E5",'1'&x"69E6",'1'&x"69E7",'1'&x"69E8",'1'&x"69E9",'1'&x"69EA",'1'&x"69EB",'1'&x"69EC",'1'&x"69ED",'1'&x"69EE",'1'&x"69EF",
+--'1'&x"69F0",'1'&x"69F1",'1'&x"69F2",'1'&x"69F3",'1'&x"69F4",'1'&x"69F5",'1'&x"69F6",'1'&x"69F7",'1'&x"69F8",'1'&x"69F9",'1'&x"69FA",'1'&x"69FB",'1'&x"69FC",'1'&x"69FD",'1'&x"69FE",'1'&x"69FF",
+--'1'&x"6A00",'1'&x"6A01",'1'&x"6A02",'1'&x"6A03",'1'&x"6A04",'1'&x"6A05",'1'&x"6A06",'1'&x"6A07",'1'&x"6A08",'1'&x"6A09",'1'&x"6A0A",'1'&x"6A0B",'1'&x"6A0C",'1'&x"6A0D",'1'&x"6A0E",'1'&x"6A0F",
+--'1'&x"6A10",'1'&x"6A11",'1'&x"6A12",'1'&x"6A13",'1'&x"6A14",'1'&x"6A15",'1'&x"6A16",'1'&x"6A17",'1'&x"6A18",'1'&x"6A19",'1'&x"6A1A",'1'&x"6A1B",'1'&x"6A1C",'1'&x"6A1D",'1'&x"6A1E",'1'&x"6A1F",
+--'1'&x"6A20",'1'&x"6A21",'1'&x"6A22",'1'&x"6A23",'1'&x"6A24",'1'&x"6A25",'1'&x"6A26",'1'&x"6A27",'1'&x"6A28",'1'&x"6A29",'1'&x"6A2A",'1'&x"6A2B",'1'&x"6A2C",'1'&x"6A2D",'1'&x"6A2E",'1'&x"6A2F",
+--'1'&x"6A30",'1'&x"6A31",'1'&x"6A32",'1'&x"6A33",'1'&x"6A34",'1'&x"6A35",'1'&x"6A36",'1'&x"6A37",'1'&x"6A38",'1'&x"6A39",'1'&x"6A3A",'1'&x"6A3B",'1'&x"6A3C",'1'&x"6A3D",'1'&x"6A3E",'1'&x"6A3F",
+--'1'&x"6A40",'1'&x"6A41",'1'&x"6A42",'1'&x"6A43",'1'&x"6A44",'1'&x"6A45",'1'&x"6A46",'1'&x"6A47",'1'&x"6A48",'1'&x"6A49",'1'&x"6A4A",'1'&x"6A4B",'1'&x"6A4C",'1'&x"6A4D",'1'&x"6A4E",'1'&x"6A4F",
+--'1'&x"6A50",'1'&x"6A51",'1'&x"6A52",'1'&x"6A53",'1'&x"6A54",'1'&x"6A55",'1'&x"6A56",'1'&x"6A57",'1'&x"6A58",'1'&x"6A59",'1'&x"6A5A",'1'&x"6A5B",'1'&x"6A5C",'1'&x"6A5D",'1'&x"6A5E",'1'&x"6A5F",
+--'1'&x"6A60",'1'&x"6A61",'1'&x"6A62",'1'&x"6A63",'1'&x"6A64",'1'&x"6A65",'1'&x"6A66",'1'&x"6A67",'1'&x"6A68",'1'&x"6A69",'1'&x"6A6A",'1'&x"6A6B",'1'&x"6A6C",'1'&x"6A6D",'1'&x"6A6E",'1'&x"6A6F",
+--'1'&x"6A70",'1'&x"6A71",'1'&x"6A72",'1'&x"6A73",'1'&x"6A74",'1'&x"6A75",'1'&x"6A76",'1'&x"6A77",'1'&x"6A78",'1'&x"6A79",'1'&x"6A7A",'1'&x"6A7B",'1'&x"6A7C",'1'&x"6A7D",'1'&x"6A7E",'1'&x"6A7F",
+--'1'&x"6A80",'1'&x"6A81",'1'&x"6A82",'1'&x"6A83",'1'&x"6A84",'1'&x"6A85",'1'&x"6A86",'1'&x"6A87",'1'&x"6A88",'1'&x"6A89",'1'&x"6A8A",'1'&x"6A8B",'1'&x"6A8C",'1'&x"6A8D",'1'&x"6A8E",'1'&x"6A8F",
+--'1'&x"6A90",'1'&x"6A91",'1'&x"6A92",'1'&x"6A93",'1'&x"6A94",'1'&x"6A95",'1'&x"6A96",'1'&x"6A97",'1'&x"6A98",'1'&x"6A99",'1'&x"6A9A",'1'&x"6A9B",'1'&x"6A9C",'1'&x"6A9D",'1'&x"6A9E",'1'&x"6A9F",
+--'1'&x"6AA0",'1'&x"6AA1",'1'&x"6AA2",'1'&x"6AA3",'1'&x"6AA4",'1'&x"6AA5",'1'&x"6AA6",'1'&x"6AA7",'1'&x"6AA8",'1'&x"6AA9",'1'&x"6AAA",'1'&x"6AAB",'1'&x"6AAC",'1'&x"6AAD",'1'&x"6AAE",'1'&x"6AAF",
+--'1'&x"6AB0",'1'&x"6AB1",'1'&x"6AB2",'1'&x"6AB3",'1'&x"6AB4",'1'&x"6AB5",'1'&x"6AB6",'1'&x"6AB7",'1'&x"6AB8",'1'&x"6AB9",'1'&x"6ABA",'1'&x"6ABB",'1'&x"6ABC",'1'&x"6ABD",'1'&x"6ABE",'1'&x"6ABF",
+--'1'&x"6AC0",'1'&x"6AC1",'1'&x"6AC2",'1'&x"6AC3",'1'&x"6AC4",'1'&x"6AC5",'1'&x"6AC6",'1'&x"6AC7",'1'&x"6AC8",'1'&x"6AC9",'1'&x"6ACA",'1'&x"6ACB",'1'&x"6ACC",'1'&x"6ACD",'1'&x"6ACE",'1'&x"6ACF",
+--'1'&x"6AD0",'1'&x"6AD1",'1'&x"6AD2",'1'&x"6AD3",'1'&x"6AD4",'1'&x"6AD5",'1'&x"6AD6",'1'&x"6AD7",'1'&x"6AD8",'1'&x"6AD9",'1'&x"6ADA",'1'&x"6ADB",'1'&x"6ADC",'1'&x"6ADD",'1'&x"6ADE",'1'&x"6ADF",
+--'1'&x"6AE0",'1'&x"6AE1",'1'&x"6AE2",'1'&x"6AE3",'1'&x"6AE4",'1'&x"6AE5",'1'&x"6AE6",'1'&x"6AE7",'1'&x"6AE8",'1'&x"6AE9",'1'&x"6AEA",'1'&x"6AEB",'1'&x"6AEC",'1'&x"6AED",'1'&x"6AEE",'1'&x"6AEF",
+--'1'&x"6AF0",'1'&x"6AF1",'1'&x"6AF2",'1'&x"6AF3",'1'&x"6AF4",'1'&x"6AF5",'1'&x"6AF6",'1'&x"6AF7",'1'&x"6AF8",'1'&x"6AF9",'1'&x"6AFA",'1'&x"6AFB",'1'&x"6AFC",'1'&x"6AFD",'1'&x"6AFE",'1'&x"6AFF",
+--'1'&x"6B00",'1'&x"6B01",'1'&x"6B02",'1'&x"6B03",'1'&x"6B04",'1'&x"6B05",'1'&x"6B06",'1'&x"6B07",'1'&x"6B08",'1'&x"6B09",'1'&x"6B0A",'1'&x"6B0B",'1'&x"6B0C",'1'&x"6B0D",'1'&x"6B0E",'1'&x"6B0F",
+--'1'&x"6B10",'1'&x"6B11",'1'&x"6B12",'1'&x"6B13",'1'&x"6B14",'1'&x"6B15",'1'&x"6B16",'1'&x"6B17",'1'&x"6B18",'1'&x"6B19",'1'&x"6B1A",'1'&x"6B1B",'1'&x"6B1C",'1'&x"6B1D",'1'&x"6B1E",'1'&x"6B1F",
+--'1'&x"6B20",'1'&x"6B21",'1'&x"6B22",'1'&x"6B23",'1'&x"6B24",'1'&x"6B25",'1'&x"6B26",'1'&x"6B27",'1'&x"6B28",'1'&x"6B29",'1'&x"6B2A",'1'&x"6B2B",'1'&x"6B2C",'1'&x"6B2D",'1'&x"6B2E",'1'&x"6B2F",
+--'1'&x"6B30",'1'&x"6B31",'1'&x"6B32",'1'&x"6B33",'1'&x"6B34",'1'&x"6B35",'1'&x"6B36",'1'&x"6B37",'1'&x"6B38",'1'&x"6B39",'1'&x"6B3A",'1'&x"6B3B",'1'&x"6B3C",'1'&x"6B3D",'1'&x"6B3E",'1'&x"6B3F",
+--'1'&x"6B40",'1'&x"6B41",'1'&x"6B42",'1'&x"6B43",'1'&x"6B44",'1'&x"6B45",'1'&x"6B46",'1'&x"6B47",'1'&x"6B48",'1'&x"6B49",'1'&x"6B4A",'1'&x"6B4B",'1'&x"6B4C",'1'&x"6B4D",'1'&x"6B4E",'1'&x"6B4F",
+--'1'&x"6B50",'1'&x"6B51",'1'&x"6B52",'1'&x"6B53",'1'&x"6B54",'1'&x"6B55",'1'&x"6B56",'1'&x"6B57",'1'&x"6B58",'1'&x"6B59",'1'&x"6B5A",'1'&x"6B5B",'1'&x"6B5C",'1'&x"6B5D",'1'&x"6B5E",'1'&x"6B5F",
+--'1'&x"6B60",'1'&x"6B61",'1'&x"6B62",'1'&x"6B63",'1'&x"6B64",'1'&x"6B65",'1'&x"6B66",'1'&x"6B67",'1'&x"6B68",'1'&x"6B69",'1'&x"6B6A",'1'&x"6B6B",'1'&x"6B6C",'1'&x"6B6D",'1'&x"6B6E",'1'&x"6B6F",
+--'1'&x"6B70",'1'&x"6B71",'1'&x"6B72",'1'&x"6B73",'1'&x"6B74",'1'&x"6B75",'1'&x"6B76",'1'&x"6B77",'1'&x"6B78",'1'&x"6B79",'1'&x"6B7A",'1'&x"6B7B",'1'&x"6B7C",'1'&x"6B7D",'1'&x"6B7E",'1'&x"6B7F",
+--'1'&x"6B80",'1'&x"6B81",'1'&x"6B82",'1'&x"6B83",'1'&x"6B84",'1'&x"6B85",'1'&x"6B86",'1'&x"6B87",'1'&x"6B88",'1'&x"6B89",'1'&x"6B8A",'1'&x"6B8B",'1'&x"6B8C",'1'&x"6B8D",'1'&x"6B8E",'1'&x"6B8F",
+--'1'&x"6B90",'1'&x"6B91",'1'&x"6B92",'1'&x"6B93",'1'&x"6B94",'1'&x"6B95",'1'&x"6B96",'1'&x"6B97",'1'&x"6B98",'1'&x"6B99",'1'&x"6B9A",'1'&x"6B9B",'1'&x"6B9C",'1'&x"6B9D",'1'&x"6B9E",'1'&x"6B9F",
+--'1'&x"6BA0",'1'&x"6BA1",'1'&x"6BA2",'1'&x"6BA3",'1'&x"6BA4",'1'&x"6BA5",'1'&x"6BA6",'1'&x"6BA7",'1'&x"6BA8",'1'&x"6BA9",'1'&x"6BAA",'1'&x"6BAB",'1'&x"6BAC",'1'&x"6BAD",'1'&x"6BAE",'1'&x"6BAF",
+--'1'&x"6BB0",'1'&x"6BB1",'1'&x"6BB2",'1'&x"6BB3",'1'&x"6BB4",'1'&x"6BB5",'1'&x"6BB6",'1'&x"6BB7",'1'&x"6BB8",'1'&x"6BB9",'1'&x"6BBA",'1'&x"6BBB",'1'&x"6BBC",'1'&x"6BBD",'1'&x"6BBE",'1'&x"6BBF",
+--'1'&x"6BC0",'1'&x"6BC1",'1'&x"6BC2",'1'&x"6BC3",'1'&x"6BC4",'1'&x"6BC5",'1'&x"6BC6",'1'&x"6BC7",'1'&x"6BC8",'1'&x"6BC9",'1'&x"6BCA",'1'&x"6BCB",'1'&x"6BCC",'1'&x"6BCD",'1'&x"6BCE",'1'&x"6BCF",
+--'1'&x"6BD0",'1'&x"6BD1",'1'&x"6BD2",'1'&x"6BD3",'1'&x"6BD4",'1'&x"6BD5",'1'&x"6BD6",'1'&x"6BD7",'1'&x"6BD8",'1'&x"6BD9",'1'&x"6BDA",'1'&x"6BDB",'1'&x"6BDC",'1'&x"6BDD",'1'&x"6BDE",'1'&x"6BDF",
+--'1'&x"6BE0",'1'&x"6BE1",'1'&x"6BE2",'1'&x"6BE3",'1'&x"6BE4",'1'&x"6BE5",'1'&x"6BE6",'1'&x"6BE7",'1'&x"6BE8",'1'&x"6BE9",'1'&x"6BEA",'1'&x"6BEB",'1'&x"6BEC",'1'&x"6BED",'1'&x"6BEE",'1'&x"6BEF",
+--'1'&x"6BF0",'1'&x"6BF1",'1'&x"6BF2",'1'&x"6BF3",'1'&x"6BF4",'1'&x"6BF5",'1'&x"6BF6",'1'&x"6BF7",'1'&x"6BF8",'1'&x"6BF9",'1'&x"6BFA",'1'&x"6BFB",'1'&x"6BFC",'1'&x"6BFD",'1'&x"6BFE",'1'&x"6BFF",
+--'1'&x"6C00",'1'&x"6C01",'1'&x"6C02",'1'&x"6C03",'1'&x"6C04",'1'&x"6C05",'1'&x"6C06",'1'&x"6C07",'1'&x"6C08",'1'&x"6C09",'1'&x"6C0A",'1'&x"6C0B",'1'&x"6C0C",'1'&x"6C0D",'1'&x"6C0E",'1'&x"6C0F",
+--'1'&x"6C10",'1'&x"6C11",'1'&x"6C12",'1'&x"6C13",'1'&x"6C14",'1'&x"6C15",'1'&x"6C16",'1'&x"6C17",'1'&x"6C18",'1'&x"6C19",'1'&x"6C1A",'1'&x"6C1B",'1'&x"6C1C",'1'&x"6C1D",'1'&x"6C1E",'1'&x"6C1F",
+--'1'&x"6C20",'1'&x"6C21",'1'&x"6C22",'1'&x"6C23",'1'&x"6C24",'1'&x"6C25",'1'&x"6C26",'1'&x"6C27",'1'&x"6C28",'1'&x"6C29",'1'&x"6C2A",'1'&x"6C2B",'1'&x"6C2C",'1'&x"6C2D",'1'&x"6C2E",'1'&x"6C2F",
+--'1'&x"6C30",'1'&x"6C31",'1'&x"6C32",'1'&x"6C33",'1'&x"6C34",'1'&x"6C35",'1'&x"6C36",'1'&x"6C37",'1'&x"6C38",'1'&x"6C39",'1'&x"6C3A",'1'&x"6C3B",'1'&x"6C3C",'1'&x"6C3D",'1'&x"6C3E",'1'&x"6C3F",
+--'1'&x"6C40",'1'&x"6C41",'1'&x"6C42",'1'&x"6C43",'1'&x"6C44",'1'&x"6C45",'1'&x"6C46",'1'&x"6C47",'1'&x"6C48",'1'&x"6C49",'1'&x"6C4A",'1'&x"6C4B",'1'&x"6C4C",'1'&x"6C4D",'1'&x"6C4E",'1'&x"6C4F",
+--'1'&x"6C50",'1'&x"6C51",'1'&x"6C52",'1'&x"6C53",'1'&x"6C54",'1'&x"6C55",'1'&x"6C56",'1'&x"6C57",'1'&x"6C58",'1'&x"6C59",'1'&x"6C5A",'1'&x"6C5B",'1'&x"6C5C",'1'&x"6C5D",'1'&x"6C5E",'1'&x"6C5F",
+--'1'&x"6C60",'1'&x"6C61",'1'&x"6C62",'1'&x"6C63",'1'&x"6C64",'1'&x"6C65",'1'&x"6C66",'1'&x"6C67",'1'&x"6C68",'1'&x"6C69",'1'&x"6C6A",'1'&x"6C6B",'1'&x"6C6C",'1'&x"6C6D",'1'&x"6C6E",'1'&x"6C6F",
+--'1'&x"6C70",'1'&x"6C71",'1'&x"6C72",'1'&x"6C73",'1'&x"6C74",'1'&x"6C75",'1'&x"6C76",'1'&x"6C77",'1'&x"6C78",'1'&x"6C79",'1'&x"6C7A",'1'&x"6C7B",'1'&x"6C7C",'1'&x"6C7D",'1'&x"6C7E",'1'&x"6C7F",
+--'1'&x"6C80",'1'&x"6C81",'1'&x"6C82",'1'&x"6C83",'1'&x"6C84",'1'&x"6C85",'1'&x"6C86",'1'&x"6C87",'1'&x"6C88",'1'&x"6C89",'1'&x"6C8A",'1'&x"6C8B",'1'&x"6C8C",'1'&x"6C8D",'1'&x"6C8E",'1'&x"6C8F",
+--'1'&x"6C90",'1'&x"6C91",'1'&x"6C92",'1'&x"6C93",'1'&x"6C94",'1'&x"6C95",'1'&x"6C96",'1'&x"6C97",'1'&x"6C98",'1'&x"6C99",'1'&x"6C9A",'1'&x"6C9B",'1'&x"6C9C",'1'&x"6C9D",'1'&x"6C9E",'1'&x"6C9F",
+--'1'&x"6CA0",'1'&x"6CA1",'1'&x"6CA2",'1'&x"6CA3",'1'&x"6CA4",'1'&x"6CA5",'1'&x"6CA6",'1'&x"6CA7",'1'&x"6CA8",'1'&x"6CA9",'1'&x"6CAA",'1'&x"6CAB",'1'&x"6CAC",'1'&x"6CAD",'1'&x"6CAE",'1'&x"6CAF",
+--'1'&x"6CB0",'1'&x"6CB1",'1'&x"6CB2",'1'&x"6CB3",'1'&x"6CB4",'1'&x"6CB5",'1'&x"6CB6",'1'&x"6CB7",'1'&x"6CB8",'1'&x"6CB9",'1'&x"6CBA",'1'&x"6CBB",'1'&x"6CBC",'1'&x"6CBD",'1'&x"6CBE",'1'&x"6CBF",
+--'1'&x"6CC0",'1'&x"6CC1",'1'&x"6CC2",'1'&x"6CC3",'1'&x"6CC4",'1'&x"6CC5",'1'&x"6CC6",'1'&x"6CC7",'1'&x"6CC8",'1'&x"6CC9",'1'&x"6CCA",'1'&x"6CCB",'1'&x"6CCC",'1'&x"6CCD",'1'&x"6CCE",'1'&x"6CCF",
+--'1'&x"6CD0",'1'&x"6CD1",'1'&x"6CD2",'1'&x"6CD3",'1'&x"6CD4",'1'&x"6CD5",'1'&x"6CD6",'1'&x"6CD7",'1'&x"6CD8",'1'&x"6CD9",'1'&x"6CDA",'1'&x"6CDB",'1'&x"6CDC",'1'&x"6CDD",'1'&x"6CDE",'1'&x"6CDF",
+--'1'&x"6CE0",'1'&x"6CE1",'1'&x"6CE2",'1'&x"6CE3",'1'&x"6CE4",'1'&x"6CE5",'1'&x"6CE6",'1'&x"6CE7",'1'&x"6CE8",'1'&x"6CE9",'1'&x"6CEA",'1'&x"6CEB",'1'&x"6CEC",'1'&x"6CED",'1'&x"6CEE",'1'&x"6CEF",
+--'1'&x"6CF0",'1'&x"6CF1",'1'&x"6CF2",'1'&x"6CF3",'1'&x"6CF4",'1'&x"6CF5",'1'&x"6CF6",'1'&x"6CF7",'1'&x"6CF8",'1'&x"6CF9",'1'&x"6CFA",'1'&x"6CFB",'1'&x"6CFC",'1'&x"6CFD",'1'&x"6CFE",'1'&x"6CFF",
+--'1'&x"6D00",'1'&x"6D01",'1'&x"6D02",'1'&x"6D03",'1'&x"6D04",'1'&x"6D05",'1'&x"6D06",'1'&x"6D07",'1'&x"6D08",'1'&x"6D09",'1'&x"6D0A",'1'&x"6D0B",'1'&x"6D0C",'1'&x"6D0D",'1'&x"6D0E",'1'&x"6D0F",
+--'1'&x"6D10",'1'&x"6D11",'1'&x"6D12",'1'&x"6D13",'1'&x"6D14",'1'&x"6D15",'1'&x"6D16",'1'&x"6D17",'1'&x"6D18",'1'&x"6D19",'1'&x"6D1A",'1'&x"6D1B",'1'&x"6D1C",'1'&x"6D1D",'1'&x"6D1E",'1'&x"6D1F",
+--'1'&x"6D20",'1'&x"6D21",'1'&x"6D22",'1'&x"6D23",'1'&x"6D24",'1'&x"6D25",'1'&x"6D26",'1'&x"6D27",'1'&x"6D28",'1'&x"6D29",'1'&x"6D2A",'1'&x"6D2B",'1'&x"6D2C",'1'&x"6D2D",'1'&x"6D2E",'1'&x"6D2F",
+--'1'&x"6D30",'1'&x"6D31",'1'&x"6D32",'1'&x"6D33",'1'&x"6D34",'1'&x"6D35",'1'&x"6D36",'1'&x"6D37",'1'&x"6D38",'1'&x"6D39",'1'&x"6D3A",'1'&x"6D3B",'1'&x"6D3C",'1'&x"6D3D",'1'&x"6D3E",'1'&x"6D3F",
+--'1'&x"6D40",'1'&x"6D41",'1'&x"6D42",'1'&x"6D43",'1'&x"6D44",'1'&x"6D45",'1'&x"6D46",'1'&x"6D47",'1'&x"6D48",'1'&x"6D49",'1'&x"6D4A",'1'&x"6D4B",'1'&x"6D4C",'1'&x"6D4D",'1'&x"6D4E",'1'&x"6D4F",
+--'1'&x"6D50",'1'&x"6D51",'1'&x"6D52",'1'&x"6D53",'1'&x"6D54",'1'&x"6D55",'1'&x"6D56",'1'&x"6D57",'1'&x"6D58",'1'&x"6D59",'1'&x"6D5A",'1'&x"6D5B",'1'&x"6D5C",'1'&x"6D5D",'1'&x"6D5E",'1'&x"6D5F",
+--'1'&x"6D60",'1'&x"6D61",'1'&x"6D62",'1'&x"6D63",'1'&x"6D64",'1'&x"6D65",'1'&x"6D66",'1'&x"6D67",'1'&x"6D68",'1'&x"6D69",'1'&x"6D6A",'1'&x"6D6B",'1'&x"6D6C",'1'&x"6D6D",'1'&x"6D6E",'1'&x"6D6F",
+--'1'&x"6D70",'1'&x"6D71",'1'&x"6D72",'1'&x"6D73",'1'&x"6D74",'1'&x"6D75",'1'&x"6D76",'1'&x"6D77",'1'&x"6D78",'1'&x"6D79",'1'&x"6D7A",'1'&x"6D7B",'1'&x"6D7C",'1'&x"6D7D",'1'&x"6D7E",'1'&x"6D7F",
+--'1'&x"6D80",'1'&x"6D81",'1'&x"6D82",'1'&x"6D83",'1'&x"6D84",'1'&x"6D85",'1'&x"6D86",'1'&x"6D87",'1'&x"6D88",'1'&x"6D89",'1'&x"6D8A",'1'&x"6D8B",'1'&x"6D8C",'1'&x"6D8D",'1'&x"6D8E",'1'&x"6D8F",
+--'1'&x"6D90",'1'&x"6D91",'1'&x"6D92",'1'&x"6D93",'1'&x"6D94",'1'&x"6D95",'1'&x"6D96",'1'&x"6D97",'1'&x"6D98",'1'&x"6D99",'1'&x"6D9A",'1'&x"6D9B",'1'&x"6D9C",'1'&x"6D9D",'1'&x"6D9E",'1'&x"6D9F",
+--'1'&x"6DA0",'1'&x"6DA1",'1'&x"6DA2",'1'&x"6DA3",'1'&x"6DA4",'1'&x"6DA5",'1'&x"6DA6",'1'&x"6DA7",'1'&x"6DA8",'1'&x"6DA9",'1'&x"6DAA",'1'&x"6DAB",'1'&x"6DAC",'1'&x"6DAD",'1'&x"6DAE",'1'&x"6DAF",
+--'1'&x"6DB0",'1'&x"6DB1",'1'&x"6DB2",'1'&x"6DB3",'1'&x"6DB4",'1'&x"6DB5",'1'&x"6DB6",'1'&x"6DB7",'1'&x"6DB8",'1'&x"6DB9",'1'&x"6DBA",'1'&x"6DBB",'1'&x"6DBC",'1'&x"6DBD",'1'&x"6DBE",'1'&x"6DBF",
+--'1'&x"6DC0",'1'&x"6DC1",'1'&x"6DC2",'1'&x"6DC3",'1'&x"6DC4",'1'&x"6DC5",'1'&x"6DC6",'1'&x"6DC7",'1'&x"6DC8",'1'&x"6DC9",'1'&x"6DCA",'1'&x"6DCB",'1'&x"6DCC",'1'&x"6DCD",'1'&x"6DCE",'1'&x"6DCF",
+--'1'&x"6DD0",'1'&x"6DD1",'1'&x"6DD2",'1'&x"6DD3",'1'&x"6DD4",'1'&x"6DD5",'1'&x"6DD6",'1'&x"6DD7",'1'&x"6DD8",'1'&x"6DD9",'1'&x"6DDA",'1'&x"6DDB",'1'&x"6DDC",'1'&x"6DDD",'1'&x"6DDE",'1'&x"6DDF",
+--'1'&x"6DE0",'1'&x"6DE1",'1'&x"6DE2",'1'&x"6DE3",'1'&x"6DE4",'1'&x"6DE5",'1'&x"6DE6",'1'&x"6DE7",'1'&x"6DE8",'1'&x"6DE9",'1'&x"6DEA",'1'&x"6DEB",'1'&x"6DEC",'1'&x"6DED",'1'&x"6DEE",'1'&x"6DEF",
+--'1'&x"6DF0",'1'&x"6DF1",'1'&x"6DF2",'1'&x"6DF3",'1'&x"6DF4",'1'&x"6DF5",'1'&x"6DF6",'1'&x"6DF7",'1'&x"6DF8",'1'&x"6DF9",'1'&x"6DFA",'1'&x"6DFB",'1'&x"6DFC",'1'&x"6DFD",'1'&x"6DFE",'1'&x"6DFF",
+--'1'&x"6E00",'1'&x"6E01",'1'&x"6E02",'1'&x"6E03",'1'&x"6E04",'1'&x"6E05",'1'&x"6E06",'1'&x"6E07",'1'&x"6E08",'1'&x"6E09",'1'&x"6E0A",'1'&x"6E0B",'1'&x"6E0C",'1'&x"6E0D",'1'&x"6E0E",'1'&x"6E0F",
+--'1'&x"6E10",'1'&x"6E11",'1'&x"6E12",'1'&x"6E13",'1'&x"6E14",'1'&x"6E15",'1'&x"6E16",'1'&x"6E17",'1'&x"6E18",'1'&x"6E19",'1'&x"6E1A",'1'&x"6E1B",'1'&x"6E1C",'1'&x"6E1D",'1'&x"6E1E",'1'&x"6E1F",
+--'1'&x"6E20",'1'&x"6E21",'1'&x"6E22",'1'&x"6E23",'1'&x"6E24",'1'&x"6E25",'1'&x"6E26",'1'&x"6E27",'1'&x"6E28",'1'&x"6E29",'1'&x"6E2A",'1'&x"6E2B",'1'&x"6E2C",'1'&x"6E2D",'1'&x"6E2E",'1'&x"6E2F",
+--'1'&x"6E30",'1'&x"6E31",'1'&x"6E32",'1'&x"6E33",'1'&x"6E34",'1'&x"6E35",'1'&x"6E36",'1'&x"6E37",'1'&x"6E38",'1'&x"6E39",'1'&x"6E3A",'1'&x"6E3B",'1'&x"6E3C",'1'&x"6E3D",'1'&x"6E3E",'1'&x"6E3F",
+--'1'&x"6E40",'1'&x"6E41",'1'&x"6E42",'1'&x"6E43",'1'&x"6E44",'1'&x"6E45",'1'&x"6E46",'1'&x"6E47",'1'&x"6E48",'1'&x"6E49",'1'&x"6E4A",'1'&x"6E4B",'1'&x"6E4C",'1'&x"6E4D",'1'&x"6E4E",'1'&x"6E4F",
+--'1'&x"6E50",'1'&x"6E51",'1'&x"6E52",'1'&x"6E53",'1'&x"6E54",'1'&x"6E55",'1'&x"6E56",'1'&x"6E57",'1'&x"6E58",'1'&x"6E59",'1'&x"6E5A",'1'&x"6E5B",'1'&x"6E5C",'1'&x"6E5D",'1'&x"6E5E",'1'&x"6E5F",
+--'1'&x"6E60",'1'&x"6E61",'1'&x"6E62",'1'&x"6E63",'1'&x"6E64",'1'&x"6E65",'1'&x"6E66",'1'&x"6E67",'1'&x"6E68",'1'&x"6E69",'1'&x"6E6A",'1'&x"6E6B",'1'&x"6E6C",'1'&x"6E6D",'1'&x"6E6E",'1'&x"6E6F",
+--'1'&x"6E70",'1'&x"6E71",'1'&x"6E72",'1'&x"6E73",'1'&x"6E74",'1'&x"6E75",'1'&x"6E76",'1'&x"6E77",'1'&x"6E78",'1'&x"6E79",'1'&x"6E7A",'1'&x"6E7B",'1'&x"6E7C",'1'&x"6E7D",'1'&x"6E7E",'1'&x"6E7F",
+--'1'&x"6E80",'1'&x"6E81",'1'&x"6E82",'1'&x"6E83",'1'&x"6E84",'1'&x"6E85",'1'&x"6E86",'1'&x"6E87",'1'&x"6E88",'1'&x"6E89",'1'&x"6E8A",'1'&x"6E8B",'1'&x"6E8C",'1'&x"6E8D",'1'&x"6E8E",'1'&x"6E8F",
+--'1'&x"6E90",'1'&x"6E91",'1'&x"6E92",'1'&x"6E93",'1'&x"6E94",'1'&x"6E95",'1'&x"6E96",'1'&x"6E97",'1'&x"6E98",'1'&x"6E99",'1'&x"6E9A",'1'&x"6E9B",'1'&x"6E9C",'1'&x"6E9D",'1'&x"6E9E",'1'&x"6E9F",
+--'1'&x"6EA0",'1'&x"6EA1",'1'&x"6EA2",'1'&x"6EA3",'1'&x"6EA4",'1'&x"6EA5",'1'&x"6EA6",'1'&x"6EA7",'1'&x"6EA8",'1'&x"6EA9",'1'&x"6EAA",'1'&x"6EAB",'1'&x"6EAC",'1'&x"6EAD",'1'&x"6EAE",'1'&x"6EAF",
+--'1'&x"6EB0",'1'&x"6EB1",'1'&x"6EB2",'1'&x"6EB3",'1'&x"6EB4",'1'&x"6EB5",'1'&x"6EB6",'1'&x"6EB7",'1'&x"6EB8",'1'&x"6EB9",'1'&x"6EBA",'1'&x"6EBB",'1'&x"6EBC",'1'&x"6EBD",'1'&x"6EBE",'1'&x"6EBF",
+--'1'&x"6EC0",'1'&x"6EC1",'1'&x"6EC2",'1'&x"6EC3",'1'&x"6EC4",'1'&x"6EC5",'1'&x"6EC6",'1'&x"6EC7",'1'&x"6EC8",'1'&x"6EC9",'1'&x"6ECA",'1'&x"6ECB",'1'&x"6ECC",'1'&x"6ECD",'1'&x"6ECE",'1'&x"6ECF",
+--'1'&x"6ED0",'1'&x"6ED1",'1'&x"6ED2",'1'&x"6ED3",'1'&x"6ED4",'1'&x"6ED5",'1'&x"6ED6",'1'&x"6ED7",'1'&x"6ED8",'1'&x"6ED9",'1'&x"6EDA",'1'&x"6EDB",'1'&x"6EDC",'1'&x"6EDD",'1'&x"6EDE",'1'&x"6EDF",
+--'1'&x"6EE0",'1'&x"6EE1",'1'&x"6EE2",'1'&x"6EE3",'1'&x"6EE4",'1'&x"6EE5",'1'&x"6EE6",'1'&x"6EE7",'1'&x"6EE8",'1'&x"6EE9",'1'&x"6EEA",'1'&x"6EEB",'1'&x"6EEC",'1'&x"6EED",'1'&x"6EEE",'1'&x"6EEF",
+--'1'&x"6EF0",'1'&x"6EF1",'1'&x"6EF2",'1'&x"6EF3",'1'&x"6EF4",'1'&x"6EF5",'1'&x"6EF6",'1'&x"6EF7",'1'&x"6EF8",'1'&x"6EF9",'1'&x"6EFA",'1'&x"6EFB",'1'&x"6EFC",'1'&x"6EFD",'1'&x"6EFE",'1'&x"6EFF",
+--'1'&x"6F00",'1'&x"6F01",'1'&x"6F02",'1'&x"6F03",'1'&x"6F04",'1'&x"6F05",'1'&x"6F06",'1'&x"6F07",'1'&x"6F08",'1'&x"6F09",'1'&x"6F0A",'1'&x"6F0B",'1'&x"6F0C",'1'&x"6F0D",'1'&x"6F0E",'1'&x"6F0F",
+--'1'&x"6F10",'1'&x"6F11",'1'&x"6F12",'1'&x"6F13",'1'&x"6F14",'1'&x"6F15",'1'&x"6F16",'1'&x"6F17",'1'&x"6F18",'1'&x"6F19",'1'&x"6F1A",'1'&x"6F1B",'1'&x"6F1C",'1'&x"6F1D",'1'&x"6F1E",'1'&x"6F1F",
+--'1'&x"6F20",'1'&x"6F21",'1'&x"6F22",'1'&x"6F23",'1'&x"6F24",'1'&x"6F25",'1'&x"6F26",'1'&x"6F27",'1'&x"6F28",'1'&x"6F29",'1'&x"6F2A",'1'&x"6F2B",'1'&x"6F2C",'1'&x"6F2D",'1'&x"6F2E",'1'&x"6F2F",
+--'1'&x"6F30",'1'&x"6F31",'1'&x"6F32",'1'&x"6F33",'1'&x"6F34",'1'&x"6F35",'1'&x"6F36",'1'&x"6F37",'1'&x"6F38",'1'&x"6F39",'1'&x"6F3A",'1'&x"6F3B",'1'&x"6F3C",'1'&x"6F3D",'1'&x"6F3E",'1'&x"6F3F",
+--'1'&x"6F40",'1'&x"6F41",'1'&x"6F42",'1'&x"6F43",'1'&x"6F44",'1'&x"6F45",'1'&x"6F46",'1'&x"6F47",'1'&x"6F48",'1'&x"6F49",'1'&x"6F4A",'1'&x"6F4B",'1'&x"6F4C",'1'&x"6F4D",'1'&x"6F4E",'1'&x"6F4F",
+--'1'&x"6F50",'1'&x"6F51",'1'&x"6F52",'1'&x"6F53",'1'&x"6F54",'1'&x"6F55",'1'&x"6F56",'1'&x"6F57",'1'&x"6F58",'1'&x"6F59",'1'&x"6F5A",'1'&x"6F5B",'1'&x"6F5C",'1'&x"6F5D",'1'&x"6F5E",'1'&x"6F5F",
+--'1'&x"6F60",'1'&x"6F61",'1'&x"6F62",'1'&x"6F63",'1'&x"6F64",'1'&x"6F65",'1'&x"6F66",'1'&x"6F67",'1'&x"6F68",'1'&x"6F69",'1'&x"6F6A",'1'&x"6F6B",'1'&x"6F6C",'1'&x"6F6D",'1'&x"6F6E",'1'&x"6F6F",
+--'1'&x"6F70",'1'&x"6F71",'1'&x"6F72",'1'&x"6F73",'1'&x"6F74",'1'&x"6F75",'1'&x"6F76",'1'&x"6F77",'1'&x"6F78",'1'&x"6F79",'1'&x"6F7A",'1'&x"6F7B",'1'&x"6F7C",'1'&x"6F7D",'1'&x"6F7E",'1'&x"6F7F",
+--'1'&x"6F80",'1'&x"6F81",'1'&x"6F82",'1'&x"6F83",'1'&x"6F84",'1'&x"6F85",'1'&x"6F86",'1'&x"6F87",'1'&x"6F88",'1'&x"6F89",'1'&x"6F8A",'1'&x"6F8B",'1'&x"6F8C",'1'&x"6F8D",'1'&x"6F8E",'1'&x"6F8F",
+--'1'&x"6F90",'1'&x"6F91",'1'&x"6F92",'1'&x"6F93",'1'&x"6F94",'1'&x"6F95",'1'&x"6F96",'1'&x"6F97",'1'&x"6F98",'1'&x"6F99",'1'&x"6F9A",'1'&x"6F9B",'1'&x"6F9C",'1'&x"6F9D",'1'&x"6F9E",'1'&x"6F9F",
+--'1'&x"6FA0",'1'&x"6FA1",'1'&x"6FA2",'1'&x"6FA3",'1'&x"6FA4",'1'&x"6FA5",'1'&x"6FA6",'1'&x"6FA7",'1'&x"6FA8",'1'&x"6FA9",'1'&x"6FAA",'1'&x"6FAB",'1'&x"6FAC",'1'&x"6FAD",'1'&x"6FAE",'1'&x"6FAF",
+--'1'&x"6FB0",'1'&x"6FB1",'1'&x"6FB2",'1'&x"6FB3",'1'&x"6FB4",'1'&x"6FB5",'1'&x"6FB6",'1'&x"6FB7",'1'&x"6FB8",'1'&x"6FB9",'1'&x"6FBA",'1'&x"6FBB",'1'&x"6FBC",'1'&x"6FBD",'1'&x"6FBE",'1'&x"6FBF",
+--'1'&x"6FC0",'1'&x"6FC1",'1'&x"6FC2",'1'&x"6FC3",'1'&x"6FC4",'1'&x"6FC5",'1'&x"6FC6",'1'&x"6FC7",'1'&x"6FC8",'1'&x"6FC9",'1'&x"6FCA",'1'&x"6FCB",'1'&x"6FCC",'1'&x"6FCD",'1'&x"6FCE",'1'&x"6FCF",
+--'1'&x"6FD0",'1'&x"6FD1",'1'&x"6FD2",'1'&x"6FD3",'1'&x"6FD4",'1'&x"6FD5",'1'&x"6FD6",'1'&x"6FD7",'1'&x"6FD8",'1'&x"6FD9",'1'&x"6FDA",'1'&x"6FDB",'1'&x"6FDC",'1'&x"6FDD",'1'&x"6FDE",'1'&x"6FDF",
+--'1'&x"6FE0",'1'&x"6FE1",'1'&x"6FE2",'1'&x"6FE3",'1'&x"6FE4",'1'&x"6FE5",'1'&x"6FE6",'1'&x"6FE7",'1'&x"6FE8",'1'&x"6FE9",'1'&x"6FEA",'1'&x"6FEB",'1'&x"6FEC",'1'&x"6FED",'1'&x"6FEE",'1'&x"6FEF",
+--'1'&x"6FF0",'1'&x"6FF1",'1'&x"6FF2",'1'&x"6FF3",'1'&x"6FF4",'1'&x"6FF5",'1'&x"6FF6",'1'&x"6FF7",'1'&x"6FF8",'1'&x"6FF9",'1'&x"6FFA",'1'&x"6FFB",'1'&x"6FFC",'1'&x"6FFD",'1'&x"6FFE",'1'&x"6FFF",
+--'1'&x"7000",'1'&x"7001",'1'&x"7002",'1'&x"7003",'1'&x"7004",'1'&x"7005",'1'&x"7006",'1'&x"7007",'1'&x"7008",'1'&x"7009",'1'&x"700A",'1'&x"700B",'1'&x"700C",'1'&x"700D",'1'&x"700E",'1'&x"700F",
+--'1'&x"7010",'1'&x"7011",'1'&x"7012",'1'&x"7013",'1'&x"7014",'1'&x"7015",'1'&x"7016",'1'&x"7017",'1'&x"7018",'1'&x"7019",'1'&x"701A",'1'&x"701B",'1'&x"701C",'1'&x"701D",'1'&x"701E",'1'&x"701F",
+--'1'&x"7020",'1'&x"7021",'1'&x"7022",'1'&x"7023",'1'&x"7024",'1'&x"7025",'1'&x"7026",'1'&x"7027",'1'&x"7028",'1'&x"7029",'1'&x"702A",'1'&x"702B",'1'&x"702C",'1'&x"702D",'1'&x"702E",'1'&x"702F",
+--'1'&x"7030",'1'&x"7031",'1'&x"7032",'1'&x"7033",'1'&x"7034",'1'&x"7035",'1'&x"7036",'1'&x"7037",'1'&x"7038",'1'&x"7039",'1'&x"703A",'1'&x"703B",'1'&x"703C",'1'&x"703D",'1'&x"703E",'1'&x"703F",
+--'1'&x"7040",'1'&x"7041",'1'&x"7042",'1'&x"7043",'1'&x"7044",'1'&x"7045",'1'&x"7046",'1'&x"7047",'1'&x"7048",'1'&x"7049",'1'&x"704A",'1'&x"704B",'1'&x"704C",'1'&x"704D",'1'&x"704E",'1'&x"704F",
+--'1'&x"7050",'1'&x"7051",'1'&x"7052",'1'&x"7053",'1'&x"7054",'1'&x"7055",'1'&x"7056",'1'&x"7057",'1'&x"7058",'1'&x"7059",'1'&x"705A",'1'&x"705B",'1'&x"705C",'1'&x"705D",'1'&x"705E",'1'&x"705F",
+--'1'&x"7060",'1'&x"7061",'1'&x"7062",'1'&x"7063",'1'&x"7064",'1'&x"7065",'1'&x"7066",'1'&x"7067",'1'&x"7068",'1'&x"7069",'1'&x"706A",'1'&x"706B",'1'&x"706C",'1'&x"706D",'1'&x"706E",'1'&x"706F",
+--'1'&x"7070",'1'&x"7071",'1'&x"7072",'1'&x"7073",'1'&x"7074",'1'&x"7075",'1'&x"7076",'1'&x"7077",'1'&x"7078",'1'&x"7079",'1'&x"707A",'1'&x"707B",'1'&x"707C",'1'&x"707D",'1'&x"707E",'1'&x"707F",
+--'1'&x"7080",'1'&x"7081",'1'&x"7082",'1'&x"7083",'1'&x"7084",'1'&x"7085",'1'&x"7086",'1'&x"7087",'1'&x"7088",'1'&x"7089",'1'&x"708A",'1'&x"708B",'1'&x"708C",'1'&x"708D",'1'&x"708E",'1'&x"708F",
+--'1'&x"7090",'1'&x"7091",'1'&x"7092",'1'&x"7093",'1'&x"7094",'1'&x"7095",'1'&x"7096",'1'&x"7097",'1'&x"7098",'1'&x"7099",'1'&x"709A",'1'&x"709B",'1'&x"709C",'1'&x"709D",'1'&x"709E",'1'&x"709F",
+--'1'&x"70A0",'1'&x"70A1",'1'&x"70A2",'1'&x"70A3",'1'&x"70A4",'1'&x"70A5",'1'&x"70A6",'1'&x"70A7",'1'&x"70A8",'1'&x"70A9",'1'&x"70AA",'1'&x"70AB",'1'&x"70AC",'1'&x"70AD",'1'&x"70AE",'1'&x"70AF",
+--'1'&x"70B0",'1'&x"70B1",'1'&x"70B2",'1'&x"70B3",'1'&x"70B4",'1'&x"70B5",'1'&x"70B6",'1'&x"70B7",'1'&x"70B8",'1'&x"70B9",'1'&x"70BA",'1'&x"70BB",'1'&x"70BC",'1'&x"70BD",'1'&x"70BE",'1'&x"70BF",
+--'1'&x"70C0",'1'&x"70C1",'1'&x"70C2",'1'&x"70C3",'1'&x"70C4",'1'&x"70C5",'1'&x"70C6",'1'&x"70C7",'1'&x"70C8",'1'&x"70C9",'1'&x"70CA",'1'&x"70CB",'1'&x"70CC",'1'&x"70CD",'1'&x"70CE",'1'&x"70CF",
+--'1'&x"70D0",'1'&x"70D1",'1'&x"70D2",'1'&x"70D3",'1'&x"70D4",'1'&x"70D5",'1'&x"70D6",'1'&x"70D7",'1'&x"70D8",'1'&x"70D9",'1'&x"70DA",'1'&x"70DB",'1'&x"70DC",'1'&x"70DD",'1'&x"70DE",'1'&x"70DF",
+--'1'&x"70E0",'1'&x"70E1",'1'&x"70E2",'1'&x"70E3",'1'&x"70E4",'1'&x"70E5",'1'&x"70E6",'1'&x"70E7",'1'&x"70E8",'1'&x"70E9",'1'&x"70EA",'1'&x"70EB",'1'&x"70EC",'1'&x"70ED",'1'&x"70EE",'1'&x"70EF",
+--'1'&x"70F0",'1'&x"70F1",'1'&x"70F2",'1'&x"70F3",'1'&x"70F4",'1'&x"70F5",'1'&x"70F6",'1'&x"70F7",'1'&x"70F8",'1'&x"70F9",'1'&x"70FA",'1'&x"70FB",'1'&x"70FC",'1'&x"70FD",'1'&x"70FE",'1'&x"70FF",
+--'1'&x"7100",'1'&x"7101",'1'&x"7102",'1'&x"7103",'1'&x"7104",'1'&x"7105",'1'&x"7106",'1'&x"7107",'1'&x"7108",'1'&x"7109",'1'&x"710A",'1'&x"710B",'1'&x"710C",'1'&x"710D",'1'&x"710E",'1'&x"710F",
+--'1'&x"7110",'1'&x"7111",'1'&x"7112",'1'&x"7113",'1'&x"7114",'1'&x"7115",'1'&x"7116",'1'&x"7117",'1'&x"7118",'1'&x"7119",'1'&x"711A",'1'&x"711B",'1'&x"711C",'1'&x"711D",'1'&x"711E",'1'&x"711F",
+--'1'&x"7120",'1'&x"7121",'1'&x"7122",'1'&x"7123",'1'&x"7124",'1'&x"7125",'1'&x"7126",'1'&x"7127",'1'&x"7128",'1'&x"7129",'1'&x"712A",'1'&x"712B",'1'&x"712C",'1'&x"712D",'1'&x"712E",'1'&x"712F",
+--'1'&x"7130",'1'&x"7131",'1'&x"7132",'1'&x"7133",'1'&x"7134",'1'&x"7135",'1'&x"7136",'1'&x"7137",'1'&x"7138",'1'&x"7139",'1'&x"713A",'1'&x"713B",'1'&x"713C",'1'&x"713D",'1'&x"713E",'1'&x"713F",
+--'1'&x"7140",'1'&x"7141",'1'&x"7142",'1'&x"7143",'1'&x"7144",'1'&x"7145",'1'&x"7146",'1'&x"7147",'1'&x"7148",'1'&x"7149",'1'&x"714A",'1'&x"714B",'1'&x"714C",'1'&x"714D",'1'&x"714E",'1'&x"714F",
+--'1'&x"7150",'1'&x"7151",'1'&x"7152",'1'&x"7153",'1'&x"7154",'1'&x"7155",'1'&x"7156",'1'&x"7157",'1'&x"7158",'1'&x"7159",'1'&x"715A",'1'&x"715B",'1'&x"715C",'1'&x"715D",'1'&x"715E",'1'&x"715F",
+--'1'&x"7160",'1'&x"7161",'1'&x"7162",'1'&x"7163",'1'&x"7164",'1'&x"7165",'1'&x"7166",'1'&x"7167",'1'&x"7168",'1'&x"7169",'1'&x"716A",'1'&x"716B",'1'&x"716C",'1'&x"716D",'1'&x"716E",'1'&x"716F",
+--'1'&x"7170",'1'&x"7171",'1'&x"7172",'1'&x"7173",'1'&x"7174",'1'&x"7175",'1'&x"7176",'1'&x"7177",'1'&x"7178",'1'&x"7179",'1'&x"717A",'1'&x"717B",'1'&x"717C",'1'&x"717D",'1'&x"717E",'1'&x"717F",
+--'1'&x"7180",'1'&x"7181",'1'&x"7182",'1'&x"7183",'1'&x"7184",'1'&x"7185",'1'&x"7186",'1'&x"7187",'1'&x"7188",'1'&x"7189",'1'&x"718A",'1'&x"718B",'1'&x"718C",'1'&x"718D",'1'&x"718E",'1'&x"718F",
+--'1'&x"7190",'1'&x"7191",'1'&x"7192",'1'&x"7193",'1'&x"7194",'1'&x"7195",'1'&x"7196",'1'&x"7197",'1'&x"7198",'1'&x"7199",'1'&x"719A",'1'&x"719B",'1'&x"719C",'1'&x"719D",'1'&x"719E",'1'&x"719F",
+--'1'&x"71A0",'1'&x"71A1",'1'&x"71A2",'1'&x"71A3",'1'&x"71A4",'1'&x"71A5",'1'&x"71A6",'1'&x"71A7",'1'&x"71A8",'1'&x"71A9",'1'&x"71AA",'1'&x"71AB",'1'&x"71AC",'1'&x"71AD",'1'&x"71AE",'1'&x"71AF",
+--'1'&x"71B0",'1'&x"71B1",'1'&x"71B2",'1'&x"71B3",'1'&x"71B4",'1'&x"71B5",'1'&x"71B6",'1'&x"71B7",'1'&x"71B8",'1'&x"71B9",'1'&x"71BA",'1'&x"71BB",'1'&x"71BC",'1'&x"71BD",'1'&x"71BE",'1'&x"71BF",
+--'1'&x"71C0",'1'&x"71C1",'1'&x"71C2",'1'&x"71C3",'1'&x"71C4",'1'&x"71C5",'1'&x"71C6",'1'&x"71C7",'1'&x"71C8",'1'&x"71C9",'1'&x"71CA",'1'&x"71CB",'1'&x"71CC",'1'&x"71CD",'1'&x"71CE",'1'&x"71CF",
+--'1'&x"71D0",'1'&x"71D1",'1'&x"71D2",'1'&x"71D3",'1'&x"71D4",'1'&x"71D5",'1'&x"71D6",'1'&x"71D7",'1'&x"71D8",'1'&x"71D9",'1'&x"71DA",'1'&x"71DB",'1'&x"71DC",'1'&x"71DD",'1'&x"71DE",'1'&x"71DF",
+--'1'&x"71E0",'1'&x"71E1",'1'&x"71E2",'1'&x"71E3",'1'&x"71E4",'1'&x"71E5",'1'&x"71E6",'1'&x"71E7",'1'&x"71E8",'1'&x"71E9",'1'&x"71EA",'1'&x"71EB",'1'&x"71EC",'1'&x"71ED",'1'&x"71EE",'1'&x"71EF",
+--'1'&x"71F0",'1'&x"71F1",'1'&x"71F2",'1'&x"71F3",'1'&x"71F4",'1'&x"71F5",'1'&x"71F6",'1'&x"71F7",'1'&x"71F8",'1'&x"71F9",'1'&x"71FA",'1'&x"71FB",'1'&x"71FC",'1'&x"71FD",'1'&x"71FE",'1'&x"71FF",
+--'1'&x"7200",'1'&x"7201",'1'&x"7202",'1'&x"7203",'1'&x"7204",'1'&x"7205",'1'&x"7206",'1'&x"7207",'1'&x"7208",'1'&x"7209",'1'&x"720A",'1'&x"720B",'1'&x"720C",'1'&x"720D",'1'&x"720E",'1'&x"720F",
+--'1'&x"7210",'1'&x"7211",'1'&x"7212",'1'&x"7213",'1'&x"7214",'1'&x"7215",'1'&x"7216",'1'&x"7217",'1'&x"7218",'1'&x"7219",'1'&x"721A",'1'&x"721B",'1'&x"721C",'1'&x"721D",'1'&x"721E",'1'&x"721F",
+--'1'&x"7220",'1'&x"7221",'1'&x"7222",'1'&x"7223",'1'&x"7224",'1'&x"7225",'1'&x"7226",'1'&x"7227",'1'&x"7228",'1'&x"7229",'1'&x"722A",'1'&x"722B",'1'&x"722C",'1'&x"722D",'1'&x"722E",'1'&x"722F",
+--'1'&x"7230",'1'&x"7231",'1'&x"7232",'1'&x"7233",'1'&x"7234",'1'&x"7235",'1'&x"7236",'1'&x"7237",'1'&x"7238",'1'&x"7239",'1'&x"723A",'1'&x"723B",'1'&x"723C",'1'&x"723D",'1'&x"723E",'1'&x"723F",
+--'1'&x"7240",'1'&x"7241",'1'&x"7242",'1'&x"7243",'1'&x"7244",'1'&x"7245",'1'&x"7246",'1'&x"7247",'1'&x"7248",'1'&x"7249",'1'&x"724A",'1'&x"724B",'1'&x"724C",'1'&x"724D",'1'&x"724E",'1'&x"724F",
+--'1'&x"7250",'1'&x"7251",'1'&x"7252",'1'&x"7253",'1'&x"7254",'1'&x"7255",'1'&x"7256",'1'&x"7257",'1'&x"7258",'1'&x"7259",'1'&x"725A",'1'&x"725B",'1'&x"725C",'1'&x"725D",'1'&x"725E",'1'&x"725F",
+--'1'&x"7260",'1'&x"7261",'1'&x"7262",'1'&x"7263",'1'&x"7264",'1'&x"7265",'1'&x"7266",'1'&x"7267",'1'&x"7268",'1'&x"7269",'1'&x"726A",'1'&x"726B",'1'&x"726C",'1'&x"726D",'1'&x"726E",'1'&x"726F",
+--'1'&x"7270",'1'&x"7271",'1'&x"7272",'1'&x"7273",'1'&x"7274",'1'&x"7275",'1'&x"7276",'1'&x"7277",'1'&x"7278",'1'&x"7279",'1'&x"727A",'1'&x"727B",'1'&x"727C",'1'&x"727D",'1'&x"727E",'1'&x"727F",
+--'1'&x"7280",'1'&x"7281",'1'&x"7282",'1'&x"7283",'1'&x"7284",'1'&x"7285",'1'&x"7286",'1'&x"7287",'1'&x"7288",'1'&x"7289",'1'&x"728A",'1'&x"728B",'1'&x"728C",'1'&x"728D",'1'&x"728E",'1'&x"728F",
+--'1'&x"7290",'1'&x"7291",'1'&x"7292",'1'&x"7293",'1'&x"7294",'1'&x"7295",'1'&x"7296",'1'&x"7297",'1'&x"7298",'1'&x"7299",'1'&x"729A",'1'&x"729B",'1'&x"729C",'1'&x"729D",'1'&x"729E",'1'&x"729F",
+--'1'&x"72A0",'1'&x"72A1",'1'&x"72A2",'1'&x"72A3",'1'&x"72A4",'1'&x"72A5",'1'&x"72A6",'1'&x"72A7",'1'&x"72A8",'1'&x"72A9",'1'&x"72AA",'1'&x"72AB",'1'&x"72AC",'1'&x"72AD",'1'&x"72AE",'1'&x"72AF",
+--'1'&x"72B0",'1'&x"72B1",'1'&x"72B2",'1'&x"72B3",'1'&x"72B4",'1'&x"72B5",'1'&x"72B6",'1'&x"72B7",'1'&x"72B8",'1'&x"72B9",'1'&x"72BA",'1'&x"72BB",'1'&x"72BC",'1'&x"72BD",'1'&x"72BE",'1'&x"72BF",
+--'1'&x"72C0",'1'&x"72C1",'1'&x"72C2",'1'&x"72C3",'1'&x"72C4",'1'&x"72C5",'1'&x"72C6",'1'&x"72C7",'1'&x"72C8",'1'&x"72C9",'1'&x"72CA",'1'&x"72CB",'1'&x"72CC",'1'&x"72CD",'1'&x"72CE",'1'&x"72CF",
+--'1'&x"72D0",'1'&x"72D1",'1'&x"72D2",'1'&x"72D3",'1'&x"72D4",'1'&x"72D5",'1'&x"72D6",'1'&x"72D7",'1'&x"72D8",'1'&x"72D9",'1'&x"72DA",'1'&x"72DB",'1'&x"72DC",'1'&x"72DD",'1'&x"72DE",'1'&x"72DF",
+--'1'&x"72E0",'1'&x"72E1",'1'&x"72E2",'1'&x"72E3",'1'&x"72E4",'1'&x"72E5",'1'&x"72E6",'1'&x"72E7",'1'&x"72E8",'1'&x"72E9",'1'&x"72EA",'1'&x"72EB",'1'&x"72EC",'1'&x"72ED",'1'&x"72EE",'1'&x"72EF",
+--'1'&x"72F0",'1'&x"72F1",'1'&x"72F2",'1'&x"72F3",'1'&x"72F4",'1'&x"72F5",'1'&x"72F6",'1'&x"72F7",'1'&x"72F8",'1'&x"72F9",'1'&x"72FA",'1'&x"72FB",'1'&x"72FC",'1'&x"72FD",'1'&x"72FE",'1'&x"72FF",
+--'1'&x"7300",'1'&x"7301",'1'&x"7302",'1'&x"7303",'1'&x"7304",'1'&x"7305",'1'&x"7306",'1'&x"7307",'1'&x"7308",'1'&x"7309",'1'&x"730A",'1'&x"730B",'1'&x"730C",'1'&x"730D",'1'&x"730E",'1'&x"730F",
+--'1'&x"7310",'1'&x"7311",'1'&x"7312",'1'&x"7313",'1'&x"7314",'1'&x"7315",'1'&x"7316",'1'&x"7317",'1'&x"7318",'1'&x"7319",'1'&x"731A",'1'&x"731B",'1'&x"731C",'1'&x"731D",'1'&x"731E",'1'&x"731F",
+--'1'&x"7320",'1'&x"7321",'1'&x"7322",'1'&x"7323",'1'&x"7324",'1'&x"7325",'1'&x"7326",'1'&x"7327",'1'&x"7328",'1'&x"7329",'1'&x"732A",'1'&x"732B",'1'&x"732C",'1'&x"732D",'1'&x"732E",'1'&x"732F",
+--'1'&x"7330",'1'&x"7331",'1'&x"7332",'1'&x"7333",'1'&x"7334",'1'&x"7335",'1'&x"7336",'1'&x"7337",'1'&x"7338",'1'&x"7339",'1'&x"733A",'1'&x"733B",'1'&x"733C",'1'&x"733D",'1'&x"733E",'1'&x"733F",
+--'1'&x"7340",'1'&x"7341",'1'&x"7342",'1'&x"7343",'1'&x"7344",'1'&x"7345",'1'&x"7346",'1'&x"7347",'1'&x"7348",'1'&x"7349",'1'&x"734A",'1'&x"734B",'1'&x"734C",'1'&x"734D",'1'&x"734E",'1'&x"734F",
+--'1'&x"7350",'1'&x"7351",'1'&x"7352",'1'&x"7353",'1'&x"7354",'1'&x"7355",'1'&x"7356",'1'&x"7357",'1'&x"7358",'1'&x"7359",'1'&x"735A",'1'&x"735B",'1'&x"735C",'1'&x"735D",'1'&x"735E",'1'&x"735F",
+--'1'&x"7360",'1'&x"7361",'1'&x"7362",'1'&x"7363",'1'&x"7364",'1'&x"7365",'1'&x"7366",'1'&x"7367",'1'&x"7368",'1'&x"7369",'1'&x"736A",'1'&x"736B",'1'&x"736C",'1'&x"736D",'1'&x"736E",'1'&x"736F",
+--'1'&x"7370",'1'&x"7371",'1'&x"7372",'1'&x"7373",'1'&x"7374",'1'&x"7375",'1'&x"7376",'1'&x"7377",'1'&x"7378",'1'&x"7379",'1'&x"737A",'1'&x"737B",'1'&x"737C",'1'&x"737D",'1'&x"737E",'1'&x"737F",
+--'1'&x"7380",'1'&x"7381",'1'&x"7382",'1'&x"7383",'1'&x"7384",'1'&x"7385",'1'&x"7386",'1'&x"7387",'1'&x"7388",'1'&x"7389",'1'&x"738A",'1'&x"738B",'1'&x"738C",'1'&x"738D",'1'&x"738E",'1'&x"738F",
+--'1'&x"7390",'1'&x"7391",'1'&x"7392",'1'&x"7393",'1'&x"7394",'1'&x"7395",'1'&x"7396",'1'&x"7397",'1'&x"7398",'1'&x"7399",'1'&x"739A",'1'&x"739B",'1'&x"739C",'1'&x"739D",'1'&x"739E",'1'&x"739F",
+--'1'&x"73A0",'1'&x"73A1",'1'&x"73A2",'1'&x"73A3",'1'&x"73A4",'1'&x"73A5",'1'&x"73A6",'1'&x"73A7",'1'&x"73A8",'1'&x"73A9",'1'&x"73AA",'1'&x"73AB",'1'&x"73AC",'1'&x"73AD",'1'&x"73AE",'1'&x"73AF",
+--'1'&x"73B0",'1'&x"73B1",'1'&x"73B2",'1'&x"73B3",'1'&x"73B4",'1'&x"73B5",'1'&x"73B6",'1'&x"73B7",'1'&x"73B8",'1'&x"73B9",'1'&x"73BA",'1'&x"73BB",'1'&x"73BC",'1'&x"73BD",'1'&x"73BE",'1'&x"73BF",
+--'1'&x"73C0",'1'&x"73C1",'1'&x"73C2",'1'&x"73C3",'1'&x"73C4",'1'&x"73C5",'1'&x"73C6",'1'&x"73C7",'1'&x"73C8",'1'&x"73C9",'1'&x"73CA",'1'&x"73CB",'1'&x"73CC",'1'&x"73CD",'1'&x"73CE",'1'&x"73CF",
+--'1'&x"73D0",'1'&x"73D1",'1'&x"73D2",'1'&x"73D3",'1'&x"73D4",'1'&x"73D5",'1'&x"73D6",'1'&x"73D7",'1'&x"73D8",'1'&x"73D9",'1'&x"73DA",'1'&x"73DB",'1'&x"73DC",'1'&x"73DD",'1'&x"73DE",'1'&x"73DF",
+--'1'&x"73E0",'1'&x"73E1",'1'&x"73E2",'1'&x"73E3",'1'&x"73E4",'1'&x"73E5",'1'&x"73E6",'1'&x"73E7",'1'&x"73E8",'1'&x"73E9",'1'&x"73EA",'1'&x"73EB",'1'&x"73EC",'1'&x"73ED",'1'&x"73EE",'1'&x"73EF",
+--'1'&x"73F0",'1'&x"73F1",'1'&x"73F2",'1'&x"73F3",'1'&x"73F4",'1'&x"73F5",'1'&x"73F6",'1'&x"73F7",'1'&x"73F8",'1'&x"73F9",'1'&x"73FA",'1'&x"73FB",'1'&x"73FC",'1'&x"73FD",'1'&x"73FE",'1'&x"73FF",
+--'1'&x"7400",'1'&x"7401",'1'&x"7402",'1'&x"7403",'1'&x"7404",'1'&x"7405",'1'&x"7406",'1'&x"7407",'1'&x"7408",'1'&x"7409",'1'&x"740A",'1'&x"740B",'1'&x"740C",'1'&x"740D",'1'&x"740E",'1'&x"740F",
+--'1'&x"7410",'1'&x"7411",'1'&x"7412",'1'&x"7413",'1'&x"7414",'1'&x"7415",'1'&x"7416",'1'&x"7417",'1'&x"7418",'1'&x"7419",'1'&x"741A",'1'&x"741B",'1'&x"741C",'1'&x"741D",'1'&x"741E",'1'&x"741F",
+--'1'&x"7420",'1'&x"7421",'1'&x"7422",'1'&x"7423",'1'&x"7424",'1'&x"7425",'1'&x"7426",'1'&x"7427",'1'&x"7428",'1'&x"7429",'1'&x"742A",'1'&x"742B",'1'&x"742C",'1'&x"742D",'1'&x"742E",'1'&x"742F",
+--'1'&x"7430",'1'&x"7431",'1'&x"7432",'1'&x"7433",'1'&x"7434",'1'&x"7435",'1'&x"7436",'1'&x"7437",'1'&x"7438",'1'&x"7439",'1'&x"743A",'1'&x"743B",'1'&x"743C",'1'&x"743D",'1'&x"743E",'1'&x"743F",
+--'1'&x"7440",'1'&x"7441",'1'&x"7442",'1'&x"7443",'1'&x"7444",'1'&x"7445",'1'&x"7446",'1'&x"7447",'1'&x"7448",'1'&x"7449",'1'&x"744A",'1'&x"744B",'1'&x"744C",'1'&x"744D",'1'&x"744E",'1'&x"744F",
+--'1'&x"7450",'1'&x"7451",'1'&x"7452",'1'&x"7453",'1'&x"7454",'1'&x"7455",'1'&x"7456",'1'&x"7457",'1'&x"7458",'1'&x"7459",'1'&x"745A",'1'&x"745B",'1'&x"745C",'1'&x"745D",'1'&x"745E",'1'&x"745F",
+--'1'&x"7460",'1'&x"7461",'1'&x"7462",'1'&x"7463",'1'&x"7464",'1'&x"7465",'1'&x"7466",'1'&x"7467",'1'&x"7468",'1'&x"7469",'1'&x"746A",'1'&x"746B",'1'&x"746C",'1'&x"746D",'1'&x"746E",'1'&x"746F",
+--'1'&x"7470",'1'&x"7471",'1'&x"7472",'1'&x"7473",'1'&x"7474",'1'&x"7475",'1'&x"7476",'1'&x"7477",'1'&x"7478",'1'&x"7479",'1'&x"747A",'1'&x"747B",'1'&x"747C",'1'&x"747D",'1'&x"747E",'1'&x"747F",
+--'1'&x"7480",'1'&x"7481",'1'&x"7482",'1'&x"7483",'1'&x"7484",'1'&x"7485",'1'&x"7486",'1'&x"7487",'1'&x"7488",'1'&x"7489",'1'&x"748A",'1'&x"748B",'1'&x"748C",'1'&x"748D",'1'&x"748E",'1'&x"748F",
+--'1'&x"7490",'1'&x"7491",'1'&x"7492",'1'&x"7493",'1'&x"7494",'1'&x"7495",'1'&x"7496",'1'&x"7497",'1'&x"7498",'1'&x"7499",'1'&x"749A",'1'&x"749B",'1'&x"749C",'1'&x"749D",'1'&x"749E",'1'&x"749F",
+--'1'&x"74A0",'1'&x"74A1",'1'&x"74A2",'1'&x"74A3",'1'&x"74A4",'1'&x"74A5",'1'&x"74A6",'1'&x"74A7",'1'&x"74A8",'1'&x"74A9",'1'&x"74AA",'1'&x"74AB",'1'&x"74AC",'1'&x"74AD",'1'&x"74AE",'1'&x"74AF",
+--'1'&x"74B0",'1'&x"74B1",'1'&x"74B2",'1'&x"74B3",'1'&x"74B4",'1'&x"74B5",'1'&x"74B6",'1'&x"74B7",'1'&x"74B8",'1'&x"74B9",'1'&x"74BA",'1'&x"74BB",'1'&x"74BC",'1'&x"74BD",'1'&x"74BE",'1'&x"74BF",
+--'1'&x"74C0",'1'&x"74C1",'1'&x"74C2",'1'&x"74C3",'1'&x"74C4",'1'&x"74C5",'1'&x"74C6",'1'&x"74C7",'1'&x"74C8",'1'&x"74C9",'1'&x"74CA",'1'&x"74CB",'1'&x"74CC",'1'&x"74CD",'1'&x"74CE",'1'&x"74CF",
+--'1'&x"74D0",'1'&x"74D1",'1'&x"74D2",'1'&x"74D3",'1'&x"74D4",'1'&x"74D5",'1'&x"74D6",'1'&x"74D7",'1'&x"74D8",'1'&x"74D9",'1'&x"74DA",'1'&x"74DB",'1'&x"74DC",'1'&x"74DD",'1'&x"74DE",'1'&x"74DF",
+--'1'&x"74E0",'1'&x"74E1",'1'&x"74E2",'1'&x"74E3",'1'&x"74E4",'1'&x"74E5",'1'&x"74E6",'1'&x"74E7",'1'&x"74E8",'1'&x"74E9",'1'&x"74EA",'1'&x"74EB",'1'&x"74EC",'1'&x"74ED",'1'&x"74EE",'1'&x"74EF",
+--'1'&x"74F0",'1'&x"74F1",'1'&x"74F2",'1'&x"74F3",'1'&x"74F4",'1'&x"74F5",'1'&x"74F6",'1'&x"74F7",'1'&x"74F8",'1'&x"74F9",'1'&x"74FA",'1'&x"74FB",'1'&x"74FC",'1'&x"74FD",'1'&x"74FE",'1'&x"74FF",
+--'1'&x"7500",'1'&x"7501",'1'&x"7502",'1'&x"7503",'1'&x"7504",'1'&x"7505",'1'&x"7506",'1'&x"7507",'1'&x"7508",'1'&x"7509",'1'&x"750A",'1'&x"750B",'1'&x"750C",'1'&x"750D",'1'&x"750E",'1'&x"750F",
+--'1'&x"7510",'1'&x"7511",'1'&x"7512",'1'&x"7513",'1'&x"7514",'1'&x"7515",'1'&x"7516",'1'&x"7517",'1'&x"7518",'1'&x"7519",'1'&x"751A",'1'&x"751B",'1'&x"751C",'1'&x"751D",'1'&x"751E",'1'&x"751F",
+--'1'&x"7520",'1'&x"7521",'1'&x"7522",'1'&x"7523",'1'&x"7524",'1'&x"7525",'1'&x"7526",'1'&x"7527",'1'&x"7528",'1'&x"7529",'1'&x"752A",'1'&x"752B",'1'&x"752C",'1'&x"752D",'1'&x"752E",'1'&x"752F",
+--'1'&x"7530",'1'&x"7531",'1'&x"7532",'1'&x"7533",'1'&x"7534",'1'&x"7535",'1'&x"7536",'1'&x"7537",'1'&x"7538",'1'&x"7539",'1'&x"753A",'1'&x"753B",'1'&x"753C",'1'&x"753D",'1'&x"753E",'1'&x"753F",
+--'1'&x"7540",'1'&x"7541",'1'&x"7542",'1'&x"7543",'1'&x"7544",'1'&x"7545",'1'&x"7546",'1'&x"7547",'1'&x"7548",'1'&x"7549",'1'&x"754A",'1'&x"754B",'1'&x"754C",'1'&x"754D",'1'&x"754E",'1'&x"754F",
+--'1'&x"7550",'1'&x"7551",'1'&x"7552",'1'&x"7553",'1'&x"7554",'1'&x"7555",'1'&x"7556",'1'&x"7557",'1'&x"7558",'1'&x"7559",'1'&x"755A",'1'&x"755B",'1'&x"755C",'1'&x"755D",'1'&x"755E",'1'&x"755F",
+--'1'&x"7560",'1'&x"7561",'1'&x"7562",'1'&x"7563",'1'&x"7564",'1'&x"7565",'1'&x"7566",'1'&x"7567",'1'&x"7568",'1'&x"7569",'1'&x"756A",'1'&x"756B",'1'&x"756C",'1'&x"756D",'1'&x"756E",'1'&x"756F",
+--'1'&x"7570",'1'&x"7571",'1'&x"7572",'1'&x"7573",'1'&x"7574",'1'&x"7575",'1'&x"7576",'1'&x"7577",'1'&x"7578",'1'&x"7579",'1'&x"757A",'1'&x"757B",'1'&x"757C",'1'&x"757D",'1'&x"757E",'1'&x"757F",
+--'1'&x"7580",'1'&x"7581",'1'&x"7582",'1'&x"7583",'1'&x"7584",'1'&x"7585",'1'&x"7586",'1'&x"7587",'1'&x"7588",'1'&x"7589",'1'&x"758A",'1'&x"758B",'1'&x"758C",'1'&x"758D",'1'&x"758E",'1'&x"758F",
+--'1'&x"7590",'1'&x"7591",'1'&x"7592",'1'&x"7593",'1'&x"7594",'1'&x"7595",'1'&x"7596",'1'&x"7597",'1'&x"7598",'1'&x"7599",'1'&x"759A",'1'&x"759B",'1'&x"759C",'1'&x"759D",'1'&x"759E",'1'&x"759F",
+--'1'&x"75A0",'1'&x"75A1",'1'&x"75A2",'1'&x"75A3",'1'&x"75A4",'1'&x"75A5",'1'&x"75A6",'1'&x"75A7",'1'&x"75A8",'1'&x"75A9",'1'&x"75AA",'1'&x"75AB",'1'&x"75AC",'1'&x"75AD",'1'&x"75AE",'1'&x"75AF",
+--'1'&x"75B0",'1'&x"75B1",'1'&x"75B2",'1'&x"75B3",'1'&x"75B4",'1'&x"75B5",'1'&x"75B6",'1'&x"75B7",'1'&x"75B8",'1'&x"75B9",'1'&x"75BA",'1'&x"75BB",'1'&x"75BC",'1'&x"75BD",'1'&x"75BE",'1'&x"75BF",
+--'1'&x"75C0",'1'&x"75C1",'1'&x"75C2",'1'&x"75C3",'1'&x"75C4",'1'&x"75C5",'1'&x"75C6",'1'&x"75C7",'1'&x"75C8",'1'&x"75C9",'1'&x"75CA",'1'&x"75CB",'1'&x"75CC",'1'&x"75CD",'1'&x"75CE",'1'&x"75CF",
+--'1'&x"75D0",'1'&x"75D1",'1'&x"75D2",'1'&x"75D3",'1'&x"75D4",'1'&x"75D5",'1'&x"75D6",'1'&x"75D7",'1'&x"75D8",'1'&x"75D9",'1'&x"75DA",'1'&x"75DB",'1'&x"75DC",'1'&x"75DD",'1'&x"75DE",'1'&x"75DF",
+--'1'&x"75E0",'1'&x"75E1",'1'&x"75E2",'1'&x"75E3",'1'&x"75E4",'1'&x"75E5",'1'&x"75E6",'1'&x"75E7",'1'&x"75E8",'1'&x"75E9",'1'&x"75EA",'1'&x"75EB",'1'&x"75EC",'1'&x"75ED",'1'&x"75EE",'1'&x"75EF",
+--'1'&x"75F0",'1'&x"75F1",'1'&x"75F2",'1'&x"75F3",'1'&x"75F4",'1'&x"75F5",'1'&x"75F6",'1'&x"75F7",'1'&x"75F8",'1'&x"75F9",'1'&x"75FA",'1'&x"75FB",'1'&x"75FC",'1'&x"75FD",'1'&x"75FE",'1'&x"75FF",
+--'1'&x"7600",'1'&x"7601",'1'&x"7602",'1'&x"7603",'1'&x"7604",'1'&x"7605",'1'&x"7606",'1'&x"7607",'1'&x"7608",'1'&x"7609",'1'&x"760A",'1'&x"760B",'1'&x"760C",'1'&x"760D",'1'&x"760E",'1'&x"760F",
+--'1'&x"7610",'1'&x"7611",'1'&x"7612",'1'&x"7613",'1'&x"7614",'1'&x"7615",'1'&x"7616",'1'&x"7617",'1'&x"7618",'1'&x"7619",'1'&x"761A",'1'&x"761B",'1'&x"761C",'1'&x"761D",'1'&x"761E",'1'&x"761F",
+--'1'&x"7620",'1'&x"7621",'1'&x"7622",'1'&x"7623",'1'&x"7624",'1'&x"7625",'1'&x"7626",'1'&x"7627",'1'&x"7628",'1'&x"7629",'1'&x"762A",'1'&x"762B",'1'&x"762C",'1'&x"762D",'1'&x"762E",'1'&x"762F",
+--'1'&x"7630",'1'&x"7631",'1'&x"7632",'1'&x"7633",'1'&x"7634",'1'&x"7635",'1'&x"7636",'1'&x"7637",'1'&x"7638",'1'&x"7639",'1'&x"763A",'1'&x"763B",'1'&x"763C",'1'&x"763D",'1'&x"763E",'1'&x"763F",
+--'1'&x"7640",'1'&x"7641",'1'&x"7642",'1'&x"7643",'1'&x"7644",'1'&x"7645",'1'&x"7646",'1'&x"7647",'1'&x"7648",'1'&x"7649",'1'&x"764A",'1'&x"764B",'1'&x"764C",'1'&x"764D",'1'&x"764E",'1'&x"764F",
+--'1'&x"7650",'1'&x"7651",'1'&x"7652",'1'&x"7653",'1'&x"7654",'1'&x"7655",'1'&x"7656",'1'&x"7657",'1'&x"7658",'1'&x"7659",'1'&x"765A",'1'&x"765B",'1'&x"765C",'1'&x"765D",'1'&x"765E",'1'&x"765F",
+--'1'&x"7660",'1'&x"7661",'1'&x"7662",'1'&x"7663",'1'&x"7664",'1'&x"7665",'1'&x"7666",'1'&x"7667",'1'&x"7668",'1'&x"7669",'1'&x"766A",'1'&x"766B",'1'&x"766C",'1'&x"766D",'1'&x"766E",'1'&x"766F",
+--'1'&x"7670",'1'&x"7671",'1'&x"7672",'1'&x"7673",'1'&x"7674",'1'&x"7675",'1'&x"7676",'1'&x"7677",'1'&x"7678",'1'&x"7679",'1'&x"767A",'1'&x"767B",'1'&x"767C",'1'&x"767D",'1'&x"767E",'1'&x"767F",
+--'1'&x"7680",'1'&x"7681",'1'&x"7682",'1'&x"7683",'1'&x"7684",'1'&x"7685",'1'&x"7686",'1'&x"7687",'1'&x"7688",'1'&x"7689",'1'&x"768A",'1'&x"768B",'1'&x"768C",'1'&x"768D",'1'&x"768E",'1'&x"768F",
+--'1'&x"7690",'1'&x"7691",'1'&x"7692",'1'&x"7693",'1'&x"7694",'1'&x"7695",'1'&x"7696",'1'&x"7697",'1'&x"7698",'1'&x"7699",'1'&x"769A",'1'&x"769B",'1'&x"769C",'1'&x"769D",'1'&x"769E",'1'&x"769F",
+--'1'&x"76A0",'1'&x"76A1",'1'&x"76A2",'1'&x"76A3",'1'&x"76A4",'1'&x"76A5",'1'&x"76A6",'1'&x"76A7",'1'&x"76A8",'1'&x"76A9",'1'&x"76AA",'1'&x"76AB",'1'&x"76AC",'1'&x"76AD",'1'&x"76AE",'1'&x"76AF",
+--'1'&x"76B0",'1'&x"76B1",'1'&x"76B2",'1'&x"76B3",'1'&x"76B4",'1'&x"76B5",'1'&x"76B6",'1'&x"76B7",'1'&x"76B8",'1'&x"76B9",'1'&x"76BA",'1'&x"76BB",'1'&x"76BC",'1'&x"76BD",'1'&x"76BE",'1'&x"76BF",
+--'1'&x"76C0",'1'&x"76C1",'1'&x"76C2",'1'&x"76C3",'1'&x"76C4",'1'&x"76C5",'1'&x"76C6",'1'&x"76C7",'1'&x"76C8",'1'&x"76C9",'1'&x"76CA",'1'&x"76CB",'1'&x"76CC",'1'&x"76CD",'1'&x"76CE",'1'&x"76CF",
+--'1'&x"76D0",'1'&x"76D1",'1'&x"76D2",'1'&x"76D3",'1'&x"76D4",'1'&x"76D5",'1'&x"76D6",'1'&x"76D7",'1'&x"76D8",'1'&x"76D9",'1'&x"76DA",'1'&x"76DB",'1'&x"76DC",'1'&x"76DD",'1'&x"76DE",'1'&x"76DF",
+--'1'&x"76E0",'1'&x"76E1",'1'&x"76E2",'1'&x"76E3",'1'&x"76E4",'1'&x"76E5",'1'&x"76E6",'1'&x"76E7",'1'&x"76E8",'1'&x"76E9",'1'&x"76EA",'1'&x"76EB",'1'&x"76EC",'1'&x"76ED",'1'&x"76EE",'1'&x"76EF",
+--'1'&x"76F0",'1'&x"76F1",'1'&x"76F2",'1'&x"76F3",'1'&x"76F4",'1'&x"76F5",'1'&x"76F6",'1'&x"76F7",'1'&x"76F8",'1'&x"76F9",'1'&x"76FA",'1'&x"76FB",'1'&x"76FC",'1'&x"76FD",'1'&x"76FE",'1'&x"76FF",
+--'1'&x"7700",'1'&x"7701",'1'&x"7702",'1'&x"7703",'1'&x"7704",'1'&x"7705",'1'&x"7706",'1'&x"7707",'1'&x"7708",'1'&x"7709",'1'&x"770A",'1'&x"770B",'1'&x"770C",'1'&x"770D",'1'&x"770E",'1'&x"770F",
+--'1'&x"7710",'1'&x"7711",'1'&x"7712",'1'&x"7713",'1'&x"7714",'1'&x"7715",'1'&x"7716",'1'&x"7717",'1'&x"7718",'1'&x"7719",'1'&x"771A",'1'&x"771B",'1'&x"771C",'1'&x"771D",'1'&x"771E",'1'&x"771F",
+--'1'&x"7720",'1'&x"7721",'1'&x"7722",'1'&x"7723",'1'&x"7724",'1'&x"7725",'1'&x"7726",'1'&x"7727",'1'&x"7728",'1'&x"7729",'1'&x"772A",'1'&x"772B",'1'&x"772C",'1'&x"772D",'1'&x"772E",'1'&x"772F",
+--'1'&x"7730",'1'&x"7731",'1'&x"7732",'1'&x"7733",'1'&x"7734",'1'&x"7735",'1'&x"7736",'1'&x"7737",'1'&x"7738",'1'&x"7739",'1'&x"773A",'1'&x"773B",'1'&x"773C",'1'&x"773D",'1'&x"773E",'1'&x"773F",
+--'1'&x"7740",'1'&x"7741",'1'&x"7742",'1'&x"7743",'1'&x"7744",'1'&x"7745",'1'&x"7746",'1'&x"7747",'1'&x"7748",'1'&x"7749",'1'&x"774A",'1'&x"774B",'1'&x"774C",'1'&x"774D",'1'&x"774E",'1'&x"774F",
+--'1'&x"7750",'1'&x"7751",'1'&x"7752",'1'&x"7753",'1'&x"7754",'1'&x"7755",'1'&x"7756",'1'&x"7757",'1'&x"7758",'1'&x"7759",'1'&x"775A",'1'&x"775B",'1'&x"775C",'1'&x"775D",'1'&x"775E",'1'&x"775F",
+--'1'&x"7760",'1'&x"7761",'1'&x"7762",'1'&x"7763",'1'&x"7764",'1'&x"7765",'1'&x"7766",'1'&x"7767",'1'&x"7768",'1'&x"7769",'1'&x"776A",'1'&x"776B",'1'&x"776C",'1'&x"776D",'1'&x"776E",'1'&x"776F",
+--'1'&x"7770",'1'&x"7771",'1'&x"7772",'1'&x"7773",'1'&x"7774",'1'&x"7775",'1'&x"7776",'1'&x"7777",'1'&x"7778",'1'&x"7779",'1'&x"777A",'1'&x"777B",'1'&x"777C",'1'&x"777D",'1'&x"777E",'1'&x"777F",
+--'1'&x"7780",'1'&x"7781",'1'&x"7782",'1'&x"7783",'1'&x"7784",'1'&x"7785",'1'&x"7786",'1'&x"7787",'1'&x"7788",'1'&x"7789",'1'&x"778A",'1'&x"778B",'1'&x"778C",'1'&x"778D",'1'&x"778E",'1'&x"778F",
+--'1'&x"7790",'1'&x"7791",'1'&x"7792",'1'&x"7793",'1'&x"7794",'1'&x"7795",'1'&x"7796",'1'&x"7797",'1'&x"7798",'1'&x"7799",'1'&x"779A",'1'&x"779B",'1'&x"779C",'1'&x"779D",'1'&x"779E",'1'&x"779F",
+--'1'&x"77A0",'1'&x"77A1",'1'&x"77A2",'1'&x"77A3",'1'&x"77A4",'1'&x"77A5",'1'&x"77A6",'1'&x"77A7",'1'&x"77A8",'1'&x"77A9",'1'&x"77AA",'1'&x"77AB",'1'&x"77AC",'1'&x"77AD",'1'&x"77AE",'1'&x"77AF",
+--'1'&x"77B0",'1'&x"77B1",'1'&x"77B2",'1'&x"77B3",'1'&x"77B4",'1'&x"77B5",'1'&x"77B6",'1'&x"77B7",'1'&x"77B8",'1'&x"77B9",'1'&x"77BA",'1'&x"77BB",'1'&x"77BC",'1'&x"77BD",'1'&x"77BE",'1'&x"77BF",
+--'1'&x"77C0",'1'&x"77C1",'1'&x"77C2",'1'&x"77C3",'1'&x"77C4",'1'&x"77C5",'1'&x"77C6",'1'&x"77C7",'1'&x"77C8",'1'&x"77C9",'1'&x"77CA",'1'&x"77CB",'1'&x"77CC",'1'&x"77CD",'1'&x"77CE",'1'&x"77CF",
+--'1'&x"77D0",'1'&x"77D1",'1'&x"77D2",'1'&x"77D3",'1'&x"77D4",'1'&x"77D5",'1'&x"77D6",'1'&x"77D7",'1'&x"77D8",'1'&x"77D9",'1'&x"77DA",'1'&x"77DB",'1'&x"77DC",'1'&x"77DD",'1'&x"77DE",'1'&x"77DF",
+--'1'&x"77E0",'1'&x"77E1",'1'&x"77E2",'1'&x"77E3",'1'&x"77E4",'1'&x"77E5",'1'&x"77E6",'1'&x"77E7",'1'&x"77E8",'1'&x"77E9",'1'&x"77EA",'1'&x"77EB",'1'&x"77EC",'1'&x"77ED",'1'&x"77EE",'1'&x"77EF",
+--'1'&x"77F0",'1'&x"77F1",'1'&x"77F2",'1'&x"77F3",'1'&x"77F4",'1'&x"77F5",'1'&x"77F6",'1'&x"77F7",'1'&x"77F8",'1'&x"77F9",'1'&x"77FA",'1'&x"77FB",'1'&x"77FC",'1'&x"77FD",'1'&x"77FE",'1'&x"77FF",
+--'1'&x"7800",'1'&x"7801",'1'&x"7802",'1'&x"7803",'1'&x"7804",'1'&x"7805",'1'&x"7806",'1'&x"7807",'1'&x"7808",'1'&x"7809",'1'&x"780A",'1'&x"780B",'1'&x"780C",'1'&x"780D",'1'&x"780E",'1'&x"780F",
+--'1'&x"7810",'1'&x"7811",'1'&x"7812",'1'&x"7813",'1'&x"7814",'1'&x"7815",'1'&x"7816",'1'&x"7817",'1'&x"7818",'1'&x"7819",'1'&x"781A",'1'&x"781B",'1'&x"781C",'1'&x"781D",'1'&x"781E",'1'&x"781F",
+--'1'&x"7820",'1'&x"7821",'1'&x"7822",'1'&x"7823",'1'&x"7824",'1'&x"7825",'1'&x"7826",'1'&x"7827",'1'&x"7828",'1'&x"7829",'1'&x"782A",'1'&x"782B",'1'&x"782C",'1'&x"782D",'1'&x"782E",'1'&x"782F",
+--'1'&x"7830",'1'&x"7831",'1'&x"7832",'1'&x"7833",'1'&x"7834",'1'&x"7835",'1'&x"7836",'1'&x"7837",'1'&x"7838",'1'&x"7839",'1'&x"783A",'1'&x"783B",'1'&x"783C",'1'&x"783D",'1'&x"783E",'1'&x"783F",
+--'1'&x"7840",'1'&x"7841",'1'&x"7842",'1'&x"7843",'1'&x"7844",'1'&x"7845",'1'&x"7846",'1'&x"7847",'1'&x"7848",'1'&x"7849",'1'&x"784A",'1'&x"784B",'1'&x"784C",'1'&x"784D",'1'&x"784E",'1'&x"784F",
+--'1'&x"7850",'1'&x"7851",'1'&x"7852",'1'&x"7853",'1'&x"7854",'1'&x"7855",'1'&x"7856",'1'&x"7857",'1'&x"7858",'1'&x"7859",'1'&x"785A",'1'&x"785B",'1'&x"785C",'1'&x"785D",'1'&x"785E",'1'&x"785F",
+--'1'&x"7860",'1'&x"7861",'1'&x"7862",'1'&x"7863",'1'&x"7864",'1'&x"7865",'1'&x"7866",'1'&x"7867",'1'&x"7868",'1'&x"7869",'1'&x"786A",'1'&x"786B",'1'&x"786C",'1'&x"786D",'1'&x"786E",'1'&x"786F",
+--'1'&x"7870",'1'&x"7871",'1'&x"7872",'1'&x"7873",'1'&x"7874",'1'&x"7875",'1'&x"7876",'1'&x"7877",'1'&x"7878",'1'&x"7879",'1'&x"787A",'1'&x"787B",'1'&x"787C",'1'&x"787D",'1'&x"787E",'1'&x"787F",
+--'1'&x"7880",'1'&x"7881",'1'&x"7882",'1'&x"7883",'1'&x"7884",'1'&x"7885",'1'&x"7886",'1'&x"7887",'1'&x"7888",'1'&x"7889",'1'&x"788A",'1'&x"788B",'1'&x"788C",'1'&x"788D",'1'&x"788E",'1'&x"788F",
+--'1'&x"7890",'1'&x"7891",'1'&x"7892",'1'&x"7893",'1'&x"7894",'1'&x"7895",'1'&x"7896",'1'&x"7897",'1'&x"7898",'1'&x"7899",'1'&x"789A",'1'&x"789B",'1'&x"789C",'1'&x"789D",'1'&x"789E",'1'&x"789F",
+--'1'&x"78A0",'1'&x"78A1",'1'&x"78A2",'1'&x"78A3",'1'&x"78A4",'1'&x"78A5",'1'&x"78A6",'1'&x"78A7",'1'&x"78A8",'1'&x"78A9",'1'&x"78AA",'1'&x"78AB",'1'&x"78AC",'1'&x"78AD",'1'&x"78AE",'1'&x"78AF",
+--'1'&x"78B0",'1'&x"78B1",'1'&x"78B2",'1'&x"78B3",'1'&x"78B4",'1'&x"78B5",'1'&x"78B6",'1'&x"78B7",'1'&x"78B8",'1'&x"78B9",'1'&x"78BA",'1'&x"78BB",'1'&x"78BC",'1'&x"78BD",'1'&x"78BE",'1'&x"78BF",
+--'1'&x"78C0",'1'&x"78C1",'1'&x"78C2",'1'&x"78C3",'1'&x"78C4",'1'&x"78C5",'1'&x"78C6",'1'&x"78C7",'1'&x"78C8",'1'&x"78C9",'1'&x"78CA",'1'&x"78CB",'1'&x"78CC",'1'&x"78CD",'1'&x"78CE",'1'&x"78CF",
+--'1'&x"78D0",'1'&x"78D1",'1'&x"78D2",'1'&x"78D3",'1'&x"78D4",'1'&x"78D5",'1'&x"78D6",'1'&x"78D7",'1'&x"78D8",'1'&x"78D9",'1'&x"78DA",'1'&x"78DB",'1'&x"78DC",'1'&x"78DD",'1'&x"78DE",'1'&x"78DF",
+--'1'&x"78E0",'1'&x"78E1",'1'&x"78E2",'1'&x"78E3",'1'&x"78E4",'1'&x"78E5",'1'&x"78E6",'1'&x"78E7",'1'&x"78E8",'1'&x"78E9",'1'&x"78EA",'1'&x"78EB",'1'&x"78EC",'1'&x"78ED",'1'&x"78EE",'1'&x"78EF",
+--'1'&x"78F0",'1'&x"78F1",'1'&x"78F2",'1'&x"78F3",'1'&x"78F4",'1'&x"78F5",'1'&x"78F6",'1'&x"78F7",'1'&x"78F8",'1'&x"78F9",'1'&x"78FA",'1'&x"78FB",'1'&x"78FC",'1'&x"78FD",'1'&x"78FE",'1'&x"78FF",
+--'1'&x"7900",'1'&x"7901",'1'&x"7902",'1'&x"7903",'1'&x"7904",'1'&x"7905",'1'&x"7906",'1'&x"7907",'1'&x"7908",'1'&x"7909",'1'&x"790A",'1'&x"790B",'1'&x"790C",'1'&x"790D",'1'&x"790E",'1'&x"790F",
+--'1'&x"7910",'1'&x"7911",'1'&x"7912",'1'&x"7913",'1'&x"7914",'1'&x"7915",'1'&x"7916",'1'&x"7917",'1'&x"7918",'1'&x"7919",'1'&x"791A",'1'&x"791B",'1'&x"791C",'1'&x"791D",'1'&x"791E",'1'&x"791F",
+--'1'&x"7920",'1'&x"7921",'1'&x"7922",'1'&x"7923",'1'&x"7924",'1'&x"7925",'1'&x"7926",'1'&x"7927",'1'&x"7928",'1'&x"7929",'1'&x"792A",'1'&x"792B",'1'&x"792C",'1'&x"792D",'1'&x"792E",'1'&x"792F",
+--'1'&x"7930",'1'&x"7931",'1'&x"7932",'1'&x"7933",'1'&x"7934",'1'&x"7935",'1'&x"7936",'1'&x"7937",'1'&x"7938",'1'&x"7939",'1'&x"793A",'1'&x"793B",'1'&x"793C",'1'&x"793D",'1'&x"793E",'1'&x"793F",
+--'1'&x"7940",'1'&x"7941",'1'&x"7942",'1'&x"7943",'1'&x"7944",'1'&x"7945",'1'&x"7946",'1'&x"7947",'1'&x"7948",'1'&x"7949",'1'&x"794A",'1'&x"794B",'1'&x"794C",'1'&x"794D",'1'&x"794E",'1'&x"794F",
+--'1'&x"7950",'1'&x"7951",'1'&x"7952",'1'&x"7953",'1'&x"7954",'1'&x"7955",'1'&x"7956",'1'&x"7957",'1'&x"7958",'1'&x"7959",'1'&x"795A",'1'&x"795B",'1'&x"795C",'1'&x"795D",'1'&x"795E",'1'&x"795F",
+--'1'&x"7960",'1'&x"7961",'1'&x"7962",'1'&x"7963",'1'&x"7964",'1'&x"7965",'1'&x"7966",'1'&x"7967",'1'&x"7968",'1'&x"7969",'1'&x"796A",'1'&x"796B",'1'&x"796C",'1'&x"796D",'1'&x"796E",'1'&x"796F",
+--'1'&x"7970",'1'&x"7971",'1'&x"7972",'1'&x"7973",'1'&x"7974",'1'&x"7975",'1'&x"7976",'1'&x"7977",'1'&x"7978",'1'&x"7979",'1'&x"797A",'1'&x"797B",'1'&x"797C",'1'&x"797D",'1'&x"797E",'1'&x"797F",
+--'1'&x"7980",'1'&x"7981",'1'&x"7982",'1'&x"7983",'1'&x"7984",'1'&x"7985",'1'&x"7986",'1'&x"7987",'1'&x"7988",'1'&x"7989",'1'&x"798A",'1'&x"798B",'1'&x"798C",'1'&x"798D",'1'&x"798E",'1'&x"798F",
+--'1'&x"7990",'1'&x"7991",'1'&x"7992",'1'&x"7993",'1'&x"7994",'1'&x"7995",'1'&x"7996",'1'&x"7997",'1'&x"7998",'1'&x"7999",'1'&x"799A",'1'&x"799B",'1'&x"799C",'1'&x"799D",'1'&x"799E",'1'&x"799F",
+--'1'&x"79A0",'1'&x"79A1",'1'&x"79A2",'1'&x"79A3",'1'&x"79A4",'1'&x"79A5",'1'&x"79A6",'1'&x"79A7",'1'&x"79A8",'1'&x"79A9",'1'&x"79AA",'1'&x"79AB",'1'&x"79AC",'1'&x"79AD",'1'&x"79AE",'1'&x"79AF",
+--'1'&x"79B0",'1'&x"79B1",'1'&x"79B2",'1'&x"79B3",'1'&x"79B4",'1'&x"79B5",'1'&x"79B6",'1'&x"79B7",'1'&x"79B8",'1'&x"79B9",'1'&x"79BA",'1'&x"79BB",'1'&x"79BC",'1'&x"79BD",'1'&x"79BE",'1'&x"79BF",
+--'1'&x"79C0",'1'&x"79C1",'1'&x"79C2",'1'&x"79C3",'1'&x"79C4",'1'&x"79C5",'1'&x"79C6",'1'&x"79C7",'1'&x"79C8",'1'&x"79C9",'1'&x"79CA",'1'&x"79CB",'1'&x"79CC",'1'&x"79CD",'1'&x"79CE",'1'&x"79CF",
+--'1'&x"79D0",'1'&x"79D1",'1'&x"79D2",'1'&x"79D3",'1'&x"79D4",'1'&x"79D5",'1'&x"79D6",'1'&x"79D7",'1'&x"79D8",'1'&x"79D9",'1'&x"79DA",'1'&x"79DB",'1'&x"79DC",'1'&x"79DD",'1'&x"79DE",'1'&x"79DF",
+--'1'&x"79E0",'1'&x"79E1",'1'&x"79E2",'1'&x"79E3",'1'&x"79E4",'1'&x"79E5",'1'&x"79E6",'1'&x"79E7",'1'&x"79E8",'1'&x"79E9",'1'&x"79EA",'1'&x"79EB",'1'&x"79EC",'1'&x"79ED",'1'&x"79EE",'1'&x"79EF",
+--'1'&x"79F0",'1'&x"79F1",'1'&x"79F2",'1'&x"79F3",'1'&x"79F4",'1'&x"79F5",'1'&x"79F6",'1'&x"79F7",'1'&x"79F8",'1'&x"79F9",'1'&x"79FA",'1'&x"79FB",'1'&x"79FC",'1'&x"79FD",'1'&x"79FE",'1'&x"79FF",
+--'1'&x"7A00",'1'&x"7A01",'1'&x"7A02",'1'&x"7A03",'1'&x"7A04",'1'&x"7A05",'1'&x"7A06",'1'&x"7A07",'1'&x"7A08",'1'&x"7A09",'1'&x"7A0A",'1'&x"7A0B",'1'&x"7A0C",'1'&x"7A0D",'1'&x"7A0E",'1'&x"7A0F",
+--'1'&x"7A10",'1'&x"7A11",'1'&x"7A12",'1'&x"7A13",'1'&x"7A14",'1'&x"7A15",'1'&x"7A16",'1'&x"7A17",'1'&x"7A18",'1'&x"7A19",'1'&x"7A1A",'1'&x"7A1B",'1'&x"7A1C",'1'&x"7A1D",'1'&x"7A1E",'1'&x"7A1F",
+--'1'&x"7A20",'1'&x"7A21",'1'&x"7A22",'1'&x"7A23",'1'&x"7A24",'1'&x"7A25",'1'&x"7A26",'1'&x"7A27",'1'&x"7A28",'1'&x"7A29",'1'&x"7A2A",'1'&x"7A2B",'1'&x"7A2C",'1'&x"7A2D",'1'&x"7A2E",'1'&x"7A2F",
+--'1'&x"7A30",'1'&x"7A31",'1'&x"7A32",'1'&x"7A33",'1'&x"7A34",'1'&x"7A35",'1'&x"7A36",'1'&x"7A37",'1'&x"7A38",'1'&x"7A39",'1'&x"7A3A",'1'&x"7A3B",'1'&x"7A3C",'1'&x"7A3D",'1'&x"7A3E",'1'&x"7A3F",
+--'1'&x"7A40",'1'&x"7A41",'1'&x"7A42",'1'&x"7A43",'1'&x"7A44",'1'&x"7A45",'1'&x"7A46",'1'&x"7A47",'1'&x"7A48",'1'&x"7A49",'1'&x"7A4A",'1'&x"7A4B",'1'&x"7A4C",'1'&x"7A4D",'1'&x"7A4E",'1'&x"7A4F",
+--'1'&x"7A50",'1'&x"7A51",'1'&x"7A52",'1'&x"7A53",'1'&x"7A54",'1'&x"7A55",'1'&x"7A56",'1'&x"7A57",'1'&x"7A58",'1'&x"7A59",'1'&x"7A5A",'1'&x"7A5B",'1'&x"7A5C",'1'&x"7A5D",'1'&x"7A5E",'1'&x"7A5F",
+--'1'&x"7A60",'1'&x"7A61",'1'&x"7A62",'1'&x"7A63",'1'&x"7A64",'1'&x"7A65",'1'&x"7A66",'1'&x"7A67",'1'&x"7A68",'1'&x"7A69",'1'&x"7A6A",'1'&x"7A6B",'1'&x"7A6C",'1'&x"7A6D",'1'&x"7A6E",'1'&x"7A6F",
+--'1'&x"7A70",'1'&x"7A71",'1'&x"7A72",'1'&x"7A73",'1'&x"7A74",'1'&x"7A75",'1'&x"7A76",'1'&x"7A77",'1'&x"7A78",'1'&x"7A79",'1'&x"7A7A",'1'&x"7A7B",'1'&x"7A7C",'1'&x"7A7D",'1'&x"7A7E",'1'&x"7A7F",
+--'1'&x"7A80",'1'&x"7A81",'1'&x"7A82",'1'&x"7A83",'1'&x"7A84",'1'&x"7A85",'1'&x"7A86",'1'&x"7A87",'1'&x"7A88",'1'&x"7A89",'1'&x"7A8A",'1'&x"7A8B",'1'&x"7A8C",'1'&x"7A8D",'1'&x"7A8E",'1'&x"7A8F",
+--'1'&x"7A90",'1'&x"7A91",'1'&x"7A92",'1'&x"7A93",'1'&x"7A94",'1'&x"7A95",'1'&x"7A96",'1'&x"7A97",'1'&x"7A98",'1'&x"7A99",'1'&x"7A9A",'1'&x"7A9B",'1'&x"7A9C",'1'&x"7A9D",'1'&x"7A9E",'1'&x"7A9F",
+--'1'&x"7AA0",'1'&x"7AA1",'1'&x"7AA2",'1'&x"7AA3",'1'&x"7AA4",'1'&x"7AA5",'1'&x"7AA6",'1'&x"7AA7",'1'&x"7AA8",'1'&x"7AA9",'1'&x"7AAA",'1'&x"7AAB",'1'&x"7AAC",'1'&x"7AAD",'1'&x"7AAE",'1'&x"7AAF",
+--'1'&x"7AB0",'1'&x"7AB1",'1'&x"7AB2",'1'&x"7AB3",'1'&x"7AB4",'1'&x"7AB5",'1'&x"7AB6",'1'&x"7AB7",'1'&x"7AB8",'1'&x"7AB9",'1'&x"7ABA",'1'&x"7ABB",'1'&x"7ABC",'1'&x"7ABD",'1'&x"7ABE",'1'&x"7ABF",
+--'1'&x"7AC0",'1'&x"7AC1",'1'&x"7AC2",'1'&x"7AC3",'1'&x"7AC4",'1'&x"7AC5",'1'&x"7AC6",'1'&x"7AC7",'1'&x"7AC8",'1'&x"7AC9",'1'&x"7ACA",'1'&x"7ACB",'1'&x"7ACC",'1'&x"7ACD",'1'&x"7ACE",'1'&x"7ACF",
+--'1'&x"7AD0",'1'&x"7AD1",'1'&x"7AD2",'1'&x"7AD3",'1'&x"7AD4",'1'&x"7AD5",'1'&x"7AD6",'1'&x"7AD7",'1'&x"7AD8",'1'&x"7AD9",'1'&x"7ADA",'1'&x"7ADB",'1'&x"7ADC",'1'&x"7ADD",'1'&x"7ADE",'1'&x"7ADF",
+--'1'&x"7AE0",'1'&x"7AE1",'1'&x"7AE2",'1'&x"7AE3",'1'&x"7AE4",'1'&x"7AE5",'1'&x"7AE6",'1'&x"7AE7",'1'&x"7AE8",'1'&x"7AE9",'1'&x"7AEA",'1'&x"7AEB",'1'&x"7AEC",'1'&x"7AED",'1'&x"7AEE",'1'&x"7AEF",
+--'1'&x"7AF0",'1'&x"7AF1",'1'&x"7AF2",'1'&x"7AF3",'1'&x"7AF4",'1'&x"7AF5",'1'&x"7AF6",'1'&x"7AF7",'1'&x"7AF8",'1'&x"7AF9",'1'&x"7AFA",'1'&x"7AFB",'1'&x"7AFC",'1'&x"7AFD",'1'&x"7AFE",'1'&x"7AFF",
+--'1'&x"7B00",'1'&x"7B01",'1'&x"7B02",'1'&x"7B03",'1'&x"7B04",'1'&x"7B05",'1'&x"7B06",'1'&x"7B07",'1'&x"7B08",'1'&x"7B09",'1'&x"7B0A",'1'&x"7B0B",'1'&x"7B0C",'1'&x"7B0D",'1'&x"7B0E",'1'&x"7B0F",
+--'1'&x"7B10",'1'&x"7B11",'1'&x"7B12",'1'&x"7B13",'1'&x"7B14",'1'&x"7B15",'1'&x"7B16",'1'&x"7B17",'1'&x"7B18",'1'&x"7B19",'1'&x"7B1A",'1'&x"7B1B",'1'&x"7B1C",'1'&x"7B1D",'1'&x"7B1E",'1'&x"7B1F",
+--'1'&x"7B20",'1'&x"7B21",'1'&x"7B22",'1'&x"7B23",'1'&x"7B24",'1'&x"7B25",'1'&x"7B26",'1'&x"7B27",'1'&x"7B28",'1'&x"7B29",'1'&x"7B2A",'1'&x"7B2B",'1'&x"7B2C",'1'&x"7B2D",'1'&x"7B2E",'1'&x"7B2F",
+--'1'&x"7B30",'1'&x"7B31",'1'&x"7B32",'1'&x"7B33",'1'&x"7B34",'1'&x"7B35",'1'&x"7B36",'1'&x"7B37",'1'&x"7B38",'1'&x"7B39",'1'&x"7B3A",'1'&x"7B3B",'1'&x"7B3C",'1'&x"7B3D",'1'&x"7B3E",'1'&x"7B3F",
+--'1'&x"7B40",'1'&x"7B41",'1'&x"7B42",'1'&x"7B43",'1'&x"7B44",'1'&x"7B45",'1'&x"7B46",'1'&x"7B47",'1'&x"7B48",'1'&x"7B49",'1'&x"7B4A",'1'&x"7B4B",'1'&x"7B4C",'1'&x"7B4D",'1'&x"7B4E",'1'&x"7B4F",
+--'1'&x"7B50",'1'&x"7B51",'1'&x"7B52",'1'&x"7B53",'1'&x"7B54",'1'&x"7B55",'1'&x"7B56",'1'&x"7B57",'1'&x"7B58",'1'&x"7B59",'1'&x"7B5A",'1'&x"7B5B",'1'&x"7B5C",'1'&x"7B5D",'1'&x"7B5E",'1'&x"7B5F",
+--'1'&x"7B60",'1'&x"7B61",'1'&x"7B62",'1'&x"7B63",'1'&x"7B64",'1'&x"7B65",'1'&x"7B66",'1'&x"7B67",'1'&x"7B68",'1'&x"7B69",'1'&x"7B6A",'1'&x"7B6B",'1'&x"7B6C",'1'&x"7B6D",'1'&x"7B6E",'1'&x"7B6F",
+--'1'&x"7B70",'1'&x"7B71",'1'&x"7B72",'1'&x"7B73",'1'&x"7B74",'1'&x"7B75",'1'&x"7B76",'1'&x"7B77",'1'&x"7B78",'1'&x"7B79",'1'&x"7B7A",'1'&x"7B7B",'1'&x"7B7C",'1'&x"7B7D",'1'&x"7B7E",'1'&x"7B7F",
+--'1'&x"7B80",'1'&x"7B81",'1'&x"7B82",'1'&x"7B83",'1'&x"7B84",'1'&x"7B85",'1'&x"7B86",'1'&x"7B87",'1'&x"7B88",'1'&x"7B89",'1'&x"7B8A",'1'&x"7B8B",'1'&x"7B8C",'1'&x"7B8D",'1'&x"7B8E",'1'&x"7B8F",
+--'1'&x"7B90",'1'&x"7B91",'1'&x"7B92",'1'&x"7B93",'1'&x"7B94",'1'&x"7B95",'1'&x"7B96",'1'&x"7B97",'1'&x"7B98",'1'&x"7B99",'1'&x"7B9A",'1'&x"7B9B",'1'&x"7B9C",'1'&x"7B9D",'1'&x"7B9E",'1'&x"7B9F",
+--'1'&x"7BA0",'1'&x"7BA1",'1'&x"7BA2",'1'&x"7BA3",'1'&x"7BA4",'1'&x"7BA5",'1'&x"7BA6",'1'&x"7BA7",'1'&x"7BA8",'1'&x"7BA9",'1'&x"7BAA",'1'&x"7BAB",'1'&x"7BAC",'1'&x"7BAD",'1'&x"7BAE",'1'&x"7BAF",
+--'1'&x"7BB0",'1'&x"7BB1",'1'&x"7BB2",'1'&x"7BB3",'1'&x"7BB4",'1'&x"7BB5",'1'&x"7BB6",'1'&x"7BB7",'1'&x"7BB8",'1'&x"7BB9",'1'&x"7BBA",'1'&x"7BBB",'1'&x"7BBC",'1'&x"7BBD",'1'&x"7BBE",'1'&x"7BBF",
+--'1'&x"7BC0",'1'&x"7BC1",'1'&x"7BC2",'1'&x"7BC3",'1'&x"7BC4",'1'&x"7BC5",'1'&x"7BC6",'1'&x"7BC7",'1'&x"7BC8",'1'&x"7BC9",'1'&x"7BCA",'1'&x"7BCB",'1'&x"7BCC",'1'&x"7BCD",'1'&x"7BCE",'1'&x"7BCF",
+--'1'&x"7BD0",'1'&x"7BD1",'1'&x"7BD2",'1'&x"7BD3",'1'&x"7BD4",'1'&x"7BD5",'1'&x"7BD6",'1'&x"7BD7",'1'&x"7BD8",'1'&x"7BD9",'1'&x"7BDA",'1'&x"7BDB",'1'&x"7BDC",'1'&x"7BDD",'1'&x"7BDE",'1'&x"7BDF",
+--'1'&x"7BE0",'1'&x"7BE1",'1'&x"7BE2",'1'&x"7BE3",'1'&x"7BE4",'1'&x"7BE5",'1'&x"7BE6",'1'&x"7BE7",'1'&x"7BE8",'1'&x"7BE9",'1'&x"7BEA",'1'&x"7BEB",'1'&x"7BEC",'1'&x"7BED",'1'&x"7BEE",'1'&x"7BEF",
+--'1'&x"7BF0",'1'&x"7BF1",'1'&x"7BF2",'1'&x"7BF3",'1'&x"7BF4",'1'&x"7BF5",'1'&x"7BF6",'1'&x"7BF7",'1'&x"7BF8",'1'&x"7BF9",'1'&x"7BFA",'1'&x"7BFB",'1'&x"7BFC",'1'&x"7BFD",'1'&x"7BFE",'1'&x"7BFF",
+--'1'&x"7C00",'1'&x"7C01",'1'&x"7C02",'1'&x"7C03",'1'&x"7C04",'1'&x"7C05",'1'&x"7C06",'1'&x"7C07",'1'&x"7C08",'1'&x"7C09",'1'&x"7C0A",'1'&x"7C0B",'1'&x"7C0C",'1'&x"7C0D",'1'&x"7C0E",'1'&x"7C0F",
+--'1'&x"7C10",'1'&x"7C11",'1'&x"7C12",'1'&x"7C13",'1'&x"7C14",'1'&x"7C15",'1'&x"7C16",'1'&x"7C17",'1'&x"7C18",'1'&x"7C19",'1'&x"7C1A",'1'&x"7C1B",'1'&x"7C1C",'1'&x"7C1D",'1'&x"7C1E",'1'&x"7C1F",
+--'1'&x"7C20",'1'&x"7C21",'1'&x"7C22",'1'&x"7C23",'1'&x"7C24",'1'&x"7C25",'1'&x"7C26",'1'&x"7C27",'1'&x"7C28",'1'&x"7C29",'1'&x"7C2A",'1'&x"7C2B",'1'&x"7C2C",'1'&x"7C2D",'1'&x"7C2E",'1'&x"7C2F",
+--'1'&x"7C30",'1'&x"7C31",'1'&x"7C32",'1'&x"7C33",'1'&x"7C34",'1'&x"7C35",'1'&x"7C36",'1'&x"7C37",'1'&x"7C38",'1'&x"7C39",'1'&x"7C3A",'1'&x"7C3B",'1'&x"7C3C",'1'&x"7C3D",'1'&x"7C3E",'1'&x"7C3F",
+--'1'&x"7C40",'1'&x"7C41",'1'&x"7C42",'1'&x"7C43",'1'&x"7C44",'1'&x"7C45",'1'&x"7C46",'1'&x"7C47",'1'&x"7C48",'1'&x"7C49",'1'&x"7C4A",'1'&x"7C4B",'1'&x"7C4C",'1'&x"7C4D",'1'&x"7C4E",'1'&x"7C4F",
+--'1'&x"7C50",'1'&x"7C51",'1'&x"7C52",'1'&x"7C53",'1'&x"7C54",'1'&x"7C55",'1'&x"7C56",'1'&x"7C57",'1'&x"7C58",'1'&x"7C59",'1'&x"7C5A",'1'&x"7C5B",'1'&x"7C5C",'1'&x"7C5D",'1'&x"7C5E",'1'&x"7C5F",
+--'1'&x"7C60",'1'&x"7C61",'1'&x"7C62",'1'&x"7C63",'1'&x"7C64",'1'&x"7C65",'1'&x"7C66",'1'&x"7C67",'1'&x"7C68",'1'&x"7C69",'1'&x"7C6A",'1'&x"7C6B",'1'&x"7C6C",'1'&x"7C6D",'1'&x"7C6E",'1'&x"7C6F",
+--'1'&x"7C70",'1'&x"7C71",'1'&x"7C72",'1'&x"7C73",'1'&x"7C74",'1'&x"7C75",'1'&x"7C76",'1'&x"7C77",'1'&x"7C78",'1'&x"7C79",'1'&x"7C7A",'1'&x"7C7B",'1'&x"7C7C",'1'&x"7C7D",'1'&x"7C7E",'1'&x"7C7F",
+--'1'&x"7C80",'1'&x"7C81",'1'&x"7C82",'1'&x"7C83",'1'&x"7C84",'1'&x"7C85",'1'&x"7C86",'1'&x"7C87",'1'&x"7C88",'1'&x"7C89",'1'&x"7C8A",'1'&x"7C8B",'1'&x"7C8C",'1'&x"7C8D",'1'&x"7C8E",'1'&x"7C8F",
+--'1'&x"7C90",'1'&x"7C91",'1'&x"7C92",'1'&x"7C93",'1'&x"7C94",'1'&x"7C95",'1'&x"7C96",'1'&x"7C97",'1'&x"7C98",'1'&x"7C99",'1'&x"7C9A",'1'&x"7C9B",'1'&x"7C9C",'1'&x"7C9D",'1'&x"7C9E",'1'&x"7C9F",
+--'1'&x"7CA0",'1'&x"7CA1",'1'&x"7CA2",'1'&x"7CA3",'1'&x"7CA4",'1'&x"7CA5",'1'&x"7CA6",'1'&x"7CA7",'1'&x"7CA8",'1'&x"7CA9",'1'&x"7CAA",'1'&x"7CAB",'1'&x"7CAC",'1'&x"7CAD",'1'&x"7CAE",'1'&x"7CAF",
+--'1'&x"7CB0",'1'&x"7CB1",'1'&x"7CB2",'1'&x"7CB3",'1'&x"7CB4",'1'&x"7CB5",'1'&x"7CB6",'1'&x"7CB7",'1'&x"7CB8",'1'&x"7CB9",'1'&x"7CBA",'1'&x"7CBB",'1'&x"7CBC",'1'&x"7CBD",'1'&x"7CBE",'1'&x"7CBF",
+--'1'&x"7CC0",'1'&x"7CC1",'1'&x"7CC2",'1'&x"7CC3",'1'&x"7CC4",'1'&x"7CC5",'1'&x"7CC6",'1'&x"7CC7",'1'&x"7CC8",'1'&x"7CC9",'1'&x"7CCA",'1'&x"7CCB",'1'&x"7CCC",'1'&x"7CCD",'1'&x"7CCE",'1'&x"7CCF",
+--'1'&x"7CD0",'1'&x"7CD1",'1'&x"7CD2",'1'&x"7CD3",'1'&x"7CD4",'1'&x"7CD5",'1'&x"7CD6",'1'&x"7CD7",'1'&x"7CD8",'1'&x"7CD9",'1'&x"7CDA",'1'&x"7CDB",'1'&x"7CDC",'1'&x"7CDD",'1'&x"7CDE",'1'&x"7CDF",
+--'1'&x"7CE0",'1'&x"7CE1",'1'&x"7CE2",'1'&x"7CE3",'1'&x"7CE4",'1'&x"7CE5",'1'&x"7CE6",'1'&x"7CE7",'1'&x"7CE8",'1'&x"7CE9",'1'&x"7CEA",'1'&x"7CEB",'1'&x"7CEC",'1'&x"7CED",'1'&x"7CEE",'1'&x"7CEF",
+--'1'&x"7CF0",'1'&x"7CF1",'1'&x"7CF2",'1'&x"7CF3",'1'&x"7CF4",'1'&x"7CF5",'1'&x"7CF6",'1'&x"7CF7",'1'&x"7CF8",'1'&x"7CF9",'1'&x"7CFA",'1'&x"7CFB",'1'&x"7CFC",'1'&x"7CFD",'1'&x"7CFE",'1'&x"7CFF",
+--'1'&x"7D00",'1'&x"7D01",'1'&x"7D02",'1'&x"7D03",'1'&x"7D04",'1'&x"7D05",'1'&x"7D06",'1'&x"7D07",'1'&x"7D08",'1'&x"7D09",'1'&x"7D0A",'1'&x"7D0B",'1'&x"7D0C",'1'&x"7D0D",'1'&x"7D0E",'1'&x"7D0F",
+--'1'&x"7D10",'1'&x"7D11",'1'&x"7D12",'1'&x"7D13",'1'&x"7D14",'1'&x"7D15",'1'&x"7D16",'1'&x"7D17",'1'&x"7D18",'1'&x"7D19",'1'&x"7D1A",'1'&x"7D1B",'1'&x"7D1C",'1'&x"7D1D",'1'&x"7D1E",'1'&x"7D1F",
+--'1'&x"7D20",'1'&x"7D21",'1'&x"7D22",'1'&x"7D23",'1'&x"7D24",'1'&x"7D25",'1'&x"7D26",'1'&x"7D27",'1'&x"7D28",'1'&x"7D29",'1'&x"7D2A",'1'&x"7D2B",'1'&x"7D2C",'1'&x"7D2D",'1'&x"7D2E",'1'&x"7D2F",
+--'1'&x"7D30",'1'&x"7D31",'1'&x"7D32",'1'&x"7D33",'1'&x"7D34",'1'&x"7D35",'1'&x"7D36",'1'&x"7D37",'1'&x"7D38",'1'&x"7D39",'1'&x"7D3A",'1'&x"7D3B",'1'&x"7D3C",'1'&x"7D3D",'1'&x"7D3E",'1'&x"7D3F",
+--'1'&x"7D40",'1'&x"7D41",'1'&x"7D42",'1'&x"7D43",'1'&x"7D44",'1'&x"7D45",'1'&x"7D46",'1'&x"7D47",'1'&x"7D48",'1'&x"7D49",'1'&x"7D4A",'1'&x"7D4B",'1'&x"7D4C",'1'&x"7D4D",'1'&x"7D4E",'1'&x"7D4F",
+--'1'&x"7D50",'1'&x"7D51",'1'&x"7D52",'1'&x"7D53",'1'&x"7D54",'1'&x"7D55",'1'&x"7D56",'1'&x"7D57",'1'&x"7D58",'1'&x"7D59",'1'&x"7D5A",'1'&x"7D5B",'1'&x"7D5C",'1'&x"7D5D",'1'&x"7D5E",'1'&x"7D5F",
+--'1'&x"7D60",'1'&x"7D61",'1'&x"7D62",'1'&x"7D63",'1'&x"7D64",'1'&x"7D65",'1'&x"7D66",'1'&x"7D67",'1'&x"7D68",'1'&x"7D69",'1'&x"7D6A",'1'&x"7D6B",'1'&x"7D6C",'1'&x"7D6D",'1'&x"7D6E",'1'&x"7D6F",
+--'1'&x"7D70",'1'&x"7D71",'1'&x"7D72",'1'&x"7D73",'1'&x"7D74",'1'&x"7D75",'1'&x"7D76",'1'&x"7D77",'1'&x"7D78",'1'&x"7D79",'1'&x"7D7A",'1'&x"7D7B",'1'&x"7D7C",'1'&x"7D7D",'1'&x"7D7E",'1'&x"7D7F",
+--'1'&x"7D80",'1'&x"7D81",'1'&x"7D82",'1'&x"7D83",'1'&x"7D84",'1'&x"7D85",'1'&x"7D86",'1'&x"7D87",'1'&x"7D88",'1'&x"7D89",'1'&x"7D8A",'1'&x"7D8B",'1'&x"7D8C",'1'&x"7D8D",'1'&x"7D8E",'1'&x"7D8F",
+--'1'&x"7D90",'1'&x"7D91",'1'&x"7D92",'1'&x"7D93",'1'&x"7D94",'1'&x"7D95",'1'&x"7D96",'1'&x"7D97",'1'&x"7D98",'1'&x"7D99",'1'&x"7D9A",'1'&x"7D9B",'1'&x"7D9C",'1'&x"7D9D",'1'&x"7D9E",'1'&x"7D9F",
+--'1'&x"7DA0",'1'&x"7DA1",'1'&x"7DA2",'1'&x"7DA3",'1'&x"7DA4",'1'&x"7DA5",'1'&x"7DA6",'1'&x"7DA7",'1'&x"7DA8",'1'&x"7DA9",'1'&x"7DAA",'1'&x"7DAB",'1'&x"7DAC",'1'&x"7DAD",'1'&x"7DAE",'1'&x"7DAF",
+--'1'&x"7DB0",'1'&x"7DB1",'1'&x"7DB2",'1'&x"7DB3",'1'&x"7DB4",'1'&x"7DB5",'1'&x"7DB6",'1'&x"7DB7",'1'&x"7DB8",'1'&x"7DB9",'1'&x"7DBA",'1'&x"7DBB",'1'&x"7DBC",'1'&x"7DBD",'1'&x"7DBE",'1'&x"7DBF",
+--'1'&x"7DC0",'1'&x"7DC1",'1'&x"7DC2",'1'&x"7DC3",'1'&x"7DC4",'1'&x"7DC5",'1'&x"7DC6",'1'&x"7DC7",'1'&x"7DC8",'1'&x"7DC9",'1'&x"7DCA",'1'&x"7DCB",'1'&x"7DCC",'1'&x"7DCD",'1'&x"7DCE",'1'&x"7DCF",
+--'1'&x"7DD0",'1'&x"7DD1",'1'&x"7DD2",'1'&x"7DD3",'1'&x"7DD4",'1'&x"7DD5",'1'&x"7DD6",'1'&x"7DD7",'1'&x"7DD8",'1'&x"7DD9",'1'&x"7DDA",'1'&x"7DDB",'1'&x"7DDC",'1'&x"7DDD",'1'&x"7DDE",'1'&x"7DDF",
+--'1'&x"7DE0",'1'&x"7DE1",'1'&x"7DE2",'1'&x"7DE3",'1'&x"7DE4",'1'&x"7DE5",'1'&x"7DE6",'1'&x"7DE7",'1'&x"7DE8",'1'&x"7DE9",'1'&x"7DEA",'1'&x"7DEB",'1'&x"7DEC",'1'&x"7DED",'1'&x"7DEE",'1'&x"7DEF",
+--'1'&x"7DF0",'1'&x"7DF1",'1'&x"7DF2",'1'&x"7DF3",'1'&x"7DF4",'1'&x"7DF5",'1'&x"7DF6",'1'&x"7DF7",'1'&x"7DF8",'1'&x"7DF9",'1'&x"7DFA",'1'&x"7DFB",'1'&x"7DFC",'1'&x"7DFD",'1'&x"7DFE",'1'&x"7DFF",
+--'1'&x"7E00",'1'&x"7E01",'1'&x"7E02",'1'&x"7E03",'1'&x"7E04",'1'&x"7E05",'1'&x"7E06",'1'&x"7E07",'1'&x"7E08",'1'&x"7E09",'1'&x"7E0A",'1'&x"7E0B",'1'&x"7E0C",'1'&x"7E0D",'1'&x"7E0E",'1'&x"7E0F",
+--'1'&x"7E10",'1'&x"7E11",'1'&x"7E12",'1'&x"7E13",'1'&x"7E14",'1'&x"7E15",'1'&x"7E16",'1'&x"7E17",'1'&x"7E18",'1'&x"7E19",'1'&x"7E1A",'1'&x"7E1B",'1'&x"7E1C",'1'&x"7E1D",'1'&x"7E1E",'1'&x"7E1F",
+--'1'&x"7E20",'1'&x"7E21",'1'&x"7E22",'1'&x"7E23",'1'&x"7E24",'1'&x"7E25",'1'&x"7E26",'1'&x"7E27",'1'&x"7E28",'1'&x"7E29",'1'&x"7E2A",'1'&x"7E2B",'1'&x"7E2C",'1'&x"7E2D",'1'&x"7E2E",'1'&x"7E2F",
+--'1'&x"7E30",'1'&x"7E31",'1'&x"7E32",'1'&x"7E33",'1'&x"7E34",'1'&x"7E35",'1'&x"7E36",'1'&x"7E37",'1'&x"7E38",'1'&x"7E39",'1'&x"7E3A",'1'&x"7E3B",'1'&x"7E3C",'1'&x"7E3D",'1'&x"7E3E",'1'&x"7E3F",
+--'1'&x"7E40",'1'&x"7E41",'1'&x"7E42",'1'&x"7E43",'1'&x"7E44",'1'&x"7E45",'1'&x"7E46",'1'&x"7E47",'1'&x"7E48",'1'&x"7E49",'1'&x"7E4A",'1'&x"7E4B",'1'&x"7E4C",'1'&x"7E4D",'1'&x"7E4E",'1'&x"7E4F",
+--'1'&x"7E50",'1'&x"7E51",'1'&x"7E52",'1'&x"7E53",'1'&x"7E54",'1'&x"7E55",'1'&x"7E56",'1'&x"7E57",'1'&x"7E58",'1'&x"7E59",'1'&x"7E5A",'1'&x"7E5B",'1'&x"7E5C",'1'&x"7E5D",'1'&x"7E5E",'1'&x"7E5F",
+--'1'&x"7E60",'1'&x"7E61",'1'&x"7E62",'1'&x"7E63",'1'&x"7E64",'1'&x"7E65",'1'&x"7E66",'1'&x"7E67",'1'&x"7E68",'1'&x"7E69",'1'&x"7E6A",'1'&x"7E6B",'1'&x"7E6C",'1'&x"7E6D",'1'&x"7E6E",'1'&x"7E6F",
+--'1'&x"7E70",'1'&x"7E71",'1'&x"7E72",'1'&x"7E73",'1'&x"7E74",'1'&x"7E75",'1'&x"7E76",'1'&x"7E77",'1'&x"7E78",'1'&x"7E79",'1'&x"7E7A",'1'&x"7E7B",'1'&x"7E7C",'1'&x"7E7D",'1'&x"7E7E",'1'&x"7E7F",
+--'1'&x"7E80",'1'&x"7E81",'1'&x"7E82",'1'&x"7E83",'1'&x"7E84",'1'&x"7E85",'1'&x"7E86",'1'&x"7E87",'1'&x"7E88",'1'&x"7E89",'1'&x"7E8A",'1'&x"7E8B",'1'&x"7E8C",'1'&x"7E8D",'1'&x"7E8E",'1'&x"7E8F",
+--'1'&x"7E90",'1'&x"7E91",'1'&x"7E92",'1'&x"7E93",'1'&x"7E94",'1'&x"7E95",'1'&x"7E96",'1'&x"7E97",'1'&x"7E98",'1'&x"7E99",'1'&x"7E9A",'1'&x"7E9B",'1'&x"7E9C",'1'&x"7E9D",'1'&x"7E9E",'1'&x"7E9F",
+--'1'&x"7EA0",'1'&x"7EA1",'1'&x"7EA2",'1'&x"7EA3",'1'&x"7EA4",'1'&x"7EA5",'1'&x"7EA6",'1'&x"7EA7",'1'&x"7EA8",'1'&x"7EA9",'1'&x"7EAA",'1'&x"7EAB",'1'&x"7EAC",'1'&x"7EAD",'1'&x"7EAE",'1'&x"7EAF",
+--'1'&x"7EB0",'1'&x"7EB1",'1'&x"7EB2",'1'&x"7EB3",'1'&x"7EB4",'1'&x"7EB5",'1'&x"7EB6",'1'&x"7EB7",'1'&x"7EB8",'1'&x"7EB9",'1'&x"7EBA",'1'&x"7EBB",'1'&x"7EBC",'1'&x"7EBD",'1'&x"7EBE",'1'&x"7EBF",
+--'1'&x"7EC0",'1'&x"7EC1",'1'&x"7EC2",'1'&x"7EC3",'1'&x"7EC4",'1'&x"7EC5",'1'&x"7EC6",'1'&x"7EC7",'1'&x"7EC8",'1'&x"7EC9",'1'&x"7ECA",'1'&x"7ECB",'1'&x"7ECC",'1'&x"7ECD",'1'&x"7ECE",'1'&x"7ECF",
+--'1'&x"7ED0",'1'&x"7ED1",'1'&x"7ED2",'1'&x"7ED3",'1'&x"7ED4",'1'&x"7ED5",'1'&x"7ED6",'1'&x"7ED7",'1'&x"7ED8",'1'&x"7ED9",'1'&x"7EDA",'1'&x"7EDB",'1'&x"7EDC",'1'&x"7EDD",'1'&x"7EDE",'1'&x"7EDF",
+--'1'&x"7EE0",'1'&x"7EE1",'1'&x"7EE2",'1'&x"7EE3",'1'&x"7EE4",'1'&x"7EE5",'1'&x"7EE6",'1'&x"7EE7",'1'&x"7EE8",'1'&x"7EE9",'1'&x"7EEA",'1'&x"7EEB",'1'&x"7EEC",'1'&x"7EED",'1'&x"7EEE",'1'&x"7EEF",
+--'1'&x"7EF0",'1'&x"7EF1",'1'&x"7EF2",'1'&x"7EF3",'1'&x"7EF4",'1'&x"7EF5",'1'&x"7EF6",'1'&x"7EF7",'1'&x"7EF8",'1'&x"7EF9",'1'&x"7EFA",'1'&x"7EFB",'1'&x"7EFC",'1'&x"7EFD",'1'&x"7EFE",'1'&x"7EFF",
+--'1'&x"7F00",'1'&x"7F01",'1'&x"7F02",'1'&x"7F03",'1'&x"7F04",'1'&x"7F05",'1'&x"7F06",'1'&x"7F07",'1'&x"7F08",'1'&x"7F09",'1'&x"7F0A",'1'&x"7F0B",'1'&x"7F0C",'1'&x"7F0D",'1'&x"7F0E",'1'&x"7F0F",
+--'1'&x"7F10",'1'&x"7F11",'1'&x"7F12",'1'&x"7F13",'1'&x"7F14",'1'&x"7F15",'1'&x"7F16",'1'&x"7F17",'1'&x"7F18",'1'&x"7F19",'1'&x"7F1A",'1'&x"7F1B",'1'&x"7F1C",'1'&x"7F1D",'1'&x"7F1E",'1'&x"7F1F",
+--'1'&x"7F20",'1'&x"7F21",'1'&x"7F22",'1'&x"7F23",'1'&x"7F24",'1'&x"7F25",'1'&x"7F26",'1'&x"7F27",'1'&x"7F28",'1'&x"7F29",'1'&x"7F2A",'1'&x"7F2B",'1'&x"7F2C",'1'&x"7F2D",'1'&x"7F2E",'1'&x"7F2F",
+--'1'&x"7F30",'1'&x"7F31",'1'&x"7F32",'1'&x"7F33",'1'&x"7F34",'1'&x"7F35",'1'&x"7F36",'1'&x"7F37",'1'&x"7F38",'1'&x"7F39",'1'&x"7F3A",'1'&x"7F3B",'1'&x"7F3C",'1'&x"7F3D",'1'&x"7F3E",'1'&x"7F3F",
+--'1'&x"7F40",'1'&x"7F41",'1'&x"7F42",'1'&x"7F43",'1'&x"7F44",'1'&x"7F45",'1'&x"7F46",'1'&x"7F47",'1'&x"7F48",'1'&x"7F49",'1'&x"7F4A",'1'&x"7F4B",'1'&x"7F4C",'1'&x"7F4D",'1'&x"7F4E",'1'&x"7F4F",
+--'1'&x"7F50",'1'&x"7F51",'1'&x"7F52",'1'&x"7F53",'1'&x"7F54",'1'&x"7F55",'1'&x"7F56",'1'&x"7F57",'1'&x"7F58",'1'&x"7F59",'1'&x"7F5A",'1'&x"7F5B",'1'&x"7F5C",'1'&x"7F5D",'1'&x"7F5E",'1'&x"7F5F",
+--'1'&x"7F60",'1'&x"7F61",'1'&x"7F62",'1'&x"7F63",'1'&x"7F64",'1'&x"7F65",'1'&x"7F66",'1'&x"7F67",'1'&x"7F68",'1'&x"7F69",'1'&x"7F6A",'1'&x"7F6B",'1'&x"7F6C",'1'&x"7F6D",'1'&x"7F6E",'1'&x"7F6F",
+--'1'&x"7F70",'1'&x"7F71",'1'&x"7F72",'1'&x"7F73",'1'&x"7F74",'1'&x"7F75",'1'&x"7F76",'1'&x"7F77",'1'&x"7F78",'1'&x"7F79",'1'&x"7F7A",'1'&x"7F7B",'1'&x"7F7C",'1'&x"7F7D",'1'&x"7F7E",'1'&x"7F7F",
+--'1'&x"7F80",'1'&x"7F81",'1'&x"7F82",'1'&x"7F83",'1'&x"7F84",'1'&x"7F85",'1'&x"7F86",'1'&x"7F87",'1'&x"7F88",'1'&x"7F89",'1'&x"7F8A",'1'&x"7F8B",'1'&x"7F8C",'1'&x"7F8D",'1'&x"7F8E",'1'&x"7F8F",
+--'1'&x"7F90",'1'&x"7F91",'1'&x"7F92",'1'&x"7F93",'1'&x"7F94",'1'&x"7F95",'1'&x"7F96",'1'&x"7F97",'1'&x"7F98",'1'&x"7F99",'1'&x"7F9A",'1'&x"7F9B",'1'&x"7F9C",'1'&x"7F9D",'1'&x"7F9E",'1'&x"7F9F",
+--'1'&x"7FA0",'1'&x"7FA1",'1'&x"7FA2",'1'&x"7FA3",'1'&x"7FA4",'1'&x"7FA5",'1'&x"7FA6",'1'&x"7FA7",'1'&x"7FA8",'1'&x"7FA9",'1'&x"7FAA",'1'&x"7FAB",'1'&x"7FAC",'1'&x"7FAD",'1'&x"7FAE",'1'&x"7FAF",
+--'1'&x"7FB0",'1'&x"7FB1",'1'&x"7FB2",'1'&x"7FB3",'1'&x"7FB4",'1'&x"7FB5",'1'&x"7FB6",'1'&x"7FB7",'1'&x"7FB8",'1'&x"7FB9",'1'&x"7FBA",'1'&x"7FBB",'1'&x"7FBC",'1'&x"7FBD",'1'&x"7FBE",'1'&x"7FBF",
+--'1'&x"7FC0",'1'&x"7FC1",'1'&x"7FC2",'1'&x"7FC3",'1'&x"7FC4",'1'&x"7FC5",'1'&x"7FC6",'1'&x"7FC7",'1'&x"7FC8",'1'&x"7FC9",'1'&x"7FCA",'1'&x"7FCB",'1'&x"7FCC",'1'&x"7FCD",'1'&x"7FCE",'1'&x"7FCF",
+--'1'&x"7FD0",'1'&x"7FD1",'1'&x"7FD2",'1'&x"7FD3",'1'&x"7FD4",'1'&x"7FD5",'1'&x"7FD6",'1'&x"7FD7",'1'&x"7FD8",'1'&x"7FD9",'1'&x"7FDA",'1'&x"7FDB",'1'&x"7FDC",'1'&x"7FDD",'1'&x"7FDE",'1'&x"7FDF",
+--'1'&x"7FE0",'1'&x"7FE1",'1'&x"7FE2",'1'&x"7FE3",'1'&x"7FE4",'1'&x"7FE5",'1'&x"7FE6",'1'&x"7FE7",'1'&x"7FE8",'1'&x"7FE9",'1'&x"7FEA",'1'&x"7FEB",'1'&x"7FEC",'1'&x"7FED",'1'&x"7FEE",'1'&x"7FEF",
+--'1'&x"7FF0",'1'&x"7FF1",'1'&x"7FF2",'1'&x"7FF3",'1'&x"7FF4",'1'&x"7FF5",'1'&x"7FF6",'1'&x"7FF7",'1'&x"7FF8",'1'&x"7FF9",'1'&x"7FFA",'1'&x"7FFB",'1'&x"7FFC",'1'&x"7FFD",'1'&x"7FFE",'1'&x"7FFF",
+--'1'&x"8000",'1'&x"8001",'1'&x"8002",'1'&x"8003",'1'&x"8004",'1'&x"8005",'1'&x"8006",'1'&x"8007",'1'&x"8008",'1'&x"8009",'1'&x"800A",'1'&x"800B",'1'&x"800C",'1'&x"800D",'1'&x"800E",'1'&x"800F",
+--'1'&x"8010",'1'&x"8011",'1'&x"8012",'1'&x"8013",'1'&x"8014",'1'&x"8015",'1'&x"8016",'1'&x"8017",'1'&x"8018",'1'&x"8019",'1'&x"801A",'1'&x"801B",'1'&x"801C",'1'&x"801D",'1'&x"801E",'1'&x"801F",
+--'1'&x"8020",'1'&x"8021",'1'&x"8022",'1'&x"8023",'1'&x"8024",'1'&x"8025",'1'&x"8026",'1'&x"8027",'1'&x"8028",'1'&x"8029",'1'&x"802A",'1'&x"802B",'1'&x"802C",'1'&x"802D",'1'&x"802E",'1'&x"802F",
+--'1'&x"8030",'1'&x"8031",'1'&x"8032",'1'&x"8033",'1'&x"8034",'1'&x"8035",'1'&x"8036",'1'&x"8037",'1'&x"8038",'1'&x"8039",'1'&x"803A",'1'&x"803B",'1'&x"803C",'1'&x"803D",'1'&x"803E",'1'&x"803F",
+--'1'&x"8040",'1'&x"8041",'1'&x"8042",'1'&x"8043",'1'&x"8044",'1'&x"8045",'1'&x"8046",'1'&x"8047",'1'&x"8048",'1'&x"8049",'1'&x"804A",'1'&x"804B",'1'&x"804C",'1'&x"804D",'1'&x"804E",'1'&x"804F",
+--'1'&x"8050",'1'&x"8051",'1'&x"8052",'1'&x"8053",'1'&x"8054",'1'&x"8055",'1'&x"8056",'1'&x"8057",'1'&x"8058",'1'&x"8059",'1'&x"805A",'1'&x"805B",'1'&x"805C",'1'&x"805D",'1'&x"805E",'1'&x"805F",
+--'1'&x"8060",'1'&x"8061",'1'&x"8062",'1'&x"8063",'1'&x"8064",'1'&x"8065",'1'&x"8066",'1'&x"8067",'1'&x"8068",'1'&x"8069",'1'&x"806A",'1'&x"806B",'1'&x"806C",'1'&x"806D",'1'&x"806E",'1'&x"806F",
+--'1'&x"8070",'1'&x"8071",'1'&x"8072",'1'&x"8073",'1'&x"8074",'1'&x"8075",'1'&x"8076",'1'&x"8077",'1'&x"8078",'1'&x"8079",'1'&x"807A",'1'&x"807B",'1'&x"807C",'1'&x"807D",'1'&x"807E",'1'&x"807F",
+--'1'&x"8080",'1'&x"8081",'1'&x"8082",'1'&x"8083",'1'&x"8084",'1'&x"8085",'1'&x"8086",'1'&x"8087",'1'&x"8088",'1'&x"8089",'1'&x"808A",'1'&x"808B",'1'&x"808C",'1'&x"808D",'1'&x"808E",'1'&x"808F",
+--'1'&x"8090",'1'&x"8091",'1'&x"8092",'1'&x"8093",'1'&x"8094",'1'&x"8095",'1'&x"8096",'1'&x"8097",'1'&x"8098",'1'&x"8099",'1'&x"809A",'1'&x"809B",'1'&x"809C",'1'&x"809D",'1'&x"809E",'1'&x"809F",
+--'1'&x"80A0",'1'&x"80A1",'1'&x"80A2",'1'&x"80A3",'1'&x"80A4",'1'&x"80A5",'1'&x"80A6",'1'&x"80A7",'1'&x"80A8",'1'&x"80A9",'1'&x"80AA",'1'&x"80AB",'1'&x"80AC",'1'&x"80AD",'1'&x"80AE",'1'&x"80AF",
+--'1'&x"80B0",'1'&x"80B1",'1'&x"80B2",'1'&x"80B3",'1'&x"80B4",'1'&x"80B5",'1'&x"80B6",'1'&x"80B7",'1'&x"80B8",'1'&x"80B9",'1'&x"80BA",'1'&x"80BB",'1'&x"80BC",'1'&x"80BD",'1'&x"80BE",'1'&x"80BF",
+--'1'&x"80C0",'1'&x"80C1",'1'&x"80C2",'1'&x"80C3",'1'&x"80C4",'1'&x"80C5",'1'&x"80C6",'1'&x"80C7",'1'&x"80C8",'1'&x"80C9",'1'&x"80CA",'1'&x"80CB",'1'&x"80CC",'1'&x"80CD",'1'&x"80CE",'1'&x"80CF",
+--'1'&x"80D0",'1'&x"80D1",'1'&x"80D2",'1'&x"80D3",'1'&x"80D4",'1'&x"80D5",'1'&x"80D6",'1'&x"80D7",'1'&x"80D8",'1'&x"80D9",'1'&x"80DA",'1'&x"80DB",'1'&x"80DC",'1'&x"80DD",'1'&x"80DE",'1'&x"80DF",
+--'1'&x"80E0",'1'&x"80E1",'1'&x"80E2",'1'&x"80E3",'1'&x"80E4",'1'&x"80E5",'1'&x"80E6",'1'&x"80E7",'1'&x"80E8",'1'&x"80E9",'1'&x"80EA",'1'&x"80EB",'1'&x"80EC",'1'&x"80ED",'1'&x"80EE",'1'&x"80EF",
+--'1'&x"80F0",'1'&x"80F1",'1'&x"80F2",'1'&x"80F3",'1'&x"80F4",'1'&x"80F5",'1'&x"80F6",'1'&x"80F7",'1'&x"80F8",'1'&x"80F9",'1'&x"80FA",'1'&x"80FB",'1'&x"80FC",'1'&x"80FD",'1'&x"80FE",'1'&x"80FF",
+--'1'&x"8100",'1'&x"8101",'1'&x"8102",'1'&x"8103",'1'&x"8104",'1'&x"8105",'1'&x"8106",'1'&x"8107",'1'&x"8108",'1'&x"8109",'1'&x"810A",'1'&x"810B",'1'&x"810C",'1'&x"810D",'1'&x"810E",'1'&x"810F",
+--'1'&x"8110",'1'&x"8111",'1'&x"8112",'1'&x"8113",'1'&x"8114",'1'&x"8115",'1'&x"8116",'1'&x"8117",'1'&x"8118",'1'&x"8119",'1'&x"811A",'1'&x"811B",'1'&x"811C",'1'&x"811D",'1'&x"811E",'1'&x"811F",
+--'1'&x"8120",'1'&x"8121",'1'&x"8122",'1'&x"8123",'1'&x"8124",'1'&x"8125",'1'&x"8126",'1'&x"8127",'1'&x"8128",'1'&x"8129",'1'&x"812A",'1'&x"812B",'1'&x"812C",'1'&x"812D",'1'&x"812E",'1'&x"812F",
+--'1'&x"8130",'1'&x"8131",'1'&x"8132",'1'&x"8133",'1'&x"8134",'1'&x"8135",'1'&x"8136",'1'&x"8137",'1'&x"8138",'1'&x"8139",'1'&x"813A",'1'&x"813B",'1'&x"813C",'1'&x"813D",'1'&x"813E",'1'&x"813F",
+--'1'&x"8140",'1'&x"8141",'1'&x"8142",'1'&x"8143",'1'&x"8144",'1'&x"8145",'1'&x"8146",'1'&x"8147",'1'&x"8148",'1'&x"8149",'1'&x"814A",'1'&x"814B",'1'&x"814C",'1'&x"814D",'1'&x"814E",'1'&x"814F",
+--'1'&x"8150",'1'&x"8151",'1'&x"8152",'1'&x"8153",'1'&x"8154",'1'&x"8155",'1'&x"8156",'1'&x"8157",'1'&x"8158",'1'&x"8159",'1'&x"815A",'1'&x"815B",'1'&x"815C",'1'&x"815D",'1'&x"815E",'1'&x"815F",
+--'1'&x"8160",'1'&x"8161",'1'&x"8162",'1'&x"8163",'1'&x"8164",'1'&x"8165",'1'&x"8166",'1'&x"8167",'1'&x"8168",'1'&x"8169",'1'&x"816A",'1'&x"816B",'1'&x"816C",'1'&x"816D",'1'&x"816E",'1'&x"816F",
+--'1'&x"8170",'1'&x"8171",'1'&x"8172",'1'&x"8173",'1'&x"8174",'1'&x"8175",'1'&x"8176",'1'&x"8177",'1'&x"8178",'1'&x"8179",'1'&x"817A",'1'&x"817B",'1'&x"817C",'1'&x"817D",'1'&x"817E",'1'&x"817F",
+--'1'&x"8180",'1'&x"8181",'1'&x"8182",'1'&x"8183",'1'&x"8184",'1'&x"8185",'1'&x"8186",'1'&x"8187",'1'&x"8188",'1'&x"8189",'1'&x"818A",'1'&x"818B",'1'&x"818C",'1'&x"818D",'1'&x"818E",'1'&x"818F",
+--'1'&x"8190",'1'&x"8191",'1'&x"8192",'1'&x"8193",'1'&x"8194",'1'&x"8195",'1'&x"8196",'1'&x"8197",'1'&x"8198",'1'&x"8199",'1'&x"819A",'1'&x"819B",'1'&x"819C",'1'&x"819D",'1'&x"819E",'1'&x"819F",
+--'1'&x"81A0",'1'&x"81A1",'1'&x"81A2",'1'&x"81A3",'1'&x"81A4",'1'&x"81A5",'1'&x"81A6",'1'&x"81A7",'1'&x"81A8",'1'&x"81A9",'1'&x"81AA",'1'&x"81AB",'1'&x"81AC",'1'&x"81AD",'1'&x"81AE",'1'&x"81AF",
+--'1'&x"81B0",'1'&x"81B1",'1'&x"81B2",'1'&x"81B3",'1'&x"81B4",'1'&x"81B5",'1'&x"81B6",'1'&x"81B7",'1'&x"81B8",'1'&x"81B9",'1'&x"81BA",'1'&x"81BB",'1'&x"81BC",'1'&x"81BD",'1'&x"81BE",'1'&x"81BF",
+--'1'&x"81C0",'1'&x"81C1",'1'&x"81C2",'1'&x"81C3",'1'&x"81C4",'1'&x"81C5",'1'&x"81C6",'1'&x"81C7",'1'&x"81C8",'1'&x"81C9",'1'&x"81CA",'1'&x"81CB",'1'&x"81CC",'1'&x"81CD",'1'&x"81CE",'1'&x"81CF",
+--'1'&x"81D0",'1'&x"81D1",'1'&x"81D2",'1'&x"81D3",'1'&x"81D4",'1'&x"81D5",'1'&x"81D6",'1'&x"81D7",'1'&x"81D8",'1'&x"81D9",'1'&x"81DA",'1'&x"81DB",'1'&x"81DC",'1'&x"81DD",'1'&x"81DE",'1'&x"81DF",
+--'1'&x"81E0",'1'&x"81E1",'1'&x"81E2",'1'&x"81E3",'1'&x"81E4",'1'&x"81E5",'1'&x"81E6",'1'&x"81E7",'1'&x"81E8",'1'&x"81E9",'1'&x"81EA",'1'&x"81EB",'1'&x"81EC",'1'&x"81ED",'1'&x"81EE",'1'&x"81EF",
+--'1'&x"81F0",'1'&x"81F1",'1'&x"81F2",'1'&x"81F3",'1'&x"81F4",'1'&x"81F5",'1'&x"81F6",'1'&x"81F7",'1'&x"81F8",'1'&x"81F9",'1'&x"81FA",'1'&x"81FB",'1'&x"81FC",'1'&x"81FD",'1'&x"81FE",'1'&x"81FF",
+--'1'&x"8200",'1'&x"8201",'1'&x"8202",'1'&x"8203",'1'&x"8204",'1'&x"8205",'1'&x"8206",'1'&x"8207",'1'&x"8208",'1'&x"8209",'1'&x"820A",'1'&x"820B",'1'&x"820C",'1'&x"820D",'1'&x"820E",'1'&x"820F",
+--'1'&x"8210",'1'&x"8211",'1'&x"8212",'1'&x"8213",'1'&x"8214",'1'&x"8215",'1'&x"8216",'1'&x"8217",'1'&x"8218",'1'&x"8219",'1'&x"821A",'1'&x"821B",'1'&x"821C",'1'&x"821D",'1'&x"821E",'1'&x"821F",
+--'1'&x"8220",'1'&x"8221",'1'&x"8222",'1'&x"8223",'1'&x"8224",'1'&x"8225",'1'&x"8226",'1'&x"8227",'1'&x"8228",'1'&x"8229",'1'&x"822A",'1'&x"822B",'1'&x"822C",'1'&x"822D",'1'&x"822E",'1'&x"822F",
+--'1'&x"8230",'1'&x"8231",'1'&x"8232",'1'&x"8233",'1'&x"8234",'1'&x"8235",'1'&x"8236",'1'&x"8237",'1'&x"8238",'1'&x"8239",'1'&x"823A",'1'&x"823B",'1'&x"823C",'1'&x"823D",'1'&x"823E",'1'&x"823F",
+--'1'&x"8240",'1'&x"8241",'1'&x"8242",'1'&x"8243",'1'&x"8244",'1'&x"8245",'1'&x"8246",'1'&x"8247",'1'&x"8248",'1'&x"8249",'1'&x"824A",'1'&x"824B",'1'&x"824C",'1'&x"824D",'1'&x"824E",'1'&x"824F",
+--'1'&x"8250",'1'&x"8251",'1'&x"8252",'1'&x"8253",'1'&x"8254",'1'&x"8255",'1'&x"8256",'1'&x"8257",'1'&x"8258",'1'&x"8259",'1'&x"825A",'1'&x"825B",'1'&x"825C",'1'&x"825D",'1'&x"825E",'1'&x"825F",
+--'1'&x"8260",'1'&x"8261",'1'&x"8262",'1'&x"8263",'1'&x"8264",'1'&x"8265",'1'&x"8266",'1'&x"8267",'1'&x"8268",'1'&x"8269",'1'&x"826A",'1'&x"826B",'1'&x"826C",'1'&x"826D",'1'&x"826E",'1'&x"826F",
+--'1'&x"8270",'1'&x"8271",'1'&x"8272",'1'&x"8273",'1'&x"8274",'1'&x"8275",'1'&x"8276",'1'&x"8277",'1'&x"8278",'1'&x"8279",'1'&x"827A",'1'&x"827B",'1'&x"827C",'1'&x"827D",'1'&x"827E",'1'&x"827F",
+--'1'&x"8280",'1'&x"8281",'1'&x"8282",'1'&x"8283",'1'&x"8284",'1'&x"8285",'1'&x"8286",'1'&x"8287",'1'&x"8288",'1'&x"8289",'1'&x"828A",'1'&x"828B",'1'&x"828C",'1'&x"828D",'1'&x"828E",'1'&x"828F",
+--'1'&x"8290",'1'&x"8291",'1'&x"8292",'1'&x"8293",'1'&x"8294",'1'&x"8295",'1'&x"8296",'1'&x"8297",'1'&x"8298",'1'&x"8299",'1'&x"829A",'1'&x"829B",'1'&x"829C",'1'&x"829D",'1'&x"829E",'1'&x"829F",
+--'1'&x"82A0",'1'&x"82A1",'1'&x"82A2",'1'&x"82A3",'1'&x"82A4",'1'&x"82A5",'1'&x"82A6",'1'&x"82A7",'1'&x"82A8",'1'&x"82A9",'1'&x"82AA",'1'&x"82AB",'1'&x"82AC",'1'&x"82AD",'1'&x"82AE",'1'&x"82AF",
+--'1'&x"82B0",'1'&x"82B1",'1'&x"82B2",'1'&x"82B3",'1'&x"82B4",'1'&x"82B5",'1'&x"82B6",'1'&x"82B7",'1'&x"82B8",'1'&x"82B9",'1'&x"82BA",'1'&x"82BB",'1'&x"82BC",'1'&x"82BD",'1'&x"82BE",'1'&x"82BF",
+--'1'&x"82C0",'1'&x"82C1",'1'&x"82C2",'1'&x"82C3",'1'&x"82C4",'1'&x"82C5",'1'&x"82C6",'1'&x"82C7",'1'&x"82C8",'1'&x"82C9",'1'&x"82CA",'1'&x"82CB",'1'&x"82CC",'1'&x"82CD",'1'&x"82CE",'1'&x"82CF",
+--'1'&x"82D0",'1'&x"82D1",'1'&x"82D2",'1'&x"82D3",'1'&x"82D4",'1'&x"82D5",'1'&x"82D6",'1'&x"82D7",'1'&x"82D8",'1'&x"82D9",'1'&x"82DA",'1'&x"82DB",'1'&x"82DC",'1'&x"82DD",'1'&x"82DE",'1'&x"82DF",
+--'1'&x"82E0",'1'&x"82E1",'1'&x"82E2",'1'&x"82E3",'1'&x"82E4",'1'&x"82E5",'1'&x"82E6",'1'&x"82E7",'1'&x"82E8",'1'&x"82E9",'1'&x"82EA",'1'&x"82EB",'1'&x"82EC",'1'&x"82ED",'1'&x"82EE",'1'&x"82EF",
+--'1'&x"82F0",'1'&x"82F1",'1'&x"82F2",'1'&x"82F3",'1'&x"82F4",'1'&x"82F5",'1'&x"82F6",'1'&x"82F7",'1'&x"82F8",'1'&x"82F9",'1'&x"82FA",'1'&x"82FB",'1'&x"82FC",'1'&x"82FD",'1'&x"82FE",'1'&x"82FF",
+--'1'&x"8300",'1'&x"8301",'1'&x"8302",'1'&x"8303",'1'&x"8304",'1'&x"8305",'1'&x"8306",'1'&x"8307",'1'&x"8308",'1'&x"8309",'1'&x"830A",'1'&x"830B",'1'&x"830C",'1'&x"830D",'1'&x"830E",'1'&x"830F",
+--'1'&x"8310",'1'&x"8311",'1'&x"8312",'1'&x"8313",'1'&x"8314",'1'&x"8315",'1'&x"8316",'1'&x"8317",'1'&x"8318",'1'&x"8319",'1'&x"831A",'1'&x"831B",'1'&x"831C",'1'&x"831D",'1'&x"831E",'1'&x"831F",
+--'1'&x"8320",'1'&x"8321",'1'&x"8322",'1'&x"8323",'1'&x"8324",'1'&x"8325",'1'&x"8326",'1'&x"8327",'1'&x"8328",'1'&x"8329",'1'&x"832A",'1'&x"832B",'1'&x"832C",'1'&x"832D",'1'&x"832E",'1'&x"832F",
+--'1'&x"8330",'1'&x"8331",'1'&x"8332",'1'&x"8333",'1'&x"8334",'1'&x"8335",'1'&x"8336",'1'&x"8337",'1'&x"8338",'1'&x"8339",'1'&x"833A",'1'&x"833B",'1'&x"833C",'1'&x"833D",'1'&x"833E",'1'&x"833F",
+--'1'&x"8340",'1'&x"8341",'1'&x"8342",'1'&x"8343",'1'&x"8344",'1'&x"8345",'1'&x"8346",'1'&x"8347",'1'&x"8348",'1'&x"8349",'1'&x"834A",'1'&x"834B",'1'&x"834C",'1'&x"834D",'1'&x"834E",'1'&x"834F",
+--'1'&x"8350",'1'&x"8351",'1'&x"8352",'1'&x"8353",'1'&x"8354",'1'&x"8355",'1'&x"8356",'1'&x"8357",'1'&x"8358",'1'&x"8359",'1'&x"835A",'1'&x"835B",'1'&x"835C",'1'&x"835D",'1'&x"835E",'1'&x"835F",
+--'1'&x"8360",'1'&x"8361",'1'&x"8362",'1'&x"8363",'1'&x"8364",'1'&x"8365",'1'&x"8366",'1'&x"8367",'1'&x"8368",'1'&x"8369",'1'&x"836A",'1'&x"836B",'1'&x"836C",'1'&x"836D",'1'&x"836E",'1'&x"836F",
+--'1'&x"8370",'1'&x"8371",'1'&x"8372",'1'&x"8373",'1'&x"8374",'1'&x"8375",'1'&x"8376",'1'&x"8377",'1'&x"8378",'1'&x"8379",'1'&x"837A",'1'&x"837B",'1'&x"837C",'1'&x"837D",'1'&x"837E",'1'&x"837F",
+--'1'&x"8380",'1'&x"8381",'1'&x"8382",'1'&x"8383",'1'&x"8384",'1'&x"8385",'1'&x"8386",'1'&x"8387",'1'&x"8388",'1'&x"8389",'1'&x"838A",'1'&x"838B",'1'&x"838C",'1'&x"838D",'1'&x"838E",'1'&x"838F",
+--'1'&x"8390",'1'&x"8391",'1'&x"8392",'1'&x"8393",'1'&x"8394",'1'&x"8395",'1'&x"8396",'1'&x"8397",'1'&x"8398",'1'&x"8399",'1'&x"839A",'1'&x"839B",'1'&x"839C",'1'&x"839D",'1'&x"839E",'1'&x"839F",
+--'1'&x"83A0",'1'&x"83A1",'1'&x"83A2",'1'&x"83A3",'1'&x"83A4",'1'&x"83A5",'1'&x"83A6",'1'&x"83A7",'1'&x"83A8",'1'&x"83A9",'1'&x"83AA",'1'&x"83AB",'1'&x"83AC",'1'&x"83AD",'1'&x"83AE",'1'&x"83AF",
+--'1'&x"83B0",'1'&x"83B1",'1'&x"83B2",'1'&x"83B3",'1'&x"83B4",'1'&x"83B5",'1'&x"83B6",'1'&x"83B7",'1'&x"83B8",'1'&x"83B9",'1'&x"83BA",'1'&x"83BB",'1'&x"83BC",'1'&x"83BD",'1'&x"83BE",'1'&x"83BF",
+--'1'&x"83C0",'1'&x"83C1",'1'&x"83C2",'1'&x"83C3",'1'&x"83C4",'1'&x"83C5",'1'&x"83C6",'1'&x"83C7",'1'&x"83C8",'1'&x"83C9",'1'&x"83CA",'1'&x"83CB",'1'&x"83CC",'1'&x"83CD",'1'&x"83CE",'1'&x"83CF",
+--'1'&x"83D0",'1'&x"83D1",'1'&x"83D2",'1'&x"83D3",'1'&x"83D4",'1'&x"83D5",'1'&x"83D6",'1'&x"83D7",'1'&x"83D8",'1'&x"83D9",'1'&x"83DA",'1'&x"83DB",'1'&x"83DC",'1'&x"83DD",'1'&x"83DE",'1'&x"83DF",
+--'1'&x"83E0",'1'&x"83E1",'1'&x"83E2",'1'&x"83E3",'1'&x"83E4",'1'&x"83E5",'1'&x"83E6",'1'&x"83E7",'1'&x"83E8",'1'&x"83E9",'1'&x"83EA",'1'&x"83EB",'1'&x"83EC",'1'&x"83ED",'1'&x"83EE",'1'&x"83EF",
+--'1'&x"83F0",'1'&x"83F1",'1'&x"83F2",'1'&x"83F3",'1'&x"83F4",'1'&x"83F5",'1'&x"83F6",'1'&x"83F7",'1'&x"83F8",'1'&x"83F9",'1'&x"83FA",'1'&x"83FB",'1'&x"83FC",'1'&x"83FD",'1'&x"83FE",'1'&x"83FF",
+--'1'&x"8400",'1'&x"8401",'1'&x"8402",'1'&x"8403",'1'&x"8404",'1'&x"8405",'1'&x"8406",'1'&x"8407",'1'&x"8408",'1'&x"8409",'1'&x"840A",'1'&x"840B",'1'&x"840C",'1'&x"840D",'1'&x"840E",'1'&x"840F",
+--'1'&x"8410",'1'&x"8411",'1'&x"8412",'1'&x"8413",'1'&x"8414",'1'&x"8415",'1'&x"8416",'1'&x"8417",'1'&x"8418",'1'&x"8419",'1'&x"841A",'1'&x"841B",'1'&x"841C",'1'&x"841D",'1'&x"841E",'1'&x"841F",
+--'1'&x"8420",'1'&x"8421",'1'&x"8422",'1'&x"8423",'1'&x"8424",'1'&x"8425",'1'&x"8426",'1'&x"8427",'1'&x"8428",'1'&x"8429",'1'&x"842A",'1'&x"842B",'1'&x"842C",'1'&x"842D",'1'&x"842E",'1'&x"842F",
+--'1'&x"8430",'1'&x"8431",'1'&x"8432",'1'&x"8433",'1'&x"8434",'1'&x"8435",'1'&x"8436",'1'&x"8437",'1'&x"8438",'1'&x"8439",'1'&x"843A",'1'&x"843B",'1'&x"843C",'1'&x"843D",'1'&x"843E",'1'&x"843F",
+--'1'&x"8440",'1'&x"8441",'1'&x"8442",'1'&x"8443",'1'&x"8444",'1'&x"8445",'1'&x"8446",'1'&x"8447",'1'&x"8448",'1'&x"8449",'1'&x"844A",'1'&x"844B",'1'&x"844C",'1'&x"844D",'1'&x"844E",'1'&x"844F",
+--'1'&x"8450",'1'&x"8451",'1'&x"8452",'1'&x"8453",'1'&x"8454",'1'&x"8455",'1'&x"8456",'1'&x"8457",'1'&x"8458",'1'&x"8459",'1'&x"845A",'1'&x"845B",'1'&x"845C",'1'&x"845D",'1'&x"845E",'1'&x"845F",
+--'1'&x"8460",'1'&x"8461",'1'&x"8462",'1'&x"8463",'1'&x"8464",'1'&x"8465",'1'&x"8466",'1'&x"8467",'1'&x"8468",'1'&x"8469",'1'&x"846A",'1'&x"846B",'1'&x"846C",'1'&x"846D",'1'&x"846E",'1'&x"846F",
+--'1'&x"8470",'1'&x"8471",'1'&x"8472",'1'&x"8473",'1'&x"8474",'1'&x"8475",'1'&x"8476",'1'&x"8477",'1'&x"8478",'1'&x"8479",'1'&x"847A",'1'&x"847B",'1'&x"847C",'1'&x"847D",'1'&x"847E",'1'&x"847F",
+--'1'&x"8480",'1'&x"8481",'1'&x"8482",'1'&x"8483",'1'&x"8484",'1'&x"8485",'1'&x"8486",'1'&x"8487",'1'&x"8488",'1'&x"8489",'1'&x"848A",'1'&x"848B",'1'&x"848C",'1'&x"848D",'1'&x"848E",'1'&x"848F",
+--'1'&x"8490",'1'&x"8491",'1'&x"8492",'1'&x"8493",'1'&x"8494",'1'&x"8495",'1'&x"8496",'1'&x"8497",'1'&x"8498",'1'&x"8499",'1'&x"849A",'1'&x"849B",'1'&x"849C",'1'&x"849D",'1'&x"849E",'1'&x"849F",
+--'1'&x"84A0",'1'&x"84A1",'1'&x"84A2",'1'&x"84A3",'1'&x"84A4",'1'&x"84A5",'1'&x"84A6",'1'&x"84A7",'1'&x"84A8",'1'&x"84A9",'1'&x"84AA",'1'&x"84AB",'1'&x"84AC",'1'&x"84AD",'1'&x"84AE",'1'&x"84AF",
+--'1'&x"84B0",'1'&x"84B1",'1'&x"84B2",'1'&x"84B3",'1'&x"84B4",'1'&x"84B5",'1'&x"84B6",'1'&x"84B7",'1'&x"84B8",'1'&x"84B9",'1'&x"84BA",'1'&x"84BB",'1'&x"84BC",'1'&x"84BD",'1'&x"84BE",'1'&x"84BF",
+--'1'&x"84C0",'1'&x"84C1",'1'&x"84C2",'1'&x"84C3",'1'&x"84C4",'1'&x"84C5",'1'&x"84C6",'1'&x"84C7",'1'&x"84C8",'1'&x"84C9",'1'&x"84CA",'1'&x"84CB",'1'&x"84CC",'1'&x"84CD",'1'&x"84CE",'1'&x"84CF",
+--'1'&x"84D0",'1'&x"84D1",'1'&x"84D2",'1'&x"84D3",'1'&x"84D4",'1'&x"84D5",'1'&x"84D6",'1'&x"84D7",'1'&x"84D8",'1'&x"84D9",'1'&x"84DA",'1'&x"84DB",'1'&x"84DC",'1'&x"84DD",'1'&x"84DE",'1'&x"84DF",
+--'1'&x"84E0",'1'&x"84E1",'1'&x"84E2",'1'&x"84E3",'1'&x"84E4",'1'&x"84E5",'1'&x"84E6",'1'&x"84E7",'1'&x"84E8",'1'&x"84E9",'1'&x"84EA",'1'&x"84EB",'1'&x"84EC",'1'&x"84ED",'1'&x"84EE",'1'&x"84EF",
+--'1'&x"84F0",'1'&x"84F1",'1'&x"84F2",'1'&x"84F3",'1'&x"84F4",'1'&x"84F5",'1'&x"84F6",'1'&x"84F7",'1'&x"84F8",'1'&x"84F9",'1'&x"84FA",'1'&x"84FB",'1'&x"84FC",'1'&x"84FD",'1'&x"84FE",'1'&x"84FF",
+--'1'&x"8500",'1'&x"8501",'1'&x"8502",'1'&x"8503",'1'&x"8504",'1'&x"8505",'1'&x"8506",'1'&x"8507",'1'&x"8508",'1'&x"8509",'1'&x"850A",'1'&x"850B",'1'&x"850C",'1'&x"850D",'1'&x"850E",'1'&x"850F",
+--'1'&x"8510",'1'&x"8511",'1'&x"8512",'1'&x"8513",'1'&x"8514",'1'&x"8515",'1'&x"8516",'1'&x"8517",'1'&x"8518",'1'&x"8519",'1'&x"851A",'1'&x"851B",'1'&x"851C",'1'&x"851D",'1'&x"851E",'1'&x"851F",
+--'1'&x"8520",'1'&x"8521",'1'&x"8522",'1'&x"8523",'1'&x"8524",'1'&x"8525",'1'&x"8526",'1'&x"8527",'1'&x"8528",'1'&x"8529",'1'&x"852A",'1'&x"852B",'1'&x"852C",'1'&x"852D",'1'&x"852E",'1'&x"852F",
+--'1'&x"8530",'1'&x"8531",'1'&x"8532",'1'&x"8533",'1'&x"8534",'1'&x"8535",'1'&x"8536",'1'&x"8537",'1'&x"8538",'1'&x"8539",'1'&x"853A",'1'&x"853B",'1'&x"853C",'1'&x"853D",'1'&x"853E",'1'&x"853F",
+--'1'&x"8540",'1'&x"8541",'1'&x"8542",'1'&x"8543",'1'&x"8544",'1'&x"8545",'1'&x"8546",'1'&x"8547",'1'&x"8548",'1'&x"8549",'1'&x"854A",'1'&x"854B",'1'&x"854C",'1'&x"854D",'1'&x"854E",'1'&x"854F",
+--'1'&x"8550",'1'&x"8551",'1'&x"8552",'1'&x"8553",'1'&x"8554",'1'&x"8555",'1'&x"8556",'1'&x"8557",'1'&x"8558",'1'&x"8559",'1'&x"855A",'1'&x"855B",'1'&x"855C",'1'&x"855D",'1'&x"855E",'1'&x"855F",
+--'1'&x"8560",'1'&x"8561",'1'&x"8562",'1'&x"8563",'1'&x"8564",'1'&x"8565",'1'&x"8566",'1'&x"8567",'1'&x"8568",'1'&x"8569",'1'&x"856A",'1'&x"856B",'1'&x"856C",'1'&x"856D",'1'&x"856E",'1'&x"856F",
+--'1'&x"8570",'1'&x"8571",'1'&x"8572",'1'&x"8573",'1'&x"8574",'1'&x"8575",'1'&x"8576",'1'&x"8577",'1'&x"8578",'1'&x"8579",'1'&x"857A",'1'&x"857B",'1'&x"857C",'1'&x"857D",'1'&x"857E",'1'&x"857F",
+--'1'&x"8580",'1'&x"8581",'1'&x"8582",'1'&x"8583",'1'&x"8584",'1'&x"8585",'1'&x"8586",'1'&x"8587",'1'&x"8588",'1'&x"8589",'1'&x"858A",'1'&x"858B",'1'&x"858C",'1'&x"858D",'1'&x"858E",'1'&x"858F",
+--'1'&x"8590",'1'&x"8591",'1'&x"8592",'1'&x"8593",'1'&x"8594",'1'&x"8595",'1'&x"8596",'1'&x"8597",'1'&x"8598",'1'&x"8599",'1'&x"859A",'1'&x"859B",'1'&x"859C",'1'&x"859D",'1'&x"859E",'1'&x"859F",
+--'1'&x"85A0",'1'&x"85A1",'1'&x"85A2",'1'&x"85A3",'1'&x"85A4",'1'&x"85A5",'1'&x"85A6",'1'&x"85A7",'1'&x"85A8",'1'&x"85A9",'1'&x"85AA",'1'&x"85AB",'1'&x"85AC",'1'&x"85AD",'1'&x"85AE",'1'&x"85AF",
+--'1'&x"85B0",'1'&x"85B1",'1'&x"85B2",'1'&x"85B3",'1'&x"85B4",'1'&x"85B5",'1'&x"85B6",'1'&x"85B7",'1'&x"85B8",'1'&x"85B9",'1'&x"85BA",'1'&x"85BB",'1'&x"85BC",'1'&x"85BD",'1'&x"85BE",'1'&x"85BF",
+--'1'&x"85C0",'1'&x"85C1",'1'&x"85C2",'1'&x"85C3",'1'&x"85C4",'1'&x"85C5",'1'&x"85C6",'1'&x"85C7",'1'&x"85C8",'1'&x"85C9",'1'&x"85CA",'1'&x"85CB",'1'&x"85CC",'1'&x"85CD",'1'&x"85CE",'1'&x"85CF",
+--'1'&x"85D0",'1'&x"85D1",'1'&x"85D2",'1'&x"85D3",'1'&x"85D4",'1'&x"85D5",'1'&x"85D6",'1'&x"85D7",'1'&x"85D8",'1'&x"85D9",'1'&x"85DA",'1'&x"85DB",'1'&x"85DC",'1'&x"85DD",'1'&x"85DE",'1'&x"85DF",
+--'1'&x"85E0",'1'&x"85E1",'1'&x"85E2",'1'&x"85E3",'1'&x"85E4",'1'&x"85E5",'1'&x"85E6",'1'&x"85E7",'1'&x"85E8",'1'&x"85E9",'1'&x"85EA",'1'&x"85EB",'1'&x"85EC",'1'&x"85ED",'1'&x"85EE",'1'&x"85EF",
+--'1'&x"85F0",'1'&x"85F1",'1'&x"85F2",'1'&x"85F3",'1'&x"85F4",'1'&x"85F5",'1'&x"85F6",'1'&x"85F7",'1'&x"85F8",'1'&x"85F9",'1'&x"85FA",'1'&x"85FB",'1'&x"85FC",'1'&x"85FD",'1'&x"85FE",'1'&x"85FF",
+--'1'&x"8600",'1'&x"8601",'1'&x"8602",'1'&x"8603",'1'&x"8604",'1'&x"8605",'1'&x"8606",'1'&x"8607",'1'&x"8608",'1'&x"8609",'1'&x"860A",'1'&x"860B",'1'&x"860C",'1'&x"860D",'1'&x"860E",'1'&x"860F",
+--'1'&x"8610",'1'&x"8611",'1'&x"8612",'1'&x"8613",'1'&x"8614",'1'&x"8615",'1'&x"8616",'1'&x"8617",'1'&x"8618",'1'&x"8619",'1'&x"861A",'1'&x"861B",'1'&x"861C",'1'&x"861D",'1'&x"861E",'1'&x"861F",
+--'1'&x"8620",'1'&x"8621",'1'&x"8622",'1'&x"8623",'1'&x"8624",'1'&x"8625",'1'&x"8626",'1'&x"8627",'1'&x"8628",'1'&x"8629",'1'&x"862A",'1'&x"862B",'1'&x"862C",'1'&x"862D",'1'&x"862E",'1'&x"862F",
+--'1'&x"8630",'1'&x"8631",'1'&x"8632",'1'&x"8633",'1'&x"8634",'1'&x"8635",'1'&x"8636",'1'&x"8637",'1'&x"8638",'1'&x"8639",'1'&x"863A",'1'&x"863B",'1'&x"863C",'1'&x"863D",'1'&x"863E",'1'&x"863F",
+--'1'&x"8640",'1'&x"8641",'1'&x"8642",'1'&x"8643",'1'&x"8644",'1'&x"8645",'1'&x"8646",'1'&x"8647",'1'&x"8648",'1'&x"8649",'1'&x"864A",'1'&x"864B",'1'&x"864C",'1'&x"864D",'1'&x"864E",'1'&x"864F",
+--'1'&x"8650",'1'&x"8651",'1'&x"8652",'1'&x"8653",'1'&x"8654",'1'&x"8655",'1'&x"8656",'1'&x"8657",'1'&x"8658",'1'&x"8659",'1'&x"865A",'1'&x"865B",'1'&x"865C",'1'&x"865D",'1'&x"865E",'1'&x"865F",
+--'1'&x"8660",'1'&x"8661",'1'&x"8662",'1'&x"8663",'1'&x"8664",'1'&x"8665",'1'&x"8666",'1'&x"8667",'1'&x"8668",'1'&x"8669",'1'&x"866A",'1'&x"866B",'1'&x"866C",'1'&x"866D",'1'&x"866E",'1'&x"866F",
+--'1'&x"8670",'1'&x"8671",'1'&x"8672",'1'&x"8673",'1'&x"8674",'1'&x"8675",'1'&x"8676",'1'&x"8677",'1'&x"8678",'1'&x"8679",'1'&x"867A",'1'&x"867B",'1'&x"867C",'1'&x"867D",'1'&x"867E",'1'&x"867F",
+--'1'&x"8680",'1'&x"8681",'1'&x"8682",'1'&x"8683",'1'&x"8684",'1'&x"8685",'1'&x"8686",'1'&x"8687",'1'&x"8688",'1'&x"8689",'1'&x"868A",'1'&x"868B",'1'&x"868C",'1'&x"868D",'1'&x"868E",'1'&x"868F",
+--'1'&x"8690",'1'&x"8691",'1'&x"8692",'1'&x"8693",'1'&x"8694",'1'&x"8695",'1'&x"8696",'1'&x"8697",'1'&x"8698",'1'&x"8699",'1'&x"869A",'1'&x"869B",'1'&x"869C",'1'&x"869D",'1'&x"869E",'1'&x"869F",
+--'1'&x"86A0",'1'&x"86A1",'1'&x"86A2",'1'&x"86A3",'1'&x"86A4",'1'&x"86A5",'1'&x"86A6",'1'&x"86A7",'1'&x"86A8",'1'&x"86A9",'1'&x"86AA",'1'&x"86AB",'1'&x"86AC",'1'&x"86AD",'1'&x"86AE",'1'&x"86AF",
+--'1'&x"86B0",'1'&x"86B1",'1'&x"86B2",'1'&x"86B3",'1'&x"86B4",'1'&x"86B5",'1'&x"86B6",'1'&x"86B7",'1'&x"86B8",'1'&x"86B9",'1'&x"86BA",'1'&x"86BB",'1'&x"86BC",'1'&x"86BD",'1'&x"86BE",'1'&x"86BF",
+--'1'&x"86C0",'1'&x"86C1",'1'&x"86C2",'1'&x"86C3",'1'&x"86C4",'1'&x"86C5",'1'&x"86C6",'1'&x"86C7",'1'&x"86C8",'1'&x"86C9",'1'&x"86CA",'1'&x"86CB",'1'&x"86CC",'1'&x"86CD",'1'&x"86CE",'1'&x"86CF",
+--'1'&x"86D0",'1'&x"86D1",'1'&x"86D2",'1'&x"86D3",'1'&x"86D4",'1'&x"86D5",'1'&x"86D6",'1'&x"86D7",'1'&x"86D8",'1'&x"86D9",'1'&x"86DA",'1'&x"86DB",'1'&x"86DC",'1'&x"86DD",'1'&x"86DE",'1'&x"86DF",
+--'1'&x"86E0",'1'&x"86E1",'1'&x"86E2",'1'&x"86E3",'1'&x"86E4",'1'&x"86E5",'1'&x"86E6",'1'&x"86E7",'1'&x"86E8",'1'&x"86E9",'1'&x"86EA",'1'&x"86EB",'1'&x"86EC",'1'&x"86ED",'1'&x"86EE",'1'&x"86EF",
+--'1'&x"86F0",'1'&x"86F1",'1'&x"86F2",'1'&x"86F3",'1'&x"86F4",'1'&x"86F5",'1'&x"86F6",'1'&x"86F7",'1'&x"86F8",'1'&x"86F9",'1'&x"86FA",'1'&x"86FB",'1'&x"86FC",'1'&x"86FD",'1'&x"86FE",'1'&x"86FF",
+--'1'&x"8700",'1'&x"8701",'1'&x"8702",'1'&x"8703",'1'&x"8704",'1'&x"8705",'1'&x"8706",'1'&x"8707",'1'&x"8708",'1'&x"8709",'1'&x"870A",'1'&x"870B",'1'&x"870C",'1'&x"870D",'1'&x"870E",'1'&x"870F",
+--'1'&x"8710",'1'&x"8711",'1'&x"8712",'1'&x"8713",'1'&x"8714",'1'&x"8715",'1'&x"8716",'1'&x"8717",'1'&x"8718",'1'&x"8719",'1'&x"871A",'1'&x"871B",'1'&x"871C",'1'&x"871D",'1'&x"871E",'1'&x"871F",
+--'1'&x"8720",'1'&x"8721",'1'&x"8722",'1'&x"8723",'1'&x"8724",'1'&x"8725",'1'&x"8726",'1'&x"8727",'1'&x"8728",'1'&x"8729",'1'&x"872A",'1'&x"872B",'1'&x"872C",'1'&x"872D",'1'&x"872E",'1'&x"872F",
+--'1'&x"8730",'1'&x"8731",'1'&x"8732",'1'&x"8733",'1'&x"8734",'1'&x"8735",'1'&x"8736",'1'&x"8737",'1'&x"8738",'1'&x"8739",'1'&x"873A",'1'&x"873B",'1'&x"873C",'1'&x"873D",'1'&x"873E",'1'&x"873F",
+--'1'&x"8740",'1'&x"8741",'1'&x"8742",'1'&x"8743",'1'&x"8744",'1'&x"8745",'1'&x"8746",'1'&x"8747",'1'&x"8748",'1'&x"8749",'1'&x"874A",'1'&x"874B",'1'&x"874C",'1'&x"874D",'1'&x"874E",'1'&x"874F",
+--'1'&x"8750",'1'&x"8751",'1'&x"8752",'1'&x"8753",'1'&x"8754",'1'&x"8755",'1'&x"8756",'1'&x"8757",'1'&x"8758",'1'&x"8759",'1'&x"875A",'1'&x"875B",'1'&x"875C",'1'&x"875D",'1'&x"875E",'1'&x"875F",
+--'1'&x"8760",'1'&x"8761",'1'&x"8762",'1'&x"8763",'1'&x"8764",'1'&x"8765",'1'&x"8766",'1'&x"8767",'1'&x"8768",'1'&x"8769",'1'&x"876A",'1'&x"876B",'1'&x"876C",'1'&x"876D",'1'&x"876E",'1'&x"876F",
+--'1'&x"8770",'1'&x"8771",'1'&x"8772",'1'&x"8773",'1'&x"8774",'1'&x"8775",'1'&x"8776",'1'&x"8777",'1'&x"8778",'1'&x"8779",'1'&x"877A",'1'&x"877B",'1'&x"877C",'1'&x"877D",'1'&x"877E",'1'&x"877F",
+--'1'&x"8780",'1'&x"8781",'1'&x"8782",'1'&x"8783",'1'&x"8784",'1'&x"8785",'1'&x"8786",'1'&x"8787",'1'&x"8788",'1'&x"8789",'1'&x"878A",'1'&x"878B",'1'&x"878C",'1'&x"878D",'1'&x"878E",'1'&x"878F",
+--'1'&x"8790",'1'&x"8791",'1'&x"8792",'1'&x"8793",'1'&x"8794",'1'&x"8795",'1'&x"8796",'1'&x"8797",'1'&x"8798",'1'&x"8799",'1'&x"879A",'1'&x"879B",'1'&x"879C",'1'&x"879D",'1'&x"879E",'1'&x"879F",
+--'1'&x"87A0",'1'&x"87A1",'1'&x"87A2",'1'&x"87A3",'1'&x"87A4",'1'&x"87A5",'1'&x"87A6",'1'&x"87A7",'1'&x"87A8",'1'&x"87A9",'1'&x"87AA",'1'&x"87AB",'1'&x"87AC",'1'&x"87AD",'1'&x"87AE",'1'&x"87AF",
+--'1'&x"87B0",'1'&x"87B1",'1'&x"87B2",'1'&x"87B3",'1'&x"87B4",'1'&x"87B5",'1'&x"87B6",'1'&x"87B7",'1'&x"87B8",'1'&x"87B9",'1'&x"87BA",'1'&x"87BB",'1'&x"87BC",'1'&x"87BD",'1'&x"87BE",'1'&x"87BF",
+--'1'&x"87C0",'1'&x"87C1",'1'&x"87C2",'1'&x"87C3",'1'&x"87C4",'1'&x"87C5",'1'&x"87C6",'1'&x"87C7",'1'&x"87C8",'1'&x"87C9",'1'&x"87CA",'1'&x"87CB",'1'&x"87CC",'1'&x"87CD",'1'&x"87CE",'1'&x"87CF",
+--'1'&x"87D0",'1'&x"87D1",'1'&x"87D2",'1'&x"87D3",'1'&x"87D4",'1'&x"87D5",'1'&x"87D6",'1'&x"87D7",'1'&x"87D8",'1'&x"87D9",'1'&x"87DA",'1'&x"87DB",'1'&x"87DC",'1'&x"87DD",'1'&x"87DE",'1'&x"87DF",
+--'1'&x"87E0",'1'&x"87E1",'1'&x"87E2",'1'&x"87E3",'1'&x"87E4",'1'&x"87E5",'1'&x"87E6",'1'&x"87E7",'1'&x"87E8",'1'&x"87E9",'1'&x"87EA",'1'&x"87EB",'1'&x"87EC",'1'&x"87ED",'1'&x"87EE",'1'&x"87EF",
+--'1'&x"87F0",'1'&x"87F1",'1'&x"87F2",'1'&x"87F3",'1'&x"87F4",'1'&x"87F5",'1'&x"87F6",'1'&x"87F7",'1'&x"87F8",'1'&x"87F9",'1'&x"87FA",'1'&x"87FB",'1'&x"87FC",'1'&x"87FD",'1'&x"87FE",'1'&x"87FF",
+--'1'&x"8800",'1'&x"8801",'1'&x"8802",'1'&x"8803",'1'&x"8804",'1'&x"8805",'1'&x"8806",'1'&x"8807",'1'&x"8808",'1'&x"8809",'1'&x"880A",'1'&x"880B",'1'&x"880C",'1'&x"880D",'1'&x"880E",'1'&x"880F",
+--'1'&x"8810",'1'&x"8811",'1'&x"8812",'1'&x"8813",'1'&x"8814",'1'&x"8815",'1'&x"8816",'1'&x"8817",'1'&x"8818",'1'&x"8819",'1'&x"881A",'1'&x"881B",'1'&x"881C",'1'&x"881D",'1'&x"881E",'1'&x"881F",
+--'1'&x"8820",'1'&x"8821",'1'&x"8822",'1'&x"8823",'1'&x"8824",'1'&x"8825",'1'&x"8826",'1'&x"8827",'1'&x"8828",'1'&x"8829",'1'&x"882A",'1'&x"882B",'1'&x"882C",'1'&x"882D",'1'&x"882E",'1'&x"882F",
+--'1'&x"8830",'1'&x"8831",'1'&x"8832",'1'&x"8833",'1'&x"8834",'1'&x"8835",'1'&x"8836",'1'&x"8837",'1'&x"8838",'1'&x"8839",'1'&x"883A",'1'&x"883B",'1'&x"883C",'1'&x"883D",'1'&x"883E",'1'&x"883F",
+--'1'&x"8840",'1'&x"8841",'1'&x"8842",'1'&x"8843",'1'&x"8844",'1'&x"8845",'1'&x"8846",'1'&x"8847",'1'&x"8848",'1'&x"8849",'1'&x"884A",'1'&x"884B",'1'&x"884C",'1'&x"884D",'1'&x"884E",'1'&x"884F",
+--'1'&x"8850",'1'&x"8851",'1'&x"8852",'1'&x"8853",'1'&x"8854",'1'&x"8855",'1'&x"8856",'1'&x"8857",'1'&x"8858",'1'&x"8859",'1'&x"885A",'1'&x"885B",'1'&x"885C",'1'&x"885D",'1'&x"885E",'1'&x"885F",
+--'1'&x"8860",'1'&x"8861",'1'&x"8862",'1'&x"8863",'1'&x"8864",'1'&x"8865",'1'&x"8866",'1'&x"8867",'1'&x"8868",'1'&x"8869",'1'&x"886A",'1'&x"886B",'1'&x"886C",'1'&x"886D",'1'&x"886E",'1'&x"886F",
+--'1'&x"8870",'1'&x"8871",'1'&x"8872",'1'&x"8873",'1'&x"8874",'1'&x"8875",'1'&x"8876",'1'&x"8877",'1'&x"8878",'1'&x"8879",'1'&x"887A",'1'&x"887B",'1'&x"887C",'1'&x"887D",'1'&x"887E",'1'&x"887F",
+--'1'&x"8880",'1'&x"8881",'1'&x"8882",'1'&x"8883",'1'&x"8884",'1'&x"8885",'1'&x"8886",'1'&x"8887",'1'&x"8888",'1'&x"8889",'1'&x"888A",'1'&x"888B",'1'&x"888C",'1'&x"888D",'1'&x"888E",'1'&x"888F",
+--'1'&x"8890",'1'&x"8891",'1'&x"8892",'1'&x"8893",'1'&x"8894",'1'&x"8895",'1'&x"8896",'1'&x"8897",'1'&x"8898",'1'&x"8899",'1'&x"889A",'1'&x"889B",'1'&x"889C",'1'&x"889D",'1'&x"889E",'1'&x"889F",
+--'1'&x"88A0",'1'&x"88A1",'1'&x"88A2",'1'&x"88A3",'1'&x"88A4",'1'&x"88A5",'1'&x"88A6",'1'&x"88A7",'1'&x"88A8",'1'&x"88A9",'1'&x"88AA",'1'&x"88AB",'1'&x"88AC",'1'&x"88AD",'1'&x"88AE",'1'&x"88AF",
+--'1'&x"88B0",'1'&x"88B1",'1'&x"88B2",'1'&x"88B3",'1'&x"88B4",'1'&x"88B5",'1'&x"88B6",'1'&x"88B7",'1'&x"88B8",'1'&x"88B9",'1'&x"88BA",'1'&x"88BB",'1'&x"88BC",'1'&x"88BD",'1'&x"88BE",'1'&x"88BF",
+--'1'&x"88C0",'1'&x"88C1",'1'&x"88C2",'1'&x"88C3",'1'&x"88C4",'1'&x"88C5",'1'&x"88C6",'1'&x"88C7",'1'&x"88C8",'1'&x"88C9",'1'&x"88CA",'1'&x"88CB",'1'&x"88CC",'1'&x"88CD",'1'&x"88CE",'1'&x"88CF",
+--'1'&x"88D0",'1'&x"88D1",'1'&x"88D2",'1'&x"88D3",'1'&x"88D4",'1'&x"88D5",'1'&x"88D6",'1'&x"88D7",'1'&x"88D8",'1'&x"88D9",'1'&x"88DA",'1'&x"88DB",'1'&x"88DC",'1'&x"88DD",'1'&x"88DE",'1'&x"88DF",
+--'1'&x"88E0",'1'&x"88E1",'1'&x"88E2",'1'&x"88E3",'1'&x"88E4",'1'&x"88E5",'1'&x"88E6",'1'&x"88E7",'1'&x"88E8",'1'&x"88E9",'1'&x"88EA",'1'&x"88EB",'1'&x"88EC",'1'&x"88ED",'1'&x"88EE",'1'&x"88EF",
+--'1'&x"88F0",'1'&x"88F1",'1'&x"88F2",'1'&x"88F3",'1'&x"88F4",'1'&x"88F5",'1'&x"88F6",'1'&x"88F7",'1'&x"88F8",'1'&x"88F9",'1'&x"88FA",'1'&x"88FB",'1'&x"88FC",'1'&x"88FD",'1'&x"88FE",'1'&x"88FF",
+--'1'&x"8900",'1'&x"8901",'1'&x"8902",'1'&x"8903",'1'&x"8904",'1'&x"8905",'1'&x"8906",'1'&x"8907",'1'&x"8908",'1'&x"8909",'1'&x"890A",'1'&x"890B",'1'&x"890C",'1'&x"890D",'1'&x"890E",'1'&x"890F",
+--'1'&x"8910",'1'&x"8911",'1'&x"8912",'1'&x"8913",'1'&x"8914",'1'&x"8915",'1'&x"8916",'1'&x"8917",'1'&x"8918",'1'&x"8919",'1'&x"891A",'1'&x"891B",'1'&x"891C",'1'&x"891D",'1'&x"891E",'1'&x"891F",
+--'1'&x"8920",'1'&x"8921",'1'&x"8922",'1'&x"8923",'1'&x"8924",'1'&x"8925",'1'&x"8926",'1'&x"8927",'1'&x"8928",'1'&x"8929",'1'&x"892A",'1'&x"892B",'1'&x"892C",'1'&x"892D",'1'&x"892E",'1'&x"892F",
+--'1'&x"8930",'1'&x"8931",'1'&x"8932",'1'&x"8933",'1'&x"8934",'1'&x"8935",'1'&x"8936",'1'&x"8937",'1'&x"8938",'1'&x"8939",'1'&x"893A",'1'&x"893B",'1'&x"893C",'1'&x"893D",'1'&x"893E",'1'&x"893F",
+--'1'&x"8940",'1'&x"8941",'1'&x"8942",'1'&x"8943",'1'&x"8944",'1'&x"8945",'1'&x"8946",'1'&x"8947",'1'&x"8948",'1'&x"8949",'1'&x"894A",'1'&x"894B",'1'&x"894C",'1'&x"894D",'1'&x"894E",'1'&x"894F",
+--'1'&x"8950",'1'&x"8951",'1'&x"8952",'1'&x"8953",'1'&x"8954",'1'&x"8955",'1'&x"8956",'1'&x"8957",'1'&x"8958",'1'&x"8959",'1'&x"895A",'1'&x"895B",'1'&x"895C",'1'&x"895D",'1'&x"895E",'1'&x"895F",
+--'1'&x"8960",'1'&x"8961",'1'&x"8962",'1'&x"8963",'1'&x"8964",'1'&x"8965",'1'&x"8966",'1'&x"8967",'1'&x"8968",'1'&x"8969",'1'&x"896A",'1'&x"896B",'1'&x"896C",'1'&x"896D",'1'&x"896E",'1'&x"896F",
+--'1'&x"8970",'1'&x"8971",'1'&x"8972",'1'&x"8973",'1'&x"8974",'1'&x"8975",'1'&x"8976",'1'&x"8977",'1'&x"8978",'1'&x"8979",'1'&x"897A",'1'&x"897B",'1'&x"897C",'1'&x"897D",'1'&x"897E",'1'&x"897F",
+--'1'&x"8980",'1'&x"8981",'1'&x"8982",'1'&x"8983",'1'&x"8984",'1'&x"8985",'1'&x"8986",'1'&x"8987",'1'&x"8988",'1'&x"8989",'1'&x"898A",'1'&x"898B",'1'&x"898C",'1'&x"898D",'1'&x"898E",'1'&x"898F",
+--'1'&x"8990",'1'&x"8991",'1'&x"8992",'1'&x"8993",'1'&x"8994",'1'&x"8995",'1'&x"8996",'1'&x"8997",'1'&x"8998",'1'&x"8999",'1'&x"899A",'1'&x"899B",'1'&x"899C",'1'&x"899D",'1'&x"899E",'1'&x"899F",
+--'1'&x"89A0",'1'&x"89A1",'1'&x"89A2",'1'&x"89A3",'1'&x"89A4",'1'&x"89A5",'1'&x"89A6",'1'&x"89A7",'1'&x"89A8",'1'&x"89A9",'1'&x"89AA",'1'&x"89AB",'1'&x"89AC",'1'&x"89AD",'1'&x"89AE",'1'&x"89AF",
+--'1'&x"89B0",'1'&x"89B1",'1'&x"89B2",'1'&x"89B3",'1'&x"89B4",'1'&x"89B5",'1'&x"89B6",'1'&x"89B7",'1'&x"89B8",'1'&x"89B9",'1'&x"89BA",'1'&x"89BB",'1'&x"89BC",'1'&x"89BD",'1'&x"89BE",'1'&x"89BF",
+--'1'&x"89C0",'1'&x"89C1",'1'&x"89C2",'1'&x"89C3",'1'&x"89C4",'1'&x"89C5",'1'&x"89C6",'1'&x"89C7",'1'&x"89C8",'1'&x"89C9",'1'&x"89CA",'1'&x"89CB",'1'&x"89CC",'1'&x"89CD",'1'&x"89CE",'1'&x"89CF",
+--'1'&x"89D0",'1'&x"89D1",'1'&x"89D2",'1'&x"89D3",'1'&x"89D4",'1'&x"89D5",'1'&x"89D6",'1'&x"89D7",'1'&x"89D8",'1'&x"89D9",'1'&x"89DA",'1'&x"89DB",'1'&x"89DC",'1'&x"89DD",'1'&x"89DE",'1'&x"89DF",
+--'1'&x"89E0",'1'&x"89E1",'1'&x"89E2",'1'&x"89E3",'1'&x"89E4",'1'&x"89E5",'1'&x"89E6",'1'&x"89E7",'1'&x"89E8",'1'&x"89E9",'1'&x"89EA",'1'&x"89EB",'1'&x"89EC",'1'&x"89ED",'1'&x"89EE",'1'&x"89EF",
+--'1'&x"89F0",'1'&x"89F1",'1'&x"89F2",'1'&x"89F3",'1'&x"89F4",'1'&x"89F5",'1'&x"89F6",'1'&x"89F7",'1'&x"89F8",'1'&x"89F9",'1'&x"89FA",'1'&x"89FB",'1'&x"89FC",'1'&x"89FD",'1'&x"89FE",'1'&x"89FF",
+--'1'&x"8A00",'1'&x"8A01",'1'&x"8A02",'1'&x"8A03",'1'&x"8A04",'1'&x"8A05",'1'&x"8A06",'1'&x"8A07",'1'&x"8A08",'1'&x"8A09",'1'&x"8A0A",'1'&x"8A0B",'1'&x"8A0C",'1'&x"8A0D",'1'&x"8A0E",'1'&x"8A0F",
+--'1'&x"8A10",'1'&x"8A11",'1'&x"8A12",'1'&x"8A13",'1'&x"8A14",'1'&x"8A15",'1'&x"8A16",'1'&x"8A17",'1'&x"8A18",'1'&x"8A19",'1'&x"8A1A",'1'&x"8A1B",'1'&x"8A1C",'1'&x"8A1D",'1'&x"8A1E",'1'&x"8A1F",
+--'1'&x"8A20",'1'&x"8A21",'1'&x"8A22",'1'&x"8A23",'1'&x"8A24",'1'&x"8A25",'1'&x"8A26",'1'&x"8A27",'1'&x"8A28",'1'&x"8A29",'1'&x"8A2A",'1'&x"8A2B",'1'&x"8A2C",'1'&x"8A2D",'1'&x"8A2E",'1'&x"8A2F",
+--'1'&x"8A30",'1'&x"8A31",'1'&x"8A32",'1'&x"8A33",'1'&x"8A34",'1'&x"8A35",'1'&x"8A36",'1'&x"8A37",'1'&x"8A38",'1'&x"8A39",'1'&x"8A3A",'1'&x"8A3B",'1'&x"8A3C",'1'&x"8A3D",'1'&x"8A3E",'1'&x"8A3F",
+--'1'&x"8A40",'1'&x"8A41",'1'&x"8A42",'1'&x"8A43",'1'&x"8A44",'1'&x"8A45",'1'&x"8A46",'1'&x"8A47",'1'&x"8A48",'1'&x"8A49",'1'&x"8A4A",'1'&x"8A4B",'1'&x"8A4C",'1'&x"8A4D",'1'&x"8A4E",'1'&x"8A4F",
+--'1'&x"8A50",'1'&x"8A51",'1'&x"8A52",'1'&x"8A53",'1'&x"8A54",'1'&x"8A55",'1'&x"8A56",'1'&x"8A57",'1'&x"8A58",'1'&x"8A59",'1'&x"8A5A",'1'&x"8A5B",'1'&x"8A5C",'1'&x"8A5D",'1'&x"8A5E",'1'&x"8A5F",
+--'1'&x"8A60",'1'&x"8A61",'1'&x"8A62",'1'&x"8A63",'1'&x"8A64",'1'&x"8A65",'1'&x"8A66",'1'&x"8A67",'1'&x"8A68",'1'&x"8A69",'1'&x"8A6A",'1'&x"8A6B",'1'&x"8A6C",'1'&x"8A6D",'1'&x"8A6E",'1'&x"8A6F",
+--'1'&x"8A70",'1'&x"8A71",'1'&x"8A72",'1'&x"8A73",'1'&x"8A74",'1'&x"8A75",'1'&x"8A76",'1'&x"8A77",'1'&x"8A78",'1'&x"8A79",'1'&x"8A7A",'1'&x"8A7B",'1'&x"8A7C",'1'&x"8A7D",'1'&x"8A7E",'1'&x"8A7F",
+--'1'&x"8A80",'1'&x"8A81",'1'&x"8A82",'1'&x"8A83",'1'&x"8A84",'1'&x"8A85",'1'&x"8A86",'1'&x"8A87",'1'&x"8A88",'1'&x"8A89",'1'&x"8A8A",'1'&x"8A8B",'1'&x"8A8C",'1'&x"8A8D",'1'&x"8A8E",'1'&x"8A8F",
+--'1'&x"8A90",'1'&x"8A91",'1'&x"8A92",'1'&x"8A93",'1'&x"8A94",'1'&x"8A95",'1'&x"8A96",'1'&x"8A97",'1'&x"8A98",'1'&x"8A99",'1'&x"8A9A",'1'&x"8A9B",'1'&x"8A9C",'1'&x"8A9D",'1'&x"8A9E",'1'&x"8A9F",
+--'1'&x"8AA0",'1'&x"8AA1",'1'&x"8AA2",'1'&x"8AA3",'1'&x"8AA4",'1'&x"8AA5",'1'&x"8AA6",'1'&x"8AA7",'1'&x"8AA8",'1'&x"8AA9",'1'&x"8AAA",'1'&x"8AAB",'1'&x"8AAC",'1'&x"8AAD",'1'&x"8AAE",'1'&x"8AAF",
+--'1'&x"8AB0",'1'&x"8AB1",'1'&x"8AB2",'1'&x"8AB3",'1'&x"8AB4",'1'&x"8AB5",'1'&x"8AB6",'1'&x"8AB7",'1'&x"8AB8",'1'&x"8AB9",'1'&x"8ABA",'1'&x"8ABB",'1'&x"8ABC",'1'&x"8ABD",'1'&x"8ABE",'1'&x"8ABF",
+--'1'&x"8AC0",'1'&x"8AC1",'1'&x"8AC2",'1'&x"8AC3",'1'&x"8AC4",'1'&x"8AC5",'1'&x"8AC6",'1'&x"8AC7",'1'&x"8AC8",'1'&x"8AC9",'1'&x"8ACA",'1'&x"8ACB",'1'&x"8ACC",'1'&x"8ACD",'1'&x"8ACE",'1'&x"8ACF",
+--'1'&x"8AD0",'1'&x"8AD1",'1'&x"8AD2",'1'&x"8AD3",'1'&x"8AD4",'1'&x"8AD5",'1'&x"8AD6",'1'&x"8AD7",'1'&x"8AD8",'1'&x"8AD9",'1'&x"8ADA",'1'&x"8ADB",'1'&x"8ADC",'1'&x"8ADD",'1'&x"8ADE",'1'&x"8ADF",
+--'1'&x"8AE0",'1'&x"8AE1",'1'&x"8AE2",'1'&x"8AE3",'1'&x"8AE4",'1'&x"8AE5",'1'&x"8AE6",'1'&x"8AE7",'1'&x"8AE8",'1'&x"8AE9",'1'&x"8AEA",'1'&x"8AEB",'1'&x"8AEC",'1'&x"8AED",'1'&x"8AEE",'1'&x"8AEF",
+--'1'&x"8AF0",'1'&x"8AF1",'1'&x"8AF2",'1'&x"8AF3",'1'&x"8AF4",'1'&x"8AF5",'1'&x"8AF6",'1'&x"8AF7",'1'&x"8AF8",'1'&x"8AF9",'1'&x"8AFA",'1'&x"8AFB",'1'&x"8AFC",'1'&x"8AFD",'1'&x"8AFE",'1'&x"8AFF",
+--'1'&x"8B00",'1'&x"8B01",'1'&x"8B02",'1'&x"8B03",'1'&x"8B04",'1'&x"8B05",'1'&x"8B06",'1'&x"8B07",'1'&x"8B08",'1'&x"8B09",'1'&x"8B0A",'1'&x"8B0B",'1'&x"8B0C",'1'&x"8B0D",'1'&x"8B0E",'1'&x"8B0F",
+--'1'&x"8B10",'1'&x"8B11",'1'&x"8B12",'1'&x"8B13",'1'&x"8B14",'1'&x"8B15",'1'&x"8B16",'1'&x"8B17",'1'&x"8B18",'1'&x"8B19",'1'&x"8B1A",'1'&x"8B1B",'1'&x"8B1C",'1'&x"8B1D",'1'&x"8B1E",'1'&x"8B1F",
+--'1'&x"8B20",'1'&x"8B21",'1'&x"8B22",'1'&x"8B23",'1'&x"8B24",'1'&x"8B25",'1'&x"8B26",'1'&x"8B27",'1'&x"8B28",'1'&x"8B29",'1'&x"8B2A",'1'&x"8B2B",'1'&x"8B2C",'1'&x"8B2D",'1'&x"8B2E",'1'&x"8B2F",
+--'1'&x"8B30",'1'&x"8B31",'1'&x"8B32",'1'&x"8B33",'1'&x"8B34",'1'&x"8B35",'1'&x"8B36",'1'&x"8B37",'1'&x"8B38",'1'&x"8B39",'1'&x"8B3A",'1'&x"8B3B",'1'&x"8B3C",'1'&x"8B3D",'1'&x"8B3E",'1'&x"8B3F",
+--'1'&x"8B40",'1'&x"8B41",'1'&x"8B42",'1'&x"8B43",'1'&x"8B44",'1'&x"8B45",'1'&x"8B46",'1'&x"8B47",'1'&x"8B48",'1'&x"8B49",'1'&x"8B4A",'1'&x"8B4B",'1'&x"8B4C",'1'&x"8B4D",'1'&x"8B4E",'1'&x"8B4F",
+--'1'&x"8B50",'1'&x"8B51",'1'&x"8B52",'1'&x"8B53",'1'&x"8B54",'1'&x"8B55",'1'&x"8B56",'1'&x"8B57",'1'&x"8B58",'1'&x"8B59",'1'&x"8B5A",'1'&x"8B5B",'1'&x"8B5C",'1'&x"8B5D",'1'&x"8B5E",'1'&x"8B5F",
+--'1'&x"8B60",'1'&x"8B61",'1'&x"8B62",'1'&x"8B63",'1'&x"8B64",'1'&x"8B65",'1'&x"8B66",'1'&x"8B67",'1'&x"8B68",'1'&x"8B69",'1'&x"8B6A",'1'&x"8B6B",'1'&x"8B6C",'1'&x"8B6D",'1'&x"8B6E",'1'&x"8B6F",
+--'1'&x"8B70",'1'&x"8B71",'1'&x"8B72",'1'&x"8B73",'1'&x"8B74",'1'&x"8B75",'1'&x"8B76",'1'&x"8B77",'1'&x"8B78",'1'&x"8B79",'1'&x"8B7A",'1'&x"8B7B",'1'&x"8B7C",'1'&x"8B7D",'1'&x"8B7E",'1'&x"8B7F",
+--'1'&x"8B80",'1'&x"8B81",'1'&x"8B82",'1'&x"8B83",'1'&x"8B84",'1'&x"8B85",'1'&x"8B86",'1'&x"8B87",'1'&x"8B88",'1'&x"8B89",'1'&x"8B8A",'1'&x"8B8B",'1'&x"8B8C",'1'&x"8B8D",'1'&x"8B8E",'1'&x"8B8F",
+--'1'&x"8B90",'1'&x"8B91",'1'&x"8B92",'1'&x"8B93",'1'&x"8B94",'1'&x"8B95",'1'&x"8B96",'1'&x"8B97",'1'&x"8B98",'1'&x"8B99",'1'&x"8B9A",'1'&x"8B9B",'1'&x"8B9C",'1'&x"8B9D",'1'&x"8B9E",'1'&x"8B9F",
+--'1'&x"8BA0",'1'&x"8BA1",'1'&x"8BA2",'1'&x"8BA3",'1'&x"8BA4",'1'&x"8BA5",'1'&x"8BA6",'1'&x"8BA7",'1'&x"8BA8",'1'&x"8BA9",'1'&x"8BAA",'1'&x"8BAB",'1'&x"8BAC",'1'&x"8BAD",'1'&x"8BAE",'1'&x"8BAF",
+--'1'&x"8BB0",'1'&x"8BB1",'1'&x"8BB2",'1'&x"8BB3",'1'&x"8BB4",'1'&x"8BB5",'1'&x"8BB6",'1'&x"8BB7",'1'&x"8BB8",'1'&x"8BB9",'1'&x"8BBA",'1'&x"8BBB",'1'&x"8BBC",'1'&x"8BBD",'1'&x"8BBE",'1'&x"8BBF",
+--'1'&x"8BC0",'1'&x"8BC1",'1'&x"8BC2",'1'&x"8BC3",'1'&x"8BC4",'1'&x"8BC5",'1'&x"8BC6",'1'&x"8BC7",'1'&x"8BC8",'1'&x"8BC9",'1'&x"8BCA",'1'&x"8BCB",'1'&x"8BCC",'1'&x"8BCD",'1'&x"8BCE",'1'&x"8BCF",
+--'1'&x"8BD0",'1'&x"8BD1",'1'&x"8BD2",'1'&x"8BD3",'1'&x"8BD4",'1'&x"8BD5",'1'&x"8BD6",'1'&x"8BD7",'1'&x"8BD8",'1'&x"8BD9",'1'&x"8BDA",'1'&x"8BDB",'1'&x"8BDC",'1'&x"8BDD",'1'&x"8BDE",'1'&x"8BDF",
+--'1'&x"8BE0",'1'&x"8BE1",'1'&x"8BE2",'1'&x"8BE3",'1'&x"8BE4",'1'&x"8BE5",'1'&x"8BE6",'1'&x"8BE7",'1'&x"8BE8",'1'&x"8BE9",'1'&x"8BEA",'1'&x"8BEB",'1'&x"8BEC",'1'&x"8BED",'1'&x"8BEE",'1'&x"8BEF",
+--'1'&x"8BF0",'1'&x"8BF1",'1'&x"8BF2",'1'&x"8BF3",'1'&x"8BF4",'1'&x"8BF5",'1'&x"8BF6",'1'&x"8BF7",'1'&x"8BF8",'1'&x"8BF9",'1'&x"8BFA",'1'&x"8BFB",'1'&x"8BFC",'1'&x"8BFD",'1'&x"8BFE",'1'&x"8BFF",
+--'1'&x"8C00",'1'&x"8C01",'1'&x"8C02",'1'&x"8C03",'1'&x"8C04",'1'&x"8C05",'1'&x"8C06",'1'&x"8C07",'1'&x"8C08",'1'&x"8C09",'1'&x"8C0A",'1'&x"8C0B",'1'&x"8C0C",'1'&x"8C0D",'1'&x"8C0E",'1'&x"8C0F",
+--'1'&x"8C10",'1'&x"8C11",'1'&x"8C12",'1'&x"8C13",'1'&x"8C14",'1'&x"8C15",'1'&x"8C16",'1'&x"8C17",'1'&x"8C18",'1'&x"8C19",'1'&x"8C1A",'1'&x"8C1B",'1'&x"8C1C",'1'&x"8C1D",'1'&x"8C1E",'1'&x"8C1F",
+--'1'&x"8C20",'1'&x"8C21",'1'&x"8C22",'1'&x"8C23",'1'&x"8C24",'1'&x"8C25",'1'&x"8C26",'1'&x"8C27",'1'&x"8C28",'1'&x"8C29",'1'&x"8C2A",'1'&x"8C2B",'1'&x"8C2C",'1'&x"8C2D",'1'&x"8C2E",'1'&x"8C2F",
+--'1'&x"8C30",'1'&x"8C31",'1'&x"8C32",'1'&x"8C33",'1'&x"8C34",'1'&x"8C35",'1'&x"8C36",'1'&x"8C37",'1'&x"8C38",'1'&x"8C39",'1'&x"8C3A",'1'&x"8C3B",'1'&x"8C3C",'1'&x"8C3D",'1'&x"8C3E",'1'&x"8C3F",
+--'1'&x"8C40",'1'&x"8C41",'1'&x"8C42",'1'&x"8C43",'1'&x"8C44",'1'&x"8C45",'1'&x"8C46",'1'&x"8C47",'1'&x"8C48",'1'&x"8C49",'1'&x"8C4A",'1'&x"8C4B",'1'&x"8C4C",'1'&x"8C4D",'1'&x"8C4E",'1'&x"8C4F",
+--'1'&x"8C50",'1'&x"8C51",'1'&x"8C52",'1'&x"8C53",'1'&x"8C54",'1'&x"8C55",'1'&x"8C56",'1'&x"8C57",'1'&x"8C58",'1'&x"8C59",'1'&x"8C5A",'1'&x"8C5B",'1'&x"8C5C",'1'&x"8C5D",'1'&x"8C5E",'1'&x"8C5F",
+--'1'&x"8C60",'1'&x"8C61",'1'&x"8C62",'1'&x"8C63",'1'&x"8C64",'1'&x"8C65",'1'&x"8C66",'1'&x"8C67",'1'&x"8C68",'1'&x"8C69",'1'&x"8C6A",'1'&x"8C6B",'1'&x"8C6C",'1'&x"8C6D",'1'&x"8C6E",'1'&x"8C6F",
+--'1'&x"8C70",'1'&x"8C71",'1'&x"8C72",'1'&x"8C73",'1'&x"8C74",'1'&x"8C75",'1'&x"8C76",'1'&x"8C77",'1'&x"8C78",'1'&x"8C79",'1'&x"8C7A",'1'&x"8C7B",'1'&x"8C7C",'1'&x"8C7D",'1'&x"8C7E",'1'&x"8C7F",
+--'1'&x"8C80",'1'&x"8C81",'1'&x"8C82",'1'&x"8C83",'1'&x"8C84",'1'&x"8C85",'1'&x"8C86",'1'&x"8C87",'1'&x"8C88",'1'&x"8C89",'1'&x"8C8A",'1'&x"8C8B",'1'&x"8C8C",'1'&x"8C8D",'1'&x"8C8E",'1'&x"8C8F",
+--'1'&x"8C90",'1'&x"8C91",'1'&x"8C92",'1'&x"8C93",'1'&x"8C94",'1'&x"8C95",'1'&x"8C96",'1'&x"8C97",'1'&x"8C98",'1'&x"8C99",'1'&x"8C9A",'1'&x"8C9B",'1'&x"8C9C",'1'&x"8C9D",'1'&x"8C9E",'1'&x"8C9F",
+--'1'&x"8CA0",'1'&x"8CA1",'1'&x"8CA2",'1'&x"8CA3",'1'&x"8CA4",'1'&x"8CA5",'1'&x"8CA6",'1'&x"8CA7",'1'&x"8CA8",'1'&x"8CA9",'1'&x"8CAA",'1'&x"8CAB",'1'&x"8CAC",'1'&x"8CAD",'1'&x"8CAE",'1'&x"8CAF",
+--'1'&x"8CB0",'1'&x"8CB1",'1'&x"8CB2",'1'&x"8CB3",'1'&x"8CB4",'1'&x"8CB5",'1'&x"8CB6",'1'&x"8CB7",'1'&x"8CB8",'1'&x"8CB9",'1'&x"8CBA",'1'&x"8CBB",'1'&x"8CBC",'1'&x"8CBD",'1'&x"8CBE",'1'&x"8CBF",
+--'1'&x"8CC0",'1'&x"8CC1",'1'&x"8CC2",'1'&x"8CC3",'1'&x"8CC4",'1'&x"8CC5",'1'&x"8CC6",'1'&x"8CC7",'1'&x"8CC8",'1'&x"8CC9",'1'&x"8CCA",'1'&x"8CCB",'1'&x"8CCC",'1'&x"8CCD",'1'&x"8CCE",'1'&x"8CCF",
+--'1'&x"8CD0",'1'&x"8CD1",'1'&x"8CD2",'1'&x"8CD3",'1'&x"8CD4",'1'&x"8CD5",'1'&x"8CD6",'1'&x"8CD7",'1'&x"8CD8",'1'&x"8CD9",'1'&x"8CDA",'1'&x"8CDB",'1'&x"8CDC",'1'&x"8CDD",'1'&x"8CDE",'1'&x"8CDF",
+--'1'&x"8CE0",'1'&x"8CE1",'1'&x"8CE2",'1'&x"8CE3",'1'&x"8CE4",'1'&x"8CE5",'1'&x"8CE6",'1'&x"8CE7",'1'&x"8CE8",'1'&x"8CE9",'1'&x"8CEA",'1'&x"8CEB",'1'&x"8CEC",'1'&x"8CED",'1'&x"8CEE",'1'&x"8CEF",
+--'1'&x"8CF0",'1'&x"8CF1",'1'&x"8CF2",'1'&x"8CF3",'1'&x"8CF4",'1'&x"8CF5",'1'&x"8CF6",'1'&x"8CF7",'1'&x"8CF8",'1'&x"8CF9",'1'&x"8CFA",'1'&x"8CFB",'1'&x"8CFC",'1'&x"8CFD",'1'&x"8CFE",'1'&x"8CFF",
+--'1'&x"8D00",'1'&x"8D01",'1'&x"8D02",'1'&x"8D03",'1'&x"8D04",'1'&x"8D05",'1'&x"8D06",'1'&x"8D07",'1'&x"8D08",'1'&x"8D09",'1'&x"8D0A",'1'&x"8D0B",'1'&x"8D0C",'1'&x"8D0D",'1'&x"8D0E",'1'&x"8D0F",
+--'1'&x"8D10",'1'&x"8D11",'1'&x"8D12",'1'&x"8D13",'1'&x"8D14",'1'&x"8D15",'1'&x"8D16",'1'&x"8D17",'1'&x"8D18",'1'&x"8D19",'1'&x"8D1A",'1'&x"8D1B",'1'&x"8D1C",'1'&x"8D1D",'1'&x"8D1E",'1'&x"8D1F",
+--'1'&x"8D20",'1'&x"8D21",'1'&x"8D22",'1'&x"8D23",'1'&x"8D24",'1'&x"8D25",'1'&x"8D26",'1'&x"8D27",'1'&x"8D28",'1'&x"8D29",'1'&x"8D2A",'1'&x"8D2B",'1'&x"8D2C",'1'&x"8D2D",'1'&x"8D2E",'1'&x"8D2F",
+--'1'&x"8D30",'1'&x"8D31",'1'&x"8D32",'1'&x"8D33",'1'&x"8D34",'1'&x"8D35",'1'&x"8D36",'1'&x"8D37",'1'&x"8D38",'1'&x"8D39",'1'&x"8D3A",'1'&x"8D3B",'1'&x"8D3C",'1'&x"8D3D",'1'&x"8D3E",'1'&x"8D3F",
+--'1'&x"8D40",'1'&x"8D41",'1'&x"8D42",'1'&x"8D43",'1'&x"8D44",'1'&x"8D45",'1'&x"8D46",'1'&x"8D47",'1'&x"8D48",'1'&x"8D49",'1'&x"8D4A",'1'&x"8D4B",'1'&x"8D4C",'1'&x"8D4D",'1'&x"8D4E",'1'&x"8D4F",
+--'1'&x"8D50",'1'&x"8D51",'1'&x"8D52",'1'&x"8D53",'1'&x"8D54",'1'&x"8D55",'1'&x"8D56",'1'&x"8D57",'1'&x"8D58",'1'&x"8D59",'1'&x"8D5A",'1'&x"8D5B",'1'&x"8D5C",'1'&x"8D5D",'1'&x"8D5E",'1'&x"8D5F",
+--'1'&x"8D60",'1'&x"8D61",'1'&x"8D62",'1'&x"8D63",'1'&x"8D64",'1'&x"8D65",'1'&x"8D66",'1'&x"8D67",'1'&x"8D68",'1'&x"8D69",'1'&x"8D6A",'1'&x"8D6B",'1'&x"8D6C",'1'&x"8D6D",'1'&x"8D6E",'1'&x"8D6F",
+--'1'&x"8D70",'1'&x"8D71",'1'&x"8D72",'1'&x"8D73",'1'&x"8D74",'1'&x"8D75",'1'&x"8D76",'1'&x"8D77",'1'&x"8D78",'1'&x"8D79",'1'&x"8D7A",'1'&x"8D7B",'1'&x"8D7C",'1'&x"8D7D",'1'&x"8D7E",'1'&x"8D7F",
+--'1'&x"8D80",'1'&x"8D81",'1'&x"8D82",'1'&x"8D83",'1'&x"8D84",'1'&x"8D85",'1'&x"8D86",'1'&x"8D87",'1'&x"8D88",'1'&x"8D89",'1'&x"8D8A",'1'&x"8D8B",'1'&x"8D8C",'1'&x"8D8D",'1'&x"8D8E",'1'&x"8D8F",
+--'1'&x"8D90",'1'&x"8D91",'1'&x"8D92",'1'&x"8D93",'1'&x"8D94",'1'&x"8D95",'1'&x"8D96",'1'&x"8D97",'1'&x"8D98",'1'&x"8D99",'1'&x"8D9A",'1'&x"8D9B",'1'&x"8D9C",'1'&x"8D9D",'1'&x"8D9E",'1'&x"8D9F",
+--'1'&x"8DA0",'1'&x"8DA1",'1'&x"8DA2",'1'&x"8DA3",'1'&x"8DA4",'1'&x"8DA5",'1'&x"8DA6",'1'&x"8DA7",'1'&x"8DA8",'1'&x"8DA9",'1'&x"8DAA",'1'&x"8DAB",'1'&x"8DAC",'1'&x"8DAD",'1'&x"8DAE",'1'&x"8DAF",
+--'1'&x"8DB0",'1'&x"8DB1",'1'&x"8DB2",'1'&x"8DB3",'1'&x"8DB4",'1'&x"8DB5",'1'&x"8DB6",'1'&x"8DB7",'1'&x"8DB8",'1'&x"8DB9",'1'&x"8DBA",'1'&x"8DBB",'1'&x"8DBC",'1'&x"8DBD",'1'&x"8DBE",'1'&x"8DBF",
+--'1'&x"8DC0",'1'&x"8DC1",'1'&x"8DC2",'1'&x"8DC3",'1'&x"8DC4",'1'&x"8DC5",'1'&x"8DC6",'1'&x"8DC7",'1'&x"8DC8",'1'&x"8DC9",'1'&x"8DCA",'1'&x"8DCB",'1'&x"8DCC",'1'&x"8DCD",'1'&x"8DCE",'1'&x"8DCF",
+--'1'&x"8DD0",'1'&x"8DD1",'1'&x"8DD2",'1'&x"8DD3",'1'&x"8DD4",'1'&x"8DD5",'1'&x"8DD6",'1'&x"8DD7",'1'&x"8DD8",'1'&x"8DD9",'1'&x"8DDA",'1'&x"8DDB",'1'&x"8DDC",'1'&x"8DDD",'1'&x"8DDE",'1'&x"8DDF",
+--'1'&x"8DE0",'1'&x"8DE1",'1'&x"8DE2",'1'&x"8DE3",'1'&x"8DE4",'1'&x"8DE5",'1'&x"8DE6",'1'&x"8DE7",'1'&x"8DE8",'1'&x"8DE9",'1'&x"8DEA",'1'&x"8DEB",'1'&x"8DEC",'1'&x"8DED",'1'&x"8DEE",'1'&x"8DEF",
+--'1'&x"8DF0",'1'&x"8DF1",'1'&x"8DF2",'1'&x"8DF3",'1'&x"8DF4",'1'&x"8DF5",'1'&x"8DF6",'1'&x"8DF7",'1'&x"8DF8",'1'&x"8DF9",'1'&x"8DFA",'1'&x"8DFB",'1'&x"8DFC",'1'&x"8DFD",'1'&x"8DFE",'1'&x"8DFF",
+--'1'&x"8E00",'1'&x"8E01",'1'&x"8E02",'1'&x"8E03",'1'&x"8E04",'1'&x"8E05",'1'&x"8E06",'1'&x"8E07",'1'&x"8E08",'1'&x"8E09",'1'&x"8E0A",'1'&x"8E0B",'1'&x"8E0C",'1'&x"8E0D",'1'&x"8E0E",'1'&x"8E0F",
+--'1'&x"8E10",'1'&x"8E11",'1'&x"8E12",'1'&x"8E13",'1'&x"8E14",'1'&x"8E15",'1'&x"8E16",'1'&x"8E17",'1'&x"8E18",'1'&x"8E19",'1'&x"8E1A",'1'&x"8E1B",'1'&x"8E1C",'1'&x"8E1D",'1'&x"8E1E",'1'&x"8E1F",
+--'1'&x"8E20",'1'&x"8E21",'1'&x"8E22",'1'&x"8E23",'1'&x"8E24",'1'&x"8E25",'1'&x"8E26",'1'&x"8E27",'1'&x"8E28",'1'&x"8E29",'1'&x"8E2A",'1'&x"8E2B",'1'&x"8E2C",'1'&x"8E2D",'1'&x"8E2E",'1'&x"8E2F",
+--'1'&x"8E30",'1'&x"8E31",'1'&x"8E32",'1'&x"8E33",'1'&x"8E34",'1'&x"8E35",'1'&x"8E36",'1'&x"8E37",'1'&x"8E38",'1'&x"8E39",'1'&x"8E3A",'1'&x"8E3B",'1'&x"8E3C",'1'&x"8E3D",'1'&x"8E3E",'1'&x"8E3F",
+--'1'&x"8E40",'1'&x"8E41",'1'&x"8E42",'1'&x"8E43",'1'&x"8E44",'1'&x"8E45",'1'&x"8E46",'1'&x"8E47",'1'&x"8E48",'1'&x"8E49",'1'&x"8E4A",'1'&x"8E4B",'1'&x"8E4C",'1'&x"8E4D",'1'&x"8E4E",'1'&x"8E4F",
+--'1'&x"8E50",'1'&x"8E51",'1'&x"8E52",'1'&x"8E53",'1'&x"8E54",'1'&x"8E55",'1'&x"8E56",'1'&x"8E57",'1'&x"8E58",'1'&x"8E59",'1'&x"8E5A",'1'&x"8E5B",'1'&x"8E5C",'1'&x"8E5D",'1'&x"8E5E",'1'&x"8E5F",
+--'1'&x"8E60",'1'&x"8E61",'1'&x"8E62",'1'&x"8E63",'1'&x"8E64",'1'&x"8E65",'1'&x"8E66",'1'&x"8E67",'1'&x"8E68",'1'&x"8E69",'1'&x"8E6A",'1'&x"8E6B",'1'&x"8E6C",'1'&x"8E6D",'1'&x"8E6E",'1'&x"8E6F",
+--'1'&x"8E70",'1'&x"8E71",'1'&x"8E72",'1'&x"8E73",'1'&x"8E74",'1'&x"8E75",'1'&x"8E76",'1'&x"8E77",'1'&x"8E78",'1'&x"8E79",'1'&x"8E7A",'1'&x"8E7B",'1'&x"8E7C",'1'&x"8E7D",'1'&x"8E7E",'1'&x"8E7F",
+--'1'&x"8E80",'1'&x"8E81",'1'&x"8E82",'1'&x"8E83",'1'&x"8E84",'1'&x"8E85",'1'&x"8E86",'1'&x"8E87",'1'&x"8E88",'1'&x"8E89",'1'&x"8E8A",'1'&x"8E8B",'1'&x"8E8C",'1'&x"8E8D",'1'&x"8E8E",'1'&x"8E8F",
+--'1'&x"8E90",'1'&x"8E91",'1'&x"8E92",'1'&x"8E93",'1'&x"8E94",'1'&x"8E95",'1'&x"8E96",'1'&x"8E97",'1'&x"8E98",'1'&x"8E99",'1'&x"8E9A",'1'&x"8E9B",'1'&x"8E9C",'1'&x"8E9D",'1'&x"8E9E",'1'&x"8E9F",
+--'1'&x"8EA0",'1'&x"8EA1",'1'&x"8EA2",'1'&x"8EA3",'1'&x"8EA4",'1'&x"8EA5",'1'&x"8EA6",'1'&x"8EA7",'1'&x"8EA8",'1'&x"8EA9",'1'&x"8EAA",'1'&x"8EAB",'1'&x"8EAC",'1'&x"8EAD",'1'&x"8EAE",'1'&x"8EAF",
+--'1'&x"8EB0",'1'&x"8EB1",'1'&x"8EB2",'1'&x"8EB3",'1'&x"8EB4",'1'&x"8EB5",'1'&x"8EB6",'1'&x"8EB7",'1'&x"8EB8",'1'&x"8EB9",'1'&x"8EBA",'1'&x"8EBB",'1'&x"8EBC",'1'&x"8EBD",'1'&x"8EBE",'1'&x"8EBF",
+--'1'&x"8EC0",'1'&x"8EC1",'1'&x"8EC2",'1'&x"8EC3",'1'&x"8EC4",'1'&x"8EC5",'1'&x"8EC6",'1'&x"8EC7",'1'&x"8EC8",'1'&x"8EC9",'1'&x"8ECA",'1'&x"8ECB",'1'&x"8ECC",'1'&x"8ECD",'1'&x"8ECE",'1'&x"8ECF",
+--'1'&x"8ED0",'1'&x"8ED1",'1'&x"8ED2",'1'&x"8ED3",'1'&x"8ED4",'1'&x"8ED5",'1'&x"8ED6",'1'&x"8ED7",'1'&x"8ED8",'1'&x"8ED9",'1'&x"8EDA",'1'&x"8EDB",'1'&x"8EDC",'1'&x"8EDD",'1'&x"8EDE",'1'&x"8EDF",
+--'1'&x"8EE0",'1'&x"8EE1",'1'&x"8EE2",'1'&x"8EE3",'1'&x"8EE4",'1'&x"8EE5",'1'&x"8EE6",'1'&x"8EE7",'1'&x"8EE8",'1'&x"8EE9",'1'&x"8EEA",'1'&x"8EEB",'1'&x"8EEC",'1'&x"8EED",'1'&x"8EEE",'1'&x"8EEF",
+--'1'&x"8EF0",'1'&x"8EF1",'1'&x"8EF2",'1'&x"8EF3",'1'&x"8EF4",'1'&x"8EF5",'1'&x"8EF6",'1'&x"8EF7",'1'&x"8EF8",'1'&x"8EF9",'1'&x"8EFA",'1'&x"8EFB",'1'&x"8EFC",'1'&x"8EFD",'1'&x"8EFE",'1'&x"8EFF",
+--'1'&x"8F00",'1'&x"8F01",'1'&x"8F02",'1'&x"8F03",'1'&x"8F04",'1'&x"8F05",'1'&x"8F06",'1'&x"8F07",'1'&x"8F08",'1'&x"8F09",'1'&x"8F0A",'1'&x"8F0B",'1'&x"8F0C",'1'&x"8F0D",'1'&x"8F0E",'1'&x"8F0F",
+--'1'&x"8F10",'1'&x"8F11",'1'&x"8F12",'1'&x"8F13",'1'&x"8F14",'1'&x"8F15",'1'&x"8F16",'1'&x"8F17",'1'&x"8F18",'1'&x"8F19",'1'&x"8F1A",'1'&x"8F1B",'1'&x"8F1C",'1'&x"8F1D",'1'&x"8F1E",'1'&x"8F1F",
+--'1'&x"8F20",'1'&x"8F21",'1'&x"8F22",'1'&x"8F23",'1'&x"8F24",'1'&x"8F25",'1'&x"8F26",'1'&x"8F27",'1'&x"8F28",'1'&x"8F29",'1'&x"8F2A",'1'&x"8F2B",'1'&x"8F2C",'1'&x"8F2D",'1'&x"8F2E",'1'&x"8F2F",
+--'1'&x"8F30",'1'&x"8F31",'1'&x"8F32",'1'&x"8F33",'1'&x"8F34",'1'&x"8F35",'1'&x"8F36",'1'&x"8F37",'1'&x"8F38",'1'&x"8F39",'1'&x"8F3A",'1'&x"8F3B",'1'&x"8F3C",'1'&x"8F3D",'1'&x"8F3E",'1'&x"8F3F",
+--'1'&x"8F40",'1'&x"8F41",'1'&x"8F42",'1'&x"8F43",'1'&x"8F44",'1'&x"8F45",'1'&x"8F46",'1'&x"8F47",'1'&x"8F48",'1'&x"8F49",'1'&x"8F4A",'1'&x"8F4B",'1'&x"8F4C",'1'&x"8F4D",'1'&x"8F4E",'1'&x"8F4F",
+--'1'&x"8F50",'1'&x"8F51",'1'&x"8F52",'1'&x"8F53",'1'&x"8F54",'1'&x"8F55",'1'&x"8F56",'1'&x"8F57",'1'&x"8F58",'1'&x"8F59",'1'&x"8F5A",'1'&x"8F5B",'1'&x"8F5C",'1'&x"8F5D",'1'&x"8F5E",'1'&x"8F5F",
+--'1'&x"8F60",'1'&x"8F61",'1'&x"8F62",'1'&x"8F63",'1'&x"8F64",'1'&x"8F65",'1'&x"8F66",'1'&x"8F67",'1'&x"8F68",'1'&x"8F69",'1'&x"8F6A",'1'&x"8F6B",'1'&x"8F6C",'1'&x"8F6D",'1'&x"8F6E",'1'&x"8F6F",
+--'1'&x"8F70",'1'&x"8F71",'1'&x"8F72",'1'&x"8F73",'1'&x"8F74",'1'&x"8F75",'1'&x"8F76",'1'&x"8F77",'1'&x"8F78",'1'&x"8F79",'1'&x"8F7A",'1'&x"8F7B",'1'&x"8F7C",'1'&x"8F7D",'1'&x"8F7E",'1'&x"8F7F",
+--'1'&x"8F80",'1'&x"8F81",'1'&x"8F82",'1'&x"8F83",'1'&x"8F84",'1'&x"8F85",'1'&x"8F86",'1'&x"8F87",'1'&x"8F88",'1'&x"8F89",'1'&x"8F8A",'1'&x"8F8B",'1'&x"8F8C",'1'&x"8F8D",'1'&x"8F8E",'1'&x"8F8F",
+--'1'&x"8F90",'1'&x"8F91",'1'&x"8F92",'1'&x"8F93",'1'&x"8F94",'1'&x"8F95",'1'&x"8F96",'1'&x"8F97",'1'&x"8F98",'1'&x"8F99",'1'&x"8F9A",'1'&x"8F9B",'1'&x"8F9C",'1'&x"8F9D",'1'&x"8F9E",'1'&x"8F9F",
+--'1'&x"8FA0",'1'&x"8FA1",'1'&x"8FA2",'1'&x"8FA3",'1'&x"8FA4",'1'&x"8FA5",'1'&x"8FA6",'1'&x"8FA7",'1'&x"8FA8",'1'&x"8FA9",'1'&x"8FAA",'1'&x"8FAB",'1'&x"8FAC",'1'&x"8FAD",'1'&x"8FAE",'1'&x"8FAF",
+--'1'&x"8FB0",'1'&x"8FB1",'1'&x"8FB2",'1'&x"8FB3",'1'&x"8FB4",'1'&x"8FB5",'1'&x"8FB6",'1'&x"8FB7",'1'&x"8FB8",'1'&x"8FB9",'1'&x"8FBA",'1'&x"8FBB",'1'&x"8FBC",'1'&x"8FBD",'1'&x"8FBE",'1'&x"8FBF",
+--'1'&x"8FC0",'1'&x"8FC1",'1'&x"8FC2",'1'&x"8FC3",'1'&x"8FC4",'1'&x"8FC5",'1'&x"8FC6",'1'&x"8FC7",'1'&x"8FC8",'1'&x"8FC9",'1'&x"8FCA",'1'&x"8FCB",'1'&x"8FCC",'1'&x"8FCD",'1'&x"8FCE",'1'&x"8FCF",
+--'1'&x"8FD0",'1'&x"8FD1",'1'&x"8FD2",'1'&x"8FD3",'1'&x"8FD4",'1'&x"8FD5",'1'&x"8FD6",'1'&x"8FD7",'1'&x"8FD8",'1'&x"8FD9",'1'&x"8FDA",'1'&x"8FDB",'1'&x"8FDC",'1'&x"8FDD",'1'&x"8FDE",'1'&x"8FDF",
+--'1'&x"8FE0",'1'&x"8FE1",'1'&x"8FE2",'1'&x"8FE3",'1'&x"8FE4",'1'&x"8FE5",'1'&x"8FE6",'1'&x"8FE7",'1'&x"8FE8",'1'&x"8FE9",'1'&x"8FEA",'1'&x"8FEB",'1'&x"8FEC",'1'&x"8FED",'1'&x"8FEE",'1'&x"8FEF",
+--'1'&x"8FF0",'1'&x"8FF1",'1'&x"8FF2",'1'&x"8FF3",'1'&x"8FF4",'1'&x"8FF5",'1'&x"8FF6",'1'&x"8FF7",'1'&x"8FF8",'1'&x"8FF9",'1'&x"8FFA",'1'&x"8FFB",'1'&x"8FFC",'1'&x"8FFD",'1'&x"8FFE",'1'&x"8FFF",
+--'1'&x"9000",'1'&x"9001",'1'&x"9002",'1'&x"9003",'1'&x"9004",'1'&x"9005",'1'&x"9006",'1'&x"9007",'1'&x"9008",'1'&x"9009",'1'&x"900A",'1'&x"900B",'1'&x"900C",'1'&x"900D",'1'&x"900E",'1'&x"900F",
+--'1'&x"9010",'1'&x"9011",'1'&x"9012",'1'&x"9013",'1'&x"9014",'1'&x"9015",'1'&x"9016",'1'&x"9017",'1'&x"9018",'1'&x"9019",'1'&x"901A",'1'&x"901B",'1'&x"901C",'1'&x"901D",'1'&x"901E",'1'&x"901F",
+--'1'&x"9020",'1'&x"9021",'1'&x"9022",'1'&x"9023",'1'&x"9024",'1'&x"9025",'1'&x"9026",'1'&x"9027",'1'&x"9028",'1'&x"9029",'1'&x"902A",'1'&x"902B",'1'&x"902C",'1'&x"902D",'1'&x"902E",'1'&x"902F",
+--'1'&x"9030",'1'&x"9031",'1'&x"9032",'1'&x"9033",'1'&x"9034",'1'&x"9035",'1'&x"9036",'1'&x"9037",'1'&x"9038",'1'&x"9039",'1'&x"903A",'1'&x"903B",'1'&x"903C",'1'&x"903D",'1'&x"903E",'1'&x"903F",
+--'1'&x"9040",'1'&x"9041",'1'&x"9042",'1'&x"9043",'1'&x"9044",'1'&x"9045",'1'&x"9046",'1'&x"9047",'1'&x"9048",'1'&x"9049",'1'&x"904A",'1'&x"904B",'1'&x"904C",'1'&x"904D",'1'&x"904E",'1'&x"904F",
+--'1'&x"9050",'1'&x"9051",'1'&x"9052",'1'&x"9053",'1'&x"9054",'1'&x"9055",'1'&x"9056",'1'&x"9057",'1'&x"9058",'1'&x"9059",'1'&x"905A",'1'&x"905B",'1'&x"905C",'1'&x"905D",'1'&x"905E",'1'&x"905F",
+--'1'&x"9060",'1'&x"9061",'1'&x"9062",'1'&x"9063",'1'&x"9064",'1'&x"9065",'1'&x"9066",'1'&x"9067",'1'&x"9068",'1'&x"9069",'1'&x"906A",'1'&x"906B",'1'&x"906C",'1'&x"906D",'1'&x"906E",'1'&x"906F",
+--'1'&x"9070",'1'&x"9071",'1'&x"9072",'1'&x"9073",'1'&x"9074",'1'&x"9075",'1'&x"9076",'1'&x"9077",'1'&x"9078",'1'&x"9079",'1'&x"907A",'1'&x"907B",'1'&x"907C",'1'&x"907D",'1'&x"907E",'1'&x"907F",
+--'1'&x"9080",'1'&x"9081",'1'&x"9082",'1'&x"9083",'1'&x"9084",'1'&x"9085",'1'&x"9086",'1'&x"9087",'1'&x"9088",'1'&x"9089",'1'&x"908A",'1'&x"908B",'1'&x"908C",'1'&x"908D",'1'&x"908E",'1'&x"908F",
+--'1'&x"9090",'1'&x"9091",'1'&x"9092",'1'&x"9093",'1'&x"9094",'1'&x"9095",'1'&x"9096",'1'&x"9097",'1'&x"9098",'1'&x"9099",'1'&x"909A",'1'&x"909B",'1'&x"909C",'1'&x"909D",'1'&x"909E",'1'&x"909F",
+--'1'&x"90A0",'1'&x"90A1",'1'&x"90A2",'1'&x"90A3",'1'&x"90A4",'1'&x"90A5",'1'&x"90A6",'1'&x"90A7",'1'&x"90A8",'1'&x"90A9",'1'&x"90AA",'1'&x"90AB",'1'&x"90AC",'1'&x"90AD",'1'&x"90AE",'1'&x"90AF",
+--'1'&x"90B0",'1'&x"90B1",'1'&x"90B2",'1'&x"90B3",'1'&x"90B4",'1'&x"90B5",'1'&x"90B6",'1'&x"90B7",'1'&x"90B8",'1'&x"90B9",'1'&x"90BA",'1'&x"90BB",'1'&x"90BC",'1'&x"90BD",'1'&x"90BE",'1'&x"90BF",
+--'1'&x"90C0",'1'&x"90C1",'1'&x"90C2",'1'&x"90C3",'1'&x"90C4",'1'&x"90C5",'1'&x"90C6",'1'&x"90C7",'1'&x"90C8",'1'&x"90C9",'1'&x"90CA",'1'&x"90CB",'1'&x"90CC",'1'&x"90CD",'1'&x"90CE",'1'&x"90CF",
+--'1'&x"90D0",'1'&x"90D1",'1'&x"90D2",'1'&x"90D3",'1'&x"90D4",'1'&x"90D5",'1'&x"90D6",'1'&x"90D7",'1'&x"90D8",'1'&x"90D9",'1'&x"90DA",'1'&x"90DB",'1'&x"90DC",'1'&x"90DD",'1'&x"90DE",'1'&x"90DF",
+--'1'&x"90E0",'1'&x"90E1",'1'&x"90E2",'1'&x"90E3",'1'&x"90E4",'1'&x"90E5",'1'&x"90E6",'1'&x"90E7",'1'&x"90E8",'1'&x"90E9",'1'&x"90EA",'1'&x"90EB",'1'&x"90EC",'1'&x"90ED",'1'&x"90EE",'1'&x"90EF",
+--'1'&x"90F0",'1'&x"90F1",'1'&x"90F2",'1'&x"90F3",'1'&x"90F4",'1'&x"90F5",'1'&x"90F6",'1'&x"90F7",'1'&x"90F8",'1'&x"90F9",'1'&x"90FA",'1'&x"90FB",'1'&x"90FC",'1'&x"90FD",'1'&x"90FE",'1'&x"90FF",
+--'1'&x"9100",'1'&x"9101",'1'&x"9102",'1'&x"9103",'1'&x"9104",'1'&x"9105",'1'&x"9106",'1'&x"9107",'1'&x"9108",'1'&x"9109",'1'&x"910A",'1'&x"910B",'1'&x"910C",'1'&x"910D",'1'&x"910E",'1'&x"910F",
+--'1'&x"9110",'1'&x"9111",'1'&x"9112",'1'&x"9113",'1'&x"9114",'1'&x"9115",'1'&x"9116",'1'&x"9117",'1'&x"9118",'1'&x"9119",'1'&x"911A",'1'&x"911B",'1'&x"911C",'1'&x"911D",'1'&x"911E",'1'&x"911F",
+--'1'&x"9120",'1'&x"9121",'1'&x"9122",'1'&x"9123",'1'&x"9124",'1'&x"9125",'1'&x"9126",'1'&x"9127",'1'&x"9128",'1'&x"9129",'1'&x"912A",'1'&x"912B",'1'&x"912C",'1'&x"912D",'1'&x"912E",'1'&x"912F",
+--'1'&x"9130",'1'&x"9131",'1'&x"9132",'1'&x"9133",'1'&x"9134",'1'&x"9135",'1'&x"9136",'1'&x"9137",'1'&x"9138",'1'&x"9139",'1'&x"913A",'1'&x"913B",'1'&x"913C",'1'&x"913D",'1'&x"913E",'1'&x"913F",
+--'1'&x"9140",'1'&x"9141",'1'&x"9142",'1'&x"9143",'1'&x"9144",'1'&x"9145",'1'&x"9146",'1'&x"9147",'1'&x"9148",'1'&x"9149",'1'&x"914A",'1'&x"914B",'1'&x"914C",'1'&x"914D",'1'&x"914E",'1'&x"914F",
+--'1'&x"9150",'1'&x"9151",'1'&x"9152",'1'&x"9153",'1'&x"9154",'1'&x"9155",'1'&x"9156",'1'&x"9157",'1'&x"9158",'1'&x"9159",'1'&x"915A",'1'&x"915B",'1'&x"915C",'1'&x"915D",'1'&x"915E",'1'&x"915F",
+--'1'&x"9160",'1'&x"9161",'1'&x"9162",'1'&x"9163",'1'&x"9164",'1'&x"9165",'1'&x"9166",'1'&x"9167",'1'&x"9168",'1'&x"9169",'1'&x"916A",'1'&x"916B",'1'&x"916C",'1'&x"916D",'1'&x"916E",'1'&x"916F",
+--'1'&x"9170",'1'&x"9171",'1'&x"9172",'1'&x"9173",'1'&x"9174",'1'&x"9175",'1'&x"9176",'1'&x"9177",'1'&x"9178",'1'&x"9179",'1'&x"917A",'1'&x"917B",'1'&x"917C",'1'&x"917D",'1'&x"917E",'1'&x"917F",
+--'1'&x"9180",'1'&x"9181",'1'&x"9182",'1'&x"9183",'1'&x"9184",'1'&x"9185",'1'&x"9186",'1'&x"9187",'1'&x"9188",'1'&x"9189",'1'&x"918A",'1'&x"918B",'1'&x"918C",'1'&x"918D",'1'&x"918E",'1'&x"918F",
+--'1'&x"9190",'1'&x"9191",'1'&x"9192",'1'&x"9193",'1'&x"9194",'1'&x"9195",'1'&x"9196",'1'&x"9197",'1'&x"9198",'1'&x"9199",'1'&x"919A",'1'&x"919B",'1'&x"919C",'1'&x"919D",'1'&x"919E",'1'&x"919F",
+--'1'&x"91A0",'1'&x"91A1",'1'&x"91A2",'1'&x"91A3",'1'&x"91A4",'1'&x"91A5",'1'&x"91A6",'1'&x"91A7",'1'&x"91A8",'1'&x"91A9",'1'&x"91AA",'1'&x"91AB",'1'&x"91AC",'1'&x"91AD",'1'&x"91AE",'1'&x"91AF",
+--'1'&x"91B0",'1'&x"91B1",'1'&x"91B2",'1'&x"91B3",'1'&x"91B4",'1'&x"91B5",'1'&x"91B6",'1'&x"91B7",'1'&x"91B8",'1'&x"91B9",'1'&x"91BA",'1'&x"91BB",'1'&x"91BC",'1'&x"91BD",'1'&x"91BE",'1'&x"91BF",
+--'1'&x"91C0",'1'&x"91C1",'1'&x"91C2",'1'&x"91C3",'1'&x"91C4",'1'&x"91C5",'1'&x"91C6",'1'&x"91C7",'1'&x"91C8",'1'&x"91C9",'1'&x"91CA",'1'&x"91CB",'1'&x"91CC",'1'&x"91CD",'1'&x"91CE",'1'&x"91CF",
+--'1'&x"91D0",'1'&x"91D1",'1'&x"91D2",'1'&x"91D3",'1'&x"91D4",'1'&x"91D5",'1'&x"91D6",'1'&x"91D7",'1'&x"91D8",'1'&x"91D9",'1'&x"91DA",'1'&x"91DB",'1'&x"91DC",'1'&x"91DD",'1'&x"91DE",'1'&x"91DF",
+--'1'&x"91E0",'1'&x"91E1",'1'&x"91E2",'1'&x"91E3",'1'&x"91E4",'1'&x"91E5",'1'&x"91E6",'1'&x"91E7",'1'&x"91E8",'1'&x"91E9",'1'&x"91EA",'1'&x"91EB",'1'&x"91EC",'1'&x"91ED",'1'&x"91EE",'1'&x"91EF",
+--'1'&x"91F0",'1'&x"91F1",'1'&x"91F2",'1'&x"91F3",'1'&x"91F4",'1'&x"91F5",'1'&x"91F6",'1'&x"91F7",'1'&x"91F8",'1'&x"91F9",'1'&x"91FA",'1'&x"91FB",'1'&x"91FC",'1'&x"91FD",'1'&x"91FE",'1'&x"91FF",
+--'1'&x"9200",'1'&x"9201",'1'&x"9202",'1'&x"9203",'1'&x"9204",'1'&x"9205",'1'&x"9206",'1'&x"9207",'1'&x"9208",'1'&x"9209",'1'&x"920A",'1'&x"920B",'1'&x"920C",'1'&x"920D",'1'&x"920E",'1'&x"920F",
+--'1'&x"9210",'1'&x"9211",'1'&x"9212",'1'&x"9213",'1'&x"9214",'1'&x"9215",'1'&x"9216",'1'&x"9217",'1'&x"9218",'1'&x"9219",'1'&x"921A",'1'&x"921B",'1'&x"921C",'1'&x"921D",'1'&x"921E",'1'&x"921F",
+--'1'&x"9220",'1'&x"9221",'1'&x"9222",'1'&x"9223",'1'&x"9224",'1'&x"9225",'1'&x"9226",'1'&x"9227",'1'&x"9228",'1'&x"9229",'1'&x"922A",'1'&x"922B",'1'&x"922C",'1'&x"922D",'1'&x"922E",'1'&x"922F",
+--'1'&x"9230",'1'&x"9231",'1'&x"9232",'1'&x"9233",'1'&x"9234",'1'&x"9235",'1'&x"9236",'1'&x"9237",'1'&x"9238",'1'&x"9239",'1'&x"923A",'1'&x"923B",'1'&x"923C",'1'&x"923D",'1'&x"923E",'1'&x"923F",
+--'1'&x"9240",'1'&x"9241",'1'&x"9242",'1'&x"9243",'1'&x"9244",'1'&x"9245",'1'&x"9246",'1'&x"9247",'1'&x"9248",'1'&x"9249",'1'&x"924A",'1'&x"924B",'1'&x"924C",'1'&x"924D",'1'&x"924E",'1'&x"924F",
+--'1'&x"9250",'1'&x"9251",'1'&x"9252",'1'&x"9253",'1'&x"9254",'1'&x"9255",'1'&x"9256",'1'&x"9257",'1'&x"9258",'1'&x"9259",'1'&x"925A",'1'&x"925B",'1'&x"925C",'1'&x"925D",'1'&x"925E",'1'&x"925F",
+--'1'&x"9260",'1'&x"9261",'1'&x"9262",'1'&x"9263",'1'&x"9264",'1'&x"9265",'1'&x"9266",'1'&x"9267",'1'&x"9268",'1'&x"9269",'1'&x"926A",'1'&x"926B",'1'&x"926C",'1'&x"926D",'1'&x"926E",'1'&x"926F",
+--'1'&x"9270",'1'&x"9271",'1'&x"9272",'1'&x"9273",'1'&x"9274",'1'&x"9275",'1'&x"9276",'1'&x"9277",'1'&x"9278",'1'&x"9279",'1'&x"927A",'1'&x"927B",'1'&x"927C",'1'&x"927D",'1'&x"927E",'1'&x"927F",
+--'1'&x"9280",'1'&x"9281",'1'&x"9282",'1'&x"9283",'1'&x"9284",'1'&x"9285",'1'&x"9286",'1'&x"9287",'1'&x"9288",'1'&x"9289",'1'&x"928A",'1'&x"928B",'1'&x"928C",'1'&x"928D",'1'&x"928E",'1'&x"928F",
+--'1'&x"9290",'1'&x"9291",'1'&x"9292",'1'&x"9293",'1'&x"9294",'1'&x"9295",'1'&x"9296",'1'&x"9297",'1'&x"9298",'1'&x"9299",'1'&x"929A",'1'&x"929B",'1'&x"929C",'1'&x"929D",'1'&x"929E",'1'&x"929F",
+--'1'&x"92A0",'1'&x"92A1",'1'&x"92A2",'1'&x"92A3",'1'&x"92A4",'1'&x"92A5",'1'&x"92A6",'1'&x"92A7",'1'&x"92A8",'1'&x"92A9",'1'&x"92AA",'1'&x"92AB",'1'&x"92AC",'1'&x"92AD",'1'&x"92AE",'1'&x"92AF",
+--'1'&x"92B0",'1'&x"92B1",'1'&x"92B2",'1'&x"92B3",'1'&x"92B4",'1'&x"92B5",'1'&x"92B6",'1'&x"92B7",'1'&x"92B8",'1'&x"92B9",'1'&x"92BA",'1'&x"92BB",'1'&x"92BC",'1'&x"92BD",'1'&x"92BE",'1'&x"92BF",
+--'1'&x"92C0",'1'&x"92C1",'1'&x"92C2",'1'&x"92C3",'1'&x"92C4",'1'&x"92C5",'1'&x"92C6",'1'&x"92C7",'1'&x"92C8",'1'&x"92C9",'1'&x"92CA",'1'&x"92CB",'1'&x"92CC",'1'&x"92CD",'1'&x"92CE",'1'&x"92CF",
+--'1'&x"92D0",'1'&x"92D1",'1'&x"92D2",'1'&x"92D3",'1'&x"92D4",'1'&x"92D5",'1'&x"92D6",'1'&x"92D7",'1'&x"92D8",'1'&x"92D9",'1'&x"92DA",'1'&x"92DB",'1'&x"92DC",'1'&x"92DD",'1'&x"92DE",'1'&x"92DF",
+--'1'&x"92E0",'1'&x"92E1",'1'&x"92E2",'1'&x"92E3",'1'&x"92E4",'1'&x"92E5",'1'&x"92E6",'1'&x"92E7",'1'&x"92E8",'1'&x"92E9",'1'&x"92EA",'1'&x"92EB",'1'&x"92EC",'1'&x"92ED",'1'&x"92EE",'1'&x"92EF",
+--'1'&x"92F0",'1'&x"92F1",'1'&x"92F2",'1'&x"92F3",'1'&x"92F4",'1'&x"92F5",'1'&x"92F6",'1'&x"92F7",'1'&x"92F8",'1'&x"92F9",'1'&x"92FA",'1'&x"92FB",'1'&x"92FC",'1'&x"92FD",'1'&x"92FE",'1'&x"92FF",
+--'1'&x"9300",'1'&x"9301",'1'&x"9302",'1'&x"9303",'1'&x"9304",'1'&x"9305",'1'&x"9306",'1'&x"9307",'1'&x"9308",'1'&x"9309",'1'&x"930A",'1'&x"930B",'1'&x"930C",'1'&x"930D",'1'&x"930E",'1'&x"930F",
+--'1'&x"9310",'1'&x"9311",'1'&x"9312",'1'&x"9313",'1'&x"9314",'1'&x"9315",'1'&x"9316",'1'&x"9317",'1'&x"9318",'1'&x"9319",'1'&x"931A",'1'&x"931B",'1'&x"931C",'1'&x"931D",'1'&x"931E",'1'&x"931F",
+--'1'&x"9320",'1'&x"9321",'1'&x"9322",'1'&x"9323",'1'&x"9324",'1'&x"9325",'1'&x"9326",'1'&x"9327",'1'&x"9328",'1'&x"9329",'1'&x"932A",'1'&x"932B",'1'&x"932C",'1'&x"932D",'1'&x"932E",'1'&x"932F",
+--'1'&x"9330",'1'&x"9331",'1'&x"9332",'1'&x"9333",'1'&x"9334",'1'&x"9335",'1'&x"9336",'1'&x"9337",'1'&x"9338",'1'&x"9339",'1'&x"933A",'1'&x"933B",'1'&x"933C",'1'&x"933D",'1'&x"933E",'1'&x"933F",
+--'1'&x"9340",'1'&x"9341",'1'&x"9342",'1'&x"9343",'1'&x"9344",'1'&x"9345",'1'&x"9346",'1'&x"9347",'1'&x"9348",'1'&x"9349",'1'&x"934A",'1'&x"934B",'1'&x"934C",'1'&x"934D",'1'&x"934E",'1'&x"934F",
+--'1'&x"9350",'1'&x"9351",'1'&x"9352",'1'&x"9353",'1'&x"9354",'1'&x"9355",'1'&x"9356",'1'&x"9357",'1'&x"9358",'1'&x"9359",'1'&x"935A",'1'&x"935B",'1'&x"935C",'1'&x"935D",'1'&x"935E",'1'&x"935F",
+--'1'&x"9360",'1'&x"9361",'1'&x"9362",'1'&x"9363",'1'&x"9364",'1'&x"9365",'1'&x"9366",'1'&x"9367",'1'&x"9368",'1'&x"9369",'1'&x"936A",'1'&x"936B",'1'&x"936C",'1'&x"936D",'1'&x"936E",'1'&x"936F",
+--'1'&x"9370",'1'&x"9371",'1'&x"9372",'1'&x"9373",'1'&x"9374",'1'&x"9375",'1'&x"9376",'1'&x"9377",'1'&x"9378",'1'&x"9379",'1'&x"937A",'1'&x"937B",'1'&x"937C",'1'&x"937D",'1'&x"937E",'1'&x"937F",
+--'1'&x"9380",'1'&x"9381",'1'&x"9382",'1'&x"9383",'1'&x"9384",'1'&x"9385",'1'&x"9386",'1'&x"9387",'1'&x"9388",'1'&x"9389",'1'&x"938A",'1'&x"938B",'1'&x"938C",'1'&x"938D",'1'&x"938E",'1'&x"938F",
+--'1'&x"9390",'1'&x"9391",'1'&x"9392",'1'&x"9393",'1'&x"9394",'1'&x"9395",'1'&x"9396",'1'&x"9397",'1'&x"9398",'1'&x"9399",'1'&x"939A",'1'&x"939B",'1'&x"939C",'1'&x"939D",'1'&x"939E",'1'&x"939F",
+--'1'&x"93A0",'1'&x"93A1",'1'&x"93A2",'1'&x"93A3",'1'&x"93A4",'1'&x"93A5",'1'&x"93A6",'1'&x"93A7",'1'&x"93A8",'1'&x"93A9",'1'&x"93AA",'1'&x"93AB",'1'&x"93AC",'1'&x"93AD",'1'&x"93AE",'1'&x"93AF",
+--'1'&x"93B0",'1'&x"93B1",'1'&x"93B2",'1'&x"93B3",'1'&x"93B4",'1'&x"93B5",'1'&x"93B6",'1'&x"93B7",'1'&x"93B8",'1'&x"93B9",'1'&x"93BA",'1'&x"93BB",'1'&x"93BC",'1'&x"93BD",'1'&x"93BE",'1'&x"93BF",
+--'1'&x"93C0",'1'&x"93C1",'1'&x"93C2",'1'&x"93C3",'1'&x"93C4",'1'&x"93C5",'1'&x"93C6",'1'&x"93C7",'1'&x"93C8",'1'&x"93C9",'1'&x"93CA",'1'&x"93CB",'1'&x"93CC",'1'&x"93CD",'1'&x"93CE",'1'&x"93CF",
+--'1'&x"93D0",'1'&x"93D1",'1'&x"93D2",'1'&x"93D3",'1'&x"93D4",'1'&x"93D5",'1'&x"93D6",'1'&x"93D7",'1'&x"93D8",'1'&x"93D9",'1'&x"93DA",'1'&x"93DB",'1'&x"93DC",'1'&x"93DD",'1'&x"93DE",'1'&x"93DF",
+--'1'&x"93E0",'1'&x"93E1",'1'&x"93E2",'1'&x"93E3",'1'&x"93E4",'1'&x"93E5",'1'&x"93E6",'1'&x"93E7",'1'&x"93E8",'1'&x"93E9",'1'&x"93EA",'1'&x"93EB",'1'&x"93EC",'1'&x"93ED",'1'&x"93EE",'1'&x"93EF",
+--'1'&x"93F0",'1'&x"93F1",'1'&x"93F2",'1'&x"93F3",'1'&x"93F4",'1'&x"93F5",'1'&x"93F6",'1'&x"93F7",'1'&x"93F8",'1'&x"93F9",'1'&x"93FA",'1'&x"93FB",'1'&x"93FC",'1'&x"93FD",'1'&x"93FE",'1'&x"93FF",
+--'1'&x"9400",'1'&x"9401",'1'&x"9402",'1'&x"9403",'1'&x"9404",'1'&x"9405",'1'&x"9406",'1'&x"9407",'1'&x"9408",'1'&x"9409",'1'&x"940A",'1'&x"940B",'1'&x"940C",'1'&x"940D",'1'&x"940E",'1'&x"940F",
+--'1'&x"9410",'1'&x"9411",'1'&x"9412",'1'&x"9413",'1'&x"9414",'1'&x"9415",'1'&x"9416",'1'&x"9417",'1'&x"9418",'1'&x"9419",'1'&x"941A",'1'&x"941B",'1'&x"941C",'1'&x"941D",'1'&x"941E",'1'&x"941F",
+--'1'&x"9420",'1'&x"9421",'1'&x"9422",'1'&x"9423",'1'&x"9424",'1'&x"9425",'1'&x"9426",'1'&x"9427",'1'&x"9428",'1'&x"9429",'1'&x"942A",'1'&x"942B",'1'&x"942C",'1'&x"942D",'1'&x"942E",'1'&x"942F",
+--'1'&x"9430",'1'&x"9431",'1'&x"9432",'1'&x"9433",'1'&x"9434",'1'&x"9435",'1'&x"9436",'1'&x"9437",'1'&x"9438",'1'&x"9439",'1'&x"943A",'1'&x"943B",'1'&x"943C",'1'&x"943D",'1'&x"943E",'1'&x"943F",
+--'1'&x"9440",'1'&x"9441",'1'&x"9442",'1'&x"9443",'1'&x"9444",'1'&x"9445",'1'&x"9446",'1'&x"9447",'1'&x"9448",'1'&x"9449",'1'&x"944A",'1'&x"944B",'1'&x"944C",'1'&x"944D",'1'&x"944E",'1'&x"944F",
+--'1'&x"9450",'1'&x"9451",'1'&x"9452",'1'&x"9453",'1'&x"9454",'1'&x"9455",'1'&x"9456",'1'&x"9457",'1'&x"9458",'1'&x"9459",'1'&x"945A",'1'&x"945B",'1'&x"945C",'1'&x"945D",'1'&x"945E",'1'&x"945F",
+--'1'&x"9460",'1'&x"9461",'1'&x"9462",'1'&x"9463",'1'&x"9464",'1'&x"9465",'1'&x"9466",'1'&x"9467",'1'&x"9468",'1'&x"9469",'1'&x"946A",'1'&x"946B",'1'&x"946C",'1'&x"946D",'1'&x"946E",'1'&x"946F",
+--'1'&x"9470",'1'&x"9471",'1'&x"9472",'1'&x"9473",'1'&x"9474",'1'&x"9475",'1'&x"9476",'1'&x"9477",'1'&x"9478",'1'&x"9479",'1'&x"947A",'1'&x"947B",'1'&x"947C",'1'&x"947D",'1'&x"947E",'1'&x"947F",
+--'1'&x"9480",'1'&x"9481",'1'&x"9482",'1'&x"9483",'1'&x"9484",'1'&x"9485",'1'&x"9486",'1'&x"9487",'1'&x"9488",'1'&x"9489",'1'&x"948A",'1'&x"948B",'1'&x"948C",'1'&x"948D",'1'&x"948E",'1'&x"948F",
+--'1'&x"9490",'1'&x"9491",'1'&x"9492",'1'&x"9493",'1'&x"9494",'1'&x"9495",'1'&x"9496",'1'&x"9497",'1'&x"9498",'1'&x"9499",'1'&x"949A",'1'&x"949B",'1'&x"949C",'1'&x"949D",'1'&x"949E",'1'&x"949F",
+--'1'&x"94A0",'1'&x"94A1",'1'&x"94A2",'1'&x"94A3",'1'&x"94A4",'1'&x"94A5",'1'&x"94A6",'1'&x"94A7",'1'&x"94A8",'1'&x"94A9",'1'&x"94AA",'1'&x"94AB",'1'&x"94AC",'1'&x"94AD",'1'&x"94AE",'1'&x"94AF",
+--'1'&x"94B0",'1'&x"94B1",'1'&x"94B2",'1'&x"94B3",'1'&x"94B4",'1'&x"94B5",'1'&x"94B6",'1'&x"94B7",'1'&x"94B8",'1'&x"94B9",'1'&x"94BA",'1'&x"94BB",'1'&x"94BC",'1'&x"94BD",'1'&x"94BE",'1'&x"94BF",
+--'1'&x"94C0",'1'&x"94C1",'1'&x"94C2",'1'&x"94C3",'1'&x"94C4",'1'&x"94C5",'1'&x"94C6",'1'&x"94C7",'1'&x"94C8",'1'&x"94C9",'1'&x"94CA",'1'&x"94CB",'1'&x"94CC",'1'&x"94CD",'1'&x"94CE",'1'&x"94CF",
+--'1'&x"94D0",'1'&x"94D1",'1'&x"94D2",'1'&x"94D3",'1'&x"94D4",'1'&x"94D5",'1'&x"94D6",'1'&x"94D7",'1'&x"94D8",'1'&x"94D9",'1'&x"94DA",'1'&x"94DB",'1'&x"94DC",'1'&x"94DD",'1'&x"94DE",'1'&x"94DF",
+--'1'&x"94E0",'1'&x"94E1",'1'&x"94E2",'1'&x"94E3",'1'&x"94E4",'1'&x"94E5",'1'&x"94E6",'1'&x"94E7",'1'&x"94E8",'1'&x"94E9",'1'&x"94EA",'1'&x"94EB",'1'&x"94EC",'1'&x"94ED",'1'&x"94EE",'1'&x"94EF",
+--'1'&x"94F0",'1'&x"94F1",'1'&x"94F2",'1'&x"94F3",'1'&x"94F4",'1'&x"94F5",'1'&x"94F6",'1'&x"94F7",'1'&x"94F8",'1'&x"94F9",'1'&x"94FA",'1'&x"94FB",'1'&x"94FC",'1'&x"94FD",'1'&x"94FE",'1'&x"94FF",
+--'1'&x"9500",'1'&x"9501",'1'&x"9502",'1'&x"9503",'1'&x"9504",'1'&x"9505",'1'&x"9506",'1'&x"9507",'1'&x"9508",'1'&x"9509",'1'&x"950A",'1'&x"950B",'1'&x"950C",'1'&x"950D",'1'&x"950E",'1'&x"950F",
+--'1'&x"9510",'1'&x"9511",'1'&x"9512",'1'&x"9513",'1'&x"9514",'1'&x"9515",'1'&x"9516",'1'&x"9517",'1'&x"9518",'1'&x"9519",'1'&x"951A",'1'&x"951B",'1'&x"951C",'1'&x"951D",'1'&x"951E",'1'&x"951F",
+--'1'&x"9520",'1'&x"9521",'1'&x"9522",'1'&x"9523",'1'&x"9524",'1'&x"9525",'1'&x"9526",'1'&x"9527",'1'&x"9528",'1'&x"9529",'1'&x"952A",'1'&x"952B",'1'&x"952C",'1'&x"952D",'1'&x"952E",'1'&x"952F",
+--'1'&x"9530",'1'&x"9531",'1'&x"9532",'1'&x"9533",'1'&x"9534",'1'&x"9535",'1'&x"9536",'1'&x"9537",'1'&x"9538",'1'&x"9539",'1'&x"953A",'1'&x"953B",'1'&x"953C",'1'&x"953D",'1'&x"953E",'1'&x"953F",
+--'1'&x"9540",'1'&x"9541",'1'&x"9542",'1'&x"9543",'1'&x"9544",'1'&x"9545",'1'&x"9546",'1'&x"9547",'1'&x"9548",'1'&x"9549",'1'&x"954A",'1'&x"954B",'1'&x"954C",'1'&x"954D",'1'&x"954E",'1'&x"954F",
+--'1'&x"9550",'1'&x"9551",'1'&x"9552",'1'&x"9553",'1'&x"9554",'1'&x"9555",'1'&x"9556",'1'&x"9557",'1'&x"9558",'1'&x"9559",'1'&x"955A",'1'&x"955B",'1'&x"955C",'1'&x"955D",'1'&x"955E",'1'&x"955F",
+--'1'&x"9560",'1'&x"9561",'1'&x"9562",'1'&x"9563",'1'&x"9564",'1'&x"9565",'1'&x"9566",'1'&x"9567",'1'&x"9568",'1'&x"9569",'1'&x"956A",'1'&x"956B",'1'&x"956C",'1'&x"956D",'1'&x"956E",'1'&x"956F",
+--'1'&x"9570",'1'&x"9571",'1'&x"9572",'1'&x"9573",'1'&x"9574",'1'&x"9575",'1'&x"9576",'1'&x"9577",'1'&x"9578",'1'&x"9579",'1'&x"957A",'1'&x"957B",'1'&x"957C",'1'&x"957D",'1'&x"957E",'1'&x"957F",
+--'1'&x"9580",'1'&x"9581",'1'&x"9582",'1'&x"9583",'1'&x"9584",'1'&x"9585",'1'&x"9586",'1'&x"9587",'1'&x"9588",'1'&x"9589",'1'&x"958A",'1'&x"958B",'1'&x"958C",'1'&x"958D",'1'&x"958E",'1'&x"958F",
+--'1'&x"9590",'1'&x"9591",'1'&x"9592",'1'&x"9593",'1'&x"9594",'1'&x"9595",'1'&x"9596",'1'&x"9597",'1'&x"9598",'1'&x"9599",'1'&x"959A",'1'&x"959B",'1'&x"959C",'1'&x"959D",'1'&x"959E",'1'&x"959F",
+--'1'&x"95A0",'1'&x"95A1",'1'&x"95A2",'1'&x"95A3",'1'&x"95A4",'1'&x"95A5",'1'&x"95A6",'1'&x"95A7",'1'&x"95A8",'1'&x"95A9",'1'&x"95AA",'1'&x"95AB",'1'&x"95AC",'1'&x"95AD",'1'&x"95AE",'1'&x"95AF",
+--'1'&x"95B0",'1'&x"95B1",'1'&x"95B2",'1'&x"95B3",'1'&x"95B4",'1'&x"95B5",'1'&x"95B6",'1'&x"95B7",'1'&x"95B8",'1'&x"95B9",'1'&x"95BA",'1'&x"95BB",'1'&x"95BC",'1'&x"95BD",'1'&x"95BE",'1'&x"95BF",
+--'1'&x"95C0",'1'&x"95C1",'1'&x"95C2",'1'&x"95C3",'1'&x"95C4",'1'&x"95C5",'1'&x"95C6",'1'&x"95C7",'1'&x"95C8",'1'&x"95C9",'1'&x"95CA",'1'&x"95CB",'1'&x"95CC",'1'&x"95CD",'1'&x"95CE",'1'&x"95CF",
+--'1'&x"95D0",'1'&x"95D1",'1'&x"95D2",'1'&x"95D3",'1'&x"95D4",'1'&x"95D5",'1'&x"95D6",'1'&x"95D7",'1'&x"95D8",'1'&x"95D9",'1'&x"95DA",'1'&x"95DB",'1'&x"95DC",'1'&x"95DD",'1'&x"95DE",'1'&x"95DF",
+--'1'&x"95E0",'1'&x"95E1",'1'&x"95E2",'1'&x"95E3",'1'&x"95E4",'1'&x"95E5",'1'&x"95E6",'1'&x"95E7",'1'&x"95E8",'1'&x"95E9",'1'&x"95EA",'1'&x"95EB",'1'&x"95EC",'1'&x"95ED",'1'&x"95EE",'1'&x"95EF",
+--'1'&x"95F0",'1'&x"95F1",'1'&x"95F2",'1'&x"95F3",'1'&x"95F4",'1'&x"95F5",'1'&x"95F6",'1'&x"95F7",'1'&x"95F8",'1'&x"95F9",'1'&x"95FA",'1'&x"95FB",'1'&x"95FC",'1'&x"95FD",'1'&x"95FE",'1'&x"95FF",
+--'1'&x"9600",'1'&x"9601",'1'&x"9602",'1'&x"9603",'1'&x"9604",'1'&x"9605",'1'&x"9606",'1'&x"9607",'1'&x"9608",'1'&x"9609",'1'&x"960A",'1'&x"960B",'1'&x"960C",'1'&x"960D",'1'&x"960E",'1'&x"960F",
+--'1'&x"9610",'1'&x"9611",'1'&x"9612",'1'&x"9613",'1'&x"9614",'1'&x"9615",'1'&x"9616",'1'&x"9617",'1'&x"9618",'1'&x"9619",'1'&x"961A",'1'&x"961B",'1'&x"961C",'1'&x"961D",'1'&x"961E",'1'&x"961F",
+--'1'&x"9620",'1'&x"9621",'1'&x"9622",'1'&x"9623",'1'&x"9624",'1'&x"9625",'1'&x"9626",'1'&x"9627",'1'&x"9628",'1'&x"9629",'1'&x"962A",'1'&x"962B",'1'&x"962C",'1'&x"962D",'1'&x"962E",'1'&x"962F",
+--'1'&x"9630",'1'&x"9631",'1'&x"9632",'1'&x"9633",'1'&x"9634",'1'&x"9635",'1'&x"9636",'1'&x"9637",'1'&x"9638",'1'&x"9639",'1'&x"963A",'1'&x"963B",'1'&x"963C",'1'&x"963D",'1'&x"963E",'1'&x"963F",
+--'1'&x"9640",'1'&x"9641",'1'&x"9642",'1'&x"9643",'1'&x"9644",'1'&x"9645",'1'&x"9646",'1'&x"9647",'1'&x"9648",'1'&x"9649",'1'&x"964A",'1'&x"964B",'1'&x"964C",'1'&x"964D",'1'&x"964E",'1'&x"964F",
+--'1'&x"9650",'1'&x"9651",'1'&x"9652",'1'&x"9653",'1'&x"9654",'1'&x"9655",'1'&x"9656",'1'&x"9657",'1'&x"9658",'1'&x"9659",'1'&x"965A",'1'&x"965B",'1'&x"965C",'1'&x"965D",'1'&x"965E",'1'&x"965F",
+--'1'&x"9660",'1'&x"9661",'1'&x"9662",'1'&x"9663",'1'&x"9664",'1'&x"9665",'1'&x"9666",'1'&x"9667",'1'&x"9668",'1'&x"9669",'1'&x"966A",'1'&x"966B",'1'&x"966C",'1'&x"966D",'1'&x"966E",'1'&x"966F",
+--'1'&x"9670",'1'&x"9671",'1'&x"9672",'1'&x"9673",'1'&x"9674",'1'&x"9675",'1'&x"9676",'1'&x"9677",'1'&x"9678",'1'&x"9679",'1'&x"967A",'1'&x"967B",'1'&x"967C",'1'&x"967D",'1'&x"967E",'1'&x"967F",
+--'1'&x"9680",'1'&x"9681",'1'&x"9682",'1'&x"9683",'1'&x"9684",'1'&x"9685",'1'&x"9686",'1'&x"9687",'1'&x"9688",'1'&x"9689",'1'&x"968A",'1'&x"968B",'1'&x"968C",'1'&x"968D",'1'&x"968E",'1'&x"968F",
+--'1'&x"9690",'1'&x"9691",'1'&x"9692",'1'&x"9693",'1'&x"9694",'1'&x"9695",'1'&x"9696",'1'&x"9697",'1'&x"9698",'1'&x"9699",'1'&x"969A",'1'&x"969B",'1'&x"969C",'1'&x"969D",'1'&x"969E",'1'&x"969F",
+--'1'&x"96A0",'1'&x"96A1",'1'&x"96A2",'1'&x"96A3",'1'&x"96A4",'1'&x"96A5",'1'&x"96A6",'1'&x"96A7",'1'&x"96A8",'1'&x"96A9",'1'&x"96AA",'1'&x"96AB",'1'&x"96AC",'1'&x"96AD",'1'&x"96AE",'1'&x"96AF",
+--'1'&x"96B0",'1'&x"96B1",'1'&x"96B2",'1'&x"96B3",'1'&x"96B4",'1'&x"96B5",'1'&x"96B6",'1'&x"96B7",'1'&x"96B8",'1'&x"96B9",'1'&x"96BA",'1'&x"96BB",'1'&x"96BC",'1'&x"96BD",'1'&x"96BE",'1'&x"96BF",
+--'1'&x"96C0",'1'&x"96C1",'1'&x"96C2",'1'&x"96C3",'1'&x"96C4",'1'&x"96C5",'1'&x"96C6",'1'&x"96C7",'1'&x"96C8",'1'&x"96C9",'1'&x"96CA",'1'&x"96CB",'1'&x"96CC",'1'&x"96CD",'1'&x"96CE",'1'&x"96CF",
+--'1'&x"96D0",'1'&x"96D1",'1'&x"96D2",'1'&x"96D3",'1'&x"96D4",'1'&x"96D5",'1'&x"96D6",'1'&x"96D7",'1'&x"96D8",'1'&x"96D9",'1'&x"96DA",'1'&x"96DB",'1'&x"96DC",'1'&x"96DD",'1'&x"96DE",'1'&x"96DF",
+--'1'&x"96E0",'1'&x"96E1",'1'&x"96E2",'1'&x"96E3",'1'&x"96E4",'1'&x"96E5",'1'&x"96E6",'1'&x"96E7",'1'&x"96E8",'1'&x"96E9",'1'&x"96EA",'1'&x"96EB",'1'&x"96EC",'1'&x"96ED",'1'&x"96EE",'1'&x"96EF",
+--'1'&x"96F0",'1'&x"96F1",'1'&x"96F2",'1'&x"96F3",'1'&x"96F4",'1'&x"96F5",'1'&x"96F6",'1'&x"96F7",'1'&x"96F8",'1'&x"96F9",'1'&x"96FA",'1'&x"96FB",'1'&x"96FC",'1'&x"96FD",'1'&x"96FE",'1'&x"96FF",
+--'1'&x"9700",'1'&x"9701",'1'&x"9702",'1'&x"9703",'1'&x"9704",'1'&x"9705",'1'&x"9706",'1'&x"9707",'1'&x"9708",'1'&x"9709",'1'&x"970A",'1'&x"970B",'1'&x"970C",'1'&x"970D",'1'&x"970E",'1'&x"970F",
+--'1'&x"9710",'1'&x"9711",'1'&x"9712",'1'&x"9713",'1'&x"9714",'1'&x"9715",'1'&x"9716",'1'&x"9717",'1'&x"9718",'1'&x"9719",'1'&x"971A",'1'&x"971B",'1'&x"971C",'1'&x"971D",'1'&x"971E",'1'&x"971F",
+--'1'&x"9720",'1'&x"9721",'1'&x"9722",'1'&x"9723",'1'&x"9724",'1'&x"9725",'1'&x"9726",'1'&x"9727",'1'&x"9728",'1'&x"9729",'1'&x"972A",'1'&x"972B",'1'&x"972C",'1'&x"972D",'1'&x"972E",'1'&x"972F",
+--'1'&x"9730",'1'&x"9731",'1'&x"9732",'1'&x"9733",'1'&x"9734",'1'&x"9735",'1'&x"9736",'1'&x"9737",'1'&x"9738",'1'&x"9739",'1'&x"973A",'1'&x"973B",'1'&x"973C",'1'&x"973D",'1'&x"973E",'1'&x"973F",
+--'1'&x"9740",'1'&x"9741",'1'&x"9742",'1'&x"9743",'1'&x"9744",'1'&x"9745",'1'&x"9746",'1'&x"9747",'1'&x"9748",'1'&x"9749",'1'&x"974A",'1'&x"974B",'1'&x"974C",'1'&x"974D",'1'&x"974E",'1'&x"974F",
+--'1'&x"9750",'1'&x"9751",'1'&x"9752",'1'&x"9753",'1'&x"9754",'1'&x"9755",'1'&x"9756",'1'&x"9757",'1'&x"9758",'1'&x"9759",'1'&x"975A",'1'&x"975B",'1'&x"975C",'1'&x"975D",'1'&x"975E",'1'&x"975F",
+--'1'&x"9760",'1'&x"9761",'1'&x"9762",'1'&x"9763",'1'&x"9764",'1'&x"9765",'1'&x"9766",'1'&x"9767",'1'&x"9768",'1'&x"9769",'1'&x"976A",'1'&x"976B",'1'&x"976C",'1'&x"976D",'1'&x"976E",'1'&x"976F",
+--'1'&x"9770",'1'&x"9771",'1'&x"9772",'1'&x"9773",'1'&x"9774",'1'&x"9775",'1'&x"9776",'1'&x"9777",'1'&x"9778",'1'&x"9779",'1'&x"977A",'1'&x"977B",'1'&x"977C",'1'&x"977D",'1'&x"977E",'1'&x"977F",
+--'1'&x"9780",'1'&x"9781",'1'&x"9782",'1'&x"9783",'1'&x"9784",'1'&x"9785",'1'&x"9786",'1'&x"9787",'1'&x"9788",'1'&x"9789",'1'&x"978A",'1'&x"978B",'1'&x"978C",'1'&x"978D",'1'&x"978E",'1'&x"978F",
+--'1'&x"9790",'1'&x"9791",'1'&x"9792",'1'&x"9793",'1'&x"9794",'1'&x"9795",'1'&x"9796",'1'&x"9797",'1'&x"9798",'1'&x"9799",'1'&x"979A",'1'&x"979B",'1'&x"979C",'1'&x"979D",'1'&x"979E",'1'&x"979F",
+--'1'&x"97A0",'1'&x"97A1",'1'&x"97A2",'1'&x"97A3",'1'&x"97A4",'1'&x"97A5",'1'&x"97A6",'1'&x"97A7",'1'&x"97A8",'1'&x"97A9",'1'&x"97AA",'1'&x"97AB",'1'&x"97AC",'1'&x"97AD",'1'&x"97AE",'1'&x"97AF",
+--'1'&x"97B0",'1'&x"97B1",'1'&x"97B2",'1'&x"97B3",'1'&x"97B4",'1'&x"97B5",'1'&x"97B6",'1'&x"97B7",'1'&x"97B8",'1'&x"97B9",'1'&x"97BA",'1'&x"97BB",'1'&x"97BC",'1'&x"97BD",'1'&x"97BE",'1'&x"97BF",
+--'1'&x"97C0",'1'&x"97C1",'1'&x"97C2",'1'&x"97C3",'1'&x"97C4",'1'&x"97C5",'1'&x"97C6",'1'&x"97C7",'1'&x"97C8",'1'&x"97C9",'1'&x"97CA",'1'&x"97CB",'1'&x"97CC",'1'&x"97CD",'1'&x"97CE",'1'&x"97CF",
+--'1'&x"97D0",'1'&x"97D1",'1'&x"97D2",'1'&x"97D3",'1'&x"97D4",'1'&x"97D5",'1'&x"97D6",'1'&x"97D7",'1'&x"97D8",'1'&x"97D9",'1'&x"97DA",'1'&x"97DB",'1'&x"97DC",'1'&x"97DD",'1'&x"97DE",'1'&x"97DF",
+--'1'&x"97E0",'1'&x"97E1",'1'&x"97E2",'1'&x"97E3",'1'&x"97E4",'1'&x"97E5",'1'&x"97E6",'1'&x"97E7",'1'&x"97E8",'1'&x"97E9",'1'&x"97EA",'1'&x"97EB",'1'&x"97EC",'1'&x"97ED",'1'&x"97EE",'1'&x"97EF",
+--'1'&x"97F0",'1'&x"97F1",'1'&x"97F2",'1'&x"97F3",'1'&x"97F4",'1'&x"97F5",'1'&x"97F6",'1'&x"97F7",'1'&x"97F8",'1'&x"97F9",'1'&x"97FA",'1'&x"97FB",'1'&x"97FC",'1'&x"97FD",'1'&x"97FE",'1'&x"97FF",
+--'1'&x"9800",'1'&x"9801",'1'&x"9802",'1'&x"9803",'1'&x"9804",'1'&x"9805",'1'&x"9806",'1'&x"9807",'1'&x"9808",'1'&x"9809",'1'&x"980A",'1'&x"980B",'1'&x"980C",'1'&x"980D",'1'&x"980E",'1'&x"980F",
+--'1'&x"9810",'1'&x"9811",'1'&x"9812",'1'&x"9813",'1'&x"9814",'1'&x"9815",'1'&x"9816",'1'&x"9817",'1'&x"9818",'1'&x"9819",'1'&x"981A",'1'&x"981B",'1'&x"981C",'1'&x"981D",'1'&x"981E",'1'&x"981F",
+--'1'&x"9820",'1'&x"9821",'1'&x"9822",'1'&x"9823",'1'&x"9824",'1'&x"9825",'1'&x"9826",'1'&x"9827",'1'&x"9828",'1'&x"9829",'1'&x"982A",'1'&x"982B",'1'&x"982C",'1'&x"982D",'1'&x"982E",'1'&x"982F",
+--'1'&x"9830",'1'&x"9831",'1'&x"9832",'1'&x"9833",'1'&x"9834",'1'&x"9835",'1'&x"9836",'1'&x"9837",'1'&x"9838",'1'&x"9839",'1'&x"983A",'1'&x"983B",'1'&x"983C",'1'&x"983D",'1'&x"983E",'1'&x"983F",
+--'1'&x"9840",'1'&x"9841",'1'&x"9842",'1'&x"9843",'1'&x"9844",'1'&x"9845",'1'&x"9846",'1'&x"9847",'1'&x"9848",'1'&x"9849",'1'&x"984A",'1'&x"984B",'1'&x"984C",'1'&x"984D",'1'&x"984E",'1'&x"984F",
+--'1'&x"9850",'1'&x"9851",'1'&x"9852",'1'&x"9853",'1'&x"9854",'1'&x"9855",'1'&x"9856",'1'&x"9857",'1'&x"9858",'1'&x"9859",'1'&x"985A",'1'&x"985B",'1'&x"985C",'1'&x"985D",'1'&x"985E",'1'&x"985F",
+--'1'&x"9860",'1'&x"9861",'1'&x"9862",'1'&x"9863",'1'&x"9864",'1'&x"9865",'1'&x"9866",'1'&x"9867",'1'&x"9868",'1'&x"9869",'1'&x"986A",'1'&x"986B",'1'&x"986C",'1'&x"986D",'1'&x"986E",'1'&x"986F",
+--'1'&x"9870",'1'&x"9871",'1'&x"9872",'1'&x"9873",'1'&x"9874",'1'&x"9875",'1'&x"9876",'1'&x"9877",'1'&x"9878",'1'&x"9879",'1'&x"987A",'1'&x"987B",'1'&x"987C",'1'&x"987D",'1'&x"987E",'1'&x"987F",
+--'1'&x"9880",'1'&x"9881",'1'&x"9882",'1'&x"9883",'1'&x"9884",'1'&x"9885",'1'&x"9886",'1'&x"9887",'1'&x"9888",'1'&x"9889",'1'&x"988A",'1'&x"988B",'1'&x"988C",'1'&x"988D",'1'&x"988E",'1'&x"988F",
+--'1'&x"9890",'1'&x"9891",'1'&x"9892",'1'&x"9893",'1'&x"9894",'1'&x"9895",'1'&x"9896",'1'&x"9897",'1'&x"9898",'1'&x"9899",'1'&x"989A",'1'&x"989B",'1'&x"989C",'1'&x"989D",'1'&x"989E",'1'&x"989F",
+--'1'&x"98A0",'1'&x"98A1",'1'&x"98A2",'1'&x"98A3",'1'&x"98A4",'1'&x"98A5",'1'&x"98A6",'1'&x"98A7",'1'&x"98A8",'1'&x"98A9",'1'&x"98AA",'1'&x"98AB",'1'&x"98AC",'1'&x"98AD",'1'&x"98AE",'1'&x"98AF",
+--'1'&x"98B0",'1'&x"98B1",'1'&x"98B2",'1'&x"98B3",'1'&x"98B4",'1'&x"98B5",'1'&x"98B6",'1'&x"98B7",'1'&x"98B8",'1'&x"98B9",'1'&x"98BA",'1'&x"98BB",'1'&x"98BC",'1'&x"98BD",'1'&x"98BE",'1'&x"98BF",
+--'1'&x"98C0",'1'&x"98C1",'1'&x"98C2",'1'&x"98C3",'1'&x"98C4",'1'&x"98C5",'1'&x"98C6",'1'&x"98C7",'1'&x"98C8",'1'&x"98C9",'1'&x"98CA",'1'&x"98CB",'1'&x"98CC",'1'&x"98CD",'1'&x"98CE",'1'&x"98CF",
+--'1'&x"98D0",'1'&x"98D1",'1'&x"98D2",'1'&x"98D3",'1'&x"98D4",'1'&x"98D5",'1'&x"98D6",'1'&x"98D7",'1'&x"98D8",'1'&x"98D9",'1'&x"98DA",'1'&x"98DB",'1'&x"98DC",'1'&x"98DD",'1'&x"98DE",'1'&x"98DF",
+--'1'&x"98E0",'1'&x"98E1",'1'&x"98E2",'1'&x"98E3",'1'&x"98E4",'1'&x"98E5",'1'&x"98E6",'1'&x"98E7",'1'&x"98E8",'1'&x"98E9",'1'&x"98EA",'1'&x"98EB",'1'&x"98EC",'1'&x"98ED",'1'&x"98EE",'1'&x"98EF",
+--'1'&x"98F0",'1'&x"98F1",'1'&x"98F2",'1'&x"98F3",'1'&x"98F4",'1'&x"98F5",'1'&x"98F6",'1'&x"98F7",'1'&x"98F8",'1'&x"98F9",'1'&x"98FA",'1'&x"98FB",'1'&x"98FC",'1'&x"98FD",'1'&x"98FE",'1'&x"98FF",
+--'1'&x"9900",'1'&x"9901",'1'&x"9902",'1'&x"9903",'1'&x"9904",'1'&x"9905",'1'&x"9906",'1'&x"9907",'1'&x"9908",'1'&x"9909",'1'&x"990A",'1'&x"990B",'1'&x"990C",'1'&x"990D",'1'&x"990E",'1'&x"990F",
+--'1'&x"9910",'1'&x"9911",'1'&x"9912",'1'&x"9913",'1'&x"9914",'1'&x"9915",'1'&x"9916",'1'&x"9917",'1'&x"9918",'1'&x"9919",'1'&x"991A",'1'&x"991B",'1'&x"991C",'1'&x"991D",'1'&x"991E",'1'&x"991F",
+--'1'&x"9920",'1'&x"9921",'1'&x"9922",'1'&x"9923",'1'&x"9924",'1'&x"9925",'1'&x"9926",'1'&x"9927",'1'&x"9928",'1'&x"9929",'1'&x"992A",'1'&x"992B",'1'&x"992C",'1'&x"992D",'1'&x"992E",'1'&x"992F",
+--'1'&x"9930",'1'&x"9931",'1'&x"9932",'1'&x"9933",'1'&x"9934",'1'&x"9935",'1'&x"9936",'1'&x"9937",'1'&x"9938",'1'&x"9939",'1'&x"993A",'1'&x"993B",'1'&x"993C",'1'&x"993D",'1'&x"993E",'1'&x"993F",
+--'1'&x"9940",'1'&x"9941",'1'&x"9942",'1'&x"9943",'1'&x"9944",'1'&x"9945",'1'&x"9946",'1'&x"9947",'1'&x"9948",'1'&x"9949",'1'&x"994A",'1'&x"994B",'1'&x"994C",'1'&x"994D",'1'&x"994E",'1'&x"994F",
+--'1'&x"9950",'1'&x"9951",'1'&x"9952",'1'&x"9953",'1'&x"9954",'1'&x"9955",'1'&x"9956",'1'&x"9957",'1'&x"9958",'1'&x"9959",'1'&x"995A",'1'&x"995B",'1'&x"995C",'1'&x"995D",'1'&x"995E",'1'&x"995F",
+--'1'&x"9960",'1'&x"9961",'1'&x"9962",'1'&x"9963",'1'&x"9964",'1'&x"9965",'1'&x"9966",'1'&x"9967",'1'&x"9968",'1'&x"9969",'1'&x"996A",'1'&x"996B",'1'&x"996C",'1'&x"996D",'1'&x"996E",'1'&x"996F",
+--'1'&x"9970",'1'&x"9971",'1'&x"9972",'1'&x"9973",'1'&x"9974",'1'&x"9975",'1'&x"9976",'1'&x"9977",'1'&x"9978",'1'&x"9979",'1'&x"997A",'1'&x"997B",'1'&x"997C",'1'&x"997D",'1'&x"997E",'1'&x"997F",
+--'1'&x"9980",'1'&x"9981",'1'&x"9982",'1'&x"9983",'1'&x"9984",'1'&x"9985",'1'&x"9986",'1'&x"9987",'1'&x"9988",'1'&x"9989",'1'&x"998A",'1'&x"998B",'1'&x"998C",'1'&x"998D",'1'&x"998E",'1'&x"998F",
+--'1'&x"9990",'1'&x"9991",'1'&x"9992",'1'&x"9993",'1'&x"9994",'1'&x"9995",'1'&x"9996",'1'&x"9997",'1'&x"9998",'1'&x"9999",'1'&x"999A",'1'&x"999B",'1'&x"999C",'1'&x"999D",'1'&x"999E",'1'&x"999F",
+--'1'&x"99A0",'1'&x"99A1",'1'&x"99A2",'1'&x"99A3",'1'&x"99A4",'1'&x"99A5",'1'&x"99A6",'1'&x"99A7",'1'&x"99A8",'1'&x"99A9",'1'&x"99AA",'1'&x"99AB",'1'&x"99AC",'1'&x"99AD",'1'&x"99AE",'1'&x"99AF",
+--'1'&x"99B0",'1'&x"99B1",'1'&x"99B2",'1'&x"99B3",'1'&x"99B4",'1'&x"99B5",'1'&x"99B6",'1'&x"99B7",'1'&x"99B8",'1'&x"99B9",'1'&x"99BA",'1'&x"99BB",'1'&x"99BC",'1'&x"99BD",'1'&x"99BE",'1'&x"99BF",
+--'1'&x"99C0",'1'&x"99C1",'1'&x"99C2",'1'&x"99C3",'1'&x"99C4",'1'&x"99C5",'1'&x"99C6",'1'&x"99C7",'1'&x"99C8",'1'&x"99C9",'1'&x"99CA",'1'&x"99CB",'1'&x"99CC",'1'&x"99CD",'1'&x"99CE",'1'&x"99CF",
+--'1'&x"99D0",'1'&x"99D1",'1'&x"99D2",'1'&x"99D3",'1'&x"99D4",'1'&x"99D5",'1'&x"99D6",'1'&x"99D7",'1'&x"99D8",'1'&x"99D9",'1'&x"99DA",'1'&x"99DB",'1'&x"99DC",'1'&x"99DD",'1'&x"99DE",'1'&x"99DF",
+--'1'&x"99E0",'1'&x"99E1",'1'&x"99E2",'1'&x"99E3",'1'&x"99E4",'1'&x"99E5",'1'&x"99E6",'1'&x"99E7",'1'&x"99E8",'1'&x"99E9",'1'&x"99EA",'1'&x"99EB",'1'&x"99EC",'1'&x"99ED",'1'&x"99EE",'1'&x"99EF",
+--'1'&x"99F0",'1'&x"99F1",'1'&x"99F2",'1'&x"99F3",'1'&x"99F4",'1'&x"99F5",'1'&x"99F6",'1'&x"99F7",'1'&x"99F8",'1'&x"99F9",'1'&x"99FA",'1'&x"99FB",'1'&x"99FC",'1'&x"99FD",'1'&x"99FE",'1'&x"99FF",
+--'1'&x"9A00",'1'&x"9A01",'1'&x"9A02",'1'&x"9A03",'1'&x"9A04",'1'&x"9A05",'1'&x"9A06",'1'&x"9A07",'1'&x"9A08",'1'&x"9A09",'1'&x"9A0A",'1'&x"9A0B",'1'&x"9A0C",'1'&x"9A0D",'1'&x"9A0E",'1'&x"9A0F",
+--'1'&x"9A10",'1'&x"9A11",'1'&x"9A12",'1'&x"9A13",'1'&x"9A14",'1'&x"9A15",'1'&x"9A16",'1'&x"9A17",'1'&x"9A18",'1'&x"9A19",'1'&x"9A1A",'1'&x"9A1B",'1'&x"9A1C",'1'&x"9A1D",'1'&x"9A1E",'1'&x"9A1F",
+--'1'&x"9A20",'1'&x"9A21",'1'&x"9A22",'1'&x"9A23",'1'&x"9A24",'1'&x"9A25",'1'&x"9A26",'1'&x"9A27",'1'&x"9A28",'1'&x"9A29",'1'&x"9A2A",'1'&x"9A2B",'1'&x"9A2C",'1'&x"9A2D",'1'&x"9A2E",'1'&x"9A2F",
+--'1'&x"9A30",'1'&x"9A31",'1'&x"9A32",'1'&x"9A33",'1'&x"9A34",'1'&x"9A35",'1'&x"9A36",'1'&x"9A37",'1'&x"9A38",'1'&x"9A39",'1'&x"9A3A",'1'&x"9A3B",'1'&x"9A3C",'1'&x"9A3D",'1'&x"9A3E",'1'&x"9A3F",
+--'1'&x"9A40",'1'&x"9A41",'1'&x"9A42",'1'&x"9A43",'1'&x"9A44",'1'&x"9A45",'1'&x"9A46",'1'&x"9A47",'1'&x"9A48",'1'&x"9A49",'1'&x"9A4A",'1'&x"9A4B",'1'&x"9A4C",'1'&x"9A4D",'1'&x"9A4E",'1'&x"9A4F",
+--'1'&x"9A50",'1'&x"9A51",'1'&x"9A52",'1'&x"9A53",'1'&x"9A54",'1'&x"9A55",'1'&x"9A56",'1'&x"9A57",'1'&x"9A58",'1'&x"9A59",'1'&x"9A5A",'1'&x"9A5B",'1'&x"9A5C",'1'&x"9A5D",'1'&x"9A5E",'1'&x"9A5F",
+--'1'&x"9A60",'1'&x"9A61",'1'&x"9A62",'1'&x"9A63",'1'&x"9A64",'1'&x"9A65",'1'&x"9A66",'1'&x"9A67",'1'&x"9A68",'1'&x"9A69",'1'&x"9A6A",'1'&x"9A6B",'1'&x"9A6C",'1'&x"9A6D",'1'&x"9A6E",'1'&x"9A6F",
+--'1'&x"9A70",'1'&x"9A71",'1'&x"9A72",'1'&x"9A73",'1'&x"9A74",'1'&x"9A75",'1'&x"9A76",'1'&x"9A77",'1'&x"9A78",'1'&x"9A79",'1'&x"9A7A",'1'&x"9A7B",'1'&x"9A7C",'1'&x"9A7D",'1'&x"9A7E",'1'&x"9A7F",
+--'1'&x"9A80",'1'&x"9A81",'1'&x"9A82",'1'&x"9A83",'1'&x"9A84",'1'&x"9A85",'1'&x"9A86",'1'&x"9A87",'1'&x"9A88",'1'&x"9A89",'1'&x"9A8A",'1'&x"9A8B",'1'&x"9A8C",'1'&x"9A8D",'1'&x"9A8E",'1'&x"9A8F",
+--'1'&x"9A90",'1'&x"9A91",'1'&x"9A92",'1'&x"9A93",'1'&x"9A94",'1'&x"9A95",'1'&x"9A96",'1'&x"9A97",'1'&x"9A98",'1'&x"9A99",'1'&x"9A9A",'1'&x"9A9B",'1'&x"9A9C",'1'&x"9A9D",'1'&x"9A9E",'1'&x"9A9F",
+--'1'&x"9AA0",'1'&x"9AA1",'1'&x"9AA2",'1'&x"9AA3",'1'&x"9AA4",'1'&x"9AA5",'1'&x"9AA6",'1'&x"9AA7",'1'&x"9AA8",'1'&x"9AA9",'1'&x"9AAA",'1'&x"9AAB",'1'&x"9AAC",'1'&x"9AAD",'1'&x"9AAE",'1'&x"9AAF",
+--'1'&x"9AB0",'1'&x"9AB1",'1'&x"9AB2",'1'&x"9AB3",'1'&x"9AB4",'1'&x"9AB5",'1'&x"9AB6",'1'&x"9AB7",'1'&x"9AB8",'1'&x"9AB9",'1'&x"9ABA",'1'&x"9ABB",'1'&x"9ABC",'1'&x"9ABD",'1'&x"9ABE",'1'&x"9ABF",
+--'1'&x"9AC0",'1'&x"9AC1",'1'&x"9AC2",'1'&x"9AC3",'1'&x"9AC4",'1'&x"9AC5",'1'&x"9AC6",'1'&x"9AC7",'1'&x"9AC8",'1'&x"9AC9",'1'&x"9ACA",'1'&x"9ACB",'1'&x"9ACC",'1'&x"9ACD",'1'&x"9ACE",'1'&x"9ACF",
+--'1'&x"9AD0",'1'&x"9AD1",'1'&x"9AD2",'1'&x"9AD3",'1'&x"9AD4",'1'&x"9AD5",'1'&x"9AD6",'1'&x"9AD7",'1'&x"9AD8",'1'&x"9AD9",'1'&x"9ADA",'1'&x"9ADB",'1'&x"9ADC",'1'&x"9ADD",'1'&x"9ADE",'1'&x"9ADF",
+--'1'&x"9AE0",'1'&x"9AE1",'1'&x"9AE2",'1'&x"9AE3",'1'&x"9AE4",'1'&x"9AE5",'1'&x"9AE6",'1'&x"9AE7",'1'&x"9AE8",'1'&x"9AE9",'1'&x"9AEA",'1'&x"9AEB",'1'&x"9AEC",'1'&x"9AED",'1'&x"9AEE",'1'&x"9AEF",
+--'1'&x"9AF0",'1'&x"9AF1",'1'&x"9AF2",'1'&x"9AF3",'1'&x"9AF4",'1'&x"9AF5",'1'&x"9AF6",'1'&x"9AF7",'1'&x"9AF8",'1'&x"9AF9",'1'&x"9AFA",'1'&x"9AFB",'1'&x"9AFC",'1'&x"9AFD",'1'&x"9AFE",'1'&x"9AFF",
+--'1'&x"9B00",'1'&x"9B01",'1'&x"9B02",'1'&x"9B03",'1'&x"9B04",'1'&x"9B05",'1'&x"9B06",'1'&x"9B07",'1'&x"9B08",'1'&x"9B09",'1'&x"9B0A",'1'&x"9B0B",'1'&x"9B0C",'1'&x"9B0D",'1'&x"9B0E",'1'&x"9B0F",
+--'1'&x"9B10",'1'&x"9B11",'1'&x"9B12",'1'&x"9B13",'1'&x"9B14",'1'&x"9B15",'1'&x"9B16",'1'&x"9B17",'1'&x"9B18",'1'&x"9B19",'1'&x"9B1A",'1'&x"9B1B",'1'&x"9B1C",'1'&x"9B1D",'1'&x"9B1E",'1'&x"9B1F",
+--'1'&x"9B20",'1'&x"9B21",'1'&x"9B22",'1'&x"9B23",'1'&x"9B24",'1'&x"9B25",'1'&x"9B26",'1'&x"9B27",'1'&x"9B28",'1'&x"9B29",'1'&x"9B2A",'1'&x"9B2B",'1'&x"9B2C",'1'&x"9B2D",'1'&x"9B2E",'1'&x"9B2F",
+--'1'&x"9B30",'1'&x"9B31",'1'&x"9B32",'1'&x"9B33",'1'&x"9B34",'1'&x"9B35",'1'&x"9B36",'1'&x"9B37",'1'&x"9B38",'1'&x"9B39",'1'&x"9B3A",'1'&x"9B3B",'1'&x"9B3C",'1'&x"9B3D",'1'&x"9B3E",'1'&x"9B3F",
+--'1'&x"9B40",'1'&x"9B41",'1'&x"9B42",'1'&x"9B43",'1'&x"9B44",'1'&x"9B45",'1'&x"9B46",'1'&x"9B47",'1'&x"9B48",'1'&x"9B49",'1'&x"9B4A",'1'&x"9B4B",'1'&x"9B4C",'1'&x"9B4D",'1'&x"9B4E",'1'&x"9B4F",
+--'1'&x"9B50",'1'&x"9B51",'1'&x"9B52",'1'&x"9B53",'1'&x"9B54",'1'&x"9B55",'1'&x"9B56",'1'&x"9B57",'1'&x"9B58",'1'&x"9B59",'1'&x"9B5A",'1'&x"9B5B",'1'&x"9B5C",'1'&x"9B5D",'1'&x"9B5E",'1'&x"9B5F",
+--'1'&x"9B60",'1'&x"9B61",'1'&x"9B62",'1'&x"9B63",'1'&x"9B64",'1'&x"9B65",'1'&x"9B66",'1'&x"9B67",'1'&x"9B68",'1'&x"9B69",'1'&x"9B6A",'1'&x"9B6B",'1'&x"9B6C",'1'&x"9B6D",'1'&x"9B6E",'1'&x"9B6F",
+--'1'&x"9B70",'1'&x"9B71",'1'&x"9B72",'1'&x"9B73",'1'&x"9B74",'1'&x"9B75",'1'&x"9B76",'1'&x"9B77",'1'&x"9B78",'1'&x"9B79",'1'&x"9B7A",'1'&x"9B7B",'1'&x"9B7C",'1'&x"9B7D",'1'&x"9B7E",'1'&x"9B7F",
+--'1'&x"9B80",'1'&x"9B81",'1'&x"9B82",'1'&x"9B83",'1'&x"9B84",'1'&x"9B85",'1'&x"9B86",'1'&x"9B87",'1'&x"9B88",'1'&x"9B89",'1'&x"9B8A",'1'&x"9B8B",'1'&x"9B8C",'1'&x"9B8D",'1'&x"9B8E",'1'&x"9B8F",
+--'1'&x"9B90",'1'&x"9B91",'1'&x"9B92",'1'&x"9B93",'1'&x"9B94",'1'&x"9B95",'1'&x"9B96",'1'&x"9B97",'1'&x"9B98",'1'&x"9B99",'1'&x"9B9A",'1'&x"9B9B",'1'&x"9B9C",'1'&x"9B9D",'1'&x"9B9E",'1'&x"9B9F",
+--'1'&x"9BA0",'1'&x"9BA1",'1'&x"9BA2",'1'&x"9BA3",'1'&x"9BA4",'1'&x"9BA5",'1'&x"9BA6",'1'&x"9BA7",'1'&x"9BA8",'1'&x"9BA9",'1'&x"9BAA",'1'&x"9BAB",'1'&x"9BAC",'1'&x"9BAD",'1'&x"9BAE",'1'&x"9BAF",
+--'1'&x"9BB0",'1'&x"9BB1",'1'&x"9BB2",'1'&x"9BB3",'1'&x"9BB4",'1'&x"9BB5",'1'&x"9BB6",'1'&x"9BB7",'1'&x"9BB8",'1'&x"9BB9",'1'&x"9BBA",'1'&x"9BBB",'1'&x"9BBC",'1'&x"9BBD",'1'&x"9BBE",'1'&x"9BBF",
+--'1'&x"9BC0",'1'&x"9BC1",'1'&x"9BC2",'1'&x"9BC3",'1'&x"9BC4",'1'&x"9BC5",'1'&x"9BC6",'1'&x"9BC7",'1'&x"9BC8",'1'&x"9BC9",'1'&x"9BCA",'1'&x"9BCB",'1'&x"9BCC",'1'&x"9BCD",'1'&x"9BCE",'1'&x"9BCF",
+--'1'&x"9BD0",'1'&x"9BD1",'1'&x"9BD2",'1'&x"9BD3",'1'&x"9BD4",'1'&x"9BD5",'1'&x"9BD6",'1'&x"9BD7",'1'&x"9BD8",'1'&x"9BD9",'1'&x"9BDA",'1'&x"9BDB",'1'&x"9BDC",'1'&x"9BDD",'1'&x"9BDE",'1'&x"9BDF",
+--'1'&x"9BE0",'1'&x"9BE1",'1'&x"9BE2",'1'&x"9BE3",'1'&x"9BE4",'1'&x"9BE5",'1'&x"9BE6",'1'&x"9BE7",'1'&x"9BE8",'1'&x"9BE9",'1'&x"9BEA",'1'&x"9BEB",'1'&x"9BEC",'1'&x"9BED",'1'&x"9BEE",'1'&x"9BEF",
+--'1'&x"9BF0",'1'&x"9BF1",'1'&x"9BF2",'1'&x"9BF3",'1'&x"9BF4",'1'&x"9BF5",'1'&x"9BF6",'1'&x"9BF7",'1'&x"9BF8",'1'&x"9BF9",'1'&x"9BFA",'1'&x"9BFB",'1'&x"9BFC",'1'&x"9BFD",'1'&x"9BFE",'1'&x"9BFF",
+--'1'&x"9C00",'1'&x"9C01",'1'&x"9C02",'1'&x"9C03",'1'&x"9C04",'1'&x"9C05",'1'&x"9C06",'1'&x"9C07",'1'&x"9C08",'1'&x"9C09",'1'&x"9C0A",'1'&x"9C0B",'1'&x"9C0C",'1'&x"9C0D",'1'&x"9C0E",'1'&x"9C0F",
+--'1'&x"9C10",'1'&x"9C11",'1'&x"9C12",'1'&x"9C13",'1'&x"9C14",'1'&x"9C15",'1'&x"9C16",'1'&x"9C17",'1'&x"9C18",'1'&x"9C19",'1'&x"9C1A",'1'&x"9C1B",'1'&x"9C1C",'1'&x"9C1D",'1'&x"9C1E",'1'&x"9C1F",
+--'1'&x"9C20",'1'&x"9C21",'1'&x"9C22",'1'&x"9C23",'1'&x"9C24",'1'&x"9C25",'1'&x"9C26",'1'&x"9C27",'1'&x"9C28",'1'&x"9C29",'1'&x"9C2A",'1'&x"9C2B",'1'&x"9C2C",'1'&x"9C2D",'1'&x"9C2E",'1'&x"9C2F",
+--'1'&x"9C30",'1'&x"9C31",'1'&x"9C32",'1'&x"9C33",'1'&x"9C34",'1'&x"9C35",'1'&x"9C36",'1'&x"9C37",'1'&x"9C38",'1'&x"9C39",'1'&x"9C3A",'1'&x"9C3B",'1'&x"9C3C",'1'&x"9C3D",'1'&x"9C3E",'1'&x"9C3F",
+--'1'&x"9C40",'1'&x"9C41",'1'&x"9C42",'1'&x"9C43",'1'&x"9C44",'1'&x"9C45",'1'&x"9C46",'1'&x"9C47",'1'&x"9C48",'1'&x"9C49",'1'&x"9C4A",'1'&x"9C4B",'1'&x"9C4C",'1'&x"9C4D",'1'&x"9C4E",'1'&x"9C4F",
+--'1'&x"9C50",'1'&x"9C51",'1'&x"9C52",'1'&x"9C53",'1'&x"9C54",'1'&x"9C55",'1'&x"9C56",'1'&x"9C57",'1'&x"9C58",'1'&x"9C59",'1'&x"9C5A",'1'&x"9C5B",'1'&x"9C5C",'1'&x"9C5D",'1'&x"9C5E",'1'&x"9C5F",
+--'1'&x"9C60",'1'&x"9C61",'1'&x"9C62",'1'&x"9C63",'1'&x"9C64",'1'&x"9C65",'1'&x"9C66",'1'&x"9C67",'1'&x"9C68",'1'&x"9C69",'1'&x"9C6A",'1'&x"9C6B",'1'&x"9C6C",'1'&x"9C6D",'1'&x"9C6E",'1'&x"9C6F",
+--'1'&x"9C70",'1'&x"9C71",'1'&x"9C72",'1'&x"9C73",'1'&x"9C74",'1'&x"9C75",'1'&x"9C76",'1'&x"9C77",'1'&x"9C78",'1'&x"9C79",'1'&x"9C7A",'1'&x"9C7B",'1'&x"9C7C",'1'&x"9C7D",'1'&x"9C7E",'1'&x"9C7F",
+--'1'&x"9C80",'1'&x"9C81",'1'&x"9C82",'1'&x"9C83",'1'&x"9C84",'1'&x"9C85",'1'&x"9C86",'1'&x"9C87",'1'&x"9C88",'1'&x"9C89",'1'&x"9C8A",'1'&x"9C8B",'1'&x"9C8C",'1'&x"9C8D",'1'&x"9C8E",'1'&x"9C8F",
+--'1'&x"9C90",'1'&x"9C91",'1'&x"9C92",'1'&x"9C93",'1'&x"9C94",'1'&x"9C95",'1'&x"9C96",'1'&x"9C97",'1'&x"9C98",'1'&x"9C99",'1'&x"9C9A",'1'&x"9C9B",'1'&x"9C9C",'1'&x"9C9D",'1'&x"9C9E",'1'&x"9C9F",
+--'1'&x"9CA0",'1'&x"9CA1",'1'&x"9CA2",'1'&x"9CA3",'1'&x"9CA4",'1'&x"9CA5",'1'&x"9CA6",'1'&x"9CA7",'1'&x"9CA8",'1'&x"9CA9",'1'&x"9CAA",'1'&x"9CAB",'1'&x"9CAC",'1'&x"9CAD",'1'&x"9CAE",'1'&x"9CAF",
+--'1'&x"9CB0",'1'&x"9CB1",'1'&x"9CB2",'1'&x"9CB3",'1'&x"9CB4",'1'&x"9CB5",'1'&x"9CB6",'1'&x"9CB7",'1'&x"9CB8",'1'&x"9CB9",'1'&x"9CBA",'1'&x"9CBB",'1'&x"9CBC",'1'&x"9CBD",'1'&x"9CBE",'1'&x"9CBF",
+--'1'&x"9CC0",'1'&x"9CC1",'1'&x"9CC2",'1'&x"9CC3",'1'&x"9CC4",'1'&x"9CC5",'1'&x"9CC6",'1'&x"9CC7",'1'&x"9CC8",'1'&x"9CC9",'1'&x"9CCA",'1'&x"9CCB",'1'&x"9CCC",'1'&x"9CCD",'1'&x"9CCE",'1'&x"9CCF",
+--'1'&x"9CD0",'1'&x"9CD1",'1'&x"9CD2",'1'&x"9CD3",'1'&x"9CD4",'1'&x"9CD5",'1'&x"9CD6",'1'&x"9CD7",'1'&x"9CD8",'1'&x"9CD9",'1'&x"9CDA",'1'&x"9CDB",'1'&x"9CDC",'1'&x"9CDD",'1'&x"9CDE",'1'&x"9CDF",
+--'1'&x"9CE0",'1'&x"9CE1",'1'&x"9CE2",'1'&x"9CE3",'1'&x"9CE4",'1'&x"9CE5",'1'&x"9CE6",'1'&x"9CE7",'1'&x"9CE8",'1'&x"9CE9",'1'&x"9CEA",'1'&x"9CEB",'1'&x"9CEC",'1'&x"9CED",'1'&x"9CEE",'1'&x"9CEF",
+--'1'&x"9CF0",'1'&x"9CF1",'1'&x"9CF2",'1'&x"9CF3",'1'&x"9CF4",'1'&x"9CF5",'1'&x"9CF6",'1'&x"9CF7",'1'&x"9CF8",'1'&x"9CF9",'1'&x"9CFA",'1'&x"9CFB",'1'&x"9CFC",'1'&x"9CFD",'1'&x"9CFE",'1'&x"9CFF",
+--'1'&x"9D00",'1'&x"9D01",'1'&x"9D02",'1'&x"9D03",'1'&x"9D04",'1'&x"9D05",'1'&x"9D06",'1'&x"9D07",'1'&x"9D08",'1'&x"9D09",'1'&x"9D0A",'1'&x"9D0B",'1'&x"9D0C",'1'&x"9D0D",'1'&x"9D0E",'1'&x"9D0F",
+--'1'&x"9D10",'1'&x"9D11",'1'&x"9D12",'1'&x"9D13",'1'&x"9D14",'1'&x"9D15",'1'&x"9D16",'1'&x"9D17",'1'&x"9D18",'1'&x"9D19",'1'&x"9D1A",'1'&x"9D1B",'1'&x"9D1C",'1'&x"9D1D",'1'&x"9D1E",'1'&x"9D1F",
+--'1'&x"9D20",'1'&x"9D21",'1'&x"9D22",'1'&x"9D23",'1'&x"9D24",'1'&x"9D25",'1'&x"9D26",'1'&x"9D27",'1'&x"9D28",'1'&x"9D29",'1'&x"9D2A",'1'&x"9D2B",'1'&x"9D2C",'1'&x"9D2D",'1'&x"9D2E",'1'&x"9D2F",
+--'1'&x"9D30",'1'&x"9D31",'1'&x"9D32",'1'&x"9D33",'1'&x"9D34",'1'&x"9D35",'1'&x"9D36",'1'&x"9D37",'1'&x"9D38",'1'&x"9D39",'1'&x"9D3A",'1'&x"9D3B",'1'&x"9D3C",'1'&x"9D3D",'1'&x"9D3E",'1'&x"9D3F",
+--'1'&x"9D40",'1'&x"9D41",'1'&x"9D42",'1'&x"9D43",'1'&x"9D44",'1'&x"9D45",'1'&x"9D46",'1'&x"9D47",'1'&x"9D48",'1'&x"9D49",'1'&x"9D4A",'1'&x"9D4B",'1'&x"9D4C",'1'&x"9D4D",'1'&x"9D4E",'1'&x"9D4F",
+--'1'&x"9D50",'1'&x"9D51",'1'&x"9D52",'1'&x"9D53",'1'&x"9D54",'1'&x"9D55",'1'&x"9D56",'1'&x"9D57",'1'&x"9D58",'1'&x"9D59",'1'&x"9D5A",'1'&x"9D5B",'1'&x"9D5C",'1'&x"9D5D",'1'&x"9D5E",'1'&x"9D5F",
+--'1'&x"9D60",'1'&x"9D61",'1'&x"9D62",'1'&x"9D63",'1'&x"9D64",'1'&x"9D65",'1'&x"9D66",'1'&x"9D67",'1'&x"9D68",'1'&x"9D69",'1'&x"9D6A",'1'&x"9D6B",'1'&x"9D6C",'1'&x"9D6D",'1'&x"9D6E",'1'&x"9D6F",
+--'1'&x"9D70",'1'&x"9D71",'1'&x"9D72",'1'&x"9D73",'1'&x"9D74",'1'&x"9D75",'1'&x"9D76",'1'&x"9D77",'1'&x"9D78",'1'&x"9D79",'1'&x"9D7A",'1'&x"9D7B",'1'&x"9D7C",'1'&x"9D7D",'1'&x"9D7E",'1'&x"9D7F",
+--'1'&x"9D80",'1'&x"9D81",'1'&x"9D82",'1'&x"9D83",'1'&x"9D84",'1'&x"9D85",'1'&x"9D86",'1'&x"9D87",'1'&x"9D88",'1'&x"9D89",'1'&x"9D8A",'1'&x"9D8B",'1'&x"9D8C",'1'&x"9D8D",'1'&x"9D8E",'1'&x"9D8F",
+--'1'&x"9D90",'1'&x"9D91",'1'&x"9D92",'1'&x"9D93",'1'&x"9D94",'1'&x"9D95",'1'&x"9D96",'1'&x"9D97",'1'&x"9D98",'1'&x"9D99",'1'&x"9D9A",'1'&x"9D9B",'1'&x"9D9C",'1'&x"9D9D",'1'&x"9D9E",'1'&x"9D9F",
+--'1'&x"9DA0",'1'&x"9DA1",'1'&x"9DA2",'1'&x"9DA3",'1'&x"9DA4",'1'&x"9DA5",'1'&x"9DA6",'1'&x"9DA7",'1'&x"9DA8",'1'&x"9DA9",'1'&x"9DAA",'1'&x"9DAB",'1'&x"9DAC",'1'&x"9DAD",'1'&x"9DAE",'1'&x"9DAF",
+--'1'&x"9DB0",'1'&x"9DB1",'1'&x"9DB2",'1'&x"9DB3",'1'&x"9DB4",'1'&x"9DB5",'1'&x"9DB6",'1'&x"9DB7",'1'&x"9DB8",'1'&x"9DB9",'1'&x"9DBA",'1'&x"9DBB",'1'&x"9DBC",'1'&x"9DBD",'1'&x"9DBE",'1'&x"9DBF",
+--'1'&x"9DC0",'1'&x"9DC1",'1'&x"9DC2",'1'&x"9DC3",'1'&x"9DC4",'1'&x"9DC5",'1'&x"9DC6",'1'&x"9DC7",'1'&x"9DC8",'1'&x"9DC9",'1'&x"9DCA",'1'&x"9DCB",'1'&x"9DCC",'1'&x"9DCD",'1'&x"9DCE",'1'&x"9DCF",
+--'1'&x"9DD0",'1'&x"9DD1",'1'&x"9DD2",'1'&x"9DD3",'1'&x"9DD4",'1'&x"9DD5",'1'&x"9DD6",'1'&x"9DD7",'1'&x"9DD8",'1'&x"9DD9",'1'&x"9DDA",'1'&x"9DDB",'1'&x"9DDC",'1'&x"9DDD",'1'&x"9DDE",'1'&x"9DDF",
+--'1'&x"9DE0",'1'&x"9DE1",'1'&x"9DE2",'1'&x"9DE3",'1'&x"9DE4",'1'&x"9DE5",'1'&x"9DE6",'1'&x"9DE7",'1'&x"9DE8",'1'&x"9DE9",'1'&x"9DEA",'1'&x"9DEB",'1'&x"9DEC",'1'&x"9DED",'1'&x"9DEE",'1'&x"9DEF",
+--'1'&x"9DF0",'1'&x"9DF1",'1'&x"9DF2",'1'&x"9DF3",'1'&x"9DF4",'1'&x"9DF5",'1'&x"9DF6",'1'&x"9DF7",'1'&x"9DF8",'1'&x"9DF9",'1'&x"9DFA",'1'&x"9DFB",'1'&x"9DFC",'1'&x"9DFD",'1'&x"9DFE",'1'&x"9DFF",
+--'1'&x"9E00",'1'&x"9E01",'1'&x"9E02",'1'&x"9E03",'1'&x"9E04",'1'&x"9E05",'1'&x"9E06",'1'&x"9E07",'1'&x"9E08",'1'&x"9E09",'1'&x"9E0A",'1'&x"9E0B",'1'&x"9E0C",'1'&x"9E0D",'1'&x"9E0E",'1'&x"9E0F",
+--'1'&x"9E10",'1'&x"9E11",'1'&x"9E12",'1'&x"9E13",'1'&x"9E14",'1'&x"9E15",'1'&x"9E16",'1'&x"9E17",'1'&x"9E18",'1'&x"9E19",'1'&x"9E1A",'1'&x"9E1B",'1'&x"9E1C",'1'&x"9E1D",'1'&x"9E1E",'1'&x"9E1F",
+--'1'&x"9E20",'1'&x"9E21",'1'&x"9E22",'1'&x"9E23",'1'&x"9E24",'1'&x"9E25",'1'&x"9E26",'1'&x"9E27",'1'&x"9E28",'1'&x"9E29",'1'&x"9E2A",'1'&x"9E2B",'1'&x"9E2C",'1'&x"9E2D",'1'&x"9E2E",'1'&x"9E2F",
+--'1'&x"9E30",'1'&x"9E31",'1'&x"9E32",'1'&x"9E33",'1'&x"9E34",'1'&x"9E35",'1'&x"9E36",'1'&x"9E37",'1'&x"9E38",'1'&x"9E39",'1'&x"9E3A",'1'&x"9E3B",'1'&x"9E3C",'1'&x"9E3D",'1'&x"9E3E",'1'&x"9E3F",
+--'1'&x"9E40",'1'&x"9E41",'1'&x"9E42",'1'&x"9E43",'1'&x"9E44",'1'&x"9E45",'1'&x"9E46",'1'&x"9E47",'1'&x"9E48",'1'&x"9E49",'1'&x"9E4A",'1'&x"9E4B",'1'&x"9E4C",'1'&x"9E4D",'1'&x"9E4E",'1'&x"9E4F",
+--'1'&x"9E50",'1'&x"9E51",'1'&x"9E52",'1'&x"9E53",'1'&x"9E54",'1'&x"9E55",'1'&x"9E56",'1'&x"9E57",'1'&x"9E58",'1'&x"9E59",'1'&x"9E5A",'1'&x"9E5B",'1'&x"9E5C",'1'&x"9E5D",'1'&x"9E5E",'1'&x"9E5F",
+--'1'&x"9E60",'1'&x"9E61",'1'&x"9E62",'1'&x"9E63",'1'&x"9E64",'1'&x"9E65",'1'&x"9E66",'1'&x"9E67",'1'&x"9E68",'1'&x"9E69",'1'&x"9E6A",'1'&x"9E6B",'1'&x"9E6C",'1'&x"9E6D",'1'&x"9E6E",'1'&x"9E6F",
+--'1'&x"9E70",'1'&x"9E71",'1'&x"9E72",'1'&x"9E73",'1'&x"9E74",'1'&x"9E75",'1'&x"9E76",'1'&x"9E77",'1'&x"9E78",'1'&x"9E79",'1'&x"9E7A",'1'&x"9E7B",'1'&x"9E7C",'1'&x"9E7D",'1'&x"9E7E",'1'&x"9E7F",
+--'1'&x"9E80",'1'&x"9E81",'1'&x"9E82",'1'&x"9E83",'1'&x"9E84",'1'&x"9E85",'1'&x"9E86",'1'&x"9E87",'1'&x"9E88",'1'&x"9E89",'1'&x"9E8A",'1'&x"9E8B",'1'&x"9E8C",'1'&x"9E8D",'1'&x"9E8E",'1'&x"9E8F",
+--'1'&x"9E90",'1'&x"9E91",'1'&x"9E92",'1'&x"9E93",'1'&x"9E94",'1'&x"9E95",'1'&x"9E96",'1'&x"9E97",'1'&x"9E98",'1'&x"9E99",'1'&x"9E9A",'1'&x"9E9B",'1'&x"9E9C",'1'&x"9E9D",'1'&x"9E9E",'1'&x"9E9F",
+--'1'&x"9EA0",'1'&x"9EA1",'1'&x"9EA2",'1'&x"9EA3",'1'&x"9EA4",'1'&x"9EA5",'1'&x"9EA6",'1'&x"9EA7",'1'&x"9EA8",'1'&x"9EA9",'1'&x"9EAA",'1'&x"9EAB",'1'&x"9EAC",'1'&x"9EAD",'1'&x"9EAE",'1'&x"9EAF",
+--'1'&x"9EB0",'1'&x"9EB1",'1'&x"9EB2",'1'&x"9EB3",'1'&x"9EB4",'1'&x"9EB5",'1'&x"9EB6",'1'&x"9EB7",'1'&x"9EB8",'1'&x"9EB9",'1'&x"9EBA",'1'&x"9EBB",'1'&x"9EBC",'1'&x"9EBD",'1'&x"9EBE",'1'&x"9EBF",
+--'1'&x"9EC0",'1'&x"9EC1",'1'&x"9EC2",'1'&x"9EC3",'1'&x"9EC4",'1'&x"9EC5",'1'&x"9EC6",'1'&x"9EC7",'1'&x"9EC8",'1'&x"9EC9",'1'&x"9ECA",'1'&x"9ECB",'1'&x"9ECC",'1'&x"9ECD",'1'&x"9ECE",'1'&x"9ECF",
+--'1'&x"9ED0",'1'&x"9ED1",'1'&x"9ED2",'1'&x"9ED3",'1'&x"9ED4",'1'&x"9ED5",'1'&x"9ED6",'1'&x"9ED7",'1'&x"9ED8",'1'&x"9ED9",'1'&x"9EDA",'1'&x"9EDB",'1'&x"9EDC",'1'&x"9EDD",'1'&x"9EDE",'1'&x"9EDF",
+--'1'&x"9EE0",'1'&x"9EE1",'1'&x"9EE2",'1'&x"9EE3",'1'&x"9EE4",'1'&x"9EE5",'1'&x"9EE6",'1'&x"9EE7",'1'&x"9EE8",'1'&x"9EE9",'1'&x"9EEA",'1'&x"9EEB",'1'&x"9EEC",'1'&x"9EED",'1'&x"9EEE",'1'&x"9EEF",
+--'1'&x"9EF0",'1'&x"9EF1",'1'&x"9EF2",'1'&x"9EF3",'1'&x"9EF4",'1'&x"9EF5",'1'&x"9EF6",'1'&x"9EF7",'1'&x"9EF8",'1'&x"9EF9",'1'&x"9EFA",'1'&x"9EFB",'1'&x"9EFC",'1'&x"9EFD",'1'&x"9EFE",'1'&x"9EFF",
+--'1'&x"9F00",'1'&x"9F01",'1'&x"9F02",'1'&x"9F03",'1'&x"9F04",'1'&x"9F05",'1'&x"9F06",'1'&x"9F07",'1'&x"9F08",'1'&x"9F09",'1'&x"9F0A",'1'&x"9F0B",'1'&x"9F0C",'1'&x"9F0D",'1'&x"9F0E",'1'&x"9F0F",
+--'1'&x"9F10",'1'&x"9F11",'1'&x"9F12",'1'&x"9F13",'1'&x"9F14",'1'&x"9F15",'1'&x"9F16",'1'&x"9F17",'1'&x"9F18",'1'&x"9F19",'1'&x"9F1A",'1'&x"9F1B",'1'&x"9F1C",'1'&x"9F1D",'1'&x"9F1E",'1'&x"9F1F",
+--'1'&x"9F20",'1'&x"9F21",'1'&x"9F22",'1'&x"9F23",'1'&x"9F24",'1'&x"9F25",'1'&x"9F26",'1'&x"9F27",'1'&x"9F28",'1'&x"9F29",'1'&x"9F2A",'1'&x"9F2B",'1'&x"9F2C",'1'&x"9F2D",'1'&x"9F2E",'1'&x"9F2F",
+--'1'&x"9F30",'1'&x"9F31",'1'&x"9F32",'1'&x"9F33",'1'&x"9F34",'1'&x"9F35",'1'&x"9F36",'1'&x"9F37",'1'&x"9F38",'1'&x"9F39",'1'&x"9F3A",'1'&x"9F3B",'1'&x"9F3C",'1'&x"9F3D",'1'&x"9F3E",'1'&x"9F3F",
+--'1'&x"9F40",'1'&x"9F41",'1'&x"9F42",'1'&x"9F43",'1'&x"9F44",'1'&x"9F45",'1'&x"9F46",'1'&x"9F47",'1'&x"9F48",'1'&x"9F49",'1'&x"9F4A",'1'&x"9F4B",'1'&x"9F4C",'1'&x"9F4D",'1'&x"9F4E",'1'&x"9F4F",
+--'1'&x"9F50",'1'&x"9F51",'1'&x"9F52",'1'&x"9F53",'1'&x"9F54",'1'&x"9F55",'1'&x"9F56",'1'&x"9F57",'1'&x"9F58",'1'&x"9F59",'1'&x"9F5A",'1'&x"9F5B",'1'&x"9F5C",'1'&x"9F5D",'1'&x"9F5E",'1'&x"9F5F",
+--'1'&x"9F60",'1'&x"9F61",'1'&x"9F62",'1'&x"9F63",'1'&x"9F64",'1'&x"9F65",'1'&x"9F66",'1'&x"9F67",'1'&x"9F68",'1'&x"9F69",'1'&x"9F6A",'1'&x"9F6B",'1'&x"9F6C",'1'&x"9F6D",'1'&x"9F6E",'1'&x"9F6F",
+--'1'&x"9F70",'1'&x"9F71",'1'&x"9F72",'1'&x"9F73",'1'&x"9F74",'1'&x"9F75",'1'&x"9F76",'1'&x"9F77",'1'&x"9F78",'1'&x"9F79",'1'&x"9F7A",'1'&x"9F7B",'1'&x"9F7C",'1'&x"9F7D",'1'&x"9F7E",'1'&x"9F7F",
+--'1'&x"9F80",'1'&x"9F81",'1'&x"9F82",'1'&x"9F83",'1'&x"9F84",'1'&x"9F85",'1'&x"9F86",'1'&x"9F87",'1'&x"9F88",'1'&x"9F89",'1'&x"9F8A",'1'&x"9F8B",'1'&x"9F8C",'1'&x"9F8D",'1'&x"9F8E",'1'&x"9F8F",
+--'1'&x"9F90",'1'&x"9F91",'1'&x"9F92",'1'&x"9F93",'1'&x"9F94",'1'&x"9F95",'1'&x"9F96",'1'&x"9F97",'1'&x"9F98",'1'&x"9F99",'1'&x"9F9A",'1'&x"9F9B",'1'&x"9F9C",'1'&x"9F9D",'1'&x"9F9E",'1'&x"9F9F",
+--'1'&x"9FA0",'1'&x"9FA1",'1'&x"9FA2",'1'&x"9FA3",'1'&x"9FA4",'1'&x"9FA5",'1'&x"9FA6",'1'&x"9FA7",'1'&x"9FA8",'1'&x"9FA9",'1'&x"9FAA",'1'&x"9FAB",'1'&x"9FAC",'1'&x"9FAD",'1'&x"9FAE",'1'&x"9FAF",
+--'1'&x"9FB0",'1'&x"9FB1",'1'&x"9FB2",'1'&x"9FB3",'1'&x"9FB4",'1'&x"9FB5",'1'&x"9FB6",'1'&x"9FB7",'1'&x"9FB8",'1'&x"9FB9",'1'&x"9FBA",'1'&x"9FBB",'1'&x"9FBC",'1'&x"9FBD",'1'&x"9FBE",'1'&x"9FBF",
+--'1'&x"9FC0",'1'&x"9FC1",'1'&x"9FC2",'1'&x"9FC3",'1'&x"9FC4",'1'&x"9FC5",'1'&x"9FC6",'1'&x"9FC7",'1'&x"9FC8",'1'&x"9FC9",'1'&x"9FCA",'1'&x"9FCB",'1'&x"9FCC",'1'&x"9FCD",'1'&x"9FCE",'1'&x"9FCF",
+--'1'&x"9FD0",'1'&x"9FD1",'1'&x"9FD2",'1'&x"9FD3",'1'&x"9FD4",'1'&x"9FD5",'1'&x"9FD6",'1'&x"9FD7",'1'&x"9FD8",'1'&x"9FD9",'1'&x"9FDA",'1'&x"9FDB",'1'&x"9FDC",'1'&x"9FDD",'1'&x"9FDE",'1'&x"9FDF",
+--'1'&x"9FE0",'1'&x"9FE1",'1'&x"9FE2",'1'&x"9FE3",'1'&x"9FE4",'1'&x"9FE5",'1'&x"9FE6",'1'&x"9FE7",'1'&x"9FE8",'1'&x"9FE9",'1'&x"9FEA",'1'&x"9FEB",'1'&x"9FEC",'1'&x"9FED",'1'&x"9FEE",'1'&x"9FEF",
+--'1'&x"9FF0",'1'&x"9FF1",'1'&x"9FF2",'1'&x"9FF3",'1'&x"9FF4",'1'&x"9FF5",'1'&x"9FF6",'1'&x"9FF7",'1'&x"9FF8",'1'&x"9FF9",'1'&x"9FFA",'1'&x"9FFB",'1'&x"9FFC",'1'&x"9FFD",'1'&x"9FFE",'1'&x"9FFF",
+--'1'&x"A000",'1'&x"A001",'1'&x"A002",'1'&x"A003",'1'&x"A004",'1'&x"A005",'1'&x"A006",'1'&x"A007",'1'&x"A008",'1'&x"A009",'1'&x"A00A",'1'&x"A00B",'1'&x"A00C",'1'&x"A00D",'1'&x"A00E",'1'&x"A00F",
+--'1'&x"A010",'1'&x"A011",'1'&x"A012",'1'&x"A013",'1'&x"A014",'1'&x"A015",'1'&x"A016",'1'&x"A017",'1'&x"A018",'1'&x"A019",'1'&x"A01A",'1'&x"A01B",'1'&x"A01C",'1'&x"A01D",'1'&x"A01E",'1'&x"A01F",
+--'1'&x"A020",'1'&x"A021",'1'&x"A022",'1'&x"A023",'1'&x"A024",'1'&x"A025",'1'&x"A026",'1'&x"A027",'1'&x"A028",'1'&x"A029",'1'&x"A02A",'1'&x"A02B",'1'&x"A02C",'1'&x"A02D",'1'&x"A02E",'1'&x"A02F",
+--'1'&x"A030",'1'&x"A031",'1'&x"A032",'1'&x"A033",'1'&x"A034",'1'&x"A035",'1'&x"A036",'1'&x"A037",'1'&x"A038",'1'&x"A039",'1'&x"A03A",'1'&x"A03B",'1'&x"A03C",'1'&x"A03D",'1'&x"A03E",'1'&x"A03F",
+--'1'&x"A040",'1'&x"A041",'1'&x"A042",'1'&x"A043",'1'&x"A044",'1'&x"A045",'1'&x"A046",'1'&x"A047",'1'&x"A048",'1'&x"A049",'1'&x"A04A",'1'&x"A04B",'1'&x"A04C",'1'&x"A04D",'1'&x"A04E",'1'&x"A04F",
+--'1'&x"A050",'1'&x"A051",'1'&x"A052",'1'&x"A053",'1'&x"A054",'1'&x"A055",'1'&x"A056",'1'&x"A057",'1'&x"A058",'1'&x"A059",'1'&x"A05A",'1'&x"A05B",'1'&x"A05C",'1'&x"A05D",'1'&x"A05E",'1'&x"A05F",
+--'1'&x"A060",'1'&x"A061",'1'&x"A062",'1'&x"A063",'1'&x"A064",'1'&x"A065",'1'&x"A066",'1'&x"A067",'1'&x"A068",'1'&x"A069",'1'&x"A06A",'1'&x"A06B",'1'&x"A06C",'1'&x"A06D",'1'&x"A06E",'1'&x"A06F",
+--'1'&x"A070",'1'&x"A071",'1'&x"A072",'1'&x"A073",'1'&x"A074",'1'&x"A075",'1'&x"A076",'1'&x"A077",'1'&x"A078",'1'&x"A079",'1'&x"A07A",'1'&x"A07B",'1'&x"A07C",'1'&x"A07D",'1'&x"A07E",'1'&x"A07F",
+--'1'&x"A080",'1'&x"A081",'1'&x"A082",'1'&x"A083",'1'&x"A084",'1'&x"A085",'1'&x"A086",'1'&x"A087",'1'&x"A088",'1'&x"A089",'1'&x"A08A",'1'&x"A08B",'1'&x"A08C",'1'&x"A08D",'1'&x"A08E",'1'&x"A08F",
+--'1'&x"A090",'1'&x"A091",'1'&x"A092",'1'&x"A093",'1'&x"A094",'1'&x"A095",'1'&x"A096",'1'&x"A097",'1'&x"A098",'1'&x"A099",'1'&x"A09A",'1'&x"A09B",'1'&x"A09C",'1'&x"A09D",'1'&x"A09E",'1'&x"A09F",
+--'1'&x"A0A0",'1'&x"A0A1",'1'&x"A0A2",'1'&x"A0A3",'1'&x"A0A4",'1'&x"A0A5",'1'&x"A0A6",'1'&x"A0A7",'1'&x"A0A8",'1'&x"A0A9",'1'&x"A0AA",'1'&x"A0AB",'1'&x"A0AC",'1'&x"A0AD",'1'&x"A0AE",'1'&x"A0AF",
+--'1'&x"A0B0",'1'&x"A0B1",'1'&x"A0B2",'1'&x"A0B3",'1'&x"A0B4",'1'&x"A0B5",'1'&x"A0B6",'1'&x"A0B7",'1'&x"A0B8",'1'&x"A0B9",'1'&x"A0BA",'1'&x"A0BB",'1'&x"A0BC",'1'&x"A0BD",'1'&x"A0BE",'1'&x"A0BF",
+--'1'&x"A0C0",'1'&x"A0C1",'1'&x"A0C2",'1'&x"A0C3",'1'&x"A0C4",'1'&x"A0C5",'1'&x"A0C6",'1'&x"A0C7",'1'&x"A0C8",'1'&x"A0C9",'1'&x"A0CA",'1'&x"A0CB",'1'&x"A0CC",'1'&x"A0CD",'1'&x"A0CE",'1'&x"A0CF",
+--'1'&x"A0D0",'1'&x"A0D1",'1'&x"A0D2",'1'&x"A0D3",'1'&x"A0D4",'1'&x"A0D5",'1'&x"A0D6",'1'&x"A0D7",'1'&x"A0D8",'1'&x"A0D9",'1'&x"A0DA",'1'&x"A0DB",'1'&x"A0DC",'1'&x"A0DD",'1'&x"A0DE",'1'&x"A0DF",
+--'1'&x"A0E0",'1'&x"A0E1",'1'&x"A0E2",'1'&x"A0E3",'1'&x"A0E4",'1'&x"A0E5",'1'&x"A0E6",'1'&x"A0E7",'1'&x"A0E8",'1'&x"A0E9",'1'&x"A0EA",'1'&x"A0EB",'1'&x"A0EC",'1'&x"A0ED",'1'&x"A0EE",'1'&x"A0EF",
+--'1'&x"A0F0",'1'&x"A0F1",'1'&x"A0F2",'1'&x"A0F3",'1'&x"A0F4",'1'&x"A0F5",'1'&x"A0F6",'1'&x"A0F7",'1'&x"A0F8",'1'&x"A0F9",'1'&x"A0FA",'1'&x"A0FB",'1'&x"A0FC",'1'&x"A0FD",'1'&x"A0FE",'1'&x"A0FF",
+--'1'&x"A100",'1'&x"A101",'1'&x"A102",'1'&x"A103",'1'&x"A104",'1'&x"A105",'1'&x"A106",'1'&x"A107",'1'&x"A108",'1'&x"A109",'1'&x"A10A",'1'&x"A10B",'1'&x"A10C",'1'&x"A10D",'1'&x"A10E",'1'&x"A10F",
+--'1'&x"A110",'1'&x"A111",'1'&x"A112",'1'&x"A113",'1'&x"A114",'1'&x"A115",'1'&x"A116",'1'&x"A117",'1'&x"A118",'1'&x"A119",'1'&x"A11A",'1'&x"A11B",'1'&x"A11C",'1'&x"A11D",'1'&x"A11E",'1'&x"A11F",
+--'1'&x"A120",'1'&x"A121",'1'&x"A122",'1'&x"A123",'1'&x"A124",'1'&x"A125",'1'&x"A126",'1'&x"A127",'1'&x"A128",'1'&x"A129",'1'&x"A12A",'1'&x"A12B",'1'&x"A12C",'1'&x"A12D",'1'&x"A12E",'1'&x"A12F",
+--'1'&x"A130",'1'&x"A131",'1'&x"A132",'1'&x"A133",'1'&x"A134",'1'&x"A135",'1'&x"A136",'1'&x"A137",'1'&x"A138",'1'&x"A139",'1'&x"A13A",'1'&x"A13B",'1'&x"A13C",'1'&x"A13D",'1'&x"A13E",'1'&x"A13F",
+--'1'&x"A140",'1'&x"A141",'1'&x"A142",'1'&x"A143",'1'&x"A144",'1'&x"A145",'1'&x"A146",'1'&x"A147",'1'&x"A148",'1'&x"A149",'1'&x"A14A",'1'&x"A14B",'1'&x"A14C",'1'&x"A14D",'1'&x"A14E",'1'&x"A14F",
+--'1'&x"A150",'1'&x"A151",'1'&x"A152",'1'&x"A153",'1'&x"A154",'1'&x"A155",'1'&x"A156",'1'&x"A157",'1'&x"A158",'1'&x"A159",'1'&x"A15A",'1'&x"A15B",'1'&x"A15C",'1'&x"A15D",'1'&x"A15E",'1'&x"A15F",
+--'1'&x"A160",'1'&x"A161",'1'&x"A162",'1'&x"A163",'1'&x"A164",'1'&x"A165",'1'&x"A166",'1'&x"A167",'1'&x"A168",'1'&x"A169",'1'&x"A16A",'1'&x"A16B",'1'&x"A16C",'1'&x"A16D",'1'&x"A16E",'1'&x"A16F",
+--'1'&x"A170",'1'&x"A171",'1'&x"A172",'1'&x"A173",'1'&x"A174",'1'&x"A175",'1'&x"A176",'1'&x"A177",'1'&x"A178",'1'&x"A179",'1'&x"A17A",'1'&x"A17B",'1'&x"A17C",'1'&x"A17D",'1'&x"A17E",'1'&x"A17F",
+--'1'&x"A180",'1'&x"A181",'1'&x"A182",'1'&x"A183",'1'&x"A184",'1'&x"A185",'1'&x"A186",'1'&x"A187",'1'&x"A188",'1'&x"A189",'1'&x"A18A",'1'&x"A18B",'1'&x"A18C",'1'&x"A18D",'1'&x"A18E",'1'&x"A18F",
+--'1'&x"A190",'1'&x"A191",'1'&x"A192",'1'&x"A193",'1'&x"A194",'1'&x"A195",'1'&x"A196",'1'&x"A197",'1'&x"A198",'1'&x"A199",'1'&x"A19A",'1'&x"A19B",'1'&x"A19C",'1'&x"A19D",'1'&x"A19E",'1'&x"A19F",
+--'1'&x"A1A0",'1'&x"A1A1",'1'&x"A1A2",'1'&x"A1A3",'1'&x"A1A4",'1'&x"A1A5",'1'&x"A1A6",'1'&x"A1A7",'1'&x"A1A8",'1'&x"A1A9",'1'&x"A1AA",'1'&x"A1AB",'1'&x"A1AC",'1'&x"A1AD",'1'&x"A1AE",'1'&x"A1AF",
+--'1'&x"A1B0",'1'&x"A1B1",'1'&x"A1B2",'1'&x"A1B3",'1'&x"A1B4",'1'&x"A1B5",'1'&x"A1B6",'1'&x"A1B7",'1'&x"A1B8",'1'&x"A1B9",'1'&x"A1BA",'1'&x"A1BB",'1'&x"A1BC",'1'&x"A1BD",'1'&x"A1BE",'1'&x"A1BF",
+--'1'&x"A1C0",'1'&x"A1C1",'1'&x"A1C2",'1'&x"A1C3",'1'&x"A1C4",'1'&x"A1C5",'1'&x"A1C6",'1'&x"A1C7",'1'&x"A1C8",'1'&x"A1C9",'1'&x"A1CA",'1'&x"A1CB",'1'&x"A1CC",'1'&x"A1CD",'1'&x"A1CE",'1'&x"A1CF",
+--'1'&x"A1D0",'1'&x"A1D1",'1'&x"A1D2",'1'&x"A1D3",'1'&x"A1D4",'1'&x"A1D5",'1'&x"A1D6",'1'&x"A1D7",'1'&x"A1D8",'1'&x"A1D9",'1'&x"A1DA",'1'&x"A1DB",'1'&x"A1DC",'1'&x"A1DD",'1'&x"A1DE",'1'&x"A1DF",
+--'1'&x"A1E0",'1'&x"A1E1",'1'&x"A1E2",'1'&x"A1E3",'1'&x"A1E4",'1'&x"A1E5",'1'&x"A1E6",'1'&x"A1E7",'1'&x"A1E8",'1'&x"A1E9",'1'&x"A1EA",'1'&x"A1EB",'1'&x"A1EC",'1'&x"A1ED",'1'&x"A1EE",'1'&x"A1EF",
+--'1'&x"A1F0",'1'&x"A1F1",'1'&x"A1F2",'1'&x"A1F3",'1'&x"A1F4",'1'&x"A1F5",'1'&x"A1F6",'1'&x"A1F7",'1'&x"A1F8",'1'&x"A1F9",'1'&x"A1FA",'1'&x"A1FB",'1'&x"A1FC",'1'&x"A1FD",'1'&x"A1FE",'1'&x"A1FF",
+--'1'&x"A200",'1'&x"A201",'1'&x"A202",'1'&x"A203",'1'&x"A204",'1'&x"A205",'1'&x"A206",'1'&x"A207",'1'&x"A208",'1'&x"A209",'1'&x"A20A",'1'&x"A20B",'1'&x"A20C",'1'&x"A20D",'1'&x"A20E",'1'&x"A20F",
+--'1'&x"A210",'1'&x"A211",'1'&x"A212",'1'&x"A213",'1'&x"A214",'1'&x"A215",'1'&x"A216",'1'&x"A217",'1'&x"A218",'1'&x"A219",'1'&x"A21A",'1'&x"A21B",'1'&x"A21C",'1'&x"A21D",'1'&x"A21E",'1'&x"A21F",
+--'1'&x"A220",'1'&x"A221",'1'&x"A222",'1'&x"A223",'1'&x"A224",'1'&x"A225",'1'&x"A226",'1'&x"A227",'1'&x"A228",'1'&x"A229",'1'&x"A22A",'1'&x"A22B",'1'&x"A22C",'1'&x"A22D",'1'&x"A22E",'1'&x"A22F",
+--'1'&x"A230",'1'&x"A231",'1'&x"A232",'1'&x"A233",'1'&x"A234",'1'&x"A235",'1'&x"A236",'1'&x"A237",'1'&x"A238",'1'&x"A239",'1'&x"A23A",'1'&x"A23B",'1'&x"A23C",'1'&x"A23D",'1'&x"A23E",'1'&x"A23F",
+--'1'&x"A240",'1'&x"A241",'1'&x"A242",'1'&x"A243",'1'&x"A244",'1'&x"A245",'1'&x"A246",'1'&x"A247",'1'&x"A248",'1'&x"A249",'1'&x"A24A",'1'&x"A24B",'1'&x"A24C",'1'&x"A24D",'1'&x"A24E",'1'&x"A24F",
+--'1'&x"A250",'1'&x"A251",'1'&x"A252",'1'&x"A253",'1'&x"A254",'1'&x"A255",'1'&x"A256",'1'&x"A257",'1'&x"A258",'1'&x"A259",'1'&x"A25A",'1'&x"A25B",'1'&x"A25C",'1'&x"A25D",'1'&x"A25E",'1'&x"A25F",
+--'1'&x"A260",'1'&x"A261",'1'&x"A262",'1'&x"A263",'1'&x"A264",'1'&x"A265",'1'&x"A266",'1'&x"A267",'1'&x"A268",'1'&x"A269",'1'&x"A26A",'1'&x"A26B",'1'&x"A26C",'1'&x"A26D",'1'&x"A26E",'1'&x"A26F",
+--'1'&x"A270",'1'&x"A271",'1'&x"A272",'1'&x"A273",'1'&x"A274",'1'&x"A275",'1'&x"A276",'1'&x"A277",'1'&x"A278",'1'&x"A279",'1'&x"A27A",'1'&x"A27B",'1'&x"A27C",'1'&x"A27D",'1'&x"A27E",'1'&x"A27F",
+--'1'&x"A280",'1'&x"A281",'1'&x"A282",'1'&x"A283",'1'&x"A284",'1'&x"A285",'1'&x"A286",'1'&x"A287",'1'&x"A288",'1'&x"A289",'1'&x"A28A",'1'&x"A28B",'1'&x"A28C",'1'&x"A28D",'1'&x"A28E",'1'&x"A28F",
+--'1'&x"A290",'1'&x"A291",'1'&x"A292",'1'&x"A293",'1'&x"A294",'1'&x"A295",'1'&x"A296",'1'&x"A297",'1'&x"A298",'1'&x"A299",'1'&x"A29A",'1'&x"A29B",'1'&x"A29C",'1'&x"A29D",'1'&x"A29E",'1'&x"A29F",
+--'1'&x"A2A0",'1'&x"A2A1",'1'&x"A2A2",'1'&x"A2A3",'1'&x"A2A4",'1'&x"A2A5",'1'&x"A2A6",'1'&x"A2A7",'1'&x"A2A8",'1'&x"A2A9",'1'&x"A2AA",'1'&x"A2AB",'1'&x"A2AC",'1'&x"A2AD",'1'&x"A2AE",'1'&x"A2AF",
+--'1'&x"A2B0",'1'&x"A2B1",'1'&x"A2B2",'1'&x"A2B3",'1'&x"A2B4",'1'&x"A2B5",'1'&x"A2B6",'1'&x"A2B7",'1'&x"A2B8",'1'&x"A2B9",'1'&x"A2BA",'1'&x"A2BB",'1'&x"A2BC",'1'&x"A2BD",'1'&x"A2BE",'1'&x"A2BF",
+--'1'&x"A2C0",'1'&x"A2C1",'1'&x"A2C2",'1'&x"A2C3",'1'&x"A2C4",'1'&x"A2C5",'1'&x"A2C6",'1'&x"A2C7",'1'&x"A2C8",'1'&x"A2C9",'1'&x"A2CA",'1'&x"A2CB",'1'&x"A2CC",'1'&x"A2CD",'1'&x"A2CE",'1'&x"A2CF",
+--'1'&x"A2D0",'1'&x"A2D1",'1'&x"A2D2",'1'&x"A2D3",'1'&x"A2D4",'1'&x"A2D5",'1'&x"A2D6",'1'&x"A2D7",'1'&x"A2D8",'1'&x"A2D9",'1'&x"A2DA",'1'&x"A2DB",'1'&x"A2DC",'1'&x"A2DD",'1'&x"A2DE",'1'&x"A2DF",
+--'1'&x"A2E0",'1'&x"A2E1",'1'&x"A2E2",'1'&x"A2E3",'1'&x"A2E4",'1'&x"A2E5",'1'&x"A2E6",'1'&x"A2E7",'1'&x"A2E8",'1'&x"A2E9",'1'&x"A2EA",'1'&x"A2EB",'1'&x"A2EC",'1'&x"A2ED",'1'&x"A2EE",'1'&x"A2EF",
+--'1'&x"A2F0",'1'&x"A2F1",'1'&x"A2F2",'1'&x"A2F3",'1'&x"A2F4",'1'&x"A2F5",'1'&x"A2F6",'1'&x"A2F7",'1'&x"A2F8",'1'&x"A2F9",'1'&x"A2FA",'1'&x"A2FB",'1'&x"A2FC",'1'&x"A2FD",'1'&x"A2FE",'1'&x"A2FF",
+--'1'&x"A300",'1'&x"A301",'1'&x"A302",'1'&x"A303",'1'&x"A304",'1'&x"A305",'1'&x"A306",'1'&x"A307",'1'&x"A308",'1'&x"A309",'1'&x"A30A",'1'&x"A30B",'1'&x"A30C",'1'&x"A30D",'1'&x"A30E",'1'&x"A30F",
+--'1'&x"A310",'1'&x"A311",'1'&x"A312",'1'&x"A313",'1'&x"A314",'1'&x"A315",'1'&x"A316",'1'&x"A317",'1'&x"A318",'1'&x"A319",'1'&x"A31A",'1'&x"A31B",'1'&x"A31C",'1'&x"A31D",'1'&x"A31E",'1'&x"A31F",
+--'1'&x"A320",'1'&x"A321",'1'&x"A322",'1'&x"A323",'1'&x"A324",'1'&x"A325",'1'&x"A326",'1'&x"A327",'1'&x"A328",'1'&x"A329",'1'&x"A32A",'1'&x"A32B",'1'&x"A32C",'1'&x"A32D",'1'&x"A32E",'1'&x"A32F",
+--'1'&x"A330",'1'&x"A331",'1'&x"A332",'1'&x"A333",'1'&x"A334",'1'&x"A335",'1'&x"A336",'1'&x"A337",'1'&x"A338",'1'&x"A339",'1'&x"A33A",'1'&x"A33B",'1'&x"A33C",'1'&x"A33D",'1'&x"A33E",'1'&x"A33F",
+--'1'&x"A340",'1'&x"A341",'1'&x"A342",'1'&x"A343",'1'&x"A344",'1'&x"A345",'1'&x"A346",'1'&x"A347",'1'&x"A348",'1'&x"A349",'1'&x"A34A",'1'&x"A34B",'1'&x"A34C",'1'&x"A34D",'1'&x"A34E",'1'&x"A34F",
+--'1'&x"A350",'1'&x"A351",'1'&x"A352",'1'&x"A353",'1'&x"A354",'1'&x"A355",'1'&x"A356",'1'&x"A357",'1'&x"A358",'1'&x"A359",'1'&x"A35A",'1'&x"A35B",'1'&x"A35C",'1'&x"A35D",'1'&x"A35E",'1'&x"A35F",
+--'1'&x"A360",'1'&x"A361",'1'&x"A362",'1'&x"A363",'1'&x"A364",'1'&x"A365",'1'&x"A366",'1'&x"A367",'1'&x"A368",'1'&x"A369",'1'&x"A36A",'1'&x"A36B",'1'&x"A36C",'1'&x"A36D",'1'&x"A36E",'1'&x"A36F",
+--'1'&x"A370",'1'&x"A371",'1'&x"A372",'1'&x"A373",'1'&x"A374",'1'&x"A375",'1'&x"A376",'1'&x"A377",'1'&x"A378",'1'&x"A379",'1'&x"A37A",'1'&x"A37B",'1'&x"A37C",'1'&x"A37D",'1'&x"A37E",'1'&x"A37F",
+--'1'&x"A380",'1'&x"A381",'1'&x"A382",'1'&x"A383",'1'&x"A384",'1'&x"A385",'1'&x"A386",'1'&x"A387",'1'&x"A388",'1'&x"A389",'1'&x"A38A",'1'&x"A38B",'1'&x"A38C",'1'&x"A38D",'1'&x"A38E",'1'&x"A38F",
+--'1'&x"A390",'1'&x"A391",'1'&x"A392",'1'&x"A393",'1'&x"A394",'1'&x"A395",'1'&x"A396",'1'&x"A397",'1'&x"A398",'1'&x"A399",'1'&x"A39A",'1'&x"A39B",'1'&x"A39C",'1'&x"A39D",'1'&x"A39E",'1'&x"A39F",
+--'1'&x"A3A0",'1'&x"A3A1",'1'&x"A3A2",'1'&x"A3A3",'1'&x"A3A4",'1'&x"A3A5",'1'&x"A3A6",'1'&x"A3A7",'1'&x"A3A8",'1'&x"A3A9",'1'&x"A3AA",'1'&x"A3AB",'1'&x"A3AC",'1'&x"A3AD",'1'&x"A3AE",'1'&x"A3AF",
+--'1'&x"A3B0",'1'&x"A3B1",'1'&x"A3B2",'1'&x"A3B3",'1'&x"A3B4",'1'&x"A3B5",'1'&x"A3B6",'1'&x"A3B7",'1'&x"A3B8",'1'&x"A3B9",'1'&x"A3BA",'1'&x"A3BB",'1'&x"A3BC",'1'&x"A3BD",'1'&x"A3BE",'1'&x"A3BF",
+--'1'&x"A3C0",'1'&x"A3C1",'1'&x"A3C2",'1'&x"A3C3",'1'&x"A3C4",'1'&x"A3C5",'1'&x"A3C6",'1'&x"A3C7",'1'&x"A3C8",'1'&x"A3C9",'1'&x"A3CA",'1'&x"A3CB",'1'&x"A3CC",'1'&x"A3CD",'1'&x"A3CE",'1'&x"A3CF",
+--'1'&x"A3D0",'1'&x"A3D1",'1'&x"A3D2",'1'&x"A3D3",'1'&x"A3D4",'1'&x"A3D5",'1'&x"A3D6",'1'&x"A3D7",'1'&x"A3D8",'1'&x"A3D9",'1'&x"A3DA",'1'&x"A3DB",'1'&x"A3DC",'1'&x"A3DD",'1'&x"A3DE",'1'&x"A3DF",
+--'1'&x"A3E0",'1'&x"A3E1",'1'&x"A3E2",'1'&x"A3E3",'1'&x"A3E4",'1'&x"A3E5",'1'&x"A3E6",'1'&x"A3E7",'1'&x"A3E8",'1'&x"A3E9",'1'&x"A3EA",'1'&x"A3EB",'1'&x"A3EC",'1'&x"A3ED",'1'&x"A3EE",'1'&x"A3EF",
+--'1'&x"A3F0",'1'&x"A3F1",'1'&x"A3F2",'1'&x"A3F3",'1'&x"A3F4",'1'&x"A3F5",'1'&x"A3F6",'1'&x"A3F7",'1'&x"A3F8",'1'&x"A3F9",'1'&x"A3FA",'1'&x"A3FB",'1'&x"A3FC",'1'&x"A3FD",'1'&x"A3FE",'1'&x"A3FF",
+--'1'&x"A400",'1'&x"A401",'1'&x"A402",'1'&x"A403",'1'&x"A404",'1'&x"A405",'1'&x"A406",'1'&x"A407",'1'&x"A408",'1'&x"A409",'1'&x"A40A",'1'&x"A40B",'1'&x"A40C",'1'&x"A40D",'1'&x"A40E",'1'&x"A40F",
+--'1'&x"A410",'1'&x"A411",'1'&x"A412",'1'&x"A413",'1'&x"A414",'1'&x"A415",'1'&x"A416",'1'&x"A417",'1'&x"A418",'1'&x"A419",'1'&x"A41A",'1'&x"A41B",'1'&x"A41C",'1'&x"A41D",'1'&x"A41E",'1'&x"A41F",
+--'1'&x"A420",'1'&x"A421",'1'&x"A422",'1'&x"A423",'1'&x"A424",'1'&x"A425",'1'&x"A426",'1'&x"A427",'1'&x"A428",'1'&x"A429",'1'&x"A42A",'1'&x"A42B",'1'&x"A42C",'1'&x"A42D",'1'&x"A42E",'1'&x"A42F",
+--'1'&x"A430",'1'&x"A431",'1'&x"A432",'1'&x"A433",'1'&x"A434",'1'&x"A435",'1'&x"A436",'1'&x"A437",'1'&x"A438",'1'&x"A439",'1'&x"A43A",'1'&x"A43B",'1'&x"A43C",'1'&x"A43D",'1'&x"A43E",'1'&x"A43F",
+--'1'&x"A440",'1'&x"A441",'1'&x"A442",'1'&x"A443",'1'&x"A444",'1'&x"A445",'1'&x"A446",'1'&x"A447",'1'&x"A448",'1'&x"A449",'1'&x"A44A",'1'&x"A44B",'1'&x"A44C",'1'&x"A44D",'1'&x"A44E",'1'&x"A44F",
+--'1'&x"A450",'1'&x"A451",'1'&x"A452",'1'&x"A453",'1'&x"A454",'1'&x"A455",'1'&x"A456",'1'&x"A457",'1'&x"A458",'1'&x"A459",'1'&x"A45A",'1'&x"A45B",'1'&x"A45C",'1'&x"A45D",'1'&x"A45E",'1'&x"A45F",
+--'1'&x"A460",'1'&x"A461",'1'&x"A462",'1'&x"A463",'1'&x"A464",'1'&x"A465",'1'&x"A466",'1'&x"A467",'1'&x"A468",'1'&x"A469",'1'&x"A46A",'1'&x"A46B",'1'&x"A46C",'1'&x"A46D",'1'&x"A46E",'1'&x"A46F",
+--'1'&x"A470",'1'&x"A471",'1'&x"A472",'1'&x"A473",'1'&x"A474",'1'&x"A475",'1'&x"A476",'1'&x"A477",'1'&x"A478",'1'&x"A479",'1'&x"A47A",'1'&x"A47B",'1'&x"A47C",'1'&x"A47D",'1'&x"A47E",'1'&x"A47F",
+--'1'&x"A480",'1'&x"A481",'1'&x"A482",'1'&x"A483",'1'&x"A484",'1'&x"A485",'1'&x"A486",'1'&x"A487",'1'&x"A488",'1'&x"A489",'1'&x"A48A",'1'&x"A48B",'1'&x"A48C",'1'&x"A48D",'1'&x"A48E",'1'&x"A48F",
+--'1'&x"A490",'1'&x"A491",'1'&x"A492",'1'&x"A493",'1'&x"A494",'1'&x"A495",'1'&x"A496",'1'&x"A497",'1'&x"A498",'1'&x"A499",'1'&x"A49A",'1'&x"A49B",'1'&x"A49C",'1'&x"A49D",'1'&x"A49E",'1'&x"A49F",
+--'1'&x"A4A0",'1'&x"A4A1",'1'&x"A4A2",'1'&x"A4A3",'1'&x"A4A4",'1'&x"A4A5",'1'&x"A4A6",'1'&x"A4A7",'1'&x"A4A8",'1'&x"A4A9",'1'&x"A4AA",'1'&x"A4AB",'1'&x"A4AC",'1'&x"A4AD",'1'&x"A4AE",'1'&x"A4AF",
+--'1'&x"A4B0",'1'&x"A4B1",'1'&x"A4B2",'1'&x"A4B3",'1'&x"A4B4",'1'&x"A4B5",'1'&x"A4B6",'1'&x"A4B7",'1'&x"A4B8",'1'&x"A4B9",'1'&x"A4BA",'1'&x"A4BB",'1'&x"A4BC",'1'&x"A4BD",'1'&x"A4BE",'1'&x"A4BF",
+--'1'&x"A4C0",'1'&x"A4C1",'1'&x"A4C2",'1'&x"A4C3",'1'&x"A4C4",'1'&x"A4C5",'1'&x"A4C6",'1'&x"A4C7",'1'&x"A4C8",'1'&x"A4C9",'1'&x"A4CA",'1'&x"A4CB",'1'&x"A4CC",'1'&x"A4CD",'1'&x"A4CE",'1'&x"A4CF",
+--'1'&x"A4D0",'1'&x"A4D1",'1'&x"A4D2",'1'&x"A4D3",'1'&x"A4D4",'1'&x"A4D5",'1'&x"A4D6",'1'&x"A4D7",'1'&x"A4D8",'1'&x"A4D9",'1'&x"A4DA",'1'&x"A4DB",'1'&x"A4DC",'1'&x"A4DD",'1'&x"A4DE",'1'&x"A4DF",
+--'1'&x"A4E0",'1'&x"A4E1",'1'&x"A4E2",'1'&x"A4E3",'1'&x"A4E4",'1'&x"A4E5",'1'&x"A4E6",'1'&x"A4E7",'1'&x"A4E8",'1'&x"A4E9",'1'&x"A4EA",'1'&x"A4EB",'1'&x"A4EC",'1'&x"A4ED",'1'&x"A4EE",'1'&x"A4EF",
+--'1'&x"A4F0",'1'&x"A4F1",'1'&x"A4F2",'1'&x"A4F3",'1'&x"A4F4",'1'&x"A4F5",'1'&x"A4F6",'1'&x"A4F7",'1'&x"A4F8",'1'&x"A4F9",'1'&x"A4FA",'1'&x"A4FB",'1'&x"A4FC",'1'&x"A4FD",'1'&x"A4FE",'1'&x"A4FF",
+--'1'&x"A500",'1'&x"A501",'1'&x"A502",'1'&x"A503",'1'&x"A504",'1'&x"A505",'1'&x"A506",'1'&x"A507",'1'&x"A508",'1'&x"A509",'1'&x"A50A",'1'&x"A50B",'1'&x"A50C",'1'&x"A50D",'1'&x"A50E",'1'&x"A50F",
+--'1'&x"A510",'1'&x"A511",'1'&x"A512",'1'&x"A513",'1'&x"A514",'1'&x"A515",'1'&x"A516",'1'&x"A517",'1'&x"A518",'1'&x"A519",'1'&x"A51A",'1'&x"A51B",'1'&x"A51C",'1'&x"A51D",'1'&x"A51E",'1'&x"A51F",
+--'1'&x"A520",'1'&x"A521",'1'&x"A522",'1'&x"A523",'1'&x"A524",'1'&x"A525",'1'&x"A526",'1'&x"A527",'1'&x"A528",'1'&x"A529",'1'&x"A52A",'1'&x"A52B",'1'&x"A52C",'1'&x"A52D",'1'&x"A52E",'1'&x"A52F",
+--'1'&x"A530",'1'&x"A531",'1'&x"A532",'1'&x"A533",'1'&x"A534",'1'&x"A535",'1'&x"A536",'1'&x"A537",'1'&x"A538",'1'&x"A539",'1'&x"A53A",'1'&x"A53B",'1'&x"A53C",'1'&x"A53D",'1'&x"A53E",'1'&x"A53F",
+--'1'&x"A540",'1'&x"A541",'1'&x"A542",'1'&x"A543",'1'&x"A544",'1'&x"A545",'1'&x"A546",'1'&x"A547",'1'&x"A548",'1'&x"A549",'1'&x"A54A",'1'&x"A54B",'1'&x"A54C",'1'&x"A54D",'1'&x"A54E",'1'&x"A54F",
+--'1'&x"A550",'1'&x"A551",'1'&x"A552",'1'&x"A553",'1'&x"A554",'1'&x"A555",'1'&x"A556",'1'&x"A557",'1'&x"A558",'1'&x"A559",'1'&x"A55A",'1'&x"A55B",'1'&x"A55C",'1'&x"A55D",'1'&x"A55E",'1'&x"A55F",
+--'1'&x"A560",'1'&x"A561",'1'&x"A562",'1'&x"A563",'1'&x"A564",'1'&x"A565",'1'&x"A566",'1'&x"A567",'1'&x"A568",'1'&x"A569",'1'&x"A56A",'1'&x"A56B",'1'&x"A56C",'1'&x"A56D",'1'&x"A56E",'1'&x"A56F",
+--'1'&x"A570",'1'&x"A571",'1'&x"A572",'1'&x"A573",'1'&x"A574",'1'&x"A575",'1'&x"A576",'1'&x"A577",'1'&x"A578",'1'&x"A579",'1'&x"A57A",'1'&x"A57B",'1'&x"A57C",'1'&x"A57D",'1'&x"A57E",'1'&x"A57F",
+--'1'&x"A580",'1'&x"A581",'1'&x"A582",'1'&x"A583",'1'&x"A584",'1'&x"A585",'1'&x"A586",'1'&x"A587",'1'&x"A588",'1'&x"A589",'1'&x"A58A",'1'&x"A58B",'1'&x"A58C",'1'&x"A58D",'1'&x"A58E",'1'&x"A58F",
+--'1'&x"A590",'1'&x"A591",'1'&x"A592",'1'&x"A593",'1'&x"A594",'1'&x"A595",'1'&x"A596",'1'&x"A597",'1'&x"A598",'1'&x"A599",'1'&x"A59A",'1'&x"A59B",'1'&x"A59C",'1'&x"A59D",'1'&x"A59E",'1'&x"A59F",
+--'1'&x"A5A0",'1'&x"A5A1",'1'&x"A5A2",'1'&x"A5A3",'1'&x"A5A4",'1'&x"A5A5",'1'&x"A5A6",'1'&x"A5A7",'1'&x"A5A8",'1'&x"A5A9",'1'&x"A5AA",'1'&x"A5AB",'1'&x"A5AC",'1'&x"A5AD",'1'&x"A5AE",'1'&x"A5AF",
+--'1'&x"A5B0",'1'&x"A5B1",'1'&x"A5B2",'1'&x"A5B3",'1'&x"A5B4",'1'&x"A5B5",'1'&x"A5B6",'1'&x"A5B7",'1'&x"A5B8",'1'&x"A5B9",'1'&x"A5BA",'1'&x"A5BB",'1'&x"A5BC",'1'&x"A5BD",'1'&x"A5BE",'1'&x"A5BF",
+--'1'&x"A5C0",'1'&x"A5C1",'1'&x"A5C2",'1'&x"A5C3",'1'&x"A5C4",'1'&x"A5C5",'1'&x"A5C6",'1'&x"A5C7",'1'&x"A5C8",'1'&x"A5C9",'1'&x"A5CA",'1'&x"A5CB",'1'&x"A5CC",'1'&x"A5CD",'1'&x"A5CE",'1'&x"A5CF",
+--'1'&x"A5D0",'1'&x"A5D1",'1'&x"A5D2",'1'&x"A5D3",'1'&x"A5D4",'1'&x"A5D5",'1'&x"A5D6",'1'&x"A5D7",'1'&x"A5D8",'1'&x"A5D9",'1'&x"A5DA",'1'&x"A5DB",'1'&x"A5DC",'1'&x"A5DD",'1'&x"A5DE",'1'&x"A5DF",
+--'1'&x"A5E0",'1'&x"A5E1",'1'&x"A5E2",'1'&x"A5E3",'1'&x"A5E4",'1'&x"A5E5",'1'&x"A5E6",'1'&x"A5E7",'1'&x"A5E8",'1'&x"A5E9",'1'&x"A5EA",'1'&x"A5EB",'1'&x"A5EC",'1'&x"A5ED",'1'&x"A5EE",'1'&x"A5EF",
+--'1'&x"A5F0",'1'&x"A5F1",'1'&x"A5F2",'1'&x"A5F3",'1'&x"A5F4",'1'&x"A5F5",'1'&x"A5F6",'1'&x"A5F7",'1'&x"A5F8",'1'&x"A5F9",'1'&x"A5FA",'1'&x"A5FB",'1'&x"A5FC",'1'&x"A5FD",'1'&x"A5FE",'1'&x"A5FF",
+--'1'&x"A600",'1'&x"A601",'1'&x"A602",'1'&x"A603",'1'&x"A604",'1'&x"A605",'1'&x"A606",'1'&x"A607",'1'&x"A608",'1'&x"A609",'1'&x"A60A",'1'&x"A60B",'1'&x"A60C",'1'&x"A60D",'1'&x"A60E",'1'&x"A60F",
+--'1'&x"A610",'1'&x"A611",'1'&x"A612",'1'&x"A613",'1'&x"A614",'1'&x"A615",'1'&x"A616",'1'&x"A617",'1'&x"A618",'1'&x"A619",'1'&x"A61A",'1'&x"A61B",'1'&x"A61C",'1'&x"A61D",'1'&x"A61E",'1'&x"A61F",
+--'1'&x"A620",'1'&x"A621",'1'&x"A622",'1'&x"A623",'1'&x"A624",'1'&x"A625",'1'&x"A626",'1'&x"A627",'1'&x"A628",'1'&x"A629",'1'&x"A62A",'1'&x"A62B",'1'&x"A62C",'1'&x"A62D",'1'&x"A62E",'1'&x"A62F",
+--'1'&x"A630",'1'&x"A631",'1'&x"A632",'1'&x"A633",'1'&x"A634",'1'&x"A635",'1'&x"A636",'1'&x"A637",'1'&x"A638",'1'&x"A639",'1'&x"A63A",'1'&x"A63B",'1'&x"A63C",'1'&x"A63D",'1'&x"A63E",'1'&x"A63F",
+--'1'&x"A640",'1'&x"A641",'1'&x"A642",'1'&x"A643",'1'&x"A644",'1'&x"A645",'1'&x"A646",'1'&x"A647",'1'&x"A648",'1'&x"A649",'1'&x"A64A",'1'&x"A64B",'1'&x"A64C",'1'&x"A64D",'1'&x"A64E",'1'&x"A64F",
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+--'1'&x"AC50",'1'&x"AC51",'1'&x"AC52",'1'&x"AC53",'1'&x"AC54",'1'&x"AC55",'1'&x"AC56",'1'&x"AC57",'1'&x"AC58",'1'&x"AC59",'1'&x"AC5A",'1'&x"AC5B",'1'&x"AC5C",'1'&x"AC5D",'1'&x"AC5E",'1'&x"AC5F",
+--'1'&x"AC60",'1'&x"AC61",'1'&x"AC62",'1'&x"AC63",'1'&x"AC64",'1'&x"AC65",'1'&x"AC66",'1'&x"AC67",'1'&x"AC68",'1'&x"AC69",'1'&x"AC6A",'1'&x"AC6B",'1'&x"AC6C",'1'&x"AC6D",'1'&x"AC6E",'1'&x"AC6F",
+--'1'&x"AC70",'1'&x"AC71",'1'&x"AC72",'1'&x"AC73",'1'&x"AC74",'1'&x"AC75",'1'&x"AC76",'1'&x"AC77",'1'&x"AC78",'1'&x"AC79",'1'&x"AC7A",'1'&x"AC7B",'1'&x"AC7C",'1'&x"AC7D",'1'&x"AC7E",'1'&x"AC7F",
+--'1'&x"AC80",'1'&x"AC81",'1'&x"AC82",'1'&x"AC83",'1'&x"AC84",'1'&x"AC85",'1'&x"AC86",'1'&x"AC87",'1'&x"AC88",'1'&x"AC89",'1'&x"AC8A",'1'&x"AC8B",'1'&x"AC8C",'1'&x"AC8D",'1'&x"AC8E",'1'&x"AC8F",
+--'1'&x"AC90",'1'&x"AC91",'1'&x"AC92",'1'&x"AC93",'1'&x"AC94",'1'&x"AC95",'1'&x"AC96",'1'&x"AC97",'1'&x"AC98",'1'&x"AC99",'1'&x"AC9A",'1'&x"AC9B",'1'&x"AC9C",'1'&x"AC9D",'1'&x"AC9E",'1'&x"AC9F",
+--'1'&x"ACA0",'1'&x"ACA1",'1'&x"ACA2",'1'&x"ACA3",'1'&x"ACA4",'1'&x"ACA5",'1'&x"ACA6",'1'&x"ACA7",'1'&x"ACA8",'1'&x"ACA9",'1'&x"ACAA",'1'&x"ACAB",'1'&x"ACAC",'1'&x"ACAD",'1'&x"ACAE",'1'&x"ACAF",
+--'1'&x"ACB0",'1'&x"ACB1",'1'&x"ACB2",'1'&x"ACB3",'1'&x"ACB4",'1'&x"ACB5",'1'&x"ACB6",'1'&x"ACB7",'1'&x"ACB8",'1'&x"ACB9",'1'&x"ACBA",'1'&x"ACBB",'1'&x"ACBC",'1'&x"ACBD",'1'&x"ACBE",'1'&x"ACBF",
+--'1'&x"ACC0",'1'&x"ACC1",'1'&x"ACC2",'1'&x"ACC3",'1'&x"ACC4",'1'&x"ACC5",'1'&x"ACC6",'1'&x"ACC7",'1'&x"ACC8",'1'&x"ACC9",'1'&x"ACCA",'1'&x"ACCB",'1'&x"ACCC",'1'&x"ACCD",'1'&x"ACCE",'1'&x"ACCF",
+--'1'&x"ACD0",'1'&x"ACD1",'1'&x"ACD2",'1'&x"ACD3",'1'&x"ACD4",'1'&x"ACD5",'1'&x"ACD6",'1'&x"ACD7",'1'&x"ACD8",'1'&x"ACD9",'1'&x"ACDA",'1'&x"ACDB",'1'&x"ACDC",'1'&x"ACDD",'1'&x"ACDE",'1'&x"ACDF",
+--'1'&x"ACE0",'1'&x"ACE1",'1'&x"ACE2",'1'&x"ACE3",'1'&x"ACE4",'1'&x"ACE5",'1'&x"ACE6",'1'&x"ACE7",'1'&x"ACE8",'1'&x"ACE9",'1'&x"ACEA",'1'&x"ACEB",'1'&x"ACEC",'1'&x"ACED",'1'&x"ACEE",'1'&x"ACEF",
+--'1'&x"ACF0",'1'&x"ACF1",'1'&x"ACF2",'1'&x"ACF3",'1'&x"ACF4",'1'&x"ACF5",'1'&x"ACF6",'1'&x"ACF7",'1'&x"ACF8",'1'&x"ACF9",'1'&x"ACFA",'1'&x"ACFB",'1'&x"ACFC",'1'&x"ACFD",'1'&x"ACFE",'1'&x"ACFF",
+--'1'&x"AD00",'1'&x"AD01",'1'&x"AD02",'1'&x"AD03",'1'&x"AD04",'1'&x"AD05",'1'&x"AD06",'1'&x"AD07",'1'&x"AD08",'1'&x"AD09",'1'&x"AD0A",'1'&x"AD0B",'1'&x"AD0C",'1'&x"AD0D",'1'&x"AD0E",'1'&x"AD0F",
+--'1'&x"AD10",'1'&x"AD11",'1'&x"AD12",'1'&x"AD13",'1'&x"AD14",'1'&x"AD15",'1'&x"AD16",'1'&x"AD17",'1'&x"AD18",'1'&x"AD19",'1'&x"AD1A",'1'&x"AD1B",'1'&x"AD1C",'1'&x"AD1D",'1'&x"AD1E",'1'&x"AD1F",
+--'1'&x"AD20",'1'&x"AD21",'1'&x"AD22",'1'&x"AD23",'1'&x"AD24",'1'&x"AD25",'1'&x"AD26",'1'&x"AD27",'1'&x"AD28",'1'&x"AD29",'1'&x"AD2A",'1'&x"AD2B",'1'&x"AD2C",'1'&x"AD2D",'1'&x"AD2E",'1'&x"AD2F",
+--'1'&x"AD30",'1'&x"AD31",'1'&x"AD32",'1'&x"AD33",'1'&x"AD34",'1'&x"AD35",'1'&x"AD36",'1'&x"AD37",'1'&x"AD38",'1'&x"AD39",'1'&x"AD3A",'1'&x"AD3B",'1'&x"AD3C",'1'&x"AD3D",'1'&x"AD3E",'1'&x"AD3F",
+--'1'&x"AD40",'1'&x"AD41",'1'&x"AD42",'1'&x"AD43",'1'&x"AD44",'1'&x"AD45",'1'&x"AD46",'1'&x"AD47",'1'&x"AD48",'1'&x"AD49",'1'&x"AD4A",'1'&x"AD4B",'1'&x"AD4C",'1'&x"AD4D",'1'&x"AD4E",'1'&x"AD4F",
+--'1'&x"AD50",'1'&x"AD51",'1'&x"AD52",'1'&x"AD53",'1'&x"AD54",'1'&x"AD55",'1'&x"AD56",'1'&x"AD57",'1'&x"AD58",'1'&x"AD59",'1'&x"AD5A",'1'&x"AD5B",'1'&x"AD5C",'1'&x"AD5D",'1'&x"AD5E",'1'&x"AD5F",
+--'1'&x"AD60",'1'&x"AD61",'1'&x"AD62",'1'&x"AD63",'1'&x"AD64",'1'&x"AD65",'1'&x"AD66",'1'&x"AD67",'1'&x"AD68",'1'&x"AD69",'1'&x"AD6A",'1'&x"AD6B",'1'&x"AD6C",'1'&x"AD6D",'1'&x"AD6E",'1'&x"AD6F",
+--'1'&x"AD70",'1'&x"AD71",'1'&x"AD72",'1'&x"AD73",'1'&x"AD74",'1'&x"AD75",'1'&x"AD76",'1'&x"AD77",'1'&x"AD78",'1'&x"AD79",'1'&x"AD7A",'1'&x"AD7B",'1'&x"AD7C",'1'&x"AD7D",'1'&x"AD7E",'1'&x"AD7F",
+--'1'&x"AD80",'1'&x"AD81",'1'&x"AD82",'1'&x"AD83",'1'&x"AD84",'1'&x"AD85",'1'&x"AD86",'1'&x"AD87",'1'&x"AD88",'1'&x"AD89",'1'&x"AD8A",'1'&x"AD8B",'1'&x"AD8C",'1'&x"AD8D",'1'&x"AD8E",'1'&x"AD8F",
+--'1'&x"AD90",'1'&x"AD91",'1'&x"AD92",'1'&x"AD93",'1'&x"AD94",'1'&x"AD95",'1'&x"AD96",'1'&x"AD97",'1'&x"AD98",'1'&x"AD99",'1'&x"AD9A",'1'&x"AD9B",'1'&x"AD9C",'1'&x"AD9D",'1'&x"AD9E",'1'&x"AD9F",
+--'1'&x"ADA0",'1'&x"ADA1",'1'&x"ADA2",'1'&x"ADA3",'1'&x"ADA4",'1'&x"ADA5",'1'&x"ADA6",'1'&x"ADA7",'1'&x"ADA8",'1'&x"ADA9",'1'&x"ADAA",'1'&x"ADAB",'1'&x"ADAC",'1'&x"ADAD",'1'&x"ADAE",'1'&x"ADAF",
+--'1'&x"ADB0",'1'&x"ADB1",'1'&x"ADB2",'1'&x"ADB3",'1'&x"ADB4",'1'&x"ADB5",'1'&x"ADB6",'1'&x"ADB7",'1'&x"ADB8",'1'&x"ADB9",'1'&x"ADBA",'1'&x"ADBB",'1'&x"ADBC",'1'&x"ADBD",'1'&x"ADBE",'1'&x"ADBF",
+--'1'&x"ADC0",'1'&x"ADC1",'1'&x"ADC2",'1'&x"ADC3",'1'&x"ADC4",'1'&x"ADC5",'1'&x"ADC6",'1'&x"ADC7",'1'&x"ADC8",'1'&x"ADC9",'1'&x"ADCA",'1'&x"ADCB",'1'&x"ADCC",'1'&x"ADCD",'1'&x"ADCE",'1'&x"ADCF",
+--'1'&x"ADD0",'1'&x"ADD1",'1'&x"ADD2",'1'&x"ADD3",'1'&x"ADD4",'1'&x"ADD5",'1'&x"ADD6",'1'&x"ADD7",'1'&x"ADD8",'1'&x"ADD9",'1'&x"ADDA",'1'&x"ADDB",'1'&x"ADDC",'1'&x"ADDD",'1'&x"ADDE",'1'&x"ADDF",
+--'1'&x"ADE0",'1'&x"ADE1",'1'&x"ADE2",'1'&x"ADE3",'1'&x"ADE4",'1'&x"ADE5",'1'&x"ADE6",'1'&x"ADE7",'1'&x"ADE8",'1'&x"ADE9",'1'&x"ADEA",'1'&x"ADEB",'1'&x"ADEC",'1'&x"ADED",'1'&x"ADEE",'1'&x"ADEF",
+--'1'&x"ADF0",'1'&x"ADF1",'1'&x"ADF2",'1'&x"ADF3",'1'&x"ADF4",'1'&x"ADF5",'1'&x"ADF6",'1'&x"ADF7",'1'&x"ADF8",'1'&x"ADF9",'1'&x"ADFA",'1'&x"ADFB",'1'&x"ADFC",'1'&x"ADFD",'1'&x"ADFE",'1'&x"ADFF",
+--'1'&x"AE00",'1'&x"AE01",'1'&x"AE02",'1'&x"AE03",'1'&x"AE04",'1'&x"AE05",'1'&x"AE06",'1'&x"AE07",'1'&x"AE08",'1'&x"AE09",'1'&x"AE0A",'1'&x"AE0B",'1'&x"AE0C",'1'&x"AE0D",'1'&x"AE0E",'1'&x"AE0F",
+--'1'&x"AE10",'1'&x"AE11",'1'&x"AE12",'1'&x"AE13",'1'&x"AE14",'1'&x"AE15",'1'&x"AE16",'1'&x"AE17",'1'&x"AE18",'1'&x"AE19",'1'&x"AE1A",'1'&x"AE1B",'1'&x"AE1C",'1'&x"AE1D",'1'&x"AE1E",'1'&x"AE1F",
+--'1'&x"AE20",'1'&x"AE21",'1'&x"AE22",'1'&x"AE23",'1'&x"AE24",'1'&x"AE25",'1'&x"AE26",'1'&x"AE27",'1'&x"AE28",'1'&x"AE29",'1'&x"AE2A",'1'&x"AE2B",'1'&x"AE2C",'1'&x"AE2D",'1'&x"AE2E",'1'&x"AE2F",
+--'1'&x"AE30",'1'&x"AE31",'1'&x"AE32",'1'&x"AE33",'1'&x"AE34",'1'&x"AE35",'1'&x"AE36",'1'&x"AE37",'1'&x"AE38",'1'&x"AE39",'1'&x"AE3A",'1'&x"AE3B",'1'&x"AE3C",'1'&x"AE3D",'1'&x"AE3E",'1'&x"AE3F",
+--'1'&x"AE40",'1'&x"AE41",'1'&x"AE42",'1'&x"AE43",'1'&x"AE44",'1'&x"AE45",'1'&x"AE46",'1'&x"AE47",'1'&x"AE48",'1'&x"AE49",'1'&x"AE4A",'1'&x"AE4B",'1'&x"AE4C",'1'&x"AE4D",'1'&x"AE4E",'1'&x"AE4F",
+--'1'&x"AE50",'1'&x"AE51",'1'&x"AE52",'1'&x"AE53",'1'&x"AE54",'1'&x"AE55",'1'&x"AE56",'1'&x"AE57",'1'&x"AE58",'1'&x"AE59",'1'&x"AE5A",'1'&x"AE5B",'1'&x"AE5C",'1'&x"AE5D",'1'&x"AE5E",'1'&x"AE5F",
+--'1'&x"AE60",'1'&x"AE61",'1'&x"AE62",'1'&x"AE63",'1'&x"AE64",'1'&x"AE65",'1'&x"AE66",'1'&x"AE67",'1'&x"AE68",'1'&x"AE69",'1'&x"AE6A",'1'&x"AE6B",'1'&x"AE6C",'1'&x"AE6D",'1'&x"AE6E",'1'&x"AE6F",
+--'1'&x"AE70",'1'&x"AE71",'1'&x"AE72",'1'&x"AE73",'1'&x"AE74",'1'&x"AE75",'1'&x"AE76",'1'&x"AE77",'1'&x"AE78",'1'&x"AE79",'1'&x"AE7A",'1'&x"AE7B",'1'&x"AE7C",'1'&x"AE7D",'1'&x"AE7E",'1'&x"AE7F",
+--'1'&x"AE80",'1'&x"AE81",'1'&x"AE82",'1'&x"AE83",'1'&x"AE84",'1'&x"AE85",'1'&x"AE86",'1'&x"AE87",'1'&x"AE88",'1'&x"AE89",'1'&x"AE8A",'1'&x"AE8B",'1'&x"AE8C",'1'&x"AE8D",'1'&x"AE8E",'1'&x"AE8F",
+--'1'&x"AE90",'1'&x"AE91",'1'&x"AE92",'1'&x"AE93",'1'&x"AE94",'1'&x"AE95",'1'&x"AE96",'1'&x"AE97",'1'&x"AE98",'1'&x"AE99",'1'&x"AE9A",'1'&x"AE9B",'1'&x"AE9C",'1'&x"AE9D",'1'&x"AE9E",'1'&x"AE9F",
+--'1'&x"AEA0",'1'&x"AEA1",'1'&x"AEA2",'1'&x"AEA3",'1'&x"AEA4",'1'&x"AEA5",'1'&x"AEA6",'1'&x"AEA7",'1'&x"AEA8",'1'&x"AEA9",'1'&x"AEAA",'1'&x"AEAB",'1'&x"AEAC",'1'&x"AEAD",'1'&x"AEAE",'1'&x"AEAF",
+--'1'&x"AEB0",'1'&x"AEB1",'1'&x"AEB2",'1'&x"AEB3",'1'&x"AEB4",'1'&x"AEB5",'1'&x"AEB6",'1'&x"AEB7",'1'&x"AEB8",'1'&x"AEB9",'1'&x"AEBA",'1'&x"AEBB",'1'&x"AEBC",'1'&x"AEBD",'1'&x"AEBE",'1'&x"AEBF",
+--'1'&x"AEC0",'1'&x"AEC1",'1'&x"AEC2",'1'&x"AEC3",'1'&x"AEC4",'1'&x"AEC5",'1'&x"AEC6",'1'&x"AEC7",'1'&x"AEC8",'1'&x"AEC9",'1'&x"AECA",'1'&x"AECB",'1'&x"AECC",'1'&x"AECD",'1'&x"AECE",'1'&x"AECF",
+--'1'&x"AED0",'1'&x"AED1",'1'&x"AED2",'1'&x"AED3",'1'&x"AED4",'1'&x"AED5",'1'&x"AED6",'1'&x"AED7",'1'&x"AED8",'1'&x"AED9",'1'&x"AEDA",'1'&x"AEDB",'1'&x"AEDC",'1'&x"AEDD",'1'&x"AEDE",'1'&x"AEDF",
+--'1'&x"AEE0",'1'&x"AEE1",'1'&x"AEE2",'1'&x"AEE3",'1'&x"AEE4",'1'&x"AEE5",'1'&x"AEE6",'1'&x"AEE7",'1'&x"AEE8",'1'&x"AEE9",'1'&x"AEEA",'1'&x"AEEB",'1'&x"AEEC",'1'&x"AEED",'1'&x"AEEE",'1'&x"AEEF",
+--'1'&x"AEF0",'1'&x"AEF1",'1'&x"AEF2",'1'&x"AEF3",'1'&x"AEF4",'1'&x"AEF5",'1'&x"AEF6",'1'&x"AEF7",'1'&x"AEF8",'1'&x"AEF9",'1'&x"AEFA",'1'&x"AEFB",'1'&x"AEFC",'1'&x"AEFD",'1'&x"AEFE",'1'&x"AEFF",
+--'1'&x"AF00",'1'&x"AF01",'1'&x"AF02",'1'&x"AF03",'1'&x"AF04",'1'&x"AF05",'1'&x"AF06",'1'&x"AF07",'1'&x"AF08",'1'&x"AF09",'1'&x"AF0A",'1'&x"AF0B",'1'&x"AF0C",'1'&x"AF0D",'1'&x"AF0E",'1'&x"AF0F",
+--'1'&x"AF10",'1'&x"AF11",'1'&x"AF12",'1'&x"AF13",'1'&x"AF14",'1'&x"AF15",'1'&x"AF16",'1'&x"AF17",'1'&x"AF18",'1'&x"AF19",'1'&x"AF1A",'1'&x"AF1B",'1'&x"AF1C",'1'&x"AF1D",'1'&x"AF1E",'1'&x"AF1F",
+--'1'&x"AF20",'1'&x"AF21",'1'&x"AF22",'1'&x"AF23",'1'&x"AF24",'1'&x"AF25",'1'&x"AF26",'1'&x"AF27",'1'&x"AF28",'1'&x"AF29",'1'&x"AF2A",'1'&x"AF2B",'1'&x"AF2C",'1'&x"AF2D",'1'&x"AF2E",'1'&x"AF2F",
+--'1'&x"AF30",'1'&x"AF31",'1'&x"AF32",'1'&x"AF33",'1'&x"AF34",'1'&x"AF35",'1'&x"AF36",'1'&x"AF37",'1'&x"AF38",'1'&x"AF39",'1'&x"AF3A",'1'&x"AF3B",'1'&x"AF3C",'1'&x"AF3D",'1'&x"AF3E",'1'&x"AF3F",
+--'1'&x"AF40",'1'&x"AF41",'1'&x"AF42",'1'&x"AF43",'1'&x"AF44",'1'&x"AF45",'1'&x"AF46",'1'&x"AF47",'1'&x"AF48",'1'&x"AF49",'1'&x"AF4A",'1'&x"AF4B",'1'&x"AF4C",'1'&x"AF4D",'1'&x"AF4E",'1'&x"AF4F",
+--'1'&x"AF50",'1'&x"AF51",'1'&x"AF52",'1'&x"AF53",'1'&x"AF54",'1'&x"AF55",'1'&x"AF56",'1'&x"AF57",'1'&x"AF58",'1'&x"AF59",'1'&x"AF5A",'1'&x"AF5B",'1'&x"AF5C",'1'&x"AF5D",'1'&x"AF5E",'1'&x"AF5F",
+--'1'&x"AF60",'1'&x"AF61",'1'&x"AF62",'1'&x"AF63",'1'&x"AF64",'1'&x"AF65",'1'&x"AF66",'1'&x"AF67",'1'&x"AF68",'1'&x"AF69",'1'&x"AF6A",'1'&x"AF6B",'1'&x"AF6C",'1'&x"AF6D",'1'&x"AF6E",'1'&x"AF6F",
+--'1'&x"AF70",'1'&x"AF71",'1'&x"AF72",'1'&x"AF73",'1'&x"AF74",'1'&x"AF75",'1'&x"AF76",'1'&x"AF77",'1'&x"AF78",'1'&x"AF79",'1'&x"AF7A",'1'&x"AF7B",'1'&x"AF7C",'1'&x"AF7D",'1'&x"AF7E",'1'&x"AF7F",
+--'1'&x"AF80",'1'&x"AF81",'1'&x"AF82",'1'&x"AF83",'1'&x"AF84",'1'&x"AF85",'1'&x"AF86",'1'&x"AF87",'1'&x"AF88",'1'&x"AF89",'1'&x"AF8A",'1'&x"AF8B",'1'&x"AF8C",'1'&x"AF8D",'1'&x"AF8E",'1'&x"AF8F",
+--'1'&x"AF90",'1'&x"AF91",'1'&x"AF92",'1'&x"AF93",'1'&x"AF94",'1'&x"AF95",'1'&x"AF96",'1'&x"AF97",'1'&x"AF98",'1'&x"AF99",'1'&x"AF9A",'1'&x"AF9B",'1'&x"AF9C",'1'&x"AF9D",'1'&x"AF9E",'1'&x"AF9F",
+--'1'&x"AFA0",'1'&x"AFA1",'1'&x"AFA2",'1'&x"AFA3",'1'&x"AFA4",'1'&x"AFA5",'1'&x"AFA6",'1'&x"AFA7",'1'&x"AFA8",'1'&x"AFA9",'1'&x"AFAA",'1'&x"AFAB",'1'&x"AFAC",'1'&x"AFAD",'1'&x"AFAE",'1'&x"AFAF",
+--'1'&x"AFB0",'1'&x"AFB1",'1'&x"AFB2",'1'&x"AFB3",'1'&x"AFB4",'1'&x"AFB5",'1'&x"AFB6",'1'&x"AFB7",'1'&x"AFB8",'1'&x"AFB9",'1'&x"AFBA",'1'&x"AFBB",'1'&x"AFBC",'1'&x"AFBD",'1'&x"AFBE",'1'&x"AFBF",
+--'1'&x"AFC0",'1'&x"AFC1",'1'&x"AFC2",'1'&x"AFC3",'1'&x"AFC4",'1'&x"AFC5",'1'&x"AFC6",'1'&x"AFC7",'1'&x"AFC8",'1'&x"AFC9",'1'&x"AFCA",'1'&x"AFCB",'1'&x"AFCC",'1'&x"AFCD",'1'&x"AFCE",'1'&x"AFCF",
+--'1'&x"AFD0",'1'&x"AFD1",'1'&x"AFD2",'1'&x"AFD3",'1'&x"AFD4",'1'&x"AFD5",'1'&x"AFD6",'1'&x"AFD7",'1'&x"AFD8",'1'&x"AFD9",'1'&x"AFDA",'1'&x"AFDB",'1'&x"AFDC",'1'&x"AFDD",'1'&x"AFDE",'1'&x"AFDF",
+--'1'&x"AFE0",'1'&x"AFE1",'1'&x"AFE2",'1'&x"AFE3",'1'&x"AFE4",'1'&x"AFE5",'1'&x"AFE6",'1'&x"AFE7",'1'&x"AFE8",'1'&x"AFE9",'1'&x"AFEA",'1'&x"AFEB",'1'&x"AFEC",'1'&x"AFED",'1'&x"AFEE",'1'&x"AFEF",
+--'1'&x"AFF0",'1'&x"AFF1",'1'&x"AFF2",'1'&x"AFF3",'1'&x"AFF4",'1'&x"AFF5",'1'&x"AFF6",'1'&x"AFF7",'1'&x"AFF8",'1'&x"AFF9",'1'&x"AFFA",'1'&x"AFFB",'1'&x"AFFC",'1'&x"AFFD",'1'&x"AFFE",'1'&x"AFFF",
+--'1'&x"B000",'1'&x"B001",'1'&x"B002",'1'&x"B003",'1'&x"B004",'1'&x"B005",'1'&x"B006",'1'&x"B007",'1'&x"B008",'1'&x"B009",'1'&x"B00A",'1'&x"B00B",'1'&x"B00C",'1'&x"B00D",'1'&x"B00E",'1'&x"B00F",
+--'1'&x"B010",'1'&x"B011",'1'&x"B012",'1'&x"B013",'1'&x"B014",'1'&x"B015",'1'&x"B016",'1'&x"B017",'1'&x"B018",'1'&x"B019",'1'&x"B01A",'1'&x"B01B",'1'&x"B01C",'1'&x"B01D",'1'&x"B01E",'1'&x"B01F",
+--'1'&x"B020",'1'&x"B021",'1'&x"B022",'1'&x"B023",'1'&x"B024",'1'&x"B025",'1'&x"B026",'1'&x"B027",'1'&x"B028",'1'&x"B029",'1'&x"B02A",'1'&x"B02B",'1'&x"B02C",'1'&x"B02D",'1'&x"B02E",'1'&x"B02F",
+--'1'&x"B030",'1'&x"B031",'1'&x"B032",'1'&x"B033",'1'&x"B034",'1'&x"B035",'1'&x"B036",'1'&x"B037",'1'&x"B038",'1'&x"B039",'1'&x"B03A",'1'&x"B03B",'1'&x"B03C",'1'&x"B03D",'1'&x"B03E",'1'&x"B03F",
+--'1'&x"B040",'1'&x"B041",'1'&x"B042",'1'&x"B043",'1'&x"B044",'1'&x"B045",'1'&x"B046",'1'&x"B047",'1'&x"B048",'1'&x"B049",'1'&x"B04A",'1'&x"B04B",'1'&x"B04C",'1'&x"B04D",'1'&x"B04E",'1'&x"B04F",
+--'1'&x"B050",'1'&x"B051",'1'&x"B052",'1'&x"B053",'1'&x"B054",'1'&x"B055",'1'&x"B056",'1'&x"B057",'1'&x"B058",'1'&x"B059",'1'&x"B05A",'1'&x"B05B",'1'&x"B05C",'1'&x"B05D",'1'&x"B05E",'1'&x"B05F",
+--'1'&x"B060",'1'&x"B061",'1'&x"B062",'1'&x"B063",'1'&x"B064",'1'&x"B065",'1'&x"B066",'1'&x"B067",'1'&x"B068",'1'&x"B069",'1'&x"B06A",'1'&x"B06B",'1'&x"B06C",'1'&x"B06D",'1'&x"B06E",'1'&x"B06F",
+--'1'&x"B070",'1'&x"B071",'1'&x"B072",'1'&x"B073",'1'&x"B074",'1'&x"B075",'1'&x"B076",'1'&x"B077",'1'&x"B078",'1'&x"B079",'1'&x"B07A",'1'&x"B07B",'1'&x"B07C",'1'&x"B07D",'1'&x"B07E",'1'&x"B07F",
+--'1'&x"B080",'1'&x"B081",'1'&x"B082",'1'&x"B083",'1'&x"B084",'1'&x"B085",'1'&x"B086",'1'&x"B087",'1'&x"B088",'1'&x"B089",'1'&x"B08A",'1'&x"B08B",'1'&x"B08C",'1'&x"B08D",'1'&x"B08E",'1'&x"B08F",
+--'1'&x"B090",'1'&x"B091",'1'&x"B092",'1'&x"B093",'1'&x"B094",'1'&x"B095",'1'&x"B096",'1'&x"B097",'1'&x"B098",'1'&x"B099",'1'&x"B09A",'1'&x"B09B",'1'&x"B09C",'1'&x"B09D",'1'&x"B09E",'1'&x"B09F",
+--'1'&x"B0A0",'1'&x"B0A1",'1'&x"B0A2",'1'&x"B0A3",'1'&x"B0A4",'1'&x"B0A5",'1'&x"B0A6",'1'&x"B0A7",'1'&x"B0A8",'1'&x"B0A9",'1'&x"B0AA",'1'&x"B0AB",'1'&x"B0AC",'1'&x"B0AD",'1'&x"B0AE",'1'&x"B0AF",
+--'1'&x"B0B0",'1'&x"B0B1",'1'&x"B0B2",'1'&x"B0B3",'1'&x"B0B4",'1'&x"B0B5",'1'&x"B0B6",'1'&x"B0B7",'1'&x"B0B8",'1'&x"B0B9",'1'&x"B0BA",'1'&x"B0BB",'1'&x"B0BC",'1'&x"B0BD",'1'&x"B0BE",'1'&x"B0BF",
+--'1'&x"B0C0",'1'&x"B0C1",'1'&x"B0C2",'1'&x"B0C3",'1'&x"B0C4",'1'&x"B0C5",'1'&x"B0C6",'1'&x"B0C7",'1'&x"B0C8",'1'&x"B0C9",'1'&x"B0CA",'1'&x"B0CB",'1'&x"B0CC",'1'&x"B0CD",'1'&x"B0CE",'1'&x"B0CF",
+--'1'&x"B0D0",'1'&x"B0D1",'1'&x"B0D2",'1'&x"B0D3",'1'&x"B0D4",'1'&x"B0D5",'1'&x"B0D6",'1'&x"B0D7",'1'&x"B0D8",'1'&x"B0D9",'1'&x"B0DA",'1'&x"B0DB",'1'&x"B0DC",'1'&x"B0DD",'1'&x"B0DE",'1'&x"B0DF",
+--'1'&x"B0E0",'1'&x"B0E1",'1'&x"B0E2",'1'&x"B0E3",'1'&x"B0E4",'1'&x"B0E5",'1'&x"B0E6",'1'&x"B0E7",'1'&x"B0E8",'1'&x"B0E9",'1'&x"B0EA",'1'&x"B0EB",'1'&x"B0EC",'1'&x"B0ED",'1'&x"B0EE",'1'&x"B0EF",
+--'1'&x"B0F0",'1'&x"B0F1",'1'&x"B0F2",'1'&x"B0F3",'1'&x"B0F4",'1'&x"B0F5",'1'&x"B0F6",'1'&x"B0F7",'1'&x"B0F8",'1'&x"B0F9",'1'&x"B0FA",'1'&x"B0FB",'1'&x"B0FC",'1'&x"B0FD",'1'&x"B0FE",'1'&x"B0FF",
+--'1'&x"B100",'1'&x"B101",'1'&x"B102",'1'&x"B103",'1'&x"B104",'1'&x"B105",'1'&x"B106",'1'&x"B107",'1'&x"B108",'1'&x"B109",'1'&x"B10A",'1'&x"B10B",'1'&x"B10C",'1'&x"B10D",'1'&x"B10E",'1'&x"B10F",
+--'1'&x"B110",'1'&x"B111",'1'&x"B112",'1'&x"B113",'1'&x"B114",'1'&x"B115",'1'&x"B116",'1'&x"B117",'1'&x"B118",'1'&x"B119",'1'&x"B11A",'1'&x"B11B",'1'&x"B11C",'1'&x"B11D",'1'&x"B11E",'1'&x"B11F",
+--'1'&x"B120",'1'&x"B121",'1'&x"B122",'1'&x"B123",'1'&x"B124",'1'&x"B125",'1'&x"B126",'1'&x"B127",'1'&x"B128",'1'&x"B129",'1'&x"B12A",'1'&x"B12B",'1'&x"B12C",'1'&x"B12D",'1'&x"B12E",'1'&x"B12F",
+--'1'&x"B130",'1'&x"B131",'1'&x"B132",'1'&x"B133",'1'&x"B134",'1'&x"B135",'1'&x"B136",'1'&x"B137",'1'&x"B138",'1'&x"B139",'1'&x"B13A",'1'&x"B13B",'1'&x"B13C",'1'&x"B13D",'1'&x"B13E",'1'&x"B13F",
+--'1'&x"B140",'1'&x"B141",'1'&x"B142",'1'&x"B143",'1'&x"B144",'1'&x"B145",'1'&x"B146",'1'&x"B147",'1'&x"B148",'1'&x"B149",'1'&x"B14A",'1'&x"B14B",'1'&x"B14C",'1'&x"B14D",'1'&x"B14E",'1'&x"B14F",
+--'1'&x"B150",'1'&x"B151",'1'&x"B152",'1'&x"B153",'1'&x"B154",'1'&x"B155",'1'&x"B156",'1'&x"B157",'1'&x"B158",'1'&x"B159",'1'&x"B15A",'1'&x"B15B",'1'&x"B15C",'1'&x"B15D",'1'&x"B15E",'1'&x"B15F",
+--'1'&x"B160",'1'&x"B161",'1'&x"B162",'1'&x"B163",'1'&x"B164",'1'&x"B165",'1'&x"B166",'1'&x"B167",'1'&x"B168",'1'&x"B169",'1'&x"B16A",'1'&x"B16B",'1'&x"B16C",'1'&x"B16D",'1'&x"B16E",'1'&x"B16F",
+--'1'&x"B170",'1'&x"B171",'1'&x"B172",'1'&x"B173",'1'&x"B174",'1'&x"B175",'1'&x"B176",'1'&x"B177",'1'&x"B178",'1'&x"B179",'1'&x"B17A",'1'&x"B17B",'1'&x"B17C",'1'&x"B17D",'1'&x"B17E",'1'&x"B17F",
+--'1'&x"B180",'1'&x"B181",'1'&x"B182",'1'&x"B183",'1'&x"B184",'1'&x"B185",'1'&x"B186",'1'&x"B187",'1'&x"B188",'1'&x"B189",'1'&x"B18A",'1'&x"B18B",'1'&x"B18C",'1'&x"B18D",'1'&x"B18E",'1'&x"B18F",
+--'1'&x"B190",'1'&x"B191",'1'&x"B192",'1'&x"B193",'1'&x"B194",'1'&x"B195",'1'&x"B196",'1'&x"B197",'1'&x"B198",'1'&x"B199",'1'&x"B19A",'1'&x"B19B",'1'&x"B19C",'1'&x"B19D",'1'&x"B19E",'1'&x"B19F",
+--'1'&x"B1A0",'1'&x"B1A1",'1'&x"B1A2",'1'&x"B1A3",'1'&x"B1A4",'1'&x"B1A5",'1'&x"B1A6",'1'&x"B1A7",'1'&x"B1A8",'1'&x"B1A9",'1'&x"B1AA",'1'&x"B1AB",'1'&x"B1AC",'1'&x"B1AD",'1'&x"B1AE",'1'&x"B1AF",
+--'1'&x"B1B0",'1'&x"B1B1",'1'&x"B1B2",'1'&x"B1B3",'1'&x"B1B4",'1'&x"B1B5",'1'&x"B1B6",'1'&x"B1B7",'1'&x"B1B8",'1'&x"B1B9",'1'&x"B1BA",'1'&x"B1BB",'1'&x"B1BC",'1'&x"B1BD",'1'&x"B1BE",'1'&x"B1BF",
+--'1'&x"B1C0",'1'&x"B1C1",'1'&x"B1C2",'1'&x"B1C3",'1'&x"B1C4",'1'&x"B1C5",'1'&x"B1C6",'1'&x"B1C7",'1'&x"B1C8",'1'&x"B1C9",'1'&x"B1CA",'1'&x"B1CB",'1'&x"B1CC",'1'&x"B1CD",'1'&x"B1CE",'1'&x"B1CF",
+--'1'&x"B1D0",'1'&x"B1D1",'1'&x"B1D2",'1'&x"B1D3",'1'&x"B1D4",'1'&x"B1D5",'1'&x"B1D6",'1'&x"B1D7",'1'&x"B1D8",'1'&x"B1D9",'1'&x"B1DA",'1'&x"B1DB",'1'&x"B1DC",'1'&x"B1DD",'1'&x"B1DE",'1'&x"B1DF",
+--'1'&x"B1E0",'1'&x"B1E1",'1'&x"B1E2",'1'&x"B1E3",'1'&x"B1E4",'1'&x"B1E5",'1'&x"B1E6",'1'&x"B1E7",'1'&x"B1E8",'1'&x"B1E9",'1'&x"B1EA",'1'&x"B1EB",'1'&x"B1EC",'1'&x"B1ED",'1'&x"B1EE",'1'&x"B1EF",
+--'1'&x"B1F0",'1'&x"B1F1",'1'&x"B1F2",'1'&x"B1F3",'1'&x"B1F4",'1'&x"B1F5",'1'&x"B1F6",'1'&x"B1F7",'1'&x"B1F8",'1'&x"B1F9",'1'&x"B1FA",'1'&x"B1FB",'1'&x"B1FC",'1'&x"B1FD",'1'&x"B1FE",'1'&x"B1FF",
+--'1'&x"B200",'1'&x"B201",'1'&x"B202",'1'&x"B203",'1'&x"B204",'1'&x"B205",'1'&x"B206",'1'&x"B207",'1'&x"B208",'1'&x"B209",'1'&x"B20A",'1'&x"B20B",'1'&x"B20C",'1'&x"B20D",'1'&x"B20E",'1'&x"B20F",
+--'1'&x"B210",'1'&x"B211",'1'&x"B212",'1'&x"B213",'1'&x"B214",'1'&x"B215",'1'&x"B216",'1'&x"B217",'1'&x"B218",'1'&x"B219",'1'&x"B21A",'1'&x"B21B",'1'&x"B21C",'1'&x"B21D",'1'&x"B21E",'1'&x"B21F",
+--'1'&x"B220",'1'&x"B221",'1'&x"B222",'1'&x"B223",'1'&x"B224",'1'&x"B225",'1'&x"B226",'1'&x"B227",'1'&x"B228",'1'&x"B229",'1'&x"B22A",'1'&x"B22B",'1'&x"B22C",'1'&x"B22D",'1'&x"B22E",'1'&x"B22F",
+--'1'&x"B230",'1'&x"B231",'1'&x"B232",'1'&x"B233",'1'&x"B234",'1'&x"B235",'1'&x"B236",'1'&x"B237",'1'&x"B238",'1'&x"B239",'1'&x"B23A",'1'&x"B23B",'1'&x"B23C",'1'&x"B23D",'1'&x"B23E",'1'&x"B23F",
+--'1'&x"B240",'1'&x"B241",'1'&x"B242",'1'&x"B243",'1'&x"B244",'1'&x"B245",'1'&x"B246",'1'&x"B247",'1'&x"B248",'1'&x"B249",'1'&x"B24A",'1'&x"B24B",'1'&x"B24C",'1'&x"B24D",'1'&x"B24E",'1'&x"B24F",
+--'1'&x"B250",'1'&x"B251",'1'&x"B252",'1'&x"B253",'1'&x"B254",'1'&x"B255",'1'&x"B256",'1'&x"B257",'1'&x"B258",'1'&x"B259",'1'&x"B25A",'1'&x"B25B",'1'&x"B25C",'1'&x"B25D",'1'&x"B25E",'1'&x"B25F",
+--'1'&x"B260",'1'&x"B261",'1'&x"B262",'1'&x"B263",'1'&x"B264",'1'&x"B265",'1'&x"B266",'1'&x"B267",'1'&x"B268",'1'&x"B269",'1'&x"B26A",'1'&x"B26B",'1'&x"B26C",'1'&x"B26D",'1'&x"B26E",'1'&x"B26F",
+--'1'&x"B270",'1'&x"B271",'1'&x"B272",'1'&x"B273",'1'&x"B274",'1'&x"B275",'1'&x"B276",'1'&x"B277",'1'&x"B278",'1'&x"B279",'1'&x"B27A",'1'&x"B27B",'1'&x"B27C",'1'&x"B27D",'1'&x"B27E",'1'&x"B27F",
+--'1'&x"B280",'1'&x"B281",'1'&x"B282",'1'&x"B283",'1'&x"B284",'1'&x"B285",'1'&x"B286",'1'&x"B287",'1'&x"B288",'1'&x"B289",'1'&x"B28A",'1'&x"B28B",'1'&x"B28C",'1'&x"B28D",'1'&x"B28E",'1'&x"B28F",
+--'1'&x"B290",'1'&x"B291",'1'&x"B292",'1'&x"B293",'1'&x"B294",'1'&x"B295",'1'&x"B296",'1'&x"B297",'1'&x"B298",'1'&x"B299",'1'&x"B29A",'1'&x"B29B",'1'&x"B29C",'1'&x"B29D",'1'&x"B29E",'1'&x"B29F",
+--'1'&x"B2A0",'1'&x"B2A1",'1'&x"B2A2",'1'&x"B2A3",'1'&x"B2A4",'1'&x"B2A5",'1'&x"B2A6",'1'&x"B2A7",'1'&x"B2A8",'1'&x"B2A9",'1'&x"B2AA",'1'&x"B2AB",'1'&x"B2AC",'1'&x"B2AD",'1'&x"B2AE",'1'&x"B2AF",
+--'1'&x"B2B0",'1'&x"B2B1",'1'&x"B2B2",'1'&x"B2B3",'1'&x"B2B4",'1'&x"B2B5",'1'&x"B2B6",'1'&x"B2B7",'1'&x"B2B8",'1'&x"B2B9",'1'&x"B2BA",'1'&x"B2BB",'1'&x"B2BC",'1'&x"B2BD",'1'&x"B2BE",'1'&x"B2BF",
+--'1'&x"B2C0",'1'&x"B2C1",'1'&x"B2C2",'1'&x"B2C3",'1'&x"B2C4",'1'&x"B2C5",'1'&x"B2C6",'1'&x"B2C7",'1'&x"B2C8",'1'&x"B2C9",'1'&x"B2CA",'1'&x"B2CB",'1'&x"B2CC",'1'&x"B2CD",'1'&x"B2CE",'1'&x"B2CF",
+--'1'&x"B2D0",'1'&x"B2D1",'1'&x"B2D2",'1'&x"B2D3",'1'&x"B2D4",'1'&x"B2D5",'1'&x"B2D6",'1'&x"B2D7",'1'&x"B2D8",'1'&x"B2D9",'1'&x"B2DA",'1'&x"B2DB",'1'&x"B2DC",'1'&x"B2DD",'1'&x"B2DE",'1'&x"B2DF",
+--'1'&x"B2E0",'1'&x"B2E1",'1'&x"B2E2",'1'&x"B2E3",'1'&x"B2E4",'1'&x"B2E5",'1'&x"B2E6",'1'&x"B2E7",'1'&x"B2E8",'1'&x"B2E9",'1'&x"B2EA",'1'&x"B2EB",'1'&x"B2EC",'1'&x"B2ED",'1'&x"B2EE",'1'&x"B2EF",
+--'1'&x"B2F0",'1'&x"B2F1",'1'&x"B2F2",'1'&x"B2F3",'1'&x"B2F4",'1'&x"B2F5",'1'&x"B2F6",'1'&x"B2F7",'1'&x"B2F8",'1'&x"B2F9",'1'&x"B2FA",'1'&x"B2FB",'1'&x"B2FC",'1'&x"B2FD",'1'&x"B2FE",'1'&x"B2FF",
+--'1'&x"B300",'1'&x"B301",'1'&x"B302",'1'&x"B303",'1'&x"B304",'1'&x"B305",'1'&x"B306",'1'&x"B307",'1'&x"B308",'1'&x"B309",'1'&x"B30A",'1'&x"B30B",'1'&x"B30C",'1'&x"B30D",'1'&x"B30E",'1'&x"B30F",
+--'1'&x"B310",'1'&x"B311",'1'&x"B312",'1'&x"B313",'1'&x"B314",'1'&x"B315",'1'&x"B316",'1'&x"B317",'1'&x"B318",'1'&x"B319",'1'&x"B31A",'1'&x"B31B",'1'&x"B31C",'1'&x"B31D",'1'&x"B31E",'1'&x"B31F",
+--'1'&x"B320",'1'&x"B321",'1'&x"B322",'1'&x"B323",'1'&x"B324",'1'&x"B325",'1'&x"B326",'1'&x"B327",'1'&x"B328",'1'&x"B329",'1'&x"B32A",'1'&x"B32B",'1'&x"B32C",'1'&x"B32D",'1'&x"B32E",'1'&x"B32F",
+--'1'&x"B330",'1'&x"B331",'1'&x"B332",'1'&x"B333",'1'&x"B334",'1'&x"B335",'1'&x"B336",'1'&x"B337",'1'&x"B338",'1'&x"B339",'1'&x"B33A",'1'&x"B33B",'1'&x"B33C",'1'&x"B33D",'1'&x"B33E",'1'&x"B33F",
+--'1'&x"B340",'1'&x"B341",'1'&x"B342",'1'&x"B343",'1'&x"B344",'1'&x"B345",'1'&x"B346",'1'&x"B347",'1'&x"B348",'1'&x"B349",'1'&x"B34A",'1'&x"B34B",'1'&x"B34C",'1'&x"B34D",'1'&x"B34E",'1'&x"B34F",
+--'1'&x"B350",'1'&x"B351",'1'&x"B352",'1'&x"B353",'1'&x"B354",'1'&x"B355",'1'&x"B356",'1'&x"B357",'1'&x"B358",'1'&x"B359",'1'&x"B35A",'1'&x"B35B",'1'&x"B35C",'1'&x"B35D",'1'&x"B35E",'1'&x"B35F",
+--'1'&x"B360",'1'&x"B361",'1'&x"B362",'1'&x"B363",'1'&x"B364",'1'&x"B365",'1'&x"B366",'1'&x"B367",'1'&x"B368",'1'&x"B369",'1'&x"B36A",'1'&x"B36B",'1'&x"B36C",'1'&x"B36D",'1'&x"B36E",'1'&x"B36F",
+--'1'&x"B370",'1'&x"B371",'1'&x"B372",'1'&x"B373",'1'&x"B374",'1'&x"B375",'1'&x"B376",'1'&x"B377",'1'&x"B378",'1'&x"B379",'1'&x"B37A",'1'&x"B37B",'1'&x"B37C",'1'&x"B37D",'1'&x"B37E",'1'&x"B37F",
+--'1'&x"B380",'1'&x"B381",'1'&x"B382",'1'&x"B383",'1'&x"B384",'1'&x"B385",'1'&x"B386",'1'&x"B387",'1'&x"B388",'1'&x"B389",'1'&x"B38A",'1'&x"B38B",'1'&x"B38C",'1'&x"B38D",'1'&x"B38E",'1'&x"B38F",
+--'1'&x"B390",'1'&x"B391",'1'&x"B392",'1'&x"B393",'1'&x"B394",'1'&x"B395",'1'&x"B396",'1'&x"B397",'1'&x"B398",'1'&x"B399",'1'&x"B39A",'1'&x"B39B",'1'&x"B39C",'1'&x"B39D",'1'&x"B39E",'1'&x"B39F",
+--'1'&x"B3A0",'1'&x"B3A1",'1'&x"B3A2",'1'&x"B3A3",'1'&x"B3A4",'1'&x"B3A5",'1'&x"B3A6",'1'&x"B3A7",'1'&x"B3A8",'1'&x"B3A9",'1'&x"B3AA",'1'&x"B3AB",'1'&x"B3AC",'1'&x"B3AD",'1'&x"B3AE",'1'&x"B3AF",
+--'1'&x"B3B0",'1'&x"B3B1",'1'&x"B3B2",'1'&x"B3B3",'1'&x"B3B4",'1'&x"B3B5",'1'&x"B3B6",'1'&x"B3B7",'1'&x"B3B8",'1'&x"B3B9",'1'&x"B3BA",'1'&x"B3BB",'1'&x"B3BC",'1'&x"B3BD",'1'&x"B3BE",'1'&x"B3BF",
+--'1'&x"B3C0",'1'&x"B3C1",'1'&x"B3C2",'1'&x"B3C3",'1'&x"B3C4",'1'&x"B3C5",'1'&x"B3C6",'1'&x"B3C7",'1'&x"B3C8",'1'&x"B3C9",'1'&x"B3CA",'1'&x"B3CB",'1'&x"B3CC",'1'&x"B3CD",'1'&x"B3CE",'1'&x"B3CF",
+--'1'&x"B3D0",'1'&x"B3D1",'1'&x"B3D2",'1'&x"B3D3",'1'&x"B3D4",'1'&x"B3D5",'1'&x"B3D6",'1'&x"B3D7",'1'&x"B3D8",'1'&x"B3D9",'1'&x"B3DA",'1'&x"B3DB",'1'&x"B3DC",'1'&x"B3DD",'1'&x"B3DE",'1'&x"B3DF",
+--'1'&x"B3E0",'1'&x"B3E1",'1'&x"B3E2",'1'&x"B3E3",'1'&x"B3E4",'1'&x"B3E5",'1'&x"B3E6",'1'&x"B3E7",'1'&x"B3E8",'1'&x"B3E9",'1'&x"B3EA",'1'&x"B3EB",'1'&x"B3EC",'1'&x"B3ED",'1'&x"B3EE",'1'&x"B3EF",
+--'1'&x"B3F0",'1'&x"B3F1",'1'&x"B3F2",'1'&x"B3F3",'1'&x"B3F4",'1'&x"B3F5",'1'&x"B3F6",'1'&x"B3F7",'1'&x"B3F8",'1'&x"B3F9",'1'&x"B3FA",'1'&x"B3FB",'1'&x"B3FC",'1'&x"B3FD",'1'&x"B3FE",'1'&x"B3FF",
+--'1'&x"B400",'1'&x"B401",'1'&x"B402",'1'&x"B403",'1'&x"B404",'1'&x"B405",'1'&x"B406",'1'&x"B407",'1'&x"B408",'1'&x"B409",'1'&x"B40A",'1'&x"B40B",'1'&x"B40C",'1'&x"B40D",'1'&x"B40E",'1'&x"B40F",
+--'1'&x"B410",'1'&x"B411",'1'&x"B412",'1'&x"B413",'1'&x"B414",'1'&x"B415",'1'&x"B416",'1'&x"B417",'1'&x"B418",'1'&x"B419",'1'&x"B41A",'1'&x"B41B",'1'&x"B41C",'1'&x"B41D",'1'&x"B41E",'1'&x"B41F",
+--'1'&x"B420",'1'&x"B421",'1'&x"B422",'1'&x"B423",'1'&x"B424",'1'&x"B425",'1'&x"B426",'1'&x"B427",'1'&x"B428",'1'&x"B429",'1'&x"B42A",'1'&x"B42B",'1'&x"B42C",'1'&x"B42D",'1'&x"B42E",'1'&x"B42F",
+--'1'&x"B430",'1'&x"B431",'1'&x"B432",'1'&x"B433",'1'&x"B434",'1'&x"B435",'1'&x"B436",'1'&x"B437",'1'&x"B438",'1'&x"B439",'1'&x"B43A",'1'&x"B43B",'1'&x"B43C",'1'&x"B43D",'1'&x"B43E",'1'&x"B43F",
+--'1'&x"B440",'1'&x"B441",'1'&x"B442",'1'&x"B443",'1'&x"B444",'1'&x"B445",'1'&x"B446",'1'&x"B447",'1'&x"B448",'1'&x"B449",'1'&x"B44A",'1'&x"B44B",'1'&x"B44C",'1'&x"B44D",'1'&x"B44E",'1'&x"B44F",
+--'1'&x"B450",'1'&x"B451",'1'&x"B452",'1'&x"B453",'1'&x"B454",'1'&x"B455",'1'&x"B456",'1'&x"B457",'1'&x"B458",'1'&x"B459",'1'&x"B45A",'1'&x"B45B",'1'&x"B45C",'1'&x"B45D",'1'&x"B45E",'1'&x"B45F",
+--'1'&x"B460",'1'&x"B461",'1'&x"B462",'1'&x"B463",'1'&x"B464",'1'&x"B465",'1'&x"B466",'1'&x"B467",'1'&x"B468",'1'&x"B469",'1'&x"B46A",'1'&x"B46B",'1'&x"B46C",'1'&x"B46D",'1'&x"B46E",'1'&x"B46F",
+--'1'&x"B470",'1'&x"B471",'1'&x"B472",'1'&x"B473",'1'&x"B474",'1'&x"B475",'1'&x"B476",'1'&x"B477",'1'&x"B478",'1'&x"B479",'1'&x"B47A",'1'&x"B47B",'1'&x"B47C",'1'&x"B47D",'1'&x"B47E",'1'&x"B47F",
+--'1'&x"B480",'1'&x"B481",'1'&x"B482",'1'&x"B483",'1'&x"B484",'1'&x"B485",'1'&x"B486",'1'&x"B487",'1'&x"B488",'1'&x"B489",'1'&x"B48A",'1'&x"B48B",'1'&x"B48C",'1'&x"B48D",'1'&x"B48E",'1'&x"B48F",
+--'1'&x"B490",'1'&x"B491",'1'&x"B492",'1'&x"B493",'1'&x"B494",'1'&x"B495",'1'&x"B496",'1'&x"B497",'1'&x"B498",'1'&x"B499",'1'&x"B49A",'1'&x"B49B",'1'&x"B49C",'1'&x"B49D",'1'&x"B49E",'1'&x"B49F",
+--'1'&x"B4A0",'1'&x"B4A1",'1'&x"B4A2",'1'&x"B4A3",'1'&x"B4A4",'1'&x"B4A5",'1'&x"B4A6",'1'&x"B4A7",'1'&x"B4A8",'1'&x"B4A9",'1'&x"B4AA",'1'&x"B4AB",'1'&x"B4AC",'1'&x"B4AD",'1'&x"B4AE",'1'&x"B4AF",
+--'1'&x"B4B0",'1'&x"B4B1",'1'&x"B4B2",'1'&x"B4B3",'1'&x"B4B4",'1'&x"B4B5",'1'&x"B4B6",'1'&x"B4B7",'1'&x"B4B8",'1'&x"B4B9",'1'&x"B4BA",'1'&x"B4BB",'1'&x"B4BC",'1'&x"B4BD",'1'&x"B4BE",'1'&x"B4BF",
+--'1'&x"B4C0",'1'&x"B4C1",'1'&x"B4C2",'1'&x"B4C3",'1'&x"B4C4",'1'&x"B4C5",'1'&x"B4C6",'1'&x"B4C7",'1'&x"B4C8",'1'&x"B4C9",'1'&x"B4CA",'1'&x"B4CB",'1'&x"B4CC",'1'&x"B4CD",'1'&x"B4CE",'1'&x"B4CF",
+--'1'&x"B4D0",'1'&x"B4D1",'1'&x"B4D2",'1'&x"B4D3",'1'&x"B4D4",'1'&x"B4D5",'1'&x"B4D6",'1'&x"B4D7",'1'&x"B4D8",'1'&x"B4D9",'1'&x"B4DA",'1'&x"B4DB",'1'&x"B4DC",'1'&x"B4DD",'1'&x"B4DE",'1'&x"B4DF",
+--'1'&x"B4E0",'1'&x"B4E1",'1'&x"B4E2",'1'&x"B4E3",'1'&x"B4E4",'1'&x"B4E5",'1'&x"B4E6",'1'&x"B4E7",'1'&x"B4E8",'1'&x"B4E9",'1'&x"B4EA",'1'&x"B4EB",'1'&x"B4EC",'1'&x"B4ED",'1'&x"B4EE",'1'&x"B4EF",
+--'1'&x"B4F0",'1'&x"B4F1",'1'&x"B4F2",'1'&x"B4F3",'1'&x"B4F4",'1'&x"B4F5",'1'&x"B4F6",'1'&x"B4F7",'1'&x"B4F8",'1'&x"B4F9",'1'&x"B4FA",'1'&x"B4FB",'1'&x"B4FC",'1'&x"B4FD",'1'&x"B4FE",'1'&x"B4FF",
+--'1'&x"B500",'1'&x"B501",'1'&x"B502",'1'&x"B503",'1'&x"B504",'1'&x"B505",'1'&x"B506",'1'&x"B507",'1'&x"B508",'1'&x"B509",'1'&x"B50A",'1'&x"B50B",'1'&x"B50C",'1'&x"B50D",'1'&x"B50E",'1'&x"B50F",
+--'1'&x"B510",'1'&x"B511",'1'&x"B512",'1'&x"B513",'1'&x"B514",'1'&x"B515",'1'&x"B516",'1'&x"B517",'1'&x"B518",'1'&x"B519",'1'&x"B51A",'1'&x"B51B",'1'&x"B51C",'1'&x"B51D",'1'&x"B51E",'1'&x"B51F",
+--'1'&x"B520",'1'&x"B521",'1'&x"B522",'1'&x"B523",'1'&x"B524",'1'&x"B525",'1'&x"B526",'1'&x"B527",'1'&x"B528",'1'&x"B529",'1'&x"B52A",'1'&x"B52B",'1'&x"B52C",'1'&x"B52D",'1'&x"B52E",'1'&x"B52F",
+--'1'&x"B530",'1'&x"B531",'1'&x"B532",'1'&x"B533",'1'&x"B534",'1'&x"B535",'1'&x"B536",'1'&x"B537",'1'&x"B538",'1'&x"B539",'1'&x"B53A",'1'&x"B53B",'1'&x"B53C",'1'&x"B53D",'1'&x"B53E",'1'&x"B53F",
+--'1'&x"B540",'1'&x"B541",'1'&x"B542",'1'&x"B543",'1'&x"B544",'1'&x"B545",'1'&x"B546",'1'&x"B547",'1'&x"B548",'1'&x"B549",'1'&x"B54A",'1'&x"B54B",'1'&x"B54C",'1'&x"B54D",'1'&x"B54E",'1'&x"B54F",
+--'1'&x"B550",'1'&x"B551",'1'&x"B552",'1'&x"B553",'1'&x"B554",'1'&x"B555",'1'&x"B556",'1'&x"B557",'1'&x"B558",'1'&x"B559",'1'&x"B55A",'1'&x"B55B",'1'&x"B55C",'1'&x"B55D",'1'&x"B55E",'1'&x"B55F",
+--'1'&x"B560",'1'&x"B561",'1'&x"B562",'1'&x"B563",'1'&x"B564",'1'&x"B565",'1'&x"B566",'1'&x"B567",'1'&x"B568",'1'&x"B569",'1'&x"B56A",'1'&x"B56B",'1'&x"B56C",'1'&x"B56D",'1'&x"B56E",'1'&x"B56F",
+--'1'&x"B570",'1'&x"B571",'1'&x"B572",'1'&x"B573",'1'&x"B574",'1'&x"B575",'1'&x"B576",'1'&x"B577",'1'&x"B578",'1'&x"B579",'1'&x"B57A",'1'&x"B57B",'1'&x"B57C",'1'&x"B57D",'1'&x"B57E",'1'&x"B57F",
+--'1'&x"B580",'1'&x"B581",'1'&x"B582",'1'&x"B583",'1'&x"B584",'1'&x"B585",'1'&x"B586",'1'&x"B587",'1'&x"B588",'1'&x"B589",'1'&x"B58A",'1'&x"B58B",'1'&x"B58C",'1'&x"B58D",'1'&x"B58E",'1'&x"B58F",
+--'1'&x"B590",'1'&x"B591",'1'&x"B592",'1'&x"B593",'1'&x"B594",'1'&x"B595",'1'&x"B596",'1'&x"B597",'1'&x"B598",'1'&x"B599",'1'&x"B59A",'1'&x"B59B",'1'&x"B59C",'1'&x"B59D",'1'&x"B59E",'1'&x"B59F",
+--'1'&x"B5A0",'1'&x"B5A1",'1'&x"B5A2",'1'&x"B5A3",'1'&x"B5A4",'1'&x"B5A5",'1'&x"B5A6",'1'&x"B5A7",'1'&x"B5A8",'1'&x"B5A9",'1'&x"B5AA",'1'&x"B5AB",'1'&x"B5AC",'1'&x"B5AD",'1'&x"B5AE",'1'&x"B5AF",
+--'1'&x"B5B0",'1'&x"B5B1",'1'&x"B5B2",'1'&x"B5B3",'1'&x"B5B4",'1'&x"B5B5",'1'&x"B5B6",'1'&x"B5B7",'1'&x"B5B8",'1'&x"B5B9",'1'&x"B5BA",'1'&x"B5BB",'1'&x"B5BC",'1'&x"B5BD",'1'&x"B5BE",'1'&x"B5BF",
+--'1'&x"B5C0",'1'&x"B5C1",'1'&x"B5C2",'1'&x"B5C3",'1'&x"B5C4",'1'&x"B5C5",'1'&x"B5C6",'1'&x"B5C7",'1'&x"B5C8",'1'&x"B5C9",'1'&x"B5CA",'1'&x"B5CB",'1'&x"B5CC",'1'&x"B5CD",'1'&x"B5CE",'1'&x"B5CF",
+--'1'&x"B5D0",'1'&x"B5D1",'1'&x"B5D2",'1'&x"B5D3",'1'&x"B5D4",'1'&x"B5D5",'1'&x"B5D6",'1'&x"B5D7",'1'&x"B5D8",'1'&x"B5D9",'1'&x"B5DA",'1'&x"B5DB",'1'&x"B5DC",'1'&x"B5DD",'1'&x"B5DE",'1'&x"B5DF",
+--'1'&x"B5E0",'1'&x"B5E1",'1'&x"B5E2",'1'&x"B5E3",'1'&x"B5E4",'1'&x"B5E5",'1'&x"B5E6",'1'&x"B5E7",'1'&x"B5E8",'1'&x"B5E9",'1'&x"B5EA",'1'&x"B5EB",'1'&x"B5EC",'1'&x"B5ED",'1'&x"B5EE",'1'&x"B5EF",
+--'1'&x"B5F0",'1'&x"B5F1",'1'&x"B5F2",'1'&x"B5F3",'1'&x"B5F4",'1'&x"B5F5",'1'&x"B5F6",'1'&x"B5F7",'1'&x"B5F8",'1'&x"B5F9",'1'&x"B5FA",'1'&x"B5FB",'1'&x"B5FC",'1'&x"B5FD",'1'&x"B5FE",'1'&x"B5FF",
+--'1'&x"B600",'1'&x"B601",'1'&x"B602",'1'&x"B603",'1'&x"B604",'1'&x"B605",'1'&x"B606",'1'&x"B607",'1'&x"B608",'1'&x"B609",'1'&x"B60A",'1'&x"B60B",'1'&x"B60C",'1'&x"B60D",'1'&x"B60E",'1'&x"B60F",
+--'1'&x"B610",'1'&x"B611",'1'&x"B612",'1'&x"B613",'1'&x"B614",'1'&x"B615",'1'&x"B616",'1'&x"B617",'1'&x"B618",'1'&x"B619",'1'&x"B61A",'1'&x"B61B",'1'&x"B61C",'1'&x"B61D",'1'&x"B61E",'1'&x"B61F",
+--'1'&x"B620",'1'&x"B621",'1'&x"B622",'1'&x"B623",'1'&x"B624",'1'&x"B625",'1'&x"B626",'1'&x"B627",'1'&x"B628",'1'&x"B629",'1'&x"B62A",'1'&x"B62B",'1'&x"B62C",'1'&x"B62D",'1'&x"B62E",'1'&x"B62F",
+--'1'&x"B630",'1'&x"B631",'1'&x"B632",'1'&x"B633",'1'&x"B634",'1'&x"B635",'1'&x"B636",'1'&x"B637",'1'&x"B638",'1'&x"B639",'1'&x"B63A",'1'&x"B63B",'1'&x"B63C",'1'&x"B63D",'1'&x"B63E",'1'&x"B63F",
+--'1'&x"B640",'1'&x"B641",'1'&x"B642",'1'&x"B643",'1'&x"B644",'1'&x"B645",'1'&x"B646",'1'&x"B647",'1'&x"B648",'1'&x"B649",'1'&x"B64A",'1'&x"B64B",'1'&x"B64C",'1'&x"B64D",'1'&x"B64E",'1'&x"B64F",
+--'1'&x"B650",'1'&x"B651",'1'&x"B652",'1'&x"B653",'1'&x"B654",'1'&x"B655",'1'&x"B656",'1'&x"B657",'1'&x"B658",'1'&x"B659",'1'&x"B65A",'1'&x"B65B",'1'&x"B65C",'1'&x"B65D",'1'&x"B65E",'1'&x"B65F",
+--'1'&x"B660",'1'&x"B661",'1'&x"B662",'1'&x"B663",'1'&x"B664",'1'&x"B665",'1'&x"B666",'1'&x"B667",'1'&x"B668",'1'&x"B669",'1'&x"B66A",'1'&x"B66B",'1'&x"B66C",'1'&x"B66D",'1'&x"B66E",'1'&x"B66F",
+--'1'&x"B670",'1'&x"B671",'1'&x"B672",'1'&x"B673",'1'&x"B674",'1'&x"B675",'1'&x"B676",'1'&x"B677",'1'&x"B678",'1'&x"B679",'1'&x"B67A",'1'&x"B67B",'1'&x"B67C",'1'&x"B67D",'1'&x"B67E",'1'&x"B67F",
+--'1'&x"B680",'1'&x"B681",'1'&x"B682",'1'&x"B683",'1'&x"B684",'1'&x"B685",'1'&x"B686",'1'&x"B687",'1'&x"B688",'1'&x"B689",'1'&x"B68A",'1'&x"B68B",'1'&x"B68C",'1'&x"B68D",'1'&x"B68E",'1'&x"B68F",
+--'1'&x"B690",'1'&x"B691",'1'&x"B692",'1'&x"B693",'1'&x"B694",'1'&x"B695",'1'&x"B696",'1'&x"B697",'1'&x"B698",'1'&x"B699",'1'&x"B69A",'1'&x"B69B",'1'&x"B69C",'1'&x"B69D",'1'&x"B69E",'1'&x"B69F",
+--'1'&x"B6A0",'1'&x"B6A1",'1'&x"B6A2",'1'&x"B6A3",'1'&x"B6A4",'1'&x"B6A5",'1'&x"B6A6",'1'&x"B6A7",'1'&x"B6A8",'1'&x"B6A9",'1'&x"B6AA",'1'&x"B6AB",'1'&x"B6AC",'1'&x"B6AD",'1'&x"B6AE",'1'&x"B6AF",
+--'1'&x"B6B0",'1'&x"B6B1",'1'&x"B6B2",'1'&x"B6B3",'1'&x"B6B4",'1'&x"B6B5",'1'&x"B6B6",'1'&x"B6B7",'1'&x"B6B8",'1'&x"B6B9",'1'&x"B6BA",'1'&x"B6BB",'1'&x"B6BC",'1'&x"B6BD",'1'&x"B6BE",'1'&x"B6BF",
+--'1'&x"B6C0",'1'&x"B6C1",'1'&x"B6C2",'1'&x"B6C3",'1'&x"B6C4",'1'&x"B6C5",'1'&x"B6C6",'1'&x"B6C7",'1'&x"B6C8",'1'&x"B6C9",'1'&x"B6CA",'1'&x"B6CB",'1'&x"B6CC",'1'&x"B6CD",'1'&x"B6CE",'1'&x"B6CF",
+--'1'&x"B6D0",'1'&x"B6D1",'1'&x"B6D2",'1'&x"B6D3",'1'&x"B6D4",'1'&x"B6D5",'1'&x"B6D6",'1'&x"B6D7",'1'&x"B6D8",'1'&x"B6D9",'1'&x"B6DA",'1'&x"B6DB",'1'&x"B6DC",'1'&x"B6DD",'1'&x"B6DE",'1'&x"B6DF",
+--'1'&x"B6E0",'1'&x"B6E1",'1'&x"B6E2",'1'&x"B6E3",'1'&x"B6E4",'1'&x"B6E5",'1'&x"B6E6",'1'&x"B6E7",'1'&x"B6E8",'1'&x"B6E9",'1'&x"B6EA",'1'&x"B6EB",'1'&x"B6EC",'1'&x"B6ED",'1'&x"B6EE",'1'&x"B6EF",
+--'1'&x"B6F0",'1'&x"B6F1",'1'&x"B6F2",'1'&x"B6F3",'1'&x"B6F4",'1'&x"B6F5",'1'&x"B6F6",'1'&x"B6F7",'1'&x"B6F8",'1'&x"B6F9",'1'&x"B6FA",'1'&x"B6FB",'1'&x"B6FC",'1'&x"B6FD",'1'&x"B6FE",'1'&x"B6FF",
+--'1'&x"B700",'1'&x"B701",'1'&x"B702",'1'&x"B703",'1'&x"B704",'1'&x"B705",'1'&x"B706",'1'&x"B707",'1'&x"B708",'1'&x"B709",'1'&x"B70A",'1'&x"B70B",'1'&x"B70C",'1'&x"B70D",'1'&x"B70E",'1'&x"B70F",
+--'1'&x"B710",'1'&x"B711",'1'&x"B712",'1'&x"B713",'1'&x"B714",'1'&x"B715",'1'&x"B716",'1'&x"B717",'1'&x"B718",'1'&x"B719",'1'&x"B71A",'1'&x"B71B",'1'&x"B71C",'1'&x"B71D",'1'&x"B71E",'1'&x"B71F",
+--'1'&x"B720",'1'&x"B721",'1'&x"B722",'1'&x"B723",'1'&x"B724",'1'&x"B725",'1'&x"B726",'1'&x"B727",'1'&x"B728",'1'&x"B729",'1'&x"B72A",'1'&x"B72B",'1'&x"B72C",'1'&x"B72D",'1'&x"B72E",'1'&x"B72F",
+--'1'&x"B730",'1'&x"B731",'1'&x"B732",'1'&x"B733",'1'&x"B734",'1'&x"B735",'1'&x"B736",'1'&x"B737",'1'&x"B738",'1'&x"B739",'1'&x"B73A",'1'&x"B73B",'1'&x"B73C",'1'&x"B73D",'1'&x"B73E",'1'&x"B73F",
+--'1'&x"B740",'1'&x"B741",'1'&x"B742",'1'&x"B743",'1'&x"B744",'1'&x"B745",'1'&x"B746",'1'&x"B747",'1'&x"B748",'1'&x"B749",'1'&x"B74A",'1'&x"B74B",'1'&x"B74C",'1'&x"B74D",'1'&x"B74E",'1'&x"B74F",
+--'1'&x"B750",'1'&x"B751",'1'&x"B752",'1'&x"B753",'1'&x"B754",'1'&x"B755",'1'&x"B756",'1'&x"B757",'1'&x"B758",'1'&x"B759",'1'&x"B75A",'1'&x"B75B",'1'&x"B75C",'1'&x"B75D",'1'&x"B75E",'1'&x"B75F",
+--'1'&x"B760",'1'&x"B761",'1'&x"B762",'1'&x"B763",'1'&x"B764",'1'&x"B765",'1'&x"B766",'1'&x"B767",'1'&x"B768",'1'&x"B769",'1'&x"B76A",'1'&x"B76B",'1'&x"B76C",'1'&x"B76D",'1'&x"B76E",'1'&x"B76F",
+--'1'&x"B770",'1'&x"B771",'1'&x"B772",'1'&x"B773",'1'&x"B774",'1'&x"B775",'1'&x"B776",'1'&x"B777",'1'&x"B778",'1'&x"B779",'1'&x"B77A",'1'&x"B77B",'1'&x"B77C",'1'&x"B77D",'1'&x"B77E",'1'&x"B77F",
+--'1'&x"B780",'1'&x"B781",'1'&x"B782",'1'&x"B783",'1'&x"B784",'1'&x"B785",'1'&x"B786",'1'&x"B787",'1'&x"B788",'1'&x"B789",'1'&x"B78A",'1'&x"B78B",'1'&x"B78C",'1'&x"B78D",'1'&x"B78E",'1'&x"B78F",
+--'1'&x"B790",'1'&x"B791",'1'&x"B792",'1'&x"B793",'1'&x"B794",'1'&x"B795",'1'&x"B796",'1'&x"B797",'1'&x"B798",'1'&x"B799",'1'&x"B79A",'1'&x"B79B",'1'&x"B79C",'1'&x"B79D",'1'&x"B79E",'1'&x"B79F",
+--'1'&x"B7A0",'1'&x"B7A1",'1'&x"B7A2",'1'&x"B7A3",'1'&x"B7A4",'1'&x"B7A5",'1'&x"B7A6",'1'&x"B7A7",'1'&x"B7A8",'1'&x"B7A9",'1'&x"B7AA",'1'&x"B7AB",'1'&x"B7AC",'1'&x"B7AD",'1'&x"B7AE",'1'&x"B7AF",
+--'1'&x"B7B0",'1'&x"B7B1",'1'&x"B7B2",'1'&x"B7B3",'1'&x"B7B4",'1'&x"B7B5",'1'&x"B7B6",'1'&x"B7B7",'1'&x"B7B8",'1'&x"B7B9",'1'&x"B7BA",'1'&x"B7BB",'1'&x"B7BC",'1'&x"B7BD",'1'&x"B7BE",'1'&x"B7BF",
+--'1'&x"B7C0",'1'&x"B7C1",'1'&x"B7C2",'1'&x"B7C3",'1'&x"B7C4",'1'&x"B7C5",'1'&x"B7C6",'1'&x"B7C7",'1'&x"B7C8",'1'&x"B7C9",'1'&x"B7CA",'1'&x"B7CB",'1'&x"B7CC",'1'&x"B7CD",'1'&x"B7CE",'1'&x"B7CF",
+--'1'&x"B7D0",'1'&x"B7D1",'1'&x"B7D2",'1'&x"B7D3",'1'&x"B7D4",'1'&x"B7D5",'1'&x"B7D6",'1'&x"B7D7",'1'&x"B7D8",'1'&x"B7D9",'1'&x"B7DA",'1'&x"B7DB",'1'&x"B7DC",'1'&x"B7DD",'1'&x"B7DE",'1'&x"B7DF",
+--'1'&x"B7E0",'1'&x"B7E1",'1'&x"B7E2",'1'&x"B7E3",'1'&x"B7E4",'1'&x"B7E5",'1'&x"B7E6",'1'&x"B7E7",'1'&x"B7E8",'1'&x"B7E9",'1'&x"B7EA",'1'&x"B7EB",'1'&x"B7EC",'1'&x"B7ED",'1'&x"B7EE",'1'&x"B7EF",
+--'1'&x"B7F0",'1'&x"B7F1",'1'&x"B7F2",'1'&x"B7F3",'1'&x"B7F4",'1'&x"B7F5",'1'&x"B7F6",'1'&x"B7F7",'1'&x"B7F8",'1'&x"B7F9",'1'&x"B7FA",'1'&x"B7FB",'1'&x"B7FC",'1'&x"B7FD",'1'&x"B7FE",'1'&x"B7FF",
+--'1'&x"B800",'1'&x"B801",'1'&x"B802",'1'&x"B803",'1'&x"B804",'1'&x"B805",'1'&x"B806",'1'&x"B807",'1'&x"B808",'1'&x"B809",'1'&x"B80A",'1'&x"B80B",'1'&x"B80C",'1'&x"B80D",'1'&x"B80E",'1'&x"B80F",
+--'1'&x"B810",'1'&x"B811",'1'&x"B812",'1'&x"B813",'1'&x"B814",'1'&x"B815",'1'&x"B816",'1'&x"B817",'1'&x"B818",'1'&x"B819",'1'&x"B81A",'1'&x"B81B",'1'&x"B81C",'1'&x"B81D",'1'&x"B81E",'1'&x"B81F",
+--'1'&x"B820",'1'&x"B821",'1'&x"B822",'1'&x"B823",'1'&x"B824",'1'&x"B825",'1'&x"B826",'1'&x"B827",'1'&x"B828",'1'&x"B829",'1'&x"B82A",'1'&x"B82B",'1'&x"B82C",'1'&x"B82D",'1'&x"B82E",'1'&x"B82F",
+--'1'&x"B830",'1'&x"B831",'1'&x"B832",'1'&x"B833",'1'&x"B834",'1'&x"B835",'1'&x"B836",'1'&x"B837",'1'&x"B838",'1'&x"B839",'1'&x"B83A",'1'&x"B83B",'1'&x"B83C",'1'&x"B83D",'1'&x"B83E",'1'&x"B83F",
+--'1'&x"B840",'1'&x"B841",'1'&x"B842",'1'&x"B843",'1'&x"B844",'1'&x"B845",'1'&x"B846",'1'&x"B847",'1'&x"B848",'1'&x"B849",'1'&x"B84A",'1'&x"B84B",'1'&x"B84C",'1'&x"B84D",'1'&x"B84E",'1'&x"B84F",
+--'1'&x"B850",'1'&x"B851",'1'&x"B852",'1'&x"B853",'1'&x"B854",'1'&x"B855",'1'&x"B856",'1'&x"B857",'1'&x"B858",'1'&x"B859",'1'&x"B85A",'1'&x"B85B",'1'&x"B85C",'1'&x"B85D",'1'&x"B85E",'1'&x"B85F",
+--'1'&x"B860",'1'&x"B861",'1'&x"B862",'1'&x"B863",'1'&x"B864",'1'&x"B865",'1'&x"B866",'1'&x"B867",'1'&x"B868",'1'&x"B869",'1'&x"B86A",'1'&x"B86B",'1'&x"B86C",'1'&x"B86D",'1'&x"B86E",'1'&x"B86F",
+--'1'&x"B870",'1'&x"B871",'1'&x"B872",'1'&x"B873",'1'&x"B874",'1'&x"B875",'1'&x"B876",'1'&x"B877",'1'&x"B878",'1'&x"B879",'1'&x"B87A",'1'&x"B87B",'1'&x"B87C",'1'&x"B87D",'1'&x"B87E",'1'&x"B87F",
+--'1'&x"B880",'1'&x"B881",'1'&x"B882",'1'&x"B883",'1'&x"B884",'1'&x"B885",'1'&x"B886",'1'&x"B887",'1'&x"B888",'1'&x"B889",'1'&x"B88A",'1'&x"B88B",'1'&x"B88C",'1'&x"B88D",'1'&x"B88E",'1'&x"B88F",
+--'1'&x"B890",'1'&x"B891",'1'&x"B892",'1'&x"B893",'1'&x"B894",'1'&x"B895",'1'&x"B896",'1'&x"B897",'1'&x"B898",'1'&x"B899",'1'&x"B89A",'1'&x"B89B",'1'&x"B89C",'1'&x"B89D",'1'&x"B89E",'1'&x"B89F",
+--'1'&x"B8A0",'1'&x"B8A1",'1'&x"B8A2",'1'&x"B8A3",'1'&x"B8A4",'1'&x"B8A5",'1'&x"B8A6",'1'&x"B8A7",'1'&x"B8A8",'1'&x"B8A9",'1'&x"B8AA",'1'&x"B8AB",'1'&x"B8AC",'1'&x"B8AD",'1'&x"B8AE",'1'&x"B8AF",
+--'1'&x"B8B0",'1'&x"B8B1",'1'&x"B8B2",'1'&x"B8B3",'1'&x"B8B4",'1'&x"B8B5",'1'&x"B8B6",'1'&x"B8B7",'1'&x"B8B8",'1'&x"B8B9",'1'&x"B8BA",'1'&x"B8BB",'1'&x"B8BC",'1'&x"B8BD",'1'&x"B8BE",'1'&x"B8BF",
+--'1'&x"B8C0",'1'&x"B8C1",'1'&x"B8C2",'1'&x"B8C3",'1'&x"B8C4",'1'&x"B8C5",'1'&x"B8C6",'1'&x"B8C7",'1'&x"B8C8",'1'&x"B8C9",'1'&x"B8CA",'1'&x"B8CB",'1'&x"B8CC",'1'&x"B8CD",'1'&x"B8CE",'1'&x"B8CF",
+--'1'&x"B8D0",'1'&x"B8D1",'1'&x"B8D2",'1'&x"B8D3",'1'&x"B8D4",'1'&x"B8D5",'1'&x"B8D6",'1'&x"B8D7",'1'&x"B8D8",'1'&x"B8D9",'1'&x"B8DA",'1'&x"B8DB",'1'&x"B8DC",'1'&x"B8DD",'1'&x"B8DE",'1'&x"B8DF",
+--'1'&x"B8E0",'1'&x"B8E1",'1'&x"B8E2",'1'&x"B8E3",'1'&x"B8E4",'1'&x"B8E5",'1'&x"B8E6",'1'&x"B8E7",'1'&x"B8E8",'1'&x"B8E9",'1'&x"B8EA",'1'&x"B8EB",'1'&x"B8EC",'1'&x"B8ED",'1'&x"B8EE",'1'&x"B8EF",
+--'1'&x"B8F0",'1'&x"B8F1",'1'&x"B8F2",'1'&x"B8F3",'1'&x"B8F4",'1'&x"B8F5",'1'&x"B8F6",'1'&x"B8F7",'1'&x"B8F8",'1'&x"B8F9",'1'&x"B8FA",'1'&x"B8FB",'1'&x"B8FC",'1'&x"B8FD",'1'&x"B8FE",'1'&x"B8FF",
+--'1'&x"B900",'1'&x"B901",'1'&x"B902",'1'&x"B903",'1'&x"B904",'1'&x"B905",'1'&x"B906",'1'&x"B907",'1'&x"B908",'1'&x"B909",'1'&x"B90A",'1'&x"B90B",'1'&x"B90C",'1'&x"B90D",'1'&x"B90E",'1'&x"B90F",
+--'1'&x"B910",'1'&x"B911",'1'&x"B912",'1'&x"B913",'1'&x"B914",'1'&x"B915",'1'&x"B916",'1'&x"B917",'1'&x"B918",'1'&x"B919",'1'&x"B91A",'1'&x"B91B",'1'&x"B91C",'1'&x"B91D",'1'&x"B91E",'1'&x"B91F",
+--'1'&x"B920",'1'&x"B921",'1'&x"B922",'1'&x"B923",'1'&x"B924",'1'&x"B925",'1'&x"B926",'1'&x"B927",'1'&x"B928",'1'&x"B929",'1'&x"B92A",'1'&x"B92B",'1'&x"B92C",'1'&x"B92D",'1'&x"B92E",'1'&x"B92F",
+--'1'&x"B930",'1'&x"B931",'1'&x"B932",'1'&x"B933",'1'&x"B934",'1'&x"B935",'1'&x"B936",'1'&x"B937",'1'&x"B938",'1'&x"B939",'1'&x"B93A",'1'&x"B93B",'1'&x"B93C",'1'&x"B93D",'1'&x"B93E",'1'&x"B93F",
+--'1'&x"B940",'1'&x"B941",'1'&x"B942",'1'&x"B943",'1'&x"B944",'1'&x"B945",'1'&x"B946",'1'&x"B947",'1'&x"B948",'1'&x"B949",'1'&x"B94A",'1'&x"B94B",'1'&x"B94C",'1'&x"B94D",'1'&x"B94E",'1'&x"B94F",
+--'1'&x"B950",'1'&x"B951",'1'&x"B952",'1'&x"B953",'1'&x"B954",'1'&x"B955",'1'&x"B956",'1'&x"B957",'1'&x"B958",'1'&x"B959",'1'&x"B95A",'1'&x"B95B",'1'&x"B95C",'1'&x"B95D",'1'&x"B95E",'1'&x"B95F",
+--'1'&x"B960",'1'&x"B961",'1'&x"B962",'1'&x"B963",'1'&x"B964",'1'&x"B965",'1'&x"B966",'1'&x"B967",'1'&x"B968",'1'&x"B969",'1'&x"B96A",'1'&x"B96B",'1'&x"B96C",'1'&x"B96D",'1'&x"B96E",'1'&x"B96F",
+--'1'&x"B970",'1'&x"B971",'1'&x"B972",'1'&x"B973",'1'&x"B974",'1'&x"B975",'1'&x"B976",'1'&x"B977",'1'&x"B978",'1'&x"B979",'1'&x"B97A",'1'&x"B97B",'1'&x"B97C",'1'&x"B97D",'1'&x"B97E",'1'&x"B97F",
+--'1'&x"B980",'1'&x"B981",'1'&x"B982",'1'&x"B983",'1'&x"B984",'1'&x"B985",'1'&x"B986",'1'&x"B987",'1'&x"B988",'1'&x"B989",'1'&x"B98A",'1'&x"B98B",'1'&x"B98C",'1'&x"B98D",'1'&x"B98E",'1'&x"B98F",
+--'1'&x"B990",'1'&x"B991",'1'&x"B992",'1'&x"B993",'1'&x"B994",'1'&x"B995",'1'&x"B996",'1'&x"B997",'1'&x"B998",'1'&x"B999",'1'&x"B99A",'1'&x"B99B",'1'&x"B99C",'1'&x"B99D",'1'&x"B99E",'1'&x"B99F",
+--'1'&x"B9A0",'1'&x"B9A1",'1'&x"B9A2",'1'&x"B9A3",'1'&x"B9A4",'1'&x"B9A5",'1'&x"B9A6",'1'&x"B9A7",'1'&x"B9A8",'1'&x"B9A9",'1'&x"B9AA",'1'&x"B9AB",'1'&x"B9AC",'1'&x"B9AD",'1'&x"B9AE",'1'&x"B9AF",
+--'1'&x"B9B0",'1'&x"B9B1",'1'&x"B9B2",'1'&x"B9B3",'1'&x"B9B4",'1'&x"B9B5",'1'&x"B9B6",'1'&x"B9B7",'1'&x"B9B8",'1'&x"B9B9",'1'&x"B9BA",'1'&x"B9BB",'1'&x"B9BC",'1'&x"B9BD",'1'&x"B9BE",'1'&x"B9BF",
+--'1'&x"B9C0",'1'&x"B9C1",'1'&x"B9C2",'1'&x"B9C3",'1'&x"B9C4",'1'&x"B9C5",'1'&x"B9C6",'1'&x"B9C7",'1'&x"B9C8",'1'&x"B9C9",'1'&x"B9CA",'1'&x"B9CB",'1'&x"B9CC",'1'&x"B9CD",'1'&x"B9CE",'1'&x"B9CF",
+--'1'&x"B9D0",'1'&x"B9D1",'1'&x"B9D2",'1'&x"B9D3",'1'&x"B9D4",'1'&x"B9D5",'1'&x"B9D6",'1'&x"B9D7",'1'&x"B9D8",'1'&x"B9D9",'1'&x"B9DA",'1'&x"B9DB",'1'&x"B9DC",'1'&x"B9DD",'1'&x"B9DE",'1'&x"B9DF",
+--'1'&x"B9E0",'1'&x"B9E1",'1'&x"B9E2",'1'&x"B9E3",'1'&x"B9E4",'1'&x"B9E5",'1'&x"B9E6",'1'&x"B9E7",'1'&x"B9E8",'1'&x"B9E9",'1'&x"B9EA",'1'&x"B9EB",'1'&x"B9EC",'1'&x"B9ED",'1'&x"B9EE",'1'&x"B9EF",
+--'1'&x"B9F0",'1'&x"B9F1",'1'&x"B9F2",'1'&x"B9F3",'1'&x"B9F4",'1'&x"B9F5",'1'&x"B9F6",'1'&x"B9F7",'1'&x"B9F8",'1'&x"B9F9",'1'&x"B9FA",'1'&x"B9FB",'1'&x"B9FC",'1'&x"B9FD",'1'&x"B9FE",'1'&x"B9FF",
+--'1'&x"BA00",'1'&x"BA01",'1'&x"BA02",'1'&x"BA03",'1'&x"BA04",'1'&x"BA05",'1'&x"BA06",'1'&x"BA07",'1'&x"BA08",'1'&x"BA09",'1'&x"BA0A",'1'&x"BA0B",'1'&x"BA0C",'1'&x"BA0D",'1'&x"BA0E",'1'&x"BA0F",
+--'1'&x"BA10",'1'&x"BA11",'1'&x"BA12",'1'&x"BA13",'1'&x"BA14",'1'&x"BA15",'1'&x"BA16",'1'&x"BA17",'1'&x"BA18",'1'&x"BA19",'1'&x"BA1A",'1'&x"BA1B",'1'&x"BA1C",'1'&x"BA1D",'1'&x"BA1E",'1'&x"BA1F",
+--'1'&x"BA20",'1'&x"BA21",'1'&x"BA22",'1'&x"BA23",'1'&x"BA24",'1'&x"BA25",'1'&x"BA26",'1'&x"BA27",'1'&x"BA28",'1'&x"BA29",'1'&x"BA2A",'1'&x"BA2B",'1'&x"BA2C",'1'&x"BA2D",'1'&x"BA2E",'1'&x"BA2F",
+--'1'&x"BA30",'1'&x"BA31",'1'&x"BA32",'1'&x"BA33",'1'&x"BA34",'1'&x"BA35",'1'&x"BA36",'1'&x"BA37",'1'&x"BA38",'1'&x"BA39",'1'&x"BA3A",'1'&x"BA3B",'1'&x"BA3C",'1'&x"BA3D",'1'&x"BA3E",'1'&x"BA3F",
+--'1'&x"BA40",'1'&x"BA41",'1'&x"BA42",'1'&x"BA43",'1'&x"BA44",'1'&x"BA45",'1'&x"BA46",'1'&x"BA47",'1'&x"BA48",'1'&x"BA49",'1'&x"BA4A",'1'&x"BA4B",'1'&x"BA4C",'1'&x"BA4D",'1'&x"BA4E",'1'&x"BA4F",
+--'1'&x"BA50",'1'&x"BA51",'1'&x"BA52",'1'&x"BA53",'1'&x"BA54",'1'&x"BA55",'1'&x"BA56",'1'&x"BA57",'1'&x"BA58",'1'&x"BA59",'1'&x"BA5A",'1'&x"BA5B",'1'&x"BA5C",'1'&x"BA5D",'1'&x"BA5E",'1'&x"BA5F",
+--'1'&x"BA60",'1'&x"BA61",'1'&x"BA62",'1'&x"BA63",'1'&x"BA64",'1'&x"BA65",'1'&x"BA66",'1'&x"BA67",'1'&x"BA68",'1'&x"BA69",'1'&x"BA6A",'1'&x"BA6B",'1'&x"BA6C",'1'&x"BA6D",'1'&x"BA6E",'1'&x"BA6F",
+--'1'&x"BA70",'1'&x"BA71",'1'&x"BA72",'1'&x"BA73",'1'&x"BA74",'1'&x"BA75",'1'&x"BA76",'1'&x"BA77",'1'&x"BA78",'1'&x"BA79",'1'&x"BA7A",'1'&x"BA7B",'1'&x"BA7C",'1'&x"BA7D",'1'&x"BA7E",'1'&x"BA7F",
+--'1'&x"BA80",'1'&x"BA81",'1'&x"BA82",'1'&x"BA83",'1'&x"BA84",'1'&x"BA85",'1'&x"BA86",'1'&x"BA87",'1'&x"BA88",'1'&x"BA89",'1'&x"BA8A",'1'&x"BA8B",'1'&x"BA8C",'1'&x"BA8D",'1'&x"BA8E",'1'&x"BA8F",
+--'1'&x"BA90",'1'&x"BA91",'1'&x"BA92",'1'&x"BA93",'1'&x"BA94",'1'&x"BA95",'1'&x"BA96",'1'&x"BA97",'1'&x"BA98",'1'&x"BA99",'1'&x"BA9A",'1'&x"BA9B",'1'&x"BA9C",'1'&x"BA9D",'1'&x"BA9E",'1'&x"BA9F",
+--'1'&x"BAA0",'1'&x"BAA1",'1'&x"BAA2",'1'&x"BAA3",'1'&x"BAA4",'1'&x"BAA5",'1'&x"BAA6",'1'&x"BAA7",'1'&x"BAA8",'1'&x"BAA9",'1'&x"BAAA",'1'&x"BAAB",'1'&x"BAAC",'1'&x"BAAD",'1'&x"BAAE",'1'&x"BAAF",
+--'1'&x"BAB0",'1'&x"BAB1",'1'&x"BAB2",'1'&x"BAB3",'1'&x"BAB4",'1'&x"BAB5",'1'&x"BAB6",'1'&x"BAB7",'1'&x"BAB8",'1'&x"BAB9",'1'&x"BABA",'1'&x"BABB",'1'&x"BABC",'1'&x"BABD",'1'&x"BABE",'1'&x"BABF",
+--'1'&x"BAC0",'1'&x"BAC1",'1'&x"BAC2",'1'&x"BAC3",'1'&x"BAC4",'1'&x"BAC5",'1'&x"BAC6",'1'&x"BAC7",'1'&x"BAC8",'1'&x"BAC9",'1'&x"BACA",'1'&x"BACB",'1'&x"BACC",'1'&x"BACD",'1'&x"BACE",'1'&x"BACF",
+--'1'&x"BAD0",'1'&x"BAD1",'1'&x"BAD2",'1'&x"BAD3",'1'&x"BAD4",'1'&x"BAD5",'1'&x"BAD6",'1'&x"BAD7",'1'&x"BAD8",'1'&x"BAD9",'1'&x"BADA",'1'&x"BADB",'1'&x"BADC",'1'&x"BADD",'1'&x"BADE",'1'&x"BADF",
+--'1'&x"BAE0",'1'&x"BAE1",'1'&x"BAE2",'1'&x"BAE3",'1'&x"BAE4",'1'&x"BAE5",'1'&x"BAE6",'1'&x"BAE7",'1'&x"BAE8",'1'&x"BAE9",'1'&x"BAEA",'1'&x"BAEB",'1'&x"BAEC",'1'&x"BAED",'1'&x"BAEE",'1'&x"BAEF",
+--'1'&x"BAF0",'1'&x"BAF1",'1'&x"BAF2",'1'&x"BAF3",'1'&x"BAF4",'1'&x"BAF5",'1'&x"BAF6",'1'&x"BAF7",'1'&x"BAF8",'1'&x"BAF9",'1'&x"BAFA",'1'&x"BAFB",'1'&x"BAFC",'1'&x"BAFD",'1'&x"BAFE",'1'&x"BAFF",
+--'1'&x"BB00",'1'&x"BB01",'1'&x"BB02",'1'&x"BB03",'1'&x"BB04",'1'&x"BB05",'1'&x"BB06",'1'&x"BB07",'1'&x"BB08",'1'&x"BB09",'1'&x"BB0A",'1'&x"BB0B",'1'&x"BB0C",'1'&x"BB0D",'1'&x"BB0E",'1'&x"BB0F",
+--'1'&x"BB10",'1'&x"BB11",'1'&x"BB12",'1'&x"BB13",'1'&x"BB14",'1'&x"BB15",'1'&x"BB16",'1'&x"BB17",'1'&x"BB18",'1'&x"BB19",'1'&x"BB1A",'1'&x"BB1B",'1'&x"BB1C",'1'&x"BB1D",'1'&x"BB1E",'1'&x"BB1F",
+--'1'&x"BB20",'1'&x"BB21",'1'&x"BB22",'1'&x"BB23",'1'&x"BB24",'1'&x"BB25",'1'&x"BB26",'1'&x"BB27",'1'&x"BB28",'1'&x"BB29",'1'&x"BB2A",'1'&x"BB2B",'1'&x"BB2C",'1'&x"BB2D",'1'&x"BB2E",'1'&x"BB2F",
+--'1'&x"BB30",'1'&x"BB31",'1'&x"BB32",'1'&x"BB33",'1'&x"BB34",'1'&x"BB35",'1'&x"BB36",'1'&x"BB37",'1'&x"BB38",'1'&x"BB39",'1'&x"BB3A",'1'&x"BB3B",'1'&x"BB3C",'1'&x"BB3D",'1'&x"BB3E",'1'&x"BB3F",
+--'1'&x"BB40",'1'&x"BB41",'1'&x"BB42",'1'&x"BB43",'1'&x"BB44",'1'&x"BB45",'1'&x"BB46",'1'&x"BB47",'1'&x"BB48",'1'&x"BB49",'1'&x"BB4A",'1'&x"BB4B",'1'&x"BB4C",'1'&x"BB4D",'1'&x"BB4E",'1'&x"BB4F",
+--'1'&x"BB50",'1'&x"BB51",'1'&x"BB52",'1'&x"BB53",'1'&x"BB54",'1'&x"BB55",'1'&x"BB56",'1'&x"BB57",'1'&x"BB58",'1'&x"BB59",'1'&x"BB5A",'1'&x"BB5B",'1'&x"BB5C",'1'&x"BB5D",'1'&x"BB5E",'1'&x"BB5F",
+--'1'&x"BB60",'1'&x"BB61",'1'&x"BB62",'1'&x"BB63",'1'&x"BB64",'1'&x"BB65",'1'&x"BB66",'1'&x"BB67",'1'&x"BB68",'1'&x"BB69",'1'&x"BB6A",'1'&x"BB6B",'1'&x"BB6C",'1'&x"BB6D",'1'&x"BB6E",'1'&x"BB6F",
+--'1'&x"BB70",'1'&x"BB71",'1'&x"BB72",'1'&x"BB73",'1'&x"BB74",'1'&x"BB75",'1'&x"BB76",'1'&x"BB77",'1'&x"BB78",'1'&x"BB79",'1'&x"BB7A",'1'&x"BB7B",'1'&x"BB7C",'1'&x"BB7D",'1'&x"BB7E",'1'&x"BB7F",
+--'1'&x"BB80",'1'&x"BB81",'1'&x"BB82",'1'&x"BB83",'1'&x"BB84",'1'&x"BB85",'1'&x"BB86",'1'&x"BB87",'1'&x"BB88",'1'&x"BB89",'1'&x"BB8A",'1'&x"BB8B",'1'&x"BB8C",'1'&x"BB8D",'1'&x"BB8E",'1'&x"BB8F",
+--'1'&x"BB90",'1'&x"BB91",'1'&x"BB92",'1'&x"BB93",'1'&x"BB94",'1'&x"BB95",'1'&x"BB96",'1'&x"BB97",'1'&x"BB98",'1'&x"BB99",'1'&x"BB9A",'1'&x"BB9B",'1'&x"BB9C",'1'&x"BB9D",'1'&x"BB9E",'1'&x"BB9F",
+--'1'&x"BBA0",'1'&x"BBA1",'1'&x"BBA2",'1'&x"BBA3",'1'&x"BBA4",'1'&x"BBA5",'1'&x"BBA6",'1'&x"BBA7",'1'&x"BBA8",'1'&x"BBA9",'1'&x"BBAA",'1'&x"BBAB",'1'&x"BBAC",'1'&x"BBAD",'1'&x"BBAE",'1'&x"BBAF",
+--'1'&x"BBB0",'1'&x"BBB1",'1'&x"BBB2",'1'&x"BBB3",'1'&x"BBB4",'1'&x"BBB5",'1'&x"BBB6",'1'&x"BBB7",'1'&x"BBB8",'1'&x"BBB9",'1'&x"BBBA",'1'&x"BBBB",'1'&x"BBBC",'1'&x"BBBD",'1'&x"BBBE",'1'&x"BBBF",
+--'1'&x"BBC0",'1'&x"BBC1",'1'&x"BBC2",'1'&x"BBC3",'1'&x"BBC4",'1'&x"BBC5",'1'&x"BBC6",'1'&x"BBC7",'1'&x"BBC8",'1'&x"BBC9",'1'&x"BBCA",'1'&x"BBCB",'1'&x"BBCC",'1'&x"BBCD",'1'&x"BBCE",'1'&x"BBCF",
+--'1'&x"BBD0",'1'&x"BBD1",'1'&x"BBD2",'1'&x"BBD3",'1'&x"BBD4",'1'&x"BBD5",'1'&x"BBD6",'1'&x"BBD7",'1'&x"BBD8",'1'&x"BBD9",'1'&x"BBDA",'1'&x"BBDB",'1'&x"BBDC",'1'&x"BBDD",'1'&x"BBDE",'1'&x"BBDF",
+--'1'&x"BBE0",'1'&x"BBE1",'1'&x"BBE2",'1'&x"BBE3",'1'&x"BBE4",'1'&x"BBE5",'1'&x"BBE6",'1'&x"BBE7",'1'&x"BBE8",'1'&x"BBE9",'1'&x"BBEA",'1'&x"BBEB",'1'&x"BBEC",'1'&x"BBED",'1'&x"BBEE",'1'&x"BBEF",
+--'1'&x"BBF0",'1'&x"BBF1",'1'&x"BBF2",'1'&x"BBF3",'1'&x"BBF4",'1'&x"BBF5",'1'&x"BBF6",'1'&x"BBF7",'1'&x"BBF8",'1'&x"BBF9",'1'&x"BBFA",'1'&x"BBFB",'1'&x"BBFC",'1'&x"BBFD",'1'&x"BBFE",'1'&x"BBFF",
+--'1'&x"BC00",'1'&x"BC01",'1'&x"BC02",'1'&x"BC03",'1'&x"BC04",'1'&x"BC05",'1'&x"BC06",'1'&x"BC07",'1'&x"BC08",'1'&x"BC09",'1'&x"BC0A",'1'&x"BC0B",'1'&x"BC0C",'1'&x"BC0D",'1'&x"BC0E",'1'&x"BC0F",
+--'1'&x"BC10",'1'&x"BC11",'1'&x"BC12",'1'&x"BC13",'1'&x"BC14",'1'&x"BC15",'1'&x"BC16",'1'&x"BC17",'1'&x"BC18",'1'&x"BC19",'1'&x"BC1A",'1'&x"BC1B",'1'&x"BC1C",'1'&x"BC1D",'1'&x"BC1E",'1'&x"BC1F",
+--'1'&x"BC20",'1'&x"BC21",'1'&x"BC22",'1'&x"BC23",'1'&x"BC24",'1'&x"BC25",'1'&x"BC26",'1'&x"BC27",'1'&x"BC28",'1'&x"BC29",'1'&x"BC2A",'1'&x"BC2B",'1'&x"BC2C",'1'&x"BC2D",'1'&x"BC2E",'1'&x"BC2F",
+--'1'&x"BC30",'1'&x"BC31",'1'&x"BC32",'1'&x"BC33",'1'&x"BC34",'1'&x"BC35",'1'&x"BC36",'1'&x"BC37",'1'&x"BC38",'1'&x"BC39",'1'&x"BC3A",'1'&x"BC3B",'1'&x"BC3C",'1'&x"BC3D",'1'&x"BC3E",'1'&x"BC3F",
+--'1'&x"BC40",'1'&x"BC41",'1'&x"BC42",'1'&x"BC43",'1'&x"BC44",'1'&x"BC45",'1'&x"BC46",'1'&x"BC47",'1'&x"BC48",'1'&x"BC49",'1'&x"BC4A",'1'&x"BC4B",'1'&x"BC4C",'1'&x"BC4D",'1'&x"BC4E",'1'&x"BC4F",
+--'1'&x"BC50",'1'&x"BC51",'1'&x"BC52",'1'&x"BC53",'1'&x"BC54",'1'&x"BC55",'1'&x"BC56",'1'&x"BC57",'1'&x"BC58",'1'&x"BC59",'1'&x"BC5A",'1'&x"BC5B",'1'&x"BC5C",'1'&x"BC5D",'1'&x"BC5E",'1'&x"BC5F",
+--'1'&x"BC60",'1'&x"BC61",'1'&x"BC62",'1'&x"BC63",'1'&x"BC64",'1'&x"BC65",'1'&x"BC66",'1'&x"BC67",'1'&x"BC68",'1'&x"BC69",'1'&x"BC6A",'1'&x"BC6B",'1'&x"BC6C",'1'&x"BC6D",'1'&x"BC6E",'1'&x"BC6F",
+--'1'&x"BC70",'1'&x"BC71",'1'&x"BC72",'1'&x"BC73",'1'&x"BC74",'1'&x"BC75",'1'&x"BC76",'1'&x"BC77",'1'&x"BC78",'1'&x"BC79",'1'&x"BC7A",'1'&x"BC7B",'1'&x"BC7C",'1'&x"BC7D",'1'&x"BC7E",'1'&x"BC7F",
+--'1'&x"BC80",'1'&x"BC81",'1'&x"BC82",'1'&x"BC83",'1'&x"BC84",'1'&x"BC85",'1'&x"BC86",'1'&x"BC87",'1'&x"BC88",'1'&x"BC89",'1'&x"BC8A",'1'&x"BC8B",'1'&x"BC8C",'1'&x"BC8D",'1'&x"BC8E",'1'&x"BC8F",
+--'1'&x"BC90",'1'&x"BC91",'1'&x"BC92",'1'&x"BC93",'1'&x"BC94",'1'&x"BC95",'1'&x"BC96",'1'&x"BC97",'1'&x"BC98",'1'&x"BC99",'1'&x"BC9A",'1'&x"BC9B",'1'&x"BC9C",'1'&x"BC9D",'1'&x"BC9E",'1'&x"BC9F",
+--'1'&x"BCA0",'1'&x"BCA1",'1'&x"BCA2",'1'&x"BCA3",'1'&x"BCA4",'1'&x"BCA5",'1'&x"BCA6",'1'&x"BCA7",'1'&x"BCA8",'1'&x"BCA9",'1'&x"BCAA",'1'&x"BCAB",'1'&x"BCAC",'1'&x"BCAD",'1'&x"BCAE",'1'&x"BCAF",
+--'1'&x"BCB0",'1'&x"BCB1",'1'&x"BCB2",'1'&x"BCB3",'1'&x"BCB4",'1'&x"BCB5",'1'&x"BCB6",'1'&x"BCB7",'1'&x"BCB8",'1'&x"BCB9",'1'&x"BCBA",'1'&x"BCBB",'1'&x"BCBC",'1'&x"BCBD",'1'&x"BCBE",'1'&x"BCBF",
+--'1'&x"BCC0",'1'&x"BCC1",'1'&x"BCC2",'1'&x"BCC3",'1'&x"BCC4",'1'&x"BCC5",'1'&x"BCC6",'1'&x"BCC7",'1'&x"BCC8",'1'&x"BCC9",'1'&x"BCCA",'1'&x"BCCB",'1'&x"BCCC",'1'&x"BCCD",'1'&x"BCCE",'1'&x"BCCF",
+--'1'&x"BCD0",'1'&x"BCD1",'1'&x"BCD2",'1'&x"BCD3",'1'&x"BCD4",'1'&x"BCD5",'1'&x"BCD6",'1'&x"BCD7",'1'&x"BCD8",'1'&x"BCD9",'1'&x"BCDA",'1'&x"BCDB",'1'&x"BCDC",'1'&x"BCDD",'1'&x"BCDE",'1'&x"BCDF",
+--'1'&x"BCE0",'1'&x"BCE1",'1'&x"BCE2",'1'&x"BCE3",'1'&x"BCE4",'1'&x"BCE5",'1'&x"BCE6",'1'&x"BCE7",'1'&x"BCE8",'1'&x"BCE9",'1'&x"BCEA",'1'&x"BCEB",'1'&x"BCEC",'1'&x"BCED",'1'&x"BCEE",'1'&x"BCEF",
+--'1'&x"BCF0",'1'&x"BCF1",'1'&x"BCF2",'1'&x"BCF3",'1'&x"BCF4",'1'&x"BCF5",'1'&x"BCF6",'1'&x"BCF7",'1'&x"BCF8",'1'&x"BCF9",'1'&x"BCFA",'1'&x"BCFB",'1'&x"BCFC",'1'&x"BCFD",'1'&x"BCFE",'1'&x"BCFF",
+--'1'&x"BD00",'1'&x"BD01",'1'&x"BD02",'1'&x"BD03",'1'&x"BD04",'1'&x"BD05",'1'&x"BD06",'1'&x"BD07",'1'&x"BD08",'1'&x"BD09",'1'&x"BD0A",'1'&x"BD0B",'1'&x"BD0C",'1'&x"BD0D",'1'&x"BD0E",'1'&x"BD0F",
+--'1'&x"BD10",'1'&x"BD11",'1'&x"BD12",'1'&x"BD13",'1'&x"BD14",'1'&x"BD15",'1'&x"BD16",'1'&x"BD17",'1'&x"BD18",'1'&x"BD19",'1'&x"BD1A",'1'&x"BD1B",'1'&x"BD1C",'1'&x"BD1D",'1'&x"BD1E",'1'&x"BD1F",
+--'1'&x"BD20",'1'&x"BD21",'1'&x"BD22",'1'&x"BD23",'1'&x"BD24",'1'&x"BD25",'1'&x"BD26",'1'&x"BD27",'1'&x"BD28",'1'&x"BD29",'1'&x"BD2A",'1'&x"BD2B",'1'&x"BD2C",'1'&x"BD2D",'1'&x"BD2E",'1'&x"BD2F",
+--'1'&x"BD30",'1'&x"BD31",'1'&x"BD32",'1'&x"BD33",'1'&x"BD34",'1'&x"BD35",'1'&x"BD36",'1'&x"BD37",'1'&x"BD38",'1'&x"BD39",'1'&x"BD3A",'1'&x"BD3B",'1'&x"BD3C",'1'&x"BD3D",'1'&x"BD3E",'1'&x"BD3F",
+--'1'&x"BD40",'1'&x"BD41",'1'&x"BD42",'1'&x"BD43",'1'&x"BD44",'1'&x"BD45",'1'&x"BD46",'1'&x"BD47",'1'&x"BD48",'1'&x"BD49",'1'&x"BD4A",'1'&x"BD4B",'1'&x"BD4C",'1'&x"BD4D",'1'&x"BD4E",'1'&x"BD4F",
+--'1'&x"BD50",'1'&x"BD51",'1'&x"BD52",'1'&x"BD53",'1'&x"BD54",'1'&x"BD55",'1'&x"BD56",'1'&x"BD57",'1'&x"BD58",'1'&x"BD59",'1'&x"BD5A",'1'&x"BD5B",'1'&x"BD5C",'1'&x"BD5D",'1'&x"BD5E",'1'&x"BD5F",
+--'1'&x"BD60",'1'&x"BD61",'1'&x"BD62",'1'&x"BD63",'1'&x"BD64",'1'&x"BD65",'1'&x"BD66",'1'&x"BD67",'1'&x"BD68",'1'&x"BD69",'1'&x"BD6A",'1'&x"BD6B",'1'&x"BD6C",'1'&x"BD6D",'1'&x"BD6E",'1'&x"BD6F",
+--'1'&x"BD70",'1'&x"BD71",'1'&x"BD72",'1'&x"BD73",'1'&x"BD74",'1'&x"BD75",'1'&x"BD76",'1'&x"BD77",'1'&x"BD78",'1'&x"BD79",'1'&x"BD7A",'1'&x"BD7B",'1'&x"BD7C",'1'&x"BD7D",'1'&x"BD7E",'1'&x"BD7F",
+--'1'&x"BD80",'1'&x"BD81",'1'&x"BD82",'1'&x"BD83",'1'&x"BD84",'1'&x"BD85",'1'&x"BD86",'1'&x"BD87",'1'&x"BD88",'1'&x"BD89",'1'&x"BD8A",'1'&x"BD8B",'1'&x"BD8C",'1'&x"BD8D",'1'&x"BD8E",'1'&x"BD8F",
+--'1'&x"BD90",'1'&x"BD91",'1'&x"BD92",'1'&x"BD93",'1'&x"BD94",'1'&x"BD95",'1'&x"BD96",'1'&x"BD97",'1'&x"BD98",'1'&x"BD99",'1'&x"BD9A",'1'&x"BD9B",'1'&x"BD9C",'1'&x"BD9D",'1'&x"BD9E",'1'&x"BD9F",
+--'1'&x"BDA0",'1'&x"BDA1",'1'&x"BDA2",'1'&x"BDA3",'1'&x"BDA4",'1'&x"BDA5",'1'&x"BDA6",'1'&x"BDA7",'1'&x"BDA8",'1'&x"BDA9",'1'&x"BDAA",'1'&x"BDAB",'1'&x"BDAC",'1'&x"BDAD",'1'&x"BDAE",'1'&x"BDAF",
+--'1'&x"BDB0",'1'&x"BDB1",'1'&x"BDB2",'1'&x"BDB3",'1'&x"BDB4",'1'&x"BDB5",'1'&x"BDB6",'1'&x"BDB7",'1'&x"BDB8",'1'&x"BDB9",'1'&x"BDBA",'1'&x"BDBB",'1'&x"BDBC",'1'&x"BDBD",'1'&x"BDBE",'1'&x"BDBF",
+--'1'&x"BDC0",'1'&x"BDC1",'1'&x"BDC2",'1'&x"BDC3",'1'&x"BDC4",'1'&x"BDC5",'1'&x"BDC6",'1'&x"BDC7",'1'&x"BDC8",'1'&x"BDC9",'1'&x"BDCA",'1'&x"BDCB",'1'&x"BDCC",'1'&x"BDCD",'1'&x"BDCE",'1'&x"BDCF",
+--'1'&x"BDD0",'1'&x"BDD1",'1'&x"BDD2",'1'&x"BDD3",'1'&x"BDD4",'1'&x"BDD5",'1'&x"BDD6",'1'&x"BDD7",'1'&x"BDD8",'1'&x"BDD9",'1'&x"BDDA",'1'&x"BDDB",'1'&x"BDDC",'1'&x"BDDD",'1'&x"BDDE",'1'&x"BDDF",
+--'1'&x"BDE0",'1'&x"BDE1",'1'&x"BDE2",'1'&x"BDE3",'1'&x"BDE4",'1'&x"BDE5",'1'&x"BDE6",'1'&x"BDE7",'1'&x"BDE8",'1'&x"BDE9",'1'&x"BDEA",'1'&x"BDEB",'1'&x"BDEC",'1'&x"BDED",'1'&x"BDEE",'1'&x"BDEF",
+--'1'&x"BDF0",'1'&x"BDF1",'1'&x"BDF2",'1'&x"BDF3",'1'&x"BDF4",'1'&x"BDF5",'1'&x"BDF6",'1'&x"BDF7",'1'&x"BDF8",'1'&x"BDF9",'1'&x"BDFA",'1'&x"BDFB",'1'&x"BDFC",'1'&x"BDFD",'1'&x"BDFE",'1'&x"BDFF",
+--'1'&x"BE00",'1'&x"BE01",'1'&x"BE02",'1'&x"BE03",'1'&x"BE04",'1'&x"BE05",'1'&x"BE06",'1'&x"BE07",'1'&x"BE08",'1'&x"BE09",'1'&x"BE0A",'1'&x"BE0B",'1'&x"BE0C",'1'&x"BE0D",'1'&x"BE0E",'1'&x"BE0F",
+--'1'&x"BE10",'1'&x"BE11",'1'&x"BE12",'1'&x"BE13",'1'&x"BE14",'1'&x"BE15",'1'&x"BE16",'1'&x"BE17",'1'&x"BE18",'1'&x"BE19",'1'&x"BE1A",'1'&x"BE1B",'1'&x"BE1C",'1'&x"BE1D",'1'&x"BE1E",'1'&x"BE1F",
+--'1'&x"BE20",'1'&x"BE21",'1'&x"BE22",'1'&x"BE23",'1'&x"BE24",'1'&x"BE25",'1'&x"BE26",'1'&x"BE27",'1'&x"BE28",'1'&x"BE29",'1'&x"BE2A",'1'&x"BE2B",'1'&x"BE2C",'1'&x"BE2D",'1'&x"BE2E",'1'&x"BE2F",
+--'1'&x"BE30",'1'&x"BE31",'1'&x"BE32",'1'&x"BE33",'1'&x"BE34",'1'&x"BE35",'1'&x"BE36",'1'&x"BE37",'1'&x"BE38",'1'&x"BE39",'1'&x"BE3A",'1'&x"BE3B",'1'&x"BE3C",'1'&x"BE3D",'1'&x"BE3E",'1'&x"BE3F",
+--'1'&x"BE40",'1'&x"BE41",'1'&x"BE42",'1'&x"BE43",'1'&x"BE44",'1'&x"BE45",'1'&x"BE46",'1'&x"BE47",'1'&x"BE48",'1'&x"BE49",'1'&x"BE4A",'1'&x"BE4B",'1'&x"BE4C",'1'&x"BE4D",'1'&x"BE4E",'1'&x"BE4F",
+--'1'&x"BE50",'1'&x"BE51",'1'&x"BE52",'1'&x"BE53",'1'&x"BE54",'1'&x"BE55",'1'&x"BE56",'1'&x"BE57",'1'&x"BE58",'1'&x"BE59",'1'&x"BE5A",'1'&x"BE5B",'1'&x"BE5C",'1'&x"BE5D",'1'&x"BE5E",'1'&x"BE5F",
+--'1'&x"BE60",'1'&x"BE61",'1'&x"BE62",'1'&x"BE63",'1'&x"BE64",'1'&x"BE65",'1'&x"BE66",'1'&x"BE67",'1'&x"BE68",'1'&x"BE69",'1'&x"BE6A",'1'&x"BE6B",'1'&x"BE6C",'1'&x"BE6D",'1'&x"BE6E",'1'&x"BE6F",
+--'1'&x"BE70",'1'&x"BE71",'1'&x"BE72",'1'&x"BE73",'1'&x"BE74",'1'&x"BE75",'1'&x"BE76",'1'&x"BE77",'1'&x"BE78",'1'&x"BE79",'1'&x"BE7A",'1'&x"BE7B",'1'&x"BE7C",'1'&x"BE7D",'1'&x"BE7E",'1'&x"BE7F",
+--'1'&x"BE80",'1'&x"BE81",'1'&x"BE82",'1'&x"BE83",'1'&x"BE84",'1'&x"BE85",'1'&x"BE86",'1'&x"BE87",'1'&x"BE88",'1'&x"BE89",'1'&x"BE8A",'1'&x"BE8B",'1'&x"BE8C",'1'&x"BE8D",'1'&x"BE8E",'1'&x"BE8F",
+--'1'&x"BE90",'1'&x"BE91",'1'&x"BE92",'1'&x"BE93",'1'&x"BE94",'1'&x"BE95",'1'&x"BE96",'1'&x"BE97",'1'&x"BE98",'1'&x"BE99",'1'&x"BE9A",'1'&x"BE9B",'1'&x"BE9C",'1'&x"BE9D",'1'&x"BE9E",'1'&x"BE9F",
+--'1'&x"BEA0",'1'&x"BEA1",'1'&x"BEA2",'1'&x"BEA3",'1'&x"BEA4",'1'&x"BEA5",'1'&x"BEA6",'1'&x"BEA7",'1'&x"BEA8",'1'&x"BEA9",'1'&x"BEAA",'1'&x"BEAB",'1'&x"BEAC",'1'&x"BEAD",'1'&x"BEAE",'1'&x"BEAF",
+--'1'&x"BEB0",'1'&x"BEB1",'1'&x"BEB2",'1'&x"BEB3",'1'&x"BEB4",'1'&x"BEB5",'1'&x"BEB6",'1'&x"BEB7",'1'&x"BEB8",'1'&x"BEB9",'1'&x"BEBA",'1'&x"BEBB",'1'&x"BEBC",'1'&x"BEBD",'1'&x"BEBE",'1'&x"BEBF",
+--'1'&x"BEC0",'1'&x"BEC1",'1'&x"BEC2",'1'&x"BEC3",'1'&x"BEC4",'1'&x"BEC5",'1'&x"BEC6",'1'&x"BEC7",'1'&x"BEC8",'1'&x"BEC9",'1'&x"BECA",'1'&x"BECB",'1'&x"BECC",'1'&x"BECD",'1'&x"BECE",'1'&x"BECF",
+--'1'&x"BED0",'1'&x"BED1",'1'&x"BED2",'1'&x"BED3",'1'&x"BED4",'1'&x"BED5",'1'&x"BED6",'1'&x"BED7",'1'&x"BED8",'1'&x"BED9",'1'&x"BEDA",'1'&x"BEDB",'1'&x"BEDC",'1'&x"BEDD",'1'&x"BEDE",'1'&x"BEDF",
+--'1'&x"BEE0",'1'&x"BEE1",'1'&x"BEE2",'1'&x"BEE3",'1'&x"BEE4",'1'&x"BEE5",'1'&x"BEE6",'1'&x"BEE7",'1'&x"BEE8",'1'&x"BEE9",'1'&x"BEEA",'1'&x"BEEB",'1'&x"BEEC",'1'&x"BEED",'1'&x"BEEE",'1'&x"BEEF",
+--'1'&x"BEF0",'1'&x"BEF1",'1'&x"BEF2",'1'&x"BEF3",'1'&x"BEF4",'1'&x"BEF5",'1'&x"BEF6",'1'&x"BEF7",'1'&x"BEF8",'1'&x"BEF9",'1'&x"BEFA",'1'&x"BEFB",'1'&x"BEFC",'1'&x"BEFD",'1'&x"BEFE",'1'&x"BEFF",
+--'1'&x"BF00",'1'&x"BF01",'1'&x"BF02",'1'&x"BF03",'1'&x"BF04",'1'&x"BF05",'1'&x"BF06",'1'&x"BF07",'1'&x"BF08",'1'&x"BF09",'1'&x"BF0A",'1'&x"BF0B",'1'&x"BF0C",'1'&x"BF0D",'1'&x"BF0E",'1'&x"BF0F",
+--'1'&x"BF10",'1'&x"BF11",'1'&x"BF12",'1'&x"BF13",'1'&x"BF14",'1'&x"BF15",'1'&x"BF16",'1'&x"BF17",'1'&x"BF18",'1'&x"BF19",'1'&x"BF1A",'1'&x"BF1B",'1'&x"BF1C",'1'&x"BF1D",'1'&x"BF1E",'1'&x"BF1F",
+--'1'&x"BF20",'1'&x"BF21",'1'&x"BF22",'1'&x"BF23",'1'&x"BF24",'1'&x"BF25",'1'&x"BF26",'1'&x"BF27",'1'&x"BF28",'1'&x"BF29",'1'&x"BF2A",'1'&x"BF2B",'1'&x"BF2C",'1'&x"BF2D",'1'&x"BF2E",'1'&x"BF2F",
+--'1'&x"BF30",'1'&x"BF31",'1'&x"BF32",'1'&x"BF33",'1'&x"BF34",'1'&x"BF35",'1'&x"BF36",'1'&x"BF37",'1'&x"BF38",'1'&x"BF39",'1'&x"BF3A",'1'&x"BF3B",'1'&x"BF3C",'1'&x"BF3D",'1'&x"BF3E",'1'&x"BF3F",
+--'1'&x"BF40",'1'&x"BF41",'1'&x"BF42",'1'&x"BF43",'1'&x"BF44",'1'&x"BF45",'1'&x"BF46",'1'&x"BF47",'1'&x"BF48",'1'&x"BF49",'1'&x"BF4A",'1'&x"BF4B",'1'&x"BF4C",'1'&x"BF4D",'1'&x"BF4E",'1'&x"BF4F",
+--'1'&x"BF50",'1'&x"BF51",'1'&x"BF52",'1'&x"BF53",'1'&x"BF54",'1'&x"BF55",'1'&x"BF56",'1'&x"BF57",'1'&x"BF58",'1'&x"BF59",'1'&x"BF5A",'1'&x"BF5B",'1'&x"BF5C",'1'&x"BF5D",'1'&x"BF5E",'1'&x"BF5F",
+--'1'&x"BF60",'1'&x"BF61",'1'&x"BF62",'1'&x"BF63",'1'&x"BF64",'1'&x"BF65",'1'&x"BF66",'1'&x"BF67",'1'&x"BF68",'1'&x"BF69",'1'&x"BF6A",'1'&x"BF6B",'1'&x"BF6C",'1'&x"BF6D",'1'&x"BF6E",'1'&x"BF6F",
+--'1'&x"BF70",'1'&x"BF71",'1'&x"BF72",'1'&x"BF73",'1'&x"BF74",'1'&x"BF75",'1'&x"BF76",'1'&x"BF77",'1'&x"BF78",'1'&x"BF79",'1'&x"BF7A",'1'&x"BF7B",'1'&x"BF7C",'1'&x"BF7D",'1'&x"BF7E",'1'&x"BF7F",
+--'1'&x"BF80",'1'&x"BF81",'1'&x"BF82",'1'&x"BF83",'1'&x"BF84",'1'&x"BF85",'1'&x"BF86",'1'&x"BF87",'1'&x"BF88",'1'&x"BF89",'1'&x"BF8A",'1'&x"BF8B",'1'&x"BF8C",'1'&x"BF8D",'1'&x"BF8E",'1'&x"BF8F",
+--'1'&x"BF90",'1'&x"BF91",'1'&x"BF92",'1'&x"BF93",'1'&x"BF94",'1'&x"BF95",'1'&x"BF96",'1'&x"BF97",'1'&x"BF98",'1'&x"BF99",'1'&x"BF9A",'1'&x"BF9B",'1'&x"BF9C",'1'&x"BF9D",'1'&x"BF9E",'1'&x"BF9F",
+--'1'&x"BFA0",'1'&x"BFA1",'1'&x"BFA2",'1'&x"BFA3",'1'&x"BFA4",'1'&x"BFA5",'1'&x"BFA6",'1'&x"BFA7",'1'&x"BFA8",'1'&x"BFA9",'1'&x"BFAA",'1'&x"BFAB",'1'&x"BFAC",'1'&x"BFAD",'1'&x"BFAE",'1'&x"BFAF",
+--'1'&x"BFB0",'1'&x"BFB1",'1'&x"BFB2",'1'&x"BFB3",'1'&x"BFB4",'1'&x"BFB5",'1'&x"BFB6",'1'&x"BFB7",'1'&x"BFB8",'1'&x"BFB9",'1'&x"BFBA",'1'&x"BFBB",'1'&x"BFBC",'1'&x"BFBD",'1'&x"BFBE",'1'&x"BFBF",
+--'1'&x"BFC0",'1'&x"BFC1",'1'&x"BFC2",'1'&x"BFC3",'1'&x"BFC4",'1'&x"BFC5",'1'&x"BFC6",'1'&x"BFC7",'1'&x"BFC8",'1'&x"BFC9",'1'&x"BFCA",'1'&x"BFCB",'1'&x"BFCC",'1'&x"BFCD",'1'&x"BFCE",'1'&x"BFCF",
+--'1'&x"BFD0",'1'&x"BFD1",'1'&x"BFD2",'1'&x"BFD3",'1'&x"BFD4",'1'&x"BFD5",'1'&x"BFD6",'1'&x"BFD7",'1'&x"BFD8",'1'&x"BFD9",'1'&x"BFDA",'1'&x"BFDB",'1'&x"BFDC",'1'&x"BFDD",'1'&x"BFDE",'1'&x"BFDF",
+--'1'&x"BFE0",'1'&x"BFE1",'1'&x"BFE2",'1'&x"BFE3",'1'&x"BFE4",'1'&x"BFE5",'1'&x"BFE6",'1'&x"BFE7",'1'&x"BFE8",'1'&x"BFE9",'1'&x"BFEA",'1'&x"BFEB",'1'&x"BFEC",'1'&x"BFED",'1'&x"BFEE",'1'&x"BFEF",
+--'1'&x"BFF0",'1'&x"BFF1",'1'&x"BFF2",'1'&x"BFF3",'1'&x"BFF4",'1'&x"BFF5",'1'&x"BFF6",'1'&x"BFF7",'1'&x"BFF8",'1'&x"BFF9",'1'&x"BFFA",'1'&x"BFFB",'1'&x"BFFC",'1'&x"BFFD",'1'&x"BFFE",'1'&x"BFFF",
+--'1'&x"C000",'1'&x"C001",'1'&x"C002",'1'&x"C003",'1'&x"C004",'1'&x"C005",'1'&x"C006",'1'&x"C007",'1'&x"C008",'1'&x"C009",'1'&x"C00A",'1'&x"C00B",'1'&x"C00C",'1'&x"C00D",'1'&x"C00E",'1'&x"C00F",
+--'1'&x"C010",'1'&x"C011",'1'&x"C012",'1'&x"C013",'1'&x"C014",'1'&x"C015",'1'&x"C016",'1'&x"C017",'1'&x"C018",'1'&x"C019",'1'&x"C01A",'1'&x"C01B",'1'&x"C01C",'1'&x"C01D",'1'&x"C01E",'1'&x"C01F",
+--'1'&x"C020",'1'&x"C021",'1'&x"C022",'1'&x"C023",'1'&x"C024",'1'&x"C025",'1'&x"C026",'1'&x"C027",'1'&x"C028",'1'&x"C029",'1'&x"C02A",'1'&x"C02B",'1'&x"C02C",'1'&x"C02D",'1'&x"C02E",'1'&x"C02F",
+--'1'&x"C030",'1'&x"C031",'1'&x"C032",'1'&x"C033",'1'&x"C034",'1'&x"C035",'1'&x"C036",'1'&x"C037",'1'&x"C038",'1'&x"C039",'1'&x"C03A",'1'&x"C03B",'1'&x"C03C",'1'&x"C03D",'1'&x"C03E",'1'&x"C03F",
+--'1'&x"C040",'1'&x"C041",'1'&x"C042",'1'&x"C043",'1'&x"C044",'1'&x"C045",'1'&x"C046",'1'&x"C047",'1'&x"C048",'1'&x"C049",'1'&x"C04A",'1'&x"C04B",'1'&x"C04C",'1'&x"C04D",'1'&x"C04E",'1'&x"C04F",
+--'1'&x"C050",'1'&x"C051",'1'&x"C052",'1'&x"C053",'1'&x"C054",'1'&x"C055",'1'&x"C056",'1'&x"C057",'1'&x"C058",'1'&x"C059",'1'&x"C05A",'1'&x"C05B",'1'&x"C05C",'1'&x"C05D",'1'&x"C05E",'1'&x"C05F",
+--'1'&x"C060",'1'&x"C061",'1'&x"C062",'1'&x"C063",'1'&x"C064",'1'&x"C065",'1'&x"C066",'1'&x"C067",'1'&x"C068",'1'&x"C069",'1'&x"C06A",'1'&x"C06B",'1'&x"C06C",'1'&x"C06D",'1'&x"C06E",'1'&x"C06F",
+--'1'&x"C070",'1'&x"C071",'1'&x"C072",'1'&x"C073",'1'&x"C074",'1'&x"C075",'1'&x"C076",'1'&x"C077",'1'&x"C078",'1'&x"C079",'1'&x"C07A",'1'&x"C07B",'1'&x"C07C",'1'&x"C07D",'1'&x"C07E",'1'&x"C07F",
+--'1'&x"C080",'1'&x"C081",'1'&x"C082",'1'&x"C083",'1'&x"C084",'1'&x"C085",'1'&x"C086",'1'&x"C087",'1'&x"C088",'1'&x"C089",'1'&x"C08A",'1'&x"C08B",'1'&x"C08C",'1'&x"C08D",'1'&x"C08E",'1'&x"C08F",
+--'1'&x"C090",'1'&x"C091",'1'&x"C092",'1'&x"C093",'1'&x"C094",'1'&x"C095",'1'&x"C096",'1'&x"C097",'1'&x"C098",'1'&x"C099",'1'&x"C09A",'1'&x"C09B",'1'&x"C09C",'1'&x"C09D",'1'&x"C09E",'1'&x"C09F",
+--'1'&x"C0A0",'1'&x"C0A1",'1'&x"C0A2",'1'&x"C0A3",'1'&x"C0A4",'1'&x"C0A5",'1'&x"C0A6",'1'&x"C0A7",'1'&x"C0A8",'1'&x"C0A9",'1'&x"C0AA",'1'&x"C0AB",'1'&x"C0AC",'1'&x"C0AD",'1'&x"C0AE",'1'&x"C0AF",
+--'1'&x"C0B0",'1'&x"C0B1",'1'&x"C0B2",'1'&x"C0B3",'1'&x"C0B4",'1'&x"C0B5",'1'&x"C0B6",'1'&x"C0B7",'1'&x"C0B8",'1'&x"C0B9",'1'&x"C0BA",'1'&x"C0BB",'1'&x"C0BC",'1'&x"C0BD",'1'&x"C0BE",'1'&x"C0BF",
+--'1'&x"C0C0",'1'&x"C0C1",'1'&x"C0C2",'1'&x"C0C3",'1'&x"C0C4",'1'&x"C0C5",'1'&x"C0C6",'1'&x"C0C7",'1'&x"C0C8",'1'&x"C0C9",'1'&x"C0CA",'1'&x"C0CB",'1'&x"C0CC",'1'&x"C0CD",'1'&x"C0CE",'1'&x"C0CF",
+--'1'&x"C0D0",'1'&x"C0D1",'1'&x"C0D2",'1'&x"C0D3",'1'&x"C0D4",'1'&x"C0D5",'1'&x"C0D6",'1'&x"C0D7",'1'&x"C0D8",'1'&x"C0D9",'1'&x"C0DA",'1'&x"C0DB",'1'&x"C0DC",'1'&x"C0DD",'1'&x"C0DE",'1'&x"C0DF",
+--'1'&x"C0E0",'1'&x"C0E1",'1'&x"C0E2",'1'&x"C0E3",'1'&x"C0E4",'1'&x"C0E5",'1'&x"C0E6",'1'&x"C0E7",'1'&x"C0E8",'1'&x"C0E9",'1'&x"C0EA",'1'&x"C0EB",'1'&x"C0EC",'1'&x"C0ED",'1'&x"C0EE",'1'&x"C0EF",
+--'1'&x"C0F0",'1'&x"C0F1",'1'&x"C0F2",'1'&x"C0F3",'1'&x"C0F4",'1'&x"C0F5",'1'&x"C0F6",'1'&x"C0F7",'1'&x"C0F8",'1'&x"C0F9",'1'&x"C0FA",'1'&x"C0FB",'1'&x"C0FC",'1'&x"C0FD",'1'&x"C0FE",'1'&x"C0FF",
+--'1'&x"C100",'1'&x"C101",'1'&x"C102",'1'&x"C103",'1'&x"C104",'1'&x"C105",'1'&x"C106",'1'&x"C107",'1'&x"C108",'1'&x"C109",'1'&x"C10A",'1'&x"C10B",'1'&x"C10C",'1'&x"C10D",'1'&x"C10E",'1'&x"C10F",
+--'1'&x"C110",'1'&x"C111",'1'&x"C112",'1'&x"C113",'1'&x"C114",'1'&x"C115",'1'&x"C116",'1'&x"C117",'1'&x"C118",'1'&x"C119",'1'&x"C11A",'1'&x"C11B",'1'&x"C11C",'1'&x"C11D",'1'&x"C11E",'1'&x"C11F",
+--'1'&x"C120",'1'&x"C121",'1'&x"C122",'1'&x"C123",'1'&x"C124",'1'&x"C125",'1'&x"C126",'1'&x"C127",'1'&x"C128",'1'&x"C129",'1'&x"C12A",'1'&x"C12B",'1'&x"C12C",'1'&x"C12D",'1'&x"C12E",'1'&x"C12F",
+--'1'&x"C130",'1'&x"C131",'1'&x"C132",'1'&x"C133",'1'&x"C134",'1'&x"C135",'1'&x"C136",'1'&x"C137",'1'&x"C138",'1'&x"C139",'1'&x"C13A",'1'&x"C13B",'1'&x"C13C",'1'&x"C13D",'1'&x"C13E",'1'&x"C13F",
+--'1'&x"C140",'1'&x"C141",'1'&x"C142",'1'&x"C143",'1'&x"C144",'1'&x"C145",'1'&x"C146",'1'&x"C147",'1'&x"C148",'1'&x"C149",'1'&x"C14A",'1'&x"C14B",'1'&x"C14C",'1'&x"C14D",'1'&x"C14E",'1'&x"C14F",
+--'1'&x"C150",'1'&x"C151",'1'&x"C152",'1'&x"C153",'1'&x"C154",'1'&x"C155",'1'&x"C156",'1'&x"C157",'1'&x"C158",'1'&x"C159",'1'&x"C15A",'1'&x"C15B",'1'&x"C15C",'1'&x"C15D",'1'&x"C15E",'1'&x"C15F",
+--'1'&x"C160",'1'&x"C161",'1'&x"C162",'1'&x"C163",'1'&x"C164",'1'&x"C165",'1'&x"C166",'1'&x"C167",'1'&x"C168",'1'&x"C169",'1'&x"C16A",'1'&x"C16B",'1'&x"C16C",'1'&x"C16D",'1'&x"C16E",'1'&x"C16F",
+--'1'&x"C170",'1'&x"C171",'1'&x"C172",'1'&x"C173",'1'&x"C174",'1'&x"C175",'1'&x"C176",'1'&x"C177",'1'&x"C178",'1'&x"C179",'1'&x"C17A",'1'&x"C17B",'1'&x"C17C",'1'&x"C17D",'1'&x"C17E",'1'&x"C17F",
+--'1'&x"C180",'1'&x"C181",'1'&x"C182",'1'&x"C183",'1'&x"C184",'1'&x"C185",'1'&x"C186",'1'&x"C187",'1'&x"C188",'1'&x"C189",'1'&x"C18A",'1'&x"C18B",'1'&x"C18C",'1'&x"C18D",'1'&x"C18E",'1'&x"C18F",
+--'1'&x"C190",'1'&x"C191",'1'&x"C192",'1'&x"C193",'1'&x"C194",'1'&x"C195",'1'&x"C196",'1'&x"C197",'1'&x"C198",'1'&x"C199",'1'&x"C19A",'1'&x"C19B",'1'&x"C19C",'1'&x"C19D",'1'&x"C19E",'1'&x"C19F",
+--'1'&x"C1A0",'1'&x"C1A1",'1'&x"C1A2",'1'&x"C1A3",'1'&x"C1A4",'1'&x"C1A5",'1'&x"C1A6",'1'&x"C1A7",'1'&x"C1A8",'1'&x"C1A9",'1'&x"C1AA",'1'&x"C1AB",'1'&x"C1AC",'1'&x"C1AD",'1'&x"C1AE",'1'&x"C1AF",
+--'1'&x"C1B0",'1'&x"C1B1",'1'&x"C1B2",'1'&x"C1B3",'1'&x"C1B4",'1'&x"C1B5",'1'&x"C1B6",'1'&x"C1B7",'1'&x"C1B8",'1'&x"C1B9",'1'&x"C1BA",'1'&x"C1BB",'1'&x"C1BC",'1'&x"C1BD",'1'&x"C1BE",'1'&x"C1BF",
+--'1'&x"C1C0",'1'&x"C1C1",'1'&x"C1C2",'1'&x"C1C3",'1'&x"C1C4",'1'&x"C1C5",'1'&x"C1C6",'1'&x"C1C7",'1'&x"C1C8",'1'&x"C1C9",'1'&x"C1CA",'1'&x"C1CB",'1'&x"C1CC",'1'&x"C1CD",'1'&x"C1CE",'1'&x"C1CF",
+--'1'&x"C1D0",'1'&x"C1D1",'1'&x"C1D2",'1'&x"C1D3",'1'&x"C1D4",'1'&x"C1D5",'1'&x"C1D6",'1'&x"C1D7",'1'&x"C1D8",'1'&x"C1D9",'1'&x"C1DA",'1'&x"C1DB",'1'&x"C1DC",'1'&x"C1DD",'1'&x"C1DE",'1'&x"C1DF",
+--'1'&x"C1E0",'1'&x"C1E1",'1'&x"C1E2",'1'&x"C1E3",'1'&x"C1E4",'1'&x"C1E5",'1'&x"C1E6",'1'&x"C1E7",'1'&x"C1E8",'1'&x"C1E9",'1'&x"C1EA",'1'&x"C1EB",'1'&x"C1EC",'1'&x"C1ED",'1'&x"C1EE",'1'&x"C1EF",
+--'1'&x"C1F0",'1'&x"C1F1",'1'&x"C1F2",'1'&x"C1F3",'1'&x"C1F4",'1'&x"C1F5",'1'&x"C1F6",'1'&x"C1F7",'1'&x"C1F8",'1'&x"C1F9",'1'&x"C1FA",'1'&x"C1FB",'1'&x"C1FC",'1'&x"C1FD",'1'&x"C1FE",'1'&x"C1FF",
+--'1'&x"C200",'1'&x"C201",'1'&x"C202",'1'&x"C203",'1'&x"C204",'1'&x"C205",'1'&x"C206",'1'&x"C207",'1'&x"C208",'1'&x"C209",'1'&x"C20A",'1'&x"C20B",'1'&x"C20C",'1'&x"C20D",'1'&x"C20E",'1'&x"C20F",
+--'1'&x"C210",'1'&x"C211",'1'&x"C212",'1'&x"C213",'1'&x"C214",'1'&x"C215",'1'&x"C216",'1'&x"C217",'1'&x"C218",'1'&x"C219",'1'&x"C21A",'1'&x"C21B",'1'&x"C21C",'1'&x"C21D",'1'&x"C21E",'1'&x"C21F",
+--'1'&x"C220",'1'&x"C221",'1'&x"C222",'1'&x"C223",'1'&x"C224",'1'&x"C225",'1'&x"C226",'1'&x"C227",'1'&x"C228",'1'&x"C229",'1'&x"C22A",'1'&x"C22B",'1'&x"C22C",'1'&x"C22D",'1'&x"C22E",'1'&x"C22F",
+--'1'&x"C230",'1'&x"C231",'1'&x"C232",'1'&x"C233",'1'&x"C234",'1'&x"C235",'1'&x"C236",'1'&x"C237",'1'&x"C238",'1'&x"C239",'1'&x"C23A",'1'&x"C23B",'1'&x"C23C",'1'&x"C23D",'1'&x"C23E",'1'&x"C23F",
+--'1'&x"C240",'1'&x"C241",'1'&x"C242",'1'&x"C243",'1'&x"C244",'1'&x"C245",'1'&x"C246",'1'&x"C247",'1'&x"C248",'1'&x"C249",'1'&x"C24A",'1'&x"C24B",'1'&x"C24C",'1'&x"C24D",'1'&x"C24E",'1'&x"C24F",
+--'1'&x"C250",'1'&x"C251",'1'&x"C252",'1'&x"C253",'1'&x"C254",'1'&x"C255",'1'&x"C256",'1'&x"C257",'1'&x"C258",'1'&x"C259",'1'&x"C25A",'1'&x"C25B",'1'&x"C25C",'1'&x"C25D",'1'&x"C25E",'1'&x"C25F",
+--'1'&x"C260",'1'&x"C261",'1'&x"C262",'1'&x"C263",'1'&x"C264",'1'&x"C265",'1'&x"C266",'1'&x"C267",'1'&x"C268",'1'&x"C269",'1'&x"C26A",'1'&x"C26B",'1'&x"C26C",'1'&x"C26D",'1'&x"C26E",'1'&x"C26F",
+--'1'&x"C270",'1'&x"C271",'1'&x"C272",'1'&x"C273",'1'&x"C274",'1'&x"C275",'1'&x"C276",'1'&x"C277",'1'&x"C278",'1'&x"C279",'1'&x"C27A",'1'&x"C27B",'1'&x"C27C",'1'&x"C27D",'1'&x"C27E",'1'&x"C27F",
+--'1'&x"C280",'1'&x"C281",'1'&x"C282",'1'&x"C283",'1'&x"C284",'1'&x"C285",'1'&x"C286",'1'&x"C287",'1'&x"C288",'1'&x"C289",'1'&x"C28A",'1'&x"C28B",'1'&x"C28C",'1'&x"C28D",'1'&x"C28E",'1'&x"C28F",
+--'1'&x"C290",'1'&x"C291",'1'&x"C292",'1'&x"C293",'1'&x"C294",'1'&x"C295",'1'&x"C296",'1'&x"C297",'1'&x"C298",'1'&x"C299",'1'&x"C29A",'1'&x"C29B",'1'&x"C29C",'1'&x"C29D",'1'&x"C29E",'1'&x"C29F",
+--'1'&x"C2A0",'1'&x"C2A1",'1'&x"C2A2",'1'&x"C2A3",'1'&x"C2A4",'1'&x"C2A5",'1'&x"C2A6",'1'&x"C2A7",'1'&x"C2A8",'1'&x"C2A9",'1'&x"C2AA",'1'&x"C2AB",'1'&x"C2AC",'1'&x"C2AD",'1'&x"C2AE",'1'&x"C2AF",
+--'1'&x"C2B0",'1'&x"C2B1",'1'&x"C2B2",'1'&x"C2B3",'1'&x"C2B4",'1'&x"C2B5",'1'&x"C2B6",'1'&x"C2B7",'1'&x"C2B8",'1'&x"C2B9",'1'&x"C2BA",'1'&x"C2BB",'1'&x"C2BC",'1'&x"C2BD",'1'&x"C2BE",'1'&x"C2BF",
+--'1'&x"C2C0",'1'&x"C2C1",'1'&x"C2C2",'1'&x"C2C3",'1'&x"C2C4",'1'&x"C2C5",'1'&x"C2C6",'1'&x"C2C7",'1'&x"C2C8",'1'&x"C2C9",'1'&x"C2CA",'1'&x"C2CB",'1'&x"C2CC",'1'&x"C2CD",'1'&x"C2CE",'1'&x"C2CF",
+--'1'&x"C2D0",'1'&x"C2D1",'1'&x"C2D2",'1'&x"C2D3",'1'&x"C2D4",'1'&x"C2D5",'1'&x"C2D6",'1'&x"C2D7",'1'&x"C2D8",'1'&x"C2D9",'1'&x"C2DA",'1'&x"C2DB",'1'&x"C2DC",'1'&x"C2DD",'1'&x"C2DE",'1'&x"C2DF",
+--'1'&x"C2E0",'1'&x"C2E1",'1'&x"C2E2",'1'&x"C2E3",'1'&x"C2E4",'1'&x"C2E5",'1'&x"C2E6",'1'&x"C2E7",'1'&x"C2E8",'1'&x"C2E9",'1'&x"C2EA",'1'&x"C2EB",'1'&x"C2EC",'1'&x"C2ED",'1'&x"C2EE",'1'&x"C2EF",
+--'1'&x"C2F0",'1'&x"C2F1",'1'&x"C2F2",'1'&x"C2F3",'1'&x"C2F4",'1'&x"C2F5",'1'&x"C2F6",'1'&x"C2F7",'1'&x"C2F8",'1'&x"C2F9",'1'&x"C2FA",'1'&x"C2FB",'1'&x"C2FC",'1'&x"C2FD",'1'&x"C2FE",'1'&x"C2FF",
+--'1'&x"C300",'1'&x"C301",'1'&x"C302",'1'&x"C303",'1'&x"C304",'1'&x"C305",'1'&x"C306",'1'&x"C307",'1'&x"C308",'1'&x"C309",'1'&x"C30A",'1'&x"C30B",'1'&x"C30C",'1'&x"C30D",'1'&x"C30E",'1'&x"C30F",
+--'1'&x"C310",'1'&x"C311",'1'&x"C312",'1'&x"C313",'1'&x"C314",'1'&x"C315",'1'&x"C316",'1'&x"C317",'1'&x"C318",'1'&x"C319",'1'&x"C31A",'1'&x"C31B",'1'&x"C31C",'1'&x"C31D",'1'&x"C31E",'1'&x"C31F",
+--'1'&x"C320",'1'&x"C321",'1'&x"C322",'1'&x"C323",'1'&x"C324",'1'&x"C325",'1'&x"C326",'1'&x"C327",'1'&x"C328",'1'&x"C329",'1'&x"C32A",'1'&x"C32B",'1'&x"C32C",'1'&x"C32D",'1'&x"C32E",'1'&x"C32F",
+--'1'&x"C330",'1'&x"C331",'1'&x"C332",'1'&x"C333",'1'&x"C334",'1'&x"C335",'1'&x"C336",'1'&x"C337",'1'&x"C338",'1'&x"C339",'1'&x"C33A",'1'&x"C33B",'1'&x"C33C",'1'&x"C33D",'1'&x"C33E",'1'&x"C33F",
+--'1'&x"C340",'1'&x"C341",'1'&x"C342",'1'&x"C343",'1'&x"C344",'1'&x"C345",'1'&x"C346",'1'&x"C347",'1'&x"C348",'1'&x"C349",'1'&x"C34A",'1'&x"C34B",'1'&x"C34C",'1'&x"C34D",'1'&x"C34E",'1'&x"C34F",
+--'1'&x"C350",'1'&x"C351",'1'&x"C352",'1'&x"C353",'1'&x"C354",'1'&x"C355",'1'&x"C356",'1'&x"C357",'1'&x"C358",'1'&x"C359",'1'&x"C35A",'1'&x"C35B",'1'&x"C35C",'1'&x"C35D",'1'&x"C35E",'1'&x"C35F",
+--'1'&x"C360",'1'&x"C361",'1'&x"C362",'1'&x"C363",'1'&x"C364",'1'&x"C365",'1'&x"C366",'1'&x"C367",'1'&x"C368",'1'&x"C369",'1'&x"C36A",'1'&x"C36B",'1'&x"C36C",'1'&x"C36D",'1'&x"C36E",'1'&x"C36F",
+--'1'&x"C370",'1'&x"C371",'1'&x"C372",'1'&x"C373",'1'&x"C374",'1'&x"C375",'1'&x"C376",'1'&x"C377",'1'&x"C378",'1'&x"C379",'1'&x"C37A",'1'&x"C37B",'1'&x"C37C",'1'&x"C37D",'1'&x"C37E",'1'&x"C37F",
+--'1'&x"C380",'1'&x"C381",'1'&x"C382",'1'&x"C383",'1'&x"C384",'1'&x"C385",'1'&x"C386",'1'&x"C387",'1'&x"C388",'1'&x"C389",'1'&x"C38A",'1'&x"C38B",'1'&x"C38C",'1'&x"C38D",'1'&x"C38E",'1'&x"C38F",
+--'1'&x"C390",'1'&x"C391",'1'&x"C392",'1'&x"C393",'1'&x"C394",'1'&x"C395",'1'&x"C396",'1'&x"C397",'1'&x"C398",'1'&x"C399",'1'&x"C39A",'1'&x"C39B",'1'&x"C39C",'1'&x"C39D",'1'&x"C39E",'1'&x"C39F",
+--'1'&x"C3A0",'1'&x"C3A1",'1'&x"C3A2",'1'&x"C3A3",'1'&x"C3A4",'1'&x"C3A5",'1'&x"C3A6",'1'&x"C3A7",'1'&x"C3A8",'1'&x"C3A9",'1'&x"C3AA",'1'&x"C3AB",'1'&x"C3AC",'1'&x"C3AD",'1'&x"C3AE",'1'&x"C3AF",
+--'1'&x"C3B0",'1'&x"C3B1",'1'&x"C3B2",'1'&x"C3B3",'1'&x"C3B4",'1'&x"C3B5",'1'&x"C3B6",'1'&x"C3B7",'1'&x"C3B8",'1'&x"C3B9",'1'&x"C3BA",'1'&x"C3BB",'1'&x"C3BC",'1'&x"C3BD",'1'&x"C3BE",'1'&x"C3BF",
+--'1'&x"C3C0",'1'&x"C3C1",'1'&x"C3C2",'1'&x"C3C3",'1'&x"C3C4",'1'&x"C3C5",'1'&x"C3C6",'1'&x"C3C7",'1'&x"C3C8",'1'&x"C3C9",'1'&x"C3CA",'1'&x"C3CB",'1'&x"C3CC",'1'&x"C3CD",'1'&x"C3CE",'1'&x"C3CF",
+--'1'&x"C3D0",'1'&x"C3D1",'1'&x"C3D2",'1'&x"C3D3",'1'&x"C3D4",'1'&x"C3D5",'1'&x"C3D6",'1'&x"C3D7",'1'&x"C3D8",'1'&x"C3D9",'1'&x"C3DA",'1'&x"C3DB",'1'&x"C3DC",'1'&x"C3DD",'1'&x"C3DE",'1'&x"C3DF",
+--'1'&x"C3E0",'1'&x"C3E1",'1'&x"C3E2",'1'&x"C3E3",'1'&x"C3E4",'1'&x"C3E5",'1'&x"C3E6",'1'&x"C3E7",'1'&x"C3E8",'1'&x"C3E9",'1'&x"C3EA",'1'&x"C3EB",'1'&x"C3EC",'1'&x"C3ED",'1'&x"C3EE",'1'&x"C3EF",
+--'1'&x"C3F0",'1'&x"C3F1",'1'&x"C3F2",'1'&x"C3F3",'1'&x"C3F4",'1'&x"C3F5",'1'&x"C3F6",'1'&x"C3F7",'1'&x"C3F8",'1'&x"C3F9",'1'&x"C3FA",'1'&x"C3FB",'1'&x"C3FC",'1'&x"C3FD",'1'&x"C3FE",'1'&x"C3FF",
+--'1'&x"C400",'1'&x"C401",'1'&x"C402",'1'&x"C403",'1'&x"C404",'1'&x"C405",'1'&x"C406",'1'&x"C407",'1'&x"C408",'1'&x"C409",'1'&x"C40A",'1'&x"C40B",'1'&x"C40C",'1'&x"C40D",'1'&x"C40E",'1'&x"C40F",
+--'1'&x"C410",'1'&x"C411",'1'&x"C412",'1'&x"C413",'1'&x"C414",'1'&x"C415",'1'&x"C416",'1'&x"C417",'1'&x"C418",'1'&x"C419",'1'&x"C41A",'1'&x"C41B",'1'&x"C41C",'1'&x"C41D",'1'&x"C41E",'1'&x"C41F",
+--'1'&x"C420",'1'&x"C421",'1'&x"C422",'1'&x"C423",'1'&x"C424",'1'&x"C425",'1'&x"C426",'1'&x"C427",'1'&x"C428",'1'&x"C429",'1'&x"C42A",'1'&x"C42B",'1'&x"C42C",'1'&x"C42D",'1'&x"C42E",'1'&x"C42F",
+--'1'&x"C430",'1'&x"C431",'1'&x"C432",'1'&x"C433",'1'&x"C434",'1'&x"C435",'1'&x"C436",'1'&x"C437",'1'&x"C438",'1'&x"C439",'1'&x"C43A",'1'&x"C43B",'1'&x"C43C",'1'&x"C43D",'1'&x"C43E",'1'&x"C43F",
+--'1'&x"C440",'1'&x"C441",'1'&x"C442",'1'&x"C443",'1'&x"C444",'1'&x"C445",'1'&x"C446",'1'&x"C447",'1'&x"C448",'1'&x"C449",'1'&x"C44A",'1'&x"C44B",'1'&x"C44C",'1'&x"C44D",'1'&x"C44E",'1'&x"C44F",
+--'1'&x"C450",'1'&x"C451",'1'&x"C452",'1'&x"C453",'1'&x"C454",'1'&x"C455",'1'&x"C456",'1'&x"C457",'1'&x"C458",'1'&x"C459",'1'&x"C45A",'1'&x"C45B",'1'&x"C45C",'1'&x"C45D",'1'&x"C45E",'1'&x"C45F",
+--'1'&x"C460",'1'&x"C461",'1'&x"C462",'1'&x"C463",'1'&x"C464",'1'&x"C465",'1'&x"C466",'1'&x"C467",'1'&x"C468",'1'&x"C469",'1'&x"C46A",'1'&x"C46B",'1'&x"C46C",'1'&x"C46D",'1'&x"C46E",'1'&x"C46F",
+--'1'&x"C470",'1'&x"C471",'1'&x"C472",'1'&x"C473",'1'&x"C474",'1'&x"C475",'1'&x"C476",'1'&x"C477",'1'&x"C478",'1'&x"C479",'1'&x"C47A",'1'&x"C47B",'1'&x"C47C",'1'&x"C47D",'1'&x"C47E",'1'&x"C47F",
+--'1'&x"C480",'1'&x"C481",'1'&x"C482",'1'&x"C483",'1'&x"C484",'1'&x"C485",'1'&x"C486",'1'&x"C487",'1'&x"C488",'1'&x"C489",'1'&x"C48A",'1'&x"C48B",'1'&x"C48C",'1'&x"C48D",'1'&x"C48E",'1'&x"C48F",
+--'1'&x"C490",'1'&x"C491",'1'&x"C492",'1'&x"C493",'1'&x"C494",'1'&x"C495",'1'&x"C496",'1'&x"C497",'1'&x"C498",'1'&x"C499",'1'&x"C49A",'1'&x"C49B",'1'&x"C49C",'1'&x"C49D",'1'&x"C49E",'1'&x"C49F",
+--'1'&x"C4A0",'1'&x"C4A1",'1'&x"C4A2",'1'&x"C4A3",'1'&x"C4A4",'1'&x"C4A5",'1'&x"C4A6",'1'&x"C4A7",'1'&x"C4A8",'1'&x"C4A9",'1'&x"C4AA",'1'&x"C4AB",'1'&x"C4AC",'1'&x"C4AD",'1'&x"C4AE",'1'&x"C4AF",
+--'1'&x"C4B0",'1'&x"C4B1",'1'&x"C4B2",'1'&x"C4B3",'1'&x"C4B4",'1'&x"C4B5",'1'&x"C4B6",'1'&x"C4B7",'1'&x"C4B8",'1'&x"C4B9",'1'&x"C4BA",'1'&x"C4BB",'1'&x"C4BC",'1'&x"C4BD",'1'&x"C4BE",'1'&x"C4BF",
+--'1'&x"C4C0",'1'&x"C4C1",'1'&x"C4C2",'1'&x"C4C3",'1'&x"C4C4",'1'&x"C4C5",'1'&x"C4C6",'1'&x"C4C7",'1'&x"C4C8",'1'&x"C4C9",'1'&x"C4CA",'1'&x"C4CB",'1'&x"C4CC",'1'&x"C4CD",'1'&x"C4CE",'1'&x"C4CF",
+--'1'&x"C4D0",'1'&x"C4D1",'1'&x"C4D2",'1'&x"C4D3",'1'&x"C4D4",'1'&x"C4D5",'1'&x"C4D6",'1'&x"C4D7",'1'&x"C4D8",'1'&x"C4D9",'1'&x"C4DA",'1'&x"C4DB",'1'&x"C4DC",'1'&x"C4DD",'1'&x"C4DE",'1'&x"C4DF",
+--'1'&x"C4E0",'1'&x"C4E1",'1'&x"C4E2",'1'&x"C4E3",'1'&x"C4E4",'1'&x"C4E5",'1'&x"C4E6",'1'&x"C4E7",'1'&x"C4E8",'1'&x"C4E9",'1'&x"C4EA",'1'&x"C4EB",'1'&x"C4EC",'1'&x"C4ED",'1'&x"C4EE",'1'&x"C4EF",
+--'1'&x"C4F0",'1'&x"C4F1",'1'&x"C4F2",'1'&x"C4F3",'1'&x"C4F4",'1'&x"C4F5",'1'&x"C4F6",'1'&x"C4F7",'1'&x"C4F8",'1'&x"C4F9",'1'&x"C4FA",'1'&x"C4FB",'1'&x"C4FC",'1'&x"C4FD",'1'&x"C4FE",'1'&x"C4FF",
+--'1'&x"C500",'1'&x"C501",'1'&x"C502",'1'&x"C503",'1'&x"C504",'1'&x"C505",'1'&x"C506",'1'&x"C507",'1'&x"C508",'1'&x"C509",'1'&x"C50A",'1'&x"C50B",'1'&x"C50C",'1'&x"C50D",'1'&x"C50E",'1'&x"C50F",
+--'1'&x"C510",'1'&x"C511",'1'&x"C512",'1'&x"C513",'1'&x"C514",'1'&x"C515",'1'&x"C516",'1'&x"C517",'1'&x"C518",'1'&x"C519",'1'&x"C51A",'1'&x"C51B",'1'&x"C51C",'1'&x"C51D",'1'&x"C51E",'1'&x"C51F",
+--'1'&x"C520",'1'&x"C521",'1'&x"C522",'1'&x"C523",'1'&x"C524",'1'&x"C525",'1'&x"C526",'1'&x"C527",'1'&x"C528",'1'&x"C529",'1'&x"C52A",'1'&x"C52B",'1'&x"C52C",'1'&x"C52D",'1'&x"C52E",'1'&x"C52F",
+--'1'&x"C530",'1'&x"C531",'1'&x"C532",'1'&x"C533",'1'&x"C534",'1'&x"C535",'1'&x"C536",'1'&x"C537",'1'&x"C538",'1'&x"C539",'1'&x"C53A",'1'&x"C53B",'1'&x"C53C",'1'&x"C53D",'1'&x"C53E",'1'&x"C53F",
+--'1'&x"C540",'1'&x"C541",'1'&x"C542",'1'&x"C543",'1'&x"C544",'1'&x"C545",'1'&x"C546",'1'&x"C547",'1'&x"C548",'1'&x"C549",'1'&x"C54A",'1'&x"C54B",'1'&x"C54C",'1'&x"C54D",'1'&x"C54E",'1'&x"C54F",
+--'1'&x"C550",'1'&x"C551",'1'&x"C552",'1'&x"C553",'1'&x"C554",'1'&x"C555",'1'&x"C556",'1'&x"C557",'1'&x"C558",'1'&x"C559",'1'&x"C55A",'1'&x"C55B",'1'&x"C55C",'1'&x"C55D",'1'&x"C55E",'1'&x"C55F",
+--'1'&x"C560",'1'&x"C561",'1'&x"C562",'1'&x"C563",'1'&x"C564",'1'&x"C565",'1'&x"C566",'1'&x"C567",'1'&x"C568",'1'&x"C569",'1'&x"C56A",'1'&x"C56B",'1'&x"C56C",'1'&x"C56D",'1'&x"C56E",'1'&x"C56F",
+--'1'&x"C570",'1'&x"C571",'1'&x"C572",'1'&x"C573",'1'&x"C574",'1'&x"C575",'1'&x"C576",'1'&x"C577",'1'&x"C578",'1'&x"C579",'1'&x"C57A",'1'&x"C57B",'1'&x"C57C",'1'&x"C57D",'1'&x"C57E",'1'&x"C57F",
+--'1'&x"C580",'1'&x"C581",'1'&x"C582",'1'&x"C583",'1'&x"C584",'1'&x"C585",'1'&x"C586",'1'&x"C587",'1'&x"C588",'1'&x"C589",'1'&x"C58A",'1'&x"C58B",'1'&x"C58C",'1'&x"C58D",'1'&x"C58E",'1'&x"C58F",
+--'1'&x"C590",'1'&x"C591",'1'&x"C592",'1'&x"C593",'1'&x"C594",'1'&x"C595",'1'&x"C596",'1'&x"C597",'1'&x"C598",'1'&x"C599",'1'&x"C59A",'1'&x"C59B",'1'&x"C59C",'1'&x"C59D",'1'&x"C59E",'1'&x"C59F",
+--'1'&x"C5A0",'1'&x"C5A1",'1'&x"C5A2",'1'&x"C5A3",'1'&x"C5A4",'1'&x"C5A5",'1'&x"C5A6",'1'&x"C5A7",'1'&x"C5A8",'1'&x"C5A9",'1'&x"C5AA",'1'&x"C5AB",'1'&x"C5AC",'1'&x"C5AD",'1'&x"C5AE",'1'&x"C5AF",
+--'1'&x"C5B0",'1'&x"C5B1",'1'&x"C5B2",'1'&x"C5B3",'1'&x"C5B4",'1'&x"C5B5",'1'&x"C5B6",'1'&x"C5B7",'1'&x"C5B8",'1'&x"C5B9",'1'&x"C5BA",'1'&x"C5BB",'1'&x"C5BC",'1'&x"C5BD",'1'&x"C5BE",'1'&x"C5BF",
+--'1'&x"C5C0",'1'&x"C5C1",'1'&x"C5C2",'1'&x"C5C3",'1'&x"C5C4",'1'&x"C5C5",'1'&x"C5C6",'1'&x"C5C7",'1'&x"C5C8",'1'&x"C5C9",'1'&x"C5CA",'1'&x"C5CB",'1'&x"C5CC",'1'&x"C5CD",'1'&x"C5CE",'1'&x"C5CF",
+--'1'&x"C5D0",'1'&x"C5D1",'1'&x"C5D2",'1'&x"C5D3",'1'&x"C5D4",'1'&x"C5D5",'1'&x"C5D6",'1'&x"C5D7",'1'&x"C5D8",'1'&x"C5D9",'1'&x"C5DA",'1'&x"C5DB",'1'&x"C5DC",'1'&x"C5DD",'1'&x"C5DE",'1'&x"C5DF",
+--'1'&x"C5E0",'1'&x"C5E1",'1'&x"C5E2",'1'&x"C5E3",'1'&x"C5E4",'1'&x"C5E5",'1'&x"C5E6",'1'&x"C5E7",'1'&x"C5E8",'1'&x"C5E9",'1'&x"C5EA",'1'&x"C5EB",'1'&x"C5EC",'1'&x"C5ED",'1'&x"C5EE",'1'&x"C5EF",
+--'1'&x"C5F0",'1'&x"C5F1",'1'&x"C5F2",'1'&x"C5F3",'1'&x"C5F4",'1'&x"C5F5",'1'&x"C5F6",'1'&x"C5F7",'1'&x"C5F8",'1'&x"C5F9",'1'&x"C5FA",'1'&x"C5FB",'1'&x"C5FC",'1'&x"C5FD",'1'&x"C5FE",'1'&x"C5FF",
+--'1'&x"C600",'1'&x"C601",'1'&x"C602",'1'&x"C603",'1'&x"C604",'1'&x"C605",'1'&x"C606",'1'&x"C607",'1'&x"C608",'1'&x"C609",'1'&x"C60A",'1'&x"C60B",'1'&x"C60C",'1'&x"C60D",'1'&x"C60E",'1'&x"C60F",
+--'1'&x"C610",'1'&x"C611",'1'&x"C612",'1'&x"C613",'1'&x"C614",'1'&x"C615",'1'&x"C616",'1'&x"C617",'1'&x"C618",'1'&x"C619",'1'&x"C61A",'1'&x"C61B",'1'&x"C61C",'1'&x"C61D",'1'&x"C61E",'1'&x"C61F",
+--'1'&x"C620",'1'&x"C621",'1'&x"C622",'1'&x"C623",'1'&x"C624",'1'&x"C625",'1'&x"C626",'1'&x"C627",'1'&x"C628",'1'&x"C629",'1'&x"C62A",'1'&x"C62B",'1'&x"C62C",'1'&x"C62D",'1'&x"C62E",'1'&x"C62F",
+--'1'&x"C630",'1'&x"C631",'1'&x"C632",'1'&x"C633",'1'&x"C634",'1'&x"C635",'1'&x"C636",'1'&x"C637",'1'&x"C638",'1'&x"C639",'1'&x"C63A",'1'&x"C63B",'1'&x"C63C",'1'&x"C63D",'1'&x"C63E",'1'&x"C63F",
+--'1'&x"C640",'1'&x"C641",'1'&x"C642",'1'&x"C643",'1'&x"C644",'1'&x"C645",'1'&x"C646",'1'&x"C647",'1'&x"C648",'1'&x"C649",'1'&x"C64A",'1'&x"C64B",'1'&x"C64C",'1'&x"C64D",'1'&x"C64E",'1'&x"C64F",
+--'1'&x"C650",'1'&x"C651",'1'&x"C652",'1'&x"C653",'1'&x"C654",'1'&x"C655",'1'&x"C656",'1'&x"C657",'1'&x"C658",'1'&x"C659",'1'&x"C65A",'1'&x"C65B",'1'&x"C65C",'1'&x"C65D",'1'&x"C65E",'1'&x"C65F",
+--'1'&x"C660",'1'&x"C661",'1'&x"C662",'1'&x"C663",'1'&x"C664",'1'&x"C665",'1'&x"C666",'1'&x"C667",'1'&x"C668",'1'&x"C669",'1'&x"C66A",'1'&x"C66B",'1'&x"C66C",'1'&x"C66D",'1'&x"C66E",'1'&x"C66F",
+--'1'&x"C670",'1'&x"C671",'1'&x"C672",'1'&x"C673",'1'&x"C674",'1'&x"C675",'1'&x"C676",'1'&x"C677",'1'&x"C678",'1'&x"C679",'1'&x"C67A",'1'&x"C67B",'1'&x"C67C",'1'&x"C67D",'1'&x"C67E",'1'&x"C67F",
+--'1'&x"C680",'1'&x"C681",'1'&x"C682",'1'&x"C683",'1'&x"C684",'1'&x"C685",'1'&x"C686",'1'&x"C687",'1'&x"C688",'1'&x"C689",'1'&x"C68A",'1'&x"C68B",'1'&x"C68C",'1'&x"C68D",'1'&x"C68E",'1'&x"C68F",
+--'1'&x"C690",'1'&x"C691",'1'&x"C692",'1'&x"C693",'1'&x"C694",'1'&x"C695",'1'&x"C696",'1'&x"C697",'1'&x"C698",'1'&x"C699",'1'&x"C69A",'1'&x"C69B",'1'&x"C69C",'1'&x"C69D",'1'&x"C69E",'1'&x"C69F",
+--'1'&x"C6A0",'1'&x"C6A1",'1'&x"C6A2",'1'&x"C6A3",'1'&x"C6A4",'1'&x"C6A5",'1'&x"C6A6",'1'&x"C6A7",'1'&x"C6A8",'1'&x"C6A9",'1'&x"C6AA",'1'&x"C6AB",'1'&x"C6AC",'1'&x"C6AD",'1'&x"C6AE",'1'&x"C6AF",
+--'1'&x"C6B0",'1'&x"C6B1",'1'&x"C6B2",'1'&x"C6B3",'1'&x"C6B4",'1'&x"C6B5",'1'&x"C6B6",'1'&x"C6B7",'1'&x"C6B8",'1'&x"C6B9",'1'&x"C6BA",'1'&x"C6BB",'1'&x"C6BC",'1'&x"C6BD",'1'&x"C6BE",'1'&x"C6BF",
+--'1'&x"C6C0",'1'&x"C6C1",'1'&x"C6C2",'1'&x"C6C3",'1'&x"C6C4",'1'&x"C6C5",'1'&x"C6C6",'1'&x"C6C7",'1'&x"C6C8",'1'&x"C6C9",'1'&x"C6CA",'1'&x"C6CB",'1'&x"C6CC",'1'&x"C6CD",'1'&x"C6CE",'1'&x"C6CF",
+--'1'&x"C6D0",'1'&x"C6D1",'1'&x"C6D2",'1'&x"C6D3",'1'&x"C6D4",'1'&x"C6D5",'1'&x"C6D6",'1'&x"C6D7",'1'&x"C6D8",'1'&x"C6D9",'1'&x"C6DA",'1'&x"C6DB",'1'&x"C6DC",'1'&x"C6DD",'1'&x"C6DE",'1'&x"C6DF",
+--'1'&x"C6E0",'1'&x"C6E1",'1'&x"C6E2",'1'&x"C6E3",'1'&x"C6E4",'1'&x"C6E5",'1'&x"C6E6",'1'&x"C6E7",'1'&x"C6E8",'1'&x"C6E9",'1'&x"C6EA",'1'&x"C6EB",'1'&x"C6EC",'1'&x"C6ED",'1'&x"C6EE",'1'&x"C6EF",
+--'1'&x"C6F0",'1'&x"C6F1",'1'&x"C6F2",'1'&x"C6F3",'1'&x"C6F4",'1'&x"C6F5",'1'&x"C6F6",'1'&x"C6F7",'1'&x"C6F8",'1'&x"C6F9",'1'&x"C6FA",'1'&x"C6FB",'1'&x"C6FC",'1'&x"C6FD",'1'&x"C6FE",'1'&x"C6FF",
+--'1'&x"C700",'1'&x"C701",'1'&x"C702",'1'&x"C703",'1'&x"C704",'1'&x"C705",'1'&x"C706",'1'&x"C707",'1'&x"C708",'1'&x"C709",'1'&x"C70A",'1'&x"C70B",'1'&x"C70C",'1'&x"C70D",'1'&x"C70E",'1'&x"C70F",
+--'1'&x"C710",'1'&x"C711",'1'&x"C712",'1'&x"C713",'1'&x"C714",'1'&x"C715",'1'&x"C716",'1'&x"C717",'1'&x"C718",'1'&x"C719",'1'&x"C71A",'1'&x"C71B",'1'&x"C71C",'1'&x"C71D",'1'&x"C71E",'1'&x"C71F",
+--'1'&x"C720",'1'&x"C721",'1'&x"C722",'1'&x"C723",'1'&x"C724",'1'&x"C725",'1'&x"C726",'1'&x"C727",'1'&x"C728",'1'&x"C729",'1'&x"C72A",'1'&x"C72B",'1'&x"C72C",'1'&x"C72D",'1'&x"C72E",'1'&x"C72F",
+--'1'&x"C730",'1'&x"C731",'1'&x"C732",'1'&x"C733",'1'&x"C734",'1'&x"C735",'1'&x"C736",'1'&x"C737",'1'&x"C738",'1'&x"C739",'1'&x"C73A",'1'&x"C73B",'1'&x"C73C",'1'&x"C73D",'1'&x"C73E",'1'&x"C73F",
+--'1'&x"C740",'1'&x"C741",'1'&x"C742",'1'&x"C743",'1'&x"C744",'1'&x"C745",'1'&x"C746",'1'&x"C747",'1'&x"C748",'1'&x"C749",'1'&x"C74A",'1'&x"C74B",'1'&x"C74C",'1'&x"C74D",'1'&x"C74E",'1'&x"C74F",
+--'1'&x"C750",'1'&x"C751",'1'&x"C752",'1'&x"C753",'1'&x"C754",'1'&x"C755",'1'&x"C756",'1'&x"C757",'1'&x"C758",'1'&x"C759",'1'&x"C75A",'1'&x"C75B",'1'&x"C75C",'1'&x"C75D",'1'&x"C75E",'1'&x"C75F",
+--'1'&x"C760",'1'&x"C761",'1'&x"C762",'1'&x"C763",'1'&x"C764",'1'&x"C765",'1'&x"C766",'1'&x"C767",'1'&x"C768",'1'&x"C769",'1'&x"C76A",'1'&x"C76B",'1'&x"C76C",'1'&x"C76D",'1'&x"C76E",'1'&x"C76F",
+--'1'&x"C770",'1'&x"C771",'1'&x"C772",'1'&x"C773",'1'&x"C774",'1'&x"C775",'1'&x"C776",'1'&x"C777",'1'&x"C778",'1'&x"C779",'1'&x"C77A",'1'&x"C77B",'1'&x"C77C",'1'&x"C77D",'1'&x"C77E",'1'&x"C77F",
+--'1'&x"C780",'1'&x"C781",'1'&x"C782",'1'&x"C783",'1'&x"C784",'1'&x"C785",'1'&x"C786",'1'&x"C787",'1'&x"C788",'1'&x"C789",'1'&x"C78A",'1'&x"C78B",'1'&x"C78C",'1'&x"C78D",'1'&x"C78E",'1'&x"C78F",
+--'1'&x"C790",'1'&x"C791",'1'&x"C792",'1'&x"C793",'1'&x"C794",'1'&x"C795",'1'&x"C796",'1'&x"C797",'1'&x"C798",'1'&x"C799",'1'&x"C79A",'1'&x"C79B",'1'&x"C79C",'1'&x"C79D",'1'&x"C79E",'1'&x"C79F",
+--'1'&x"C7A0",'1'&x"C7A1",'1'&x"C7A2",'1'&x"C7A3",'1'&x"C7A4",'1'&x"C7A5",'1'&x"C7A6",'1'&x"C7A7",'1'&x"C7A8",'1'&x"C7A9",'1'&x"C7AA",'1'&x"C7AB",'1'&x"C7AC",'1'&x"C7AD",'1'&x"C7AE",'1'&x"C7AF",
+--'1'&x"C7B0",'1'&x"C7B1",'1'&x"C7B2",'1'&x"C7B3",'1'&x"C7B4",'1'&x"C7B5",'1'&x"C7B6",'1'&x"C7B7",'1'&x"C7B8",'1'&x"C7B9",'1'&x"C7BA",'1'&x"C7BB",'1'&x"C7BC",'1'&x"C7BD",'1'&x"C7BE",'1'&x"C7BF",
+--'1'&x"C7C0",'1'&x"C7C1",'1'&x"C7C2",'1'&x"C7C3",'1'&x"C7C4",'1'&x"C7C5",'1'&x"C7C6",'1'&x"C7C7",'1'&x"C7C8",'1'&x"C7C9",'1'&x"C7CA",'1'&x"C7CB",'1'&x"C7CC",'1'&x"C7CD",'1'&x"C7CE",'1'&x"C7CF",
+--'1'&x"C7D0",'1'&x"C7D1",'1'&x"C7D2",'1'&x"C7D3",'1'&x"C7D4",'1'&x"C7D5",'1'&x"C7D6",'1'&x"C7D7",'1'&x"C7D8",'1'&x"C7D9",'1'&x"C7DA",'1'&x"C7DB",'1'&x"C7DC",'1'&x"C7DD",'1'&x"C7DE",'1'&x"C7DF",
+--'1'&x"C7E0",'1'&x"C7E1",'1'&x"C7E2",'1'&x"C7E3",'1'&x"C7E4",'1'&x"C7E5",'1'&x"C7E6",'1'&x"C7E7",'1'&x"C7E8",'1'&x"C7E9",'1'&x"C7EA",'1'&x"C7EB",'1'&x"C7EC",'1'&x"C7ED",'1'&x"C7EE",'1'&x"C7EF",
+--'1'&x"C7F0",'1'&x"C7F1",'1'&x"C7F2",'1'&x"C7F3",'1'&x"C7F4",'1'&x"C7F5",'1'&x"C7F6",'1'&x"C7F7",'1'&x"C7F8",'1'&x"C7F9",'1'&x"C7FA",'1'&x"C7FB",'1'&x"C7FC",'1'&x"C7FD",'1'&x"C7FE",'1'&x"C7FF",
+--'1'&x"C800",'1'&x"C801",'1'&x"C802",'1'&x"C803",'1'&x"C804",'1'&x"C805",'1'&x"C806",'1'&x"C807",'1'&x"C808",'1'&x"C809",'1'&x"C80A",'1'&x"C80B",'1'&x"C80C",'1'&x"C80D",'1'&x"C80E",'1'&x"C80F",
+--'1'&x"C810",'1'&x"C811",'1'&x"C812",'1'&x"C813",'1'&x"C814",'1'&x"C815",'1'&x"C816",'1'&x"C817",'1'&x"C818",'1'&x"C819",'1'&x"C81A",'1'&x"C81B",'1'&x"C81C",'1'&x"C81D",'1'&x"C81E",'1'&x"C81F",
+--'1'&x"C820",'1'&x"C821",'1'&x"C822",'1'&x"C823",'1'&x"C824",'1'&x"C825",'1'&x"C826",'1'&x"C827",'1'&x"C828",'1'&x"C829",'1'&x"C82A",'1'&x"C82B",'1'&x"C82C",'1'&x"C82D",'1'&x"C82E",'1'&x"C82F",
+--'1'&x"C830",'1'&x"C831",'1'&x"C832",'1'&x"C833",'1'&x"C834",'1'&x"C835",'1'&x"C836",'1'&x"C837",'1'&x"C838",'1'&x"C839",'1'&x"C83A",'1'&x"C83B",'1'&x"C83C",'1'&x"C83D",'1'&x"C83E",'1'&x"C83F",
+--'1'&x"C840",'1'&x"C841",'1'&x"C842",'1'&x"C843",'1'&x"C844",'1'&x"C845",'1'&x"C846",'1'&x"C847",'1'&x"C848",'1'&x"C849",'1'&x"C84A",'1'&x"C84B",'1'&x"C84C",'1'&x"C84D",'1'&x"C84E",'1'&x"C84F",
+--'1'&x"C850",'1'&x"C851",'1'&x"C852",'1'&x"C853",'1'&x"C854",'1'&x"C855",'1'&x"C856",'1'&x"C857",'1'&x"C858",'1'&x"C859",'1'&x"C85A",'1'&x"C85B",'1'&x"C85C",'1'&x"C85D",'1'&x"C85E",'1'&x"C85F",
+--'1'&x"C860",'1'&x"C861",'1'&x"C862",'1'&x"C863",'1'&x"C864",'1'&x"C865",'1'&x"C866",'1'&x"C867",'1'&x"C868",'1'&x"C869",'1'&x"C86A",'1'&x"C86B",'1'&x"C86C",'1'&x"C86D",'1'&x"C86E",'1'&x"C86F",
+--'1'&x"C870",'1'&x"C871",'1'&x"C872",'1'&x"C873",'1'&x"C874",'1'&x"C875",'1'&x"C876",'1'&x"C877",'1'&x"C878",'1'&x"C879",'1'&x"C87A",'1'&x"C87B",'1'&x"C87C",'1'&x"C87D",'1'&x"C87E",'1'&x"C87F",
+--'1'&x"C880",'1'&x"C881",'1'&x"C882",'1'&x"C883",'1'&x"C884",'1'&x"C885",'1'&x"C886",'1'&x"C887",'1'&x"C888",'1'&x"C889",'1'&x"C88A",'1'&x"C88B",'1'&x"C88C",'1'&x"C88D",'1'&x"C88E",'1'&x"C88F",
+--'1'&x"C890",'1'&x"C891",'1'&x"C892",'1'&x"C893",'1'&x"C894",'1'&x"C895",'1'&x"C896",'1'&x"C897",'1'&x"C898",'1'&x"C899",'1'&x"C89A",'1'&x"C89B",'1'&x"C89C",'1'&x"C89D",'1'&x"C89E",'1'&x"C89F",
+--'1'&x"C8A0",'1'&x"C8A1",'1'&x"C8A2",'1'&x"C8A3",'1'&x"C8A4",'1'&x"C8A5",'1'&x"C8A6",'1'&x"C8A7",'1'&x"C8A8",'1'&x"C8A9",'1'&x"C8AA",'1'&x"C8AB",'1'&x"C8AC",'1'&x"C8AD",'1'&x"C8AE",'1'&x"C8AF",
+--'1'&x"C8B0",'1'&x"C8B1",'1'&x"C8B2",'1'&x"C8B3",'1'&x"C8B4",'1'&x"C8B5",'1'&x"C8B6",'1'&x"C8B7",'1'&x"C8B8",'1'&x"C8B9",'1'&x"C8BA",'1'&x"C8BB",'1'&x"C8BC",'1'&x"C8BD",'1'&x"C8BE",'1'&x"C8BF",
+--'1'&x"C8C0",'1'&x"C8C1",'1'&x"C8C2",'1'&x"C8C3",'1'&x"C8C4",'1'&x"C8C5",'1'&x"C8C6",'1'&x"C8C7",'1'&x"C8C8",'1'&x"C8C9",'1'&x"C8CA",'1'&x"C8CB",'1'&x"C8CC",'1'&x"C8CD",'1'&x"C8CE",'1'&x"C8CF",
+--'1'&x"C8D0",'1'&x"C8D1",'1'&x"C8D2",'1'&x"C8D3",'1'&x"C8D4",'1'&x"C8D5",'1'&x"C8D6",'1'&x"C8D7",'1'&x"C8D8",'1'&x"C8D9",'1'&x"C8DA",'1'&x"C8DB",'1'&x"C8DC",'1'&x"C8DD",'1'&x"C8DE",'1'&x"C8DF",
+--'1'&x"C8E0",'1'&x"C8E1",'1'&x"C8E2",'1'&x"C8E3",'1'&x"C8E4",'1'&x"C8E5",'1'&x"C8E6",'1'&x"C8E7",'1'&x"C8E8",'1'&x"C8E9",'1'&x"C8EA",'1'&x"C8EB",'1'&x"C8EC",'1'&x"C8ED",'1'&x"C8EE",'1'&x"C8EF",
+--'1'&x"C8F0",'1'&x"C8F1",'1'&x"C8F2",'1'&x"C8F3",'1'&x"C8F4",'1'&x"C8F5",'1'&x"C8F6",'1'&x"C8F7",'1'&x"C8F8",'1'&x"C8F9",'1'&x"C8FA",'1'&x"C8FB",'1'&x"C8FC",'1'&x"C8FD",'1'&x"C8FE",'1'&x"C8FF",
+--'1'&x"C900",'1'&x"C901",'1'&x"C902",'1'&x"C903",'1'&x"C904",'1'&x"C905",'1'&x"C906",'1'&x"C907",'1'&x"C908",'1'&x"C909",'1'&x"C90A",'1'&x"C90B",'1'&x"C90C",'1'&x"C90D",'1'&x"C90E",'1'&x"C90F",
+--'1'&x"C910",'1'&x"C911",'1'&x"C912",'1'&x"C913",'1'&x"C914",'1'&x"C915",'1'&x"C916",'1'&x"C917",'1'&x"C918",'1'&x"C919",'1'&x"C91A",'1'&x"C91B",'1'&x"C91C",'1'&x"C91D",'1'&x"C91E",'1'&x"C91F",
+--'1'&x"C920",'1'&x"C921",'1'&x"C922",'1'&x"C923",'1'&x"C924",'1'&x"C925",'1'&x"C926",'1'&x"C927",'1'&x"C928",'1'&x"C929",'1'&x"C92A",'1'&x"C92B",'1'&x"C92C",'1'&x"C92D",'1'&x"C92E",'1'&x"C92F",
+--'1'&x"C930",'1'&x"C931",'1'&x"C932",'1'&x"C933",'1'&x"C934",'1'&x"C935",'1'&x"C936",'1'&x"C937",'1'&x"C938",'1'&x"C939",'1'&x"C93A",'1'&x"C93B",'1'&x"C93C",'1'&x"C93D",'1'&x"C93E",'1'&x"C93F",
+--'1'&x"C940",'1'&x"C941",'1'&x"C942",'1'&x"C943",'1'&x"C944",'1'&x"C945",'1'&x"C946",'1'&x"C947",'1'&x"C948",'1'&x"C949",'1'&x"C94A",'1'&x"C94B",'1'&x"C94C",'1'&x"C94D",'1'&x"C94E",'1'&x"C94F",
+--'1'&x"C950",'1'&x"C951",'1'&x"C952",'1'&x"C953",'1'&x"C954",'1'&x"C955",'1'&x"C956",'1'&x"C957",'1'&x"C958",'1'&x"C959",'1'&x"C95A",'1'&x"C95B",'1'&x"C95C",'1'&x"C95D",'1'&x"C95E",'1'&x"C95F",
+--'1'&x"C960",'1'&x"C961",'1'&x"C962",'1'&x"C963",'1'&x"C964",'1'&x"C965",'1'&x"C966",'1'&x"C967",'1'&x"C968",'1'&x"C969",'1'&x"C96A",'1'&x"C96B",'1'&x"C96C",'1'&x"C96D",'1'&x"C96E",'1'&x"C96F",
+--'1'&x"C970",'1'&x"C971",'1'&x"C972",'1'&x"C973",'1'&x"C974",'1'&x"C975",'1'&x"C976",'1'&x"C977",'1'&x"C978",'1'&x"C979",'1'&x"C97A",'1'&x"C97B",'1'&x"C97C",'1'&x"C97D",'1'&x"C97E",'1'&x"C97F",
+--'1'&x"C980",'1'&x"C981",'1'&x"C982",'1'&x"C983",'1'&x"C984",'1'&x"C985",'1'&x"C986",'1'&x"C987",'1'&x"C988",'1'&x"C989",'1'&x"C98A",'1'&x"C98B",'1'&x"C98C",'1'&x"C98D",'1'&x"C98E",'1'&x"C98F",
+--'1'&x"C990",'1'&x"C991",'1'&x"C992",'1'&x"C993",'1'&x"C994",'1'&x"C995",'1'&x"C996",'1'&x"C997",'1'&x"C998",'1'&x"C999",'1'&x"C99A",'1'&x"C99B",'1'&x"C99C",'1'&x"C99D",'1'&x"C99E",'1'&x"C99F",
+--'1'&x"C9A0",'1'&x"C9A1",'1'&x"C9A2",'1'&x"C9A3",'1'&x"C9A4",'1'&x"C9A5",'1'&x"C9A6",'1'&x"C9A7",'1'&x"C9A8",'1'&x"C9A9",'1'&x"C9AA",'1'&x"C9AB",'1'&x"C9AC",'1'&x"C9AD",'1'&x"C9AE",'1'&x"C9AF",
+--'1'&x"C9B0",'1'&x"C9B1",'1'&x"C9B2",'1'&x"C9B3",'1'&x"C9B4",'1'&x"C9B5",'1'&x"C9B6",'1'&x"C9B7",'1'&x"C9B8",'1'&x"C9B9",'1'&x"C9BA",'1'&x"C9BB",'1'&x"C9BC",'1'&x"C9BD",'1'&x"C9BE",'1'&x"C9BF",
+--'1'&x"C9C0",'1'&x"C9C1",'1'&x"C9C2",'1'&x"C9C3",'1'&x"C9C4",'1'&x"C9C5",'1'&x"C9C6",'1'&x"C9C7",'1'&x"C9C8",'1'&x"C9C9",'1'&x"C9CA",'1'&x"C9CB",'1'&x"C9CC",'1'&x"C9CD",'1'&x"C9CE",'1'&x"C9CF",
+--'1'&x"C9D0",'1'&x"C9D1",'1'&x"C9D2",'1'&x"C9D3",'1'&x"C9D4",'1'&x"C9D5",'1'&x"C9D6",'1'&x"C9D7",'1'&x"C9D8",'1'&x"C9D9",'1'&x"C9DA",'1'&x"C9DB",'1'&x"C9DC",'1'&x"C9DD",'1'&x"C9DE",'1'&x"C9DF",
+--'1'&x"C9E0",'1'&x"C9E1",'1'&x"C9E2",'1'&x"C9E3",'1'&x"C9E4",'1'&x"C9E5",'1'&x"C9E6",'1'&x"C9E7",'1'&x"C9E8",'1'&x"C9E9",'1'&x"C9EA",'1'&x"C9EB",'1'&x"C9EC",'1'&x"C9ED",'1'&x"C9EE",'1'&x"C9EF",
+--'1'&x"C9F0",'1'&x"C9F1",'1'&x"C9F2",'1'&x"C9F3",'1'&x"C9F4",'1'&x"C9F5",'1'&x"C9F6",'1'&x"C9F7",'1'&x"C9F8",'1'&x"C9F9",'1'&x"C9FA",'1'&x"C9FB",'1'&x"C9FC",'1'&x"C9FD",'1'&x"C9FE",'1'&x"C9FF",
+--'1'&x"CA00",'1'&x"CA01",'1'&x"CA02",'1'&x"CA03",'1'&x"CA04",'1'&x"CA05",'1'&x"CA06",'1'&x"CA07",'1'&x"CA08",'1'&x"CA09",'1'&x"CA0A",'1'&x"CA0B",'1'&x"CA0C",'1'&x"CA0D",'1'&x"CA0E",'1'&x"CA0F",
+--'1'&x"CA10",'1'&x"CA11",'1'&x"CA12",'1'&x"CA13",'1'&x"CA14",'1'&x"CA15",'1'&x"CA16",'1'&x"CA17",'1'&x"CA18",'1'&x"CA19",'1'&x"CA1A",'1'&x"CA1B",'1'&x"CA1C",'1'&x"CA1D",'1'&x"CA1E",'1'&x"CA1F",
+--'1'&x"CA20",'1'&x"CA21",'1'&x"CA22",'1'&x"CA23",'1'&x"CA24",'1'&x"CA25",'1'&x"CA26",'1'&x"CA27",'1'&x"CA28",'1'&x"CA29",'1'&x"CA2A",'1'&x"CA2B",'1'&x"CA2C",'1'&x"CA2D",'1'&x"CA2E",'1'&x"CA2F",
+--'1'&x"CA30",'1'&x"CA31",'1'&x"CA32",'1'&x"CA33",'1'&x"CA34",'1'&x"CA35",'1'&x"CA36",'1'&x"CA37",'1'&x"CA38",'1'&x"CA39",'1'&x"CA3A",'1'&x"CA3B",'1'&x"CA3C",'1'&x"CA3D",'1'&x"CA3E",'1'&x"CA3F",
+--'1'&x"CA40",'1'&x"CA41",'1'&x"CA42",'1'&x"CA43",'1'&x"CA44",'1'&x"CA45",'1'&x"CA46",'1'&x"CA47",'1'&x"CA48",'1'&x"CA49",'1'&x"CA4A",'1'&x"CA4B",'1'&x"CA4C",'1'&x"CA4D",'1'&x"CA4E",'1'&x"CA4F",
+--'1'&x"CA50",'1'&x"CA51",'1'&x"CA52",'1'&x"CA53",'1'&x"CA54",'1'&x"CA55",'1'&x"CA56",'1'&x"CA57",'1'&x"CA58",'1'&x"CA59",'1'&x"CA5A",'1'&x"CA5B",'1'&x"CA5C",'1'&x"CA5D",'1'&x"CA5E",'1'&x"CA5F",
+--'1'&x"CA60",'1'&x"CA61",'1'&x"CA62",'1'&x"CA63",'1'&x"CA64",'1'&x"CA65",'1'&x"CA66",'1'&x"CA67",'1'&x"CA68",'1'&x"CA69",'1'&x"CA6A",'1'&x"CA6B",'1'&x"CA6C",'1'&x"CA6D",'1'&x"CA6E",'1'&x"CA6F",
+--'1'&x"CA70",'1'&x"CA71",'1'&x"CA72",'1'&x"CA73",'1'&x"CA74",'1'&x"CA75",'1'&x"CA76",'1'&x"CA77",'1'&x"CA78",'1'&x"CA79",'1'&x"CA7A",'1'&x"CA7B",'1'&x"CA7C",'1'&x"CA7D",'1'&x"CA7E",'1'&x"CA7F",
+--'1'&x"CA80",'1'&x"CA81",'1'&x"CA82",'1'&x"CA83",'1'&x"CA84",'1'&x"CA85",'1'&x"CA86",'1'&x"CA87",'1'&x"CA88",'1'&x"CA89",'1'&x"CA8A",'1'&x"CA8B",'1'&x"CA8C",'1'&x"CA8D",'1'&x"CA8E",'1'&x"CA8F",
+--'1'&x"CA90",'1'&x"CA91",'1'&x"CA92",'1'&x"CA93",'1'&x"CA94",'1'&x"CA95",'1'&x"CA96",'1'&x"CA97",'1'&x"CA98",'1'&x"CA99",'1'&x"CA9A",'1'&x"CA9B",'1'&x"CA9C",'1'&x"CA9D",'1'&x"CA9E",'1'&x"CA9F",
+--'1'&x"CAA0",'1'&x"CAA1",'1'&x"CAA2",'1'&x"CAA3",'1'&x"CAA4",'1'&x"CAA5",'1'&x"CAA6",'1'&x"CAA7",'1'&x"CAA8",'1'&x"CAA9",'1'&x"CAAA",'1'&x"CAAB",'1'&x"CAAC",'1'&x"CAAD",'1'&x"CAAE",'1'&x"CAAF",
+--'1'&x"CAB0",'1'&x"CAB1",'1'&x"CAB2",'1'&x"CAB3",'1'&x"CAB4",'1'&x"CAB5",'1'&x"CAB6",'1'&x"CAB7",'1'&x"CAB8",'1'&x"CAB9",'1'&x"CABA",'1'&x"CABB",'1'&x"CABC",'1'&x"CABD",'1'&x"CABE",'1'&x"CABF",
+--'1'&x"CAC0",'1'&x"CAC1",'1'&x"CAC2",'1'&x"CAC3",'1'&x"CAC4",'1'&x"CAC5",'1'&x"CAC6",'1'&x"CAC7",'1'&x"CAC8",'1'&x"CAC9",'1'&x"CACA",'1'&x"CACB",'1'&x"CACC",'1'&x"CACD",'1'&x"CACE",'1'&x"CACF",
+--'1'&x"CAD0",'1'&x"CAD1",'1'&x"CAD2",'1'&x"CAD3",'1'&x"CAD4",'1'&x"CAD5",'1'&x"CAD6",'1'&x"CAD7",'1'&x"CAD8",'1'&x"CAD9",'1'&x"CADA",'1'&x"CADB",'1'&x"CADC",'1'&x"CADD",'1'&x"CADE",'1'&x"CADF",
+--'1'&x"CAE0",'1'&x"CAE1",'1'&x"CAE2",'1'&x"CAE3",'1'&x"CAE4",'1'&x"CAE5",'1'&x"CAE6",'1'&x"CAE7",'1'&x"CAE8",'1'&x"CAE9",'1'&x"CAEA",'1'&x"CAEB",'1'&x"CAEC",'1'&x"CAED",'1'&x"CAEE",'1'&x"CAEF",
+--'1'&x"CAF0",'1'&x"CAF1",'1'&x"CAF2",'1'&x"CAF3",'1'&x"CAF4",'1'&x"CAF5",'1'&x"CAF6",'1'&x"CAF7",'1'&x"CAF8",'1'&x"CAF9",'1'&x"CAFA",'1'&x"CAFB",'1'&x"CAFC",'1'&x"CAFD",'1'&x"CAFE",'1'&x"CAFF",
+--'1'&x"CB00",'1'&x"CB01",'1'&x"CB02",'1'&x"CB03",'1'&x"CB04",'1'&x"CB05",'1'&x"CB06",'1'&x"CB07",'1'&x"CB08",'1'&x"CB09",'1'&x"CB0A",'1'&x"CB0B",'1'&x"CB0C",'1'&x"CB0D",'1'&x"CB0E",'1'&x"CB0F",
+--'1'&x"CB10",'1'&x"CB11",'1'&x"CB12",'1'&x"CB13",'1'&x"CB14",'1'&x"CB15",'1'&x"CB16",'1'&x"CB17",'1'&x"CB18",'1'&x"CB19",'1'&x"CB1A",'1'&x"CB1B",'1'&x"CB1C",'1'&x"CB1D",'1'&x"CB1E",'1'&x"CB1F",
+--'1'&x"CB20",'1'&x"CB21",'1'&x"CB22",'1'&x"CB23",'1'&x"CB24",'1'&x"CB25",'1'&x"CB26",'1'&x"CB27",'1'&x"CB28",'1'&x"CB29",'1'&x"CB2A",'1'&x"CB2B",'1'&x"CB2C",'1'&x"CB2D",'1'&x"CB2E",'1'&x"CB2F",
+--'1'&x"CB30",'1'&x"CB31",'1'&x"CB32",'1'&x"CB33",'1'&x"CB34",'1'&x"CB35",'1'&x"CB36",'1'&x"CB37",'1'&x"CB38",'1'&x"CB39",'1'&x"CB3A",'1'&x"CB3B",'1'&x"CB3C",'1'&x"CB3D",'1'&x"CB3E",'1'&x"CB3F",
+--'1'&x"CB40",'1'&x"CB41",'1'&x"CB42",'1'&x"CB43",'1'&x"CB44",'1'&x"CB45",'1'&x"CB46",'1'&x"CB47",'1'&x"CB48",'1'&x"CB49",'1'&x"CB4A",'1'&x"CB4B",'1'&x"CB4C",'1'&x"CB4D",'1'&x"CB4E",'1'&x"CB4F",
+--'1'&x"CB50",'1'&x"CB51",'1'&x"CB52",'1'&x"CB53",'1'&x"CB54",'1'&x"CB55",'1'&x"CB56",'1'&x"CB57",'1'&x"CB58",'1'&x"CB59",'1'&x"CB5A",'1'&x"CB5B",'1'&x"CB5C",'1'&x"CB5D",'1'&x"CB5E",'1'&x"CB5F",
+--'1'&x"CB60",'1'&x"CB61",'1'&x"CB62",'1'&x"CB63",'1'&x"CB64",'1'&x"CB65",'1'&x"CB66",'1'&x"CB67",'1'&x"CB68",'1'&x"CB69",'1'&x"CB6A",'1'&x"CB6B",'1'&x"CB6C",'1'&x"CB6D",'1'&x"CB6E",'1'&x"CB6F",
+--'1'&x"CB70",'1'&x"CB71",'1'&x"CB72",'1'&x"CB73",'1'&x"CB74",'1'&x"CB75",'1'&x"CB76",'1'&x"CB77",'1'&x"CB78",'1'&x"CB79",'1'&x"CB7A",'1'&x"CB7B",'1'&x"CB7C",'1'&x"CB7D",'1'&x"CB7E",'1'&x"CB7F",
+--'1'&x"CB80",'1'&x"CB81",'1'&x"CB82",'1'&x"CB83",'1'&x"CB84",'1'&x"CB85",'1'&x"CB86",'1'&x"CB87",'1'&x"CB88",'1'&x"CB89",'1'&x"CB8A",'1'&x"CB8B",'1'&x"CB8C",'1'&x"CB8D",'1'&x"CB8E",'1'&x"CB8F",
+--'1'&x"CB90",'1'&x"CB91",'1'&x"CB92",'1'&x"CB93",'1'&x"CB94",'1'&x"CB95",'1'&x"CB96",'1'&x"CB97",'1'&x"CB98",'1'&x"CB99",'1'&x"CB9A",'1'&x"CB9B",'1'&x"CB9C",'1'&x"CB9D",'1'&x"CB9E",'1'&x"CB9F",
+--'1'&x"CBA0",'1'&x"CBA1",'1'&x"CBA2",'1'&x"CBA3",'1'&x"CBA4",'1'&x"CBA5",'1'&x"CBA6",'1'&x"CBA7",'1'&x"CBA8",'1'&x"CBA9",'1'&x"CBAA",'1'&x"CBAB",'1'&x"CBAC",'1'&x"CBAD",'1'&x"CBAE",'1'&x"CBAF",
+--'1'&x"CBB0",'1'&x"CBB1",'1'&x"CBB2",'1'&x"CBB3",'1'&x"CBB4",'1'&x"CBB5",'1'&x"CBB6",'1'&x"CBB7",'1'&x"CBB8",'1'&x"CBB9",'1'&x"CBBA",'1'&x"CBBB",'1'&x"CBBC",'1'&x"CBBD",'1'&x"CBBE",'1'&x"CBBF",
+--'1'&x"CBC0",'1'&x"CBC1",'1'&x"CBC2",'1'&x"CBC3",'1'&x"CBC4",'1'&x"CBC5",'1'&x"CBC6",'1'&x"CBC7",'1'&x"CBC8",'1'&x"CBC9",'1'&x"CBCA",'1'&x"CBCB",'1'&x"CBCC",'1'&x"CBCD",'1'&x"CBCE",'1'&x"CBCF",
+--'1'&x"CBD0",'1'&x"CBD1",'1'&x"CBD2",'1'&x"CBD3",'1'&x"CBD4",'1'&x"CBD5",'1'&x"CBD6",'1'&x"CBD7",'1'&x"CBD8",'1'&x"CBD9",'1'&x"CBDA",'1'&x"CBDB",'1'&x"CBDC",'1'&x"CBDD",'1'&x"CBDE",'1'&x"CBDF",
+--'1'&x"CBE0",'1'&x"CBE1",'1'&x"CBE2",'1'&x"CBE3",'1'&x"CBE4",'1'&x"CBE5",'1'&x"CBE6",'1'&x"CBE7",'1'&x"CBE8",'1'&x"CBE9",'1'&x"CBEA",'1'&x"CBEB",'1'&x"CBEC",'1'&x"CBED",'1'&x"CBEE",'1'&x"CBEF",
+--'1'&x"CBF0",'1'&x"CBF1",'1'&x"CBF2",'1'&x"CBF3",'1'&x"CBF4",'1'&x"CBF5",'1'&x"CBF6",'1'&x"CBF7",'1'&x"CBF8",'1'&x"CBF9",'1'&x"CBFA",'1'&x"CBFB",'1'&x"CBFC",'1'&x"CBFD",'1'&x"CBFE",'1'&x"CBFF",
+--'1'&x"CC00",'1'&x"CC01",'1'&x"CC02",'1'&x"CC03",'1'&x"CC04",'1'&x"CC05",'1'&x"CC06",'1'&x"CC07",'1'&x"CC08",'1'&x"CC09",'1'&x"CC0A",'1'&x"CC0B",'1'&x"CC0C",'1'&x"CC0D",'1'&x"CC0E",'1'&x"CC0F",
+--'1'&x"CC10",'1'&x"CC11",'1'&x"CC12",'1'&x"CC13",'1'&x"CC14",'1'&x"CC15",'1'&x"CC16",'1'&x"CC17",'1'&x"CC18",'1'&x"CC19",'1'&x"CC1A",'1'&x"CC1B",'1'&x"CC1C",'1'&x"CC1D",'1'&x"CC1E",'1'&x"CC1F",
+--'1'&x"CC20",'1'&x"CC21",'1'&x"CC22",'1'&x"CC23",'1'&x"CC24",'1'&x"CC25",'1'&x"CC26",'1'&x"CC27",'1'&x"CC28",'1'&x"CC29",'1'&x"CC2A",'1'&x"CC2B",'1'&x"CC2C",'1'&x"CC2D",'1'&x"CC2E",'1'&x"CC2F",
+--'1'&x"CC30",'1'&x"CC31",'1'&x"CC32",'1'&x"CC33",'1'&x"CC34",'1'&x"CC35",'1'&x"CC36",'1'&x"CC37",'1'&x"CC38",'1'&x"CC39",'1'&x"CC3A",'1'&x"CC3B",'1'&x"CC3C",'1'&x"CC3D",'1'&x"CC3E",'1'&x"CC3F",
+--'1'&x"CC40",'1'&x"CC41",'1'&x"CC42",'1'&x"CC43",'1'&x"CC44",'1'&x"CC45",'1'&x"CC46",'1'&x"CC47",'1'&x"CC48",'1'&x"CC49",'1'&x"CC4A",'1'&x"CC4B",'1'&x"CC4C",'1'&x"CC4D",'1'&x"CC4E",'1'&x"CC4F",
+--'1'&x"CC50",'1'&x"CC51",'1'&x"CC52",'1'&x"CC53",'1'&x"CC54",'1'&x"CC55",'1'&x"CC56",'1'&x"CC57",'1'&x"CC58",'1'&x"CC59",'1'&x"CC5A",'1'&x"CC5B",'1'&x"CC5C",'1'&x"CC5D",'1'&x"CC5E",'1'&x"CC5F",
+--'1'&x"CC60",'1'&x"CC61",'1'&x"CC62",'1'&x"CC63",'1'&x"CC64",'1'&x"CC65",'1'&x"CC66",'1'&x"CC67",'1'&x"CC68",'1'&x"CC69",'1'&x"CC6A",'1'&x"CC6B",'1'&x"CC6C",'1'&x"CC6D",'1'&x"CC6E",'1'&x"CC6F",
+--'1'&x"CC70",'1'&x"CC71",'1'&x"CC72",'1'&x"CC73",'1'&x"CC74",'1'&x"CC75",'1'&x"CC76",'1'&x"CC77",'1'&x"CC78",'1'&x"CC79",'1'&x"CC7A",'1'&x"CC7B",'1'&x"CC7C",'1'&x"CC7D",'1'&x"CC7E",'1'&x"CC7F",
+--'1'&x"CC80",'1'&x"CC81",'1'&x"CC82",'1'&x"CC83",'1'&x"CC84",'1'&x"CC85",'1'&x"CC86",'1'&x"CC87",'1'&x"CC88",'1'&x"CC89",'1'&x"CC8A",'1'&x"CC8B",'1'&x"CC8C",'1'&x"CC8D",'1'&x"CC8E",'1'&x"CC8F",
+--'1'&x"CC90",'1'&x"CC91",'1'&x"CC92",'1'&x"CC93",'1'&x"CC94",'1'&x"CC95",'1'&x"CC96",'1'&x"CC97",'1'&x"CC98",'1'&x"CC99",'1'&x"CC9A",'1'&x"CC9B",'1'&x"CC9C",'1'&x"CC9D",'1'&x"CC9E",'1'&x"CC9F",
+--'1'&x"CCA0",'1'&x"CCA1",'1'&x"CCA2",'1'&x"CCA3",'1'&x"CCA4",'1'&x"CCA5",'1'&x"CCA6",'1'&x"CCA7",'1'&x"CCA8",'1'&x"CCA9",'1'&x"CCAA",'1'&x"CCAB",'1'&x"CCAC",'1'&x"CCAD",'1'&x"CCAE",'1'&x"CCAF",
+--'1'&x"CCB0",'1'&x"CCB1",'1'&x"CCB2",'1'&x"CCB3",'1'&x"CCB4",'1'&x"CCB5",'1'&x"CCB6",'1'&x"CCB7",'1'&x"CCB8",'1'&x"CCB9",'1'&x"CCBA",'1'&x"CCBB",'1'&x"CCBC",'1'&x"CCBD",'1'&x"CCBE",'1'&x"CCBF",
+--'1'&x"CCC0",'1'&x"CCC1",'1'&x"CCC2",'1'&x"CCC3",'1'&x"CCC4",'1'&x"CCC5",'1'&x"CCC6",'1'&x"CCC7",'1'&x"CCC8",'1'&x"CCC9",'1'&x"CCCA",'1'&x"CCCB",'1'&x"CCCC",'1'&x"CCCD",'1'&x"CCCE",'1'&x"CCCF",
+--'1'&x"CCD0",'1'&x"CCD1",'1'&x"CCD2",'1'&x"CCD3",'1'&x"CCD4",'1'&x"CCD5",'1'&x"CCD6",'1'&x"CCD7",'1'&x"CCD8",'1'&x"CCD9",'1'&x"CCDA",'1'&x"CCDB",'1'&x"CCDC",'1'&x"CCDD",'1'&x"CCDE",'1'&x"CCDF",
+--'1'&x"CCE0",'1'&x"CCE1",'1'&x"CCE2",'1'&x"CCE3",'1'&x"CCE4",'1'&x"CCE5",'1'&x"CCE6",'1'&x"CCE7",'1'&x"CCE8",'1'&x"CCE9",'1'&x"CCEA",'1'&x"CCEB",'1'&x"CCEC",'1'&x"CCED",'1'&x"CCEE",'1'&x"CCEF",
+--'1'&x"CCF0",'1'&x"CCF1",'1'&x"CCF2",'1'&x"CCF3",'1'&x"CCF4",'1'&x"CCF5",'1'&x"CCF6",'1'&x"CCF7",'1'&x"CCF8",'1'&x"CCF9",'1'&x"CCFA",'1'&x"CCFB",'1'&x"CCFC",'1'&x"CCFD",'1'&x"CCFE",'1'&x"CCFF",
+--'1'&x"CD00",'1'&x"CD01",'1'&x"CD02",'1'&x"CD03",'1'&x"CD04",'1'&x"CD05",'1'&x"CD06",'1'&x"CD07",'1'&x"CD08",'1'&x"CD09",'1'&x"CD0A",'1'&x"CD0B",'1'&x"CD0C",'1'&x"CD0D",'1'&x"CD0E",'1'&x"CD0F",
+--'1'&x"CD10",'1'&x"CD11",'1'&x"CD12",'1'&x"CD13",'1'&x"CD14",'1'&x"CD15",'1'&x"CD16",'1'&x"CD17",'1'&x"CD18",'1'&x"CD19",'1'&x"CD1A",'1'&x"CD1B",'1'&x"CD1C",'1'&x"CD1D",'1'&x"CD1E",'1'&x"CD1F",
+--'1'&x"CD20",'1'&x"CD21",'1'&x"CD22",'1'&x"CD23",'1'&x"CD24",'1'&x"CD25",'1'&x"CD26",'1'&x"CD27",'1'&x"CD28",'1'&x"CD29",'1'&x"CD2A",'1'&x"CD2B",'1'&x"CD2C",'1'&x"CD2D",'1'&x"CD2E",'1'&x"CD2F",
+--'1'&x"CD30",'1'&x"CD31",'1'&x"CD32",'1'&x"CD33",'1'&x"CD34",'1'&x"CD35",'1'&x"CD36",'1'&x"CD37",'1'&x"CD38",'1'&x"CD39",'1'&x"CD3A",'1'&x"CD3B",'1'&x"CD3C",'1'&x"CD3D",'1'&x"CD3E",'1'&x"CD3F",
+--'1'&x"CD40",'1'&x"CD41",'1'&x"CD42",'1'&x"CD43",'1'&x"CD44",'1'&x"CD45",'1'&x"CD46",'1'&x"CD47",'1'&x"CD48",'1'&x"CD49",'1'&x"CD4A",'1'&x"CD4B",'1'&x"CD4C",'1'&x"CD4D",'1'&x"CD4E",'1'&x"CD4F",
+--'1'&x"CD50",'1'&x"CD51",'1'&x"CD52",'1'&x"CD53",'1'&x"CD54",'1'&x"CD55",'1'&x"CD56",'1'&x"CD57",'1'&x"CD58",'1'&x"CD59",'1'&x"CD5A",'1'&x"CD5B",'1'&x"CD5C",'1'&x"CD5D",'1'&x"CD5E",'1'&x"CD5F",
+--'1'&x"CD60",'1'&x"CD61",'1'&x"CD62",'1'&x"CD63",'1'&x"CD64",'1'&x"CD65",'1'&x"CD66",'1'&x"CD67",'1'&x"CD68",'1'&x"CD69",'1'&x"CD6A",'1'&x"CD6B",'1'&x"CD6C",'1'&x"CD6D",'1'&x"CD6E",'1'&x"CD6F",
+--'1'&x"CD70",'1'&x"CD71",'1'&x"CD72",'1'&x"CD73",'1'&x"CD74",'1'&x"CD75",'1'&x"CD76",'1'&x"CD77",'1'&x"CD78",'1'&x"CD79",'1'&x"CD7A",'1'&x"CD7B",'1'&x"CD7C",'1'&x"CD7D",'1'&x"CD7E",'1'&x"CD7F",
+--'1'&x"CD80",'1'&x"CD81",'1'&x"CD82",'1'&x"CD83",'1'&x"CD84",'1'&x"CD85",'1'&x"CD86",'1'&x"CD87",'1'&x"CD88",'1'&x"CD89",'1'&x"CD8A",'1'&x"CD8B",'1'&x"CD8C",'1'&x"CD8D",'1'&x"CD8E",'1'&x"CD8F",
+--'1'&x"CD90",'1'&x"CD91",'1'&x"CD92",'1'&x"CD93",'1'&x"CD94",'1'&x"CD95",'1'&x"CD96",'1'&x"CD97",'1'&x"CD98",'1'&x"CD99",'1'&x"CD9A",'1'&x"CD9B",'1'&x"CD9C",'1'&x"CD9D",'1'&x"CD9E",'1'&x"CD9F",
+--'1'&x"CDA0",'1'&x"CDA1",'1'&x"CDA2",'1'&x"CDA3",'1'&x"CDA4",'1'&x"CDA5",'1'&x"CDA6",'1'&x"CDA7",'1'&x"CDA8",'1'&x"CDA9",'1'&x"CDAA",'1'&x"CDAB",'1'&x"CDAC",'1'&x"CDAD",'1'&x"CDAE",'1'&x"CDAF",
+--'1'&x"CDB0",'1'&x"CDB1",'1'&x"CDB2",'1'&x"CDB3",'1'&x"CDB4",'1'&x"CDB5",'1'&x"CDB6",'1'&x"CDB7",'1'&x"CDB8",'1'&x"CDB9",'1'&x"CDBA",'1'&x"CDBB",'1'&x"CDBC",'1'&x"CDBD",'1'&x"CDBE",'1'&x"CDBF",
+--'1'&x"CDC0",'1'&x"CDC1",'1'&x"CDC2",'1'&x"CDC3",'1'&x"CDC4",'1'&x"CDC5",'1'&x"CDC6",'1'&x"CDC7",'1'&x"CDC8",'1'&x"CDC9",'1'&x"CDCA",'1'&x"CDCB",'1'&x"CDCC",'1'&x"CDCD",'1'&x"CDCE",'1'&x"CDCF",
+--'1'&x"CDD0",'1'&x"CDD1",'1'&x"CDD2",'1'&x"CDD3",'1'&x"CDD4",'1'&x"CDD5",'1'&x"CDD6",'1'&x"CDD7",'1'&x"CDD8",'1'&x"CDD9",'1'&x"CDDA",'1'&x"CDDB",'1'&x"CDDC",'1'&x"CDDD",'1'&x"CDDE",'1'&x"CDDF",
+--'1'&x"CDE0",'1'&x"CDE1",'1'&x"CDE2",'1'&x"CDE3",'1'&x"CDE4",'1'&x"CDE5",'1'&x"CDE6",'1'&x"CDE7",'1'&x"CDE8",'1'&x"CDE9",'1'&x"CDEA",'1'&x"CDEB",'1'&x"CDEC",'1'&x"CDED",'1'&x"CDEE",'1'&x"CDEF",
+--'1'&x"CDF0",'1'&x"CDF1",'1'&x"CDF2",'1'&x"CDF3",'1'&x"CDF4",'1'&x"CDF5",'1'&x"CDF6",'1'&x"CDF7",'1'&x"CDF8",'1'&x"CDF9",'1'&x"CDFA",'1'&x"CDFB",'1'&x"CDFC",'1'&x"CDFD",'1'&x"CDFE",'1'&x"CDFF",
+--'1'&x"CE00",'1'&x"CE01",'1'&x"CE02",'1'&x"CE03",'1'&x"CE04",'1'&x"CE05",'1'&x"CE06",'1'&x"CE07",'1'&x"CE08",'1'&x"CE09",'1'&x"CE0A",'1'&x"CE0B",'1'&x"CE0C",'1'&x"CE0D",'1'&x"CE0E",'1'&x"CE0F",
+--'1'&x"CE10",'1'&x"CE11",'1'&x"CE12",'1'&x"CE13",'1'&x"CE14",'1'&x"CE15",'1'&x"CE16",'1'&x"CE17",'1'&x"CE18",'1'&x"CE19",'1'&x"CE1A",'1'&x"CE1B",'1'&x"CE1C",'1'&x"CE1D",'1'&x"CE1E",'1'&x"CE1F",
+--'1'&x"CE20",'1'&x"CE21",'1'&x"CE22",'1'&x"CE23",'1'&x"CE24",'1'&x"CE25",'1'&x"CE26",'1'&x"CE27",'1'&x"CE28",'1'&x"CE29",'1'&x"CE2A",'1'&x"CE2B",'1'&x"CE2C",'1'&x"CE2D",'1'&x"CE2E",'1'&x"CE2F",
+--'1'&x"CE30",'1'&x"CE31",'1'&x"CE32",'1'&x"CE33",'1'&x"CE34",'1'&x"CE35",'1'&x"CE36",'1'&x"CE37",'1'&x"CE38",'1'&x"CE39",'1'&x"CE3A",'1'&x"CE3B",'1'&x"CE3C",'1'&x"CE3D",'1'&x"CE3E",'1'&x"CE3F",
+--'1'&x"CE40",'1'&x"CE41",'1'&x"CE42",'1'&x"CE43",'1'&x"CE44",'1'&x"CE45",'1'&x"CE46",'1'&x"CE47",'1'&x"CE48",'1'&x"CE49",'1'&x"CE4A",'1'&x"CE4B",'1'&x"CE4C",'1'&x"CE4D",'1'&x"CE4E",'1'&x"CE4F",
+--'1'&x"CE50",'1'&x"CE51",'1'&x"CE52",'1'&x"CE53",'1'&x"CE54",'1'&x"CE55",'1'&x"CE56",'1'&x"CE57",'1'&x"CE58",'1'&x"CE59",'1'&x"CE5A",'1'&x"CE5B",'1'&x"CE5C",'1'&x"CE5D",'1'&x"CE5E",'1'&x"CE5F",
+--'1'&x"CE60",'1'&x"CE61",'1'&x"CE62",'1'&x"CE63",'1'&x"CE64",'1'&x"CE65",'1'&x"CE66",'1'&x"CE67",'1'&x"CE68",'1'&x"CE69",'1'&x"CE6A",'1'&x"CE6B",'1'&x"CE6C",'1'&x"CE6D",'1'&x"CE6E",'1'&x"CE6F",
+--'1'&x"CE70",'1'&x"CE71",'1'&x"CE72",'1'&x"CE73",'1'&x"CE74",'1'&x"CE75",'1'&x"CE76",'1'&x"CE77",'1'&x"CE78",'1'&x"CE79",'1'&x"CE7A",'1'&x"CE7B",'1'&x"CE7C",'1'&x"CE7D",'1'&x"CE7E",'1'&x"CE7F",
+--'1'&x"CE80",'1'&x"CE81",'1'&x"CE82",'1'&x"CE83",'1'&x"CE84",'1'&x"CE85",'1'&x"CE86",'1'&x"CE87",'1'&x"CE88",'1'&x"CE89",'1'&x"CE8A",'1'&x"CE8B",'1'&x"CE8C",'1'&x"CE8D",'1'&x"CE8E",'1'&x"CE8F",
+--'1'&x"CE90",'1'&x"CE91",'1'&x"CE92",'1'&x"CE93",'1'&x"CE94",'1'&x"CE95",'1'&x"CE96",'1'&x"CE97",'1'&x"CE98",'1'&x"CE99",'1'&x"CE9A",'1'&x"CE9B",'1'&x"CE9C",'1'&x"CE9D",'1'&x"CE9E",'1'&x"CE9F",
+--'1'&x"CEA0",'1'&x"CEA1",'1'&x"CEA2",'1'&x"CEA3",'1'&x"CEA4",'1'&x"CEA5",'1'&x"CEA6",'1'&x"CEA7",'1'&x"CEA8",'1'&x"CEA9",'1'&x"CEAA",'1'&x"CEAB",'1'&x"CEAC",'1'&x"CEAD",'1'&x"CEAE",'1'&x"CEAF",
+--'1'&x"CEB0",'1'&x"CEB1",'1'&x"CEB2",'1'&x"CEB3",'1'&x"CEB4",'1'&x"CEB5",'1'&x"CEB6",'1'&x"CEB7",'1'&x"CEB8",'1'&x"CEB9",'1'&x"CEBA",'1'&x"CEBB",'1'&x"CEBC",'1'&x"CEBD",'1'&x"CEBE",'1'&x"CEBF",
+--'1'&x"CEC0",'1'&x"CEC1",'1'&x"CEC2",'1'&x"CEC3",'1'&x"CEC4",'1'&x"CEC5",'1'&x"CEC6",'1'&x"CEC7",'1'&x"CEC8",'1'&x"CEC9",'1'&x"CECA",'1'&x"CECB",'1'&x"CECC",'1'&x"CECD",'1'&x"CECE",'1'&x"CECF",
+--'1'&x"CED0",'1'&x"CED1",'1'&x"CED2",'1'&x"CED3",'1'&x"CED4",'1'&x"CED5",'1'&x"CED6",'1'&x"CED7",'1'&x"CED8",'1'&x"CED9",'1'&x"CEDA",'1'&x"CEDB",'1'&x"CEDC",'1'&x"CEDD",'1'&x"CEDE",'1'&x"CEDF",
+--'1'&x"CEE0",'1'&x"CEE1",'1'&x"CEE2",'1'&x"CEE3",'1'&x"CEE4",'1'&x"CEE5",'1'&x"CEE6",'1'&x"CEE7",'1'&x"CEE8",'1'&x"CEE9",'1'&x"CEEA",'1'&x"CEEB",'1'&x"CEEC",'1'&x"CEED",'1'&x"CEEE",'1'&x"CEEF",
+--'1'&x"CEF0",'1'&x"CEF1",'1'&x"CEF2",'1'&x"CEF3",'1'&x"CEF4",'1'&x"CEF5",'1'&x"CEF6",'1'&x"CEF7",'1'&x"CEF8",'1'&x"CEF9",'1'&x"CEFA",'1'&x"CEFB",'1'&x"CEFC",'1'&x"CEFD",'1'&x"CEFE",'1'&x"CEFF",
+--'1'&x"CF00",'1'&x"CF01",'1'&x"CF02",'1'&x"CF03",'1'&x"CF04",'1'&x"CF05",'1'&x"CF06",'1'&x"CF07",'1'&x"CF08",'1'&x"CF09",'1'&x"CF0A",'1'&x"CF0B",'1'&x"CF0C",'1'&x"CF0D",'1'&x"CF0E",'1'&x"CF0F",
+--'1'&x"CF10",'1'&x"CF11",'1'&x"CF12",'1'&x"CF13",'1'&x"CF14",'1'&x"CF15",'1'&x"CF16",'1'&x"CF17",'1'&x"CF18",'1'&x"CF19",'1'&x"CF1A",'1'&x"CF1B",'1'&x"CF1C",'1'&x"CF1D",'1'&x"CF1E",'1'&x"CF1F",
+--'1'&x"CF20",'1'&x"CF21",'1'&x"CF22",'1'&x"CF23",'1'&x"CF24",'1'&x"CF25",'1'&x"CF26",'1'&x"CF27",'1'&x"CF28",'1'&x"CF29",'1'&x"CF2A",'1'&x"CF2B",'1'&x"CF2C",'1'&x"CF2D",'1'&x"CF2E",'1'&x"CF2F",
+--'1'&x"CF30",'1'&x"CF31",'1'&x"CF32",'1'&x"CF33",'1'&x"CF34",'1'&x"CF35",'1'&x"CF36",'1'&x"CF37",'1'&x"CF38",'1'&x"CF39",'1'&x"CF3A",'1'&x"CF3B",'1'&x"CF3C",'1'&x"CF3D",'1'&x"CF3E",'1'&x"CF3F",
+--'1'&x"CF40",'1'&x"CF41",'1'&x"CF42",'1'&x"CF43",'1'&x"CF44",'1'&x"CF45",'1'&x"CF46",'1'&x"CF47",'1'&x"CF48",'1'&x"CF49",'1'&x"CF4A",'1'&x"CF4B",'1'&x"CF4C",'1'&x"CF4D",'1'&x"CF4E",'1'&x"CF4F",
+--'1'&x"CF50",'1'&x"CF51",'1'&x"CF52",'1'&x"CF53",'1'&x"CF54",'1'&x"CF55",'1'&x"CF56",'1'&x"CF57",'1'&x"CF58",'1'&x"CF59",'1'&x"CF5A",'1'&x"CF5B",'1'&x"CF5C",'1'&x"CF5D",'1'&x"CF5E",'1'&x"CF5F",
+--'1'&x"CF60",'1'&x"CF61",'1'&x"CF62",'1'&x"CF63",'1'&x"CF64",'1'&x"CF65",'1'&x"CF66",'1'&x"CF67",'1'&x"CF68",'1'&x"CF69",'1'&x"CF6A",'1'&x"CF6B",'1'&x"CF6C",'1'&x"CF6D",'1'&x"CF6E",'1'&x"CF6F",
+--'1'&x"CF70",'1'&x"CF71",'1'&x"CF72",'1'&x"CF73",'1'&x"CF74",'1'&x"CF75",'1'&x"CF76",'1'&x"CF77",'1'&x"CF78",'1'&x"CF79",'1'&x"CF7A",'1'&x"CF7B",'1'&x"CF7C",'1'&x"CF7D",'1'&x"CF7E",'1'&x"CF7F",
+--'1'&x"CF80",'1'&x"CF81",'1'&x"CF82",'1'&x"CF83",'1'&x"CF84",'1'&x"CF85",'1'&x"CF86",'1'&x"CF87",'1'&x"CF88",'1'&x"CF89",'1'&x"CF8A",'1'&x"CF8B",'1'&x"CF8C",'1'&x"CF8D",'1'&x"CF8E",'1'&x"CF8F",
+--'1'&x"CF90",'1'&x"CF91",'1'&x"CF92",'1'&x"CF93",'1'&x"CF94",'1'&x"CF95",'1'&x"CF96",'1'&x"CF97",'1'&x"CF98",'1'&x"CF99",'1'&x"CF9A",'1'&x"CF9B",'1'&x"CF9C",'1'&x"CF9D",'1'&x"CF9E",'1'&x"CF9F",
+--'1'&x"CFA0",'1'&x"CFA1",'1'&x"CFA2",'1'&x"CFA3",'1'&x"CFA4",'1'&x"CFA5",'1'&x"CFA6",'1'&x"CFA7",'1'&x"CFA8",'1'&x"CFA9",'1'&x"CFAA",'1'&x"CFAB",'1'&x"CFAC",'1'&x"CFAD",'1'&x"CFAE",'1'&x"CFAF",
+--'1'&x"CFB0",'1'&x"CFB1",'1'&x"CFB2",'1'&x"CFB3",'1'&x"CFB4",'1'&x"CFB5",'1'&x"CFB6",'1'&x"CFB7",'1'&x"CFB8",'1'&x"CFB9",'1'&x"CFBA",'1'&x"CFBB",'1'&x"CFBC",'1'&x"CFBD",'1'&x"CFBE",'1'&x"CFBF",
+--'1'&x"CFC0",'1'&x"CFC1",'1'&x"CFC2",'1'&x"CFC3",'1'&x"CFC4",'1'&x"CFC5",'1'&x"CFC6",'1'&x"CFC7",'1'&x"CFC8",'1'&x"CFC9",'1'&x"CFCA",'1'&x"CFCB",'1'&x"CFCC",'1'&x"CFCD",'1'&x"CFCE",'1'&x"CFCF",
+--'1'&x"CFD0",'1'&x"CFD1",'1'&x"CFD2",'1'&x"CFD3",'1'&x"CFD4",'1'&x"CFD5",'1'&x"CFD6",'1'&x"CFD7",'1'&x"CFD8",'1'&x"CFD9",'1'&x"CFDA",'1'&x"CFDB",'1'&x"CFDC",'1'&x"CFDD",'1'&x"CFDE",'1'&x"CFDF",
+--'1'&x"CFE0",'1'&x"CFE1",'1'&x"CFE2",'1'&x"CFE3",'1'&x"CFE4",'1'&x"CFE5",'1'&x"CFE6",'1'&x"CFE7",'1'&x"CFE8",'1'&x"CFE9",'1'&x"CFEA",'1'&x"CFEB",'1'&x"CFEC",'1'&x"CFED",'1'&x"CFEE",'1'&x"CFEF",
+--'1'&x"CFF0",'1'&x"CFF1",'1'&x"CFF2",'1'&x"CFF3",'1'&x"CFF4",'1'&x"CFF5",'1'&x"CFF6",'1'&x"CFF7",'1'&x"CFF8",'1'&x"CFF9",'1'&x"CFFA",'1'&x"CFFB",'1'&x"CFFC",'1'&x"CFFD",'1'&x"CFFE",'1'&x"CFFF",
+--'1'&x"D000",'1'&x"D001",'1'&x"D002",'1'&x"D003",'1'&x"D004",'1'&x"D005",'1'&x"D006",'1'&x"D007",'1'&x"D008",'1'&x"D009",'1'&x"D00A",'1'&x"D00B",'1'&x"D00C",'1'&x"D00D",'1'&x"D00E",'1'&x"D00F",
+--'1'&x"D010",'1'&x"D011",'1'&x"D012",'1'&x"D013",'1'&x"D014",'1'&x"D015",'1'&x"D016",'1'&x"D017",'1'&x"D018",'1'&x"D019",'1'&x"D01A",'1'&x"D01B",'1'&x"D01C",'1'&x"D01D",'1'&x"D01E",'1'&x"D01F",
+--'1'&x"D020",'1'&x"D021",'1'&x"D022",'1'&x"D023",'1'&x"D024",'1'&x"D025",'1'&x"D026",'1'&x"D027",'1'&x"D028",'1'&x"D029",'1'&x"D02A",'1'&x"D02B",'1'&x"D02C",'1'&x"D02D",'1'&x"D02E",'1'&x"D02F",
+--'1'&x"D030",'1'&x"D031",'1'&x"D032",'1'&x"D033",'1'&x"D034",'1'&x"D035",'1'&x"D036",'1'&x"D037",'1'&x"D038",'1'&x"D039",'1'&x"D03A",'1'&x"D03B",'1'&x"D03C",'1'&x"D03D",'1'&x"D03E",'1'&x"D03F",
+--'1'&x"D040",'1'&x"D041",'1'&x"D042",'1'&x"D043",'1'&x"D044",'1'&x"D045",'1'&x"D046",'1'&x"D047",'1'&x"D048",'1'&x"D049",'1'&x"D04A",'1'&x"D04B",'1'&x"D04C",'1'&x"D04D",'1'&x"D04E",'1'&x"D04F",
+--'1'&x"D050",'1'&x"D051",'1'&x"D052",'1'&x"D053",'1'&x"D054",'1'&x"D055",'1'&x"D056",'1'&x"D057",'1'&x"D058",'1'&x"D059",'1'&x"D05A",'1'&x"D05B",'1'&x"D05C",'1'&x"D05D",'1'&x"D05E",'1'&x"D05F",
+--'1'&x"D060",'1'&x"D061",'1'&x"D062",'1'&x"D063",'1'&x"D064",'1'&x"D065",'1'&x"D066",'1'&x"D067",'1'&x"D068",'1'&x"D069",'1'&x"D06A",'1'&x"D06B",'1'&x"D06C",'1'&x"D06D",'1'&x"D06E",'1'&x"D06F",
+--'1'&x"D070",'1'&x"D071",'1'&x"D072",'1'&x"D073",'1'&x"D074",'1'&x"D075",'1'&x"D076",'1'&x"D077",'1'&x"D078",'1'&x"D079",'1'&x"D07A",'1'&x"D07B",'1'&x"D07C",'1'&x"D07D",'1'&x"D07E",'1'&x"D07F",
+--'1'&x"D080",'1'&x"D081",'1'&x"D082",'1'&x"D083",'1'&x"D084",'1'&x"D085",'1'&x"D086",'1'&x"D087",'1'&x"D088",'1'&x"D089",'1'&x"D08A",'1'&x"D08B",'1'&x"D08C",'1'&x"D08D",'1'&x"D08E",'1'&x"D08F",
+--'1'&x"D090",'1'&x"D091",'1'&x"D092",'1'&x"D093",'1'&x"D094",'1'&x"D095",'1'&x"D096",'1'&x"D097",'1'&x"D098",'1'&x"D099",'1'&x"D09A",'1'&x"D09B",'1'&x"D09C",'1'&x"D09D",'1'&x"D09E",'1'&x"D09F",
+--'1'&x"D0A0",'1'&x"D0A1",'1'&x"D0A2",'1'&x"D0A3",'1'&x"D0A4",'1'&x"D0A5",'1'&x"D0A6",'1'&x"D0A7",'1'&x"D0A8",'1'&x"D0A9",'1'&x"D0AA",'1'&x"D0AB",'1'&x"D0AC",'1'&x"D0AD",'1'&x"D0AE",'1'&x"D0AF",
+--'1'&x"D0B0",'1'&x"D0B1",'1'&x"D0B2",'1'&x"D0B3",'1'&x"D0B4",'1'&x"D0B5",'1'&x"D0B6",'1'&x"D0B7",'1'&x"D0B8",'1'&x"D0B9",'1'&x"D0BA",'1'&x"D0BB",'1'&x"D0BC",'1'&x"D0BD",'1'&x"D0BE",'1'&x"D0BF",
+--'1'&x"D0C0",'1'&x"D0C1",'1'&x"D0C2",'1'&x"D0C3",'1'&x"D0C4",'1'&x"D0C5",'1'&x"D0C6",'1'&x"D0C7",'1'&x"D0C8",'1'&x"D0C9",'1'&x"D0CA",'1'&x"D0CB",'1'&x"D0CC",'1'&x"D0CD",'1'&x"D0CE",'1'&x"D0CF",
+--'1'&x"D0D0",'1'&x"D0D1",'1'&x"D0D2",'1'&x"D0D3",'1'&x"D0D4",'1'&x"D0D5",'1'&x"D0D6",'1'&x"D0D7",'1'&x"D0D8",'1'&x"D0D9",'1'&x"D0DA",'1'&x"D0DB",'1'&x"D0DC",'1'&x"D0DD",'1'&x"D0DE",'1'&x"D0DF",
+--'1'&x"D0E0",'1'&x"D0E1",'1'&x"D0E2",'1'&x"D0E3",'1'&x"D0E4",'1'&x"D0E5",'1'&x"D0E6",'1'&x"D0E7",'1'&x"D0E8",'1'&x"D0E9",'1'&x"D0EA",'1'&x"D0EB",'1'&x"D0EC",'1'&x"D0ED",'1'&x"D0EE",'1'&x"D0EF",
+--'1'&x"D0F0",'1'&x"D0F1",'1'&x"D0F2",'1'&x"D0F3",'1'&x"D0F4",'1'&x"D0F5",'1'&x"D0F6",'1'&x"D0F7",'1'&x"D0F8",'1'&x"D0F9",'1'&x"D0FA",'1'&x"D0FB",'1'&x"D0FC",'1'&x"D0FD",'1'&x"D0FE",'1'&x"D0FF",
+--'1'&x"D100",'1'&x"D101",'1'&x"D102",'1'&x"D103",'1'&x"D104",'1'&x"D105",'1'&x"D106",'1'&x"D107",'1'&x"D108",'1'&x"D109",'1'&x"D10A",'1'&x"D10B",'1'&x"D10C",'1'&x"D10D",'1'&x"D10E",'1'&x"D10F",
+--'1'&x"D110",'1'&x"D111",'1'&x"D112",'1'&x"D113",'1'&x"D114",'1'&x"D115",'1'&x"D116",'1'&x"D117",'1'&x"D118",'1'&x"D119",'1'&x"D11A",'1'&x"D11B",'1'&x"D11C",'1'&x"D11D",'1'&x"D11E",'1'&x"D11F",
+--'1'&x"D120",'1'&x"D121",'1'&x"D122",'1'&x"D123",'1'&x"D124",'1'&x"D125",'1'&x"D126",'1'&x"D127",'1'&x"D128",'1'&x"D129",'1'&x"D12A",'1'&x"D12B",'1'&x"D12C",'1'&x"D12D",'1'&x"D12E",'1'&x"D12F",
+--'1'&x"D130",'1'&x"D131",'1'&x"D132",'1'&x"D133",'1'&x"D134",'1'&x"D135",'1'&x"D136",'1'&x"D137",'1'&x"D138",'1'&x"D139",'1'&x"D13A",'1'&x"D13B",'1'&x"D13C",'1'&x"D13D",'1'&x"D13E",'1'&x"D13F",
+--'1'&x"D140",'1'&x"D141",'1'&x"D142",'1'&x"D143",'1'&x"D144",'1'&x"D145",'1'&x"D146",'1'&x"D147",'1'&x"D148",'1'&x"D149",'1'&x"D14A",'1'&x"D14B",'1'&x"D14C",'1'&x"D14D",'1'&x"D14E",'1'&x"D14F",
+--'1'&x"D150",'1'&x"D151",'1'&x"D152",'1'&x"D153",'1'&x"D154",'1'&x"D155",'1'&x"D156",'1'&x"D157",'1'&x"D158",'1'&x"D159",'1'&x"D15A",'1'&x"D15B",'1'&x"D15C",'1'&x"D15D",'1'&x"D15E",'1'&x"D15F",
+--'1'&x"D160",'1'&x"D161",'1'&x"D162",'1'&x"D163",'1'&x"D164",'1'&x"D165",'1'&x"D166",'1'&x"D167",'1'&x"D168",'1'&x"D169",'1'&x"D16A",'1'&x"D16B",'1'&x"D16C",'1'&x"D16D",'1'&x"D16E",'1'&x"D16F",
+--'1'&x"D170",'1'&x"D171",'1'&x"D172",'1'&x"D173",'1'&x"D174",'1'&x"D175",'1'&x"D176",'1'&x"D177",'1'&x"D178",'1'&x"D179",'1'&x"D17A",'1'&x"D17B",'1'&x"D17C",'1'&x"D17D",'1'&x"D17E",'1'&x"D17F",
+--'1'&x"D180",'1'&x"D181",'1'&x"D182",'1'&x"D183",'1'&x"D184",'1'&x"D185",'1'&x"D186",'1'&x"D187",'1'&x"D188",'1'&x"D189",'1'&x"D18A",'1'&x"D18B",'1'&x"D18C",'1'&x"D18D",'1'&x"D18E",'1'&x"D18F",
+--'1'&x"D190",'1'&x"D191",'1'&x"D192",'1'&x"D193",'1'&x"D194",'1'&x"D195",'1'&x"D196",'1'&x"D197",'1'&x"D198",'1'&x"D199",'1'&x"D19A",'1'&x"D19B",'1'&x"D19C",'1'&x"D19D",'1'&x"D19E",'1'&x"D19F",
+--'1'&x"D1A0",'1'&x"D1A1",'1'&x"D1A2",'1'&x"D1A3",'1'&x"D1A4",'1'&x"D1A5",'1'&x"D1A6",'1'&x"D1A7",'1'&x"D1A8",'1'&x"D1A9",'1'&x"D1AA",'1'&x"D1AB",'1'&x"D1AC",'1'&x"D1AD",'1'&x"D1AE",'1'&x"D1AF",
+--'1'&x"D1B0",'1'&x"D1B1",'1'&x"D1B2",'1'&x"D1B3",'1'&x"D1B4",'1'&x"D1B5",'1'&x"D1B6",'1'&x"D1B7",'1'&x"D1B8",'1'&x"D1B9",'1'&x"D1BA",'1'&x"D1BB",'1'&x"D1BC",'1'&x"D1BD",'1'&x"D1BE",'1'&x"D1BF",
+--'1'&x"D1C0",'1'&x"D1C1",'1'&x"D1C2",'1'&x"D1C3",'1'&x"D1C4",'1'&x"D1C5",'1'&x"D1C6",'1'&x"D1C7",'1'&x"D1C8",'1'&x"D1C9",'1'&x"D1CA",'1'&x"D1CB",'1'&x"D1CC",'1'&x"D1CD",'1'&x"D1CE",'1'&x"D1CF",
+--'1'&x"D1D0",'1'&x"D1D1",'1'&x"D1D2",'1'&x"D1D3",'1'&x"D1D4",'1'&x"D1D5",'1'&x"D1D6",'1'&x"D1D7",'1'&x"D1D8",'1'&x"D1D9",'1'&x"D1DA",'1'&x"D1DB",'1'&x"D1DC",'1'&x"D1DD",'1'&x"D1DE",'1'&x"D1DF",
+--'1'&x"D1E0",'1'&x"D1E1",'1'&x"D1E2",'1'&x"D1E3",'1'&x"D1E4",'1'&x"D1E5",'1'&x"D1E6",'1'&x"D1E7",'1'&x"D1E8",'1'&x"D1E9",'1'&x"D1EA",'1'&x"D1EB",'1'&x"D1EC",'1'&x"D1ED",'1'&x"D1EE",'1'&x"D1EF",
+--'1'&x"D1F0",'1'&x"D1F1",'1'&x"D1F2",'1'&x"D1F3",'1'&x"D1F4",'1'&x"D1F5",'1'&x"D1F6",'1'&x"D1F7",'1'&x"D1F8",'1'&x"D1F9",'1'&x"D1FA",'1'&x"D1FB",'1'&x"D1FC",'1'&x"D1FD",'1'&x"D1FE",'1'&x"D1FF",
+--'1'&x"D200",'1'&x"D201",'1'&x"D202",'1'&x"D203",'1'&x"D204",'1'&x"D205",'1'&x"D206",'1'&x"D207",'1'&x"D208",'1'&x"D209",'1'&x"D20A",'1'&x"D20B",'1'&x"D20C",'1'&x"D20D",'1'&x"D20E",'1'&x"D20F",
+--'1'&x"D210",'1'&x"D211",'1'&x"D212",'1'&x"D213",'1'&x"D214",'1'&x"D215",'1'&x"D216",'1'&x"D217",'1'&x"D218",'1'&x"D219",'1'&x"D21A",'1'&x"D21B",'1'&x"D21C",'1'&x"D21D",'1'&x"D21E",'1'&x"D21F",
+--'1'&x"D220",'1'&x"D221",'1'&x"D222",'1'&x"D223",'1'&x"D224",'1'&x"D225",'1'&x"D226",'1'&x"D227",'1'&x"D228",'1'&x"D229",'1'&x"D22A",'1'&x"D22B",'1'&x"D22C",'1'&x"D22D",'1'&x"D22E",'1'&x"D22F",
+--'1'&x"D230",'1'&x"D231",'1'&x"D232",'1'&x"D233",'1'&x"D234",'1'&x"D235",'1'&x"D236",'1'&x"D237",'1'&x"D238",'1'&x"D239",'1'&x"D23A",'1'&x"D23B",'1'&x"D23C",'1'&x"D23D",'1'&x"D23E",'1'&x"D23F",
+--'1'&x"D240",'1'&x"D241",'1'&x"D242",'1'&x"D243",'1'&x"D244",'1'&x"D245",'1'&x"D246",'1'&x"D247",'1'&x"D248",'1'&x"D249",'1'&x"D24A",'1'&x"D24B",'1'&x"D24C",'1'&x"D24D",'1'&x"D24E",'1'&x"D24F",
+--'1'&x"D250",'1'&x"D251",'1'&x"D252",'1'&x"D253",'1'&x"D254",'1'&x"D255",'1'&x"D256",'1'&x"D257",'1'&x"D258",'1'&x"D259",'1'&x"D25A",'1'&x"D25B",'1'&x"D25C",'1'&x"D25D",'1'&x"D25E",'1'&x"D25F",
+--'1'&x"D260",'1'&x"D261",'1'&x"D262",'1'&x"D263",'1'&x"D264",'1'&x"D265",'1'&x"D266",'1'&x"D267",'1'&x"D268",'1'&x"D269",'1'&x"D26A",'1'&x"D26B",'1'&x"D26C",'1'&x"D26D",'1'&x"D26E",'1'&x"D26F",
+--'1'&x"D270",'1'&x"D271",'1'&x"D272",'1'&x"D273",'1'&x"D274",'1'&x"D275",'1'&x"D276",'1'&x"D277",'1'&x"D278",'1'&x"D279",'1'&x"D27A",'1'&x"D27B",'1'&x"D27C",'1'&x"D27D",'1'&x"D27E",'1'&x"D27F",
+--'1'&x"D280",'1'&x"D281",'1'&x"D282",'1'&x"D283",'1'&x"D284",'1'&x"D285",'1'&x"D286",'1'&x"D287",'1'&x"D288",'1'&x"D289",'1'&x"D28A",'1'&x"D28B",'1'&x"D28C",'1'&x"D28D",'1'&x"D28E",'1'&x"D28F",
+--'1'&x"D290",'1'&x"D291",'1'&x"D292",'1'&x"D293",'1'&x"D294",'1'&x"D295",'1'&x"D296",'1'&x"D297",'1'&x"D298",'1'&x"D299",'1'&x"D29A",'1'&x"D29B",'1'&x"D29C",'1'&x"D29D",'1'&x"D29E",'1'&x"D29F",
+--'1'&x"D2A0",'1'&x"D2A1",'1'&x"D2A2",'1'&x"D2A3",'1'&x"D2A4",'1'&x"D2A5",'1'&x"D2A6",'1'&x"D2A7",'1'&x"D2A8",'1'&x"D2A9",'1'&x"D2AA",'1'&x"D2AB",'1'&x"D2AC",'1'&x"D2AD",'1'&x"D2AE",'1'&x"D2AF",
+--'1'&x"D2B0",'1'&x"D2B1",'1'&x"D2B2",'1'&x"D2B3",'1'&x"D2B4",'1'&x"D2B5",'1'&x"D2B6",'1'&x"D2B7",'1'&x"D2B8",'1'&x"D2B9",'1'&x"D2BA",'1'&x"D2BB",'1'&x"D2BC",'1'&x"D2BD",'1'&x"D2BE",'1'&x"D2BF",
+--'1'&x"D2C0",'1'&x"D2C1",'1'&x"D2C2",'1'&x"D2C3",'1'&x"D2C4",'1'&x"D2C5",'1'&x"D2C6",'1'&x"D2C7",'1'&x"D2C8",'1'&x"D2C9",'1'&x"D2CA",'1'&x"D2CB",'1'&x"D2CC",'1'&x"D2CD",'1'&x"D2CE",'1'&x"D2CF",
+--'1'&x"D2D0",'1'&x"D2D1",'1'&x"D2D2",'1'&x"D2D3",'1'&x"D2D4",'1'&x"D2D5",'1'&x"D2D6",'1'&x"D2D7",'1'&x"D2D8",'1'&x"D2D9",'1'&x"D2DA",'1'&x"D2DB",'1'&x"D2DC",'1'&x"D2DD",'1'&x"D2DE",'1'&x"D2DF",
+--'1'&x"D2E0",'1'&x"D2E1",'1'&x"D2E2",'1'&x"D2E3",'1'&x"D2E4",'1'&x"D2E5",'1'&x"D2E6",'1'&x"D2E7",'1'&x"D2E8",'1'&x"D2E9",'1'&x"D2EA",'1'&x"D2EB",'1'&x"D2EC",'1'&x"D2ED",'1'&x"D2EE",'1'&x"D2EF",
+--'1'&x"D2F0",'1'&x"D2F1",'1'&x"D2F2",'1'&x"D2F3",'1'&x"D2F4",'1'&x"D2F5",'1'&x"D2F6",'1'&x"D2F7",'1'&x"D2F8",'1'&x"D2F9",'1'&x"D2FA",'1'&x"D2FB",'1'&x"D2FC",'1'&x"D2FD",'1'&x"D2FE",'1'&x"D2FF",
+--'1'&x"D300",'1'&x"D301",'1'&x"D302",'1'&x"D303",'1'&x"D304",'1'&x"D305",'1'&x"D306",'1'&x"D307",'1'&x"D308",'1'&x"D309",'1'&x"D30A",'1'&x"D30B",'1'&x"D30C",'1'&x"D30D",'1'&x"D30E",'1'&x"D30F",
+--'1'&x"D310",'1'&x"D311",'1'&x"D312",'1'&x"D313",'1'&x"D314",'1'&x"D315",'1'&x"D316",'1'&x"D317",'1'&x"D318",'1'&x"D319",'1'&x"D31A",'1'&x"D31B",'1'&x"D31C",'1'&x"D31D",'1'&x"D31E",'1'&x"D31F",
+--'1'&x"D320",'1'&x"D321",'1'&x"D322",'1'&x"D323",'1'&x"D324",'1'&x"D325",'1'&x"D326",'1'&x"D327",'1'&x"D328",'1'&x"D329",'1'&x"D32A",'1'&x"D32B",'1'&x"D32C",'1'&x"D32D",'1'&x"D32E",'1'&x"D32F",
+--'1'&x"D330",'1'&x"D331",'1'&x"D332",'1'&x"D333",'1'&x"D334",'1'&x"D335",'1'&x"D336",'1'&x"D337",'1'&x"D338",'1'&x"D339",'1'&x"D33A",'1'&x"D33B",'1'&x"D33C",'1'&x"D33D",'1'&x"D33E",'1'&x"D33F",
+--'1'&x"D340",'1'&x"D341",'1'&x"D342",'1'&x"D343",'1'&x"D344",'1'&x"D345",'1'&x"D346",'1'&x"D347",'1'&x"D348",'1'&x"D349",'1'&x"D34A",'1'&x"D34B",'1'&x"D34C",'1'&x"D34D",'1'&x"D34E",'1'&x"D34F",
+--'1'&x"D350",'1'&x"D351",'1'&x"D352",'1'&x"D353",'1'&x"D354",'1'&x"D355",'1'&x"D356",'1'&x"D357",'1'&x"D358",'1'&x"D359",'1'&x"D35A",'1'&x"D35B",'1'&x"D35C",'1'&x"D35D",'1'&x"D35E",'1'&x"D35F",
+--'1'&x"D360",'1'&x"D361",'1'&x"D362",'1'&x"D363",'1'&x"D364",'1'&x"D365",'1'&x"D366",'1'&x"D367",'1'&x"D368",'1'&x"D369",'1'&x"D36A",'1'&x"D36B",'1'&x"D36C",'1'&x"D36D",'1'&x"D36E",'1'&x"D36F",
+--'1'&x"D370",'1'&x"D371",'1'&x"D372",'1'&x"D373",'1'&x"D374",'1'&x"D375",'1'&x"D376",'1'&x"D377",'1'&x"D378",'1'&x"D379",'1'&x"D37A",'1'&x"D37B",'1'&x"D37C",'1'&x"D37D",'1'&x"D37E",'1'&x"D37F",
+--'1'&x"D380",'1'&x"D381",'1'&x"D382",'1'&x"D383",'1'&x"D384",'1'&x"D385",'1'&x"D386",'1'&x"D387",'1'&x"D388",'1'&x"D389",'1'&x"D38A",'1'&x"D38B",'1'&x"D38C",'1'&x"D38D",'1'&x"D38E",'1'&x"D38F",
+--'1'&x"D390",'1'&x"D391",'1'&x"D392",'1'&x"D393",'1'&x"D394",'1'&x"D395",'1'&x"D396",'1'&x"D397",'1'&x"D398",'1'&x"D399",'1'&x"D39A",'1'&x"D39B",'1'&x"D39C",'1'&x"D39D",'1'&x"D39E",'1'&x"D39F",
+--'1'&x"D3A0",'1'&x"D3A1",'1'&x"D3A2",'1'&x"D3A3",'1'&x"D3A4",'1'&x"D3A5",'1'&x"D3A6",'1'&x"D3A7",'1'&x"D3A8",'1'&x"D3A9",'1'&x"D3AA",'1'&x"D3AB",'1'&x"D3AC",'1'&x"D3AD",'1'&x"D3AE",'1'&x"D3AF",
+--'1'&x"D3B0",'1'&x"D3B1",'1'&x"D3B2",'1'&x"D3B3",'1'&x"D3B4",'1'&x"D3B5",'1'&x"D3B6",'1'&x"D3B7",'1'&x"D3B8",'1'&x"D3B9",'1'&x"D3BA",'1'&x"D3BB",'1'&x"D3BC",'1'&x"D3BD",'1'&x"D3BE",'1'&x"D3BF",
+--'1'&x"D3C0",'1'&x"D3C1",'1'&x"D3C2",'1'&x"D3C3",'1'&x"D3C4",'1'&x"D3C5",'1'&x"D3C6",'1'&x"D3C7",'1'&x"D3C8",'1'&x"D3C9",'1'&x"D3CA",'1'&x"D3CB",'1'&x"D3CC",'1'&x"D3CD",'1'&x"D3CE",'1'&x"D3CF",
+--'1'&x"D3D0",'1'&x"D3D1",'1'&x"D3D2",'1'&x"D3D3",'1'&x"D3D4",'1'&x"D3D5",'1'&x"D3D6",'1'&x"D3D7",'1'&x"D3D8",'1'&x"D3D9",'1'&x"D3DA",'1'&x"D3DB",'1'&x"D3DC",'1'&x"D3DD",'1'&x"D3DE",'1'&x"D3DF",
+--'1'&x"D3E0",'1'&x"D3E1",'1'&x"D3E2",'1'&x"D3E3",'1'&x"D3E4",'1'&x"D3E5",'1'&x"D3E6",'1'&x"D3E7",'1'&x"D3E8",'1'&x"D3E9",'1'&x"D3EA",'1'&x"D3EB",'1'&x"D3EC",'1'&x"D3ED",'1'&x"D3EE",'1'&x"D3EF",
+--'1'&x"D3F0",'1'&x"D3F1",'1'&x"D3F2",'1'&x"D3F3",'1'&x"D3F4",'1'&x"D3F5",'1'&x"D3F6",'1'&x"D3F7",'1'&x"D3F8",'1'&x"D3F9",'1'&x"D3FA",'1'&x"D3FB",'1'&x"D3FC",'1'&x"D3FD",'1'&x"D3FE",'1'&x"D3FF",
+--'1'&x"D400",'1'&x"D401",'1'&x"D402",'1'&x"D403",'1'&x"D404",'1'&x"D405",'1'&x"D406",'1'&x"D407",'1'&x"D408",'1'&x"D409",'1'&x"D40A",'1'&x"D40B",'1'&x"D40C",'1'&x"D40D",'1'&x"D40E",'1'&x"D40F",
+--'1'&x"D410",'1'&x"D411",'1'&x"D412",'1'&x"D413",'1'&x"D414",'1'&x"D415",'1'&x"D416",'1'&x"D417",'1'&x"D418",'1'&x"D419",'1'&x"D41A",'1'&x"D41B",'1'&x"D41C",'1'&x"D41D",'1'&x"D41E",'1'&x"D41F",
+--'1'&x"D420",'1'&x"D421",'1'&x"D422",'1'&x"D423",'1'&x"D424",'1'&x"D425",'1'&x"D426",'1'&x"D427",'1'&x"D428",'1'&x"D429",'1'&x"D42A",'1'&x"D42B",'1'&x"D42C",'1'&x"D42D",'1'&x"D42E",'1'&x"D42F",
+--'1'&x"D430",'1'&x"D431",'1'&x"D432",'1'&x"D433",'1'&x"D434",'1'&x"D435",'1'&x"D436",'1'&x"D437",'1'&x"D438",'1'&x"D439",'1'&x"D43A",'1'&x"D43B",'1'&x"D43C",'1'&x"D43D",'1'&x"D43E",'1'&x"D43F",
+--'1'&x"D440",'1'&x"D441",'1'&x"D442",'1'&x"D443",'1'&x"D444",'1'&x"D445",'1'&x"D446",'1'&x"D447",'1'&x"D448",'1'&x"D449",'1'&x"D44A",'1'&x"D44B",'1'&x"D44C",'1'&x"D44D",'1'&x"D44E",'1'&x"D44F",
+--'1'&x"D450",'1'&x"D451",'1'&x"D452",'1'&x"D453",'1'&x"D454",'1'&x"D455",'1'&x"D456",'1'&x"D457",'1'&x"D458",'1'&x"D459",'1'&x"D45A",'1'&x"D45B",'1'&x"D45C",'1'&x"D45D",'1'&x"D45E",'1'&x"D45F",
+--'1'&x"D460",'1'&x"D461",'1'&x"D462",'1'&x"D463",'1'&x"D464",'1'&x"D465",'1'&x"D466",'1'&x"D467",'1'&x"D468",'1'&x"D469",'1'&x"D46A",'1'&x"D46B",'1'&x"D46C",'1'&x"D46D",'1'&x"D46E",'1'&x"D46F",
+--'1'&x"D470",'1'&x"D471",'1'&x"D472",'1'&x"D473",'1'&x"D474",'1'&x"D475",'1'&x"D476",'1'&x"D477",'1'&x"D478",'1'&x"D479",'1'&x"D47A",'1'&x"D47B",'1'&x"D47C",'1'&x"D47D",'1'&x"D47E",'1'&x"D47F",
+--'1'&x"D480",'1'&x"D481",'1'&x"D482",'1'&x"D483",'1'&x"D484",'1'&x"D485",'1'&x"D486",'1'&x"D487",'1'&x"D488",'1'&x"D489",'1'&x"D48A",'1'&x"D48B",'1'&x"D48C",'1'&x"D48D",'1'&x"D48E",'1'&x"D48F",
+--'1'&x"D490",'1'&x"D491",'1'&x"D492",'1'&x"D493",'1'&x"D494",'1'&x"D495",'1'&x"D496",'1'&x"D497",'1'&x"D498",'1'&x"D499",'1'&x"D49A",'1'&x"D49B",'1'&x"D49C",'1'&x"D49D",'1'&x"D49E",'1'&x"D49F",
+--'1'&x"D4A0",'1'&x"D4A1",'1'&x"D4A2",'1'&x"D4A3",'1'&x"D4A4",'1'&x"D4A5",'1'&x"D4A6",'1'&x"D4A7",'1'&x"D4A8",'1'&x"D4A9",'1'&x"D4AA",'1'&x"D4AB",'1'&x"D4AC",'1'&x"D4AD",'1'&x"D4AE",'1'&x"D4AF",
+--'1'&x"D4B0",'1'&x"D4B1",'1'&x"D4B2",'1'&x"D4B3",'1'&x"D4B4",'1'&x"D4B5",'1'&x"D4B6",'1'&x"D4B7",'1'&x"D4B8",'1'&x"D4B9",'1'&x"D4BA",'1'&x"D4BB",'1'&x"D4BC",'1'&x"D4BD",'1'&x"D4BE",'1'&x"D4BF",
+--'1'&x"D4C0",'1'&x"D4C1",'1'&x"D4C2",'1'&x"D4C3",'1'&x"D4C4",'1'&x"D4C5",'1'&x"D4C6",'1'&x"D4C7",'1'&x"D4C8",'1'&x"D4C9",'1'&x"D4CA",'1'&x"D4CB",'1'&x"D4CC",'1'&x"D4CD",'1'&x"D4CE",'1'&x"D4CF",
+--'1'&x"D4D0",'1'&x"D4D1",'1'&x"D4D2",'1'&x"D4D3",'1'&x"D4D4",'1'&x"D4D5",'1'&x"D4D6",'1'&x"D4D7",'1'&x"D4D8",'1'&x"D4D9",'1'&x"D4DA",'1'&x"D4DB",'1'&x"D4DC",'1'&x"D4DD",'1'&x"D4DE",'1'&x"D4DF",
+--'1'&x"D4E0",'1'&x"D4E1",'1'&x"D4E2",'1'&x"D4E3",'1'&x"D4E4",'1'&x"D4E5",'1'&x"D4E6",'1'&x"D4E7",'1'&x"D4E8",'1'&x"D4E9",'1'&x"D4EA",'1'&x"D4EB",'1'&x"D4EC",'1'&x"D4ED",'1'&x"D4EE",'1'&x"D4EF",
+--'1'&x"D4F0",'1'&x"D4F1",'1'&x"D4F2",'1'&x"D4F3",'1'&x"D4F4",'1'&x"D4F5",'1'&x"D4F6",'1'&x"D4F7",'1'&x"D4F8",'1'&x"D4F9",'1'&x"D4FA",'1'&x"D4FB",'1'&x"D4FC",'1'&x"D4FD",'1'&x"D4FE",'1'&x"D4FF",
+--'1'&x"D500",'1'&x"D501",'1'&x"D502",'1'&x"D503",'1'&x"D504",'1'&x"D505",'1'&x"D506",'1'&x"D507",'1'&x"D508",'1'&x"D509",'1'&x"D50A",'1'&x"D50B",'1'&x"D50C",'1'&x"D50D",'1'&x"D50E",'1'&x"D50F",
+--'1'&x"D510",'1'&x"D511",'1'&x"D512",'1'&x"D513",'1'&x"D514",'1'&x"D515",'1'&x"D516",'1'&x"D517",'1'&x"D518",'1'&x"D519",'1'&x"D51A",'1'&x"D51B",'1'&x"D51C",'1'&x"D51D",'1'&x"D51E",'1'&x"D51F",
+--'1'&x"D520",'1'&x"D521",'1'&x"D522",'1'&x"D523",'1'&x"D524",'1'&x"D525",'1'&x"D526",'1'&x"D527",'1'&x"D528",'1'&x"D529",'1'&x"D52A",'1'&x"D52B",'1'&x"D52C",'1'&x"D52D",'1'&x"D52E",'1'&x"D52F",
+--'1'&x"D530",'1'&x"D531",'1'&x"D532",'1'&x"D533",'1'&x"D534",'1'&x"D535",'1'&x"D536",'1'&x"D537",'1'&x"D538",'1'&x"D539",'1'&x"D53A",'1'&x"D53B",'1'&x"D53C",'1'&x"D53D",'1'&x"D53E",'1'&x"D53F",
+--'1'&x"D540",'1'&x"D541",'1'&x"D542",'1'&x"D543",'1'&x"D544",'1'&x"D545",'1'&x"D546",'1'&x"D547",'1'&x"D548",'1'&x"D549",'1'&x"D54A",'1'&x"D54B",'1'&x"D54C",'1'&x"D54D",'1'&x"D54E",'1'&x"D54F",
+--'1'&x"D550",'1'&x"D551",'1'&x"D552",'1'&x"D553",'1'&x"D554",'1'&x"D555",'1'&x"D556",'1'&x"D557",'1'&x"D558",'1'&x"D559",'1'&x"D55A",'1'&x"D55B",'1'&x"D55C",'1'&x"D55D",'1'&x"D55E",'1'&x"D55F",
+--'1'&x"D560",'1'&x"D561",'1'&x"D562",'1'&x"D563",'1'&x"D564",'1'&x"D565",'1'&x"D566",'1'&x"D567",'1'&x"D568",'1'&x"D569",'1'&x"D56A",'1'&x"D56B",'1'&x"D56C",'1'&x"D56D",'1'&x"D56E",'1'&x"D56F",
+--'1'&x"D570",'1'&x"D571",'1'&x"D572",'1'&x"D573",'1'&x"D574",'1'&x"D575",'1'&x"D576",'1'&x"D577",'1'&x"D578",'1'&x"D579",'1'&x"D57A",'1'&x"D57B",'1'&x"D57C",'1'&x"D57D",'1'&x"D57E",'1'&x"D57F",
+--'1'&x"D580",'1'&x"D581",'1'&x"D582",'1'&x"D583",'1'&x"D584",'1'&x"D585",'1'&x"D586",'1'&x"D587",'1'&x"D588",'1'&x"D589",'1'&x"D58A",'1'&x"D58B",'1'&x"D58C",'1'&x"D58D",'1'&x"D58E",'1'&x"D58F",
+--'1'&x"D590",'1'&x"D591",'1'&x"D592",'1'&x"D593",'1'&x"D594",'1'&x"D595",'1'&x"D596",'1'&x"D597",'1'&x"D598",'1'&x"D599",'1'&x"D59A",'1'&x"D59B",'1'&x"D59C",'1'&x"D59D",'1'&x"D59E",'1'&x"D59F",
+--'1'&x"D5A0",'1'&x"D5A1",'1'&x"D5A2",'1'&x"D5A3",'1'&x"D5A4",'1'&x"D5A5",'1'&x"D5A6",'1'&x"D5A7",'1'&x"D5A8",'1'&x"D5A9",'1'&x"D5AA",'1'&x"D5AB",'1'&x"D5AC",'1'&x"D5AD",'1'&x"D5AE",'1'&x"D5AF",
+--'1'&x"D5B0",'1'&x"D5B1",'1'&x"D5B2",'1'&x"D5B3",'1'&x"D5B4",'1'&x"D5B5",'1'&x"D5B6",'1'&x"D5B7",'1'&x"D5B8",'1'&x"D5B9",'1'&x"D5BA",'1'&x"D5BB",'1'&x"D5BC",'1'&x"D5BD",'1'&x"D5BE",'1'&x"D5BF",
+--'1'&x"D5C0",'1'&x"D5C1",'1'&x"D5C2",'1'&x"D5C3",'1'&x"D5C4",'1'&x"D5C5",'1'&x"D5C6",'1'&x"D5C7",'1'&x"D5C8",'1'&x"D5C9",'1'&x"D5CA",'1'&x"D5CB",'1'&x"D5CC",'1'&x"D5CD",'1'&x"D5CE",'1'&x"D5CF",
+--'1'&x"D5D0",'1'&x"D5D1",'1'&x"D5D2",'1'&x"D5D3",'1'&x"D5D4",'1'&x"D5D5",'1'&x"D5D6",'1'&x"D5D7",'1'&x"D5D8",'1'&x"D5D9",'1'&x"D5DA",'1'&x"D5DB",'1'&x"D5DC",'1'&x"D5DD",'1'&x"D5DE",'1'&x"D5DF",
+--'1'&x"D5E0",'1'&x"D5E1",'1'&x"D5E2",'1'&x"D5E3",'1'&x"D5E4",'1'&x"D5E5",'1'&x"D5E6",'1'&x"D5E7",'1'&x"D5E8",'1'&x"D5E9",'1'&x"D5EA",'1'&x"D5EB",'1'&x"D5EC",'1'&x"D5ED",'1'&x"D5EE",'1'&x"D5EF",
+--'1'&x"D5F0",'1'&x"D5F1",'1'&x"D5F2",'1'&x"D5F3",'1'&x"D5F4",'1'&x"D5F5",'1'&x"D5F6",'1'&x"D5F7",'1'&x"D5F8",'1'&x"D5F9",'1'&x"D5FA",'1'&x"D5FB",'1'&x"D5FC",'1'&x"D5FD",'1'&x"D5FE",'1'&x"D5FF",
+--'1'&x"D600",'1'&x"D601",'1'&x"D602",'1'&x"D603",'1'&x"D604",'1'&x"D605",'1'&x"D606",'1'&x"D607",'1'&x"D608",'1'&x"D609",'1'&x"D60A",'1'&x"D60B",'1'&x"D60C",'1'&x"D60D",'1'&x"D60E",'1'&x"D60F",
+--'1'&x"D610",'1'&x"D611",'1'&x"D612",'1'&x"D613",'1'&x"D614",'1'&x"D615",'1'&x"D616",'1'&x"D617",'1'&x"D618",'1'&x"D619",'1'&x"D61A",'1'&x"D61B",'1'&x"D61C",'1'&x"D61D",'1'&x"D61E",'1'&x"D61F",
+--'1'&x"D620",'1'&x"D621",'1'&x"D622",'1'&x"D623",'1'&x"D624",'1'&x"D625",'1'&x"D626",'1'&x"D627",'1'&x"D628",'1'&x"D629",'1'&x"D62A",'1'&x"D62B",'1'&x"D62C",'1'&x"D62D",'1'&x"D62E",'1'&x"D62F",
+--'1'&x"D630",'1'&x"D631",'1'&x"D632",'1'&x"D633",'1'&x"D634",'1'&x"D635",'1'&x"D636",'1'&x"D637",'1'&x"D638",'1'&x"D639",'1'&x"D63A",'1'&x"D63B",'1'&x"D63C",'1'&x"D63D",'1'&x"D63E",'1'&x"D63F",
+--'1'&x"D640",'1'&x"D641",'1'&x"D642",'1'&x"D643",'1'&x"D644",'1'&x"D645",'1'&x"D646",'1'&x"D647",'1'&x"D648",'1'&x"D649",'1'&x"D64A",'1'&x"D64B",'1'&x"D64C",'1'&x"D64D",'1'&x"D64E",'1'&x"D64F",
+--'1'&x"D650",'1'&x"D651",'1'&x"D652",'1'&x"D653",'1'&x"D654",'1'&x"D655",'1'&x"D656",'1'&x"D657",'1'&x"D658",'1'&x"D659",'1'&x"D65A",'1'&x"D65B",'1'&x"D65C",'1'&x"D65D",'1'&x"D65E",'1'&x"D65F",
+--'1'&x"D660",'1'&x"D661",'1'&x"D662",'1'&x"D663",'1'&x"D664",'1'&x"D665",'1'&x"D666",'1'&x"D667",'1'&x"D668",'1'&x"D669",'1'&x"D66A",'1'&x"D66B",'1'&x"D66C",'1'&x"D66D",'1'&x"D66E",'1'&x"D66F",
+--'1'&x"D670",'1'&x"D671",'1'&x"D672",'1'&x"D673",'1'&x"D674",'1'&x"D675",'1'&x"D676",'1'&x"D677",'1'&x"D678",'1'&x"D679",'1'&x"D67A",'1'&x"D67B",'1'&x"D67C",'1'&x"D67D",'1'&x"D67E",'1'&x"D67F",
+--'1'&x"D680",'1'&x"D681",'1'&x"D682",'1'&x"D683",'1'&x"D684",'1'&x"D685",'1'&x"D686",'1'&x"D687",'1'&x"D688",'1'&x"D689",'1'&x"D68A",'1'&x"D68B",'1'&x"D68C",'1'&x"D68D",'1'&x"D68E",'1'&x"D68F",
+--'1'&x"D690",'1'&x"D691",'1'&x"D692",'1'&x"D693",'1'&x"D694",'1'&x"D695",'1'&x"D696",'1'&x"D697",'1'&x"D698",'1'&x"D699",'1'&x"D69A",'1'&x"D69B",'1'&x"D69C",'1'&x"D69D",'1'&x"D69E",'1'&x"D69F",
+--'1'&x"D6A0",'1'&x"D6A1",'1'&x"D6A2",'1'&x"D6A3",'1'&x"D6A4",'1'&x"D6A5",'1'&x"D6A6",'1'&x"D6A7",'1'&x"D6A8",'1'&x"D6A9",'1'&x"D6AA",'1'&x"D6AB",'1'&x"D6AC",'1'&x"D6AD",'1'&x"D6AE",'1'&x"D6AF",
+--'1'&x"D6B0",'1'&x"D6B1",'1'&x"D6B2",'1'&x"D6B3",'1'&x"D6B4",'1'&x"D6B5",'1'&x"D6B6",'1'&x"D6B7",'1'&x"D6B8",'1'&x"D6B9",'1'&x"D6BA",'1'&x"D6BB",'1'&x"D6BC",'1'&x"D6BD",'1'&x"D6BE",'1'&x"D6BF",
+--'1'&x"D6C0",'1'&x"D6C1",'1'&x"D6C2",'1'&x"D6C3",'1'&x"D6C4",'1'&x"D6C5",'1'&x"D6C6",'1'&x"D6C7",'1'&x"D6C8",'1'&x"D6C9",'1'&x"D6CA",'1'&x"D6CB",'1'&x"D6CC",'1'&x"D6CD",'1'&x"D6CE",'1'&x"D6CF",
+--'1'&x"D6D0",'1'&x"D6D1",'1'&x"D6D2",'1'&x"D6D3",'1'&x"D6D4",'1'&x"D6D5",'1'&x"D6D6",'1'&x"D6D7",'1'&x"D6D8",'1'&x"D6D9",'1'&x"D6DA",'1'&x"D6DB",'1'&x"D6DC",'1'&x"D6DD",'1'&x"D6DE",'1'&x"D6DF",
+--'1'&x"D6E0",'1'&x"D6E1",'1'&x"D6E2",'1'&x"D6E3",'1'&x"D6E4",'1'&x"D6E5",'1'&x"D6E6",'1'&x"D6E7",'1'&x"D6E8",'1'&x"D6E9",'1'&x"D6EA",'1'&x"D6EB",'1'&x"D6EC",'1'&x"D6ED",'1'&x"D6EE",'1'&x"D6EF",
+--'1'&x"D6F0",'1'&x"D6F1",'1'&x"D6F2",'1'&x"D6F3",'1'&x"D6F4",'1'&x"D6F5",'1'&x"D6F6",'1'&x"D6F7",'1'&x"D6F8",'1'&x"D6F9",'1'&x"D6FA",'1'&x"D6FB",'1'&x"D6FC",'1'&x"D6FD",'1'&x"D6FE",'1'&x"D6FF",
+--'1'&x"D700",'1'&x"D701",'1'&x"D702",'1'&x"D703",'1'&x"D704",'1'&x"D705",'1'&x"D706",'1'&x"D707",'1'&x"D708",'1'&x"D709",'1'&x"D70A",'1'&x"D70B",'1'&x"D70C",'1'&x"D70D",'1'&x"D70E",'1'&x"D70F",
+--'1'&x"D710",'1'&x"D711",'1'&x"D712",'1'&x"D713",'1'&x"D714",'1'&x"D715",'1'&x"D716",'1'&x"D717",'1'&x"D718",'1'&x"D719",'1'&x"D71A",'1'&x"D71B",'1'&x"D71C",'1'&x"D71D",'1'&x"D71E",'1'&x"D71F",
+--'1'&x"D720",'1'&x"D721",'1'&x"D722",'1'&x"D723",'1'&x"D724",'1'&x"D725",'1'&x"D726",'1'&x"D727",'1'&x"D728",'1'&x"D729",'1'&x"D72A",'1'&x"D72B",'1'&x"D72C",'1'&x"D72D",'1'&x"D72E",'1'&x"D72F",
+--'1'&x"D730",'1'&x"D731",'1'&x"D732",'1'&x"D733",'1'&x"D734",'1'&x"D735",'1'&x"D736",'1'&x"D737",'1'&x"D738",'1'&x"D739",'1'&x"D73A",'1'&x"D73B",'1'&x"D73C",'1'&x"D73D",'1'&x"D73E",'1'&x"D73F",
+--'1'&x"D740",'1'&x"D741",'1'&x"D742",'1'&x"D743",'1'&x"D744",'1'&x"D745",'1'&x"D746",'1'&x"D747",'1'&x"D748",'1'&x"D749",'1'&x"D74A",'1'&x"D74B",'1'&x"D74C",'1'&x"D74D",'1'&x"D74E",'1'&x"D74F",
+--'1'&x"D750",'1'&x"D751",'1'&x"D752",'1'&x"D753",'1'&x"D754",'1'&x"D755",'1'&x"D756",'1'&x"D757",'1'&x"D758",'1'&x"D759",'1'&x"D75A",'1'&x"D75B",'1'&x"D75C",'1'&x"D75D",'1'&x"D75E",'1'&x"D75F",
+--'1'&x"D760",'1'&x"D761",'1'&x"D762",'1'&x"D763",'1'&x"D764",'1'&x"D765",'1'&x"D766",'1'&x"D767",'1'&x"D768",'1'&x"D769",'1'&x"D76A",'1'&x"D76B",'1'&x"D76C",'1'&x"D76D",'1'&x"D76E",'1'&x"D76F",
+--'1'&x"D770",'1'&x"D771",'1'&x"D772",'1'&x"D773",'1'&x"D774",'1'&x"D775",'1'&x"D776",'1'&x"D777",'1'&x"D778",'1'&x"D779",'1'&x"D77A",'1'&x"D77B",'1'&x"D77C",'1'&x"D77D",'1'&x"D77E",'1'&x"D77F",
+--'1'&x"D780",'1'&x"D781",'1'&x"D782",'1'&x"D783",'1'&x"D784",'1'&x"D785",'1'&x"D786",'1'&x"D787",'1'&x"D788",'1'&x"D789",'1'&x"D78A",'1'&x"D78B",'1'&x"D78C",'1'&x"D78D",'1'&x"D78E",'1'&x"D78F",
+--'1'&x"D790",'1'&x"D791",'1'&x"D792",'1'&x"D793",'1'&x"D794",'1'&x"D795",'1'&x"D796",'1'&x"D797",'1'&x"D798",'1'&x"D799",'1'&x"D79A",'1'&x"D79B",'1'&x"D79C",'1'&x"D79D",'1'&x"D79E",'1'&x"D79F",
+--'1'&x"D7A0",'1'&x"D7A1",'1'&x"D7A2",'1'&x"D7A3",'1'&x"D7A4",'1'&x"D7A5",'1'&x"D7A6",'1'&x"D7A7",'1'&x"D7A8",'1'&x"D7A9",'1'&x"D7AA",'1'&x"D7AB",'1'&x"D7AC",'1'&x"D7AD",'1'&x"D7AE",'1'&x"D7AF",
+--'1'&x"D7B0",'1'&x"D7B1",'1'&x"D7B2",'1'&x"D7B3",'1'&x"D7B4",'1'&x"D7B5",'1'&x"D7B6",'1'&x"D7B7",'1'&x"D7B8",'1'&x"D7B9",'1'&x"D7BA",'1'&x"D7BB",'1'&x"D7BC",'1'&x"D7BD",'1'&x"D7BE",'1'&x"D7BF",
+--'1'&x"D7C0",'1'&x"D7C1",'1'&x"D7C2",'1'&x"D7C3",'1'&x"D7C4",'1'&x"D7C5",'1'&x"D7C6",'1'&x"D7C7",'1'&x"D7C8",'1'&x"D7C9",'1'&x"D7CA",'1'&x"D7CB",'1'&x"D7CC",'1'&x"D7CD",'1'&x"D7CE",'1'&x"D7CF",
+--'1'&x"D7D0",'1'&x"D7D1",'1'&x"D7D2",'1'&x"D7D3",'1'&x"D7D4",'1'&x"D7D5",'1'&x"D7D6",'1'&x"D7D7",'1'&x"D7D8",'1'&x"D7D9",'1'&x"D7DA",'1'&x"D7DB",'1'&x"D7DC",'1'&x"D7DD",'1'&x"D7DE",'1'&x"D7DF",
+--'1'&x"D7E0",'1'&x"D7E1",'1'&x"D7E2",'1'&x"D7E3",'1'&x"D7E4",'1'&x"D7E5",'1'&x"D7E6",'1'&x"D7E7",'1'&x"D7E8",'1'&x"D7E9",'1'&x"D7EA",'1'&x"D7EB",'1'&x"D7EC",'1'&x"D7ED",'1'&x"D7EE",'1'&x"D7EF",
+--'1'&x"D7F0",'1'&x"D7F1",'1'&x"D7F2",'1'&x"D7F3",'1'&x"D7F4",'1'&x"D7F5",'1'&x"D7F6",'1'&x"D7F7",'1'&x"D7F8",'1'&x"D7F9",'1'&x"D7FA",'1'&x"D7FB",'1'&x"D7FC",'1'&x"D7FD",'1'&x"D7FE",'1'&x"D7FF",
+--'1'&x"D800",'1'&x"D801",'1'&x"D802",'1'&x"D803",'1'&x"D804",'1'&x"D805",'1'&x"D806",'1'&x"D807",'1'&x"D808",'1'&x"D809",'1'&x"D80A",'1'&x"D80B",'1'&x"D80C",'1'&x"D80D",'1'&x"D80E",'1'&x"D80F",
+--'1'&x"D810",'1'&x"D811",'1'&x"D812",'1'&x"D813",'1'&x"D814",'1'&x"D815",'1'&x"D816",'1'&x"D817",'1'&x"D818",'1'&x"D819",'1'&x"D81A",'1'&x"D81B",'1'&x"D81C",'1'&x"D81D",'1'&x"D81E",'1'&x"D81F",
+--'1'&x"D820",'1'&x"D821",'1'&x"D822",'1'&x"D823",'1'&x"D824",'1'&x"D825",'1'&x"D826",'1'&x"D827",'1'&x"D828",'1'&x"D829",'1'&x"D82A",'1'&x"D82B",'1'&x"D82C",'1'&x"D82D",'1'&x"D82E",'1'&x"D82F",
+--'1'&x"D830",'1'&x"D831",'1'&x"D832",'1'&x"D833",'1'&x"D834",'1'&x"D835",'1'&x"D836",'1'&x"D837",'1'&x"D838",'1'&x"D839",'1'&x"D83A",'1'&x"D83B",'1'&x"D83C",'1'&x"D83D",'1'&x"D83E",'1'&x"D83F",
+--'1'&x"D840",'1'&x"D841",'1'&x"D842",'1'&x"D843",'1'&x"D844",'1'&x"D845",'1'&x"D846",'1'&x"D847",'1'&x"D848",'1'&x"D849",'1'&x"D84A",'1'&x"D84B",'1'&x"D84C",'1'&x"D84D",'1'&x"D84E",'1'&x"D84F",
+--'1'&x"D850",'1'&x"D851",'1'&x"D852",'1'&x"D853",'1'&x"D854",'1'&x"D855",'1'&x"D856",'1'&x"D857",'1'&x"D858",'1'&x"D859",'1'&x"D85A",'1'&x"D85B",'1'&x"D85C",'1'&x"D85D",'1'&x"D85E",'1'&x"D85F",
+--'1'&x"D860",'1'&x"D861",'1'&x"D862",'1'&x"D863",'1'&x"D864",'1'&x"D865",'1'&x"D866",'1'&x"D867",'1'&x"D868",'1'&x"D869",'1'&x"D86A",'1'&x"D86B",'1'&x"D86C",'1'&x"D86D",'1'&x"D86E",'1'&x"D86F",
+--'1'&x"D870",'1'&x"D871",'1'&x"D872",'1'&x"D873",'1'&x"D874",'1'&x"D875",'1'&x"D876",'1'&x"D877",'1'&x"D878",'1'&x"D879",'1'&x"D87A",'1'&x"D87B",'1'&x"D87C",'1'&x"D87D",'1'&x"D87E",'1'&x"D87F",
+--'1'&x"D880",'1'&x"D881",'1'&x"D882",'1'&x"D883",'1'&x"D884",'1'&x"D885",'1'&x"D886",'1'&x"D887",'1'&x"D888",'1'&x"D889",'1'&x"D88A",'1'&x"D88B",'1'&x"D88C",'1'&x"D88D",'1'&x"D88E",'1'&x"D88F",
+--'1'&x"D890",'1'&x"D891",'1'&x"D892",'1'&x"D893",'1'&x"D894",'1'&x"D895",'1'&x"D896",'1'&x"D897",'1'&x"D898",'1'&x"D899",'1'&x"D89A",'1'&x"D89B",'1'&x"D89C",'1'&x"D89D",'1'&x"D89E",'1'&x"D89F",
+--'1'&x"D8A0",'1'&x"D8A1",'1'&x"D8A2",'1'&x"D8A3",'1'&x"D8A4",'1'&x"D8A5",'1'&x"D8A6",'1'&x"D8A7",'1'&x"D8A8",'1'&x"D8A9",'1'&x"D8AA",'1'&x"D8AB",'1'&x"D8AC",'1'&x"D8AD",'1'&x"D8AE",'1'&x"D8AF",
+--'1'&x"D8B0",'1'&x"D8B1",'1'&x"D8B2",'1'&x"D8B3",'1'&x"D8B4",'1'&x"D8B5",'1'&x"D8B6",'1'&x"D8B7",'1'&x"D8B8",'1'&x"D8B9",'1'&x"D8BA",'1'&x"D8BB",'1'&x"D8BC",'1'&x"D8BD",'1'&x"D8BE",'1'&x"D8BF",
+--'1'&x"D8C0",'1'&x"D8C1",'1'&x"D8C2",'1'&x"D8C3",'1'&x"D8C4",'1'&x"D8C5",'1'&x"D8C6",'1'&x"D8C7",'1'&x"D8C8",'1'&x"D8C9",'1'&x"D8CA",'1'&x"D8CB",'1'&x"D8CC",'1'&x"D8CD",'1'&x"D8CE",'1'&x"D8CF",
+--'1'&x"D8D0",'1'&x"D8D1",'1'&x"D8D2",'1'&x"D8D3",'1'&x"D8D4",'1'&x"D8D5",'1'&x"D8D6",'1'&x"D8D7",'1'&x"D8D8",'1'&x"D8D9",'1'&x"D8DA",'1'&x"D8DB",'1'&x"D8DC",'1'&x"D8DD",'1'&x"D8DE",'1'&x"D8DF",
+--'1'&x"D8E0",'1'&x"D8E1",'1'&x"D8E2",'1'&x"D8E3",'1'&x"D8E4",'1'&x"D8E5",'1'&x"D8E6",'1'&x"D8E7",'1'&x"D8E8",'1'&x"D8E9",'1'&x"D8EA",'1'&x"D8EB",'1'&x"D8EC",'1'&x"D8ED",'1'&x"D8EE",'1'&x"D8EF",
+--'1'&x"D8F0",'1'&x"D8F1",'1'&x"D8F2",'1'&x"D8F3",'1'&x"D8F4",'1'&x"D8F5",'1'&x"D8F6",'1'&x"D8F7",'1'&x"D8F8",'1'&x"D8F9",'1'&x"D8FA",'1'&x"D8FB",'1'&x"D8FC",'1'&x"D8FD",'1'&x"D8FE",'1'&x"D8FF",
+--'1'&x"D900",'1'&x"D901",'1'&x"D902",'1'&x"D903",'1'&x"D904",'1'&x"D905",'1'&x"D906",'1'&x"D907",'1'&x"D908",'1'&x"D909",'1'&x"D90A",'1'&x"D90B",'1'&x"D90C",'1'&x"D90D",'1'&x"D90E",'1'&x"D90F",
+--'1'&x"D910",'1'&x"D911",'1'&x"D912",'1'&x"D913",'1'&x"D914",'1'&x"D915",'1'&x"D916",'1'&x"D917",'1'&x"D918",'1'&x"D919",'1'&x"D91A",'1'&x"D91B",'1'&x"D91C",'1'&x"D91D",'1'&x"D91E",'1'&x"D91F",
+--'1'&x"D920",'1'&x"D921",'1'&x"D922",'1'&x"D923",'1'&x"D924",'1'&x"D925",'1'&x"D926",'1'&x"D927",'1'&x"D928",'1'&x"D929",'1'&x"D92A",'1'&x"D92B",'1'&x"D92C",'1'&x"D92D",'1'&x"D92E",'1'&x"D92F",
+--'1'&x"D930",'1'&x"D931",'1'&x"D932",'1'&x"D933",'1'&x"D934",'1'&x"D935",'1'&x"D936",'1'&x"D937",'1'&x"D938",'1'&x"D939",'1'&x"D93A",'1'&x"D93B",'1'&x"D93C",'1'&x"D93D",'1'&x"D93E",'1'&x"D93F",
+--'1'&x"D940",'1'&x"D941",'1'&x"D942",'1'&x"D943",'1'&x"D944",'1'&x"D945",'1'&x"D946",'1'&x"D947",'1'&x"D948",'1'&x"D949",'1'&x"D94A",'1'&x"D94B",'1'&x"D94C",'1'&x"D94D",'1'&x"D94E",'1'&x"D94F",
+--'1'&x"D950",'1'&x"D951",'1'&x"D952",'1'&x"D953",'1'&x"D954",'1'&x"D955",'1'&x"D956",'1'&x"D957",'1'&x"D958",'1'&x"D959",'1'&x"D95A",'1'&x"D95B",'1'&x"D95C",'1'&x"D95D",'1'&x"D95E",'1'&x"D95F",
+--'1'&x"D960",'1'&x"D961",'1'&x"D962",'1'&x"D963",'1'&x"D964",'1'&x"D965",'1'&x"D966",'1'&x"D967",'1'&x"D968",'1'&x"D969",'1'&x"D96A",'1'&x"D96B",'1'&x"D96C",'1'&x"D96D",'1'&x"D96E",'1'&x"D96F",
+--'1'&x"D970",'1'&x"D971",'1'&x"D972",'1'&x"D973",'1'&x"D974",'1'&x"D975",'1'&x"D976",'1'&x"D977",'1'&x"D978",'1'&x"D979",'1'&x"D97A",'1'&x"D97B",'1'&x"D97C",'1'&x"D97D",'1'&x"D97E",'1'&x"D97F",
+--'1'&x"D980",'1'&x"D981",'1'&x"D982",'1'&x"D983",'1'&x"D984",'1'&x"D985",'1'&x"D986",'1'&x"D987",'1'&x"D988",'1'&x"D989",'1'&x"D98A",'1'&x"D98B",'1'&x"D98C",'1'&x"D98D",'1'&x"D98E",'1'&x"D98F",
+--'1'&x"D990",'1'&x"D991",'1'&x"D992",'1'&x"D993",'1'&x"D994",'1'&x"D995",'1'&x"D996",'1'&x"D997",'1'&x"D998",'1'&x"D999",'1'&x"D99A",'1'&x"D99B",'1'&x"D99C",'1'&x"D99D",'1'&x"D99E",'1'&x"D99F",
+--'1'&x"D9A0",'1'&x"D9A1",'1'&x"D9A2",'1'&x"D9A3",'1'&x"D9A4",'1'&x"D9A5",'1'&x"D9A6",'1'&x"D9A7",'1'&x"D9A8",'1'&x"D9A9",'1'&x"D9AA",'1'&x"D9AB",'1'&x"D9AC",'1'&x"D9AD",'1'&x"D9AE",'1'&x"D9AF",
+--'1'&x"D9B0",'1'&x"D9B1",'1'&x"D9B2",'1'&x"D9B3",'1'&x"D9B4",'1'&x"D9B5",'1'&x"D9B6",'1'&x"D9B7",'1'&x"D9B8",'1'&x"D9B9",'1'&x"D9BA",'1'&x"D9BB",'1'&x"D9BC",'1'&x"D9BD",'1'&x"D9BE",'1'&x"D9BF",
+--'1'&x"D9C0",'1'&x"D9C1",'1'&x"D9C2",'1'&x"D9C3",'1'&x"D9C4",'1'&x"D9C5",'1'&x"D9C6",'1'&x"D9C7",'1'&x"D9C8",'1'&x"D9C9",'1'&x"D9CA",'1'&x"D9CB",'1'&x"D9CC",'1'&x"D9CD",'1'&x"D9CE",'1'&x"D9CF",
+--'1'&x"D9D0",'1'&x"D9D1",'1'&x"D9D2",'1'&x"D9D3",'1'&x"D9D4",'1'&x"D9D5",'1'&x"D9D6",'1'&x"D9D7",'1'&x"D9D8",'1'&x"D9D9",'1'&x"D9DA",'1'&x"D9DB",'1'&x"D9DC",'1'&x"D9DD",'1'&x"D9DE",'1'&x"D9DF",
+--'1'&x"D9E0",'1'&x"D9E1",'1'&x"D9E2",'1'&x"D9E3",'1'&x"D9E4",'1'&x"D9E5",'1'&x"D9E6",'1'&x"D9E7",'1'&x"D9E8",'1'&x"D9E9",'1'&x"D9EA",'1'&x"D9EB",'1'&x"D9EC",'1'&x"D9ED",'1'&x"D9EE",'1'&x"D9EF",
+--'1'&x"D9F0",'1'&x"D9F1",'1'&x"D9F2",'1'&x"D9F3",'1'&x"D9F4",'1'&x"D9F5",'1'&x"D9F6",'1'&x"D9F7",'1'&x"D9F8",'1'&x"D9F9",'1'&x"D9FA",'1'&x"D9FB",'1'&x"D9FC",'1'&x"D9FD",'1'&x"D9FE",'1'&x"D9FF",
+--'1'&x"DA00",'1'&x"DA01",'1'&x"DA02",'1'&x"DA03",'1'&x"DA04",'1'&x"DA05",'1'&x"DA06",'1'&x"DA07",'1'&x"DA08",'1'&x"DA09",'1'&x"DA0A",'1'&x"DA0B",'1'&x"DA0C",'1'&x"DA0D",'1'&x"DA0E",'1'&x"DA0F",
+--'1'&x"DA10",'1'&x"DA11",'1'&x"DA12",'1'&x"DA13",'1'&x"DA14",'1'&x"DA15",'1'&x"DA16",'1'&x"DA17",'1'&x"DA18",'1'&x"DA19",'1'&x"DA1A",'1'&x"DA1B",'1'&x"DA1C",'1'&x"DA1D",'1'&x"DA1E",'1'&x"DA1F",
+--'1'&x"DA20",'1'&x"DA21",'1'&x"DA22",'1'&x"DA23",'1'&x"DA24",'1'&x"DA25",'1'&x"DA26",'1'&x"DA27",'1'&x"DA28",'1'&x"DA29",'1'&x"DA2A",'1'&x"DA2B",'1'&x"DA2C",'1'&x"DA2D",'1'&x"DA2E",'1'&x"DA2F",
+--'1'&x"DA30",'1'&x"DA31",'1'&x"DA32",'1'&x"DA33",'1'&x"DA34",'1'&x"DA35",'1'&x"DA36",'1'&x"DA37",'1'&x"DA38",'1'&x"DA39",'1'&x"DA3A",'1'&x"DA3B",'1'&x"DA3C",'1'&x"DA3D",'1'&x"DA3E",'1'&x"DA3F",
+--'1'&x"DA40",'1'&x"DA41",'1'&x"DA42",'1'&x"DA43",'1'&x"DA44",'1'&x"DA45",'1'&x"DA46",'1'&x"DA47",'1'&x"DA48",'1'&x"DA49",'1'&x"DA4A",'1'&x"DA4B",'1'&x"DA4C",'1'&x"DA4D",'1'&x"DA4E",'1'&x"DA4F",
+--'1'&x"DA50",'1'&x"DA51",'1'&x"DA52",'1'&x"DA53",'1'&x"DA54",'1'&x"DA55",'1'&x"DA56",'1'&x"DA57",'1'&x"DA58",'1'&x"DA59",'1'&x"DA5A",'1'&x"DA5B",'1'&x"DA5C",'1'&x"DA5D",'1'&x"DA5E",'1'&x"DA5F",
+--'1'&x"DA60",'1'&x"DA61",'1'&x"DA62",'1'&x"DA63",'1'&x"DA64",'1'&x"DA65",'1'&x"DA66",'1'&x"DA67",'1'&x"DA68",'1'&x"DA69",'1'&x"DA6A",'1'&x"DA6B",'1'&x"DA6C",'1'&x"DA6D",'1'&x"DA6E",'1'&x"DA6F",
+--'1'&x"DA70",'1'&x"DA71",'1'&x"DA72",'1'&x"DA73",'1'&x"DA74",'1'&x"DA75",'1'&x"DA76",'1'&x"DA77",'1'&x"DA78",'1'&x"DA79",'1'&x"DA7A",'1'&x"DA7B",'1'&x"DA7C",'1'&x"DA7D",'1'&x"DA7E",'1'&x"DA7F",
+--'1'&x"DA80",'1'&x"DA81",'1'&x"DA82",'1'&x"DA83",'1'&x"DA84",'1'&x"DA85",'1'&x"DA86",'1'&x"DA87",'1'&x"DA88",'1'&x"DA89",'1'&x"DA8A",'1'&x"DA8B",'1'&x"DA8C",'1'&x"DA8D",'1'&x"DA8E",'1'&x"DA8F",
+--'1'&x"DA90",'1'&x"DA91",'1'&x"DA92",'1'&x"DA93",'1'&x"DA94",'1'&x"DA95",'1'&x"DA96",'1'&x"DA97",'1'&x"DA98",'1'&x"DA99",'1'&x"DA9A",'1'&x"DA9B",'1'&x"DA9C",'1'&x"DA9D",'1'&x"DA9E",'1'&x"DA9F",
+--'1'&x"DAA0",'1'&x"DAA1",'1'&x"DAA2",'1'&x"DAA3",'1'&x"DAA4",'1'&x"DAA5",'1'&x"DAA6",'1'&x"DAA7",'1'&x"DAA8",'1'&x"DAA9",'1'&x"DAAA",'1'&x"DAAB",'1'&x"DAAC",'1'&x"DAAD",'1'&x"DAAE",'1'&x"DAAF",
+--'1'&x"DAB0",'1'&x"DAB1",'1'&x"DAB2",'1'&x"DAB3",'1'&x"DAB4",'1'&x"DAB5",'1'&x"DAB6",'1'&x"DAB7",'1'&x"DAB8",'1'&x"DAB9",'1'&x"DABA",'1'&x"DABB",'1'&x"DABC",'1'&x"DABD",'1'&x"DABE",'1'&x"DABF",
+--'1'&x"DAC0",'1'&x"DAC1",'1'&x"DAC2",'1'&x"DAC3",'1'&x"DAC4",'1'&x"DAC5",'1'&x"DAC6",'1'&x"DAC7",'1'&x"DAC8",'1'&x"DAC9",'1'&x"DACA",'1'&x"DACB",'1'&x"DACC",'1'&x"DACD",'1'&x"DACE",'1'&x"DACF",
+--'1'&x"DAD0",'1'&x"DAD1",'1'&x"DAD2",'1'&x"DAD3",'1'&x"DAD4",'1'&x"DAD5",'1'&x"DAD6",'1'&x"DAD7",'1'&x"DAD8",'1'&x"DAD9",'1'&x"DADA",'1'&x"DADB",'1'&x"DADC",'1'&x"DADD",'1'&x"DADE",'1'&x"DADF",
+--'1'&x"DAE0",'1'&x"DAE1",'1'&x"DAE2",'1'&x"DAE3",'1'&x"DAE4",'1'&x"DAE5",'1'&x"DAE6",'1'&x"DAE7",'1'&x"DAE8",'1'&x"DAE9",'1'&x"DAEA",'1'&x"DAEB",'1'&x"DAEC",'1'&x"DAED",'1'&x"DAEE",'1'&x"DAEF",
+--'1'&x"DAF0",'1'&x"DAF1",'1'&x"DAF2",'1'&x"DAF3",'1'&x"DAF4",'1'&x"DAF5",'1'&x"DAF6",'1'&x"DAF7",'1'&x"DAF8",'1'&x"DAF9",'1'&x"DAFA",'1'&x"DAFB",'1'&x"DAFC",'1'&x"DAFD",'1'&x"DAFE",'1'&x"DAFF",
+--'1'&x"DB00",'1'&x"DB01",'1'&x"DB02",'1'&x"DB03",'1'&x"DB04",'1'&x"DB05",'1'&x"DB06",'1'&x"DB07",'1'&x"DB08",'1'&x"DB09",'1'&x"DB0A",'1'&x"DB0B",'1'&x"DB0C",'1'&x"DB0D",'1'&x"DB0E",'1'&x"DB0F",
+--'1'&x"DB10",'1'&x"DB11",'1'&x"DB12",'1'&x"DB13",'1'&x"DB14",'1'&x"DB15",'1'&x"DB16",'1'&x"DB17",'1'&x"DB18",'1'&x"DB19",'1'&x"DB1A",'1'&x"DB1B",'1'&x"DB1C",'1'&x"DB1D",'1'&x"DB1E",'1'&x"DB1F",
+--'1'&x"DB20",'1'&x"DB21",'1'&x"DB22",'1'&x"DB23",'1'&x"DB24",'1'&x"DB25",'1'&x"DB26",'1'&x"DB27",'1'&x"DB28",'1'&x"DB29",'1'&x"DB2A",'1'&x"DB2B",'1'&x"DB2C",'1'&x"DB2D",'1'&x"DB2E",'1'&x"DB2F",
+--'1'&x"DB30",'1'&x"DB31",'1'&x"DB32",'1'&x"DB33",'1'&x"DB34",'1'&x"DB35",'1'&x"DB36",'1'&x"DB37",'1'&x"DB38",'1'&x"DB39",'1'&x"DB3A",'1'&x"DB3B",'1'&x"DB3C",'1'&x"DB3D",'1'&x"DB3E",'1'&x"DB3F",
+--'1'&x"DB40",'1'&x"DB41",'1'&x"DB42",'1'&x"DB43",'1'&x"DB44",'1'&x"DB45",'1'&x"DB46",'1'&x"DB47",'1'&x"DB48",'1'&x"DB49",'1'&x"DB4A",'1'&x"DB4B",'1'&x"DB4C",'1'&x"DB4D",'1'&x"DB4E",'1'&x"DB4F",
+--'1'&x"DB50",'1'&x"DB51",'1'&x"DB52",'1'&x"DB53",'1'&x"DB54",'1'&x"DB55",'1'&x"DB56",'1'&x"DB57",'1'&x"DB58",'1'&x"DB59",'1'&x"DB5A",'1'&x"DB5B",'1'&x"DB5C",'1'&x"DB5D",'1'&x"DB5E",'1'&x"DB5F",
+--'1'&x"DB60",'1'&x"DB61",'1'&x"DB62",'1'&x"DB63",'1'&x"DB64",'1'&x"DB65",'1'&x"DB66",'1'&x"DB67",'1'&x"DB68",'1'&x"DB69",'1'&x"DB6A",'1'&x"DB6B",'1'&x"DB6C",'1'&x"DB6D",'1'&x"DB6E",'1'&x"DB6F",
+--'1'&x"DB70",'1'&x"DB71",'1'&x"DB72",'1'&x"DB73",'1'&x"DB74",'1'&x"DB75",'1'&x"DB76",'1'&x"DB77",'1'&x"DB78",'1'&x"DB79",'1'&x"DB7A",'1'&x"DB7B",'1'&x"DB7C",'1'&x"DB7D",'1'&x"DB7E",'1'&x"DB7F",
+--'1'&x"DB80",'1'&x"DB81",'1'&x"DB82",'1'&x"DB83",'1'&x"DB84",'1'&x"DB85",'1'&x"DB86",'1'&x"DB87",'1'&x"DB88",'1'&x"DB89",'1'&x"DB8A",'1'&x"DB8B",'1'&x"DB8C",'1'&x"DB8D",'1'&x"DB8E",'1'&x"DB8F",
+--'1'&x"DB90",'1'&x"DB91",'1'&x"DB92",'1'&x"DB93",'1'&x"DB94",'1'&x"DB95",'1'&x"DB96",'1'&x"DB97",'1'&x"DB98",'1'&x"DB99",'1'&x"DB9A",'1'&x"DB9B",'1'&x"DB9C",'1'&x"DB9D",'1'&x"DB9E",'1'&x"DB9F",
+--'1'&x"DBA0",'1'&x"DBA1",'1'&x"DBA2",'1'&x"DBA3",'1'&x"DBA4",'1'&x"DBA5",'1'&x"DBA6",'1'&x"DBA7",'1'&x"DBA8",'1'&x"DBA9",'1'&x"DBAA",'1'&x"DBAB",'1'&x"DBAC",'1'&x"DBAD",'1'&x"DBAE",'1'&x"DBAF",
+--'1'&x"DBB0",'1'&x"DBB1",'1'&x"DBB2",'1'&x"DBB3",'1'&x"DBB4",'1'&x"DBB5",'1'&x"DBB6",'1'&x"DBB7",'1'&x"DBB8",'1'&x"DBB9",'1'&x"DBBA",'1'&x"DBBB",'1'&x"DBBC",'1'&x"DBBD",'1'&x"DBBE",'1'&x"DBBF",
+--'1'&x"DBC0",'1'&x"DBC1",'1'&x"DBC2",'1'&x"DBC3",'1'&x"DBC4",'1'&x"DBC5",'1'&x"DBC6",'1'&x"DBC7",'1'&x"DBC8",'1'&x"DBC9",'1'&x"DBCA",'1'&x"DBCB",'1'&x"DBCC",'1'&x"DBCD",'1'&x"DBCE",'1'&x"DBCF",
+--'1'&x"DBD0",'1'&x"DBD1",'1'&x"DBD2",'1'&x"DBD3",'1'&x"DBD4",'1'&x"DBD5",'1'&x"DBD6",'1'&x"DBD7",'1'&x"DBD8",'1'&x"DBD9",'1'&x"DBDA",'1'&x"DBDB",'1'&x"DBDC",'1'&x"DBDD",'1'&x"DBDE",'1'&x"DBDF",
+--'1'&x"DBE0",'1'&x"DBE1",'1'&x"DBE2",'1'&x"DBE3",'1'&x"DBE4",'1'&x"DBE5",'1'&x"DBE6",'1'&x"DBE7",'1'&x"DBE8",'1'&x"DBE9",'1'&x"DBEA",'1'&x"DBEB",'1'&x"DBEC",'1'&x"DBED",'1'&x"DBEE",'1'&x"DBEF",
+--'1'&x"DBF0",'1'&x"DBF1",'1'&x"DBF2",'1'&x"DBF3",'1'&x"DBF4",'1'&x"DBF5",'1'&x"DBF6",'1'&x"DBF7",'1'&x"DBF8",'1'&x"DBF9",'1'&x"DBFA",'1'&x"DBFB",'1'&x"DBFC",'1'&x"DBFD",'1'&x"DBFE",'1'&x"DBFF",
+--'1'&x"DC00",'1'&x"DC01",'1'&x"DC02",'1'&x"DC03",'1'&x"DC04",'1'&x"DC05",'1'&x"DC06",'1'&x"DC07",'1'&x"DC08",'1'&x"DC09",'1'&x"DC0A",'1'&x"DC0B",'1'&x"DC0C",'1'&x"DC0D",'1'&x"DC0E",'1'&x"DC0F",
+--'1'&x"DC10",'1'&x"DC11",'1'&x"DC12",'1'&x"DC13",'1'&x"DC14",'1'&x"DC15",'1'&x"DC16",'1'&x"DC17",'1'&x"DC18",'1'&x"DC19",'1'&x"DC1A",'1'&x"DC1B",'1'&x"DC1C",'1'&x"DC1D",'1'&x"DC1E",'1'&x"DC1F",
+--'1'&x"DC20",'1'&x"DC21",'1'&x"DC22",'1'&x"DC23",'1'&x"DC24",'1'&x"DC25",'1'&x"DC26",'1'&x"DC27",'1'&x"DC28",'1'&x"DC29",'1'&x"DC2A",'1'&x"DC2B",'1'&x"DC2C",'1'&x"DC2D",'1'&x"DC2E",'1'&x"DC2F",
+--'1'&x"DC30",'1'&x"DC31",'1'&x"DC32",'1'&x"DC33",'1'&x"DC34",'1'&x"DC35",'1'&x"DC36",'1'&x"DC37",'1'&x"DC38",'1'&x"DC39",'1'&x"DC3A",'1'&x"DC3B",'1'&x"DC3C",'1'&x"DC3D",'1'&x"DC3E",'1'&x"DC3F",
+--'1'&x"DC40",'1'&x"DC41",'1'&x"DC42",'1'&x"DC43",'1'&x"DC44",'1'&x"DC45",'1'&x"DC46",'1'&x"DC47",'1'&x"DC48",'1'&x"DC49",'1'&x"DC4A",'1'&x"DC4B",'1'&x"DC4C",'1'&x"DC4D",'1'&x"DC4E",'1'&x"DC4F",
+--'1'&x"DC50",'1'&x"DC51",'1'&x"DC52",'1'&x"DC53",'1'&x"DC54",'1'&x"DC55",'1'&x"DC56",'1'&x"DC57",'1'&x"DC58",'1'&x"DC59",'1'&x"DC5A",'1'&x"DC5B",'1'&x"DC5C",'1'&x"DC5D",'1'&x"DC5E",'1'&x"DC5F",
+--'1'&x"DC60",'1'&x"DC61",'1'&x"DC62",'1'&x"DC63",'1'&x"DC64",'1'&x"DC65",'1'&x"DC66",'1'&x"DC67",'1'&x"DC68",'1'&x"DC69",'1'&x"DC6A",'1'&x"DC6B",'1'&x"DC6C",'1'&x"DC6D",'1'&x"DC6E",'1'&x"DC6F",
+--'1'&x"DC70",'1'&x"DC71",'1'&x"DC72",'1'&x"DC73",'1'&x"DC74",'1'&x"DC75",'1'&x"DC76",'1'&x"DC77",'1'&x"DC78",'1'&x"DC79",'1'&x"DC7A",'1'&x"DC7B",'1'&x"DC7C",'1'&x"DC7D",'1'&x"DC7E",'1'&x"DC7F",
+--'1'&x"DC80",'1'&x"DC81",'1'&x"DC82",'1'&x"DC83",'1'&x"DC84",'1'&x"DC85",'1'&x"DC86",'1'&x"DC87",'1'&x"DC88",'1'&x"DC89",'1'&x"DC8A",'1'&x"DC8B",'1'&x"DC8C",'1'&x"DC8D",'1'&x"DC8E",'1'&x"DC8F",
+--'1'&x"DC90",'1'&x"DC91",'1'&x"DC92",'1'&x"DC93",'1'&x"DC94",'1'&x"DC95",'1'&x"DC96",'1'&x"DC97",'1'&x"DC98",'1'&x"DC99",'1'&x"DC9A",'1'&x"DC9B",'1'&x"DC9C",'1'&x"DC9D",'1'&x"DC9E",'1'&x"DC9F",
+--'1'&x"DCA0",'1'&x"DCA1",'1'&x"DCA2",'1'&x"DCA3",'1'&x"DCA4",'1'&x"DCA5",'1'&x"DCA6",'1'&x"DCA7",'1'&x"DCA8",'1'&x"DCA9",'1'&x"DCAA",'1'&x"DCAB",'1'&x"DCAC",'1'&x"DCAD",'1'&x"DCAE",'1'&x"DCAF",
+--'1'&x"DCB0",'1'&x"DCB1",'1'&x"DCB2",'1'&x"DCB3",'1'&x"DCB4",'1'&x"DCB5",'1'&x"DCB6",'1'&x"DCB7",'1'&x"DCB8",'1'&x"DCB9",'1'&x"DCBA",'1'&x"DCBB",'1'&x"DCBC",'1'&x"DCBD",'1'&x"DCBE",'1'&x"DCBF",
+--'1'&x"DCC0",'1'&x"DCC1",'1'&x"DCC2",'1'&x"DCC3",'1'&x"DCC4",'1'&x"DCC5",'1'&x"DCC6",'1'&x"DCC7",'1'&x"DCC8",'1'&x"DCC9",'1'&x"DCCA",'1'&x"DCCB",'1'&x"DCCC",'1'&x"DCCD",'1'&x"DCCE",'1'&x"DCCF",
+--'1'&x"DCD0",'1'&x"DCD1",'1'&x"DCD2",'1'&x"DCD3",'1'&x"DCD4",'1'&x"DCD5",'1'&x"DCD6",'1'&x"DCD7",'1'&x"DCD8",'1'&x"DCD9",'1'&x"DCDA",'1'&x"DCDB",'1'&x"DCDC",'1'&x"DCDD",'1'&x"DCDE",'1'&x"DCDF",
+--'1'&x"DCE0",'1'&x"DCE1",'1'&x"DCE2",'1'&x"DCE3",'1'&x"DCE4",'1'&x"DCE5",'1'&x"DCE6",'1'&x"DCE7",'1'&x"DCE8",'1'&x"DCE9",'1'&x"DCEA",'1'&x"DCEB",'1'&x"DCEC",'1'&x"DCED",'1'&x"DCEE",'1'&x"DCEF",
+--'1'&x"DCF0",'1'&x"DCF1",'1'&x"DCF2",'1'&x"DCF3",'1'&x"DCF4",'1'&x"DCF5",'1'&x"DCF6",'1'&x"DCF7",'1'&x"DCF8",'1'&x"DCF9",'1'&x"DCFA",'1'&x"DCFB",'1'&x"DCFC",'1'&x"DCFD",'1'&x"DCFE",'1'&x"DCFF",
+--'1'&x"DD00",'1'&x"DD01",'1'&x"DD02",'1'&x"DD03",'1'&x"DD04",'1'&x"DD05",'1'&x"DD06",'1'&x"DD07",'1'&x"DD08",'1'&x"DD09",'1'&x"DD0A",'1'&x"DD0B",'1'&x"DD0C",'1'&x"DD0D",'1'&x"DD0E",'1'&x"DD0F",
+--'1'&x"DD10",'1'&x"DD11",'1'&x"DD12",'1'&x"DD13",'1'&x"DD14",'1'&x"DD15",'1'&x"DD16",'1'&x"DD17",'1'&x"DD18",'1'&x"DD19",'1'&x"DD1A",'1'&x"DD1B",'1'&x"DD1C",'1'&x"DD1D",'1'&x"DD1E",'1'&x"DD1F",
+--'1'&x"DD20",'1'&x"DD21",'1'&x"DD22",'1'&x"DD23",'1'&x"DD24",'1'&x"DD25",'1'&x"DD26",'1'&x"DD27",'1'&x"DD28",'1'&x"DD29",'1'&x"DD2A",'1'&x"DD2B",'1'&x"DD2C",'1'&x"DD2D",'1'&x"DD2E",'1'&x"DD2F",
+--'1'&x"DD30",'1'&x"DD31",'1'&x"DD32",'1'&x"DD33",'1'&x"DD34",'1'&x"DD35",'1'&x"DD36",'1'&x"DD37",'1'&x"DD38",'1'&x"DD39",'1'&x"DD3A",'1'&x"DD3B",'1'&x"DD3C",'1'&x"DD3D",'1'&x"DD3E",'1'&x"DD3F",
+--'1'&x"DD40",'1'&x"DD41",'1'&x"DD42",'1'&x"DD43",'1'&x"DD44",'1'&x"DD45",'1'&x"DD46",'1'&x"DD47",'1'&x"DD48",'1'&x"DD49",'1'&x"DD4A",'1'&x"DD4B",'1'&x"DD4C",'1'&x"DD4D",'1'&x"DD4E",'1'&x"DD4F",
+--'1'&x"DD50",'1'&x"DD51",'1'&x"DD52",'1'&x"DD53",'1'&x"DD54",'1'&x"DD55",'1'&x"DD56",'1'&x"DD57",'1'&x"DD58",'1'&x"DD59",'1'&x"DD5A",'1'&x"DD5B",'1'&x"DD5C",'1'&x"DD5D",'1'&x"DD5E",'1'&x"DD5F",
+--'1'&x"DD60",'1'&x"DD61",'1'&x"DD62",'1'&x"DD63",'1'&x"DD64",'1'&x"DD65",'1'&x"DD66",'1'&x"DD67",'1'&x"DD68",'1'&x"DD69",'1'&x"DD6A",'1'&x"DD6B",'1'&x"DD6C",'1'&x"DD6D",'1'&x"DD6E",'1'&x"DD6F",
+--'1'&x"DD70",'1'&x"DD71",'1'&x"DD72",'1'&x"DD73",'1'&x"DD74",'1'&x"DD75",'1'&x"DD76",'1'&x"DD77",'1'&x"DD78",'1'&x"DD79",'1'&x"DD7A",'1'&x"DD7B",'1'&x"DD7C",'1'&x"DD7D",'1'&x"DD7E",'1'&x"DD7F",
+--'1'&x"DD80",'1'&x"DD81",'1'&x"DD82",'1'&x"DD83",'1'&x"DD84",'1'&x"DD85",'1'&x"DD86",'1'&x"DD87",'1'&x"DD88",'1'&x"DD89",'1'&x"DD8A",'1'&x"DD8B",'1'&x"DD8C",'1'&x"DD8D",'1'&x"DD8E",'1'&x"DD8F",
+--'1'&x"DD90",'1'&x"DD91",'1'&x"DD92",'1'&x"DD93",'1'&x"DD94",'1'&x"DD95",'1'&x"DD96",'1'&x"DD97",'1'&x"DD98",'1'&x"DD99",'1'&x"DD9A",'1'&x"DD9B",'1'&x"DD9C",'1'&x"DD9D",'1'&x"DD9E",'1'&x"DD9F",
+--'1'&x"DDA0",'1'&x"DDA1",'1'&x"DDA2",'1'&x"DDA3",'1'&x"DDA4",'1'&x"DDA5",'1'&x"DDA6",'1'&x"DDA7",'1'&x"DDA8",'1'&x"DDA9",'1'&x"DDAA",'1'&x"DDAB",'1'&x"DDAC",'1'&x"DDAD",'1'&x"DDAE",'1'&x"DDAF",
+--'1'&x"DDB0",'1'&x"DDB1",'1'&x"DDB2",'1'&x"DDB3",'1'&x"DDB4",'1'&x"DDB5",'1'&x"DDB6",'1'&x"DDB7",'1'&x"DDB8",'1'&x"DDB9",'1'&x"DDBA",'1'&x"DDBB",'1'&x"DDBC",'1'&x"DDBD",'1'&x"DDBE",'1'&x"DDBF",
+--'1'&x"DDC0",'1'&x"DDC1",'1'&x"DDC2",'1'&x"DDC3",'1'&x"DDC4",'1'&x"DDC5",'1'&x"DDC6",'1'&x"DDC7",'1'&x"DDC8",'1'&x"DDC9",'1'&x"DDCA",'1'&x"DDCB",'1'&x"DDCC",'1'&x"DDCD",'1'&x"DDCE",'1'&x"DDCF",
+--'1'&x"DDD0",'1'&x"DDD1",'1'&x"DDD2",'1'&x"DDD3",'1'&x"DDD4",'1'&x"DDD5",'1'&x"DDD6",'1'&x"DDD7",'1'&x"DDD8",'1'&x"DDD9",'1'&x"DDDA",'1'&x"DDDB",'1'&x"DDDC",'1'&x"DDDD",'1'&x"DDDE",'1'&x"DDDF",
+--'1'&x"DDE0",'1'&x"DDE1",'1'&x"DDE2",'1'&x"DDE3",'1'&x"DDE4",'1'&x"DDE5",'1'&x"DDE6",'1'&x"DDE7",'1'&x"DDE8",'1'&x"DDE9",'1'&x"DDEA",'1'&x"DDEB",'1'&x"DDEC",'1'&x"DDED",'1'&x"DDEE",'1'&x"DDEF",
+--'1'&x"DDF0",'1'&x"DDF1",'1'&x"DDF2",'1'&x"DDF3",'1'&x"DDF4",'1'&x"DDF5",'1'&x"DDF6",'1'&x"DDF7",'1'&x"DDF8",'1'&x"DDF9",'1'&x"DDFA",'1'&x"DDFB",'1'&x"DDFC",'1'&x"DDFD",'1'&x"DDFE",'1'&x"DDFF",
+--'1'&x"DE00",'1'&x"DE01",'1'&x"DE02",'1'&x"DE03",'1'&x"DE04",'1'&x"DE05",'1'&x"DE06",'1'&x"DE07",'1'&x"DE08",'1'&x"DE09",'1'&x"DE0A",'1'&x"DE0B",'1'&x"DE0C",'1'&x"DE0D",'1'&x"DE0E",'1'&x"DE0F",
+--'1'&x"DE10",'1'&x"DE11",'1'&x"DE12",'1'&x"DE13",'1'&x"DE14",'1'&x"DE15",'1'&x"DE16",'1'&x"DE17",'1'&x"DE18",'1'&x"DE19",'1'&x"DE1A",'1'&x"DE1B",'1'&x"DE1C",'1'&x"DE1D",'1'&x"DE1E",'1'&x"DE1F",
+--'1'&x"DE20",'1'&x"DE21",'1'&x"DE22",'1'&x"DE23",'1'&x"DE24",'1'&x"DE25",'1'&x"DE26",'1'&x"DE27",'1'&x"DE28",'1'&x"DE29",'1'&x"DE2A",'1'&x"DE2B",'1'&x"DE2C",'1'&x"DE2D",'1'&x"DE2E",'1'&x"DE2F",
+--'1'&x"DE30",'1'&x"DE31",'1'&x"DE32",'1'&x"DE33",'1'&x"DE34",'1'&x"DE35",'1'&x"DE36",'1'&x"DE37",'1'&x"DE38",'1'&x"DE39",'1'&x"DE3A",'1'&x"DE3B",'1'&x"DE3C",'1'&x"DE3D",'1'&x"DE3E",'1'&x"DE3F",
+--'1'&x"DE40",'1'&x"DE41",'1'&x"DE42",'1'&x"DE43",'1'&x"DE44",'1'&x"DE45",'1'&x"DE46",'1'&x"DE47",'1'&x"DE48",'1'&x"DE49",'1'&x"DE4A",'1'&x"DE4B",'1'&x"DE4C",'1'&x"DE4D",'1'&x"DE4E",'1'&x"DE4F",
+--'1'&x"DE50",'1'&x"DE51",'1'&x"DE52",'1'&x"DE53",'1'&x"DE54",'1'&x"DE55",'1'&x"DE56",'1'&x"DE57",'1'&x"DE58",'1'&x"DE59",'1'&x"DE5A",'1'&x"DE5B",'1'&x"DE5C",'1'&x"DE5D",'1'&x"DE5E",'1'&x"DE5F",
+--'1'&x"DE60",'1'&x"DE61",'1'&x"DE62",'1'&x"DE63",'1'&x"DE64",'1'&x"DE65",'1'&x"DE66",'1'&x"DE67",'1'&x"DE68",'1'&x"DE69",'1'&x"DE6A",'1'&x"DE6B",'1'&x"DE6C",'1'&x"DE6D",'1'&x"DE6E",'1'&x"DE6F",
+--'1'&x"DE70",'1'&x"DE71",'1'&x"DE72",'1'&x"DE73",'1'&x"DE74",'1'&x"DE75",'1'&x"DE76",'1'&x"DE77",'1'&x"DE78",'1'&x"DE79",'1'&x"DE7A",'1'&x"DE7B",'1'&x"DE7C",'1'&x"DE7D",'1'&x"DE7E",'1'&x"DE7F",
+--'1'&x"DE80",'1'&x"DE81",'1'&x"DE82",'1'&x"DE83",'1'&x"DE84",'1'&x"DE85",'1'&x"DE86",'1'&x"DE87",'1'&x"DE88",'1'&x"DE89",'1'&x"DE8A",'1'&x"DE8B",'1'&x"DE8C",'1'&x"DE8D",'1'&x"DE8E",'1'&x"DE8F",
+--'1'&x"DE90",'1'&x"DE91",'1'&x"DE92",'1'&x"DE93",'1'&x"DE94",'1'&x"DE95",'1'&x"DE96",'1'&x"DE97",'1'&x"DE98",'1'&x"DE99",'1'&x"DE9A",'1'&x"DE9B",'1'&x"DE9C",'1'&x"DE9D",'1'&x"DE9E",'1'&x"DE9F",
+--'1'&x"DEA0",'1'&x"DEA1",'1'&x"DEA2",'1'&x"DEA3",'1'&x"DEA4",'1'&x"DEA5",'1'&x"DEA6",'1'&x"DEA7",'1'&x"DEA8",'1'&x"DEA9",'1'&x"DEAA",'1'&x"DEAB",'1'&x"DEAC",'1'&x"DEAD",'1'&x"DEAE",'1'&x"DEAF",
+--'1'&x"DEB0",'1'&x"DEB1",'1'&x"DEB2",'1'&x"DEB3",'1'&x"DEB4",'1'&x"DEB5",'1'&x"DEB6",'1'&x"DEB7",'1'&x"DEB8",'1'&x"DEB9",'1'&x"DEBA",'1'&x"DEBB",'1'&x"DEBC",'1'&x"DEBD",'1'&x"DEBE",'1'&x"DEBF",
+--'1'&x"DEC0",'1'&x"DEC1",'1'&x"DEC2",'1'&x"DEC3",'1'&x"DEC4",'1'&x"DEC5",'1'&x"DEC6",'1'&x"DEC7",'1'&x"DEC8",'1'&x"DEC9",'1'&x"DECA",'1'&x"DECB",'1'&x"DECC",'1'&x"DECD",'1'&x"DECE",'1'&x"DECF",
+--'1'&x"DED0",'1'&x"DED1",'1'&x"DED2",'1'&x"DED3",'1'&x"DED4",'1'&x"DED5",'1'&x"DED6",'1'&x"DED7",'1'&x"DED8",'1'&x"DED9",'1'&x"DEDA",'1'&x"DEDB",'1'&x"DEDC",'1'&x"DEDD",'1'&x"DEDE",'1'&x"DEDF",
+--'1'&x"DEE0",'1'&x"DEE1",'1'&x"DEE2",'1'&x"DEE3",'1'&x"DEE4",'1'&x"DEE5",'1'&x"DEE6",'1'&x"DEE7",'1'&x"DEE8",'1'&x"DEE9",'1'&x"DEEA",'1'&x"DEEB",'1'&x"DEEC",'1'&x"DEED",'1'&x"DEEE",'1'&x"DEEF",
+--'1'&x"DEF0",'1'&x"DEF1",'1'&x"DEF2",'1'&x"DEF3",'1'&x"DEF4",'1'&x"DEF5",'1'&x"DEF6",'1'&x"DEF7",'1'&x"DEF8",'1'&x"DEF9",'1'&x"DEFA",'1'&x"DEFB",'1'&x"DEFC",'1'&x"DEFD",'1'&x"DEFE",'1'&x"DEFF",
+--'1'&x"DF00",'1'&x"DF01",'1'&x"DF02",'1'&x"DF03",'1'&x"DF04",'1'&x"DF05",'1'&x"DF06",'1'&x"DF07",'1'&x"DF08",'1'&x"DF09",'1'&x"DF0A",'1'&x"DF0B",'1'&x"DF0C",'1'&x"DF0D",'1'&x"DF0E",'1'&x"DF0F",
+--'1'&x"DF10",'1'&x"DF11",'1'&x"DF12",'1'&x"DF13",'1'&x"DF14",'1'&x"DF15",'1'&x"DF16",'1'&x"DF17",'1'&x"DF18",'1'&x"DF19",'1'&x"DF1A",'1'&x"DF1B",'1'&x"DF1C",'1'&x"DF1D",'1'&x"DF1E",'1'&x"DF1F",
+--'1'&x"DF20",'1'&x"DF21",'1'&x"DF22",'1'&x"DF23",'1'&x"DF24",'1'&x"DF25",'1'&x"DF26",'1'&x"DF27",'1'&x"DF28",'1'&x"DF29",'1'&x"DF2A",'1'&x"DF2B",'1'&x"DF2C",'1'&x"DF2D",'1'&x"DF2E",'1'&x"DF2F",
+--'1'&x"DF30",'1'&x"DF31",'1'&x"DF32",'1'&x"DF33",'1'&x"DF34",'1'&x"DF35",'1'&x"DF36",'1'&x"DF37",'1'&x"DF38",'1'&x"DF39",'1'&x"DF3A",'1'&x"DF3B",'1'&x"DF3C",'1'&x"DF3D",'1'&x"DF3E",'1'&x"DF3F",
+--'1'&x"DF40",'1'&x"DF41",'1'&x"DF42",'1'&x"DF43",'1'&x"DF44",'1'&x"DF45",'1'&x"DF46",'1'&x"DF47",'1'&x"DF48",'1'&x"DF49",'1'&x"DF4A",'1'&x"DF4B",'1'&x"DF4C",'1'&x"DF4D",'1'&x"DF4E",'1'&x"DF4F",
+--'1'&x"DF50",'1'&x"DF51",'1'&x"DF52",'1'&x"DF53",'1'&x"DF54",'1'&x"DF55",'1'&x"DF56",'1'&x"DF57",'1'&x"DF58",'1'&x"DF59",'1'&x"DF5A",'1'&x"DF5B",'1'&x"DF5C",'1'&x"DF5D",'1'&x"DF5E",'1'&x"DF5F",
+--'1'&x"DF60",'1'&x"DF61",'1'&x"DF62",'1'&x"DF63",'1'&x"DF64",'1'&x"DF65",'1'&x"DF66",'1'&x"DF67",'1'&x"DF68",'1'&x"DF69",'1'&x"DF6A",'1'&x"DF6B",'1'&x"DF6C",'1'&x"DF6D",'1'&x"DF6E",'1'&x"DF6F",
+--'1'&x"DF70",'1'&x"DF71",'1'&x"DF72",'1'&x"DF73",'1'&x"DF74",'1'&x"DF75",'1'&x"DF76",'1'&x"DF77",'1'&x"DF78",'1'&x"DF79",'1'&x"DF7A",'1'&x"DF7B",'1'&x"DF7C",'1'&x"DF7D",'1'&x"DF7E",'1'&x"DF7F",
+--'1'&x"DF80",'1'&x"DF81",'1'&x"DF82",'1'&x"DF83",'1'&x"DF84",'1'&x"DF85",'1'&x"DF86",'1'&x"DF87",'1'&x"DF88",'1'&x"DF89",'1'&x"DF8A",'1'&x"DF8B",'1'&x"DF8C",'1'&x"DF8D",'1'&x"DF8E",'1'&x"DF8F",
+--'1'&x"DF90",'1'&x"DF91",'1'&x"DF92",'1'&x"DF93",'1'&x"DF94",'1'&x"DF95",'1'&x"DF96",'1'&x"DF97",'1'&x"DF98",'1'&x"DF99",'1'&x"DF9A",'1'&x"DF9B",'1'&x"DF9C",'1'&x"DF9D",'1'&x"DF9E",'1'&x"DF9F",
+--'1'&x"DFA0",'1'&x"DFA1",'1'&x"DFA2",'1'&x"DFA3",'1'&x"DFA4",'1'&x"DFA5",'1'&x"DFA6",'1'&x"DFA7",'1'&x"DFA8",'1'&x"DFA9",'1'&x"DFAA",'1'&x"DFAB",'1'&x"DFAC",'1'&x"DFAD",'1'&x"DFAE",'1'&x"DFAF",
+--'1'&x"DFB0",'1'&x"DFB1",'1'&x"DFB2",'1'&x"DFB3",'1'&x"DFB4",'1'&x"DFB5",'1'&x"DFB6",'1'&x"DFB7",'1'&x"DFB8",'1'&x"DFB9",'1'&x"DFBA",'1'&x"DFBB",'1'&x"DFBC",'1'&x"DFBD",'1'&x"DFBE",'1'&x"DFBF",
+--'1'&x"DFC0",'1'&x"DFC1",'1'&x"DFC2",'1'&x"DFC3",'1'&x"DFC4",'1'&x"DFC5",'1'&x"DFC6",'1'&x"DFC7",'1'&x"DFC8",'1'&x"DFC9",'1'&x"DFCA",'1'&x"DFCB",'1'&x"DFCC",'1'&x"DFCD",'1'&x"DFCE",'1'&x"DFCF",
+--'1'&x"DFD0",'1'&x"DFD1",'1'&x"DFD2",'1'&x"DFD3",'1'&x"DFD4",'1'&x"DFD5",'1'&x"DFD6",'1'&x"DFD7",'1'&x"DFD8",'1'&x"DFD9",'1'&x"DFDA",'1'&x"DFDB",'1'&x"DFDC",'1'&x"DFDD",'1'&x"DFDE",'1'&x"DFDF",
+--'1'&x"DFE0",'1'&x"DFE1",'1'&x"DFE2",'1'&x"DFE3",'1'&x"DFE4",'1'&x"DFE5",'1'&x"DFE6",'1'&x"DFE7",'1'&x"DFE8",'1'&x"DFE9",'1'&x"DFEA",'1'&x"DFEB",'1'&x"DFEC",'1'&x"DFED",'1'&x"DFEE",'1'&x"DFEF",
+--'1'&x"DFF0",'1'&x"DFF1",'1'&x"DFF2",'1'&x"DFF3",'1'&x"DFF4",'1'&x"DFF5",'1'&x"DFF6",'1'&x"DFF7",'1'&x"DFF8",'1'&x"DFF9",'1'&x"DFFA",'1'&x"DFFB",'1'&x"DFFC",'1'&x"DFFD",'1'&x"DFFE",'1'&x"DFFF",
+--'1'&x"E000",'1'&x"E001",'1'&x"E002",'1'&x"E003",'1'&x"E004",'1'&x"E005",'1'&x"E006",'1'&x"E007",'1'&x"E008",'1'&x"E009",'1'&x"E00A",'1'&x"E00B",'1'&x"E00C",'1'&x"E00D",'1'&x"E00E",'1'&x"E00F",
+--'1'&x"E010",'1'&x"E011",'1'&x"E012",'1'&x"E013",'1'&x"E014",'1'&x"E015",'1'&x"E016",'1'&x"E017",'1'&x"E018",'1'&x"E019",'1'&x"E01A",'1'&x"E01B",'1'&x"E01C",'1'&x"E01D",'1'&x"E01E",'1'&x"E01F",
+--'1'&x"E020",'1'&x"E021",'1'&x"E022",'1'&x"E023",'1'&x"E024",'1'&x"E025",'1'&x"E026",'1'&x"E027",'1'&x"E028",'1'&x"E029",'1'&x"E02A",'1'&x"E02B",'1'&x"E02C",'1'&x"E02D",'1'&x"E02E",'1'&x"E02F",
+--'1'&x"E030",'1'&x"E031",'1'&x"E032",'1'&x"E033",'1'&x"E034",'1'&x"E035",'1'&x"E036",'1'&x"E037",'1'&x"E038",'1'&x"E039",'1'&x"E03A",'1'&x"E03B",'1'&x"E03C",'1'&x"E03D",'1'&x"E03E",'1'&x"E03F",
+--'1'&x"E040",'1'&x"E041",'1'&x"E042",'1'&x"E043",'1'&x"E044",'1'&x"E045",'1'&x"E046",'1'&x"E047",'1'&x"E048",'1'&x"E049",'1'&x"E04A",'1'&x"E04B",'1'&x"E04C",'1'&x"E04D",'1'&x"E04E",'1'&x"E04F",
+--'1'&x"E050",'1'&x"E051",'1'&x"E052",'1'&x"E053",'1'&x"E054",'1'&x"E055",'1'&x"E056",'1'&x"E057",'1'&x"E058",'1'&x"E059",'1'&x"E05A",'1'&x"E05B",'1'&x"E05C",'1'&x"E05D",'1'&x"E05E",'1'&x"E05F",
+--'1'&x"E060",'1'&x"E061",'1'&x"E062",'1'&x"E063",'1'&x"E064",'1'&x"E065",'1'&x"E066",'1'&x"E067",'1'&x"E068",'1'&x"E069",'1'&x"E06A",'1'&x"E06B",'1'&x"E06C",'1'&x"E06D",'1'&x"E06E",'1'&x"E06F",
+--'1'&x"E070",'1'&x"E071",'1'&x"E072",'1'&x"E073",'1'&x"E074",'1'&x"E075",'1'&x"E076",'1'&x"E077",'1'&x"E078",'1'&x"E079",'1'&x"E07A",'1'&x"E07B",'1'&x"E07C",'1'&x"E07D",'1'&x"E07E",'1'&x"E07F",
+--'1'&x"E080",'1'&x"E081",'1'&x"E082",'1'&x"E083",'1'&x"E084",'1'&x"E085",'1'&x"E086",'1'&x"E087",'1'&x"E088",'1'&x"E089",'1'&x"E08A",'1'&x"E08B",'1'&x"E08C",'1'&x"E08D",'1'&x"E08E",'1'&x"E08F",
+--'1'&x"E090",'1'&x"E091",'1'&x"E092",'1'&x"E093",'1'&x"E094",'1'&x"E095",'1'&x"E096",'1'&x"E097",'1'&x"E098",'1'&x"E099",'1'&x"E09A",'1'&x"E09B",'1'&x"E09C",'1'&x"E09D",'1'&x"E09E",'1'&x"E09F",
+--'1'&x"E0A0",'1'&x"E0A1",'1'&x"E0A2",'1'&x"E0A3",'1'&x"E0A4",'1'&x"E0A5",'1'&x"E0A6",'1'&x"E0A7",'1'&x"E0A8",'1'&x"E0A9",'1'&x"E0AA",'1'&x"E0AB",'1'&x"E0AC",'1'&x"E0AD",'1'&x"E0AE",'1'&x"E0AF",
+--'1'&x"E0B0",'1'&x"E0B1",'1'&x"E0B2",'1'&x"E0B3",'1'&x"E0B4",'1'&x"E0B5",'1'&x"E0B6",'1'&x"E0B7",'1'&x"E0B8",'1'&x"E0B9",'1'&x"E0BA",'1'&x"E0BB",'1'&x"E0BC",'1'&x"E0BD",'1'&x"E0BE",'1'&x"E0BF",
+--'1'&x"E0C0",'1'&x"E0C1",'1'&x"E0C2",'1'&x"E0C3",'1'&x"E0C4",'1'&x"E0C5",'1'&x"E0C6",'1'&x"E0C7",'1'&x"E0C8",'1'&x"E0C9",'1'&x"E0CA",'1'&x"E0CB",'1'&x"E0CC",'1'&x"E0CD",'1'&x"E0CE",'1'&x"E0CF",
+--'1'&x"E0D0",'1'&x"E0D1",'1'&x"E0D2",'1'&x"E0D3",'1'&x"E0D4",'1'&x"E0D5",'1'&x"E0D6",'1'&x"E0D7",'1'&x"E0D8",'1'&x"E0D9",'1'&x"E0DA",'1'&x"E0DB",'1'&x"E0DC",'1'&x"E0DD",'1'&x"E0DE",'1'&x"E0DF",
+--'1'&x"E0E0",'1'&x"E0E1",'1'&x"E0E2",'1'&x"E0E3",'1'&x"E0E4",'1'&x"E0E5",'1'&x"E0E6",'1'&x"E0E7",'1'&x"E0E8",'1'&x"E0E9",'1'&x"E0EA",'1'&x"E0EB",'1'&x"E0EC",'1'&x"E0ED",'1'&x"E0EE",'1'&x"E0EF",
+--'1'&x"E0F0",'1'&x"E0F1",'1'&x"E0F2",'1'&x"E0F3",'1'&x"E0F4",'1'&x"E0F5",'1'&x"E0F6",'1'&x"E0F7",'1'&x"E0F8",'1'&x"E0F9",'1'&x"E0FA",'1'&x"E0FB",'1'&x"E0FC",'1'&x"E0FD",'1'&x"E0FE",'1'&x"E0FF",
+--'1'&x"E100",'1'&x"E101",'1'&x"E102",'1'&x"E103",'1'&x"E104",'1'&x"E105",'1'&x"E106",'1'&x"E107",'1'&x"E108",'1'&x"E109",'1'&x"E10A",'1'&x"E10B",'1'&x"E10C",'1'&x"E10D",'1'&x"E10E",'1'&x"E10F",
+--'1'&x"E110",'1'&x"E111",'1'&x"E112",'1'&x"E113",'1'&x"E114",'1'&x"E115",'1'&x"E116",'1'&x"E117",'1'&x"E118",'1'&x"E119",'1'&x"E11A",'1'&x"E11B",'1'&x"E11C",'1'&x"E11D",'1'&x"E11E",'1'&x"E11F",
+--'1'&x"E120",'1'&x"E121",'1'&x"E122",'1'&x"E123",'1'&x"E124",'1'&x"E125",'1'&x"E126",'1'&x"E127",'1'&x"E128",'1'&x"E129",'1'&x"E12A",'1'&x"E12B",'1'&x"E12C",'1'&x"E12D",'1'&x"E12E",'1'&x"E12F",
+--'1'&x"E130",'1'&x"E131",'1'&x"E132",'1'&x"E133",'1'&x"E134",'1'&x"E135",'1'&x"E136",'1'&x"E137",'1'&x"E138",'1'&x"E139",'1'&x"E13A",'1'&x"E13B",'1'&x"E13C",'1'&x"E13D",'1'&x"E13E",'1'&x"E13F",
+--'1'&x"E140",'1'&x"E141",'1'&x"E142",'1'&x"E143",'1'&x"E144",'1'&x"E145",'1'&x"E146",'1'&x"E147",'1'&x"E148",'1'&x"E149",'1'&x"E14A",'1'&x"E14B",'1'&x"E14C",'1'&x"E14D",'1'&x"E14E",'1'&x"E14F",
+--'1'&x"E150",'1'&x"E151",'1'&x"E152",'1'&x"E153",'1'&x"E154",'1'&x"E155",'1'&x"E156",'1'&x"E157",'1'&x"E158",'1'&x"E159",'1'&x"E15A",'1'&x"E15B",'1'&x"E15C",'1'&x"E15D",'1'&x"E15E",'1'&x"E15F",
+--'1'&x"E160",'1'&x"E161",'1'&x"E162",'1'&x"E163",'1'&x"E164",'1'&x"E165",'1'&x"E166",'1'&x"E167",'1'&x"E168",'1'&x"E169",'1'&x"E16A",'1'&x"E16B",'1'&x"E16C",'1'&x"E16D",'1'&x"E16E",'1'&x"E16F",
+--'1'&x"E170",'1'&x"E171",'1'&x"E172",'1'&x"E173",'1'&x"E174",'1'&x"E175",'1'&x"E176",'1'&x"E177",'1'&x"E178",'1'&x"E179",'1'&x"E17A",'1'&x"E17B",'1'&x"E17C",'1'&x"E17D",'1'&x"E17E",'1'&x"E17F",
+--'1'&x"E180",'1'&x"E181",'1'&x"E182",'1'&x"E183",'1'&x"E184",'1'&x"E185",'1'&x"E186",'1'&x"E187",'1'&x"E188",'1'&x"E189",'1'&x"E18A",'1'&x"E18B",'1'&x"E18C",'1'&x"E18D",'1'&x"E18E",'1'&x"E18F",
+--'1'&x"E190",'1'&x"E191",'1'&x"E192",'1'&x"E193",'1'&x"E194",'1'&x"E195",'1'&x"E196",'1'&x"E197",'1'&x"E198",'1'&x"E199",'1'&x"E19A",'1'&x"E19B",'1'&x"E19C",'1'&x"E19D",'1'&x"E19E",'1'&x"E19F",
+--'1'&x"E1A0",'1'&x"E1A1",'1'&x"E1A2",'1'&x"E1A3",'1'&x"E1A4",'1'&x"E1A5",'1'&x"E1A6",'1'&x"E1A7",'1'&x"E1A8",'1'&x"E1A9",'1'&x"E1AA",'1'&x"E1AB",'1'&x"E1AC",'1'&x"E1AD",'1'&x"E1AE",'1'&x"E1AF",
+--'1'&x"E1B0",'1'&x"E1B1",'1'&x"E1B2",'1'&x"E1B3",'1'&x"E1B4",'1'&x"E1B5",'1'&x"E1B6",'1'&x"E1B7",'1'&x"E1B8",'1'&x"E1B9",'1'&x"E1BA",'1'&x"E1BB",'1'&x"E1BC",'1'&x"E1BD",'1'&x"E1BE",'1'&x"E1BF",
+--'1'&x"E1C0",'1'&x"E1C1",'1'&x"E1C2",'1'&x"E1C3",'1'&x"E1C4",'1'&x"E1C5",'1'&x"E1C6",'1'&x"E1C7",'1'&x"E1C8",'1'&x"E1C9",'1'&x"E1CA",'1'&x"E1CB",'1'&x"E1CC",'1'&x"E1CD",'1'&x"E1CE",'1'&x"E1CF",
+--'1'&x"E1D0",'1'&x"E1D1",'1'&x"E1D2",'1'&x"E1D3",'1'&x"E1D4",'1'&x"E1D5",'1'&x"E1D6",'1'&x"E1D7",'1'&x"E1D8",'1'&x"E1D9",'1'&x"E1DA",'1'&x"E1DB",'1'&x"E1DC",'1'&x"E1DD",'1'&x"E1DE",'1'&x"E1DF",
+--'1'&x"E1E0",'1'&x"E1E1",'1'&x"E1E2",'1'&x"E1E3",'1'&x"E1E4",'1'&x"E1E5",'1'&x"E1E6",'1'&x"E1E7",'1'&x"E1E8",'1'&x"E1E9",'1'&x"E1EA",'1'&x"E1EB",'1'&x"E1EC",'1'&x"E1ED",'1'&x"E1EE",'1'&x"E1EF",
+--'1'&x"E1F0",'1'&x"E1F1",'1'&x"E1F2",'1'&x"E1F3",'1'&x"E1F4",'1'&x"E1F5",'1'&x"E1F6",'1'&x"E1F7",'1'&x"E1F8",'1'&x"E1F9",'1'&x"E1FA",'1'&x"E1FB",'1'&x"E1FC",'1'&x"E1FD",'1'&x"E1FE",'1'&x"E1FF",
+--'1'&x"E200",'1'&x"E201",'1'&x"E202",'1'&x"E203",'1'&x"E204",'1'&x"E205",'1'&x"E206",'1'&x"E207",'1'&x"E208",'1'&x"E209",'1'&x"E20A",'1'&x"E20B",'1'&x"E20C",'1'&x"E20D",'1'&x"E20E",'1'&x"E20F",
+--'1'&x"E210",'1'&x"E211",'1'&x"E212",'1'&x"E213",'1'&x"E214",'1'&x"E215",'1'&x"E216",'1'&x"E217",'1'&x"E218",'1'&x"E219",'1'&x"E21A",'1'&x"E21B",'1'&x"E21C",'1'&x"E21D",'1'&x"E21E",'1'&x"E21F",
+--'1'&x"E220",'1'&x"E221",'1'&x"E222",'1'&x"E223",'1'&x"E224",'1'&x"E225",'1'&x"E226",'1'&x"E227",'1'&x"E228",'1'&x"E229",'1'&x"E22A",'1'&x"E22B",'1'&x"E22C",'1'&x"E22D",'1'&x"E22E",'1'&x"E22F",
+--'1'&x"E230",'1'&x"E231",'1'&x"E232",'1'&x"E233",'1'&x"E234",'1'&x"E235",'1'&x"E236",'1'&x"E237",'1'&x"E238",'1'&x"E239",'1'&x"E23A",'1'&x"E23B",'1'&x"E23C",'1'&x"E23D",'1'&x"E23E",'1'&x"E23F",
+--'1'&x"E240",'1'&x"E241",'1'&x"E242",'1'&x"E243",'1'&x"E244",'1'&x"E245",'1'&x"E246",'1'&x"E247",'1'&x"E248",'1'&x"E249",'1'&x"E24A",'1'&x"E24B",'1'&x"E24C",'1'&x"E24D",'1'&x"E24E",'1'&x"E24F",
+--'1'&x"E250",'1'&x"E251",'1'&x"E252",'1'&x"E253",'1'&x"E254",'1'&x"E255",'1'&x"E256",'1'&x"E257",'1'&x"E258",'1'&x"E259",'1'&x"E25A",'1'&x"E25B",'1'&x"E25C",'1'&x"E25D",'1'&x"E25E",'1'&x"E25F",
+--'1'&x"E260",'1'&x"E261",'1'&x"E262",'1'&x"E263",'1'&x"E264",'1'&x"E265",'1'&x"E266",'1'&x"E267",'1'&x"E268",'1'&x"E269",'1'&x"E26A",'1'&x"E26B",'1'&x"E26C",'1'&x"E26D",'1'&x"E26E",'1'&x"E26F",
+--'1'&x"E270",'1'&x"E271",'1'&x"E272",'1'&x"E273",'1'&x"E274",'1'&x"E275",'1'&x"E276",'1'&x"E277",'1'&x"E278",'1'&x"E279",'1'&x"E27A",'1'&x"E27B",'1'&x"E27C",'1'&x"E27D",'1'&x"E27E",'1'&x"E27F",
+--'1'&x"E280",'1'&x"E281",'1'&x"E282",'1'&x"E283",'1'&x"E284",'1'&x"E285",'1'&x"E286",'1'&x"E287",'1'&x"E288",'1'&x"E289",'1'&x"E28A",'1'&x"E28B",'1'&x"E28C",'1'&x"E28D",'1'&x"E28E",'1'&x"E28F",
+--'1'&x"E290",'1'&x"E291",'1'&x"E292",'1'&x"E293",'1'&x"E294",'1'&x"E295",'1'&x"E296",'1'&x"E297",'1'&x"E298",'1'&x"E299",'1'&x"E29A",'1'&x"E29B",'1'&x"E29C",'1'&x"E29D",'1'&x"E29E",'1'&x"E29F",
+--'1'&x"E2A0",'1'&x"E2A1",'1'&x"E2A2",'1'&x"E2A3",'1'&x"E2A4",'1'&x"E2A5",'1'&x"E2A6",'1'&x"E2A7",'1'&x"E2A8",'1'&x"E2A9",'1'&x"E2AA",'1'&x"E2AB",'1'&x"E2AC",'1'&x"E2AD",'1'&x"E2AE",'1'&x"E2AF",
+--'1'&x"E2B0",'1'&x"E2B1",'1'&x"E2B2",'1'&x"E2B3",'1'&x"E2B4",'1'&x"E2B5",'1'&x"E2B6",'1'&x"E2B7",'1'&x"E2B8",'1'&x"E2B9",'1'&x"E2BA",'1'&x"E2BB",'1'&x"E2BC",'1'&x"E2BD",'1'&x"E2BE",'1'&x"E2BF",
+--'1'&x"E2C0",'1'&x"E2C1",'1'&x"E2C2",'1'&x"E2C3",'1'&x"E2C4",'1'&x"E2C5",'1'&x"E2C6",'1'&x"E2C7",'1'&x"E2C8",'1'&x"E2C9",'1'&x"E2CA",'1'&x"E2CB",'1'&x"E2CC",'1'&x"E2CD",'1'&x"E2CE",'1'&x"E2CF",
+--'1'&x"E2D0",'1'&x"E2D1",'1'&x"E2D2",'1'&x"E2D3",'1'&x"E2D4",'1'&x"E2D5",'1'&x"E2D6",'1'&x"E2D7",'1'&x"E2D8",'1'&x"E2D9",'1'&x"E2DA",'1'&x"E2DB",'1'&x"E2DC",'1'&x"E2DD",'1'&x"E2DE",'1'&x"E2DF",
+--'1'&x"E2E0",'1'&x"E2E1",'1'&x"E2E2",'1'&x"E2E3",'1'&x"E2E4",'1'&x"E2E5",'1'&x"E2E6",'1'&x"E2E7",'1'&x"E2E8",'1'&x"E2E9",'1'&x"E2EA",'1'&x"E2EB",'1'&x"E2EC",'1'&x"E2ED",'1'&x"E2EE",'1'&x"E2EF",
+--'1'&x"E2F0",'1'&x"E2F1",'1'&x"E2F2",'1'&x"E2F3",'1'&x"E2F4",'1'&x"E2F5",'1'&x"E2F6",'1'&x"E2F7",'1'&x"E2F8",'1'&x"E2F9",'1'&x"E2FA",'1'&x"E2FB",'1'&x"E2FC",'1'&x"E2FD",'1'&x"E2FE",'1'&x"E2FF",
+--'1'&x"E300",'1'&x"E301",'1'&x"E302",'1'&x"E303",'1'&x"E304",'1'&x"E305",'1'&x"E306",'1'&x"E307",'1'&x"E308",'1'&x"E309",'1'&x"E30A",'1'&x"E30B",'1'&x"E30C",'1'&x"E30D",'1'&x"E30E",'1'&x"E30F",
+--'1'&x"E310",'1'&x"E311",'1'&x"E312",'1'&x"E313",'1'&x"E314",'1'&x"E315",'1'&x"E316",'1'&x"E317",'1'&x"E318",'1'&x"E319",'1'&x"E31A",'1'&x"E31B",'1'&x"E31C",'1'&x"E31D",'1'&x"E31E",'1'&x"E31F",
+--'1'&x"E320",'1'&x"E321",'1'&x"E322",'1'&x"E323",'1'&x"E324",'1'&x"E325",'1'&x"E326",'1'&x"E327",'1'&x"E328",'1'&x"E329",'1'&x"E32A",'1'&x"E32B",'1'&x"E32C",'1'&x"E32D",'1'&x"E32E",'1'&x"E32F",
+--'1'&x"E330",'1'&x"E331",'1'&x"E332",'1'&x"E333",'1'&x"E334",'1'&x"E335",'1'&x"E336",'1'&x"E337",'1'&x"E338",'1'&x"E339",'1'&x"E33A",'1'&x"E33B",'1'&x"E33C",'1'&x"E33D",'1'&x"E33E",'1'&x"E33F",
+--'1'&x"E340",'1'&x"E341",'1'&x"E342",'1'&x"E343",'1'&x"E344",'1'&x"E345",'1'&x"E346",'1'&x"E347",'1'&x"E348",'1'&x"E349",'1'&x"E34A",'1'&x"E34B",'1'&x"E34C",'1'&x"E34D",'1'&x"E34E",'1'&x"E34F",
+--'1'&x"E350",'1'&x"E351",'1'&x"E352",'1'&x"E353",'1'&x"E354",'1'&x"E355",'1'&x"E356",'1'&x"E357",'1'&x"E358",'1'&x"E359",'1'&x"E35A",'1'&x"E35B",'1'&x"E35C",'1'&x"E35D",'1'&x"E35E",'1'&x"E35F",
+--'1'&x"E360",'1'&x"E361",'1'&x"E362",'1'&x"E363",'1'&x"E364",'1'&x"E365",'1'&x"E366",'1'&x"E367",'1'&x"E368",'1'&x"E369",'1'&x"E36A",'1'&x"E36B",'1'&x"E36C",'1'&x"E36D",'1'&x"E36E",'1'&x"E36F",
+--'1'&x"E370",'1'&x"E371",'1'&x"E372",'1'&x"E373",'1'&x"E374",'1'&x"E375",'1'&x"E376",'1'&x"E377",'1'&x"E378",'1'&x"E379",'1'&x"E37A",'1'&x"E37B",'1'&x"E37C",'1'&x"E37D",'1'&x"E37E",'1'&x"E37F",
+--'1'&x"E380",'1'&x"E381",'1'&x"E382",'1'&x"E383",'1'&x"E384",'1'&x"E385",'1'&x"E386",'1'&x"E387",'1'&x"E388",'1'&x"E389",'1'&x"E38A",'1'&x"E38B",'1'&x"E38C",'1'&x"E38D",'1'&x"E38E",'1'&x"E38F",
+--'1'&x"E390",'1'&x"E391",'1'&x"E392",'1'&x"E393",'1'&x"E394",'1'&x"E395",'1'&x"E396",'1'&x"E397",'1'&x"E398",'1'&x"E399",'1'&x"E39A",'1'&x"E39B",'1'&x"E39C",'1'&x"E39D",'1'&x"E39E",'1'&x"E39F",
+--'1'&x"E3A0",'1'&x"E3A1",'1'&x"E3A2",'1'&x"E3A3",'1'&x"E3A4",'1'&x"E3A5",'1'&x"E3A6",'1'&x"E3A7",'1'&x"E3A8",'1'&x"E3A9",'1'&x"E3AA",'1'&x"E3AB",'1'&x"E3AC",'1'&x"E3AD",'1'&x"E3AE",'1'&x"E3AF",
+--'1'&x"E3B0",'1'&x"E3B1",'1'&x"E3B2",'1'&x"E3B3",'1'&x"E3B4",'1'&x"E3B5",'1'&x"E3B6",'1'&x"E3B7",'1'&x"E3B8",'1'&x"E3B9",'1'&x"E3BA",'1'&x"E3BB",'1'&x"E3BC",'1'&x"E3BD",'1'&x"E3BE",'1'&x"E3BF",
+--'1'&x"E3C0",'1'&x"E3C1",'1'&x"E3C2",'1'&x"E3C3",'1'&x"E3C4",'1'&x"E3C5",'1'&x"E3C6",'1'&x"E3C7",'1'&x"E3C8",'1'&x"E3C9",'1'&x"E3CA",'1'&x"E3CB",'1'&x"E3CC",'1'&x"E3CD",'1'&x"E3CE",'1'&x"E3CF",
+--'1'&x"E3D0",'1'&x"E3D1",'1'&x"E3D2",'1'&x"E3D3",'1'&x"E3D4",'1'&x"E3D5",'1'&x"E3D6",'1'&x"E3D7",'1'&x"E3D8",'1'&x"E3D9",'1'&x"E3DA",'1'&x"E3DB",'1'&x"E3DC",'1'&x"E3DD",'1'&x"E3DE",'1'&x"E3DF",
+--'1'&x"E3E0",'1'&x"E3E1",'1'&x"E3E2",'1'&x"E3E3",'1'&x"E3E4",'1'&x"E3E5",'1'&x"E3E6",'1'&x"E3E7",'1'&x"E3E8",'1'&x"E3E9",'1'&x"E3EA",'1'&x"E3EB",'1'&x"E3EC",'1'&x"E3ED",'1'&x"E3EE",'1'&x"E3EF",
+--'1'&x"E3F0",'1'&x"E3F1",'1'&x"E3F2",'1'&x"E3F3",'1'&x"E3F4",'1'&x"E3F5",'1'&x"E3F6",'1'&x"E3F7",'1'&x"E3F8",'1'&x"E3F9",'1'&x"E3FA",'1'&x"E3FB",'1'&x"E3FC",'1'&x"E3FD",'1'&x"E3FE",'1'&x"E3FF",
+--'1'&x"E400",'1'&x"E401",'1'&x"E402",'1'&x"E403",'1'&x"E404",'1'&x"E405",'1'&x"E406",'1'&x"E407",'1'&x"E408",'1'&x"E409",'1'&x"E40A",'1'&x"E40B",'1'&x"E40C",'1'&x"E40D",'1'&x"E40E",'1'&x"E40F",
+--'1'&x"E410",'1'&x"E411",'1'&x"E412",'1'&x"E413",'1'&x"E414",'1'&x"E415",'1'&x"E416",'1'&x"E417",'1'&x"E418",'1'&x"E419",'1'&x"E41A",'1'&x"E41B",'1'&x"E41C",'1'&x"E41D",'1'&x"E41E",'1'&x"E41F",
+--'1'&x"E420",'1'&x"E421",'1'&x"E422",'1'&x"E423",'1'&x"E424",'1'&x"E425",'1'&x"E426",'1'&x"E427",'1'&x"E428",'1'&x"E429",'1'&x"E42A",'1'&x"E42B",'1'&x"E42C",'1'&x"E42D",'1'&x"E42E",'1'&x"E42F",
+--'1'&x"E430",'1'&x"E431",'1'&x"E432",'1'&x"E433",'1'&x"E434",'1'&x"E435",'1'&x"E436",'1'&x"E437",'1'&x"E438",'1'&x"E439",'1'&x"E43A",'1'&x"E43B",'1'&x"E43C",'1'&x"E43D",'1'&x"E43E",'1'&x"E43F",
+--'1'&x"E440",'1'&x"E441",'1'&x"E442",'1'&x"E443",'1'&x"E444",'1'&x"E445",'1'&x"E446",'1'&x"E447",'1'&x"E448",'1'&x"E449",'1'&x"E44A",'1'&x"E44B",'1'&x"E44C",'1'&x"E44D",'1'&x"E44E",'1'&x"E44F",
+--'1'&x"E450",'1'&x"E451",'1'&x"E452",'1'&x"E453",'1'&x"E454",'1'&x"E455",'1'&x"E456",'1'&x"E457",'1'&x"E458",'1'&x"E459",'1'&x"E45A",'1'&x"E45B",'1'&x"E45C",'1'&x"E45D",'1'&x"E45E",'1'&x"E45F",
+--'1'&x"E460",'1'&x"E461",'1'&x"E462",'1'&x"E463",'1'&x"E464",'1'&x"E465",'1'&x"E466",'1'&x"E467",'1'&x"E468",'1'&x"E469",'1'&x"E46A",'1'&x"E46B",'1'&x"E46C",'1'&x"E46D",'1'&x"E46E",'1'&x"E46F",
+--'1'&x"E470",'1'&x"E471",'1'&x"E472",'1'&x"E473",'1'&x"E474",'1'&x"E475",'1'&x"E476",'1'&x"E477",'1'&x"E478",'1'&x"E479",'1'&x"E47A",'1'&x"E47B",'1'&x"E47C",'1'&x"E47D",'1'&x"E47E",'1'&x"E47F",
+--'1'&x"E480",'1'&x"E481",'1'&x"E482",'1'&x"E483",'1'&x"E484",'1'&x"E485",'1'&x"E486",'1'&x"E487",'1'&x"E488",'1'&x"E489",'1'&x"E48A",'1'&x"E48B",'1'&x"E48C",'1'&x"E48D",'1'&x"E48E",'1'&x"E48F",
+--'1'&x"E490",'1'&x"E491",'1'&x"E492",'1'&x"E493",'1'&x"E494",'1'&x"E495",'1'&x"E496",'1'&x"E497",'1'&x"E498",'1'&x"E499",'1'&x"E49A",'1'&x"E49B",'1'&x"E49C",'1'&x"E49D",'1'&x"E49E",'1'&x"E49F",
+--'1'&x"E4A0",'1'&x"E4A1",'1'&x"E4A2",'1'&x"E4A3",'1'&x"E4A4",'1'&x"E4A5",'1'&x"E4A6",'1'&x"E4A7",'1'&x"E4A8",'1'&x"E4A9",'1'&x"E4AA",'1'&x"E4AB",'1'&x"E4AC",'1'&x"E4AD",'1'&x"E4AE",'1'&x"E4AF",
+--'1'&x"E4B0",'1'&x"E4B1",'1'&x"E4B2",'1'&x"E4B3",'1'&x"E4B4",'1'&x"E4B5",'1'&x"E4B6",'1'&x"E4B7",'1'&x"E4B8",'1'&x"E4B9",'1'&x"E4BA",'1'&x"E4BB",'1'&x"E4BC",'1'&x"E4BD",'1'&x"E4BE",'1'&x"E4BF",
+--'1'&x"E4C0",'1'&x"E4C1",'1'&x"E4C2",'1'&x"E4C3",'1'&x"E4C4",'1'&x"E4C5",'1'&x"E4C6",'1'&x"E4C7",'1'&x"E4C8",'1'&x"E4C9",'1'&x"E4CA",'1'&x"E4CB",'1'&x"E4CC",'1'&x"E4CD",'1'&x"E4CE",'1'&x"E4CF",
+--'1'&x"E4D0",'1'&x"E4D1",'1'&x"E4D2",'1'&x"E4D3",'1'&x"E4D4",'1'&x"E4D5",'1'&x"E4D6",'1'&x"E4D7",'1'&x"E4D8",'1'&x"E4D9",'1'&x"E4DA",'1'&x"E4DB",'1'&x"E4DC",'1'&x"E4DD",'1'&x"E4DE",'1'&x"E4DF",
+--'1'&x"E4E0",'1'&x"E4E1",'1'&x"E4E2",'1'&x"E4E3",'1'&x"E4E4",'1'&x"E4E5",'1'&x"E4E6",'1'&x"E4E7",'1'&x"E4E8",'1'&x"E4E9",'1'&x"E4EA",'1'&x"E4EB",'1'&x"E4EC",'1'&x"E4ED",'1'&x"E4EE",'1'&x"E4EF",
+--'1'&x"E4F0",'1'&x"E4F1",'1'&x"E4F2",'1'&x"E4F3",'1'&x"E4F4",'1'&x"E4F5",'1'&x"E4F6",'1'&x"E4F7",'1'&x"E4F8",'1'&x"E4F9",'1'&x"E4FA",'1'&x"E4FB",'1'&x"E4FC",'1'&x"E4FD",'1'&x"E4FE",'1'&x"E4FF",
+--'1'&x"E500",'1'&x"E501",'1'&x"E502",'1'&x"E503",'1'&x"E504",'1'&x"E505",'1'&x"E506",'1'&x"E507",'1'&x"E508",'1'&x"E509",'1'&x"E50A",'1'&x"E50B",'1'&x"E50C",'1'&x"E50D",'1'&x"E50E",'1'&x"E50F",
+--'1'&x"E510",'1'&x"E511",'1'&x"E512",'1'&x"E513",'1'&x"E514",'1'&x"E515",'1'&x"E516",'1'&x"E517",'1'&x"E518",'1'&x"E519",'1'&x"E51A",'1'&x"E51B",'1'&x"E51C",'1'&x"E51D",'1'&x"E51E",'1'&x"E51F",
+--'1'&x"E520",'1'&x"E521",'1'&x"E522",'1'&x"E523",'1'&x"E524",'1'&x"E525",'1'&x"E526",'1'&x"E527",'1'&x"E528",'1'&x"E529",'1'&x"E52A",'1'&x"E52B",'1'&x"E52C",'1'&x"E52D",'1'&x"E52E",'1'&x"E52F",
+--'1'&x"E530",'1'&x"E531",'1'&x"E532",'1'&x"E533",'1'&x"E534",'1'&x"E535",'1'&x"E536",'1'&x"E537",'1'&x"E538",'1'&x"E539",'1'&x"E53A",'1'&x"E53B",'1'&x"E53C",'1'&x"E53D",'1'&x"E53E",'1'&x"E53F",
+--'1'&x"E540",'1'&x"E541",'1'&x"E542",'1'&x"E543",'1'&x"E544",'1'&x"E545",'1'&x"E546",'1'&x"E547",'1'&x"E548",'1'&x"E549",'1'&x"E54A",'1'&x"E54B",'1'&x"E54C",'1'&x"E54D",'1'&x"E54E",'1'&x"E54F",
+--'1'&x"E550",'1'&x"E551",'1'&x"E552",'1'&x"E553",'1'&x"E554",'1'&x"E555",'1'&x"E556",'1'&x"E557",'1'&x"E558",'1'&x"E559",'1'&x"E55A",'1'&x"E55B",'1'&x"E55C",'1'&x"E55D",'1'&x"E55E",'1'&x"E55F",
+--'1'&x"E560",'1'&x"E561",'1'&x"E562",'1'&x"E563",'1'&x"E564",'1'&x"E565",'1'&x"E566",'1'&x"E567",'1'&x"E568",'1'&x"E569",'1'&x"E56A",'1'&x"E56B",'1'&x"E56C",'1'&x"E56D",'1'&x"E56E",'1'&x"E56F",
+--'1'&x"E570",'1'&x"E571",'1'&x"E572",'1'&x"E573",'1'&x"E574",'1'&x"E575",'1'&x"E576",'1'&x"E577",'1'&x"E578",'1'&x"E579",'1'&x"E57A",'1'&x"E57B",'1'&x"E57C",'1'&x"E57D",'1'&x"E57E",'1'&x"E57F",
+--'1'&x"E580",'1'&x"E581",'1'&x"E582",'1'&x"E583",'1'&x"E584",'1'&x"E585",'1'&x"E586",'1'&x"E587",'1'&x"E588",'1'&x"E589",'1'&x"E58A",'1'&x"E58B",'1'&x"E58C",'1'&x"E58D",'1'&x"E58E",'1'&x"E58F",
+--'1'&x"E590",'1'&x"E591",'1'&x"E592",'1'&x"E593",'1'&x"E594",'1'&x"E595",'1'&x"E596",'1'&x"E597",'1'&x"E598",'1'&x"E599",'1'&x"E59A",'1'&x"E59B",'1'&x"E59C",'1'&x"E59D",'1'&x"E59E",'1'&x"E59F",
+--'1'&x"E5A0",'1'&x"E5A1",'1'&x"E5A2",'1'&x"E5A3",'1'&x"E5A4",'1'&x"E5A5",'1'&x"E5A6",'1'&x"E5A7",'1'&x"E5A8",'1'&x"E5A9",'1'&x"E5AA",'1'&x"E5AB",'1'&x"E5AC",'1'&x"E5AD",'1'&x"E5AE",'1'&x"E5AF",
+--'1'&x"E5B0",'1'&x"E5B1",'1'&x"E5B2",'1'&x"E5B3",'1'&x"E5B4",'1'&x"E5B5",'1'&x"E5B6",'1'&x"E5B7",'1'&x"E5B8",'1'&x"E5B9",'1'&x"E5BA",'1'&x"E5BB",'1'&x"E5BC",'1'&x"E5BD",'1'&x"E5BE",'1'&x"E5BF",
+--'1'&x"E5C0",'1'&x"E5C1",'1'&x"E5C2",'1'&x"E5C3",'1'&x"E5C4",'1'&x"E5C5",'1'&x"E5C6",'1'&x"E5C7",'1'&x"E5C8",'1'&x"E5C9",'1'&x"E5CA",'1'&x"E5CB",'1'&x"E5CC",'1'&x"E5CD",'1'&x"E5CE",'1'&x"E5CF",
+--'1'&x"E5D0",'1'&x"E5D1",'1'&x"E5D2",'1'&x"E5D3",'1'&x"E5D4",'1'&x"E5D5",'1'&x"E5D6",'1'&x"E5D7",'1'&x"E5D8",'1'&x"E5D9",'1'&x"E5DA",'1'&x"E5DB",'1'&x"E5DC",'1'&x"E5DD",'1'&x"E5DE",'1'&x"E5DF",
+--'1'&x"E5E0",'1'&x"E5E1",'1'&x"E5E2",'1'&x"E5E3",'1'&x"E5E4",'1'&x"E5E5",'1'&x"E5E6",'1'&x"E5E7",'1'&x"E5E8",'1'&x"E5E9",'1'&x"E5EA",'1'&x"E5EB",'1'&x"E5EC",'1'&x"E5ED",'1'&x"E5EE",'1'&x"E5EF",
+--'1'&x"E5F0",'1'&x"E5F1",'1'&x"E5F2",'1'&x"E5F3",'1'&x"E5F4",'1'&x"E5F5",'1'&x"E5F6",'1'&x"E5F7",'1'&x"E5F8",'1'&x"E5F9",'1'&x"E5FA",'1'&x"E5FB",'1'&x"E5FC",'1'&x"E5FD",'1'&x"E5FE",'1'&x"E5FF",
+--'1'&x"E600",'1'&x"E601",'1'&x"E602",'1'&x"E603",'1'&x"E604",'1'&x"E605",'1'&x"E606",'1'&x"E607",'1'&x"E608",'1'&x"E609",'1'&x"E60A",'1'&x"E60B",'1'&x"E60C",'1'&x"E60D",'1'&x"E60E",'1'&x"E60F",
+--'1'&x"E610",'1'&x"E611",'1'&x"E612",'1'&x"E613",'1'&x"E614",'1'&x"E615",'1'&x"E616",'1'&x"E617",'1'&x"E618",'1'&x"E619",'1'&x"E61A",'1'&x"E61B",'1'&x"E61C",'1'&x"E61D",'1'&x"E61E",'1'&x"E61F",
+--'1'&x"E620",'1'&x"E621",'1'&x"E622",'1'&x"E623",'1'&x"E624",'1'&x"E625",'1'&x"E626",'1'&x"E627",'1'&x"E628",'1'&x"E629",'1'&x"E62A",'1'&x"E62B",'1'&x"E62C",'1'&x"E62D",'1'&x"E62E",'1'&x"E62F",
+--'1'&x"E630",'1'&x"E631",'1'&x"E632",'1'&x"E633",'1'&x"E634",'1'&x"E635",'1'&x"E636",'1'&x"E637",'1'&x"E638",'1'&x"E639",'1'&x"E63A",'1'&x"E63B",'1'&x"E63C",'1'&x"E63D",'1'&x"E63E",'1'&x"E63F",
+--'1'&x"E640",'1'&x"E641",'1'&x"E642",'1'&x"E643",'1'&x"E644",'1'&x"E645",'1'&x"E646",'1'&x"E647",'1'&x"E648",'1'&x"E649",'1'&x"E64A",'1'&x"E64B",'1'&x"E64C",'1'&x"E64D",'1'&x"E64E",'1'&x"E64F",
+--'1'&x"E650",'1'&x"E651",'1'&x"E652",'1'&x"E653",'1'&x"E654",'1'&x"E655",'1'&x"E656",'1'&x"E657",'1'&x"E658",'1'&x"E659",'1'&x"E65A",'1'&x"E65B",'1'&x"E65C",'1'&x"E65D",'1'&x"E65E",'1'&x"E65F",
+--'1'&x"E660",'1'&x"E661",'1'&x"E662",'1'&x"E663",'1'&x"E664",'1'&x"E665",'1'&x"E666",'1'&x"E667",'1'&x"E668",'1'&x"E669",'1'&x"E66A",'1'&x"E66B",'1'&x"E66C",'1'&x"E66D",'1'&x"E66E",'1'&x"E66F",
+--'1'&x"E670",'1'&x"E671",'1'&x"E672",'1'&x"E673",'1'&x"E674",'1'&x"E675",'1'&x"E676",'1'&x"E677",'1'&x"E678",'1'&x"E679",'1'&x"E67A",'1'&x"E67B",'1'&x"E67C",'1'&x"E67D",'1'&x"E67E",'1'&x"E67F",
+--'1'&x"E680",'1'&x"E681",'1'&x"E682",'1'&x"E683",'1'&x"E684",'1'&x"E685",'1'&x"E686",'1'&x"E687",'1'&x"E688",'1'&x"E689",'1'&x"E68A",'1'&x"E68B",'1'&x"E68C",'1'&x"E68D",'1'&x"E68E",'1'&x"E68F",
+--'1'&x"E690",'1'&x"E691",'1'&x"E692",'1'&x"E693",'1'&x"E694",'1'&x"E695",'1'&x"E696",'1'&x"E697",'1'&x"E698",'1'&x"E699",'1'&x"E69A",'1'&x"E69B",'1'&x"E69C",'1'&x"E69D",'1'&x"E69E",'1'&x"E69F",
+--'1'&x"E6A0",'1'&x"E6A1",'1'&x"E6A2",'1'&x"E6A3",'1'&x"E6A4",'1'&x"E6A5",'1'&x"E6A6",'1'&x"E6A7",'1'&x"E6A8",'1'&x"E6A9",'1'&x"E6AA",'1'&x"E6AB",'1'&x"E6AC",'1'&x"E6AD",'1'&x"E6AE",'1'&x"E6AF",
+--'1'&x"E6B0",'1'&x"E6B1",'1'&x"E6B2",'1'&x"E6B3",'1'&x"E6B4",'1'&x"E6B5",'1'&x"E6B6",'1'&x"E6B7",'1'&x"E6B8",'1'&x"E6B9",'1'&x"E6BA",'1'&x"E6BB",'1'&x"E6BC",'1'&x"E6BD",'1'&x"E6BE",'1'&x"E6BF",
+--'1'&x"E6C0",'1'&x"E6C1",'1'&x"E6C2",'1'&x"E6C3",'1'&x"E6C4",'1'&x"E6C5",'1'&x"E6C6",'1'&x"E6C7",'1'&x"E6C8",'1'&x"E6C9",'1'&x"E6CA",'1'&x"E6CB",'1'&x"E6CC",'1'&x"E6CD",'1'&x"E6CE",'1'&x"E6CF",
+--'1'&x"E6D0",'1'&x"E6D1",'1'&x"E6D2",'1'&x"E6D3",'1'&x"E6D4",'1'&x"E6D5",'1'&x"E6D6",'1'&x"E6D7",'1'&x"E6D8",'1'&x"E6D9",'1'&x"E6DA",'1'&x"E6DB",'1'&x"E6DC",'1'&x"E6DD",'1'&x"E6DE",'1'&x"E6DF",
+--'1'&x"E6E0",'1'&x"E6E1",'1'&x"E6E2",'1'&x"E6E3",'1'&x"E6E4",'1'&x"E6E5",'1'&x"E6E6",'1'&x"E6E7",'1'&x"E6E8",'1'&x"E6E9",'1'&x"E6EA",'1'&x"E6EB",'1'&x"E6EC",'1'&x"E6ED",'1'&x"E6EE",'1'&x"E6EF",
+--'1'&x"E6F0",'1'&x"E6F1",'1'&x"E6F2",'1'&x"E6F3",'1'&x"E6F4",'1'&x"E6F5",'1'&x"E6F6",'1'&x"E6F7",'1'&x"E6F8",'1'&x"E6F9",'1'&x"E6FA",'1'&x"E6FB",'1'&x"E6FC",'1'&x"E6FD",'1'&x"E6FE",'1'&x"E6FF",
+--'1'&x"E700",'1'&x"E701",'1'&x"E702",'1'&x"E703",'1'&x"E704",'1'&x"E705",'1'&x"E706",'1'&x"E707",'1'&x"E708",'1'&x"E709",'1'&x"E70A",'1'&x"E70B",'1'&x"E70C",'1'&x"E70D",'1'&x"E70E",'1'&x"E70F",
+--'1'&x"E710",'1'&x"E711",'1'&x"E712",'1'&x"E713",'1'&x"E714",'1'&x"E715",'1'&x"E716",'1'&x"E717",'1'&x"E718",'1'&x"E719",'1'&x"E71A",'1'&x"E71B",'1'&x"E71C",'1'&x"E71D",'1'&x"E71E",'1'&x"E71F",
+--'1'&x"E720",'1'&x"E721",'1'&x"E722",'1'&x"E723",'1'&x"E724",'1'&x"E725",'1'&x"E726",'1'&x"E727",'1'&x"E728",'1'&x"E729",'1'&x"E72A",'1'&x"E72B",'1'&x"E72C",'1'&x"E72D",'1'&x"E72E",'1'&x"E72F",
+--'1'&x"E730",'1'&x"E731",'1'&x"E732",'1'&x"E733",'1'&x"E734",'1'&x"E735",'1'&x"E736",'1'&x"E737",'1'&x"E738",'1'&x"E739",'1'&x"E73A",'1'&x"E73B",'1'&x"E73C",'1'&x"E73D",'1'&x"E73E",'1'&x"E73F",
+--'1'&x"E740",'1'&x"E741",'1'&x"E742",'1'&x"E743",'1'&x"E744",'1'&x"E745",'1'&x"E746",'1'&x"E747",'1'&x"E748",'1'&x"E749",'1'&x"E74A",'1'&x"E74B",'1'&x"E74C",'1'&x"E74D",'1'&x"E74E",'1'&x"E74F",
+--'1'&x"E750",'1'&x"E751",'1'&x"E752",'1'&x"E753",'1'&x"E754",'1'&x"E755",'1'&x"E756",'1'&x"E757",'1'&x"E758",'1'&x"E759",'1'&x"E75A",'1'&x"E75B",'1'&x"E75C",'1'&x"E75D",'1'&x"E75E",'1'&x"E75F",
+--'1'&x"E760",'1'&x"E761",'1'&x"E762",'1'&x"E763",'1'&x"E764",'1'&x"E765",'1'&x"E766",'1'&x"E767",'1'&x"E768",'1'&x"E769",'1'&x"E76A",'1'&x"E76B",'1'&x"E76C",'1'&x"E76D",'1'&x"E76E",'1'&x"E76F",
+--'1'&x"E770",'1'&x"E771",'1'&x"E772",'1'&x"E773",'1'&x"E774",'1'&x"E775",'1'&x"E776",'1'&x"E777",'1'&x"E778",'1'&x"E779",'1'&x"E77A",'1'&x"E77B",'1'&x"E77C",'1'&x"E77D",'1'&x"E77E",'1'&x"E77F",
+--'1'&x"E780",'1'&x"E781",'1'&x"E782",'1'&x"E783",'1'&x"E784",'1'&x"E785",'1'&x"E786",'1'&x"E787",'1'&x"E788",'1'&x"E789",'1'&x"E78A",'1'&x"E78B",'1'&x"E78C",'1'&x"E78D",'1'&x"E78E",'1'&x"E78F",
+--'1'&x"E790",'1'&x"E791",'1'&x"E792",'1'&x"E793",'1'&x"E794",'1'&x"E795",'1'&x"E796",'1'&x"E797",'1'&x"E798",'1'&x"E799",'1'&x"E79A",'1'&x"E79B",'1'&x"E79C",'1'&x"E79D",'1'&x"E79E",'1'&x"E79F",
+--'1'&x"E7A0",'1'&x"E7A1",'1'&x"E7A2",'1'&x"E7A3",'1'&x"E7A4",'1'&x"E7A5",'1'&x"E7A6",'1'&x"E7A7",'1'&x"E7A8",'1'&x"E7A9",'1'&x"E7AA",'1'&x"E7AB",'1'&x"E7AC",'1'&x"E7AD",'1'&x"E7AE",'1'&x"E7AF",
+--'1'&x"E7B0",'1'&x"E7B1",'1'&x"E7B2",'1'&x"E7B3",'1'&x"E7B4",'1'&x"E7B5",'1'&x"E7B6",'1'&x"E7B7",'1'&x"E7B8",'1'&x"E7B9",'1'&x"E7BA",'1'&x"E7BB",'1'&x"E7BC",'1'&x"E7BD",'1'&x"E7BE",'1'&x"E7BF",
+--'1'&x"E7C0",'1'&x"E7C1",'1'&x"E7C2",'1'&x"E7C3",'1'&x"E7C4",'1'&x"E7C5",'1'&x"E7C6",'1'&x"E7C7",'1'&x"E7C8",'1'&x"E7C9",'1'&x"E7CA",'1'&x"E7CB",'1'&x"E7CC",'1'&x"E7CD",'1'&x"E7CE",'1'&x"E7CF",
+--'1'&x"E7D0",'1'&x"E7D1",'1'&x"E7D2",'1'&x"E7D3",'1'&x"E7D4",'1'&x"E7D5",'1'&x"E7D6",'1'&x"E7D7",'1'&x"E7D8",'1'&x"E7D9",'1'&x"E7DA",'1'&x"E7DB",'1'&x"E7DC",'1'&x"E7DD",'1'&x"E7DE",'1'&x"E7DF",
+--'1'&x"E7E0",'1'&x"E7E1",'1'&x"E7E2",'1'&x"E7E3",'1'&x"E7E4",'1'&x"E7E5",'1'&x"E7E6",'1'&x"E7E7",'1'&x"E7E8",'1'&x"E7E9",'1'&x"E7EA",'1'&x"E7EB",'1'&x"E7EC",'1'&x"E7ED",'1'&x"E7EE",'1'&x"E7EF",
+--'1'&x"E7F0",'1'&x"E7F1",'1'&x"E7F2",'1'&x"E7F3",'1'&x"E7F4",'1'&x"E7F5",'1'&x"E7F6",'1'&x"E7F7",'1'&x"E7F8",'1'&x"E7F9",'1'&x"E7FA",'1'&x"E7FB",'1'&x"E7FC",'1'&x"E7FD",'1'&x"E7FE",'1'&x"E7FF",
+--'1'&x"E800",'1'&x"E801",'1'&x"E802",'1'&x"E803",'1'&x"E804",'1'&x"E805",'1'&x"E806",'1'&x"E807",'1'&x"E808",'1'&x"E809",'1'&x"E80A",'1'&x"E80B",'1'&x"E80C",'1'&x"E80D",'1'&x"E80E",'1'&x"E80F",
+--'1'&x"E810",'1'&x"E811",'1'&x"E812",'1'&x"E813",'1'&x"E814",'1'&x"E815",'1'&x"E816",'1'&x"E817",'1'&x"E818",'1'&x"E819",'1'&x"E81A",'1'&x"E81B",'1'&x"E81C",'1'&x"E81D",'1'&x"E81E",'1'&x"E81F",
+--'1'&x"E820",'1'&x"E821",'1'&x"E822",'1'&x"E823",'1'&x"E824",'1'&x"E825",'1'&x"E826",'1'&x"E827",'1'&x"E828",'1'&x"E829",'1'&x"E82A",'1'&x"E82B",'1'&x"E82C",'1'&x"E82D",'1'&x"E82E",'1'&x"E82F",
+--'1'&x"E830",'1'&x"E831",'1'&x"E832",'1'&x"E833",'1'&x"E834",'1'&x"E835",'1'&x"E836",'1'&x"E837",'1'&x"E838",'1'&x"E839",'1'&x"E83A",'1'&x"E83B",'1'&x"E83C",'1'&x"E83D",'1'&x"E83E",'1'&x"E83F",
+--'1'&x"E840",'1'&x"E841",'1'&x"E842",'1'&x"E843",'1'&x"E844",'1'&x"E845",'1'&x"E846",'1'&x"E847",'1'&x"E848",'1'&x"E849",'1'&x"E84A",'1'&x"E84B",'1'&x"E84C",'1'&x"E84D",'1'&x"E84E",'1'&x"E84F",
+--'1'&x"E850",'1'&x"E851",'1'&x"E852",'1'&x"E853",'1'&x"E854",'1'&x"E855",'1'&x"E856",'1'&x"E857",'1'&x"E858",'1'&x"E859",'1'&x"E85A",'1'&x"E85B",'1'&x"E85C",'1'&x"E85D",'1'&x"E85E",'1'&x"E85F",
+--'1'&x"E860",'1'&x"E861",'1'&x"E862",'1'&x"E863",'1'&x"E864",'1'&x"E865",'1'&x"E866",'1'&x"E867",'1'&x"E868",'1'&x"E869",'1'&x"E86A",'1'&x"E86B",'1'&x"E86C",'1'&x"E86D",'1'&x"E86E",'1'&x"E86F",
+--'1'&x"E870",'1'&x"E871",'1'&x"E872",'1'&x"E873",'1'&x"E874",'1'&x"E875",'1'&x"E876",'1'&x"E877",'1'&x"E878",'1'&x"E879",'1'&x"E87A",'1'&x"E87B",'1'&x"E87C",'1'&x"E87D",'1'&x"E87E",'1'&x"E87F",
+--'1'&x"E880",'1'&x"E881",'1'&x"E882",'1'&x"E883",'1'&x"E884",'1'&x"E885",'1'&x"E886",'1'&x"E887",'1'&x"E888",'1'&x"E889",'1'&x"E88A",'1'&x"E88B",'1'&x"E88C",'1'&x"E88D",'1'&x"E88E",'1'&x"E88F",
+--'1'&x"E890",'1'&x"E891",'1'&x"E892",'1'&x"E893",'1'&x"E894",'1'&x"E895",'1'&x"E896",'1'&x"E897",'1'&x"E898",'1'&x"E899",'1'&x"E89A",'1'&x"E89B",'1'&x"E89C",'1'&x"E89D",'1'&x"E89E",'1'&x"E89F",
+--'1'&x"E8A0",'1'&x"E8A1",'1'&x"E8A2",'1'&x"E8A3",'1'&x"E8A4",'1'&x"E8A5",'1'&x"E8A6",'1'&x"E8A7",'1'&x"E8A8",'1'&x"E8A9",'1'&x"E8AA",'1'&x"E8AB",'1'&x"E8AC",'1'&x"E8AD",'1'&x"E8AE",'1'&x"E8AF",
+--'1'&x"E8B0",'1'&x"E8B1",'1'&x"E8B2",'1'&x"E8B3",'1'&x"E8B4",'1'&x"E8B5",'1'&x"E8B6",'1'&x"E8B7",'1'&x"E8B8",'1'&x"E8B9",'1'&x"E8BA",'1'&x"E8BB",'1'&x"E8BC",'1'&x"E8BD",'1'&x"E8BE",'1'&x"E8BF",
+--'1'&x"E8C0",'1'&x"E8C1",'1'&x"E8C2",'1'&x"E8C3",'1'&x"E8C4",'1'&x"E8C5",'1'&x"E8C6",'1'&x"E8C7",'1'&x"E8C8",'1'&x"E8C9",'1'&x"E8CA",'1'&x"E8CB",'1'&x"E8CC",'1'&x"E8CD",'1'&x"E8CE",'1'&x"E8CF",
+--'1'&x"E8D0",'1'&x"E8D1",'1'&x"E8D2",'1'&x"E8D3",'1'&x"E8D4",'1'&x"E8D5",'1'&x"E8D6",'1'&x"E8D7",'1'&x"E8D8",'1'&x"E8D9",'1'&x"E8DA",'1'&x"E8DB",'1'&x"E8DC",'1'&x"E8DD",'1'&x"E8DE",'1'&x"E8DF",
+--'1'&x"E8E0",'1'&x"E8E1",'1'&x"E8E2",'1'&x"E8E3",'1'&x"E8E4",'1'&x"E8E5",'1'&x"E8E6",'1'&x"E8E7",'1'&x"E8E8",'1'&x"E8E9",'1'&x"E8EA",'1'&x"E8EB",'1'&x"E8EC",'1'&x"E8ED",'1'&x"E8EE",'1'&x"E8EF",
+--'1'&x"E8F0",'1'&x"E8F1",'1'&x"E8F2",'1'&x"E8F3",'1'&x"E8F4",'1'&x"E8F5",'1'&x"E8F6",'1'&x"E8F7",'1'&x"E8F8",'1'&x"E8F9",'1'&x"E8FA",'1'&x"E8FB",'1'&x"E8FC",'1'&x"E8FD",'1'&x"E8FE",'1'&x"E8FF",
+--'1'&x"E900",'1'&x"E901",'1'&x"E902",'1'&x"E903",'1'&x"E904",'1'&x"E905",'1'&x"E906",'1'&x"E907",'1'&x"E908",'1'&x"E909",'1'&x"E90A",'1'&x"E90B",'1'&x"E90C",'1'&x"E90D",'1'&x"E90E",'1'&x"E90F",
+--'1'&x"E910",'1'&x"E911",'1'&x"E912",'1'&x"E913",'1'&x"E914",'1'&x"E915",'1'&x"E916",'1'&x"E917",'1'&x"E918",'1'&x"E919",'1'&x"E91A",'1'&x"E91B",'1'&x"E91C",'1'&x"E91D",'1'&x"E91E",'1'&x"E91F",
+--'1'&x"E920",'1'&x"E921",'1'&x"E922",'1'&x"E923",'1'&x"E924",'1'&x"E925",'1'&x"E926",'1'&x"E927",'1'&x"E928",'1'&x"E929",'1'&x"E92A",'1'&x"E92B",'1'&x"E92C",'1'&x"E92D",'1'&x"E92E",'1'&x"E92F",
+--'1'&x"E930",'1'&x"E931",'1'&x"E932",'1'&x"E933",'1'&x"E934",'1'&x"E935",'1'&x"E936",'1'&x"E937",'1'&x"E938",'1'&x"E939",'1'&x"E93A",'1'&x"E93B",'1'&x"E93C",'1'&x"E93D",'1'&x"E93E",'1'&x"E93F",
+--'1'&x"E940",'1'&x"E941",'1'&x"E942",'1'&x"E943",'1'&x"E944",'1'&x"E945",'1'&x"E946",'1'&x"E947",'1'&x"E948",'1'&x"E949",'1'&x"E94A",'1'&x"E94B",'1'&x"E94C",'1'&x"E94D",'1'&x"E94E",'1'&x"E94F",
+--'1'&x"E950",'1'&x"E951",'1'&x"E952",'1'&x"E953",'1'&x"E954",'1'&x"E955",'1'&x"E956",'1'&x"E957",'1'&x"E958",'1'&x"E959",'1'&x"E95A",'1'&x"E95B",'1'&x"E95C",'1'&x"E95D",'1'&x"E95E",'1'&x"E95F",
+--'1'&x"E960",'1'&x"E961",'1'&x"E962",'1'&x"E963",'1'&x"E964",'1'&x"E965",'1'&x"E966",'1'&x"E967",'1'&x"E968",'1'&x"E969",'1'&x"E96A",'1'&x"E96B",'1'&x"E96C",'1'&x"E96D",'1'&x"E96E",'1'&x"E96F",
+--'1'&x"E970",'1'&x"E971",'1'&x"E972",'1'&x"E973",'1'&x"E974",'1'&x"E975",'1'&x"E976",'1'&x"E977",'1'&x"E978",'1'&x"E979",'1'&x"E97A",'1'&x"E97B",'1'&x"E97C",'1'&x"E97D",'1'&x"E97E",'1'&x"E97F",
+--'1'&x"E980",'1'&x"E981",'1'&x"E982",'1'&x"E983",'1'&x"E984",'1'&x"E985",'1'&x"E986",'1'&x"E987",'1'&x"E988",'1'&x"E989",'1'&x"E98A",'1'&x"E98B",'1'&x"E98C",'1'&x"E98D",'1'&x"E98E",'1'&x"E98F",
+--'1'&x"E990",'1'&x"E991",'1'&x"E992",'1'&x"E993",'1'&x"E994",'1'&x"E995",'1'&x"E996",'1'&x"E997",'1'&x"E998",'1'&x"E999",'1'&x"E99A",'1'&x"E99B",'1'&x"E99C",'1'&x"E99D",'1'&x"E99E",'1'&x"E99F",
+--'1'&x"E9A0",'1'&x"E9A1",'1'&x"E9A2",'1'&x"E9A3",'1'&x"E9A4",'1'&x"E9A5",'1'&x"E9A6",'1'&x"E9A7",'1'&x"E9A8",'1'&x"E9A9",'1'&x"E9AA",'1'&x"E9AB",'1'&x"E9AC",'1'&x"E9AD",'1'&x"E9AE",'1'&x"E9AF",
+--'1'&x"E9B0",'1'&x"E9B1",'1'&x"E9B2",'1'&x"E9B3",'1'&x"E9B4",'1'&x"E9B5",'1'&x"E9B6",'1'&x"E9B7",'1'&x"E9B8",'1'&x"E9B9",'1'&x"E9BA",'1'&x"E9BB",'1'&x"E9BC",'1'&x"E9BD",'1'&x"E9BE",'1'&x"E9BF",
+--'1'&x"E9C0",'1'&x"E9C1",'1'&x"E9C2",'1'&x"E9C3",'1'&x"E9C4",'1'&x"E9C5",'1'&x"E9C6",'1'&x"E9C7",'1'&x"E9C8",'1'&x"E9C9",'1'&x"E9CA",'1'&x"E9CB",'1'&x"E9CC",'1'&x"E9CD",'1'&x"E9CE",'1'&x"E9CF",
+--'1'&x"E9D0",'1'&x"E9D1",'1'&x"E9D2",'1'&x"E9D3",'1'&x"E9D4",'1'&x"E9D5",'1'&x"E9D6",'1'&x"E9D7",'1'&x"E9D8",'1'&x"E9D9",'1'&x"E9DA",'1'&x"E9DB",'1'&x"E9DC",'1'&x"E9DD",'1'&x"E9DE",'1'&x"E9DF",
+--'1'&x"E9E0",'1'&x"E9E1",'1'&x"E9E2",'1'&x"E9E3",'1'&x"E9E4",'1'&x"E9E5",'1'&x"E9E6",'1'&x"E9E7",'1'&x"E9E8",'1'&x"E9E9",'1'&x"E9EA",'1'&x"E9EB",'1'&x"E9EC",'1'&x"E9ED",'1'&x"E9EE",'1'&x"E9EF",
+--'1'&x"E9F0",'1'&x"E9F1",'1'&x"E9F2",'1'&x"E9F3",'1'&x"E9F4",'1'&x"E9F5",'1'&x"E9F6",'1'&x"E9F7",'1'&x"E9F8",'1'&x"E9F9",'1'&x"E9FA",'1'&x"E9FB",'1'&x"E9FC",'1'&x"E9FD",'1'&x"E9FE",'1'&x"E9FF",
+--'1'&x"EA00",'1'&x"EA01",'1'&x"EA02",'1'&x"EA03",'1'&x"EA04",'1'&x"EA05",'1'&x"EA06",'1'&x"EA07",'1'&x"EA08",'1'&x"EA09",'1'&x"EA0A",'1'&x"EA0B",'1'&x"EA0C",'1'&x"EA0D",'1'&x"EA0E",'1'&x"EA0F",
+--'1'&x"EA10",'1'&x"EA11",'1'&x"EA12",'1'&x"EA13",'1'&x"EA14",'1'&x"EA15",'1'&x"EA16",'1'&x"EA17",'1'&x"EA18",'1'&x"EA19",'1'&x"EA1A",'1'&x"EA1B",'1'&x"EA1C",'1'&x"EA1D",'1'&x"EA1E",'1'&x"EA1F",
+--'1'&x"EA20",'1'&x"EA21",'1'&x"EA22",'1'&x"EA23",'1'&x"EA24",'1'&x"EA25",'1'&x"EA26",'1'&x"EA27",'1'&x"EA28",'1'&x"EA29",'1'&x"EA2A",'1'&x"EA2B",'1'&x"EA2C",'1'&x"EA2D",'1'&x"EA2E",'1'&x"EA2F",
+--'1'&x"EA30",'1'&x"EA31",'1'&x"EA32",'1'&x"EA33",'1'&x"EA34",'1'&x"EA35",'1'&x"EA36",'1'&x"EA37",'1'&x"EA38",'1'&x"EA39",'1'&x"EA3A",'1'&x"EA3B",'1'&x"EA3C",'1'&x"EA3D",'1'&x"EA3E",'1'&x"EA3F",
+--'1'&x"EA40",'1'&x"EA41",'1'&x"EA42",'1'&x"EA43",'1'&x"EA44",'1'&x"EA45",'1'&x"EA46",'1'&x"EA47",'1'&x"EA48",'1'&x"EA49",'1'&x"EA4A",'1'&x"EA4B",'1'&x"EA4C",'1'&x"EA4D",'1'&x"EA4E",'1'&x"EA4F",
+--'1'&x"EA50",'1'&x"EA51",'1'&x"EA52",'1'&x"EA53",'1'&x"EA54",'1'&x"EA55",'1'&x"EA56",'1'&x"EA57",'1'&x"EA58",'1'&x"EA59",'1'&x"EA5A",'1'&x"EA5B",'1'&x"EA5C",'1'&x"EA5D",'1'&x"EA5E",'1'&x"EA5F",
+--'1'&x"EA60",'1'&x"EA61",'1'&x"EA62",'1'&x"EA63",'1'&x"EA64",'1'&x"EA65",'1'&x"EA66",'1'&x"EA67",'1'&x"EA68",'1'&x"EA69",'1'&x"EA6A",'1'&x"EA6B",'1'&x"EA6C",'1'&x"EA6D",'1'&x"EA6E",'1'&x"EA6F",
+--'1'&x"EA70",'1'&x"EA71",'1'&x"EA72",'1'&x"EA73",'1'&x"EA74",'1'&x"EA75",'1'&x"EA76",'1'&x"EA77",'1'&x"EA78",'1'&x"EA79",'1'&x"EA7A",'1'&x"EA7B",'1'&x"EA7C",'1'&x"EA7D",'1'&x"EA7E",'1'&x"EA7F",
+--'1'&x"EA80",'1'&x"EA81",'1'&x"EA82",'1'&x"EA83",'1'&x"EA84",'1'&x"EA85",'1'&x"EA86",'1'&x"EA87",'1'&x"EA88",'1'&x"EA89",'1'&x"EA8A",'1'&x"EA8B",'1'&x"EA8C",'1'&x"EA8D",'1'&x"EA8E",'1'&x"EA8F",
+--'1'&x"EA90",'1'&x"EA91",'1'&x"EA92",'1'&x"EA93",'1'&x"EA94",'1'&x"EA95",'1'&x"EA96",'1'&x"EA97",'1'&x"EA98",'1'&x"EA99",'1'&x"EA9A",'1'&x"EA9B",'1'&x"EA9C",'1'&x"EA9D",'1'&x"EA9E",'1'&x"EA9F",
+--'1'&x"EAA0",'1'&x"EAA1",'1'&x"EAA2",'1'&x"EAA3",'1'&x"EAA4",'1'&x"EAA5",'1'&x"EAA6",'1'&x"EAA7",'1'&x"EAA8",'1'&x"EAA9",'1'&x"EAAA",'1'&x"EAAB",'1'&x"EAAC",'1'&x"EAAD",'1'&x"EAAE",'1'&x"EAAF",
+--'1'&x"EAB0",'1'&x"EAB1",'1'&x"EAB2",'1'&x"EAB3",'1'&x"EAB4",'1'&x"EAB5",'1'&x"EAB6",'1'&x"EAB7",'1'&x"EAB8",'1'&x"EAB9",'1'&x"EABA",'1'&x"EABB",'1'&x"EABC",'1'&x"EABD",'1'&x"EABE",'1'&x"EABF",
+--'1'&x"EAC0",'1'&x"EAC1",'1'&x"EAC2",'1'&x"EAC3",'1'&x"EAC4",'1'&x"EAC5",'1'&x"EAC6",'1'&x"EAC7",'1'&x"EAC8",'1'&x"EAC9",'1'&x"EACA",'1'&x"EACB",'1'&x"EACC",'1'&x"EACD",'1'&x"EACE",'1'&x"EACF",
+--'1'&x"EAD0",'1'&x"EAD1",'1'&x"EAD2",'1'&x"EAD3",'1'&x"EAD4",'1'&x"EAD5",'1'&x"EAD6",'1'&x"EAD7",'1'&x"EAD8",'1'&x"EAD9",'1'&x"EADA",'1'&x"EADB",'1'&x"EADC",'1'&x"EADD",'1'&x"EADE",'1'&x"EADF",
+--'1'&x"EAE0",'1'&x"EAE1",'1'&x"EAE2",'1'&x"EAE3",'1'&x"EAE4",'1'&x"EAE5",'1'&x"EAE6",'1'&x"EAE7",'1'&x"EAE8",'1'&x"EAE9",'1'&x"EAEA",'1'&x"EAEB",'1'&x"EAEC",'1'&x"EAED",'1'&x"EAEE",'1'&x"EAEF",
+--'1'&x"EAF0",'1'&x"EAF1",'1'&x"EAF2",'1'&x"EAF3",'1'&x"EAF4",'1'&x"EAF5",'1'&x"EAF6",'1'&x"EAF7",'1'&x"EAF8",'1'&x"EAF9",'1'&x"EAFA",'1'&x"EAFB",'1'&x"EAFC",'1'&x"EAFD",'1'&x"EAFE",'1'&x"EAFF",
+--'1'&x"EB00",'1'&x"EB01",'1'&x"EB02",'1'&x"EB03",'1'&x"EB04",'1'&x"EB05",'1'&x"EB06",'1'&x"EB07",'1'&x"EB08",'1'&x"EB09",'1'&x"EB0A",'1'&x"EB0B",'1'&x"EB0C",'1'&x"EB0D",'1'&x"EB0E",'1'&x"EB0F",
+--'1'&x"EB10",'1'&x"EB11",'1'&x"EB12",'1'&x"EB13",'1'&x"EB14",'1'&x"EB15",'1'&x"EB16",'1'&x"EB17",'1'&x"EB18",'1'&x"EB19",'1'&x"EB1A",'1'&x"EB1B",'1'&x"EB1C",'1'&x"EB1D",'1'&x"EB1E",'1'&x"EB1F",
+--'1'&x"EB20",'1'&x"EB21",'1'&x"EB22",'1'&x"EB23",'1'&x"EB24",'1'&x"EB25",'1'&x"EB26",'1'&x"EB27",'1'&x"EB28",'1'&x"EB29",'1'&x"EB2A",'1'&x"EB2B",'1'&x"EB2C",'1'&x"EB2D",'1'&x"EB2E",'1'&x"EB2F",
+--'1'&x"EB30",'1'&x"EB31",'1'&x"EB32",'1'&x"EB33",'1'&x"EB34",'1'&x"EB35",'1'&x"EB36",'1'&x"EB37",'1'&x"EB38",'1'&x"EB39",'1'&x"EB3A",'1'&x"EB3B",'1'&x"EB3C",'1'&x"EB3D",'1'&x"EB3E",'1'&x"EB3F",
+--'1'&x"EB40",'1'&x"EB41",'1'&x"EB42",'1'&x"EB43",'1'&x"EB44",'1'&x"EB45",'1'&x"EB46",'1'&x"EB47",'1'&x"EB48",'1'&x"EB49",'1'&x"EB4A",'1'&x"EB4B",'1'&x"EB4C",'1'&x"EB4D",'1'&x"EB4E",'1'&x"EB4F",
+--'1'&x"EB50",'1'&x"EB51",'1'&x"EB52",'1'&x"EB53",'1'&x"EB54",'1'&x"EB55",'1'&x"EB56",'1'&x"EB57",'1'&x"EB58",'1'&x"EB59",'1'&x"EB5A",'1'&x"EB5B",'1'&x"EB5C",'1'&x"EB5D",'1'&x"EB5E",'1'&x"EB5F",
+--'1'&x"EB60",'1'&x"EB61",'1'&x"EB62",'1'&x"EB63",'1'&x"EB64",'1'&x"EB65",'1'&x"EB66",'1'&x"EB67",'1'&x"EB68",'1'&x"EB69",'1'&x"EB6A",'1'&x"EB6B",'1'&x"EB6C",'1'&x"EB6D",'1'&x"EB6E",'1'&x"EB6F",
+--'1'&x"EB70",'1'&x"EB71",'1'&x"EB72",'1'&x"EB73",'1'&x"EB74",'1'&x"EB75",'1'&x"EB76",'1'&x"EB77",'1'&x"EB78",'1'&x"EB79",'1'&x"EB7A",'1'&x"EB7B",'1'&x"EB7C",'1'&x"EB7D",'1'&x"EB7E",'1'&x"EB7F",
+--'1'&x"EB80",'1'&x"EB81",'1'&x"EB82",'1'&x"EB83",'1'&x"EB84",'1'&x"EB85",'1'&x"EB86",'1'&x"EB87",'1'&x"EB88",'1'&x"EB89",'1'&x"EB8A",'1'&x"EB8B",'1'&x"EB8C",'1'&x"EB8D",'1'&x"EB8E",'1'&x"EB8F",
+--'1'&x"EB90",'1'&x"EB91",'1'&x"EB92",'1'&x"EB93",'1'&x"EB94",'1'&x"EB95",'1'&x"EB96",'1'&x"EB97",'1'&x"EB98",'1'&x"EB99",'1'&x"EB9A",'1'&x"EB9B",'1'&x"EB9C",'1'&x"EB9D",'1'&x"EB9E",'1'&x"EB9F",
+--'1'&x"EBA0",'1'&x"EBA1",'1'&x"EBA2",'1'&x"EBA3",'1'&x"EBA4",'1'&x"EBA5",'1'&x"EBA6",'1'&x"EBA7",'1'&x"EBA8",'1'&x"EBA9",'1'&x"EBAA",'1'&x"EBAB",'1'&x"EBAC",'1'&x"EBAD",'1'&x"EBAE",'1'&x"EBAF",
+--'1'&x"EBB0",'1'&x"EBB1",'1'&x"EBB2",'1'&x"EBB3",'1'&x"EBB4",'1'&x"EBB5",'1'&x"EBB6",'1'&x"EBB7",'1'&x"EBB8",'1'&x"EBB9",'1'&x"EBBA",'1'&x"EBBB",'1'&x"EBBC",'1'&x"EBBD",'1'&x"EBBE",'1'&x"EBBF",
+--'1'&x"EBC0",'1'&x"EBC1",'1'&x"EBC2",'1'&x"EBC3",'1'&x"EBC4",'1'&x"EBC5",'1'&x"EBC6",'1'&x"EBC7",'1'&x"EBC8",'1'&x"EBC9",'1'&x"EBCA",'1'&x"EBCB",'1'&x"EBCC",'1'&x"EBCD",'1'&x"EBCE",'1'&x"EBCF",
+--'1'&x"EBD0",'1'&x"EBD1",'1'&x"EBD2",'1'&x"EBD3",'1'&x"EBD4",'1'&x"EBD5",'1'&x"EBD6",'1'&x"EBD7",'1'&x"EBD8",'1'&x"EBD9",'1'&x"EBDA",'1'&x"EBDB",'1'&x"EBDC",'1'&x"EBDD",'1'&x"EBDE",'1'&x"EBDF",
+--'1'&x"EBE0",'1'&x"EBE1",'1'&x"EBE2",'1'&x"EBE3",'1'&x"EBE4",'1'&x"EBE5",'1'&x"EBE6",'1'&x"EBE7",'1'&x"EBE8",'1'&x"EBE9",'1'&x"EBEA",'1'&x"EBEB",'1'&x"EBEC",'1'&x"EBED",'1'&x"EBEE",'1'&x"EBEF",
+--'1'&x"EBF0",'1'&x"EBF1",'1'&x"EBF2",'1'&x"EBF3",'1'&x"EBF4",'1'&x"EBF5",'1'&x"EBF6",'1'&x"EBF7",'1'&x"EBF8",'1'&x"EBF9",'1'&x"EBFA",'1'&x"EBFB",'1'&x"EBFC",'1'&x"EBFD",'1'&x"EBFE",'1'&x"EBFF",
+--'1'&x"EC00",'1'&x"EC01",'1'&x"EC02",'1'&x"EC03",'1'&x"EC04",'1'&x"EC05",'1'&x"EC06",'1'&x"EC07",'1'&x"EC08",'1'&x"EC09",'1'&x"EC0A",'1'&x"EC0B",'1'&x"EC0C",'1'&x"EC0D",'1'&x"EC0E",'1'&x"EC0F",
+--'1'&x"EC10",'1'&x"EC11",'1'&x"EC12",'1'&x"EC13",'1'&x"EC14",'1'&x"EC15",'1'&x"EC16",'1'&x"EC17",'1'&x"EC18",'1'&x"EC19",'1'&x"EC1A",'1'&x"EC1B",'1'&x"EC1C",'1'&x"EC1D",'1'&x"EC1E",'1'&x"EC1F",
+--'1'&x"EC20",'1'&x"EC21",'1'&x"EC22",'1'&x"EC23",'1'&x"EC24",'1'&x"EC25",'1'&x"EC26",'1'&x"EC27",'1'&x"EC28",'1'&x"EC29",'1'&x"EC2A",'1'&x"EC2B",'1'&x"EC2C",'1'&x"EC2D",'1'&x"EC2E",'1'&x"EC2F",
+--'1'&x"EC30",'1'&x"EC31",'1'&x"EC32",'1'&x"EC33",'1'&x"EC34",'1'&x"EC35",'1'&x"EC36",'1'&x"EC37",'1'&x"EC38",'1'&x"EC39",'1'&x"EC3A",'1'&x"EC3B",'1'&x"EC3C",'1'&x"EC3D",'1'&x"EC3E",'1'&x"EC3F",
+--'1'&x"EC40",'1'&x"EC41",'1'&x"EC42",'1'&x"EC43",'1'&x"EC44",'1'&x"EC45",'1'&x"EC46",'1'&x"EC47",'1'&x"EC48",'1'&x"EC49",'1'&x"EC4A",'1'&x"EC4B",'1'&x"EC4C",'1'&x"EC4D",'1'&x"EC4E",'1'&x"EC4F",
+--'1'&x"EC50",'1'&x"EC51",'1'&x"EC52",'1'&x"EC53",'1'&x"EC54",'1'&x"EC55",'1'&x"EC56",'1'&x"EC57",'1'&x"EC58",'1'&x"EC59",'1'&x"EC5A",'1'&x"EC5B",'1'&x"EC5C",'1'&x"EC5D",'1'&x"EC5E",'1'&x"EC5F",
+--'1'&x"EC60",'1'&x"EC61",'1'&x"EC62",'1'&x"EC63",'1'&x"EC64",'1'&x"EC65",'1'&x"EC66",'1'&x"EC67",'1'&x"EC68",'1'&x"EC69",'1'&x"EC6A",'1'&x"EC6B",'1'&x"EC6C",'1'&x"EC6D",'1'&x"EC6E",'1'&x"EC6F",
+--'1'&x"EC70",'1'&x"EC71",'1'&x"EC72",'1'&x"EC73",'1'&x"EC74",'1'&x"EC75",'1'&x"EC76",'1'&x"EC77",'1'&x"EC78",'1'&x"EC79",'1'&x"EC7A",'1'&x"EC7B",'1'&x"EC7C",'1'&x"EC7D",'1'&x"EC7E",'1'&x"EC7F",
+--'1'&x"EC80",'1'&x"EC81",'1'&x"EC82",'1'&x"EC83",'1'&x"EC84",'1'&x"EC85",'1'&x"EC86",'1'&x"EC87",'1'&x"EC88",'1'&x"EC89",'1'&x"EC8A",'1'&x"EC8B",'1'&x"EC8C",'1'&x"EC8D",'1'&x"EC8E",'1'&x"EC8F",
+--'1'&x"EC90",'1'&x"EC91",'1'&x"EC92",'1'&x"EC93",'1'&x"EC94",'1'&x"EC95",'1'&x"EC96",'1'&x"EC97",'1'&x"EC98",'1'&x"EC99",'1'&x"EC9A",'1'&x"EC9B",'1'&x"EC9C",'1'&x"EC9D",'1'&x"EC9E",'1'&x"EC9F",
+--'1'&x"ECA0",'1'&x"ECA1",'1'&x"ECA2",'1'&x"ECA3",'1'&x"ECA4",'1'&x"ECA5",'1'&x"ECA6",'1'&x"ECA7",'1'&x"ECA8",'1'&x"ECA9",'1'&x"ECAA",'1'&x"ECAB",'1'&x"ECAC",'1'&x"ECAD",'1'&x"ECAE",'1'&x"ECAF",
+--'1'&x"ECB0",'1'&x"ECB1",'1'&x"ECB2",'1'&x"ECB3",'1'&x"ECB4",'1'&x"ECB5",'1'&x"ECB6",'1'&x"ECB7",'1'&x"ECB8",'1'&x"ECB9",'1'&x"ECBA",'1'&x"ECBB",'1'&x"ECBC",'1'&x"ECBD",'1'&x"ECBE",'1'&x"ECBF",
+--'1'&x"ECC0",'1'&x"ECC1",'1'&x"ECC2",'1'&x"ECC3",'1'&x"ECC4",'1'&x"ECC5",'1'&x"ECC6",'1'&x"ECC7",'1'&x"ECC8",'1'&x"ECC9",'1'&x"ECCA",'1'&x"ECCB",'1'&x"ECCC",'1'&x"ECCD",'1'&x"ECCE",'1'&x"ECCF",
+--'1'&x"ECD0",'1'&x"ECD1",'1'&x"ECD2",'1'&x"ECD3",'1'&x"ECD4",'1'&x"ECD5",'1'&x"ECD6",'1'&x"ECD7",'1'&x"ECD8",'1'&x"ECD9",'1'&x"ECDA",'1'&x"ECDB",'1'&x"ECDC",'1'&x"ECDD",'1'&x"ECDE",'1'&x"ECDF",
+--'1'&x"ECE0",'1'&x"ECE1",'1'&x"ECE2",'1'&x"ECE3",'1'&x"ECE4",'1'&x"ECE5",'1'&x"ECE6",'1'&x"ECE7",'1'&x"ECE8",'1'&x"ECE9",'1'&x"ECEA",'1'&x"ECEB",'1'&x"ECEC",'1'&x"ECED",'1'&x"ECEE",'1'&x"ECEF",
+--'1'&x"ECF0",'1'&x"ECF1",'1'&x"ECF2",'1'&x"ECF3",'1'&x"ECF4",'1'&x"ECF5",'1'&x"ECF6",'1'&x"ECF7",'1'&x"ECF8",'1'&x"ECF9",'1'&x"ECFA",'1'&x"ECFB",'1'&x"ECFC",'1'&x"ECFD",'1'&x"ECFE",'1'&x"ECFF",
+--'1'&x"ED00",'1'&x"ED01",'1'&x"ED02",'1'&x"ED03",'1'&x"ED04",'1'&x"ED05",'1'&x"ED06",'1'&x"ED07",'1'&x"ED08",'1'&x"ED09",'1'&x"ED0A",'1'&x"ED0B",'1'&x"ED0C",'1'&x"ED0D",'1'&x"ED0E",'1'&x"ED0F",
+--'1'&x"ED10",'1'&x"ED11",'1'&x"ED12",'1'&x"ED13",'1'&x"ED14",'1'&x"ED15",'1'&x"ED16",'1'&x"ED17",'1'&x"ED18",'1'&x"ED19",'1'&x"ED1A",'1'&x"ED1B",'1'&x"ED1C",'1'&x"ED1D",'1'&x"ED1E",'1'&x"ED1F",
+--'1'&x"ED20",'1'&x"ED21",'1'&x"ED22",'1'&x"ED23",'1'&x"ED24",'1'&x"ED25",'1'&x"ED26",'1'&x"ED27",'1'&x"ED28",'1'&x"ED29",'1'&x"ED2A",'1'&x"ED2B",'1'&x"ED2C",'1'&x"ED2D",'1'&x"ED2E",'1'&x"ED2F",
+--'1'&x"ED30",'1'&x"ED31",'1'&x"ED32",'1'&x"ED33",'1'&x"ED34",'1'&x"ED35",'1'&x"ED36",'1'&x"ED37",'1'&x"ED38",'1'&x"ED39",'1'&x"ED3A",'1'&x"ED3B",'1'&x"ED3C",'1'&x"ED3D",'1'&x"ED3E",'1'&x"ED3F",
+--'1'&x"ED40",'1'&x"ED41",'1'&x"ED42",'1'&x"ED43",'1'&x"ED44",'1'&x"ED45",'1'&x"ED46",'1'&x"ED47",'1'&x"ED48",'1'&x"ED49",'1'&x"ED4A",'1'&x"ED4B",'1'&x"ED4C",'1'&x"ED4D",'1'&x"ED4E",'1'&x"ED4F",
+--'1'&x"ED50",'1'&x"ED51",'1'&x"ED52",'1'&x"ED53",'1'&x"ED54",'1'&x"ED55",'1'&x"ED56",'1'&x"ED57",'1'&x"ED58",'1'&x"ED59",'1'&x"ED5A",'1'&x"ED5B",'1'&x"ED5C",'1'&x"ED5D",'1'&x"ED5E",'1'&x"ED5F",
+--'1'&x"ED60",'1'&x"ED61",'1'&x"ED62",'1'&x"ED63",'1'&x"ED64",'1'&x"ED65",'1'&x"ED66",'1'&x"ED67",'1'&x"ED68",'1'&x"ED69",'1'&x"ED6A",'1'&x"ED6B",'1'&x"ED6C",'1'&x"ED6D",'1'&x"ED6E",'1'&x"ED6F",
+--'1'&x"ED70",'1'&x"ED71",'1'&x"ED72",'1'&x"ED73",'1'&x"ED74",'1'&x"ED75",'1'&x"ED76",'1'&x"ED77",'1'&x"ED78",'1'&x"ED79",'1'&x"ED7A",'1'&x"ED7B",'1'&x"ED7C",'1'&x"ED7D",'1'&x"ED7E",'1'&x"ED7F",
+--'1'&x"ED80",'1'&x"ED81",'1'&x"ED82",'1'&x"ED83",'1'&x"ED84",'1'&x"ED85",'1'&x"ED86",'1'&x"ED87",'1'&x"ED88",'1'&x"ED89",'1'&x"ED8A",'1'&x"ED8B",'1'&x"ED8C",'1'&x"ED8D",'1'&x"ED8E",'1'&x"ED8F",
+--'1'&x"ED90",'1'&x"ED91",'1'&x"ED92",'1'&x"ED93",'1'&x"ED94",'1'&x"ED95",'1'&x"ED96",'1'&x"ED97",'1'&x"ED98",'1'&x"ED99",'1'&x"ED9A",'1'&x"ED9B",'1'&x"ED9C",'1'&x"ED9D",'1'&x"ED9E",'1'&x"ED9F",
+--'1'&x"EDA0",'1'&x"EDA1",'1'&x"EDA2",'1'&x"EDA3",'1'&x"EDA4",'1'&x"EDA5",'1'&x"EDA6",'1'&x"EDA7",'1'&x"EDA8",'1'&x"EDA9",'1'&x"EDAA",'1'&x"EDAB",'1'&x"EDAC",'1'&x"EDAD",'1'&x"EDAE",'1'&x"EDAF",
+--'1'&x"EDB0",'1'&x"EDB1",'1'&x"EDB2",'1'&x"EDB3",'1'&x"EDB4",'1'&x"EDB5",'1'&x"EDB6",'1'&x"EDB7",'1'&x"EDB8",'1'&x"EDB9",'1'&x"EDBA",'1'&x"EDBB",'1'&x"EDBC",'1'&x"EDBD",'1'&x"EDBE",'1'&x"EDBF",
+--'1'&x"EDC0",'1'&x"EDC1",'1'&x"EDC2",'1'&x"EDC3",'1'&x"EDC4",'1'&x"EDC5",'1'&x"EDC6",'1'&x"EDC7",'1'&x"EDC8",'1'&x"EDC9",'1'&x"EDCA",'1'&x"EDCB",'1'&x"EDCC",'1'&x"EDCD",'1'&x"EDCE",'1'&x"EDCF",
+--'1'&x"EDD0",'1'&x"EDD1",'1'&x"EDD2",'1'&x"EDD3",'1'&x"EDD4",'1'&x"EDD5",'1'&x"EDD6",'1'&x"EDD7",'1'&x"EDD8",'1'&x"EDD9",'1'&x"EDDA",'1'&x"EDDB",'1'&x"EDDC",'1'&x"EDDD",'1'&x"EDDE",'1'&x"EDDF",
+--'1'&x"EDE0",'1'&x"EDE1",'1'&x"EDE2",'1'&x"EDE3",'1'&x"EDE4",'1'&x"EDE5",'1'&x"EDE6",'1'&x"EDE7",'1'&x"EDE8",'1'&x"EDE9",'1'&x"EDEA",'1'&x"EDEB",'1'&x"EDEC",'1'&x"EDED",'1'&x"EDEE",'1'&x"EDEF",
+--'1'&x"EDF0",'1'&x"EDF1",'1'&x"EDF2",'1'&x"EDF3",'1'&x"EDF4",'1'&x"EDF5",'1'&x"EDF6",'1'&x"EDF7",'1'&x"EDF8",'1'&x"EDF9",'1'&x"EDFA",'1'&x"EDFB",'1'&x"EDFC",'1'&x"EDFD",'1'&x"EDFE",'1'&x"EDFF",
+--'1'&x"EE00",'1'&x"EE01",'1'&x"EE02",'1'&x"EE03",'1'&x"EE04",'1'&x"EE05",'1'&x"EE06",'1'&x"EE07",'1'&x"EE08",'1'&x"EE09",'1'&x"EE0A",'1'&x"EE0B",'1'&x"EE0C",'1'&x"EE0D",'1'&x"EE0E",'1'&x"EE0F",
+--'1'&x"EE10",'1'&x"EE11",'1'&x"EE12",'1'&x"EE13",'1'&x"EE14",'1'&x"EE15",'1'&x"EE16",'1'&x"EE17",'1'&x"EE18",'1'&x"EE19",'1'&x"EE1A",'1'&x"EE1B",'1'&x"EE1C",'1'&x"EE1D",'1'&x"EE1E",'1'&x"EE1F",
+--'1'&x"EE20",'1'&x"EE21",'1'&x"EE22",'1'&x"EE23",'1'&x"EE24",'1'&x"EE25",'1'&x"EE26",'1'&x"EE27",'1'&x"EE28",'1'&x"EE29",'1'&x"EE2A",'1'&x"EE2B",'1'&x"EE2C",'1'&x"EE2D",'1'&x"EE2E",'1'&x"EE2F",
+--'1'&x"EE30",'1'&x"EE31",'1'&x"EE32",'1'&x"EE33",'1'&x"EE34",'1'&x"EE35",'1'&x"EE36",'1'&x"EE37",'1'&x"EE38",'1'&x"EE39",'1'&x"EE3A",'1'&x"EE3B",'1'&x"EE3C",'1'&x"EE3D",'1'&x"EE3E",'1'&x"EE3F",
+--'1'&x"EE40",'1'&x"EE41",'1'&x"EE42",'1'&x"EE43",'1'&x"EE44",'1'&x"EE45",'1'&x"EE46",'1'&x"EE47",'1'&x"EE48",'1'&x"EE49",'1'&x"EE4A",'1'&x"EE4B",'1'&x"EE4C",'1'&x"EE4D",'1'&x"EE4E",'1'&x"EE4F",
+--'1'&x"EE50",'1'&x"EE51",'1'&x"EE52",'1'&x"EE53",'1'&x"EE54",'1'&x"EE55",'1'&x"EE56",'1'&x"EE57",'1'&x"EE58",'1'&x"EE59",'1'&x"EE5A",'1'&x"EE5B",'1'&x"EE5C",'1'&x"EE5D",'1'&x"EE5E",'1'&x"EE5F",
+--'1'&x"EE60",'1'&x"EE61",'1'&x"EE62",'1'&x"EE63",'1'&x"EE64",'1'&x"EE65",'1'&x"EE66",'1'&x"EE67",'1'&x"EE68",'1'&x"EE69",'1'&x"EE6A",'1'&x"EE6B",'1'&x"EE6C",'1'&x"EE6D",'1'&x"EE6E",'1'&x"EE6F",
+--'1'&x"EE70",'1'&x"EE71",'1'&x"EE72",'1'&x"EE73",'1'&x"EE74",'1'&x"EE75",'1'&x"EE76",'1'&x"EE77",'1'&x"EE78",'1'&x"EE79",'1'&x"EE7A",'1'&x"EE7B",'1'&x"EE7C",'1'&x"EE7D",'1'&x"EE7E",'1'&x"EE7F",
+--'1'&x"EE80",'1'&x"EE81",'1'&x"EE82",'1'&x"EE83",'1'&x"EE84",'1'&x"EE85",'1'&x"EE86",'1'&x"EE87",'1'&x"EE88",'1'&x"EE89",'1'&x"EE8A",'1'&x"EE8B",'1'&x"EE8C",'1'&x"EE8D",'1'&x"EE8E",'1'&x"EE8F",
+--'1'&x"EE90",'1'&x"EE91",'1'&x"EE92",'1'&x"EE93",'1'&x"EE94",'1'&x"EE95",'1'&x"EE96",'1'&x"EE97",'1'&x"EE98",'1'&x"EE99",'1'&x"EE9A",'1'&x"EE9B",'1'&x"EE9C",'1'&x"EE9D",'1'&x"EE9E",'1'&x"EE9F",
+--'1'&x"EEA0",'1'&x"EEA1",'1'&x"EEA2",'1'&x"EEA3",'1'&x"EEA4",'1'&x"EEA5",'1'&x"EEA6",'1'&x"EEA7",'1'&x"EEA8",'1'&x"EEA9",'1'&x"EEAA",'1'&x"EEAB",'1'&x"EEAC",'1'&x"EEAD",'1'&x"EEAE",'1'&x"EEAF",
+--'1'&x"EEB0",'1'&x"EEB1",'1'&x"EEB2",'1'&x"EEB3",'1'&x"EEB4",'1'&x"EEB5",'1'&x"EEB6",'1'&x"EEB7",'1'&x"EEB8",'1'&x"EEB9",'1'&x"EEBA",'1'&x"EEBB",'1'&x"EEBC",'1'&x"EEBD",'1'&x"EEBE",'1'&x"EEBF",
+--'1'&x"EEC0",'1'&x"EEC1",'1'&x"EEC2",'1'&x"EEC3",'1'&x"EEC4",'1'&x"EEC5",'1'&x"EEC6",'1'&x"EEC7",'1'&x"EEC8",'1'&x"EEC9",'1'&x"EECA",'1'&x"EECB",'1'&x"EECC",'1'&x"EECD",'1'&x"EECE",'1'&x"EECF",
+--'1'&x"EED0",'1'&x"EED1",'1'&x"EED2",'1'&x"EED3",'1'&x"EED4",'1'&x"EED5",'1'&x"EED6",'1'&x"EED7",'1'&x"EED8",'1'&x"EED9",'1'&x"EEDA",'1'&x"EEDB",'1'&x"EEDC",'1'&x"EEDD",'1'&x"EEDE",'1'&x"EEDF",
+--'1'&x"EEE0",'1'&x"EEE1",'1'&x"EEE2",'1'&x"EEE3",'1'&x"EEE4",'1'&x"EEE5",'1'&x"EEE6",'1'&x"EEE7",'1'&x"EEE8",'1'&x"EEE9",'1'&x"EEEA",'1'&x"EEEB",'1'&x"EEEC",'1'&x"EEED",'1'&x"EEEE",'1'&x"EEEF",
+--'1'&x"EEF0",'1'&x"EEF1",'1'&x"EEF2",'1'&x"EEF3",'1'&x"EEF4",'1'&x"EEF5",'1'&x"EEF6",'1'&x"EEF7",'1'&x"EEF8",'1'&x"EEF9",'1'&x"EEFA",'1'&x"EEFB",'1'&x"EEFC",'1'&x"EEFD",'1'&x"EEFE",'1'&x"EEFF",
+--'1'&x"EF00",'1'&x"EF01",'1'&x"EF02",'1'&x"EF03",'1'&x"EF04",'1'&x"EF05",'1'&x"EF06",'1'&x"EF07",'1'&x"EF08",'1'&x"EF09",'1'&x"EF0A",'1'&x"EF0B",'1'&x"EF0C",'1'&x"EF0D",'1'&x"EF0E",'1'&x"EF0F",
+--'1'&x"EF10",'1'&x"EF11",'1'&x"EF12",'1'&x"EF13",'1'&x"EF14",'1'&x"EF15",'1'&x"EF16",'1'&x"EF17",'1'&x"EF18",'1'&x"EF19",'1'&x"EF1A",'1'&x"EF1B",'1'&x"EF1C",'1'&x"EF1D",'1'&x"EF1E",'1'&x"EF1F",
+--'1'&x"EF20",'1'&x"EF21",'1'&x"EF22",'1'&x"EF23",'1'&x"EF24",'1'&x"EF25",'1'&x"EF26",'1'&x"EF27",'1'&x"EF28",'1'&x"EF29",'1'&x"EF2A",'1'&x"EF2B",'1'&x"EF2C",'1'&x"EF2D",'1'&x"EF2E",'1'&x"EF2F",
+--'1'&x"EF30",'1'&x"EF31",'1'&x"EF32",'1'&x"EF33",'1'&x"EF34",'1'&x"EF35",'1'&x"EF36",'1'&x"EF37",'1'&x"EF38",'1'&x"EF39",'1'&x"EF3A",'1'&x"EF3B",'1'&x"EF3C",'1'&x"EF3D",'1'&x"EF3E",'1'&x"EF3F",
+--'1'&x"EF40",'1'&x"EF41",'1'&x"EF42",'1'&x"EF43",'1'&x"EF44",'1'&x"EF45",'1'&x"EF46",'1'&x"EF47",'1'&x"EF48",'1'&x"EF49",'1'&x"EF4A",'1'&x"EF4B",'1'&x"EF4C",'1'&x"EF4D",'1'&x"EF4E",'1'&x"EF4F",
+--'1'&x"EF50",'1'&x"EF51",'1'&x"EF52",'1'&x"EF53",'1'&x"EF54",'1'&x"EF55",'1'&x"EF56",'1'&x"EF57",'1'&x"EF58",'1'&x"EF59",'1'&x"EF5A",'1'&x"EF5B",'1'&x"EF5C",'1'&x"EF5D",'1'&x"EF5E",'1'&x"EF5F",
+--'1'&x"EF60",'1'&x"EF61",'1'&x"EF62",'1'&x"EF63",'1'&x"EF64",'1'&x"EF65",'1'&x"EF66",'1'&x"EF67",'1'&x"EF68",'1'&x"EF69",'1'&x"EF6A",'1'&x"EF6B",'1'&x"EF6C",'1'&x"EF6D",'1'&x"EF6E",'1'&x"EF6F",
+--'1'&x"EF70",'1'&x"EF71",'1'&x"EF72",'1'&x"EF73",'1'&x"EF74",'1'&x"EF75",'1'&x"EF76",'1'&x"EF77",'1'&x"EF78",'1'&x"EF79",'1'&x"EF7A",'1'&x"EF7B",'1'&x"EF7C",'1'&x"EF7D",'1'&x"EF7E",'1'&x"EF7F",
+--'1'&x"EF80",'1'&x"EF81",'1'&x"EF82",'1'&x"EF83",'1'&x"EF84",'1'&x"EF85",'1'&x"EF86",'1'&x"EF87",'1'&x"EF88",'1'&x"EF89",'1'&x"EF8A",'1'&x"EF8B",'1'&x"EF8C",'1'&x"EF8D",'1'&x"EF8E",'1'&x"EF8F",
+--'1'&x"EF90",'1'&x"EF91",'1'&x"EF92",'1'&x"EF93",'1'&x"EF94",'1'&x"EF95",'1'&x"EF96",'1'&x"EF97",'1'&x"EF98",'1'&x"EF99",'1'&x"EF9A",'1'&x"EF9B",'1'&x"EF9C",'1'&x"EF9D",'1'&x"EF9E",'1'&x"EF9F",
+--'1'&x"EFA0",'1'&x"EFA1",'1'&x"EFA2",'1'&x"EFA3",'1'&x"EFA4",'1'&x"EFA5",'1'&x"EFA6",'1'&x"EFA7",'1'&x"EFA8",'1'&x"EFA9",'1'&x"EFAA",'1'&x"EFAB",'1'&x"EFAC",'1'&x"EFAD",'1'&x"EFAE",'1'&x"EFAF",
+--'1'&x"EFB0",'1'&x"EFB1",'1'&x"EFB2",'1'&x"EFB3",'1'&x"EFB4",'1'&x"EFB5",'1'&x"EFB6",'1'&x"EFB7",'1'&x"EFB8",'1'&x"EFB9",'1'&x"EFBA",'1'&x"EFBB",'1'&x"EFBC",'1'&x"EFBD",'1'&x"EFBE",'1'&x"EFBF",
+--'1'&x"EFC0",'1'&x"EFC1",'1'&x"EFC2",'1'&x"EFC3",'1'&x"EFC4",'1'&x"EFC5",'1'&x"EFC6",'1'&x"EFC7",'1'&x"EFC8",'1'&x"EFC9",'1'&x"EFCA",'1'&x"EFCB",'1'&x"EFCC",'1'&x"EFCD",'1'&x"EFCE",'1'&x"EFCF",
+--'1'&x"EFD0",'1'&x"EFD1",'1'&x"EFD2",'1'&x"EFD3",'1'&x"EFD4",'1'&x"EFD5",'1'&x"EFD6",'1'&x"EFD7",'1'&x"EFD8",'1'&x"EFD9",'1'&x"EFDA",'1'&x"EFDB",'1'&x"EFDC",'1'&x"EFDD",'1'&x"EFDE",'1'&x"EFDF",
+--'1'&x"EFE0",'1'&x"EFE1",'1'&x"EFE2",'1'&x"EFE3",'1'&x"EFE4",'1'&x"EFE5",'1'&x"EFE6",'1'&x"EFE7",'1'&x"EFE8",'1'&x"EFE9",'1'&x"EFEA",'1'&x"EFEB",'1'&x"EFEC",'1'&x"EFED",'1'&x"EFEE",'1'&x"EFEF",
+--'1'&x"EFF0",'1'&x"EFF1",'1'&x"EFF2",'1'&x"EFF3",'1'&x"EFF4",'1'&x"EFF5",'1'&x"EFF6",'1'&x"EFF7",'1'&x"EFF8",'1'&x"EFF9",'1'&x"EFFA",'1'&x"EFFB",'1'&x"EFFC",'1'&x"EFFD",'1'&x"EFFE",'1'&x"EFFF",
+--'1'&x"F000",'1'&x"F001",'1'&x"F002",'1'&x"F003",'1'&x"F004",'1'&x"F005",'1'&x"F006",'1'&x"F007",'1'&x"F008",'1'&x"F009",'1'&x"F00A",'1'&x"F00B",'1'&x"F00C",'1'&x"F00D",'1'&x"F00E",'1'&x"F00F",
+--'1'&x"F010",'1'&x"F011",'1'&x"F012",'1'&x"F013",'1'&x"F014",'1'&x"F015",'1'&x"F016",'1'&x"F017",'1'&x"F018",'1'&x"F019",'1'&x"F01A",'1'&x"F01B",'1'&x"F01C",'1'&x"F01D",'1'&x"F01E",'1'&x"F01F",
+--'1'&x"F020",'1'&x"F021",'1'&x"F022",'1'&x"F023",'1'&x"F024",'1'&x"F025",'1'&x"F026",'1'&x"F027",'1'&x"F028",'1'&x"F029",'1'&x"F02A",'1'&x"F02B",'1'&x"F02C",'1'&x"F02D",'1'&x"F02E",'1'&x"F02F",
+--'1'&x"F030",'1'&x"F031",'1'&x"F032",'1'&x"F033",'1'&x"F034",'1'&x"F035",'1'&x"F036",'1'&x"F037",'1'&x"F038",'1'&x"F039",'1'&x"F03A",'1'&x"F03B",'1'&x"F03C",'1'&x"F03D",'1'&x"F03E",'1'&x"F03F",
+--'1'&x"F040",'1'&x"F041",'1'&x"F042",'1'&x"F043",'1'&x"F044",'1'&x"F045",'1'&x"F046",'1'&x"F047",'1'&x"F048",'1'&x"F049",'1'&x"F04A",'1'&x"F04B",'1'&x"F04C",'1'&x"F04D",'1'&x"F04E",'1'&x"F04F",
+--'1'&x"F050",'1'&x"F051",'1'&x"F052",'1'&x"F053",'1'&x"F054",'1'&x"F055",'1'&x"F056",'1'&x"F057",'1'&x"F058",'1'&x"F059",'1'&x"F05A",'1'&x"F05B",'1'&x"F05C",'1'&x"F05D",'1'&x"F05E",'1'&x"F05F",
+--'1'&x"F060",'1'&x"F061",'1'&x"F062",'1'&x"F063",'1'&x"F064",'1'&x"F065",'1'&x"F066",'1'&x"F067",'1'&x"F068",'1'&x"F069",'1'&x"F06A",'1'&x"F06B",'1'&x"F06C",'1'&x"F06D",'1'&x"F06E",'1'&x"F06F",
+--'1'&x"F070",'1'&x"F071",'1'&x"F072",'1'&x"F073",'1'&x"F074",'1'&x"F075",'1'&x"F076",'1'&x"F077",'1'&x"F078",'1'&x"F079",'1'&x"F07A",'1'&x"F07B",'1'&x"F07C",'1'&x"F07D",'1'&x"F07E",'1'&x"F07F",
+--'1'&x"F080",'1'&x"F081",'1'&x"F082",'1'&x"F083",'1'&x"F084",'1'&x"F085",'1'&x"F086",'1'&x"F087",'1'&x"F088",'1'&x"F089",'1'&x"F08A",'1'&x"F08B",'1'&x"F08C",'1'&x"F08D",'1'&x"F08E",'1'&x"F08F",
+--'1'&x"F090",'1'&x"F091",'1'&x"F092",'1'&x"F093",'1'&x"F094",'1'&x"F095",'1'&x"F096",'1'&x"F097",'1'&x"F098",'1'&x"F099",'1'&x"F09A",'1'&x"F09B",'1'&x"F09C",'1'&x"F09D",'1'&x"F09E",'1'&x"F09F",
+--'1'&x"F0A0",'1'&x"F0A1",'1'&x"F0A2",'1'&x"F0A3",'1'&x"F0A4",'1'&x"F0A5",'1'&x"F0A6",'1'&x"F0A7",'1'&x"F0A8",'1'&x"F0A9",'1'&x"F0AA",'1'&x"F0AB",'1'&x"F0AC",'1'&x"F0AD",'1'&x"F0AE",'1'&x"F0AF",
+--'1'&x"F0B0",'1'&x"F0B1",'1'&x"F0B2",'1'&x"F0B3",'1'&x"F0B4",'1'&x"F0B5",'1'&x"F0B6",'1'&x"F0B7",'1'&x"F0B8",'1'&x"F0B9",'1'&x"F0BA",'1'&x"F0BB",'1'&x"F0BC",'1'&x"F0BD",'1'&x"F0BE",'1'&x"F0BF",
+--'1'&x"F0C0",'1'&x"F0C1",'1'&x"F0C2",'1'&x"F0C3",'1'&x"F0C4",'1'&x"F0C5",'1'&x"F0C6",'1'&x"F0C7",'1'&x"F0C8",'1'&x"F0C9",'1'&x"F0CA",'1'&x"F0CB",'1'&x"F0CC",'1'&x"F0CD",'1'&x"F0CE",'1'&x"F0CF",
+--'1'&x"F0D0",'1'&x"F0D1",'1'&x"F0D2",'1'&x"F0D3",'1'&x"F0D4",'1'&x"F0D5",'1'&x"F0D6",'1'&x"F0D7",'1'&x"F0D8",'1'&x"F0D9",'1'&x"F0DA",'1'&x"F0DB",'1'&x"F0DC",'1'&x"F0DD",'1'&x"F0DE",'1'&x"F0DF",
+--'1'&x"F0E0",'1'&x"F0E1",'1'&x"F0E2",'1'&x"F0E3",'1'&x"F0E4",'1'&x"F0E5",'1'&x"F0E6",'1'&x"F0E7",'1'&x"F0E8",'1'&x"F0E9",'1'&x"F0EA",'1'&x"F0EB",'1'&x"F0EC",'1'&x"F0ED",'1'&x"F0EE",'1'&x"F0EF",
+--'1'&x"F0F0",'1'&x"F0F1",'1'&x"F0F2",'1'&x"F0F3",'1'&x"F0F4",'1'&x"F0F5",'1'&x"F0F6",'1'&x"F0F7",'1'&x"F0F8",'1'&x"F0F9",'1'&x"F0FA",'1'&x"F0FB",'1'&x"F0FC",'1'&x"F0FD",'1'&x"F0FE",'1'&x"F0FF",
+--'1'&x"F100",'1'&x"F101",'1'&x"F102",'1'&x"F103",'1'&x"F104",'1'&x"F105",'1'&x"F106",'1'&x"F107",'1'&x"F108",'1'&x"F109",'1'&x"F10A",'1'&x"F10B",'1'&x"F10C",'1'&x"F10D",'1'&x"F10E",'1'&x"F10F",
+--'1'&x"F110",'1'&x"F111",'1'&x"F112",'1'&x"F113",'1'&x"F114",'1'&x"F115",'1'&x"F116",'1'&x"F117",'1'&x"F118",'1'&x"F119",'1'&x"F11A",'1'&x"F11B",'1'&x"F11C",'1'&x"F11D",'1'&x"F11E",'1'&x"F11F",
+--'1'&x"F120",'1'&x"F121",'1'&x"F122",'1'&x"F123",'1'&x"F124",'1'&x"F125",'1'&x"F126",'1'&x"F127",'1'&x"F128",'1'&x"F129",'1'&x"F12A",'1'&x"F12B",'1'&x"F12C",'1'&x"F12D",'1'&x"F12E",'1'&x"F12F",
+--'1'&x"F130",'1'&x"F131",'1'&x"F132",'1'&x"F133",'1'&x"F134",'1'&x"F135",'1'&x"F136",'1'&x"F137",'1'&x"F138",'1'&x"F139",'1'&x"F13A",'1'&x"F13B",'1'&x"F13C",'1'&x"F13D",'1'&x"F13E",'1'&x"F13F",
+--'1'&x"F140",'1'&x"F141",'1'&x"F142",'1'&x"F143",'1'&x"F144",'1'&x"F145",'1'&x"F146",'1'&x"F147",'1'&x"F148",'1'&x"F149",'1'&x"F14A",'1'&x"F14B",'1'&x"F14C",'1'&x"F14D",'1'&x"F14E",'1'&x"F14F",
+--'1'&x"F150",'1'&x"F151",'1'&x"F152",'1'&x"F153",'1'&x"F154",'1'&x"F155",'1'&x"F156",'1'&x"F157",'1'&x"F158",'1'&x"F159",'1'&x"F15A",'1'&x"F15B",'1'&x"F15C",'1'&x"F15D",'1'&x"F15E",'1'&x"F15F",
+--'1'&x"F160",'1'&x"F161",'1'&x"F162",'1'&x"F163",'1'&x"F164",'1'&x"F165",'1'&x"F166",'1'&x"F167",'1'&x"F168",'1'&x"F169",'1'&x"F16A",'1'&x"F16B",'1'&x"F16C",'1'&x"F16D",'1'&x"F16E",'1'&x"F16F",
+--'1'&x"F170",'1'&x"F171",'1'&x"F172",'1'&x"F173",'1'&x"F174",'1'&x"F175",'1'&x"F176",'1'&x"F177",'1'&x"F178",'1'&x"F179",'1'&x"F17A",'1'&x"F17B",'1'&x"F17C",'1'&x"F17D",'1'&x"F17E",'1'&x"F17F",
+--'1'&x"F180",'1'&x"F181",'1'&x"F182",'1'&x"F183",'1'&x"F184",'1'&x"F185",'1'&x"F186",'1'&x"F187",'1'&x"F188",'1'&x"F189",'1'&x"F18A",'1'&x"F18B",'1'&x"F18C",'1'&x"F18D",'1'&x"F18E",'1'&x"F18F",
+--'1'&x"F190",'1'&x"F191",'1'&x"F192",'1'&x"F193",'1'&x"F194",'1'&x"F195",'1'&x"F196",'1'&x"F197",'1'&x"F198",'1'&x"F199",'1'&x"F19A",'1'&x"F19B",'1'&x"F19C",'1'&x"F19D",'1'&x"F19E",'1'&x"F19F",
+--'1'&x"F1A0",'1'&x"F1A1",'1'&x"F1A2",'1'&x"F1A3",'1'&x"F1A4",'1'&x"F1A5",'1'&x"F1A6",'1'&x"F1A7",'1'&x"F1A8",'1'&x"F1A9",'1'&x"F1AA",'1'&x"F1AB",'1'&x"F1AC",'1'&x"F1AD",'1'&x"F1AE",'1'&x"F1AF",
+--'1'&x"F1B0",'1'&x"F1B1",'1'&x"F1B2",'1'&x"F1B3",'1'&x"F1B4",'1'&x"F1B5",'1'&x"F1B6",'1'&x"F1B7",'1'&x"F1B8",'1'&x"F1B9",'1'&x"F1BA",'1'&x"F1BB",'1'&x"F1BC",'1'&x"F1BD",'1'&x"F1BE",'1'&x"F1BF",
+--'1'&x"F1C0",'1'&x"F1C1",'1'&x"F1C2",'1'&x"F1C3",'1'&x"F1C4",'1'&x"F1C5",'1'&x"F1C6",'1'&x"F1C7",'1'&x"F1C8",'1'&x"F1C9",'1'&x"F1CA",'1'&x"F1CB",'1'&x"F1CC",'1'&x"F1CD",'1'&x"F1CE",'1'&x"F1CF",
+--'1'&x"F1D0",'1'&x"F1D1",'1'&x"F1D2",'1'&x"F1D3",'1'&x"F1D4",'1'&x"F1D5",'1'&x"F1D6",'1'&x"F1D7",'1'&x"F1D8",'1'&x"F1D9",'1'&x"F1DA",'1'&x"F1DB",'1'&x"F1DC",'1'&x"F1DD",'1'&x"F1DE",'1'&x"F1DF",
+--'1'&x"F1E0",'1'&x"F1E1",'1'&x"F1E2",'1'&x"F1E3",'1'&x"F1E4",'1'&x"F1E5",'1'&x"F1E6",'1'&x"F1E7",'1'&x"F1E8",'1'&x"F1E9",'1'&x"F1EA",'1'&x"F1EB",'1'&x"F1EC",'1'&x"F1ED",'1'&x"F1EE",'1'&x"F1EF",
+--'1'&x"F1F0",'1'&x"F1F1",'1'&x"F1F2",'1'&x"F1F3",'1'&x"F1F4",'1'&x"F1F5",'1'&x"F1F6",'1'&x"F1F7",'1'&x"F1F8",'1'&x"F1F9",'1'&x"F1FA",'1'&x"F1FB",'1'&x"F1FC",'1'&x"F1FD",'1'&x"F1FE",'1'&x"F1FF",
+--'1'&x"F200",'1'&x"F201",'1'&x"F202",'1'&x"F203",'1'&x"F204",'1'&x"F205",'1'&x"F206",'1'&x"F207",'1'&x"F208",'1'&x"F209",'1'&x"F20A",'1'&x"F20B",'1'&x"F20C",'1'&x"F20D",'1'&x"F20E",'1'&x"F20F",
+--'1'&x"F210",'1'&x"F211",'1'&x"F212",'1'&x"F213",'1'&x"F214",'1'&x"F215",'1'&x"F216",'1'&x"F217",'1'&x"F218",'1'&x"F219",'1'&x"F21A",'1'&x"F21B",'1'&x"F21C",'1'&x"F21D",'1'&x"F21E",'1'&x"F21F",
+--'1'&x"F220",'1'&x"F221",'1'&x"F222",'1'&x"F223",'1'&x"F224",'1'&x"F225",'1'&x"F226",'1'&x"F227",'1'&x"F228",'1'&x"F229",'1'&x"F22A",'1'&x"F22B",'1'&x"F22C",'1'&x"F22D",'1'&x"F22E",'1'&x"F22F",
+--'1'&x"F230",'1'&x"F231",'1'&x"F232",'1'&x"F233",'1'&x"F234",'1'&x"F235",'1'&x"F236",'1'&x"F237",'1'&x"F238",'1'&x"F239",'1'&x"F23A",'1'&x"F23B",'1'&x"F23C",'1'&x"F23D",'1'&x"F23E",'1'&x"F23F",
+--'1'&x"F240",'1'&x"F241",'1'&x"F242",'1'&x"F243",'1'&x"F244",'1'&x"F245",'1'&x"F246",'1'&x"F247",'1'&x"F248",'1'&x"F249",'1'&x"F24A",'1'&x"F24B",'1'&x"F24C",'1'&x"F24D",'1'&x"F24E",'1'&x"F24F",
+--'1'&x"F250",'1'&x"F251",'1'&x"F252",'1'&x"F253",'1'&x"F254",'1'&x"F255",'1'&x"F256",'1'&x"F257",'1'&x"F258",'1'&x"F259",'1'&x"F25A",'1'&x"F25B",'1'&x"F25C",'1'&x"F25D",'1'&x"F25E",'1'&x"F25F",
+--'1'&x"F260",'1'&x"F261",'1'&x"F262",'1'&x"F263",'1'&x"F264",'1'&x"F265",'1'&x"F266",'1'&x"F267",'1'&x"F268",'1'&x"F269",'1'&x"F26A",'1'&x"F26B",'1'&x"F26C",'1'&x"F26D",'1'&x"F26E",'1'&x"F26F",
+--'1'&x"F270",'1'&x"F271",'1'&x"F272",'1'&x"F273",'1'&x"F274",'1'&x"F275",'1'&x"F276",'1'&x"F277",'1'&x"F278",'1'&x"F279",'1'&x"F27A",'1'&x"F27B",'1'&x"F27C",'1'&x"F27D",'1'&x"F27E",'1'&x"F27F",
+--'1'&x"F280",'1'&x"F281",'1'&x"F282",'1'&x"F283",'1'&x"F284",'1'&x"F285",'1'&x"F286",'1'&x"F287",'1'&x"F288",'1'&x"F289",'1'&x"F28A",'1'&x"F28B",'1'&x"F28C",'1'&x"F28D",'1'&x"F28E",'1'&x"F28F",
+--'1'&x"F290",'1'&x"F291",'1'&x"F292",'1'&x"F293",'1'&x"F294",'1'&x"F295",'1'&x"F296",'1'&x"F297",'1'&x"F298",'1'&x"F299",'1'&x"F29A",'1'&x"F29B",'1'&x"F29C",'1'&x"F29D",'1'&x"F29E",'1'&x"F29F",
+--'1'&x"F2A0",'1'&x"F2A1",'1'&x"F2A2",'1'&x"F2A3",'1'&x"F2A4",'1'&x"F2A5",'1'&x"F2A6",'1'&x"F2A7",'1'&x"F2A8",'1'&x"F2A9",'1'&x"F2AA",'1'&x"F2AB",'1'&x"F2AC",'1'&x"F2AD",'1'&x"F2AE",'1'&x"F2AF",
+--'1'&x"F2B0",'1'&x"F2B1",'1'&x"F2B2",'1'&x"F2B3",'1'&x"F2B4",'1'&x"F2B5",'1'&x"F2B6",'1'&x"F2B7",'1'&x"F2B8",'1'&x"F2B9",'1'&x"F2BA",'1'&x"F2BB",'1'&x"F2BC",'1'&x"F2BD",'1'&x"F2BE",'1'&x"F2BF",
+--'1'&x"F2C0",'1'&x"F2C1",'1'&x"F2C2",'1'&x"F2C3",'1'&x"F2C4",'1'&x"F2C5",'1'&x"F2C6",'1'&x"F2C7",'1'&x"F2C8",'1'&x"F2C9",'1'&x"F2CA",'1'&x"F2CB",'1'&x"F2CC",'1'&x"F2CD",'1'&x"F2CE",'1'&x"F2CF",
+--'1'&x"F2D0",'1'&x"F2D1",'1'&x"F2D2",'1'&x"F2D3",'1'&x"F2D4",'1'&x"F2D5",'1'&x"F2D6",'1'&x"F2D7",'1'&x"F2D8",'1'&x"F2D9",'1'&x"F2DA",'1'&x"F2DB",'1'&x"F2DC",'1'&x"F2DD",'1'&x"F2DE",'1'&x"F2DF",
+--'1'&x"F2E0",'1'&x"F2E1",'1'&x"F2E2",'1'&x"F2E3",'1'&x"F2E4",'1'&x"F2E5",'1'&x"F2E6",'1'&x"F2E7",'1'&x"F2E8",'1'&x"F2E9",'1'&x"F2EA",'1'&x"F2EB",'1'&x"F2EC",'1'&x"F2ED",'1'&x"F2EE",'1'&x"F2EF",
+--'1'&x"F2F0",'1'&x"F2F1",'1'&x"F2F2",'1'&x"F2F3",'1'&x"F2F4",'1'&x"F2F5",'1'&x"F2F6",'1'&x"F2F7",'1'&x"F2F8",'1'&x"F2F9",'1'&x"F2FA",'1'&x"F2FB",'1'&x"F2FC",'1'&x"F2FD",'1'&x"F2FE",'1'&x"F2FF",
+--'1'&x"F300",'1'&x"F301",'1'&x"F302",'1'&x"F303",'1'&x"F304",'1'&x"F305",'1'&x"F306",'1'&x"F307",'1'&x"F308",'1'&x"F309",'1'&x"F30A",'1'&x"F30B",'1'&x"F30C",'1'&x"F30D",'1'&x"F30E",'1'&x"F30F",
+--'1'&x"F310",'1'&x"F311",'1'&x"F312",'1'&x"F313",'1'&x"F314",'1'&x"F315",'1'&x"F316",'1'&x"F317",'1'&x"F318",'1'&x"F319",'1'&x"F31A",'1'&x"F31B",'1'&x"F31C",'1'&x"F31D",'1'&x"F31E",'1'&x"F31F",
+--'1'&x"F320",'1'&x"F321",'1'&x"F322",'1'&x"F323",'1'&x"F324",'1'&x"F325",'1'&x"F326",'1'&x"F327",'1'&x"F328",'1'&x"F329",'1'&x"F32A",'1'&x"F32B",'1'&x"F32C",'1'&x"F32D",'1'&x"F32E",'1'&x"F32F",
+--'1'&x"F330",'1'&x"F331",'1'&x"F332",'1'&x"F333",'1'&x"F334",'1'&x"F335",'1'&x"F336",'1'&x"F337",'1'&x"F338",'1'&x"F339",'1'&x"F33A",'1'&x"F33B",'1'&x"F33C",'1'&x"F33D",'1'&x"F33E",'1'&x"F33F",
+--'1'&x"F340",'1'&x"F341",'1'&x"F342",'1'&x"F343",'1'&x"F344",'1'&x"F345",'1'&x"F346",'1'&x"F347",'1'&x"F348",'1'&x"F349",'1'&x"F34A",'1'&x"F34B",'1'&x"F34C",'1'&x"F34D",'1'&x"F34E",'1'&x"F34F",
+--'1'&x"F350",'1'&x"F351",'1'&x"F352",'1'&x"F353",'1'&x"F354",'1'&x"F355",'1'&x"F356",'1'&x"F357",'1'&x"F358",'1'&x"F359",'1'&x"F35A",'1'&x"F35B",'1'&x"F35C",'1'&x"F35D",'1'&x"F35E",'1'&x"F35F",
+--'1'&x"F360",'1'&x"F361",'1'&x"F362",'1'&x"F363",'1'&x"F364",'1'&x"F365",'1'&x"F366",'1'&x"F367",'1'&x"F368",'1'&x"F369",'1'&x"F36A",'1'&x"F36B",'1'&x"F36C",'1'&x"F36D",'1'&x"F36E",'1'&x"F36F",
+--'1'&x"F370",'1'&x"F371",'1'&x"F372",'1'&x"F373",'1'&x"F374",'1'&x"F375",'1'&x"F376",'1'&x"F377",'1'&x"F378",'1'&x"F379",'1'&x"F37A",'1'&x"F37B",'1'&x"F37C",'1'&x"F37D",'1'&x"F37E",'1'&x"F37F",
+--'1'&x"F380",'1'&x"F381",'1'&x"F382",'1'&x"F383",'1'&x"F384",'1'&x"F385",'1'&x"F386",'1'&x"F387",'1'&x"F388",'1'&x"F389",'1'&x"F38A",'1'&x"F38B",'1'&x"F38C",'1'&x"F38D",'1'&x"F38E",'1'&x"F38F",
+--'1'&x"F390",'1'&x"F391",'1'&x"F392",'1'&x"F393",'1'&x"F394",'1'&x"F395",'1'&x"F396",'1'&x"F397",'1'&x"F398",'1'&x"F399",'1'&x"F39A",'1'&x"F39B",'1'&x"F39C",'1'&x"F39D",'1'&x"F39E",'1'&x"F39F",
+--'1'&x"F3A0",'1'&x"F3A1",'1'&x"F3A2",'1'&x"F3A3",'1'&x"F3A4",'1'&x"F3A5",'1'&x"F3A6",'1'&x"F3A7",'1'&x"F3A8",'1'&x"F3A9",'1'&x"F3AA",'1'&x"F3AB",'1'&x"F3AC",'1'&x"F3AD",'1'&x"F3AE",'1'&x"F3AF",
+--'1'&x"F3B0",'1'&x"F3B1",'1'&x"F3B2",'1'&x"F3B3",'1'&x"F3B4",'1'&x"F3B5",'1'&x"F3B6",'1'&x"F3B7",'1'&x"F3B8",'1'&x"F3B9",'1'&x"F3BA",'1'&x"F3BB",'1'&x"F3BC",'1'&x"F3BD",'1'&x"F3BE",'1'&x"F3BF",
+--'1'&x"F3C0",'1'&x"F3C1",'1'&x"F3C2",'1'&x"F3C3",'1'&x"F3C4",'1'&x"F3C5",'1'&x"F3C6",'1'&x"F3C7",'1'&x"F3C8",'1'&x"F3C9",'1'&x"F3CA",'1'&x"F3CB",'1'&x"F3CC",'1'&x"F3CD",'1'&x"F3CE",'1'&x"F3CF",
+--'1'&x"F3D0",'1'&x"F3D1",'1'&x"F3D2",'1'&x"F3D3",'1'&x"F3D4",'1'&x"F3D5",'1'&x"F3D6",'1'&x"F3D7",'1'&x"F3D8",'1'&x"F3D9",'1'&x"F3DA",'1'&x"F3DB",'1'&x"F3DC",'1'&x"F3DD",'1'&x"F3DE",'1'&x"F3DF",
+--'1'&x"F3E0",'1'&x"F3E1",'1'&x"F3E2",'1'&x"F3E3",'1'&x"F3E4",'1'&x"F3E5",'1'&x"F3E6",'1'&x"F3E7",'1'&x"F3E8",'1'&x"F3E9",'1'&x"F3EA",'1'&x"F3EB",'1'&x"F3EC",'1'&x"F3ED",'1'&x"F3EE",'1'&x"F3EF",
+--'1'&x"F3F0",'1'&x"F3F1",'1'&x"F3F2",'1'&x"F3F3",'1'&x"F3F4",'1'&x"F3F5",'1'&x"F3F6",'1'&x"F3F7",'1'&x"F3F8",'1'&x"F3F9",'1'&x"F3FA",'1'&x"F3FB",'1'&x"F3FC",'1'&x"F3FD",'1'&x"F3FE",'1'&x"F3FF",
+--'1'&x"F400",'1'&x"F401",'1'&x"F402",'1'&x"F403",'1'&x"F404",'1'&x"F405",'1'&x"F406",'1'&x"F407",'1'&x"F408",'1'&x"F409",'1'&x"F40A",'1'&x"F40B",'1'&x"F40C",'1'&x"F40D",'1'&x"F40E",'1'&x"F40F",
+--'1'&x"F410",'1'&x"F411",'1'&x"F412",'1'&x"F413",'1'&x"F414",'1'&x"F415",'1'&x"F416",'1'&x"F417",'1'&x"F418",'1'&x"F419",'1'&x"F41A",'1'&x"F41B",'1'&x"F41C",'1'&x"F41D",'1'&x"F41E",'1'&x"F41F",
+--'1'&x"F420",'1'&x"F421",'1'&x"F422",'1'&x"F423",'1'&x"F424",'1'&x"F425",'1'&x"F426",'1'&x"F427",'1'&x"F428",'1'&x"F429",'1'&x"F42A",'1'&x"F42B",'1'&x"F42C",'1'&x"F42D",'1'&x"F42E",'1'&x"F42F",
+--'1'&x"F430",'1'&x"F431",'1'&x"F432",'1'&x"F433",'1'&x"F434",'1'&x"F435",'1'&x"F436",'1'&x"F437",'1'&x"F438",'1'&x"F439",'1'&x"F43A",'1'&x"F43B",'1'&x"F43C",'1'&x"F43D",'1'&x"F43E",'1'&x"F43F",
+--'1'&x"F440",'1'&x"F441",'1'&x"F442",'1'&x"F443",'1'&x"F444",'1'&x"F445",'1'&x"F446",'1'&x"F447",'1'&x"F448",'1'&x"F449",'1'&x"F44A",'1'&x"F44B",'1'&x"F44C",'1'&x"F44D",'1'&x"F44E",'1'&x"F44F",
+--'1'&x"F450",'1'&x"F451",'1'&x"F452",'1'&x"F453",'1'&x"F454",'1'&x"F455",'1'&x"F456",'1'&x"F457",'1'&x"F458",'1'&x"F459",'1'&x"F45A",'1'&x"F45B",'1'&x"F45C",'1'&x"F45D",'1'&x"F45E",'1'&x"F45F",
+--'1'&x"F460",'1'&x"F461",'1'&x"F462",'1'&x"F463",'1'&x"F464",'1'&x"F465",'1'&x"F466",'1'&x"F467",'1'&x"F468",'1'&x"F469",'1'&x"F46A",'1'&x"F46B",'1'&x"F46C",'1'&x"F46D",'1'&x"F46E",'1'&x"F46F",
+--'1'&x"F470",'1'&x"F471",'1'&x"F472",'1'&x"F473",'1'&x"F474",'1'&x"F475",'1'&x"F476",'1'&x"F477",'1'&x"F478",'1'&x"F479",'1'&x"F47A",'1'&x"F47B",'1'&x"F47C",'1'&x"F47D",'1'&x"F47E",'1'&x"F47F",
+--'1'&x"F480",'1'&x"F481",'1'&x"F482",'1'&x"F483",'1'&x"F484",'1'&x"F485",'1'&x"F486",'1'&x"F487",'1'&x"F488",'1'&x"F489",'1'&x"F48A",'1'&x"F48B",'1'&x"F48C",'1'&x"F48D",'1'&x"F48E",'1'&x"F48F",
+--'1'&x"F490",'1'&x"F491",'1'&x"F492",'1'&x"F493",'1'&x"F494",'1'&x"F495",'1'&x"F496",'1'&x"F497",'1'&x"F498",'1'&x"F499",'1'&x"F49A",'1'&x"F49B",'1'&x"F49C",'1'&x"F49D",'1'&x"F49E",'1'&x"F49F",
+--'1'&x"F4A0",'1'&x"F4A1",'1'&x"F4A2",'1'&x"F4A3",'1'&x"F4A4",'1'&x"F4A5",'1'&x"F4A6",'1'&x"F4A7",'1'&x"F4A8",'1'&x"F4A9",'1'&x"F4AA",'1'&x"F4AB",'1'&x"F4AC",'1'&x"F4AD",'1'&x"F4AE",'1'&x"F4AF",
+--'1'&x"F4B0",'1'&x"F4B1",'1'&x"F4B2",'1'&x"F4B3",'1'&x"F4B4",'1'&x"F4B5",'1'&x"F4B6",'1'&x"F4B7",'1'&x"F4B8",'1'&x"F4B9",'1'&x"F4BA",'1'&x"F4BB",'1'&x"F4BC",'1'&x"F4BD",'1'&x"F4BE",'1'&x"F4BF",
+--'1'&x"F4C0",'1'&x"F4C1",'1'&x"F4C2",'1'&x"F4C3",'1'&x"F4C4",'1'&x"F4C5",'1'&x"F4C6",'1'&x"F4C7",'1'&x"F4C8",'1'&x"F4C9",'1'&x"F4CA",'1'&x"F4CB",'1'&x"F4CC",'1'&x"F4CD",'1'&x"F4CE",'1'&x"F4CF",
+--'1'&x"F4D0",'1'&x"F4D1",'1'&x"F4D2",'1'&x"F4D3",'1'&x"F4D4",'1'&x"F4D5",'1'&x"F4D6",'1'&x"F4D7",'1'&x"F4D8",'1'&x"F4D9",'1'&x"F4DA",'1'&x"F4DB",'1'&x"F4DC",'1'&x"F4DD",'1'&x"F4DE",'1'&x"F4DF",
+--'1'&x"F4E0",'1'&x"F4E1",'1'&x"F4E2",'1'&x"F4E3",'1'&x"F4E4",'1'&x"F4E5",'1'&x"F4E6",'1'&x"F4E7",'1'&x"F4E8",'1'&x"F4E9",'1'&x"F4EA",'1'&x"F4EB",'1'&x"F4EC",'1'&x"F4ED",'1'&x"F4EE",'1'&x"F4EF",
+--'1'&x"F4F0",'1'&x"F4F1",'1'&x"F4F2",'1'&x"F4F3",'1'&x"F4F4",'1'&x"F4F5",'1'&x"F4F6",'1'&x"F4F7",'1'&x"F4F8",'1'&x"F4F9",'1'&x"F4FA",'1'&x"F4FB",'1'&x"F4FC",'1'&x"F4FD",'1'&x"F4FE",'1'&x"F4FF",
+--'1'&x"F500",'1'&x"F501",'1'&x"F502",'1'&x"F503",'1'&x"F504",'1'&x"F505",'1'&x"F506",'1'&x"F507",'1'&x"F508",'1'&x"F509",'1'&x"F50A",'1'&x"F50B",'1'&x"F50C",'1'&x"F50D",'1'&x"F50E",'1'&x"F50F",
+--'1'&x"F510",'1'&x"F511",'1'&x"F512",'1'&x"F513",'1'&x"F514",'1'&x"F515",'1'&x"F516",'1'&x"F517",'1'&x"F518",'1'&x"F519",'1'&x"F51A",'1'&x"F51B",'1'&x"F51C",'1'&x"F51D",'1'&x"F51E",'1'&x"F51F",
+--'1'&x"F520",'1'&x"F521",'1'&x"F522",'1'&x"F523",'1'&x"F524",'1'&x"F525",'1'&x"F526",'1'&x"F527",'1'&x"F528",'1'&x"F529",'1'&x"F52A",'1'&x"F52B",'1'&x"F52C",'1'&x"F52D",'1'&x"F52E",'1'&x"F52F",
+--'1'&x"F530",'1'&x"F531",'1'&x"F532",'1'&x"F533",'1'&x"F534",'1'&x"F535",'1'&x"F536",'1'&x"F537",'1'&x"F538",'1'&x"F539",'1'&x"F53A",'1'&x"F53B",'1'&x"F53C",'1'&x"F53D",'1'&x"F53E",'1'&x"F53F",
+--'1'&x"F540",'1'&x"F541",'1'&x"F542",'1'&x"F543",'1'&x"F544",'1'&x"F545",'1'&x"F546",'1'&x"F547",'1'&x"F548",'1'&x"F549",'1'&x"F54A",'1'&x"F54B",'1'&x"F54C",'1'&x"F54D",'1'&x"F54E",'1'&x"F54F",
+--'1'&x"F550",'1'&x"F551",'1'&x"F552",'1'&x"F553",'1'&x"F554",'1'&x"F555",'1'&x"F556",'1'&x"F557",'1'&x"F558",'1'&x"F559",'1'&x"F55A",'1'&x"F55B",'1'&x"F55C",'1'&x"F55D",'1'&x"F55E",'1'&x"F55F",
+--'1'&x"F560",'1'&x"F561",'1'&x"F562",'1'&x"F563",'1'&x"F564",'1'&x"F565",'1'&x"F566",'1'&x"F567",'1'&x"F568",'1'&x"F569",'1'&x"F56A",'1'&x"F56B",'1'&x"F56C",'1'&x"F56D",'1'&x"F56E",'1'&x"F56F",
+--'1'&x"F570",'1'&x"F571",'1'&x"F572",'1'&x"F573",'1'&x"F574",'1'&x"F575",'1'&x"F576",'1'&x"F577",'1'&x"F578",'1'&x"F579",'1'&x"F57A",'1'&x"F57B",'1'&x"F57C",'1'&x"F57D",'1'&x"F57E",'1'&x"F57F",
+--'1'&x"F580",'1'&x"F581",'1'&x"F582",'1'&x"F583",'1'&x"F584",'1'&x"F585",'1'&x"F586",'1'&x"F587",'1'&x"F588",'1'&x"F589",'1'&x"F58A",'1'&x"F58B",'1'&x"F58C",'1'&x"F58D",'1'&x"F58E",'1'&x"F58F",
+--'1'&x"F590",'1'&x"F591",'1'&x"F592",'1'&x"F593",'1'&x"F594",'1'&x"F595",'1'&x"F596",'1'&x"F597",'1'&x"F598",'1'&x"F599",'1'&x"F59A",'1'&x"F59B",'1'&x"F59C",'1'&x"F59D",'1'&x"F59E",'1'&x"F59F",
+--'1'&x"F5A0",'1'&x"F5A1",'1'&x"F5A2",'1'&x"F5A3",'1'&x"F5A4",'1'&x"F5A5",'1'&x"F5A6",'1'&x"F5A7",'1'&x"F5A8",'1'&x"F5A9",'1'&x"F5AA",'1'&x"F5AB",'1'&x"F5AC",'1'&x"F5AD",'1'&x"F5AE",'1'&x"F5AF",
+--'1'&x"F5B0",'1'&x"F5B1",'1'&x"F5B2",'1'&x"F5B3",'1'&x"F5B4",'1'&x"F5B5",'1'&x"F5B6",'1'&x"F5B7",'1'&x"F5B8",'1'&x"F5B9",'1'&x"F5BA",'1'&x"F5BB",'1'&x"F5BC",'1'&x"F5BD",'1'&x"F5BE",'1'&x"F5BF",
+--'1'&x"F5C0",'1'&x"F5C1",'1'&x"F5C2",'1'&x"F5C3",'1'&x"F5C4",'1'&x"F5C5",'1'&x"F5C6",'1'&x"F5C7",'1'&x"F5C8",'1'&x"F5C9",'1'&x"F5CA",'1'&x"F5CB",'1'&x"F5CC",'1'&x"F5CD",'1'&x"F5CE",'1'&x"F5CF",
+--'1'&x"F5D0",'1'&x"F5D1",'1'&x"F5D2",'1'&x"F5D3",'1'&x"F5D4",'1'&x"F5D5",'1'&x"F5D6",'1'&x"F5D7",'1'&x"F5D8",'1'&x"F5D9",'1'&x"F5DA",'1'&x"F5DB",'1'&x"F5DC",'1'&x"F5DD",'1'&x"F5DE",'1'&x"F5DF",
+--'1'&x"F5E0",'1'&x"F5E1",'1'&x"F5E2",'1'&x"F5E3",'1'&x"F5E4",'1'&x"F5E5",'1'&x"F5E6",'1'&x"F5E7",'1'&x"F5E8",'1'&x"F5E9",'1'&x"F5EA",'1'&x"F5EB",'1'&x"F5EC",'1'&x"F5ED",'1'&x"F5EE",'1'&x"F5EF",
+--'1'&x"F5F0",'1'&x"F5F1",'1'&x"F5F2",'1'&x"F5F3",'1'&x"F5F4",'1'&x"F5F5",'1'&x"F5F6",'1'&x"F5F7",'1'&x"F5F8",'1'&x"F5F9",'1'&x"F5FA",'1'&x"F5FB",'1'&x"F5FC",'1'&x"F5FD",'1'&x"F5FE",'1'&x"F5FF",
+--'1'&x"F600",'1'&x"F601",'1'&x"F602",'1'&x"F603",'1'&x"F604",'1'&x"F605",'1'&x"F606",'1'&x"F607",'1'&x"F608",'1'&x"F609",'1'&x"F60A",'1'&x"F60B",'1'&x"F60C",'1'&x"F60D",'1'&x"F60E",'1'&x"F60F",
+--'1'&x"F610",'1'&x"F611",'1'&x"F612",'1'&x"F613",'1'&x"F614",'1'&x"F615",'1'&x"F616",'1'&x"F617",'1'&x"F618",'1'&x"F619",'1'&x"F61A",'1'&x"F61B",'1'&x"F61C",'1'&x"F61D",'1'&x"F61E",'1'&x"F61F",
+--'1'&x"F620",'1'&x"F621",'1'&x"F622",'1'&x"F623",'1'&x"F624",'1'&x"F625",'1'&x"F626",'1'&x"F627",'1'&x"F628",'1'&x"F629",'1'&x"F62A",'1'&x"F62B",'1'&x"F62C",'1'&x"F62D",'1'&x"F62E",'1'&x"F62F",
+--'1'&x"F630",'1'&x"F631",'1'&x"F632",'1'&x"F633",'1'&x"F634",'1'&x"F635",'1'&x"F636",'1'&x"F637",'1'&x"F638",'1'&x"F639",'1'&x"F63A",'1'&x"F63B",'1'&x"F63C",'1'&x"F63D",'1'&x"F63E",'1'&x"F63F",
+--'1'&x"F640",'1'&x"F641",'1'&x"F642",'1'&x"F643",'1'&x"F644",'1'&x"F645",'1'&x"F646",'1'&x"F647",'1'&x"F648",'1'&x"F649",'1'&x"F64A",'1'&x"F64B",'1'&x"F64C",'1'&x"F64D",'1'&x"F64E",'1'&x"F64F",
+--'1'&x"F650",'1'&x"F651",'1'&x"F652",'1'&x"F653",'1'&x"F654",'1'&x"F655",'1'&x"F656",'1'&x"F657",'1'&x"F658",'1'&x"F659",'1'&x"F65A",'1'&x"F65B",'1'&x"F65C",'1'&x"F65D",'1'&x"F65E",'1'&x"F65F",
+--'1'&x"F660",'1'&x"F661",'1'&x"F662",'1'&x"F663",'1'&x"F664",'1'&x"F665",'1'&x"F666",'1'&x"F667",'1'&x"F668",'1'&x"F669",'1'&x"F66A",'1'&x"F66B",'1'&x"F66C",'1'&x"F66D",'1'&x"F66E",'1'&x"F66F",
+--'1'&x"F670",'1'&x"F671",'1'&x"F672",'1'&x"F673",'1'&x"F674",'1'&x"F675",'1'&x"F676",'1'&x"F677",'1'&x"F678",'1'&x"F679",'1'&x"F67A",'1'&x"F67B",'1'&x"F67C",'1'&x"F67D",'1'&x"F67E",'1'&x"F67F",
+--'1'&x"F680",'1'&x"F681",'1'&x"F682",'1'&x"F683",'1'&x"F684",'1'&x"F685",'1'&x"F686",'1'&x"F687",'1'&x"F688",'1'&x"F689",'1'&x"F68A",'1'&x"F68B",'1'&x"F68C",'1'&x"F68D",'1'&x"F68E",'1'&x"F68F",
+--'1'&x"F690",'1'&x"F691",'1'&x"F692",'1'&x"F693",'1'&x"F694",'1'&x"F695",'1'&x"F696",'1'&x"F697",'1'&x"F698",'1'&x"F699",'1'&x"F69A",'1'&x"F69B",'1'&x"F69C",'1'&x"F69D",'1'&x"F69E",'1'&x"F69F",
+--'1'&x"F6A0",'1'&x"F6A1",'1'&x"F6A2",'1'&x"F6A3",'1'&x"F6A4",'1'&x"F6A5",'1'&x"F6A6",'1'&x"F6A7",'1'&x"F6A8",'1'&x"F6A9",'1'&x"F6AA",'1'&x"F6AB",'1'&x"F6AC",'1'&x"F6AD",'1'&x"F6AE",'1'&x"F6AF",
+--'1'&x"F6B0",'1'&x"F6B1",'1'&x"F6B2",'1'&x"F6B3",'1'&x"F6B4",'1'&x"F6B5",'1'&x"F6B6",'1'&x"F6B7",'1'&x"F6B8",'1'&x"F6B9",'1'&x"F6BA",'1'&x"F6BB",'1'&x"F6BC",'1'&x"F6BD",'1'&x"F6BE",'1'&x"F6BF",
+--'1'&x"F6C0",'1'&x"F6C1",'1'&x"F6C2",'1'&x"F6C3",'1'&x"F6C4",'1'&x"F6C5",'1'&x"F6C6",'1'&x"F6C7",'1'&x"F6C8",'1'&x"F6C9",'1'&x"F6CA",'1'&x"F6CB",'1'&x"F6CC",'1'&x"F6CD",'1'&x"F6CE",'1'&x"F6CF",
+--'1'&x"F6D0",'1'&x"F6D1",'1'&x"F6D2",'1'&x"F6D3",'1'&x"F6D4",'1'&x"F6D5",'1'&x"F6D6",'1'&x"F6D7",'1'&x"F6D8",'1'&x"F6D9",'1'&x"F6DA",'1'&x"F6DB",'1'&x"F6DC",'1'&x"F6DD",'1'&x"F6DE",'1'&x"F6DF",
+--'1'&x"F6E0",'1'&x"F6E1",'1'&x"F6E2",'1'&x"F6E3",'1'&x"F6E4",'1'&x"F6E5",'1'&x"F6E6",'1'&x"F6E7",'1'&x"F6E8",'1'&x"F6E9",'1'&x"F6EA",'1'&x"F6EB",'1'&x"F6EC",'1'&x"F6ED",'1'&x"F6EE",'1'&x"F6EF",
+--'1'&x"F6F0",'1'&x"F6F1",'1'&x"F6F2",'1'&x"F6F3",'1'&x"F6F4",'1'&x"F6F5",'1'&x"F6F6",'1'&x"F6F7",'1'&x"F6F8",'1'&x"F6F9",'1'&x"F6FA",'1'&x"F6FB",'1'&x"F6FC",'1'&x"F6FD",'1'&x"F6FE",'1'&x"F6FF",
+--'1'&x"F700",'1'&x"F701",'1'&x"F702",'1'&x"F703",'1'&x"F704",'1'&x"F705",'1'&x"F706",'1'&x"F707",'1'&x"F708",'1'&x"F709",'1'&x"F70A",'1'&x"F70B",'1'&x"F70C",'1'&x"F70D",'1'&x"F70E",'1'&x"F70F",
+--'1'&x"F710",'1'&x"F711",'1'&x"F712",'1'&x"F713",'1'&x"F714",'1'&x"F715",'1'&x"F716",'1'&x"F717",'1'&x"F718",'1'&x"F719",'1'&x"F71A",'1'&x"F71B",'1'&x"F71C",'1'&x"F71D",'1'&x"F71E",'1'&x"F71F",
+--'1'&x"F720",'1'&x"F721",'1'&x"F722",'1'&x"F723",'1'&x"F724",'1'&x"F725",'1'&x"F726",'1'&x"F727",'1'&x"F728",'1'&x"F729",'1'&x"F72A",'1'&x"F72B",'1'&x"F72C",'1'&x"F72D",'1'&x"F72E",'1'&x"F72F",
+--'1'&x"F730",'1'&x"F731",'1'&x"F732",'1'&x"F733",'1'&x"F734",'1'&x"F735",'1'&x"F736",'1'&x"F737",'1'&x"F738",'1'&x"F739",'1'&x"F73A",'1'&x"F73B",'1'&x"F73C",'1'&x"F73D",'1'&x"F73E",'1'&x"F73F",
+--'1'&x"F740",'1'&x"F741",'1'&x"F742",'1'&x"F743",'1'&x"F744",'1'&x"F745",'1'&x"F746",'1'&x"F747",'1'&x"F748",'1'&x"F749",'1'&x"F74A",'1'&x"F74B",'1'&x"F74C",'1'&x"F74D",'1'&x"F74E",'1'&x"F74F",
+--'1'&x"F750",'1'&x"F751",'1'&x"F752",'1'&x"F753",'1'&x"F754",'1'&x"F755",'1'&x"F756",'1'&x"F757",'1'&x"F758",'1'&x"F759",'1'&x"F75A",'1'&x"F75B",'1'&x"F75C",'1'&x"F75D",'1'&x"F75E",'1'&x"F75F",
+--'1'&x"F760",'1'&x"F761",'1'&x"F762",'1'&x"F763",'1'&x"F764",'1'&x"F765",'1'&x"F766",'1'&x"F767",'1'&x"F768",'1'&x"F769",'1'&x"F76A",'1'&x"F76B",'1'&x"F76C",'1'&x"F76D",'1'&x"F76E",'1'&x"F76F",
+--'1'&x"F770",'1'&x"F771",'1'&x"F772",'1'&x"F773",'1'&x"F774",'1'&x"F775",'1'&x"F776",'1'&x"F777",'1'&x"F778",'1'&x"F779",'1'&x"F77A",'1'&x"F77B",'1'&x"F77C",'1'&x"F77D",'1'&x"F77E",'1'&x"F77F",
+--'1'&x"F780",'1'&x"F781",'1'&x"F782",'1'&x"F783",'1'&x"F784",'1'&x"F785",'1'&x"F786",'1'&x"F787",'1'&x"F788",'1'&x"F789",'1'&x"F78A",'1'&x"F78B",'1'&x"F78C",'1'&x"F78D",'1'&x"F78E",'1'&x"F78F",
+--'1'&x"F790",'1'&x"F791",'1'&x"F792",'1'&x"F793",'1'&x"F794",'1'&x"F795",'1'&x"F796",'1'&x"F797",'1'&x"F798",'1'&x"F799",'1'&x"F79A",'1'&x"F79B",'1'&x"F79C",'1'&x"F79D",'1'&x"F79E",'1'&x"F79F",
+--'1'&x"F7A0",'1'&x"F7A1",'1'&x"F7A2",'1'&x"F7A3",'1'&x"F7A4",'1'&x"F7A5",'1'&x"F7A6",'1'&x"F7A7",'1'&x"F7A8",'1'&x"F7A9",'1'&x"F7AA",'1'&x"F7AB",'1'&x"F7AC",'1'&x"F7AD",'1'&x"F7AE",'1'&x"F7AF",
+--'1'&x"F7B0",'1'&x"F7B1",'1'&x"F7B2",'1'&x"F7B3",'1'&x"F7B4",'1'&x"F7B5",'1'&x"F7B6",'1'&x"F7B7",'1'&x"F7B8",'1'&x"F7B9",'1'&x"F7BA",'1'&x"F7BB",'1'&x"F7BC",'1'&x"F7BD",'1'&x"F7BE",'1'&x"F7BF",
+--'1'&x"F7C0",'1'&x"F7C1",'1'&x"F7C2",'1'&x"F7C3",'1'&x"F7C4",'1'&x"F7C5",'1'&x"F7C6",'1'&x"F7C7",'1'&x"F7C8",'1'&x"F7C9",'1'&x"F7CA",'1'&x"F7CB",'1'&x"F7CC",'1'&x"F7CD",'1'&x"F7CE",'1'&x"F7CF",
+--'1'&x"F7D0",'1'&x"F7D1",'1'&x"F7D2",'1'&x"F7D3",'1'&x"F7D4",'1'&x"F7D5",'1'&x"F7D6",'1'&x"F7D7",'1'&x"F7D8",'1'&x"F7D9",'1'&x"F7DA",'1'&x"F7DB",'1'&x"F7DC",'1'&x"F7DD",'1'&x"F7DE",'1'&x"F7DF",
+--'1'&x"F7E0",'1'&x"F7E1",'1'&x"F7E2",'1'&x"F7E3",'1'&x"F7E4",'1'&x"F7E5",'1'&x"F7E6",'1'&x"F7E7",'1'&x"F7E8",'1'&x"F7E9",'1'&x"F7EA",'1'&x"F7EB",'1'&x"F7EC",'1'&x"F7ED",'1'&x"F7EE",'1'&x"F7EF",
+--'1'&x"F7F0",'1'&x"F7F1",'1'&x"F7F2",'1'&x"F7F3",'1'&x"F7F4",'1'&x"F7F5",'1'&x"F7F6",'1'&x"F7F7",'1'&x"F7F8",'1'&x"F7F9",'1'&x"F7FA",'1'&x"F7FB",'1'&x"F7FC",'1'&x"F7FD",'1'&x"F7FE",'1'&x"F7FF",
+--'1'&x"F800",'1'&x"F801",'1'&x"F802",'1'&x"F803",'1'&x"F804",'1'&x"F805",'1'&x"F806",'1'&x"F807",'1'&x"F808",'1'&x"F809",'1'&x"F80A",'1'&x"F80B",'1'&x"F80C",'1'&x"F80D",'1'&x"F80E",'1'&x"F80F",
+--'1'&x"F810",'1'&x"F811",'1'&x"F812",'1'&x"F813",'1'&x"F814",'1'&x"F815",'1'&x"F816",'1'&x"F817",'1'&x"F818",'1'&x"F819",'1'&x"F81A",'1'&x"F81B",'1'&x"F81C",'1'&x"F81D",'1'&x"F81E",'1'&x"F81F",
+--'1'&x"F820",'1'&x"F821",'1'&x"F822",'1'&x"F823",'1'&x"F824",'1'&x"F825",'1'&x"F826",'1'&x"F827",'1'&x"F828",'1'&x"F829",'1'&x"F82A",'1'&x"F82B",'1'&x"F82C",'1'&x"F82D",'1'&x"F82E",'1'&x"F82F",
+--'1'&x"F830",'1'&x"F831",'1'&x"F832",'1'&x"F833",'1'&x"F834",'1'&x"F835",'1'&x"F836",'1'&x"F837",'1'&x"F838",'1'&x"F839",'1'&x"F83A",'1'&x"F83B",'1'&x"F83C",'1'&x"F83D",'1'&x"F83E",'1'&x"F83F",
+--'1'&x"F840",'1'&x"F841",'1'&x"F842",'1'&x"F843",'1'&x"F844",'1'&x"F845",'1'&x"F846",'1'&x"F847",'1'&x"F848",'1'&x"F849",'1'&x"F84A",'1'&x"F84B",'1'&x"F84C",'1'&x"F84D",'1'&x"F84E",'1'&x"F84F",
+--'1'&x"F850",'1'&x"F851",'1'&x"F852",'1'&x"F853",'1'&x"F854",'1'&x"F855",'1'&x"F856",'1'&x"F857",'1'&x"F858",'1'&x"F859",'1'&x"F85A",'1'&x"F85B",'1'&x"F85C",'1'&x"F85D",'1'&x"F85E",'1'&x"F85F",
+--'1'&x"F860",'1'&x"F861",'1'&x"F862",'1'&x"F863",'1'&x"F864",'1'&x"F865",'1'&x"F866",'1'&x"F867",'1'&x"F868",'1'&x"F869",'1'&x"F86A",'1'&x"F86B",'1'&x"F86C",'1'&x"F86D",'1'&x"F86E",'1'&x"F86F",
+--'1'&x"F870",'1'&x"F871",'1'&x"F872",'1'&x"F873",'1'&x"F874",'1'&x"F875",'1'&x"F876",'1'&x"F877",'1'&x"F878",'1'&x"F879",'1'&x"F87A",'1'&x"F87B",'1'&x"F87C",'1'&x"F87D",'1'&x"F87E",'1'&x"F87F",
+--'1'&x"F880",'1'&x"F881",'1'&x"F882",'1'&x"F883",'1'&x"F884",'1'&x"F885",'1'&x"F886",'1'&x"F887",'1'&x"F888",'1'&x"F889",'1'&x"F88A",'1'&x"F88B",'1'&x"F88C",'1'&x"F88D",'1'&x"F88E",'1'&x"F88F",
+--'1'&x"F890",'1'&x"F891",'1'&x"F892",'1'&x"F893",'1'&x"F894",'1'&x"F895",'1'&x"F896",'1'&x"F897",'1'&x"F898",'1'&x"F899",'1'&x"F89A",'1'&x"F89B",'1'&x"F89C",'1'&x"F89D",'1'&x"F89E",'1'&x"F89F",
+--'1'&x"F8A0",'1'&x"F8A1",'1'&x"F8A2",'1'&x"F8A3",'1'&x"F8A4",'1'&x"F8A5",'1'&x"F8A6",'1'&x"F8A7",'1'&x"F8A8",'1'&x"F8A9",'1'&x"F8AA",'1'&x"F8AB",'1'&x"F8AC",'1'&x"F8AD",'1'&x"F8AE",'1'&x"F8AF",
+--'1'&x"F8B0",'1'&x"F8B1",'1'&x"F8B2",'1'&x"F8B3",'1'&x"F8B4",'1'&x"F8B5",'1'&x"F8B6",'1'&x"F8B7",'1'&x"F8B8",'1'&x"F8B9",'1'&x"F8BA",'1'&x"F8BB",'1'&x"F8BC",'1'&x"F8BD",'1'&x"F8BE",'1'&x"F8BF",
+--'1'&x"F8C0",'1'&x"F8C1",'1'&x"F8C2",'1'&x"F8C3",'1'&x"F8C4",'1'&x"F8C5",'1'&x"F8C6",'1'&x"F8C7",'1'&x"F8C8",'1'&x"F8C9",'1'&x"F8CA",'1'&x"F8CB",'1'&x"F8CC",'1'&x"F8CD",'1'&x"F8CE",'1'&x"F8CF",
+--'1'&x"F8D0",'1'&x"F8D1",'1'&x"F8D2",'1'&x"F8D3",'1'&x"F8D4",'1'&x"F8D5",'1'&x"F8D6",'1'&x"F8D7",'1'&x"F8D8",'1'&x"F8D9",'1'&x"F8DA",'1'&x"F8DB",'1'&x"F8DC",'1'&x"F8DD",'1'&x"F8DE",'1'&x"F8DF",
+--'1'&x"F8E0",'1'&x"F8E1",'1'&x"F8E2",'1'&x"F8E3",'1'&x"F8E4",'1'&x"F8E5",'1'&x"F8E6",'1'&x"F8E7",'1'&x"F8E8",'1'&x"F8E9",'1'&x"F8EA",'1'&x"F8EB",'1'&x"F8EC",'1'&x"F8ED",'1'&x"F8EE",'1'&x"F8EF",
+--'1'&x"F8F0",'1'&x"F8F1",'1'&x"F8F2",'1'&x"F8F3",'1'&x"F8F4",'1'&x"F8F5",'1'&x"F8F6",'1'&x"F8F7",'1'&x"F8F8",'1'&x"F8F9",'1'&x"F8FA",'1'&x"F8FB",'1'&x"F8FC",'1'&x"F8FD",'1'&x"F8FE",'1'&x"F8FF",
+--'1'&x"F900",'1'&x"F901",'1'&x"F902",'1'&x"F903",'1'&x"F904",'1'&x"F905",'1'&x"F906",'1'&x"F907",'1'&x"F908",'1'&x"F909",'1'&x"F90A",'1'&x"F90B",'1'&x"F90C",'1'&x"F90D",'1'&x"F90E",'1'&x"F90F",
+--'1'&x"F910",'1'&x"F911",'1'&x"F912",'1'&x"F913",'1'&x"F914",'1'&x"F915",'1'&x"F916",'1'&x"F917",'1'&x"F918",'1'&x"F919",'1'&x"F91A",'1'&x"F91B",'1'&x"F91C",'1'&x"F91D",'1'&x"F91E",'1'&x"F91F",
+--'1'&x"F920",'1'&x"F921",'1'&x"F922",'1'&x"F923",'1'&x"F924",'1'&x"F925",'1'&x"F926",'1'&x"F927",'1'&x"F928",'1'&x"F929",'1'&x"F92A",'1'&x"F92B",'1'&x"F92C",'1'&x"F92D",'1'&x"F92E",'1'&x"F92F",
+--'1'&x"F930",'1'&x"F931",'1'&x"F932",'1'&x"F933",'1'&x"F934",'1'&x"F935",'1'&x"F936",'1'&x"F937",'1'&x"F938",'1'&x"F939",'1'&x"F93A",'1'&x"F93B",'1'&x"F93C",'1'&x"F93D",'1'&x"F93E",'1'&x"F93F",
+--'1'&x"F940",'1'&x"F941",'1'&x"F942",'1'&x"F943",'1'&x"F944",'1'&x"F945",'1'&x"F946",'1'&x"F947",'1'&x"F948",'1'&x"F949",'1'&x"F94A",'1'&x"F94B",'1'&x"F94C",'1'&x"F94D",'1'&x"F94E",'1'&x"F94F",
+--'1'&x"F950",'1'&x"F951",'1'&x"F952",'1'&x"F953",'1'&x"F954",'1'&x"F955",'1'&x"F956",'1'&x"F957",'1'&x"F958",'1'&x"F959",'1'&x"F95A",'1'&x"F95B",'1'&x"F95C",'1'&x"F95D",'1'&x"F95E",'1'&x"F95F",
+--'1'&x"F960",'1'&x"F961",'1'&x"F962",'1'&x"F963",'1'&x"F964",'1'&x"F965",'1'&x"F966",'1'&x"F967",'1'&x"F968",'1'&x"F969",'1'&x"F96A",'1'&x"F96B",'1'&x"F96C",'1'&x"F96D",'1'&x"F96E",'1'&x"F96F",
+--'1'&x"F970",'1'&x"F971",'1'&x"F972",'1'&x"F973",'1'&x"F974",'1'&x"F975",'1'&x"F976",'1'&x"F977",'1'&x"F978",'1'&x"F979",'1'&x"F97A",'1'&x"F97B",'1'&x"F97C",'1'&x"F97D",'1'&x"F97E",'1'&x"F97F",
+--'1'&x"F980",'1'&x"F981",'1'&x"F982",'1'&x"F983",'1'&x"F984",'1'&x"F985",'1'&x"F986",'1'&x"F987",'1'&x"F988",'1'&x"F989",'1'&x"F98A",'1'&x"F98B",'1'&x"F98C",'1'&x"F98D",'1'&x"F98E",'1'&x"F98F",
+--'1'&x"F990",'1'&x"F991",'1'&x"F992",'1'&x"F993",'1'&x"F994",'1'&x"F995",'1'&x"F996",'1'&x"F997",'1'&x"F998",'1'&x"F999",'1'&x"F99A",'1'&x"F99B",'1'&x"F99C",'1'&x"F99D",'1'&x"F99E",'1'&x"F99F",
+--'1'&x"F9A0",'1'&x"F9A1",'1'&x"F9A2",'1'&x"F9A3",'1'&x"F9A4",'1'&x"F9A5",'1'&x"F9A6",'1'&x"F9A7",'1'&x"F9A8",'1'&x"F9A9",'1'&x"F9AA",'1'&x"F9AB",'1'&x"F9AC",'1'&x"F9AD",'1'&x"F9AE",'1'&x"F9AF",
+--'1'&x"F9B0",'1'&x"F9B1",'1'&x"F9B2",'1'&x"F9B3",'1'&x"F9B4",'1'&x"F9B5",'1'&x"F9B6",'1'&x"F9B7",'1'&x"F9B8",'1'&x"F9B9",'1'&x"F9BA",'1'&x"F9BB",'1'&x"F9BC",'1'&x"F9BD",'1'&x"F9BE",'1'&x"F9BF",
+--'1'&x"F9C0",'1'&x"F9C1",'1'&x"F9C2",'1'&x"F9C3",'1'&x"F9C4",'1'&x"F9C5",'1'&x"F9C6",'1'&x"F9C7",'1'&x"F9C8",'1'&x"F9C9",'1'&x"F9CA",'1'&x"F9CB",'1'&x"F9CC",'1'&x"F9CD",'1'&x"F9CE",'1'&x"F9CF",
+--'1'&x"F9D0",'1'&x"F9D1",'1'&x"F9D2",'1'&x"F9D3",'1'&x"F9D4",'1'&x"F9D5",'1'&x"F9D6",'1'&x"F9D7",'1'&x"F9D8",'1'&x"F9D9",'1'&x"F9DA",'1'&x"F9DB",'1'&x"F9DC",'1'&x"F9DD",'1'&x"F9DE",'1'&x"F9DF",
+--'1'&x"F9E0",'1'&x"F9E1",'1'&x"F9E2",'1'&x"F9E3",'1'&x"F9E4",'1'&x"F9E5",'1'&x"F9E6",'1'&x"F9E7",'1'&x"F9E8",'1'&x"F9E9",'1'&x"F9EA",'1'&x"F9EB",'1'&x"F9EC",'1'&x"F9ED",'1'&x"F9EE",'1'&x"F9EF",
+--'1'&x"F9F0",'1'&x"F9F1",'1'&x"F9F2",'1'&x"F9F3",'1'&x"F9F4",'1'&x"F9F5",'1'&x"F9F6",'1'&x"F9F7",'1'&x"F9F8",'1'&x"F9F9",'1'&x"F9FA",'1'&x"F9FB",'1'&x"F9FC",'1'&x"F9FD",'1'&x"F9FE",'1'&x"F9FF",
+--'1'&x"FA00",'1'&x"FA01",'1'&x"FA02",'1'&x"FA03",'1'&x"FA04",'1'&x"FA05",'1'&x"FA06",'1'&x"FA07",'1'&x"FA08",'1'&x"FA09",'1'&x"FA0A",'1'&x"FA0B",'1'&x"FA0C",'1'&x"FA0D",'1'&x"FA0E",'1'&x"FA0F",
+--'1'&x"FA10",'1'&x"FA11",'1'&x"FA12",'1'&x"FA13",'1'&x"FA14",'1'&x"FA15",'1'&x"FA16",'1'&x"FA17",'1'&x"FA18",'1'&x"FA19",'1'&x"FA1A",'1'&x"FA1B",'1'&x"FA1C",'1'&x"FA1D",'1'&x"FA1E",'1'&x"FA1F",
+--'1'&x"FA20",'1'&x"FA21",'1'&x"FA22",'1'&x"FA23",'1'&x"FA24",'1'&x"FA25",'1'&x"FA26",'1'&x"FA27",'1'&x"FA28",'1'&x"FA29",'1'&x"FA2A",'1'&x"FA2B",'1'&x"FA2C",'1'&x"FA2D",'1'&x"FA2E",'1'&x"FA2F",
+--'1'&x"FA30",'1'&x"FA31",'1'&x"FA32",'1'&x"FA33",'1'&x"FA34",'1'&x"FA35",'1'&x"FA36",'1'&x"FA37",'1'&x"FA38",'1'&x"FA39",'1'&x"FA3A",'1'&x"FA3B",'1'&x"FA3C",'1'&x"FA3D",'1'&x"FA3E",'1'&x"FA3F",
+--'1'&x"FA40",'1'&x"FA41",'1'&x"FA42",'1'&x"FA43",'1'&x"FA44",'1'&x"FA45",'1'&x"FA46",'1'&x"FA47",'1'&x"FA48",'1'&x"FA49",'1'&x"FA4A",'1'&x"FA4B",'1'&x"FA4C",'1'&x"FA4D",'1'&x"FA4E",'1'&x"FA4F",
+--'1'&x"FA50",'1'&x"FA51",'1'&x"FA52",'1'&x"FA53",'1'&x"FA54",'1'&x"FA55",'1'&x"FA56",'1'&x"FA57",'1'&x"FA58",'1'&x"FA59",'1'&x"FA5A",'1'&x"FA5B",'1'&x"FA5C",'1'&x"FA5D",'1'&x"FA5E",'1'&x"FA5F",
+--'1'&x"FA60",'1'&x"FA61",'1'&x"FA62",'1'&x"FA63",'1'&x"FA64",'1'&x"FA65",'1'&x"FA66",'1'&x"FA67",'1'&x"FA68",'1'&x"FA69",'1'&x"FA6A",'1'&x"FA6B",'1'&x"FA6C",'1'&x"FA6D",'1'&x"FA6E",'1'&x"FA6F",
+--'1'&x"FA70",'1'&x"FA71",'1'&x"FA72",'1'&x"FA73",'1'&x"FA74",'1'&x"FA75",'1'&x"FA76",'1'&x"FA77",'1'&x"FA78",'1'&x"FA79",'1'&x"FA7A",'1'&x"FA7B",'1'&x"FA7C",'1'&x"FA7D",'1'&x"FA7E",'1'&x"FA7F",
+--'1'&x"FA80",'1'&x"FA81",'1'&x"FA82",'1'&x"FA83",'1'&x"FA84",'1'&x"FA85",'1'&x"FA86",'1'&x"FA87",'1'&x"FA88",'1'&x"FA89",'1'&x"FA8A",'1'&x"FA8B",'1'&x"FA8C",'1'&x"FA8D",'1'&x"FA8E",'1'&x"FA8F",
+--'1'&x"FA90",'1'&x"FA91",'1'&x"FA92",'1'&x"FA93",'1'&x"FA94",'1'&x"FA95",'1'&x"FA96",'1'&x"FA97",'1'&x"FA98",'1'&x"FA99",'1'&x"FA9A",'1'&x"FA9B",'1'&x"FA9C",'1'&x"FA9D",'1'&x"FA9E",'1'&x"FA9F",
+--'1'&x"FAA0",'1'&x"FAA1",'1'&x"FAA2",'1'&x"FAA3",'1'&x"FAA4",'1'&x"FAA5",'1'&x"FAA6",'1'&x"FAA7",'1'&x"FAA8",'1'&x"FAA9",'1'&x"FAAA",'1'&x"FAAB",'1'&x"FAAC",'1'&x"FAAD",'1'&x"FAAE",'1'&x"FAAF",
+--'1'&x"FAB0",'1'&x"FAB1",'1'&x"FAB2",'1'&x"FAB3",'1'&x"FAB4",'1'&x"FAB5",'1'&x"FAB6",'1'&x"FAB7",'1'&x"FAB8",'1'&x"FAB9",'1'&x"FABA",'1'&x"FABB",'1'&x"FABC",'1'&x"FABD",'1'&x"FABE",'1'&x"FABF",
+--'1'&x"FAC0",'1'&x"FAC1",'1'&x"FAC2",'1'&x"FAC3",'1'&x"FAC4",'1'&x"FAC5",'1'&x"FAC6",'1'&x"FAC7",'1'&x"FAC8",'1'&x"FAC9",'1'&x"FACA",'1'&x"FACB",'1'&x"FACC",'1'&x"FACD",'1'&x"FACE",'1'&x"FACF",
+--'1'&x"FAD0",'1'&x"FAD1",'1'&x"FAD2",'1'&x"FAD3",'1'&x"FAD4",'1'&x"FAD5",'1'&x"FAD6",'1'&x"FAD7",'1'&x"FAD8",'1'&x"FAD9",'1'&x"FADA",'1'&x"FADB",'1'&x"FADC",'1'&x"FADD",'1'&x"FADE",'1'&x"FADF",
+--'1'&x"FAE0",'1'&x"FAE1",'1'&x"FAE2",'1'&x"FAE3",'1'&x"FAE4",'1'&x"FAE5",'1'&x"FAE6",'1'&x"FAE7",'1'&x"FAE8",'1'&x"FAE9",'1'&x"FAEA",'1'&x"FAEB",'1'&x"FAEC",'1'&x"FAED",'1'&x"FAEE",'1'&x"FAEF",
+--'1'&x"FAF0",'1'&x"FAF1",'1'&x"FAF2",'1'&x"FAF3",'1'&x"FAF4",'1'&x"FAF5",'1'&x"FAF6",'1'&x"FAF7",'1'&x"FAF8",'1'&x"FAF9",'1'&x"FAFA",'1'&x"FAFB",'1'&x"FAFC",'1'&x"FAFD",'1'&x"FAFE",'1'&x"FAFF",
+--'1'&x"FB00",'1'&x"FB01",'1'&x"FB02",'1'&x"FB03",'1'&x"FB04",'1'&x"FB05",'1'&x"FB06",'1'&x"FB07",'1'&x"FB08",'1'&x"FB09",'1'&x"FB0A",'1'&x"FB0B",'1'&x"FB0C",'1'&x"FB0D",'1'&x"FB0E",'1'&x"FB0F",
+--'1'&x"FB10",'1'&x"FB11",'1'&x"FB12",'1'&x"FB13",'1'&x"FB14",'1'&x"FB15",'1'&x"FB16",'1'&x"FB17",'1'&x"FB18",'1'&x"FB19",'1'&x"FB1A",'1'&x"FB1B",'1'&x"FB1C",'1'&x"FB1D",'1'&x"FB1E",'1'&x"FB1F",
+--'1'&x"FB20",'1'&x"FB21",'1'&x"FB22",'1'&x"FB23",'1'&x"FB24",'1'&x"FB25",'1'&x"FB26",'1'&x"FB27",'1'&x"FB28",'1'&x"FB29",'1'&x"FB2A",'1'&x"FB2B",'1'&x"FB2C",'1'&x"FB2D",'1'&x"FB2E",'1'&x"FB2F",
+--'1'&x"FB30",'1'&x"FB31",'1'&x"FB32",'1'&x"FB33",'1'&x"FB34",'1'&x"FB35",'1'&x"FB36",'1'&x"FB37",'1'&x"FB38",'1'&x"FB39",'1'&x"FB3A",'1'&x"FB3B",'1'&x"FB3C",'1'&x"FB3D",'1'&x"FB3E",'1'&x"FB3F",
+--'1'&x"FB40",'1'&x"FB41",'1'&x"FB42",'1'&x"FB43",'1'&x"FB44",'1'&x"FB45",'1'&x"FB46",'1'&x"FB47",'1'&x"FB48",'1'&x"FB49",'1'&x"FB4A",'1'&x"FB4B",'1'&x"FB4C",'1'&x"FB4D",'1'&x"FB4E",'1'&x"FB4F",
+--'1'&x"FB50",'1'&x"FB51",'1'&x"FB52",'1'&x"FB53",'1'&x"FB54",'1'&x"FB55",'1'&x"FB56",'1'&x"FB57",'1'&x"FB58",'1'&x"FB59",'1'&x"FB5A",'1'&x"FB5B",'1'&x"FB5C",'1'&x"FB5D",'1'&x"FB5E",'1'&x"FB5F",
+--'1'&x"FB60",'1'&x"FB61",'1'&x"FB62",'1'&x"FB63",'1'&x"FB64",'1'&x"FB65",'1'&x"FB66",'1'&x"FB67",'1'&x"FB68",'1'&x"FB69",'1'&x"FB6A",'1'&x"FB6B",'1'&x"FB6C",'1'&x"FB6D",'1'&x"FB6E",'1'&x"FB6F",
+--'1'&x"FB70",'1'&x"FB71",'1'&x"FB72",'1'&x"FB73",'1'&x"FB74",'1'&x"FB75",'1'&x"FB76",'1'&x"FB77",'1'&x"FB78",'1'&x"FB79",'1'&x"FB7A",'1'&x"FB7B",'1'&x"FB7C",'1'&x"FB7D",'1'&x"FB7E",'1'&x"FB7F",
+--'1'&x"FB80",'1'&x"FB81",'1'&x"FB82",'1'&x"FB83",'1'&x"FB84",'1'&x"FB85",'1'&x"FB86",'1'&x"FB87",'1'&x"FB88",'1'&x"FB89",'1'&x"FB8A",'1'&x"FB8B",'1'&x"FB8C",'1'&x"FB8D",'1'&x"FB8E",'1'&x"FB8F",
+--'1'&x"FB90",'1'&x"FB91",'1'&x"FB92",'1'&x"FB93",'1'&x"FB94",'1'&x"FB95",'1'&x"FB96",'1'&x"FB97",'1'&x"FB98",'1'&x"FB99",'1'&x"FB9A",'1'&x"FB9B",'1'&x"FB9C",'1'&x"FB9D",'1'&x"FB9E",'1'&x"FB9F",
+--'1'&x"FBA0",'1'&x"FBA1",'1'&x"FBA2",'1'&x"FBA3",'1'&x"FBA4",'1'&x"FBA5",'1'&x"FBA6",'1'&x"FBA7",'1'&x"FBA8",'1'&x"FBA9",'1'&x"FBAA",'1'&x"FBAB",'1'&x"FBAC",'1'&x"FBAD",'1'&x"FBAE",'1'&x"FBAF",
+--'1'&x"FBB0",'1'&x"FBB1",'1'&x"FBB2",'1'&x"FBB3",'1'&x"FBB4",'1'&x"FBB5",'1'&x"FBB6",'1'&x"FBB7",'1'&x"FBB8",'1'&x"FBB9",'1'&x"FBBA",'1'&x"FBBB",'1'&x"FBBC",'1'&x"FBBD",'1'&x"FBBE",'1'&x"FBBF",
+--'1'&x"FBC0",'1'&x"FBC1",'1'&x"FBC2",'1'&x"FBC3",'1'&x"FBC4",'1'&x"FBC5",'1'&x"FBC6",'1'&x"FBC7",'1'&x"FBC8",'1'&x"FBC9",'1'&x"FBCA",'1'&x"FBCB",'1'&x"FBCC",'1'&x"FBCD",'1'&x"FBCE",'1'&x"FBCF",
+--'1'&x"FBD0",'1'&x"FBD1",'1'&x"FBD2",'1'&x"FBD3",'1'&x"FBD4",'1'&x"FBD5",'1'&x"FBD6",'1'&x"FBD7",'1'&x"FBD8",'1'&x"FBD9",'1'&x"FBDA",'1'&x"FBDB",'1'&x"FBDC",'1'&x"FBDD",'1'&x"FBDE",'1'&x"FBDF",
+--'1'&x"FBE0",'1'&x"FBE1",'1'&x"FBE2",'1'&x"FBE3",'1'&x"FBE4",'1'&x"FBE5",'1'&x"FBE6",'1'&x"FBE7",'1'&x"FBE8",'1'&x"FBE9",'1'&x"FBEA",'1'&x"FBEB",'1'&x"FBEC",'1'&x"FBED",'1'&x"FBEE",'1'&x"FBEF",
+--'1'&x"FBF0",'1'&x"FBF1",'1'&x"FBF2",'1'&x"FBF3",'1'&x"FBF4",'1'&x"FBF5",'1'&x"FBF6",'1'&x"FBF7",'1'&x"FBF8",'1'&x"FBF9",'1'&x"FBFA",'1'&x"FBFB",'1'&x"FBFC",'1'&x"FBFD",'1'&x"FBFE",'1'&x"FBFF",
+--'1'&x"FC00",'1'&x"FC01",'1'&x"FC02",'1'&x"FC03",'1'&x"FC04",'1'&x"FC05",'1'&x"FC06",'1'&x"FC07",'1'&x"FC08",'1'&x"FC09",'1'&x"FC0A",'1'&x"FC0B",'1'&x"FC0C",'1'&x"FC0D",'1'&x"FC0E",'1'&x"FC0F",
+--'1'&x"FC10",'1'&x"FC11",'1'&x"FC12",'1'&x"FC13",'1'&x"FC14",'1'&x"FC15",'1'&x"FC16",'1'&x"FC17",'1'&x"FC18",'1'&x"FC19",'1'&x"FC1A",'1'&x"FC1B",'1'&x"FC1C",'1'&x"FC1D",'1'&x"FC1E",'1'&x"FC1F",
+--'1'&x"FC20",'1'&x"FC21",'1'&x"FC22",'1'&x"FC23",'1'&x"FC24",'1'&x"FC25",'1'&x"FC26",'1'&x"FC27",'1'&x"FC28",'1'&x"FC29",'1'&x"FC2A",'1'&x"FC2B",'1'&x"FC2C",'1'&x"FC2D",'1'&x"FC2E",'1'&x"FC2F",
+--'1'&x"FC30",'1'&x"FC31",'1'&x"FC32",'1'&x"FC33",'1'&x"FC34",'1'&x"FC35",'1'&x"FC36",'1'&x"FC37",'1'&x"FC38",'1'&x"FC39",'1'&x"FC3A",'1'&x"FC3B",'1'&x"FC3C",'1'&x"FC3D",'1'&x"FC3E",'1'&x"FC3F",
+--'1'&x"FC40",'1'&x"FC41",'1'&x"FC42",'1'&x"FC43",'1'&x"FC44",'1'&x"FC45",'1'&x"FC46",'1'&x"FC47",'1'&x"FC48",'1'&x"FC49",'1'&x"FC4A",'1'&x"FC4B",'1'&x"FC4C",'1'&x"FC4D",'1'&x"FC4E",'1'&x"FC4F",
+--'1'&x"FC50",'1'&x"FC51",'1'&x"FC52",'1'&x"FC53",'1'&x"FC54",'1'&x"FC55",'1'&x"FC56",'1'&x"FC57",'1'&x"FC58",'1'&x"FC59",'1'&x"FC5A",'1'&x"FC5B",'1'&x"FC5C",'1'&x"FC5D",'1'&x"FC5E",'1'&x"FC5F",
+--'1'&x"FC60",'1'&x"FC61",'1'&x"FC62",'1'&x"FC63",'1'&x"FC64",'1'&x"FC65",'1'&x"FC66",'1'&x"FC67",'1'&x"FC68",'1'&x"FC69",'1'&x"FC6A",'1'&x"FC6B",'1'&x"FC6C",'1'&x"FC6D",'1'&x"FC6E",'1'&x"FC6F",
+--'1'&x"FC70",'1'&x"FC71",'1'&x"FC72",'1'&x"FC73",'1'&x"FC74",'1'&x"FC75",'1'&x"FC76",'1'&x"FC77",'1'&x"FC78",'1'&x"FC79",'1'&x"FC7A",'1'&x"FC7B",'1'&x"FC7C",'1'&x"FC7D",'1'&x"FC7E",'1'&x"FC7F",
+--'1'&x"FC80",'1'&x"FC81",'1'&x"FC82",'1'&x"FC83",'1'&x"FC84",'1'&x"FC85",'1'&x"FC86",'1'&x"FC87",'1'&x"FC88",'1'&x"FC89",'1'&x"FC8A",'1'&x"FC8B",'1'&x"FC8C",'1'&x"FC8D",'1'&x"FC8E",'1'&x"FC8F",
+--'1'&x"FC90",'1'&x"FC91",'1'&x"FC92",'1'&x"FC93",'1'&x"FC94",'1'&x"FC95",'1'&x"FC96",'1'&x"FC97",'1'&x"FC98",'1'&x"FC99",'1'&x"FC9A",'1'&x"FC9B",'1'&x"FC9C",'1'&x"FC9D",'1'&x"FC9E",'1'&x"FC9F",
+--'1'&x"FCA0",'1'&x"FCA1",'1'&x"FCA2",'1'&x"FCA3",'1'&x"FCA4",'1'&x"FCA5",'1'&x"FCA6",'1'&x"FCA7",'1'&x"FCA8",'1'&x"FCA9",'1'&x"FCAA",'1'&x"FCAB",'1'&x"FCAC",'1'&x"FCAD",'1'&x"FCAE",'1'&x"FCAF",
+--'1'&x"FCB0",'1'&x"FCB1",'1'&x"FCB2",'1'&x"FCB3",'1'&x"FCB4",'1'&x"FCB5",'1'&x"FCB6",'1'&x"FCB7",'1'&x"FCB8",'1'&x"FCB9",'1'&x"FCBA",'1'&x"FCBB",'1'&x"FCBC",'1'&x"FCBD",'1'&x"FCBE",'1'&x"FCBF",
+--'1'&x"FCC0",'1'&x"FCC1",'1'&x"FCC2",'1'&x"FCC3",'1'&x"FCC4",'1'&x"FCC5",'1'&x"FCC6",'1'&x"FCC7",'1'&x"FCC8",'1'&x"FCC9",'1'&x"FCCA",'1'&x"FCCB",'1'&x"FCCC",'1'&x"FCCD",'1'&x"FCCE",'1'&x"FCCF",
+--'1'&x"FCD0",'1'&x"FCD1",'1'&x"FCD2",'1'&x"FCD3",'1'&x"FCD4",'1'&x"FCD5",'1'&x"FCD6",'1'&x"FCD7",'1'&x"FCD8",'1'&x"FCD9",'1'&x"FCDA",'1'&x"FCDB",'1'&x"FCDC",'1'&x"FCDD",'1'&x"FCDE",'1'&x"FCDF",
+--'1'&x"FCE0",'1'&x"FCE1",'1'&x"FCE2",'1'&x"FCE3",'1'&x"FCE4",'1'&x"FCE5",'1'&x"FCE6",'1'&x"FCE7",'1'&x"FCE8",'1'&x"FCE9",'1'&x"FCEA",'1'&x"FCEB",'1'&x"FCEC",'1'&x"FCED",'1'&x"FCEE",'1'&x"FCEF",
+--'1'&x"FCF0",'1'&x"FCF1",'1'&x"FCF2",'1'&x"FCF3",'1'&x"FCF4",'1'&x"FCF5",'1'&x"FCF6",'1'&x"FCF7",'1'&x"FCF8",'1'&x"FCF9",'1'&x"FCFA",'1'&x"FCFB",'1'&x"FCFC",'1'&x"FCFD",'1'&x"FCFE",'1'&x"FCFF",
+--'1'&x"FD00",'1'&x"FD01",'1'&x"FD02",'1'&x"FD03",'1'&x"FD04",'1'&x"FD05",'1'&x"FD06",'1'&x"FD07",'1'&x"FD08",'1'&x"FD09",'1'&x"FD0A",'1'&x"FD0B",'1'&x"FD0C",'1'&x"FD0D",'1'&x"FD0E",'1'&x"FD0F",
+--'1'&x"FD10",'1'&x"FD11",'1'&x"FD12",'1'&x"FD13",'1'&x"FD14",'1'&x"FD15",'1'&x"FD16",'1'&x"FD17",'1'&x"FD18",'1'&x"FD19",'1'&x"FD1A",'1'&x"FD1B",'1'&x"FD1C",'1'&x"FD1D",'1'&x"FD1E",'1'&x"FD1F",
+--'1'&x"FD20",'1'&x"FD21",'1'&x"FD22",'1'&x"FD23",'1'&x"FD24",'1'&x"FD25",'1'&x"FD26",'1'&x"FD27",'1'&x"FD28",'1'&x"FD29",'1'&x"FD2A",'1'&x"FD2B",'1'&x"FD2C",'1'&x"FD2D",'1'&x"FD2E",'1'&x"FD2F",
+--'1'&x"FD30",'1'&x"FD31",'1'&x"FD32",'1'&x"FD33",'1'&x"FD34",'1'&x"FD35",'1'&x"FD36",'1'&x"FD37",'1'&x"FD38",'1'&x"FD39",'1'&x"FD3A",'1'&x"FD3B",'1'&x"FD3C",'1'&x"FD3D",'1'&x"FD3E",'1'&x"FD3F",
+--'1'&x"FD40",'1'&x"FD41",'1'&x"FD42",'1'&x"FD43",'1'&x"FD44",'1'&x"FD45",'1'&x"FD46",'1'&x"FD47",'1'&x"FD48",'1'&x"FD49",'1'&x"FD4A",'1'&x"FD4B",'1'&x"FD4C",'1'&x"FD4D",'1'&x"FD4E",'1'&x"FD4F",
+--'1'&x"FD50",'1'&x"FD51",'1'&x"FD52",'1'&x"FD53",'1'&x"FD54",'1'&x"FD55",'1'&x"FD56",'1'&x"FD57",'1'&x"FD58",'1'&x"FD59",'1'&x"FD5A",'1'&x"FD5B",'1'&x"FD5C",'1'&x"FD5D",'1'&x"FD5E",'1'&x"FD5F",
+--'1'&x"FD60",'1'&x"FD61",'1'&x"FD62",'1'&x"FD63",'1'&x"FD64",'1'&x"FD65",'1'&x"FD66",'1'&x"FD67",'1'&x"FD68",'1'&x"FD69",'1'&x"FD6A",'1'&x"FD6B",'1'&x"FD6C",'1'&x"FD6D",'1'&x"FD6E",'1'&x"FD6F",
+--'1'&x"FD70",'1'&x"FD71",'1'&x"FD72",'1'&x"FD73",'1'&x"FD74",'1'&x"FD75",'1'&x"FD76",'1'&x"FD77",'1'&x"FD78",'1'&x"FD79",'1'&x"FD7A",'1'&x"FD7B",'1'&x"FD7C",'1'&x"FD7D",'1'&x"FD7E",'1'&x"FD7F",
+--'1'&x"FD80",'1'&x"FD81",'1'&x"FD82",'1'&x"FD83",'1'&x"FD84",'1'&x"FD85",'1'&x"FD86",'1'&x"FD87",'1'&x"FD88",'1'&x"FD89",'1'&x"FD8A",'1'&x"FD8B",'1'&x"FD8C",'1'&x"FD8D",'1'&x"FD8E",'1'&x"FD8F",
+--'1'&x"FD90",'1'&x"FD91",'1'&x"FD92",'1'&x"FD93",'1'&x"FD94",'1'&x"FD95",'1'&x"FD96",'1'&x"FD97",'1'&x"FD98",'1'&x"FD99",'1'&x"FD9A",'1'&x"FD9B",'1'&x"FD9C",'1'&x"FD9D",'1'&x"FD9E",'1'&x"FD9F",
+--'1'&x"FDA0",'1'&x"FDA1",'1'&x"FDA2",'1'&x"FDA3",'1'&x"FDA4",'1'&x"FDA5",'1'&x"FDA6",'1'&x"FDA7",'1'&x"FDA8",'1'&x"FDA9",'1'&x"FDAA",'1'&x"FDAB",'1'&x"FDAC",'1'&x"FDAD",'1'&x"FDAE",'1'&x"FDAF",
+--'1'&x"FDB0",'1'&x"FDB1",'1'&x"FDB2",'1'&x"FDB3",'1'&x"FDB4",'1'&x"FDB5",'1'&x"FDB6",'1'&x"FDB7",'1'&x"FDB8",'1'&x"FDB9",'1'&x"FDBA",'1'&x"FDBB",'1'&x"FDBC",'1'&x"FDBD",'1'&x"FDBE",'1'&x"FDBF",
+--'1'&x"FDC0",'1'&x"FDC1",'1'&x"FDC2",'1'&x"FDC3",'1'&x"FDC4",'1'&x"FDC5",'1'&x"FDC6",'1'&x"FDC7",'1'&x"FDC8",'1'&x"FDC9",'1'&x"FDCA",'1'&x"FDCB",'1'&x"FDCC",'1'&x"FDCD",'1'&x"FDCE",'1'&x"FDCF",
+--'1'&x"FDD0",'1'&x"FDD1",'1'&x"FDD2",'1'&x"FDD3",'1'&x"FDD4",'1'&x"FDD5",'1'&x"FDD6",'1'&x"FDD7",'1'&x"FDD8",'1'&x"FDD9",'1'&x"FDDA",'1'&x"FDDB",'1'&x"FDDC",'1'&x"FDDD",'1'&x"FDDE",'1'&x"FDDF",
+--'1'&x"FDE0",'1'&x"FDE1",'1'&x"FDE2",'1'&x"FDE3",'1'&x"FDE4",'1'&x"FDE5",'1'&x"FDE6",'1'&x"FDE7",'1'&x"FDE8",'1'&x"FDE9",'1'&x"FDEA",'1'&x"FDEB",'1'&x"FDEC",'1'&x"FDED",'1'&x"FDEE",'1'&x"FDEF",
+--'1'&x"FDF0",'1'&x"FDF1",'1'&x"FDF2",'1'&x"FDF3",'1'&x"FDF4",'1'&x"FDF5",'1'&x"FDF6",'1'&x"FDF7",'1'&x"FDF8",'1'&x"FDF9",'1'&x"FDFA",'1'&x"FDFB",'1'&x"FDFC",'1'&x"FDFD",'1'&x"FDFE",'1'&x"FDFF",
+--'1'&x"FE00",'1'&x"FE01",'1'&x"FE02",'1'&x"FE03",'1'&x"FE04",'1'&x"FE05",'1'&x"FE06",'1'&x"FE07",'1'&x"FE08",'1'&x"FE09",'1'&x"FE0A",'1'&x"FE0B",'1'&x"FE0C",'1'&x"FE0D",'1'&x"FE0E",'1'&x"FE0F",
+--'1'&x"FE10",'1'&x"FE11",'1'&x"FE12",'1'&x"FE13",'1'&x"FE14",'1'&x"FE15",'1'&x"FE16",'1'&x"FE17",'1'&x"FE18",'1'&x"FE19",'1'&x"FE1A",'1'&x"FE1B",'1'&x"FE1C",'1'&x"FE1D",'1'&x"FE1E",'1'&x"FE1F",
+--'1'&x"FE20",'1'&x"FE21",'1'&x"FE22",'1'&x"FE23",'1'&x"FE24",'1'&x"FE25",'1'&x"FE26",'1'&x"FE27",'1'&x"FE28",'1'&x"FE29",'1'&x"FE2A",'1'&x"FE2B",'1'&x"FE2C",'1'&x"FE2D",'1'&x"FE2E",'1'&x"FE2F",
+--'1'&x"FE30",'1'&x"FE31",'1'&x"FE32",'1'&x"FE33",'1'&x"FE34",'1'&x"FE35",'1'&x"FE36",'1'&x"FE37",'1'&x"FE38",'1'&x"FE39",'1'&x"FE3A",'1'&x"FE3B",'1'&x"FE3C",'1'&x"FE3D",'1'&x"FE3E",'1'&x"FE3F",
+--'1'&x"FE40",'1'&x"FE41",'1'&x"FE42",'1'&x"FE43",'1'&x"FE44",'1'&x"FE45",'1'&x"FE46",'1'&x"FE47",'1'&x"FE48",'1'&x"FE49",'1'&x"FE4A",'1'&x"FE4B",'1'&x"FE4C",'1'&x"FE4D",'1'&x"FE4E",'1'&x"FE4F",
+--'1'&x"FE50",'1'&x"FE51",'1'&x"FE52",'1'&x"FE53",'1'&x"FE54",'1'&x"FE55",'1'&x"FE56",'1'&x"FE57",'1'&x"FE58",'1'&x"FE59",'1'&x"FE5A",'1'&x"FE5B",'1'&x"FE5C",'1'&x"FE5D",'1'&x"FE5E",'1'&x"FE5F",
+--'1'&x"FE60",'1'&x"FE61",'1'&x"FE62",'1'&x"FE63",'1'&x"FE64",'1'&x"FE65",'1'&x"FE66",'1'&x"FE67",'1'&x"FE68",'1'&x"FE69",'1'&x"FE6A",'1'&x"FE6B",'1'&x"FE6C",'1'&x"FE6D",'1'&x"FE6E",'1'&x"FE6F",
+--'1'&x"FE70",'1'&x"FE71",'1'&x"FE72",'1'&x"FE73",'1'&x"FE74",'1'&x"FE75",'1'&x"FE76",'1'&x"FE77",'1'&x"FE78",'1'&x"FE79",'1'&x"FE7A",'1'&x"FE7B",'1'&x"FE7C",'1'&x"FE7D",'1'&x"FE7E",'1'&x"FE7F",
+--'1'&x"FE80",'1'&x"FE81",'1'&x"FE82",'1'&x"FE83",'1'&x"FE84",'1'&x"FE85",'1'&x"FE86",'1'&x"FE87",'1'&x"FE88",'1'&x"FE89",'1'&x"FE8A",'1'&x"FE8B",'1'&x"FE8C",'1'&x"FE8D",'1'&x"FE8E",'1'&x"FE8F",
+--'1'&x"FE90",'1'&x"FE91",'1'&x"FE92",'1'&x"FE93",'1'&x"FE94",'1'&x"FE95",'1'&x"FE96",'1'&x"FE97",'1'&x"FE98",'1'&x"FE99",'1'&x"FE9A",'1'&x"FE9B",'1'&x"FE9C",'1'&x"FE9D",'1'&x"FE9E",'1'&x"FE9F",
+--'1'&x"FEA0",'1'&x"FEA1",'1'&x"FEA2",'1'&x"FEA3",'1'&x"FEA4",'1'&x"FEA5",'1'&x"FEA6",'1'&x"FEA7",'1'&x"FEA8",'1'&x"FEA9",'1'&x"FEAA",'1'&x"FEAB",'1'&x"FEAC",'1'&x"FEAD",'1'&x"FEAE",'1'&x"FEAF",
+--'1'&x"FEB0",'1'&x"FEB1",'1'&x"FEB2",'1'&x"FEB3",'1'&x"FEB4",'1'&x"FEB5",'1'&x"FEB6",'1'&x"FEB7",'1'&x"FEB8",'1'&x"FEB9",'1'&x"FEBA",'1'&x"FEBB",'1'&x"FEBC",'1'&x"FEBD",'1'&x"FEBE",'1'&x"FEBF",
+--'1'&x"FEC0",'1'&x"FEC1",'1'&x"FEC2",'1'&x"FEC3",'1'&x"FEC4",'1'&x"FEC5",'1'&x"FEC6",'1'&x"FEC7",'1'&x"FEC8",'1'&x"FEC9",'1'&x"FECA",'1'&x"FECB",'1'&x"FECC",'1'&x"FECD",'1'&x"FECE",'1'&x"FECF",
+--'1'&x"FED0",'1'&x"FED1",'1'&x"FED2",'1'&x"FED3",'1'&x"FED4",'1'&x"FED5",'1'&x"FED6",'1'&x"FED7",'1'&x"FED8",'1'&x"FED9",'1'&x"FEDA",'1'&x"FEDB",'1'&x"FEDC",'1'&x"FEDD",'1'&x"FEDE",'1'&x"FEDF",
+--'1'&x"FEE0",'1'&x"FEE1",'1'&x"FEE2",'1'&x"FEE3",'1'&x"FEE4",'1'&x"FEE5",'1'&x"FEE6",'1'&x"FEE7",'1'&x"FEE8",'1'&x"FEE9",'1'&x"FEEA",'1'&x"FEEB",'1'&x"FEEC",'1'&x"FEED",'1'&x"FEEE",'1'&x"FEEF",
+--'1'&x"FEF0",'1'&x"FEF1",'1'&x"FEF2",'1'&x"FEF3",'1'&x"FEF4",'1'&x"FEF5",'1'&x"FEF6",'1'&x"FEF7",'1'&x"FEF8",'1'&x"FEF9",'1'&x"FEFA",'1'&x"FEFB",'1'&x"FEFC",'1'&x"FEFD",'1'&x"FEFE",'1'&x"FEFF",
+--'1'&x"FF00",'1'&x"FF01",'1'&x"FF02",'1'&x"FF03",'1'&x"FF04",'1'&x"FF05",'1'&x"FF06",'1'&x"FF07",'1'&x"FF08",'1'&x"FF09",'1'&x"FF0A",'1'&x"FF0B",'1'&x"FF0C",'1'&x"FF0D",'1'&x"FF0E",'1'&x"FF0F",
+--'1'&x"FF10",'1'&x"FF11",'1'&x"FF12",'1'&x"FF13",'1'&x"FF14",'1'&x"FF15",'1'&x"FF16",'1'&x"FF17",'1'&x"FF18",'1'&x"FF19",'1'&x"FF1A",'1'&x"FF1B",'1'&x"FF1C",'1'&x"FF1D",'1'&x"FF1E",'1'&x"FF1F",
+--'1'&x"FF20",'1'&x"FF21",'1'&x"FF22",'1'&x"FF23",'1'&x"FF24",'1'&x"FF25",'1'&x"FF26",'1'&x"FF27",'1'&x"FF28",'1'&x"FF29",'1'&x"FF2A",'1'&x"FF2B",'1'&x"FF2C",'1'&x"FF2D",'1'&x"FF2E",'1'&x"FF2F",
+--'1'&x"FF30",'1'&x"FF31",'1'&x"FF32",'1'&x"FF33",'1'&x"FF34",'1'&x"FF35",'1'&x"FF36",'1'&x"FF37",'1'&x"FF38",'1'&x"FF39",'1'&x"FF3A",'1'&x"FF3B",'1'&x"FF3C",'1'&x"FF3D",'1'&x"FF3E",'1'&x"FF3F",
+--'1'&x"FF40",'1'&x"FF41",'1'&x"FF42",'1'&x"FF43",'1'&x"FF44",'1'&x"FF45",'1'&x"FF46",'1'&x"FF47",'1'&x"FF48",'1'&x"FF49",'1'&x"FF4A",'1'&x"FF4B",'1'&x"FF4C",'1'&x"FF4D",'1'&x"FF4E",'1'&x"FF4F",
+--'1'&x"FF50",'1'&x"FF51",'1'&x"FF52",'1'&x"FF53",'1'&x"FF54",'1'&x"FF55",'1'&x"FF56",'1'&x"FF57",'1'&x"FF58",'1'&x"FF59",'1'&x"FF5A",'1'&x"FF5B",'1'&x"FF5C",'1'&x"FF5D",'1'&x"FF5E",'1'&x"FF5F",
+--'1'&x"FF60",'1'&x"FF61",'1'&x"FF62",'1'&x"FF63",'1'&x"FF64",'1'&x"FF65",'1'&x"FF66",'1'&x"FF67",'1'&x"FF68",'1'&x"FF69",'1'&x"FF6A",'1'&x"FF6B",'1'&x"FF6C",'1'&x"FF6D",'1'&x"FF6E",'1'&x"FF6F",
+--'1'&x"FF70",'1'&x"FF71",'1'&x"FF72",'1'&x"FF73",'1'&x"FF74",'1'&x"FF75",'1'&x"FF76",'1'&x"FF77",'1'&x"FF78",'1'&x"FF79",'1'&x"FF7A",'1'&x"FF7B",'1'&x"FF7C",'1'&x"FF7D",'1'&x"FF7E",'1'&x"FF7F",
+--'1'&x"FF80",'1'&x"FF81",'1'&x"FF82",'1'&x"FF83",'1'&x"FF84",'1'&x"FF85",'1'&x"FF86",'1'&x"FF87",'1'&x"FF88",'1'&x"FF89",'1'&x"FF8A",'1'&x"FF8B",'1'&x"FF8C",'1'&x"FF8D",'1'&x"FF8E",'1'&x"FF8F",
+--'1'&x"FF90",'1'&x"FF91",'1'&x"FF92",'1'&x"FF93",'1'&x"FF94",'1'&x"FF95",'1'&x"FF96",'1'&x"FF97",'1'&x"FF98",'1'&x"FF99",'1'&x"FF9A",'1'&x"FF9B",'1'&x"FF9C",'1'&x"FF9D",'1'&x"FF9E",'1'&x"FF9F",
+--'1'&x"FFA0",'1'&x"FFA1",'1'&x"FFA2",'1'&x"FFA3",'1'&x"FFA4",'1'&x"FFA5",'1'&x"FFA6",'1'&x"FFA7",'1'&x"FFA8",'1'&x"FFA9",'1'&x"FFAA",'1'&x"FFAB",'1'&x"FFAC",'1'&x"FFAD",'1'&x"FFAE",'1'&x"FFAF",
+--'1'&x"FFB0",'1'&x"FFB1",'1'&x"FFB2",'1'&x"FFB3",'1'&x"FFB4",'1'&x"FFB5",'1'&x"FFB6",'1'&x"FFB7",'1'&x"FFB8",'1'&x"FFB9",'1'&x"FFBA",'1'&x"FFBB",'1'&x"FFBC",'1'&x"FFBD",'1'&x"FFBE",'1'&x"FFBF",
+--'1'&x"FFC0",'1'&x"FFC1",'1'&x"FFC2",'1'&x"FFC3",'1'&x"FFC4",'1'&x"FFC5",'1'&x"FFC6",'1'&x"FFC7",'1'&x"FFC8",'1'&x"FFC9",'1'&x"FFCA",'1'&x"FFCB",'1'&x"FFCC",'1'&x"FFCD",'1'&x"FFCE",'1'&x"FFCF",
+--'1'&x"FFD0",'1'&x"FFD1",'1'&x"FFD2",'1'&x"FFD3",'1'&x"FFD4",'1'&x"FFD5",'1'&x"FFD6",'1'&x"FFD7",'1'&x"FFD8",'1'&x"FFD9",'1'&x"FFDA",'1'&x"FFDB",'1'&x"FFDC",'1'&x"FFDD",'1'&x"FFDE",'1'&x"FFDF",
+--'1'&x"FFE0",'1'&x"FFE1",'1'&x"FFE2",'1'&x"FFE3",'1'&x"FFE4",'1'&x"FFE5",'1'&x"FFE6",'1'&x"FFE7",'1'&x"FFE8",'1'&x"FFE9",'1'&x"FFEA",'1'&x"FFEB",'1'&x"FFEC",'1'&x"FFED",'1'&x"FFEE",'1'&x"FFEF",
+--'1'&x"FFF0",'1'&x"FFF1",'1'&x"FFF2",'1'&x"FFF3",'1'&x"FFF4",'1'&x"FFF5",'1'&x"FFF6",'1'&x"FFF7",'1'&x"FFF8",'1'&x"FFF9",'1'&x"FFFA",'1'&x"FFFB",'1'&x"FFFC",'1'&x"FFFD",'1'&x"FFFE",'1'&x"FFFF");
+
+attribute RAM_STYLE : string;
+attribute RAM_STYLE of mem_S: signal is "BLOCK";
+
+begin
+
+-- process (clock)
+-- begin
+-- if (clock'event and clock = '1') then
+-- if (write_enable = '1') then
+-- mem_S(conv_integer(write_address)) <= data_in;
+-- end if;
+-- data_out <= mem_S(conv_integer(read_address));
+-- end if;
+-- end process;
+ process (clock)
+ begin
+ if (clock'event and clock = '1') then
+ if (write_enable = '1') then
+ mem_S(conv_integer(write_address)) <= data_in(16);
+ end if;
+ data_out(16) <= mem_S(conv_integer(read_address));
+ data_out(14 downto 0) <= read_address(15 downto 1);
+ data_out(15) <= '0';
+ end if;
+ end process;
+
+end architecture behavioral;
\ No newline at end of file
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 26-06-2016
+-- Module Name: CN_cluster_build
+-- Description: Construct clusters from a bunch of hits
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+use std.textio.all;
+use IEEE.std_logic_textio.all; -- I/O for logic types
+
+----------------------------------------------------------------------------------
+-- CN_cluster_build
+-- Construct clusters from a bunch of (pre-)clusters, based on time and XY-position
+-- C-software developed by Marcel Tiemens
+-- Input precluster-data from module that splits up a stream in timebunches.
+-- If a cluster contains only one hit and if this hit is not position on the edge of the region then this cluster is skipped.
+--
+-- Input and output data format is the same:
+--
+-- Cluster packets with 64 bits data words:
+-- 64bits word1, only valid on a new superburst, when the signal data_in_first/data_out_first is active:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- for cluster data, for each cluster
+-- 64bits word2, clusterresults
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..30 = diameter
+-- bit29..20 = Y position, multiplied by 2
+-- bit19..10 = X position, multiplied by 2
+-- bit9..0 = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- Criteria neighbours:
+-- crystal-positions (X0pos,Y0pos) and (X1pos,Y1pos) are neighbours :
+-- if (((X0pos>=X1pos) and (2*X0pos-2*X1pos <= diameter0+diameter1)) or ((X0pos<X1pos) and (2*X1pos-2*X0pos <= diameter0+diameter1)) and
+-- ((Y0pos>=Y1pos) and (2*Y0pos-2*Y1pos <= diameter0+diameter1)) or ((Y0pos<Y1pos) and (2*Y1pos-2*Y0pos <= diameter0+diameter1)) and
+-- (((pre0_t>=pre1_t) and (pre0_t-pre1_t <= timedifference)) or ((pre0_t<pre1_t) and (pre1_t-pre0_t <= timedifference))) then
+-- (time1-time0<=timedifference))
+--
+-- Library
+--
+--
+-- Generics:
+-- CLUSTERBITS : number of bits for the number of hits in one timebunch
+-- MAXCLUSTERSBITS : number of bits for the maximum clusters in one timebunch
+-- MINIMUMENERGYBITS : number of bits for the miminum energy value
+-- SKIPSINGLEHITCLUSTERS : skip cluster if it contains only one hit and is not positioned on the edge
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset
+-- timedifference : maximum difference in time between hits in a cluster, resolutie from Constant Fraction (6.1ps)
+-- minimal_energy : minimum energy for a cluster; clusters with less are skipped if they are not positioned on the edge of a region
+-- data_in : 64-bits input data
+-- data_in_onedge : '1' if the hit is on the edge of the XY-area,
+-- data_in_active : timebunch active
+-- data_in_write : write signal for input data
+-- data_in_first : input data contains new superburst
+-- data_in_last : indicates that the cluster is the last in a superburst
+-- data_out_clusterallowed : allowed to write clusters to output
+--
+--
+-- Outputs:
+-- data_in_allowed : writing of input data allowed
+-- busy : busy processing timebunch
+-- data_out : 64 bits output data
+-- data_out_write : write signal for 64 bits output data
+-- data_out_first : 64 bits output data contains new superburst
+-- data_out_last : 64 bits output data is the last data of a superburst
+-- nextcluster : signal that indicates the last data of a timebunch
+-- dataerror : error in data
+--
+-- Components:
+-- blockmem : synchronous memory block
+-- blockmemdirectread : synchronous memory block from which the output reacts directly on the written value
+--
+----------------------------------------------------------------------------------
+
+entity CN_cluster_build is
+ generic(
+ CLUSTERBITS : natural := 8;
+ MAXCLUSTERSBITS : natural := 5;
+ MINIMUMENERGYBITS : natural := 8;
+ SKIPSINGLEHITCLUSTERS : boolean := TRUE
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ timedifference : in std_logic_vector(23 downto 0);
+ minimal_energy : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_onedge : in std_logic;
+ data_in_active : in std_logic;
+ data_in_write : in std_logic;
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_allowed : out std_logic;
+ busy : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_clusterallowed : in std_logic;
+ nextcluster : out std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end CN_cluster_build;
+
+
+architecture behaviour of CN_cluster_build is
+
+component blockmem is
+ generic (
+ ADDRESS_BITS : natural := 16;
+ DATA_BITS : natural := 32
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)
+ );
+end component;
+
+component blockmemdirectread is
+ generic (
+ ADDRESS_BITS : natural := 16;
+ DATA_BITS : natural := 32
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)
+ );
+end component;
+
+constant ONES : std_logic_vector(63 downto 0) := (others => '1');
+constant ZEROS : std_logic_vector(63 downto 0) := (others => '0');
+type state_type is (INITIALIZE,COLLECT,PRE_READ0,PRE_READ1,PRIMARY,PRIMARY1,PRIMARY1_0,PRIMARY2,PRIMARY2_0,
+ SECONDAIRY,SECONDAIRY1,ADJUSTSIMULARITIES,SECONDAIRY2,SORTING,
+ WRITESUPERBURST,WRITEONECLUSTER,WRITEONECLUSTERHITS,
+ WRITECLUSTER,WRITEHITS0,WRITEHITS1,WRITEHITS);
+signal state_S : state_type := INITIALIZE;
+signal stateprev_S : state_type;
+
+signal error_S : std_logic := '0';
+signal data_in_write_S : std_logic;
+signal data_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_prev_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_nextaddress_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_i_s : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_j_s : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_onedge_S : std_logic_vector(0 to 2**CLUSTERBITS);
+signal minimal_energy_S : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+
+signal data_in_S : std_logic_vector(63 downto 0);
+signal precluster0_S : std_logic_vector(63 downto 0);
+signal data_first_S : std_logic := '0';
+signal data_last_S : std_logic := '0';
+signal data_in_onedge_S : std_logic := '0';
+
+signal energy_in_S : std_logic_vector(MINIMUMENERGYBITS downto 0);
+signal energy_out_S : std_logic_vector(MINIMUMENERGYBITS downto 0);
+signal energy_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal energy_read_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal energy_write_S : std_logic := '0';
+signal sum_energy_S : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+
+signal neighbours_write_S : std_logic;
+signal neighbours_data_in_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_data_out_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_data_prev_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal nNeighbours_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_write_address_S : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+signal neighbours_read_address_S : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+signal neighbours_size_S : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+
+signal overflow_S : std_logic := '0';
+signal passononecluster_S : std_logic;
+
+signal hitcounter_s : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal nPres_S : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal pre_i_s : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal pre_j_s : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal last_pre_S : std_logic := '0';
+
+signal prim_k_S : integer range 0 to 2**CLUSTERBITS-1;
+
+signal nClusters1_S : integer range 0 to 2**CLUSTERBITS-1;
+signal simLength_S : integer range 0 to 2**CLUSTERBITS-1;
+
+signal isAdded_write_S : std_logic;
+signal isAdded_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0) := (others => '0');
+signal isAdded_read_address_S : std_logic_vector(CLUSTERBITS-1 downto 0) := (others => '0');
+signal isAdded_data_in_S : std_logic_vector(CLUSTERBITS downto 0);
+signal isAdded_data_out_S : std_logic_vector(CLUSTERBITS downto 0);
+signal isAdded_k_S : std_logic_vector(CLUSTERBITS downto 0);
+
+signal nrofneighbours_s : integer range 0 to 2**CLUSTERBITS-1;
+signal prim_m_S : integer range 0 to 2**CLUSTERBITS-1;
+signal prim_j_s : integer range 0 to 2**CLUSTERBITS-1;
+--type similarities_type is array(0 to 2*(2**CLUSTERBITS)-1) of std_logic_vector(CLUSTERBITS-1 downto 0);
+--signal similarities_s : similarities_type;
+
+signal similarities_write_S : std_logic;
+signal similarities_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_data_in_S : std_logic_vector(CLUSTERBITS*2-1 downto 0);
+signal similarities_read_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_data_out_S : std_logic_vector(CLUSTERBITS*2-1 downto 0);
+signal similarities_source_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_destination_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+
+
+signal sec1_i_S : integer range 0 to 2**CLUSTERBITS-1;
+signal sec1_j_S : integer range 0 to 2**CLUSTERBITS-1;
+signal sec1_m_S : integer range 0 to 2**CLUSTERBITS-1;
+signal sec2_i_S : integer range 0 to 2**CLUSTERBITS-1;
+signal sec2_n_S : std_logic;
+signal nClusters2_S : integer range 0 to 2**MAXCLUSTERSBITS-1;
+
+signal result_diameter_S : std_logic_vector(9 downto 0);
+signal result_positionX_S : std_logic_vector(9 downto 0);
+signal result_positionY_S : std_logic_vector(9 downto 0);
+signal result_time_S : std_logic_vector(23 downto 0);
+signal result_index_S : integer range 0 to 2**CLUSTERBITS-1;
+signal result_nrofhits_S : std_logic_vector(9 downto 0);
+signal result_onedge_S : std_logic;
+
+signal results_write_address_S : std_logic_vector(MAXCLUSTERSBITS-1 downto 0);
+signal results_read_address_S : std_logic_vector(MAXCLUSTERSBITS-1 downto 0);
+signal results_data_in_S : std_logic_vector(CLUSTERBITS+63 downto 0);
+signal results_data_out_S : std_logic_vector(CLUSTERBITS+63 downto 0);
+signal results_write_S : std_logic;
+signal results_index_s : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal results_filled_S : std_logic;
+
+signal hitidx_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_data_in_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_read_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_data_out_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_write_S : std_logic;
+signal hitidx_index_S : integer range 0 to 2**CLUSTERBITS-1;
+signal hitidx_endaddress_s : integer range 0 to 2**CLUSTERBITS-1;
+
+signal hitidx_hitpointer_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_nrofprehits_S : integer range 0 to 1023 := 0;
+signal hitidx_nrofhits_S : integer range 0 to 1023 := 0;
+
+signal nrofclocks_S : integer range 0 to 16383;
+signal isAdded_int_in_S : integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+signal isAdded_int_out_S : integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+
+signal sort_readkey_s : std_logic;
+signal sort_ready_S : std_logic;
+type clustersortarray_type is array(0 to 2**MAXCLUSTERSBITS-1) of integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal clustersortarray_s : clustersortarray_type;
+signal sort_i_s : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal sort_j_s : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal sort_j_neg_S : std_logic;
+signal sort_key_S : std_logic_vector(23 downto 0) := (others => '0');
+
+signal data_out_S : std_logic_vector(63 downto 0);
+signal data_out_write_S : std_logic;
+signal data_out_first_S : std_logic;
+signal data_out_last_S : std_logic;
+
+
+--type isAdded_array is array(0 to 2**CLUSTERBITS-1) of integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+--signal debug_isAdded_S : isAdded_array;
+signal debug_error_S : std_logic;
+signal debug_minimal_energy_reached_S : std_logic;
+signal debug_sum_energy_S : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+
+begin
+
+
+dataerror <= error_S;
+data_in_allowed <= '1' when (state_S=INITIALIZE) or (state_S=COLLECT) else '0';
+busy <= '1' when (state_S/=INITIALIZE) else '0';
+data_in_write_S <= '1' when (data_in_write='1') and (data_in_first='0') else '0';
+minimal_energy_S <= minimal_energy;
+
+datamemory: blockmem
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS,
+ DATA_BITS => 64
+ )
+ port map(
+ clock => clock,
+ write_enable => data_in_write_S,
+ write_address => data_write_address_S,
+ data_in(63 downto 0) => data_in,
+ read_address => data_read_address_S,
+ data_out(63 downto 0) => data_in_S
+ );
+
+energymemory: blockmem
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS,
+ DATA_BITS => MINIMUMENERGYBITS+1
+ )
+ port map(
+ clock => clock,
+ write_enable => energy_write_S,
+ write_address => energy_write_address_S,
+ data_in => energy_in_S,
+ read_address => energy_read_address_S,
+ data_out => energy_out_S
+ );
+
+neighbours: blockmemdirectread
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS+2,
+ DATA_BITS => CLUSTERBITS
+ )
+ port map(
+ clock => clock,
+ write_enable => neighbours_write_S,
+ write_address => neighbours_write_address_S,
+ data_in => neighbours_data_in_S,
+ read_address => neighbours_read_address_S,
+ data_out => neighbours_data_out_S
+ );
+
+isAddedmem: blockmemdirectread
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS,
+ DATA_BITS => CLUSTERBITS+1
+ )
+ port map(
+ clock => clock,
+ write_enable => isAdded_write_S,
+ write_address => isAdded_write_address_S,
+ data_in => isAdded_data_in_S,
+ read_address => isAdded_read_address_S,
+ data_out => isAdded_data_out_S
+ );
+isAdded_int_in_S <= -1 when isAdded_data_in_S(CLUSTERBITS)='0' else conv_integer(unsigned(isAdded_data_in_S(CLUSTERBITS-1 downto 0)));
+isAdded_int_out_S <= -1 when isAdded_data_out_S(CLUSTERBITS)='0' else conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)));
+
+similarities: blockmemdirectread
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS,
+ DATA_BITS => CLUSTERBITS*2
+ )
+ port map(
+ clock => clock,
+ write_enable => similarities_write_S,
+ write_address => similarities_write_address_S,
+ data_in => similarities_data_in_S,
+ read_address => similarities_read_address_S,
+ data_out => similarities_data_out_S
+ );
+
+results: blockmemdirectread
+ generic map (
+ ADDRESS_BITS => MAXCLUSTERSBITS,
+ DATA_BITS => CLUSTERBITS+40+24
+ )
+ port map(
+ clock => clock,
+ write_enable => results_write_S,
+ write_address => results_write_address_S,
+ data_in => results_data_in_S,
+ read_address => results_read_address_S,
+ data_out => results_data_out_S
+ );
+
+hitidices: blockmem
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS,
+ DATA_BITS => CLUSTERBITS
+ )
+ port map(
+ clock => clock,
+ write_enable => hitidx_write_S,
+ write_address => hitidx_write_address_S,
+ data_in => hitidx_data_in_S,
+ read_address => hitidx_read_address_S,
+ data_out => hitidx_data_out_S
+ );
+
+data_read_address_S <=
+ (others => '0') when (state_S=COLLECT) else
+ conv_std_logic_vector(conv_integer(unsigned(data_read_address_i_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS)
+ when (state_S=PRE_READ0) else
+ data_read_address_i_S when (state_S=PRE_READ1) and (pre_j_S>=nPres_S-1) else
+ conv_std_logic_vector(conv_integer(unsigned(data_read_address_j_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS)
+ when (state_S=PRE_READ1) else
+
+
+ (others => '0') when (state_S=SECONDAIRY1) else
+ conv_std_logic_vector(conv_integer(unsigned(hitidx_hitpointer_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS) when (state_S=SECONDAIRY2) and (sec1_m_S<nPres_S-1) else
+ (others => '0') when (state_S=SECONDAIRY2) else
+ (others => '0') when (state_S=WRITESUPERBURST) else
+ hitidx_hitpointer_S when (state_S=WRITEONECLUSTER) else
+ hitidx_hitpointer_S when (state_S=WRITEONECLUSTERHITS) else
+
+ hitidx_data_out_S when (state_S=WRITECLUSTER) else
+ hitidx_data_out_S when (state_S=WRITEHITS0) else
+ hitidx_hitpointer_S when (state_S=WRITEHITS1) else
+ hitidx_data_out_S when (state_S=WRITEHITS) and (hitidx_nrofprehits_S<=1) else
+ hitidx_hitpointer_S when (state_S=WRITEHITS) else
+ (others => '0');
+
+energy_read_address_S <= isAdded_read_address_S; --//??
+
+isAdded_read_address_S <=
+-- conv_std_logic_vector(nPres_S,CLUSTERBITS) when (state_S=PRIMARY) and (neighbours_read_address_S>=neighbours_size_S) else
+ conv_std_logic_vector(nPres_S,CLUSTERBITS)-1 when (state_S=PRIMARY) and (not ((neighbours_read_address_S<neighbours_size_S) or ((neighbours_size_S=1) and (neighbours_read_address_S=1)))) else
+ conv_std_logic_vector(nPres_S,CLUSTERBITS)-1 when (state_S=PRIMARY) and (neighbours_read_address_S>=neighbours_size_S) else
+ conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY) and (conv_integer(unsigned(neighbours_data_out_S))=0) else
+ conv_std_logic_vector(prim_k_S,CLUSTERBITS) when (state_S=PRIMARY) else
+
+ neighbours_data_out_S when (state_S=PRIMARY1) else
+ neighbours_data_out_S when (state_S=PRIMARY1_0) and (prim_j_S<nrofneighbours_S-1) else
+
+ conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY1_0) and (prim_j_S>=nrofneighbours_S-1) else
+ neighbours_data_out_S when (state_S=PRIMARY2) else
+ neighbours_data_out_S when (state_S=PRIMARY2_0) and (prim_j_S<nrofneighbours_S-1) else
+ conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY2_0) and (prim_j_S>=nrofneighbours_S-1) else
+
+ conv_std_logic_vector(sec1_m_S,CLUSTERBITS) when (state_S=SECONDAIRY) else
+
+ (others => '0') when ((state_S=SECONDAIRY1) and ((simLength_S=0) or ((sec1_i_S=simLength_S-1) and (sec1_m_S=nPres_S-1)))) else
+ conv_std_logic_vector(sec1_m_S+1,CLUSTERBITS) when (state_S=SECONDAIRY1) and (sec1_m_S<nPres_S-1) and
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) else
+ (others => '0') when (state_S=SECONDAIRY1) else
+
+ conv_std_logic_vector(sec1_m_S,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) else
+
+ conv_std_logic_vector(sec1_m_S+1,CLUSTERBITS) when (state_S=SECONDAIRY2) and (sec1_m_S<nPres_S-1) else
+ (others => '0') when (state_S=SECONDAIRY2) and (sec1_m_S>=nPres_S) else
+
+ (others => '0');
+
+similarities_read_address_S <=
+ (others => '0') when (state_S=SECONDAIRY) else
+ conv_std_logic_vector(sec1_i_S,CLUSTERBITS) when (state_S=SECONDAIRY1) and (sec1_m_S<nPres_S-1) and
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) else
+ conv_std_logic_vector(sec1_i_S+1,CLUSTERBITS) when (state_S=SECONDAIRY1) else
+ conv_std_logic_vector(sec1_i_S,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) and (sec1_j_S=simLength_S-1) else
+ conv_std_logic_vector(sec1_j_S+1,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) else
+ (others => '0');
+
+results_read_address_S <=
+ conv_std_logic_vector(1,MAXCLUSTERSBITS) when (state_S=SECONDAIRY1) else
+ conv_std_logic_vector(clustersortarray_S(sort_i_S-1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='1') and (results_filled_S='1') and (sort_i_S<=results_write_address_S) else
+ conv_std_logic_vector(clustersortarray_S(sort_i_S),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='1') else
+ conv_std_logic_vector(clustersortarray_S(sort_j_S-1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='0') and (sort_j_S>0) and (sort_j_neg_S='0') and (results_data_out_S(30+23 downto 30)>sort_key_S) else
+ conv_std_logic_vector(clustersortarray_S(sort_i_S),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_i_S=2**MAXCLUSTERSBITS-1) else
+ conv_std_logic_vector(clustersortarray_S(sort_i_S+1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) else
+ conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITESUPERBURST else
+ conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITECLUSTER else
+ conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS0 else
+ conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS1 else
+ conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS else
+ (others => '0');
+
+hitidx_read_address_S <=
+--?? results_data_out_S(2*CLUSTERBITS+30+23 downto CLUSTERBITS+30+24) when (state_S=WRITESUPERBURST) else
+ results_data_out_S(CLUSTERBITS+63 downto 64) when (state_S=WRITECLUSTER) else
+ conv_std_logic_vector(hitidx_index_S,CLUSTERBITS) when (state_S=WRITEHITS0) else
+ conv_std_logic_vector(hitidx_index_S,CLUSTERBITS) when (state_S=WRITEHITS1) else
+ conv_std_logic_vector(hitidx_index_S+1,CLUSTERBITS) when (state_S=WRITEHITS) and (hitidx_nrofprehits_S<=1) else
+ conv_std_logic_vector(hitidx_index_S,CLUSTERBITS) when (state_S=WRITEHITS) else
+ (others => '0');
+
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ case state_S is
+ when INITIALIZE =>
+ for i in 0 to 2**MAXCLUSTERSBITS-1 loop
+ clustersortarray_S(i) <= i;
+ end loop;
+ when COLLECT =>
+ when PRE_READ0 =>
+ when PRE_READ1 =>
+
+ when SECONDAIRY1 =>
+ sort_i_S <= 1;
+ sort_readkey_S <= '1';
+ sort_ready_S <= '0';
+ -- results_read_address_S <= 1;
+ when SECONDAIRY2 | SORTING =>
+ -- for (int i = 1; i < nPreclusters; i++)
+ -- {
+ -- int key = clusters_time[clustersortarray[i]];
+ -- int j = i - 1;
+ -- while (j >= 0 && clusters_time[clustersortarray[j]] > key)
+ -- {
+ -- clustersortarray[j + 1] = clustersortarray[j];
+ -- j = j - 1;
+ -- }
+ -- clustersortarray[j + 1] = i;
+ -- }
+ if sort_readkey_S='1' then
+ if (results_filled_S='1') and (sort_i_S<=results_write_address_S) then
+ sort_key_S <= results_data_out_S(30+23 downto 30);
+ sort_readkey_S <= '0';
+ sort_j_S <= sort_i_S-1;
+ sort_j_neg_S <= '0';
+ -- results_read_address_S <= clustersortarray_S(sort_i_S-1);
+ else
+ -- results_read_address_S <= clustersortarray_S(sort_i_S);
+ if state_S=SORTING then
+ sort_ready_S <= '1';
+ end if;
+ end if;
+ else
+ if (sort_j_neg_S='0') and (results_data_out_S(30+23 downto 30)>sort_key_S) then
+ -- results_read_address_S <= clustersortarray_S(sort_j_S-1);
+ clustersortarray_S(sort_j_S+1) <= clustersortarray_S(sort_j_S);
+ if sort_j_S>0 then
+ sort_j_S <= sort_j_S-1;
+ sort_j_neg_S <= '0';
+ else
+ sort_j_neg_S <= '1';
+ end if;
+ else
+ -- results_read_address_S <= clustersortarray_S(sort_i_S+1);
+ if sort_j_neg_S='1' then
+ clustersortarray_S(0) <= sort_i_S;
+ else
+ clustersortarray_S(sort_j_S+1) <= sort_i_S;
+ end if;
+ if sort_i_S<2**MAXCLUSTERSBITS-1 then
+ sort_i_S <= sort_i_S+1;
+ else
+ sort_ready_S <= '1';
+ end if;
+ sort_readkey_S <= '1';
+ end if;
+ end if;
+ when others =>
+ end case;
+ stateprev_S <= state_S;
+ end if;
+end process;
+
+
+process(clock)
+file dfile: text;
+variable l : line;
+variable result_startaddress_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable result_nrofhits_V : std_logic_vector(9 downto 0);
+variable result_nrofclusters_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable result_nrhits_max_V : std_logic_vector(9 downto 0);
+variable result_Xpad_min_V : std_logic_vector(9 downto 0);
+variable result_Ypad_min_V : std_logic_vector(9 downto 0);
+variable result_Xpad_max_V : std_logic_vector(9 downto 0);
+variable result_Ypad_max_V : std_logic_vector(9 downto 0);
+variable result_diameter_V : std_logic_vector(10 downto 0);
+variable result_positionX_V : std_logic_vector(10 downto 0);
+variable result_positionY_V : std_logic_vector(10 downto 0);
+variable result_nrofhits_max_V : std_logic_vector(9 downto 0);
+variable result_time_max_V : std_logic_vector(23 downto 0);
+variable result_onedge_V : std_logic;
+variable sum_energy_V : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+variable minimal_energy_reached_V : std_logic;
+variable nClusters2_V : integer range 0 to 2**MAXCLUSTERSBITS-1 := 0;
+variable hitidx_write_address_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable diameter_V : std_logic_vector(9 downto 0);
+variable overflow_V : std_logic;
+variable pre0_x : std_logic_vector(9 downto 0);
+variable pre1_x : std_logic_vector(9 downto 0);
+variable pre0_y : std_logic_vector(9 downto 0);
+variable pre1_y : std_logic_vector(9 downto 0);
+variable pre_d : std_logic_vector(9 downto 0);
+--variable pre_r : std_logic_vector(9 downto 0);
+variable pre0_t : std_logic_vector(23 downto 0);
+variable pre1_t : std_logic_vector(23 downto 0);
+
+begin
+ if (rising_edge(clock)) then
+ error_S <= '0';
+ nextcluster <= '0';
+ energy_write_S <= '0';
+ neighbours_write_S <= '0';
+ isAdded_write_S <= '0';
+ data_out_write_S <= '0';
+ data_out_first_S <= '0';
+ data_out_last_S <= '0';
+ similarities_write_S <= '0';
+ results_write_S <= '0';
+ hitidx_write_S <= '0';
+ case state_S is
+ when INITIALIZE =>
+ data_first_S <= '0';
+ data_last_S <= '0';
+ nPres_S <= 0;
+ hitcounter_S <= 0;
+ nClusters1_S <= 0;
+ nClusters2_S <= 0;
+ simLength_S <= 0;
+ results_index_S <= 0;
+ last_pre_S <= '0';
+ data_in_onedge_S <= '0';
+ passononecluster_S <= '0';
+ sum_energy_S <= (others => '0');
+ neighbours_size_S <= (others => '0');
+ data_write_address_S <= (others => '0');
+ data_read_nextaddress_S <= (others => '0');
+ hitidx_hitpointer_S <= (others => '0');
+ if (data_in_write='1') and (data_in_first='1') then
+ data_out_S <= data_in;
+ data_first_S <= '1';
+ end if;
+ if (data_in_write='1') and (data_in_last='1') then
+ data_last_S <= '1';
+ end if;
+ if data_in_active='1' then
+ state_S <= COLLECT;
+ if data_in_write_S='1' then
+ data_write_address_S(0) <= '1';
+ hitcounter_S <= conv_integer(unsigned(data_in(CLUSTERBITS-1 downto 0)));
+ if conv_integer(unsigned(data_in(CLUSTERBITS-1 downto 0)))=0 then
+ error_S <= '1';
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ nextcluster <= '1';
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ end if;
+ nPres_S <= 1;
+ end if;
+ elsif data_in_write='1' then -- empty superburst
+ if (data_in_first='0') or (data_in_last='0') then
+ error_S <= '1';
+ end if;
+ state_S <= WRITESUPERBURST;
+ end if;
+ overflow_S <= '0';
+ isAdded_data_in_S <= (others => '0');
+ if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= isAdded_write_address_S+1;
+ end if;
+ when COLLECT =>
+ pre_i_S <= 0;
+ nNeighbours_S <= (others => '0');
+ data_read_address_i_S <= (others => '0');
+ if (data_in_write='1') and (data_in_first='1') then
+ data_first_S <= '1';
+ data_out_S <= data_in;
+ end if;
+ if (data_in_write='1') and (data_in_last='1') then
+ data_last_S <= '1';
+ end if;
+ if data_in_active='0' then
+ if hitcounter_S/=0 then
+ error_S <= '1';
+ if nPres_S>0 then
+ nPres_S <= nPres_S-1;
+ else
+ end if;
+ end if;
+ if (nPres_S=0) then
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ elsif nPres_S=1 then
+ if (SKIPSINGLEHITCLUSTERS=TRUE) and (sum_energy_S/=ONES(MINIMUMENERGYBITS-1 downto 0)) then
+ nPres_S <= 0;
+ else
+ passononecluster_S <= '1';
+ end if;
+ state_S <= WRITESUPERBURST;
+ else
+ data_onedge_S(nPres_S-1) <= data_in_onedge_S;
+ energy_write_address_S <= conv_std_logic_vector(nPres_S-1,CLUSTERBITS);
+ energy_in_S <= data_in_onedge_S & sum_energy_S;
+ energy_write_S <= '1';
+ state_S <= PRE_READ0;
+ end if;
+ else
+ if data_in_write_S='1' then
+ if data_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+ data_write_address_S <= data_write_address_S+1;
+ else
+ overflow_S <= '1';
+ end if;
+ if hitcounter_S=0 then
+ hitcounter_S <= conv_integer(unsigned(data_in(CLUSTERBITS-1 downto 0)));
+ if nPres_S>0 then
+ data_onedge_S(nPres_S-1) <= data_in_onedge_S; --//
+ energy_write_address_S <= conv_std_logic_vector(nPres_S-1,CLUSTERBITS);
+ energy_in_S <= data_in_onedge_S & sum_energy_S;
+ energy_write_S <= '1';
+ sum_energy_S <= (others => '0');
+ end if;
+ nPres_S <= nPres_S+1;
+ else
+ if conv_integer(unsigned(data_in(15 downto 0)))+conv_integer(unsigned(sum_energy_S))<conv_integer(unsigned(minimal_energy_S)) then
+ sum_energy_S <= conv_std_logic_vector(conv_integer(unsigned(data_in(15 downto 0)))+conv_integer(unsigned(sum_energy_S)),MINIMUMENERGYBITS);
+ else
+ sum_energy_S <= (others => '1');
+ end if;
+ if data_in_onedge='1' then
+ data_in_onedge_S <= '1';
+ end if;
+ hitcounter_S <= hitcounter_S-1;
+ end if;
+ end if;
+ end if;
+ isAdded_data_in_S <= (others => '0');
+ if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= isAdded_write_address_S+1;
+ end if;
+ when PRE_READ0 =>
+ prim_k_S <= 0;
+ -- for (int iClus = 0; iClus < nPres - 1; iClus++) {
+ -- int nNeighbours = 0; // #neighbouring preclusters, reset nNeighbours
+ -- neighbours[neighbours_size++] = 0;
+ -- for (int j = iClus + 1; j < nPres; j++) {
+ -- if ((abs(fPreclusterArray[iClus].Xpos - fPreclusterArray[j].Xpos) <= 1+(fPreclusterArray[iClus].diameter + fPreclusterArray[j].diameter + 1) / 2) && (abs(fPreclusterArray[iClus].time - fPreclusterArray[j].time) <= deltaT)) {
+ -- neighbours[neighbours_size++] = j;
+ -- nNeighbours++;
+ -- }
+ -- }
+ -- neighbours[neighbours_size - (nNeighbours + 1)] = nNeighbours; // write nr of neighbours to the appropiate entry in neighbours2[]
+ -- }
+ neighbours_read_address_S <= (others => '0');
+ precluster0_S <= data_in_S;
+ pre_j_S <= pre_i_S+1;
+ isAdded_data_in_S <= (others => '0');
+ neighbours_write_address_S <= conv_std_logic_vector(conv_integer(unsigned(neighbours_size_S))-(conv_integer(unsigned(nNeighbours_S))+1),CLUSTERBITS+2);
+ neighbours_data_in_S <= nNeighbours_S;
+ if stateprev_S/=COLLECT then
+ neighbours_write_S <= '1';
+ end if;
+ nNeighbours_S <= (others => '0');
+ if last_pre_S='1' then
+ if (neighbours_size_S>0) then
+ neighbours_read_address_S(0) <= '1';
+ end if;
+ state_S <= PRIMARY;
+ else
+ neighbours_size_S <= neighbours_size_S+1;
+ state_S <= PRE_READ1;
+ end if;
+ data_read_address_i_S <= conv_std_logic_vector(conv_integer(unsigned(data_read_address_i_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS);
+ data_read_address_j_S <= conv_std_logic_vector(conv_integer(unsigned(data_read_address_i_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS);
+ when PRE_READ1 =>
+ neighbours_read_address_S <= (others => '0');
+ if pre_j_S<nPres_S-1 then
+ pre_j_S <= pre_j_S+1;
+ data_read_address_j_S <= conv_std_logic_vector(conv_integer(unsigned(data_read_address_j_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS);
+ else
+ if pre_i_S+1>=nPres_S-1 then
+ last_pre_S <= '1';
+ end if;
+ pre_i_S <= pre_i_S+1;
+ state_S <= PRE_READ0;
+ end if;
+ pre0_x := precluster0_S(29 downto 20);
+ pre1_x := data_in_S(29 downto 20);
+ pre0_y := precluster0_S(19 downto 10);
+ pre1_y := data_in_S(19 downto 10);
+ pre_d := precluster0_S(39 downto 30) + data_in_S(39 downto 30);
+ pre0_t := precluster0_S(63 downto 40);
+ pre1_t := data_in_S(63 downto 40);
+ if (((pre0_x>=pre1_x) and (pre0_x-pre1_x <= pre_d)) or ((pre0_x<pre1_x) and (pre1_x-pre0_x <= pre_d))) and
+ (((pre0_y>=pre1_y) and (pre0_y-pre1_y <= pre_d)) or ((pre0_y<pre1_y) and (pre1_y-pre0_y <= pre_d))) and
+ (((pre0_t>=pre1_t) and (pre0_t-pre1_t <= timedifference)) or ((pre0_t<pre1_t) and (pre1_t-pre0_t <= timedifference))) then
+ neighbours_write_address_S <= neighbours_size_S;
+ neighbours_size_S <= neighbours_size_S+1;
+ nNeighbours_S <= nNeighbours_S+1;
+ neighbours_data_in_S <= conv_std_logic_vector(pre_j_S,CLUSTERBITS);
+ neighbours_write_S <= '1';
+ end if;
+ when PRIMARY =>
+ sec1_i_S <= 0;
+ sec1_m_S <= 0;
+ if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+ isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters1_S,CLUSTERBITS);
+ isAdded_write_address_S <= conv_std_logic_vector(prim_k_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ nrofneighbours_S <= conv_integer(unsigned(neighbours_data_out_S));
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ if conv_integer(unsigned(neighbours_data_out_S))>0 then
+ prim_j_S <= 0;
+ state_S <= PRIMARY1;
+ else
+ prim_k_S <= prim_k_S+1;
+ nClusters1_S <= nClusters1_S+1;
+ end if;
+ else
+ nrofneighbours_S <= conv_integer(unsigned(neighbours_data_out_S));
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ if conv_integer(unsigned(neighbours_data_out_S))>0 then
+ prim_j_S <= 0;
+ state_S <= PRIMARY2;
+ else
+ --????
+ prim_k_S <= prim_k_S+1;
+ end if;
+ end if;
+ if (neighbours_read_address_S>=neighbours_size_S) then
+ state_S <= SECONDAIRY;
+ end if;
+ when PRIMARY1 =>
+ prim_m_S <= conv_integer(unsigned(neighbours_data_out_S));
+ if (nrofneighbours_S>1) then
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ neighbours_data_prev_S <= neighbours_data_out_S;
+ state_S <= PRIMARY1_0;
+ when PRIMARY1_0 =>
+ if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+ isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters1_S,CLUSTERBITS);
+ isAdded_write_address_S <= neighbours_data_prev_S; -- conv_std_logic_vector(prim_m_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ elsif conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))/=nClusters1_S then
+ if nClusters1_S>conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0))) then
+ similarities_data_in_S <= conv_std_logic_vector(nClusters1_S,CLUSTERBITS) & isAdded_data_out_S(CLUSTERBITS-1 downto 0);
+ else
+ similarities_data_in_S <= isAdded_data_out_S(CLUSTERBITS-1 downto 0) & conv_std_logic_vector(nClusters1_S,CLUSTERBITS);
+ end if;
+ similarities_write_S <= '1';
+ similarities_write_address_S <= conv_std_logic_vector(simLength_S,CLUSTERBITS);
+ simLength_S <= simLength_S+1;
+ end if;
+ neighbours_data_prev_S <= neighbours_data_out_S;
+ if prim_j_S+2/=nrofneighbours_S then
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ if (nrofneighbours_S>1) and (prim_j_S<nrofneighbours_S-1) then
+ prim_j_S <= prim_j_S+1;
+ else
+ nClusters1_S <= nClusters1_S+1;
+ prim_k_S <= prim_k_S+1;
+ state_S <= PRIMARY;
+ end if;
+ when PRIMARY2 =>
+ prim_m_S <= conv_integer(unsigned(neighbours_data_out_S));
+ if (nrofneighbours_S>1) then
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ isAdded_k_S <= isAdded_data_out_S;
+ neighbours_data_prev_S <= neighbours_data_out_S;
+ state_S <= PRIMARY2_0;
+ when PRIMARY2_0 =>
+ if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+ isAdded_data_in_S <= isAdded_k_S;
+ isAdded_write_address_S <= neighbours_data_prev_S; -- conv_std_logic_vector(prim_m_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ elsif isAdded_data_out_S/=isAdded_k_S then --hier verder
+ if isAdded_k_S(CLUSTERBITS-1 downto 0)>isAdded_data_out_S(CLUSTERBITS-1 downto 0) then
+ similarities_data_in_S <= isAdded_k_S(CLUSTERBITS-1 downto 0) & isAdded_data_out_S(CLUSTERBITS-1 downto 0);
+ else
+ similarities_data_in_S <= isAdded_data_out_S(CLUSTERBITS-1 downto 0) & isAdded_k_S(CLUSTERBITS-1 downto 0);
+ end if;
+ similarities_write_S <= '1';
+ similarities_write_address_S <= conv_std_logic_vector(simLength_S,CLUSTERBITS);
+ simLength_S <= simLength_S+1;
+ end if;
+ neighbours_data_prev_S <= neighbours_data_out_S;
+ if prim_j_S+2/=nrofneighbours_S then
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ if (nrofneighbours_S>1) and (prim_j_S<nrofneighbours_S-1) then
+ prim_j_S <= prim_j_S+1;
+ else
+ prim_k_S <= prim_k_S+1;
+ state_S <= PRIMARY;
+ end if;
+ when SECONDAIRY =>
+ sec1_i_S <= 0;
+ sec1_m_S <= 0;
+ if (isAdded_data_out_S(CLUSTERBITS)='0') then
+ isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters1_S,CLUSTERBITS);
+ isAdded_write_address_S <= conv_std_logic_vector(nPres_S-1,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ nClusters1_S <= nClusters1_S+1;
+ end if;
+ state_S <= SECONDAIRY1;
+ when SECONDAIRY1 =>
+ results_filled_S <= '0';
+ results_write_address_S <= (others => '1');
+ hitidx_write_address_S <= (others => '1');
+ hitidx_write_address_V := (others => '1');
+ result_startaddress_V := (others => '0');
+ result_nrofhits_V := (others => '0');
+ result_nrofclusters_V := (others => '0');
+ result_Xpad_min_V := (others => '1');
+ result_Ypad_min_V := (others => '1');
+ result_Xpad_max_V := (others => '0');
+ result_Ypad_max_V := (others => '0');
+ result_nrhits_max_V := (others => '0');
+ result_time_max_V := (others => '0');
+ result_onedge_V := '0';
+ minimal_energy_reached_V := '0';
+ sum_energy_V := (others => '0');
+ sec1_j_S <= sec1_i_S+1;
+ sec2_i_S <= 0;
+ sec2_n_S <= '0';
+ nClusters2_S <= 0;
+ nClusters2_V := 0;
+ hitidx_hitpointer_S <= (others => '0');
+ if (isAdded_data_out_S(CLUSTERBITS-1 downto 0)=similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)) and
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0))
+ then -- filled bit not set
+ isAdded_data_in_S <= '1' & similarities_data_out_S(CLUSTERBITS-1 downto 0);
+ isAdded_write_address_S <= conv_std_logic_vector(sec1_m_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ end if;
+ if (sec1_m_S<nPres_S-1) and (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) then
+ sec1_m_S <= sec1_m_S+1;
+ else
+ sec1_i_S <= sec1_i_S+1;
+ sec1_m_S <= 0;
+ end if;
+
+ if (simLength_S=0) or ((sec1_i_S=simLength_S-1) and ((sec1_m_S=nPres_S-1) or
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)=similarities_data_out_S(CLUSTERBITS-1 downto 0)))) then
+ sec1_m_S <= 0;
+ state_S <= SECONDAIRY2;
+ elsif (sec1_m_S=nPres_S-1) and
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) then
+ similarities_source_S <= similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS);
+ similarities_destination_S <= similarities_data_out_S(CLUSTERBITS-1 downto 0);
+ sec1_m_S <= 0;
+ state_S <= ADJUSTSIMULARITIES;
+ end if;
+ when ADJUSTSIMULARITIES =>
+ similarities_data_in_S <= similarities_data_out_S;
+ similarities_write_address_S <= conv_std_logic_vector(sec1_j_S,CLUSTERBITS);
+ if similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)=similarities_source_S then
+ similarities_data_in_S(CLUSTERBITS*2-1 downto CLUSTERBITS) <= similarities_destination_S;
+ similarities_write_S <= '1';
+ end if;
+ if similarities_data_out_S(CLUSTERBITS-1 downto 0)=similarities_source_S then
+ similarities_data_in_S(CLUSTERBITS-1 downto 0) <= similarities_destination_S;
+ similarities_write_S <= '1';
+ end if;
+ if sec1_j_S<simLength_S-1 then
+ sec1_j_S <= sec1_j_S+1;
+ else
+ sec1_j_S <= sec1_i_S+1;
+ state_S <= SECONDAIRY1;
+ end if;
+ when SECONDAIRY2 =>
+ overflow_V := '0';
+ results_index_S <= 0;
+ if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S then
+ sec2_n_S <= '1';
+ isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters2_S,CLUSTERBITS);
+ isAdded_write_address_S <= conv_std_logic_vector(sec1_m_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ end if;
+ if (nClusters1_S>0) then
+ if sec1_m_S<nPres_S-1 then
+ sec1_m_S <= sec1_m_S+1;
+ -- data_read_address_S <= hitidx_hitpointer_S+data_in_S(9 downto 0)+1
+ hitidx_hitpointer_S <= conv_std_logic_vector(conv_integer(unsigned(hitidx_hitpointer_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS);
+ else
+ -- data_read_address_S <= (others => '0');
+ hitidx_hitpointer_S <= (others => '0');
+ sec1_m_S <= 0;
+ sec2_i_S <= sec2_i_S+1;
+ if (sec2_n_S='1') or (conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S) then
+ if nClusters2_S<2**MAXCLUSTERSBITS-1 then
+ nClusters2_S <= nClusters2_S+1;
+ else
+ error_S <= '1';
+ end if;
+ end if;
+ sec2_n_S <= '0';
+ end if;
+ end if;
+
+ if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S then
+ result_nrofhits_V := result_nrofhits_V+data_in_S(9 downto 0);
+ result_nrofclusters_V := result_nrofclusters_V+1;
+ diameter_V := data_in_S(39 downto 30);
+ if data_in_S(29 downto 20)>diameter_V then
+ if data_in_S(29 downto 20)-diameter_V<=result_Xpad_min_V then
+ result_Xpad_min_V := data_in_S(29 downto 20)-diameter_V;
+ end if;
+ else
+ result_Xpad_min_V := (others => '0');
+ end if;
+ if data_in_S(19 downto 10)>diameter_V then
+ if data_in_S(19 downto 10)-diameter_V<=result_Ypad_min_V then
+ result_Ypad_min_V := data_in_S(19 downto 10)-diameter_V;
+ end if;
+ else
+ result_Ypad_min_V := (others => '0');
+ end if;
+ if data_in_S(29 downto 20)+diameter_V>result_Xpad_max_V then
+ result_Xpad_max_V := data_in_S(29 downto 20)+diameter_V;
+ end if;
+ if data_in_S(19 downto 10)+diameter_V>result_Ypad_max_V then
+ result_Ypad_max_V := data_in_S(19 downto 10)+diameter_V;
+ end if;
+ if data_in_S(9 downto 0)>result_nrhits_max_V then
+ result_nrhits_max_V := data_in_S(9 downto 0);
+ result_time_max_V := data_in_S(63 downto 40);
+ end if;
+ if data_onedge_S(sec1_m_S)='1' then
+ result_onedge_V := '1';
+ end if;
+ if (minimal_energy_reached_V='0') and (conv_integer(unsigned(sum_energy_V))+conv_integer(unsigned(energy_out_S(MINIMUMENERGYBITS-1 downto 0)))<conv_integer(unsigned(minimal_energy_S))) then
+ sum_energy_V := sum_energy_V+energy_out_S(MINIMUMENERGYBITS-1 downto 0);
+ else
+ minimal_energy_reached_V := '1';
+ end if;
+ hitidx_data_in_S <= data_read_address_prev_S;
+ hitidx_write_address_S <= hitidx_write_address_S+1;
+ hitidx_write_address_V := hitidx_write_address_S+1;
+ hitidx_write_S <='1';
+ end if;
+ if (nClusters1_S>0) then
+ if sec1_m_S<nPres_S-1 then
+ else
+ if (sec2_n_S='1') or (conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S)
+-- or
+-- ((sec2_i_S=nClusters1_S-1) and (sec1_m_S=nPres_S-1))
+ then
+ if result_Xpad_max_V-result_Xpad_min_V>result_Ypad_max_V-result_Ypad_min_V then
+ result_diameter_V := ('0' & result_Xpad_max_V)-('0' & result_Xpad_min_V);
+ else
+ result_diameter_V := ('0' & result_Ypad_max_V)-('0' & result_Ypad_min_V);
+ end if;
+ result_diameter_S <= result_diameter_V(10 downto 1);
+ result_time_S <= result_time_max_V;
+ result_positionX_V := ('0'&result_Xpad_min_V)+('0'&result_Xpad_max_V);
+ result_positionX_S <= result_positionX_V(10 downto 1);
+ result_positionY_V := ('0'&result_Ypad_min_V)+('0'&result_Ypad_max_V);
+ result_positionY_S <= result_positionY_V(10 downto 1);
+ result_nrofhits_S <= result_nrofhits_V;
+ result_onedge_S <= result_onedge_V;
+ results_data_in_S <= result_startaddress_V & result_nrofhits_V & result_time_max_V & result_diameter_V(10 downto 1) & result_positionX_V(10 downto 1) & result_positionY_V(10 downto 1);
+ if (result_onedge_V='1') or (SKIPSINGLEHITCLUSTERS=FALSE) or (minimal_energy_reached_V='1') then -- or (result_nrofhits_V>1)
+ results_write_S <= '1';
+ if (conv_integer(unsigned(results_write_address_S))<(2**MAXCLUSTERSBITS-1)) or (results_filled_S='0') then --// and (sec1_i_S<31) then
+ results_write_address_S <= results_write_address_S+1;
+ else
+ overflow_V := '1';
+ end if;
+ results_filled_S <= '1';
+ result_startaddress_V := hitidx_write_address_V+1;
+ if nClusters2_V<2**MAXCLUSTERSBITS-1 then
+ nClusters2_V := nClusters2_V+1;
+ end if;
+ else
+if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))/=sec2_i_S then
+ hitidx_write_address_S <= hitidx_write_address_V-result_nrofclusters_V;
+end if;
+ end if;
+ end if;
+ result_nrofhits_V := (others => '0');
+ result_nrofclusters_V := (others => '0');
+ result_Xpad_min_V := (others => '1');
+ result_Ypad_min_V := (others => '1');
+ result_Xpad_max_V := (others => '0');
+ result_Ypad_max_V := (others => '0');
+ result_nrhits_max_V := (others => '0');
+ result_time_max_V := (others => '0');
+ result_onedge_V := '0';
+ minimal_energy_reached_V := '0';
+ sum_energy_V := (others => '0');
+ end if;
+ end if;
+
+ if ((sec2_i_S=nClusters1_S-1) and (sec1_m_S=nPres_S-1)) or (nClusters1_S=0) then
+ nPres_S <= nClusters2_V;
+ if (nClusters2_V<=1) then
+ hitidx_hitpointer_S <= (others => '0');
+ nClusters2_S <= nClusters2_V;
+ state_S <= WRITESUPERBURST;
+ else
+ nClusters2_S <= nClusters2_V;
+ state_S <= SORTING;
+ end if;
+ elsif overflow_V='1' then
+ nPres_S <= nClusters2_V;
+ error_S <= '1';
+ overflow_S <= '1';
+ state_S <= SORTING;
+ end if;
+ when SORTING =>
+ hitidx_hitpointer_S <= (others => '0');
+ results_index_S <= 0;
+ if sort_ready_S='1' then
+ state_S <= WRITESUPERBURST;
+ end if;
+-- if (((sort_readkey_S='0') and (sort_i_S>=results_write_address_S-1)) and
+-- ((sort_j_neg_S='1') or (results_data_out_S(30+23 downto 30)<=sort_key_S))) or
+-- ((sort_readkey_S='1') and (sort_i_S>=results_write_address_S) and (stateprev_S/=SECONDAIRY2)) then
+-- state_S <= WRITESUPERBURST;
+-- end if;
+ when WRITESUPERBURST =>
+ -- results_read_address_S <= clustersortarray_S(0)
+ hitidx_hitpointer_S <= (others => '0');
+ sec1_m_S <= 0;
+ results_index_S <= 0;
+ if (data_out_clusterallowed='1') then
+ data_out_first_S <= data_first_S;
+ data_out_write_S <= data_first_S;
+ if (nPres_S=0) then
+ data_out_last_S <= data_last_S;
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ nextcluster <= '1';
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ elsif (passononecluster_S='1') then
+ state_S <= WRITEONECLUSTER;
+ hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+ else
+ state_S <= WRITECLUSTER;
+ end if;
+ end if;
+ when WRITEONECLUSTER =>
+ -- data_read_address_S <= data_read_address_S+1;
+ data_out_S <= data_in_S(63 downto 0);
+ data_out_write_S <= '1';
+ hitidx_nrofprehits_S <= conv_integer(unsigned(data_in_S(9 downto 0)));
+ hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+ state_S <= WRITEONECLUSTERHITS;
+ when WRITEONECLUSTERHITS =>
+ -- data_read_address_S <= data_read_address_S+1;
+ data_write_address_S <= (others => '0');
+ data_out_S <= data_in_S(63 downto 0);
+ data_out_write_S <= '1';
+ hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+ if hitidx_nrofprehits_S>1 then
+ hitidx_nrofprehits_S <= hitidx_nrofprehits_S-1;
+ else
+ if data_last_S='1' then
+ data_out_last_S <= '1';
+ end if;
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ nextcluster <= '1';
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ end if;
+ when WRITECLUSTER => -- results_data_out_S available
+ -- data_read_address_S <= hitidx_data_out_S;
+ -- results_read_address_S <= clustersortarray_S(results_index_S)
+ -- hitidx_read_address_S <= results_data_out_S(CLUSTERBITS+63 downto 64);
+ if results_index_S<2**MAXCLUSTERSBITS-1 then
+ results_index_S <= results_index_S+1;
+ end if;
+ data_out_S <= (others => '0');
+ data_out_S(63 downto 40) <= results_data_out_S(53 downto 30); -- time 24 bits
+ data_out_S(39 downto 30) <= results_data_out_S(29 downto 20); -- diameter 10bits
+ data_out_S(29 downto 20) <= results_data_out_S(19 downto 10); -- X 10bits
+ data_out_S(19 downto 10) <= results_data_out_S(9 downto 0); -- Y 10bits
+ data_out_S(9 downto 0) <= results_data_out_S(63 downto 54); -- number of hits 10bits
+ data_out_write_S <= '1';
+ hitidx_nrofhits_S <= conv_integer(unsigned(results_data_out_S(63 downto 54)));
+ hitidx_index_S <= conv_integer(unsigned(results_data_out_S(CLUSTERBITS+63 downto 64)));
+ state_S <= WRITEHITS0;
+ when WRITEHITS0 => -- hitidx_data_out_S available
+ -- data_read_address_S <= hitidx_data_out_S;
+ -- results_read_address_S <= clustersortarray_S(results_index_S)
+ -- hitidx_read_address_S <= hitidx_index_S;
+ hitidx_hitpointer_S <= hitidx_data_out_S+1;
+ hitidx_index_S <= hitidx_index_S+1;
+ state_S <= WRITEHITS1;
+ when WRITEHITS1 => -- clusterdata available
+ -- data_read_address_S <= hitidx_hitpointer_S;
+ -- results_read_address_S <= clustersortarray_S(results_index_S)
+ -- hitidx_read_address_S <= hitidx_index_S;
+ hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+ if conv_integer(unsigned(data_in_S(9 downto 0)))>0 then
+ hitidx_nrofprehits_S <= conv_integer(unsigned(data_in_S(9 downto 0)));
+ else
+ hitidx_nrofprehits_S <= 1;
+ end if;
+ state_S <= WRITEHITS;
+ when WRITEHITS =>
+ -- data_read_address_S <= hitidx_hitpointer_S;
+ -- results_read_address_S <= clustersortarray_S(results_index_S)
+ -- hitidx_read_address_S <= hitidx_index_S;
+ hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+ data_out_S <= data_in_S(63 downto 0);
+ data_out_write_S <= '1';
+ if hitidx_nrofprehits_S>1 then
+ hitidx_nrofprehits_S <= hitidx_nrofprehits_S-1;
+ else
+ if hitidx_nrofhits_S>1 then
+ hitidx_hitpointer_S <= hitidx_data_out_S+1;
+ hitidx_index_S <= hitidx_index_S+1;
+ -- data_read_address_S <= hitidx_data_out_S;
+ -- hitidx_read_address_S <= hitidx_index_S+1;
+ state_S <= WRITEHITS1;
+ else -- all hits in output cluster processed
+ if results_index_S<nClusters2_S then
+ state_S <= WRITECLUSTER;
+ else
+ if data_last_S='1' then
+ data_out_last_S <= '1';
+ end if;
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ nextcluster <= '1';
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ end if;
+ end if;
+ end if;
+ hitidx_nrofhits_S <= hitidx_nrofhits_S-1;
+ when others =>
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ end case;
+ if reset='1' then
+ data_first_S <= '0';
+ data_last_S <= '0';
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ end if;
+ data_read_address_prev_S <= data_read_address_S;
+ debug_minimal_energy_reached_S <= minimal_energy_reached_V;
+ debug_sum_energy_S <= sum_energy_V;
+ end if;
+end process;
+
+data_out_write <= data_out_write_S;
+data_out_last <= '1' when (data_out_last_S='1') and (data_out_write_S='1') else '0';
+data_out_first <= '1' when (data_out_first_S='1') and (data_out_write_S='1') else '0';
+data_out <= data_out_S;
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0) := (others => '0');
+variable clusterresult_V : std_logic := '0';
+variable same_superburst_V : std_logic := '0';
+variable nrofhits_V : std_logic_vector(9 downto 0) := (others => '0');
+variable hitscounter_V : std_logic_vector(9 downto 0) := (others => '0');
+variable prev_resulttime_V : std_logic_vector(23 downto 0) := (others => '0');
+variable prev_hittime_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ debug_error_S <= '0';
+ if data_out_write_S='1' then
+ if data_out_first_S='1' then
+ if data_out_S(30 downto 0) < prev_superburst_V then
+ debug_error_S <= '1';
+ end if;
+ if data_out_S(30 downto 0)=prev_superburst_V then
+ same_superburst_V := '1';
+ else
+ same_superburst_V := '0';
+ end if;
+ prev_superburst_V := data_out_S(30 downto 0);
+ clusterresult_V := '1';
+ elsif clusterresult_V='1' then
+ if hitscounter_V/=nrofhits_V then
+ debug_error_S <= '1';
+ end if;
+ nrofhits_V := data_out_S(9 downto 0);
+ if (same_superburst_V='1') and (prev_resulttime_V>data_out_S(63 downto 40)) then
+ debug_error_S <= '1';
+ end if;
+ same_superburst_V := '1';
+ prev_resulttime_V := data_out_S(63 downto 40);
+ hitscounter_V := (others => '0');
+ prev_hittime_V := (others => '0');
+ clusterresult_V := '0';
+ else
+ if data_out_last_S='1' then
+ if hitscounter_V/=nrofhits_V-1 then
+ debug_error_S <= '1';
+ end if;
+ end if;
+ if data_out_S(63 downto 40)<prev_hittime_V then
+-- debug_error_S <= '1';
+ end if;
+ prev_hittime_V := data_out_S(63 downto 40);
+ if hitscounter_V=nrofhits_V-1 then
+ clusterresult_V := '1';
+ end if;
+ hitscounter_V := hitscounter_V+1;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if state_S=INITIALIZE then
+ nrofclocks_S <= 0;
+ else
+ nrofclocks_S <= nrofclocks_S+1;
+ end if;
+ end if;
+end process;
+
+--process(clock)
+--begin
+-- if (rising_edge(clock)) then
+-- if isAdded_write_S='1' then
+-- if isAdded_data_in_S(CLUSTERBITS)='0' then
+-- debug_isAdded_S(conv_integer(unsigned(isAdded_write_address_S))) <= -1;
+-- else
+-- debug_isAdded_S(conv_integer(unsigned(isAdded_write_address_S))) <= conv_integer(unsigned(isAdded_data_in_S(CLUSTERBITS-1 downto 0)));
+-- end if;
+-- end if;
+-- end if;
+--end process;
+--
+--process(clock)
+--begin
+-- if (rising_edge(clock)) then
+-- if similarities_write_S='1' then
+-- similarities_s(conv_integer(unsigned(similarities_write_address_S))*2) <= similarities_data_in_S(CLUSTERBITS*2-1 downto CLUSTERBITS);
+-- similarities_s(conv_integer(unsigned(similarities_write_address_S))*2+1) <= similarities_data_in_S(CLUSTERBITS-1 downto 0);
+-- end if;
+-- end if;
+--end process;
+
+--testword0(4 downto 0) <=
+testword0(115 downto 111) <=
+ "00000" when state_S=INITIALIZE else
+ "00001" when state_S=COLLECT else
+ "00010" when state_S=PRE_READ0 else
+ "00011" when state_S=PRE_READ1 else
+ "00100" when state_S=PRIMARY else
+ "00101" when state_S=PRIMARY1 else
+ "00110" when state_S=PRIMARY1_0 else
+ "00111" when state_S=PRIMARY2 else
+ "01000" when state_S=PRIMARY2_0 else
+ "01001" when state_S=SECONDAIRY else
+ "01010" when state_S=SECONDAIRY1 else
+ "01011" when state_S=ADJUSTSIMULARITIES else
+ "01100" when state_S=SECONDAIRY2 else
+ "01101" when state_S=SORTING else
+ "01110" when state_S=WRITESUPERBURST else
+ "01111" when state_S=WRITEONECLUSTER else
+ "10000" when state_S=WRITEONECLUSTERHITS else
+ "10001" when state_S=WRITECLUSTER else
+ "10010" when state_S=WRITEHITS0 else
+ "10011" when state_S=WRITEHITS1 else
+ "10100" when state_S=WRITEHITS else
+ "11111";
+--testword0(5) <= data_in_write;
+--testword0(6) <= error_S;
+--testword0(7) <= data_out_clusterallowed;
+
+testword0(63 downto 0) <= data_in;
+testword0(64) <= data_in_first;
+testword0(65) <= data_in_last;
+testword0(66) <= data_in_write;
+testword0(67) <= data_in_active;
+testword0(68) <= data_in_onedge;
+testword0(79 downto 70) <= conv_std_logic_vector(sec2_i_S,10);
+testword0(89 downto 80) <= conv_std_logic_vector(nClusters1_S,10);
+testword0(99 downto 90) <= conv_std_logic_vector(sec1_m_S,10);
+testword0(109 downto 100) <= conv_std_logic_vector(nPres_S,10);
+
+testword0(116) <= error_S;
+testword0(MAXCLUSTERSBITS+116 downto 117) <= results_write_address_S;
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 19-08-2016
+-- Module Name: CN_cluster_findgap
+-- Description: Breaks stream of (pre-)clusters into timebunches
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_cluster_findgap
+-- Breaks stream of (pre-)clusters into timebunches.
+-- If the time between two clusters is larger than the specified gap time, or if a new superburst starts,
+-- then an output signal indicates that the next timebuch is starting.
+-- An on-edge signal is added to the data to indicate if the crystal is on the edge of the region that this module is processing.
+-- The module can be configured to process either SODAnet packets, or superburst packets without any preceding header.
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word0: (only if HEADERWORD0 is set to TRUE)
+-- bit63 = last-packet flag
+-- bit62..48 = packet number
+-- bit47..32 = data size in bytes
+-- bit31..0 = Not used (same as HADES)
+-- 64bits word1:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- for cluster data, for each cluster
+-- 64bits word2, clusterresults
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..30 = diameter
+-- bit29..20 = Y position, multiplied by 2
+-- bit19..10 = X position, multiplied by 2
+-- bit9..0 = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- Library
+--
+-- generics:
+-- HEADERWORD0 : true : process SODAnet packet, false process packet with first word containing superburstnumber
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset
+-- gap_time : maximum gap time between clusters, resolutie from Constant Fraction (6.1ps)
+-- onedgeLUT_write : write signal for on-edge Look Up Table
+-- onedgeLUT_load : when '1' the LUT can be loaded with values, on '0' the writing address is set back to zero
+-- onedgeLUT_data : loading data for the LUT: 'on edge'
+-- data_in : 64bits data
+-- data_in_first : indicates that 64bits data is first in a packet
+-- data_in_last : indicates that 64bits data is last in packet
+-- data_in_write : write signal for 64bits data
+-- data_out_allowed : allowed to write output data
+--
+-- Outputs:
+-- data_in_allowed : allow input data to be written
+-- data_out : 64 bits output data
+-- data_out_onedge : the hit in the output data is positioned on the edge of the Data Concentrator region
+-- data_out_active : timebunch active
+-- data_out_nexttimebunch : actual and further output data belongs to new timebunch
+-- data_out_write : write signal for 64 bits / XY and on-edge output data
+-- data_out_first : 64 bits output data contains new superburst
+-- data_out_last : 64 bits output data is the last data of a superburst
+-- superburst_rewind : new superburstnumber is lower than previous
+-- dataerror : error in data
+--
+-- Components:
+-- CN_cluster_onedge_LUT : memory block for on-edge Look Up Table
+--
+----------------------------------------------------------------------------------
+
+entity CN_cluster_findgap is
+ generic(
+ HEADERWORD0 : boolean := TRUE
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ gap_time : in std_logic_vector(23 downto 0);
+ onedgeLUT_write : in std_logic;
+ onedgeLUT_load : in std_logic;
+ onedgeLUT_data : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_onedge : out std_logic;
+ data_out_active : out std_logic;
+ data_out_nexttimebunch : out std_logic;
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ superburst_rewind : out std_logic;
+ dataerror : out std_logic
+ );
+end CN_cluster_findgap;
+
+
+architecture behaviour of CN_cluster_findgap is
+
+component CN_cluster_onedge_LUT is
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(15 downto 0);
+ data_in : in std_logic;
+ read_address : in std_logic_vector(15 downto 0);
+ data_out : out std_logic
+ );
+end component;
+
+signal timeoutcount_S : std_logic_vector(11 downto 0);
+signal data_in_write_S : std_logic;
+signal data_in_allowed_S : std_logic;
+
+signal dataerror1_S : std_logic := '0';
+signal wave_S : std_logic := '0';
+signal new_superburst_S : std_logic := '0';
+signal time_S : std_logic_vector(23 downto 0);
+signal prev_suberburst_S : std_logic_vector(30 downto 0) := (others => '0');
+signal packetsize_S : integer range 0 to 65535;
+signal data_in_count_S : integer range 0 to 65535;
+signal waitforfirst_S : std_logic := '1';
+
+signal expectfirst_S : std_logic := '1';
+signal expect_resultword_S : std_logic := '1';
+signal nrofhits_S : std_logic_vector(9 downto 0);
+signal hitscounter_S : std_logic_vector(9 downto 0);
+
+signal data_out_nextbunch_S : std_logic;
+signal data_out_nextbunch0_S : std_logic := '0';
+
+signal data_out_allowed_S : std_logic := '0';
+signal data_out_active_S : std_logic := '0';
+signal data_out_write_S : std_logic := '0';
+signal data_out_first_S : std_logic := '0';
+signal data_out_last_S : std_logic := '0';
+signal data_out_write0_S : std_logic := '0';
+
+signal onedgeLUT_loadaddress_S : std_logic_vector(15 downto 0) := (others => '0');
+signal onedgeLUT_data_S : std_logic;
+signal onedgeLUT_data0_S : std_logic;
+
+begin
+
+dataerror <= '1' when (dataerror1_S='1') else '0';
+data_in_allowed_S <= '1' when (data_out_allowed='1') else '0';
+data_in_allowed <= data_in_allowed_S;
+data_out_write <= '1' when (data_out_write_S='1') and (data_out_allowed='1') else '0';
+data_out_first <= '1' when (data_out_first_S='1') and (data_out_allowed='1') else '0';
+data_out_last <= '1' when (data_out_last_S='1') and (data_out_allowed='1') else '0';
+data_in_write_S <= '1' when (data_in_write='1') and (data_in_allowed_S='1') else '0';
+
+data_out_active <= data_out_active_S;
+data_out_nexttimebunch <= data_out_nextbunch_S;
+
+-- Look Up Table for position of hits near edge of region
+LUT1: CN_cluster_onedge_LUT port map(
+ clock => clock,
+ write_enable => onedgeLUT_write,
+ write_address => onedgeLUT_loadaddress_S,
+ data_in => onedgeLUT_data,
+ read_address => data_in(31 downto 16),
+ data_out => onedgeLUT_data_S);
+data_out_onedge <= onedgeLUT_data0_S when (data_out_allowed_S='0') and (data_out_allowed='1') else onedgeLUT_data_S;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if onedgeLUT_load='1' then
+ if onedgeLUT_write='1' then
+ onedgeLUT_loadaddress_S <= onedgeLUT_loadaddress_S+1;
+ end if;
+ else
+ onedgeLUT_loadaddress_S <= (others => '0');
+ end if;
+ if data_out_write0_S='1' then
+ onedgeLUT_data0_S <= onedgeLUT_data_S;
+ end if;
+ data_out_allowed_S <= data_out_allowed;
+ end if;
+end process;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ data_out_allowed_S <= data_out_allowed;
+ end if;
+end process;
+
+
+-- input data handling process
+process(clock)
+variable prev_suberburst_V : std_logic_vector(30 downto 0);
+begin
+ if (rising_edge(clock)) then
+ dataerror1_S <= '0';
+ superburst_rewind <= '0';
+ data_out_nextbunch_S <= '0';
+ data_out_write_S <= '0';
+ data_out_write0_S <= '0';
+ data_out_first_S <= '0';
+ data_out_last_S <= '0';
+ if reset='1' then
+ waitforfirst_S <= '1';
+ data_out_nextbunch0_S <='0';
+ new_superburst_S <= '0';
+ data_out_active_S <= '0';
+ data_out_last_S <= '0';
+ data_out_first_S <= '0';
+ expectfirst_S <= '1';
+ expect_resultword_S <= '0';
+ prev_suberburst_S <= (others => '0');
+ else
+ if (data_out_write_S='1') and (data_out_allowed='1') and (data_out_last_S='1') then
+ data_out_active_S <= '0';
+ end if;
+ if (data_out_nextbunch_S='1') and (data_out_allowed='0') then
+ --// data_out_nextbunch_S <= '1'; -- retry
+ end if;
+ if (data_out_write_S='1') and (data_out_allowed='0') then
+ data_out_write_S <= '1'; -- retry;
+ data_out_last_S <= data_out_last_S;
+ data_out_first_S <= data_out_first_S;
+ else
+ if data_out_nextbunch0_S='1' then
+ data_out_nextbunch_S <= '1';
+ data_out_nextbunch0_S <='0';
+ end if;
+ end if;
+ if (data_in_write_S='1') then
+ timeoutcount_S <= (others => '0');
+ if (data_in_first='1') then
+ waitforfirst_S <= '0';
+ data_in_count_S <= 1;
+ data_out_active_S <= '0';
+ time_S <= (others => '0');
+ if expectfirst_S='0' then
+ dataerror1_S <= '1';
+ end if;
+ if new_superburst_S='0' then
+ data_out_nextbunch_S <= '1';
+ end if;
+ new_superburst_S <= '1';
+ if (HEADERWORD0=TRUE) then
+ if data_in(63)='0' then
+ dataerror1_S <= '1';
+ end if;
+ packetsize_S <= conv_integer(unsigned(data_in(47 downto 32)));
+ if data_in(31 downto 0)/=x"00000000" then
+ dataerror1_S <= '1';
+ end if;
+ else
+ prev_suberburst_V := prev_suberburst_S+1;
+ if (data_in(30 downto 0)/=prev_suberburst_V) and (conv_integer(unsigned(prev_suberburst_S))/=0) then
+ dataerror1_S <= '1';
+ end if;
+ if prev_suberburst_S>data_in(30 downto 0) then
+ superburst_rewind <= '1';
+ end if;
+ prev_suberburst_S <= data_in(30 downto 0);
+ data_out <= data_in;
+ data_out_write_S <= '1';
+ data_out_first_S <= '1';
+ if (data_in_last='1') then -- empty superburst
+ data_out_last_S <= '1';
+ data_out_nextbunch0_S <= '1';
+ expect_resultword_S <= '0';
+ expectfirst_S <= '1';
+ else
+ data_out_active_S <= '1';
+ expect_resultword_S <= '1';
+ expectfirst_S <= '0';
+ end if;
+ end if;
+ elsif (HEADERWORD0=TRUE) and (data_in_count_S=1) and (waitforfirst_S='0') then
+ data_out_active_S <= '0';
+ prev_suberburst_V := prev_suberburst_S+1;
+ if (data_in(30 downto 0)/=prev_suberburst_V) and (conv_integer(unsigned(prev_suberburst_S))/=0) then
+ dataerror1_S <= '1';
+ end if;
+ if prev_suberburst_S>data_in(30 downto 0) then
+ superburst_rewind <= '1';
+ end if;
+ prev_suberburst_S <= data_in(30 downto 0);
+ data_out <= data_in;
+ data_out_first_S <= '1';
+ time_S <= (others => '0');
+ if (data_in_last='1') then -- empty superburst
+ data_out_last_S <= '1';
+ data_out_write_S <= '1';
+ data_out_nextbunch0_S <= '1';
+ expect_resultword_S <= '0';
+ expectfirst_S <= '1';
+ else
+ data_out_active_S <= '1';
+ expect_resultword_S <= '1';
+ expectfirst_S <= '0';
+ end if;
+ if data_in_last='1' then
+ if packetsize_S/=(data_in_count_S+1)*8 then
+ dataerror1_S <= '1';
+ end if;
+ end if;
+ data_in_count_S <= data_in_count_S+1;
+ elsif (expect_resultword_S='1') and (waitforfirst_S='0') then
+ data_out_active_S <= '1';
+ if data_in(63 downto 40) < time_S(23 downto 0) then
+ dataerror1_S <= '1';
+ end if;
+ time_S <= data_in(63 downto 40);
+ nrofhits_S <= data_in(9 downto 0);
+ hitscounter_S <= (others => '0');
+ if conv_integer(unsigned(data_in(9 downto 0)))=0 then
+ dataerror1_S <= '1';
+ if data_in_last='1' then
+ expectfirst_S <= '1';
+ expect_resultword_S <= '0';
+ else
+ expectfirst_S <= '0';
+ expect_resultword_S <= '1';
+ end if;
+ else
+ if data_in_last='1' then
+ dataerror1_S <= '1';
+ expectfirst_S <= '1';
+ expect_resultword_S <= '0';
+ else
+ expectfirst_S <= '0';
+ expect_resultword_S <= '0';
+ end if;
+ end if;
+ if (new_superburst_S='1') or ('0' & data_in(63 downto 40))>('0' & time_S) + ('0' & gap_time) then
+ if (new_superburst_S='0') then
+ data_out_nextbunch_S <= '1';
+ end if;
+ new_superburst_S <= '0';
+ data_out <= data_in;
+ data_out_last_S <= data_in_last;
+ data_out_write_S <= '1';
+ data_out_write0_S <= '1';
+ else
+ data_out <= data_in;
+ data_out_last_S <= data_in_last;
+ data_out_write_S <= '1';
+ data_out_write0_S <= '1';
+ end if;
+ data_in_count_S <= data_in_count_S+1;
+ elsif waitforfirst_S='0' then
+ if hitscounter_S>=nrofhits_S-1 then
+ if data_in_last='1' then
+ expectfirst_S <= '1';
+ expect_resultword_S <= '0';
+ else
+ expectfirst_S <= '0';
+ expect_resultword_S <= '1';
+ end if;
+ else
+ if data_in_last='1' then
+ dataerror1_S <= '1';
+ expectfirst_S <= '1';
+ expect_resultword_S <= '0';
+ else
+ expectfirst_S <= '0';
+ expect_resultword_S <= '0';
+ end if;
+ end if;
+ data_out <= data_in;
+ data_out_last_S <= data_in_last;
+ data_out_write_S <= '1';
+ data_out_write0_S <= '1';
+ if (HEADERWORD0=TRUE) and (data_in_last='1') then
+ if packetsize_S/=(data_in_count_S+1)*8 then
+ dataerror1_S <= '1';
+ end if;
+ end if;
+ hitscounter_S <= hitscounter_S+1;
+ data_in_count_S <= data_in_count_S+1;
+ end if;
+ else
+ if (data_out_active_S='1') then
+ if (timeoutcount_S(timeoutcount_S'left)='0') then
+ if data_out_allowed='1' then
+ timeoutcount_S <= timeoutcount_S+1;
+ end if;
+ else
+ data_out_nextbunch_S <= '1';
+ data_out_active_S <= '0';
+ -- superburst_rewind <= '1';
+ timeoutcount_S <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 31-01-2012
+-- Module Name: CN_cluster_onedge_LUT
+-- Description: Look Up Table for on-edge indication
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- CN_cluster_onedge_LUT
+-- Look Up Table for bit that indicates if the crystal is on the edge of the region.
+--
+--
+-- generics
+-- ADDRESS_BITS : Number of bits for the address
+-- DATA_BITS : number of bits for data
+--
+-- inputs
+-- clock : clock
+-- write_enable : write to memory
+-- write_address : address to write to
+-- data_in : data to write into memory
+-- read_address : address to read from
+--
+-- outputs
+-- data_out : data from memory
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+entity CN_cluster_onedge_LUT is
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(15 downto 0);
+ data_in : in std_logic;
+ read_address : in std_logic_vector(15 downto 0);
+ data_out : out std_logic
+ );
+end CN_cluster_onedge_LUT;
+
+architecture behavioral of CN_cluster_onedge_LUT is
+type mem_type is array (0 to 2**16-1) of std_logic;
+signal mem_S : mem_type := (others => '1');
+
+attribute RAM_STYLE : string;
+attribute RAM_STYLE of mem_S: signal is "BLOCK";
+
+begin
+
+ process (clock)
+ begin
+ if (clock'event and clock = '1') then
+ if (write_enable = '1') then
+ mem_S(conv_integer(write_address)) <= data_in;
+ end if;
+ data_out <= mem_S(conv_integer(read_address));
+ end if;
+ end process;
+
+
+end architecture behavioral;
\ No newline at end of file
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 01-07-2016
+-- Module Name: CN_clustering
+-- Description: Clustering part of the PANDA cluster finding
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_clustering
+-- Clustering algorithm, developed by Marcel Tiemens (KVI-cart) for the PANDA Detector at GSI.
+-- This clustering stage searches for time-gaps in the pre-clusters and calculates if pre-clusters are part of the same cluster.
+-- Pre-clusters are considered to belong to the same cluster if the time and distance between the hits are small (next to each other, also diagonally).
+-- The timegap searching divides the input stream into time-bunches in module CN_cluster_findgap.
+-- The time-bunch is processed by module CN_cluster_build to split the data into clusters.
+-- To increase the throughput several mudules are put in parallel.
+-- If a cluster contains only one hit and if this hit is not position on the edge of the region then this cluster is skipped.
+--
+-- The input data consist of a data package from the Panda Data concentrator. Waveforms packages are ignored.
+-- This module can be configured to process data that does not contain the first header word (generic HEADERWORD0).
+-- The output data has the same structure, but only without the header word 0
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word0: (only if HEADERWORD0 is set to TRUE)
+-- bit63 = last-packet flag
+-- bit62..48 = packet number
+-- bit47..32 = data size in bytes
+-- bit31..0 = Not used (same as HADES)
+-- 64bits word1:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- for pulse data
+-- 64bits word2 and further, for each pulse:
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- for wave data (ignored)
+-- 64bits word2:
+-- bit63..56 = status byte
+-- bit55..40 = adc channel
+-- bit39..32 = number of samples in wave
+-- bit15..0 = timestamp in respect to superburst of the first sample in the waveform
+-- 64bits word3 and further :
+-- bit63..48 = next_adcsample(15:0)
+-- bit47..32 = next_adcsample(15:0)
+-- bit31..16 = next_adcsample(15:0)
+-- bit15..0 = next_adcsample(15:0)
+--
+-- for cluster data
+-- 64bits word2, clusterresults
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..30 = diameter
+-- bit29..20 = Y position, multiplied by 2
+-- bit19..10 = X position, multiplied by 2
+-- bit9..0 = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- Library
+--
+-- Generics:
+-- CLUSTERBITS : number of bits for the number of hits in one timebunch
+-- MAXCLUSTERSBITS : number of bits for the maximum clusters in one timebunch
+-- PARALLELBUILDS : number of CN_precluster_build modules to work in parallel
+-- HEADERWORD0 : true : process SODAnet packet, false process packet with first word containing superburstnumber
+-- MINIMUMENERGYBITS : number of bits for the miminum energy value
+-- SKIPSINGLEHITCLUSTERS : skip precluster if it contains only one hit and is not positioned on the edge
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset
+-- gap_time : maximum gap time between hits, resolutie from Constant Fraction (6.1ps)
+-- timedifference : maximum difference in time between hits in a cluster, resolutie from Constant Fraction (6.1ps)
+-- minimal_energy : minimum energy for a cluster; clusters with less are skipped if they are not positioned on the edge of a region
+-- onedgeLUT_write : write signal for on-edge Look Up Table
+-- onedgeLUT_load : when '1' the LUT can be loaded with values, on '0' the writing address is set back to zero
+-- onedgeLUT_data : loading data for the LUT: 'on edge'
+-- data_in : 64bits data
+-- data_in_first : indicates that 64bits data is first in a packet
+-- data_in_last : indicates that 64bits data is last in packet
+-- data_in_write : write signal for 64bits data
+-- data_out_allowed : allowed to write output data
+--
+-- Outputs:
+-- data_in_allowed : writing of input data allowed
+-- data_out : 64 bits output data
+-- data_out_write : write signal for 64 bits output data
+-- data_out_first : 64 bits output data contains the new superburst number
+-- data_out_last : 64 bits output data is the last of a superburst (not necessarily the same as timebunch)
+-- dataerror : error in data
+--
+-- Components:
+-- CN_cluster_findgap : Breaks stream of hits into timebunches
+-- CN_cluster_build : Construct clusters from a bunch of hits
+-- syncfifo_1024x66_almostempty256 : synchronous fifo to buffer output data
+-- CN_fiforead2write : Converts reading from fifo to write
+--
+----------------------------------------------------------------------------------
+
+entity CN_clustering is
+ generic(
+ CLUSTERBITS : natural := 8;
+ MAXCLUSTERSBITS : natural := 5;
+ PARALLELBUILDS : natural := 4;
+ HEADERWORD0 : boolean := TRUE;
+ MINIMUMENERGYBITS : natural := 8;
+ SKIPSINGLEHITCLUSTERS : boolean := FALSE
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ gap_time : in std_logic_vector(23 downto 0);
+ timedifference : in std_logic_vector(23 downto 0);
+ minimal_energy : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+ onedgeLUT_write : in std_logic;
+ onedgeLUT_load : in std_logic;
+ onedgeLUT_data : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end CN_clustering;
+
+
+architecture behaviour of CN_clustering is
+
+component CN_cluster_findgap is
+ generic(
+ HEADERWORD0 : boolean := HEADERWORD0
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ gap_time : in std_logic_vector(23 downto 0);
+ onedgeLUT_write : in std_logic;
+ onedgeLUT_load : in std_logic;
+ onedgeLUT_data : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_onedge : out std_logic;
+ data_out_active : out std_logic;
+ data_out_nexttimebunch : out std_logic;
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ superburst_rewind : out std_logic;
+ dataerror : out std_logic
+ );
+end component;
+
+
+component CN_cluster_build is
+ generic(
+ CLUSTERBITS : natural := CLUSTERBITS;
+ MAXCLUSTERSBITS : natural := MAXCLUSTERSBITS;
+ MINIMUMENERGYBITS : natural := MINIMUMENERGYBITS;
+ SKIPSINGLEHITCLUSTERS : boolean := SKIPSINGLEHITCLUSTERS
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ timedifference : in std_logic_vector(23 downto 0);
+ minimal_energy : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_onedge : in std_logic;
+ data_in_active : in std_logic;
+ data_in_write : in std_logic;
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_allowed : out std_logic;
+ busy : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_clusterallowed : in std_logic;
+ nextcluster : out std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component syncfifo_1024x66_almostempty256 is
+ port(
+ clk : in std_logic;
+ srst : in std_logic;
+ din : in std_logic_vector(65 DOWNTO 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(65 DOWNTO 0);
+ full : out std_logic;
+ empty : out std_logic;
+ prog_empty : out std_logic
+ );
+end component;
+
+component syncfifo_4096x66_almostempty3524 is
+ port(
+ clk : in std_logic;
+ srst : in std_logic;
+ din : in std_logic_vector(65 DOWNTO 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(65 DOWNTO 0);
+ full : out std_logic;
+ empty : out std_logic;
+ prog_empty : out std_logic
+ );
+end component;
+
+component CN_fiforead2write is
+ generic(
+ BITS : integer := 66
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(BITS-1 downto 0);
+ data_in_empty : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(BITS-1 downto 0);
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic
+ );
+end component;
+
+signal build_reset_S : std_logic;
+signal superburst_rewind_S : std_logic := '0';
+signal gapdata_S : std_logic_vector(63 downto 0);
+signal gapdata_onedge_S : std_logic := '1';
+signal gapdataerror_S : std_logic;
+signal gapdata_active_S : std_logic;
+signal gapdata_write_S : std_logic;
+signal gapdata_first_s : std_logic;
+signal gapdata_last_S : std_logic;
+signal gapdata_allowed_S : std_logic;
+signal gapdata_nexttimebunch_S : std_logic;
+signal build_actual0_S : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_next_S : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_actual_S : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_read_S : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_active_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_allowed_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_write_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_write_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_firsts_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_last_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_allowed_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal busy_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_nextcluster_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_error_S : std_logic_vector(0 to PARALLELBUILDS-1);
+
+signal fifoout_datain_S : std_logic_vector(65 downto 0);
+signal fifoout_dataout_S : std_logic_vector(65 downto 0);
+signal fifoout_write_S : std_logic;
+signal fifoout_read_S : std_logic;
+signal fifoout_full_S : std_logic;
+signal fifoout_empty_S : std_logic;
+signal fifoout_prog_empty_S : std_logic;
+
+
+
+
+type data_out_type is array(0 to PARALLELBUILDS-1) of std_logic_vector(63 downto 0);
+signal data_out_S : data_out_type;
+
+type testword_type is array(0 to PARALLELBUILDS-1) of std_logic_vector(127 downto 0);
+signal testword0_S : testword_type;
+
+signal debug_error_S : std_logic;
+
+begin
+dataerror <= '1' when (gapdataerror_S='1') or (conv_integer(unsigned(build_error_S))/=0) or (fifoout_full_S='1') else '0';
+CN_cluster_findgap1: CN_cluster_findgap port map(
+ clock => clock,
+ reset => reset,
+ gap_time => gap_time,
+ onedgeLUT_write => onedgeLUT_write,
+ onedgeLUT_load => onedgeLUT_load,
+ onedgeLUT_data => onedgeLUT_data,
+ data_in => data_in,
+ data_in_first => data_in_first,
+ data_in_last => data_in_last,
+ data_in_write => data_in_write,
+ data_in_allowed => data_in_allowed,
+ data_out => gapdata_S,
+ data_out_onedge => gapdata_onedge_S,
+ data_out_active => gapdata_active_S,
+ data_out_nexttimebunch => gapdata_nexttimebunch_S,
+ data_out_write => gapdata_write_S,
+ data_out_first => gapdata_first_S,
+ data_out_last => gapdata_last_S,
+ data_out_allowed => gapdata_allowed_S,
+ superburst_rewind => superburst_rewind_S,
+ dataerror => gapdataerror_S);
+
+gapdata_allowed_S <= build_allowed_S(build_actual_S);
+
+build_actual_S <= build_next_S when (gapdata_nexttimebunch_S='1') else build_actual0_S;
+build_next_S <= 0 when build_actual0_S>=PARALLELBUILDS-1 else build_actual0_S+1;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if (gapdata_nexttimebunch_S='1') then
+ if build_actual0_S<PARALLELBUILDS-1 then
+ build_actual0_S <= build_actual0_S+1;
+ else
+ build_actual0_S <= 0;
+ end if;
+ end if;
+ end if;
+end process;
+
+-- gapdata_allowed_S <= '1' when
+ -- ((build_allowed_S(build_actual0_S)='1') and (gapdata_nexttimebunch_S='0')) or
+ -- ((build_allowed_S(build_next_S)='1') and (gapdata_nexttimebunch_S='1'))
+ -- else '0';
+
+-- build_actual_S <= build_next_S when (gapdata_nexttimebunch_S='1') and (build_allowed_S(build_next_S)='1') else build_actual0_S;
+-- build_next_S <= 0 when build_actual0_S>=PARALLELBUILDS-1 else build_actual0_S+1;
+
+-- process(clock)
+-- begin
+ -- if (rising_edge(clock)) then
+ -- if (gapdata_nexttimebunch_S='1') and (gapdata_allowed_S='1') then
+ -- if build_actual0_S<PARALLELBUILDS-1 then
+ -- build_actual0_S <= build_actual0_S+1;
+ -- else
+ -- build_actual0_S <= 0;
+ -- end if;
+ -- end if;
+ -- end if;
+-- end process;
+build_reset_S <= '1' when (superburst_rewind_S='1') or (reset='1') else '0';
+CN_cluster_builds: for idx in 0 to PARALLELBUILDS-1 generate
+
+ build_write_S(idx) <= gapdata_write_S when idx=build_actual_S else '0';
+ build_active_S(idx) <= gapdata_active_S when idx=build_actual_S else '0';
+
+ CN_cluster_build0: CN_cluster_build port map(
+ clock => clock,
+ reset => build_reset_S,
+ timedifference => timedifference,
+ minimal_energy => minimal_energy,
+ data_in => gapdata_S,
+ data_in_onedge => gapdata_onedge_S,
+ data_in_active => build_active_S(idx),
+ data_in_write => build_write_S(idx),
+ data_in_first => gapdata_first_S,
+ data_in_last => gapdata_last_S,
+ data_in_allowed => build_allowed_S(idx),
+ busy => busy_S(idx),
+ data_out => data_out_S(idx),
+ data_out_write => data_out_write_S(idx),
+ data_out_first => data_out_firsts_S(idx),
+ data_out_last => data_out_last_S(idx),
+ data_out_clusterallowed => data_out_allowed_S(idx),
+ nextcluster => build_nextcluster_S(idx),
+ dataerror => build_error_S(idx),
+ testword0 => testword0_S(idx)
+ );
+data_out_allowed_S(idx) <= fifoout_prog_empty_S when build_read_S=idx else '0';
+
+end generate;
+
+fifoout_datain_S(63 downto 0) <= data_out_S(build_read_S);
+fifoout_write_S <= data_out_write_S(build_read_S);
+fifoout_datain_S(65) <= data_out_firsts_S(build_read_S);
+fifoout_datain_S(64) <= data_out_last_S(build_read_S);
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if build_actual_S/=build_read_S then
+ if busy_S(build_read_S)='0' then
+ if build_read_S<PARALLELBUILDS-1 then
+ build_read_S <= build_read_S+1;
+ else
+ build_read_S <= 0;
+ end if;
+ end if;
+ else
+ if (build_nextcluster_S(build_read_S)='1') then
+ if build_read_S<PARALLELBUILDS-1 then
+ build_read_S <= build_read_S+1;
+ else
+ build_read_S <= 0;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+outfifo: syncfifo_1024x66_almostempty256 port map(
+--outfifo: syncfifo_4096x66_almostempty3524 port map(
+ clk => clock,
+ srst => build_reset_S,
+ din => fifoout_datain_S,
+ wr_en => fifoout_write_S,
+ rd_en => fifoout_read_S,
+ dout => fifoout_dataout_S,
+ full => fifoout_full_S,
+ empty => fifoout_empty_S,
+ prog_empty => fifoout_prog_empty_S);
+
+
+read2write: CN_fiforead2write port map(
+ clock => clock,
+ reset => build_reset_S,
+ data_in => fifoout_dataout_S,
+ data_in_empty => fifoout_empty_S,
+ data_in_read => fifoout_read_S,
+ data_out(65) => data_out_first,
+ data_out(64) => data_out_last,
+ data_out(63 downto 0) => data_out,
+ data_out_write => data_out_write,
+ data_out_allowed => data_out_allowed);
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0) := (others => '0');
+variable clusterresult_V : std_logic := '0';
+variable same_superburst_V : std_logic := '0';
+variable nextissuperburst_V : std_logic := '1';
+variable nrofhits_V : std_logic_vector(9 downto 0) := (others => '0');
+variable hitscounter_V : std_logic_vector(9 downto 0) := (others => '0');
+variable prev_resulttime_V : std_logic_vector(23 downto 0) := (others => '0');
+variable prev_hittime_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ debug_error_S <= '0';
+ if reset='1' then
+ prev_superburst_V := (others => '0');
+ clusterresult_V := '0';
+ same_superburst_V := '0';
+ nextissuperburst_V := '1';
+ nrofhits_V := (others => '0');
+ hitscounter_V := (others => '0');
+ prev_resulttime_V := (others => '0');
+ prev_hittime_V := (others => '0');
+ elsif fifoout_write_S='1' then
+ if fifoout_datain_S(65)='1' then -- first
+ if nextissuperburst_V='0' then
+ end if;
+ if (fifoout_datain_S(30 downto 0)/=prev_superburst_V+1) and (conv_integer(unsigned(prev_superburst_V))/=0) then
+ debug_error_S <= '1';
+ end if;
+ same_superburst_V := '0';
+ prev_superburst_V := fifoout_datain_S(30 downto 0);
+ clusterresult_V := '1';
+ if fifoout_datain_S(64)='1' then -- last
+ nextissuperburst_V := '1';
+ else
+ nextissuperburst_V := '0';
+ end if;
+ elsif clusterresult_V='1' then
+ if fifoout_datain_S(64)='1' then -- last
+ nextissuperburst_V := '1';
+ debug_error_S <= '1';
+ else
+ nextissuperburst_V := '0';
+ end if;
+ if hitscounter_V/=nrofhits_V then
+ debug_error_S <= '1';
+ end if;
+ nrofhits_V := fifoout_datain_S(9 downto 0);
+ if (same_superburst_V='1') and (prev_resulttime_V>fifoout_datain_S(63 downto 40)) then
+ debug_error_S <= '1';
+ end if;
+ same_superburst_V := '1';
+ prev_resulttime_V := fifoout_datain_S(63 downto 40);
+ hitscounter_V := (others => '0');
+ prev_hittime_V := (others => '0');
+ clusterresult_V := '0';
+ else
+ if fifoout_datain_S(64)='1' then -- last
+ if hitscounter_V/=nrofhits_V-1 then
+ debug_error_S <= '1';
+ end if;
+ nextissuperburst_V := '1';
+ else
+ nextissuperburst_V := '0';
+ end if;
+ if fifoout_datain_S(63 downto 40)<prev_hittime_V then
+-- debug_error_S <= '1'; -- hits not sequential
+ end if;
+ prev_hittime_V := fifoout_datain_S(63 downto 40);
+ if hitscounter_V=nrofhits_V-1 then
+ clusterresult_V := '1';
+ end if;
+ hitscounter_V := hitscounter_V+1;
+ end if;
+ end if;
+ end if;
+end process;
+
+-- testword0(63 downto 0) <= gapdata_S;
+-- testword0(64) <= gapdata_first_s;
+-- testword0(65) <= gapdata_last_S;
+-- testword0(66) <= gapdata_write_S;
+-- testword0(67) <= gapdata_allowed_S;
+-- testword0(68) <= gapdata_active_S;
+-- testword0(69) <= gapdataerror_S;
+-- testword0(70) <= gapdata_nexttimebunch_S;
+-- testword0(71) <= '0' when build_actual0_S=0 else '1';
+-- testword0(72) <= '0' when build_next_S=0 else '1';
+-- testword0(73) <= '0' when build_actual_S=0 else '1';
+-- testword0(74) <= '0' when build_read_S=0 else '1';
+-- testword0(75) <= build_active_S(0);
+-- testword0(76) <= build_active_S(1);
+-- testword0(77) <= build_allowed_S(0);
+-- testword0(78) <= build_allowed_S(1);
+-- testword0(79) <= build_write_S(0);
+-- testword0(80) <= build_write_S(1);
+-- testword0(81) <= data_out_write_S(0);
+-- testword0(82) <= data_out_write_S(1);
+-- testword0(83) <= data_out_firsts_S(0);
+-- testword0(84) <= data_out_firsts_S(1);
+-- testword0(85) <= data_out_last_S(0);
+-- testword0(86) <= data_out_last_S(1);
+-- testword0(87) <= data_out_allowed_S(0);
+-- testword0(88) <= data_out_allowed_S(1);
+-- testword0(89) <= busy_S(0);
+-- testword0(90) <= busy_S(1);
+-- testword0(91) <= build_nextcluster_S(0);
+-- testword0(92) <= build_nextcluster_S(1);
+-- testword0(93) <= build_error_S(0);
+-- testword0(94) <= build_error_S(1);
+-- testword0(95) <= fifoout_write_S;
+-- testword0(96) <= fifoout_full_S;
+-- testword0(97) <= fifoout_prog_empty_S;
+-- testword0(98) <= fifoout_empty_S;
+-- testword0(99) <= fifoout_read_S;
+-- testword0(100) <= gapdata_first_s;
+-- testword0(101) <= build_reset_S;
+-- testword0(102) <= superburst_rewind_S;
+
+
+-- testword0(119 downto 112) <= testword0_S(0)(7 downto 0);
+-- testword0(127 downto 120) <= testword0_S(1)(7 downto 0);
+
+testword0 <= testword0_S(1);
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI-cart/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 01-07-2016
+-- Module Name: CN_combine2clusters
+-- Description: Combines two streams of cluster data to one
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_combine2clusters
+-- Combines two streams of cluster data to one, based on superburst number and time within superburst.
+-- Depending on if an input is connected and functioning an input can be enabled/disabled with the data_in_exists input.
+-- Data packets are compared, the oldest are passed on until both superburst numbers are identical.
+-- Then the cluster-time of the clusters of both inputs are compared and the oldest is passed on.
+-- There is a timeout if no data is available of one of the inputs. This should only happen if there is an error in the system.
+-- The input and output data structure is the same:
+--
+-- The 64 bits data:
+-- 64bits word1:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- 64bits word2, clusterresults
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..30 = diameter
+-- bit29..20 = Y position, multiplied by 2
+-- bit19..10 = X position, multiplied by 2
+-- bit9..0 = number of hits in cluster
+-- 64bits word3..word4+nrofhits : pulse data
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- Library
+--
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset
+-- data1_in : 64bits data
+-- data1_in_first : indicates that 64bits data is first in a packet
+-- data1_in_last : indicates that 64bits data is last in packet
+-- data1_in_write : write signal for 64bits data
+-- data1_in_exists_S : input is being used
+-- data2_in : 64bits data
+-- data2_in_first : indicates that 64bits data is first in a packet
+-- data2_in_last : indicates that 64bits data is last in packet
+-- data2_in_write : write signal for 64bits data
+-- data2_in_exists_S : input is being used
+-- data_out_allowed : allowed to write output data
+--
+-- Outputs:
+-- data1_in_allowed : allowed to write data to input data1
+-- data2_in_allowed : allowed to write data to input data2
+-- data_in_allowed : writing of input data allowed
+-- data_out : 64 bits output data
+-- data_out_write : write signal for 64 bits output data
+-- data_out_first : 64 bits output data contains the new superburst number
+-- data_out_last : 64 bits output data is the last of a superburst
+-- data_out_exists : output is being used
+-- dataerror : error in data
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity CN_combine2clusters is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic_vector(63 downto 0);
+ data1_in_first : in std_logic;
+ data1_in_last : in std_logic;
+ data1_in_write : in std_logic;
+ data1_in_exists : in std_logic;
+ data1_in_allowed : out std_logic;
+ data2_in : in std_logic_vector(63 downto 0);
+ data2_in_first : in std_logic;
+ data2_in_last : in std_logic;
+ data2_in_write : in std_logic;
+ data2_in_exists : in std_logic;
+ data2_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_exists : out std_logic;
+ data_out_allowed : in std_logic;
+ dataerror : out std_logic
+ );
+end CN_combine2clusters;
+
+
+architecture behaviour of CN_combine2clusters is
+constant TIMEOUTBITS : integer := 12;
+signal timeout_counter_S : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
+type state_type is (INITIALIZE,CLUSTER1,CLUSTER2,WAITSUPERBURST,CLUSTERRESULT);
+signal state_S : state_type := INITIALIZE;
+
+signal error_S : std_logic := '0';
+signal data1_in_exists_S : std_logic := '0';
+signal data2_in_exists_S : std_logic := '0';
+signal data1_in_alive_S : std_logic := '1';
+signal data2_in_alive_S : std_logic := '1';
+signal data1_in_allowed_S : std_logic := '0';
+signal data2_in_allowed_S : std_logic := '0';
+signal data1_in_write_S : std_logic := '0';
+signal data2_in_write_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+signal data_out_write_S : std_logic := '0';
+signal data_out_S : std_logic_vector(63 downto 0) := (others => '0');
+signal data1_timestamp_valid_S : std_logic := '0';
+signal data2_timestamp_valid_S : std_logic := '0';
+
+signal data1_packetfinished_S : std_logic := '1';
+signal data2_packetfinished_S : std_logic := '1';
+signal data1_passon_S : std_logic := '0';
+signal data2_passon_S : std_logic := '0';
+signal superburst_same_S : std_logic := '0';
+signal data_out_first_S : std_logic := '0';
+signal data_out_last_S : std_logic := '0';
+signal count_S : std_logic_vector(9 downto 0) := (others => '0');
+signal superburst1_valid_S : std_logic := '0';
+signal superburst2_valid_S : std_logic := '0';
+
+
+signal debug_hits1_S : std_logic_vector(9 downto 0) := (others => '0');
+signal debug_hits2_S : std_logic_vector(9 downto 0) := (others => '0');
+signal debug_data1_results_S : std_logic_vector(63 downto 0) := (others => '0');
+signal debug_data2_results_S : std_logic_vector(63 downto 0) := (others => '0');
+signal debug_data1_sb_S : std_logic_vector(63 downto 0) := (others => '0');
+signal debug_data2_sb_S : std_logic_vector(63 downto 0) := (others => '0');
+
+
+begin
+
+data1_in_exists_S <= '1' when (data1_in_exists='1') and (data1_in_alive_S='1') else '0';
+data2_in_exists_S <= '1' when (data2_in_exists='1') and (data2_in_alive_S='1') else '0';
+data_out_exists <= '1' when (data1_in_exists_S='1') or (data2_in_exists_S='1') else '0';
+
+dataerror <= error_S when (data1_in_exists_S='1') and (data2_in_exists_S='1') else '0';
+
+data_out <=
+ data_out_S when (data1_in_exists_S='1') and (data2_in_exists_S='1') else
+ data1_in when (data1_in_exists_S='1') and (data2_in_exists_S='0') else
+ data2_in when (data1_in_exists_S='0') and (data2_in_exists_S='1') else
+ (others => '0');
+data_out_write <=
+ data_out_write_S when (data1_in_exists_S='1') and (data2_in_exists_S='1') else
+ data1_in_write when (data1_in_exists_S='1') and (data2_in_exists_S='0') else
+ data2_in_write when (data1_in_exists_S='0') and (data2_in_exists_S='1') else
+ '0';
+data_out_write_S <= '1' when ((data_out_trywrite_S='1') and (data_out_allowed='1')) else '0';
+data_out_first <=
+ '1' when ((data_out_first_S='1') and (data_out_allowed='1')) and ((data1_in_exists_S='1') and (data2_in_exists_S='1')) else
+ data1_in_first when (data1_in_exists_S='1') and (data2_in_exists_S='0') else
+ data2_in_first when (data1_in_exists_S='0') and (data2_in_exists_S='1') else
+ '0';
+data_out_last <=
+ '1' when ((data_out_last_S='1') and (data_out_allowed='1')) and ((data1_in_exists_S='1') and (data2_in_exists_S='1')) else
+ data1_in_last when (data1_in_exists_S='1') and (data2_in_exists_S='0') else
+ data2_in_last when (data1_in_exists_S='0') and (data2_in_exists_S='1') else
+ '0';
+data1_in_allowed <=
+ data1_in_allowed_S when ((data1_in_exists_S='1') and (data2_in_exists_S='1')) else
+ data_out_allowed;
+data1_in_allowed_S <= '1' when (data_out_allowed='1') and (data2_passon_S='0')
+ and (
+ (data1_passon_S='1') or
+ ((state_S=CLUSTER1) and (data1_packetfinished_S='0')) or
+ ((state_S=WAITSUPERBURST) and (superburst1_valid_S='0')) or
+ ((state_S=CLUSTERRESULT) and (data1_timestamp_valid_S='0') and (data1_packetfinished_S='0'))
+ )
+ else '0';
+
+data2_in_allowed <=
+ data2_in_allowed_S when ((data1_in_exists_S='1') and (data2_in_exists_S='1')) else
+ data_out_allowed;
+data2_in_allowed_S <= '1' when (data_out_allowed='1') and (data1_passon_S='0')
+ and (
+ (data2_passon_S='1') or
+ ((state_S=CLUSTER2) and (data2_packetfinished_S='0')) or
+ ((state_S=WAITSUPERBURST) and (superburst2_valid_S='0')) or
+ ((state_S=CLUSTERRESULT) and (data2_timestamp_valid_S='0') and (data2_packetfinished_S='0'))
+ )
+ else '0';
+
+data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';
+data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';
+
+readprocess: process(clock)
+variable data1_results_V : std_logic_vector(63 downto 0) := (others => '0');
+variable data2_results_V : std_logic_vector(63 downto 0) := (others => '0');
+variable superburst1_word_V : std_logic_vector(63 downto 0) := (others => '0');
+variable superburst2_word_V : std_logic_vector(63 downto 0) := (others => '0');
+variable superburst1_last_V : std_logic := '0';
+variable superburst2_last_V : std_logic := '0';
+variable superburst1_valid_V : std_logic := '0';
+variable superburst2_valid_V : std_logic := '0';
+variable data1_timestamp_valid_V : std_logic := '0';
+variable data2_timestamp_valid_V : std_logic := '0';
+
+begin
+ if rising_edge(clock) then
+ error_S <= '0';
+ data_out_trywrite_S <= '0';
+ data_out_first_S <= '0';
+ data_out_last_S <= '0';
+ if reset='1' then
+ data1_in_alive_S <= '1';
+ data2_in_alive_S <= '1';
+ timeout_counter_S <= (others => '0');
+ data1_results_V := (others => '0');
+ data2_results_V := (others => '0');
+ superburst1_word_V := (others => '0');
+ superburst2_word_V := (others => '0');
+ superburst1_last_V := '0';
+ superburst2_last_V := '0';
+ superburst1_valid_V := '0';
+ superburst2_valid_V := '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ state_S <= INITIALIZE;
+ elsif (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
+ data_out_first_S <= data_out_first_S;
+ data_out_last_S <= data_out_last_S;
+ data_out_trywrite_S <= '1'; -- try again
+ timeout_counter_S <= (others => '0');
+ else
+ case state_S is
+ when INITIALIZE =>
+ data1_in_alive_S <= '1';
+ data2_in_alive_S <= '1';
+ superburst1_last_V := '0';
+ superburst2_last_V := '0';
+ superburst1_valid_V := '0';
+ superburst2_valid_V := '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ state_S <= WAITSUPERBURST;
+ when CLUSTER1 =>
+ data1_timestamp_valid_V := '0';
+ if data1_in_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ if (data1_in_first='1') then
+ error_S <= '1';
+ state_S <= WAITSUPERBURST;
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ superburst1_valid_V := '1';
+ superburst1_word_V := data1_in;
+ superburst1_last_V := data1_in_last;
+ elsif (data1_in_last='1') then
+ if count_S/=data1_results_V(9 downto 0)-1 then
+ error_S <= '1';
+ end if;
+ data_out_S <= data1_in;
+ data_out_trywrite_S <= '1';
+ data1_packetfinished_S <= '1';
+ if (data2_packetfinished_S='1') or (data1_passon_S='1') then
+ data_out_last_S <= '1';
+ state_S <= WAITSUPERBURST;
+ else
+ state_S <= CLUSTERRESULT;
+ end if;
+ elsif (count_S>=data1_results_V(9 downto 0)-1) then -- last data
+ data_out_S <= data1_in;
+ data_out_trywrite_S <= '1';
+ state_S <= CLUSTERRESULT;
+ else
+ data_out_S <= data1_in;
+ data_out_first_S <= '0';
+ data_out_trywrite_S <= '1';
+ count_S <= count_S+1;
+ end if;
+ else
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ data1_in_alive_S <= '0';
+ error_S <= '1';
+ state_S <= WAITSUPERBURST;
+ superburst1_valid_V := '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ timeout_counter_S <= (others => '0');
+ else
+ if data_out_allowed='1' then
+ if data_out_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ else
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ end if;
+ end if;
+ end if;
+ if (data1_packetfinished_S='1') then
+ error_S <= '1';
+ if (data2_packetfinished_S='1') then
+ state_S <= WAITSUPERBURST;
+ else
+ state_S <= CLUSTERRESULT;
+ end if;
+ end if;
+ when CLUSTER2 =>
+ data2_timestamp_valid_V := '0';
+ if data2_in_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ if (data2_in_first='1') then
+ error_S <= '1';
+ state_S <= WAITSUPERBURST;
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ superburst2_valid_V := '1';
+ superburst2_word_V := data2_in;
+ superburst2_last_V := data2_in_last;
+ elsif (data2_in_last='1') then
+ if count_S/=data2_results_V(9 downto 0)-1 then
+ error_S <= '1';
+ end if;
+ data_out_S <= data2_in;
+ data_out_trywrite_S <= '1';
+ data2_packetfinished_S <= '1';
+ if (data1_packetfinished_S='1') or (data2_passon_S='1') then
+ data_out_last_S <= '1';
+ state_S <= WAITSUPERBURST;
+ else
+ state_S <= CLUSTERRESULT;
+ end if;
+ elsif (count_S>=data2_results_V(9 downto 0)-1) then -- last data
+ data_out_S <= data2_in;
+ data_out_trywrite_S <= '1';
+ state_S <= CLUSTERRESULT;
+ else
+ data_out_S <= data2_in;
+ data_out_first_S <= '0';
+ data_out_trywrite_S <= '1';
+ count_S <= count_S+1;
+ end if;
+ else
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ data2_in_alive_S <= '0';
+ error_S <= '1';
+ state_S <= WAITSUPERBURST;
+ superburst2_valid_V := '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ timeout_counter_S <= (others => '0');
+ else
+ if data_out_allowed='1' then
+ if data_out_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ else
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ end if;
+ end if;
+ end if;
+ if (data2_packetfinished_S='1') then
+ error_S <= '1';
+ if (data1_packetfinished_S='1') then
+ state_S <= WAITSUPERBURST;
+ else
+ state_S <= CLUSTERRESULT;
+ end if;
+ end if;
+ when WAITSUPERBURST =>
+ data1_packetfinished_S <= '0';
+ data2_packetfinished_S <= '0';
+ superburst_same_S <= '0';
+ data1_passon_S <= '0';
+ data2_passon_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ count_S <= (others => '0');
+ if (data1_in_write_S='1') and (data1_in_first='1') then
+ superburst1_valid_V := '1';
+ superburst1_word_V := data1_in;
+ superburst1_last_V := data1_in_last;
+ end if;
+ if (data2_in_write_S='1') and (data2_in_first='1') then
+ superburst2_valid_V := '1';
+ superburst2_word_V := data2_in;
+ superburst2_last_V := data2_in_last;
+ end if;
+ if (superburst1_valid_V='1') and (superburst2_valid_V='1') then
+ if superburst1_word_V(30 downto 0)=superburst2_word_V(30 downto 0) then
+ if (superburst1_last_V='1') and (superburst2_last_V='1') then
+ data_out_trywrite_S <= '1';
+ data_out_first_S <= '1';
+ data_out_last_S <= '1';
+ data_out_S <= superburst1_word_V;
+ state_S <= WAITSUPERBURST;
+ superburst1_valid_V := '0';
+ superburst2_valid_V := '0';
+ elsif (superburst1_last_V='1') and (superburst2_last_V='0') then
+ data_out_trywrite_S <= '1';
+ data_out_first_S <= '1';
+ data_out_last_S <= '0';
+ data2_passon_S <= '1';
+ data_out_S <= superburst2_word_V;
+ state_S <= CLUSTERRESULT;
+ superburst1_valid_V := '0';
+ superburst2_valid_V := '0';
+ elsif (superburst1_last_V='0') and (superburst2_last_V='1') then
+ data_out_trywrite_S <= '1';
+ data_out_first_S <= '1';
+ data_out_last_S <= '0';
+ data1_passon_S <= '1';
+ data_out_S <= superburst1_word_V;
+ state_S <= CLUSTERRESULT;
+ superburst1_valid_V := '0';
+ superburst2_valid_V := '0';
+ else
+ data_out_trywrite_S <= '1';
+ data_out_first_S <= '1';
+ data_out_last_S <= '0';
+ superburst_same_S <= '1';
+ data_out_S <= superburst1_word_V;
+ state_S <= CLUSTERRESULT;
+ superburst1_valid_V := '0';
+ superburst2_valid_V := '0';
+ end if;
+ elsif superburst2_word_V(30 downto 0)>superburst1_word_V(30 downto 0) then
+ if (superburst1_last_V='1') then
+ data_out_trywrite_S <= '1';
+ data_out_first_S <= '1';
+ data_out_S <= superburst1_word_V;
+ state_S <= WAITSUPERBURST;
+ superburst1_valid_V := '0';
+ else
+ data_out_trywrite_S <= '1';
+ data_out_first_S <= '1';
+ data_out_last_S <= '0';
+ data1_passon_S <= '1';
+ data_out_S <= superburst1_word_V;
+ state_S <= CLUSTERRESULT;
+ superburst1_valid_V := '0';
+ end if;
+ else
+ if (superburst2_last_V='1') then
+ data_out_trywrite_S <= '1';
+ data_out_first_S <= '1';
+ data_out_S <= superburst2_word_V;
+ state_S <= WAITSUPERBURST;
+ superburst2_valid_V := '0';
+ else
+ data_out_trywrite_S <= '1';
+ data_out_first_S <= '1';
+ data_out_last_S <= '0';
+ data2_passon_S <= '1';
+ data_out_S <= superburst2_word_V;
+ state_S <= CLUSTERRESULT;
+ superburst2_valid_V := '0';
+ end if;
+ end if;
+ else
+ -- timeout
+ end if;
+ when CLUSTERRESULT =>
+ count_S <= (others => '0');
+ if data1_in_write_S='1' then
+ data1_results_V := data1_in;
+ debug_hits1_S <= data1_in(9 downto 0);
+ if conv_integer(unsigned(data1_in(9 downto 0)))/=0 then
+ data1_timestamp_valid_V := '1';
+ else
+ data1_timestamp_valid_V := '0';
+ error_S <= '1';
+ end if;
+ if (data1_in_first='1') or (data1_in_last='1') then
+ error_S <= '1';
+ end if;
+ elsif (data1_packetfinished_S='1') then
+ data1_timestamp_valid_V := '0';
+ end if;
+ if data2_in_write_S='1' then
+ data2_results_V := data2_in;
+ debug_hits2_S <= data2_in(9 downto 0);
+ if conv_integer(unsigned(data2_in(9 downto 0)))/=0 then
+ data2_timestamp_valid_V := '1';
+ else
+ data2_timestamp_valid_V := '0';
+ error_S <= '1';
+ end if;
+ if (data2_in_first='1') or (data2_in_last='1') then
+ error_S <= '1';
+ end if;
+ elsif (data2_packetfinished_S='1') then
+ data2_timestamp_valid_V := '0';
+ end if;
+ if (data1_packetfinished_S='1') and (data2_packetfinished_S='1') then
+ error_S <= '1';
+ state_S <= WAITSUPERBURST;
+ elsif ((data1_passon_S='1') or (data2_packetfinished_S='1')) and (data1_timestamp_valid_V='1') then
+ timeout_counter_S <= (others => '0');
+ data1_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= data1_results_V;
+ state_S <= CLUSTER1;
+ elsif ((data2_passon_S='1') or (data1_packetfinished_S='1')) and (data2_timestamp_valid_V='1') then
+ timeout_counter_S <= (others => '0');
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= data2_results_V;
+ state_S <= CLUSTER2;
+ else
+ if (data1_timestamp_valid_V='1') and (data2_timestamp_valid_V='1') then
+ timeout_counter_S <= (others => '0');
+ if (data1_results_V(63 downto 40)<data2_results_V(63 downto 40)) then -- select 1
+ data1_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= data1_results_V;
+ state_S <= CLUSTER1;
+ else -- select 2
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= data2_results_V;
+ state_S <= CLUSTER2;
+ end if;
+ elsif (data1_timestamp_valid_V='1') and (data2_timestamp_valid_V='0') then -- wait
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ data2_in_alive_S <= '0';
+ error_S <= '1';
+ data1_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= data1_results_V;
+ timeout_counter_S <= (others => '0');
+ state_S <= CLUSTER1;
+ else
+ if data_out_allowed='1' then
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ end if;
+ elsif (data1_timestamp_valid_V='0') and (data2_timestamp_valid_V='1') then -- wait
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ data1_in_alive_S <= '0';
+ error_S <= '1';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= data2_results_V;
+ timeout_counter_S <= (others => '0');
+ state_S <= CLUSTER2;
+ else
+ if data_out_allowed='1' then
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ end if;
+ else -- no valid timestamps
+ end if;
+ end if;
+ when OTHERS =>
+ state_S <= INITIALIZE;
+ end case;
+ end if;
+ superburst1_valid_S <= superburst1_valid_V;
+ superburst2_valid_S <= superburst2_valid_V;
+ data1_timestamp_valid_S <= data1_timestamp_valid_V;
+ data2_timestamp_valid_S <= data2_timestamp_valid_V;
+ debug_data1_results_S <= data1_results_V;
+ debug_data2_results_S <= data2_results_V;
+ debug_data1_sb_S <= superburst1_word_V;
+ debug_data2_sb_S <= superburst2_word_V;
+ if (data1_in_write='1') then
+ data1_in_alive_S <= '1';
+ end if;
+ if (data2_in_write='1') then
+ data2_in_alive_S <= '1';
+ end if;
+ end if;
+end process;
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 01-09-2016
+-- Module Name: CN_combineclusters
+-- Description: Combines multiple streams of cluster data to one
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library work;
+USE work.CN_package.all;
+----------------------------------------------------------------------------------
+-- CN_combineclusters
+-- Combines multiple streams of cluster data to one, based on superburst number and time within superburst.
+-- The inputs are compared and combined in a tree structure with two inputs and one output.
+-- If the number of inputs is not a power of 2 then the missing inputs are filled up with empty data.
+-- Also, depending on if an input is connected and functioning an input can be enabled/disabled with the data_in_exists input.
+-- The input and output data structure is the same:
+--
+-- The 64 bits data:
+-- 64bits word1:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- 64bits word2, clusterresults
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..30 = diameter
+-- bit29..20 = Y position, multiplied by 2
+-- bit19..10 = X position, multiplied by 2
+-- bit9..0 = number of hits in cluster
+-- 64bits word3..word4+nrofhits : pulse data
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- Library
+--
+--
+-- Inputs:
+-- clock : clock for data input
+-- reset : reset
+-- data_in : array of 64bits data
+-- data_in_first : array of bits that indicates that corresponding 64bits data is first in packet
+-- data_in_last : array of bits that indicates that corresponding 64bits data is last in packet
+-- data_in_write : array of write signals for corresponding 64bits data
+-- data_in_exists : input is being used
+-- data_out_allowed : allowed to write output data
+--
+--
+-- Outputs:
+-- data_in_allowed : array of signals to allow writing to corresponding input
+-- data_out : 64 bits output data
+-- data_out_write : write signal for 64 bits output data
+-- data_out_first : 64 bits output data contains the new superburst number
+-- data_out_last : 64 bits output data is the last of a superburst
+-- dataerror : error in data
+--
+-- Components:
+-- CN_combine2clusters : Combines two streams of cluster data to one
+--
+----------------------------------------------------------------------------------
+
+entity CN_combineclusters is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in CN_inputs64bits_type;
+ data_in_first : in std_logic_vector(0 to NROFCNINPUTS-1);
+ data_in_last : in std_logic_vector(0 to NROFCNINPUTS-1);
+ data_in_write : in std_logic_vector(0 to NROFCNINPUTS-1);
+ data_in_exists : in std_logic_vector(0 to NROFCNINPUTS-1);
+ data_in_allowed : out std_logic_vector(0 to NROFCNINPUTS-1);
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end CN_combineclusters;
+
+
+architecture behaviour of CN_combineclusters is
+constant TIMEOUTBITS : integer := 12;
+constant mux2to1_gen_max : integer := twologarray(NROFCNINPUTS);
+constant NROFCNINPUTSPOW2 : integer := 2**mux2to1_gen_max;
+
+component CN_combine2clusters is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic_vector(63 downto 0);
+ data1_in_first : in std_logic;
+ data1_in_last : in std_logic;
+ data1_in_write : in std_logic;
+ data1_in_exists : in std_logic;
+ data1_in_allowed : out std_logic;
+ data2_in : in std_logic_vector(63 downto 0);
+ data2_in_first : in std_logic;
+ data2_in_last : in std_logic;
+ data2_in_write : in std_logic;
+ data2_in_exists : in std_logic;
+ data2_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_exists : out std_logic;
+ data_out_allowed : in std_logic;
+ dataerror : out std_logic
+ );
+end component;
+
+
+type data_element_type is array(0 to NROFCNINPUTSPOW2-1) of std_logic_vector(63 downto 0);
+type data_type is array(0 to mux2to1_gen_max) of data_element_type;
+type singlebit_type is array(0 to mux2to1_gen_max) of std_logic_vector(0 to NROFCNINPUTSPOW2-1);
+
+signal data_S : data_type;
+signal data_first_S : singlebit_type;
+signal data_last_S : singlebit_type;
+signal data_write_S : singlebit_type;
+signal data_exists_S : singlebit_type;
+signal data_allowed_S : singlebit_type;
+signal dataerror_S : singlebit_type;
+
+begin
+
+gen_inputs: for i in 0 to NROFCNINPUTSPOW2-1 generate
+
+ data_S(0)(i) <= data_in(i) when i<NROFCNINPUTS else (others => '0');
+ data_first_S(0)(i) <= data_in_first(i) when i<NROFCNINPUTS else '0';
+ data_last_S(0)(i) <= data_in_last(i) when i<NROFCNINPUTS else '0';
+ data_write_S(0)(i) <= data_in_write(i) when i<NROFCNINPUTS else '0';
+ data_exists_S(0)(i) <= data_in_exists(i) when i<NROFCNINPUTS else '0';
+ gen_aollowed: if i<NROFCNINPUTS generate
+ data_in_allowed(i) <= data_allowed_S(0)(i);
+ end generate;
+
+end generate;
+
+
+MUX_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate
+
+ MUX_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate
+ CN_combine2clusters_all: CN_combine2clusters port map(
+ clock => clock,
+ reset => reset,
+ data1_in => data_S(i1)(i2*2),
+ data1_in_first => data_first_S(i1)(i2*2),
+ data1_in_last => data_last_S(i1)(i2*2),
+ data1_in_write => data_write_S(i1)(i2*2),
+ data1_in_exists => data_exists_S(i1)(i2*2),
+ data1_in_allowed => data_allowed_S(i1)(i2*2),
+ data2_in => data_S(i1)(i2*2+1),
+ data2_in_first => data_first_S(i1)(i2*2+1),
+ data2_in_last => data_last_S(i1)(i2*2+1),
+ data2_in_write => data_write_S(i1)(i2*2+1),
+ data2_in_exists => data_exists_S(i1)(i2*2+1),
+ data2_in_allowed => data_allowed_S(i1)(i2*2+1),
+ data_out => data_S(i1+1)(i2),
+ data_out_write => data_write_S(i1+1)(i2),
+ data_out_first => data_first_S(i1+1)(i2),
+ data_out_last => data_last_S(i1+1)(i2),
+ data_out_exists => data_exists_S(i1+1)(i2),
+ data_out_allowed => data_allowed_S(i1+1)(i2),
+ dataerror => dataerror_S(i1+1)(i2)
+ );
+ end generate;
+end generate;
+
+data_out <= data_S(mux2to1_gen_max)(0);
+data_out_write <= data_write_S(mux2to1_gen_max)(0);
+data_out_first <= data_first_S(mux2to1_gen_max)(0);
+data_out_last <= data_last_S(mux2to1_gen_max)(0);
+data_allowed_S(mux2to1_gen_max)(0) <= data_out_allowed;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ dataerror <= '0';
+ for i1 in 0 to mux2to1_gen_max-1 loop
+ for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop
+ if dataerror_S(i1)(i2)='1' then
+ dataerror <= '1';
+ end if;
+ end loop;
+ end loop;
+ end if;
+end process;
+
+
+testword0(7 downto 0) <= data_in(0)(7 downto 0);
+testword0(8) <= data_in_write(0);
+testword0(9) <= data_in_first(0);
+testword0(10) <= data_in_last(0);
+testword0(11) <= data_allowed_S(0)(0);
+testword0(19 downto 12) <= data_in(1)(7 downto 0);
+testword0(20) <= data_in_write(1);
+testword0(21) <= data_in_first(1);
+testword0(22) <= data_in_last(1);
+testword0(23) <= data_allowed_S(0)(1);
+testword0(31 downto 24) <= data_in(2)(7 downto 0);
+testword0(32) <= data_in_write(2);
+testword0(33) <= data_in_first(2);
+testword0(34) <= data_in_last(2);
+testword0(35) <= data_allowed_S(0)(2);
+testword0(43 downto 36) <= data_in(3)(7 downto 0);
+testword0(44) <= data_in_write(3);
+testword0(45) <= data_in_first(3);
+testword0(46) <= data_in_last(3);
+testword0(47) <= data_allowed_S(0)(3);
+
+
+testword0(55 downto 48) <= data_S(1)(0)(7 downto 0);
+testword0(56) <= data_write_S(1)(0);
+testword0(57) <= data_first_S(1)(0);
+testword0(58) <= data_last_S(1)(0);
+testword0(59) <= data_allowed_S(1)(0);
+testword0(60) <= dataerror_S(1)(0);
+
+testword0(68 downto 61) <= data_S(1)(1)(7 downto 0);
+testword0(69) <= data_write_S(1)(1);
+testword0(70) <= data_first_S(1)(1);
+testword0(71) <= data_last_S(1)(1);
+testword0(72) <= data_allowed_S(1)(1);
+testword0(73) <= dataerror_S(1)(1);
+
+testword0(81 downto 74) <= data_S(2)(0)(7 downto 0);
+testword0(82) <= data_write_S(2)(0);
+testword0(83) <= data_first_S(2)(0);
+testword0(84) <= data_last_S(2)(0);
+testword0(85) <= data_allowed_S(2)(0);
+testword0(86) <= dataerror_S(2)(0);
+
+testword0(87) <= data_in_exists(0);
+testword0(88) <= data_in_exists(1);
+testword0(89) <= data_in_exists(2);
+testword0(90) <= data_in_exists(3);
+
+testword0(91) <= data_exists_S(1)(0);
+testword0(92) <= data_exists_S(1)(1);
+testword0(93) <= data_exists_S(2)(0);
+
+
+
+
+
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 14-03-2016
+-- Module Name: CN_fiforead2write
+-- Description: Converts reading from fifo to write
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+----------------------------------------------------------------------------------
+-- CN_fiforead2write
+-- Converts reading from fifo to write
+--
+--
+--
+-- Library
+--
+--
+-- Generics
+-- BITS : number of bits at input and output
+--
+-- Inputs:
+-- clock : clock input for 64 bits data
+-- data_in : input data
+-- data_in_empty : empty from connected fifo
+-- data_out_allowed : writing of input data is allowed
+--
+-- Outputs:
+-- data_in_read : read data from fifo
+-- data_out : output data
+-- data_out_write : write signal for output data
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity CN_fiforead2write is
+ generic(
+ BITS : integer := 32
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(BITS-1 downto 0);
+ data_in_empty : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(BITS-1 downto 0);
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic
+ );
+end CN_fiforead2write;
+
+
+
+architecture behaviour of CN_fiforead2write is
+
+signal data_in_read_S : std_logic;
+signal data_in_read_aftr1clk_S : std_logic := '0';
+signal data_out_filled_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+signal data_out_buf_S : std_logic_vector(BITS-1 downto 0);
+signal data_out_S : std_logic_vector(BITS-1 downto 0);
+
+
+begin
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_in_empty='0') and (data_out_allowed='1') and (data_out_filled_S='0') and (reset='0') else '0';
+out_process: process(clock)
+begin
+ if rising_edge(clock) then
+ data_out_trywrite_S <= '0';
+ if reset='1' then
+ data_in_read_aftr1clk_S <= '0';
+ data_out_filled_S <= '0';
+ else
+ data_in_read_aftr1clk_S <= data_in_read_S;
+ if data_in_read_aftr1clk_S='1' then
+ if data_out_allowed='1' then
+ if (data_out_trywrite_S='1') then
+ if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+ data_out_S <= data_out_buf_S;
+ data_out_buf_S <= data_in;
+ data_out_trywrite_S <= '1'; -- write previous data
+ data_out_filled_S <= '1';
+ else -- write new data
+ data_out_S <= data_in;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '0';
+ end if;
+ else -- data_out_trywrite_S='0'
+ if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+ data_out_S <= data_out_buf_S;
+ data_out_buf_S <= data_in;
+ data_out_trywrite_S <= '1'; -- write previous data
+ data_out_filled_S <= '1';
+ else -- -- data_out_filled_S='0', write new data
+ data_out_S <= data_in;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '0';
+ end if;
+ end if;
+ else -- data_out_allowed='0'
+ if data_out_trywrite_S='1' then -- try again, save new data
+ data_out_buf_S <= data_in;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '1';
+ if data_out_filled_S='1' then
+ --error
+ end if;
+ else -- data_out_trywrite_S='0'
+ if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+ data_out_S <= data_out_buf_S;
+ data_out_buf_S <= data_in;
+ data_out_trywrite_S <= '1'; -- write previous data
+ data_out_filled_S <= '1';
+ else -- data_out_filled_S='0'
+ data_out_S <= data_in;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '0';
+ end if;
+ end if;
+ end if;
+ elsif (data_out_allowed='0') and (data_out_trywrite_S='1') then -- try again
+ data_out_trywrite_S <= '1';
+ elsif data_out_filled_S='1' then
+ if data_out_allowed='1' then
+ data_out_S <= data_out_buf_S;
+ data_out_trywrite_S <= '1';
+ data_out_filled_S <= '0';
+ end if;
+ else
+ end if;
+ end if;
+ end if;
+end process;
+data_out_write <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+data_out <= data_out_S;
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI-cart/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 20-04-2016
+-- Module Name: CN_package
+-- Description: Package with constants and functions for Compute Node
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+package CN_package is
+
+ constant NROFCNINPUTS : natural := 4; -- 147;
+ constant XYPAD_BITSIZE : natural := 8;
+-- constant ADCCLOCKFREQUENCY : natural := 80000000; -- 80000000; -- 62500000;
+
+-- fiber constants
+constant KCHAR280 : std_logic_vector(7 downto 0) := "00011100"; -- 1C
+constant KCHAR281 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
+constant KCHAR285 : std_logic_vector(7 downto 0) := "10111100"; -- BC
+-- constant KCHAR277 : std_logic_vector(7 downto 0) := "11111011"; -- FB
+constant KCHAR286 : std_logic_vector(7 downto 0) := x"DC";
+
+ type CN_inputs8bits_type is array(0 to NROFCNINPUTS-1) of std_logic_vector(7 downto 0);
+ type CN_inputs32bits_type is array(0 to NROFCNINPUTS-1) of std_logic_vector(31 downto 0);
+ type CN_inputs64bits_type is array(0 to NROFCNINPUTS-1) of std_logic_vector(63 downto 0);
+
+ type twologarray_type is array(0 to 256) of natural;
+ constant twologarray : twologarray_type :=
+(0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
+7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
+8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8);
+-- (0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
+-- 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7);
+
+component CN_posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+component CN_handledata is
+ port(
+ clock_rx : in std_logic_vector(0 to NROFCNINPUTS-1);
+ clock_tx : in std_logic_vector(0 to NROFCNINPUTS-1);
+ clock : in std_logic;
+ clock_UDP : in std_logic;
+ reset : in std_logic;
+ filter_enable : in std_logic;
+ filter_bothgain : in std_logic;
+ filter_adcnr : in std_logic_vector(15 downto 0);
+ dc_locked : in std_logic_vector(0 to NROFCNINPUTS-1);
+ rxdata : in CN_inputs8bits_type;
+ rx_k : in std_logic_vector(0 to NROFCNINPUTS-1);
+ txdata : out CN_inputs8bits_type;
+ tx_k : out std_logic_vector(0 to NROFCNINPUTS-1);
+ ll_data : out std_logic_vector(31 downto 0);
+ ll_sof_n : out std_logic;
+ ll_eof_n : out std_logic;
+ ll_src_ready_n : out std_logic;
+ ll_dst_ready_n : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0');
+ testword1 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_handleclusters is
+ port(
+ clock_rx : in std_logic_vector(0 to NROFCNINPUTS-1);
+ clock_tx : in std_logic_vector(0 to NROFCNINPUTS-1);
+ clock : in std_logic;
+ clock_UDP : in std_logic;
+ reset : in std_logic;
+ XYLUT_write : in std_logic_vector(0 to NROFCNINPUTS-1);
+ XYLUT_load : in std_logic_vector(0 to NROFCNINPUTS-1);
+ XYLUT_data : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+ data_in_exists : in std_logic_vector(0 to NROFCNINPUTS-1);
+ dc_locked : in std_logic_vector(0 to NROFCNINPUTS-1);
+ rxdata : in CN_inputs8bits_type;
+ rx_k : in std_logic_vector(0 to NROFCNINPUTS-1);
+ txdata : out CN_inputs8bits_type;
+ tx_k : out std_logic_vector(0 to NROFCNINPUTS-1);
+ ll_data : out std_logic_vector(31 downto 0);
+ ll_sof_n : out std_logic;
+ ll_eof_n : out std_logic;
+ ll_src_ready_n : out std_logic;
+ ll_dst_ready_n : in std_logic;
+ error : out std_logic;
+ autoreset : out std_logic;
+ select_out : in std_logic_vector(3 downto 0) := (others => '0');
+ select_UDP_speed : in std_logic_vector(2 downto 0) := (others => '0');
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0');
+ testword1 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_fiberdatato64bits is
+ port(
+ clock_rx : in std_logic;
+ clock_tx : in std_logic;
+ clock : in std_logic;
+ reset : in std_logic;
+ rxdata : in std_logic_vector(7 downto 0);
+ rx_k : in std_logic;
+ txdata : out std_logic_vector(7 downto 0);
+ tx_k : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic;
+ data_out_error : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_separatewaves is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_connected : in std_logic;
+ data_in_allowed : out std_logic;
+ data_in_error : in std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic;
+ data_out_error : out std_logic;
+ wave_out : out std_logic_vector(63 downto 0);
+ wave_out_first : out std_logic;
+ wave_out_last : out std_logic;
+ wave_out_write : out std_logic;
+ wave_out_allowed : in std_logic;
+ wave_out_error : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_bufferdata is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_in_error : in std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_write : out std_logic;
+ data_out_bufferfull : out std_logic;
+ data_out_allowed : in std_logic;
+ data_out_error : out std_logic
+ );
+end component;
+
+component CN_combine2packets is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data0_in : in std_logic_vector(63 downto 0);
+ data0_in_first : in std_logic;
+ data0_in_last : in std_logic;
+ data0_in_write : in std_logic;
+ data0_in_connected : in std_logic;
+ data0_in_allowed : out std_logic;
+ data0_in_error : in std_logic;
+ data1_in : in std_logic_vector(63 downto 0);
+ data1_in_first : in std_logic;
+ data1_in_last : in std_logic;
+ data1_in_write : in std_logic;
+ data1_in_connected : in std_logic;
+ data1_in_allowed : out std_logic;
+ data1_in_error : in std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic;
+ data_out_error : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_sortwavepackets is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data0_in : in std_logic_vector(63 downto 0);
+ data0_in_first : in std_logic;
+ data0_in_last : in std_logic;
+ data0_in_write : in std_logic;
+ data0_in_connected : in std_logic;
+ data0_bufferfull : in std_logic;
+ data0_in_allowed : out std_logic;
+ data0_in_error : in std_logic;
+ data1_in : in std_logic_vector(63 downto 0);
+ data1_in_first : in std_logic;
+ data1_in_last : in std_logic;
+ data1_in_write : in std_logic;
+ data1_in_connected : in std_logic;
+ data1_bufferfull : in std_logic;
+ data1_in_allowed : out std_logic;
+ data1_in_error : in std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic;
+ data_out_error : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_process_DCdata is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ error : out std_logic
+ );
+end component;
+
+component CN_combine2streams is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data0_in : in std_logic_vector(63 downto 0);
+ data0_in_first : in std_logic;
+ data0_in_last : in std_logic;
+ data0_in_write : in std_logic;
+ data0_in_allowed : out std_logic;
+ data0_in_error : in std_logic;
+ data1_in : in std_logic_vector(63 downto 0);
+ data1_in_first : in std_logic;
+ data1_in_last : in std_logic;
+ data1_in_write : in std_logic;
+ data1_in_allowed : out std_logic;
+ data1_in_error : in std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic;
+ data_out_error : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_filter is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ filter_enable : in std_logic;
+ filter_bothgain : in std_logic;
+ filter_adcnr : in std_logic_vector(15 downto 0);
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_error : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_error : out std_logic;
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_data64to32bits is
+ port(
+ clock : in std_logic;
+ clock_UDP : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_error : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ ll_data : out std_logic_vector(31 downto 0);
+ ll_sof_n : out std_logic;
+ ll_eof_n : out std_logic;
+ ll_src_ready_n : out std_logic;
+ ll_dst_ready_n : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_fiforead2write is
+ generic(
+ BITS : integer := 32
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(BITS-1 downto 0);
+ data_in_empty : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(BITS-1 downto 0);
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic
+ );
+end component;
+
+component CN_checkdata is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_error : in std_logic;
+ data_in_write : in std_logic;
+ dataerror : out std_logic;
+ timeerror : out std_logic;
+ waveerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_checkcluster is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ headerword0 : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_error : in std_logic;
+ data_in_write : in std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component sync_bit is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+end component;
+
+component CN_preclustering is
+ generic(
+ XYPAD_BITSIZE : natural := 8;
+ CLUSTERBITS : natural := 8;
+ MAXCLUSTERSBITS : natural := 5;
+ PARALLELBUILDS : natural := 4;
+ MINIMUMENERGYBITS : natural := 8;
+ SKIPSINGLEHITCLUSTERS : boolean := FALSE;
+ HEADERWORD0 : boolean := TRUE
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ gap_time : in std_logic_vector(23 downto 0);
+ timedifference : in std_logic_vector(23 downto 0);
+ minimal_energy : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+ XYLUT_write : in std_logic;
+ XYLUT_load : in std_logic;
+ XYLUT_data : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ superburst_rewind : out std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0)
+ );
+end component;
+
+component CN_combineclusters is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in CN_inputs64bits_type;
+ data_in_first : in std_logic_vector(0 to NROFCNINPUTS-1);
+ data_in_last : in std_logic_vector(0 to NROFCNINPUTS-1);
+ data_in_write : in std_logic_vector(0 to NROFCNINPUTS-1);
+ data_in_exists : in std_logic_vector(0 to NROFCNINPUTS-1);
+ data_in_allowed : out std_logic_vector(0 to NROFCNINPUTS-1);
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+component CN_clustering is
+ generic(
+ CLUSTERBITS : natural := 9;
+ MAXCLUSTERSBITS : natural := 5;
+ PARALLELBUILDS : natural := 4;
+ HEADERWORD0 : boolean := FALSE;
+ MINIMUMENERGYBITS : natural := 8;
+ SKIPSINGLEHITCLUSTERS : boolean := FALSE
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ gap_time : in std_logic_vector(23 downto 0);
+ timedifference : in std_logic_vector(23 downto 0);
+ minimal_energy : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+ onedgeLUT_write : in std_logic;
+ onedgeLUT_load : in std_logic;
+ onedgeLUT_data : in std_logic;
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end component;
+
+end CN_package;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 26-06-2016
+-- Module Name: CN_precluster_build
+-- Description: Construct clusters from a bunch of hits
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+use std.textio.all;
+use IEEE.std_logic_textio.all; -- I/O for logic types
+
+----------------------------------------------------------------------------------
+-- CN_precluster_build
+-- Construct clusters from a bunch of hits, based on time and XY-position
+-- C-software developed by Marcel Tiemens
+-- Input hit-data from module that splits up a stream in timebunches:
+-- If a cluster contains only one hit and if this hit is not position on the edge of the region then this cluster is skipped.
+--
+-- Input data from CN_precluster_findgap module:
+-- 64bits word1:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- 64bits word2 and further, for each hit:
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+--
+-- Output packets with 64 bits data words:
+-- 64bits word1:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- for cluster data
+-- 64bits word2, clusterresults
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..30 = diameter
+-- bit29..20 = Y position, multiplied by 2
+-- bit19..10 = X position, multiplied by 2
+-- bit9..0 = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- Criteria neighbours:
+-- crystal-positions (X0pos,Y0pos) and (X1pos,Y1pos) are neighbours :
+-- if (((X0pos+1==X1pos) or (X0pos==X1pos+1) or (X0pos==X1pos)) and
+-- (Y0pos+1==Y1pos) or (Y0pos==Y1pos+1) or (Y0pos==Y1pos)) and
+-- (time1-time0<=timedifference))
+--
+--
+--
+-- Library
+--
+--
+-- Generics:
+-- XYPAD_BITSIZE : number of bits for the X and Y position
+-- CLUSTERBITS : number of bits for the number of hits in one timebunch
+-- MAXCLUSTERSBITS : number of bits for the maximum clusters in one timebunch
+-- MINIMUMENERGYBITS : number of bits for the miminum energy value
+-- SKIPSINGLEHITCLUSTERS : skip precluster if it contains only one hit and is not positioned on the edge
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset
+-- timedifference : maximum difference in time between hits in a cluster, resolutie from Constant Fraction (6.1ps)
+-- minimal_energy : minimum energy for a cluster; clusters with less are skipped if they are not positioned on the edge of a region
+-- data_in : 64-bits input data
+-- data_in_Xpad : X-position of the crystal of the hit
+-- data_in_Ypad : Y-position of the crystal of the hit
+-- data_in_onedge : '1' if the hit is on the edge of the XY-area, not yet used
+-- data_in_active : timebunch active
+-- data_in_write : write signal for hitdata
+-- data_in_first : indicates that the data contains new superburst number
+-- data_in_last : indicates that the hit is the last one in a superburst
+-- data_out_clusterallowed : allowed to write clusters to output
+--
+-- Outputs:
+-- data_in_allowed : writing of input data allowed
+-- busy : busy processing timebunch
+-- data_out : 64 bits output data
+-- data_out_write : write signal for 64 bits output data
+-- data_out_first : 64 bits output data contains the new superburst number
+-- data_out_last : 64 bits output data is the last of a superburst (not necessarily the same as timebunch)
+-- nextcluster : signal that indicates the last data of a timebunch
+-- dataerror : error in data
+--
+-- Components:
+-- blockmem : synchronous memory block
+-- blockmemdirectread : synchronous memory block from which the output reacts directly on the written value
+--
+----------------------------------------------------------------------------------
+
+entity CN_precluster_build is
+ generic(
+ XYPAD_BITSIZE : natural := 8;
+ CLUSTERBITS : natural := 8;
+ MAXCLUSTERSBITS : natural := 5;
+ MINIMUMENERGYBITS : natural := 8;
+ SKIPSINGLEHITCLUSTERS : boolean := FALSE
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ timedifference : in std_logic_vector(23 downto 0);
+ minimal_energy : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_Xpad : in std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+ data_in_Ypad : in std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+ data_in_onedge : in std_logic;
+ data_in_active : in std_logic;
+ data_in_write : in std_logic;
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_allowed : out std_logic;
+ busy : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_clusterallowed : in std_logic;
+ nextcluster : out std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(36 downto 0) := (others => '0')
+ );
+end CN_precluster_build;
+
+
+architecture behaviour of CN_precluster_build is
+
+component blockmem is
+ generic (
+ ADDRESS_BITS : natural := 16;
+ DATA_BITS : natural := 32
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)
+ );
+end component;
+
+component blockmemdirectread is
+ generic (
+ ADDRESS_BITS : natural := 16;
+ DATA_BITS : natural := 32
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)
+ );
+end component;
+
+constant ONES : std_logic_vector(63 downto 0) := (others => '1');
+constant ZEROS : std_logic_vector(63 downto 0) := (others => '0');
+type state_type is (INITIALIZE,COLLECT,PRE_READ0,PRE_READ1,PRIMARY,PRIMARY1,PRIMARY1_0,PRIMARY2,PRIMARY2_0,
+ SECONDAIRY,SECONDAIRY1,ADJUSTSIMULARITIES,SECONDAIRY2,SORTING,
+ WRITESUPERBURST,WRITECLUSTER,WRITEHITS0,WRITEHITS);
+signal state_S : state_type := INITIALIZE;
+signal nextstate_S : state_type;
+signal stateprev_S : state_type;
+
+signal error_S : std_logic := '0';
+signal data_in_write_S : std_logic;
+signal data_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_f_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_prev_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_nextaddress_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal minimal_energy_S : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+
+
+signal datamem_in_S : std_logic_vector(16+8+16+24+2*XYPAD_BITSIZE downto 0);
+signal datamem_out_S : std_logic_vector(16+8+16+24+2*XYPAD_BITSIZE downto 0);
+signal data_in_channel_S : std_logic_vector(15 downto 0);
+signal data_in_statusbyte_S : std_logic_vector(7 downto 0);
+signal data_in_energy_S : std_logic_vector(15 downto 0);
+signal data_in_time_S : std_logic_vector(23 downto 0);
+signal data_in_Xpad_S : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data_in_Ypad_S : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data_in_onedge_S : std_logic;
+signal data0_channel_S : std_logic_vector(15 downto 0);
+signal data0_statusbyte_S : std_logic_vector(7 downto 0);
+signal data0_energy_S : std_logic_vector(15 downto 0);
+signal data0_time_S : std_logic_vector(23 downto 0);
+signal data0_Xpad_S : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data0_Ypad_S : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data0_onedge_S : std_logic;
+signal data_first_S : std_logic := '0';
+signal data_last_S : std_logic := '0';
+
+
+signal neighbours_write_S : std_logic;
+signal neighbours_data_in_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_data_out_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_data_prev_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal nNeighbours_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_write_address_S : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+signal neighbours_read_address_S : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+signal neighbours_index_S : std_logic_vector(CLUSTERBITS+1 downto 0);
+signal neighbours_count_index_S : std_logic_vector(CLUSTERBITS+1 downto 0);
+
+signal nDigis_S : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal only_one_hit_S : std_logic;
+signal overflow_S : std_logic := '0';
+signal data_read_first_S : std_logic;
+signal data_read_last_S : std_logic;
+
+signal prim_k_S : integer range 0 to 2**CLUSTERBITS-1;
+
+signal nClusters_S : integer range 0 to 2**CLUSTERBITS-1;
+signal simLength_S : integer range 0 to 2**CLUSTERBITS-1;
+
+signal isAdded_write_S : std_logic;
+signal isAdded_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0) := (others => '0');
+signal isAdded_read_address_S : std_logic_vector(CLUSTERBITS-1 downto 0) := (others => '0');
+signal isAdded_read_address_f_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal isadded_read_address_aftr1clk_s : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal isAdded_data_in_S : std_logic_vector(CLUSTERBITS downto 0);
+signal isAdded_data_out_S : std_logic_vector(CLUSTERBITS downto 0);
+signal isAdded_k_S : std_logic_vector(CLUSTERBITS downto 0);
+
+signal nrofneighbours_s : integer range 0 to 2**CLUSTERBITS-1;
+signal prim_m_S : integer range 0 to 2**CLUSTERBITS-1;
+signal prim_j_s : integer range 0 to 2**CLUSTERBITS-1;
+--type similarities_type is array(0 to 2*(2**CLUSTERBITS)-1) of std_logic_vector(CLUSTERBITS-1 downto 0);
+--signal similarities_s : similarities_type;
+
+signal similarities_write_S : std_logic;
+signal similarities_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_data_in_S : std_logic_vector(CLUSTERBITS*2-1 downto 0);
+signal similarities_read_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_data_out_S : std_logic_vector(CLUSTERBITS*2-1 downto 0);
+signal similarities_source_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_destination_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+
+
+signal sec1_i_S : integer range 0 to 2**CLUSTERBITS-1;
+signal sec1_j_S : integer range 0 to 2**CLUSTERBITS-1;
+signal sec1_m_S : integer range 0 to 2**CLUSTERBITS-1;
+signal sec2_i_S : integer range 0 to 2**CLUSTERBITS-1;
+signal sec2_n_S : std_logic;
+signal nPreclusters_S : integer range 0 to 2**CLUSTERBITS-1;
+
+signal result_diameter_S : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal result_positionX_S : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal result_positionY_S : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal result_time_S : std_logic_vector(23 downto 0);
+signal result_index_S : integer range 0 to 2**CLUSTERBITS-1;
+signal result_nrofhits_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal result_onedge_S : std_logic;
+
+signal results_write_address_S : std_logic_vector(MAXCLUSTERSBITS-1 downto 0);
+signal results_read_address_S : std_logic_vector(MAXCLUSTERSBITS-1 downto 0);
+signal results_data_in_S : std_logic_vector(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+24-1 downto 0);
+signal results_data_out_S : std_logic_vector(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+24-1 downto 0);
+signal results_write_S : std_logic;
+signal results_index_s : integer range 0 to 2**CLUSTERBITS-1;
+signal results_filled_S : std_logic;
+
+signal hitidx_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_data_in_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_read_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_data_out_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_write_S : std_logic;
+signal hitidx_index_S : integer range 0 to 2**CLUSTERBITS-1;
+signal hitidx_endaddress_s : integer range 0 to 2**CLUSTERBITS-1;
+
+signal nrofclocks_S : integer range 0 to 16383;
+signal isAdded_int_in_S : integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+signal isAdded_int_out_S : integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+
+signal sort_readkey_s : std_logic;
+type clustersortarray_type is array(0 to 2**MAXCLUSTERSBITS-1) of integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal clustersortarray_s : clustersortarray_type;
+signal sort_i_s : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal sort_j_s : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal sort_j_neg_S : std_logic;
+signal sort_key_S : std_logic_vector(23 downto 0) := (others => '0');
+
+signal data_out_S : std_logic_vector(63 downto 0);
+signal data_out_write_S : std_logic;
+signal data_out_first_S : std_logic;
+signal data_out_last_S : std_logic;
+signal nextcluster_S : std_logic;
+
+
+
+--type isAdded_array is array(0 to 2**CLUSTERBITS-1) of integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+--signal debug_isAdded_S : isAdded_array;
+signal debug_error_S : std_logic;
+signal debug_minimal_energy_reached_S : std_logic;
+
+attribute mark_debug : string;
+attribute mark_debug of debug_error_S : signal is "true";
+
+begin
+
+dataerror <= error_S;
+data_in_allowed <= '1' when (state_S=INITIALIZE) or (state_S=COLLECT) else '0';
+busy <= '1' when (state_S/=INITIALIZE) else '0';
+data_in_write_S <= '1' when (data_in_write='1') and (data_in_first='0') else '0';
+minimal_energy_S <= minimal_energy;
+
+datamemory: blockmem
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS,
+ DATA_BITS => 16+8+16+24+2*XYPAD_BITSIZE+1
+ )
+ port map(
+ clock => clock,
+ write_enable => data_in_write_S,
+ write_address => data_write_address_S,
+ data_in => datamem_in_S,
+ read_address => data_read_address_f_S,
+ data_out => datamem_out_S
+ );
+
+datamem_in_S(15 downto 0) <= data_in(31 downto 16); -- channel
+datamem_in_S(23 downto 16) <= data_in(39 downto 32); -- statusbyte
+datamem_in_S(39 downto 24) <= data_in(15 downto 0); -- energy
+datamem_in_S(63 downto 40) <= data_in(63 downto 40); -- time
+datamem_in_S(63+XYPAD_BITSIZE downto 64) <= data_in_Xpad;
+datamem_in_S(63+2*XYPAD_BITSIZE downto 64+XYPAD_BITSIZE) <= data_in_Ypad;
+datamem_in_S(64+2*XYPAD_BITSIZE) <= data_in_onedge;
+data_in_channel_S <= datamem_out_S(15 downto 0);
+data_in_statusbyte_S <= datamem_out_S(23 downto 16);
+data_in_energy_S <= datamem_out_S(39 downto 24);
+data_in_time_S <= datamem_out_S(63 downto 40);
+data_in_Xpad_S <= datamem_out_S(63+XYPAD_BITSIZE downto 64);
+data_in_Ypad_S <= datamem_out_S(63+2*XYPAD_BITSIZE downto 64+XYPAD_BITSIZE);
+data_in_onedge_S <= datamem_out_S(64+2*XYPAD_BITSIZE);
+
+
+
+neighbours: blockmemdirectread
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS+2,
+ DATA_BITS => CLUSTERBITS
+ )
+ port map(
+ clock => clock,
+ write_enable => neighbours_write_S,
+ write_address => neighbours_write_address_S,
+ data_in => neighbours_data_in_S,
+ read_address => neighbours_read_address_S,
+ data_out => neighbours_data_out_S
+ );
+
+
+isAddedmem: blockmemdirectread
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS,
+ DATA_BITS => CLUSTERBITS+1
+ )
+ port map(
+ clock => clock,
+ write_enable => isAdded_write_S,
+ write_address => isAdded_write_address_S,
+ data_in => isAdded_data_in_S,
+ read_address => isAdded_read_address_f_S,
+ data_out => isAdded_data_out_S
+ );
+isAdded_int_in_S <= -1 when isAdded_data_in_S(CLUSTERBITS)='0' else conv_integer(unsigned(isAdded_data_in_S(CLUSTERBITS-1 downto 0)));
+isAdded_int_out_S <= -1 when isAdded_data_out_S(CLUSTERBITS)='0' else conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)));
+
+similarities: blockmemdirectread
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS,
+ DATA_BITS => CLUSTERBITS*2
+ )
+ port map(
+ clock => clock,
+ write_enable => similarities_write_S,
+ write_address => similarities_write_address_S,
+ data_in => similarities_data_in_S,
+ read_address => similarities_read_address_S,
+ data_out => similarities_data_out_S
+ );
+
+results: blockmemdirectread
+ generic map (
+ ADDRESS_BITS => MAXCLUSTERSBITS,
+ DATA_BITS => 2*CLUSTERBITS+XYPAD_BITSIZE*3+2+24
+ )
+ port map(
+ clock => clock,
+ write_enable => results_write_S,
+ write_address => results_write_address_S,
+ data_in => results_data_in_S,
+ read_address => results_read_address_S,
+ data_out => results_data_out_S
+ );
+
+hitidices: blockmem
+ generic map (
+ ADDRESS_BITS => CLUSTERBITS,
+ DATA_BITS => CLUSTERBITS
+ )
+ port map(
+ clock => clock,
+ write_enable => hitidx_write_S,
+ write_address => hitidx_write_address_S,
+ data_in => hitidx_data_in_S,
+ read_address => hitidx_read_address_S,
+ data_out => hitidx_data_out_S
+ );
+
+data_read_address_f_S <=
+ hitidx_data_out_S when (state_S=WRITECLUSTER) else
+ hitidx_data_out_S when (state_S=WRITEHITS0) else
+ hitidx_data_out_S when (state_S=WRITEHITS) else
+ data_read_address_S;
+
+isAdded_read_address_f_S <=
+-- data_write_address_S-1 when (state_S=PRIMARY) and (neighbours_read_address_S>=neighbours_count_index_S) else
+ data_write_address_S-1 when (state_S=PRIMARY) and (not ((neighbours_read_address_S<neighbours_count_index_S) or ((neighbours_count_index_S=1) and (neighbours_read_address_S=1)))) else
+ data_write_address_S-1 when (state_S=PRIMARY) and (neighbours_read_address_S>=neighbours_count_index_S) else
+ conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY) and (conv_integer(unsigned(neighbours_data_out_S))=0) else
+ conv_std_logic_vector(prim_k_S,CLUSTERBITS) when (state_S=PRIMARY) else
+
+ neighbours_data_out_S when (state_S=PRIMARY1) else
+ neighbours_data_out_S when (state_S=PRIMARY1_0) and (prim_j_S<nrofneighbours_S-1) else
+
+ conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY1_0) and (prim_j_S>=nrofneighbours_S-1) else
+ neighbours_data_out_S when (state_S=PRIMARY2) else
+ neighbours_data_out_S when (state_S=PRIMARY2_0) and (prim_j_S<nrofneighbours_S-1) else
+ conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY2_0) and (prim_j_S>=nrofneighbours_S-1) else
+
+ conv_std_logic_vector(sec1_m_S,CLUSTERBITS) when (state_S=SECONDAIRY) else
+
+ (others => '0') when ((state_S=SECONDAIRY1) and ((simLength_S=0) or ((sec1_i_S=simLength_S-1) and (sec1_m_S=conv_integer(unsigned(data_write_address_S))-1)))) else
+ conv_std_logic_vector(sec1_m_S+1,CLUSTERBITS) when (state_S=SECONDAIRY1) and (sec1_m_S<conv_integer(unsigned(data_write_address_S))-1) and
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) else
+ (others => '0') when (state_S=SECONDAIRY1) else
+
+ conv_std_logic_vector(sec1_m_S,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) else
+
+ conv_std_logic_vector(sec1_m_S+1,CLUSTERBITS) when (state_S=SECONDAIRY2) and (sec1_m_S<conv_integer(unsigned(data_write_address_S))-1) else
+ (others => '0') when (state_S=SECONDAIRY2) and (sec1_m_S>=conv_integer(unsigned(data_write_address_S))) else
+
+ isAdded_read_address_S;
+
+similarities_read_address_S <=
+ (others => '0') when (state_S=SECONDAIRY) else
+ conv_std_logic_vector(sec1_i_S,CLUSTERBITS) when (state_S=SECONDAIRY1) and (sec1_m_S<conv_integer(unsigned(data_write_address_S))-1) and
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) else
+ conv_std_logic_vector(sec1_i_S+1,CLUSTERBITS) when (state_S=SECONDAIRY1) else
+ conv_std_logic_vector(sec1_i_S,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) and (sec1_j_S=simLength_S-1) else
+ conv_std_logic_vector(sec1_j_S+1,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) else
+ (others => '0');
+
+results_read_address_S <=
+ conv_std_logic_vector(1,MAXCLUSTERSBITS) when (state_S=SECONDAIRY1) else
+ conv_std_logic_vector(clustersortarray_S(sort_i_S-1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='1') and (results_filled_S='1') and (sort_i_S<=results_write_address_S) else
+ conv_std_logic_vector(clustersortarray_S(sort_i_S),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='1') else
+ conv_std_logic_vector(clustersortarray_S(sort_j_S-1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='0') and (sort_j_S>0) and (sort_j_neg_S='0') and (results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2)>sort_key_S) else
+ conv_std_logic_vector(clustersortarray_S(sort_i_S+1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) else
+ conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITESUPERBURST else
+ conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITECLUSTER else
+ conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS else
+ conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS0 else
+ (others => '0');
+
+hitidx_read_address_S <=
+ results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24) when (state_S=WRITESUPERBURST) else
+ results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24) when (state_S=WRITECLUSTER) else
+ conv_std_logic_vector(hitidx_index_S+1,CLUSTERBITS) when (state_S=WRITEHITS0) else
+ conv_std_logic_vector(hitidx_index_S+1,CLUSTERBITS) when (state_S=WRITEHITS) and (hitidx_index_S<hitidx_endaddress_S-1) else
+ conv_std_logic_vector(hitidx_index_S,CLUSTERBITS) when (state_S=WRITEHITS) else
+ (others => '0');
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ neighbours_write_S <= '0';
+ case state_S is
+ when INITIALIZE =>
+ for i in 0 to 2**MAXCLUSTERSBITS-1 loop
+ clustersortarray_S(i) <= i;
+ end loop;
+ when COLLECT =>
+ neighbours_index_S <= (others => '0');
+ neighbours_index_S(0) <= '1';
+ neighbours_count_index_S <= (others => '0');
+ nNeighbours_S <= (others => '0');
+ data_read_first_S <= '1';
+ when PRE_READ0 =>
+ neighbours_write_address_S <= neighbours_count_index_S;
+ neighbours_data_in_S <= nNeighbours_S;
+ neighbours_write_S <= '1';
+ if (data_read_first_S='0') then -- and (data_read_last_S='0') then
+ neighbours_count_index_S <= neighbours_index_S;
+ neighbours_index_S <= neighbours_index_S+1;
+ else
+ data_read_first_S <= '0';
+ end if;
+ nNeighbours_S <= (others => '0');
+ when PRE_READ1 =>
+ if ((conv_integer(unsigned(data0_Xpad_S))+1=conv_integer(unsigned(data_in_Xpad_S))) or
+ (conv_integer(unsigned(data0_Xpad_S))=conv_integer(unsigned(data_in_Xpad_S))+1) or
+ (conv_integer(unsigned(data0_Xpad_S))=conv_integer(unsigned(data_in_Xpad_S)))) and
+ ((conv_integer(unsigned(data0_Ypad_S))+1=conv_integer(unsigned(data_in_Ypad_S))) or
+ (conv_integer(unsigned(data0_Ypad_S))=conv_integer(unsigned(data_in_Ypad_S))+1) or
+ (conv_integer(unsigned(data0_Ypad_S))=conv_integer(unsigned(data_in_Ypad_S)))) and
+ (data_in_time_S-data0_time_S<=timedifference) then
+ neighbours_write_address_S <= neighbours_index_S;
+ neighbours_data_in_S <= data_read_address_prev_S;
+ neighbours_write_S <= '1';
+ neighbours_index_S <= neighbours_index_S+1;
+ nNeighbours_S <= nNeighbours_S+1;
+ else
+ end if;
+ when SECONDAIRY1 =>
+ sort_i_S <= 1;
+ sort_readkey_S <= '1';
+ -- results_read_address_S <= 1;
+ when SECONDAIRY2 | SORTING =>
+ -- for (int i = 1; i < nPreclusters; i++)
+ -- {
+ -- int key = clusters_time[clustersortarray[i]];
+ -- int j = i - 1;
+ -- while (j >= 0 && clusters_time[clustersortarray[j]] > key)
+ -- {
+ -- clustersortarray[j + 1] = clustersortarray[j];
+ -- j = j - 1;
+ -- }
+ -- clustersortarray[j + 1] = i;
+ -- }
+ if sort_readkey_S='1' then
+ if (results_filled_S='1') and (sort_i_S<=results_write_address_S) then
+ sort_key_S <= results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2);
+ sort_readkey_S <= '0';
+ sort_j_S <= sort_i_S-1;
+ sort_j_neg_S <= '0';
+ -- results_read_address_S <= clustersortarray_S(sort_i_S-1);
+ else
+ -- results_read_address_S <= clustersortarray_S(sort_i_S);
+ end if;
+ else
+ if (sort_j_neg_S='0') and (results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2)>sort_key_S) then
+ -- results_read_address_S <= clustersortarray_S(sort_j_S-1);
+ clustersortarray_S(sort_j_S+1) <= clustersortarray_S(sort_j_S);
+ if sort_j_S>0 then
+ sort_j_S <= sort_j_S-1;
+ sort_j_neg_S <= '0';
+ else
+ sort_j_neg_S <= '1';
+ end if;
+ else
+ -- results_read_address_S <= clustersortarray_S(sort_i_S+1);
+ if sort_j_neg_S='1' then
+ clustersortarray_S(0) <= sort_i_S;
+ else
+ clustersortarray_S(sort_j_S+1) <= sort_i_S;
+ end if;
+ sort_i_S <= sort_i_S+1;
+ sort_readkey_S <= '1';
+ end if;
+ end if;
+ when others =>
+ end case;
+ stateprev_S <= state_S;
+ end if;
+end process;
+
+
+process(clock)
+file dfile: text;
+variable l : line;
+variable result_startaddress_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable result_nrofhits_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable result_Xpad_min_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_Ypad_min_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_Xpad_max_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_Ypad_max_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_diameter_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_positionX_V : std_logic_vector(XYPAD_BITSIZE downto 0);
+variable result_positionY_V : std_logic_vector(XYPAD_BITSIZE downto 0);
+variable result_energy_max_V : std_logic_vector(15 downto 0);
+variable result_time_max_V : std_logic_vector(23 downto 0);
+variable result_onedge_V : std_logic;
+variable sum_energy_V : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+variable minimal_energy_reached_V : std_logic;
+variable nPreclusters_V : integer range 0 to 2**CLUSTERBITS-1 := 0;
+variable hitidx_write_address_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+begin
+ if (rising_edge(clock)) then
+ error_S <= '0';
+ isAdded_read_address_aftr1clk_S <= isAdded_read_address_f_S;
+ only_one_hit_S <= '0';
+ nextcluster_S <= '0';
+ isAdded_write_S <= '0';
+ data_out_write_S <= '0';
+ data_out_first_S <= '0';
+ data_out_last_S <= '0';
+ similarities_write_S <= '0';
+ results_write_S <= '0';
+ hitidx_write_S <= '0';
+ case state_S is
+ when INITIALIZE =>
+ nDigis_S <= 0;
+ nClusters_S <= 0;
+ nPreclusters_S <= 0;
+ results_index_S <= 0;
+ result_onedge_V := '0';
+ data_write_address_S <= (others => '0');
+ data_read_address_S <= (others => '0');
+ data_read_nextaddress_S <= (others => '0');
+ hitidx_data_in_S <= (others => '0');
+ hitidx_write_address_S <= (others => '0');
+ hitidx_write_S <='1';
+ minimal_energy_reached_V := '0';
+ if (data_in_write='1') and (data_in_last='1') then
+ data_last_S <= '1';
+ end if;
+ if (data_in_write='1') and (data_in_first='1') then
+ data_first_S <= '1';
+ data_out_S <= data_in;
+ end if;
+ if (data_in_write_S='1') and (data_in_active='1') then
+ result_onedge_V := data_in_onedge;
+ if conv_integer(unsigned(data_in(15 downto 0)))>=conv_integer(unsigned(minimal_energy_S)) then
+ minimal_energy_reached_V := '1';
+ end if;
+ end if;
+ if data_in_active='1' then
+ if data_in_write_S='1' then
+ data_write_address_S(0) <= '1';
+ nDigis_S <= 1;
+ end if;
+ state_S <= COLLECT;
+ elsif data_in_write='1' then -- empty superburst
+ data_out_S <= data_in;
+ if (data_in_first='0') or (data_in_last='0') then
+ error_S <= '1';
+ end if;
+ state_S <= WRITESUPERBURST;
+ end if;
+ overflow_S <= '0';
+ isAdded_data_in_S <= (others => '0');
+ if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= isAdded_write_address_S+1;
+ end if;
+ when COLLECT =>
+ if (data_in_write='1') and (data_in_last='1') then
+ data_last_S <= '1';
+ end if;
+ if (data_in_write='1') and (data_in_first='1') then
+ data_first_S <= '1';
+ data_out_S <= data_in;
+ end if;
+ if (data_in_write_S='1') then
+ result_onedge_V := data_in_onedge;
+ if conv_integer(unsigned(data_in(15 downto 0)))>=conv_integer(unsigned(minimal_energy_S)) then
+ minimal_energy_reached_V := '1';
+ end if;
+ end if;
+ neighbours_read_address_S <= (others => '0');
+ data_read_last_S <= '0';
+ data_read_address_S <= (others => '0');
+ data_read_nextaddress_S <= (others => '0');
+ if data_in_active='0' then
+ if nDigis_S=0 then
+ data_first_S <= '0';
+ data_last_S <= '0';
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ nextcluster_S <= '1';
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ elsif nDigis_S=1 then
+ if (SKIPSINGLEHITCLUSTERS=FALSE) or (result_onedge_V='1') or (minimal_energy_reached_V='1') then
+ -- or (((data_last_S='1') or ((data_in_write='1') and (data_in_last='1'))) and (data_first_S='0')) then
+ only_one_hit_S <= '1';
+ data_write_address_S <= (others => '0');
+ data_write_address_S(0) <= '1';
+ state_S <= WRITESUPERBURST;
+ else -- skip this hit
+ state_S <= WRITESUPERBURST;
+ end if;
+ else
+ state_S <= PRE_READ0;
+ data_read_address_S(0) <= '1';
+ end if;
+ else
+ if data_in_write_S='1' then
+ if data_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+ data_write_address_S <= data_write_address_S+1;
+ nDigis_S <= nDigis_S+1;
+ else
+ overflow_S <= '1';
+ end if;
+ end if;
+ end if;
+ isAdded_data_in_S <= (others => '0');
+ if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= isAdded_write_address_S+1;
+ end if;
+ when PRE_READ0 =>
+ neighbours_read_address_S <= (others => '0');
+ isAdded_data_in_S <= (others => '0');
+ if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= isAdded_write_address_S+1;
+ end if;
+ isAdded_read_address_S <= (others => '0');
+ data0_channel_S <= data_in_channel_S;
+ data0_statusbyte_S <= data_in_statusbyte_S;
+ data0_energy_S <= data_in_energy_S;
+ data0_time_S <= data_in_time_S;
+ data0_Xpad_S <= data_in_Xpad_S;
+ data0_Ypad_S <= data_in_Ypad_S;
+ data0_onedge_S <= data_in_onedge_S;
+ if data_read_last_S='1' then
+ if (neighbours_index_S>1) then
+ neighbours_read_address_S(0) <= '1';
+ end if;
+ prim_k_S <= 0;
+ nClusters_S <= 0;
+ simLength_S <= 0;
+ state_S <= PRIMARY;
+ elsif data_read_address_S<data_write_address_S-1 then
+ data_read_address_S <= data_read_address_S+1;
+ data_read_nextaddress_S <= data_read_nextaddress_S+1;
+ state_S <= PRE_READ1;
+ nextstate_S <= PRE_READ1;
+ else
+ state_S <= PRE_READ1;
+ nextstate_S <= PRE_READ0;
+ data_read_last_S <= '1';
+ end if;
+ when PRE_READ1 =>
+ isAdded_data_in_S <= (others => '0');
+ if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= isAdded_write_address_S+1;
+ end if;
+ neighbours_read_address_S <= (others => '0');
+ if data_read_address_S<data_write_address_S-1 then
+ data_read_address_S <= data_read_address_S+1;
+ else
+ data_read_address_S <= data_read_nextaddress_S;
+ nextstate_S <= PRE_READ0;
+ end if;
+ state_S <= nextstate_S;
+ when PRIMARY =>
+ sec1_i_S <= 0;
+ sec1_m_S <= 0;
+ if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+ isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters_S,CLUSTERBITS);
+ isAdded_write_address_S <= conv_std_logic_vector(prim_k_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ nrofneighbours_S <= conv_integer(unsigned(neighbours_data_out_S));
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ if conv_integer(unsigned(neighbours_data_out_S))>0 then
+ prim_j_S <= 0;
+ state_S <= PRIMARY1;
+ else
+ --????
+ prim_k_S <= prim_k_S+1;
+ nClusters_S <= nClusters_S+1;
+-- neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ else
+ nrofneighbours_S <= conv_integer(unsigned(neighbours_data_out_S));
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ if conv_integer(unsigned(neighbours_data_out_S))>0 then
+ prim_j_S <= 0;
+ state_S <= PRIMARY2;
+ else
+ --????
+ prim_k_S <= prim_k_S+1;
+-- neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ end if;
+-- if (neighbours_read_address_S<neighbours_count_index_S) or ((neighbours_count_index_S=1) and (neighbours_read_address_S=1)) then -- neighbours_count_index_S contains size of neighbour array
+-- else
+ if (neighbours_read_address_S>=neighbours_count_index_S) then -- neighbours_count_index_S contains size of neighbour array
+ state_S <= SECONDAIRY;
+ end if;
+ when PRIMARY1 =>
+ prim_m_S <= conv_integer(unsigned(neighbours_data_out_S));
+ if (nrofneighbours_S>1) then
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ neighbours_data_prev_S <= neighbours_data_out_S;
+ state_S <= PRIMARY1_0;
+ when PRIMARY1_0 =>
+ if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+ isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters_S,CLUSTERBITS);
+ isAdded_write_address_S <= neighbours_data_prev_S; -- conv_std_logic_vector(prim_m_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ elsif conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))/=nClusters_S then
+ if nClusters_S>conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0))) then
+ similarities_data_in_S <= conv_std_logic_vector(nClusters_S,CLUSTERBITS) & isAdded_data_out_S(CLUSTERBITS-1 downto 0);
+ else
+ similarities_data_in_S <= isAdded_data_out_S(CLUSTERBITS-1 downto 0) & conv_std_logic_vector(nClusters_S,CLUSTERBITS);
+ end if;
+ similarities_write_S <= '1';
+ similarities_write_address_S <= conv_std_logic_vector(simLength_S,CLUSTERBITS);
+ simLength_S <= simLength_S+1;
+ end if;
+ neighbours_data_prev_S <= neighbours_data_out_S;
+ if prim_j_S+2/=nrofneighbours_S then
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ if (nrofneighbours_S>1) and (prim_j_S<nrofneighbours_S-1) then
+ prim_j_S <= prim_j_S+1;
+ else
+ nClusters_S <= nClusters_S+1;
+ prim_k_S <= prim_k_S+1;
+ state_S <= PRIMARY;
+ end if;
+ when PRIMARY2 =>
+ prim_m_S <= conv_integer(unsigned(neighbours_data_out_S));
+ if (nrofneighbours_S>1) then
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ isAdded_k_S <= isAdded_data_out_S;
+ neighbours_data_prev_S <= neighbours_data_out_S;
+ state_S <= PRIMARY2_0;
+ when PRIMARY2_0 =>
+ if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+ isAdded_data_in_S <= isAdded_k_S;
+ isAdded_write_address_S <= neighbours_data_prev_S; -- conv_std_logic_vector(prim_m_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ elsif isAdded_data_out_S/=isAdded_k_S then --hier verder
+ if isAdded_k_S(CLUSTERBITS-1 downto 0)>isAdded_data_out_S(CLUSTERBITS-1 downto 0) then
+ similarities_data_in_S <= isAdded_k_S(CLUSTERBITS-1 downto 0) & isAdded_data_out_S(CLUSTERBITS-1 downto 0);
+ else
+ similarities_data_in_S <= isAdded_data_out_S(CLUSTERBITS-1 downto 0) & isAdded_k_S(CLUSTERBITS-1 downto 0);
+ end if;
+ similarities_write_S <= '1';
+ similarities_write_address_S <= conv_std_logic_vector(simLength_S,CLUSTERBITS);
+ simLength_S <= simLength_S+1;
+ end if;
+ neighbours_data_prev_S <= neighbours_data_out_S;
+ if prim_j_S+2/=nrofneighbours_S then
+ neighbours_read_address_S <= neighbours_read_address_S+1;
+ end if;
+ if (nrofneighbours_S>1) and (prim_j_S<nrofneighbours_S-1) then
+ prim_j_S <= prim_j_S+1;
+ else
+ prim_k_S <= prim_k_S+1;
+ state_S <= PRIMARY;
+ end if;
+ when SECONDAIRY =>
+ data_read_address_S <= (others => '0');
+ sec1_i_S <= 0;
+ sec1_m_S <= 0;
+ if (isAdded_data_out_S(CLUSTERBITS)='0') then
+ isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters_S,CLUSTERBITS);
+ isAdded_write_address_S <= data_write_address_S-1;
+ isAdded_write_S <= '1';
+ nClusters_S <= nClusters_S+1;
+ end if;
+ state_S <= SECONDAIRY1;
+ when SECONDAIRY1 =>
+ results_filled_S <= '0';
+ data_read_address_S <= (others => '0');
+ results_write_address_S <= (others => '1');
+ hitidx_write_address_S <= (others => '1');
+ hitidx_write_address_V := (others => '1');
+ result_startaddress_V := (others => '0');
+ result_nrofhits_V := (others => '0');
+ result_Xpad_min_V := (others => '1');
+ result_Ypad_min_V := (others => '1');
+ result_Xpad_max_V := (others => '0');
+ result_Ypad_max_V := (others => '0');
+ result_energy_max_V := (others => '0');
+ result_time_max_V := (others => '0');
+ result_onedge_V := '0';
+ minimal_energy_reached_V := '0';
+ sum_energy_V := (others => '0');
+ sec1_j_S <= sec1_i_S+1;
+ sec2_i_S <= 0;
+ sec2_n_S <= '0';
+ nPreclusters_S <= 0;
+ nPreclusters_V := 0;
+ if (isAdded_data_out_S(CLUSTERBITS-1 downto 0)=similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)) and
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0))
+ then -- filled bit not set
+ isAdded_data_in_S <= '1' & similarities_data_out_S(CLUSTERBITS-1 downto 0);
+ isAdded_write_address_S <= conv_std_logic_vector(sec1_m_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ end if;
+ if (sec1_m_S<conv_integer(unsigned(data_write_address_S))-1) and (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) then
+ sec1_m_S <= sec1_m_S+1;
+ else
+ sec1_i_S <= sec1_i_S+1;
+ sec1_m_S <= 0;
+ end if;
+
+ if (simLength_S=0) or ((sec1_i_S=simLength_S-1) and ((sec1_m_S=conv_integer(unsigned(data_write_address_S))-1) or
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)=similarities_data_out_S(CLUSTERBITS-1 downto 0)))) then
+ data_read_address_S <= data_read_address_S+1;
+ sec1_m_S <= 0;
+ state_S <= SECONDAIRY2;
+ elsif (sec1_m_S=conv_integer(unsigned(data_write_address_S))-1) and
+ (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) then
+ similarities_source_S <= similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS);
+ similarities_destination_S <= similarities_data_out_S(CLUSTERBITS-1 downto 0);
+ sec1_m_S <= 0;
+ state_S <= ADJUSTSIMULARITIES;
+ end if;
+ when ADJUSTSIMULARITIES =>
+ similarities_data_in_S <= similarities_data_out_S;
+ similarities_write_address_S <= conv_std_logic_vector(sec1_j_S,CLUSTERBITS);
+ if similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)=similarities_source_S then
+ similarities_data_in_S(CLUSTERBITS*2-1 downto CLUSTERBITS) <= similarities_destination_S;
+ similarities_write_S <= '1';
+ end if;
+ if similarities_data_out_S(CLUSTERBITS-1 downto 0)=similarities_source_S then
+ similarities_data_in_S(CLUSTERBITS-1 downto 0) <= similarities_destination_S;
+ similarities_write_S <= '1';
+ end if;
+ if sec1_j_S<simLength_S-1 then
+ sec1_j_S <= sec1_j_S+1;
+ else
+ sec1_j_S <= sec1_i_S+1;
+ state_S <= SECONDAIRY1;
+ end if;
+ when SECONDAIRY2 =>
+ results_index_S <= 0;
+ if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S then
+ sec2_n_S <= '1';
+ isAdded_data_in_S <= '1' & conv_std_logic_vector(nPreclusters_S,CLUSTERBITS);
+ isAdded_write_address_S <= conv_std_logic_vector(sec1_m_S,CLUSTERBITS);
+ isAdded_write_S <= '1';
+ end if;
+ if (nClusters_S>0) then
+ if sec1_m_S<conv_integer(unsigned(data_write_address_S))-1 then
+ sec1_m_S <= sec1_m_S+1;
+ else
+ sec1_m_S <= 0;
+ sec2_i_S <= sec2_i_S+1;
+ if (sec2_n_S='1') or (conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S) then
+ if nPreclusters_S<2**MAXCLUSTERSBITS-1 then
+ nPreclusters_S <= nPreclusters_S+1;
+--// nPreclusters_V := nPreclusters_S+1;
+ else
+ error_S <= '1';
+ end if;
+ end if;
+ sec2_n_S <= '0';
+ end if;
+ end if;
+
+ if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S then
+ result_nrofhits_V := result_nrofhits_V+1;
+ if data_in_Xpad_S<=result_Xpad_min_V then
+ result_Xpad_min_V := data_in_Xpad_S;
+ end if;
+ if data_in_Ypad_S<=result_Ypad_min_V then
+ result_Ypad_min_V := data_in_Ypad_S;
+ end if;
+ if data_in_Xpad_S>=result_Xpad_max_V then
+ result_Xpad_max_V := data_in_Xpad_S;
+ end if;
+ if data_in_Ypad_S>=result_Ypad_max_V then
+ result_Ypad_max_V := data_in_Ypad_S;
+ end if;
+ if data_in_energy_S>result_energy_max_V then
+ result_energy_max_V := data_in_energy_S;
+ result_time_max_V := data_in_time_S;
+ end if;
+ if (minimal_energy_reached_V='0') and (conv_integer(unsigned(sum_energy_V))+conv_integer(unsigned(data_in_energy_S))<conv_integer(unsigned(minimal_energy_S))) then
+ sum_energy_V := sum_energy_V+data_in_energy_S(MINIMUMENERGYBITS-1 downto 0);
+ else
+ minimal_energy_reached_V := '1';
+ end if;
+ if data_in_onedge_S='1' then
+ result_onedge_V := '1';
+ end if;
+ hitidx_data_in_S <= isAdded_read_address_aftr1clk_S;
+ hitidx_write_address_V := hitidx_write_address_V+1;
+ hitidx_write_address_S <= hitidx_write_address_V;
+ hitidx_write_S <='1';
+ end if;
+ if (nClusters_S>0) then
+ if sec1_m_S<conv_integer(unsigned(data_write_address_S))-1 then
+ if sec1_m_S+1<conv_integer(unsigned(data_write_address_S))-1 then
+ data_read_address_S <= data_read_address_S+1;
+ else
+ data_read_address_S <= (others => '0');
+ end if;
+ else
+ data_read_address_S <= data_read_address_S+1;
+ if (sec2_n_S='1') or (conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S)
+-- or
+-- ((sec2_i_S=nClusters_S-1) and (sec1_m_S=conv_integer(unsigned(data_write_address_S))-1))
+ then
+ if result_Xpad_max_V-result_Xpad_min_V>result_Ypad_max_V-result_Ypad_min_V then
+ result_diameter_V := (1+result_Xpad_max_V)-result_Xpad_min_V;
+ else
+ result_diameter_V := (1+result_Ypad_max_V)-result_Ypad_min_V;
+ end if;
+ result_diameter_S <= result_diameter_V;
+ result_time_S <= result_time_max_V;
+ result_positionX_V := ('0'&result_Xpad_min_V)+('0'&result_Xpad_max_V);
+ result_positionX_S <= result_positionX_V(XYPAD_BITSIZE downto 1);
+ result_positionY_V := ('0'&result_Ypad_min_V)+('0'&result_Ypad_max_V);
+ result_positionY_S <= result_positionY_V(XYPAD_BITSIZE downto 1);
+ results_data_in_S <= result_startaddress_V & result_nrofhits_V & result_time_max_V & result_diameter_V & result_positionX_V & result_positionY_V;
+ result_nrofhits_S <= result_nrofhits_V;
+ result_onedge_S <= result_onedge_V;
+ if (result_onedge_V='1') or (SKIPSINGLEHITCLUSTERS=FALSE) or (minimal_energy_reached_V='1') then -- or (result_nrofhits_V>1)
+ results_write_S <= '1';
+ results_write_address_S <= results_write_address_S+1;
+ results_filled_S <= '1';
+ result_startaddress_V := hitidx_write_address_V+1;
+ nPreclusters_V := nPreclusters_V+1;
+ else
+ hitidx_write_address_V := hitidx_write_address_V-result_nrofhits_V;
+ end if;
+ end if;
+ result_nrofhits_V := (others => '0');
+ result_Xpad_min_V := (others => '1');
+ result_Ypad_min_V := (others => '1');
+ result_Xpad_max_V := (others => '0');
+ result_Ypad_max_V := (others => '0');
+ result_energy_max_V := (others => '0');
+ result_time_max_V := (others => '0');
+ result_onedge_V := '0';
+ minimal_energy_reached_V := '0';
+ sum_energy_V := (others => '0');
+ end if;
+ end if;
+
+ if ((sec2_i_S=nClusters_S-1) and (sec1_m_S=conv_integer(unsigned(data_write_address_S))-1)) or (nClusters_S=0) then
+ if (nPreclusters_V<=1) then
+ nPreclusters_S <= nPreclusters_V;
+ state_S <= WRITESUPERBURST;
+ else
+ nPreclusters_S <= nPreclusters_V;
+ state_S <= SORTING;
+ end if;
+ end if;
+ when SORTING =>
+ results_index_S <= 0;
+ if (((sort_readkey_S='0') and (sort_i_S>=results_write_address_S-1)) and
+ ((sort_j_neg_S='1') or (results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2)<=sort_key_S))) or
+ ((sort_readkey_S='1') and (sort_i_S>=results_write_address_S) and (stateprev_S/=SECONDAIRY2)) then
+ state_S <= WRITESUPERBURST;
+ end if;
+ when WRITESUPERBURST =>
+ -- results_read_address_S <= clustersortarray_S(0)
+ -- data_read_address_S <= hitidx_data_out_S;
+ -- hitidx_read_address_S <= results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24);
+ if only_one_hit_S='1' then
+ nPreclusters_S <= 1;
+ results_write_address_S <= (others => '0');
+ results_data_in_S <= ZEROS(CLUSTERBITS-1 downto 0) & ZEROS(CLUSTERBITS-1 downto 1)&'1' &
+ data_in_time_S & conv_std_logic_vector(1,XYPAD_BITSIZE) & data_in_Xpad_S & '0' & data_in_Ypad_S & '0';
+ results_write_S <= '1';
+ end if;
+ sec1_m_S <= 0;
+ results_index_S <= 0;
+ if (data_out_clusterallowed='1') then
+ data_out_first_S <= data_first_S;
+ data_out_write_S <= data_first_S;
+ if (nPreclusters_S=0) and (only_one_hit_S='0') then
+ if data_last_S='1' then
+ data_out_last_S <= '1';
+ end if;
+ data_first_S <= '0';
+ data_last_S <= '0';
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ nextcluster_S <= '1';
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ else
+ state_S <= WRITECLUSTER;
+ end if;
+ end if;
+ when WRITECLUSTER =>
+ -- data_read_address_S <= hitidx_data_out_S;
+ -- results_read_address_S <= clustersortarray_S(results_index_S)
+ results_index_S <= results_index_S+1;
+ data_out_S <= (others => '0');
+ data_out_S(63 downto 40) <= results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2); -- time 24 bits
+ data_out_S(XYPAD_BITSIZE+29 downto 30) <= results_data_out_S(XYPAD_BITSIZE*3+2-1 downto XYPAD_BITSIZE*2+2); -- diameter 10bits
+ data_out_S(XYPAD_BITSIZE+20 downto 20) <= results_data_out_S(XYPAD_BITSIZE*2+1 downto XYPAD_BITSIZE+1); -- X *2 10bits
+ data_out_S(XYPAD_BITSIZE+10 downto 10) <= results_data_out_S(XYPAD_BITSIZE downto 0); -- Y *2 10bits
+ data_out_S(CLUSTERBITS-1 downto 0) <= results_data_out_S(CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2+24); -- number of hits 10bits
+ data_out_write_S <= '1';
+ hitidx_index_S <= conv_integer(unsigned(results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24)));
+ hitidx_endaddress_S <= conv_integer(unsigned(results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24)))+
+ conv_integer(unsigned(results_data_out_S(CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2+24)));
+ state_S <= WRITEHITS0;
+ when WRITEHITS0 =>
+ hitidx_index_S <= hitidx_index_S+1;
+ state_S <= WRITEHITS;
+ when WRITEHITS =>
+ -- results_read_address_S <= clustersortarray_S(results_index_S)
+ -- data_read_address_S <= hitidx_data_out_S;
+ data_out_S <= data_in_time_S & data_in_statusbyte_S & data_in_channel_S & data_in_energy_S;
+ data_out_write_S <= '1';
+ if hitidx_index_S<hitidx_endaddress_S then
+ hitidx_index_S <= hitidx_index_S+1;
+ -- hitidx_read_address_S <= hitidx_index_S+1;
+ else
+ if results_index_S<nPreclusters_S then
+ state_S <= WRITECLUSTER;
+ else
+ if data_last_S='1' then
+ data_out_last_S <= '1';
+ end if;
+ data_first_S <= '0';
+ data_last_S <= '0';
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ nextcluster_S <= '1';
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ end if;
+ end if;
+ when others =>
+ data_write_address_S <= (others => '0');
+ state_S <= INITIALIZE;
+ end case;
+ data_read_address_prev_S <= data_read_address_S;
+ if reset='1' then
+ data_first_S <= '0';
+ data_last_S <= '0';
+ isAdded_data_in_S <= (others => '0');
+ isAdded_write_S <= '1';
+ isAdded_write_address_S <= (others => '0');
+ data_write_address_S <= (others => '0');
+ data_out_write_S <= '0';
+ data_out_first_S <= '0';
+ data_out_last_S <= '0';
+ nextcluster_S <= '0';
+ state_S <= INITIALIZE;
+ end if;
+ debug_minimal_energy_reached_S <= minimal_energy_reached_V;
+ end if;
+end process;
+
+data_out_write <= data_out_write_S;
+data_out_last <= '1' when (data_out_last_S='1') and (data_out_write_S='1') else '0';
+data_out_first <= '1' when (data_out_first_S='1') and (data_out_write_S='1') else '0';
+data_out <= data_out_S;
+nextcluster <= nextcluster_S;
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0) := (others => '0');
+variable clusterresult_V : std_logic := '0';
+variable same_superburst_V : std_logic := '0';
+variable nrofhits_V : std_logic_vector(9 downto 0) := (others => '0');
+variable hitscounter_V : std_logic_vector(9 downto 0) := (others => '0');
+variable prev_resulttime_V : std_logic_vector(23 downto 0) := (others => '0');
+variable prev_hittime_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ debug_error_S <= '0';
+ if data_out_write_S='1' then
+ if data_out_first_S='1' then
+ if data_out_S(30 downto 0) < prev_superburst_V then
+ debug_error_S <= '1';
+ end if;
+ if data_out_S(30 downto 0)=prev_superburst_V then
+ same_superburst_V := '1';
+ else
+ same_superburst_V := '0';
+ end if;
+ prev_superburst_V := data_out_S(30 downto 0);
+ clusterresult_V := '1';
+ elsif clusterresult_V='1' then
+ if hitscounter_V/=nrofhits_V then
+ debug_error_S <= '1';
+ end if;
+ nrofhits_V := data_out_S(9 downto 0);
+ if (same_superburst_V='1') and (prev_resulttime_V>data_out_S(63 downto 40)) then
+ debug_error_S <= '1';
+ end if;
+ same_superburst_V := '1';
+ prev_resulttime_V := data_out_S(63 downto 40);
+ hitscounter_V := (others => '0');
+ prev_hittime_V := (others => '0');
+ clusterresult_V := '0';
+ else
+ if data_out_last_S='1' then
+ if hitscounter_V/=nrofhits_V-1 then
+ debug_error_S <= '1';
+ end if;
+ end if;
+ if data_out_S(63 downto 40)<prev_hittime_V then
+ debug_error_S <= '1';
+ end if;
+ prev_hittime_V := data_out_S(63 downto 40);
+ if hitscounter_V=nrofhits_V-1 then
+ clusterresult_V := '1';
+ end if;
+ hitscounter_V := hitscounter_V+1;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if state_S=INITIALIZE then
+ nrofclocks_S <= 0;
+ else
+ nrofclocks_S <= nrofclocks_S+1;
+ end if;
+ end if;
+end process;
+
+--process(clock)
+--begin
+-- if (rising_edge(clock)) then
+-- if isAdded_write_S='1' then
+-- if isAdded_data_in_S(CLUSTERBITS)='0' then
+-- debug_isAdded_S(conv_integer(unsigned(isAdded_write_address_S))) <= -1;
+-- else
+-- debug_isAdded_S(conv_integer(unsigned(isAdded_write_address_S))) <= conv_integer(unsigned(isAdded_data_in_S(CLUSTERBITS-1 downto 0)));
+-- end if;
+-- end if;
+-- end if;
+--end process;
+
+--process(clock)
+--begin
+-- if (rising_edge(clock)) then
+-- if similarities_write_S='1' then
+-- similarities_s(conv_integer(unsigned(similarities_write_address_S))*2) <= similarities_data_in_S(CLUSTERBITS*2-1 downto CLUSTERBITS);
+-- similarities_s(conv_integer(unsigned(similarities_write_address_S))*2+1) <= similarities_data_in_S(CLUSTERBITS-1 downto 0);
+-- end if;
+-- end if;
+--end process;
+
+
+testword0(0) <= data_in_active;
+testword0(1) <= data_in_write;
+testword0(2) <= data_in_first;
+testword0(3) <= data_in_last;
+testword0(7 downto 4) <=
+ x"0" when state_S=INITIALIZE else
+ x"1" when state_S=COLLECT else
+ x"2" when state_S=PRE_READ0 else
+ x"3" when state_S=PRE_READ1 else
+ x"4" when state_S=PRIMARY else
+ x"5" when state_S=PRIMARY1 or state_S=PRIMARY1_0 else
+ x"6" when state_S=PRIMARY2 or state_S=PRIMARY2_0 else
+ x"7" when state_S=SECONDAIRY or state_S=SECONDAIRY1 else
+ x"8" when state_S=ADJUSTSIMULARITIES else
+ x"9" when state_S=SECONDAIRY2 else
+ x"a" when state_S=SORTING else
+ x"b" when state_S=WRITESUPERBURST else
+ x"c" when state_S=WRITECLUSTER else
+ x"d" when state_S=WRITEHITS0 else
+ x"e" when state_S=WRITEHITS else
+ x"f";
+testword0(8) <= data_first_S;
+testword0(9) <= data_last_S;
+testword0(10) <= data_out_write_S;
+testword0(11) <= data_out_first_S;
+testword0(12) <= data_out_last_S;
+testword0(13) <= data_out_clusterallowed;
+testword0(14) <= overflow_S;
+testword0(15) <= debug_error_S;
+testword0(16) <= error_S;
+testword0(17) <= nextcluster_S;
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 26-06-2016
+-- Module Name: CN_precluster_findgap
+-- Description: Breaks stream of hits into timebunches
+-- Modifications:
+-- 04-01-2017 HEADERWORD0 added
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_precluster_findgap
+-- Breaks stream of hits into timebunches.
+-- If the time between two hits is larger than the specified gap time, or if a new superburst starts,
+-- then an output signal indicates that the next timebuch is starting.
+-- The following parameters are added to the data : X-position of the crystal, Y-position of the crystal,
+-- on edge signal that indicates if the crystal is on the edge of a Data Concentrator region.
+--
+-- The 64 bits input packets, according to SODAnet specs, (wave data is ignored):
+-- 64bits word1: only if HEADERWORD0=true
+-- bit63 = last-packet flag
+-- bit62..48 = packet number
+-- bit47..32 = data size in bytes
+-- bit31..0 = Not used (same as HADES)
+-- 64bits word2:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- for pulse data
+-- 64bits word3 and further, for each pulse:
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- for wave data
+-- 64bits word3:
+-- bit63..56 = status byte
+-- bit55..40 = adc channel
+-- bit39..32 = number of samples in wave
+-- bit15..0 = timestamp in respect to superburst of the first sample in the waveform
+-- 64bits word4 and further :
+-- bit63..48 = next_adcsample(15:0)
+-- bit47..32 = next_adcsample(15:0)
+-- bit31..16 = next_adcsample(15:0)
+-- bit15..0 = next_adcsample(15:0)
+--
+-- Output data:
+-- 64bits word1, only valid on a new superburst, when the signal data_out_first is active:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+-- 64bits word2 and further, for each pulse:
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+--
+-- Library
+--
+-- Generics:
+-- XYPAD_BITSIZE : number of bits for the X and Y position
+-- HEADERWORD0 : Panda header word in data
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset
+-- gap_time : maximum gap time between hits, resolutie from Constant Fraction (6.1ps)
+-- XYLUT_write : write signal for XY position and on-edge Look Up Table
+-- XYLUT_load : when '1' the LUT can be loaded with values, on '0' the writing address is set back to zero
+-- XYLUT_data : loading data for the LUT: 'on edge', X-value, Y-value
+-- data_in : 64bits data
+-- data_in_first : indicates that 64bits data is first in a packet
+-- data_in_last : indicates that 64bits data is last in packet
+-- data_in_write : write signal for 64bits data
+-- data_out_allowed : allowed to write output data
+--
+--
+-- Outputs:
+-- data_in_allowed : writing of input data allowed
+-- data_out : 64 bits output data
+-- data_out_Xpad : X-position of the hit in the output data
+-- data_out_Ypad : Y-position of the hit in the output data
+-- data_out_onedge : the hit in the output data is positioned on the edge of the Data Concentrator region
+-- data_out_active : timebunch active
+-- data_out_nexttimebunch : actual and further output data belongs to new timebunch
+-- data_out_write : write signal for 64 bits / XY and on-edge output data
+-- data_out_first : 64 bits output data contains new superburst
+-- data_out_last : 64 bits output data is the last data of a superburst
+-- superburst_rewind : new superburstnumber is lower than previous
+-- dataerror : error in data
+--
+-- Components:
+-- CN_cluster_XY_LUT : memory block for X,Y position and on-edge Look Up Table
+--
+----------------------------------------------------------------------------------
+
+entity CN_precluster_findgap is
+ generic(
+ XYPAD_BITSIZE : natural := 7;
+ HEADERWORD0 : boolean := TRUE
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ gap_time : in std_logic_vector(23 downto 0);
+ XYLUT_write : in std_logic;
+ XYLUT_load : in std_logic;
+ XYLUT_data : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_Xpad : out std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+ data_out_Ypad : out std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+ data_out_onedge : out std_logic;
+ data_out_active : out std_logic;
+ data_out_nexttimebunch : out std_logic;
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ superburst_rewind : out std_logic;
+ dataerror : out std_logic
+ );
+end CN_precluster_findgap;
+
+
+architecture behaviour of CN_precluster_findgap is
+
+component CN_cluster_XY_LUT is
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(15 downto 0);
+ data_in : in std_logic_vector(16 downto 0);
+ read_address : in std_logic_vector(15 downto 0);
+ data_out : out std_logic_vector(16 downto 0)
+ );
+end component;
+
+
+signal timeoutcount_S : std_logic_vector(17 downto 0);
+signal data_in_write_S : std_logic;
+signal data_in_allowed_S : std_logic;
+
+signal dataerror1_S : std_logic := '0';
+signal wave_S : std_logic := '0';
+signal new_superburst_S : std_logic := '0';
+signal time_S : std_logic_vector(23 downto 0);
+signal prev_suberburst_S : std_logic_vector(30 downto 0) := (others => '0');
+signal packetsize_S : integer range 0 to 65535;
+signal data_in_count_S : integer range 0 to 65535;
+signal waitforfirst_S : std_logic := '1';
+
+signal data_out_nextbunch_S : std_logic;
+signal data_out_nextbunch0_S : std_logic := '0';
+
+signal XYLUT_loadaddress_S : std_logic_vector(15 downto 0) := (others => '0');
+signal XYLUT_data_in_S : std_logic_vector(16 downto 0);
+signal XYlut_data_S : std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+signal XYlut_data0_S : std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+signal data_out_allowed_S : std_logic := '0';
+signal data_out_write0_S : std_logic := '0';
+signal data_out_active_S : std_logic := '0';
+signal data_out_write_S : std_logic := '0';
+signal data_out_last_S : std_logic := '0';
+signal data_out_first_S : std_logic := '0';
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of data_in : signal is "true";
+-- attribute mark_debug of data_in_write : signal is "true";
+-- attribute mark_debug of data_in_first : signal is "true";
+-- attribute mark_debug of data_in_last : signal is "true";
+-- attribute mark_debug of data_in_allowed : signal is "true";
+-- attribute mark_debug of data_out : signal is "true";
+-- attribute mark_debug of data_out_write : signal is "true";
+-- attribute mark_debug of data_out_first : signal is "true";
+-- attribute mark_debug of data_out_last : signal is "true";
+-- attribute mark_debug of data_out_allowed : signal is "true";
+-- attribute mark_debug of waitforfirst_S : signal is "true";
+-- attribute mark_debug of data_out_nextbunch_S : signal is "true";
+-- attribute mark_debug of data_out_allowed_S : signal is "true";
+-- attribute mark_debug of data_out_write0_S : signal is "true";
+-- attribute mark_debug of data_out_active_S : signal is "true";
+
+-- attribute mark_debug of timeoutcount_S : signal is "true";
+-- attribute mark_debug of dataerror1_S : signal is "true";
+
+begin
+
+dataerror <= '1' when (dataerror1_S='1') else '0';
+data_in_allowed_S <= '1' when (data_out_allowed='1') and (XYLUT_load='0')
+and (data_out_last_S='0') --//
+else '0';
+data_in_allowed <= data_in_allowed_S;
+data_out_write <= '1' when (data_out_write_S='1') and (data_out_allowed='1') else '0';
+data_out_last <= data_out_last_S;
+data_in_write_S <= '1' when (data_in_write='1') and (data_in_allowed_S='1') else '0';
+data_out_first <= data_out_first_S;
+
+data_out_active <= data_out_active_S;
+data_out_nexttimebunch <= data_out_nextbunch_S;
+
+
+-- Look Up Table to translate ADC channel number to XY pad position
+XYLUT_data_in_S(XYPAD_BITSIZE-1 downto 0) <= XYLUT_data(XYPAD_BITSIZE-1 downto 0);
+XYLUT_data_in_S(XYPAD_BITSIZE+7 downto 8) <= XYLUT_data(XYPAD_BITSIZE*2-1 downto XYPAD_BITSIZE);
+XYLUT_data_in_S(16) <= XYLUT_data(2*XYPAD_BITSIZE);
+LUT1: CN_cluster_XY_LUT port map(
+ clock => clock,
+ write_enable => XYLUT_write,
+ write_address => XYLUT_loadaddress_S,
+ data_in => XYLUT_data_in_S,
+ read_address => data_in(31 downto 16),
+ data_out => XYlut_data_S);
+
+data_out_Xpad <= XYlut_data0_S(XYPAD_BITSIZE+7 downto 8) when (data_out_allowed_S='0') else XYlut_data_S(XYPAD_BITSIZE+7 downto 8);
+data_out_Ypad <= XYlut_data0_S(XYPAD_BITSIZE-1 downto 0) when (data_out_allowed_S='0') and (data_out_allowed='1') else XYlut_data_S(XYPAD_BITSIZE-1 downto 0);
+data_out_onedge <= XYlut_data0_S(16) when (data_out_allowed_S='0') and (data_out_allowed='1') else XYlut_data_S(XYPAD_BITSIZE*2);
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if XYLUT_load='1' then
+ if XYLUT_write='1' then
+ XYLUT_loadaddress_S <= XYLUT_loadaddress_S+1;
+ end if;
+ else
+ XYLUT_loadaddress_S <= (others => '0');
+ end if;
+ if data_out_write0_S='1' then
+ XYlut_data0_S <= XYlut_data_S;
+ end if;
+ data_out_allowed_S <= data_out_allowed;
+ end if;
+end process;
+
+
+-- input data handling process
+process(clock)
+variable prev_suberburst_V : std_logic_vector(30 downto 0);
+begin
+ if (rising_edge(clock)) then
+ dataerror1_S <= '0';
+ superburst_rewind <= '0';
+ data_out_nextbunch_S <= '0';
+ data_out_write0_S <= '0';
+ data_out_write_S <= '0';
+ data_out_last_S <= '0';
+ data_out_first_S <= '0';
+ if reset='1' then
+ waitforfirst_S <= '1';
+ data_out_nextbunch0_S <='0';
+ new_superburst_S <= '0';
+ data_out_active_S <= '0';
+ prev_suberburst_S <= (others => '0');
+ data_in_count_S <= 0;
+ else
+ if (data_out_nextbunch_S='1') and (data_out_allowed='0') then
+ --// data_out_nextbunch_S <= '1'; -- retry
+ end if;
+ if (data_out_write_S='1') and (data_out_allowed='0') then
+ data_out_write_S <= '1'; -- retry;
+ data_out_last_S <= data_out_last_S;
+ data_out_first_S <= data_out_first_S;
+ else
+ if data_out_last_S='1' then
+ data_out_active_S <= '0';
+ end if;
+ if data_out_nextbunch0_S='1' then
+ data_out_nextbunch_S <= '1';
+ data_out_nextbunch0_S <='0';
+ end if;
+ end if;
+ if (data_in_write_S='1') then
+ timeoutcount_S <= (others => '0');
+ if (data_in_first='1') and (HEADERWORD0=true) then
+ waitforfirst_S <= '0';
+ data_in_count_S <= 1;
+ if data_in(63)='0' then
+ dataerror1_S <= '1';
+ end if;
+ packetsize_S <= conv_integer(unsigned(data_in(47 downto 32)));
+ if data_in(31 downto 0)/=x"00000000" then
+ dataerror1_S <= '1';
+ end if;
+ data_out_active_S <= '0';
+ if new_superburst_S='0' then
+ data_out_nextbunch_S <= '1';
+ end if;
+ new_superburst_S <= '1';
+ elsif (waitforfirst_S='0') or (HEADERWORD0=false) then
+ if (data_in_last='1') and (HEADERWORD0=true) then
+ if packetsize_S/=(data_in_count_S+1)*8 then
+ dataerror1_S <= '1';
+ end if;
+ end if;
+ if (data_in_first='1') and (HEADERWORD0=false) then
+ if new_superburst_S='0' then
+ data_out_nextbunch_S <= '1';
+ end if;
+ new_superburst_S <= '1';
+ end if;
+ if ((data_in_count_S=1) and (HEADERWORD0=true)) or ((data_in_first='1') and (HEADERWORD0=false)) then
+ if data_in(63)='1' then
+ wave_S <= '1';
+ else
+ wave_S <= '0';
+ data_out <= data_in;
+ prev_suberburst_V := prev_suberburst_S+1;
+ if (data_in(30 downto 0)/=prev_suberburst_V) and (conv_integer(unsigned(prev_suberburst_S))/=0) then
+ dataerror1_S <= '1';
+ end if;
+ if prev_suberburst_S>data_in(30 downto 0) then
+ superburst_rewind <= '1';
+ end if;
+ prev_suberburst_S <= data_in(30 downto 0);
+ time_S <= (others => '0');
+ data_out_first_S <= '1';
+ data_out_write_S <= '1';
+ if data_in_last='1' then -- empty superburst
+ data_out_active_S <= '0';
+ data_out_last_S <= '1';
+ data_out_nextbunch0_S <= '1';
+ else
+ data_out_active_S <= '1';
+ end if;
+ end if;
+ elsif (wave_S='0') then
+ if data_in(63 downto 40) < time_S(23 downto 0) then
+ dataerror1_S <= '1';
+ end if;
+ time_S <= data_in(63 downto 40);
+ if (new_superburst_S='1') or ('0' & data_in(63 downto 40))>('0' & time_S) + ('0' & gap_time) then
+ if (new_superburst_S='0') then
+ data_out_nextbunch_S <= '1';
+ end if;
+ new_superburst_S <= '0';
+ data_out_active_S <= '1';
+ data_out <= data_in;
+ data_out_last_S <= data_in_last;
+ data_out_write_S <= '1';
+ data_out_write0_S <= '1';
+ else
+ data_out_active_S <= '1';
+ data_out <= data_in;
+ data_out_last_S <= data_in_last;
+ data_out_write_S <= '1';
+ data_out_write0_S <= '1';
+ end if;
+ end if;
+ data_in_count_S <= data_in_count_S+1;
+ end if;
+ else
+ if (data_out_active_S='1') then
+ if (timeoutcount_S(timeoutcount_S'left)='0') then
+ if data_out_allowed='1' then
+ timeoutcount_S <= timeoutcount_S+1;
+ end if;
+ else
+ data_out_nextbunch_S <= '1';
+ data_out_active_S <= '0';
+ -- superburst_rewind <= '1';
+ timeoutcount_S <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+
+end behaviour;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI-cart/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 01-07-2016
+-- Module Name: CN_preclustering
+-- Description: Pre-clustering part of the PANDA cluster finding
+-- Modifications:
+-- 04-01-2017 HEADERWORD0 added
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_preclustering
+-- First stage of the clustering algorithm, developed by Marcel Tiemens (KVI-cart) for the PANDA Detector at GSI.
+-- This stage searches for time-gaps in the measured hits (digis) and calculates which hits are part of the same cluster.
+-- Hits are considered to belong to the same cluster if the time and distance between the hits are small (next to each other, also diagonally).
+-- The timegap searching divides the input hit stream into time-bunches in module CN_precluster_findgap.
+-- The time-bunch is processed by module CN_precluster_build to split the data into preclusters.
+-- To increase the throughput several mudules are put in parallel.
+-- If a cluster contains only one hit and if this hit is not position on the edge of the region then this cluster is skipped.
+--
+-- The input data consist of a data package from the Panda Data concentrator. Waveforms packages are ignored.
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word1:
+-- bit63 = last-packet flag
+-- bit62..48 = packet number
+-- bit47..32 = data size in bytes
+-- bit31..0 = Not used (same as HADES)
+-- 64bits word2:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+--
+-- for pulse data
+-- 64bits word3 and further, for each pulse:
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+-- for wave data
+-- 64bits word3:
+-- bit63..56 = status byte
+-- bit55..40 = adc channel
+-- bit39..32 = number of samples in wave
+-- bit15..0 = timestamp in respect to superburst of the first sample in the waveform
+-- 64bits word4 and further :
+-- bit63..48 = next_adcsample(15:0)
+-- bit47..32 = next_adcsample(15:0)
+-- bit31..16 = next_adcsample(15:0)
+-- bit15..0 = next_adcsample(15:0)
+--
+-- The output data contains clusters, with in each cluster the original hit-data. There is no header with the size of the packet.
+-- Only a header for the superburst number.
+--
+-- 64bits word1:
+-- bi63..48 = Status
+-- bit48=internal data-error
+-- bit49=internal error
+-- bit50=error in pulse-data/superburst number
+-- bit63=0:pulse data packet, 1:waveform packet
+-- bit47..32 = System ID
+-- bit31 = 0
+-- bit30..0 = Super-burst number
+-- 64bits word2, clusterresults
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..30 = diameter
+-- bit29..20 = Y position, multiplied by 2
+-- bit19..10 = X position, multiplied by 2
+-- bit9..0 = number of hits in cluster
+-- 64bits word3..word4+nrofhits : pulse data
+-- bit63..51 = offset in respect to superburst
+-- bit50..40 = Time fraction (11 bits used)
+-- bit39..32 = status byte
+-- bit31..16 = adc channel
+-- bit15..0 = Energy (pulse height)
+--
+--
+-- Library
+--
+-- Generics:
+-- XYPAD_BITSIZE : number of bits for the X and Y position
+-- CLUSTERBITS : number of bits for the number of hits in one timebunch
+-- MAXCLUSTERSBITS : number of bits for the maximum clusters in one timebunch
+-- PARALLELBUILDS : number of CN_precluster_build modules to work in parallel
+-- MINIMUMENERGYBITS : number of bits for the miminum energy value
+-- SKIPSINGLEHITCLUSTERS : skip precluster if it contains only one hit and is not positioned on the edge
+-- HEADERWORD0 : Panda header word in data
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset
+-- gap_time : maximum gap time between hits, resolutie from Constant Fraction (6.1ps)
+-- timedifference : maximum difference in time between hits in a cluster, resolutie from Constant Fraction (6.1ps)
+-- minimal_energy : minimum energy for a cluster; clusters with less are skipped if they are not positioned on the edge of a region
+-- XYLUT_write : write signal for XY position and on-edge Look Up Table
+-- XYLUT_load : when '1' the LUT can be loaded with values, on '0' the writing address is set back to zero
+-- XYLUT_data : loading data for the LUT: 'on edge', X-value, Y-value
+-- data_in : 64bits data
+-- data_in_first : indicates that 64bits data is first in a packet
+-- data_in_last : indicates that 64bits data is last in packet
+-- data_in_write : write signal for 64bits data
+-- data_out_allowed : allowed to write output data
+--
+-- Outputs:
+-- data_in_allowed : writing of input data allowed
+-- data_out : 64 bits output data
+-- data_out_write : write signal for 64 bits output data
+-- data_out_first : 64 bits output data contains the new superburst number
+-- data_out_last : 64 bits output data is the last of a superburst (not necessarily the same as timebunch)
+-- superburst_rewind : new superburstnumber is lower than previous
+-- dataerror : error in data
+--
+-- Components:
+-- CN_precluster_findgap : Breaks stream of hits into timebunches
+-- CN_precluster_build : Construct clusters from a bunch of hits
+-- syncfifo_4096x66_almostempty3524 : synchronous fifo to buffer output data
+-- CN_fiforead2write : Converts reading from fifo to write
+--
+----------------------------------------------------------------------------------
+
+entity CN_preclustering is
+ generic(
+ XYPAD_BITSIZE : natural := 8;
+ CLUSTERBITS : natural := 8;
+ MAXCLUSTERSBITS : natural := 5;
+ PARALLELBUILDS : natural := 4;
+ MINIMUMENERGYBITS : natural := 8;
+ SKIPSINGLEHITCLUSTERS : boolean := FALSE;
+ HEADERWORD0 : boolean := TRUE
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ gap_time : in std_logic_vector(23 downto 0);
+ timedifference : in std_logic_vector(23 downto 0);
+ minimal_energy : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+ XYLUT_write : in std_logic;
+ XYLUT_load : in std_logic;
+ XYLUT_data : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ superburst_rewind : out std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(127 downto 0) := (others => '0')
+ );
+end CN_preclustering;
+
+
+architecture behaviour of CN_preclustering is
+
+component CN_precluster_findgap is
+ generic(
+ XYPAD_BITSIZE : natural := XYPAD_BITSIZE;
+ HEADERWORD0 : boolean := HEADERWORD0
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ gap_time : in std_logic_vector(23 downto 0);
+ XYLUT_write : in std_logic;
+ XYLUT_load : in std_logic;
+ XYLUT_data : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_write : in std_logic;
+ data_in_allowed : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_Xpad : out std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+ data_out_Ypad : out std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+ data_out_onedge : out std_logic;
+ data_out_active : out std_logic;
+ data_out_nexttimebunch : out std_logic;
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_allowed : in std_logic;
+ superburst_rewind : out std_logic;
+ dataerror : out std_logic
+ );
+end component;
+
+component CN_precluster_build is
+ generic(
+ XYPAD_BITSIZE : natural := XYPAD_BITSIZE;
+ CLUSTERBITS : natural := CLUSTERBITS;
+ MAXCLUSTERSBITS : natural := MAXCLUSTERSBITS;
+ MINIMUMENERGYBITS : natural := MINIMUMENERGYBITS;
+ SKIPSINGLEHITCLUSTERS : boolean := SKIPSINGLEHITCLUSTERS
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ timedifference : in std_logic_vector(23 downto 0);
+ minimal_energy : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+ data_in : in std_logic_vector(63 downto 0);
+ data_in_Xpad : in std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+ data_in_Ypad : in std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+ data_in_onedge : in std_logic;
+ data_in_active : in std_logic;
+ data_in_write : in std_logic;
+ data_in_first : in std_logic;
+ data_in_last : in std_logic;
+ data_in_allowed : out std_logic;
+ busy : out std_logic;
+ data_out : out std_logic_vector(63 downto 0);
+ data_out_write : out std_logic;
+ data_out_first : out std_logic;
+ data_out_last : out std_logic;
+ data_out_clusterallowed : in std_logic;
+ nextcluster : out std_logic;
+ dataerror : out std_logic;
+ testword0 : out std_logic_vector(36 downto 0) := (others => '0')
+ );
+end component;
+
+component syncfifo_1024x66_almostempty256 is
+ port(
+ clk : in std_logic;
+ srst : in std_logic;
+ din : in std_logic_vector(65 DOWNTO 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(65 DOWNTO 0);
+ full : out std_logic;
+ empty : out std_logic;
+ prog_empty : out std_logic
+ );
+end component;
+
+component syncfifo_4096x66_almostempty3524 is
+ port(
+ clk : in std_logic;
+ srst : in std_logic;
+ din : in std_logic_vector(65 DOWNTO 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(65 DOWNTO 0);
+ full : out std_logic;
+ empty : out std_logic;
+ prog_empty : out std_logic
+ );
+end component;
+
+component CN_fiforead2write is
+ generic(
+ BITS : integer := 66
+ );
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(BITS-1 downto 0);
+ data_in_empty : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(BITS-1 downto 0);
+ data_out_write : out std_logic;
+ data_out_allowed : in std_logic
+ );
+end component;
+
+signal data_S : std_logic_vector(63 downto 0);
+signal data_Xpad_S : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data_Ypad_S : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data_onedge_S : std_logic;
+signal data_active_S : std_logic;
+signal data_write_S : std_logic;
+signal data_last_S : std_logic;
+signal data_first_S : std_logic;
+signal data_allowed_S : std_logic;
+signal data_out_nexttimebunch_S: std_logic;
+signal superburst_rewind_S : std_logic;
+
+signal build_reset_S : std_logic;
+signal build_actual0_S : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_next_S : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_actual_S : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_read_S : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_active_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_allowed_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_write_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_write_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_firsts_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_last_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_allowed_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal busy_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_nextcluster_S : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_error_S : std_logic_vector(0 to PARALLELBUILDS-1);
+
+signal fifoout0_datain_S : std_logic_vector(65 downto 0);
+signal fifoout_datain_S : std_logic_vector(65 downto 0);
+signal fifoout_dataout_S : std_logic_vector(65 downto 0);
+signal fifoout_reset_S : std_logic;
+signal fifoout_write_S : std_logic;
+signal fifoout_read_S : std_logic;
+signal fifoout_full_S : std_logic;
+signal fifoout_empty_S : std_logic;
+signal fifoout_prog_empty_S : std_logic;
+
+
+
+signal dataerror0_S : std_logic;
+
+type data_out_type is array(0 to PARALLELBUILDS-1) of std_logic_vector(63 downto 0);
+signal data_out_S : data_out_type;
+
+signal debug_data_in_error_S : std_logic;
+signal debug_error_S : std_logic;
+type testwords36_type is array(0 to PARALLELBUILDS-1) of std_logic_vector(36 downto 0);
+signal testwords36_S : testwords36_type;
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of debug_data_in_error_S : signal is "true";
+-- attribute mark_debug of debug_error_S : signal is "true";
+-- attribute mark_debug of dataerror0_S : signal is "true";
+-- attribute mark_debug of build_error_S : signal is "true";
+
+-- attribute mark_debug of fifoout_datain_S : signal is "true";
+-- attribute mark_debug of fifoout_write_S : signal is "true";
+-- attribute mark_debug of fifoout_full_S : signal is "true";
+-- attribute mark_debug of fifoout_empty_S : signal is "true";
+
+
+begin
+
+dataerror <= '1' when (dataerror0_S='1') or (conv_integer(unsigned(build_error_S))/=0) or (fifoout_full_S='1') else '0';
+superburst_rewind <= superburst_rewind_S;
+
+CN_precluster_findgap1: CN_precluster_findgap port map(
+ clock => clock,
+ reset => reset,
+ gap_time => gap_time,
+ XYLUT_write => XYLUT_write,
+ XYLUT_load => XYLUT_load,
+ XYLUT_data => XYLUT_data,
+ data_in => data_in,
+ data_in_first => data_in_first,
+ data_in_last => data_in_last,
+ data_in_write => data_in_write,
+ data_in_allowed => data_in_allowed,
+ data_out => data_S,
+ data_out_Xpad => data_Xpad_S,
+ data_out_Ypad => data_Ypad_S,
+ data_out_onedge => data_onedge_S,
+ data_out_active => data_active_S,
+ data_out_nexttimebunch => data_out_nexttimebunch_S,
+ data_out_write => data_write_S,
+ data_out_last => data_last_S,
+ data_out_first => data_first_S,
+ data_out_allowed => data_allowed_S,
+ superburst_rewind => superburst_rewind_S,
+ dataerror => dataerror0_S);
+
+data_allowed_S <= build_allowed_S(build_actual_S);
+
+build_actual_S <= build_next_S when (data_out_nexttimebunch_S='1') else build_actual0_S;
+build_next_S <= 0 when build_actual0_S>=PARALLELBUILDS-1 else build_actual0_S+1;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ build_actual0_S <= 0;
+ else
+ if (data_out_nexttimebunch_S='1') then
+ if build_actual0_S<PARALLELBUILDS-1 then
+ build_actual0_S <= build_actual0_S+1;
+ else
+ build_actual0_S <= 0;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+----------
+-- data_allowed_S <= '1' when
+ -- ((build_allowed_S(build_actual0_S)='1') and (data_out_nexttimebunch_S='0')) or
+ -- ((build_allowed_S(build_next_S)='1') and (data_out_nexttimebunch_S='1'))
+ -- else '0';
+
+-- build_actual_S <= build_next_S when (data_out_nexttimebunch_S='1') and (build_allowed_S(build_next_S)='1') else build_actual0_S;
+-- build_next_S <= 0 when build_actual0_S>=PARALLELBUILDS-1 else build_actual0_S+1;
+
+-- process(clock)
+-- begin
+ -- if (rising_edge(clock)) then
+ -- if (data_out_nexttimebunch_S='1') and (data_allowed_S='1') then
+ -- if build_actual0_S<PARALLELBUILDS-1 then
+ -- build_actual0_S <= build_actual0_S+1;
+ -- else
+ -- build_actual0_S <= 0;
+ -- end if;
+ -- end if;
+ -- end if;
+-- end process;
+
+CN_cluster_builds: for idx in 0 to PARALLELBUILDS-1 generate
+
+ build_write_S(idx) <= data_write_S when idx=build_actual_S else '0';
+ build_active_S(idx) <= data_active_S when idx=build_actual_S else '0';
+ build_reset_S <= '1' when (superburst_rewind_S='1') or (reset='1') else '0';
+
+ CN_precluster_build0: CN_precluster_build port map(
+ clock => clock,
+ reset => build_reset_S,
+ timedifference => timedifference,
+ minimal_energy => minimal_energy,
+ data_in => data_S,
+ data_in_Xpad => data_Xpad_S,
+ data_in_Ypad => data_Ypad_S,
+ data_in_onedge => data_onedge_S,
+ data_in_active => build_active_S(idx),
+ data_in_write => build_write_S(idx),
+ data_in_first => data_first_S,
+ data_in_last => data_last_S,
+ data_in_allowed => build_allowed_S(idx),
+ busy => busy_S(idx),
+ data_out => data_out_S(idx),
+ data_out_write => data_out_write_S(idx),
+ data_out_first => data_out_firsts_S(idx),
+ data_out_last => data_out_last_S(idx),
+ data_out_clusterallowed => data_out_allowed_S(idx),
+ nextcluster => build_nextcluster_S(idx),
+ dataerror => build_error_S(idx),
+ testword0 => testwords36_S(idx));
+data_out_allowed_S(idx) <= fifoout_prog_empty_S when build_read_S=idx else '0';
+
+end generate;
+
+-- fifoout_datain_S(63 downto 0) <= data_out_S(build_read_S);
+-- fifoout_write_S <= data_out_write_S(build_read_S);
+-- fifoout_datain_S(65) <= data_out_firsts_S(build_read_S);
+-- fifoout_datain_S(64) <= data_out_last_S(build_read_S);
+process(clock)
+variable regfilled_V : std_logic := '0';
+begin
+ if (rising_edge(clock)) then
+ fifoout_write_S <= '0';
+ if reset='1' then
+ regfilled_V := '0';
+ else
+ if data_out_write_S(build_read_S)='1' then
+ fifoout0_datain_S(63 downto 0) <= data_out_S(build_read_S);
+ fifoout0_datain_S(65) <= data_out_firsts_S(build_read_S);
+ fifoout0_datain_S(64) <= data_out_last_S(build_read_S);
+ if regfilled_V='1' then
+ fifoout_datain_S <= fifoout0_datain_S;
+ if data_out_firsts_S(build_read_S)='1' then
+ fifoout_datain_S(64) <= '1'; -- force last
+ end if;
+ fifoout_write_S <= '1';
+ regfilled_V := '1';
+ else
+ if data_out_last_S(build_read_S)='1' then
+ fifoout_datain_S(63 downto 0) <= data_out_S(build_read_S);
+ fifoout_datain_S(65) <= data_out_firsts_S(build_read_S);
+ fifoout_datain_S(64) <= '1';
+ fifoout_write_S <= '1';
+ regfilled_V := '0';
+ else
+ regfilled_V := '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ build_read_S <= 0;
+ else
+ if build_actual_S/=build_read_S then
+ if busy_S(build_read_S)='0' then
+ if build_read_S<PARALLELBUILDS-1 then
+ build_read_S <= build_read_S+1;
+ else
+ build_read_S <= 0;
+ end if;
+ end if;
+ else
+ if (build_nextcluster_S(build_read_S)='1') then
+ if build_read_S<PARALLELBUILDS-1 then
+ build_read_S <= build_read_S+1;
+ else
+ build_read_S <= 0;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+fifoout_reset_S <= '1' when (superburst_rewind_S='1') or (reset='1') else '0';
+outfifo: syncfifo_1024x66_almostempty256 port map(
+--outfifo: syncfifo_4096x66_almostempty3524 port map(
+ clk => clock,
+ srst => fifoout_reset_S,
+ din => fifoout_datain_S,
+ wr_en => fifoout_write_S,
+ rd_en => fifoout_read_S,
+ dout => fifoout_dataout_S,
+ full => fifoout_full_S,
+ empty => fifoout_empty_S,
+ prog_empty => fifoout_prog_empty_S);
+
+
+read2write: CN_fiforead2write port map(
+ clock => clock,
+ reset => fifoout_reset_S,
+ data_in => fifoout_dataout_S,
+ data_in_empty => fifoout_empty_S,
+ data_in_read => fifoout_read_S,
+ data_out(65) => data_out_first,
+ data_out(64) => data_out_last,
+ data_out(63 downto 0) => data_out,
+ data_out_write => data_out_write,
+ data_out_allowed => data_out_allowed);
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0) := (others => '0');
+variable clusterresult_V : std_logic := '0';
+variable same_superburst_V : std_logic := '0';
+variable nextissuperburst_V : std_logic := '1';
+variable nrofhits_V : std_logic_vector(9 downto 0) := (others => '0');
+variable hitscounter_V : std_logic_vector(9 downto 0) := (others => '0');
+variable prev_resulttime_V : std_logic_vector(23 downto 0) := (others => '0');
+variable prev_hittime_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ debug_error_S <= '0';
+ if reset='1' then
+ prev_superburst_V := (others => '0');
+ clusterresult_V := '0';
+ same_superburst_V := '0';
+ nextissuperburst_V := '1';
+ nrofhits_V := (others => '0');
+ hitscounter_V := (others => '0');
+ prev_resulttime_V := (others => '0');
+ prev_hittime_V := (others => '0');
+ else
+ if fifoout_write_S='1' then
+ if fifoout_datain_S(65)='1' then -- first
+ if nextissuperburst_V='0' then
+ end if;
+ if (fifoout_datain_S(30 downto 0)/=prev_superburst_V+1) and (conv_integer(unsigned(prev_superburst_V))/=0) then
+ debug_error_S <= '1';
+ end if;
+ same_superburst_V := '0';
+ prev_superburst_V := fifoout_datain_S(30 downto 0);
+ clusterresult_V := '1';
+ if fifoout_datain_S(64)='1' then -- last
+ nextissuperburst_V := '1';
+ else
+ nextissuperburst_V := '0';
+ end if;
+ elsif clusterresult_V='1' then
+ if fifoout_datain_S(64)='1' then -- last
+ nextissuperburst_V := '1';
+ debug_error_S <= '1';
+ else
+ nextissuperburst_V := '0';
+ end if;
+ if hitscounter_V/=nrofhits_V then
+ debug_error_S <= '1';
+ end if;
+ nrofhits_V := fifoout_datain_S(9 downto 0);
+ if (same_superburst_V='1') and (prev_resulttime_V>fifoout_datain_S(63 downto 40)) then
+ debug_error_S <= '1';
+ end if;
+ same_superburst_V := '1';
+ prev_resulttime_V := fifoout_datain_S(63 downto 40);
+ hitscounter_V := (others => '0');
+ prev_hittime_V := (others => '0');
+ clusterresult_V := '0';
+ else
+ if fifoout_datain_S(64)='1' then -- last
+ if hitscounter_V/=nrofhits_V-1 then
+ debug_error_S <= '1';
+ end if;
+ nextissuperburst_V := '1';
+ else
+ nextissuperburst_V := '0';
+ end if;
+ if fifoout_datain_S(63 downto 40)<prev_hittime_V then
+ debug_error_S <= '1';
+ end if;
+ prev_hittime_V := fifoout_datain_S(63 downto 40);
+ if hitscounter_V=nrofhits_V-1 then
+ clusterresult_V := '1';
+ end if;
+ hitscounter_V := hitscounter_V+1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(clock)
+variable SB_V : std_logic_vector(30 downto 0);
+begin
+ if (rising_edge(clock)) then
+ debug_data_in_error_S <= '0';
+ if data_in_write='1' then
+ if data_in_first='1' then
+ if SB_V /= data_in(30 downto 0) then
+ debug_data_in_error_S <= '1';
+ end if;
+ SB_V := data_in(30 downto 0)+1;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+testword0(63 downto 0) <= fifoout_datain_S(63 downto 0);
+testword0(64) <= fifoout_datain_S(64);
+testword0(65) <= fifoout_datain_S(65);
+testword0(66) <= fifoout_write_S;
+testword0(67) <= fifoout_full_S;
+testword0(68) <= fifoout_prog_empty_S;
+testword0(70 downto 69) <= conv_std_logic_vector(build_read_S,2);
+testword0(71) <= superburst_rewind_S;
+testword0(72) <= dataerror0_S;
+testword0(73) <= debug_error_S;
+
+
+testword0(74) <= data_write_S;
+testword0(75) <= data_in_write;
+testword0(76) <= data_in_first;
+testword0(77) <= data_in_last;
+testword0(78) <= data_active_S;
+testword0(79) <= data_first_S;
+testword0(80) <= data_last_S;
+testword0(81) <= data_allowed_S;
+testword0(82) <= data_out_nexttimebunch_S;
+testword0(83) <= superburst_rewind_S;
+testword0(84) <= build_reset_S;
+testword0(85) <= build_allowed_S(0);
+testword0(86) <= build_allowed_S(1);
+
+testword0(105 downto 88) <= testwords36_S(0)(17 downto 0);
+testword0(123 downto 106) <= testwords36_S(1)(17 downto 0);
+
+
+end behaviour;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 18-07-2016
+-- Module Name: blockmemdirectread
+-- Description: Generic memory block
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- blockmemdirectread
+-- Generic memory block with separated addresses for reading and writing
+-- Data is immidiately available on output when read from written address
+--
+--
+-- generics
+-- ADDRESS_BITS : Number of bits for the address
+-- DATA_BITS : number of bits for data
+--
+-- inputs
+-- clock : clock
+-- write_enable : write to memory
+-- write_address : address to write to
+-- data_in : data to write into memory
+-- read_address : address to read from
+--
+-- outputs
+-- data_out : data from memory
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+entity blockmemdirectread is
+ generic (
+ ADDRESS_BITS : natural := 8;
+ DATA_BITS : natural := 18
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)
+ );
+end blockmemdirectread;
+
+architecture behavioral of blockmemdirectread is
+type mem_type is array (2**ADDRESS_BITS-1 downto 0) of std_logic_vector (DATA_BITS-1 downto 0);
+signal mem_S : mem_type := (others => (others => '0'));
+attribute RAM_STYLE : string;
+attribute RAM_STYLE of mem_S: signal is "BLOCK";
+
+signal data_out_S : std_logic_vector(DATA_BITS-1 downto 0);
+signal data_in_prev_S : std_logic_vector(DATA_BITS-1 downto 0);
+signal read_address_prev_S : std_logic_vector(ADDRESS_BITS-1 downto 0);
+signal correction0_S : std_logic;
+signal correction1_S : std_logic;
+signal correctionp_S : std_logic;
+
+begin
+
+ process (clock)
+ begin
+ if (clock'event and clock = '1') then
+ if (write_enable = '1') then
+ mem_S(conv_integer(write_address)) <= data_in;
+ end if;
+ data_out_S <= mem_S(conv_integer(read_address));
+ end if;
+ end process;
+
+data_out <=
+ data_in when correctionp_S='1' else
+ data_in_prev_S when correction1_S='1' else
+ data_out_S;
+
+correctionp_S <= '1' when (write_address=read_address_prev_S) and (write_enable='1') else '0';
+correction0_S <= '1' when (write_address=read_address) and (write_enable='1') else '0';
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ correction1_S <= correction0_S;
+ data_in_prev_S <= data_in;
+ read_address_prev_S <= read_address;
+ end if;
+end process;
+
+
+end architecture behavioral;
\ No newline at end of file
--- /dev/null
+----------------------------------------
+-- Conditional adder
+-- op_a + op_b or only op_a depending on sel
+--
+----------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity cond_adder is
+ generic (
+ XBITS : natural := 32;
+ YBITS : natural := 32
+ );
+ port (
+ op_a: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ op_b: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ sel: in STD_LOGIC;
+ outp: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+ );
+end cond_adder;
+
+architecture simple_arch of cond_adder is
+
+begin
+ anAdder: process (sel,op_a,op_b)
+ begin
+ if sel = '1' then
+ outp <= op_a + op_b;
+ else
+ outp <= op_a;
+ end if;
+ end process;
+end simple_arch;
+
--- /dev/null
+-----------------------------------------------------------------------
+---- Pipelined radix 4 Divisor based on Arch2 (half arch)
+---- A, and B naturals (non negative integers) with XBITS and YBITS width
+---- there is no restriction XBITS >= YBITS.
+---- Return quotient Q of XBITS and remainder R of NBITS
+---- GRAIN defines the amount of bits computed at each cycle.
+----
+---- The circuit captures operands at each cycle
+---- The algorithm needs XBITS/GRAIN/DEPTH + 1 cylcles to calculate the quotient
+---- and remainder (Latency). Its posible to obtain the result one cycle before.
+---- GRAIN = 2 for that radix 4 divider
+---- DEPTH (logic depth) every how many basic cell we register.
+---- DEPTH = 1 maximun pipeline
+----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity div_r4_pipe is
+ generic (
+ XBITS : natural := 32;
+ YBITS : natural := 32;
+ GRAIN : natural := 2;
+ DEPTH : natural := 8
+ );
+ port (
+ A: in STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ B: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ clk: in STD_LOGIC;
+ Q: out STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ R: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+ );
+end div_r4_pipe;
+
+architecture simple_arch of div_r4_pipe is
+
+ component cond_adder is
+ generic (
+ XBITS : natural := XBITS;
+ YBITS : natural := YBITS
+ );
+ port (
+ op_a: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ op_b: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ sel: in STD_LOGIC;
+ outp: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+ );
+ end component;
+
+ component nr_r4_half_cell is
+ generic (
+ XBITS : natural := XBITS;
+ YBITS : natural := YBITS
+ );
+ port (
+ op_r: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_y: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_3y: in STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ x_1: in STD_LOGIC;
+ x_0: in STD_LOGIC;
+ n_qneg: out STD_LOGIC_VECTOR (1 downto 0);
+ new_r: out STD_LOGIC_VECTOR (YBITS downto 0)
+ );
+ end component;
+
+
+ type connectionmatrix is array (0 to GRAIN) of STD_LOGIC_VECTOR (YBITS downto 0);
+ Signal iR, reg_Y_rem: STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ Signal iQ: STD_LOGIC_VECTOR (XBITS-1 downto 0);
+
+ type matrix_rem is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS downto 0);
+ signal rem_in, rem_out: matrix_rem := (others => (others => '0'));
+ type matrix_Y is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS downto 0);
+ signal reg_Y: matrix_Y := (others => (others => '0'));
+ type matrix_3Y is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ signal reg_3Y: matrix_3Y := (others => (others => '0'));
+ type matrix_X is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ signal reg_X: matrix_X := (others => (others => '0'));
+ type matrix_Q is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ signal reg_Q: matrix_Q := (others => (others => '0'));
+
+signal rem_no_adj: STD_LOGIC_VECTOR (YBITS downto 0);
+
+--attribute keep_hierarchy: string;
+--attribute keep_hierarchy of low_level_arch: architecture is "yes";
+--attribute IOB: string;
+--attribute IOB of low_level_arch: architecture is "FALSE";
+
+begin
+
+ FF_0: process (clk)
+ begin
+ if CLK'event and CLK='1' then --CLK rising edge
+ reg_Y(0) <= ('0' & B);
+ reg_3Y(0) <= ('0' & B) + ('0' & B & '0');
+ reg_X(0) <= A;
+ --Q <= not reg_Q(XBITS/GRAIN-1); --ito obtain the result a cycle before
+ Q <= iQ; iQ <= not reg_Q(XBITS/GRAIN-1);
+ rem_no_adj <= rem_out(XBITS/GRAIN-1);
+ reg_Y_rem <= reg_Y(XBITS/GRAIN-1)(YBITS-1 downto 0);
+ R <= iR;
+ end if;
+ end process;
+
+
+ rem_in(0) <= (others => '0');
+
+ g1: for i in 0 to XBITS/GRAIN -1 generate
+ cell: nr_r4_half_cell port map( op_r => rem_in(i),
+ op_y => reg_Y(i), op_3y => reg_3Y(i),
+ x_1 => reg_X(i)(XBITS-1-i*2), x_0 => reg_X(i)(XBITS-2-i*2),
+ n_qneg => reg_Q(i)(XBITS-1-i*2 downto XBITS-2-i*2), new_r => rem_out(i) );
+ end generate;
+
+ g2: for i in 0 to XBITS/GRAIN-2 generate
+ g2c: if (i+1) mod DEPTH /= 0 generate
+ rem_in(i+1) <= rem_out(i);
+ reg_Y(i+1) <= reg_Y(i); reg_3Y(i+1) <= reg_3Y(i);
+ reg_X(i+1) <= reg_X(i);
+ reg_Q(i+1)(XBITS-1 downto XBITS-2-i*2) <= reg_Q(i)(XBITS-1 downto XBITS-2-i*2);
+ end generate;
+ g2FF: if (i+1) mod DEPTH = 0 generate
+ FFs: process(clk)
+ begin
+ if CLK'event and CLK='1' then --CLK rising edge
+ rem_in(i+1) <= rem_out(i);
+ reg_Y(i+1) <= reg_Y(i); reg_3Y(i+1) <= reg_3Y(i);
+ reg_X(i+1) <= reg_X(i);
+ reg_Q(i+1)(XBITS-1 downto XBITS-2-i*2) <= reg_Q(i)(XBITS-1 downto XBITS-2-i*2);
+ end if;
+ end process;
+ end generate;
+ end generate;
+
+
+-- use this code to obtain the remainder a cycle before
+-- final_rem_Adjust: cond_adder port map (op_a => rem_out(XBITS/GRAIN-1)(YBITS-1 downto 0),
+-- op_b => reg_Y(XBITS/GRAIN-1)(YBITS-1 downto 0),
+-- sel => rem_out(XBITS/GRAIN-1)(YBITS), outp => iR);
+
+
+ final_rem_Adjust: cond_adder port map (op_a => rem_no_adj(YBITS-1 downto 0),
+ op_b => reg_Y_rem(YBITS-1 downto 0),
+ sel => rem_no_adj(YBITS), outp => iR);
+
+
+end simple_arch;
--- /dev/null
+-------------------------------------
+-- Defines the dataPath width
+--
+-------------------------------------
+package mypackage is
+ constant XBITS :INTEGER := 32;
+ constant YBITS :INTEGER := 32;
+ constant GRAIN :INTEGER := 2; --Allways in 2!!!!
+ constant DEPTH :INTEGER := 1; --Every how much steps register
+end mypackage;
--- /dev/null
+--------------------------------------------------------
+--
+-- Basic cell radix 4 arch 2. divider
+--------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+use work.mypackage.all;
+
+entity nr_r4_half_cell is
+ generic (
+ XBITS : natural := 32;
+ YBITS : natural := 32
+ );
+ --generic(pos_x: integer:= 0; pos_y: integer := 0; agroup: string:= "cell_r4");
+ port (
+ op_r: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_y: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_3y: in STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ x_1: in STD_LOGIC;
+ x_0: in STD_LOGIC;
+ n_qneg: out STD_LOGIC_VECTOR (1 downto 0);
+ new_r: out STD_LOGIC_VECTOR (YBITS downto 0)
+ );
+end nr_r4_half_cell;
+
+architecture half of nr_r4_half_cell is
+ signal op_4r: STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ signal a2_pm_b, a4_pm_b, a4_pm_3b: STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ signal sr: STD_LOGIC;
+begin
+ sr <= op_r(YBITS);
+ op_4r <= op_r(YBITS-1 downto 0) & x_1 & x_0;
+
+ a2_pm_b <= (op_r & x_1) + (op_y) when sr = '1' else (sr & op_y) + not (op_r & x_1);
+ a4_pm_3b <= (op_4r + op_3y) when sr = '1' else (op_4r) - (op_3y);
+ a4_pm_b <= (op_4r + op_y) when sr = '1' else (op_4r) - (sr & op_y);
+
+ mux_outps: process (a2_pm_b, a4_pm_b, a4_pm_3b)
+ begin
+ if a2_pm_b(YBITS)= '1' then
+ new_r <= a4_pm_3b(YBITS downto 0);
+ n_qneg(0) <= a4_pm_3b(YBITS);
+ else
+ new_r <= a4_pm_b(YBITS downto 0);
+ n_qneg(0) <= a4_pm_b(YBITS);
+ end if;
+ end process;
+
+ mux_nqb: process (sr,a2_pm_b, a4_pm_b, a4_pm_3b)
+ begin
+ if sr = '1' then --11
+ n_qneg(1) <= a2_pm_b(YBITS);
+ else
+ n_qneg(1) <= not a2_pm_b(YBITS);
+ end if;
+
+ end process;
+
+end half;
--- /dev/null
+--------------------------------------------------------------------
+-- VHDL Test Bench for sequential divider
+--
+-- Notes:
+-- Exhaustive testbench.
+-- Only for small values of XBITS and YBITS
+--------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_unsigned.all;
+
+LIBRARY ieee;
+USE IEEE.STD_LOGIC_TEXTIO.ALL;
+USE STD.TEXTIO.ALL;
+
+ENTITY testb_tb_pipe IS
+END testb_tb_pipe;
+
+ARCHITECTURE pruebas OF testb_tb_pipe IS
+FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
+ constant XBITS :INTEGER := 28;
+ constant YBITS :INTEGER := 16;
+ constant GRAIN :INTEGER := 2; --Allways in 2!!!!
+ constant DEPTH :INTEGER := 1; --Every how much steps register
+
+
+ COMPONENT div_r4_pipe
+ generic (
+ XBITS : natural := XBITS;
+ YBITS : natural := YBITS;
+ GRAIN : natural := GRAIN;
+ DEPTH : natural := DEPTH
+ );
+ PORT(
+ a : IN std_logic_vector(XBITS-1 downto 0);
+ b : IN std_logic_vector(YBITS-1 downto 0);
+ clk : IN std_logic;
+ q : OUT std_logic_vector(XBITS-1 downto 0);
+ r : OUT std_logic_vector(YBITS-1 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL x : std_logic_vector(XBITS-1 downto 0);
+ SIGNAL y : std_logic_vector(YBITS-1 downto 0);
+ SIGNAL clk : std_logic;
+ SIGNAL q : std_logic_vector(XBITS-1 downto 0);
+ SIGNAL r : std_logic_vector(YBITS-1 downto 0);
+ constant PERIOD: time := 10 ns;
+
+BEGIN
+
+ uut: div_r4_pipe PORT MAP(
+ a => x,
+ b => y,
+ clk => clk,
+ q => q,
+ r => r
+ );
+
+ PROCESS -- clock process (drives clk),
+ BEGIN
+ clk <= '0';
+ WAIT FOR PERIOD/2;
+ clk <= '1';
+ WAIT FOR PERIOD/2;
+ END PROCESS;
+
+
+tb_gen : PROCESS --generate values
+ VARIABLE TX_LOC : LINE;
+ VARIABLE TX_STR : String(1 to 4096);
+ BEGIN
+ x <= CONV_STD_LOGIC_VECTOR (200, XBITS);
+ y <= CONV_STD_LOGIC_VECTOR (10, YBITS);
+ WAIT FOR PERIOD*(YBITS+4);
+ x <= CONV_STD_LOGIC_VECTOR (4364537, XBITS);
+ y <= CONV_STD_LOGIC_VECTOR (4325, YBITS);
+ WAIT FOR PERIOD*(YBITS+4);
+
+ x <= CONV_STD_LOGIC_VECTOR (83456342, XBITS);
+ y <= CONV_STD_LOGIC_VECTOR (6545, YBITS);
+ WAIT FOR PERIOD*(YBITS+4);
+ for i in 0 to 20 loop
+ x <= CONV_STD_LOGIC_VECTOR (100+i*2000, XBITS);
+ y <= CONV_STD_LOGIC_VECTOR (2000, YBITS);
+ WAIT FOR PERIOD;
+ end loop;
+
+ END PROCESS;
+
+-- tb_gen : PROCESS --generate values
+-- VARIABLE TX_LOC : LINE;
+-- VARIABLE TX_STR : String(1 to 4096);
+-- BEGIN
+-- for I in 0 to 2**XBITS -1 loop
+-- for J in 1 to 2**YBITS -1 loop
+-- x <= CONV_STD_LOGIC_VECTOR (I, XBITS);
+-- y <= CONV_STD_LOGIC_VECTOR (J, YBITS);
+-- WAIT FOR PERIOD;
+-- end loop;
+-- end loop;
+--
+-- WAIT FOR 3 * PERIOD;
+--
+-- END PROCESS;
+--
+-- tb_test : PROCESS --test the correctness of data
+-- VARIABLE TX_LOC : LINE;
+-- VARIABLE TX_STR : String(1 to 4096);
+-- BEGIN
+-- WAIT FOR (XBITS/GRAIN/DEPTH)*PERIOD;
+--
+-- Wait for PERIOD; --Only if you produce the result one cycle later
+--
+-- for I in 0 to 2**XBITS -1 loop
+-- for J in 1 to 2**YBITS -1 loop
+-- WAIT FOR PERIOD;
+-- IF ( I /= (J * CONV_INTEGER(Q)) + CONV_INTEGER(R)) THEN
+-- write(TX_LOC,string'("ERROR!!! X=")); write(TX_LOC, X);
+-- write(TX_LOC,string'(" Y=")); write(TX_LOC, Y);
+-- write(TX_LOC,string'(" Q=")); write(TX_LOC, Q);
+-- write(TX_LOC,string'(" R=")); write(TX_LOC, R);
+-- write(TX_LOC, string'(" "));
+-- write(TX_LOC,string'(" (i=")); write(TX_LOC, i);
+-- write(TX_LOC,string'(" j=")); write(TX_LOC, j);
+-- write(TX_LOC, string'(")"));
+-- TX_STR(TX_LOC.all'range) := TX_LOC.all;
+-- writeline(results, TX_LOC);
+-- Deallocate(TX_LOC);
+-- ASSERT (FALSE) REPORT TX_STR SEVERITY FAILURE;
+-- ELSIF (J < CONV_INTEGER(R)) THEN
+-- write(TX_LOC,string'("--> Error Resto Mayor que Y =")); write(TX_LOC, 0.0);
+-- write(TX_LOC,string'("ns X=")); write(TX_LOC, X);
+-- write(TX_LOC,string'(" Y=")); write(TX_LOC, Y);
+-- write(TX_LOC,string'(" Q=")); write(TX_LOC, Q);
+-- write(TX_LOC,string'(" R=")); write(TX_LOC, R);
+-- write(TX_LOC, string'(" "));
+-- TX_STR(TX_LOC.all'range) := TX_LOC.all;
+-- writeline(results, TX_LOC);
+-- Deallocate(TX_LOC);
+-- ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+---- ELSE -- print if everything is ok
+---- write(TX_LOC,string'("OK -> X=")); write(TX_LOC, X);
+---- write(TX_LOC,string'(" Y=")); write(TX_LOC, Y);
+---- write(TX_LOC,string'(" Q=")); write(TX_LOC, Q);
+---- write(TX_LOC,string'(" R=")); write(TX_LOC, R);
+---- write(TX_LOC, string'(" "));
+---- TX_STR(TX_LOC.all'range) := TX_LOC.all;
+---- writeline(results, TX_LOC);
+---- Deallocate(TX_LOC);
+---- ASSERT (FALSE) REPORT TX_STR SEVERITY WARNING;
+--
+-- END IF;
+--
+-- end loop;
+-- end loop;
+-- ASSERT (FALSE) REPORT
+-- "Simulation successful (not a failure). No problems detected. "
+-- SEVERITY FAILURE;
+-- --wait; -- will wait forever
+-- END PROCESS;
+
+END;
--- /dev/null
+-- Dual port, single clock memory, inferrable in Xilinx and Altera FPGA
+
+library ieee;
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+entity dp_ram_scl is
+
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+
+ port
+ (
+ clk : in std_logic;
+ addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+ addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+ data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ we_a : in std_logic := '1';
+ we_b : in std_logic := '1';
+ q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
+ q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
+ );
+
+end dp_ram_scl;
+
+
+architecture rtl of dp_ram_scl is
+
+ -- Create a type for data word
+ subtype data_word is std_logic_vector((DATA_WIDTH-1) downto 0);
+ type ram_memory is array((2**ADDR_WIDTH-1) downto 0) of data_word;
+
+ -- Declare the RAM variable.
+ shared variable ram : ram_memory;
+
+begin
+
+ process(clk)
+ begin
+ if(rising_edge(clk)) then
+ -- Port B
+ if(we_b = '1') then
+ ram(conv_integer(unsigned(addr_b))) := data_b;
+ end if;
+ q_b <= ram(conv_integer(unsigned(addr_b)));
+ end if;
+ end process;
+
+ process(clk)
+ begin
+ if(rising_edge(clk)) then
+ -- Port A
+ if(we_a = '1') then
+ ram(conv_integer(unsigned(addr_a))) := data_a;
+ end if;
+ q_a <= ram(conv_integer(unsigned(addr_a)));
+ end if;
+ end process;
+
+end rtl;
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : Parametrized DP RAM for heap-sorter
+-- Project : heap-sorter
+-------------------------------------------------------------------------------
+-- File : sort_dpram.vhd
+-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
+-- Company :
+-- Created : 2010-05-14
+-- Last update: 2011-07-06
+-- Platform :
+-- Standard : VHDL'93
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Wojciech M. Zabolotny
+-- This file is published under the BSD license, so you can freely adapt
+-- it for your own purposes.
+-- Additionally this design has been described in my article:
+-- Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
+-- for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
+-- I'd be glad if you cite this article when you publish something based
+-- on my design.
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-05-14 1.0 wzab Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+library work;
+use work.sorter_pkg.all;
+use work.sys_config.all;
+
+entity sort_dp_ram is
+
+ generic
+ (
+ ADDR_WIDTH : natural;
+ NLEVELS : natural;
+ NAME : string := "X"
+ );
+
+ port
+ (
+ clk : in std_logic;
+ addr_a : in std_logic_vector(NLEVELS-1 downto 0);
+ addr_b : in std_logic_vector(NLEVELS-1 downto 0);
+ data_a : in T_DATA_REC;
+ data_b : in T_DATA_REC;
+ we_a : in std_logic;
+ we_b : in std_logic;
+ q_a : out T_DATA_REC;
+ q_b : out T_DATA_REC
+ );
+
+end sort_dp_ram;
+
+architecture rtl of sort_dp_ram is
+
+ signal vq_a, vq_b, tdata_a, tdata_b : std_logic_vector(DATA_REC_WIDTH-1 downto 0);
+ signal reg : T_DATA_REC := DATA_REC_INIT_DATA;
+
+ component dp_ram_scl
+ generic (
+ DATA_WIDTH : natural;
+ ADDR_WIDTH : natural);
+ port (
+ clk : in std_logic;
+ addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+ addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+ data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ we_a : in std_logic := '1';
+ we_b : in std_logic := '1';
+ q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
+ q_b : out std_logic_vector((DATA_WIDTH -1) downto 0));
+ end component;
+
+begin
+
+ -- Convert our data records int std_logic_vector, so that
+ -- standard DP RAM may handle it
+ tdata_a <= tdrec2stlv(data_a);
+ tdata_b <= tdrec2stlv(data_b);
+
+
+ i1 : if ADDR_WIDTH > 0 generate
+ -- When ADDR_WIDTH is above 0 embed the real DP RAM
+ -- (even though synthesis tool may still replace it with
+ -- registers during optimization for low ADDR_WIDTH)
+
+ q_a <= stlv2tdrec(vq_a);
+ q_b <= stlv2tdrec(vq_b);
+
+ dp_ram_1 : dp_ram_scl
+ generic map (
+ DATA_WIDTH => DATA_REC_WIDTH,
+ ADDR_WIDTH => ADDR_WIDTH)
+ port map (
+ clk => clk,
+ addr_a => addr_a(ADDR_WIDTH-1 downto 0),
+ addr_b => addr_b(ADDR_WIDTH-1 downto 0),
+ data_a => tdata_a,
+ data_b => tdata_b,
+ we_a => we_a,
+ we_b => we_b,
+ q_a => vq_a,
+ q_b => vq_b);
+
+ end generate i1;
+
+ i2 : if ADDR_WIDTH = 0 generate
+ -- When ADDR_WIDTH is 0, DP RAM should be simply replaced
+ -- with a register implemented below
+
+ p1 : process (clk)
+ begin -- process p1
+ if clk'event and clk = '1' then -- rising clock edge
+ if we_a = '1' then
+ reg <= data_a;
+ q_a <= data_a;
+ q_b <= data_a;
+ elsif we_b = '1' then
+ reg <= data_b;
+ q_a <= data_b;
+ q_b <= data_b;
+ else
+ q_a <= reg;
+ q_b <= reg;
+ end if;
+ end if;
+ end process p1;
+
+ end generate i2;
+
+ dbg1 : if SORT_DEBUG generate
+
+ -- Process monitoring read/write accesses to the memory (only for debugging)
+ p3 : process (clk)
+ variable rline : line;
+ begin -- process p1
+ if clk'event and clk = '1' then -- rising clock edge
+ if(we_a = '1' and we_b = '1') then
+ write(rline, NAME);
+ write(rline, ADDR_WIDTH);
+ write(rline, string'(" Possible write collision!"));
+ writeline(reports, rline);
+ end if;
+
+ end if;
+ end process p3;
+ end generate dbg1;
+end rtl;
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : Sorting node controller for heap-sorter
+-- Project : heap-sorter
+-------------------------------------------------------------------------------
+-- File : sorter_ctrl.vhd
+-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
+-- Company :
+-- Created : 2010-05-14
+-- Last update: 2013-07-04
+-- Platform :
+-- Standard : VHDL'93
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Wojciech M. Zabolotny
+-- This file is published under the BSD license, so you can freely adapt
+-- it for your own purposes.
+-- Additionally this design has been described in my article:
+-- Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
+-- for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
+-- I'd be glad if you cite this article when you publish something based
+-- on my design.
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-05-14 1.0 wzab Created
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- The sorter controller is connected with three dual port memories.
+-- The first dual port memory tm_... provides the "upstream data"
+-- The second dual port memory lm_... provides the "left branch of downstream data"
+-- The third dual port memory rm_... provides the "right branch of downstream data"
+-- The controller is notified about availability of the new data by the
+-- "update" signal.
+-- However in this architecture we need to service two upstream memories!
+-- That's because we want to save one cycle, and to be able to issue
+--
+-- Important feature of each controller is the ability to clear the memory
+-- after reset.
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+library work;
+use work.sorter_pkg.all;
+use work.sys_config.all;
+
+entity sorter_ctrl is
+
+ generic (
+ NLEVELS : integer; -- number of levels (max number of
+ -- address bits
+ NADDRBITS : integer -- number of used address bits
+ );
+
+ port (
+ -- Top memory connections
+ tm_din : in T_DATA_REC;
+ tm_dout : out T_DATA_REC;
+ tm_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ tm_we : out std_logic;
+ -- Left memory connections
+ lm_din : in T_DATA_REC;
+ lm_dout : out T_DATA_REC;
+ lm_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ lm_we : out std_logic;
+ -- Right memory connections
+ rm_din : in T_DATA_REC;
+ rm_dout : out T_DATA_REC;
+ rm_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ rm_we : out std_logic;
+ -- Upper level controller connections
+ up_in : in std_logic;
+ up_in_val : in T_DATA_REC;
+ up_in_addr : in std_logic_vector(NLEVELS-1 downto 0);
+ -- Upper level update notifier
+ up_out : out std_logic;
+ up_out_val : out T_DATA_REC;
+ up_out_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ -- Lower level controller connections
+ low_out : out std_logic;
+ low_out_val : out T_DATA_REC;
+ low_out_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ low_in : in std_logic;
+ low_in_val : in T_DATA_REC;
+ low_in_addr : in std_logic_vector(NLEVELS-1 downto 0);
+ -- Lower level update notifier
+ -- System connections
+ clk : in std_logic;
+ clk_en : in std_logic;
+ ready_in : in std_logic;
+ ready_out : out std_logic; -- signals, when memory is cleared
+ -- after reset
+ rst_n : in std_logic);
+end sorter_ctrl;
+
+architecture sorter_ctrl_arch1 of sorter_ctrl is
+
+ type T_CTRL_STATE is (CTRL_RESET, CTRL_CLEAR, CTRL_IDLE, CTRL_S1, CTRL_S0);
+ signal ctrl_state, ctrl_state_next : T_CTRL_STATE := CTRL_IDLE;
+ signal addr, addr_i : std_logic_vector(NLEVELS-1 downto 0);
+ signal s_low_in_addr, s_low_in_addr_i : std_logic_vector(NLEVELS-1 downto 0);
+ signal s_up_in_addr, s_up_in_addr_i : std_logic_vector(NLEVELS-1 downto 0);
+ signal s_ready_out, s_ready_out_i : std_logic;
+ signal s_low_in, s_low_in_i : std_logic;
+ signal s_addr_out : std_logic_vector(NLEVELS-1 downto 0);
+ signal s_tm_dout : T_DATA_REC;
+ signal s_up_in_val_i, s_up_in_val : T_DATA_REC := DATA_REC_INIT_DATA;
+ signal s_low_in_val_i, s_low_in_val : T_DATA_REC := DATA_REC_INIT_DATA;
+
+
+ constant ADDR_MAX : std_logic_vector(NLEVELS-1 downto 0) := std_logic_vector(to_unsigned(2**NADDRBITS-1, NLEVELS));
+
+begin
+
+ tm_dout <= s_tm_dout;
+-- We have the two-process state machine.
+ p1 : process (addr, ctrl_state, lm_din, low_in, low_in_addr, low_in_val,
+ ready_in, rm_din, s_addr_out, s_low_in, s_low_in_addr,
+ s_low_in_val, s_ready_out, s_up_in_val, up_in, up_in_addr,
+ up_in_val)
+ variable l_val : T_DATA_REC;
+ variable r_val : T_DATA_REC;
+
+ begin -- process p1
+ -- defaults
+ ctrl_state_next <= ctrl_state;
+ tm_we <= '0';
+ rm_we <= '0';
+ lm_we <= '0';
+ lm_addr <= (others => '0');
+ rm_addr <= (others => '0');
+ tm_addr <= (others => '0');
+ s_ready_out_i <= s_ready_out;
+ addr_i <= addr;
+ up_out_val <= DATA_REC_INIT_DATA; -- to avoid latches
+ low_out_val <= DATA_REC_INIT_DATA; -- to avoid latches
+ s_low_in_addr_i <= s_low_in_addr;
+ s_low_in_i <= low_in;
+ low_out <= '0';
+ up_out <= '0';
+ up_out_addr <= (others => '0');
+ s_up_in_val_i <= s_up_in_val;
+ s_low_in_val_i <= s_low_in_val;
+ lm_dout <= DATA_REC_INIT_DATA;
+ rm_dout <= DATA_REC_INIT_DATA;
+ s_tm_dout <= DATA_REC_INIT_DATA;
+ s_addr_out <= (others => '0');
+ case ctrl_state is
+ when CTRL_RESET =>
+ addr_i <= (others => '0');
+ s_ready_out_i <= '0';
+ ctrl_state_next <= CTRL_CLEAR;
+ when CTRL_CLEAR =>
+ lm_addr <= addr;
+ rm_addr <= addr;
+ lm_dout <= DATA_REC_INIT_DATA;
+ rm_dout <= DATA_REC_INIT_DATA;
+ lm_we <= '1';
+ rm_we <= '1';
+ if addr = ADDR_MAX then
+ if ready_in = '1' then
+ s_ready_out_i <= '1';
+ ctrl_state_next <= CTRL_IDLE;
+ end if;
+ else
+ addr_i <= std_logic_vector(unsigned(addr)+1);
+ end if;
+ when CTRL_IDLE =>
+ -- We read "down" memories ("upper" value is provided by the ``bypass channel'')
+ if up_in = '1' then
+ ctrl_state_next <= CTRL_S1;
+ tm_addr <= up_in_addr;
+ lm_addr <= up_in_addr;
+ rm_addr <= up_in_addr;
+ addr_i <= up_in_addr;
+ s_up_in_val_i <= up_in_val;
+ if low_in = '1' then
+ s_low_in_val_i <= low_in_val;
+ s_low_in_addr_i <= low_in_addr;
+ end if;
+ end if;
+ when CTRL_S1 =>
+ -- In this cycle we can compare data
+ l_val := lm_din;
+ r_val := rm_din;
+ -- Check, if we need to take value from lower ``bypass channel''
+ if s_low_in = '1' then
+ if (addr(NADDRBITS-1 downto 0) = s_low_in_addr(NADDRBITS-1 downto 0)) then
+ -- We are reading a value which was just updated, so we need to get it
+ -- from ``bypass channel'' instead of memory
+ if s_low_in_addr(NADDRBITS) = '1' then
+ l_val := s_low_in_val;
+ else
+ r_val := s_low_in_val;
+ end if;
+ end if;
+ end if;
+ if sort_cmp_lt(l_val, s_up_in_val) and sort_cmp_lt(l_val, r_val) then
+ -- The L-ram value is the smallest
+ -- Output the value from the L-ram and put the new value into the L-ram
+ s_tm_dout <= l_val;
+ tm_addr <= addr;
+ tm_we <= '1';
+
+ up_out_val <= l_val;
+ up_out <= '1';
+ up_out_addr <= addr;
+
+ lm_addr <= addr;
+ lm_dout <= s_up_in_val;
+ lm_we <= '1';
+
+ low_out <= '1';
+ low_out_val <= s_up_in_val;
+ s_addr_out(NADDRBITS) <= '1';
+
+ if NADDRBITS > 0 then
+ s_addr_out(NADDRBITS-1 downto 0) <= addr(NADDRBITS-1 downto 0);
+ end if;
+ ctrl_state_next <= CTRL_IDLE;
+ elsif sort_cmp_lt(r_val, s_up_in_val) then
+ -- The R-ram value is the smallest
+ -- Output the value from the R-ram and put the new value into the R-ram
+ s_tm_dout <= r_val;
+ tm_addr <= addr;
+ tm_we <= '1';
+
+ up_out_val <= r_val;
+ up_out <= '1';
+ up_out_addr <= addr;
+
+ rm_addr <= addr;
+ rm_dout <= s_up_in_val;
+ rm_we <= '1';
+
+ low_out <= '1';
+ low_out_val <= s_up_in_val;
+
+ s_addr_out(NADDRBITS) <= '0';
+ if NADDRBITS > 0 then
+ s_addr_out(NADDRBITS-1 downto 0) <= addr(NADDRBITS-1 downto 0);
+ end if;
+ ctrl_state_next <= CTRL_IDLE;
+ else
+ -- The new value is the smallest
+ -- Nothing to do, no update downstream
+ s_tm_dout <= s_up_in_val;
+ tm_we <= '1';
+ tm_addr <= addr;
+
+ up_out_val <= s_up_in_val;
+ up_out <= '1';
+ up_out_addr <= addr;
+
+ ctrl_state_next <= CTRL_IDLE;
+ end if;
+ when others => null;
+ end case;
+ end process p1;
+
+ p2 : process (clk, rst_n) is
+ begin -- process p2
+ if rst_n = '0' then -- asynchronous reset (active low)
+ ctrl_state <= CTRL_RESET;
+ s_ready_out <= '0';
+ addr <= (others => '0');
+ s_low_in_addr <= (others => '0');
+ s_low_in <= '0';
+ s_low_in_val <= DATA_REC_INIT_DATA;
+ s_up_in_val <= DATA_REC_INIT_DATA;
+ --update_out <= '0';
+ --addr_out <= (others => '0');
+ elsif clk'event and clk = '1' then -- rising clock edge
+ s_ready_out <= s_ready_out_i;
+ ctrl_state <= ctrl_state_next;
+ addr <= addr_i;
+ s_low_in_addr <= s_low_in_addr_i;
+ s_low_in_val <= s_low_in_val_i;
+ s_up_in_val <= s_up_in_val_i;
+ s_low_in <= s_low_in_i;
+ end if;
+ end process p2;
+ ready_out <= s_ready_out;
+ low_out_addr <= s_addr_out;
+end sorter_ctrl_arch1;
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : Definitions for heap-sorter
+-- Project : heap-sorter
+-------------------------------------------------------------------------------
+-- File : sorter_pkg.vhd
+-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
+-- Company :
+-- Created : 2010-05-14
+-- Last update: 2011-07-11
+-- Platform :
+-- Standard : VHDL'93
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Wojciech M. Zabolotny
+-- This file is published under the BSD license, so you can freely adapt
+-- it for your own purposes.
+-- Additionally this design has been described in my article:
+-- Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
+-- for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
+-- I'd be glad if you cite this article when you publish something based
+-- on my design.
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-05-14 1.0 wzab Created
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+library work;
+use work.sys_config.all;
+
+package sorter_pkg is
+ constant DATA_REC_WIDTH : integer := DATA_REC_SORT_KEY_WIDTH +
+ DATA_REC_PAYLOAD_WIDTH + 2;
+
+
+ subtype T_SORT_KEY is unsigned (DATA_REC_SORT_KEY_WIDTH - 1 downto 0);
+ subtype T_PAYLOAD is std_logic_vector(DATA_REC_PAYLOAD_WIDTH - 1 downto 0);
+
+ --alias T_SORT_KEY is unsigned (12 downto 0);
+ type T_DATA_REC is record
+ d_key : T_SORT_KEY;
+ init : std_logic;
+ valid : std_logic;
+ d_payload : T_PAYLOAD;
+ end record;
+
+ -- Special constant used to initially fill the sorter
+ -- Must be sorted so, that is smaller, than any other data
+ constant DATA_REC_INIT_DATA : T_DATA_REC := (
+ d_key => to_unsigned(0, DATA_REC_SORT_KEY_WIDTH),
+ init => '1',
+ valid => '0',
+ d_payload => (others => '0')
+ );
+
+ -- Special constant used to ``flush'' the sorter at the end
+ constant DATA_REC_END_DATA : T_DATA_REC := (
+ d_key => to_unsigned(0, DATA_REC_SORT_KEY_WIDTH),
+ init => '1',
+ valid => '1',
+ d_payload => (others => '0')
+ );
+
+
+ function sort_cmp_lt (
+ constant v1 : T_DATA_REC;
+ constant v2 : T_DATA_REC)
+ return boolean;
+
+ function tdrec2stlv (
+ constant drec : T_DATA_REC)
+ return std_logic_vector;
+
+ function stlv2tdrec (
+ constant dstlv : std_logic_vector)
+ return T_DATA_REC;
+
+ file reports : text open write_mode is "STD_OUTPUT";
+
+end sorter_pkg;
+
+package body sorter_pkg is
+
+ function stlv2tdrec (
+ constant dstlv : std_logic_vector)
+ return T_DATA_REC is
+ variable result : T_DATA_REC;
+ variable j : integer := 0;
+ begin -- stlv2drec
+ j := 0;
+ result.d_key := unsigned(dstlv(j-1+DATA_REC_SORT_KEY_WIDTH downto j));
+ j := j+DATA_REC_SORT_KEY_WIDTH;
+ result.valid := dstlv(j);
+ j := j+1;
+ result.init := dstlv(j);
+ j := j+1;
+ result.d_payload := dstlv(j-1+DATA_REC_PAYLOAD_WIDTH downto j);
+ j := j+DATA_REC_PAYLOAD_WIDTH;
+ return result;
+ end stlv2tdrec;
+
+ function tdrec2stlv (
+ constant drec : T_DATA_REC)
+ return std_logic_vector is
+ variable result : std_logic_vector(DATA_REC_WIDTH-1 downto 0);
+ variable j : integer := 0;
+ begin -- tdrec2stlv
+ j := 0;
+ result(j-1+DATA_REC_SORT_KEY_WIDTH downto j) := std_logic_vector(drec.d_key);
+ j := j+DATA_REC_SORT_KEY_WIDTH;
+ result(j) := drec.valid;
+ j := j+1;
+ result(j) := drec.init;
+ j := j+1;
+ result(j-1+DATA_REC_PAYLOAD_WIDTH downto j) := std_logic_vector(drec.d_payload);
+ j := j+DATA_REC_PAYLOAD_WIDTH;
+ return result;
+ end tdrec2stlv;
+
+
+ -- Function sort_cmp_lt returns TRUE when the first opperand is ``less'' than
+ -- the second one
+ function sort_cmp_lt (
+ constant v1 : T_DATA_REC;
+ constant v2 : T_DATA_REC)
+ return boolean is
+ variable rline : line;
+ variable dcomp : unsigned(DATA_REC_SORT_KEY_WIDTH-1 downto 0) := (others => '0');
+ begin -- sort_cmp_lt
+ -- Check the special cases
+ if (v1.init = '1') and (v2.init = '0') then
+ -- v1 is the special record, v2 is the standard one
+ if v1.valid = '0' then
+ -- initialization record - ``smaller'' than all standard records
+ return true;
+ else
+ -- end record - ``bigger'' than all standard records
+ return false;
+ end if;
+ elsif (v1.init = '0') and (v2.init = '1') then
+ -- v2 is the special record, v1 is the standard one
+ if (v2.valid = '0') then
+ -- v2 is the initialization record - it is ``smaller'' than standard record v1
+ return false;
+ else
+ -- v2 is the end record - it is ``bigger'' than standard record v1
+ return true;
+ end if;
+ elsif (v1.init = '1') and (v2.init = '1') then
+ -- both v1 and v2 are special records
+ if (v1.valid = '0') and (v2.valid = '1') then
+ -- v1 - initial record, v2 - end record
+ return true;
+ else
+ -- v1 is end record, so it is ``bigger'' or ``equal'' to other records
+ return false;
+ end if;
+ elsif (v1.init = '0') and (v2.init = '0') then
+ -- We compare standard words
+ -- We must consider the fact, that in longer sequences of data records
+ -- the sort keys may wrap around
+ -- therefore we perform subtraction modulo
+ -- 2**DATA_REC_SORT_KEY_WIDTH and check the MSB
+ dcomp := v1.d_key-v2.d_key;
+ if dcomp(DATA_REC_SORT_KEY_WIDTH-1) = '1' then
+ --if signed(v1.d_key - v2.d_key)<0 then -- old implementation
+ return true;
+ elsif v2.d_key = v1.d_key then
+ if v2.valid = '1' then
+ return true;
+ else
+ -- Empty data records should wait
+ return false;
+ end if;
+ else
+ return false;
+ end if;
+ else
+ assert false report "Wrong records in sort_cmp_lt" severity error;
+ return false;
+ end if;
+ return false; -- should never happen
+ end sort_cmp_lt;
+
+
+end sorter_pkg;
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- Title : Top entity of heap-sorter
+-- Project : heap-sorter
+-------------------------------------------------------------------------------
+-- File : sorter_sys.vhd
+-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
+-- Company :
+-- Created : 2010-05-14
+-- Last update: 2011-07-11
+-- Platform :
+-- Standard : VHDL'93
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Wojciech M. Zabolotny
+-- This file is published under the BSD license, so you can freely adapt
+-- it for your own purposes.
+-- Additionally this design has been described in my article
+-- Additionally this design has been described in my article:
+-- Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
+-- for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
+-- I'd be glad if you cite this article when you publish something based
+-- on my design.
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2010-05-14 1.0 wzab Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+library work;
+use work.sorter_pkg.all;
+use work.sys_config.all;
+
+entity sorter_sys is
+ generic (
+ NLEVELS : integer := SYS_NLEVELS -- number of levels in the sorter heap
+ );
+
+ port (
+ din : in T_DATA_REC;
+ we : in std_logic;
+ dout : out T_DATA_REC;
+ dav : out std_logic;
+ clk : in std_logic;
+ rst_n : in std_logic;
+ ready : out std_logic);
+end sorter_sys;
+
+architecture sorter_sys_arch1 of sorter_sys is
+
+ component sort_dp_ram
+ generic (
+ ADDR_WIDTH : natural;
+ NLEVELS : natural;
+ NAME : string);
+ port (
+ clk : in std_logic;
+ addr_a : in std_logic_vector(NLEVELS-1 downto 0);
+ addr_b : in std_logic_vector(NLEVELS-1 downto 0);
+ data_a : in T_DATA_REC;
+ data_b : in T_DATA_REC;
+ we_a : in std_logic;
+ we_b : in std_logic;
+ q_a : out T_DATA_REC;
+ q_b : out T_DATA_REC);
+ end component;
+
+ component sorter_ctrl
+ generic (
+ NLEVELS : integer;
+ NADDRBITS : integer);
+ port (
+ tm_din : in T_DATA_REC;
+ tm_dout : out T_DATA_REC;
+ tm_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ tm_we : out std_logic;
+ lm_din : in T_DATA_REC;
+ lm_dout : out T_DATA_REC;
+ lm_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ lm_we : out std_logic;
+ rm_din : in T_DATA_REC;
+ rm_dout : out T_DATA_REC;
+ rm_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ rm_we : out std_logic;
+ up_in : in std_logic;
+ up_in_val : in T_DATA_REC;
+ up_in_addr : in std_logic_vector(NLEVELS-1 downto 0);
+ up_out : out std_logic;
+ up_out_val : out T_DATA_REC;
+ up_out_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ low_out : out std_logic;
+ low_out_val : out T_DATA_REC;
+ low_out_addr : out std_logic_vector(NLEVELS-1 downto 0);
+ low_in : in std_logic;
+ low_in_val : in T_DATA_REC;
+ low_in_addr : in std_logic_vector(NLEVELS-1 downto 0);
+ clk : in std_logic;
+ clk_en : in std_logic;
+ ready_in : in std_logic;
+ ready_out : out std_logic;
+ rst_n : in std_logic);
+ end component;
+
+ -- Create signals for address buses
+ -- Some of them will remain unused.
+ subtype T_SORT_BUS_ADDR is std_logic_vector(NLEVELS-1 downto 0);
+ type T_SORT_ADDR_BUSES is array (NLEVELS downto 0) of T_SORT_BUS_ADDR;
+ signal low_addr, up_addr, addr_dr, addr_dl, addr_u : T_SORT_ADDR_BUSES := (others => (others => '0'));
+ type T_SORT_DATA_BUSES is array (NLEVELS downto 0) of T_DATA_REC;
+ signal up_update_path, low_update_path, data_d, data_dl, data_dr, data_u : T_SORT_DATA_BUSES := (others => DATA_REC_INIT_DATA);
+ signal q_dr, q_dl, q_u, q_ul, q_ur : T_SORT_DATA_BUSES := (others => DATA_REC_INIT_DATA);
+ signal we_ul, we_ur, we_u, we_dl, we_dr, low_update, up_update, s_ready : std_logic_vector(NLEVELS downto 0) := (others => '0');
+ signal addr_switch, addr_switch_del : std_logic_vector(NLEVELS downto 0);
+ signal l0_reg : T_DATA_REC;
+ signal clk_en : std_logic := '1';
+
+begin -- sorter_sys_arch1
+
+-- Build the sorting tree
+
+ g1 : for i in 0 to NLEVELS-1 generate
+
+ -- Two RAMs from the upper level are seen as a single RAM
+ -- We use the most significant bit (i-th bit) to distinguish RAM
+ -- In all RAMs the A-ports are used for upstream connections
+ -- and the B-ports are used for downstream connections
+
+ -- Below are processes used to combine two upstream RAMs in a single one
+ i0a : if i >= 1 generate
+ addr_switch(i) <= addr_u(i)(i-1);
+ end generate i0a;
+ i0b : if i = 0 generate
+ addr_switch(i) <= '0';
+ end generate i0b;
+
+ -- There is a problem with reading of data provided by two upstream RAMs
+ -- we need to multiplex the data...
+ -- Delay for read data multiplexer
+ s1 : process (clk, rst_n)
+ begin -- process s1
+ if rst_n = '0' then -- asynchronous reset (active low)
+ addr_switch_del(i) <= '0';
+ elsif clk'event and clk = '1' then -- rising clock edge
+ addr_switch_del(i) <= addr_switch(i);
+ end if;
+ end process s1;
+
+ -- Upper RAM signals' multiplexer
+ c1 : process (addr_switch, addr_switch_del, q_ul, q_ur, we_u)
+ begin -- process c1
+ we_ul(i) <= '0';
+ we_ur(i) <= '0';
+ if addr_switch(i) = '1' then
+ we_ul(i) <= we_u(i);
+ else
+ we_ur(i) <= we_u(i);
+ end if;
+ if addr_switch_del(i) = '1' then
+ q_u(i) <= q_ul(i);
+ else
+ q_u(i) <= q_ur(i);
+ end if;
+ end process c1;
+
+ dp_ram_l : sort_dp_ram
+ generic map (
+ NLEVELS => NLEVELS,
+ ADDR_WIDTH => i,
+ NAME => "L")
+ port map (
+ clk => clk,
+ addr_a => addr_dl(i),
+ addr_b => addr_u(i+1),
+ data_a => data_dl(i),
+ data_b => data_u(i+1),
+ we_a => we_dl(i),
+ we_b => we_ul(i+1),
+ q_a => q_dl(i),
+ q_b => q_ul(i+1));
+
+ dp_ram_r : sort_dp_ram
+ generic map (
+ NLEVELS => NLEVELS,
+ ADDR_WIDTH => i,
+ NAME => "R")
+ port map (
+ clk => clk,
+ addr_a => addr_dr(i),
+ addr_b => addr_u(i+1),
+ data_a => data_dr(i),
+ data_b => data_u(i+1),
+ we_a => we_dr(i),
+ we_b => we_ur(i+1),
+ q_a => q_dr(i),
+ q_b => q_ur(i+1));
+
+ sorter_ctrl_1 : sorter_ctrl
+ generic map (
+ NLEVELS => NLEVELS,
+ NADDRBITS => i)
+ port map (
+ tm_din => q_u(i),
+ tm_dout => data_u(i),
+ tm_addr => addr_u(i),
+ tm_we => we_u(i),
+ lm_din => q_dl(i),
+ lm_dout => data_dl(i),
+ lm_addr => addr_dl(i),
+ lm_we => we_dl(i),
+ rm_din => q_dr(i),
+ rm_dout => data_dr(i),
+ rm_addr => addr_dr(i),
+ rm_we => we_dr(i),
+ up_in => up_update(i),
+ up_in_val => up_update_path(i),
+ up_in_addr => up_addr(i),
+ up_out => low_update(i),
+ up_out_val => low_update_path(i),
+ up_out_addr => low_addr(i),
+ low_in => low_update(i+1),
+ low_in_val => low_update_path(i+1),
+ low_in_addr => low_addr(i+1),
+ low_out => up_update(i+1), -- connections to the next level
+ low_out_val => up_update_path(i+1),
+ low_out_addr => up_addr(i+1),
+ clk => clk,
+ clk_en => clk_en,
+ ready_in => s_ready(i+1),
+ ready_out => s_ready(i),
+ rst_n => rst_n);
+
+ end generate g1;
+ -- top level
+
+ -- On the top level we have only a single register
+ process (clk, rst_n)
+ variable rline : line;
+ begin -- process
+ if rst_n = '0' then -- asynchronous reset (active low)
+ l0_reg <= DATA_REC_INIT_DATA;
+ elsif clk'event and clk = '1' then -- rising clock edge
+ dav <= '0';
+ if we_u(0) = '1' then
+ l0_reg <= data_u(0);
+ dout <= data_u(0);
+ dav <= '1';
+ if SORT_DEBUG then
+ write(rline, string'("OUT: "));
+ write(rline, tdrec2stlv(data_u(0)));
+ writeline(reports, rline);
+ end if;
+ elsif we = '1' then
+ if SORT_DEBUG then
+ write(rline, string'("IN: "));
+ write(rline, tdrec2stlv(din));
+ writeline(reports, rline);
+ end if;
+ l0_reg <= din;
+ dout <= din;
+ else
+ dout <= l0_reg;
+ end if;
+ end if;
+ end process;
+ ready <= s_ready(0);
+ q_ur(0) <= l0_reg;
+ q_ul(0) <= l0_reg;
+ up_update(0) <= we;
+ up_update_path(0) <= din;
+ up_addr(0) <= (others => '0');
+
+ -- signals for the last level
+
+ s_ready(NLEVELS) <= '1';
+ --addr(NLEVELS) <= (others => '0');
+ data_dr(NLEVELS) <= DATA_REC_INIT_DATA;
+ data_dl(NLEVELS) <= DATA_REC_INIT_DATA;
+ we_dl(NLEVELS) <= '0';
+ we_dr(NLEVELS) <= '0';
+
+ low_update(NLEVELS) <= '0';
+ low_update_path(NLEVELS) <= DATA_REC_INIT_DATA;
+ low_addr(0) <= (others => '0');
+
+end sorter_sys_arch1;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+package sys_config is
+ constant SORT_DEBUG : boolean :=false;
+ constant SYS_NLEVELS : integer :=5;
+ constant DATA_REC_SORT_KEY_WIDTH : integer :=31+16+12; -- superburst+timestamp+constantfraction
+ constant DATA_REC_PAYLOAD_WIDTH : integer :=16+16+8; -- adcnumber+energy+status
+end sys_config;
+++ /dev/null
------------------------------------------------------------------------------------\r
--- Wrapper for asynchronous FIFO : width 32, 8 deep\r
------------------------------------------------------------------------------------\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.all;\r
-\r
-ENTITY async_fifo_nn_thfull_FWFT_512x36 IS\r
- PORT\r
- (\r
- rst : in std_logic;\r
- wr_clk : in std_logic;\r
- rd_clk : in std_logic;\r
- din : in std_logic_vector(35 downto 0);\r
- wr_en : in std_logic;\r
- rd_en : in std_logic;\r
- dout : out std_logic_vector(35 downto 0);\r
- full : out std_logic;\r
- empty : out std_logic;\r
- rd_data_count : out std_logic_vector(8 downto 0);\r
- prog_full : out std_logic\r
- );\r
-END async_fifo_nn_thfull_FWFT_512x36;\r
-\r
-\r
-ARCHITECTURE Behavioral OF async_fifo_nn_thfull_FWFT_512x36 IS\r
-component async_fifo_nn_thfull_512x36_ecp3\r
- port (\r
- Data: in std_logic_vector(35 downto 0); \r
- WrClock: in std_logic; \r
- RdClock: in std_logic; \r
- WrEn: in std_logic; \r
- RdEn: in std_logic; \r
- Reset: in std_logic; \r
- RPReset: in std_logic; \r
- Q: out std_logic_vector(35 downto 0); \r
- RCNT: out std_logic_vector(9 downto 0); \r
- Empty: out std_logic; \r
- Full: out std_logic; \r
- AlmostFull: out std_logic);\r
-end component;\r
-\r
-signal ff_data_out : std_logic_vector (35 DOWNTO 0) := (others => '0');\r
-signal ff_read_request : std_logic := '0';\r
-signal ff_read_request_i : std_logic := '0';\r
-signal ff_read_request_final : std_logic := '0';\r
-signal ff_empty : std_logic := '0';\r
-signal data_available_i : std_logic := '0';\r
-signal rd_data_count_i : std_logic_vector (9 DOWNTO 0) := (others => '0');\r
-\r
-BEGIN\r
--- data_available <= data_available_i;\r
-process (rd_clk)\r
-begin\r
- if rising_edge(rd_clk) then\r
- ff_read_request <= '0';\r
- if rst='1' then\r
- data_available_i <= '0';\r
- else\r
- if (ff_empty='0') and (data_available_i='0') and (rd_en='0') then\r
- if ff_read_request_i='1' then\r
- ff_read_request <= '0';\r
- dout <= ff_data_out;\r
- data_available_i <= '1';\r
- empty <= '0';\r
- else \r
- if ff_read_request='0' then\r
- ff_read_request <= '1';\r
- end if;\r
- data_available_i <= '0';\r
--- empty <= '0';\r
- end if;\r
- elsif (ff_empty='0') and (data_available_i='0') and (rd_en='1') then -- ignore\r
- if ff_read_request_i='1' then\r
- ff_read_request <= '0';\r
- dout <= ff_data_out;\r
- data_available_i <= '1';\r
- empty <= '0';\r
- else \r
- ff_read_request <= '1';\r
- data_available_i <= '0';\r
--- empty <= '0';\r
- end if;\r
- \r
- elsif (ff_empty='0') and (data_available_i='1') and (rd_en='0') then \r
- if ff_read_request_i='1' then -- should not occur\r
- ff_read_request <= '0';\r
- dout <= ff_data_out;\r
- data_available_i <= '1';\r
- empty <= '0';\r
- else \r
- ff_read_request <= '0';\r
- data_available_i <= '1';\r
- empty <= '0';\r
- end if;\r
- elsif (ff_empty='0') and (data_available_i='1') and (rd_en='1') then \r
- if ff_read_request_i='1' then\r
- ff_read_request <= '1';\r
- dout <= ff_data_out;\r
- data_available_i <= '1';\r
- empty <= '0';\r
- else \r
- ff_read_request <= '1';\r
- data_available_i <= '0';\r
- empty <= '0';\r
- end if;\r
-\r
- elsif (ff_empty='1') and (data_available_i='0') and (rd_en='0') then \r
- if ff_read_request_i='1' then\r
- ff_read_request <= '0';\r
- dout <= ff_data_out;\r
- data_available_i <= '1';\r
- empty <= '0';\r
- else \r
- ff_read_request <= '0';\r
- data_available_i <= '0';\r
- empty <= '1';\r
- end if;\r
- elsif (ff_empty='1') and (data_available_i='0') and (rd_en='1') then -- ignore rd\r
- if ff_read_request_i='1' then\r
- ff_read_request <= '0';\r
- dout <= ff_data_out;\r
- data_available_i <= '1';\r
- empty <= '0';\r
- else \r
- ff_read_request <= '0';\r
- data_available_i <= '0';\r
- empty <= '1';\r
- end if;\r
-\r
- elsif (ff_empty='1') and (data_available_i='1') and (rd_en='0') then \r
- if ff_read_request_i='1' then\r
- ff_read_request <= '0';\r
- dout <= ff_data_out;\r
- data_available_i <= '1';\r
- empty <= '0';\r
- else \r
- ff_read_request <= '0';\r
- data_available_i <= '1';\r
- empty <= '0';\r
- end if;\r
- elsif (ff_empty='1') and (data_available_i='1') and (rd_en='1') then \r
- if ff_read_request_i='1' then\r
- ff_read_request <= '0';\r
- dout <= ff_data_out;\r
- data_available_i <= '1';\r
- empty <= '0';\r
- else \r
- ff_read_request <= '0';\r
- data_available_i <= '0';\r
- empty <= '1';\r
- end if;\r
- end if;\r
- end if;\r
- ff_read_request_i <= ff_read_request_final;\r
- end if;\r
-end process;\r
-\r
-async_fifo_nn_thfull_512x36_ecp3_1: async_fifo_nn_thfull_512x36_ecp3 port map(\r
- Data => din,\r
- WrClock => wr_clk,\r
- RdClock => rd_clk,\r
- WrEn => wr_en,\r
- RdEn => ff_read_request_final,\r
- Reset => rst,\r
- RPReset => rst,\r
- Q => ff_data_out,\r
- RCNT => rd_data_count_i, \r
- Empty => ff_empty,\r
- Full => full,\r
- AlmostFull => prog_full);\r
-rd_data_count <= (others => '1') when rd_data_count_i(9)='1' else rd_data_count_i(8 downto 0);\r
-\r
-ff_read_request_final <= '1' when\r
- ((rd_en='1') and (ff_empty='0') and (data_available_i='1')) or\r
- ((rd_en='0') and (ff_empty='0') and (data_available_i='0') and (ff_read_request_i='0'))\r
- else '0';\r
-\r
-\r
-\r
-END Behavioral;\r
+++ /dev/null
------------------------------------------------------------------------------------\r
--- Wrapper for asynchronous FIFO : width 32, 8 deep\r
------------------------------------------------------------------------------------\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.all;\r
-\r
-ENTITY async_fifo_nn_thfull_FWFT_512x36 IS\r
- PORT\r
- (\r
- rst : in std_logic;\r
- wr_clk : in std_logic;\r
- rd_clk : in std_logic;\r
- din : in std_logic_vector(35 downto 0);\r
- wr_en : in std_logic;\r
- rd_en : in std_logic;\r
- dout : out std_logic_vector(35 downto 0);\r
- full : out std_logic;\r
- empty : out std_logic;\r
- rd_data_count : out std_logic_vector(8 downto 0);\r
- prog_full : out std_logic\r
- );\r
-END async_fifo_nn_thfull_FWFT_512x36;\r
-\r
-\r
-ARCHITECTURE Behavioral OF async_fifo_nn_thfull_FWFT_512x36 IS\r
-component async_fifo_nn_thfull_512x36_ecp3\r
- port (\r
- Data: in std_logic_vector(35 downto 0); \r
- WrClock: in std_logic; \r
- RdClock: in std_logic; \r
- WrEn: in std_logic; \r
- RdEn: in std_logic; \r
- Reset: in std_logic; \r
- RPReset: in std_logic; \r
- Q: out std_logic_vector(35 downto 0); \r
- RCNT: out std_logic_vector(9 downto 0); \r
- Empty: out std_logic; \r
- Full: out std_logic; \r
- AlmostFull: out std_logic);\r
-end component;\r
-\r
-\r
-signal fifo_dout : std_logic_vector (35 downto 0) := (others => '0');\r
-signal middle_dout : std_logic_vector (35 downto 0) := (others => '0');\r
-signal rd_data_count_i : std_logic_vector (9 downto 0) := (others => '0');\r
-signal fifo_empty : std_logic := '0';\r
-signal will_update_middle : std_logic := '0';\r
-signal will_update_dout : std_logic := '0';\r
-signal middle_valid : std_logic := '0';\r
-signal fifo_valid : std_logic := '0';\r
-signal dout_valid : std_logic := '0';\r
-signal fifo_rd_en : std_logic := '0';\r
-\r
-\r
-BEGIN\r
- \r
-async_fifo_nn_thfull_512x36_ecp3_1: async_fifo_nn_thfull_512x36_ecp3 port map(\r
- Data => din,\r
- WrClock => wr_clk,\r
- RdClock => rd_clk,\r
- WrEn => wr_en,\r
- RdEn => fifo_rd_en,\r
- Reset => rst,\r
- RPReset => rst,\r
- Q => fifo_dout,\r
- RCNT => rd_data_count_i, \r
- Empty => fifo_empty,\r
- Full => full,\r
- AlmostFull => prog_full);\r
-rd_data_count <= (others => '1') when rd_data_count_i(9)='1' else rd_data_count_i(8 downto 0);\r
- \r
-will_update_middle <= '1' when (fifo_valid='1') and (middle_valid=will_update_dout) else '0';\r
-will_update_dout <= '1' when ((middle_valid='1') or (fifo_valid='1')) and ((rd_en='1') and (dout_valid='0')) else '0';\r
-fifo_rd_en <= '1' when (fifo_empty='0') and (not (((middle_valid='1') and (dout_valid='1') and (fifo_valid='1')))) else '0';\r
-empty <= not dout_valid;\r
-\r
-process (rd_clk)\r
-begin\r
- if rising_edge(rd_clk) then\r
- if rst='1' then\r
- fifo_valid <= '0';\r
- middle_valid <= '0';\r
- dout_valid <= '0';\r
- dout <= (others => '0');\r
- middle_dout <= (others => '0');\r
- else\r
- if (will_update_middle='1') then\r
- middle_dout <= fifo_dout;\r
- end if;\r
- if (will_update_dout='1') then\r
- if middle_valid='1' then\r
- dout <= middle_dout;\r
- else\r
- dout <= fifo_dout;\r
- end if;\r
- end if;\r
- if (fifo_rd_en='1') then\r
- fifo_valid <= '1';\r
- elsif ((will_update_middle='1') or (will_update_dout='1')) then\r
- fifo_valid <= '0';\r
- end if;\r
- if (will_update_middle='1') then\r
- middle_valid <= '1';\r
- elsif (will_update_dout='1') then\r
- middle_valid <= '0';\r
- end if;\r
- if (will_update_dout='1') then\r
- dout_valid <= '1';\r
- elsif (rd_en='1') then\r
- dout_valid <= '0';\r
- end if;\r
- end if;\r
- end if;\r
-end process;\r
-\r
-END Behavioral;\r
+++ /dev/null
---Media interface for Lattice ECP3 using PCS at 2GHz\r
-\r
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.med_sync_define.all;\r
-\r
-entity trb_net16_med_1_2sync_3_ecp3_sfp is\r
- port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
- REFCLK2CORE_OUT : out std_logic;\r
- CLK_RX_HALF_OUT : out std_logic;\r
- CLK_RX_FULL_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic; -- SFP disable\r
- --Control Interface\r
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
- SCI_READ : in std_logic := '0';\r
- SCI_WRITE : in std_logic := '0';\r
- SCI_ACK : out std_logic := '0';\r
- SCI_NACK : out std_logic := '0';\r
- -- SODA serdes channel\r
- SODA_RXD_P_IN : in std_logic;\r
- SODA_RXD_N_IN : in std_logic;\r
- SODA_TXD_P_OUT : out std_logic;\r
- SODA_TXD_N_OUT : out std_logic;\r
- SODA_DLM_IN : in std_logic;\r
- SODA_DLM_WORD_IN : in std_logic_vector(7 downto 0);\r
- SODA_DLM_OUT : out std_logic;\r
- SODA_DLM_WORD_OUT : out std_logic_vector(7 downto 0);\r
- SODA_CLOCK_OUT : out std_logic; -- 200MHz\r
- \r
- -- Connection to addon interface \r
- DOUT_TXD_P_OUT : out std_logic;\r
- DOUT_TXD_N_OUT : out std_logic;\r
- SFP_MOD0_5 : in std_logic;\r
- SFP_MOD0_3 : in std_logic; \r
- SFP_LOS_5 : in std_logic; \r
- SFP_LOS_3 : in std_logic;\r
- TX_READY_CH3 : out std_logic;\r
- TX_DATA_CH3 : in std_logic_vector(7 downto 0);\r
- TX_K_CH3 : in std_logic;\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end entity;\r
-\r
-architecture trb_net16_med_1_2sync_3_ecp3_sfp_arch of trb_net16_med_1_2sync_3_ecp3_sfp is\r
-\r
-\r
- -- Placer Directives\r
- attribute HGROUP : string;\r
- -- for whole architecture\r
- attribute HGROUP of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "media_interface_group";\r
- attribute syn_sharing : string;\r
- attribute syn_sharing of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "off";\r
-\r
- --OJK 29-nov-2013\r
- component sfp_1_3_200_int\r
- port(\r
- hdinp_ch1 : IN std_logic;
- hdinn_ch1 : IN std_logic;
- sci_sel_ch1 : IN std_logic;
- rxiclk_ch1 : IN std_logic;
- txiclk_ch1 : IN std_logic;
- fpga_rxrefclk_ch1 : IN std_logic;
- txdata_ch1 : IN std_logic_vector(15 downto 0);
- tx_k_ch1 : IN std_logic_vector(1 downto 0);
- tx_force_disp_ch1 : IN std_logic_vector(1 downto 0);
- tx_disp_sel_ch1 : IN std_logic_vector(1 downto 0);
- sb_felb_ch1_c : IN std_logic;
- sb_felb_rst_ch1_c : IN std_logic;
- tx_pwrup_ch1_c : IN std_logic;
- rx_pwrup_ch1_c : IN std_logic;
- tx_div2_mode_ch1_c : IN std_logic;
- rx_div2_mode_ch1_c : IN std_logic;
- sci_sel_ch3 : IN std_logic;
- txiclk_ch3 : IN std_logic;
- fpga_rxrefclk_ch3 : IN std_logic;
- txdata_ch3 : IN std_logic_vector(7 downto 0);
- tx_k_ch3 : IN std_logic;
- tx_force_disp_ch3 : IN std_logic;
- tx_disp_sel_ch3 : IN std_logic;
- tx_pwrup_ch3_c : IN std_logic;
- tx_div2_mode_ch3_c : IN std_logic;
- sci_wrdata : IN std_logic_vector(7 downto 0);
- sci_addr : IN std_logic_vector(5 downto 0);
- sci_sel_quad : IN std_logic;
- sci_rd : IN std_logic;
- sci_wrn : IN std_logic;
- fpga_txrefclk : IN std_logic;
- tx_serdes_rst_c : IN std_logic;
- tx_sync_qd_c : IN std_logic;
- rst_n : IN std_logic;
- serdes_rst_qd_c : IN std_logic;
- hdoutp_ch1 : OUT std_logic;
- hdoutn_ch1 : OUT std_logic;
- rx_full_clk_ch1 : OUT std_logic;
- rx_half_clk_ch1 : OUT std_logic;
- tx_full_clk_ch1 : OUT std_logic;
- tx_half_clk_ch1 : OUT std_logic;
- rxdata_ch1 : OUT std_logic_vector(15 downto 0);
- rx_k_ch1 : OUT std_logic_vector(1 downto 0);
- rx_disp_err_ch1 : OUT std_logic_vector(1 downto 0);
- rx_cv_err_ch1 : OUT std_logic_vector(1 downto 0);
- rx_los_low_ch1_s : OUT std_logic;
- lsm_status_ch1_s : OUT std_logic;
- rx_cdr_lol_ch1_s : OUT std_logic;
- hdoutp_ch3 : OUT std_logic;
- hdoutn_ch3 : OUT std_logic;
- tx_full_clk_ch3 : OUT std_logic;
- tx_half_clk_ch3 : OUT std_logic;
- sci_rddata : OUT std_logic_vector(7 downto 0);
- tx_pll_lol_qd_s : OUT std_logic;
- refclk2fpga : OUT std_logic\r
- );\r
- end component;\r
- \r
--- Peter Schakel 02-12-14\r
-component sfp_1_2sync_3_200_int is\r
- port (\r
-------------------\r
--- CH0 --\r
--- CH1 --\r
- hdinp_ch1, hdinn_ch1 : in std_logic;\r
- hdoutp_ch1, hdoutn_ch1 : out std_logic;\r
- sci_sel_ch1 : in std_logic;\r
- rxiclk_ch1 : in std_logic;\r
- txiclk_ch1 : in std_logic;\r
- rx_full_clk_ch1 : out std_logic;\r
- rx_half_clk_ch1 : out std_logic;\r
- tx_full_clk_ch1 : out std_logic;\r
- tx_half_clk_ch1 : out std_logic;\r
- fpga_rxrefclk_ch1 : in std_logic;\r
- txdata_ch1 : in std_logic_vector (15 downto 0);\r
- tx_k_ch1 : in std_logic_vector (1 downto 0);\r
- tx_force_disp_ch1 : in std_logic_vector (1 downto 0);\r
- tx_disp_sel_ch1 : in std_logic_vector (1 downto 0);\r
- rxdata_ch1 : out std_logic_vector (15 downto 0);\r
- rx_k_ch1 : out std_logic_vector (1 downto 0);\r
- rx_disp_err_ch1 : out std_logic_vector (1 downto 0);\r
- rx_cv_err_ch1 : out std_logic_vector (1 downto 0);\r
- rx_serdes_rst_ch1_c : in std_logic;\r
- sb_felb_ch1_c : in std_logic;\r
- sb_felb_rst_ch1_c : in std_logic;\r
- tx_pcs_rst_ch1_c : in std_logic;\r
- tx_pwrup_ch1_c : in std_logic;\r
- rx_pcs_rst_ch1_c : in std_logic;\r
- rx_pwrup_ch1_c : in std_logic;\r
- rx_los_low_ch1_s : out std_logic;\r
- lsm_status_ch1_s : out std_logic;\r
- rx_cdr_lol_ch1_s : out std_logic;\r
- tx_div2_mode_ch1_c : in std_logic;\r
- rx_div2_mode_ch1_c : in std_logic;\r
--- CH2 --\r
- hdinp_ch2, hdinn_ch2 : in std_logic;\r
- hdoutp_ch2, hdoutn_ch2 : out std_logic;\r
- sci_sel_ch2 : in std_logic;\r
- rxiclk_ch2 : in std_logic;\r
- txiclk_ch2 : in std_logic;\r
- rx_full_clk_ch2 : out std_logic;\r
- rx_half_clk_ch2 : out std_logic;\r
- tx_full_clk_ch2 : out std_logic;\r
- tx_half_clk_ch2 : out std_logic;\r
- fpga_rxrefclk_ch2 : in std_logic;\r
- txdata_ch2 : in std_logic_vector (7 downto 0);\r
- tx_k_ch2 : in std_logic;\r
- tx_force_disp_ch2 : in std_logic;\r
- tx_disp_sel_ch2 : in std_logic;\r
- rxdata_ch2 : out std_logic_vector (7 downto 0);\r
- rx_k_ch2 : out std_logic;\r
- rx_disp_err_ch2 : out std_logic;\r
- rx_cv_err_ch2 : out std_logic;\r
- rx_serdes_rst_ch2_c : in std_logic;\r
- sb_felb_ch2_c : in std_logic;\r
- sb_felb_rst_ch2_c : in std_logic;\r
- tx_pcs_rst_ch2_c : in std_logic;\r
- tx_pwrup_ch2_c : in std_logic;\r
- rx_pcs_rst_ch2_c : in std_logic;\r
- rx_pwrup_ch2_c : in std_logic;\r
- rx_los_low_ch2_s : out std_logic;\r
- lsm_status_ch2_s : out std_logic;\r
- rx_cdr_lol_ch2_s : out std_logic;\r
- tx_div2_mode_ch2_c : in std_logic;\r
- rx_div2_mode_ch2_c : in std_logic;\r
--- CH3 --\r
- hdoutp_ch3, hdoutn_ch3 : out std_logic;\r
- sci_sel_ch3 : in std_logic;\r
- txiclk_ch3 : in std_logic;\r
- tx_full_clk_ch3 : out std_logic;\r
- tx_half_clk_ch3 : out std_logic;\r
- txdata_ch3 : in std_logic_vector (7 downto 0);\r
- tx_k_ch3 : in std_logic;\r
- tx_force_disp_ch3 : in std_logic;\r
- tx_disp_sel_ch3 : in std_logic;\r
- tx_pcs_rst_ch3_c : in std_logic;\r
- tx_pwrup_ch3_c : in std_logic;\r
- tx_div2_mode_ch3_c : in std_logic;\r
----- Miscillaneous ports\r
- sci_wrdata : in std_logic_vector (7 downto 0);\r
- sci_addr : in std_logic_vector (5 downto 0);\r
- sci_rddata : out std_logic_vector (7 downto 0);\r
- sci_sel_quad : in std_logic;\r
- sci_rd : in std_logic;\r
- sci_wrn : in std_logic;\r
- fpga_txrefclk : in std_logic;\r
- tx_serdes_rst_c : in std_logic;\r
- tx_pll_lol_qd_s : out std_logic;\r
- tx_sync_qd_c : in std_logic;\r
- rst_qd_c : in std_logic;\r
- serdes_rst_qd_c : in std_logic);\r
-\r
-end component;\r
-\r
- \r
- \r
- signal refck2core : std_logic;\r
--- signal clock : std_logic;\r
- --reset signals\r
- signal ffc_quad_rst : std_logic;\r
- signal ffc_lane_tx_rst : std_logic;\r
- signal ffc_lane_rx_rst : std_logic;\r
- --serdes connections\r
- signal tx_data : std_logic_vector(15 downto 0);\r
- signal tx_k : std_logic_vector(1 downto 0);\r
- signal rx_data : std_logic_vector(15 downto 0); -- delayed signals\r
- signal rx_k : std_logic_vector(1 downto 0); -- delayed signals\r
- signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP\r
- signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP\r
- signal link_ok : std_logic_vector(1 downto 0); -- OJK 02-dec-2013: Changed width from 1 bit to 2 bits\r
- signal link_error : std_logic_vector(10 downto 0);-- OJK 02-dec-2013: Changed width from 10 bits to 11 bits\r
- signal ff_txhalfclk : std_logic;\r
- signal ff_rxhalfclk : std_logic;\r
- signal ff_rxfullclk : std_logic;\r
- --rx fifo signals\r
- signal fifo_rx_rd_en : std_logic;\r
- signal fifo_rx_wr_en : std_logic;\r
- signal fifo_rx_reset : std_logic;\r
- signal fifo_rx_din : std_logic_vector(17 downto 0);\r
- signal fifo_rx_dout : std_logic_vector(17 downto 0);\r
- signal fifo_rx_full : std_logic;\r
- signal fifo_rx_empty : std_logic;\r
- --tx fifo signals\r
- signal fifo_tx_rd_en : std_logic;\r
- signal fifo_tx_wr_en : std_logic;\r
- signal fifo_tx_reset : std_logic;\r
- signal fifo_tx_din : std_logic_vector(17 downto 0);\r
- signal fifo_tx_dout : std_logic_vector(17 downto 0);\r
- signal fifo_tx_full : std_logic;\r
- signal fifo_tx_empty : std_logic;\r
- signal fifo_tx_almost_full : std_logic;\r
- --rx path\r
- signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- signal buf_med_dataready_out : std_logic;\r
- signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- signal last_rx : std_logic_vector(8 downto 0);\r
- signal last_fifo_rx_empty : std_logic;\r
- --tx path\r
- signal last_fifo_tx_empty : std_logic;\r
- --link status\r
- signal rx_k_q : std_logic_vector(1 downto 0);\r
-\r
- signal quad_rst : std_logic;\r
- signal lane_rst : std_logic;\r
- signal tx_allow : std_logic;\r
- signal rx_allow : std_logic;\r
- signal tx_allow_qtx : std_logic;\r
-\r
- signal rx_allow_q : std_logic; -- clock domain changed signal\r
- signal tx_allow_q : std_logic;\r
- signal swap_bytes : std_logic;\r
- signal buf_stat_debug : std_logic_vector(31 downto 0);\r
-\r
- -- status inputs from SFP\r
- signal sfp_prsnt_n : std_logic; -- synchronized input signals\r
- signal sfp_los : std_logic; -- synchronized input signals\r
-\r
- signal buf_STAT_OP : std_logic_vector(15 downto 0);\r
-\r
- signal led_counter : unsigned(16 downto 0);\r
- signal rx_led : std_logic;\r
- signal tx_led : std_logic;\r
-\r
-\r
- signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion\r
- signal first_idle : std_logic; -- tag the first IDLE2 after data\r
-\r
- signal reset_word_cnt : unsigned(4 downto 0);\r
- signal make_trbnet_reset : std_logic;\r
- signal make_trbnet_reset_q : std_logic;\r
- signal send_reset_words : std_logic;\r
- signal send_reset_words_q : std_logic;\r
- signal send_reset_in : std_logic;\r
- signal send_reset_in_qtx : std_logic;\r
- signal reset_i : std_logic;\r
- signal reset_i_rx : std_logic;\r
- signal pwr_up : std_logic;\r
- signal clear_n : std_logic;\r
-\r
- signal clk_sys : std_logic;\r
- signal clk_tx : std_logic;\r
- signal clk_rx : std_logic;\r
- signal clk_rxref : std_logic;\r
- signal clk_txref : std_logic;\r
-\r
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);\r
-signal sci_state : sci_ctrl;\r
- signal sci_ch_i : std_logic_vector(3 downto 0);\r
- signal sci_qd_i : std_logic;\r
- signal sci_reg_i : std_logic;\r
- signal sci_addr_i : std_logic_vector(8 downto 0);\r
- signal sci_data_in_i : std_logic_vector(7 downto 0);\r
- signal sci_data_out_i : std_logic_vector(7 downto 0);\r
- signal sci_read_i : std_logic;\r
- signal sci_write_i : std_logic;\r
--- signal sci_write_shift_i : std_logic_vector(2 downto 0);\r
--- signal sci_read_shift_i : std_logic_vector(2 downto 0); \r
- \r
- --OJK 13-dec-2013\r
- signal cnt : integer range 0 to 10000;\r
- signal tx_pll_lol_qd_i : std_logic;\r
- -- Peter Schakel 3-dec-2014\r
- \r
- signal sci_timer : unsigned(12 downto 0) := (others => '0');\r
- signal reset_n : std_logic;\r
- signal trb_rx_serdes_rst : std_logic;\r
- signal trb_rx_cdr_lol : std_logic;\r
- signal trb_rx_los_low : std_logic;\r
- signal trb_rx_pcs_rst : std_logic;\r
- signal trb_tx_pcs_rst : std_logic;\r
- signal rst_qd : std_logic;\r
- signal link_OK_S : std_logic;\r
- signal trb_tx_fsm_state : std_logic_vector(3 downto 0);
- signal trb_rx_fsm_state : std_logic_vector(3 downto 0);
- \r
- signal sync_clk_rx_full : std_logic;\r
- signal sync_clk_rx_half : std_logic;\r
- signal sync_clk_tx_full : std_logic;\r
- signal sync_clk_tx_half : std_logic;\r
- signal sync_tx_k : std_logic;\r
- signal sync_tx_data : std_logic_vector(7 downto 0);\r
-\r
- signal syncfifo_din : std_logic_vector(17 downto 0);\r
- signal syncfifo_dout : std_logic_vector(17 downto 0);\r
- \r
- signal sync_rx_k : std_logic;\r
- signal sync_rx_data : std_logic_vector(7 downto 0);\r
- signal sync_rx_serdes_rst : std_logic;\r
- signal sync_rx_cdr_lol : std_logic;\r
- signal sync_tx_pcs_rst : std_logic;\r
- signal sync_rx_pcs_rst : std_logic;\r
- signal sync_rx_los_low : std_logic;\r
- signal sync_lsm_status : std_logic;\r
- signal SD_tx_pcs_rst : std_logic;\r
- signal DLM_fifo_rd_en : std_logic;\r
- signal DLM_fifo_empty : std_logic;\r
- signal DLM_fifo_reading : std_logic := '0'; \r
- signal SODA_dlm_word_S : std_logic_vector(7 downto 0);\r
- signal DLM_received_S : std_logic;\r
- signal sync_wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";\r
- signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";\r
- signal sync_rx_fsm_state : std_logic_vector(3 downto 0);\r
- signal sync_tx_fsm_state : std_logic_vector(3 downto 0);\r
- signal CH3_tx_fsm_state : std_logic_vector(3 downto 0);\r
-\r
- signal CLKdiv100_S : std_logic;\r
- signal sync_clk_rx_fulldiv100_S : std_logic;\r
- \r
- attribute syn_keep : boolean;\r
- attribute syn_preserve : boolean;\r
- attribute syn_keep of led_counter : signal is true;\r
- attribute syn_keep of send_reset_in : signal is true;\r
- attribute syn_keep of reset_i : signal is true;\r
- attribute syn_preserve of reset_i : signal is true;\r
-\r
-begin\r
-\r
---------------------------------------------------------------------------\r
--- Select proper clock configuration\r
---------------------------------------------------------------------------\r
- clk_sys <= SYSCLK;\r
- clk_tx <= SYSCLK;\r
- clk_rx <= ff_rxhalfclk;\r
- clk_rxref <= CLK;\r
- clk_txref <= CLK;\r
-\r
-\r
-\r
-\r
---------------------------------------------------------------------------\r
--- Internal Lane Resets\r
---------------------------------------------------------------------------\r
- clear_n <= not clear;\r
-\r
-\r
- PROC_RESET : process(clk_sys)\r
- begin\r
- if rising_edge(clk_sys) then\r
- reset_i <= RESET;\r
- send_reset_in <= ctrl_op(15);\r
- pwr_up <= '1'; --not CTRL_OP(i*16+14);\r
- end if;\r
- end process;\r
-\r
---------------------------------------------------------------------------\r
--- Synchronizer stages\r
---------------------------------------------------------------------------\r
-\r
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)\r
-THE_SFP_STATUS_SYNC: signal_sync\r
- generic map(\r
- DEPTH => 3,\r
- WIDTH => 2\r
- )\r
- port map(\r
- RESET => '0',\r
- D_IN(0) => sd_prsnt_n_in,\r
- D_IN(1) => sd_los_in,\r
- CLK0 => clk_sys,\r
- CLK1 => clk_sys,\r
- D_OUT(0) => sfp_prsnt_n,\r
- D_OUT(1) => sfp_los\r
- );\r
-\r
-\r
-THE_RX_K_SYNC: signal_sync\r
- generic map(\r
- DEPTH => 1,\r
- WIDTH => 4\r
- )\r
- port map(\r
- RESET => reset_i,\r
- D_IN(1 downto 0) => comb_rx_k,\r
- D_IN(2) => send_reset_words,\r
- D_IN(3) => make_trbnet_reset,\r
- CLK0 => clk_rx, -- CHANGED\r
- CLK1 => clk_sys,\r
- D_OUT(1 downto 0) => rx_k_q,\r
- D_OUT(2) => send_reset_words_q,\r
- D_OUT(3) => make_trbnet_reset_q\r
- );\r
-\r
-THE_RX_DATA_DELAY: signal_sync\r
- generic map(\r
- DEPTH => 2,\r
- WIDTH => 16\r
- )\r
- port map(\r
- RESET => reset_i,\r
- D_IN => comb_rx_data,\r
- CLK0 => clk_rx,\r
- CLK1 => clk_rx,\r
- D_OUT => rx_data\r
- );\r
-\r
-THE_RX_K_DELAY: signal_sync\r
- generic map(\r
- DEPTH => 2,\r
- WIDTH => 2\r
- )\r
- port map(\r
- RESET => reset_i,\r
- D_IN => comb_rx_k,\r
- CLK0 => clk_rx,\r
- CLK1 => clk_rx,\r
- D_OUT => rx_k\r
- );\r
-\r
-THE_RX_RESET: signal_sync\r
- generic map(\r
- DEPTH => 1,\r
- WIDTH => 1\r
- )\r
- port map(\r
- RESET => '0',\r
- D_IN(0) => reset_i,\r
- CLK0 => clk_rx,\r
- CLK1 => clk_rx,\r
- D_OUT(0) => reset_i_rx\r
- );\r
-\r
--- Delay for ALLOW signals\r
-THE_RX_ALLOW_SYNC: signal_sync\r
- generic map(\r
- DEPTH => 2,\r
- WIDTH => 2\r
- )\r
- port map(\r
- RESET => reset_i,\r
- D_IN(0) => rx_allow,\r
- D_IN(1) => tx_allow,\r
- CLK0 => clk_sys,\r
- CLK1 => clk_sys,\r
- D_OUT(0) => rx_allow_q,\r
- D_OUT(1) => tx_allow_q\r
- );\r
-\r
-THE_TX_SYNC: signal_sync\r
- generic map(\r
- DEPTH => 1,\r
- WIDTH => 2\r
- )\r
- port map(\r
- RESET => '0',\r
- D_IN(0) => send_reset_in,\r
- D_IN(1) => tx_allow,\r
- CLK0 => clk_tx,\r
- CLK1 => clk_tx,\r
- D_OUT(0) => send_reset_in_qtx,\r
- D_OUT(1) => tx_allow_qtx\r
- );\r
-\r
-\r
---------------------------------------------------------------------------\r
--- Main control state machine, startup control for SFP\r
---------------------------------------------------------------------------\r
-\r
-THE_SFP_LSM: trb_net16_lsm_sfp\r
- generic map (\r
- HIGHSPEED_STARTUP => c_YES\r
- )\r
- port map(\r
- SYSCLK => clk_sys,\r
- RESET => reset_i,\r
- CLEAR => clear,\r
- SFP_MISSING_IN => sfp_prsnt_n,\r
- SFP_LOS_IN => sfp_los,\r
- SD_LINK_OK_IN => link_OK_S, --// ?? link_ok(0),\r
- SD_LOS_IN => link_error(8),\r
- SD_TXCLK_BAD_IN => link_error(5),\r
- SD_RXCLK_BAD_IN => link_error(4),\r
- SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope\r
- SD_ALIGNMENT_IN => rx_k_q,\r
- SD_CV_IN => link_error(7 downto 6),\r
- FULL_RESET_OUT => quad_rst,\r
- LANE_RESET_OUT => lane_rst,\r
- TX_ALLOW_OUT => tx_allow,\r
- RX_ALLOW_OUT => rx_allow,\r
- SWAP_BYTES_OUT => swap_bytes,\r
- STAT_OP => buf_stat_op,\r
- CTRL_OP => ctrl_op,\r
- STAT_DEBUG => buf_stat_debug\r
- );\r
-\r
-sd_txdis_out <= quad_rst or reset_i;\r
-\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
-\r
-ffc_quad_rst <= quad_rst;\r
-ffc_lane_tx_rst <= lane_rst;\r
-\r
-\r
-ffc_lane_rx_rst <= lane_rst;\r
-\r
--- SerDes clock output to FPGA fabric\r
-REFCLK2CORE_OUT <= ff_rxhalfclk;\r
-CLK_RX_HALF_OUT <= ff_rxhalfclk;\r
-CLK_RX_FULL_OUT <= ff_rxfullclk;\r
-\r
-THE_SERDES: sfp_1_2sync_3_200_int port map(\r
-------------------\r
--- CH0 --\r
--- CH1 --\r
- hdinp_ch1 => sd_rxd_p_in, \r
- hdinn_ch1 => sd_rxd_n_in, \r
- hdoutp_ch1 => sd_txd_p_out, \r
- hdoutn_ch1 => sd_txd_n_out, \r
-\r
- sci_sel_ch1 => sci_ch_i(1),\r
- rxiclk_ch1 => clk_rx, \r
- txiclk_ch1 => clk_tx, \r
- rx_full_clk_ch1 => ff_rxfullclk, \r
- rx_half_clk_ch1 => ff_rxhalfclk, \r
- tx_full_clk_ch1 => open, \r
- tx_half_clk_ch1 => ff_txhalfclk, \r
- fpga_rxrefclk_ch1 => clk_rxref, \r
- txdata_ch1 => tx_data, \r
- tx_k_ch1 => tx_k, \r
- tx_force_disp_ch1 => tx_correct, \r
- tx_disp_sel_ch1 => "00", \r
- rxdata_ch1 => comb_rx_data, \r
- rx_k_ch1 => comb_rx_k, \r
- rx_disp_err_ch1 => open, \r
- rx_cv_err_ch1 => link_error(7 downto 6),\r
- rx_serdes_rst_ch1_c => trb_rx_serdes_rst,\r
- sb_felb_ch1_c => '0', \r
- sb_felb_rst_ch1_c => '0', \r
- tx_pcs_rst_ch1_c => trb_tx_pcs_rst,\r
- tx_pwrup_ch1_c => '1', \r
- rx_pcs_rst_ch1_c => trb_rx_pcs_rst,\r
- rx_pwrup_ch1_c => '1', \r
- rx_los_low_ch1_s => trb_rx_los_low, -- link_error(8), \r
- lsm_status_ch1_s => link_ok(0), \r
- rx_cdr_lol_ch1_s => trb_rx_cdr_lol, -- link_error(4), \r
- tx_div2_mode_ch1_c => '0', \r
- rx_div2_mode_ch1_c => '0',\r
-\r
--- CH2 --\r
- hdinp_ch2 => SODA_RXD_P_IN,\r
- hdinn_ch2 => SODA_RXD_N_IN,\r
- hdoutp_ch2 => SODA_TXD_P_OUT,\r
- hdoutn_ch2 => SODA_TXD_N_OUT,\r
- sci_sel_ch2 => sci_ch_i(2),\r
- rxiclk_ch2 => sync_clk_rx_full, -- ?? CLK,\r
- txiclk_ch2 => sync_clk_tx_full, -- ??CLK, --????? clk_txref\r
- rx_full_clk_ch2 => sync_clk_rx_full,\r
- rx_half_clk_ch2 => sync_clk_rx_half,\r
- tx_full_clk_ch2 => sync_clk_tx_full,\r
- tx_half_clk_ch2 => sync_clk_tx_half,\r
- fpga_rxrefclk_ch2 => CLK,\r
- txdata_ch2 => sync_tx_data,\r
- tx_k_ch2 => sync_tx_k,\r
- tx_force_disp_ch2 => '0',\r
- tx_disp_sel_ch2 => '0',\r
- rxdata_ch2 => sync_rx_data,\r
- rx_k_ch2 => sync_rx_k,\r
- rx_disp_err_ch2 => open,\r
- rx_cv_err_ch2 => open,\r
- rx_serdes_rst_ch2_c => sync_rx_serdes_rst,\r
- sb_felb_ch2_c => '0',\r
- sb_felb_rst_ch2_c => '0',\r
- tx_pcs_rst_ch2_c => sync_tx_pcs_rst,\r
- tx_pwrup_ch2_c => '1',\r
- rx_pcs_rst_ch2_c => sync_rx_pcs_rst,\r
- rx_pwrup_ch2_c => '1',\r
- rx_los_low_ch2_s => sync_rx_los_low,\r
- lsm_status_ch2_s => sync_lsm_status,\r
- rx_cdr_lol_ch2_s => sync_rx_cdr_lol,\r
- tx_div2_mode_ch2_c => '0',\r
- rx_div2_mode_ch2_c => '0',\r
- \r
--- CH3 --\r
- hdoutp_ch3 => DOUT_TXD_P_OUT, \r
- hdoutn_ch3 => DOUT_TXD_N_OUT, \r
- sci_sel_ch3 => '0', --disable access to channel 3 registers\r
- txiclk_ch3 => clk_tx, \r
- tx_full_clk_ch3 => open, \r
- tx_half_clk_ch3 => open, \r
---//???? fpga_rxrefclk_ch3 => clk_rxref, \r
- txdata_ch3 => tx_data_ch3, \r
- tx_k_ch3 => tx_k_ch3,\r
- tx_force_disp_ch3 => '0', \r
- tx_disp_sel_ch3 => '0', \r
- tx_pcs_rst_ch3_c => SD_tx_pcs_rst,\r
- tx_pwrup_ch3_c => '1', \r
- tx_div2_mode_ch3_c => '1', \r
-\r
----- Miscillaneous ports\r
- sci_wrdata => sci_data_in_i,\r
- sci_addr => sci_addr_i(5 downto 0),\r
- sci_rddata => sci_data_out_i,\r
- sci_sel_quad => sci_qd_i,\r
- sci_rd => sci_read_i,\r
- sci_wrn => sci_write_i,\r
- fpga_txrefclk => clk_txref, \r
- tx_serdes_rst_c => CLEAR, \r
- tx_pll_lol_qd_s => tx_pll_lol_qd_i, \r
- tx_sync_qd_c => '0', -- Multiple channel transmit synchronization is not needed?\r
---// refclk2fpga => open, -- Not needed?\r
- rst_qd_c => rst_qd,\r
---//?? rst_n => '1', \r
- serdes_rst_qd_c => ffc_quad_rst \r
- );\r
-\r
- syncfifo_din(7 downto 0) <= SODA_DLM_WORD_IN;\r
- syncfifo_din(17 downto 8) <= (others => '0');\r
- SODA_dlm_word_S <= syncfifo_dout(7 downto 0);\r
-sync_DLM_tx: trb_net_fifo_16bit_bram_dualport\r
-generic map(\r
- USE_STATUS_FLAGS => c_NO\r
- )\r
-port map( read_clock_in => sync_clk_tx_full,\r
- write_clock_in => sync_clk_rx_full, \r
- read_enable_in => DLM_fifo_rd_en,\r
- write_enable_in => SODA_DLM_IN,\r
- fifo_gsr_in => reset,\r
- write_data_in => syncfifo_din,\r
- read_data_out => syncfifo_dout,\r
- full_out => open,\r
- empty_out => DLM_fifo_empty\r
- );\r
-\r
-process(sync_clk_rx_full)\r
-begin\r
- if rising_edge(sync_clk_rx_full) then\r
- SODA_DLM_OUT <= '0';\r
- if DLM_received_S='1' then\r
- DLM_received_S <= '0';\r
- SODA_DLM_OUT <= '1';\r
- SODA_DLM_WORD_OUT <= sync_rx_data;\r
- elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then\r
- DLM_received_S <= '1';\r
- end if;\r
- end if;\r
-end process; \r
-\r
-process(sync_clk_tx_full)\r
-begin\r
- if rising_edge(sync_clk_tx_full) then\r
- if DLM_fifo_rd_en='1' then\r
- DLM_fifo_rd_en <= '0';\r
- sync_tx_data <= SODA_dlm_word_S;\r
- sync_tx_k <= '0';\r
- elsif (DLM_fifo_empty='0') and (DLM_fifo_reading='1') then\r
- DLM_fifo_rd_en <= '1';\r
- sync_tx_data <= x"DC";\r
- sync_tx_k <= '1';\r
- elsif DLM_fifo_empty='0' then\r
- DLM_fifo_reading <= '1';\r
- DLM_fifo_rd_en <= '0';\r
- sync_tx_data <= x"BC"; -- idle\r
- sync_tx_k <= '1'; \r
- else\r
- DLM_fifo_reading <= '0';\r
- DLM_fifo_rd_en <= '0';\r
- sync_tx_data <= x"BC"; -- idle\r
- sync_tx_k <= '1';\r
- end if;\r
- end if;\r
-end process; \r
-SODA_CLOCK_OUT <= sync_clk_rx_full;\r
-\r
-\r
-link_error(8) <= trb_rx_los_low; -- loss of signal\r
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock \r
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock\r
-\r
-reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';\r
-\r
-------------------------------------------------- \r
--- Reset FSM & Link states\r
-------------------------------------------------- \r
-THE_RX_FSM1: rx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- RX_REFCLK => CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RX_SERDES_RST_CH_C => trb_rx_serdes_rst,\r
- RX_CDR_LOL_CH_S => trb_rx_cdr_lol,\r
- RX_LOS_LOW_CH_S => trb_rx_los_low,\r
- RX_PCS_RST_CH_C => trb_rx_pcs_rst,\r
- WA_POSITION => "0000",\r
- STATE_OUT => trb_rx_fsm_state\r
- );\r
-\r
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';\r
-THE_TX_FSM1: tx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- TX_REFCLK => CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RST_QD_C => rst_qd,\r
- TX_PCS_RST_CH_C => trb_tx_pcs_rst,\r
- STATE_OUT => trb_tx_fsm_state\r
- );\r
-\r
-THE_RX_FSM2: rx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- RX_REFCLK => sync_clk_rx_full, --??CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RX_SERDES_RST_CH_C => sync_rx_serdes_rst,\r
- RX_CDR_LOL_CH_S => sync_rx_cdr_lol,\r
- RX_LOS_LOW_CH_S => sync_rx_los_low,\r
- RX_PCS_RST_CH_C => sync_rx_pcs_rst,\r
- WA_POSITION => sync_wa_position_rx(11 downto 8),\r
- STATE_OUT => sync_rx_fsm_state\r
- );\r
-SYNC_WA_POSITION : process(sync_clk_rx_full) --??CLK)\r
-begin\r
- if rising_edge(sync_clk_rx_full) then\r
- sync_wa_position_rx <= wa_position;\r
- end if;\r
-end process;\r
- \r
-THE_TX_FSM2: tx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- TX_REFCLK => CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RST_QD_C => open, --??\r
- TX_PCS_RST_CH_C => sync_tx_pcs_rst,\r
- STATE_OUT => sync_tx_fsm_state\r
- );\r
- \r
-THE_TX_FSM3 : tx_reset_fsm\r
- port map(\r
- RST_N => reset_n,\r
- TX_REFCLK => CLK,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,\r
- RST_QD_C => open, --??\r
- TX_PCS_RST_CH_C => SD_tx_pcs_rst,\r
- STATE_OUT => CH3_tx_fsm_state\r
- );\r
-TX_READY_CH3 <= '1' when (CH3_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';\r
- \r
- \r
--------------------------------------------------------------------------\r
--- RX Fifo & Data output\r
--------------------------------------------------------------------------\r
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport\r
-generic map(\r
- USE_STATUS_FLAGS => c_NO\r
- )\r
-port map( read_clock_in => clk_sys,\r
- write_clock_in => clk_rx, -- CHANGED\r
- read_enable_in => fifo_rx_rd_en,\r
- write_enable_in => fifo_rx_wr_en,\r
- fifo_gsr_in => fifo_rx_reset,\r
- write_data_in => fifo_rx_din,\r
- read_data_out => fifo_rx_dout,\r
- full_out => fifo_rx_full,\r
- empty_out => fifo_rx_empty\r
- );\r
-\r
-fifo_rx_reset <= reset_i or not rx_allow_q;\r
-fifo_rx_rd_en <= not fifo_rx_empty;\r
-\r
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path\r
-THE_BYTE_SWAP_PROC: process(clk_rx)\r
- begin\r
- if rising_edge(clk_rx) then\r
- last_rx <= rx_k(1) & rx_data(15 downto 8);\r
- if( swap_bytes = '0' ) then\r
- fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);\r
- fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);\r
- else\r
- fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);\r
- fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);\r
- end if;\r
- end if;\r
- end process THE_BYTE_SWAP_PROC;\r
-\r
-buf_med_data_out <= fifo_rx_dout(15 downto 0);\r
-buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;\r
-buf_med_packet_num_out <= rx_counter;\r
-med_read_out <= tx_allow_q and not fifo_tx_almost_full;\r
-\r
-\r
-THE_CNT_RESET_PROC : process(clk_rx)\r
- begin\r
- if rising_edge(clk_rx) then\r
- if reset_i_rx = '1' then\r
- send_reset_words <= '0';\r
- make_trbnet_reset <= '0';\r
- reset_word_cnt <= (others => '0');\r
- else\r
- send_reset_words <= '0';\r
- make_trbnet_reset <= '0';\r
- if fifo_rx_din = "11" & x"FEFE" then\r
- if reset_word_cnt(4) = '0' then\r
- reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);\r
- else\r
- send_reset_words <= '1';\r
- end if;\r
- else\r
- reset_word_cnt <= (others => '0');\r
- make_trbnet_reset <= reset_word_cnt(4);\r
- end if;\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
-THE_SYNC_PROC: process(clk_rx)\r
- begin\r
- if rising_edge(clk_rx) then\r
- med_dataready_out <= buf_med_dataready_out;\r
- med_data_out <= buf_med_data_out;\r
- med_packet_num_out <= buf_med_packet_num_out;\r
- if reset_i = '1' then\r
- med_dataready_out <= '0';\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
---rx packet counter\r
----------------------\r
-THE_RX_PACKETS_PROC: process( clk_sys )\r
- begin\r
- if( rising_edge(clk_sys) ) then\r
- last_fifo_rx_empty <= fifo_rx_empty;\r
- if reset_i = '1' or rx_allow_q = '0' then\r
- rx_counter <= c_H0;\r
- else\r
- if( buf_med_dataready_out = '1' ) then\r
- if( rx_counter = c_max_word_number ) then\r
- rx_counter <= (others => '0');\r
- else\r
- rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));\r
- end if;\r
- end if;\r
- end if;\r
- end if;\r
- end process;\r
-\r
---TX Fifo & Data output to Serdes\r
----------------------\r
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport\r
- generic map(\r
- USE_STATUS_FLAGS => c_NO\r
- )\r
- port map( read_clock_in => clk_tx,\r
- write_clock_in => clk_sys,\r
- read_enable_in => fifo_tx_rd_en,\r
- write_enable_in => fifo_tx_wr_en,\r
- fifo_gsr_in => fifo_tx_reset,\r
- write_data_in => fifo_tx_din,\r
- read_data_out => fifo_tx_dout,\r
- full_out => fifo_tx_full,\r
- empty_out => fifo_tx_empty,\r
- almost_full_out => fifo_tx_almost_full\r
- );\r
-\r
-fifo_tx_reset <= reset_i or not tx_allow_q;\r
-fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;\r
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;\r
-fifo_tx_rd_en <= tx_allow_qtx;\r
-\r
-\r
-THE_SERDES_INPUT_PROC: process( clk_tx )\r
- begin\r
- if( rising_edge(clk_tx) ) then\r
- last_fifo_tx_empty <= fifo_tx_empty;\r
- first_idle <= not last_fifo_tx_empty and fifo_tx_empty;\r
- if send_reset_in = '1' then\r
- tx_data <= x"FEFE";\r
- tx_k <= "11";\r
- elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then\r
- tx_data <= x"50bc";\r
- tx_k <= "01";\r
- tx_correct <= first_idle & '0';\r
- else\r
- tx_data <= fifo_tx_dout(15 downto 0);\r
- tx_k <= "00";\r
- tx_correct <= "00";\r
- end if;\r
- end if;\r
- end process THE_SERDES_INPUT_PROC;\r
-\r
-------------------------------------------------- \r
--- SCI\r
-------------------------------------------------- \r
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us\r
-PROC_SCI_CTRL: process(clk_sys)\r
- variable cnt : integer range 0 to 4 := 0;\r
-begin\r
- if( rising_edge(clk_sys) ) then\r
- SCI_ACK <= '0';\r
- case sci_state is\r
- when IDLE =>\r
- sci_ch_i <= x"0";\r
- sci_qd_i <= '0';\r
- sci_reg_i <= '0';\r
- sci_read_i <= '0';\r
- sci_write_i <= '0';\r
- sci_timer <= sci_timer + 1;\r
- if SCI_READ = '1' or SCI_WRITE = '1' then\r
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
- sci_addr_i <= SCI_ADDR;\r
- sci_data_in_i <= SCI_DATA_IN;\r
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
- sci_state <= SCTRL;\r
- elsif sci_timer(sci_timer'left) = '1' then\r
- sci_timer <= (others => '0');\r
- sci_state <= GET_WA;\r
- end if; \r
- when SCTRL =>\r
- if sci_reg_i = '1' then\r
---// SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));\r
- SCI_DATA_OUT <= (others => '0');\r
- SCI_ACK <= '1';\r
- sci_write_i <= '0';\r
- sci_read_i <= '0';\r
- sci_state <= IDLE;\r
- else\r
- sci_state <= SCTRL_WAIT;\r
- end if;\r
- when SCTRL_WAIT =>\r
- sci_state <= SCTRL_WAIT2;\r
- when SCTRL_WAIT2 =>\r
- sci_state <= SCTRL_FINISH;\r
- when SCTRL_FINISH =>\r
- SCI_DATA_OUT <= sci_data_out_i;\r
- SCI_ACK <= '1';\r
- sci_write_i <= '0';\r
- sci_read_i <= '0';\r
- sci_state <= IDLE;\r
- \r
- when GET_WA =>\r
- if cnt = 4 then\r
- cnt := 0;\r
- sci_state <= IDLE;\r
- else\r
- sci_state <= GET_WA_WAIT;\r
- sci_addr_i <= '0' & x"22";\r
- sci_ch_i <= x"0";\r
- sci_ch_i(cnt) <= '1';\r
- sci_read_i <= '1';\r
- end if;\r
- when GET_WA_WAIT =>\r
- sci_state <= GET_WA_WAIT2;\r
- when GET_WA_WAIT2 =>\r
- sci_state <= GET_WA_FINISH;\r
- when GET_WA_FINISH =>\r
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);\r
- sci_state <= GET_WA; \r
- cnt := cnt + 1;\r
- end case;\r
- \r
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then\r
- SCI_NACK <= '1';\r
- else\r
- SCI_NACK <= '0';\r
- end if;\r
- end if;\r
-end process;\r
- \r
- \r
-\r
---Generate LED signals\r
-----------------------\r
-process( clk_sys )\r
- begin\r
- if rising_edge(clk_sys) then\r
- led_counter <= led_counter + to_unsigned(1,1);\r
-\r
- if buf_med_dataready_out = '1' then\r
- rx_led <= '1';\r
- elsif led_counter = 0 then\r
- rx_led <= '0';\r
- end if;\r
-\r
- if tx_k(0) = '0' then\r
- tx_led <= '1';\r
- elsif led_counter = 0 then\r
- tx_led <= '0';\r
- end if;\r
-\r
- end if;\r
- end process;\r
-\r
-stat_op(15) <= send_reset_words_q;\r
-stat_op(14) <= buf_stat_op(14);\r
-stat_op(13) <= make_trbnet_reset_q;\r
-stat_op(12) <= '0';\r
-stat_op(11) <= tx_led; --tx led\r
-stat_op(10) <= rx_led; --rx led\r
-stat_op(9 downto 0) <= buf_stat_op(9 downto 0);\r
-\r
--- Debug output\r
-stat_debug(15 downto 0) <= rx_data;\r
-stat_debug(17 downto 16) <= rx_k;\r
-stat_debug(19 downto 18) <= (others => '0');\r
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);\r
-stat_debug(24) <= fifo_rx_rd_en;\r
-stat_debug(25) <= fifo_rx_wr_en;\r
-stat_debug(26) <= fifo_rx_reset;\r
-stat_debug(27) <= fifo_rx_empty;\r
-stat_debug(28) <= fifo_rx_full;\r
-stat_debug(29) <= last_rx(8);\r
-stat_debug(30) <= rx_allow_q;\r
-stat_debug(41 downto 31) <= (others => '0');\r
-stat_debug(42) <= clk_sys;\r
-stat_debug(43) <= clk_sys;\r
-stat_debug(59 downto 44) <= (others => '0');\r
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);\r
-\r
---stat_debug(3 downto 0) <= buf_stat_debug(3 downto 0); -- state_bits\r
---stat_debug(4) <= buf_stat_debug(4); -- alignme\r
---stat_debug(5) <= sfp_prsnt_n;\r
---stat_debug(6) <= tx_k(0);\r
---stat_debug(7) <= tx_k(1);\r
---stat_debug(8) <= rx_k_q(0);\r
---stat_debug(9) <= rx_k_q(1);\r
---stat_debug(18 downto 10) <= link_error;\r
---stat_debug(19) <= '0';\r
---stat_debug(20) <= link_ok(0);\r
---stat_debug(38 downto 21) <= fifo_rx_din;\r
---stat_debug(39) <= swap_bytes;\r
---stat_debug(40) <= buf_stat_debug(7); -- sfp_missing_in\r
---stat_debug(41) <= buf_stat_debug(8); -- sfp_los_in\r
---stat_debug(42) <= buf_stat_debug(6); -- resync\r
---stat_debug(59 downto 43) <= (others => '0');\r
---stat_debug(63 downto 60) <= link_error(3 downto 0);\r
-\r
-CLKdiv100_process: process(CLK)\r
-variable counter_V : integer range 0 to 99 := 0;\r
-begin\r
- if (rising_edge(CLK)) then \r
- if counter_V<49 then -- 99 for 125MHz\r
- counter_V := counter_V+1;\r
- else\r
- counter_V := 0;\r
- CLKdiv100_S <= not CLKdiv100_S;\r
- end if;\r
- end if;\r
-end process;\r
-sync_clk_rx_fulldiv100_process: process(sync_clk_rx_full)\r
-variable counter_V : integer range 0 to 99 := 0;\r
-begin\r
- if (rising_edge(sync_clk_rx_full)) then \r
- if counter_V<49 then -- 99 for 125MHz\r
- counter_V := counter_V+1;\r
- else\r
- counter_V := 0;\r
- sync_clk_rx_fulldiv100_S <= not sync_clk_rx_fulldiv100_S;\r
- end if;\r
- end if;\r
-end process;\r
-\r
-end architecture;
\ No newline at end of file
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 05-02-2015
+-- Module Name: DC_SODAserdesWrapper
+-- Description: GTP/GTX tranceiver for PANDA Front End Electronics on Kintex7 with clock synchronization
+-- Modifications:
+-- 05-02-2015 Originally FEE_gtxWrapper_Virtex6
+-- 05-02-2015 Originally FEE_gtxWrapper_Kintex7
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library work;
+use work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- DC_SODAserdesWrapper
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization on a Virtex5.
+--
+-- Receiver makes recovered synchronous clock on incomming serial data (SODA).
+-- Data is 16-bits, synchronous to recovered clock.
+-- Transmitter sends 16-bits data.
+--
+-- Only one channel of the dual GTP or GTX is used.
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+--
+-- Inputs:
+-- refClk : Reference clock for GTP/GTX, frequency must match expected SODA frequency
+-- refClk_P : Reference clock for GTP/GTX in case of differential input pins, frequency must match expected SODA frequency
+-- refClk_N : Reference clock for GTP/GTX in case of differential input pins, frequency must match expected SODA frequency
+-- sysClk : stable clock (80MHz)
+-- asyncclk : clock for synchronous resetting
+-- gtpReset : reset GTP/GTX
+-- disable_GTX_reset : disable ressetting temporarely
+-- txData : 16-bits input data to transmit
+-- txCharIsK : data to transmit are K-characters
+-- rxP,rxN : differential transmit inputs from the GTP/GTX
+--
+-- Outputs:
+-- txP,txN : differential transmit outputs of the GTP/GTX
+-- txUsrClk : clock for transmit data
+-- txLocked : transmitter locked
+-- rxData : 16-bits received data
+-- rxCharIsK : received 16-bits data (2 bytes) are K-characters
+-- rxNotInTable : receiver data not valid
+-- rxUsrClk : Recovered synchronous clock
+-- rxLocked : receiver locked to incoming data
+-- GT0_QPLLOUTCLK_OUT : QPLL reference clock, needed for Xilinx
+-- GT0_QPLLOUTREFCLK_OUT : QPLL reference clock, needed for Xilinx
+-- resetDone : resetting ready
+--
+-- Components:
+-- GTXVIRTEX5FEE : Xilinx module for GTP or GTX, generated with the IP core generator with a few adjustments
+-- FEE_rxBitLock : Module for checking and resetting the GTP/GTX to lock the receiver clock at the right phase
+-- Clock_62M5_doubler : Clock doubler with PLL
+--
+----------------------------------------------------------------------------------
+
+entity DC_SODAserdesWrapper is
+ port (
+ refClk : in std_logic;
+ refClk_P : in std_logic;
+ refClk_N : in std_logic;
+ sysClk : in std_logic;
+ asyncclk : in std_logic;
+ gtpReset : in std_logic;
+ disable_GTX_reset : in std_logic;
+
+ txData : in std_logic_vector (7 downto 0);
+ txCharIsK : in std_logic;
+ txP : out std_logic;
+ txN : out std_logic;
+ txUsrClk : out std_logic;
+ txLocked : out std_logic;
+
+ rxData : out std_logic_vector (7 downto 0);
+ rxCharIsK : out std_logic;
+ rxNotInTable : out std_logic;
+ rxP : in std_logic;
+ rxN : in std_logic;
+ rxUsrClk : out std_logic;
+ rxUsrClkdiv2 : out std_logic;
+ rxLocked : out std_logic;
+
+ GT0_QPLLOUTCLK_OUT : out std_logic := '0';
+ GT0_QPLLOUTREFCLK_OUT : out std_logic := '0';
+ resetDone : out std_logic
+ );
+end DC_SODAserdesWrapper;
+
+architecture Behavioral of DC_SODAserdesWrapper is
+
+component GTX_SODAinput_support
+generic
+(
+ -- Simulation attributes
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to TRUE to speed up sim reset
+ STABLE_CLOCK_PERIOD : integer := 10
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_OUT : out std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic := '0';
+ GT0_QPLLOUTREFCLK_OUT : out std_logic := '0';
+ sysclk_in : in std_logic;
+ q2_clk1_gtrefclk : in std_logic; --//modification
+ q3_clk0_gtrefclk : in std_logic --//modification
+);
+end component;
+
+
+component clock100to200 is
+ port
+ (
+ clk_in1 : in std_logic;
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+component DC_rxBitLock is
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ resetDone : in std_logic;
+ lossOfSync : in std_logic;
+ rxPllLocked : in std_logic;
+ rxReset : out std_logic;
+ fsmStatus : out std_logic_vector (1 downto 0)
+ );
+end component;
+
+component DC_data8to16 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ kchar_in : in std_logic;
+ clock_out : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ kchar_out : out std_logic_vector(1 downto 0)
+ );
+end component;
+
+component DC_data16to8 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ kchar_in : in std_logic_vector(1 downto 0);
+ notintable_in : in std_logic_vector(1 downto 0);
+ clock_out : out std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ kchar_out : out std_logic;
+ notintable_out : out std_logic
+ );
+end component;
+
+component DC_posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+component sync_bit is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+end component;
+
+signal gtpReset_S : std_logic;
+signal txReset_S : std_logic;
+signal txResetdone_S : std_logic;
+signal txUsrClkx2_S : std_logic; -- tx clock at double tx speed
+
+signal gtx0_txresetdone_r : std_logic;
+signal gtx0_txresetdone_r2 : std_logic;
+signal txLocked_S : std_logic;
+signal txOutClk_S : std_logic :='0';
+signal txUsrClk_buf_S : std_logic :='0';
+signal txData16_S : std_logic_vector(15 downto 0);
+signal txCharIsK16_S : std_logic_vector(1 downto 0);
+signal txmmcm_lock_S : std_logic;
+signal txmmcm_reset_S : std_logic;
+
+
+signal rxRecClk_S : std_logic :='0';
+signal rxReset_S : std_logic :='0';
+signal rxData_S : std_logic_vector(7 downto 0);
+signal rxCharIsK_S : std_logic;
+signal rxNotInTable_S : std_logic;
+signal rxData16_S : std_logic_vector(15 downto 0);
+signal rxCharIsK16_S : std_logic_vector(1 downto 0);
+signal rxNotInTable16_S : std_logic_vector(1 downto 0);
+signal rxDispError16_S : std_logic_vector(1 downto 0);
+signal rxLocked0_S : std_logic;
+signal rxLocked1_S : std_logic;
+signal rxLocked2_S : std_logic;
+signal rxResetBitLock_S : std_logic :='0';
+signal sync_rxResetBitLock_S : std_logic :='0';
+signal prev_rxResetBitLock_S : std_logic :='0';
+signal rxLossOfSync1_S : std_logic;
+signal fsmStatus_S : std_logic_vector(1 downto 0);
+signal rxPLLwrapper_reset_S : std_logic :='0';
+signal rxResetBitLock_pulse_S : std_logic :='0';
+
+signal rxphmonitor_S : std_logic_vector(4 downto 0);
+signal rxphslipmonitor_S : std_logic_vector(4 downto 0);
+
+signal pllLkDet_S : std_logic :='0';
+signal resetDone_S : std_logic :='0';
+
+signal eyescandataerror_S : std_logic :='0';
+signal rxCDRlock_S : std_logic :='0';
+signal CDR_reset_S : std_logic :='0';
+
+signal drpaddr_in_S : std_logic_vector(8 downto 0);
+signal drpdi_in_S : std_logic_vector(15 downto 0);
+signal drpdo_out_S : std_logic_vector(15 downto 0);
+signal drpen_in_S : std_logic;
+signal drprdy_out_S : std_logic;
+signal drpwe_in_S : std_logic;
+
+signal comma_align_latency_S : std_logic_vector(6 downto 0);
+signal comma_align_latency0_valid_S : std_logic;
+signal comma_align_latency_valid_S : std_logic;
+
+
+type drp_state_type is (initting, running, reading);
+signal drp_state_S : drp_state_type := initting;
+
+
+
+begin
+ resetDone <= resetDone_S;
+ rxLocked <= rxLocked2_S;
+ txLocked <= txLocked_S;
+ rxUsrClkdiv2 <= rxRecClk_S;
+ txUsrClk <= txUsrClkx2_S;
+
+
+process(txUsrClk_buf_S,txResetdone_S)
+ begin
+ if(txResetdone_S = '0') then
+ gtx0_txresetdone_r <= '0';
+ gtx0_txresetdone_r2 <= '0';
+ elsif(txUsrClk_buf_S'event and txUsrClk_buf_S = '1') then
+ gtx0_txresetdone_r <= txResetdone_S;
+ gtx0_txresetdone_r2 <= gtx0_txresetdone_r;
+ end if;
+ end process;
+txReset_S <= '0';
+txLocked_S <= '1' when (gtx0_txresetdone_r2='1') else '0';
+
+
+DC_data8to16_1: DC_data8to16
+ port map(
+ clock_in => txUsrClkx2_S,
+ data_in => txData,
+ kchar_in => txCharIsK,
+ clock_out => txUsrClk_buf_S,
+ data_out => txData16_S,
+ kchar_out => txCharIsK16_S
+ );
+
+DC_data16to8_1: DC_data16to8
+ port map(
+ clock_in => rxRecClk_S,
+ data_in => rxData16_S,
+ kchar_in => rxCharIsK16_S,
+ notintable_in => rxNotInTable16_S,
+ clock_out => rxUsrClk,
+ data_out => rxData_S,
+ kchar_out => rxCharIsK_S,
+ notintable_out => rxNotInTable_S
+ );
+rxData <= rxData_S;
+rxCharIsK <= rxCharIsK_S;
+rxNotInTable <= rxNotInTable_S;
+
+
+-- clock100to200a: clock100to200 port map(
+ -- clk_in1 => txoutclk_S,
+ -- clk_out1 => txUsrClk_buf_S,
+ -- clk_out2 => txUsrClkx2_S,
+ -- reset => gtpReset_S,
+ -- locked => open);
+
+
+--buf_rxclk: BUFG port map(I => rxRecClk_S, O => rxRecClk_buf_S);
+
+
+
+gtx_i : GTX_SODAinput_support
+ port map(
+ SOFT_RESET_TX_IN => gtpReset_S,
+ SOFT_RESET_RX_IN => gtpReset_S,
+ DONT_RESET_ON_DATA_ERROR_IN => '1',
+ Q3_CLK0_GTREFCLK_PAD_N_IN => '0', --// Modified
+ Q3_CLK0_GTREFCLK_PAD_P_IN => '0', --// Modified
+ GT0_TX_MMCM_LOCK_OUT => open,
+ GT0_TX_FSM_RESET_DONE_OUT => open, --// txResetdone_S,
+ GT0_RX_FSM_RESET_DONE_OUT => open, --// resetDone_S,
+ GT0_DATA_VALID_IN => '1',
+ GT0_TXUSRCLK_OUT => open,
+ GT0_TXUSRCLK2_OUT => txoutclk_S,
+ GT0_TXUSRCLKX2_OUT => txUsrClkx2_S,
+ GT0_RXUSRCLK_OUT => open,
+ GT0_RXUSRCLK2_OUT => rxRecClk_S,
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => open,
+ gt0_cplllock_out => pllLkDet_S,
+ gt0_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => drpaddr_in_S,
+ gt0_drpdi_in => drpdi_in_S,
+ gt0_drpdo_out => drpdo_out_S,
+ gt0_drpen_in => drpen_in_S,
+ gt0_drprdy_out => drprdy_out_S,
+ gt0_drpwe_in => drpwe_in_S,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => '0',
+ gt0_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => eyescandataerror_S,
+ gt0_eyescantrigger_in => '0',
+ -------------------------- RX CDR Reset Ports ------------------------ // modified
+ GT0_RXCDRRESET_IN => CDR_reset_S,
+ GT0_RXCDRLOCK_OUT => rxCDRlock_S,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => rxData16_S,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => rxDispError16_S,
+ gt0_rxnotintable_out => rxNotInTable16_S,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => rxP,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => rxN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => rxphmonitor_S,
+ gt0_rxphslipmonitor_out => rxphslipmonitor_S,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => '0',
+ gt0_rxmonitorout_out => open,
+ gt0_rxmonitorsel_in => "00",
+
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => rxReset_S, --// => '0',
+ gt0_rxpmareset_in => rxReset_S, --// => '0',
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => rxCharIsK16_S,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => resetDone_S,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => txReset_S,
+ gt0_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => txData16_S,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => txN,
+ gt0_gtxtxp_out => txP,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out => open,
+ gt0_txoutclkpcs_out => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => txCharIsK16_S,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => txResetdone_S,
+ GT0_QPLLOUTCLK_OUT => GT0_QPLLOUTCLK_OUT,
+ GT0_QPLLOUTREFCLK_OUT => GT0_QPLLOUTREFCLK_OUT,
+ sysclk_in => sysClk,
+ q2_clk1_gtrefclk => refClk_P, --//modification
+ q3_clk0_gtrefclk => refClk_N --//modification
+ );
+
+rxLossOfSync1_S <= '0' when (rxNotInTable16_S="00") or (disable_GTX_reset='1') else '1';
+DC_rxBitLock1 : DC_rxBitLock port map (
+ clk => rxRecClk_S,
+ reset => gtpReset_S,
+ resetDone => resetDone_S,
+ lossOfSync => rxLossOfSync1_S,
+ rxPllLocked => PllLkDet_S,
+ rxReset => rxResetBitLock_S,
+ fsmStatus => fsmStatus_S
+ );
+
+process(sysClk,gtpReset)
+variable counter_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+ if gtpReset='1' then
+ gtpReset_S <= '1';
+ counter_V := (others => '0');
+ elsif rising_edge(sysClk) then
+ gtpReset_S <= '0';
+ if counter_V(counter_V'left)='1' then
+ if resetDone_S='0' then
+ counter_V := (others => '0');
+ gtpReset_S <= '1';
+ end if;
+ else
+ counter_V := counter_V+1;
+ end if;
+ end if;
+end process;
+
+---- rxReset_S <= gtpReset;
+rxReset_S <= '1' when ((rxPLLwrapper_reset_S='1') or (gtpReset_S='1') or (rxResetBitLock_pulse_S='1')) and (disable_GTX_reset='0') else '0';
+--//rxLocked_S <= '1' when (fsmStatus_S = "10") else '0';
+-- peter: gepulste reset (op refclk) voor zowel GTP als PLL
+-- lengte van de reset-pulse varieert om te voorkomen dat de reset synchroon is met de GTP
+----rxPLLwrapper_reset_S <= '1' when (notPllLkDet_S='1') or (rxResetBitLock_pulse_S='1') else '0';
+
+
+--//rxPLLwrapper_reset_S <= '0'; --// '1' when (rxResetBitLock_pulse_S='1') else '0';
+
+rxLocked0_S <= '1' when (resetDone_S='1') and (fsmStatus_S = "10") else '0';
+sync_rx_locked: sync_bit port map(
+ clock => sysClk,
+ data_in => rxLocked0_S,
+ data_out => rxLocked1_S);
+
+process(asyncclk)
+variable resetcounter_V : integer range 0 to 63 := 0;
+variable lastresetcounter_V : integer range 0 to 63 := 10;
+begin
+ if rising_edge(asyncclk) then
+ if (sync_rxResetBitLock_S='1') and (prev_rxResetBitLock_S='0') then
+ rxResetBitLock_pulse_S <= '1';
+ resetcounter_V := 0;
+ if lastresetcounter_V<63 then
+ lastresetcounter_V := lastresetcounter_V+1;
+ else
+ lastresetcounter_V := 10;
+ end if;
+ elsif resetcounter_V<lastresetcounter_V then
+ rxResetBitLock_pulse_S <= '1';
+ resetcounter_V := resetcounter_V+1;
+ else
+ rxResetBitLock_pulse_S <= '0';
+ end if;
+ sync_rxResetBitLock_S <= rxResetBitLock_S;
+ prev_rxResetBitLock_S <= sync_rxResetBitLock_S;
+ end if;
+end process;
+process(sysClk)
+variable counter_V : std_logic_vector(5 downto 0) := (others => '0');
+variable timoutcounter_V : std_logic_vector(11 downto 0) := (others => '0');
+begin
+ if rising_edge(sysClk) then
+ rxPLLwrapper_reset_S <= '0';
+ CDR_reset_S <= '0';
+ comma_align_latency0_valid_S <= '0';
+ drpen_in_S <= '0';
+ drpwe_in_S <= '0';
+ drpdi_in_S <= (others => '0');
+ case drp_state_S is
+ when initting =>
+ rxLocked2_S <= '0';
+ counter_V := (others => '0');
+ if resetDone_S='1' then
+ drp_state_S <= running;
+ end if;
+ when running =>
+ if rxLocked1_S='0' then
+ drp_state_S <= initting;
+ else
+ if counter_V(counter_V'left) = '1' then
+ counter_V := (others => '0');
+ timoutcounter_V := (others => '0');
+ drpen_in_S <= '1';
+ drpaddr_in_S <= "101001110"; -- x"14E";
+ drp_state_S <= reading;
+ else
+ counter_V := counter_V+1;
+ end if;
+ end if;
+ when reading =>
+ if drprdy_out_S='1' then
+ comma_align_latency_S <= drpdo_out_S(6 downto 0); -- COMMA_ALIGN_LATENCY
+ comma_align_latency0_valid_S <= '1';
+ if drpdo_out_S(6 downto 0)/="0000000" then
+ CDR_reset_S <= '1'; --// rxPLLwrapper_reset_S <= '1';
+ rxLocked2_S <= '0';
+ else
+ rxLocked2_S <= '1';
+ end if;
+ drp_state_S <= running;
+ elsif timoutcounter_V(timoutcounter_V'left)='1' then
+ CDR_reset_S <= '1';
+ rxPLLwrapper_reset_S <= '1';
+ drp_state_S <= initting;
+ else
+ timoutcounter_V := timoutcounter_V+1;
+ end if;
+ when others =>
+ drp_state_S <= initting;
+ end case;
+ end if;
+end process;
+
+
+pulse_comma_align_latency: DC_posedge_to_pulse port map(
+ clock_in => sysClk,
+ clock_out => rxRecClk_S,
+ en_clk => '1',
+ signal_in => comma_align_latency0_valid_S,
+ pulse => comma_align_latency_valid_S);
+
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 04-02-2015
+-- Module Name: DC_data16to8
+-- Description: Converts 16 bits data at 100MHz to 8 bits data at 200MHz
+-- Modifications:
+-- 04-05-2015 version Data Concentrator instead of Front End Electronics
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- DC_data16to8
+-- Converts 16 bits data at 100MHz to 8 bits data at 200MHz
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock_in : input clock at single
+-- data_in : 16 bits input data
+-- kchar_in : corresponding k-character (one for each input byte)
+-- notintable_in : error, signal not in 10/8 decoder table
+--
+-- Outputs:
+-- clock_out : output clock at double speed
+-- data_out : 8 bits output data at double speed
+-- kchar_out : corresponding k-character
+-- notintable_out : error, signal not in 10/8 decoder table
+--
+-- Components:
+-- clock100to200 : clock doubler : 100MHz -> 200MHz
+--
+----------------------------------------------------------------------------------
+
+entity DC_data16to8 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ kchar_in : in std_logic_vector(1 downto 0);
+ notintable_in : in std_logic_vector(1 downto 0);
+ clock_out : out std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ kchar_out : out std_logic;
+ notintable_out : out std_logic
+ );
+end DC_data16to8;
+
+architecture Behavioral of DC_data16to8 is
+
+component clock100to200 is
+ port
+ (
+ clk_in1 : in std_logic;
+ clk_out1 : out std_logic;
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+signal clock_out_S : std_logic;
+signal phase_S : std_logic;
+signal kchar_in_S : std_logic_vector(1 downto 0);
+
+begin
+
+clock100to200_1: clock100to200 port map(
+ clk_in1 => clock_in,
+ clk_out1 => clock_out_S,
+ reset => '0',
+ locked => open);
+clock_out <= clock_out_S;
+
+process(clock_out_S)
+begin
+ if (rising_edge(clock_out_S)) then
+ kchar_in_S <= kchar_in;
+ end if;
+end process;
+
+process(clock_out_S)
+begin
+ if (rising_edge(clock_out_S)) then
+ if kchar_in_S/=kchar_in then
+ phase_S <= '0';
+ else
+ phase_S <= not phase_S;
+ end if;
+ end if;
+end process;
+
+process(clock_out_S)
+begin
+ if (rising_edge(clock_out_S)) then
+ if phase_S='1' then
+ data_out <= data_in(7 downto 0);
+ kchar_out <= kchar_in(0);
+ notintable_out <= notintable_in(0);
+ else
+ data_out <= data_in(15 downto 8);
+ kchar_out <= kchar_in(1);
+ notintable_out <= notintable_in(1);
+ end if;
+ end if;
+end process;
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 06-02-2015
+-- Module Name: DC_data8to16
+-- Description: Converts 8 bits data at 200MHz to 16 bits data at 100MHz
+-- Modifications:
+-- 04-05-2015 version Data Concentrator instead of Front End Electronics
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- DC_data8to16
+-- Converts 8 bits data at 200MHz to 16 bits data at 100MHz
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock_in : input clock
+-- data_in : 8 bits input data
+-- kchar_in : corresponding k-character
+--
+-- Outputs:
+-- clock_out : output clock at half speed
+-- data_out : 16 bits output data at half speed
+-- kchar_out : corresponding k-character (one for each byte)
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity DC_data8to16 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ kchar_in : in std_logic;
+ clock_out : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ kchar_out : out std_logic_vector(1 downto 0)
+ );
+end DC_data8to16;
+
+architecture Behavioral of DC_data8to16 is
+
+signal clock_in_S : std_logic;
+signal data_in0_S : std_logic_vector(7 downto 0);
+signal kchar_in0_S : std_logic;
+signal data_in1_S : std_logic_vector(7 downto 0);
+signal kchar_in1_S : std_logic;
+signal data_out_S : std_logic_vector(15 downto 0);
+signal kchar_out_S : std_logic_vector(1 downto 0);
+
+begin
+
+clock_in_S <= clock_in;
+
+
+process(clock_in_S)
+begin
+ if (rising_edge(clock_in_S)) then
+ data_in0_S <= data_in;
+ kchar_in0_S <= kchar_in;
+ data_in1_S <= data_in0_S;
+ kchar_in1_S <= kchar_in0_S;
+ end if;
+end process;
+
+process(clock_out)
+begin
+ if (rising_edge(clock_out)) then
+ data_out_S <= data_in0_S & data_in1_S;
+ kchar_out_S <= kchar_in0_S & kchar_in1_S;
+ data_out <= data_out_S;
+ kchar_out <= kchar_out_S;
+ end if;
+end process;
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Michel Hevinga / Peter Schakel
+-- Create Date: 2010
+-- Module Name: DC_rxBitLock
+-- Description: Module to lock receiving clock of GTP/GTX at the right phase
+-- Modifications:
+-- 18-11-2014 8 bits data instead of 16 bits
+-- 19-11-2014 name changed from rxBitLock to FEE_rxBitLock
+-- 26-05-2015 name changed from FEE_rxBitLock to DC_rxBitLock
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+--use IEEE.NUMERIC_STD.ALL;
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- DC_rxBitLock
+-- Module to lock receiving clock of GTP/GTX at the right phase.
+-- First is checked if the resetDone input is high, (resetting is done)
+-- then if lossOfSync is low ('0'), (GTP/GTX loss of sync signal)
+-- If all these checks are allright the fmstatus will show that the GTP/GTX is locked on th incomming data.
+-- If one of these checks are not reached within a certain time (TIME_OUT_SYNC_MAX constant)
+-- the rxReset output is activated and checking is started again.
+-- Also, the lossOfSync is always checked during operation.
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clk : recovered clock from the GTP/GTX
+-- reset : reset
+-- resetDone : Reset is done, ready to check lock & synchronisation
+-- lossOfSync : Loss of Sync: "00" means synchronised
+-- rxPllLocked : Receiver PLL locked, not used at the moment
+--
+-- Outputs:
+-- rxReset : Reset GTP/GTX to try another lock
+-- fsmStatus : Status of the state machine:
+-- 00 : WAIT_RESET_DONE : waiting until ResetDone
+-- 01 : WAIT_TIME_OUT_SYNC : waiting for word aligned
+-- 10 : CHECK_LOSS_SYNC : running state : keep on checking for Loss of sync and bytes swapped
+-- 11 : RX_RESET : resetting for a new lock attempt
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+entity DC_rxBitLock is
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ resetDone : in std_logic;
+ lossOfSync : in std_logic;
+ rxPllLocked : in std_logic;
+ rxReset : out std_logic;
+ fsmStatus : out std_logic_vector (1 downto 0));
+end DC_rxBitLock;
+
+architecture Behavioral of DC_rxBitLock is
+
+constant TIME_OUT_SYNC_MAX : integer range 0 to 500 := 500;
+
+signal rxReset_S : std_logic :='0';
+signal fsmStatus_S : std_logic_vector (1 downto 0) :="00";
+signal timeOutSynFlag_S : std_logic :='0';
+signal timeOutSyncCounter_I : integer range 0 to TIME_OUT_SYNC_MAX :=0;
+
+signal resettimeFlag_S : std_logic :='0'; -- counter & flag for reset extender
+signal resettimeCounter_I : integer range 0 to 15 :=0; -- counter & flag for reset extender
+
+
+type state_T is (WAIT_RESET_DONE, WAIT_TIME_OUT_SYNC, CHECK_LOSS_SYNC, RX_RESET);
+signal currentState_S,nextState_S : state_T := WAIT_RESET_DONE;
+
+begin
+
+rxReset <= rxReset_S;
+fsmStatus <= fsmStatus_S;
+
+fsmClk: process(clk, reset)
+begin
+ if (reset = '1')then
+ currentState_S <= RX_RESET;
+ else
+ if rising_edge(clk) then
+ currentState_S <= nextState_S;
+ end if;
+ end if;
+end process;
+
+fsmInput: process (currentState_S,resetDone, timeOutSynFlag_S,
+ lossOfSync, rxPllLocked, timeOutSynFlag_S, resettimeFlag_S)
+begin
+ case currentState_S is
+ when WAIT_RESET_DONE => if(resetDone = '1') then
+ nextState_S <= WAIT_TIME_OUT_SYNC;
+ else
+ nextState_S <= WAIT_RESET_DONE;
+ end if;
+ when WAIT_TIME_OUT_SYNC => if (timeOutSynFlag_S = '1') then
+ nextState_S <= RX_RESET;
+ else
+ if (lossOfSync = '0') then
+ nextState_S <= CHECK_LOSS_SYNC;
+ else
+ nextState_S <= WAIT_TIME_OUT_SYNC;
+ end if;
+ end if;
+ when CHECK_LOSS_SYNC => if (lossOfSync /= '0') then
+ nextState_S <= RX_RESET;
+ else
+ nextState_S <= CHECK_LOSS_SYNC;
+ end if;
+ when RX_RESET => if (resettimeFlag_S = '1') then -- reset long to prevent that resetDone signal is missed
+ nextState_S <= WAIT_RESET_DONE;
+ else
+ nextState_S <= RX_RESET;
+ end if;
+ when others => nextState_S <= RX_RESET;
+ end case;
+end process;
+
+fsmOutput: process (clk)
+begin
+if rising_edge(clk) then
+ case currentState_S is
+ when WAIT_RESET_DONE => fsmStatus_S <= "00";
+ rxReset_S <= '0';
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '0';
+ resettimeFlag_S <= '0';
+ resettimeCounter_I <= 0;
+ when WAIT_TIME_OUT_SYNC => fsmStatus_S <= "01";
+ rxReset_S <= '0';
+ resettimeFlag_S <= '0';
+ resettimeCounter_I <= 0;
+ if (timeOutSyncCounter_I < TIME_OUT_SYNC_MAX) then
+ timeOutSyncCounter_I <= timeOutSyncCounter_I+1;
+ timeOutSynFlag_S <= '0';
+ else
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '1';
+ end if;
+ when CHECK_LOSS_SYNC => fsmStatus_S <= "10";
+ rxReset_S <= '0';
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '0';
+ resettimeFlag_S <= '0';
+ resettimeCounter_I <= 0;
+
+ when RX_RESET => fsmStatus_S <= "11";
+ rxReset_S <= '1';
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '0';
+ if resettimeCounter_I<8 then -- peter : reset langer gemaakt om te voorkomen dat resetDone signaal wordt gemist
+ resettimeCounter_I <= resettimeCounter_I+1;
+ resettimeFlag_S <= '0';
+ else
+ resettimeCounter_I <= 0;
+ resettimeFlag_S <= '1';
+ end if;
+
+ when others =>
+ end case;
+end if;
+end process;
+
+
+end Behavioral;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_2gb_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_2gb_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_2gb_wrapper is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ sysclk_in : in std_logic
+
+);
+
+end GTX_trb3_2gb_wrapper;
+
+architecture RTL of GTX_trb3_2gb_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_trb3_2gb
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_trb3_2gb_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_trb3_2gb_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_trb3_2gb_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y10)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q2_clk0_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+ gt0_qplloutclk_out <= gt0_qplloutclk_i;
+ gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+
+
+ gt_usrclk_source : GTX_trb3_2gb_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
+ Q2_CLK0_GTREFCLK_PAD_N_IN => Q2_CLK0_GTREFCLK_PAD_N_IN,
+ Q2_CLK0_GTREFCLK_PAD_P_IN => Q2_CLK0_GTREFCLK_PAD_P_IN,
+ Q2_CLK0_GTREFCLK_OUT => q2_clk0_refclk_i
+
+ );
+
+sysclk_in_i <= sysclk_in;
+
+ common0_i:GTX_trb3_2gb_common
+ generic map
+ (
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => "001"
+ )
+ port map
+ (
+ QPLLREFCLKSEL_IN => "001",
+ GTREFCLK0_IN => q2_clk0_refclk_i,
+ GTREFCLK1_IN => tied_to_ground_i,
+ QPLLLOCK_OUT => gt0_qplllock_i,
+ QPLLLOCKDETCLK_IN => sysclk_in_i,
+ QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+ common_reset_i:GTX_trb3_2gb_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ GTX_trb3_2gb_init_i : GTX_trb3_2gb
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y10)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => q2_clk0_refclk_i,
+ gt0_gtrefclk1_in => tied_to_ground_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.4
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_2gb_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_2gb_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_2gb_wrapper is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ SYSCLK_IN : in std_logic
+
+);
+
+end GTX_trb3_2gb_wrapper;
+
+architecture RTL of GTX_trb3_2gb_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_trb3_2gb
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_trb3_2gb_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_trb3_2gb_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
+);
+port
+(
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_trb3_2gb_GT_USRCLK_SOURCE
+port
+(
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_OUT : out std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ DRPCLK_IN_P : in std_logic;
+ DRPCLK_IN_N : in std_logic;
+ DRPCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y10)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q2_clk0_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+sysclk_in_i <= SYSCLK_IN;
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+ gt0_qplloutclk_out <= gt0_qplloutclk_i;
+ gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+
+
+ gt_usrclk_source : GTX_trb3_2gb_GT_USRCLK_SOURCE
+ port map
+ (
+ Q2_CLK0_GTREFCLK_PAD_N_IN => Q2_CLK0_GTREFCLK_PAD_N_IN,
+ Q2_CLK0_GTREFCLK_PAD_P_IN => Q2_CLK0_GTREFCLK_PAD_P_IN,
+ Q2_CLK0_GTREFCLK_OUT => q2_clk0_refclk_i,
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
+ DRPCLK_IN_P => '0',
+ DRPCLK_IN_N => '1',
+ DRPCLK_OUT => open
+
+ );
+
+
+ common0_i:GTX_trb3_2gb_common
+ generic map
+ (
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
+ )
+ port map
+ (
+ GTREFCLK0_IN => q2_clk0_refclk_i,
+ QPLLLOCK_OUT => gt0_qplllock_i,
+ QPLLLOCKDETCLK_IN => sysclk_in_i,
+ QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+ common_reset_i:GTX_trb3_2gb_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ GTX_trb3_2gb_init_i : GTX_trb3_2gb
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_in => SOFT_RESET_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y10)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => q2_clk0_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
--- /dev/null
+---------------------------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_2gb_common.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_trb3_2gb_common
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_trb3_2gb_common is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
+ SIM_QPLLREFCLK_SEL : bit_vector := "001"
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK1_IN : in std_logic;
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+);
+
+end GTX_trb3_2gb_common;
+
+architecture RTL of GTX_trb3_2gb_common is
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_trb3_2gb_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_TOP : integer := 16;
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
+
+begin
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+
+ gtxe2_common_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
+ SIM_VERSION => "4.0",
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (1)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GTREFCLK0_IN,
+ GTREFCLK1 => GTREFCLK1_IN,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports -----------------------
+ QPLLDMONITOR => open,
+ ----------------------- Common Block - Clocking Ports ----------------------
+ QPLLOUTCLK => QPLLOUTCLK_OUT,
+ QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
+ REFCLKOUTMONITOR => open,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => QPLLLOCK_OUT,
+ QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_vcc_i,
+ QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
+ QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
+ QPLLRESET => QPLLRESET_IN,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ --------------------------------- QPLL Ports -------------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "11111",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+end RTL;
--- /dev/null
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_2gb_common_reset.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module GTX_trb3_2gb_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_trb3_2gb_common_reset is
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic:= '0' --Reset QPLL
+ );
+end GTX_trb3_2gb_common_reset;
+
+architecture RTL of GTX_trb3_2gb_common_reset is
+
+
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+
+ signal init_wait_count : std_logic_vector(7 downto 0) :=(others => '0');
+ signal init_wait_done : std_logic :='0';
+ signal common_reset_asserted : std_logic :='0';
+ signal common_reset_i : std_logic ;
+
+ type rst_type is(
+ INIT, ASSERT_COMMON_RESET);
+
+ signal state : rst_type := INIT;
+
+begin
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ state <= INIT;
+ common_reset_asserted <= '0';
+ COMMON_RESET <= '0';
+ else
+
+ case state is
+ when INIT =>
+ if init_wait_done = '1' then
+ state <= ASSERT_COMMON_RESET;
+ end if;
+
+ when ASSERT_COMMON_RESET =>
+ if common_reset_asserted = '0' then
+ COMMON_RESET <= '1';
+ common_reset_asserted <= '1';
+ else
+ COMMON_RESET <= '0';
+ end if;
+ when OTHERS =>
+ state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_2gb_gt_usrclk_source.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_trb3_2gb_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_trb3_2gb_GT_USRCLK_SOURCE is
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_OUT : out std_logic
+);
+
+
+end GTX_trb3_2gb_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_trb3_2gb_GT_USRCLK_SOURCE is
+
+component GTX_TRB3_2GB_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+
+ attribute syn_noclockbuf : boolean;
+ signal q2_clk0_gtrefclk : std_logic;
+ attribute syn_noclockbuf of q2_clk0_gtrefclk : signal is true;
+
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+ gt0_txoutclk_i <= GT0_TXOUTCLK_IN;
+ gt0_rxoutclk_i <= GT0_RXOUTCLK_IN;
+
+ Q2_CLK0_GTREFCLK_OUT <= q2_clk0_gtrefclk;
+
+ --IBUFDS_GTE2
+ ibufds_instq2_clk0 : IBUFDS_GTE2
+ port map
+ (
+ O => q2_clk0_gtrefclk,
+ ODIV2 => open,
+ CEB => tied_to_ground_i,
+ I => Q2_CLK0_GTREFCLK_PAD_P_IN,
+ IB => Q2_CLK0_GTREFCLK_PAD_N_IN
+ );
+
+
+
+ -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+ -- for improved jitter performance, and to avoid consuming an additional BUFG
+ txoutclk_bufg0_i : BUFG
+ port map
+ (
+ I => gt0_txoutclk_i,
+ O => gt0_txusrclk_i
+ );
+
+
+ rxoutclk_bufg1_i : BUFG
+ port map
+ (
+ I => gt0_rxoutclk_i,
+ O => gt0_rxusrclk_i
+ );
+
+
+
+
+GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_quadsoda_support.vhd, renamed to GTX_quadSODA_wrapper
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_quadSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_quadSODA_wrapper is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q3_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q3_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_OUT : out std_logic;
+ GT0_RX_MMCM_LOCK_OUT : out std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+ GT1_TX_MMCM_LOCK_OUT : out std_logic;
+ GT1_RX_MMCM_LOCK_OUT : out std_logic;
+ GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_DATA_VALID_IN : in std_logic;
+ GT2_TX_MMCM_LOCK_OUT : out std_logic;
+ GT2_RX_MMCM_LOCK_OUT : out std_logic;
+ GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_DATA_VALID_IN : in std_logic;
+ GT3_TX_MMCM_LOCK_OUT : out std_logic;
+ GT3_RX_MMCM_LOCK_OUT : out std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtgrefclk_in : in std_logic;
+ gt0_gtnorthrefclk0_in : in std_logic;
+ gt0_gtnorthrefclk1_in : in std_logic;
+ gt0_gtsouthrefclk0_in : in std_logic;
+ gt0_gtsouthrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtgrefclk_in : in std_logic;
+ gt1_gtnorthrefclk0_in : in std_logic;
+ gt1_gtnorthrefclk1_in : in std_logic;
+ gt1_gtsouthrefclk0_in : in std_logic;
+ gt1_gtsouthrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --GT2 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out : out std_logic;
+ gt2_cplllock_out : out std_logic;
+ gt2_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt2_gtgrefclk_in : in std_logic;
+ gt2_gtnorthrefclk0_in : in std_logic;
+ gt2_gtnorthrefclk1_in : in std_logic;
+ gt2_gtsouthrefclk0_in : in std_logic;
+ gt2_gtsouthrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt2_drpdi_in : in std_logic_vector(15 downto 0);
+ gt2_drpdo_out : out std_logic_vector(15 downto 0);
+ gt2_drpen_in : in std_logic;
+ gt2_drprdy_out : out std_logic;
+ gt2_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in : in std_logic;
+ gt2_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out : out std_logic;
+ gt2_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in : in std_logic;
+ gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in : in std_logic;
+ gt2_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in : in std_logic;
+ gt2_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out : out std_logic;
+ gt2_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclkfabric_out : out std_logic;
+ gt2_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out : out std_logic;
+
+ --GT3 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out : out std_logic;
+ gt3_cplllock_out : out std_logic;
+ gt3_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt3_gtgrefclk_in : in std_logic;
+ gt3_gtnorthrefclk0_in : in std_logic;
+ gt3_gtnorthrefclk1_in : in std_logic;
+ gt3_gtsouthrefclk0_in : in std_logic;
+ gt3_gtsouthrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt3_drpdi_in : in std_logic_vector(15 downto 0);
+ gt3_drpdo_out : out std_logic_vector(15 downto 0);
+ gt3_drpen_in : in std_logic;
+ gt3_drprdy_out : out std_logic;
+ gt3_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in : in std_logic;
+ gt3_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out : out std_logic;
+ gt3_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in : in std_logic;
+ gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in : in std_logic;
+ gt3_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in : in std_logic;
+ gt3_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out : out std_logic;
+ gt3_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclkfabric_out : out std_logic;
+ gt3_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ sysclk_in : in std_logic
+
+);
+
+end GTX_quadSODA_wrapper;
+
+architecture RTL of GTX_quadSODA_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_quadSODA
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+ GT0_RX_MMCM_LOCK_IN : in std_logic;
+ GT0_RX_MMCM_RESET_OUT : out std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+ GT1_TX_MMCM_LOCK_IN : in std_logic;
+ GT1_TX_MMCM_RESET_OUT : out std_logic;
+ GT1_RX_MMCM_LOCK_IN : in std_logic;
+ GT1_RX_MMCM_RESET_OUT : out std_logic;
+ GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_DATA_VALID_IN : in std_logic;
+ GT2_TX_MMCM_LOCK_IN : in std_logic;
+ GT2_TX_MMCM_RESET_OUT : out std_logic;
+ GT2_RX_MMCM_LOCK_IN : in std_logic;
+ GT2_RX_MMCM_RESET_OUT : out std_logic;
+ GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_DATA_VALID_IN : in std_logic;
+ GT3_TX_MMCM_LOCK_IN : in std_logic;
+ GT3_TX_MMCM_RESET_OUT : out std_logic;
+ GT3_RX_MMCM_LOCK_IN : in std_logic;
+ GT3_RX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtgrefclk_in : in std_logic;
+ gt0_gtnorthrefclk0_in : in std_logic;
+ gt0_gtnorthrefclk1_in : in std_logic;
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ gt0_gtsouthrefclk0_in : in std_logic;
+ gt0_gtsouthrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cplllockdetclk_in : in std_logic;
+ gt1_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtgrefclk_in : in std_logic;
+ gt1_gtnorthrefclk0_in : in std_logic;
+ gt1_gtnorthrefclk1_in : in std_logic;
+ gt1_gtrefclk0_in : in std_logic;
+ gt1_gtrefclk1_in : in std_logic;
+ gt1_gtsouthrefclk0_in : in std_logic;
+ gt1_gtsouthrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpclk_in : in std_logic;
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in : in std_logic;
+ gt1_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in : in std_logic;
+ gt1_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out : out std_logic;
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --GT2 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out : out std_logic;
+ gt2_cplllock_out : out std_logic;
+ gt2_cplllockdetclk_in : in std_logic;
+ gt2_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt2_gtgrefclk_in : in std_logic;
+ gt2_gtnorthrefclk0_in : in std_logic;
+ gt2_gtnorthrefclk1_in : in std_logic;
+ gt2_gtrefclk0_in : in std_logic;
+ gt2_gtrefclk1_in : in std_logic;
+ gt2_gtsouthrefclk0_in : in std_logic;
+ gt2_gtsouthrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt2_drpclk_in : in std_logic;
+ gt2_drpdi_in : in std_logic_vector(15 downto 0);
+ gt2_drpdo_out : out std_logic_vector(15 downto 0);
+ gt2_drpen_in : in std_logic;
+ gt2_drprdy_out : out std_logic;
+ gt2_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in : in std_logic;
+ gt2_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out : out std_logic;
+ gt2_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt2_rxusrclk_in : in std_logic;
+ gt2_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in : in std_logic;
+ gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in : in std_logic;
+ gt2_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in : in std_logic;
+ gt2_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt2_txusrclk_in : in std_logic;
+ gt2_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out : out std_logic;
+ gt2_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclk_out : out std_logic;
+ gt2_txoutclkfabric_out : out std_logic;
+ gt2_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out : out std_logic;
+
+ --GT3 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out : out std_logic;
+ gt3_cplllock_out : out std_logic;
+ gt3_cplllockdetclk_in : in std_logic;
+ gt3_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt3_gtgrefclk_in : in std_logic;
+ gt3_gtnorthrefclk0_in : in std_logic;
+ gt3_gtnorthrefclk1_in : in std_logic;
+ gt3_gtrefclk0_in : in std_logic;
+ gt3_gtrefclk1_in : in std_logic;
+ gt3_gtsouthrefclk0_in : in std_logic;
+ gt3_gtsouthrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt3_drpclk_in : in std_logic;
+ gt3_drpdi_in : in std_logic_vector(15 downto 0);
+ gt3_drpdo_out : out std_logic_vector(15 downto 0);
+ gt3_drpen_in : in std_logic;
+ gt3_drprdy_out : out std_logic;
+ gt3_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in : in std_logic;
+ gt3_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out : out std_logic;
+ gt3_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt3_rxusrclk_in : in std_logic;
+ gt3_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in : in std_logic;
+ gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in : in std_logic;
+ gt3_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in : in std_logic;
+ gt3_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt3_txusrclk_in : in std_logic;
+ gt3_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out : out std_logic;
+ gt3_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclk_out : out std_logic;
+ gt3_txoutclkfabric_out : out std_logic;
+ gt3_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_quadSODA_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_quadSODA_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ GTGREFCLK_IN : in std_logic;
+ GTNORTHREFCLK0_IN : in std_logic;
+ GTNORTHREFCLK1_IN : in std_logic;
+ GTSOUTHREFCLK0_IN : in std_logic;
+ GTSOUTHREFCLK1_IN : in std_logic;
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_quadSODA_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_TXCLK_LOCK_OUT : out std_logic;
+ GT0_TX_MMCM_RESET_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXCLK_LOCK_OUT : out std_logic;
+ GT0_RX_MMCM_RESET_IN : in std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_TXOUTCLK_IN : in std_logic;
+ GT1_TXCLK_LOCK_OUT : out std_logic;
+ GT1_TX_MMCM_RESET_IN : in std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+ GT1_RXCLK_LOCK_OUT : out std_logic;
+ GT1_RX_MMCM_RESET_IN : in std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_TXOUTCLK_IN : in std_logic;
+ GT2_TXCLK_LOCK_OUT : out std_logic;
+ GT2_TX_MMCM_RESET_IN : in std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+ GT2_RXCLK_LOCK_OUT : out std_logic;
+ GT2_RX_MMCM_RESET_IN : in std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_TXOUTCLK_IN : in std_logic;
+ GT3_TXCLK_LOCK_OUT : out std_logic;
+ GT3_TX_MMCM_RESET_IN : in std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+ GT3_RXCLK_LOCK_OUT : out std_logic;
+ GT3_RX_MMCM_RESET_IN : in std_logic;
+ Q3_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q3_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+ Q3_CLK1_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+ signal gt1_txfsmresetdone_i : std_logic;
+signal gt1_rxfsmresetdone_i : std_logic;
+ signal gt1_txfsmresetdone_r : std_logic;
+ signal gt1_txfsmresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r : std_logic;
+signal gt1_rxresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r3 : std_logic;
+
+
+ signal gt2_txfsmresetdone_i : std_logic;
+signal gt2_rxfsmresetdone_i : std_logic;
+ signal gt2_txfsmresetdone_r : std_logic;
+ signal gt2_txfsmresetdone_r2 : std_logic;
+signal gt2_rxresetdone_r : std_logic;
+signal gt2_rxresetdone_r2 : std_logic;
+signal gt2_rxresetdone_r3 : std_logic;
+
+
+ signal gt3_txfsmresetdone_i : std_logic;
+signal gt3_rxfsmresetdone_i : std_logic;
+ signal gt3_txfsmresetdone_r : std_logic;
+ signal gt3_txfsmresetdone_r2 : std_logic;
+signal gt3_rxresetdone_r : std_logic;
+signal gt3_rxresetdone_r2 : std_logic;
+signal gt3_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ signal gt0_gtgrefclk_i : std_logic;
+ signal gt0_gtnorthrefclk0_i : std_logic;
+ signal gt0_gtnorthrefclk1_i : std_logic;
+ signal gt0_gtsouthrefclk0_i : std_logic;
+ signal gt0_gtsouthrefclk1_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt1_cpllfbclklost_i : std_logic;
+ signal gt1_cplllock_i : std_logic;
+ signal gt1_cpllrefclklost_i : std_logic;
+ signal gt1_cpllreset_i : std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ signal gt1_gtgrefclk_i : std_logic;
+ signal gt1_gtnorthrefclk0_i : std_logic;
+ signal gt1_gtnorthrefclk1_i : std_logic;
+ signal gt1_gtsouthrefclk0_i : std_logic;
+ signal gt1_gtsouthrefclk1_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt1_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt1_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt1_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt1_drpen_i : std_logic;
+ signal gt1_drprdy_i : std_logic;
+ signal gt1_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt1_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt1_eyescanreset_i : std_logic;
+ signal gt1_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt1_eyescandataerror_i : std_logic;
+ signal gt1_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt1_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt1_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt1_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt1_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt1_gtxrxn_i : std_logic;
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt1_rxlpmhfhold_i : std_logic;
+ signal gt1_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt1_rxdfelpmreset_i : std_logic;
+ signal gt1_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt1_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt1_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt1_gtrxreset_i : std_logic;
+ signal gt1_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt1_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt1_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt1_gttxreset_i : std_logic;
+ signal gt1_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt1_txdlyen_i : std_logic;
+ signal gt1_txdlysreset_i : std_logic;
+ signal gt1_txdlysresetdone_i : std_logic;
+ signal gt1_txphalign_i : std_logic;
+ signal gt1_txphaligndone_i : std_logic;
+ signal gt1_txphalignen_i : std_logic;
+ signal gt1_txphdlyreset_i : std_logic;
+ signal gt1_txphinit_i : std_logic;
+ signal gt1_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt1_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt1_gtxtxn_i : std_logic;
+ signal gt1_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt1_txoutclk_i : std_logic;
+ signal gt1_txoutclkfabric_i : std_logic;
+ signal gt1_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt1_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt1_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT2 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt2_cpllfbclklost_i : std_logic;
+ signal gt2_cplllock_i : std_logic;
+ signal gt2_cpllrefclklost_i : std_logic;
+ signal gt2_cpllreset_i : std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ signal gt2_gtgrefclk_i : std_logic;
+ signal gt2_gtnorthrefclk0_i : std_logic;
+ signal gt2_gtnorthrefclk1_i : std_logic;
+ signal gt2_gtsouthrefclk0_i : std_logic;
+ signal gt2_gtsouthrefclk1_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt2_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt2_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt2_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt2_drpen_i : std_logic;
+ signal gt2_drprdy_i : std_logic;
+ signal gt2_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt2_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt2_eyescanreset_i : std_logic;
+ signal gt2_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt2_eyescandataerror_i : std_logic;
+ signal gt2_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt2_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt2_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt2_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt2_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt2_gtxrxn_i : std_logic;
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt2_rxlpmhfhold_i : std_logic;
+ signal gt2_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt2_rxdfelpmreset_i : std_logic;
+ signal gt2_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt2_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt2_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt2_gtrxreset_i : std_logic;
+ signal gt2_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt2_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt2_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt2_gttxreset_i : std_logic;
+ signal gt2_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt2_txdlyen_i : std_logic;
+ signal gt2_txdlysreset_i : std_logic;
+ signal gt2_txdlysresetdone_i : std_logic;
+ signal gt2_txphalign_i : std_logic;
+ signal gt2_txphaligndone_i : std_logic;
+ signal gt2_txphalignen_i : std_logic;
+ signal gt2_txphdlyreset_i : std_logic;
+ signal gt2_txphinit_i : std_logic;
+ signal gt2_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt2_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt2_gtxtxn_i : std_logic;
+ signal gt2_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt2_txoutclk_i : std_logic;
+ signal gt2_txoutclkfabric_i : std_logic;
+ signal gt2_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt2_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt2_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT3 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt3_cpllfbclklost_i : std_logic;
+ signal gt3_cplllock_i : std_logic;
+ signal gt3_cpllrefclklost_i : std_logic;
+ signal gt3_cpllreset_i : std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ signal gt3_gtgrefclk_i : std_logic;
+ signal gt3_gtnorthrefclk0_i : std_logic;
+ signal gt3_gtnorthrefclk1_i : std_logic;
+ signal gt3_gtsouthrefclk0_i : std_logic;
+ signal gt3_gtsouthrefclk1_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt3_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt3_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt3_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt3_drpen_i : std_logic;
+ signal gt3_drprdy_i : std_logic;
+ signal gt3_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt3_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt3_eyescanreset_i : std_logic;
+ signal gt3_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt3_eyescandataerror_i : std_logic;
+ signal gt3_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt3_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt3_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt3_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt3_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt3_gtxrxn_i : std_logic;
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt3_rxlpmhfhold_i : std_logic;
+ signal gt3_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt3_rxdfelpmreset_i : std_logic;
+ signal gt3_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt3_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt3_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt3_gtrxreset_i : std_logic;
+ signal gt3_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt3_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt3_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt3_gttxreset_i : std_logic;
+ signal gt3_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt3_txdlyen_i : std_logic;
+ signal gt3_txdlysreset_i : std_logic;
+ signal gt3_txdlysresetdone_i : std_logic;
+ signal gt3_txphalign_i : std_logic;
+ signal gt3_txphaligndone_i : std_logic;
+ signal gt3_txphalignen_i : std_logic;
+ signal gt3_txphdlyreset_i : std_logic;
+ signal gt3_txphinit_i : std_logic;
+ signal gt3_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt3_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt3_gtxtxn_i : std_logic;
+ signal gt3_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt3_txoutclk_i : std_logic;
+ signal gt3_txoutclkfabric_i : std_logic;
+ signal gt3_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt3_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt3_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal gt1_tx_system_reset_c : std_logic;
+ signal gt1_rx_system_reset_c : std_logic;
+ signal gt2_tx_system_reset_c : std_logic;
+ signal gt2_rx_system_reset_c : std_logic;
+ signal gt3_tx_system_reset_c : std_logic;
+ signal gt3_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt1_txusrclk_i : std_logic;
+ signal gt1_txusrclk2_i : std_logic;
+ signal gt1_rxusrclk_i : std_logic;
+ signal gt1_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt2_txusrclk_i : std_logic;
+ signal gt2_txusrclk2_i : std_logic;
+ signal gt2_rxusrclk_i : std_logic;
+ signal gt2_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt3_txusrclk_i : std_logic;
+ signal gt3_txusrclk2_i : std_logic;
+ signal gt3_rxusrclk_i : std_logic;
+ signal gt3_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt0_txmmcm_lock_i : std_logic;
+ signal gt0_txmmcm_reset_i : std_logic;
+ signal gt0_rxmmcm_lock_i : std_logic;
+ signal gt0_rxmmcm_reset_i : std_logic;
+ signal gt1_txmmcm_lock_i : std_logic;
+ signal gt1_txmmcm_reset_i : std_logic;
+ signal gt1_rxmmcm_lock_i : std_logic;
+ signal gt1_rxmmcm_reset_i : std_logic;
+ signal gt2_txmmcm_lock_i : std_logic;
+ signal gt2_txmmcm_reset_i : std_logic;
+ signal gt2_rxmmcm_lock_i : std_logic;
+ signal gt2_rxmmcm_reset_i : std_logic;
+ signal gt3_txmmcm_lock_i : std_logic;
+ signal gt3_txmmcm_reset_i : std_logic;
+ signal gt3_rxmmcm_lock_i : std_logic;
+ signal gt3_rxmmcm_reset_i : std_logic;
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q3_clk1_refclk_i : std_logic;
+ signal gt0_gtgrefclk_common_i : std_logic;
+ signal gt0_gtnorthrefclk0_common_i : std_logic;
+ signal gt0_gtnorthrefclk1_common_i : std_logic;
+ signal gt0_gtrefclk1_common_i : std_logic;
+ signal gt0_gtsouthrefclk0_common_i : std_logic;
+ signal gt0_gtsouthrefclk1_common_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+ GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+ GT0_RX_MMCM_LOCK_OUT <= gt0_rxmmcm_lock_i;
+ GT1_TX_MMCM_LOCK_OUT <= gt1_txmmcm_lock_i;
+ GT1_RX_MMCM_LOCK_OUT <= gt1_rxmmcm_lock_i;
+ GT2_TX_MMCM_LOCK_OUT <= gt2_txmmcm_lock_i;
+ GT2_RX_MMCM_LOCK_OUT <= gt2_rxmmcm_lock_i;
+ GT3_TX_MMCM_LOCK_OUT <= gt3_txmmcm_lock_i;
+ GT3_RX_MMCM_LOCK_OUT <= gt3_rxmmcm_lock_i;
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+ gt0_qplloutclk_out <= gt0_qplloutclk_i;
+ gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+ GT1_TXUSRCLK_OUT <= gt1_txusrclk_i;
+ GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+ GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+ GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+
+ GT2_TXUSRCLK_OUT <= gt2_txusrclk_i;
+ GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
+ GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
+ GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
+
+ GT3_TXUSRCLK_OUT <= gt3_txusrclk_i;
+ GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
+ GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
+ GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
+
+
+
+
+
+
+
+
+
+
+ gt_usrclk_source : GTX_quadSODA_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_TXCLK_LOCK_OUT => gt0_txmmcm_lock_i,
+ GT0_TX_MMCM_RESET_IN => gt0_txmmcm_reset_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXCLK_LOCK_OUT => gt0_rxmmcm_lock_i,
+ GT0_RX_MMCM_RESET_IN => gt0_rxmmcm_reset_i,
+
+ GT1_TXUSRCLK_OUT => gt1_txusrclk_i,
+ GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
+ GT1_TXOUTCLK_IN => gt1_txoutclk_i,
+ GT1_TXCLK_LOCK_OUT => gt1_txmmcm_lock_i,
+ GT1_TX_MMCM_RESET_IN => gt1_txmmcm_reset_i,
+ GT1_RXUSRCLK_OUT => gt1_rxusrclk_i,
+ GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
+ GT1_RXCLK_LOCK_OUT => gt1_rxmmcm_lock_i,
+ GT1_RX_MMCM_RESET_IN => gt1_rxmmcm_reset_i,
+
+ GT2_TXUSRCLK_OUT => gt2_txusrclk_i,
+ GT2_TXUSRCLK2_OUT => gt2_txusrclk2_i,
+ GT2_TXOUTCLK_IN => gt2_txoutclk_i,
+ GT2_TXCLK_LOCK_OUT => gt2_txmmcm_lock_i,
+ GT2_TX_MMCM_RESET_IN => gt2_txmmcm_reset_i,
+ GT2_RXUSRCLK_OUT => gt2_rxusrclk_i,
+ GT2_RXUSRCLK2_OUT => gt2_rxusrclk2_i,
+ GT2_RXCLK_LOCK_OUT => gt2_rxmmcm_lock_i,
+ GT2_RX_MMCM_RESET_IN => gt2_rxmmcm_reset_i,
+
+ GT3_TXUSRCLK_OUT => gt3_txusrclk_i,
+ GT3_TXUSRCLK2_OUT => gt3_txusrclk2_i,
+ GT3_TXOUTCLK_IN => gt3_txoutclk_i,
+ GT3_TXCLK_LOCK_OUT => gt3_txmmcm_lock_i,
+ GT3_TX_MMCM_RESET_IN => gt3_txmmcm_reset_i,
+ GT3_RXUSRCLK_OUT => gt3_rxusrclk_i,
+ GT3_RXUSRCLK2_OUT => gt3_rxusrclk2_i,
+ GT3_RXCLK_LOCK_OUT => gt3_rxmmcm_lock_i,
+ GT3_RX_MMCM_RESET_IN => gt3_rxmmcm_reset_i,
+ Q3_CLK1_GTREFCLK_PAD_N_IN => Q3_CLK1_GTREFCLK_PAD_N_IN,
+ Q3_CLK1_GTREFCLK_PAD_P_IN => Q3_CLK1_GTREFCLK_PAD_P_IN,
+ Q3_CLK1_GTREFCLK_OUT => q3_clk1_refclk_i
+
+ );
+
+sysclk_in_i <= sysclk_in;
+
+ common0_i:GTX_quadSODA_common
+ generic map
+ (
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => "001"
+ )
+ port map
+ (
+ GTGREFCLK_IN => gt0_gtgrefclk_common_i,
+ GTNORTHREFCLK0_IN => gt0_gtnorthrefclk0_common_i,
+ GTNORTHREFCLK1_IN => gt0_gtnorthrefclk1_common_i,
+ GTSOUTHREFCLK0_IN => gt0_gtsouthrefclk0_common_i,
+ GTSOUTHREFCLK1_IN => gt0_gtsouthrefclk1_common_i,
+ QPLLREFCLKSEL_IN => "001",
+ GTREFCLK0_IN => tied_to_ground_i,
+ GTREFCLK1_IN => q3_clk1_refclk_i,
+ QPLLLOCK_OUT => gt0_qplllock_i,
+ QPLLLOCKDETCLK_IN => sysclk_in_i,
+ QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+ common_reset_i:GTX_quadSODA_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ GTX_quadSODA_init_i : GTX_quadSODA
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_mmcm_lock_in => gt0_txmmcm_lock_i,
+ gt0_tx_mmcm_reset_out => gt0_txmmcm_reset_i,
+ gt0_rx_mmcm_lock_in => gt0_rxmmcm_lock_i,
+ gt0_rx_mmcm_reset_out => gt0_rxmmcm_reset_i,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+ gt1_tx_mmcm_lock_in => gt1_txmmcm_lock_i,
+ gt1_tx_mmcm_reset_out => gt1_txmmcm_reset_i,
+ gt1_rx_mmcm_lock_in => gt1_rxmmcm_lock_i,
+ gt1_rx_mmcm_reset_out => gt1_rxmmcm_reset_i,
+ gt1_tx_fsm_reset_done_out => gt1_tx_fsm_reset_done_out,
+ gt1_rx_fsm_reset_done_out => gt1_rx_fsm_reset_done_out,
+ gt1_data_valid_in => gt1_data_valid_in,
+ gt2_tx_mmcm_lock_in => gt2_txmmcm_lock_i,
+ gt2_tx_mmcm_reset_out => gt2_txmmcm_reset_i,
+ gt2_rx_mmcm_lock_in => gt2_rxmmcm_lock_i,
+ gt2_rx_mmcm_reset_out => gt2_rxmmcm_reset_i,
+ gt2_tx_fsm_reset_done_out => gt2_tx_fsm_reset_done_out,
+ gt2_rx_fsm_reset_done_out => gt2_rx_fsm_reset_done_out,
+ gt2_data_valid_in => gt2_data_valid_in,
+ gt3_tx_mmcm_lock_in => gt3_txmmcm_lock_i,
+ gt3_tx_mmcm_reset_out => gt3_txmmcm_reset_i,
+ gt3_rx_mmcm_lock_in => gt3_rxmmcm_lock_i,
+ gt3_rx_mmcm_reset_out => gt3_rxmmcm_reset_i,
+ gt3_tx_fsm_reset_done_out => gt3_tx_fsm_reset_done_out,
+ gt3_rx_fsm_reset_done_out => gt3_rx_fsm_reset_done_out,
+ gt3_data_valid_in => gt3_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtgrefclk_in => gt0_gtgrefclk_in,
+ gt0_gtnorthrefclk0_in => gt0_gtnorthrefclk0_in,
+ gt0_gtnorthrefclk1_in => gt0_gtnorthrefclk1_in,
+ gt0_gtrefclk0_in => tied_to_ground_i,
+ gt0_gtrefclk1_in => q3_clk1_refclk_i,
+ gt0_gtsouthrefclk0_in => gt0_gtsouthrefclk0_in,
+ gt0_gtsouthrefclk1_in => gt0_gtsouthrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out => gt1_cpllfbclklost_out,
+ gt1_cplllock_out => gt1_cplllock_out,
+ gt1_cplllockdetclk_in => sysclk_in_i,
+ gt1_cpllreset_in => gt1_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtgrefclk_in => gt1_gtgrefclk_in,
+ gt1_gtnorthrefclk0_in => gt1_gtnorthrefclk0_in,
+ gt1_gtnorthrefclk1_in => gt1_gtnorthrefclk1_in,
+ gt1_gtrefclk0_in => tied_to_ground_i,
+ gt1_gtrefclk1_in => q3_clk1_refclk_i,
+ gt1_gtsouthrefclk0_in => gt1_gtsouthrefclk0_in,
+ gt1_gtsouthrefclk1_in => gt1_gtsouthrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in => gt1_drpaddr_in,
+ gt1_drpclk_in => sysclk_in_i,
+ gt1_drpdi_in => gt1_drpdi_in,
+ gt1_drpdo_out => gt1_drpdo_out,
+ gt1_drpen_in => gt1_drpen_in,
+ gt1_drprdy_out => gt1_drprdy_out,
+ gt1_drpwe_in => gt1_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out => gt1_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in => gt1_eyescanreset_in,
+ gt1_rxuserrdy_in => gt1_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out => gt1_eyescandataerror_out,
+ gt1_eyescantrigger_in => gt1_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in => gt1_rxusrclk_i,
+ gt1_rxusrclk2_in => gt1_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out => gt1_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out => gt1_rxdisperr_out,
+ gt1_rxnotintable_out => gt1_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in => gt1_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in => gt1_gtxrxn_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in,
+ gt1_rxmonitorout_out => gt1_rxmonitorout_out,
+ gt1_rxmonitorsel_in => gt1_rxmonitorsel_in,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in => gt1_gtrxreset_in,
+ gt1_rxpmareset_in => gt1_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out => gt1_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out => gt1_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in => gt1_gttxreset_in,
+ gt1_txuserrdy_in => gt1_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in => gt1_txusrclk_i,
+ gt1_txusrclk2_in => gt1_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in => gt1_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out => gt1_gtxtxn_out,
+ gt1_gtxtxp_out => gt1_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out => gt1_txoutclk_i,
+ gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
+ gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in => gt1_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out => gt1_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT2 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out => gt2_cpllfbclklost_out,
+ gt2_cplllock_out => gt2_cplllock_out,
+ gt2_cplllockdetclk_in => sysclk_in_i,
+ gt2_cpllreset_in => gt2_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt2_gtgrefclk_in => gt2_gtgrefclk_in,
+ gt2_gtnorthrefclk0_in => gt2_gtnorthrefclk0_in,
+ gt2_gtnorthrefclk1_in => gt2_gtnorthrefclk1_in,
+ gt2_gtrefclk0_in => tied_to_ground_i,
+ gt2_gtrefclk1_in => q3_clk1_refclk_i,
+ gt2_gtsouthrefclk0_in => gt2_gtsouthrefclk0_in,
+ gt2_gtsouthrefclk1_in => gt2_gtsouthrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in => gt2_drpaddr_in,
+ gt2_drpclk_in => sysclk_in_i,
+ gt2_drpdi_in => gt2_drpdi_in,
+ gt2_drpdo_out => gt2_drpdo_out,
+ gt2_drpen_in => gt2_drpen_in,
+ gt2_drprdy_out => gt2_drprdy_out,
+ gt2_drpwe_in => gt2_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out => gt2_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in => gt2_eyescanreset_in,
+ gt2_rxuserrdy_in => gt2_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out => gt2_eyescandataerror_out,
+ gt2_eyescantrigger_in => gt2_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt2_rxusrclk_in => gt2_rxusrclk_i,
+ gt2_rxusrclk2_in => gt2_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out => gt2_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out => gt2_rxdisperr_out,
+ gt2_rxnotintable_out => gt2_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in => gt2_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in => gt2_gtxrxn_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in => gt2_rxdfelpmreset_in,
+ gt2_rxmonitorout_out => gt2_rxmonitorout_out,
+ gt2_rxmonitorsel_in => gt2_rxmonitorsel_in,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in => gt2_gtrxreset_in,
+ gt2_rxpmareset_in => gt2_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out => gt2_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out => gt2_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in => gt2_gttxreset_in,
+ gt2_txuserrdy_in => gt2_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt2_txusrclk_in => gt2_txusrclk_i,
+ gt2_txusrclk2_in => gt2_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in => gt2_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out => gt2_gtxtxn_out,
+ gt2_gtxtxp_out => gt2_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclk_out => gt2_txoutclk_i,
+ gt2_txoutclkfabric_out => gt2_txoutclkfabric_out,
+ gt2_txoutclkpcs_out => gt2_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in => gt2_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out => gt2_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT3 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out => gt3_cpllfbclklost_out,
+ gt3_cplllock_out => gt3_cplllock_out,
+ gt3_cplllockdetclk_in => sysclk_in_i,
+ gt3_cpllreset_in => gt3_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt3_gtgrefclk_in => gt3_gtgrefclk_in,
+ gt3_gtnorthrefclk0_in => gt3_gtnorthrefclk0_in,
+ gt3_gtnorthrefclk1_in => gt3_gtnorthrefclk1_in,
+ gt3_gtrefclk0_in => tied_to_ground_i,
+ gt3_gtrefclk1_in => q3_clk1_refclk_i,
+ gt3_gtsouthrefclk0_in => gt3_gtsouthrefclk0_in,
+ gt3_gtsouthrefclk1_in => gt3_gtsouthrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in => gt3_drpaddr_in,
+ gt3_drpclk_in => sysclk_in_i,
+ gt3_drpdi_in => gt3_drpdi_in,
+ gt3_drpdo_out => gt3_drpdo_out,
+ gt3_drpen_in => gt3_drpen_in,
+ gt3_drprdy_out => gt3_drprdy_out,
+ gt3_drpwe_in => gt3_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out => gt3_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in => gt3_eyescanreset_in,
+ gt3_rxuserrdy_in => gt3_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out => gt3_eyescandataerror_out,
+ gt3_eyescantrigger_in => gt3_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt3_rxusrclk_in => gt3_rxusrclk_i,
+ gt3_rxusrclk2_in => gt3_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out => gt3_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out => gt3_rxdisperr_out,
+ gt3_rxnotintable_out => gt3_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in => gt3_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in => gt3_gtxrxn_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in => gt3_rxdfelpmreset_in,
+ gt3_rxmonitorout_out => gt3_rxmonitorout_out,
+ gt3_rxmonitorsel_in => gt3_rxmonitorsel_in,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in => gt3_gtrxreset_in,
+ gt3_rxpmareset_in => gt3_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out => gt3_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out => gt3_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in => gt3_gttxreset_in,
+ gt3_txuserrdy_in => gt3_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt3_txusrclk_in => gt3_txusrclk_i,
+ gt3_txusrclk2_in => gt3_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in => gt3_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out => gt3_gtxtxn_out,
+ gt3_gtxtxp_out => gt3_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclk_out => gt3_txoutclk_i,
+ gt3_txoutclkfabric_out => gt3_txoutclkfabric_out,
+ gt3_txoutclkpcs_out => gt3_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in => gt3_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out => gt3_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_quadsoda_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_quadSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_quadSODA_wrapper is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+ GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_DATA_VALID_IN : in std_logic;
+ GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_DATA_VALID_IN : in std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --GT2 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out : out std_logic;
+ gt2_cplllock_out : out std_logic;
+ gt2_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt2_drpdi_in : in std_logic_vector(15 downto 0);
+ gt2_drpdo_out : out std_logic_vector(15 downto 0);
+ gt2_drpen_in : in std_logic;
+ gt2_drprdy_out : out std_logic;
+ gt2_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in : in std_logic;
+ gt2_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out : out std_logic;
+ gt2_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in : in std_logic;
+ gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in : in std_logic;
+ gt2_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in : in std_logic;
+ gt2_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out : out std_logic;
+ gt2_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclkfabric_out : out std_logic;
+ gt2_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out : out std_logic;
+
+ --GT3 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out : out std_logic;
+ gt3_cplllock_out : out std_logic;
+ gt3_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt3_drpdi_in : in std_logic_vector(15 downto 0);
+ gt3_drpdo_out : out std_logic_vector(15 downto 0);
+ gt3_drpen_in : in std_logic;
+ gt3_drprdy_out : out std_logic;
+ gt3_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in : in std_logic;
+ gt3_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out : out std_logic;
+ gt3_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in : in std_logic;
+ gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in : in std_logic;
+ gt3_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in : in std_logic;
+ gt3_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out : out std_logic;
+ gt3_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclkfabric_out : out std_logic;
+ gt3_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ sysclk_in : in std_logic
+
+);
+
+end GTX_quadSODA_wrapper;
+
+architecture RTL of GTX_quadSODA_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_quadSODA
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+ GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_DATA_VALID_IN : in std_logic;
+ GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_DATA_VALID_IN : in std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cplllockdetclk_in : in std_logic;
+ gt1_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtrefclk0_in : in std_logic;
+ gt1_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpclk_in : in std_logic;
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in : in std_logic;
+ gt1_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in : in std_logic;
+ gt1_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out : out std_logic;
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --GT2 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out : out std_logic;
+ gt2_cplllock_out : out std_logic;
+ gt2_cplllockdetclk_in : in std_logic;
+ gt2_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt2_gtrefclk0_in : in std_logic;
+ gt2_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt2_drpclk_in : in std_logic;
+ gt2_drpdi_in : in std_logic_vector(15 downto 0);
+ gt2_drpdo_out : out std_logic_vector(15 downto 0);
+ gt2_drpen_in : in std_logic;
+ gt2_drprdy_out : out std_logic;
+ gt2_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in : in std_logic;
+ gt2_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out : out std_logic;
+ gt2_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt2_rxusrclk_in : in std_logic;
+ gt2_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in : in std_logic;
+ gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in : in std_logic;
+ gt2_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in : in std_logic;
+ gt2_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt2_txusrclk_in : in std_logic;
+ gt2_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out : out std_logic;
+ gt2_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclk_out : out std_logic;
+ gt2_txoutclkfabric_out : out std_logic;
+ gt2_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out : out std_logic;
+
+ --GT3 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out : out std_logic;
+ gt3_cplllock_out : out std_logic;
+ gt3_cplllockdetclk_in : in std_logic;
+ gt3_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt3_gtrefclk0_in : in std_logic;
+ gt3_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt3_drpclk_in : in std_logic;
+ gt3_drpdi_in : in std_logic_vector(15 downto 0);
+ gt3_drpdo_out : out std_logic_vector(15 downto 0);
+ gt3_drpen_in : in std_logic;
+ gt3_drprdy_out : out std_logic;
+ gt3_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in : in std_logic;
+ gt3_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out : out std_logic;
+ gt3_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt3_rxusrclk_in : in std_logic;
+ gt3_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in : in std_logic;
+ gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in : in std_logic;
+ gt3_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in : in std_logic;
+ gt3_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt3_txusrclk_in : in std_logic;
+ gt3_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out : out std_logic;
+ gt3_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclk_out : out std_logic;
+ gt3_txoutclkfabric_out : out std_logic;
+ gt3_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_quadSODA_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_quadSODA_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_quadSODA_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_TXOUTCLK_IN : in std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_TXOUTCLK_IN : in std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_TXOUTCLK_IN : in std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+ signal gt1_txfsmresetdone_i : std_logic;
+signal gt1_rxfsmresetdone_i : std_logic;
+ signal gt1_txfsmresetdone_r : std_logic;
+ signal gt1_txfsmresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r : std_logic;
+signal gt1_rxresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r3 : std_logic;
+
+
+ signal gt2_txfsmresetdone_i : std_logic;
+signal gt2_rxfsmresetdone_i : std_logic;
+ signal gt2_txfsmresetdone_r : std_logic;
+ signal gt2_txfsmresetdone_r2 : std_logic;
+signal gt2_rxresetdone_r : std_logic;
+signal gt2_rxresetdone_r2 : std_logic;
+signal gt2_rxresetdone_r3 : std_logic;
+
+
+ signal gt3_txfsmresetdone_i : std_logic;
+signal gt3_rxfsmresetdone_i : std_logic;
+ signal gt3_txfsmresetdone_r : std_logic;
+ signal gt3_txfsmresetdone_r2 : std_logic;
+signal gt3_rxresetdone_r : std_logic;
+signal gt3_rxresetdone_r2 : std_logic;
+signal gt3_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt1_cpllfbclklost_i : std_logic;
+ signal gt1_cplllock_i : std_logic;
+ signal gt1_cpllrefclklost_i : std_logic;
+ signal gt1_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt1_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt1_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt1_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt1_drpen_i : std_logic;
+ signal gt1_drprdy_i : std_logic;
+ signal gt1_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt1_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt1_eyescanreset_i : std_logic;
+ signal gt1_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt1_eyescandataerror_i : std_logic;
+ signal gt1_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt1_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt1_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt1_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt1_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt1_gtxrxn_i : std_logic;
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt1_rxlpmhfhold_i : std_logic;
+ signal gt1_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt1_rxdfelpmreset_i : std_logic;
+ signal gt1_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt1_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt1_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt1_gtrxreset_i : std_logic;
+ signal gt1_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt1_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt1_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt1_gttxreset_i : std_logic;
+ signal gt1_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt1_txdlyen_i : std_logic;
+ signal gt1_txdlysreset_i : std_logic;
+ signal gt1_txdlysresetdone_i : std_logic;
+ signal gt1_txphalign_i : std_logic;
+ signal gt1_txphaligndone_i : std_logic;
+ signal gt1_txphalignen_i : std_logic;
+ signal gt1_txphdlyreset_i : std_logic;
+ signal gt1_txphinit_i : std_logic;
+ signal gt1_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt1_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt1_gtxtxn_i : std_logic;
+ signal gt1_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt1_txoutclk_i : std_logic;
+ signal gt1_txoutclkfabric_i : std_logic;
+ signal gt1_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt1_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt1_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT2 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt2_cpllfbclklost_i : std_logic;
+ signal gt2_cplllock_i : std_logic;
+ signal gt2_cpllrefclklost_i : std_logic;
+ signal gt2_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt2_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt2_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt2_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt2_drpen_i : std_logic;
+ signal gt2_drprdy_i : std_logic;
+ signal gt2_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt2_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt2_eyescanreset_i : std_logic;
+ signal gt2_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt2_eyescandataerror_i : std_logic;
+ signal gt2_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt2_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt2_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt2_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt2_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt2_gtxrxn_i : std_logic;
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt2_rxlpmhfhold_i : std_logic;
+ signal gt2_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt2_rxdfelpmreset_i : std_logic;
+ signal gt2_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt2_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt2_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt2_gtrxreset_i : std_logic;
+ signal gt2_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt2_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt2_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt2_gttxreset_i : std_logic;
+ signal gt2_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt2_txdlyen_i : std_logic;
+ signal gt2_txdlysreset_i : std_logic;
+ signal gt2_txdlysresetdone_i : std_logic;
+ signal gt2_txphalign_i : std_logic;
+ signal gt2_txphaligndone_i : std_logic;
+ signal gt2_txphalignen_i : std_logic;
+ signal gt2_txphdlyreset_i : std_logic;
+ signal gt2_txphinit_i : std_logic;
+ signal gt2_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt2_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt2_gtxtxn_i : std_logic;
+ signal gt2_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt2_txoutclk_i : std_logic;
+ signal gt2_txoutclkfabric_i : std_logic;
+ signal gt2_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt2_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt2_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT3 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt3_cpllfbclklost_i : std_logic;
+ signal gt3_cplllock_i : std_logic;
+ signal gt3_cpllrefclklost_i : std_logic;
+ signal gt3_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt3_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt3_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt3_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt3_drpen_i : std_logic;
+ signal gt3_drprdy_i : std_logic;
+ signal gt3_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt3_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt3_eyescanreset_i : std_logic;
+ signal gt3_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt3_eyescandataerror_i : std_logic;
+ signal gt3_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt3_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt3_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt3_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt3_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt3_gtxrxn_i : std_logic;
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt3_rxlpmhfhold_i : std_logic;
+ signal gt3_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt3_rxdfelpmreset_i : std_logic;
+ signal gt3_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt3_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt3_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt3_gtrxreset_i : std_logic;
+ signal gt3_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt3_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt3_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt3_gttxreset_i : std_logic;
+ signal gt3_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt3_txdlyen_i : std_logic;
+ signal gt3_txdlysreset_i : std_logic;
+ signal gt3_txdlysresetdone_i : std_logic;
+ signal gt3_txphalign_i : std_logic;
+ signal gt3_txphaligndone_i : std_logic;
+ signal gt3_txphalignen_i : std_logic;
+ signal gt3_txphdlyreset_i : std_logic;
+ signal gt3_txphinit_i : std_logic;
+ signal gt3_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt3_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt3_gtxtxn_i : std_logic;
+ signal gt3_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt3_txoutclk_i : std_logic;
+ signal gt3_txoutclkfabric_i : std_logic;
+ signal gt3_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt3_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt3_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal gt1_tx_system_reset_c : std_logic;
+ signal gt1_rx_system_reset_c : std_logic;
+ signal gt2_tx_system_reset_c : std_logic;
+ signal gt2_rx_system_reset_c : std_logic;
+ signal gt3_tx_system_reset_c : std_logic;
+ signal gt3_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt1_txusrclk_i : std_logic;
+ signal gt1_txusrclk2_i : std_logic;
+ signal gt1_rxusrclk_i : std_logic;
+ signal gt1_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt2_txusrclk_i : std_logic;
+ signal gt2_txusrclk2_i : std_logic;
+ signal gt2_rxusrclk_i : std_logic;
+ signal gt2_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt3_txusrclk_i : std_logic;
+ signal gt3_txusrclk2_i : std_logic;
+ signal gt3_rxusrclk_i : std_logic;
+ signal gt3_rxusrclk2_i : std_logic;
+
+
+
+
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q2_clk1_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+ gt0_qplloutclk_out <= gt0_qplloutclk_i;
+ gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+ GT1_TXUSRCLK_OUT <= gt1_txusrclk_i;
+ GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+ GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+ GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+
+ GT2_TXUSRCLK_OUT <= gt2_txusrclk_i;
+ GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
+ GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
+ GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
+
+ GT3_TXUSRCLK_OUT <= gt3_txusrclk_i;
+ GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
+ GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
+ GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
+
+
+
+
+
+
+
+
+
+
+ gt_usrclk_source : GTX_quadSODA_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+
+ GT1_TXUSRCLK_OUT => gt1_txusrclk_i,
+ GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
+ GT1_TXOUTCLK_IN => gt1_txoutclk_i,
+ GT1_RXUSRCLK_OUT => gt1_rxusrclk_i,
+ GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
+
+ GT2_TXUSRCLK_OUT => gt2_txusrclk_i,
+ GT2_TXUSRCLK2_OUT => gt2_txusrclk2_i,
+ GT2_TXOUTCLK_IN => gt2_txoutclk_i,
+ GT2_RXUSRCLK_OUT => gt2_rxusrclk_i,
+ GT2_RXUSRCLK2_OUT => gt2_rxusrclk2_i,
+
+ GT3_TXUSRCLK_OUT => gt3_txusrclk_i,
+ GT3_TXUSRCLK2_OUT => gt3_txusrclk2_i,
+ GT3_TXOUTCLK_IN => gt3_txoutclk_i,
+ GT3_RXUSRCLK_OUT => gt3_rxusrclk_i,
+ GT3_RXUSRCLK2_OUT => gt3_rxusrclk2_i,
+ Q2_CLK1_GTREFCLK_PAD_N_IN => Q2_CLK1_GTREFCLK_PAD_N_IN,
+ Q2_CLK1_GTREFCLK_PAD_P_IN => Q2_CLK1_GTREFCLK_PAD_P_IN,
+ Q2_CLK1_GTREFCLK_OUT => q2_clk1_refclk_i
+
+ );
+
+sysclk_in_i <= sysclk_in;
+
+ common0_i:GTX_quadSODA_common
+ generic map
+ (
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => "001"
+ )
+ port map
+ (
+ QPLLREFCLKSEL_IN => "001",
+ GTREFCLK0_IN => tied_to_ground_i,
+ GTREFCLK1_IN => q2_clk1_refclk_i,
+ QPLLLOCK_OUT => gt0_qplllock_i,
+ QPLLLOCKDETCLK_IN => sysclk_in_i,
+ QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+ common_reset_i:GTX_quadSODA_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ GTX_quadSODA_init_i : GTX_quadSODA
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+ gt1_tx_fsm_reset_done_out => gt1_tx_fsm_reset_done_out,
+ gt1_rx_fsm_reset_done_out => gt1_rx_fsm_reset_done_out,
+ gt1_data_valid_in => gt1_data_valid_in,
+ gt2_tx_fsm_reset_done_out => gt2_tx_fsm_reset_done_out,
+ gt2_rx_fsm_reset_done_out => gt2_rx_fsm_reset_done_out,
+ gt2_data_valid_in => gt2_data_valid_in,
+ gt3_tx_fsm_reset_done_out => gt3_tx_fsm_reset_done_out,
+ gt3_rx_fsm_reset_done_out => gt3_rx_fsm_reset_done_out,
+ gt3_data_valid_in => gt3_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => tied_to_ground_i,
+ gt0_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out => gt1_cpllfbclklost_out,
+ gt1_cplllock_out => gt1_cplllock_out,
+ gt1_cplllockdetclk_in => sysclk_in_i,
+ gt1_cpllreset_in => gt1_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtrefclk0_in => tied_to_ground_i,
+ gt1_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in => gt1_drpaddr_in,
+ gt1_drpclk_in => sysclk_in_i,
+ gt1_drpdi_in => gt1_drpdi_in,
+ gt1_drpdo_out => gt1_drpdo_out,
+ gt1_drpen_in => gt1_drpen_in,
+ gt1_drprdy_out => gt1_drprdy_out,
+ gt1_drpwe_in => gt1_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out => gt1_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in => gt1_eyescanreset_in,
+ gt1_rxuserrdy_in => gt1_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out => gt1_eyescandataerror_out,
+ gt1_eyescantrigger_in => gt1_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in => gt1_rxusrclk_i,
+ gt1_rxusrclk2_in => gt1_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out => gt1_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out => gt1_rxdisperr_out,
+ gt1_rxnotintable_out => gt1_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in => gt1_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in => gt1_gtxrxn_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in,
+ gt1_rxmonitorout_out => gt1_rxmonitorout_out,
+ gt1_rxmonitorsel_in => gt1_rxmonitorsel_in,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in => gt1_gtrxreset_in,
+ gt1_rxpmareset_in => gt1_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out => gt1_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out => gt1_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in => gt1_gttxreset_in,
+ gt1_txuserrdy_in => gt1_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in => gt1_txusrclk_i,
+ gt1_txusrclk2_in => gt1_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in => gt1_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out => gt1_gtxtxn_out,
+ gt1_gtxtxp_out => gt1_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out => gt1_txoutclk_i,
+ gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
+ gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in => gt1_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out => gt1_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT2 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out => gt2_cpllfbclklost_out,
+ gt2_cplllock_out => gt2_cplllock_out,
+ gt2_cplllockdetclk_in => sysclk_in_i,
+ gt2_cpllreset_in => gt2_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt2_gtrefclk0_in => tied_to_ground_i,
+ gt2_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in => gt2_drpaddr_in,
+ gt2_drpclk_in => sysclk_in_i,
+ gt2_drpdi_in => gt2_drpdi_in,
+ gt2_drpdo_out => gt2_drpdo_out,
+ gt2_drpen_in => gt2_drpen_in,
+ gt2_drprdy_out => gt2_drprdy_out,
+ gt2_drpwe_in => gt2_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out => gt2_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in => gt2_eyescanreset_in,
+ gt2_rxuserrdy_in => gt2_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out => gt2_eyescandataerror_out,
+ gt2_eyescantrigger_in => gt2_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt2_rxusrclk_in => gt2_rxusrclk_i,
+ gt2_rxusrclk2_in => gt2_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out => gt2_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out => gt2_rxdisperr_out,
+ gt2_rxnotintable_out => gt2_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in => gt2_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in => gt2_gtxrxn_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in => gt2_rxdfelpmreset_in,
+ gt2_rxmonitorout_out => gt2_rxmonitorout_out,
+ gt2_rxmonitorsel_in => gt2_rxmonitorsel_in,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in => gt2_gtrxreset_in,
+ gt2_rxpmareset_in => gt2_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out => gt2_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out => gt2_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in => gt2_gttxreset_in,
+ gt2_txuserrdy_in => gt2_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt2_txusrclk_in => gt2_txusrclk_i,
+ gt2_txusrclk2_in => gt2_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in => gt2_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out => gt2_gtxtxn_out,
+ gt2_gtxtxp_out => gt2_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclk_out => gt2_txoutclk_i,
+ gt2_txoutclkfabric_out => gt2_txoutclkfabric_out,
+ gt2_txoutclkpcs_out => gt2_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in => gt2_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out => gt2_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT3 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out => gt3_cpllfbclklost_out,
+ gt3_cplllock_out => gt3_cplllock_out,
+ gt3_cplllockdetclk_in => sysclk_in_i,
+ gt3_cpllreset_in => gt3_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt3_gtrefclk0_in => tied_to_ground_i,
+ gt3_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in => gt3_drpaddr_in,
+ gt3_drpclk_in => sysclk_in_i,
+ gt3_drpdi_in => gt3_drpdi_in,
+ gt3_drpdo_out => gt3_drpdo_out,
+ gt3_drpen_in => gt3_drpen_in,
+ gt3_drprdy_out => gt3_drprdy_out,
+ gt3_drpwe_in => gt3_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out => gt3_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in => gt3_eyescanreset_in,
+ gt3_rxuserrdy_in => gt3_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out => gt3_eyescandataerror_out,
+ gt3_eyescantrigger_in => gt3_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt3_rxusrclk_in => gt3_rxusrclk_i,
+ gt3_rxusrclk2_in => gt3_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out => gt3_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out => gt3_rxdisperr_out,
+ gt3_rxnotintable_out => gt3_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in => gt3_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in => gt3_gtxrxn_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in => gt3_rxdfelpmreset_in,
+ gt3_rxmonitorout_out => gt3_rxmonitorout_out,
+ gt3_rxmonitorsel_in => gt3_rxmonitorsel_in,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in => gt3_gtrxreset_in,
+ gt3_rxpmareset_in => gt3_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out => gt3_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out => gt3_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in => gt3_gttxreset_in,
+ gt3_txuserrdy_in => gt3_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt3_txusrclk_in => gt3_txusrclk_i,
+ gt3_txusrclk2_in => gt3_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in => gt3_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out => gt3_gtxtxn_out,
+ gt3_gtxtxp_out => gt3_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclk_out => gt3_txoutclk_i,
+ gt3_txoutclkfabric_out => gt3_txoutclkfabric_out,
+ gt3_txoutclkpcs_out => gt3_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in => gt3_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out => gt3_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_quadsoda_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_quadSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_quadSODA_wrapper is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+ GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_DATA_VALID_IN : in std_logic;
+ GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_DATA_VALID_IN : in std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --GT2 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out : out std_logic;
+ gt2_cplllock_out : out std_logic;
+ gt2_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt2_drpdi_in : in std_logic_vector(15 downto 0);
+ gt2_drpdo_out : out std_logic_vector(15 downto 0);
+ gt2_drpen_in : in std_logic;
+ gt2_drprdy_out : out std_logic;
+ gt2_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in : in std_logic;
+ gt2_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out : out std_logic;
+ gt2_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt2_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt2_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in : in std_logic;
+ gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in : in std_logic;
+ gt2_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in : in std_logic;
+ gt2_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out : out std_logic;
+ gt2_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclkfabric_out : out std_logic;
+ gt2_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out : out std_logic;
+
+ --GT3 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out : out std_logic;
+ gt3_cplllock_out : out std_logic;
+ gt3_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt3_drpdi_in : in std_logic_vector(15 downto 0);
+ gt3_drpdo_out : out std_logic_vector(15 downto 0);
+ gt3_drpen_in : in std_logic;
+ gt3_drprdy_out : out std_logic;
+ gt3_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in : in std_logic;
+ gt3_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out : out std_logic;
+ gt3_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt3_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt3_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in : in std_logic;
+ gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in : in std_logic;
+ gt3_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in : in std_logic;
+ gt3_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out : out std_logic;
+ gt3_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclkfabric_out : out std_logic;
+ gt3_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ sysclk_in : in std_logic
+
+);
+
+end GTX_quadSODA_wrapper;
+
+architecture RTL of GTX_quadSODA_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_quadSODA
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+ GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_DATA_VALID_IN : in std_logic;
+ GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_DATA_VALID_IN : in std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cplllockdetclk_in : in std_logic;
+ gt1_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtrefclk0_in : in std_logic;
+ gt1_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpclk_in : in std_logic;
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in : in std_logic;
+ gt1_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt1_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in : in std_logic;
+ gt1_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out : out std_logic;
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --GT2 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out : out std_logic;
+ gt2_cplllock_out : out std_logic;
+ gt2_cplllockdetclk_in : in std_logic;
+ gt2_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt2_gtrefclk0_in : in std_logic;
+ gt2_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt2_drpclk_in : in std_logic;
+ gt2_drpdi_in : in std_logic_vector(15 downto 0);
+ gt2_drpdo_out : out std_logic_vector(15 downto 0);
+ gt2_drpen_in : in std_logic;
+ gt2_drprdy_out : out std_logic;
+ gt2_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in : in std_logic;
+ gt2_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out : out std_logic;
+ gt2_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt2_rxusrclk_in : in std_logic;
+ gt2_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt2_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt2_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in : in std_logic;
+ gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt2_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in : in std_logic;
+ gt2_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in : in std_logic;
+ gt2_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt2_txusrclk_in : in std_logic;
+ gt2_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out : out std_logic;
+ gt2_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclk_out : out std_logic;
+ gt2_txoutclkfabric_out : out std_logic;
+ gt2_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out : out std_logic;
+
+ --GT3 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out : out std_logic;
+ gt3_cplllock_out : out std_logic;
+ gt3_cplllockdetclk_in : in std_logic;
+ gt3_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt3_gtrefclk0_in : in std_logic;
+ gt3_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt3_drpclk_in : in std_logic;
+ gt3_drpdi_in : in std_logic_vector(15 downto 0);
+ gt3_drpdo_out : out std_logic_vector(15 downto 0);
+ gt3_drpen_in : in std_logic;
+ gt3_drprdy_out : out std_logic;
+ gt3_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in : in std_logic;
+ gt3_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out : out std_logic;
+ gt3_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt3_rxusrclk_in : in std_logic;
+ gt3_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt3_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt3_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in : in std_logic;
+ gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt3_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in : in std_logic;
+ gt3_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in : in std_logic;
+ gt3_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt3_txusrclk_in : in std_logic;
+ gt3_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out : out std_logic;
+ gt3_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclk_out : out std_logic;
+ gt3_txoutclkfabric_out : out std_logic;
+ gt3_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_quadSODA_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_quadSODA_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_quadSODA_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_TXOUTCLK_IN : in std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+ GT1_RXOUTCLK_IN : in std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_TXOUTCLK_IN : in std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+ GT2_RXOUTCLK_IN : in std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_TXOUTCLK_IN : in std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+ GT3_RXOUTCLK_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+ signal gt1_txfsmresetdone_i : std_logic;
+signal gt1_rxfsmresetdone_i : std_logic;
+ signal gt1_txfsmresetdone_r : std_logic;
+ signal gt1_txfsmresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r : std_logic;
+signal gt1_rxresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r3 : std_logic;
+
+
+ signal gt2_txfsmresetdone_i : std_logic;
+signal gt2_rxfsmresetdone_i : std_logic;
+ signal gt2_txfsmresetdone_r : std_logic;
+ signal gt2_txfsmresetdone_r2 : std_logic;
+signal gt2_rxresetdone_r : std_logic;
+signal gt2_rxresetdone_r2 : std_logic;
+signal gt2_rxresetdone_r3 : std_logic;
+
+
+ signal gt3_txfsmresetdone_i : std_logic;
+signal gt3_rxfsmresetdone_i : std_logic;
+ signal gt3_txfsmresetdone_r : std_logic;
+ signal gt3_txfsmresetdone_r2 : std_logic;
+signal gt3_rxresetdone_r : std_logic;
+signal gt3_rxresetdone_r2 : std_logic;
+signal gt3_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt1_cpllfbclklost_i : std_logic;
+ signal gt1_cplllock_i : std_logic;
+ signal gt1_cpllrefclklost_i : std_logic;
+ signal gt1_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt1_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt1_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt1_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt1_drpen_i : std_logic;
+ signal gt1_drprdy_i : std_logic;
+ signal gt1_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt1_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt1_eyescanreset_i : std_logic;
+ signal gt1_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt1_eyescandataerror_i : std_logic;
+ signal gt1_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt1_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt1_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt1_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt1_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt1_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt1_rxdlyen_i : std_logic;
+ signal gt1_rxdlysreset_i : std_logic;
+ signal gt1_rxdlysresetdone_i : std_logic;
+ signal gt1_rxphalign_i : std_logic;
+ signal gt1_rxphaligndone_i : std_logic;
+ signal gt1_rxphalignen_i : std_logic;
+ signal gt1_rxphdlyreset_i : std_logic;
+ signal gt1_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt1_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt1_rxlpmhfhold_i : std_logic;
+ signal gt1_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt1_rxdfelpmreset_i : std_logic;
+ signal gt1_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt1_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt1_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt1_gtrxreset_i : std_logic;
+ signal gt1_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt1_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt1_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt1_gttxreset_i : std_logic;
+ signal gt1_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt1_txdlyen_i : std_logic;
+ signal gt1_txdlysreset_i : std_logic;
+ signal gt1_txdlysresetdone_i : std_logic;
+ signal gt1_txphalign_i : std_logic;
+ signal gt1_txphaligndone_i : std_logic;
+ signal gt1_txphalignen_i : std_logic;
+ signal gt1_txphdlyreset_i : std_logic;
+ signal gt1_txphinit_i : std_logic;
+ signal gt1_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt1_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt1_gtxtxn_i : std_logic;
+ signal gt1_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt1_txoutclk_i : std_logic;
+ signal gt1_txoutclkfabric_i : std_logic;
+ signal gt1_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt1_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt1_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT2 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt2_cpllfbclklost_i : std_logic;
+ signal gt2_cplllock_i : std_logic;
+ signal gt2_cpllrefclklost_i : std_logic;
+ signal gt2_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt2_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt2_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt2_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt2_drpen_i : std_logic;
+ signal gt2_drprdy_i : std_logic;
+ signal gt2_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt2_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt2_eyescanreset_i : std_logic;
+ signal gt2_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt2_eyescandataerror_i : std_logic;
+ signal gt2_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt2_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt2_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt2_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt2_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt2_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt2_rxdlyen_i : std_logic;
+ signal gt2_rxdlysreset_i : std_logic;
+ signal gt2_rxdlysresetdone_i : std_logic;
+ signal gt2_rxphalign_i : std_logic;
+ signal gt2_rxphaligndone_i : std_logic;
+ signal gt2_rxphalignen_i : std_logic;
+ signal gt2_rxphdlyreset_i : std_logic;
+ signal gt2_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt2_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt2_rxlpmhfhold_i : std_logic;
+ signal gt2_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt2_rxdfelpmreset_i : std_logic;
+ signal gt2_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt2_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt2_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt2_gtrxreset_i : std_logic;
+ signal gt2_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt2_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt2_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt2_gttxreset_i : std_logic;
+ signal gt2_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt2_txdlyen_i : std_logic;
+ signal gt2_txdlysreset_i : std_logic;
+ signal gt2_txdlysresetdone_i : std_logic;
+ signal gt2_txphalign_i : std_logic;
+ signal gt2_txphaligndone_i : std_logic;
+ signal gt2_txphalignen_i : std_logic;
+ signal gt2_txphdlyreset_i : std_logic;
+ signal gt2_txphinit_i : std_logic;
+ signal gt2_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt2_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt2_gtxtxn_i : std_logic;
+ signal gt2_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt2_txoutclk_i : std_logic;
+ signal gt2_txoutclkfabric_i : std_logic;
+ signal gt2_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt2_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt2_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT3 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt3_cpllfbclklost_i : std_logic;
+ signal gt3_cplllock_i : std_logic;
+ signal gt3_cpllrefclklost_i : std_logic;
+ signal gt3_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt3_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt3_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt3_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt3_drpen_i : std_logic;
+ signal gt3_drprdy_i : std_logic;
+ signal gt3_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt3_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt3_eyescanreset_i : std_logic;
+ signal gt3_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt3_eyescandataerror_i : std_logic;
+ signal gt3_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt3_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt3_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt3_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt3_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt3_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt3_rxdlyen_i : std_logic;
+ signal gt3_rxdlysreset_i : std_logic;
+ signal gt3_rxdlysresetdone_i : std_logic;
+ signal gt3_rxphalign_i : std_logic;
+ signal gt3_rxphaligndone_i : std_logic;
+ signal gt3_rxphalignen_i : std_logic;
+ signal gt3_rxphdlyreset_i : std_logic;
+ signal gt3_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt3_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt3_rxlpmhfhold_i : std_logic;
+ signal gt3_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt3_rxdfelpmreset_i : std_logic;
+ signal gt3_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt3_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt3_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt3_gtrxreset_i : std_logic;
+ signal gt3_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt3_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt3_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt3_gttxreset_i : std_logic;
+ signal gt3_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt3_txdlyen_i : std_logic;
+ signal gt3_txdlysreset_i : std_logic;
+ signal gt3_txdlysresetdone_i : std_logic;
+ signal gt3_txphalign_i : std_logic;
+ signal gt3_txphaligndone_i : std_logic;
+ signal gt3_txphalignen_i : std_logic;
+ signal gt3_txphdlyreset_i : std_logic;
+ signal gt3_txphinit_i : std_logic;
+ signal gt3_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt3_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt3_gtxtxn_i : std_logic;
+ signal gt3_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt3_txoutclk_i : std_logic;
+ signal gt3_txoutclkfabric_i : std_logic;
+ signal gt3_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt3_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt3_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal gt1_tx_system_reset_c : std_logic;
+ signal gt1_rx_system_reset_c : std_logic;
+ signal gt2_tx_system_reset_c : std_logic;
+ signal gt2_rx_system_reset_c : std_logic;
+ signal gt3_tx_system_reset_c : std_logic;
+ signal gt3_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt1_txusrclk_i : std_logic;
+ signal gt1_txusrclk2_i : std_logic;
+ signal gt1_rxusrclk_i : std_logic;
+ signal gt1_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt2_txusrclk_i : std_logic;
+ signal gt2_txusrclk2_i : std_logic;
+ signal gt2_rxusrclk_i : std_logic;
+ signal gt2_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt3_txusrclk_i : std_logic;
+ signal gt3_txusrclk2_i : std_logic;
+ signal gt3_rxusrclk_i : std_logic;
+ signal gt3_rxusrclk2_i : std_logic;
+
+
+
+
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q2_clk1_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+ gt0_qplloutclk_out <= gt0_qplloutclk_i;
+ gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+ GT1_TXUSRCLK_OUT <= gt1_txusrclk_i;
+ GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+ GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+ GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+
+ GT2_TXUSRCLK_OUT <= gt2_txusrclk_i;
+ GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
+ GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
+ GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
+
+ GT3_TXUSRCLK_OUT <= gt3_txusrclk_i;
+ GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
+ GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
+ GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
+
+
+
+
+
+
+
+
+
+
+ gt_usrclk_source : GTX_quadSODA_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
+
+ GT1_TXUSRCLK_OUT => gt1_txusrclk_i,
+ GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
+ GT1_TXOUTCLK_IN => gt1_txoutclk_i,
+ GT1_RXUSRCLK_OUT => gt1_rxusrclk_i,
+ GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
+ GT1_RXOUTCLK_IN => gt1_rxoutclk_i,
+
+ GT2_TXUSRCLK_OUT => gt2_txusrclk_i,
+ GT2_TXUSRCLK2_OUT => gt2_txusrclk2_i,
+ GT2_TXOUTCLK_IN => gt2_txoutclk_i,
+ GT2_RXUSRCLK_OUT => gt2_rxusrclk_i,
+ GT2_RXUSRCLK2_OUT => gt2_rxusrclk2_i,
+ GT2_RXOUTCLK_IN => gt2_rxoutclk_i,
+
+ GT3_TXUSRCLK_OUT => gt3_txusrclk_i,
+ GT3_TXUSRCLK2_OUT => gt3_txusrclk2_i,
+ GT3_TXOUTCLK_IN => gt3_txoutclk_i,
+ GT3_RXUSRCLK_OUT => gt3_rxusrclk_i,
+ GT3_RXUSRCLK2_OUT => gt3_rxusrclk2_i,
+ GT3_RXOUTCLK_IN => gt3_rxoutclk_i,
+ Q2_CLK1_GTREFCLK_PAD_N_IN => Q2_CLK1_GTREFCLK_PAD_N_IN,
+ Q2_CLK1_GTREFCLK_PAD_P_IN => Q2_CLK1_GTREFCLK_PAD_P_IN,
+ Q2_CLK1_GTREFCLK_OUT => q2_clk1_refclk_i
+
+ );
+
+sysclk_in_i <= sysclk_in;
+
+ common0_i:GTX_quadSODA_common
+ generic map
+ (
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => "001"
+ )
+ port map
+ (
+ QPLLREFCLKSEL_IN => "001",
+ GTREFCLK0_IN => tied_to_ground_i,
+ GTREFCLK1_IN => q2_clk1_refclk_i,
+ QPLLLOCK_OUT => gt0_qplllock_i,
+ QPLLLOCKDETCLK_IN => sysclk_in_i,
+ QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+ common_reset_i:GTX_quadSODA_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ GTX_quadSODA_init_i : GTX_quadSODA
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+ gt1_tx_fsm_reset_done_out => gt1_tx_fsm_reset_done_out,
+ gt1_rx_fsm_reset_done_out => gt1_rx_fsm_reset_done_out,
+ gt1_data_valid_in => gt1_data_valid_in,
+ gt2_tx_fsm_reset_done_out => gt2_tx_fsm_reset_done_out,
+ gt2_rx_fsm_reset_done_out => gt2_rx_fsm_reset_done_out,
+ gt2_data_valid_in => gt2_data_valid_in,
+ gt3_tx_fsm_reset_done_out => gt3_tx_fsm_reset_done_out,
+ gt3_rx_fsm_reset_done_out => gt3_rx_fsm_reset_done_out,
+ gt3_data_valid_in => gt3_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => tied_to_ground_i,
+ gt0_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out => gt1_cpllfbclklost_out,
+ gt1_cplllock_out => gt1_cplllock_out,
+ gt1_cplllockdetclk_in => sysclk_in_i,
+ gt1_cpllreset_in => gt1_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtrefclk0_in => tied_to_ground_i,
+ gt1_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in => gt1_drpaddr_in,
+ gt1_drpclk_in => sysclk_in_i,
+ gt1_drpdi_in => gt1_drpdi_in,
+ gt1_drpdo_out => gt1_drpdo_out,
+ gt1_drpen_in => gt1_drpen_in,
+ gt1_drprdy_out => gt1_drprdy_out,
+ gt1_drpwe_in => gt1_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out => gt1_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in => gt1_eyescanreset_in,
+ gt1_rxuserrdy_in => gt1_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out => gt1_eyescandataerror_out,
+ gt1_eyescantrigger_in => gt1_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in => gt1_rxusrclk_i,
+ gt1_rxusrclk2_in => gt1_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out => gt1_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out => gt1_rxdisperr_out,
+ gt1_rxnotintable_out => gt1_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in => gt1_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in => gt1_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out => gt1_rxphmonitor_out,
+ gt1_rxphslipmonitor_out => gt1_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in,
+ gt1_rxmonitorout_out => gt1_rxmonitorout_out,
+ gt1_rxmonitorsel_in => gt1_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt1_rxoutclk_out => gt1_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in => gt1_gtrxreset_in,
+ gt1_rxpmareset_in => gt1_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out => gt1_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out => gt1_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in => gt1_gttxreset_in,
+ gt1_txuserrdy_in => gt1_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in => gt1_txusrclk_i,
+ gt1_txusrclk2_in => gt1_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in => gt1_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out => gt1_gtxtxn_out,
+ gt1_gtxtxp_out => gt1_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out => gt1_txoutclk_i,
+ gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
+ gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in => gt1_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out => gt1_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT2 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out => gt2_cpllfbclklost_out,
+ gt2_cplllock_out => gt2_cplllock_out,
+ gt2_cplllockdetclk_in => sysclk_in_i,
+ gt2_cpllreset_in => gt2_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt2_gtrefclk0_in => tied_to_ground_i,
+ gt2_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in => gt2_drpaddr_in,
+ gt2_drpclk_in => sysclk_in_i,
+ gt2_drpdi_in => gt2_drpdi_in,
+ gt2_drpdo_out => gt2_drpdo_out,
+ gt2_drpen_in => gt2_drpen_in,
+ gt2_drprdy_out => gt2_drprdy_out,
+ gt2_drpwe_in => gt2_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out => gt2_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in => gt2_eyescanreset_in,
+ gt2_rxuserrdy_in => gt2_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out => gt2_eyescandataerror_out,
+ gt2_eyescantrigger_in => gt2_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt2_rxusrclk_in => gt2_rxusrclk_i,
+ gt2_rxusrclk2_in => gt2_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out => gt2_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out => gt2_rxdisperr_out,
+ gt2_rxnotintable_out => gt2_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in => gt2_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in => gt2_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt2_rxphmonitor_out => gt2_rxphmonitor_out,
+ gt2_rxphslipmonitor_out => gt2_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in => gt2_rxdfelpmreset_in,
+ gt2_rxmonitorout_out => gt2_rxmonitorout_out,
+ gt2_rxmonitorsel_in => gt2_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt2_rxoutclk_out => gt2_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in => gt2_gtrxreset_in,
+ gt2_rxpmareset_in => gt2_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out => gt2_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out => gt2_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in => gt2_gttxreset_in,
+ gt2_txuserrdy_in => gt2_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt2_txusrclk_in => gt2_txusrclk_i,
+ gt2_txusrclk2_in => gt2_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in => gt2_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out => gt2_gtxtxn_out,
+ gt2_gtxtxp_out => gt2_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclk_out => gt2_txoutclk_i,
+ gt2_txoutclkfabric_out => gt2_txoutclkfabric_out,
+ gt2_txoutclkpcs_out => gt2_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in => gt2_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out => gt2_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT3 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out => gt3_cpllfbclklost_out,
+ gt3_cplllock_out => gt3_cplllock_out,
+ gt3_cplllockdetclk_in => sysclk_in_i,
+ gt3_cpllreset_in => gt3_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt3_gtrefclk0_in => tied_to_ground_i,
+ gt3_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in => gt3_drpaddr_in,
+ gt3_drpclk_in => sysclk_in_i,
+ gt3_drpdi_in => gt3_drpdi_in,
+ gt3_drpdo_out => gt3_drpdo_out,
+ gt3_drpen_in => gt3_drpen_in,
+ gt3_drprdy_out => gt3_drprdy_out,
+ gt3_drpwe_in => gt3_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out => gt3_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in => gt3_eyescanreset_in,
+ gt3_rxuserrdy_in => gt3_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out => gt3_eyescandataerror_out,
+ gt3_eyescantrigger_in => gt3_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt3_rxusrclk_in => gt3_rxusrclk_i,
+ gt3_rxusrclk2_in => gt3_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out => gt3_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out => gt3_rxdisperr_out,
+ gt3_rxnotintable_out => gt3_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in => gt3_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in => gt3_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt3_rxphmonitor_out => gt3_rxphmonitor_out,
+ gt3_rxphslipmonitor_out => gt3_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in => gt3_rxdfelpmreset_in,
+ gt3_rxmonitorout_out => gt3_rxmonitorout_out,
+ gt3_rxmonitorsel_in => gt3_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt3_rxoutclk_out => gt3_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in => gt3_gtrxreset_in,
+ gt3_rxpmareset_in => gt3_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out => gt3_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out => gt3_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in => gt3_gttxreset_in,
+ gt3_txuserrdy_in => gt3_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt3_txusrclk_in => gt3_txusrclk_i,
+ gt3_txusrclk2_in => gt3_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in => gt3_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out => gt3_gtxtxn_out,
+ gt3_gtxtxp_out => gt3_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclk_out => gt3_txoutclk_i,
+ gt3_txoutclkfabric_out => gt3_txoutclkfabric_out,
+ gt3_txoutclkpcs_out => gt3_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in => gt3_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out => gt3_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
--- /dev/null
+---------------------------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_quadsoda_common.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_quadSODA_common
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_quadSODA_common is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
+ SIM_QPLLREFCLK_SEL : bit_vector := "001"
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK1_IN : in std_logic;
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+);
+
+end GTX_quadSODA_common;
+
+architecture RTL of GTX_quadSODA_common is
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_quadSODA_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_TOP : integer := 80;
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
+
+begin
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+
+ gtxe2_common_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
+ SIM_VERSION => "4.0",
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (3)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GTREFCLK0_IN,
+ GTREFCLK1 => GTREFCLK1_IN,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports -----------------------
+ QPLLDMONITOR => open,
+ ----------------------- Common Block - Clocking Ports ----------------------
+ QPLLOUTCLK => QPLLOUTCLK_OUT,
+ QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
+ REFCLKOUTMONITOR => open,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => QPLLLOCK_OUT,
+ QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_vcc_i,
+ QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
+ QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
+ QPLLRESET => QPLLRESET_IN,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ --------------------------------- QPLL Ports -------------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "11111",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+end RTL;
--- /dev/null
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_quadsoda_common_reset.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module GTX_quadSODA_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_quadSODA_common_reset is
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic:= '0' --Reset QPLL
+ );
+end GTX_quadSODA_common_reset;
+
+architecture RTL of GTX_quadSODA_common_reset is
+
+
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+
+ signal init_wait_count : std_logic_vector(7 downto 0) :=(others => '0');
+ signal init_wait_done : std_logic :='0';
+ signal common_reset_asserted : std_logic :='0';
+ signal common_reset_i : std_logic ;
+
+ type rst_type is(
+ INIT, ASSERT_COMMON_RESET);
+
+ signal state : rst_type := INIT;
+
+begin
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ state <= INIT;
+ common_reset_asserted <= '0';
+ COMMON_RESET <= '0';
+ else
+
+ case state is
+ when INIT =>
+ if init_wait_done = '1' then
+ state <= ASSERT_COMMON_RESET;
+ end if;
+
+ when ASSERT_COMMON_RESET =>
+ if common_reset_asserted = '0' then
+ COMMON_RESET <= '1';
+ common_reset_asserted <= '1';
+ else
+ COMMON_RESET <= '0';
+ end if;
+ when OTHERS =>
+ state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_quadsoda_gt_usrclk_source.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_quadSODA_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_quadSODA_GT_USRCLK_SOURCE is
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_TXOUTCLK_IN : in std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+ GT1_RXOUTCLK_IN : in std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_TXOUTCLK_IN : in std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+ GT2_RXOUTCLK_IN : in std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_TXOUTCLK_IN : in std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+ GT3_RXOUTCLK_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_OUT : out std_logic
+);
+
+
+end GTX_quadSODA_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_quadSODA_GT_USRCLK_SOURCE is
+
+component GTX_QUADSODA_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+
+ signal gt1_txoutclk_i : std_logic;
+ signal gt1_rxoutclk_i : std_logic;
+
+ signal gt2_txoutclk_i : std_logic;
+ signal gt2_rxoutclk_i : std_logic;
+
+ signal gt3_txoutclk_i : std_logic;
+ signal gt3_rxoutclk_i : std_logic;
+
+ attribute syn_noclockbuf : boolean;
+ signal q2_clk1_gtrefclk : std_logic;
+ attribute syn_noclockbuf of q2_clk1_gtrefclk : signal is true;
+
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+ gt0_txoutclk_i <= GT0_TXOUTCLK_IN;
+ gt0_rxoutclk_i <= GT0_RXOUTCLK_IN;
+ gt1_txoutclk_i <= GT1_TXOUTCLK_IN;
+ gt1_rxoutclk_i <= GT1_RXOUTCLK_IN;
+ gt2_txoutclk_i <= GT2_TXOUTCLK_IN;
+ gt2_rxoutclk_i <= GT2_RXOUTCLK_IN;
+ gt3_txoutclk_i <= GT3_TXOUTCLK_IN;
+ gt3_rxoutclk_i <= GT3_RXOUTCLK_IN;
+
+ Q2_CLK1_GTREFCLK_OUT <= q2_clk1_gtrefclk;
+
+ --IBUFDS_GTE2
+ ibufds_instq2_clk1 : IBUFDS_GTE2
+ port map
+ (
+ O => q2_clk1_gtrefclk,
+ ODIV2 => open,
+ CEB => tied_to_ground_i,
+ I => Q2_CLK1_GTREFCLK_PAD_P_IN,
+ IB => Q2_CLK1_GTREFCLK_PAD_N_IN
+ );
+
+
+
+ -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+ -- for improved jitter performance, and to avoid consuming an additional BUFG
+ txoutclk_bufg0_i : BUFG
+ port map
+ (
+ I => gt0_txoutclk_i,
+ O => gt0_txusrclk_i
+ );
+
+
+ rxoutclk_bufg1_i : BUFG
+ port map
+ (
+ I => gt0_rxoutclk_i,
+ O => gt0_rxusrclk_i
+ );
+
+
+
+
+GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+
+GT1_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT1_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT1_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT1_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+
+GT2_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT2_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT2_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT2_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+
+GT3_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT3_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT3_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT3_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_quadsoda_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_quadSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_quadSODA_support is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+ GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_DATA_VALID_IN : in std_logic;
+ GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_DATA_VALID_IN : in std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --GT2 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out : out std_logic;
+ gt2_cplllock_out : out std_logic;
+ gt2_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt2_drpdi_in : in std_logic_vector(15 downto 0);
+ gt2_drpdo_out : out std_logic_vector(15 downto 0);
+ gt2_drpen_in : in std_logic;
+ gt2_drprdy_out : out std_logic;
+ gt2_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in : in std_logic;
+ gt2_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out : out std_logic;
+ gt2_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt2_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt2_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in : in std_logic;
+ gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in : in std_logic;
+ gt2_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in : in std_logic;
+ gt2_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out : out std_logic;
+ gt2_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclkfabric_out : out std_logic;
+ gt2_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out : out std_logic;
+
+ --GT3 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out : out std_logic;
+ gt3_cplllock_out : out std_logic;
+ gt3_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt3_drpdi_in : in std_logic_vector(15 downto 0);
+ gt3_drpdo_out : out std_logic_vector(15 downto 0);
+ gt3_drpen_in : in std_logic;
+ gt3_drprdy_out : out std_logic;
+ gt3_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in : in std_logic;
+ gt3_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out : out std_logic;
+ gt3_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt3_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt3_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in : in std_logic;
+ gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in : in std_logic;
+ gt3_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in : in std_logic;
+ gt3_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out : out std_logic;
+ gt3_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclkfabric_out : out std_logic;
+ gt3_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ sysclk_in : in std_logic
+
+);
+
+end GTX_quadSODA_support;
+
+architecture RTL of GTX_quadSODA_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_quadSODA
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+ GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_DATA_VALID_IN : in std_logic;
+ GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_DATA_VALID_IN : in std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cplllockdetclk_in : in std_logic;
+ gt1_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtrefclk0_in : in std_logic;
+ gt1_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpclk_in : in std_logic;
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in : in std_logic;
+ gt1_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt1_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in : in std_logic;
+ gt1_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out : out std_logic;
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --GT2 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out : out std_logic;
+ gt2_cplllock_out : out std_logic;
+ gt2_cplllockdetclk_in : in std_logic;
+ gt2_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt2_gtrefclk0_in : in std_logic;
+ gt2_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt2_drpclk_in : in std_logic;
+ gt2_drpdi_in : in std_logic_vector(15 downto 0);
+ gt2_drpdo_out : out std_logic_vector(15 downto 0);
+ gt2_drpen_in : in std_logic;
+ gt2_drprdy_out : out std_logic;
+ gt2_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in : in std_logic;
+ gt2_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out : out std_logic;
+ gt2_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt2_rxusrclk_in : in std_logic;
+ gt2_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt2_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt2_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in : in std_logic;
+ gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt2_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in : in std_logic;
+ gt2_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in : in std_logic;
+ gt2_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt2_txusrclk_in : in std_logic;
+ gt2_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out : out std_logic;
+ gt2_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclk_out : out std_logic;
+ gt2_txoutclkfabric_out : out std_logic;
+ gt2_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out : out std_logic;
+
+ --GT3 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out : out std_logic;
+ gt3_cplllock_out : out std_logic;
+ gt3_cplllockdetclk_in : in std_logic;
+ gt3_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt3_gtrefclk0_in : in std_logic;
+ gt3_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt3_drpclk_in : in std_logic;
+ gt3_drpdi_in : in std_logic_vector(15 downto 0);
+ gt3_drpdo_out : out std_logic_vector(15 downto 0);
+ gt3_drpen_in : in std_logic;
+ gt3_drprdy_out : out std_logic;
+ gt3_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in : in std_logic;
+ gt3_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out : out std_logic;
+ gt3_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt3_rxusrclk_in : in std_logic;
+ gt3_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt3_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt3_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in : in std_logic;
+ gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt3_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in : in std_logic;
+ gt3_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in : in std_logic;
+ gt3_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt3_txusrclk_in : in std_logic;
+ gt3_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out : out std_logic;
+ gt3_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclk_out : out std_logic;
+ gt3_txoutclkfabric_out : out std_logic;
+ gt3_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_quadSODA_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_quadSODA_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_quadSODA_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_TXOUTCLK_IN : in std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+ GT1_RXOUTCLK_IN : in std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_TXOUTCLK_IN : in std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+ GT2_RXOUTCLK_IN : in std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_TXOUTCLK_IN : in std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+ GT3_RXOUTCLK_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+ signal gt1_txfsmresetdone_i : std_logic;
+signal gt1_rxfsmresetdone_i : std_logic;
+ signal gt1_txfsmresetdone_r : std_logic;
+ signal gt1_txfsmresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r : std_logic;
+signal gt1_rxresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r3 : std_logic;
+
+
+ signal gt2_txfsmresetdone_i : std_logic;
+signal gt2_rxfsmresetdone_i : std_logic;
+ signal gt2_txfsmresetdone_r : std_logic;
+ signal gt2_txfsmresetdone_r2 : std_logic;
+signal gt2_rxresetdone_r : std_logic;
+signal gt2_rxresetdone_r2 : std_logic;
+signal gt2_rxresetdone_r3 : std_logic;
+
+
+ signal gt3_txfsmresetdone_i : std_logic;
+signal gt3_rxfsmresetdone_i : std_logic;
+ signal gt3_txfsmresetdone_r : std_logic;
+ signal gt3_txfsmresetdone_r2 : std_logic;
+signal gt3_rxresetdone_r : std_logic;
+signal gt3_rxresetdone_r2 : std_logic;
+signal gt3_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt1_cpllfbclklost_i : std_logic;
+ signal gt1_cplllock_i : std_logic;
+ signal gt1_cpllrefclklost_i : std_logic;
+ signal gt1_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt1_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt1_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt1_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt1_drpen_i : std_logic;
+ signal gt1_drprdy_i : std_logic;
+ signal gt1_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt1_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt1_eyescanreset_i : std_logic;
+ signal gt1_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt1_eyescandataerror_i : std_logic;
+ signal gt1_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt1_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt1_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt1_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt1_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt1_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt1_rxdlyen_i : std_logic;
+ signal gt1_rxdlysreset_i : std_logic;
+ signal gt1_rxdlysresetdone_i : std_logic;
+ signal gt1_rxphalign_i : std_logic;
+ signal gt1_rxphaligndone_i : std_logic;
+ signal gt1_rxphalignen_i : std_logic;
+ signal gt1_rxphdlyreset_i : std_logic;
+ signal gt1_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt1_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt1_rxlpmhfhold_i : std_logic;
+ signal gt1_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt1_rxdfelpmreset_i : std_logic;
+ signal gt1_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt1_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt1_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt1_gtrxreset_i : std_logic;
+ signal gt1_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt1_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt1_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt1_gttxreset_i : std_logic;
+ signal gt1_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt1_txdlyen_i : std_logic;
+ signal gt1_txdlysreset_i : std_logic;
+ signal gt1_txdlysresetdone_i : std_logic;
+ signal gt1_txphalign_i : std_logic;
+ signal gt1_txphaligndone_i : std_logic;
+ signal gt1_txphalignen_i : std_logic;
+ signal gt1_txphdlyreset_i : std_logic;
+ signal gt1_txphinit_i : std_logic;
+ signal gt1_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt1_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt1_gtxtxn_i : std_logic;
+ signal gt1_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt1_txoutclk_i : std_logic;
+ signal gt1_txoutclkfabric_i : std_logic;
+ signal gt1_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt1_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt1_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT2 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt2_cpllfbclklost_i : std_logic;
+ signal gt2_cplllock_i : std_logic;
+ signal gt2_cpllrefclklost_i : std_logic;
+ signal gt2_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt2_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt2_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt2_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt2_drpen_i : std_logic;
+ signal gt2_drprdy_i : std_logic;
+ signal gt2_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt2_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt2_eyescanreset_i : std_logic;
+ signal gt2_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt2_eyescandataerror_i : std_logic;
+ signal gt2_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt2_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt2_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt2_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt2_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt2_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt2_rxdlyen_i : std_logic;
+ signal gt2_rxdlysreset_i : std_logic;
+ signal gt2_rxdlysresetdone_i : std_logic;
+ signal gt2_rxphalign_i : std_logic;
+ signal gt2_rxphaligndone_i : std_logic;
+ signal gt2_rxphalignen_i : std_logic;
+ signal gt2_rxphdlyreset_i : std_logic;
+ signal gt2_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt2_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt2_rxlpmhfhold_i : std_logic;
+ signal gt2_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt2_rxdfelpmreset_i : std_logic;
+ signal gt2_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt2_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt2_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt2_gtrxreset_i : std_logic;
+ signal gt2_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt2_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt2_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt2_gttxreset_i : std_logic;
+ signal gt2_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt2_txdlyen_i : std_logic;
+ signal gt2_txdlysreset_i : std_logic;
+ signal gt2_txdlysresetdone_i : std_logic;
+ signal gt2_txphalign_i : std_logic;
+ signal gt2_txphaligndone_i : std_logic;
+ signal gt2_txphalignen_i : std_logic;
+ signal gt2_txphdlyreset_i : std_logic;
+ signal gt2_txphinit_i : std_logic;
+ signal gt2_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt2_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt2_gtxtxn_i : std_logic;
+ signal gt2_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt2_txoutclk_i : std_logic;
+ signal gt2_txoutclkfabric_i : std_logic;
+ signal gt2_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt2_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt2_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT3 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt3_cpllfbclklost_i : std_logic;
+ signal gt3_cplllock_i : std_logic;
+ signal gt3_cpllrefclklost_i : std_logic;
+ signal gt3_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt3_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt3_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt3_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt3_drpen_i : std_logic;
+ signal gt3_drprdy_i : std_logic;
+ signal gt3_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt3_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt3_eyescanreset_i : std_logic;
+ signal gt3_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt3_eyescandataerror_i : std_logic;
+ signal gt3_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt3_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt3_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt3_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt3_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt3_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt3_rxdlyen_i : std_logic;
+ signal gt3_rxdlysreset_i : std_logic;
+ signal gt3_rxdlysresetdone_i : std_logic;
+ signal gt3_rxphalign_i : std_logic;
+ signal gt3_rxphaligndone_i : std_logic;
+ signal gt3_rxphalignen_i : std_logic;
+ signal gt3_rxphdlyreset_i : std_logic;
+ signal gt3_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt3_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt3_rxlpmhfhold_i : std_logic;
+ signal gt3_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt3_rxdfelpmreset_i : std_logic;
+ signal gt3_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt3_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt3_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt3_gtrxreset_i : std_logic;
+ signal gt3_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt3_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt3_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt3_gttxreset_i : std_logic;
+ signal gt3_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt3_txdlyen_i : std_logic;
+ signal gt3_txdlysreset_i : std_logic;
+ signal gt3_txdlysresetdone_i : std_logic;
+ signal gt3_txphalign_i : std_logic;
+ signal gt3_txphaligndone_i : std_logic;
+ signal gt3_txphalignen_i : std_logic;
+ signal gt3_txphdlyreset_i : std_logic;
+ signal gt3_txphinit_i : std_logic;
+ signal gt3_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt3_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt3_gtxtxn_i : std_logic;
+ signal gt3_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt3_txoutclk_i : std_logic;
+ signal gt3_txoutclkfabric_i : std_logic;
+ signal gt3_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt3_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt3_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal gt1_tx_system_reset_c : std_logic;
+ signal gt1_rx_system_reset_c : std_logic;
+ signal gt2_tx_system_reset_c : std_logic;
+ signal gt2_rx_system_reset_c : std_logic;
+ signal gt3_tx_system_reset_c : std_logic;
+ signal gt3_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt1_txusrclk_i : std_logic;
+ signal gt1_txusrclk2_i : std_logic;
+ signal gt1_rxusrclk_i : std_logic;
+ signal gt1_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt2_txusrclk_i : std_logic;
+ signal gt2_txusrclk2_i : std_logic;
+ signal gt2_rxusrclk_i : std_logic;
+ signal gt2_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt3_txusrclk_i : std_logic;
+ signal gt3_txusrclk2_i : std_logic;
+ signal gt3_rxusrclk_i : std_logic;
+ signal gt3_rxusrclk2_i : std_logic;
+
+
+
+
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q2_clk1_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+ gt0_qplloutclk_out <= gt0_qplloutclk_i;
+ gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+ GT1_TXUSRCLK_OUT <= gt1_txusrclk_i;
+ GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+ GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+ GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+
+ GT2_TXUSRCLK_OUT <= gt2_txusrclk_i;
+ GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
+ GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
+ GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
+
+ GT3_TXUSRCLK_OUT <= gt3_txusrclk_i;
+ GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
+ GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
+ GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
+
+
+
+
+
+
+
+
+
+
+ gt_usrclk_source : GTX_quadSODA_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
+
+ GT1_TXUSRCLK_OUT => gt1_txusrclk_i,
+ GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
+ GT1_TXOUTCLK_IN => gt1_txoutclk_i,
+ GT1_RXUSRCLK_OUT => gt1_rxusrclk_i,
+ GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
+ GT1_RXOUTCLK_IN => gt1_rxoutclk_i,
+
+ GT2_TXUSRCLK_OUT => gt2_txusrclk_i,
+ GT2_TXUSRCLK2_OUT => gt2_txusrclk2_i,
+ GT2_TXOUTCLK_IN => gt2_txoutclk_i,
+ GT2_RXUSRCLK_OUT => gt2_rxusrclk_i,
+ GT2_RXUSRCLK2_OUT => gt2_rxusrclk2_i,
+ GT2_RXOUTCLK_IN => gt2_rxoutclk_i,
+
+ GT3_TXUSRCLK_OUT => gt3_txusrclk_i,
+ GT3_TXUSRCLK2_OUT => gt3_txusrclk2_i,
+ GT3_TXOUTCLK_IN => gt3_txoutclk_i,
+ GT3_RXUSRCLK_OUT => gt3_rxusrclk_i,
+ GT3_RXUSRCLK2_OUT => gt3_rxusrclk2_i,
+ GT3_RXOUTCLK_IN => gt3_rxoutclk_i,
+ Q2_CLK1_GTREFCLK_PAD_N_IN => Q2_CLK1_GTREFCLK_PAD_N_IN,
+ Q2_CLK1_GTREFCLK_PAD_P_IN => Q2_CLK1_GTREFCLK_PAD_P_IN,
+ Q2_CLK1_GTREFCLK_OUT => q2_clk1_refclk_i
+
+ );
+
+sysclk_in_i <= sysclk_in;
+
+ common0_i:GTX_quadSODA_common
+ generic map
+ (
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => "001"
+ )
+ port map
+ (
+ QPLLREFCLKSEL_IN => "001",
+ GTREFCLK0_IN => tied_to_ground_i,
+ GTREFCLK1_IN => q2_clk1_refclk_i,
+ QPLLLOCK_OUT => gt0_qplllock_i,
+ QPLLLOCKDETCLK_IN => sysclk_in_i,
+ QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+ common_reset_i:GTX_quadSODA_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ GTX_quadSODA_init_i : GTX_quadSODA
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+ gt1_tx_fsm_reset_done_out => gt1_tx_fsm_reset_done_out,
+ gt1_rx_fsm_reset_done_out => gt1_rx_fsm_reset_done_out,
+ gt1_data_valid_in => gt1_data_valid_in,
+ gt2_tx_fsm_reset_done_out => gt2_tx_fsm_reset_done_out,
+ gt2_rx_fsm_reset_done_out => gt2_rx_fsm_reset_done_out,
+ gt2_data_valid_in => gt2_data_valid_in,
+ gt3_tx_fsm_reset_done_out => gt3_tx_fsm_reset_done_out,
+ gt3_rx_fsm_reset_done_out => gt3_rx_fsm_reset_done_out,
+ gt3_data_valid_in => gt3_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => tied_to_ground_i,
+ gt0_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out => gt1_cpllfbclklost_out,
+ gt1_cplllock_out => gt1_cplllock_out,
+ gt1_cplllockdetclk_in => sysclk_in_i,
+ gt1_cpllreset_in => gt1_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtrefclk0_in => tied_to_ground_i,
+ gt1_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in => gt1_drpaddr_in,
+ gt1_drpclk_in => sysclk_in_i,
+ gt1_drpdi_in => gt1_drpdi_in,
+ gt1_drpdo_out => gt1_drpdo_out,
+ gt1_drpen_in => gt1_drpen_in,
+ gt1_drprdy_out => gt1_drprdy_out,
+ gt1_drpwe_in => gt1_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out => gt1_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in => gt1_eyescanreset_in,
+ gt1_rxuserrdy_in => gt1_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out => gt1_eyescandataerror_out,
+ gt1_eyescantrigger_in => gt1_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in => gt1_rxusrclk_i,
+ gt1_rxusrclk2_in => gt1_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out => gt1_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out => gt1_rxdisperr_out,
+ gt1_rxnotintable_out => gt1_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in => gt1_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in => gt1_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out => gt1_rxphmonitor_out,
+ gt1_rxphslipmonitor_out => gt1_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in,
+ gt1_rxmonitorout_out => gt1_rxmonitorout_out,
+ gt1_rxmonitorsel_in => gt1_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt1_rxoutclk_out => gt1_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in => gt1_gtrxreset_in,
+ gt1_rxpmareset_in => gt1_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out => gt1_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out => gt1_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in => gt1_gttxreset_in,
+ gt1_txuserrdy_in => gt1_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in => gt1_txusrclk_i,
+ gt1_txusrclk2_in => gt1_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in => gt1_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out => gt1_gtxtxn_out,
+ gt1_gtxtxp_out => gt1_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out => gt1_txoutclk_i,
+ gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
+ gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in => gt1_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out => gt1_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT2 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out => gt2_cpllfbclklost_out,
+ gt2_cplllock_out => gt2_cplllock_out,
+ gt2_cplllockdetclk_in => sysclk_in_i,
+ gt2_cpllreset_in => gt2_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt2_gtrefclk0_in => tied_to_ground_i,
+ gt2_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in => gt2_drpaddr_in,
+ gt2_drpclk_in => sysclk_in_i,
+ gt2_drpdi_in => gt2_drpdi_in,
+ gt2_drpdo_out => gt2_drpdo_out,
+ gt2_drpen_in => gt2_drpen_in,
+ gt2_drprdy_out => gt2_drprdy_out,
+ gt2_drpwe_in => gt2_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out => gt2_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in => gt2_eyescanreset_in,
+ gt2_rxuserrdy_in => gt2_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out => gt2_eyescandataerror_out,
+ gt2_eyescantrigger_in => gt2_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt2_rxusrclk_in => gt2_rxusrclk_i,
+ gt2_rxusrclk2_in => gt2_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out => gt2_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out => gt2_rxdisperr_out,
+ gt2_rxnotintable_out => gt2_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in => gt2_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in => gt2_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt2_rxphmonitor_out => gt2_rxphmonitor_out,
+ gt2_rxphslipmonitor_out => gt2_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in => gt2_rxdfelpmreset_in,
+ gt2_rxmonitorout_out => gt2_rxmonitorout_out,
+ gt2_rxmonitorsel_in => gt2_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt2_rxoutclk_out => gt2_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in => gt2_gtrxreset_in,
+ gt2_rxpmareset_in => gt2_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out => gt2_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out => gt2_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in => gt2_gttxreset_in,
+ gt2_txuserrdy_in => gt2_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt2_txusrclk_in => gt2_txusrclk_i,
+ gt2_txusrclk2_in => gt2_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in => gt2_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out => gt2_gtxtxn_out,
+ gt2_gtxtxp_out => gt2_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclk_out => gt2_txoutclk_i,
+ gt2_txoutclkfabric_out => gt2_txoutclkfabric_out,
+ gt2_txoutclkpcs_out => gt2_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in => gt2_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out => gt2_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT3 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out => gt3_cpllfbclklost_out,
+ gt3_cplllock_out => gt3_cplllock_out,
+ gt3_cplllockdetclk_in => sysclk_in_i,
+ gt3_cpllreset_in => gt3_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt3_gtrefclk0_in => tied_to_ground_i,
+ gt3_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in => gt3_drpaddr_in,
+ gt3_drpclk_in => sysclk_in_i,
+ gt3_drpdi_in => gt3_drpdi_in,
+ gt3_drpdo_out => gt3_drpdo_out,
+ gt3_drpen_in => gt3_drpen_in,
+ gt3_drprdy_out => gt3_drprdy_out,
+ gt3_drpwe_in => gt3_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out => gt3_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in => gt3_eyescanreset_in,
+ gt3_rxuserrdy_in => gt3_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out => gt3_eyescandataerror_out,
+ gt3_eyescantrigger_in => gt3_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt3_rxusrclk_in => gt3_rxusrclk_i,
+ gt3_rxusrclk2_in => gt3_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out => gt3_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out => gt3_rxdisperr_out,
+ gt3_rxnotintable_out => gt3_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in => gt3_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in => gt3_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt3_rxphmonitor_out => gt3_rxphmonitor_out,
+ gt3_rxphslipmonitor_out => gt3_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in => gt3_rxdfelpmreset_in,
+ gt3_rxmonitorout_out => gt3_rxmonitorout_out,
+ gt3_rxmonitorsel_in => gt3_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt3_rxoutclk_out => gt3_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in => gt3_gtrxreset_in,
+ gt3_rxpmareset_in => gt3_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out => gt3_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out => gt3_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in => gt3_gttxreset_in,
+ gt3_txuserrdy_in => gt3_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt3_txusrclk_in => gt3_txusrclk_i,
+ gt3_txusrclk2_in => gt3_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in => gt3_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out => gt3_gtxtxn_out,
+ gt3_gtxtxp_out => gt3_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclk_out => gt3_txoutclk_i,
+ gt3_txoutclkfabric_out => gt3_txoutclkfabric_out,
+ gt3_txoutclkpcs_out => gt3_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in => gt3_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out => gt3_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>GTX_SODAinput</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gtwizard" spirit:version="3.5"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">GTX_SODAinput</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_SODAinput</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_tx_pll" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_rx_pll" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt15_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt15_val_tx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt15_val_rx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_decoding" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_drp_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txbuf_en" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txoutclk_source" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_comma_preset" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_align_comma_word" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxslide" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_dfe_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxslide_mode" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_SODAinput (a Core Top)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_SODAinput is
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end GTX_SODAinput;
+
+architecture RTL of GTX_SODAinput is
+ attribute DowngradeIPIdentifiedWarnings: string;
+ attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of RTL : architecture is "GTX_SODAinput,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_SODAinput,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+--**************************Component Declarations*****************************
+
+component GTX_SODAinput_init
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+
+ STABLE_CLOCK_PERIOD : integer := 10;
+ -- Set to 1 for simulation
+ EXAMPLE_USE_CHIPSCOPE : integer := 1 --// Modified -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end component;
+
+--**************************** Main Body of Code *******************************
+begin
+ U0 : GTX_SODAinput_init
+ generic map
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP => "TRUE",
+ EXAMPLE_SIMULATION => 0,
+
+ USE_BUFG => 0,
+
+ STABLE_CLOCK_PERIOD => 10,
+ EXAMPLE_USE_CHIPSCOPE => 1 --// Modified
+)
+port map
+(
+ SYSCLK_IN => SYSCLK_IN,
+ SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
+ SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
+ DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
+ GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
+ GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
+ GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
+ GT0_TX_MMCM_LOCK_IN => GT0_TX_MMCM_LOCK_IN,
+ GT0_TX_MMCM_RESET_OUT => GT0_TX_MMCM_RESET_OUT,
+
+ --_________________________________________________________________________
+ --GT0 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => gt0_cplllockdetclk_in,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => gt0_gtrefclk0_in,
+ gt0_gtrefclk1_in => gt0_gtrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => gt0_drpclk_in,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_in,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_out,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_in,
+ gt0_txusrclk2_in => gt0_txusrclk2_in,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_out,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
+ GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN
+
+);
+
+end RTL;
+
--- /dev/null
+--//////////////////////////////////////////////////////////////////////////////
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput_auto_phase_align.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : The logic below implements the procedure to do automatic phase-alignment
+-- on the 7-series GTX as described in ug476pdf, version 1.3,
+-- Chapters "Using the TX Phase Alignment to Bypass the TX Buffer"
+-- and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer"
+-- Should the logic below differ from what is described in a later version
+-- of the user-guide, you are using an auto-alignment block, which is
+-- out of date and needs to be updated for safe operation.
+--
+--
+--
+-- Module GTX_SODAinput_AUTO_PHASE_ALIGN
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity GTX_SODAinput_AUTO_PHASE_ALIGN is
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Auto phase-alignment performed sucessfully
+ PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the
+ DLYSRESET : out STD_LOGIC; -- |transceiver.
+ DLYSRESETDONE : in STD_LOGIC; --/
+ RECCLKSTABLE : in STD_LOGIC --/on the RX-side.
+
+ );
+end GTX_SODAinput_AUTO_PHASE_ALIGN;
+
+architecture RTL of GTX_SODAinput_AUTO_PHASE_ALIGN is
+
+ component GTX_SODAinput_sync_block
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ type phase_align_auto_fsm is(
+ INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE
+ );
+
+ signal phalign_state : phase_align_auto_fsm := INIT;
+ signal phaligndone_prev : std_logic := '0';
+ signal phaligndone_ris_edge : std_logic;
+
+ signal count_phalign_edges : integer range 0 to 3:= 0;
+ signal phaligndone_sync : std_logic := '0';
+ signal dlysresetdone_sync : std_logic := '0';
+
+begin
+
+ sync_PHALIGNDONE : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => PHALIGNDONE,
+ data_out => phaligndone_sync
+ );
+
+ sync_DLYSRESETDONE : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => DLYSRESETDONE,
+ data_out => dlysresetdone_sync
+ );
+
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ phaligndone_prev <= phaligndone_sync;
+ end if;
+ end process;
+ phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0';
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then
+ DLYSRESET <= '0';
+ count_phalign_edges <= 0;
+ PHASE_ALIGNMENT_DONE <= '0';
+ phalign_state <= INIT;
+ else
+ if phaligndone_ris_edge = '1' then
+ if count_phalign_edges < 3 then
+ count_phalign_edges <= count_phalign_edges + 1;
+ end if;
+ end if;
+
+ DLYSRESET <= '0';
+
+ case phalign_state is
+ when INIT =>
+ PHASE_ALIGNMENT_DONE <= '0';
+ if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then
+ --DLYSRESET is toggled to '1'
+ DLYSRESET <= '1';
+ phalign_state <= WAIT_PHRST_DONE;
+ end if;
+
+ when WAIT_PHRST_DONE =>
+ if dlysresetdone_sync = '1' then
+ phalign_state <= COUNT_PHALIGN_DONE;
+ end if;
+ --No timeout-check here as that is done in the main FSM
+
+ when COUNT_PHALIGN_DONE =>
+ if (count_phalign_edges = 2) then
+
+ --For GTX: Only on the second edge of the PHALIGNDONE-signal the
+ -- phase-alignment is completed
+ --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment
+
+ phalign_state <= PHALIGN_DONE;
+ end if;
+
+ when PHALIGN_DONE =>
+ PHASE_ALIGNMENT_DONE <= '1';
+
+ when OTHERS =>
+ phalign_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput_cpll_railing.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_SODAinput_cpll_railing
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity GTX_SODAinput_cpll_railing is
+generic( USE_BUFG : integer := 0
+ );
+ port (
+ cpll_reset_out : out std_logic;
+ cpll_pd_out : out std_logic;
+ refclk_out : out std_logic;
+
+ refclk_in : in std_logic
+ );
+ end GTX_SODAinput_cpll_railing;
+
+
+architecture RTL of GTX_SODAinput_cpll_railing is
+
+--**************************** Signal Declarations ****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+
+attribute equivalent_register_removal: string;
+signal cpllpd_wait : std_logic_vector(95 downto 0) := x"FFFFFFFFFFFFFFFFFFFFFFFF";
+signal cpllreset_wait : std_logic_vector(127 downto 0) := x"000000000000000000000000000000FF";
+attribute equivalent_register_removal of cpllpd_wait : signal is "no";
+attribute equivalent_register_removal of cpllreset_wait : signal is "no";
+signal gtrefclk0_i :std_logic ;
+--******************************** Main Body of Code***************************
+
+begin
+
+ --------------------------- Static signal Assignments ---------------------
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+
+ use_bufg_cpll:if(USE_BUFG = 1) generate
+ refclk_buf : BUFG
+ port map
+ (O => gtrefclk0_i,
+ I => refclk_in);
+
+ end generate;
+
+ use_bufr_cpll:if(USE_BUFG = 0) generate
+ refclk_buf : BUFR
+ port map
+ (O => gtrefclk0_i,
+ CE => tied_to_vcc_i,
+ CLR => tied_to_ground_i,
+ I => refclk_in);
+
+ end generate;
+
+ process( gtrefclk0_i )
+ begin
+ if(gtrefclk0_i'event and gtrefclk0_i = '1') then
+ cpllpd_wait <= cpllpd_wait(94 downto 0) & '0';
+ cpllreset_wait <= cpllreset_wait(126 downto 0) & '0';
+ end if;
+ end process;
+
+cpll_pd_out <= cpllpd_wait(95);
+cpll_reset_out <= cpllreset_wait(127);
+refclk_out <= gtrefclk0_i;
+
+
+ end RTL;
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput_gt.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_SODAinput_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity GTX_SODAinput_GT is
+generic
+(
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
+ RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
+ SIM_CPLLREFCLK_SEL : bit_vector := "001";
+ PMA_RSV_IN : bit_vector := x"00018480";
+ PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
+);
+port
+(
+ cpllpd_in : in std_logic;
+ cpllrefclksel_in : in std_logic_vector(2 downto 0);
+ --------------------------------- CPLL Ports -------------------------------
+ cpllfbclklost_out : out std_logic;
+ cplllock_out : out std_logic;
+ cplllockdetclk_in : in std_logic;
+ cpllrefclklost_out : out std_logic;
+ cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gtrefclk0_in : in std_logic;
+ gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ drpaddr_in : in std_logic_vector(8 downto 0);
+ drpclk_in : in std_logic;
+ drpdi_in : in std_logic_vector(15 downto 0);
+ drpdo_out : out std_logic_vector(15 downto 0);
+ drpen_in : in std_logic;
+ drprdy_out : out std_logic;
+ drpwe_in : in std_logic;
+ ------------------------------- Clocking Ports -----------------------------
+ qpllclk_in : in std_logic;
+ qpllrefclk_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ eyescanreset_in : in std_logic;
+ rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ eyescandataerror_out : out std_logic;
+ eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN : in std_logic; --// Modified
+ RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ rxusrclk_in : in std_logic;
+ rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ rxdisperr_out : out std_logic_vector(1 downto 0);
+ rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ rxdlyen_in : in std_logic;
+ rxdlysreset_in : in std_logic;
+ rxdlysresetdone_out : out std_logic;
+ rxphalign_in : in std_logic;
+ rxphaligndone_out : out std_logic;
+ rxphalignen_in : in std_logic;
+ rxphdlyreset_in : in std_logic;
+ rxphmonitor_out : out std_logic_vector(4 downto 0);
+ rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ rxlpmhfhold_in : in std_logic;
+ rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ rxdfelpmreset_in : in std_logic;
+ rxmonitorout_out : out std_logic_vector(6 downto 0);
+ rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gtrxreset_in : in std_logic;
+ rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gttxreset_in : in std_logic;
+ txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ txusrclk_in : in std_logic;
+ txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ txdlyen_in : in std_logic;
+ txdlysreset_in : in std_logic;
+ txdlysresetdone_out : out std_logic;
+ txphalign_in : in std_logic;
+ txphaligndone_out : out std_logic;
+ txphalignen_in : in std_logic;
+ txphdlyreset_in : in std_logic;
+ txphinit_in : in std_logic;
+ txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gtxtxn_out : out std_logic;
+ gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ txoutclk_out : out std_logic;
+ txoutclkfabric_out : out std_logic;
+ txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ txresetdone_out : out std_logic
+
+
+);
+
+
+end GTX_SODAinput_GT;
+
+architecture RTL of GTX_SODAinput_GT is
+
+--**************************** Signal Declarations ****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+
+
+
+ -- RX Datapath signals
+ signal rxdata_i : std_logic_vector(63 downto 0);
+ signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
+ signal rxcharisk_float_i : std_logic_vector(5 downto 0);
+ signal rxdisperr_float_i : std_logic_vector(5 downto 0);
+ signal rxnotintable_float_i : std_logic_vector(5 downto 0);
+ signal rxrundisp_float_i : std_logic_vector(5 downto 0);
+
+
+ -- TX Datapath signals
+ signal txdata_i : std_logic_vector(63 downto 0);
+ signal txkerr_float_i : std_logic_vector(5 downto 0);
+ signal txrundisp_float_i : std_logic_vector(5 downto 0);
+ signal rxstartofseq_float_i : std_logic;
+--******************************** Main Body of Code***************************
+
+begin
+
+ --------------------------- Static signal Assignments ---------------------
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+
+ ------------------- GT Datapath byte mapping -----------------
+ RXDATA_OUT <= rxdata_i(15 downto 0);
+
+ txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+ ----------------------------- GTXE2 Instance --------------------------
+
+ gtxe2_i :GTXE2_CHANNEL
+ generic map
+ (
+
+ --_______________________ Simulation-Only Attributes ___________________
+
+ SIM_RECEIVER_DETECT_PASS => ("TRUE"),
+ SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
+ SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
+ SIM_CPLLREFCLK_SEL => (SIM_CPLLREFCLK_SEL),
+ SIM_VERSION => ("4.0"),
+
+
+ ------------------RX Byte and Word Alignment Attributes---------------
+ ALIGN_COMMA_DOUBLE => ("FALSE"),
+ ALIGN_COMMA_ENABLE => ("1111111111"),
+ ALIGN_COMMA_WORD => (1),
+ ALIGN_MCOMMA_DET => ("TRUE"),
+ ALIGN_MCOMMA_VALUE => ("1010000011"),
+ ALIGN_PCOMMA_DET => ("TRUE"),
+ ALIGN_PCOMMA_VALUE => ("0101111100"),
+ SHOW_REALIGN_COMMA => ("FALSE"), --//("TRUE"), Modified
+ RXSLIDE_AUTO_WAIT => (7),
+ RXSLIDE_MODE => ("AUTO"), --// ("PCS"), Modified
+ RX_SIG_VALID_DLY => (10),
+
+ ------------------RX 8B/10B Decoder Attributes---------------
+ RX_DISPERR_SEQ_MATCH => ("TRUE"),
+ DEC_MCOMMA_DETECT => ("TRUE"),
+ DEC_PCOMMA_DETECT => ("TRUE"),
+ DEC_VALID_COMMA_ONLY => ("FALSE"),
+
+ ------------------------RX Clock Correction Attributes----------------------
+ CBCC_DATA_SOURCE_SEL => ("DECODED"),
+ CLK_COR_SEQ_2_USE => ("FALSE"),
+ CLK_COR_KEEP_IDLE => ("FALSE"),
+ CLK_COR_MAX_LAT => (9),
+ CLK_COR_MIN_LAT => (7),
+ CLK_COR_PRECEDENCE => ("TRUE"),
+ CLK_COR_REPEAT_WAIT => (0),
+ CLK_COR_SEQ_LEN => (1),
+ CLK_COR_SEQ_1_ENABLE => ("1111"),
+ CLK_COR_SEQ_1_1 => ("0100000000"),
+ CLK_COR_SEQ_1_2 => ("0000000000"),
+ CLK_COR_SEQ_1_3 => ("0000000000"),
+ CLK_COR_SEQ_1_4 => ("0000000000"),
+ CLK_CORRECT_USE => ("FALSE"),
+ CLK_COR_SEQ_2_ENABLE => ("1111"),
+ CLK_COR_SEQ_2_1 => ("0100000000"),
+ CLK_COR_SEQ_2_2 => ("0000000000"),
+ CLK_COR_SEQ_2_3 => ("0000000000"),
+ CLK_COR_SEQ_2_4 => ("0000000000"),
+
+ ------------------------RX Channel Bonding Attributes----------------------
+ CHAN_BOND_KEEP_ALIGN => ("FALSE"),
+ CHAN_BOND_MAX_SKEW => (1),
+ CHAN_BOND_SEQ_LEN => (1),
+ CHAN_BOND_SEQ_1_1 => ("0000000000"),
+ CHAN_BOND_SEQ_1_2 => ("0000000000"),
+ CHAN_BOND_SEQ_1_3 => ("0000000000"),
+ CHAN_BOND_SEQ_1_4 => ("0000000000"),
+ CHAN_BOND_SEQ_1_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_1 => ("0000000000"),
+ CHAN_BOND_SEQ_2_2 => ("0000000000"),
+ CHAN_BOND_SEQ_2_3 => ("0000000000"),
+ CHAN_BOND_SEQ_2_4 => ("0000000000"),
+ CHAN_BOND_SEQ_2_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_USE => ("FALSE"),
+ FTS_DESKEW_SEQ_ENABLE => ("1111"),
+ FTS_LANE_DESKEW_CFG => ("1111"),
+ FTS_LANE_DESKEW_EN => ("FALSE"),
+
+ ---------------------------RX Margin Analysis Attributes----------------------------
+ ES_CONTROL => ("000000"),
+ ES_ERRDET_EN => ("FALSE"),
+ ES_EYE_SCAN_EN => ("TRUE"),
+ ES_HORZ_OFFSET => (x"000"),
+ ES_PMA_CFG => ("0000000000"),
+ ES_PRESCALE => ("00000"),
+ ES_QUALIFIER => (x"00000000000000000000"),
+ ES_QUAL_MASK => (x"00000000000000000000"),
+ ES_SDATA_MASK => (x"00000000000000000000"),
+ ES_VERT_OFFSET => ("000000000"),
+
+ -------------------------FPGA RX Interface Attributes-------------------------
+ RX_DATA_WIDTH => (20),
+
+ ---------------------------PMA Attributes----------------------------
+ OUTREFCLK_SEL_INV => ("11"),
+ PMA_RSV => (PMA_RSV_IN),
+ PMA_RSV2 => (x"2050"),
+ PMA_RSV3 => ("00"),
+ PMA_RSV4 => (x"00000000"),
+ RX_BIAS_CFG => ("000000000100"),
+ DMONITOR_CFG => (x"000A00"),
+ RX_CM_SEL => ("00"),
+ RX_CM_TRIM => ("010"),
+ RX_DEBUG_CFG => ("000000000000"),
+ RX_OS_CFG => ("0000010000000"),
+ TERM_RCAL_CFG => ("10000"),
+ TERM_RCAL_OVRD => ('0'),
+ TST_RSV => (x"00000000"),
+ RX_CLK25_DIV => (10),
+ TX_CLK25_DIV => (10),
+ UCODEER_CLR => ('0'),
+
+ ---------------------------PCI Express Attributes----------------------------
+ PCS_PCIE_EN => ("FALSE"),
+
+ ---------------------------PCS Attributes----------------------------
+ PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
+
+ -------------RX Buffer Attributes------------
+ RXBUF_ADDR_MODE => ("FAST"),
+ RXBUF_EIDLE_HI_CNT => ("1000"),
+ RXBUF_EIDLE_LO_CNT => ("0000"),
+ RXBUF_EN => ("FALSE"),
+ RX_BUFFER_CFG => ("000000"),
+ RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
+ RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
+ RXBUF_RESET_ON_EIDLE => ("FALSE"),
+ RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
+ RXBUFRESET_TIME => ("00001"),
+ RXBUF_THRESH_OVFLW => (61),
+ RXBUF_THRESH_OVRD => ("FALSE"),
+ RXBUF_THRESH_UNDFLW => (4),
+ RXDLY_CFG => (x"001F"),
+ RXDLY_LCFG => (x"030"),
+ RXDLY_TAP_CFG => (x"0000"),
+ RXPH_CFG => (x"000000"),
+ RXPHDLY_CFG => (x"084020"),
+ RXPH_MONITOR_SEL => ("00000"),
+ RX_XCLK_SEL => ("RXUSR"),
+ RX_DDI_SEL => ("000000"),
+ RX_DEFER_RESET_BUF_EN => ("TRUE"),
+
+ -----------------------CDR Attributes-------------------------
+
+ --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+ --For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010
+
+ --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
+
+ --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
+
+ --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
+
+ --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
+
+ --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
+
+ --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
+ RXCDR_CFG => (x"03000023ff10200020"),
+ RXCDR_FR_RESET_ON_EIDLE => ('0'),
+ RXCDR_HOLD_DURING_EIDLE => ('0'),
+ RXCDR_PH_RESET_ON_EIDLE => ('0'),
+ RXCDR_LOCK_CFG => ("010101"),
+
+ -------------------RX Initialization and Reset Attributes-------------------
+ RXCDRFREQRESET_TIME => ("00001"),
+ RXCDRPHRESET_TIME => ("00001"),
+ RXISCANRESET_TIME => ("00001"),
+ RXPCSRESET_TIME => ("00001"),
+ RXPMARESET_TIME => ("00011"),
+
+ -------------------RX OOB Signaling Attributes-------------------
+ RXOOB_CFG => ("0000110"),
+
+ -------------------------RX Gearbox Attributes---------------------------
+ RXGEARBOX_EN => ("FALSE"),
+ GEARBOX_MODE => ("000"),
+
+ -------------------------PRBS Detection Attribute-----------------------
+ RXPRBS_ERR_LOOPBACK => ('0'),
+
+ -------------Power-Down Attributes----------
+ PD_TRANS_TIME_FROM_P2 => (x"03c"),
+ PD_TRANS_TIME_NONE_P2 => (x"3c"),
+ PD_TRANS_TIME_TO_P2 => (x"64"),
+
+ -------------RX OOB Signaling Attributes----------
+ SAS_MAX_COM => (64),
+ SAS_MIN_COM => (36),
+ SATA_BURST_SEQ_LEN => ("0101"),
+ SATA_BURST_VAL => ("100"),
+ SATA_EIDLE_VAL => ("100"),
+ SATA_MAX_BURST => (8),
+ SATA_MAX_INIT => (21),
+ SATA_MAX_WAKE => (7),
+ SATA_MIN_BURST => (4),
+ SATA_MIN_INIT => (12),
+ SATA_MIN_WAKE => (4),
+
+ -------------RX Fabric Clock Output Control Attributes----------
+ TRANS_TIME_RATE => (x"0E"),
+
+ --------------TX Buffer Attributes----------------
+ TXBUF_EN => ("FALSE"),
+ TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
+ TXDLY_CFG => (x"001F"),
+ TXDLY_LCFG => (x"030"),
+ TXDLY_TAP_CFG => (x"0000"),
+ TXPH_CFG => (x"0780"),
+ TXPHDLY_CFG => (x"084020"),
+ TXPH_MONITOR_SEL => ("00000"),
+ TX_XCLK_SEL => ("TXUSR"),
+
+ -------------------------FPGA TX Interface Attributes-------------------------
+ TX_DATA_WIDTH => (20),
+
+ -------------------------TX Configurable Driver Attributes-------------------------
+ TX_DEEMPH0 => ("00000"),
+ TX_DEEMPH1 => ("00000"),
+ TX_EIDLE_ASSERT_DELAY => ("110"),
+ TX_EIDLE_DEASSERT_DELAY => ("100"),
+ TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
+ TX_MAINCURSOR_SEL => ('0'),
+ TX_DRIVE_MODE => ("DIRECT"),
+ TX_MARGIN_FULL_0 => ("1001110"),
+ TX_MARGIN_FULL_1 => ("1001001"),
+ TX_MARGIN_FULL_2 => ("1000101"),
+ TX_MARGIN_FULL_3 => ("1000010"),
+ TX_MARGIN_FULL_4 => ("1000000"),
+ TX_MARGIN_LOW_0 => ("1000110"),
+ TX_MARGIN_LOW_1 => ("1000100"),
+ TX_MARGIN_LOW_2 => ("1000010"),
+ TX_MARGIN_LOW_3 => ("1000000"),
+ TX_MARGIN_LOW_4 => ("1000000"),
+
+ -------------------------TX Gearbox Attributes--------------------------
+ TXGEARBOX_EN => ("FALSE"),
+
+ -------------------------TX Initialization and Reset Attributes--------------------------
+ TXPCSRESET_TIME => ("00001"),
+ TXPMARESET_TIME => ("00001"),
+
+ -------------------------TX Receiver Detection Attributes--------------------------
+ TX_RXDETECT_CFG => (x"1832"),
+ TX_RXDETECT_REF => ("100"),
+
+ ----------------------------CPLL Attributes----------------------------
+ CPLL_CFG => (x"BC07DC"),
+ CPLL_FBDIV => (2),
+ CPLL_FBDIV_45 => (4),
+ CPLL_INIT_CFG => (x"00001E"),
+ CPLL_LOCK_CFG => (x"01E8"),
+ CPLL_REFCLK_DIV => (1),
+ RXOUT_DIV => (2),
+ TXOUT_DIV => (2),
+ SATA_CPLL_CFG => ("VCO_3000MHZ"),
+
+ --------------RX Initialization and Reset Attributes-------------
+ RXDFELPMRESET_TIME => ("0001111"),
+
+ --------------RX Equalizer Attributes-------------
+ RXLPM_HF_CFG => ("00000011110000"),
+ RXLPM_LF_CFG => ("00000011110000"),
+ RX_DFE_GAIN_CFG => (x"020FEA"),
+ RX_DFE_H2_CFG => ("000000000000"),
+ RX_DFE_H3_CFG => ("000001000000"),
+ RX_DFE_H4_CFG => ("00011110000"),
+ RX_DFE_H5_CFG => ("00011100000"),
+ RX_DFE_KL_CFG => ("0000011111110"),
+ RX_DFE_LPM_CFG => (x"0904"),
+ RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
+ RX_DFE_UT_CFG => ("10001111000000000"),
+ RX_DFE_VP_CFG => ("00011111100000011"),
+
+ -------------------------Power-Down Attributes-------------------------
+ RX_CLKMUX_PD => ('1'),
+ TX_CLKMUX_PD => ('1'),
+
+ -------------------------FPGA RX Interface Attribute-------------------------
+ RX_INT_DATAWIDTH => (0),
+
+ -------------------------FPGA TX Interface Attribute-------------------------
+ TX_INT_DATAWIDTH => (0),
+
+ ------------------TX Configurable Driver Attributes---------------
+ TX_QPI_STATUS_EN => ('0'),
+
+ -------------------------RX Equalizer Attributes--------------------------
+ RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
+ RX_DFE_XYD_CFG => ("0000000000000"),
+
+ -------------------------TX Configurable Driver Attributes--------------------------
+ TX_PREDRIVER_MODE => ('0')
+
+
+ )
+ port map
+ (
+ --------------------------------- CPLL Ports -------------------------------
+ CPLLFBCLKLOST => cpllfbclklost_out,
+ CPLLLOCK => cplllock_out,
+ CPLLLOCKDETCLK => cplllockdetclk_in,
+ CPLLLOCKEN => tied_to_vcc_i,
+ CPLLPD => cpllpd_in,
+ CPLLREFCLKLOST => cpllrefclklost_out,
+ CPLLREFCLKSEL => cpllrefclksel_in,
+ CPLLRESET => cpllreset_in,
+ GTRSVD => "0000000000000000",
+ PCSRSVDIN => "0000000000000000",
+ PCSRSVDIN2 => "00000",
+ PMARSVDIN => "00000",
+ PMARSVDIN2 => "00000",
+ TSTIN => "11111111111111111111",
+ TSTOUT => open,
+ ---------------------------------- Channel ---------------------------------
+ CLKRSVD => tied_to_ground_vec_i(3 downto 0),
+ -------------------------- Channel - Clocking Ports ------------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => gtrefclk0_in,
+ GTREFCLK1 => gtrefclk1_in,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ DRPADDR => drpaddr_in,
+ DRPCLK => drpclk_in,
+ DRPDI => drpdi_in,
+ DRPDO => drpdo_out,
+ DRPEN => drpen_in,
+ DRPRDY => drprdy_out,
+ DRPWE => drpwe_in,
+ ------------------------------- Clocking Ports -----------------------------
+ GTREFCLKMONITOR => open,
+ QPLLCLK => qpllclk_in,
+ QPLLREFCLK => qpllrefclk_in,
+ RXSYSCLKSEL => "00",
+ TXSYSCLKSEL => "00",
+ --------------------------- Digital Monitor Ports --------------------------
+ DMONITOROUT => dmonitorout_out,
+ ----------------- FPGA TX Interface Datapath Configuration ----------------
+ TX8B10BEN => tied_to_vcc_i,
+ ------------------------------- Loopback Ports -----------------------------
+ LOOPBACK => tied_to_ground_vec_i(2 downto 0),
+ ----------------------------- PCI Express Ports ----------------------------
+ PHYSTATUS => open,
+ RXRATE => tied_to_ground_vec_i(2 downto 0),
+ RXVALID => open,
+ ------------------------------ Power-Down Ports ----------------------------
+ RXPD => "00",
+ TXPD => "00",
+ -------------------------- RX 8B/10B Decoder Ports -------------------------
+ SETERRSTATUS => tied_to_ground_i,
+ --------------------- RX Initialization and Reset Ports --------------------
+ EYESCANRESET => eyescanreset_in,
+ RXUSERRDY => rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ EYESCANDATAERROR => eyescandataerror_out,
+ EYESCANMODE => tied_to_ground_i,
+ EYESCANTRIGGER => eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRFREQRESET => tied_to_ground_i,
+ RXCDRHOLD => tied_to_ground_i,
+ RXCDRLOCK => RXCDRLOCK_OUT, --// Modified
+ RXCDROVRDEN => tied_to_ground_i,
+ RXCDRRESET => RXCDRRESET_IN, --// Modified
+ RXCDRRESETRSV => tied_to_ground_i,
+ ------------------- Receive Ports - Clock Correction Ports -----------------
+ RXCLKCORCNT => open,
+ ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+ RX8B10BEN => tied_to_vcc_i,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ RXUSRCLK => rxusrclk_in,
+ RXUSRCLK2 => rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ RXDATA => rxdata_i,
+ ------------------- Receive Ports - Pattern Checker Ports ------------------
+ RXPRBSERR => open,
+ RXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
+ ------------------- Receive Ports - Pattern Checker ports ------------------
+ RXPRBSCNTRESET => tied_to_ground_i,
+ -------------------- Receive Ports - RX Equalizer Ports -------------------
+ RXDFEXYDEN => tied_to_vcc_i,
+ RXDFEXYDHOLD => tied_to_ground_i,
+ RXDFEXYDOVRDEN => tied_to_ground_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ RXDISPERR(7 downto 2) => rxdisperr_float_i,
+ RXDISPERR(1 downto 0) => rxdisperr_out,
+ RXNOTINTABLE(7 downto 2) => rxnotintable_float_i,
+ RXNOTINTABLE(1 downto 0) => rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GTXRXP => gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GTXRXN => gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ RXBUFRESET => tied_to_ground_i,
+ RXBUFSTATUS => open,
+ RXDDIEN => tied_to_vcc_i,
+ RXDLYBYPASS => tied_to_ground_i,
+ RXDLYEN => rxdlyen_in,
+ RXDLYOVRDEN => tied_to_ground_i,
+ RXDLYSRESET => rxdlysreset_in,
+ RXDLYSRESETDONE => rxdlysresetdone_out,
+ RXPHALIGN => rxphalign_in,
+ RXPHALIGNDONE => rxphaligndone_out,
+ RXPHALIGNEN => rxphalignen_in,
+ RXPHDLYPD => tied_to_ground_i,
+ RXPHDLYRESET => rxphdlyreset_in,
+ RXPHMONITOR => rxphmonitor_out,
+ RXPHOVRDEN => tied_to_ground_i,
+ RXPHSLIPMONITOR => rxphslipmonitor_out,
+ RXSTATUS => open,
+ -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+ RXBYTEISALIGNED => open,
+ RXBYTEREALIGN => open,
+ RXCOMMADET => open,
+ RXCOMMADETEN => tied_to_vcc_i,
+ RXMCOMMAALIGNEN => tied_to_vcc_i,
+ RXPCOMMAALIGNEN => tied_to_vcc_i,
+ ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+ RXCHANBONDSEQ => open,
+ RXCHBONDEN => tied_to_ground_i,
+ RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
+ RXCHBONDMASTER => tied_to_ground_i,
+ RXCHBONDO => open,
+ RXCHBONDSLAVE => tied_to_ground_i,
+ ----------------- Receive Ports - RX Channel Bonding Ports ----------------
+ RXCHANISALIGNED => open,
+ RXCHANREALIGN => open,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ RXLPMHFHOLD => rxlpmhfhold_in,
+ RXLPMHFOVRDEN => tied_to_ground_i,
+ RXLPMLFHOLD => rxlpmlfhold_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ RXDFEAGCHOLD => tied_to_ground_i,
+ RXDFEAGCOVRDEN => tied_to_ground_i,
+ RXDFECM1EN => tied_to_ground_i,
+ RXDFELFHOLD => tied_to_ground_i,
+ RXDFELFOVRDEN => tied_to_ground_i,
+ RXDFELPMRESET => rxdfelpmreset_in,
+ RXDFETAP2HOLD => tied_to_ground_i,
+ RXDFETAP2OVRDEN => tied_to_ground_i,
+ RXDFETAP3HOLD => tied_to_ground_i,
+ RXDFETAP3OVRDEN => tied_to_ground_i,
+ RXDFETAP4HOLD => tied_to_ground_i,
+ RXDFETAP4OVRDEN => tied_to_ground_i,
+ RXDFETAP5HOLD => tied_to_ground_i,
+ RXDFETAP5OVRDEN => tied_to_ground_i,
+ RXDFEUTHOLD => tied_to_ground_i,
+ RXDFEUTOVRDEN => tied_to_ground_i,
+ RXDFEVPHOLD => tied_to_ground_i,
+ RXDFEVPOVRDEN => tied_to_ground_i,
+ RXDFEVSEN => tied_to_ground_i,
+ RXLPMLFKLOVRDEN => tied_to_ground_i,
+ RXMONITOROUT => rxmonitorout_out,
+ RXMONITORSEL => rxmonitorsel_in,
+ RXOSHOLD => tied_to_ground_i,
+ RXOSOVRDEN => tied_to_ground_i,
+ ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+ RXRATEDONE => open,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ RXOUTCLK => rxoutclk_out,
+ RXOUTCLKFABRIC => open,
+ RXOUTCLKPCS => open,
+ RXOUTCLKSEL => "010",
+ ---------------------- Receive Ports - RX Gearbox Ports --------------------
+ RXDATAVALID => open,
+ RXHEADER => open,
+ RXHEADERVALID => open,
+ RXSTARTOFSEQ => open,
+ --------------------- Receive Ports - RX Gearbox Ports --------------------
+ RXGEARBOXSLIP => tied_to_ground_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GTRXRESET => gtrxreset_in,
+ RXOOBRESET => tied_to_ground_i,
+ RXPCSRESET => tied_to_ground_i,
+ RXPMARESET => rxpmareset_in,
+ ------------------ Receive Ports - RX Margin Analysis ports ----------------
+ RXLPMEN => tied_to_vcc_i,
+ ------------------- Receive Ports - RX OOB Signaling ports -----------------
+ RXCOMSASDET => open,
+ RXCOMWAKEDET => open,
+ ------------------ Receive Ports - RX OOB Signaling ports -----------------
+ RXCOMINITDET => open,
+ ------------------ Receive Ports - RX OOB signalling Ports -----------------
+ RXELECIDLE => open,
+ RXELECIDLEMODE => "11",
+ ----------------- Receive Ports - RX Polarity Control Ports ----------------
+ RXPOLARITY => tied_to_ground_i,
+ ---------------------- Receive Ports - RX gearbox ports --------------------
+ RXSLIDE => tied_to_ground_i,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ RXCHARISCOMMA => open,
+ RXCHARISK(7 downto 2) => rxcharisk_float_i,
+ RXCHARISK(1 downto 0) => rxcharisk_out,
+ ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+ RXCHBONDI => "00000",
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ RXRESETDONE => rxresetdone_out,
+ -------------------------------- Rx AFE Ports ------------------------------
+ RXQPIEN => tied_to_ground_i,
+ RXQPISENN => open,
+ RXQPISENP => open,
+ --------------------------- TX Buffer Bypass Ports -------------------------
+ TXPHDLYTSTCLK => tied_to_ground_i,
+ ------------------------ TX Configurable Driver Ports ----------------------
+ TXPOSTCURSOR => "00000",
+ TXPOSTCURSORINV => tied_to_ground_i,
+ TXPRECURSOR => tied_to_ground_vec_i(4 downto 0),
+ TXPRECURSORINV => tied_to_ground_i,
+ TXQPIBIASEN => tied_to_ground_i,
+ TXQPISTRONGPDOWN => tied_to_ground_i,
+ TXQPIWEAKPUP => tied_to_ground_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ CFGRESET => tied_to_ground_i,
+ GTTXRESET => gttxreset_in,
+ PCSRSVDOUT => open,
+ TXUSERRDY => txuserrdy_in,
+ ---------------------- Transceiver Reset Mode Operation --------------------
+ GTRESETSEL => tied_to_ground_i,
+ RESETOVRD => tied_to_ground_i,
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ TXCHARDISPMODE => tied_to_ground_vec_i(7 downto 0),
+ TXCHARDISPVAL => tied_to_ground_vec_i(7 downto 0),
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ TXUSRCLK => txusrclk_in,
+ TXUSRCLK2 => txusrclk2_in,
+ --------------------- Transmit Ports - PCI Express Ports -------------------
+ TXELECIDLE => tied_to_ground_i,
+ TXMARGIN => tied_to_ground_vec_i(2 downto 0),
+ TXRATE => tied_to_ground_vec_i(2 downto 0),
+ TXSWING => tied_to_ground_i,
+ ------------------ Transmit Ports - Pattern Generator Ports ----------------
+ TXPRBSFORCEERR => tied_to_ground_i,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ TXDLYBYPASS => tied_to_ground_i,
+ TXDLYEN => txdlyen_in,
+ TXDLYHOLD => tied_to_ground_i,
+ TXDLYOVRDEN => tied_to_ground_i,
+ TXDLYSRESET => txdlysreset_in,
+ TXDLYSRESETDONE => txdlysresetdone_out,
+ TXDLYUPDOWN => tied_to_ground_i,
+ TXPHALIGN => txphalign_in,
+ TXPHALIGNDONE => txphaligndone_out,
+ TXPHALIGNEN => txphalignen_in,
+ TXPHDLYPD => tied_to_ground_i,
+ TXPHDLYRESET => txphdlyreset_in,
+ TXPHINIT => txphinit_in,
+ TXPHINITDONE => txphinitdone_out,
+ TXPHOVRDEN => tied_to_ground_i,
+ ---------------------- Transmit Ports - TX Buffer Ports --------------------
+ TXBUFSTATUS => open,
+ --------------- Transmit Ports - TX Configurable Driver Ports --------------
+ TXBUFDIFFCTRL => "100",
+ TXDEEMPH => tied_to_ground_i,
+ TXDIFFCTRL => "1000",
+ TXDIFFPD => tied_to_ground_i,
+ TXINHIBIT => tied_to_ground_i,
+ TXMAINCURSOR => "0000000",
+ TXPISOPD => tied_to_ground_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA => txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTXTXN => gtxtxn_out,
+ GTXTXP => gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ TXOUTCLK => txoutclk_out,
+ TXOUTCLKFABRIC => txoutclkfabric_out,
+ TXOUTCLKPCS => txoutclkpcs_out,
+ TXOUTCLKSEL => "011",
+ TXRATEDONE => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ TXCHARISK(7 downto 2) => tied_to_ground_vec_i(5 downto 0),
+ TXCHARISK(1 downto 0) => txcharisk_in,
+ TXGEARBOXREADY => open,
+ TXHEADER => tied_to_ground_vec_i(2 downto 0),
+ TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
+ TXSTARTSEQ => tied_to_ground_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ TXPCSRESET => tied_to_ground_i,
+ TXPMARESET => tied_to_ground_i,
+ TXRESETDONE => txresetdone_out,
+ ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+ TXCOMFINISH => open,
+ TXCOMINIT => tied_to_ground_i,
+ TXCOMSAS => tied_to_ground_i,
+ TXCOMWAKE => tied_to_ground_i,
+ TXPDELECIDLEMODE => tied_to_ground_i,
+ ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+ TXPOLARITY => tied_to_ground_i,
+ --------------- Transmit Ports - TX Receiver Detection Ports --------------
+ TXDETECTRX => tied_to_ground_i,
+ ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+ TX8B10BBYPASS => tied_to_ground_vec_i(7 downto 0),
+ ------------------ Transmit Ports - pattern Generator Ports ----------------
+ TXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
+ ----------------------- Tx Configurable Driver Ports ----------------------
+ TXQPISENN => open,
+ TXQPISENP => open
+
+ );
+
+
+ end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput_init.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_SODAinput_init
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity GTX_SODAinput_init is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+
+ STABLE_CLOCK_PERIOD : integer := 10;
+ -- Set to 1 for simulation
+ EXAMPLE_USE_CHIPSCOPE : integer := 1 --// Modified -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+ --_________________________________________________________________________
+ --GT0 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end GTX_SODAinput_init;
+
+architecture RTL of GTX_SODAinput_init is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+
+component GTX_SODAinput_multi_gt
+generic
+(
+ -- Simulation attributes
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
+
+);
+port
+(
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllrefclklost_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxdlyen_in : in std_logic;
+ gt0_rxdlysreset_in : in std_logic;
+ gt0_rxdlysresetdone_out : out std_logic;
+ gt0_rxphalign_in : in std_logic;
+ gt0_rxphaligndone_out : out std_logic;
+ gt0_rxphalignen_in : in std_logic;
+ gt0_rxphdlyreset_in : in std_logic;
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ gt0_rxlpmhfhold_in : in std_logic;
+ gt0_rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ gt0_txdlyen_in : in std_logic;
+ gt0_txdlysreset_in : in std_logic;
+ gt0_txdlysresetdone_out : out std_logic;
+ gt0_txphalign_in : in std_logic;
+ gt0_txphaligndone_out : out std_logic;
+ gt0_txphalignen_in : in std_logic;
+ gt0_txphdlyreset_in : in std_logic;
+ gt0_txphinit_in : in std_logic;
+ gt0_txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end component;
+
+component GTX_SODAinput_TX_STARTUP_FSM
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ TXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ GTTXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='0';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
+ TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
+ TXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC:='0';
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ PHALIGNMENT_DONE : in STD_LOGIC;
+
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end component;
+
+component GTX_SODAinput_RX_STARTUP_FSM
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ EQ_MODE : string := "DFE";
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ RXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ RECCLK_STABLE : in STD_LOGIC;
+ RECCLK_MONITOR_RESTART : in STD_LOGIC;
+ DATA_VALID : in STD_LOGIC;
+ TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
+ DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
+ GTRXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='0';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
+ RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
+ RXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC;
+ PHALIGNMENT_DONE : in STD_LOGIC;
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ RXDFEAGCHOLD : out STD_LOGIC;
+ RXDFELFHOLD : out STD_LOGIC;
+ RXLPMLFHOLD : out STD_LOGIC;
+ RXLPMHFHOLD : out STD_LOGIC;
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end component;
+
+
+
+
+component GTX_SODAinput_AUTO_PHASE_ALIGN
+ port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC; -- Auto phase-alignment performed sucessfully
+ PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the
+ DLYSRESET : out STD_LOGIC; -- |transceiver.
+ DLYSRESETDONE : in STD_LOGIC; --/
+ RECCLKSTABLE : in STD_LOGIC --/on the RX-side.
+
+ );
+end component;
+
+
+component GTX_SODAinput_TX_MANUAL_PHASE_ALIGN
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ TXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHINIT : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHINITDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end component;
+
+component GTX_SODAinput_RX_MANUAL_PHASE_ALIGN
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ RXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end component;
+
+ function get_cdrlock_time(is_sim : in integer) return integer is
+ variable lock_time: integer;
+ begin
+ if (is_sim = 1) then
+ lock_time := 1000;
+ else
+ lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183
+ end if;
+ return lock_time;
+ end function;
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+ constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
+ constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
+
+
+
+ -------------------------- GT Wrapper Wires ------------------------------
+ signal gt0_txpmaresetdone_i : std_logic;
+ signal gt0_rxpmaresetdone_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ signal gt0_cpllreset_t : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_txresetdone_i : std_logic;
+ signal gt0_rxresetdone_i : std_logic;
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_gttxreset_t : std_logic;
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_gtrxreset_t : std_logic;
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ signal gt0_txuserrdy_t : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ signal gt0_rxuserrdy_t : std_logic;
+
+ signal gt0_rxdfeagchold_i : std_logic;
+ signal gt0_rxdfelfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ signal gt0_rxlpmhfhold_i : std_logic;
+
+
+
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qplllock_i : std_logic;
+
+
+ ------------------------------- Global Signals -----------------------------
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ signal gt0_run_tx_phalignment_i : std_logic;
+ signal gt0_rst_tx_phalignment_i : std_logic;
+ signal gt0_tx_phalignment_done_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+ signal gt0_rxoutclk_i2 : std_logic;
+ signal gt0_txoutclk_i2 : std_logic;
+ signal gt0_recclk_stable_i : std_logic;
+ signal gt0_rx_cdrlocked : std_logic;
+ signal gt0_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_run_rx_phalignment_i : std_logic;
+ signal gt0_rst_rx_phalignment_i : std_logic;
+ signal gt0_rx_phalignment_done_i : std_logic;
+
+
+
+ --------------------------- TX Buffer Bypass Signals --------------------
+ signal mstr0_txsyncallin_i : std_logic;
+ signal U0_TXDLYEN : std_logic_vector(0 downto 0);
+ signal U0_TXDLYSRESET : std_logic_vector(0 downto 0);
+ signal U0_TXDLYSRESETDONE : std_logic_vector(0 downto 0);
+ signal U0_TXPHINIT : std_logic_vector(0 downto 0);
+ signal U0_TXPHINITDONE : std_logic_vector(0 downto 0);
+ signal U0_TXPHALIGN : std_logic_vector(0 downto 0);
+ signal U0_TXPHALIGNDONE : std_logic_vector(0 downto 0);
+ signal U0_run_tx_phalignment_i : std_logic;
+ signal U0_rst_tx_phalignment_i : std_logic;
+
+
+ --------------------------- RX Buffer Bypass Signals --------------------
+ signal rxmstr0_rxsyncallin_i : std_logic;
+ signal U0_RXDLYEN : std_logic_vector(0 downto 0);
+ signal U0_RXDLYSRESET : std_logic_vector(0 downto 0);
+ signal U0_RXDLYSRESETDONE : std_logic_vector(0 downto 0);
+ signal U0_RXPHALIGN : std_logic_vector(0 downto 0);
+ signal U0_RXPHALIGNDONE : std_logic_vector(0 downto 0);
+ signal U0_run_rx_phalignment_i : std_logic;
+ signal U0_rst_rx_phalignment_i : std_logic;
+
+
+
+ signal rx_cdrlocked : std_logic;
+
+
+
+
+
+--**************************** Main Body of Code *******************************
+begin
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+
+ ----------------------------- The GT Wrapper -----------------------------
+
+ -- Use the instantiation template in the example directory to add the GT wrapper to your design.
+ -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
+ -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
+ -- enabled, bonding should occur after alignment.
+
+
+ GTX_SODAinput_i : GTX_SODAinput_multi_gt
+ generic map
+ (
+ USE_BUFG => USE_BUFG,
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
+ )
+ port map
+ (
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_i,
+ gt0_cplllockdetclk_in => gt0_cplllockdetclk_in,
+ gt0_cpllrefclklost_out => gt0_cpllrefclklost_i,
+ gt0_cpllreset_in => gt0_cpllreset_i,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => gt0_gtrefclk0_in,
+ gt0_gtrefclk1_in => gt0_gtrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => gt0_drpclk_in,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_i,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_in,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxdlyen_in => gt0_rxdlyen_i,
+ gt0_rxdlysreset_in => gt0_rxdlysreset_i,
+ gt0_rxdlysresetdone_out => gt0_rxdlysresetdone_i,
+ gt0_rxphalign_in => gt0_rxphalign_i,
+ gt0_rxphaligndone_out => gt0_rxphaligndone_i,
+ gt0_rxphalignen_in => gt0_rxphalignen_i,
+ gt0_rxphdlyreset_in => gt0_rxphdlyreset_i,
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ gt0_rxlpmhfhold_in => gt0_rxlpmhfhold_i,
+ gt0_rxlpmlfhold_in => gt0_rxlpmlfhold_i,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_i,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_i,
+ gt0_txuserrdy_in => gt0_txuserrdy_i,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_in,
+ gt0_txusrclk2_in => gt0_txusrclk2_in,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ gt0_txdlyen_in => gt0_txdlyen_i,
+ gt0_txdlysreset_in => gt0_txdlysreset_i,
+ gt0_txdlysresetdone_out => gt0_txdlysresetdone_i,
+ gt0_txphalign_in => gt0_txphalign_i,
+ gt0_txphaligndone_out => gt0_txphaligndone_i,
+ gt0_txphalignen_in => gt0_txphalignen_i,
+ gt0_txphdlyreset_in => gt0_txphdlyreset_i,
+ gt0_txphinit_in => gt0_txphinit_i,
+ gt0_txphinitdone_out => gt0_txphinitdone_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_i,
+
+
+
+
+ --____________________________COMMON PORTS________________________________
+ gt0_qplloutclk_in => gt0_qplloutclk_in,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_in
+ );
+
+
+gt0_rxdfelpmreset_i <= tied_to_ground_i;
+
+
+GT0_CPLLLOCK_OUT <= gt0_cplllock_i;
+GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
+GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
+GT0_RXOUTCLK_OUT <= gt0_rxoutclk_i;
+GT0_TXOUTCLK_OUT <= gt0_txoutclk_i;
+
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
+gt0_cpllreset_i <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
+ gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
+ gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
+ gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
+ gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
+end generate chipscope;
+
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
+gt0_cpllreset_i <= gt0_cpllreset_t;
+gt0_gttxreset_i <= gt0_gttxreset_t;
+gt0_gtrxreset_i <= gt0_gtrxreset_t;
+gt0_txuserrdy_i <= gt0_txuserrdy_t;
+gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
+end generate no_chipscope;
+
+
+gt0_txresetfsm_i: GTX_SODAinput_TX_STARTUP_FSM
+
+ generic map(
+ EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
+ STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH => 8,
+ TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
+ RX_QPLL_USED => FALSE, -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL => TRUE -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ )
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ TXUSERCLK => GT0_TXUSRCLK_IN,
+ SOFT_RESET => SOFT_RESET_TX_IN,
+ QPLLREFCLKLOST => tied_to_ground_i,
+ CPLLREFCLKLOST => gt0_cpllrefclklost_i,
+ QPLLLOCK => tied_to_vcc_i,
+ CPLLLOCK => gt0_cplllock_i,
+ TXRESETDONE => gt0_txresetdone_i,
+ MMCM_LOCK => GT0_TX_MMCM_LOCK_IN,
+ GTTXRESET => gt0_gttxreset_t,
+ MMCM_RESET => GT0_TX_MMCM_RESET_OUT,
+ QPLL_RESET => open,
+ CPLL_RESET => gt0_cpllreset_t,
+ TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT,
+ TXUSERRDY => gt0_txuserrdy_t,
+ RUN_PHALIGNMENT => gt0_run_tx_phalignment_i,
+ RESET_PHALIGNMENT => gt0_rst_tx_phalignment_i,
+ PHALIGNMENT_DONE => gt0_tx_phalignment_done_i,
+ RETRY_COUNTER => open
+ );
+
+
+
+
+
+
+
+
+gt0_rxresetfsm_i: GTX_SODAinput_RX_STARTUP_FSM
+
+ generic map(
+ EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
+ EQ_MODE => "LPM", --Rx Equalization Mode - Set to DFE or LPM
+ STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH => 8,
+ TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
+ RX_QPLL_USED => FALSE, -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ )
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ RXUSERCLK => GT0_RXUSRCLK_IN,
+ SOFT_RESET => SOFT_RESET_RX_IN,
+ DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
+ QPLLREFCLKLOST => tied_to_ground_i,
+ CPLLREFCLKLOST => gt0_cpllrefclklost_i,
+ QPLLLOCK => tied_to_vcc_i,
+ CPLLLOCK => gt0_cplllock_i,
+ RXRESETDONE => gt0_rxresetdone_i,
+ MMCM_LOCK => tied_to_vcc_i,
+ RECCLK_STABLE => gt0_recclk_stable_i,
+ RECCLK_MONITOR_RESTART => tied_to_ground_i,
+ DATA_VALID => GT0_DATA_VALID_IN,
+ TXUSERRDY => tied_to_vcc_i,
+ GTRXRESET => gt0_gtrxreset_t,
+ MMCM_RESET => open,
+ QPLL_RESET => open,
+ CPLL_RESET => open,
+ RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT,
+ RXUSERRDY => gt0_rxuserrdy_t,
+ RUN_PHALIGNMENT => gt0_run_rx_phalignment_i,
+ RESET_PHALIGNMENT => gt0_rst_rx_phalignment_i,
+ PHALIGNMENT_DONE => gt0_rx_phalignment_done_i,
+ RXDFEAGCHOLD => gt0_rxdfeagchold_i,
+ RXDFELFHOLD => gt0_rxdfelfhold_i,
+ RXLPMLFHOLD => gt0_rxlpmlfhold_i,
+ RXLPMHFHOLD => gt0_rxlpmhfhold_i,
+ RETRY_COUNTER => open
+ );
+
+
+
+ gt0_cdrlock_timeout:process(SYSCLK_IN)
+ begin
+ if rising_edge(SYSCLK_IN) then
+ if(gt0_gtrxreset_i = '1') then
+ gt0_rx_cdrlocked <= '0';
+ gt0_rx_cdrlock_counter <= 0 after DLY;
+ elsif (gt0_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
+ gt0_rx_cdrlocked <= '1';
+ gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter after DLY;
+ else
+ gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter + 1 after DLY;
+ end if;
+ end if;
+ end process;
+
+gt0_recclk_stable_i <= gt0_rx_cdrlocked;
+
+
+
+ --------------------------- TX Buffer Bypass Logic --------------------
+ -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer.
+ -- Include the TX SYNC module in your own design if TX Buffer is bypassed.
+
+
+--Auto
+gt0_txphdlyreset_i <= tied_to_ground_i;
+gt0_txphalignen_i <= tied_to_ground_i;
+gt0_txdlyen_i <= tied_to_ground_i;
+gt0_txphalign_i <= tied_to_ground_i;
+gt0_txphinit_i <= tied_to_ground_i;
+
+gt0_tx_auto_phase_align_i : GTX_SODAinput_AUTO_PHASE_ALIGN
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ RUN_PHALIGNMENT => gt0_run_tx_phalignment_i,
+ PHASE_ALIGNMENT_DONE => gt0_tx_phalignment_done_i,
+ PHALIGNDONE => gt0_txphaligndone_i,
+ DLYSRESET => gt0_txdlysreset_i,
+ DLYSRESETDONE => gt0_txdlysresetdone_i,
+ RECCLKSTABLE => tied_to_vcc_i
+ );
+
+
+
+
+ --------------------------- RX Buffer Bypass Logic --------------------
+-- The RX SYNC Module drives the ports needed to Bypass the RX Buffer.
+-- Include the RX SYNC module in your own design if RX Buffer is bypassed.
+
+
+--Auto
+gt0_rxphdlyreset_i <= '1'; --// Modified??????? tied_to_ground_i;
+gt0_rxphalignen_i <= '1'; --// Modified??????? tied_to_ground_i;
+gt0_rxdlyen_i <= tied_to_ground_i;
+gt0_rxphalign_i <= tied_to_ground_i;
+
+gt0_rx_phalignment_done_i <= '1'; --// Modified
+gt0_rxdlysreset_i <= '1'; --// Modified
+-- gt0_rx_auto_phase_align_i : GTX_SODAinput_AUTO_PHASE_ALIGN
+ -- port map (
+ -- STABLE_CLOCK => SYSCLK_IN,
+ -- RUN_PHALIGNMENT => gt0_run_rx_phalignment_i,
+ -- PHASE_ALIGNMENT_DONE => gt0_rx_phalignment_done_i,
+ -- PHALIGNDONE => gt0_rxphaligndone_i,
+ -- DLYSRESET => gt0_rxdlysreset_i,
+ -- DLYSRESETDONE => gt0_rxdlysresetdone_i,
+ -- RECCLKSTABLE => gt0_recclk_stable_i
+ -- );
+
+end RTL;
+
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput_multi_gt.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_SODAinput_multi_gt (a Multi GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity GTX_SODAinput_multi_gt is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
+ RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+
+ PMA_RSV_IN : bit_vector := x"00018480"
+);
+port
+(
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X0Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllrefclklost_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxdlyen_in : in std_logic;
+ gt0_rxdlysreset_in : in std_logic;
+ gt0_rxdlysresetdone_out : out std_logic;
+ gt0_rxphalign_in : in std_logic;
+ gt0_rxphaligndone_out : out std_logic;
+ gt0_rxphalignen_in : in std_logic;
+ gt0_rxphdlyreset_in : in std_logic;
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ gt0_rxlpmhfhold_in : in std_logic;
+ gt0_rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ gt0_txdlyen_in : in std_logic;
+ gt0_txdlysreset_in : in std_logic;
+ gt0_txdlysresetdone_out : out std_logic;
+ gt0_txphalign_in : in std_logic;
+ gt0_txphaligndone_out : out std_logic;
+ gt0_txphalignen_in : in std_logic;
+ gt0_txphdlyreset_in : in std_logic;
+ gt0_txphinit_in : in std_logic;
+ gt0_txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+
+end GTX_SODAinput_multi_gt;
+
+architecture RTL of GTX_SODAinput_multi_gt is
+ attribute DowngradeIPIdentifiedWarnings: string;
+ attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_SODAinput_multi_gt,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
+ signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
+
+ signal gt0_qpllclk_i : std_logic;
+ signal gt0_qpllrefclk_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ signal gt0_cpllpd_i : std_logic;
+ signal cpll_reset0_i : std_logic;
+ signal cpll_pd0_i : std_logic;
+
+--*************************** Component Declarations **************************
+component GTX_SODAinput_GT
+generic
+(
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
+ RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
+ PMA_RSV_IN : bit_vector := X"00000000";
+ SIM_CPLLREFCLK_SEL : bit_vector := "001";
+ PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
+);
+port
+(
+ cpllpd_in : in std_logic;
+ cpllrefclksel_in : in std_logic_vector (2 downto 0);
+ --------------------------------- CPLL Ports -------------------------------
+ cpllfbclklost_out : out std_logic;
+ cplllock_out : out std_logic;
+ cplllockdetclk_in : in std_logic;
+ cpllrefclklost_out : out std_logic;
+ cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gtrefclk0_in : in std_logic;
+ gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ drpaddr_in : in std_logic_vector(8 downto 0);
+ drpclk_in : in std_logic;
+ drpdi_in : in std_logic_vector(15 downto 0);
+ drpdo_out : out std_logic_vector(15 downto 0);
+ drpen_in : in std_logic;
+ drprdy_out : out std_logic;
+ drpwe_in : in std_logic;
+ ------------------------------- Clocking Ports -----------------------------
+ qpllclk_in : in std_logic;
+ qpllrefclk_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ eyescanreset_in : in std_logic;
+ rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ eyescandataerror_out : out std_logic;
+ eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN : in std_logic; --// Modified
+ RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ rxusrclk_in : in std_logic;
+ rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ rxdisperr_out : out std_logic_vector(1 downto 0);
+ rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ rxdlyen_in : in std_logic;
+ rxdlysreset_in : in std_logic;
+ rxdlysresetdone_out : out std_logic;
+ rxphalign_in : in std_logic;
+ rxphaligndone_out : out std_logic;
+ rxphalignen_in : in std_logic;
+ rxphdlyreset_in : in std_logic;
+ rxphmonitor_out : out std_logic_vector(4 downto 0);
+ rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ rxlpmhfhold_in : in std_logic;
+ rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ rxdfelpmreset_in : in std_logic;
+ rxmonitorout_out : out std_logic_vector(6 downto 0);
+ rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gtrxreset_in : in std_logic;
+ rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gttxreset_in : in std_logic;
+ txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ txusrclk_in : in std_logic;
+ txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ txdlyen_in : in std_logic;
+ txdlysreset_in : in std_logic;
+ txdlysresetdone_out : out std_logic;
+ txphalign_in : in std_logic;
+ txphaligndone_out : out std_logic;
+ txphalignen_in : in std_logic;
+ txphdlyreset_in : in std_logic;
+ txphinit_in : in std_logic;
+ txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gtxtxn_out : out std_logic;
+ gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ txoutclk_out : out std_logic;
+ txoutclkfabric_out : out std_logic;
+ txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ txresetdone_out : out std_logic
+
+
+);
+end component;
+component GTX_SODAinput_cpll_railing
+ Generic(
+ USE_BUFG : integer := 0
+);
+port
+(
+ cpll_reset_out : out std_logic;
+ cpll_pd_out : out std_logic;
+ refclk_out : out std_logic;
+
+ refclk_in : in std_logic
+
+);
+end component;
+
+
+
+--********************************* Main Body of Code**************************
+
+begin
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ gt0_qpllclk_i <= GT0_QPLLOUTCLK_IN;
+ gt0_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN;
+
+
+
+ --------------------------- GT Instances -------------------------------
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X0Y15)
+
+gt0_GTX_SODAinput_i : GTX_SODAinput_GT
+ generic map
+ (
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
+ SIM_CPLLREFCLK_SEL => "001",
+ PMA_RSV_IN => PMA_RSV_IN,
+ PCS_RSVD_ATTR_IN => X"000000000000"
+ )
+ port map
+ (
+ cpllpd_in => gt0_cpllpd_i,
+ cpllrefclksel_in => "001",
+ --------------------------------- CPLL Ports -------------------------------
+ cpllfbclklost_out => gt0_cpllfbclklost_out,
+ cplllock_out => gt0_cplllock_out,
+ cplllockdetclk_in => gt0_cplllockdetclk_in,
+ cpllrefclklost_out => gt0_cpllrefclklost_out,
+ cpllreset_in => gt0_cpllreset_i,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gtrefclk0_in => gt0_gtrefclk0_in,
+ gtrefclk1_in => gt0_gtrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ drpaddr_in => gt0_drpaddr_in,
+ drpclk_in => gt0_drpclk_in,
+ drpdi_in => gt0_drpdi_in,
+ drpdo_out => gt0_drpdo_out,
+ drpen_in => gt0_drpen_in,
+ drprdy_out => gt0_drprdy_out,
+ drpwe_in => gt0_drpwe_in,
+ ------------------------------- Clocking Ports -----------------------------
+ qpllclk_in => gt0_qpllclk_i,
+ qpllrefclk_in => gt0_qpllrefclk_i,
+ --------------------------- Digital Monitor Ports --------------------------
+ dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ eyescanreset_in => gt0_eyescanreset_in,
+ rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ eyescandataerror_out => gt0_eyescandataerror_out,
+ eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ rxusrclk_in => gt0_rxusrclk_in,
+ rxusrclk2_in => gt0_rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ rxdisperr_out => gt0_rxdisperr_out,
+ rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ rxdlyen_in => gt0_rxdlyen_in,
+ rxdlysreset_in => gt0_rxdlysreset_in,
+ rxdlysresetdone_out => gt0_rxdlysresetdone_out,
+ rxphalign_in => gt0_rxphalign_in,
+ rxphaligndone_out => gt0_rxphaligndone_out,
+ rxphalignen_in => gt0_rxphalignen_in,
+ rxphdlyreset_in => gt0_rxphdlyreset_in,
+ rxphmonitor_out => gt0_rxphmonitor_out,
+ rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ rxlpmhfhold_in => gt0_rxlpmhfhold_in,
+ rxlpmlfhold_in => gt0_rxlpmlfhold_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ rxmonitorout_out => gt0_rxmonitorout_out,
+ rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ rxoutclk_out => gt0_rxoutclk_out,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gtrxreset_in => gt0_gtrxreset_in,
+ rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gttxreset_in => gt0_gttxreset_in,
+ txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ txusrclk_in => gt0_txusrclk_in,
+ txusrclk2_in => gt0_txusrclk2_in,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ txdlyen_in => gt0_txdlyen_in,
+ txdlysreset_in => gt0_txdlysreset_in,
+ txdlysresetdone_out => gt0_txdlysresetdone_out,
+ txphalign_in => gt0_txphalign_in,
+ txphaligndone_out => gt0_txphaligndone_out,
+ txphalignen_in => gt0_txphalignen_in,
+ txphdlyreset_in => gt0_txphdlyreset_in,
+ txphinit_in => gt0_txphinit_in,
+ txphinitdone_out => gt0_txphinitdone_out,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gtxtxn_out => gt0_gtxtxn_out,
+ gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ txoutclk_out => gt0_txoutclk_out,
+ txoutclkfabric_out => gt0_txoutclkfabric_out,
+ txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ txresetdone_out => gt0_txresetdone_out
+
+ );
+
+
+ cpll_railing0_i : GTX_SODAinput_cpll_railing
+ generic map(
+ USE_BUFG => USE_BUFG
+ )
+ port map
+ (
+ cpll_reset_out => cpll_reset0_i,
+ cpll_pd_out => cpll_pd0_i,
+ refclk_out => open,
+ refclk_in => gt0_gtrefclk0_in
+);
+
+
+gt0_cpllreset_i <= cpll_reset0_i or gt0_cpllreset_in;
+gt0_cpllpd_i <= cpll_pd0_i ;
+end RTL;
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 3.5
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtx_sodainput_rx_startup_fsm.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+-- Description : This module performs RX reset and initialization.
+--
+--
+--
+-- Module GTX_SODAinput_rx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_SODAinput_RX_STARTUP_FSM is
+ Generic( EXAMPLE_SIMULATION : integer := 0;
+ EQ_MODE : string := "DFE"; --RX Equalisation Mode; set to DFE or LPM
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ RXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ RECCLK_STABLE : in STD_LOGIC;
+ RECCLK_MONITOR_RESTART : in STD_LOGIC:='0';
+ DATA_VALID : in STD_LOGIC;
+ TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
+ DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; --Used to control the Auto-Reset of FSM when Data Error is detected
+ GTRXRESET : out STD_LOGIC;
+ MMCM_RESET : out STD_LOGIC;
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
+ RX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
+ RXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC;
+ PHALIGNMENT_DONE : in STD_LOGIC;
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ RXDFEAGCHOLD : out STD_LOGIC;
+ RXDFELFHOLD : out STD_LOGIC;
+ RXLPMLFHOLD : out STD_LOGIC;
+ RXLPMHFHOLD : out STD_LOGIC;
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end GTX_SODAinput_RX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+-- are calculated at design-time based on the Generics
+--
+-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
+-- => signal which PLL has been reset
+-- *
+
+
+
+architecture RTL of GTX_SODAinput_RX_STARTUP_FSM is
+
+ component GTX_SODAinput_sync_block
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+ type rx_rst_fsm_type is(
+ INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
+ RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+ MONITOR_DATA_VALID, FSM_DONE);
+
+ signal rx_state : rx_rst_fsm_type := INIT;
+
+ constant MMCM_LOCK_CNT_MAX : integer := 256;
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+ constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
+ constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--500 us time-out
+ constant WAIT_TIMEOUT_1us : integer := 1000 / STABLE_CLOCK_PERIOD; --1 us time-out
+ constant WAIT_TIMEOUT_100us : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
+ constant WAIT_TIME_ADAPT : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD;
+ constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
+
+ signal init_wait_count : integer range 0 to WAIT_MAX:=0;
+ signal init_wait_done : std_logic := '0';
+ signal pll_reset_asserted : std_logic := '0';
+ signal rx_fsm_reset_done_int : std_logic := '0';
+ signal rx_fsm_reset_done_int_s2 : std_logic := '0';
+ signal rx_fsm_reset_done_int_s3 : std_logic := '0';
+
+ signal rxresetdone_s2 : std_logic := '0';
+ signal rxresetdone_s3 : std_logic := '0';
+
+ constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
+ signal retry_counter_int : integer range 0 to MAX_RETRIES := 0;
+ signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+ signal recclk_mon_restart_count : integer range 0 to 3:= 0;
+ signal recclk_mon_count_reset : std_logic := '0';
+
+ signal reset_time_out : std_logic := '0';
+ signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
+ signal time_tlock_max : std_logic := '0';--|have been reached.
+ signal time_out_500us : std_logic := '0';--|
+ signal time_out_1us : std_logic := '0';--/
+ signal time_out_100us : std_logic := '0';--/
+ signal check_tlock_max : std_logic := '0';
+
+ signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+ signal mmcm_lock_int : std_logic := '0';
+ signal mmcm_lock_i : std_logic := '0';
+ signal mmcm_lock_reclocked : std_logic := '0';
+ signal gtrxreset_i : std_logic := '0';
+ signal mmcm_reset_i : std_logic := '1';
+ signal rxpmaresetdone_i : std_logic := '0';
+ signal txpmaresetdone_i : std_logic := '0';
+ signal rxpmaresetdone_ss : std_logic := '0';
+ signal rxpmaresetdone_sync : std_logic ;
+ signal txpmaresetdone_sync : std_logic ;
+ signal rxpmaresetdone_s : std_logic ;
+ signal rxpmaresetdone_rx_s : std_logic ;
+ signal pmaresetdone_fallingedge_detect : std_logic ;
+ signal pmaresetdone_fallingedge_detect_s : std_logic ;
+
+ signal run_phase_alignment_int: std_logic := '0';
+ signal run_phase_alignment_int_s2 : std_logic := '0';
+ signal run_phase_alignment_int_s3 : std_logic := '0';
+
+ constant MAX_WAIT_BYPASS : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
+ signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
+ signal time_out_wait_bypass : std_logic := '0';
+ signal time_out_wait_bypass_s2 : std_logic := '0';
+ signal time_out_wait_bypass_s3 : std_logic := '0';
+
+ signal refclk_lost : std_logic;
+
+ signal time_out_adapt : std_logic := '0';
+ signal adapt_count_reset : std_logic := '0';
+ signal adapt_count : integer range 0 to WAIT_TIME_ADAPT-1;
+ signal data_valid_sync: std_logic := '0';
+ signal cplllock_sync: std_logic := '0';
+ signal qplllock_sync: std_logic := '0';
+ signal cplllock_prev: std_logic := '0';
+ signal qplllock_prev: std_logic := '0';
+ signal cplllock_ris_edge: std_logic := '0';
+ signal qplllock_ris_edge: std_logic := '0';
+ signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+ signal wait_time_done : std_logic;
+
+
+ attribute shreg_extract : string;
+ attribute ASYNC_REG : string;
+
+ signal reset_sync_reg1_tx : std_logic;
+ signal reset_sync_reg1 : std_logic;
+ signal gtrxreset_s : std_logic;
+ signal gtrxreset_tx_s : std_logic;
+ signal txpmaresetdone_s : std_logic;
+begin
+ --Alias section, signals used within this module mapped to output ports:
+ RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+ RUN_PHALIGNMENT <= run_phase_alignment_int;
+ RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
+ GTRXRESET <= gtrxreset_i;
+ MMCM_RESET <= mmcm_reset_i;
+ process(STABLE_CLOCK,SOFT_RESET)
+ begin
+ if (SOFT_RESET = '1') then
+ init_wait_done <= '0';
+ init_wait_count <= 0 ;
+ elsif rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+
+ adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
+ time_out_adapt <= '1';
+ end generate;
+
+ adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(adapt_count_reset = '1') then
+ adapt_count <= 0;
+ time_out_adapt <= '0';
+ elsif(adapt_count = WAIT_TIME_ADAPT -1) then
+ time_out_adapt <= '1';
+ else
+ adapt_count <= adapt_count + 1;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ retries_recclk_monitor:process(STABLE_CLOCK)
+ begin
+ --This counter monitors, how many retries the RECCLK monitor
+ --runs. If during startup too many retries are necessary, the whole
+ --initialisation-process of the transceivers gets restarted.
+ if rising_edge(STABLE_CLOCK) then
+ if recclk_mon_count_reset = '1' then
+ recclk_mon_restart_count <= 0;
+ elsif RECCLK_MONITOR_RESTART = '1' then
+ if recclk_mon_restart_count = 3 then
+ recclk_mon_restart_count <= 0;
+ else
+ recclk_mon_restart_count <= recclk_mon_restart_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ timeouts:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- One common large counter for generating three time-out signals.
+ -- Intermediate time-outs are derived from calculated values, based
+ -- on the period of the provided clock.
+ if reset_time_out = '1' then
+ time_out_counter <= 0;
+ time_out_2ms <= '0';
+ time_tlock_max <= '0';
+ time_out_500us <= '0';
+ time_out_1us <= '0';
+ time_out_100us <= '0';
+ else
+ if time_out_counter = WAIT_TIMEOUT_2ms then
+ time_out_2ms <= '1';
+ else
+ time_out_counter <= time_out_counter + 1;
+ end if;
+
+ if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
+ time_tlock_max <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_500us then
+ time_out_500us <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_1us then
+ time_out_1us <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_100us then
+ time_out_100us <= '1';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+
+
+ mmcm_lock_wait:process(STABLE_CLOCK)
+ begin
+ --The lock-signal from the MMCM is not immediately used but
+ --enabling a counter. Only when the counter hits its maximum,
+ --the MMCM is considered as "really" locked.
+ --The counter avoids that the FSM already starts on only a
+ --coarse lock of the MMCM (=toggling of the LOCK-signal).
+ if rising_edge(STABLE_CLOCK) then
+ if mmcm_lock_i = '0' then
+ mmcm_lock_count <= 0;
+ mmcm_lock_reclocked <= '0';
+ else
+ if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+ mmcm_lock_count <= mmcm_lock_count + 1;
+ else
+ mmcm_lock_reclocked <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ -- Clock Domain Crossing
+
+ sync_run_phase_alignment_int : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => RXUSERCLK,
+ data_in => run_phase_alignment_int,
+ data_out => run_phase_alignment_int_s2
+ );
+
+ sync_rx_fsm_reset_done_int : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => RXUSERCLK,
+ data_in => rx_fsm_reset_done_int,
+ data_out => rx_fsm_reset_done_int_s2
+ );
+
+ process(RXUSERCLK)
+ begin
+ if rising_edge(RXUSERCLK) then
+ run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
+
+ rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2;
+ end if;
+ end process;
+
+ sync_RXRESETDONE : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => RXRESETDONE,
+ data_out => rxresetdone_s2
+ );
+
+ sync_time_out_wait_bypass : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => time_out_wait_bypass,
+ data_out => time_out_wait_bypass_s2
+ );
+
+ sync_mmcm_lock_reclocked : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => MMCM_LOCK,
+ data_out => mmcm_lock_i
+ );
+
+ sync_data_valid : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => DATA_VALID,
+ data_out => data_valid_sync
+ );
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ rxresetdone_s3 <= rxresetdone_s2;
+
+ time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
+
+ cplllock_prev <= cplllock_sync;
+ qplllock_prev <= qplllock_sync;
+ end if;
+ end process;
+
+ sync_CPLLLOCK : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => CPLLLOCK,
+ data_out => cplllock_sync
+ );
+
+ sync_QPLLLOCK : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => QPLLLOCK,
+ data_out => qplllock_sync
+ );
+
+
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ cplllock_ris_edge <= '0';
+ elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+ cplllock_ris_edge <= '1';
+ elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+ cplllock_ris_edge <= cplllock_ris_edge;
+ else
+ cplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ qplllock_ris_edge <= '0';
+ elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+ qplllock_ris_edge <= '1';
+ elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+ qplllock_ris_edge <= qplllock_ris_edge;
+ else
+ qplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ timeout_buffer_bypass:process(RXUSERCLK)
+ begin
+ if rising_edge(RXUSERCLK) then
+ if run_phase_alignment_int_s3 = '0' then
+ wait_bypass_count <= 0;
+ time_out_wait_bypass <= '0';
+ elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
+ if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+ time_out_wait_bypass <= '1';
+ else
+ wait_bypass_count <= wait_bypass_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+
+ timeout_max:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if((rx_state = ASSERT_ALL_RESETS) or
+ (rx_state = RELEASE_MMCM_RESET)) then
+ wait_time_cnt <= WAIT_TIME_MAX;
+ elsif (wait_time_cnt > 0 ) then
+ wait_time_cnt <= wait_time_cnt - 1;
+ end if;
+ end if;
+ end process;
+
+ wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+
+ --FSM for resetting the GTX/GTH/GTP in the 7-series.
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ --
+ -- Following steps are performed:
+ -- 1) After configuration wait for approximately 500 ns as specified in
+ -- answer-record 43482
+ -- 2) Assert all resets on the GT and on an MMCM potentially connected.
+ -- After that wait until a reference-clock has been detected.
+ -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+ -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+ -- Also get info from the TX-side which PLL has been reset.
+ -- 5) Wait for the RESET_DONE-signal from the GT.
+ -- 6) Signal to start the phase-alignment procedure and wait for it to
+ -- finish.
+ -- 7) Reset-sequence has successfully run through. Signal this to the
+ -- rest of the design by asserting RX_FSM_RESET_DONE.
+
+ reset_fsm:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if (SOFT_RESET = '1' ) then
+ --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+ rx_state <= INIT;
+ RXUSERRDY <= '0';
+ gtrxreset_i <= '0';
+ mmcm_reset_i <= '0';
+ rx_fsm_reset_done_int <= '0';
+ QPLL_RESET <= '0';
+ CPLL_RESET <= '0';
+ pll_reset_asserted <= '0';
+ reset_time_out <= '1';
+ retry_counter_int <= 0;
+ run_phase_alignment_int <= '0';
+ check_tlock_max <= '0';
+ RESET_PHALIGNMENT <= '1';
+ recclk_mon_count_reset <= '1';
+ adapt_count_reset <= '1';
+ RXDFEAGCHOLD <= '0';
+ RXDFELFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ RXLPMHFHOLD <= '0';
+
+ else
+
+ case rx_state is
+ when INIT =>
+ --Initial state after configuration. This state will be left after
+ --approx. 500 ns and not be re-entered.
+ if init_wait_done = '1' then
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when ASSERT_ALL_RESETS =>
+ --This is the state into which the FSM will always jump back if any
+ --time-outs will occur.
+ --The number of retries is reported on the output RETRY_COUNTER. In
+ --case the transceiver never comes up for some reason, this machine
+ --will still continue its best and rerun until the FPGA is turned off
+ --or the transceivers come up correctly.
+ if RX_QPLL_USED and not TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ QPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ QPLL_RESET <= '0';
+ end if;
+ elsif not RX_QPLL_USED and TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ CPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ CPLL_RESET <= '0';
+ end if;
+ end if;
+
+ RXUSERRDY <= '0';
+ gtrxreset_i <= '1';
+ mmcm_reset_i <= '1';
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+ check_tlock_max <= '0';
+ recclk_mon_count_reset <= '1';
+ adapt_count_reset <= '1';
+
+ if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+ (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '0') and pll_reset_asserted = '1') or
+ (not RX_QPLL_USED and not TX_QPLL_USED ) or
+ (RX_QPLL_USED and TX_QPLL_USED ) then
+ rx_state <= WAIT_FOR_PLL_LOCK;
+ reset_time_out <= '1';
+ end if;
+
+ when WAIT_FOR_PLL_LOCK =>
+ if(wait_time_done = '1') then
+ rx_state <= RELEASE_PLL_RESET;
+ end if;
+
+ when RELEASE_PLL_RESET =>
+ --PLL-Reset of the GTX gets released and the time-out counter
+ --starts running.
+ pll_reset_asserted <= '0';
+ reset_time_out <= '0';
+
+ if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '1')) or
+ (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '1')) then
+ rx_state <= VERIFY_RECCLK_STABLE;
+ reset_time_out <= '1';
+ recclk_mon_count_reset <= '0';
+ adapt_count_reset <= '0';
+ elsif (RX_QPLL_USED and (qplllock_sync = '1')) or
+ (not RX_QPLL_USED and (cplllock_sync = '1')) then
+ rx_state <= VERIFY_RECCLK_STABLE;
+ reset_time_out <= '1';
+ recclk_mon_count_reset <= '0';
+ adapt_count_reset <= '0';
+ end if;
+
+ if time_out_2ms = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when VERIFY_RECCLK_STABLE =>
+ --reset_time_out <= '0';
+ --Time-out counter is not released in this state as here the FSM
+ --does not wait for a certain period of time but checks on the number
+ --of retries in the RECCLK monitor
+ gtrxreset_i <= '0';
+ if RECCLK_STABLE = '1' then
+ rx_state <= RELEASE_MMCM_RESET;
+ reset_time_out <= '1';
+
+ end if;
+
+ if recclk_mon_restart_count = 2 then
+ --If two retries are performed in the RECCLK monitor
+ --the whole initialisation-sequence gets restarted.
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when RELEASE_MMCM_RESET =>
+ --Release of the MMCM-reset. Waiting for the MMCM to lock.
+ check_tlock_max <= '1';
+
+ mmcm_reset_i <= '0';
+ reset_time_out <= '0';
+
+ if mmcm_lock_reclocked = '1' then
+ rx_state <= WAIT_FOR_RXUSRCLK;
+ reset_time_out <= '1';
+ end if;
+
+ if (time_tlock_max = '1' and reset_time_out = '0' )then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_FOR_RXUSRCLK =>
+ if wait_time_done = '1' then
+ rx_state <= WAIT_RESET_DONE;
+ end if;
+
+ when WAIT_RESET_DONE =>
+ --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
+ --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
+ if TXUSERRDY = '1' then
+ RXUSERRDY <= '1';
+ end if;
+ reset_time_out <= '0';
+ if rxresetdone_s3 = '1' then
+ rx_state <= DO_PHASE_ALIGNMENT;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_2ms = '1' and reset_time_out = '0' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when DO_PHASE_ALIGNMENT =>
+ --The direct handling of the signals for the Phase Alignment is done outside
+ --this state-machine.
+ RESET_PHALIGNMENT <= '0';
+ run_phase_alignment_int <= '1';
+ reset_time_out <= '0';
+
+ if PHALIGNMENT_DONE = '1' then
+ rx_state <= MONITOR_DATA_VALID;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_wait_bypass_s3 = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when MONITOR_DATA_VALID =>
+ reset_time_out <= '0';
+
+ if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0') then
+ rx_state <= ASSERT_ALL_RESETS;
+ rx_fsm_reset_done_int <= '0';
+ elsif (data_valid_sync = '1') then
+ rx_state <= FSM_DONE;
+ rx_fsm_reset_done_int <= '0';
+ reset_time_out <= '1';
+ end if;
+
+ when FSM_DONE =>
+ reset_time_out <= '0';
+ if data_valid_sync = '0' then
+ rx_fsm_reset_done_int <= '0';
+ reset_time_out <= '1';
+ rx_state <= MONITOR_DATA_VALID;
+
+ elsif(time_out_1us = '1' and reset_time_out = '0') then
+ rx_fsm_reset_done_int <= '1';
+ end if;
+
+ if(time_out_adapt = '1') then
+ if(EQ_MODE = "DFE") then
+ RXDFEAGCHOLD <= '1';
+ RXDFELFHOLD <= '1';
+ RXLPMHFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ else
+ RXDFEAGCHOLD <= '0';
+ RXDFELFHOLD <= '0';
+ RXLPMHFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ end if;
+ end if;
+ when OTHERS =>
+ rx_state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
+
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 3.5
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtx_sodainput_sync_block.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+--
+-- Description: Used on signals crossing from one clock domain to
+-- another, this is a flip-flop pair, with both flops
+-- placed together with RLOCs into the same slice. Thus
+-- the routing delay between the two is minimum to safe-
+-- guard against metastability issues.
+--
+--
+-- Module GTX_SODAinput_sync_block
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_SODAinput_sync_block is
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic; -- clock to be sync'ed to
+ data_in : in std_logic; -- Data to be 'synced'
+ data_out : out std_logic -- synced data
+ );
+
+-- attribute dont_touch : string;
+-- attribute dont_touch of GTX_SODAinput_sync_block : entity is "yes";
+
+end GTX_SODAinput_sync_block;
+
+
+architecture structural of GTX_SODAinput_sync_block is
+
+
+ -- Internal Signals
+ signal data_sync1 : std_logic;
+ signal data_sync2 : std_logic;
+ signal data_sync3 : std_logic;
+ signal data_sync4 : std_logic;
+ signal data_sync5 : std_logic;
+
+ -- These attributes will stop timing errors being reported in back annotated
+ -- SDF simulation.
+ attribute ASYNC_REG : string;
+ attribute ASYNC_REG of data_sync_reg1 : label is "true";
+ attribute ASYNC_REG of data_sync_reg2 : label is "true";
+ attribute ASYNC_REG of data_sync_reg3 : label is "true";
+ attribute ASYNC_REG of data_sync_reg4 : label is "true";
+ attribute ASYNC_REG of data_sync_reg5 : label is "true";
+ attribute ASYNC_REG of data_sync_reg6 : label is "true";
+
+ -- These attributes will stop XST translating the desired flip-flops into an
+ -- SRL based shift register.
+ attribute shreg_extract : string;
+ attribute shreg_extract of data_sync_reg1 : label is "no";
+ attribute shreg_extract of data_sync_reg2 : label is "no";
+ attribute shreg_extract of data_sync_reg3 : label is "no";
+ attribute shreg_extract of data_sync_reg4 : label is "no";
+ attribute shreg_extract of data_sync_reg5 : label is "no";
+ attribute shreg_extract of data_sync_reg6 : label is "no";
+
+
+begin
+
+ data_sync_reg1 : FD
+ generic map (
+ INIT => INITIALISE(0)
+ )
+ port map (
+ C => clk,
+ D => data_in,
+ Q => data_sync1
+ );
+
+ data_sync_reg2 : FD
+ generic map (
+ INIT => INITIALISE(1)
+ )
+ port map (
+ C => clk,
+ D => data_sync1,
+ Q => data_sync2
+ );
+
+ data_sync_reg3 : FD
+ generic map (
+ INIT => INITIALISE(2)
+ )
+ port map (
+ C => clk,
+ D => data_sync2,
+ Q => data_sync3
+ );
+
+ data_sync_reg4 : FD
+ generic map (
+ INIT => INITIALISE(3)
+ )
+ port map (
+ C => clk,
+ D => data_sync3,
+ Q => data_sync4
+ );
+
+ data_sync_reg5 : FD
+ generic map (
+ INIT => INITIALISE(4)
+ )
+ port map (
+ C => clk,
+ D => data_sync4,
+ Q => data_sync5
+ );
+
+ data_sync_reg6 : FD
+ generic map (
+ INIT => INITIALISE(5)
+ )
+ port map (
+ C => clk,
+ D => data_sync5,
+ Q => data_out
+ );
+
+
+
+end structural;
+
+
--- /dev/null
+--//////////////////////////////////////////////////////////////////////////////
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename :gtx_sodainput_tx_startup_fsm.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module GTX_SODAinput_tx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity GTX_SODAinput_TX_STARTUP_FSM is
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ TXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ GTTXRESET : out STD_LOGIC;
+ MMCM_RESET : out STD_LOGIC:='1';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
+ TX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
+ TXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC:='0';
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ PHALIGNMENT_DONE : in STD_LOGIC;
+
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end GTX_SODAinput_TX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+-- are calculated at design-time based on the Generics
+--
+-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
+-- => signal which PLL has been reset
+-- *
+
+
+
+architecture RTL of GTX_SODAinput_TX_STARTUP_FSM is
+
+ component GTX_SODAinput_sync_block
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ type tx_rst_fsm_type is(
+ INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET,
+ WAIT_FOR_TXOUTCLK, RELEASE_MMCM_RESET, WAIT_FOR_TXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+ RESET_FSM_DONE);
+
+ signal tx_state : tx_rst_fsm_type := INIT;
+
+ constant MMCM_LOCK_CNT_MAX : integer := 256;
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+ constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
+ constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_1us_cycles : integer := 1000 / STABLE_CLOCK_PERIOD;--1 us time-out
+ constant WAIT_1us : integer := WAIT_1us_cycles+ 10; -- 1us plus some additional margin
+
+ signal init_wait_count : integer range 0 to WAIT_MAX:=0;
+ signal init_wait_done : std_logic := '0';
+ signal pll_reset_asserted : std_logic := '0';
+
+ signal tx_fsm_reset_done_int : std_logic := '0';
+ signal tx_fsm_reset_done_int_s2 : std_logic := '0';
+ signal tx_fsm_reset_done_int_s3 : std_logic := '0';
+
+ signal txresetdone_s2 : std_logic := '0';
+ signal txresetdone_s3 : std_logic := '0';
+
+ constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
+ signal retry_counter_int : integer range 0 to MAX_RETRIES;
+ signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+
+ signal reset_time_out : std_logic := '0';
+ signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
+ signal time_tlock_max : std_logic := '0';--|have been reached.
+ signal time_out_500us : std_logic := '0';--/
+
+ signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+ signal mmcm_lock_int : std_logic := '0';
+ signal mmcm_lock_i : std_logic := '0';
+ signal mmcm_lock_reclocked : std_logic := '0';
+
+ signal run_phase_alignment_int : std_logic := '0';
+ signal run_phase_alignment_int_s2 : std_logic := '0';
+ signal run_phase_alignment_int_s3 : std_logic := '0';
+ constant MAX_WAIT_BYPASS : integer := 45824; --110000 TXUSRCLK cycles is the max time for Multi lane designs
+
+ constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
+
+ signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
+ signal time_out_wait_bypass : std_logic := '0';
+ signal time_out_wait_bypass_s2 : std_logic := '0';
+ signal time_out_wait_bypass_s3 : std_logic := '0';
+ signal txuserrdy_i : std_logic := '0';
+ signal refclk_lost : std_logic;
+ signal gttxreset_i : std_logic := '0';
+ signal txpmaresetdone_i : std_logic := '0';
+ signal txpmaresetdone_sync : std_logic ;
+
+ signal cplllock_sync: std_logic := '0';
+ signal qplllock_sync: std_logic := '0';
+ signal cplllock_prev: std_logic := '0';
+ signal qplllock_prev: std_logic := '0';
+ signal cplllock_ris_edge: std_logic := '0';
+ signal qplllock_ris_edge: std_logic := '0';
+ signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+ signal wait_time_done :std_logic;
+
+begin
+ --Alias section, signals used within this module mapped to output ports:
+ RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+ RUN_PHALIGNMENT <= run_phase_alignment_int;
+ TX_FSM_RESET_DONE <= tx_fsm_reset_done_int;
+ GTTXRESET <= gttxreset_i;
+
+ process(STABLE_CLOCK,SOFT_RESET)
+ begin
+ if (SOFT_RESET = '1') then
+ init_wait_done <= '0';
+ init_wait_count <= 0 ;
+ elsif rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ timeouts:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- One common large counter for generating three time-out signals.
+ -- Intermediate time-outs are derived from calculated values, based
+ -- on the period of the provided clock.
+ if reset_time_out = '1' then
+ time_out_counter <= 0;
+ time_out_2ms <= '0';
+ time_tlock_max <= '0';
+ time_out_500us <= '0';
+ else
+ if time_out_counter = WAIT_TIMEOUT_2ms then
+ time_out_2ms <= '1';
+ else
+ time_out_counter <= time_out_counter + 1;
+ end if;
+
+ if time_out_counter = WAIT_TLOCK_MAX then
+ time_tlock_max <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_500us then
+ time_out_500us <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ mmcm_lock_wait:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if mmcm_lock_i = '0' then
+ mmcm_lock_count <= 0;
+ mmcm_lock_reclocked <= '0';
+ else
+ if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+ mmcm_lock_count <= mmcm_lock_count + 1;
+ else
+ mmcm_lock_reclocked <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+
+ -- Clock Domain Crossing
+
+ sync_run_phase_alignment_int : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => TXUSERCLK,
+ data_in => run_phase_alignment_int,
+ data_out => run_phase_alignment_int_s2
+ );
+
+ sync_tx_fsm_reset_done_int : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => TXUSERCLK,
+ data_in => tx_fsm_reset_done_int,
+ data_out => tx_fsm_reset_done_int_s2
+ );
+
+ process(TXUSERCLK)
+ begin
+ if rising_edge(TXUSERCLK) then
+ run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
+
+ tx_fsm_reset_done_int_s3 <= tx_fsm_reset_done_int_s2;
+ end if;
+ end process;
+
+ sync_TXRESETDONE : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => TXRESETDONE,
+ data_out => txresetdone_s2
+ );
+
+ sync_time_out_wait_bypass : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => time_out_wait_bypass,
+ data_out => time_out_wait_bypass_s2
+ );
+
+ sync_mmcm_lock_reclocked : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => MMCM_LOCK,
+ data_out => mmcm_lock_i
+ );
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ txresetdone_s3 <= txresetdone_s2;
+
+ time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
+
+ cplllock_prev <= cplllock_sync;
+ qplllock_prev <= qplllock_sync;
+ end if;
+ end process;
+
+ sync_CPLLLOCK : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => CPLLLOCK,
+ data_out => cplllock_sync
+ );
+
+ sync_QPLLLOCK : GTX_SODAinput_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => QPLLLOCK,
+ data_out => qplllock_sync
+ );
+
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ cplllock_ris_edge <= '0';
+ elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+ cplllock_ris_edge <= '1';
+ elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+ cplllock_ris_edge <= cplllock_ris_edge;
+ else
+ cplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ qplllock_ris_edge <= '0';
+ elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+ qplllock_ris_edge <= '1';
+ elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+ qplllock_ris_edge <= qplllock_ris_edge;
+ else
+ qplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+
+
+ timeout_buffer_bypass:process(TXUSERCLK)
+ begin
+ if rising_edge(TXUSERCLK) then
+ if run_phase_alignment_int_s3 = '0' then
+ wait_bypass_count <= 0;
+ time_out_wait_bypass <= '0';
+ elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0') then
+ if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+ time_out_wait_bypass <= '1';
+ else
+ wait_bypass_count <= wait_bypass_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+ timeout_max:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if((tx_state = ASSERT_ALL_RESETS) or
+ (tx_state = RELEASE_PLL_RESET) or
+ (tx_state = RELEASE_MMCM_RESET)) then
+ wait_time_cnt <= WAIT_TIME_MAX;
+ elsif (wait_time_cnt > 0 ) then
+ wait_time_cnt <= wait_time_cnt - 1;
+ end if;
+ end if;
+ end process;
+
+ wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+
+ --FSM for resetting the GTX/GTH/GTP in the 7-series.
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ --
+ -- Following steps are performed:
+ -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in
+ -- answer-record 43482
+ -- 2) Assert all resets on the GT and on an MMCM potentially connected.
+ -- After that wait until a reference-clock has been detected.
+ -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+ -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+ -- Also signal to the RX-side which PLL has been reset.
+ -- 5) Wait for the RESET_DONE-signal from the GT.
+ -- 6) Signal to start the phase-alignment procedure and wait for it to
+ -- finish.
+ -- 7) Reset-sequence has successfully run through. Signal this to the
+ -- rest of the design by asserting TX_FSM_RESET_DONE.
+
+ reset_fsm:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ --if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+ tx_state <= INIT;
+ TXUSERRDY <= '0';
+ gttxreset_i <= '0';
+ MMCM_RESET <= '0';
+ tx_fsm_reset_done_int <= '0';
+ QPLL_RESET <= '0';
+ CPLL_RESET <= '0';
+ pll_reset_asserted <= '0';
+ reset_time_out <= '0';
+ retry_counter_int <= 0;
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+ else
+
+ case tx_state is
+ when INIT =>
+ --Initial state after configuration. This state will be left after
+ --approx. 500 ns and not be re-entered.
+ if init_wait_done = '1' then
+ tx_state <= ASSERT_ALL_RESETS;
+ reset_time_out <= '1';
+ end if;
+
+ when ASSERT_ALL_RESETS =>
+ --This is the state into which the FSM will always jump back if any
+ --time-outs will occur.
+ --The number of retries is reported on the output RETRY_COUNTER. In
+ --case the transceiver never comes up for some reason, this machine
+ --will still continue its best and rerun until the FPGA is turned off
+ --or the transceivers come up correctly.
+ if TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ QPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ QPLL_RESET <= '0';
+ end if;
+ else
+ if pll_reset_asserted = '0' then
+ CPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ CPLL_RESET <= '0';
+ end if;
+ end if;
+ TXUSERRDY <= '0';
+ gttxreset_i <= '1';
+ MMCM_RESET <= '1';
+ reset_time_out <= '1';
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+
+ if (TX_QPLL_USED and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+ (not TX_QPLL_USED and (cplllock_sync = '0') and pll_reset_asserted = '1') then
+ tx_state <= WAIT_FOR_PLL_LOCK;
+ end if;
+
+ when WAIT_FOR_PLL_LOCK =>
+ if(wait_time_done = '1') then
+ tx_state <= RELEASE_PLL_RESET;
+ end if;
+
+ when RELEASE_PLL_RESET =>
+ --PLL-Reset of the GTX gets released and the time-out counter
+ --starts running.
+ pll_reset_asserted <= '0';
+
+ if (TX_QPLL_USED and (qplllock_sync = '1')) or
+ (not TX_QPLL_USED and (cplllock_sync = '1')) then
+ tx_state <= WAIT_FOR_TXOUTCLK;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_2ms = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_FOR_TXOUTCLK =>
+ gttxreset_i <= '0';
+ if(wait_time_done = '1') then
+ tx_state <= RELEASE_MMCM_RESET;
+ end if;
+
+ when RELEASE_MMCM_RESET =>
+ --Release of the MMCM-reset. Waiting for the MMCM to lock.
+ MMCM_RESET <= '0';
+ reset_time_out <= '0';
+ if mmcm_lock_reclocked = '1' then
+ tx_state <= WAIT_FOR_TXUSRCLK;
+ reset_time_out <= '1';
+ end if;
+
+ if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0') then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_FOR_TXUSRCLK =>
+ if(wait_time_done = '1') then
+ tx_state <= WAIT_RESET_DONE;
+ end if;
+
+ when WAIT_RESET_DONE =>
+ TXUSERRDY <= '1';
+ reset_time_out <= '0';
+ if txresetdone_s3 = '1' then
+ tx_state <= DO_PHASE_ALIGNMENT;
+ reset_time_out <= '1';
+ end if;
+
+ if (time_out_500us = '1' and reset_time_out = '0') then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when DO_PHASE_ALIGNMENT =>
+ --The direct handling of the signals for the Phase Alignment is done outside
+ --this state-machine.
+ RESET_PHALIGNMENT <= '0';
+ run_phase_alignment_int <= '1';
+ reset_time_out <= '0';
+
+ if PHALIGNMENT_DONE = '1' then
+ tx_state <= RESET_FSM_DONE;
+ end if;
+
+ if time_out_wait_bypass_s3 = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when RESET_FSM_DONE =>
+ reset_time_out <= '1';
+ tx_fsm_reset_done_int <= '1';
+
+ when OTHERS =>
+ tx_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
--- file: clockmodule40switch.vhd\r
--- \r
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
--- \r
-------------------------------------------------------------------------------\r
--- User entered comments\r
-------------------------------------------------------------------------------\r
--- None\r
---\r
-------------------------------------------------------------------------------\r
--- "Output Output Phase Duty Pk-to-Pk Phase"\r
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
-------------------------------------------------------------------------------\r
--- CLK_OUT1____40.000______0.000______50.0______247.096____196.976\r
--- CLK_OUT2____80.000______0.000______50.0______200.412____196.976\r
---\r
-------------------------------------------------------------------------------\r
--- "Input Clock Freq (MHz) Input Jitter (UI)"\r
-------------------------------------------------------------------------------\r
--- __primary______________40____________0.010\r
--- _secondary____________40____________0.010\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.numeric_std.all;\r
-\r
-library unisim;\r
-use unisim.vcomponents.all;\r
-\r
-entity clockmodule40switch is\r
-port\r
- (-- Clock in ports\r
- CLK_IN1 : in std_logic;\r
- CLK_IN2 : in std_logic;\r
- CLK_IN_SEL : in std_logic;\r
- -- Clock out ports\r
- CLK_OUT1 : out std_logic;\r
- CLK_OUT2 : out std_logic;\r
- -- Status and control signals\r
- RESET : in std_logic;\r
- LOCKED : out std_logic\r
- );\r
-end clockmodule40switch;\r
-\r
-architecture xilinx of clockmodule40switch is\r
- attribute CORE_GENERATION_INFO : string;\r
- attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule40switch,clk_wiz_v3_6,{component_name=clockmodule40switch,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=true,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=25.000,clkin2_period=25.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";\r
- -- Input clock buffering / unused connectors\r
- signal clkin1 : std_logic;\r
- signal clkin2 : std_logic;\r
- -- Output clock buffering / unused connectors\r
- signal clkfbout : std_logic;\r
- signal clkfbout_buf : std_logic;\r
- signal clkfboutb_unused : std_logic;\r
- signal clkout0 : std_logic;\r
- signal clkout0b_unused : std_logic;\r
- signal clkout1 : std_logic;\r
- signal clkout1b_unused : std_logic;\r
- signal clkout2_unused : std_logic;\r
- signal clkout2b_unused : std_logic;\r
- signal clkout3_unused : std_logic;\r
- signal clkout3b_unused : std_logic;\r
- signal clkout4_unused : std_logic;\r
- signal clkout5_unused : std_logic;\r
- signal clkout6_unused : std_logic;\r
- -- Dynamic programming unused signals\r
- signal do_unused : std_logic_vector(15 downto 0);\r
- signal drdy_unused : std_logic;\r
- -- Dynamic phase shift unused signals\r
- signal psdone_unused : std_logic;\r
- -- Unused status signals\r
- signal clkfbstopped_unused : std_logic;\r
- signal clkinstopped_unused : std_logic;\r
-begin\r
-\r
-\r
- -- Input buffering\r
- --------------------------------------\r
- clkin1_buf : BUFG\r
- port map\r
- (O => clkin1,\r
- I => CLK_IN1);\r
-\r
- clkin2_buf : BUFG\r
- port map\r
- (O => clkin2,\r
- I => CLK_IN2);\r
-\r
- -- Clocking primitive\r
- --------------------------------------\r
- -- Instantiation of the MMCM primitive\r
- -- * Unused inputs are tied off\r
- -- * Unused outputs are labeled unused\r
- mmcm_adv_inst : MMCM_ADV\r
- generic map\r
- (BANDWIDTH => "OPTIMIZED",\r
- CLKOUT4_CASCADE => FALSE,\r
- CLOCK_HOLD => FALSE,\r
- COMPENSATION => "ZHOLD",\r
- STARTUP_WAIT => FALSE,\r
- DIVCLK_DIVIDE => 1,\r
- CLKFBOUT_MULT_F => 24.000,\r
- CLKFBOUT_PHASE => 0.000,\r
- CLKFBOUT_USE_FINE_PS => FALSE,\r
- CLKOUT0_DIVIDE_F => 24.000,\r
- CLKOUT0_PHASE => 0.000,\r
- CLKOUT0_DUTY_CYCLE => 0.500,\r
- CLKOUT0_USE_FINE_PS => FALSE,\r
- CLKOUT1_DIVIDE => 12,\r
- CLKOUT1_PHASE => 0.000,\r
- CLKOUT1_DUTY_CYCLE => 0.500,\r
- CLKOUT1_USE_FINE_PS => FALSE,\r
- CLKIN1_PERIOD => 25.000,\r
- REF_JITTER1 => 0.010,\r
- CLKIN2_PERIOD => 25.000,\r
- REF_JITTER2 => 0.010)\r
- port map\r
- -- Output clocks\r
- (CLKFBOUT => clkfbout,\r
- CLKFBOUTB => clkfboutb_unused,\r
- CLKOUT0 => clkout0,\r
- CLKOUT0B => clkout0b_unused,\r
- CLKOUT1 => clkout1,\r
- CLKOUT1B => clkout1b_unused,\r
- CLKOUT2 => clkout2_unused,\r
- CLKOUT2B => clkout2b_unused,\r
- CLKOUT3 => clkout3_unused,\r
- CLKOUT3B => clkout3b_unused,\r
- CLKOUT4 => clkout4_unused,\r
- CLKOUT5 => clkout5_unused,\r
- CLKOUT6 => clkout6_unused,\r
- -- Input clock control\r
- CLKFBIN => clkfbout_buf,\r
- CLKIN1 => clkin1,\r
- CLKIN2 => clkin2,\r
- CLKINSEL => CLK_IN_SEL,\r
- -- Ports for dynamic reconfiguration\r
- DADDR => (others => '0'),\r
- DCLK => '0',\r
- DEN => '0',\r
- DI => (others => '0'),\r
- DO => do_unused,\r
- DRDY => drdy_unused,\r
- DWE => '0',\r
- -- Ports for dynamic phase shift\r
- PSCLK => '0',\r
- PSEN => '0',\r
- PSINCDEC => '0',\r
- PSDONE => psdone_unused,\r
- -- Other control and status signals\r
- LOCKED => LOCKED,\r
- CLKINSTOPPED => clkinstopped_unused,\r
- CLKFBSTOPPED => clkfbstopped_unused,\r
- PWRDWN => '0',\r
- RST => RESET);\r
-\r
- -- Output buffering\r
- -------------------------------------\r
- clkf_buf : BUFG\r
- port map\r
- (O => clkfbout_buf,\r
- I => clkfbout);\r
-\r
-\r
- clkout1_buf : BUFG\r
- port map\r
- (O => CLK_OUT1,\r
- I => clkout0);\r
-\r
-\r
-\r
- clkout2_buf : BUFG\r
- port map\r
- (O => CLK_OUT2,\r
- I => clkout1);\r
-\r
-end xilinx;\r
+-- file: clk_wiz_v2_1.vhd
+--
+-- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1 100.000 0.000 50.000 130.958 98.575
+-- CLK_OUT2 200.000 0.000 50.000 114.829 98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock Input Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary 100.000 0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_SODAinput_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end GTX_SODAinput_CLOCK_MODULE;
+
+architecture xilinx of GTX_SODAinput_CLOCK_MODULE is
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of xilinx : architecture is "GTX_SODAinput,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+ -- Input clock buffering / unused connectors
+ signal clkin1 : std_logic;
+ -- Output clock buffering / unused connectors
+ signal clkfbout : std_logic;
+ signal clkfbout_buf : std_logic;
+ signal clkfboutb_unused : std_logic;
+ signal clkout0 : std_logic;
+ signal clkout0b_unused : std_logic;
+ signal clkout1 : std_logic;
+ signal clkout1b_unused : std_logic;
+ signal clkout2 : std_logic;
+ signal clkout2b_unused : std_logic;
+ signal clkout3 : std_logic;
+ signal clkout3b_unused : std_logic;
+ signal clkout4_unused : std_logic;
+ signal clkout5_unused : std_logic;
+ signal clkout6_unused : std_logic;
+ -- Dynamic programming unused signals
+ signal do_unused : std_logic_vector(15 downto 0);
+ signal drdy_unused : std_logic;
+ -- Dynamic phase shift unused signals
+ signal psdone_unused : std_logic;
+ -- Unused status signals
+ signal clkfbstopped_unused : std_logic;
+ signal clkinstopped_unused : std_logic;
+begin
+
+
+ -- Input buffering
+ --------------------------------------
+ clkin1_buf : BUFG
+ port map
+ (O => clkin1,
+ I => CLK_IN);
+
+ -- Clocking primitive
+ --------------------------------------
+ -- Instantiation of the MMCM primitive
+ -- * Unused inputs are tied off
+ -- * Unused outputs are labeled unused
+
+ mmcm_adv_inst : MMCME2_ADV
+ generic map
+ (BANDWIDTH => "OPTIMIZED",
+ CLKOUT4_CASCADE => FALSE,
+ COMPENSATION => "ZHOLD",
+ STARTUP_WAIT => FALSE,
+ DIVCLK_DIVIDE => DIVIDE,
+ CLKFBOUT_MULT_F => MULT,
+ CLKFBOUT_PHASE => 0.000,
+ CLKFBOUT_USE_FINE_PS => FALSE,
+ CLKOUT0_DIVIDE_F => OUT0_DIVIDE,
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKOUT0_USE_FINE_PS => FALSE,
+ CLKIN1_PERIOD => CLK_PERIOD,
+ CLKOUT1_DIVIDE => OUT1_DIVIDE,
+ CLKOUT1_PHASE => 0.000,
+ CLKOUT1_DUTY_CYCLE => 0.500,
+ CLKOUT1_USE_FINE_PS => FALSE,
+ CLKOUT2_DIVIDE => OUT2_DIVIDE,
+ CLKOUT2_PHASE => 0.000,
+ CLKOUT2_DUTY_CYCLE => 0.500,
+ CLKOUT2_USE_FINE_PS => FALSE,
+ CLKOUT3_DIVIDE => OUT3_DIVIDE,
+ CLKOUT3_PHASE => 0.000,
+ CLKOUT3_DUTY_CYCLE => 0.500,
+ CLKOUT3_USE_FINE_PS => FALSE,
+ REF_JITTER1 => 0.010)
+ port map
+ -- Output clocks
+ (CLKFBOUT => clkfbout,
+ CLKFBOUTB => clkfboutb_unused,
+ CLKOUT0 => clkout0,
+ CLKOUT0B => clkout0b_unused,
+ CLKOUT1 => clkout1,
+ CLKOUT1B => clkout1b_unused,
+ CLKOUT2 => clkout2,
+ CLKOUT2B => clkout2b_unused,
+ CLKOUT3 => clkout3,
+ CLKOUT3B => clkout3b_unused,
+ CLKOUT4 => clkout4_unused,
+ CLKOUT5 => clkout5_unused,
+ CLKOUT6 => clkout6_unused,
+ -- Input clock control
+ CLKFBIN => clkfbout,
+ CLKIN1 => clkin1,
+ CLKIN2 => '0',
+ -- Tied to always select the primary input clock
+ CLKINSEL => '1',
+ -- Ports for dynamic reconfiguration
+ DADDR => (others => '0'),
+ DCLK => '0',
+ DEN => '0',
+ DI => (others => '0'),
+ DO => do_unused,
+ DRDY => drdy_unused,
+ DWE => '0',
+ -- Ports for dynamic phase shift
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ PSDONE => psdone_unused,
+ -- Other control and status signals
+ LOCKED => MMCM_LOCKED_OUT,
+ CLKINSTOPPED => clkinstopped_unused,
+ CLKFBSTOPPED => clkfbstopped_unused,
+ PWRDWN => '0',
+ RST => MMCM_RESET_IN);
+
+ -- Output buffering
+ -------------------------------------
+ --clkf_buf : BUFG
+ --port map
+ -- (O => clkfbout_buf,
+ -- I => clkfbout);
+
+
+ clkout0_buf : BUFG
+ port map
+ (O => CLK0_OUT,
+ I => clkout0);
+
+ clkout1_buf : BUFG
+ port map
+ (O => CLK1_OUT,
+ I => clkout1);
+
+-- clkout2_buf : BUFG
+-- port map
+-- (O => CLK2_OUT,
+-- I => clkout2);
+--
+-- clkout3_buf : BUFG
+-- port map
+-- (O => CLK3_OUT,
+-- I => clkout3);
+
+CLK2_OUT <= '0';
+CLK3_OUT <= '0';
+end xilinx;
--- /dev/null
+---------------------------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput_common.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_SODAinput_common
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_SODAinput_common is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
+ SIM_QPLLREFCLK_SEL : bit_vector := "001"
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK1_IN : in std_logic;
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+);
+
+end GTX_SODAinput_common;
+
+architecture RTL of GTX_SODAinput_common is
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_SODAinput_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_TOP : integer := 16;
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
+
+begin
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+
+ gtxe2_common_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
+ SIM_VERSION => "4.0",
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (1)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GTREFCLK0_IN,
+ GTREFCLK1 => GTREFCLK1_IN,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports -----------------------
+ QPLLDMONITOR => open,
+ ----------------------- Common Block - Clocking Ports ----------------------
+ QPLLOUTCLK => QPLLOUTCLK_OUT,
+ QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
+ REFCLKOUTMONITOR => open,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => QPLLLOCK_OUT,
+ QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_vcc_i,
+ QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
+ QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
+ QPLLRESET => QPLLRESET_IN,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ --------------------------------- QPLL Ports -------------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "11111",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+end RTL;
--- /dev/null
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput_common_reset.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module GTX_SODAinput_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_SODAinput_common_reset is
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic:= '0' --Reset QPLL
+ );
+end GTX_SODAinput_common_reset;
+
+architecture RTL of GTX_SODAinput_common_reset is
+
+
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+
+ signal init_wait_count : std_logic_vector(7 downto 0) :=(others => '0');
+ signal init_wait_done : std_logic :='0';
+ signal common_reset_asserted : std_logic :='0';
+ signal common_reset_i : std_logic ;
+
+ type rst_type is(
+ INIT, ASSERT_COMMON_RESET);
+
+ signal state : rst_type := INIT;
+
+begin
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ state <= INIT;
+ common_reset_asserted <= '0';
+ COMMON_RESET <= '0';
+ else
+
+ case state is
+ when INIT =>
+ if init_wait_done = '1' then
+ state <= ASSERT_COMMON_RESET;
+ end if;
+
+ when ASSERT_COMMON_RESET =>
+ if common_reset_asserted = '0' then
+ COMMON_RESET <= '1';
+ common_reset_asserted <= '1';
+ else
+ COMMON_RESET <= '0';
+ end if;
+ when OTHERS =>
+ state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput_gt_usrclk_source.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_SODAinput_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_SODAinput_GT_USRCLK_SOURCE is
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_TXCLK_LOCK_OUT : out std_logic;
+ GT0_TX_MMCM_RESET_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_OUT : out std_logic
+);
+
+
+end GTX_SODAinput_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_SODAinput_GT_USRCLK_SOURCE is
+
+component GTX_SODAINPUT_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+
+--// Modified attribute syn_noclockbuf : boolean;
+ signal q3_clk0_gtrefclk : std_logic;
+ --// Modified attribute syn_noclockbuf of q3_clk0_gtrefclk : signal is true;
+
+ signal gt0_txusrclk_i : std_logic;
+
+ signal gt0_rxusrclk_i : std_logic;
+ signal txoutclk_mmcm0_locked_i : std_logic;
+ signal txoutclk_mmcm0_reset_i : std_logic;
+ signal gt0_txoutclk_to_mmcm_i : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+ gt0_txoutclk_i <= GT0_TXOUTCLK_IN;
+ gt0_rxoutclk_i <= GT0_RXOUTCLK_IN;
+
+ Q3_CLK0_GTREFCLK_OUT <= q3_clk0_gtrefclk;
+
+ --// Modified
+ -- --IBUFDS_GTE2
+ -- ibufds_instq3_clk0 : IBUFDS_GTE2
+ -- port map
+ -- (
+ -- O => q3_clk0_gtrefclk,
+ -- ODIV2 => open,
+ -- CEB => tied_to_ground_i,
+ -- I => Q3_CLK0_GTREFCLK_PAD_P_IN,
+ -- IB => Q3_CLK0_GTREFCLK_PAD_N_IN
+ -- );
+
+
+
+ -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+ -- for improved jitter performance, and to avoid consuming an additional BUFG
+ txoutclk_mmcm0_reset_i <= GT0_TX_MMCM_RESET_IN;
+ txoutclk_mmcm0_i : GTX_SODAinput_CLOCK_MODULE
+ generic map
+ (
+ MULT => 16.0, --// 14.0 Modified
+ DIVIDE => 5,
+ CLK_PERIOD => 4.0,
+ OUT0_DIVIDE => 8.0, --// 7.0 Modified
+ OUT1_DIVIDE => 4, --// 1.0 Modified
+ OUT2_DIVIDE => 1,
+ OUT3_DIVIDE => 1
+ )
+ port map
+ (
+ CLK0_OUT => gt0_txusrclk_i,
+ CLK1_OUT => GT0_TXUSRCLKX2_OUT, --// Modified
+ CLK2_OUT => open,
+ CLK3_OUT => open,
+ CLK_IN => gt0_txoutclk_i,
+ MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
+ MMCM_RESET_IN => txoutclk_mmcm0_reset_i
+ );
+
+
+ rxoutclk_bufg1_i : BUFG
+ port map
+ (
+ I => gt0_rxoutclk_i,
+ O => gt0_rxusrclk_i
+ );
+
+
+
+
+GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT0_TXCLK_LOCK_OUT <= txoutclk_mmcm0_locked_i;
+GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_sodainput_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_SODAinput_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_SODAinput_support is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_OUT : out std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ sysclk_in : in std_logic;
+ q2_clk1_gtrefclk : in std_logic; --//modification
+ q3_clk0_gtrefclk : in std_logic --//modification
+
+);
+
+end GTX_SODAinput_support;
+
+architecture RTL of GTX_SODAinput_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_SODAinput
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+);
+
+end component;
+
+component GTX_SODAinput_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_SODAinput_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_SODAinput_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_TXCLK_LOCK_OUT : out std_logic;
+ GT0_TX_MMCM_RESET_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt0_txmmcm_lock_i : std_logic;
+ signal gt0_txmmcm_reset_i : std_logic;
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q3_clk0_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+ GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+ gt0_qplloutclk_out <= gt0_qplloutclk_i;
+ gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+
+
+ gt_usrclk_source : GTX_SODAinput_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXUSRCLKX2_OUT => GT0_TXUSRCLKX2_OUT, --// Modified
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_TXCLK_LOCK_OUT => gt0_txmmcm_lock_i,
+ GT0_TX_MMCM_RESET_IN => gt0_txmmcm_reset_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
+ Q3_CLK0_GTREFCLK_PAD_N_IN => Q3_CLK0_GTREFCLK_PAD_N_IN,
+ Q3_CLK0_GTREFCLK_PAD_P_IN => Q3_CLK0_GTREFCLK_PAD_P_IN,
+ Q3_CLK0_GTREFCLK_OUT => open --// Modified q3_clk0_refclk_i
+
+ );
+q3_clk0_refclk_i <= q3_clk0_gtrefclk; --// Modified
+--//gt0_qplloutclk_i <= GT0_QPLLOUTCLK_IN; --// Modified
+--//gt0_qplloutrefclk_i <= GT0_QPLLOUTREFCLK_IN; --// Modified
+
+sysclk_in_i <= sysclk_in;
+
+ common0_i:GTX_SODAinput_common
+ generic map
+ (
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => "001"
+ )
+ port map
+ (
+ QPLLREFCLKSEL_IN => "001",
+ GTREFCLK0_IN => q3_clk0_refclk_i,
+ GTREFCLK1_IN => tied_to_ground_i,
+ QPLLLOCK_OUT => gt0_qplllock_i,
+ QPLLLOCKDETCLK_IN => sysclk_in_i,
+ QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+ -- common_reset_i:GTX_SODAinput_common_reset
+ -- generic map
+ -- (
+ -- STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ -- )
+ -- port map
+ -- (
+ -- STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ -- SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ -- COMMON_RESET => commonreset_i --Reset QPLL
+ -- );
+
+
+ GTX_SODAinput_init_i : GTX_SODAinput
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_mmcm_lock_in => gt0_txmmcm_lock_i,
+ gt0_tx_mmcm_reset_out => gt0_txmmcm_reset_i,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => q3_clk0_refclk_i,
+ gt0_gtrefclk1_in => tied_to_ground_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">Programmable</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_extended_timeout">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tdlock_time">1000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">GTX_dataoutput</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.example_chipscope">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">Programmable</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_extended_timeout">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tdlock_time">1000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_align_comma_word" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_comma_preset" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_decoding" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_dfe_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_drp_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxslide" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxslide_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txbuf_en" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txoutclk_source" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_rx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_tx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_rx_pll" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_tx_pll" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- file: FEE_clockbuf80MHz.vhd\r
--- \r
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
--- \r
--- This file contains confidential and proprietary information\r
--- of Xilinx, Inc. and is protected under U.S. and\r
--- international copyright and other intellectual property\r
--- laws.\r
--- \r
--- DISCLAIMER\r
--- This disclaimer is not a license and does not grant any\r
--- rights to the materials distributed herewith. Except as\r
--- otherwise provided in a valid license issued to you by\r
--- Xilinx, and to the maximum extent permitted by applicable\r
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
--- (2) Xilinx shall not be liable (whether in contract or tort,\r
--- including negligence, or under any other theory of\r
--- liability) for any loss or damage of any kind or nature\r
--- related to, arising under or in connection with these\r
--- materials, including for any direct, or any indirect,\r
--- special, incidental, or consequential loss or damage\r
--- (including loss of data, profits, goodwill, or any type of\r
--- loss or damage suffered as a result of any action brought\r
--- by a third party) even if such damage or loss was\r
--- reasonably foreseeable or Xilinx had been advised of the\r
--- possibility of the same.\r
--- \r
--- CRITICAL APPLICATIONS\r
--- Xilinx products are not designed or intended to be fail-\r
--- safe, or for use in any application requiring fail-safe\r
--- performance, such as life-support or safety devices or\r
--- systems, Class III medical devices, nuclear facilities,\r
--- applications related to the deployment of airbags, or any\r
--- other applications that could lead to death, personal\r
--- injury, or severe property or environmental damage\r
--- (individually and collectively, "Critical\r
--- Applications"). Customer assumes the sole risk and\r
--- liability of any use of Xilinx products in Critical\r
--- Applications, subject only to applicable laws and\r
--- regulations governing limitations on product liability.\r
--- \r
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
--- PART OF THIS FILE AT ALL TIMES.\r
--- \r
-------------------------------------------------------------------------------\r
--- User entered comments\r
-------------------------------------------------------------------------------\r
--- None\r
---\r
-------------------------------------------------------------------------------\r
--- "Output Output Phase Duty Pk-to-Pk Phase"\r
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
-------------------------------------------------------------------------------\r
--- CLK_OUT1____80.000______0.000______50.0______147.966____103.963\r
--- CLK_OUT2____80.000____180.000______50.0______147.966____103.963\r
---\r
-------------------------------------------------------------------------------\r
--- "Input Clock Freq (MHz) Input Jitter (UI)"\r
-------------------------------------------------------------------------------\r
--- __primary______________80____________0.010\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.numeric_std.all;\r
-\r
-library unisim;\r
-use unisim.vcomponents.all;\r
-\r
-entity FEE_clockbuf80MHz is\r
-port\r
- (-- Clock in ports\r
- CLK_IN1 : in std_logic;\r
- -- Clock out ports\r
- CLK_OUT1 : out std_logic;\r
- CLK_OUT2 : out std_logic\r
- );\r
-end FEE_clockbuf80MHz;\r
-\r
-architecture xilinx of FEE_clockbuf80MHz is\r
- attribute CORE_GENERATION_INFO : string;\r
- attribute CORE_GENERATION_INFO of xilinx : architecture is "FEE_clockbuf80MHz,clk_wiz_v3_6,{component_name=FEE_clockbuf80MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=12.500,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";\r
- -- Input clock buffering / unused connectors\r
- signal clkin1 : std_logic;\r
- -- Output clock buffering / unused connectors\r
- signal clkfbout : std_logic;\r
- signal clkfbout_buf : std_logic;\r
- signal clkfboutb_unused : std_logic;\r
- signal clkout0 : std_logic;\r
- signal clkout0b_unused : std_logic;\r
- signal clkout1 : std_logic;\r
- signal clkout1b_unused : std_logic;\r
- signal clkout2_unused : std_logic;\r
- signal clkout2b_unused : std_logic;\r
- signal clkout3_unused : std_logic;\r
- signal clkout3b_unused : std_logic;\r
- signal clkout4_unused : std_logic;\r
- signal clkout5_unused : std_logic;\r
- signal clkout6_unused : std_logic;\r
- -- Dynamic programming unused signals\r
- signal do_unused : std_logic_vector(15 downto 0);\r
- signal drdy_unused : std_logic;\r
- -- Dynamic phase shift unused signals\r
- signal psdone_unused : std_logic;\r
- -- Unused status signals\r
- signal locked_unused : std_logic;\r
- signal clkfbstopped_unused : std_logic;\r
- signal clkinstopped_unused : std_logic;\r
-begin\r
-\r
-\r
- -- Input buffering\r
- --------------------------------------\r
- clkin1 <= CLK_IN1;\r
-\r
-\r
- -- Clocking primitive\r
- --------------------------------------\r
- -- Instantiation of the MMCM primitive\r
- -- * Unused inputs are tied off\r
- -- * Unused outputs are labeled unused\r
- mmcm_adv_inst : MMCM_ADV\r
- generic map\r
- (BANDWIDTH => "OPTIMIZED",\r
- CLKOUT4_CASCADE => FALSE,\r
- CLOCK_HOLD => FALSE,\r
- COMPENSATION => "ZHOLD",\r
- STARTUP_WAIT => FALSE,\r
- DIVCLK_DIVIDE => 1,\r
- CLKFBOUT_MULT_F => 12.000,\r
- CLKFBOUT_PHASE => 0.000,\r
- CLKFBOUT_USE_FINE_PS => FALSE,\r
- CLKOUT0_DIVIDE_F => 12.000,\r
- CLKOUT0_PHASE => 0.000,\r
- CLKOUT0_DUTY_CYCLE => 0.500,\r
- CLKOUT0_USE_FINE_PS => FALSE,\r
- CLKOUT1_DIVIDE => 12,\r
- CLKOUT1_PHASE => 180.000,\r
- CLKOUT1_DUTY_CYCLE => 0.500,\r
- CLKOUT1_USE_FINE_PS => FALSE,\r
- CLKIN1_PERIOD => 12.500,\r
- REF_JITTER1 => 0.010)\r
- port map\r
- -- Output clocks\r
- (CLKFBOUT => clkfbout,\r
- CLKFBOUTB => clkfboutb_unused,\r
- CLKOUT0 => clkout0,\r
- CLKOUT0B => clkout0b_unused,\r
- CLKOUT1 => clkout1,\r
- CLKOUT1B => clkout1b_unused,\r
- CLKOUT2 => clkout2_unused,\r
- CLKOUT2B => clkout2b_unused,\r
- CLKOUT3 => clkout3_unused,\r
- CLKOUT3B => clkout3b_unused,\r
- CLKOUT4 => clkout4_unused,\r
- CLKOUT5 => clkout5_unused,\r
- CLKOUT6 => clkout6_unused,\r
- -- Input clock control\r
- CLKFBIN => clkfbout_buf,\r
- CLKIN1 => clkin1,\r
- CLKIN2 => '0',\r
- -- Tied to always select the primary input clock\r
- CLKINSEL => '1',\r
- -- Ports for dynamic reconfiguration\r
- DADDR => (others => '0'),\r
- DCLK => '0',\r
- DEN => '0',\r
- DI => (others => '0'),\r
- DO => do_unused,\r
- DRDY => drdy_unused,\r
- DWE => '0',\r
- -- Ports for dynamic phase shift\r
- PSCLK => '0',\r
- PSEN => '0',\r
- PSINCDEC => '0',\r
- PSDONE => psdone_unused,\r
- -- Other control and status signals\r
- LOCKED => locked_unused,\r
- CLKINSTOPPED => clkinstopped_unused,\r
- CLKFBSTOPPED => clkfbstopped_unused,\r
- PWRDWN => '0',\r
- RST => '0');\r
-\r
- -- Output buffering\r
- -------------------------------------\r
- clkf_buf : BUFG\r
- port map\r
- (O => clkfbout_buf,\r
- I => clkfbout);\r
-\r
-\r
- clkout1_buf : BUFG\r
- port map\r
- (O => CLK_OUT1,\r
- I => clkout0);\r
-\r
-\r
-\r
- clkout2_buf : BUFG\r
- port map\r
- (O => CLK_OUT2,\r
- I => clkout1);\r
-\r
-end xilinx;\r
+-- file: clk_wiz_v2_1.vhd
+--
+-- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1 100.000 0.000 50.000 130.958 98.575
+-- CLK_OUT2 200.000 0.000 50.000 114.829 98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock Input Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary 100.000 0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_dataoutput_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end GTX_dataoutput_CLOCK_MODULE;
+
+architecture xilinx of GTX_dataoutput_CLOCK_MODULE is
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of xilinx : architecture is "GTX_dataoutput,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+ -- Input clock buffering / unused connectors
+ signal clkin1 : std_logic;
+ -- Output clock buffering / unused connectors
+ signal clkfbout : std_logic;
+ signal clkfbout_buf : std_logic;
+ signal clkfboutb_unused : std_logic;
+ signal clkout0 : std_logic;
+ signal clkout0b_unused : std_logic;
+ signal clkout1 : std_logic;
+ signal clkout1b_unused : std_logic;
+ signal clkout2 : std_logic;
+ signal clkout2b_unused : std_logic;
+ signal clkout3 : std_logic;
+ signal clkout3b_unused : std_logic;
+ signal clkout4_unused : std_logic;
+ signal clkout5_unused : std_logic;
+ signal clkout6_unused : std_logic;
+ -- Dynamic programming unused signals
+ signal do_unused : std_logic_vector(15 downto 0);
+ signal drdy_unused : std_logic;
+ -- Dynamic phase shift unused signals
+ signal psdone_unused : std_logic;
+ -- Unused status signals
+ signal clkfbstopped_unused : std_logic;
+ signal clkinstopped_unused : std_logic;
+begin
+
+
+ -- Input buffering
+ --------------------------------------
+ clkin1_buf : BUFG
+ port map
+ (O => clkin1,
+ I => CLK_IN);
+
+ -- Clocking primitive
+ --------------------------------------
+ -- Instantiation of the MMCM primitive
+ -- * Unused inputs are tied off
+ -- * Unused outputs are labeled unused
+
+ mmcm_adv_inst : MMCME2_ADV
+ generic map
+ (BANDWIDTH => "OPTIMIZED",
+ CLKOUT4_CASCADE => FALSE,
+ COMPENSATION => "ZHOLD",
+ STARTUP_WAIT => FALSE,
+ DIVCLK_DIVIDE => DIVIDE,
+ CLKFBOUT_MULT_F => MULT,
+ CLKFBOUT_PHASE => 0.000,
+ CLKFBOUT_USE_FINE_PS => FALSE,
+ CLKOUT0_DIVIDE_F => OUT0_DIVIDE,
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKOUT0_USE_FINE_PS => FALSE,
+ CLKIN1_PERIOD => CLK_PERIOD,
+ CLKOUT1_DIVIDE => OUT1_DIVIDE,
+ CLKOUT1_PHASE => 0.000,
+ CLKOUT1_DUTY_CYCLE => 0.500,
+ CLKOUT1_USE_FINE_PS => FALSE,
+ CLKOUT2_DIVIDE => OUT2_DIVIDE,
+ CLKOUT2_PHASE => 0.000,
+ CLKOUT2_DUTY_CYCLE => 0.500,
+ CLKOUT2_USE_FINE_PS => FALSE,
+ CLKOUT3_DIVIDE => OUT3_DIVIDE,
+ CLKOUT3_PHASE => 0.000,
+ CLKOUT3_DUTY_CYCLE => 0.500,
+ CLKOUT3_USE_FINE_PS => FALSE,
+ REF_JITTER1 => 0.010)
+ port map
+ -- Output clocks
+ (CLKFBOUT => clkfbout,
+ CLKFBOUTB => clkfboutb_unused,
+ CLKOUT0 => clkout0,
+ CLKOUT0B => clkout0b_unused,
+ CLKOUT1 => clkout1,
+ CLKOUT1B => clkout1b_unused,
+ CLKOUT2 => clkout2,
+ CLKOUT2B => clkout2b_unused,
+ CLKOUT3 => clkout3,
+ CLKOUT3B => clkout3b_unused,
+ CLKOUT4 => clkout4_unused,
+ CLKOUT5 => clkout5_unused,
+ CLKOUT6 => clkout6_unused,
+ -- Input clock control
+ CLKFBIN => clkfbout,
+ CLKIN1 => clkin1,
+ CLKIN2 => '0',
+ -- Tied to always select the primary input clock
+ CLKINSEL => '1',
+ -- Ports for dynamic reconfiguration
+ DADDR => (others => '0'),
+ DCLK => '0',
+ DEN => '0',
+ DI => (others => '0'),
+ DO => do_unused,
+ DRDY => drdy_unused,
+ DWE => '0',
+ -- Ports for dynamic phase shift
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ PSDONE => psdone_unused,
+ -- Other control and status signals
+ LOCKED => MMCM_LOCKED_OUT,
+ CLKINSTOPPED => clkinstopped_unused,
+ CLKFBSTOPPED => clkfbstopped_unused,
+ PWRDWN => '0',
+ RST => MMCM_RESET_IN);
+
+ -- Output buffering
+ -------------------------------------
+ --clkf_buf : BUFG
+ --port map
+ -- (O => clkfbout_buf,
+ -- I => clkfbout);
+
+
+ clkout0_buf : BUFG
+ port map
+ (O => CLK0_OUT,
+ I => clkout0);
+
+ clkout1_buf : BUFG
+ port map
+ (O => CLK1_OUT,
+ I => clkout1);
+
+-- clkout2_buf : BUFG
+-- port map
+-- (O => CLK2_OUT,
+-- I => clkout2);
+--
+-- clkout3_buf : BUFG
+-- port map
+-- (O => CLK3_OUT,
+-- I => clkout3);
+
+CLK2_OUT <= '0';
+CLK3_OUT <= '0';
+end xilinx;
--- /dev/null
+---------------------------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_dataoutput_common.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_dataoutput_common
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_dataoutput_common is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
+ SIM_QPLLREFCLK_SEL : bit_vector := "001"
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK1_IN : in std_logic;
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+);
+
+end GTX_dataoutput_common;
+
+architecture RTL of GTX_dataoutput_common is
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_dataoutput_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_TOP : integer := 16;
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
+
+begin
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+
+ gtxe2_common_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
+ SIM_VERSION => "4.0",
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (1)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GTREFCLK0_IN,
+ GTREFCLK1 => GTREFCLK1_IN,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports -----------------------
+ QPLLDMONITOR => open,
+ ----------------------- Common Block - Clocking Ports ----------------------
+ QPLLOUTCLK => QPLLOUTCLK_OUT,
+ QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
+ REFCLKOUTMONITOR => open,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => QPLLLOCK_OUT,
+ QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_vcc_i,
+ QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
+ QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
+ QPLLRESET => QPLLRESET_IN,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ --------------------------------- QPLL Ports -------------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "11111",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+end RTL;
--- /dev/null
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_dataoutput_common_reset.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module GTX_dataoutput_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_dataoutput_common_reset is
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic:= '0' --Reset QPLL
+ );
+end GTX_dataoutput_common_reset;
+
+architecture RTL of GTX_dataoutput_common_reset is
+
+
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+
+ signal init_wait_count : std_logic_vector(7 downto 0) :=(others => '0');
+ signal init_wait_done : std_logic :='0';
+ signal common_reset_asserted : std_logic :='0';
+ signal common_reset_i : std_logic ;
+
+ type rst_type is(
+ INIT, ASSERT_COMMON_RESET);
+
+ signal state : rst_type := INIT;
+
+begin
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ state <= INIT;
+ common_reset_asserted <= '0';
+ COMMON_RESET <= '0';
+ else
+
+ case state is
+ when INIT =>
+ if init_wait_done = '1' then
+ state <= ASSERT_COMMON_RESET;
+ end if;
+
+ when ASSERT_COMMON_RESET =>
+ if common_reset_asserted = '0' then
+ COMMON_RESET <= '1';
+ common_reset_asserted <= '1';
+ else
+ COMMON_RESET <= '0';
+ end if;
+ when OTHERS =>
+ state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_dataoutput_gt_usrclk_source.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_dataoutput_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_dataoutput_GT_USRCLK_SOURCE is
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_TXCLK_LOCK_OUT : out std_logic;
+ GT0_TX_MMCM_RESET_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_OUT : out std_logic
+);
+
+
+end GTX_dataoutput_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_dataoutput_GT_USRCLK_SOURCE is
+
+component GTX_DATAOUTPUT_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+
+ attribute syn_noclockbuf : boolean;
+ signal q3_clk0_gtrefclk : std_logic;
+ attribute syn_noclockbuf of q3_clk0_gtrefclk : signal is true;
+
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal txoutclk_mmcm0_locked_i : std_logic;
+ signal txoutclk_mmcm0_reset_i : std_logic;
+ signal gt0_txoutclk_to_mmcm_i : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+ gt0_txoutclk_i <= GT0_TXOUTCLK_IN;
+ gt0_rxoutclk_i <= GT0_RXOUTCLK_IN;
+
+ Q3_CLK0_GTREFCLK_OUT <= q3_clk0_gtrefclk;
+
+ --IBUFDS_GTE2
+ ibufds_instq3_clk0 : IBUFDS_GTE2
+ port map
+ (
+ O => q3_clk0_gtrefclk,
+ ODIV2 => open,
+ CEB => tied_to_ground_i,
+ I => Q3_CLK0_GTREFCLK_PAD_P_IN,
+ IB => Q3_CLK0_GTREFCLK_PAD_N_IN
+ );
+
+
+
+ -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+ -- for improved jitter performance, and to avoid consuming an additional BUFG
+ txoutclk_mmcm0_reset_i <= GT0_TX_MMCM_RESET_IN;
+ txoutclk_mmcm0_i : GTX_dataoutput_CLOCK_MODULE
+ generic map
+ (
+ MULT => 13.0,
+ DIVIDE => 5,
+ CLK_PERIOD => 4.0,
+ OUT0_DIVIDE => 13.0,
+ OUT1_DIVIDE => 1,
+ OUT2_DIVIDE => 1,
+ OUT3_DIVIDE => 1
+ )
+ port map
+ (
+ CLK0_OUT => gt0_txusrclk_i,
+ CLK1_OUT => open,
+ CLK2_OUT => open,
+ CLK3_OUT => open,
+ CLK_IN => gt0_txoutclk_i,
+ MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
+ MMCM_RESET_IN => txoutclk_mmcm0_reset_i
+ );
+
+
+ rxoutclk_bufg1_i : BUFG
+ port map
+ (
+ I => gt0_rxoutclk_i,
+ O => gt0_rxusrclk_i
+ );
+
+
+
+
+GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT0_TXCLK_LOCK_OUT <= txoutclk_mmcm0_locked_i;
+GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_dataoutput_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_dataoutput_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_dataoutput_support is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_OUT : out std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic; --//modification
+ GT0_QPLLOUTREFCLK_IN : in std_logic; --//modification
+ sysclk_in : in std_logic;
+ q2_clk1_gtrefclk : in std_logic; --//modification
+ q3_clk0_gtrefclk : in std_logic --//modification
+
+);
+
+end GTX_dataoutput_support;
+
+architecture RTL of GTX_dataoutput_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_dataoutput
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_dataoutput_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_dataoutput_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_dataoutput_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_TXCLK_LOCK_OUT : out std_logic;
+ GT0_TX_MMCM_RESET_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q3_CLK0_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt0_txmmcm_lock_i : std_logic;
+ signal gt0_txmmcm_reset_i : std_logic;
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q3_clk0_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+ GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+--// Modified gt0_qplloutclk_out <= gt0_qplloutclk_i;
+--// Modified gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+
+
+ gt_usrclk_source : GTX_dataoutput_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_TXCLK_LOCK_OUT => gt0_txmmcm_lock_i,
+ GT0_TX_MMCM_RESET_IN => gt0_txmmcm_reset_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
+ Q3_CLK0_GTREFCLK_PAD_N_IN => Q3_CLK0_GTREFCLK_PAD_N_IN,
+ Q3_CLK0_GTREFCLK_PAD_P_IN => Q3_CLK0_GTREFCLK_PAD_P_IN,
+ Q3_CLK0_GTREFCLK_OUT => open --//modification q3_clk0_refclk_i
+
+ );
+q3_clk0_refclk_i <= q3_clk0_gtrefclk; --//modification
+
+sysclk_in_i <= sysclk_in;
+
+gt0_qplloutclk_i <= GT0_QPLLOUTCLK_IN; --// Modified
+gt0_qplloutrefclk_i <= GT0_QPLLOUTREFCLK_IN; --// Modified
+
+--// Modified
+ -- common0_i:GTX_dataoutput_common
+ -- generic map
+ -- (
+ -- WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ -- SIM_QPLLREFCLK_SEL => "001"
+ -- )
+ -- port map
+ -- (
+ -- QPLLREFCLKSEL_IN => "001",
+ -- GTREFCLK0_IN => q3_clk0_refclk_i,
+ -- GTREFCLK1_IN => tied_to_ground_i,
+ -- QPLLLOCK_OUT => gt0_qplllock_i,
+ -- QPLLLOCKDETCLK_IN => sysclk_in_i,
+ -- QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ -- QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ -- QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ -- QPLLRESET_IN => gt0_qpllreset_t
+
+-- );
+
+ common_reset_i:GTX_dataoutput_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ GTX_dataoutput_init_i : GTX_dataoutput
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_mmcm_lock_in => gt0_txmmcm_lock_i,
+ gt0_tx_mmcm_reset_out => gt0_txmmcm_reset_i,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => q3_clk0_refclk_i,
+ gt0_gtrefclk1_in => tied_to_ground_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">Programmable</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_extended_timeout">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N1">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tdlock_time">1000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">GTX_dualSODA</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.example_chipscope">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">Programmable</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_extended_timeout">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tdlock_time">1000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_align_comma_word" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_comma_preset" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_decoding" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_dfe_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_drp_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxslide" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxslide_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txbuf_en" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txoutclk_source" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt12_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt12_val_rx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt12_val_tx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt13_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt13_val_rx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt13_val_tx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_rx_pll" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_tx_pll" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+---------------------------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_dualsoda_common.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_dualSODA_common
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_dualSODA_common is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
+ SIM_QPLLREFCLK_SEL : bit_vector := "001"
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK1_IN : in std_logic;
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+);
+
+end GTX_dualSODA_common;
+
+architecture RTL of GTX_dualSODA_common is
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_dualSODA_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_TOP : integer := 16;
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
+
+begin
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+
+ gtxe2_common_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
+ SIM_VERSION => "4.0",
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (1)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GTREFCLK0_IN,
+ GTREFCLK1 => GTREFCLK1_IN,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports -----------------------
+ QPLLDMONITOR => open,
+ ----------------------- Common Block - Clocking Ports ----------------------
+ QPLLOUTCLK => QPLLOUTCLK_OUT,
+ QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
+ REFCLKOUTMONITOR => open,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => QPLLLOCK_OUT,
+ QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_vcc_i,
+ QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
+ QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
+ QPLLRESET => QPLLRESET_IN,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ --------------------------------- QPLL Ports -------------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "11111",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+end RTL;
--- /dev/null
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_dualsoda_common_reset.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module GTX_dualSODA_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_dualSODA_common_reset is
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic:= '0' --Reset QPLL
+ );
+end GTX_dualSODA_common_reset;
+
+architecture RTL of GTX_dualSODA_common_reset is
+
+
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+
+ signal init_wait_count : std_logic_vector(7 downto 0) :=(others => '0');
+ signal init_wait_done : std_logic :='0';
+ signal common_reset_asserted : std_logic :='0';
+ signal common_reset_i : std_logic ;
+
+ type rst_type is(
+ INIT, ASSERT_COMMON_RESET);
+
+ signal state : rst_type := INIT;
+
+begin
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ state <= INIT;
+ common_reset_asserted <= '0';
+ COMMON_RESET <= '0';
+ else
+
+ case state is
+ when INIT =>
+ if init_wait_done = '1' then
+ state <= ASSERT_COMMON_RESET;
+ end if;
+
+ when ASSERT_COMMON_RESET =>
+ if common_reset_asserted = '0' then
+ COMMON_RESET <= '1';
+ common_reset_asserted <= '1';
+ else
+ COMMON_RESET <= '0';
+ end if;
+ when OTHERS =>
+ state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_dualsoda_gt_usrclk_source.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_dualSODA_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_dualSODA_GT_USRCLK_SOURCE is
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_TXOUTCLK_IN : in std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+ GT1_RXOUTCLK_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_OUT : out std_logic
+);
+
+
+end GTX_dualSODA_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_dualSODA_GT_USRCLK_SOURCE is
+
+component GTX_DUALSODA_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+
+ signal gt1_txoutclk_i : std_logic;
+ signal gt1_rxoutclk_i : std_logic;
+
+--// Modified attribute syn_noclockbuf : boolean;
+ signal q2_clk1_gtrefclk : std_logic;
+--// Modified attribute syn_noclockbuf of q2_clk1_gtrefclk : signal is true;
+
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+ gt0_txoutclk_i <= GT0_TXOUTCLK_IN;
+ gt0_rxoutclk_i <= GT0_RXOUTCLK_IN;
+ gt1_txoutclk_i <= GT1_TXOUTCLK_IN;
+ gt1_rxoutclk_i <= GT1_RXOUTCLK_IN;
+
+ Q2_CLK1_GTREFCLK_OUT <= q2_clk1_gtrefclk;
+
+ --// Modified
+ --IBUFDS_GTE2
+ -- ibufds_instq2_clk1 : IBUFDS_GTE2
+ -- port map
+ -- (
+ -- O => q2_clk1_gtrefclk,
+ -- ODIV2 => open,
+ -- CEB => tied_to_ground_i,
+ -- I => Q2_CLK1_GTREFCLK_PAD_P_IN,
+ -- IB => Q2_CLK1_GTREFCLK_PAD_N_IN
+ -- );
+
+
+
+ -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+ -- for improved jitter performance, and to avoid consuming an additional BUFG
+ txoutclk_bufg0_i : BUFG
+ port map
+ (
+ I => gt0_txoutclk_i,
+ O => gt0_txusrclk_i
+ );
+
+
+ rxoutclk_bufg1_i : BUFG
+ port map
+ (
+ I => gt0_rxoutclk_i,
+ O => gt0_rxusrclk_i
+ );
+
+
+
+
+GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+
+GT1_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT1_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT1_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT1_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_dualsoda_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_dualSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_dualSODA_support is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic; --//modification
+ GT0_QPLLOUTREFCLK_IN : in std_logic; --//modification
+ sysclk_in : in std_logic;
+ q2_clk1_gtrefclk : in std_logic; --//modification
+ q3_clk0_gtrefclk : in std_logic --//modification
+);
+
+end GTX_dualSODA_support;
+
+architecture RTL of GTX_dualSODA_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_dualSODA
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cplllockdetclk_in : in std_logic;
+ gt1_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtrefclk0_in : in std_logic;
+ gt1_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpclk_in : in std_logic;
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in : in std_logic;
+ gt1_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt1_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in : in std_logic;
+ gt1_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out : out std_logic;
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_dualSODA_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_dualSODA_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_dualSODA_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_TXOUTCLK_IN : in std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+ GT1_RXOUTCLK_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+ signal gt1_txfsmresetdone_i : std_logic;
+signal gt1_rxfsmresetdone_i : std_logic;
+ signal gt1_txfsmresetdone_r : std_logic;
+ signal gt1_txfsmresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r : std_logic;
+signal gt1_rxresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt1_cpllfbclklost_i : std_logic;
+ signal gt1_cplllock_i : std_logic;
+ signal gt1_cpllrefclklost_i : std_logic;
+ signal gt1_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt1_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt1_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt1_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt1_drpen_i : std_logic;
+ signal gt1_drprdy_i : std_logic;
+ signal gt1_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt1_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt1_eyescanreset_i : std_logic;
+ signal gt1_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt1_eyescandataerror_i : std_logic;
+ signal gt1_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt1_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt1_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt1_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt1_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt1_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt1_rxdlyen_i : std_logic;
+ signal gt1_rxdlysreset_i : std_logic;
+ signal gt1_rxdlysresetdone_i : std_logic;
+ signal gt1_rxphalign_i : std_logic;
+ signal gt1_rxphaligndone_i : std_logic;
+ signal gt1_rxphalignen_i : std_logic;
+ signal gt1_rxphdlyreset_i : std_logic;
+ signal gt1_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt1_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt1_rxlpmhfhold_i : std_logic;
+ signal gt1_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt1_rxdfelpmreset_i : std_logic;
+ signal gt1_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt1_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt1_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt1_gtrxreset_i : std_logic;
+ signal gt1_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt1_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt1_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt1_gttxreset_i : std_logic;
+ signal gt1_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt1_txdlyen_i : std_logic;
+ signal gt1_txdlysreset_i : std_logic;
+ signal gt1_txdlysresetdone_i : std_logic;
+ signal gt1_txphalign_i : std_logic;
+ signal gt1_txphaligndone_i : std_logic;
+ signal gt1_txphalignen_i : std_logic;
+ signal gt1_txphdlyreset_i : std_logic;
+ signal gt1_txphinit_i : std_logic;
+ signal gt1_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt1_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt1_gtxtxn_i : std_logic;
+ signal gt1_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt1_txoutclk_i : std_logic;
+ signal gt1_txoutclkfabric_i : std_logic;
+ signal gt1_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt1_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt1_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal gt1_tx_system_reset_c : std_logic;
+ signal gt1_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt1_txusrclk_i : std_logic;
+ signal gt1_txusrclk2_i : std_logic;
+ signal gt1_rxusrclk_i : std_logic;
+ signal gt1_rxusrclk2_i : std_logic;
+
+signal q2_clk1_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+
+attribute mark_debug : string;
+
+
+
+-- attribute mark_debug of SOFT_RESET_TX_IN : signal is "true";
+-- attribute mark_debug of DONT_RESET_ON_DATA_ERROR_IN : signal is "true";
+-- attribute mark_debug of gt0_tx_fsm_reset_done_out : signal is "true";
+-- attribute mark_debug of gt0_rx_fsm_reset_done_out : signal is "true";
+-- attribute mark_debug of gt0_data_valid_in : signal is "true";
+-- attribute mark_debug of gt0_cpllfbclklost_out : signal is "true";
+-- attribute mark_debug of gt0_cplllock_out : signal is "true";
+-- attribute mark_debug of gt0_cpllreset_in : signal is "true";
+-- attribute mark_debug of gt0_rxuserrdy_in : signal is "true";
+-- attribute mark_debug of gt0_rxdata_out : signal is "true";
+-- attribute mark_debug of gt0_rxcharisk_out : signal is "true";
+-- attribute mark_debug of gt0_rxdisperr_out : signal is "true";
+-- attribute mark_debug of gt0_rxnotintable_out : signal is "true";
+-- attribute mark_debug of gt0_gtrxreset_in : signal is "true";
+-- attribute mark_debug of gt0_rxpmareset_in : signal is "true";
+-- attribute mark_debug of gt0_rxresetdone_out : signal is "true";
+-- attribute mark_debug of gt0_gttxreset_in : signal is "true";
+-- attribute mark_debug of gt0_txuserrdy_in : signal is "true";
+-- attribute mark_debug of gt0_txdata_in : signal is "true";
+-- attribute mark_debug of gt0_txcharisk_in : signal is "true";
+-- attribute mark_debug of gt0_txresetdone_out : signal is "true";
+
+
+
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+--// Modified gt0_qplloutclk_out <= gt0_qplloutclk_i;
+--// Modified gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+ GT1_TXUSRCLK_OUT <= gt1_txusrclk_i;
+ GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+ GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+ GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+
+
+
+
+
+
+ gt_usrclk_source : GTX_dualSODA_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
+
+ GT1_TXUSRCLK_OUT => gt1_txusrclk_i,
+ GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
+ GT1_TXOUTCLK_IN => gt1_txoutclk_i,
+ GT1_RXUSRCLK_OUT => gt1_rxusrclk_i,
+ GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
+ GT1_RXOUTCLK_IN => gt1_rxoutclk_i,
+ Q2_CLK1_GTREFCLK_PAD_N_IN => Q2_CLK1_GTREFCLK_PAD_N_IN,
+ Q2_CLK1_GTREFCLK_PAD_P_IN => Q2_CLK1_GTREFCLK_PAD_P_IN,
+ Q2_CLK1_GTREFCLK_OUT => open --// Modified q2_clk1_refclk_i
+
+ );
+q2_clk1_refclk_i <= q2_clk1_gtrefclk; --// Modified
+
+sysclk_in_i <= sysclk_in;
+
+gt0_qplloutclk_i <= GT0_QPLLOUTCLK_IN; --// Modified
+gt0_qplloutrefclk_i <= GT0_QPLLOUTREFCLK_IN; --// Modified
+
+--// Modified
+ -- common0_i:GTX_dualSODA_common
+ -- generic map
+ -- (
+ -- WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ -- SIM_QPLLREFCLK_SEL => "001"
+ -- )
+ -- port map
+ -- (
+ -- QPLLREFCLKSEL_IN => "001",
+ -- GTREFCLK0_IN => q3_clk0_gtrefclk, --// Modified tied_to_ground_i,
+ -- GTREFCLK1_IN => q2_clk1_refclk_i,
+ -- QPLLLOCK_OUT => gt0_qplllock_i,
+ -- QPLLLOCKDETCLK_IN => sysclk_in_i,
+ -- QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ -- QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ -- QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ -- QPLLRESET_IN => gt0_qpllreset_t
+
+-- );
+
+ common_reset_i:GTX_dualSODA_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ GTX_dualSODA_init_i : GTX_dualSODA
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+ gt1_tx_fsm_reset_done_out => gt1_tx_fsm_reset_done_out,
+ gt1_rx_fsm_reset_done_out => gt1_rx_fsm_reset_done_out,
+ gt1_data_valid_in => gt1_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => tied_to_ground_i,
+ gt0_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out => gt1_cpllfbclklost_out,
+ gt1_cplllock_out => gt1_cplllock_out,
+ gt1_cplllockdetclk_in => sysclk_in_i,
+ gt1_cpllreset_in => gt1_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt1_gtrefclk0_in => tied_to_ground_i,
+ gt1_gtrefclk1_in => q2_clk1_refclk_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in => gt1_drpaddr_in,
+ gt1_drpclk_in => sysclk_in_i,
+ gt1_drpdi_in => gt1_drpdi_in,
+ gt1_drpdo_out => gt1_drpdo_out,
+ gt1_drpen_in => gt1_drpen_in,
+ gt1_drprdy_out => gt1_drprdy_out,
+ gt1_drpwe_in => gt1_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out => gt1_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in => gt1_eyescanreset_in,
+ gt1_rxuserrdy_in => gt1_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out => gt1_eyescandataerror_out,
+ gt1_eyescantrigger_in => gt1_eyescantrigger_in,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt1_rxusrclk_in => gt1_rxusrclk_i,
+ gt1_rxusrclk2_in => gt1_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out => gt1_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out => gt1_rxdisperr_out,
+ gt1_rxnotintable_out => gt1_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in => gt1_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in => gt1_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out => gt1_rxphmonitor_out,
+ gt1_rxphslipmonitor_out => gt1_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in => gt1_rxdfelpmreset_in,
+ gt1_rxmonitorout_out => gt1_rxmonitorout_out,
+ gt1_rxmonitorsel_in => gt1_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt1_rxoutclk_out => gt1_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in => gt1_gtrxreset_in,
+ gt1_rxpmareset_in => gt1_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out => gt1_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out => gt1_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in => gt1_gttxreset_in,
+ gt1_txuserrdy_in => gt1_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt1_txusrclk_in => gt1_txusrclk_i,
+ gt1_txusrclk2_in => gt1_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in => gt1_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out => gt1_gtxtxn_out,
+ gt1_gtxtxp_out => gt1_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclk_out => gt1_txoutclk_i,
+ gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
+ gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in => gt1_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out => gt1_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+end RTL;
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com"
+ xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>GTX_quadSODA</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com"
+ spirit:library="ip"
+ spirit:name="gtwizard"
+ spirit:version="3.5"/>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_quadSODA</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
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+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_uselabtools"
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+</spirit:design>
--- /dev/null
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--- /dev/null
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--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio_0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIPE_IFACE">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USER_REPO_PATHS"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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+ <spirit:name>unknown</spirit:name>
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+ <spirit:componentInstances>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_trb3_2gb</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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+ <spirit:componentInstances>
+ <spirit:componentInstance>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_trb3_sync_2gb</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_tx_pll" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_rx_pll" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt10_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt10_val_tx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt10_val_rx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_tx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_rx_refclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_decoding" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_drp_clock" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txbuf_en" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txoutclk_source" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_comma_preset" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_align_comma_word" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxslide" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_dfe_mode" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxslide_mode" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_trb3_sync_2gb (a Core Top)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_trb3_sync_2gb is
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end GTX_trb3_sync_2gb;
+
+architecture RTL of GTX_trb3_sync_2gb is
+ attribute DowngradeIPIdentifiedWarnings: string;
+ attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of RTL : architecture is "GTX_trb3_sync_2gb,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_trb3_sync_2gb,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+--**************************Component Declarations*****************************
+
+component GTX_trb3_sync_2gb_init
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+
+ STABLE_CLOCK_PERIOD : integer := 10;
+ -- Set to 1 for simulation
+ EXAMPLE_USE_CHIPSCOPE : integer := 1 --// Modified -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end component;
+
+--**************************** Main Body of Code *******************************
+begin
+ U0 : GTX_trb3_sync_2gb_init
+ generic map
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP => "TRUE",
+ EXAMPLE_SIMULATION => 0,
+
+ USE_BUFG => 0,
+
+ STABLE_CLOCK_PERIOD => 10,
+ EXAMPLE_USE_CHIPSCOPE => 1 --// Modified
+)
+port map
+(
+ SYSCLK_IN => SYSCLK_IN,
+ SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
+ SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
+ DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN,
+ GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
+ GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
+ GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
+ GT0_TX_MMCM_LOCK_IN => GT0_TX_MMCM_LOCK_IN,
+ GT0_TX_MMCM_RESET_OUT => GT0_TX_MMCM_RESET_OUT,
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => gt0_cplllockdetclk_in,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => gt0_gtrefclk0_in,
+ gt0_gtrefclk1_in => gt0_gtrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => gt0_drpclk_in,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_in,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_out,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_in,
+ gt0_txusrclk2_in => gt0_txusrclk2_in,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_out,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
+ GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN
+
+);
+
+end RTL;
+
--- /dev/null
+--//////////////////////////////////////////////////////////////////////////////
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb_auto_phase_align.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : The logic below implements the procedure to do automatic phase-alignment
+-- on the 7-series GTX as described in ug476pdf, version 1.3,
+-- Chapters "Using the TX Phase Alignment to Bypass the TX Buffer"
+-- and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer"
+-- Should the logic below differ from what is described in a later version
+-- of the user-guide, you are using an auto-alignment block, which is
+-- out of date and needs to be updated for safe operation.
+--
+--
+--
+-- Module GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN is
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Auto phase-alignment performed sucessfully
+ PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the
+ DLYSRESET : out STD_LOGIC; -- |transceiver.
+ DLYSRESETDONE : in STD_LOGIC; --/
+ RECCLKSTABLE : in STD_LOGIC --/on the RX-side.
+
+ );
+end GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN;
+
+architecture RTL of GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN is
+
+ component GTX_trb3_sync_2gb_sync_block
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ type phase_align_auto_fsm is(
+ INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE
+ );
+
+ signal phalign_state : phase_align_auto_fsm := INIT;
+ signal phaligndone_prev : std_logic := '0';
+ signal phaligndone_ris_edge : std_logic;
+
+ signal count_phalign_edges : integer range 0 to 3:= 0;
+ signal phaligndone_sync : std_logic := '0';
+ signal dlysresetdone_sync : std_logic := '0';
+
+begin
+
+ sync_PHALIGNDONE : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => PHALIGNDONE,
+ data_out => phaligndone_sync
+ );
+
+ sync_DLYSRESETDONE : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => DLYSRESETDONE,
+ data_out => dlysresetdone_sync
+ );
+
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ phaligndone_prev <= phaligndone_sync;
+ end if;
+ end process;
+ phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0';
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then
+ DLYSRESET <= '0';
+ count_phalign_edges <= 0;
+ PHASE_ALIGNMENT_DONE <= '0';
+ phalign_state <= INIT;
+ else
+ if phaligndone_ris_edge = '1' then
+ if count_phalign_edges < 3 then
+ count_phalign_edges <= count_phalign_edges + 1;
+ end if;
+ end if;
+
+ DLYSRESET <= '0';
+
+ case phalign_state is
+ when INIT =>
+ PHASE_ALIGNMENT_DONE <= '0';
+ if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then
+ --DLYSRESET is toggled to '1'
+ DLYSRESET <= '1';
+ phalign_state <= WAIT_PHRST_DONE;
+ end if;
+
+ when WAIT_PHRST_DONE =>
+ if dlysresetdone_sync = '1' then
+ phalign_state <= COUNT_PHALIGN_DONE;
+ end if;
+ --No timeout-check here as that is done in the main FSM
+
+ when COUNT_PHALIGN_DONE =>
+ if (count_phalign_edges = 2) then
+
+ --For GTX: Only on the second edge of the PHALIGNDONE-signal the
+ -- phase-alignment is completed
+ --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment
+
+ phalign_state <= PHALIGN_DONE;
+ end if;
+
+ when PHALIGN_DONE =>
+ PHASE_ALIGNMENT_DONE <= '1';
+
+ when OTHERS =>
+ phalign_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb_cpll_railing.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_sync_2gb_cpll_railing
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_sync_2gb_cpll_railing is
+generic( USE_BUFG : integer := 0
+ );
+ port (
+ cpll_reset_out : out std_logic;
+ cpll_pd_out : out std_logic;
+ refclk_out : out std_logic;
+
+ refclk_in : in std_logic
+ );
+ end GTX_trb3_sync_2gb_cpll_railing;
+
+
+architecture RTL of GTX_trb3_sync_2gb_cpll_railing is
+
+--**************************** Signal Declarations ****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+
+attribute equivalent_register_removal: string;
+signal cpllpd_wait : std_logic_vector(95 downto 0) := x"FFFFFFFFFFFFFFFFFFFFFFFF";
+signal cpllreset_wait : std_logic_vector(127 downto 0) := x"000000000000000000000000000000FF";
+attribute equivalent_register_removal of cpllpd_wait : signal is "no";
+attribute equivalent_register_removal of cpllreset_wait : signal is "no";
+signal gtrefclk0_i :std_logic ;
+--******************************** Main Body of Code***************************
+
+begin
+
+ --------------------------- Static signal Assignments ---------------------
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+
+ use_bufg_cpll:if(USE_BUFG = 1) generate
+ refclk_buf : BUFG
+ port map
+ (O => gtrefclk0_i,
+ I => refclk_in);
+
+ end generate;
+
+ use_bufr_cpll:if(USE_BUFG = 0) generate
+ refclk_buf : BUFR
+ port map
+ (O => gtrefclk0_i,
+ CE => tied_to_vcc_i,
+ CLR => tied_to_ground_i,
+ I => refclk_in);
+
+ end generate;
+
+ process( gtrefclk0_i )
+ begin
+ if(gtrefclk0_i'event and gtrefclk0_i = '1') then
+ cpllpd_wait <= cpllpd_wait(94 downto 0) & '0';
+ cpllreset_wait <= cpllreset_wait(126 downto 0) & '0';
+ end if;
+ end process;
+
+cpll_pd_out <= cpllpd_wait(95);
+cpll_reset_out <= cpllreset_wait(127);
+refclk_out <= gtrefclk0_i;
+
+
+ end RTL;
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb_gt.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_trb3_sync_2gb_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity GTX_trb3_sync_2gb_GT is
+generic
+(
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
+ RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
+ SIM_CPLLREFCLK_SEL : bit_vector := "001";
+ PMA_RSV_IN : bit_vector := x"00018480";
+ PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
+);
+port
+(
+ cpllpd_in : in std_logic;
+ cpllrefclksel_in : in std_logic_vector(2 downto 0);
+ --------------------------------- CPLL Ports -------------------------------
+ cpllfbclklost_out : out std_logic;
+ cplllock_out : out std_logic;
+ cplllockdetclk_in : in std_logic;
+ cpllrefclklost_out : out std_logic;
+ cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gtrefclk0_in : in std_logic;
+ gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ drpaddr_in : in std_logic_vector(8 downto 0);
+ drpclk_in : in std_logic;
+ drpdi_in : in std_logic_vector(15 downto 0);
+ drpdo_out : out std_logic_vector(15 downto 0);
+ drpen_in : in std_logic;
+ drprdy_out : out std_logic;
+ drpwe_in : in std_logic;
+ ------------------------------- Clocking Ports -----------------------------
+ qpllclk_in : in std_logic;
+ qpllrefclk_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ eyescanreset_in : in std_logic;
+ rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ eyescandataerror_out : out std_logic;
+ eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN : in std_logic; --// Modified
+ RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ rxusrclk_in : in std_logic;
+ rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ rxdisperr_out : out std_logic_vector(1 downto 0);
+ rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ rxdlyen_in : in std_logic;
+ rxdlysreset_in : in std_logic;
+ rxdlysresetdone_out : out std_logic;
+ rxphalign_in : in std_logic;
+ rxphaligndone_out : out std_logic;
+ rxphalignen_in : in std_logic;
+ rxphdlyreset_in : in std_logic;
+ rxphmonitor_out : out std_logic_vector(4 downto 0);
+ rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ rxlpmhfhold_in : in std_logic;
+ rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ rxdfelpmreset_in : in std_logic;
+ rxmonitorout_out : out std_logic_vector(6 downto 0);
+ rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gtrxreset_in : in std_logic;
+ rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gttxreset_in : in std_logic;
+ txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ txusrclk_in : in std_logic;
+ txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ txdlyen_in : in std_logic;
+ txdlysreset_in : in std_logic;
+ txdlysresetdone_out : out std_logic;
+ txphalign_in : in std_logic;
+ txphaligndone_out : out std_logic;
+ txphalignen_in : in std_logic;
+ txphdlyreset_in : in std_logic;
+ txphinit_in : in std_logic;
+ txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gtxtxn_out : out std_logic;
+ gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ txoutclk_out : out std_logic;
+ txoutclkfabric_out : out std_logic;
+ txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ txresetdone_out : out std_logic
+
+
+);
+
+
+end GTX_trb3_sync_2gb_GT;
+
+architecture RTL of GTX_trb3_sync_2gb_GT is
+
+--**************************** Signal Declarations ****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+
+
+
+ -- RX Datapath signals
+ signal rxdata_i : std_logic_vector(63 downto 0);
+ signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
+ signal rxcharisk_float_i : std_logic_vector(5 downto 0);
+ signal rxdisperr_float_i : std_logic_vector(5 downto 0);
+ signal rxnotintable_float_i : std_logic_vector(5 downto 0);
+ signal rxrundisp_float_i : std_logic_vector(5 downto 0);
+
+
+ -- TX Datapath signals
+ signal txdata_i : std_logic_vector(63 downto 0);
+ signal txkerr_float_i : std_logic_vector(5 downto 0);
+ signal txrundisp_float_i : std_logic_vector(5 downto 0);
+ signal rxstartofseq_float_i : std_logic;
+--******************************** Main Body of Code***************************
+
+begin
+
+ --------------------------- Static signal Assignments ---------------------
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+
+ ------------------- GT Datapath byte mapping -----------------
+ RXDATA_OUT <= rxdata_i(15 downto 0);
+
+ txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+ ----------------------------- GTXE2 Instance --------------------------
+
+ gtxe2_i :GTXE2_CHANNEL
+ generic map
+ (
+
+ --_______________________ Simulation-Only Attributes ___________________
+
+ SIM_RECEIVER_DETECT_PASS => ("TRUE"),
+ SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
+ SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
+ SIM_CPLLREFCLK_SEL => (SIM_CPLLREFCLK_SEL),
+ SIM_VERSION => ("4.0"),
+
+
+ ------------------RX Byte and Word Alignment Attributes---------------
+ ALIGN_COMMA_DOUBLE => ("FALSE"),
+ ALIGN_COMMA_ENABLE => ("1111111111"),
+ ALIGN_COMMA_WORD => (1),
+ ALIGN_MCOMMA_DET => ("TRUE"),
+ ALIGN_MCOMMA_VALUE => ("1010000011"),
+ ALIGN_PCOMMA_DET => ("TRUE"),
+ ALIGN_PCOMMA_VALUE => ("0101111100"),
+ SHOW_REALIGN_COMMA => ("FALSE"), --//("TRUE"), Modified
+ RXSLIDE_AUTO_WAIT => (7),
+ RXSLIDE_MODE => ("AUTO"), --// ("PCS"), Modified
+ RX_SIG_VALID_DLY => (10),
+
+ ------------------RX 8B/10B Decoder Attributes---------------
+ RX_DISPERR_SEQ_MATCH => ("TRUE"),
+ DEC_MCOMMA_DETECT => ("TRUE"),
+ DEC_PCOMMA_DETECT => ("TRUE"),
+ DEC_VALID_COMMA_ONLY => ("FALSE"),
+
+ ------------------------RX Clock Correction Attributes----------------------
+ CBCC_DATA_SOURCE_SEL => ("DECODED"),
+ CLK_COR_SEQ_2_USE => ("FALSE"),
+ CLK_COR_KEEP_IDLE => ("FALSE"),
+ CLK_COR_MAX_LAT => (9),
+ CLK_COR_MIN_LAT => (7),
+ CLK_COR_PRECEDENCE => ("TRUE"),
+ CLK_COR_REPEAT_WAIT => (0),
+ CLK_COR_SEQ_LEN => (1),
+ CLK_COR_SEQ_1_ENABLE => ("1111"),
+ CLK_COR_SEQ_1_1 => ("0100000000"),
+ CLK_COR_SEQ_1_2 => ("0000000000"),
+ CLK_COR_SEQ_1_3 => ("0000000000"),
+ CLK_COR_SEQ_1_4 => ("0000000000"),
+ CLK_CORRECT_USE => ("FALSE"),
+ CLK_COR_SEQ_2_ENABLE => ("1111"),
+ CLK_COR_SEQ_2_1 => ("0100000000"),
+ CLK_COR_SEQ_2_2 => ("0000000000"),
+ CLK_COR_SEQ_2_3 => ("0000000000"),
+ CLK_COR_SEQ_2_4 => ("0000000000"),
+
+ ------------------------RX Channel Bonding Attributes----------------------
+ CHAN_BOND_KEEP_ALIGN => ("FALSE"),
+ CHAN_BOND_MAX_SKEW => (1),
+ CHAN_BOND_SEQ_LEN => (1),
+ CHAN_BOND_SEQ_1_1 => ("0000000000"),
+ CHAN_BOND_SEQ_1_2 => ("0000000000"),
+ CHAN_BOND_SEQ_1_3 => ("0000000000"),
+ CHAN_BOND_SEQ_1_4 => ("0000000000"),
+ CHAN_BOND_SEQ_1_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_1 => ("0000000000"),
+ CHAN_BOND_SEQ_2_2 => ("0000000000"),
+ CHAN_BOND_SEQ_2_3 => ("0000000000"),
+ CHAN_BOND_SEQ_2_4 => ("0000000000"),
+ CHAN_BOND_SEQ_2_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_USE => ("FALSE"),
+ FTS_DESKEW_SEQ_ENABLE => ("1111"),
+ FTS_LANE_DESKEW_CFG => ("1111"),
+ FTS_LANE_DESKEW_EN => ("FALSE"),
+
+ ---------------------------RX Margin Analysis Attributes----------------------------
+ ES_CONTROL => ("000000"),
+ ES_ERRDET_EN => ("FALSE"),
+ ES_EYE_SCAN_EN => ("TRUE"),
+ ES_HORZ_OFFSET => (x"000"),
+ ES_PMA_CFG => ("0000000000"),
+ ES_PRESCALE => ("00000"),
+ ES_QUALIFIER => (x"00000000000000000000"),
+ ES_QUAL_MASK => (x"00000000000000000000"),
+ ES_SDATA_MASK => (x"00000000000000000000"),
+ ES_VERT_OFFSET => ("000000000"),
+
+ -------------------------FPGA RX Interface Attributes-------------------------
+ RX_DATA_WIDTH => (20),
+
+ ---------------------------PMA Attributes----------------------------
+ OUTREFCLK_SEL_INV => ("11"),
+ PMA_RSV => (PMA_RSV_IN),
+ PMA_RSV2 => (x"2050"),
+ PMA_RSV3 => ("00"),
+ PMA_RSV4 => (x"00000000"),
+ RX_BIAS_CFG => ("000000000100"),
+ DMONITOR_CFG => (x"000A00"),
+ RX_CM_SEL => ("00"),
+ RX_CM_TRIM => ("010"),
+ RX_DEBUG_CFG => ("000000000000"),
+ RX_OS_CFG => ("0000010000000"),
+ TERM_RCAL_CFG => ("10000"),
+ TERM_RCAL_OVRD => ('0'),
+ TST_RSV => (x"00000000"),
+ RX_CLK25_DIV => (5),
+ TX_CLK25_DIV => (5),
+ UCODEER_CLR => ('0'),
+
+ ---------------------------PCI Express Attributes----------------------------
+ PCS_PCIE_EN => ("FALSE"),
+
+ ---------------------------PCS Attributes----------------------------
+ PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
+
+ -------------RX Buffer Attributes------------
+ RXBUF_ADDR_MODE => ("FAST"),
+ RXBUF_EIDLE_HI_CNT => ("1000"),
+ RXBUF_EIDLE_LO_CNT => ("0000"),
+ RXBUF_EN => ("FALSE"),
+ RX_BUFFER_CFG => ("000000"),
+ RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
+ RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
+ RXBUF_RESET_ON_EIDLE => ("FALSE"),
+ RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
+ RXBUFRESET_TIME => ("00001"),
+ RXBUF_THRESH_OVFLW => (61),
+ RXBUF_THRESH_OVRD => ("FALSE"),
+ RXBUF_THRESH_UNDFLW => (4),
+ RXDLY_CFG => (x"001F"),
+ RXDLY_LCFG => (x"030"),
+ RXDLY_TAP_CFG => (x"0000"),
+ RXPH_CFG => (x"000000"),
+ RXPHDLY_CFG => (x"084020"),
+ RXPH_MONITOR_SEL => ("00000"),
+ RX_XCLK_SEL => ("RXUSR"),
+ RX_DDI_SEL => ("000000"),
+ RX_DEFER_RESET_BUF_EN => ("TRUE"),
+
+ -----------------------CDR Attributes-------------------------
+
+ --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+ --For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010
+
+ --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
+
+ --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
+
+ --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
+
+ --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
+
+ --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
+
+ --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
+ RXCDR_CFG => (x"03000023ff10200020"),
+ RXCDR_FR_RESET_ON_EIDLE => ('0'),
+ RXCDR_HOLD_DURING_EIDLE => ('0'),
+ RXCDR_PH_RESET_ON_EIDLE => ('0'),
+ RXCDR_LOCK_CFG => ("010101"),
+
+ -------------------RX Initialization and Reset Attributes-------------------
+ RXCDRFREQRESET_TIME => ("00001"),
+ RXCDRPHRESET_TIME => ("00001"),
+ RXISCANRESET_TIME => ("00001"),
+ RXPCSRESET_TIME => ("00001"),
+ RXPMARESET_TIME => ("00011"),
+
+ -------------------RX OOB Signaling Attributes-------------------
+ RXOOB_CFG => ("0000110"),
+
+ -------------------------RX Gearbox Attributes---------------------------
+ RXGEARBOX_EN => ("FALSE"),
+ GEARBOX_MODE => ("000"),
+
+ -------------------------PRBS Detection Attribute-----------------------
+ RXPRBS_ERR_LOOPBACK => ('0'),
+
+ -------------Power-Down Attributes----------
+ PD_TRANS_TIME_FROM_P2 => (x"03c"),
+ PD_TRANS_TIME_NONE_P2 => (x"3c"),
+ PD_TRANS_TIME_TO_P2 => (x"64"),
+
+ -------------RX OOB Signaling Attributes----------
+ SAS_MAX_COM => (64),
+ SAS_MIN_COM => (36),
+ SATA_BURST_SEQ_LEN => ("0101"),
+ SATA_BURST_VAL => ("100"),
+ SATA_EIDLE_VAL => ("100"),
+ SATA_MAX_BURST => (8),
+ SATA_MAX_INIT => (21),
+ SATA_MAX_WAKE => (7),
+ SATA_MIN_BURST => (4),
+ SATA_MIN_INIT => (12),
+ SATA_MIN_WAKE => (4),
+
+ -------------RX Fabric Clock Output Control Attributes----------
+ TRANS_TIME_RATE => (x"0E"),
+
+ --------------TX Buffer Attributes----------------
+ TXBUF_EN => ("FALSE"),
+ TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
+ TXDLY_CFG => (x"001F"),
+ TXDLY_LCFG => (x"030"),
+ TXDLY_TAP_CFG => (x"0000"),
+ TXPH_CFG => (x"0780"),
+ TXPHDLY_CFG => (x"084020"),
+ TXPH_MONITOR_SEL => ("00000"),
+ TX_XCLK_SEL => ("TXUSR"),
+
+ -------------------------FPGA TX Interface Attributes-------------------------
+ TX_DATA_WIDTH => (20),
+
+ -------------------------TX Configurable Driver Attributes-------------------------
+ TX_DEEMPH0 => ("00000"),
+ TX_DEEMPH1 => ("00000"),
+ TX_EIDLE_ASSERT_DELAY => ("110"),
+ TX_EIDLE_DEASSERT_DELAY => ("100"),
+ TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
+ TX_MAINCURSOR_SEL => ('0'),
+ TX_DRIVE_MODE => ("DIRECT"),
+ TX_MARGIN_FULL_0 => ("1001110"),
+ TX_MARGIN_FULL_1 => ("1001001"),
+ TX_MARGIN_FULL_2 => ("1000101"),
+ TX_MARGIN_FULL_3 => ("1000010"),
+ TX_MARGIN_FULL_4 => ("1000000"),
+ TX_MARGIN_LOW_0 => ("1000110"),
+ TX_MARGIN_LOW_1 => ("1000100"),
+ TX_MARGIN_LOW_2 => ("1000010"),
+ TX_MARGIN_LOW_3 => ("1000000"),
+ TX_MARGIN_LOW_4 => ("1000000"),
+
+ -------------------------TX Gearbox Attributes--------------------------
+ TXGEARBOX_EN => ("FALSE"),
+
+ -------------------------TX Initialization and Reset Attributes--------------------------
+ TXPCSRESET_TIME => ("00001"),
+ TXPMARESET_TIME => ("00001"),
+
+ -------------------------TX Receiver Detection Attributes--------------------------
+ TX_RXDETECT_CFG => (x"1832"),
+ TX_RXDETECT_REF => ("100"),
+
+ ----------------------------CPLL Attributes----------------------------
+ CPLL_CFG => (x"BC07DC"),
+ CPLL_FBDIV => (4),
+ CPLL_FBDIV_45 => (4),
+ CPLL_INIT_CFG => (x"00001E"),
+ CPLL_LOCK_CFG => (x"01E8"),
+ CPLL_REFCLK_DIV => (1),
+ RXOUT_DIV => (2),
+ TXOUT_DIV => (2),
+ SATA_CPLL_CFG => ("VCO_3000MHZ"),
+
+ --------------RX Initialization and Reset Attributes-------------
+ RXDFELPMRESET_TIME => ("0001111"),
+
+ --------------RX Equalizer Attributes-------------
+ RXLPM_HF_CFG => ("00000011110000"),
+ RXLPM_LF_CFG => ("00000011110000"),
+ RX_DFE_GAIN_CFG => (x"020FEA"),
+ RX_DFE_H2_CFG => ("000000000000"),
+ RX_DFE_H3_CFG => ("000001000000"),
+ RX_DFE_H4_CFG => ("00011110000"),
+ RX_DFE_H5_CFG => ("00011100000"),
+ RX_DFE_KL_CFG => ("0000011111110"),
+ RX_DFE_LPM_CFG => (x"0904"),
+ RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
+ RX_DFE_UT_CFG => ("10001111000000000"),
+ RX_DFE_VP_CFG => ("00011111100000011"),
+
+ -------------------------Power-Down Attributes-------------------------
+ RX_CLKMUX_PD => ('1'),
+ TX_CLKMUX_PD => ('1'),
+
+ -------------------------FPGA RX Interface Attribute-------------------------
+ RX_INT_DATAWIDTH => (0),
+
+ -------------------------FPGA TX Interface Attribute-------------------------
+ TX_INT_DATAWIDTH => (0),
+
+ ------------------TX Configurable Driver Attributes---------------
+ TX_QPI_STATUS_EN => ('0'),
+
+ -------------------------RX Equalizer Attributes--------------------------
+ RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
+ RX_DFE_XYD_CFG => ("0000000000000"),
+
+ -------------------------TX Configurable Driver Attributes--------------------------
+ TX_PREDRIVER_MODE => ('0')
+
+
+ )
+ port map
+ (
+ --------------------------------- CPLL Ports -------------------------------
+ CPLLFBCLKLOST => cpllfbclklost_out,
+ CPLLLOCK => cplllock_out,
+ CPLLLOCKDETCLK => cplllockdetclk_in,
+ CPLLLOCKEN => tied_to_vcc_i,
+ CPLLPD => cpllpd_in,
+ CPLLREFCLKLOST => cpllrefclklost_out,
+ CPLLREFCLKSEL => cpllrefclksel_in,
+ CPLLRESET => cpllreset_in,
+ GTRSVD => "0000000000000000",
+ PCSRSVDIN => "0000000000000000",
+ PCSRSVDIN2 => "00000",
+ PMARSVDIN => "00000",
+ PMARSVDIN2 => "00000",
+ TSTIN => "11111111111111111111",
+ TSTOUT => open,
+ ---------------------------------- Channel ---------------------------------
+ CLKRSVD => tied_to_ground_vec_i(3 downto 0),
+ -------------------------- Channel - Clocking Ports ------------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => gtrefclk0_in,
+ GTREFCLK1 => gtrefclk1_in,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ DRPADDR => drpaddr_in,
+ DRPCLK => drpclk_in,
+ DRPDI => drpdi_in,
+ DRPDO => drpdo_out,
+ DRPEN => drpen_in,
+ DRPRDY => drprdy_out,
+ DRPWE => drpwe_in,
+ ------------------------------- Clocking Ports -----------------------------
+ GTREFCLKMONITOR => open,
+ QPLLCLK => qpllclk_in,
+ QPLLREFCLK => qpllrefclk_in,
+ RXSYSCLKSEL => "00",
+ TXSYSCLKSEL => "00",
+ --------------------------- Digital Monitor Ports --------------------------
+ DMONITOROUT => dmonitorout_out,
+ ----------------- FPGA TX Interface Datapath Configuration ----------------
+ TX8B10BEN => tied_to_vcc_i,
+ ------------------------------- Loopback Ports -----------------------------
+ LOOPBACK => tied_to_ground_vec_i(2 downto 0),
+ ----------------------------- PCI Express Ports ----------------------------
+ PHYSTATUS => open,
+ RXRATE => tied_to_ground_vec_i(2 downto 0),
+ RXVALID => open,
+ ------------------------------ Power-Down Ports ----------------------------
+ RXPD => "00",
+ TXPD => "00",
+ -------------------------- RX 8B/10B Decoder Ports -------------------------
+ SETERRSTATUS => tied_to_ground_i,
+ --------------------- RX Initialization and Reset Ports --------------------
+ EYESCANRESET => eyescanreset_in,
+ RXUSERRDY => rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ EYESCANDATAERROR => eyescandataerror_out,
+ EYESCANMODE => tied_to_ground_i,
+ EYESCANTRIGGER => eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRFREQRESET => tied_to_ground_i,
+ RXCDRHOLD => tied_to_ground_i,
+ RXCDRLOCK => RXCDRLOCK_OUT, --// Modified
+ RXCDROVRDEN => tied_to_ground_i,
+ RXCDRRESET => RXCDRRESET_IN, --// Modified
+ RXCDRRESETRSV => tied_to_ground_i,
+ ------------------- Receive Ports - Clock Correction Ports -----------------
+ RXCLKCORCNT => open,
+ ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+ RX8B10BEN => tied_to_vcc_i,
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ RXUSRCLK => rxusrclk_in,
+ RXUSRCLK2 => rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ RXDATA => rxdata_i,
+ ------------------- Receive Ports - Pattern Checker Ports ------------------
+ RXPRBSERR => open,
+ RXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
+ ------------------- Receive Ports - Pattern Checker ports ------------------
+ RXPRBSCNTRESET => tied_to_ground_i,
+ -------------------- Receive Ports - RX Equalizer Ports -------------------
+ RXDFEXYDEN => tied_to_vcc_i,
+ RXDFEXYDHOLD => tied_to_ground_i,
+ RXDFEXYDOVRDEN => tied_to_ground_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ RXDISPERR(7 downto 2) => rxdisperr_float_i,
+ RXDISPERR(1 downto 0) => rxdisperr_out,
+ RXNOTINTABLE(7 downto 2) => rxnotintable_float_i,
+ RXNOTINTABLE(1 downto 0) => rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ GTXRXP => gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ GTXRXN => gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ RXBUFRESET => tied_to_ground_i,
+ RXBUFSTATUS => open,
+ RXDDIEN => tied_to_vcc_i,
+ RXDLYBYPASS => tied_to_ground_i,
+ RXDLYEN => rxdlyen_in,
+ RXDLYOVRDEN => tied_to_ground_i,
+ RXDLYSRESET => rxdlysreset_in,
+ RXDLYSRESETDONE => rxdlysresetdone_out,
+ RXPHALIGN => rxphalign_in,
+ RXPHALIGNDONE => rxphaligndone_out,
+ RXPHALIGNEN => rxphalignen_in,
+ RXPHDLYPD => tied_to_ground_i,
+ RXPHDLYRESET => rxphdlyreset_in,
+ RXPHMONITOR => rxphmonitor_out,
+ RXPHOVRDEN => tied_to_ground_i,
+ RXPHSLIPMONITOR => rxphslipmonitor_out,
+ RXSTATUS => open,
+ -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+ RXBYTEISALIGNED => open,
+ RXBYTEREALIGN => open,
+ RXCOMMADET => open,
+ RXCOMMADETEN => tied_to_vcc_i,
+ RXMCOMMAALIGNEN => tied_to_vcc_i,
+ RXPCOMMAALIGNEN => tied_to_vcc_i,
+ ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+ RXCHANBONDSEQ => open,
+ RXCHBONDEN => tied_to_ground_i,
+ RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
+ RXCHBONDMASTER => tied_to_ground_i,
+ RXCHBONDO => open,
+ RXCHBONDSLAVE => tied_to_ground_i,
+ ----------------- Receive Ports - RX Channel Bonding Ports ----------------
+ RXCHANISALIGNED => open,
+ RXCHANREALIGN => open,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ RXLPMHFHOLD => rxlpmhfhold_in,
+ RXLPMHFOVRDEN => tied_to_ground_i,
+ RXLPMLFHOLD => rxlpmlfhold_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ RXDFEAGCHOLD => tied_to_ground_i,
+ RXDFEAGCOVRDEN => tied_to_ground_i,
+ RXDFECM1EN => tied_to_ground_i,
+ RXDFELFHOLD => tied_to_ground_i,
+ RXDFELFOVRDEN => tied_to_ground_i,
+ RXDFELPMRESET => rxdfelpmreset_in,
+ RXDFETAP2HOLD => tied_to_ground_i,
+ RXDFETAP2OVRDEN => tied_to_ground_i,
+ RXDFETAP3HOLD => tied_to_ground_i,
+ RXDFETAP3OVRDEN => tied_to_ground_i,
+ RXDFETAP4HOLD => tied_to_ground_i,
+ RXDFETAP4OVRDEN => tied_to_ground_i,
+ RXDFETAP5HOLD => tied_to_ground_i,
+ RXDFETAP5OVRDEN => tied_to_ground_i,
+ RXDFEUTHOLD => tied_to_ground_i,
+ RXDFEUTOVRDEN => tied_to_ground_i,
+ RXDFEVPHOLD => tied_to_ground_i,
+ RXDFEVPOVRDEN => tied_to_ground_i,
+ RXDFEVSEN => tied_to_ground_i,
+ RXLPMLFKLOVRDEN => tied_to_ground_i,
+ RXMONITOROUT => rxmonitorout_out,
+ RXMONITORSEL => rxmonitorsel_in,
+ RXOSHOLD => tied_to_ground_i,
+ RXOSOVRDEN => tied_to_ground_i,
+ ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+ RXRATEDONE => open,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ RXOUTCLK => rxoutclk_out,
+ RXOUTCLKFABRIC => open,
+ RXOUTCLKPCS => open,
+ RXOUTCLKSEL => "010",
+ ---------------------- Receive Ports - RX Gearbox Ports --------------------
+ RXDATAVALID => open,
+ RXHEADER => open,
+ RXHEADERVALID => open,
+ RXSTARTOFSEQ => open,
+ --------------------- Receive Ports - RX Gearbox Ports --------------------
+ RXGEARBOXSLIP => tied_to_ground_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ GTRXRESET => gtrxreset_in,
+ RXOOBRESET => tied_to_ground_i,
+ RXPCSRESET => tied_to_ground_i,
+ RXPMARESET => rxpmareset_in,
+ ------------------ Receive Ports - RX Margin Analysis ports ----------------
+ RXLPMEN => tied_to_vcc_i,
+ ------------------- Receive Ports - RX OOB Signaling ports -----------------
+ RXCOMSASDET => open,
+ RXCOMWAKEDET => open,
+ ------------------ Receive Ports - RX OOB Signaling ports -----------------
+ RXCOMINITDET => open,
+ ------------------ Receive Ports - RX OOB signalling Ports -----------------
+ RXELECIDLE => open,
+ RXELECIDLEMODE => "11",
+ ----------------- Receive Ports - RX Polarity Control Ports ----------------
+ RXPOLARITY => tied_to_ground_i,
+ ---------------------- Receive Ports - RX gearbox ports --------------------
+ RXSLIDE => tied_to_ground_i,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ RXCHARISCOMMA => open,
+ RXCHARISK(7 downto 2) => rxcharisk_float_i,
+ RXCHARISK(1 downto 0) => rxcharisk_out,
+ ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+ RXCHBONDI => "00000",
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ RXRESETDONE => rxresetdone_out,
+ -------------------------------- Rx AFE Ports ------------------------------
+ RXQPIEN => tied_to_ground_i,
+ RXQPISENN => open,
+ RXQPISENP => open,
+ --------------------------- TX Buffer Bypass Ports -------------------------
+ TXPHDLYTSTCLK => tied_to_ground_i,
+ ------------------------ TX Configurable Driver Ports ----------------------
+ TXPOSTCURSOR => "00000",
+ TXPOSTCURSORINV => tied_to_ground_i,
+ TXPRECURSOR => tied_to_ground_vec_i(4 downto 0),
+ TXPRECURSORINV => tied_to_ground_i,
+ TXQPIBIASEN => tied_to_ground_i,
+ TXQPISTRONGPDOWN => tied_to_ground_i,
+ TXQPIWEAKPUP => tied_to_ground_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ CFGRESET => tied_to_ground_i,
+ GTTXRESET => gttxreset_in,
+ PCSRSVDOUT => open,
+ TXUSERRDY => txuserrdy_in,
+ ---------------------- Transceiver Reset Mode Operation --------------------
+ GTRESETSEL => tied_to_ground_i,
+ RESETOVRD => tied_to_ground_i,
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ TXCHARDISPMODE => tied_to_ground_vec_i(7 downto 0),
+ TXCHARDISPVAL => tied_to_ground_vec_i(7 downto 0),
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ TXUSRCLK => txusrclk_in,
+ TXUSRCLK2 => txusrclk2_in,
+ --------------------- Transmit Ports - PCI Express Ports -------------------
+ TXELECIDLE => tied_to_ground_i,
+ TXMARGIN => tied_to_ground_vec_i(2 downto 0),
+ TXRATE => tied_to_ground_vec_i(2 downto 0),
+ TXSWING => tied_to_ground_i,
+ ------------------ Transmit Ports - Pattern Generator Ports ----------------
+ TXPRBSFORCEERR => tied_to_ground_i,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ TXDLYBYPASS => tied_to_ground_i,
+ TXDLYEN => txdlyen_in,
+ TXDLYHOLD => tied_to_ground_i,
+ TXDLYOVRDEN => tied_to_ground_i,
+ TXDLYSRESET => txdlysreset_in,
+ TXDLYSRESETDONE => txdlysresetdone_out,
+ TXDLYUPDOWN => tied_to_ground_i,
+ TXPHALIGN => txphalign_in,
+ TXPHALIGNDONE => txphaligndone_out,
+ TXPHALIGNEN => txphalignen_in,
+ TXPHDLYPD => tied_to_ground_i,
+ TXPHDLYRESET => txphdlyreset_in,
+ TXPHINIT => txphinit_in,
+ TXPHINITDONE => txphinitdone_out,
+ TXPHOVRDEN => tied_to_ground_i,
+ ---------------------- Transmit Ports - TX Buffer Ports --------------------
+ TXBUFSTATUS => open,
+ --------------- Transmit Ports - TX Configurable Driver Ports --------------
+ TXBUFDIFFCTRL => "100",
+ TXDEEMPH => tied_to_ground_i,
+ TXDIFFCTRL => "1000",
+ TXDIFFPD => tied_to_ground_i,
+ TXINHIBIT => tied_to_ground_i,
+ TXMAINCURSOR => "0000000",
+ TXPISOPD => tied_to_ground_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA => txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTXTXN => gtxtxn_out,
+ GTXTXP => gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ TXOUTCLK => txoutclk_out,
+ TXOUTCLKFABRIC => txoutclkfabric_out,
+ TXOUTCLKPCS => txoutclkpcs_out,
+ TXOUTCLKSEL => "011",
+ TXRATEDONE => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ TXCHARISK(7 downto 2) => tied_to_ground_vec_i(5 downto 0),
+ TXCHARISK(1 downto 0) => txcharisk_in,
+ TXGEARBOXREADY => open,
+ TXHEADER => tied_to_ground_vec_i(2 downto 0),
+ TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
+ TXSTARTSEQ => tied_to_ground_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ TXPCSRESET => tied_to_ground_i,
+ TXPMARESET => tied_to_ground_i,
+ TXRESETDONE => txresetdone_out,
+ ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+ TXCOMFINISH => open,
+ TXCOMINIT => tied_to_ground_i,
+ TXCOMSAS => tied_to_ground_i,
+ TXCOMWAKE => tied_to_ground_i,
+ TXPDELECIDLEMODE => tied_to_ground_i,
+ ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+ TXPOLARITY => tied_to_ground_i,
+ --------------- Transmit Ports - TX Receiver Detection Ports --------------
+ TXDETECTRX => tied_to_ground_i,
+ ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+ TX8B10BBYPASS => tied_to_ground_vec_i(7 downto 0),
+ ------------------ Transmit Ports - pattern Generator Ports ----------------
+ TXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
+ ----------------------- Tx Configurable Driver Ports ----------------------
+ TXQPISENN => open,
+ TXQPISENP => open
+
+ );
+
+
+ end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb_init.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_sync_2gb_init
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_sync_2gb_init is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+
+ STABLE_CLOCK_PERIOD : integer := 10;
+ -- Set to 1 for simulation
+ EXAMPLE_USE_CHIPSCOPE : integer := 1 --// Modified -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end GTX_trb3_sync_2gb_init;
+
+architecture RTL of GTX_trb3_sync_2gb_init is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+
+component GTX_trb3_sync_2gb_multi_gt
+generic
+(
+ -- Simulation attributes
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
+
+);
+port
+(
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllrefclklost_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxdlyen_in : in std_logic;
+ gt0_rxdlysreset_in : in std_logic;
+ gt0_rxdlysresetdone_out : out std_logic;
+ gt0_rxphalign_in : in std_logic;
+ gt0_rxphaligndone_out : out std_logic;
+ gt0_rxphalignen_in : in std_logic;
+ gt0_rxphdlyreset_in : in std_logic;
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ gt0_rxlpmhfhold_in : in std_logic;
+ gt0_rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ gt0_txdlyen_in : in std_logic;
+ gt0_txdlysreset_in : in std_logic;
+ gt0_txdlysresetdone_out : out std_logic;
+ gt0_txphalign_in : in std_logic;
+ gt0_txphaligndone_out : out std_logic;
+ gt0_txphalignen_in : in std_logic;
+ gt0_txphdlyreset_in : in std_logic;
+ gt0_txphinit_in : in std_logic;
+ gt0_txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end component;
+
+component GTX_trb3_sync_2gb_TX_STARTUP_FSM
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ TXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ GTTXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='0';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
+ TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
+ TXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC:='0';
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ PHALIGNMENT_DONE : in STD_LOGIC;
+
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end component;
+
+component GTX_trb3_sync_2gb_RX_STARTUP_FSM
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ EQ_MODE : string := "DFE";
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ RXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ RECCLK_STABLE : in STD_LOGIC;
+ RECCLK_MONITOR_RESTART : in STD_LOGIC;
+ DATA_VALID : in STD_LOGIC;
+ TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
+ DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
+ GTRXRESET : out STD_LOGIC:='0';
+ MMCM_RESET : out STD_LOGIC:='0';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
+ RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
+ RXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC;
+ PHALIGNMENT_DONE : in STD_LOGIC;
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ RXDFEAGCHOLD : out STD_LOGIC;
+ RXDFELFHOLD : out STD_LOGIC;
+ RXLPMLFHOLD : out STD_LOGIC;
+ RXLPMHFHOLD : out STD_LOGIC;
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end component;
+
+
+
+
+component GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN
+ port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC; -- Auto phase-alignment performed sucessfully
+ PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the
+ DLYSRESET : out STD_LOGIC; -- |transceiver.
+ DLYSRESETDONE : in STD_LOGIC; --/
+ RECCLKSTABLE : in STD_LOGIC --/on the RX-side.
+
+ );
+end component;
+
+
+component GTX_trb3_sync_2gb_TX_MANUAL_PHASE_ALIGN
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ TXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHINIT : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHINITDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ TXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ TXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end component;
+
+component GTX_trb3_sync_2gb_RX_MANUAL_PHASE_ALIGN
+ Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM.
+ MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment
+ );
+
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RESET_PHALIGNMENT : in STD_LOGIC;
+ RUN_PHALIGNMENT : in STD_LOGIC;
+ PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully
+ RXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+ RXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+ RXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+ );
+end component;
+
+ function get_cdrlock_time(is_sim : in integer) return integer is
+ variable lock_time: integer;
+ begin
+ if (is_sim = 1) then
+ lock_time := 1000;
+ else
+ lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183
+ end if;
+ return lock_time;
+ end function;
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+ constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
+ constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
+
+
+
+ -------------------------- GT Wrapper Wires ------------------------------
+ signal gt0_txpmaresetdone_i : std_logic;
+ signal gt0_rxpmaresetdone_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ signal gt0_cpllreset_t : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_txresetdone_i : std_logic;
+ signal gt0_rxresetdone_i : std_logic;
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_gttxreset_t : std_logic;
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_gtrxreset_t : std_logic;
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ signal gt0_txuserrdy_t : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ signal gt0_rxuserrdy_t : std_logic;
+
+ signal gt0_rxdfeagchold_i : std_logic;
+ signal gt0_rxdfelfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ signal gt0_rxlpmhfhold_i : std_logic;
+
+
+
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qplllock_i : std_logic;
+
+
+ ------------------------------- Global Signals -----------------------------
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ signal gt0_run_tx_phalignment_i : std_logic;
+ signal gt0_rst_tx_phalignment_i : std_logic;
+ signal gt0_tx_phalignment_done_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+ signal gt0_rxoutclk_i2 : std_logic;
+ signal gt0_txoutclk_i2 : std_logic;
+ signal gt0_recclk_stable_i : std_logic;
+ signal gt0_rx_cdrlocked : std_logic;
+ signal gt0_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_run_rx_phalignment_i : std_logic;
+ signal gt0_rst_rx_phalignment_i : std_logic;
+ signal gt0_rx_phalignment_done_i : std_logic;
+
+
+
+ --------------------------- TX Buffer Bypass Signals --------------------
+ signal mstr0_txsyncallin_i : std_logic;
+ signal U0_TXDLYEN : std_logic_vector(0 downto 0);
+ signal U0_TXDLYSRESET : std_logic_vector(0 downto 0);
+ signal U0_TXDLYSRESETDONE : std_logic_vector(0 downto 0);
+ signal U0_TXPHINIT : std_logic_vector(0 downto 0);
+ signal U0_TXPHINITDONE : std_logic_vector(0 downto 0);
+ signal U0_TXPHALIGN : std_logic_vector(0 downto 0);
+ signal U0_TXPHALIGNDONE : std_logic_vector(0 downto 0);
+ signal U0_run_tx_phalignment_i : std_logic;
+ signal U0_rst_tx_phalignment_i : std_logic;
+
+
+ --------------------------- RX Buffer Bypass Signals --------------------
+ signal rxmstr0_rxsyncallin_i : std_logic;
+ signal U0_RXDLYEN : std_logic_vector(0 downto 0);
+ signal U0_RXDLYSRESET : std_logic_vector(0 downto 0);
+ signal U0_RXDLYSRESETDONE : std_logic_vector(0 downto 0);
+ signal U0_RXPHALIGN : std_logic_vector(0 downto 0);
+ signal U0_RXPHALIGNDONE : std_logic_vector(0 downto 0);
+ signal U0_run_rx_phalignment_i : std_logic;
+ signal U0_rst_rx_phalignment_i : std_logic;
+
+
+
+ signal rx_cdrlocked : std_logic;
+
+
+
+
+
+--**************************** Main Body of Code *******************************
+begin
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+
+ ----------------------------- The GT Wrapper -----------------------------
+
+ -- Use the instantiation template in the example directory to add the GT wrapper to your design.
+ -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
+ -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
+ -- enabled, bonding should occur after alignment.
+
+
+ GTX_trb3_sync_2gb_i : GTX_trb3_sync_2gb_multi_gt
+ generic map
+ (
+ USE_BUFG => USE_BUFG,
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
+ )
+ port map
+ (
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y10)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_i,
+ gt0_cplllockdetclk_in => gt0_cplllockdetclk_in,
+ gt0_cpllrefclklost_out => gt0_cpllrefclklost_i,
+ gt0_cpllreset_in => gt0_cpllreset_i,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => gt0_gtrefclk0_in,
+ gt0_gtrefclk1_in => gt0_gtrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => gt0_drpclk_in,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_i,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_in,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxdlyen_in => gt0_rxdlyen_i,
+ gt0_rxdlysreset_in => gt0_rxdlysreset_i,
+ gt0_rxdlysresetdone_out => gt0_rxdlysresetdone_i,
+ gt0_rxphalign_in => gt0_rxphalign_i,
+ gt0_rxphaligndone_out => gt0_rxphaligndone_i,
+ gt0_rxphalignen_in => gt0_rxphalignen_i,
+ gt0_rxphdlyreset_in => gt0_rxphdlyreset_i,
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ gt0_rxlpmhfhold_in => gt0_rxlpmhfhold_i,
+ gt0_rxlpmlfhold_in => gt0_rxlpmlfhold_i,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_i,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_i,
+ gt0_txuserrdy_in => gt0_txuserrdy_i,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_in,
+ gt0_txusrclk2_in => gt0_txusrclk2_in,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ gt0_txdlyen_in => gt0_txdlyen_i,
+ gt0_txdlysreset_in => gt0_txdlysreset_i,
+ gt0_txdlysresetdone_out => gt0_txdlysresetdone_i,
+ gt0_txphalign_in => gt0_txphalign_i,
+ gt0_txphaligndone_out => gt0_txphaligndone_i,
+ gt0_txphalignen_in => gt0_txphalignen_i,
+ gt0_txphdlyreset_in => gt0_txphdlyreset_i,
+ gt0_txphinit_in => gt0_txphinit_i,
+ gt0_txphinitdone_out => gt0_txphinitdone_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_i,
+
+
+
+
+ --____________________________COMMON PORTS________________________________
+ gt0_qplloutclk_in => gt0_qplloutclk_in,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_in
+ );
+
+
+gt0_rxdfelpmreset_i <= tied_to_ground_i;
+
+
+GT0_CPLLLOCK_OUT <= gt0_cplllock_i;
+GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
+GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
+GT0_RXOUTCLK_OUT <= gt0_rxoutclk_i;
+GT0_TXOUTCLK_OUT <= gt0_txoutclk_i;
+
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
+gt0_cpllreset_i <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
+ gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
+ gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
+ gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
+ gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
+end generate chipscope;
+
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
+gt0_cpllreset_i <= gt0_cpllreset_t;
+gt0_gttxreset_i <= gt0_gttxreset_t;
+gt0_gtrxreset_i <= gt0_gtrxreset_t;
+gt0_txuserrdy_i <= gt0_txuserrdy_t;
+gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
+end generate no_chipscope;
+
+
+gt0_txresetfsm_i: GTX_trb3_sync_2gb_TX_STARTUP_FSM
+
+ generic map(
+ EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
+ STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH => 8,
+ TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
+ RX_QPLL_USED => FALSE, -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL => TRUE -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ )
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ TXUSERCLK => GT0_TXUSRCLK_IN,
+ SOFT_RESET => SOFT_RESET_TX_IN,
+ QPLLREFCLKLOST => tied_to_ground_i,
+ CPLLREFCLKLOST => gt0_cpllrefclklost_i,
+ QPLLLOCK => tied_to_vcc_i,
+ CPLLLOCK => gt0_cplllock_i,
+ TXRESETDONE => gt0_txresetdone_i,
+ MMCM_LOCK => GT0_TX_MMCM_LOCK_IN,
+ GTTXRESET => gt0_gttxreset_t,
+ MMCM_RESET => GT0_TX_MMCM_RESET_OUT,
+ QPLL_RESET => open,
+ CPLL_RESET => gt0_cpllreset_t,
+ TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT,
+ TXUSERRDY => gt0_txuserrdy_t,
+ RUN_PHALIGNMENT => gt0_run_tx_phalignment_i,
+ RESET_PHALIGNMENT => gt0_rst_tx_phalignment_i,
+ PHALIGNMENT_DONE => gt0_tx_phalignment_done_i,
+ RETRY_COUNTER => open
+ );
+
+
+
+
+
+
+
+
+gt0_rxresetfsm_i: GTX_trb3_sync_2gb_RX_STARTUP_FSM
+
+ generic map(
+ EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
+ EQ_MODE => "LPM", --Rx Equalization Mode - Set to DFE or LPM
+ STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH => 8,
+ TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
+ RX_QPLL_USED => FALSE, -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ )
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ RXUSERCLK => GT0_RXUSRCLK_IN,
+ SOFT_RESET => SOFT_RESET_RX_IN,
+ DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
+ QPLLREFCLKLOST => tied_to_ground_i,
+ CPLLREFCLKLOST => gt0_cpllrefclklost_i,
+ QPLLLOCK => tied_to_vcc_i,
+ CPLLLOCK => gt0_cplllock_i,
+ RXRESETDONE => gt0_rxresetdone_i,
+ MMCM_LOCK => tied_to_vcc_i,
+ RECCLK_STABLE => gt0_recclk_stable_i,
+ RECCLK_MONITOR_RESTART => tied_to_ground_i,
+ DATA_VALID => GT0_DATA_VALID_IN,
+ TXUSERRDY => tied_to_vcc_i,
+ GTRXRESET => gt0_gtrxreset_t,
+ MMCM_RESET => open,
+ QPLL_RESET => open,
+ CPLL_RESET => open,
+ RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT,
+ RXUSERRDY => gt0_rxuserrdy_t,
+ RUN_PHALIGNMENT => gt0_run_rx_phalignment_i,
+ RESET_PHALIGNMENT => gt0_rst_rx_phalignment_i,
+ PHALIGNMENT_DONE => gt0_rx_phalignment_done_i,
+ RXDFEAGCHOLD => gt0_rxdfeagchold_i,
+ RXDFELFHOLD => gt0_rxdfelfhold_i,
+ RXLPMLFHOLD => gt0_rxlpmlfhold_i,
+ RXLPMHFHOLD => gt0_rxlpmhfhold_i,
+ RETRY_COUNTER => open
+ );
+
+
+
+ gt0_cdrlock_timeout:process(SYSCLK_IN)
+ begin
+ if rising_edge(SYSCLK_IN) then
+ if(gt0_gtrxreset_i = '1') then
+ gt0_rx_cdrlocked <= '0';
+ gt0_rx_cdrlock_counter <= 0 after DLY;
+ elsif (gt0_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
+ gt0_rx_cdrlocked <= '1';
+ gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter after DLY;
+ else
+ gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter + 1 after DLY;
+ end if;
+ end if;
+ end process;
+
+gt0_recclk_stable_i <= gt0_rx_cdrlocked;
+
+
+
+ --------------------------- TX Buffer Bypass Logic --------------------
+ -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer.
+ -- Include the TX SYNC module in your own design if TX Buffer is bypassed.
+
+
+--Auto
+gt0_txphdlyreset_i <= tied_to_ground_i;
+gt0_txphalignen_i <= tied_to_ground_i;
+gt0_txdlyen_i <= tied_to_ground_i;
+gt0_txphalign_i <= tied_to_ground_i;
+gt0_txphinit_i <= tied_to_ground_i;
+
+gt0_tx_auto_phase_align_i : GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN
+ port map (
+ STABLE_CLOCK => SYSCLK_IN,
+ RUN_PHALIGNMENT => gt0_run_tx_phalignment_i,
+ PHASE_ALIGNMENT_DONE => gt0_tx_phalignment_done_i,
+ PHALIGNDONE => gt0_txphaligndone_i,
+ DLYSRESET => gt0_txdlysreset_i,
+ DLYSRESETDONE => gt0_txdlysresetdone_i,
+ RECCLKSTABLE => tied_to_vcc_i
+ );
+
+
+
+
+ --------------------------- RX Buffer Bypass Logic --------------------
+-- The RX SYNC Module drives the ports needed to Bypass the RX Buffer.
+-- Include the RX SYNC module in your own design if RX Buffer is bypassed.
+
+
+--Auto
+--Auto
+gt0_rxphdlyreset_i <= '1'; --// Modified??????? tied_to_ground_i;
+gt0_rxphalignen_i <= '1'; --// Modified??????? tied_to_ground_i;
+gt0_rxdlyen_i <= tied_to_ground_i;
+gt0_rxphalign_i <= tied_to_ground_i;
+
+gt0_rx_phalignment_done_i <= '1'; --// Modified
+gt0_rxdlysreset_i <= '1'; --// Modified
+-- gt0_rx_auto_phase_align_i : GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN
+ -- port map (
+ -- STABLE_CLOCK => SYSCLK_IN,
+ -- RUN_PHALIGNMENT => gt0_run_rx_phalignment_i,
+ -- PHASE_ALIGNMENT_DONE => gt0_rx_phalignment_done_i,
+ -- PHALIGNDONE => gt0_rxphaligndone_i,
+ -- DLYSRESET => gt0_rxdlysreset_i,
+ -- DLYSRESETDONE => gt0_rxdlysresetdone_i,
+ -- RECCLKSTABLE => gt0_recclk_stable_i
+ -- );
+
+
+
+end RTL;
+
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb_multi_gt.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_trb3_sync_2gb_multi_gt (a Multi GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity GTX_trb3_sync_2gb_multi_gt is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset
+ RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
+ USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic
+
+ PMA_RSV_IN : bit_vector := x"00018480"
+);
+port
+(
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X0Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllrefclklost_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxdlyen_in : in std_logic;
+ gt0_rxdlysreset_in : in std_logic;
+ gt0_rxdlysresetdone_out : out std_logic;
+ gt0_rxphalign_in : in std_logic;
+ gt0_rxphaligndone_out : out std_logic;
+ gt0_rxphalignen_in : in std_logic;
+ gt0_rxphdlyreset_in : in std_logic;
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ gt0_rxlpmhfhold_in : in std_logic;
+ gt0_rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ gt0_txdlyen_in : in std_logic;
+ gt0_txdlysreset_in : in std_logic;
+ gt0_txdlysresetdone_out : out std_logic;
+ gt0_txphalign_in : in std_logic;
+ gt0_txphaligndone_out : out std_logic;
+ gt0_txphalignen_in : in std_logic;
+ gt0_txphdlyreset_in : in std_logic;
+ gt0_txphinit_in : in std_logic;
+ gt0_txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+
+end GTX_trb3_sync_2gb_multi_gt;
+
+architecture RTL of GTX_trb3_sync_2gb_multi_gt is
+ attribute DowngradeIPIdentifiedWarnings: string;
+ attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_trb3_sync_2gb_multi_gt,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
+ signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
+
+ signal gt0_qpllclk_i : std_logic;
+ signal gt0_qpllrefclk_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ signal gt0_cpllpd_i : std_logic;
+ signal cpll_reset0_i : std_logic;
+ signal cpll_pd0_i : std_logic;
+
+--*************************** Component Declarations **************************
+component GTX_trb3_sync_2gb_GT
+generic
+(
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
+ RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
+ PMA_RSV_IN : bit_vector := X"00000000";
+ SIM_CPLLREFCLK_SEL : bit_vector := "001";
+ PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
+);
+port
+(
+ cpllpd_in : in std_logic;
+ cpllrefclksel_in : in std_logic_vector (2 downto 0);
+ --------------------------------- CPLL Ports -------------------------------
+ cpllfbclklost_out : out std_logic;
+ cplllock_out : out std_logic;
+ cplllockdetclk_in : in std_logic;
+ cpllrefclklost_out : out std_logic;
+ cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gtrefclk0_in : in std_logic;
+ gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ drpaddr_in : in std_logic_vector(8 downto 0);
+ drpclk_in : in std_logic;
+ drpdi_in : in std_logic_vector(15 downto 0);
+ drpdo_out : out std_logic_vector(15 downto 0);
+ drpen_in : in std_logic;
+ drprdy_out : out std_logic;
+ drpwe_in : in std_logic;
+ ------------------------------- Clocking Ports -----------------------------
+ qpllclk_in : in std_logic;
+ qpllrefclk_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ eyescanreset_in : in std_logic;
+ rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ eyescandataerror_out : out std_logic;
+ eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN : in std_logic; --// Modified
+ RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ rxusrclk_in : in std_logic;
+ rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ rxdisperr_out : out std_logic_vector(1 downto 0);
+ rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ rxdlyen_in : in std_logic;
+ rxdlysreset_in : in std_logic;
+ rxdlysresetdone_out : out std_logic;
+ rxphalign_in : in std_logic;
+ rxphaligndone_out : out std_logic;
+ rxphalignen_in : in std_logic;
+ rxphdlyreset_in : in std_logic;
+ rxphmonitor_out : out std_logic_vector(4 downto 0);
+ rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ rxlpmhfhold_in : in std_logic;
+ rxlpmlfhold_in : in std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ rxdfelpmreset_in : in std_logic;
+ rxmonitorout_out : out std_logic_vector(6 downto 0);
+ rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gtrxreset_in : in std_logic;
+ rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gttxreset_in : in std_logic;
+ txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ txusrclk_in : in std_logic;
+ txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ txdlyen_in : in std_logic;
+ txdlysreset_in : in std_logic;
+ txdlysresetdone_out : out std_logic;
+ txphalign_in : in std_logic;
+ txphaligndone_out : out std_logic;
+ txphalignen_in : in std_logic;
+ txphdlyreset_in : in std_logic;
+ txphinit_in : in std_logic;
+ txphinitdone_out : out std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gtxtxn_out : out std_logic;
+ gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ txoutclk_out : out std_logic;
+ txoutclkfabric_out : out std_logic;
+ txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ txresetdone_out : out std_logic
+
+
+);
+end component;
+component GTX_trb3_sync_2gb_cpll_railing
+ Generic(
+ USE_BUFG : integer := 0
+);
+port
+(
+ cpll_reset_out : out std_logic;
+ cpll_pd_out : out std_logic;
+ refclk_out : out std_logic;
+
+ refclk_in : in std_logic
+
+);
+end component;
+
+
+
+--********************************* Main Body of Code**************************
+
+begin
+
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ gt0_qpllclk_i <= GT0_QPLLOUTCLK_IN;
+ gt0_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN;
+
+
+
+ --------------------------- GT Instances -------------------------------
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --GT0 (X0Y10)
+
+gt0_GTX_trb3_sync_2gb_i : GTX_trb3_sync_2gb_GT
+ generic map
+ (
+ -- Simulation attributes
+ GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
+ SIM_CPLLREFCLK_SEL => "001",
+ PMA_RSV_IN => PMA_RSV_IN,
+ PCS_RSVD_ATTR_IN => X"000000000000"
+ )
+ port map
+ (
+ cpllpd_in => gt0_cpllpd_i,
+ cpllrefclksel_in => "001",
+ --------------------------------- CPLL Ports -------------------------------
+ cpllfbclklost_out => gt0_cpllfbclklost_out,
+ cplllock_out => gt0_cplllock_out,
+ cplllockdetclk_in => gt0_cplllockdetclk_in,
+ cpllrefclklost_out => gt0_cpllrefclklost_out,
+ cpllreset_in => gt0_cpllreset_i,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gtrefclk0_in => gt0_gtrefclk0_in,
+ gtrefclk1_in => gt0_gtrefclk1_in,
+ ---------------------------- Channel - DRP Ports --------------------------
+ drpaddr_in => gt0_drpaddr_in,
+ drpclk_in => gt0_drpclk_in,
+ drpdi_in => gt0_drpdi_in,
+ drpdo_out => gt0_drpdo_out,
+ drpen_in => gt0_drpen_in,
+ drprdy_out => gt0_drprdy_out,
+ drpwe_in => gt0_drpwe_in,
+ ------------------------------- Clocking Ports -----------------------------
+ qpllclk_in => gt0_qpllclk_i,
+ qpllrefclk_in => gt0_qpllrefclk_i,
+ --------------------------- Digital Monitor Ports --------------------------
+ dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ eyescanreset_in => gt0_eyescanreset_in,
+ rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ eyescandataerror_out => gt0_eyescandataerror_out,
+ eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ rxusrclk_in => gt0_rxusrclk_in,
+ rxusrclk2_in => gt0_rxusrclk2_in,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ rxdisperr_out => gt0_rxdisperr_out,
+ rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ rxdlyen_in => gt0_rxdlyen_in,
+ rxdlysreset_in => gt0_rxdlysreset_in,
+ rxdlysresetdone_out => gt0_rxdlysresetdone_out,
+ rxphalign_in => gt0_rxphalign_in,
+ rxphaligndone_out => gt0_rxphaligndone_out,
+ rxphalignen_in => gt0_rxphalignen_in,
+ rxphdlyreset_in => gt0_rxphdlyreset_in,
+ rxphmonitor_out => gt0_rxphmonitor_out,
+ rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ rxlpmhfhold_in => gt0_rxlpmhfhold_in,
+ rxlpmlfhold_in => gt0_rxlpmlfhold_in,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ rxmonitorout_out => gt0_rxmonitorout_out,
+ rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ rxoutclk_out => gt0_rxoutclk_out,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gtrxreset_in => gt0_gtrxreset_in,
+ rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gttxreset_in => gt0_gttxreset_in,
+ txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ txusrclk_in => gt0_txusrclk_in,
+ txusrclk2_in => gt0_txusrclk2_in,
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ txdlyen_in => gt0_txdlyen_in,
+ txdlysreset_in => gt0_txdlysreset_in,
+ txdlysresetdone_out => gt0_txdlysresetdone_out,
+ txphalign_in => gt0_txphalign_in,
+ txphaligndone_out => gt0_txphaligndone_out,
+ txphalignen_in => gt0_txphalignen_in,
+ txphdlyreset_in => gt0_txphdlyreset_in,
+ txphinit_in => gt0_txphinit_in,
+ txphinitdone_out => gt0_txphinitdone_out,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gtxtxn_out => gt0_gtxtxn_out,
+ gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ txoutclk_out => gt0_txoutclk_out,
+ txoutclkfabric_out => gt0_txoutclkfabric_out,
+ txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ txresetdone_out => gt0_txresetdone_out
+
+ );
+
+
+ cpll_railing0_i : GTX_trb3_sync_2gb_cpll_railing
+ generic map(
+ USE_BUFG => USE_BUFG
+ )
+ port map
+ (
+ cpll_reset_out => cpll_reset0_i,
+ cpll_pd_out => cpll_pd0_i,
+ refclk_out => open,
+ refclk_in => gt0_gtrefclk0_in
+);
+
+
+gt0_cpllreset_i <= cpll_reset0_i or gt0_cpllreset_in;
+gt0_cpllpd_i <= cpll_pd0_i ;
+end RTL;
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 3.5
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtx_trb3_sync_2gb_rx_startup_fsm.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+-- Description : This module performs RX reset and initialization.
+--
+--
+--
+-- Module GTX_trb3_sync_2gb_rx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_trb3_sync_2gb_RX_STARTUP_FSM is
+ Generic( EXAMPLE_SIMULATION : integer := 0;
+ EQ_MODE : string := "DFE"; --RX Equalisation Mode; set to DFE or LPM
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ RXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ RECCLK_STABLE : in STD_LOGIC;
+ RECCLK_MONITOR_RESTART : in STD_LOGIC:='0';
+ DATA_VALID : in STD_LOGIC;
+ TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
+ DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; --Used to control the Auto-Reset of FSM when Data Error is detected
+ GTRXRESET : out STD_LOGIC;
+ MMCM_RESET : out STD_LOGIC;
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
+ RX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
+ RXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC;
+ PHALIGNMENT_DONE : in STD_LOGIC;
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ RXDFEAGCHOLD : out STD_LOGIC;
+ RXDFELFHOLD : out STD_LOGIC;
+ RXLPMLFHOLD : out STD_LOGIC;
+ RXLPMHFHOLD : out STD_LOGIC;
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end GTX_trb3_sync_2gb_RX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+-- are calculated at design-time based on the Generics
+--
+-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
+-- => signal which PLL has been reset
+-- *
+
+
+
+architecture RTL of GTX_trb3_sync_2gb_RX_STARTUP_FSM is
+
+ component GTX_trb3_sync_2gb_sync_block
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+ type rx_rst_fsm_type is(
+ INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
+ RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+ MONITOR_DATA_VALID, FSM_DONE);
+
+ signal rx_state : rx_rst_fsm_type := INIT;
+
+ constant MMCM_LOCK_CNT_MAX : integer := 256;
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+ constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
+ constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--500 us time-out
+ constant WAIT_TIMEOUT_1us : integer := 1000 / STABLE_CLOCK_PERIOD; --1 us time-out
+ constant WAIT_TIMEOUT_100us : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
+ constant WAIT_TIME_ADAPT : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD;
+ constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
+
+ signal init_wait_count : integer range 0 to WAIT_MAX:=0;
+ signal init_wait_done : std_logic := '0';
+ signal pll_reset_asserted : std_logic := '0';
+ signal rx_fsm_reset_done_int : std_logic := '0';
+ signal rx_fsm_reset_done_int_s2 : std_logic := '0';
+ signal rx_fsm_reset_done_int_s3 : std_logic := '0';
+
+ signal rxresetdone_s2 : std_logic := '0';
+ signal rxresetdone_s3 : std_logic := '0';
+
+ constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
+ signal retry_counter_int : integer range 0 to MAX_RETRIES := 0;
+ signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+ signal recclk_mon_restart_count : integer range 0 to 3:= 0;
+ signal recclk_mon_count_reset : std_logic := '0';
+
+ signal reset_time_out : std_logic := '0';
+ signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
+ signal time_tlock_max : std_logic := '0';--|have been reached.
+ signal time_out_500us : std_logic := '0';--|
+ signal time_out_1us : std_logic := '0';--/
+ signal time_out_100us : std_logic := '0';--/
+ signal check_tlock_max : std_logic := '0';
+
+ signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+ signal mmcm_lock_int : std_logic := '0';
+ signal mmcm_lock_i : std_logic := '0';
+ signal mmcm_lock_reclocked : std_logic := '0';
+ signal gtrxreset_i : std_logic := '0';
+ signal mmcm_reset_i : std_logic := '1';
+ signal rxpmaresetdone_i : std_logic := '0';
+ signal txpmaresetdone_i : std_logic := '0';
+ signal rxpmaresetdone_ss : std_logic := '0';
+ signal rxpmaresetdone_sync : std_logic ;
+ signal txpmaresetdone_sync : std_logic ;
+ signal rxpmaresetdone_s : std_logic ;
+ signal rxpmaresetdone_rx_s : std_logic ;
+ signal pmaresetdone_fallingedge_detect : std_logic ;
+ signal pmaresetdone_fallingedge_detect_s : std_logic ;
+
+ signal run_phase_alignment_int: std_logic := '0';
+ signal run_phase_alignment_int_s2 : std_logic := '0';
+ signal run_phase_alignment_int_s3 : std_logic := '0';
+
+ constant MAX_WAIT_BYPASS : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
+ signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
+ signal time_out_wait_bypass : std_logic := '0';
+ signal time_out_wait_bypass_s2 : std_logic := '0';
+ signal time_out_wait_bypass_s3 : std_logic := '0';
+
+ signal refclk_lost : std_logic;
+
+ signal time_out_adapt : std_logic := '0';
+ signal adapt_count_reset : std_logic := '0';
+ signal adapt_count : integer range 0 to WAIT_TIME_ADAPT-1;
+ signal data_valid_sync: std_logic := '0';
+ signal cplllock_sync: std_logic := '0';
+ signal qplllock_sync: std_logic := '0';
+ signal cplllock_prev: std_logic := '0';
+ signal qplllock_prev: std_logic := '0';
+ signal cplllock_ris_edge: std_logic := '0';
+ signal qplllock_ris_edge: std_logic := '0';
+ signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+ signal wait_time_done : std_logic;
+
+
+ attribute shreg_extract : string;
+ attribute ASYNC_REG : string;
+
+ signal reset_sync_reg1_tx : std_logic;
+ signal reset_sync_reg1 : std_logic;
+ signal gtrxreset_s : std_logic;
+ signal gtrxreset_tx_s : std_logic;
+ signal txpmaresetdone_s : std_logic;
+begin
+ --Alias section, signals used within this module mapped to output ports:
+ RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+ RUN_PHALIGNMENT <= run_phase_alignment_int;
+ RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
+ GTRXRESET <= gtrxreset_i;
+ MMCM_RESET <= mmcm_reset_i;
+ process(STABLE_CLOCK,SOFT_RESET)
+ begin
+ if (SOFT_RESET = '1') then
+ init_wait_done <= '0';
+ init_wait_count <= 0 ;
+ elsif rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+
+ adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
+ time_out_adapt <= '1';
+ end generate;
+
+ adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(adapt_count_reset = '1') then
+ adapt_count <= 0;
+ time_out_adapt <= '0';
+ elsif(adapt_count = WAIT_TIME_ADAPT -1) then
+ time_out_adapt <= '1';
+ else
+ adapt_count <= adapt_count + 1;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ retries_recclk_monitor:process(STABLE_CLOCK)
+ begin
+ --This counter monitors, how many retries the RECCLK monitor
+ --runs. If during startup too many retries are necessary, the whole
+ --initialisation-process of the transceivers gets restarted.
+ if rising_edge(STABLE_CLOCK) then
+ if recclk_mon_count_reset = '1' then
+ recclk_mon_restart_count <= 0;
+ elsif RECCLK_MONITOR_RESTART = '1' then
+ if recclk_mon_restart_count = 3 then
+ recclk_mon_restart_count <= 0;
+ else
+ recclk_mon_restart_count <= recclk_mon_restart_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ timeouts:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- One common large counter for generating three time-out signals.
+ -- Intermediate time-outs are derived from calculated values, based
+ -- on the period of the provided clock.
+ if reset_time_out = '1' then
+ time_out_counter <= 0;
+ time_out_2ms <= '0';
+ time_tlock_max <= '0';
+ time_out_500us <= '0';
+ time_out_1us <= '0';
+ time_out_100us <= '0';
+ else
+ if time_out_counter = WAIT_TIMEOUT_2ms then
+ time_out_2ms <= '1';
+ else
+ time_out_counter <= time_out_counter + 1;
+ end if;
+
+ if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
+ time_tlock_max <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_500us then
+ time_out_500us <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_1us then
+ time_out_1us <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_100us then
+ time_out_100us <= '1';
+ end if;
+
+ end if;
+ end if;
+ end process;
+
+
+
+ mmcm_lock_wait:process(STABLE_CLOCK)
+ begin
+ --The lock-signal from the MMCM is not immediately used but
+ --enabling a counter. Only when the counter hits its maximum,
+ --the MMCM is considered as "really" locked.
+ --The counter avoids that the FSM already starts on only a
+ --coarse lock of the MMCM (=toggling of the LOCK-signal).
+ if rising_edge(STABLE_CLOCK) then
+ if mmcm_lock_i = '0' then
+ mmcm_lock_count <= 0;
+ mmcm_lock_reclocked <= '0';
+ else
+ if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+ mmcm_lock_count <= mmcm_lock_count + 1;
+ else
+ mmcm_lock_reclocked <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ -- Clock Domain Crossing
+
+ sync_run_phase_alignment_int : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => RXUSERCLK,
+ data_in => run_phase_alignment_int,
+ data_out => run_phase_alignment_int_s2
+ );
+
+ sync_rx_fsm_reset_done_int : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => RXUSERCLK,
+ data_in => rx_fsm_reset_done_int,
+ data_out => rx_fsm_reset_done_int_s2
+ );
+
+ process(RXUSERCLK)
+ begin
+ if rising_edge(RXUSERCLK) then
+ run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
+
+ rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2;
+ end if;
+ end process;
+
+ sync_RXRESETDONE : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => RXRESETDONE,
+ data_out => rxresetdone_s2
+ );
+
+ sync_time_out_wait_bypass : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => time_out_wait_bypass,
+ data_out => time_out_wait_bypass_s2
+ );
+
+ sync_mmcm_lock_reclocked : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => MMCM_LOCK,
+ data_out => mmcm_lock_i
+ );
+
+ sync_data_valid : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => DATA_VALID,
+ data_out => data_valid_sync
+ );
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ rxresetdone_s3 <= rxresetdone_s2;
+
+ time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
+
+ cplllock_prev <= cplllock_sync;
+ qplllock_prev <= qplllock_sync;
+ end if;
+ end process;
+
+ sync_CPLLLOCK : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => CPLLLOCK,
+ data_out => cplllock_sync
+ );
+
+ sync_QPLLLOCK : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => QPLLLOCK,
+ data_out => qplllock_sync
+ );
+
+
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ cplllock_ris_edge <= '0';
+ elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+ cplllock_ris_edge <= '1';
+ elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+ cplllock_ris_edge <= cplllock_ris_edge;
+ else
+ cplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ qplllock_ris_edge <= '0';
+ elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+ qplllock_ris_edge <= '1';
+ elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+ qplllock_ris_edge <= qplllock_ris_edge;
+ else
+ qplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ timeout_buffer_bypass:process(RXUSERCLK)
+ begin
+ if rising_edge(RXUSERCLK) then
+ if run_phase_alignment_int_s3 = '0' then
+ wait_bypass_count <= 0;
+ time_out_wait_bypass <= '0';
+ elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
+ if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+ time_out_wait_bypass <= '1';
+ else
+ wait_bypass_count <= wait_bypass_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+
+ timeout_max:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if((rx_state = ASSERT_ALL_RESETS) or
+ (rx_state = RELEASE_MMCM_RESET)) then
+ wait_time_cnt <= WAIT_TIME_MAX;
+ elsif (wait_time_cnt > 0 ) then
+ wait_time_cnt <= wait_time_cnt - 1;
+ end if;
+ end if;
+ end process;
+
+ wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+
+ --FSM for resetting the GTX/GTH/GTP in the 7-series.
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ --
+ -- Following steps are performed:
+ -- 1) After configuration wait for approximately 500 ns as specified in
+ -- answer-record 43482
+ -- 2) Assert all resets on the GT and on an MMCM potentially connected.
+ -- After that wait until a reference-clock has been detected.
+ -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+ -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+ -- Also get info from the TX-side which PLL has been reset.
+ -- 5) Wait for the RESET_DONE-signal from the GT.
+ -- 6) Signal to start the phase-alignment procedure and wait for it to
+ -- finish.
+ -- 7) Reset-sequence has successfully run through. Signal this to the
+ -- rest of the design by asserting RX_FSM_RESET_DONE.
+
+ reset_fsm:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if (SOFT_RESET = '1' ) then
+ --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+ rx_state <= INIT;
+ RXUSERRDY <= '0';
+ gtrxreset_i <= '0';
+ mmcm_reset_i <= '0';
+ rx_fsm_reset_done_int <= '0';
+ QPLL_RESET <= '0';
+ CPLL_RESET <= '0';
+ pll_reset_asserted <= '0';
+ reset_time_out <= '1';
+ retry_counter_int <= 0;
+ run_phase_alignment_int <= '0';
+ check_tlock_max <= '0';
+ RESET_PHALIGNMENT <= '1';
+ recclk_mon_count_reset <= '1';
+ adapt_count_reset <= '1';
+ RXDFEAGCHOLD <= '0';
+ RXDFELFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ RXLPMHFHOLD <= '0';
+
+ else
+
+ case rx_state is
+ when INIT =>
+ --Initial state after configuration. This state will be left after
+ --approx. 500 ns and not be re-entered.
+ if init_wait_done = '1' then
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when ASSERT_ALL_RESETS =>
+ --This is the state into which the FSM will always jump back if any
+ --time-outs will occur.
+ --The number of retries is reported on the output RETRY_COUNTER. In
+ --case the transceiver never comes up for some reason, this machine
+ --will still continue its best and rerun until the FPGA is turned off
+ --or the transceivers come up correctly.
+ if RX_QPLL_USED and not TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ QPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ QPLL_RESET <= '0';
+ end if;
+ elsif not RX_QPLL_USED and TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ CPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ CPLL_RESET <= '0';
+ end if;
+ end if;
+
+ RXUSERRDY <= '0';
+ gtrxreset_i <= '1';
+ mmcm_reset_i <= '1';
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+ check_tlock_max <= '0';
+ recclk_mon_count_reset <= '1';
+ adapt_count_reset <= '1';
+
+ if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+ (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '0') and pll_reset_asserted = '1') or
+ (not RX_QPLL_USED and not TX_QPLL_USED ) or
+ (RX_QPLL_USED and TX_QPLL_USED ) then
+ rx_state <= WAIT_FOR_PLL_LOCK;
+ reset_time_out <= '1';
+ end if;
+
+ when WAIT_FOR_PLL_LOCK =>
+ if(wait_time_done = '1') then
+ rx_state <= RELEASE_PLL_RESET;
+ end if;
+
+ when RELEASE_PLL_RESET =>
+ --PLL-Reset of the GTX gets released and the time-out counter
+ --starts running.
+ pll_reset_asserted <= '0';
+ reset_time_out <= '0';
+
+ if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '1')) or
+ (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '1')) then
+ rx_state <= VERIFY_RECCLK_STABLE;
+ reset_time_out <= '1';
+ recclk_mon_count_reset <= '0';
+ adapt_count_reset <= '0';
+ elsif (RX_QPLL_USED and (qplllock_sync = '1')) or
+ (not RX_QPLL_USED and (cplllock_sync = '1')) then
+ rx_state <= VERIFY_RECCLK_STABLE;
+ reset_time_out <= '1';
+ recclk_mon_count_reset <= '0';
+ adapt_count_reset <= '0';
+ end if;
+
+ if time_out_2ms = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when VERIFY_RECCLK_STABLE =>
+ --reset_time_out <= '0';
+ --Time-out counter is not released in this state as here the FSM
+ --does not wait for a certain period of time but checks on the number
+ --of retries in the RECCLK monitor
+ gtrxreset_i <= '0';
+ if RECCLK_STABLE = '1' then
+ rx_state <= RELEASE_MMCM_RESET;
+ reset_time_out <= '1';
+
+ end if;
+
+ if recclk_mon_restart_count = 2 then
+ --If two retries are performed in the RECCLK monitor
+ --the whole initialisation-sequence gets restarted.
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when RELEASE_MMCM_RESET =>
+ --Release of the MMCM-reset. Waiting for the MMCM to lock.
+ check_tlock_max <= '1';
+
+ mmcm_reset_i <= '0';
+ reset_time_out <= '0';
+
+ if mmcm_lock_reclocked = '1' then
+ rx_state <= WAIT_FOR_RXUSRCLK;
+ reset_time_out <= '1';
+ end if;
+
+ if (time_tlock_max = '1' and reset_time_out = '0' )then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_FOR_RXUSRCLK =>
+ if wait_time_done = '1' then
+ rx_state <= WAIT_RESET_DONE;
+ end if;
+
+ when WAIT_RESET_DONE =>
+ --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
+ --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
+ if TXUSERRDY = '1' then
+ RXUSERRDY <= '1';
+ end if;
+ reset_time_out <= '0';
+ if rxresetdone_s3 = '1' then
+ rx_state <= DO_PHASE_ALIGNMENT;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_2ms = '1' and reset_time_out = '0' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when DO_PHASE_ALIGNMENT =>
+ --The direct handling of the signals for the Phase Alignment is done outside
+ --this state-machine.
+ RESET_PHALIGNMENT <= '0';
+ run_phase_alignment_int <= '1';
+ reset_time_out <= '0';
+
+ if PHALIGNMENT_DONE = '1' then
+ rx_state <= MONITOR_DATA_VALID;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_wait_bypass_s3 = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ rx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when MONITOR_DATA_VALID =>
+ reset_time_out <= '0';
+
+ if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0') then
+ rx_state <= ASSERT_ALL_RESETS;
+ rx_fsm_reset_done_int <= '0';
+ elsif (data_valid_sync = '1') then
+ rx_state <= FSM_DONE;
+ rx_fsm_reset_done_int <= '0';
+ reset_time_out <= '1';
+ end if;
+
+ when FSM_DONE =>
+ reset_time_out <= '0';
+ if data_valid_sync = '0' then
+ rx_fsm_reset_done_int <= '0';
+ reset_time_out <= '1';
+ rx_state <= MONITOR_DATA_VALID;
+
+ elsif(time_out_1us = '1' and reset_time_out = '0') then
+ rx_fsm_reset_done_int <= '1';
+ end if;
+
+ if(time_out_adapt = '1') then
+ if(EQ_MODE = "DFE") then
+ RXDFEAGCHOLD <= '1';
+ RXDFELFHOLD <= '1';
+ RXLPMHFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ else
+ RXDFEAGCHOLD <= '0';
+ RXDFELFHOLD <= '0';
+ RXLPMHFHOLD <= '0';
+ RXLPMLFHOLD <= '0';
+ end if;
+ end if;
+ when OTHERS =>
+ rx_state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
+
--- /dev/null
+--////////////////////////////////////////////////////////////////////////////////
+--// ____ ____
+--// / /\/ /
+--// /___/ \ / Vendor: Xilinx
+--// \ \ \/ Version : 3.5
+--// \ \ Application : 7 Series FPGAs Transceivers Wizard
+--// / / Filename : gtx_trb3_sync_2gb_sync_block.vhd
+--// /___/ /\
+--// \ \ / \
+--// \___\/\___\
+--//
+--//
+--
+-- Description: Used on signals crossing from one clock domain to
+-- another, this is a flip-flop pair, with both flops
+-- placed together with RLOCs into the same slice. Thus
+-- the routing delay between the two is minimum to safe-
+-- guard against metastability issues.
+--
+--
+-- Module GTX_trb3_sync_2gb_sync_block
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_trb3_sync_2gb_sync_block is
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic; -- clock to be sync'ed to
+ data_in : in std_logic; -- Data to be 'synced'
+ data_out : out std_logic -- synced data
+ );
+
+-- attribute dont_touch : string;
+-- attribute dont_touch of GTX_trb3_sync_2gb_sync_block : entity is "yes";
+
+end GTX_trb3_sync_2gb_sync_block;
+
+
+architecture structural of GTX_trb3_sync_2gb_sync_block is
+
+
+ -- Internal Signals
+ signal data_sync1 : std_logic;
+ signal data_sync2 : std_logic;
+ signal data_sync3 : std_logic;
+ signal data_sync4 : std_logic;
+ signal data_sync5 : std_logic;
+
+ -- These attributes will stop timing errors being reported in back annotated
+ -- SDF simulation.
+ attribute ASYNC_REG : string;
+ attribute ASYNC_REG of data_sync_reg1 : label is "true";
+ attribute ASYNC_REG of data_sync_reg2 : label is "true";
+ attribute ASYNC_REG of data_sync_reg3 : label is "true";
+ attribute ASYNC_REG of data_sync_reg4 : label is "true";
+ attribute ASYNC_REG of data_sync_reg5 : label is "true";
+ attribute ASYNC_REG of data_sync_reg6 : label is "true";
+
+ -- These attributes will stop XST translating the desired flip-flops into an
+ -- SRL based shift register.
+ attribute shreg_extract : string;
+ attribute shreg_extract of data_sync_reg1 : label is "no";
+ attribute shreg_extract of data_sync_reg2 : label is "no";
+ attribute shreg_extract of data_sync_reg3 : label is "no";
+ attribute shreg_extract of data_sync_reg4 : label is "no";
+ attribute shreg_extract of data_sync_reg5 : label is "no";
+ attribute shreg_extract of data_sync_reg6 : label is "no";
+
+
+begin
+
+ data_sync_reg1 : FD
+ generic map (
+ INIT => INITIALISE(0)
+ )
+ port map (
+ C => clk,
+ D => data_in,
+ Q => data_sync1
+ );
+
+ data_sync_reg2 : FD
+ generic map (
+ INIT => INITIALISE(1)
+ )
+ port map (
+ C => clk,
+ D => data_sync1,
+ Q => data_sync2
+ );
+
+ data_sync_reg3 : FD
+ generic map (
+ INIT => INITIALISE(2)
+ )
+ port map (
+ C => clk,
+ D => data_sync2,
+ Q => data_sync3
+ );
+
+ data_sync_reg4 : FD
+ generic map (
+ INIT => INITIALISE(3)
+ )
+ port map (
+ C => clk,
+ D => data_sync3,
+ Q => data_sync4
+ );
+
+ data_sync_reg5 : FD
+ generic map (
+ INIT => INITIALISE(4)
+ )
+ port map (
+ C => clk,
+ D => data_sync4,
+ Q => data_sync5
+ );
+
+ data_sync_reg6 : FD
+ generic map (
+ INIT => INITIALISE(5)
+ )
+ port map (
+ C => clk,
+ D => data_sync5,
+ Q => data_out
+ );
+
+
+
+end structural;
+
+
--- /dev/null
+--//////////////////////////////////////////////////////////////////////////////
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename :gtx_trb3_sync_2gb_tx_startup_fsm.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module GTX_trb3_sync_2gb_tx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity GTX_trb3_sync_2gb_TX_STARTUP_FSM is
+ Generic(
+ EXAMPLE_SIMULATION : integer := 0;
+ STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+ RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
+ TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
+ RX_QPLL_USED : boolean := False; -- share these two generic values
+ PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
+ -- is enough. For single-lane applications the automatic alignment is
+ -- sufficient
+ );
+ Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
+ --or reference-clock present at startup.
+ TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
+ SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
+ QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
+ CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
+ QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
+ CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
+ TXRESETDONE : in STD_LOGIC;
+ MMCM_LOCK : in STD_LOGIC;
+ GTTXRESET : out STD_LOGIC;
+ MMCM_RESET : out STD_LOGIC:='1';
+ QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
+ CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
+ TX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished.
+ TXUSERRDY : out STD_LOGIC:='0';
+ RUN_PHALIGNMENT : out STD_LOGIC:='0';
+ RESET_PHALIGNMENT : out STD_LOGIC:='0';
+ PHALIGNMENT_DONE : in STD_LOGIC;
+
+ RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
+ -- Retries it took to get the transceiver up and running
+ );
+end GTX_trb3_sync_2gb_TX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+-- are calculated at design-time based on the Generics
+--
+-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
+-- => signal which PLL has been reset
+-- *
+
+
+
+architecture RTL of GTX_trb3_sync_2gb_TX_STARTUP_FSM is
+
+ component GTX_trb3_sync_2gb_sync_block
+ generic (
+ INITIALISE : bit_vector(5 downto 0) := "000000"
+ );
+ port (
+ clk : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+ end component;
+
+ type tx_rst_fsm_type is(
+ INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET,
+ WAIT_FOR_TXOUTCLK, RELEASE_MMCM_RESET, WAIT_FOR_TXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+ RESET_FSM_DONE);
+
+ signal tx_state : tx_rst_fsm_type := INIT;
+
+ constant MMCM_LOCK_CNT_MAX : integer := 256;
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+ constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out
+ constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--100 us time-out
+ constant WAIT_1us_cycles : integer := 1000 / STABLE_CLOCK_PERIOD;--1 us time-out
+ constant WAIT_1us : integer := WAIT_1us_cycles+ 10; -- 1us plus some additional margin
+
+ signal init_wait_count : integer range 0 to WAIT_MAX:=0;
+ signal init_wait_done : std_logic := '0';
+ signal pll_reset_asserted : std_logic := '0';
+
+ signal tx_fsm_reset_done_int : std_logic := '0';
+ signal tx_fsm_reset_done_int_s2 : std_logic := '0';
+ signal tx_fsm_reset_done_int_s3 : std_logic := '0';
+
+ signal txresetdone_s2 : std_logic := '0';
+ signal txresetdone_s3 : std_logic := '0';
+
+ constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1;
+ signal retry_counter_int : integer range 0 to MAX_RETRIES;
+ signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+
+ signal reset_time_out : std_logic := '0';
+ signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points
+ signal time_tlock_max : std_logic := '0';--|have been reached.
+ signal time_out_500us : std_logic := '0';--/
+
+ signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+ signal mmcm_lock_int : std_logic := '0';
+ signal mmcm_lock_i : std_logic := '0';
+ signal mmcm_lock_reclocked : std_logic := '0';
+
+ signal run_phase_alignment_int : std_logic := '0';
+ signal run_phase_alignment_int_s2 : std_logic := '0';
+ signal run_phase_alignment_int_s3 : std_logic := '0';
+ constant MAX_WAIT_BYPASS : integer := 45824; --110000 TXUSRCLK cycles is the max time for Multi lane designs
+
+ constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out
+
+ signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1;
+ signal time_out_wait_bypass : std_logic := '0';
+ signal time_out_wait_bypass_s2 : std_logic := '0';
+ signal time_out_wait_bypass_s3 : std_logic := '0';
+ signal txuserrdy_i : std_logic := '0';
+ signal refclk_lost : std_logic;
+ signal gttxreset_i : std_logic := '0';
+ signal txpmaresetdone_i : std_logic := '0';
+ signal txpmaresetdone_sync : std_logic ;
+
+ signal cplllock_sync: std_logic := '0';
+ signal qplllock_sync: std_logic := '0';
+ signal cplllock_prev: std_logic := '0';
+ signal qplllock_prev: std_logic := '0';
+ signal cplllock_ris_edge: std_logic := '0';
+ signal qplllock_ris_edge: std_logic := '0';
+ signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+ signal wait_time_done :std_logic;
+
+begin
+ --Alias section, signals used within this module mapped to output ports:
+ RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+ RUN_PHALIGNMENT <= run_phase_alignment_int;
+ TX_FSM_RESET_DONE <= tx_fsm_reset_done_int;
+ GTTXRESET <= gttxreset_i;
+
+ process(STABLE_CLOCK,SOFT_RESET)
+ begin
+ if (SOFT_RESET = '1') then
+ init_wait_done <= '0';
+ init_wait_count <= 0 ;
+ elsif rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ timeouts:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- One common large counter for generating three time-out signals.
+ -- Intermediate time-outs are derived from calculated values, based
+ -- on the period of the provided clock.
+ if reset_time_out = '1' then
+ time_out_counter <= 0;
+ time_out_2ms <= '0';
+ time_tlock_max <= '0';
+ time_out_500us <= '0';
+ else
+ if time_out_counter = WAIT_TIMEOUT_2ms then
+ time_out_2ms <= '1';
+ else
+ time_out_counter <= time_out_counter + 1;
+ end if;
+
+ if time_out_counter = WAIT_TLOCK_MAX then
+ time_tlock_max <= '1';
+ end if;
+
+ if time_out_counter = WAIT_TIMEOUT_500us then
+ time_out_500us <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ mmcm_lock_wait:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if mmcm_lock_i = '0' then
+ mmcm_lock_count <= 0;
+ mmcm_lock_reclocked <= '0';
+ else
+ if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+ mmcm_lock_count <= mmcm_lock_count + 1;
+ else
+ mmcm_lock_reclocked <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+
+ -- Clock Domain Crossing
+
+ sync_run_phase_alignment_int : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => TXUSERCLK,
+ data_in => run_phase_alignment_int,
+ data_out => run_phase_alignment_int_s2
+ );
+
+ sync_tx_fsm_reset_done_int : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => TXUSERCLK,
+ data_in => tx_fsm_reset_done_int,
+ data_out => tx_fsm_reset_done_int_s2
+ );
+
+ process(TXUSERCLK)
+ begin
+ if rising_edge(TXUSERCLK) then
+ run_phase_alignment_int_s3 <= run_phase_alignment_int_s2;
+
+ tx_fsm_reset_done_int_s3 <= tx_fsm_reset_done_int_s2;
+ end if;
+ end process;
+
+ sync_TXRESETDONE : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => TXRESETDONE,
+ data_out => txresetdone_s2
+ );
+
+ sync_time_out_wait_bypass : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => time_out_wait_bypass,
+ data_out => time_out_wait_bypass_s2
+ );
+
+ sync_mmcm_lock_reclocked : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => MMCM_LOCK,
+ data_out => mmcm_lock_i
+ );
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ txresetdone_s3 <= txresetdone_s2;
+
+ time_out_wait_bypass_s3 <= time_out_wait_bypass_s2;
+
+ cplllock_prev <= cplllock_sync;
+ qplllock_prev <= qplllock_sync;
+ end if;
+ end process;
+
+ sync_CPLLLOCK : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => CPLLLOCK,
+ data_out => cplllock_sync
+ );
+
+ sync_QPLLLOCK : GTX_trb3_sync_2gb_sync_block
+ port map
+ (
+ clk => STABLE_CLOCK,
+ data_in => QPLLLOCK,
+ data_out => qplllock_sync
+ );
+
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ cplllock_ris_edge <= '0';
+ elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+ cplllock_ris_edge <= '1';
+ elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+ cplllock_ris_edge <= cplllock_ris_edge;
+ else
+ cplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1' ) then
+ qplllock_ris_edge <= '0';
+ elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+ qplllock_ris_edge <= '1';
+ elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+ qplllock_ris_edge <= qplllock_ris_edge;
+ else
+ qplllock_ris_edge <= '0';
+ end if;
+ end if;
+ end process;
+
+
+
+ timeout_buffer_bypass:process(TXUSERCLK)
+ begin
+ if rising_edge(TXUSERCLK) then
+ if run_phase_alignment_int_s3 = '0' then
+ wait_bypass_count <= 0;
+ time_out_wait_bypass <= '0';
+ elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0') then
+ if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+ time_out_wait_bypass <= '1';
+ else
+ wait_bypass_count <= wait_bypass_count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+ timeout_max:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if((tx_state = ASSERT_ALL_RESETS) or
+ (tx_state = RELEASE_PLL_RESET) or
+ (tx_state = RELEASE_MMCM_RESET)) then
+ wait_time_cnt <= WAIT_TIME_MAX;
+ elsif (wait_time_cnt > 0 ) then
+ wait_time_cnt <= wait_time_cnt - 1;
+ end if;
+ end if;
+ end process;
+
+ wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+
+ --FSM for resetting the GTX/GTH/GTP in the 7-series.
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ --
+ -- Following steps are performed:
+ -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in
+ -- answer-record 43482
+ -- 2) Assert all resets on the GT and on an MMCM potentially connected.
+ -- After that wait until a reference-clock has been detected.
+ -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+ -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+ -- Also signal to the RX-side which PLL has been reset.
+ -- 5) Wait for the RESET_DONE-signal from the GT.
+ -- 6) Signal to start the phase-alignment procedure and wait for it to
+ -- finish.
+ -- 7) Reset-sequence has successfully run through. Signal this to the
+ -- rest of the design by asserting TX_FSM_RESET_DONE.
+
+ reset_fsm:process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ --if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+ tx_state <= INIT;
+ TXUSERRDY <= '0';
+ gttxreset_i <= '0';
+ MMCM_RESET <= '0';
+ tx_fsm_reset_done_int <= '0';
+ QPLL_RESET <= '0';
+ CPLL_RESET <= '0';
+ pll_reset_asserted <= '0';
+ reset_time_out <= '0';
+ retry_counter_int <= 0;
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+ else
+
+ case tx_state is
+ when INIT =>
+ --Initial state after configuration. This state will be left after
+ --approx. 500 ns and not be re-entered.
+ if init_wait_done = '1' then
+ tx_state <= ASSERT_ALL_RESETS;
+ reset_time_out <= '1';
+ end if;
+
+ when ASSERT_ALL_RESETS =>
+ --This is the state into which the FSM will always jump back if any
+ --time-outs will occur.
+ --The number of retries is reported on the output RETRY_COUNTER. In
+ --case the transceiver never comes up for some reason, this machine
+ --will still continue its best and rerun until the FPGA is turned off
+ --or the transceivers come up correctly.
+ if TX_QPLL_USED then
+ if pll_reset_asserted = '0' then
+ QPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ QPLL_RESET <= '0';
+ end if;
+ else
+ if pll_reset_asserted = '0' then
+ CPLL_RESET <= '1';
+ pll_reset_asserted <= '1';
+ else
+ CPLL_RESET <= '0';
+ end if;
+ end if;
+ TXUSERRDY <= '0';
+ gttxreset_i <= '1';
+ MMCM_RESET <= '1';
+ reset_time_out <= '1';
+ run_phase_alignment_int <= '0';
+ RESET_PHALIGNMENT <= '1';
+
+ if (TX_QPLL_USED and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+ (not TX_QPLL_USED and (cplllock_sync = '0') and pll_reset_asserted = '1') then
+ tx_state <= WAIT_FOR_PLL_LOCK;
+ end if;
+
+ when WAIT_FOR_PLL_LOCK =>
+ if(wait_time_done = '1') then
+ tx_state <= RELEASE_PLL_RESET;
+ end if;
+
+ when RELEASE_PLL_RESET =>
+ --PLL-Reset of the GTX gets released and the time-out counter
+ --starts running.
+ pll_reset_asserted <= '0';
+
+ if (TX_QPLL_USED and (qplllock_sync = '1')) or
+ (not TX_QPLL_USED and (cplllock_sync = '1')) then
+ tx_state <= WAIT_FOR_TXOUTCLK;
+ reset_time_out <= '1';
+ end if;
+
+ if time_out_2ms = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_FOR_TXOUTCLK =>
+ gttxreset_i <= '0';
+ if(wait_time_done = '1') then
+ tx_state <= RELEASE_MMCM_RESET;
+ end if;
+
+ when RELEASE_MMCM_RESET =>
+ --Release of the MMCM-reset. Waiting for the MMCM to lock.
+ MMCM_RESET <= '0';
+ reset_time_out <= '0';
+ if mmcm_lock_reclocked = '1' then
+ tx_state <= WAIT_FOR_TXUSRCLK;
+ reset_time_out <= '1';
+ end if;
+
+ if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0') then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when WAIT_FOR_TXUSRCLK =>
+ if(wait_time_done = '1') then
+ tx_state <= WAIT_RESET_DONE;
+ end if;
+
+ when WAIT_RESET_DONE =>
+ TXUSERRDY <= '1';
+ reset_time_out <= '0';
+ if txresetdone_s3 = '1' then
+ tx_state <= DO_PHASE_ALIGNMENT;
+ reset_time_out <= '1';
+ end if;
+
+ if (time_out_500us = '1' and reset_time_out = '0') then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when DO_PHASE_ALIGNMENT =>
+ --The direct handling of the signals for the Phase Alignment is done outside
+ --this state-machine.
+ RESET_PHALIGNMENT <= '0';
+ run_phase_alignment_int <= '1';
+ reset_time_out <= '0';
+
+ if PHALIGNMENT_DONE = '1' then
+ tx_state <= RESET_FSM_DONE;
+ end if;
+
+ if time_out_wait_bypass_s3 = '1' then
+ if retry_counter_int = MAX_RETRIES then
+ -- If too many retries are performed compared to what is specified in
+ -- the generic, the counter simply wraps around.
+ retry_counter_int <= 0;
+ else
+ retry_counter_int <= retry_counter_int + 1;
+ end if;
+ tx_state <= ASSERT_ALL_RESETS;
+ end if;
+
+ when RESET_FSM_DONE =>
+ reset_time_out <= '1';
+ tx_fsm_reset_done_int <= '1';
+
+ when OTHERS =>
+ tx_state <= INIT;
+
+ end case;
+ end if;
+ end if;
+ end process;
+
+end RTL;
--- /dev/null
+-- file: clk_wiz_v2_1.vhd
+--
+-- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1 100.000 0.000 50.000 130.958 98.575
+-- CLK_OUT2 200.000 0.000 50.000 114.829 98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock Input Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary 100.000 0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_trb3_sync_2gb_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end GTX_trb3_sync_2gb_CLOCK_MODULE;
+
+architecture xilinx of GTX_trb3_sync_2gb_CLOCK_MODULE is
+ attribute X_CORE_INFO : string;
+ attribute X_CORE_INFO of xilinx : architecture is "GTX_trb3_sync_2gb,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+ -- Input clock buffering / unused connectors
+ signal clkin1 : std_logic;
+ -- Output clock buffering / unused connectors
+ signal clkfbout : std_logic;
+ signal clkfbout_buf : std_logic;
+ signal clkfboutb_unused : std_logic;
+ signal clkout0 : std_logic;
+ signal clkout0b_unused : std_logic;
+ signal clkout1 : std_logic;
+ signal clkout1b_unused : std_logic;
+ signal clkout2 : std_logic;
+ signal clkout2b_unused : std_logic;
+ signal clkout3 : std_logic;
+ signal clkout3b_unused : std_logic;
+ signal clkout4_unused : std_logic;
+ signal clkout5_unused : std_logic;
+ signal clkout6_unused : std_logic;
+ -- Dynamic programming unused signals
+ signal do_unused : std_logic_vector(15 downto 0);
+ signal drdy_unused : std_logic;
+ -- Dynamic phase shift unused signals
+ signal psdone_unused : std_logic;
+ -- Unused status signals
+ signal clkfbstopped_unused : std_logic;
+ signal clkinstopped_unused : std_logic;
+begin
+
+
+ -- Input buffering
+ --------------------------------------
+ clkin1_buf : BUFG
+ port map
+ (O => clkin1,
+ I => CLK_IN);
+
+ -- Clocking primitive
+ --------------------------------------
+ -- Instantiation of the MMCM primitive
+ -- * Unused inputs are tied off
+ -- * Unused outputs are labeled unused
+
+ mmcm_adv_inst : MMCME2_ADV
+ generic map
+ (BANDWIDTH => "OPTIMIZED",
+ CLKOUT4_CASCADE => FALSE,
+ COMPENSATION => "ZHOLD",
+ STARTUP_WAIT => FALSE,
+ DIVCLK_DIVIDE => DIVIDE,
+ CLKFBOUT_MULT_F => MULT,
+ CLKFBOUT_PHASE => 0.000,
+ CLKFBOUT_USE_FINE_PS => FALSE,
+ CLKOUT0_DIVIDE_F => OUT0_DIVIDE,
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKOUT0_USE_FINE_PS => FALSE,
+ CLKIN1_PERIOD => CLK_PERIOD,
+ CLKOUT1_DIVIDE => OUT1_DIVIDE,
+ CLKOUT1_PHASE => 0.000,
+ CLKOUT1_DUTY_CYCLE => 0.500,
+ CLKOUT1_USE_FINE_PS => FALSE,
+ CLKOUT2_DIVIDE => OUT2_DIVIDE,
+ CLKOUT2_PHASE => 0.000,
+ CLKOUT2_DUTY_CYCLE => 0.500,
+ CLKOUT2_USE_FINE_PS => FALSE,
+ CLKOUT3_DIVIDE => OUT3_DIVIDE,
+ CLKOUT3_PHASE => 0.000,
+ CLKOUT3_DUTY_CYCLE => 0.500,
+ CLKOUT3_USE_FINE_PS => FALSE,
+ REF_JITTER1 => 0.010)
+ port map
+ -- Output clocks
+ (CLKFBOUT => clkfbout,
+ CLKFBOUTB => clkfboutb_unused,
+ CLKOUT0 => clkout0,
+ CLKOUT0B => clkout0b_unused,
+ CLKOUT1 => clkout1,
+ CLKOUT1B => clkout1b_unused,
+ CLKOUT2 => clkout2,
+ CLKOUT2B => clkout2b_unused,
+ CLKOUT3 => clkout3,
+ CLKOUT3B => clkout3b_unused,
+ CLKOUT4 => clkout4_unused,
+ CLKOUT5 => clkout5_unused,
+ CLKOUT6 => clkout6_unused,
+ -- Input clock control
+ CLKFBIN => clkfbout,
+ CLKIN1 => clkin1,
+ CLKIN2 => '0',
+ -- Tied to always select the primary input clock
+ CLKINSEL => '1',
+ -- Ports for dynamic reconfiguration
+ DADDR => (others => '0'),
+ DCLK => '0',
+ DEN => '0',
+ DI => (others => '0'),
+ DO => do_unused,
+ DRDY => drdy_unused,
+ DWE => '0',
+ -- Ports for dynamic phase shift
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ PSDONE => psdone_unused,
+ -- Other control and status signals
+ LOCKED => MMCM_LOCKED_OUT,
+ CLKINSTOPPED => clkinstopped_unused,
+ CLKFBSTOPPED => clkfbstopped_unused,
+ PWRDWN => '0',
+ RST => MMCM_RESET_IN);
+
+ -- Output buffering
+ -------------------------------------
+ --clkf_buf : BUFG
+ --port map
+ -- (O => clkfbout_buf,
+ -- I => clkfbout);
+
+
+ clkout0_buf : BUFG
+ port map
+ (O => CLK0_OUT,
+ I => clkout0);
+
+ clkout1_buf : BUFG
+ port map
+ (O => CLK1_OUT,
+ I => clkout1);
+
+-- clkout2_buf : BUFG
+-- port map
+-- (O => CLK2_OUT,
+-- I => clkout2);
+--
+-- clkout3_buf : BUFG
+-- port map
+-- (O => CLK3_OUT,
+-- I => clkout3);
+
+CLK2_OUT <= '0';
+CLK3_OUT <= '0';
+end xilinx;
--- /dev/null
+---------------------------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb_common.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_trb3_sync_2gb_common
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_trb3_sync_2gb_common is
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
+ SIM_QPLLREFCLK_SEL : bit_vector := "001"
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK1_IN : in std_logic;
+ GTREFCLK0_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+);
+
+end GTX_trb3_sync_2gb_common;
+
+architecture RTL of GTX_trb3_sync_2gb_common is
+
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_trb3_sync_2gb_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+ impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return "0000100000";
+ elsif (qpllfbdiv_top = 20) then
+ return "0000110000" ;
+ elsif (qpllfbdiv_top = 32) then
+ return "0001100000" ;
+ elsif (qpllfbdiv_top = 40) then
+ return "0010000000" ;
+ elsif (qpllfbdiv_top = 64) then
+ return "0011100000" ;
+ elsif (qpllfbdiv_top = 66) then
+ return "0101000000" ;
+ elsif (qpllfbdiv_top = 80) then
+ return "0100100000" ;
+ elsif (qpllfbdiv_top = 100) then
+ return "0101110000" ;
+ else
+ return "0000000000" ;
+ end if;
+ end function;
+
+ impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+ begin
+ if (qpllfbdiv_top = 16) then
+ return '1';
+ elsif (qpllfbdiv_top = 20) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 32) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 40) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 64) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 66) then
+ return '0' ;
+ elsif (qpllfbdiv_top = 80) then
+ return '1' ;
+ elsif (qpllfbdiv_top = 100) then
+ return '1' ;
+ else
+ return '1' ;
+ end if;
+ end function;
+
+ constant QPLL_FBDIV_TOP : integer := 16;
+ constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+ constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+ -- ground and tied_to_vcc_i signals
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
+
+begin
+ tied_to_ground_i <= '0';
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');
+ tied_to_vcc_i <= '1';
+ tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
+
+ --_________________________________________________________________________
+ --_________________________________________________________________________
+ --_________________________GTXE2_COMMON____________________________________
+
+ gtxe2_common_i : GTXE2_COMMON
+ generic map
+ (
+ -- Simulation attributes
+ SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
+ SIM_VERSION => "4.0",
+
+
+ ------------------COMMON BLOCK Attributes---------------
+ BIAS_CFG => (x"0000040000001000"),
+ COMMON_CFG => (x"00000000"),
+ QPLL_CFG => (x"06801C1"),
+ QPLL_CLKOUT_CFG => ("0000"),
+ QPLL_COARSE_FREQ_OVRD => ("010000"),
+ QPLL_COARSE_FREQ_OVRD_EN => ('0'),
+ QPLL_CP => ("0000011111"),
+ QPLL_CP_MONITOR_EN => ('0'),
+ QPLL_DMONITOR_SEL => ('0'),
+ QPLL_FBDIV => (QPLL_FBDIV_IN),
+ QPLL_FBDIV_MONITOR_EN => ('0'),
+ QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
+ QPLL_INIT_CFG => (x"000006"),
+ QPLL_LOCK_CFG => (x"21E8"),
+ QPLL_LPF => ("1111"),
+ QPLL_REFCLK_DIV => (1)
+
+
+ )
+ port map
+ (
+ ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
+ DRPADDR => tied_to_ground_vec_i(7 downto 0),
+ DRPCLK => tied_to_ground_i,
+ DRPDI => tied_to_ground_vec_i(15 downto 0),
+ DRPDO => open,
+ DRPEN => tied_to_ground_i,
+ DRPRDY => open,
+ DRPWE => tied_to_ground_i,
+ ---------------------- Common Block - Ref Clock Ports ---------------------
+ GTGREFCLK => tied_to_ground_i,
+ GTNORTHREFCLK0 => tied_to_ground_i,
+ GTNORTHREFCLK1 => tied_to_ground_i,
+ GTREFCLK0 => GTREFCLK0_IN,
+ GTREFCLK1 => GTREFCLK1_IN,
+ GTSOUTHREFCLK0 => tied_to_ground_i,
+ GTSOUTHREFCLK1 => tied_to_ground_i,
+ ------------------------- Common Block - QPLL Ports -----------------------
+ QPLLDMONITOR => open,
+ ----------------------- Common Block - Clocking Ports ----------------------
+ QPLLOUTCLK => QPLLOUTCLK_OUT,
+ QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
+ REFCLKOUTMONITOR => open,
+ ------------------------- Common Block - QPLL Ports ------------------------
+ QPLLFBCLKLOST => open,
+ QPLLLOCK => QPLLLOCK_OUT,
+ QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
+ QPLLLOCKEN => tied_to_vcc_i,
+ QPLLOUTRESET => tied_to_ground_i,
+ QPLLPD => tied_to_vcc_i,
+ QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
+ QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
+ QPLLRESET => QPLLRESET_IN,
+ QPLLRSVD1 => "0000000000000000",
+ QPLLRSVD2 => "11111",
+ --------------------------------- QPLL Ports -------------------------------
+ BGBYPASSB => tied_to_vcc_i,
+ BGMONITORENB => tied_to_vcc_i,
+ BGPDB => tied_to_vcc_i,
+ BGRCALOVRD => "11111",
+ PMARSVD => "00000000",
+ RCALENB => tied_to_vcc_i
+
+ );
+
+end RTL;
--- /dev/null
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb_common_reset.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Description : This module performs TX reset and initialization.
+--
+--
+--
+-- Module GTX_trb3_sync_2gb_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_trb3_sync_2gb_common_reset is
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic:= '0' --Reset QPLL
+ );
+end GTX_trb3_sync_2gb_common_reset;
+
+architecture RTL of GTX_trb3_sync_2gb_common_reset is
+
+
+ constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+ constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+ constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin
+
+
+ signal init_wait_count : std_logic_vector(7 downto 0) :=(others => '0');
+ signal init_wait_done : std_logic :='0';
+ signal common_reset_asserted : std_logic :='0';
+ signal common_reset_i : std_logic ;
+
+ type rst_type is(
+ INIT, ASSERT_COMMON_RESET);
+
+ signal state : rst_type := INIT;
+
+begin
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ -- The counter starts running when configuration has finished and
+ -- the clock is stable. When its maximum count-value has been reached,
+ -- the 500 ns from Answer Record 43482 have been passed.
+ if init_wait_count = WAIT_MAX then
+ init_wait_done <= '1';
+ else
+ init_wait_count <= init_wait_count + 1;
+ end if;
+ end if;
+ end process;
+
+ process(STABLE_CLOCK)
+ begin
+ if rising_edge(STABLE_CLOCK) then
+ if(SOFT_RESET = '1') then
+ state <= INIT;
+ common_reset_asserted <= '0';
+ COMMON_RESET <= '0';
+ else
+
+ case state is
+ when INIT =>
+ if init_wait_done = '1' then
+ state <= ASSERT_COMMON_RESET;
+ end if;
+
+ when ASSERT_COMMON_RESET =>
+ if common_reset_asserted = '0' then
+ COMMON_RESET <= '1';
+ common_reset_asserted <= '1';
+ else
+ COMMON_RESET <= '0';
+ end if;
+ when OTHERS =>
+ state <= INIT;
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end RTL;
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb_gt_usrclk_source.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+--
+-- Module GTX_trb3_sync_2gb_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_trb3_sync_2gb_GT_USRCLK_SOURCE is
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_TXCLK_LOCK_OUT : out std_logic;
+ GT0_TX_MMCM_RESET_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_OUT : out std_logic
+);
+
+
+end GTX_trb3_sync_2gb_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_trb3_sync_2gb_GT_USRCLK_SOURCE is
+
+component GTX_TRB3_SYNC_2GB_CLOCK_MODULE is
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+ (-- Clock in ports
+ CLK_IN : in std_logic;
+ -- Clock out ports
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ -- Status and control signals
+ MMCM_RESET_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_vcc_i : std_logic;
+
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_rxoutclk_i : std_logic;
+
+ attribute syn_noclockbuf : boolean;
+ signal q2_clk0_gtrefclk : std_logic;
+ attribute syn_noclockbuf of q2_clk0_gtrefclk : signal is true;
+
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal txoutclk_mmcm0_locked_i : std_logic;
+ signal txoutclk_mmcm0_reset_i : std_logic;
+ signal gt0_txoutclk_to_mmcm_i : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+ -- Static signal Assigments
+ tied_to_ground_i <= '0';
+ tied_to_vcc_i <= '1';
+ gt0_txoutclk_i <= GT0_TXOUTCLK_IN;
+ gt0_rxoutclk_i <= GT0_RXOUTCLK_IN;
+
+ Q2_CLK0_GTREFCLK_OUT <= q2_clk0_gtrefclk;
+
+ --IBUFDS_GTE2
+ ibufds_instq2_clk0 : IBUFDS_GTE2
+ port map
+ (
+ O => q2_clk0_gtrefclk,
+ ODIV2 => open,
+ CEB => tied_to_ground_i,
+ I => Q2_CLK0_GTREFCLK_PAD_P_IN,
+ IB => Q2_CLK0_GTREFCLK_PAD_N_IN
+ );
+
+
+
+ -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+ -- for improved jitter performance, and to avoid consuming an additional BUFG
+ txoutclk_mmcm0_reset_i <= GT0_TX_MMCM_RESET_IN;
+ txoutclk_mmcm0_i : GTX_trb3_sync_2gb_CLOCK_MODULE
+ generic map
+ (
+ MULT => 32.0, --// 28.0 Modified
+ DIVIDE => 5,
+ CLK_PERIOD => 8.0,
+ OUT0_DIVIDE => 8.0, --// 7.0 Modified
+ OUT1_DIVIDE => 4, --// 1 Modified
+ OUT2_DIVIDE => 1,
+ OUT3_DIVIDE => 1
+ )
+ port map
+ (
+ CLK0_OUT => gt0_txusrclk_i,
+ CLK1_OUT => GT0_TXUSRCLKX2_OUT, --// Modified
+ CLK2_OUT => open,
+ CLK3_OUT => open,
+ CLK_IN => gt0_txoutclk_i,
+ MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
+ MMCM_RESET_IN => txoutclk_mmcm0_reset_i
+ );
+
+
+ rxoutclk_bufg1_i : BUFG
+ port map
+ (
+ I => gt0_rxoutclk_i,
+ O => gt0_rxusrclk_i
+ );
+
+
+
+
+GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT <= gt0_txusrclk_i;
+GT0_TXCLK_LOCK_OUT <= txoutclk_mmcm0_locked_i;
+GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
+end RTL;
+
--- /dev/null
+------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 3.5
+-- \ \ Application : 7 Series FPGAs Transceivers Wizard
+-- / / Filename : gtx_trb3_sync_2gb_support.vhd
+-- /___/ /\
+-- \ \ / \
+-- \___\/\___\
+--
+-- Description : This module instantiates the modules required for
+-- reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_sync_2gb_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+--
+--
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_sync_2gb_support is
+generic
+(
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
+ STABLE_CLOCK_PERIOD : integer := 10
+
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_OUT : out std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ sysclk_in : in std_logic
+
+);
+
+end GTX_trb3_sync_2gb_support;
+
+architecture RTL of GTX_trb3_sync_2gb_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_trb3_sync_2gb
+
+port
+(
+ SYSCLK_IN : in std_logic;
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_IN : in std_logic;
+ GT0_TX_MMCM_RESET_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cplllockdetclk_in : in std_logic;
+ gt0_cpllreset_in : in std_logic;
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in : in std_logic;
+ gt0_gtrefclk1_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpclk_in : in std_logic;
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in : in std_logic;
+ gt0_rxusrclk2_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out : out std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in : in std_logic;
+ gt0_txusrclk2_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out : out std_logic;
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_trb3_sync_2gb_common_reset
+generic
+(
+ STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
+ );
+port
+ (
+ STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET : in std_logic; --User Reset, can be pulled any time
+ COMMON_RESET : out std_logic --Reset QPLL
+ );
+end component;
+
+component GTX_trb3_sync_2gb_common
+generic
+(
+ -- Simulation attributes
+ WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
+ SIM_QPLLREFCLK_SEL :bit_vector := "001"
+
+);
+port
+(
+ QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
+ GTREFCLK0_IN : in std_logic;
+ GTREFCLK1_IN : in std_logic;
+ QPLLLOCK_OUT : out std_logic;
+ QPLLLOCKDETCLK_IN : in std_logic;
+ QPLLOUTCLK_OUT : out std_logic;
+ QPLLOUTREFCLK_OUT : out std_logic;
+ QPLLREFCLKLOST_OUT : out std_logic;
+ QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_trb3_sync_2gb_GT_USRCLK_SOURCE
+port
+(
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_TXOUTCLK_IN : in std_logic;
+ GT0_TXCLK_LOCK_OUT : out std_logic;
+ GT0_TX_MMCM_RESET_IN : in std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+ GT0_RXOUTCLK_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_OUT : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+ constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+ signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txfsmresetdone_r : std_logic;
+ signal gt0_txfsmresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+
+
+signal reset_pulse : std_logic_vector(3 downto 0);
+ signal reset_counter : unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+ -------------------------- GT Wrapper Wires ------------------------------
+ --________________________________________________________________________
+ --________________________________________________________________________
+ --GT0 (X1Y10)
+
+ --------------------------------- CPLL Ports -------------------------------
+ signal gt0_cpllfbclklost_i : std_logic;
+ signal gt0_cplllock_i : std_logic;
+ signal gt0_cpllrefclklost_i : std_logic;
+ signal gt0_cpllreset_i : std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
+ signal gt0_drpdi_i : std_logic_vector(15 downto 0);
+ signal gt0_drpdo_i : std_logic_vector(15 downto 0);
+ signal gt0_drpen_i : std_logic;
+ signal gt0_drprdy_i : std_logic;
+ signal gt0_drpwe_i : std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ signal gt0_dmonitorout_i : std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ signal gt0_eyescanreset_i : std_logic;
+ signal gt0_rxuserrdy_i : std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ signal gt0_eyescandataerror_i : std_logic;
+ signal gt0_eyescantrigger_i : std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ signal gt0_rxdisperr_i : std_logic_vector(1 downto 0);
+ signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ signal gt0_gtxrxp_i : std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ signal gt0_gtxrxn_i : std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ signal gt0_rxdlyen_i : std_logic;
+ signal gt0_rxdlysreset_i : std_logic;
+ signal gt0_rxdlysresetdone_i : std_logic;
+ signal gt0_rxphalign_i : std_logic;
+ signal gt0_rxphaligndone_i : std_logic;
+ signal gt0_rxphalignen_i : std_logic;
+ signal gt0_rxphdlyreset_i : std_logic;
+ signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
+ signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
+ -------------------- Receive Ports - RX Equailizer Ports -------------------
+ signal gt0_rxlpmhfhold_i : std_logic;
+ signal gt0_rxlpmlfhold_i : std_logic;
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ signal gt0_rxdfelpmreset_i : std_logic;
+ signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
+ signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ signal gt0_rxoutclk_i : std_logic;
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ signal gt0_gtrxreset_i : std_logic;
+ signal gt0_rxpmareset_i : std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ signal gt0_rxresetdone_i : std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ signal gt0_gttxreset_i : std_logic;
+ signal gt0_txuserrdy_i : std_logic;
+ ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+ signal gt0_txdlyen_i : std_logic;
+ signal gt0_txdlysreset_i : std_logic;
+ signal gt0_txdlysresetdone_i : std_logic;
+ signal gt0_txphalign_i : std_logic;
+ signal gt0_txphaligndone_i : std_logic;
+ signal gt0_txphalignen_i : std_logic;
+ signal gt0_txphdlyreset_i : std_logic;
+ signal gt0_txphinit_i : std_logic;
+ signal gt0_txphinitdone_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gt0_txdata_i : std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ signal gt0_gtxtxn_i : std_logic;
+ signal gt0_gtxtxp_i : std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ signal gt0_txoutclk_i : std_logic;
+ signal gt0_txoutclkfabric_i : std_logic;
+ signal gt0_txoutclkpcs_i : std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ signal gt0_txresetdone_i : std_logic;
+
+ --____________________________COMMON PORTS________________________________
+ signal gt0_qplllock_i : std_logic;
+ signal gt0_qpllrefclklost_i : std_logic;
+ signal gt0_qpllreset_i : std_logic;
+ signal gt0_qpllreset_t : std_logic;
+ signal gt0_qplloutclk_i : std_logic;
+ signal gt0_qplloutrefclk_i : std_logic;
+
+ ------------------------------- Global Signals -----------------------------
+ signal gt0_tx_system_reset_c : std_logic;
+ signal gt0_rx_system_reset_c : std_logic;
+ signal tied_to_ground_i : std_logic;
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
+ signal tied_to_vcc_i : std_logic;
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
+ signal drpclk_in_i : std_logic;
+ signal sysclk_in_i : std_logic;
+ signal GTTXRESET_IN : std_logic;
+ signal GTRXRESET_IN : std_logic;
+ signal CPLLRESET_IN : std_logic;
+ signal QPLLRESET_IN : std_logic;
+
+ attribute keep: string;
+ ------------------------------- User Clocks ---------------------------------
+ signal gt0_txusrclk_i : std_logic;
+ signal gt0_txusrclk2_i : std_logic;
+ signal gt0_rxusrclk_i : std_logic;
+ signal gt0_rxusrclk2_i : std_logic;
+
+
+
+
+ signal gt0_txmmcm_lock_i : std_logic;
+ signal gt0_txmmcm_reset_i : std_logic;
+ ----------------------------- Reference Clocks ----------------------------
+
+signal q2_clk0_refclk_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+ -- Static signal Assigments
+tied_to_ground_i <= '0';
+tied_to_ground_vec_i <= x"0000000000000000";
+tied_to_vcc_i <= '1';
+tied_to_vcc_vec_i <= "11111111";
+
+ GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+
+ gt0_qpllreset_t <= tied_to_vcc_i;
+ gt0_qplloutclk_out <= gt0_qplloutclk_i;
+ gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+
+ GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
+ GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+ GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+ GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+
+
+ gt_usrclk_source : GTX_trb3_sync_2gb_GT_USRCLK_SOURCE
+ port map
+ (
+
+ GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_TXUSRCLKX2_OUT => GT0_TXUSRCLKX2_OUT, --// Modified
+ GT0_TXOUTCLK_IN => gt0_txoutclk_i,
+ GT0_TXCLK_LOCK_OUT => gt0_txmmcm_lock_i,
+ GT0_TX_MMCM_RESET_IN => gt0_txmmcm_reset_i,
+ GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
+ Q2_CLK0_GTREFCLK_PAD_N_IN => Q2_CLK0_GTREFCLK_PAD_N_IN,
+ Q2_CLK0_GTREFCLK_PAD_P_IN => Q2_CLK0_GTREFCLK_PAD_P_IN,
+ Q2_CLK0_GTREFCLK_OUT => q2_clk0_refclk_i
+
+ );
+
+sysclk_in_i <= sysclk_in;
+
+ common0_i:GTX_trb3_sync_2gb_common
+ generic map
+ (
+ WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+ SIM_QPLLREFCLK_SEL => "001"
+ )
+ port map
+ (
+ QPLLREFCLKSEL_IN => "001",
+ GTREFCLK0_IN => q2_clk0_refclk_i,
+ GTREFCLK1_IN => tied_to_ground_i,
+ QPLLLOCK_OUT => gt0_qplllock_i,
+ QPLLLOCKDETCLK_IN => sysclk_in_i,
+ QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+ QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+ QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
+ QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+ common_reset_i:GTX_trb3_sync_2gb_common_reset
+ generic map
+ (
+ STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
+ )
+ port map
+ (
+ STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
+ SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
+ COMMON_RESET => commonreset_i --Reset QPLL
+ );
+
+
+ GTX_trb3_sync_2gb_init_i : GTX_trb3_sync_2gb
+ port map
+ (
+ sysclk_in => sysclk_in_i,
+ soft_reset_tx_in => SOFT_RESET_TX_IN,
+ soft_reset_rx_in => SOFT_RESET_RX_IN,
+ dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
+ gt0_tx_mmcm_lock_in => gt0_txmmcm_lock_i,
+ gt0_tx_mmcm_reset_out => gt0_txmmcm_reset_i,
+ gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
+ gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
+ gt0_data_valid_in => gt0_data_valid_in,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y10)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
+ gt0_cplllock_out => gt0_cplllock_out,
+ gt0_cplllockdetclk_in => sysclk_in_i,
+ gt0_cpllreset_in => gt0_cpllreset_in,
+ -------------------------- Channel - Clocking Ports ------------------------
+ gt0_gtrefclk0_in => q2_clk0_refclk_i,
+ gt0_gtrefclk1_in => tied_to_ground_i,
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => gt0_drpaddr_in,
+ gt0_drpclk_in => sysclk_in_i,
+ gt0_drpdi_in => gt0_drpdi_in,
+ gt0_drpdo_out => gt0_drpdo_out,
+ gt0_drpen_in => gt0_drpen_in,
+ gt0_drprdy_out => gt0_drprdy_out,
+ gt0_drpwe_in => gt0_drpwe_in,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => gt0_dmonitorout_out,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => gt0_eyescanreset_in,
+ gt0_rxuserrdy_in => gt0_rxuserrdy_in,
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => gt0_eyescandataerror_out,
+ gt0_eyescantrigger_in => gt0_eyescantrigger_in,
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified
+ GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified
+ ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+ gt0_rxusrclk_in => gt0_rxusrclk_i,
+ gt0_rxusrclk2_in => gt0_rxusrclk2_i,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_out,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => gt0_rxdisperr_out,
+ gt0_rxnotintable_out => gt0_rxnotintable_out,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => gt0_gtxrxp_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => gt0_gtxrxn_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => gt0_rxphmonitor_out,
+ gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in,
+ gt0_rxmonitorout_out => gt0_rxmonitorout_out,
+ gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
+ --------------- Receive Ports - RX Fabric Output Control Ports -------------
+ gt0_rxoutclk_out => gt0_rxoutclk_i,
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_in,
+ gt0_rxpmareset_in => gt0_rxpmareset_in,
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_out,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_out,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_in,
+ gt0_txuserrdy_in => gt0_txuserrdy_in,
+ ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+ gt0_txusrclk_in => gt0_txusrclk_i,
+ gt0_txusrclk2_in => gt0_txusrclk2_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_in,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => gt0_gtxtxn_out,
+ gt0_gtxtxp_out => gt0_gtxtxp_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclk_out => gt0_txoutclk_i,
+ gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
+ gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_in,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_out,
+
+
+
+ gt0_qplloutclk_in => gt0_qplloutclk_i,
+ gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+ );
+
+
+
+end RTL;
+
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--- /dev/null
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+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">14.250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">7.125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___200.000______0.000______50.0_______89.238_____78.520</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clock100to200</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">89.238</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">78.520</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">90.666</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">79.592</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clock100to200</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">14.250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">7.125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_18x512_oreg</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Input_Port</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
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--- /dev/null
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--- /dev/null
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+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
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+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________200.000___________500.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">8.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">8.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">BUF_IN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___200.000______0.000______50.0______119.192_____71.149</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">PLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">pll_in200_out200</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">500.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">500.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">112.745</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">65.553</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFGCE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">pll_in200_out200</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">PS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">BUF_IN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.JITTER_OPTIONS" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.JITTER_SEL" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_REF_JITTER1" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_REF_JITTER2" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OVERRIDE_MMCM" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_MIN_POWER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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+ <spirit:library>xci</spirit:library>
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+ <spirit:componentInstances>
+ <spirit:componentInstance>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">53.333</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________200.000____________0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">15</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___200.000______0.000______50.0______100.010_____97.786</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2___100.000______0.000______50.0______114.523_____97.786</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3____80.000______0.000______50.0______119.805_____97.786</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">CLK_OUT4____53.333______0.000______50.0______130.134_____97.786</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Differential_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">pll_in200_out200_160_100_80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">100.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">97.786</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">114.523</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">97.786</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">119.805</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">97.786</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">80.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">130.134</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">97.786</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">53.33333</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">pll_in200_out200_160_100_80</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">10</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">15</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Differential_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
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+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
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--- /dev/null
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+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
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+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
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+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
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+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+
+entity fifo_19x16_obuf is
+port(
+ Data : in std_logic_vector(18 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmFullThresh : in std_logic_vector(3 downto 0);
+ Q : out std_logic_vector(18 downto 0);
+ WCNT : out std_logic_vector(4 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic
+);
+end entity;
+
+
+
+
+
+architecture fifo_19x16_obuf_arch of fifo_19x16_obuf is
+
+
+
+component xilinx_fifo_19x16_obuf IS
+port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(18 downto 0);
+ prog_full_thresh: IN std_logic_VECTOR(3 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(3 downto 0);
+ dout: OUT std_logic_VECTOR(18 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ prog_full: OUT std_logic
+);
+end component;
+
+
+
+begin
+
+WCNT(4) <= '0';
+
+the_xilinx_fifo_19x16_obuf: xilinx_fifo_19x16_obuf
+port map(
+ clk => Clock,
+ din => Data,
+ prog_full_thresh => AmFullThresh,
+ rd_en => RdEn,
+ rst => Reset,
+ wr_en => WrEn,
+ data_count => WCNT(3 downto 0),
+ dout => Q,
+ empty => Empty,
+ full => Full,
+ prog_full => AlmostFull
+);
+
+end architecture;
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+
+entity fifo_sbuf is
+port(
+ Data: in std_logic_vector(18 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(18 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic
+);
+end entity;
+
+
+
+
+
+architecture fifo_sbuf_arch of fifo_sbuf is
+
+
+
+component xilinx_fifo_sbuf IS
+port (
+ din: IN std_logic_VECTOR(18 downto 0);
+ clk: IN std_logic;
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ dout: OUT std_logic_VECTOR(18 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ almost_full: OUT std_logic
+);
+end component;
+
+
+
+begin
+
+
+the_xilinx_fifo_sbuf: xilinx_fifo_sbuf
+port map(
+ din => Data,
+ clk => Clock,
+ wr_en => WrEn,
+ rd_en => RdEn,
+ rst => Reset,
+ dout => Q,
+ empty => Empty,
+ full => Full,
+ almost_full => AlmostFull
+);
+
+end architecture;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity fifo_var_oreg is
+ generic(
+ FIFO_WIDTH : integer range 1 to 64 := 36;
+ FIFO_DEPTH : integer range 1 to 16 := 8
+ );
+ port(
+ Data : in std_logic_vector(FIFO_WIDTH-1 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0);
+ Q : out std_logic_vector(FIFO_WIDTH-1 downto 0);
+ WCNT : out std_logic_vector(FIFO_DEPTH downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic
+ );
+end entity;
+
+architecture fifo_var_oreg_arch of fifo_var_oreg is
+
+component fifo_18x512_oreg
+ port (
+ clk : in std_logic;
+ din : in std_logic_vector(17 downto 0);
+ prog_full_thresh : in std_logic_vector(8 downto 0);
+ rd_en : in std_logic;
+ rst : in std_logic;
+ wr_en : in std_logic;
+ data_count : out std_logic_vector(8 downto 0);
+ dout : out std_logic_vector(17 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ prog_full : out std_logic
+ );
+end component;
+
+component fifo_36x512_oreg
+ port (
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ prog_full_thresh : in std_logic_vector(8 downto 0);
+ rd_en : in std_logic;
+ rst : in std_logic;
+ wr_en : in std_logic;
+ data_count : out std_logic_vector(8 downto 0);
+ dout : out std_logic_vector(35 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ prog_full : out std_logic
+ );
+end component;
+
+
+component fifo_36x16k_oreg
+ port (
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ prog_full_thresh : in std_logic_vector(13 downto 0);
+ rd_en : in std_logic;
+ rst : in std_logic;
+ wr_en : in std_logic;
+ data_count : out std_logic_vector(13 downto 0);
+ dout : out std_logic_vector(35 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ prog_full : out std_logic
+ );
+end component;
+
+component fifo_36x32k_oreg
+ port (
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ prog_full_thresh : in std_logic_vector(14 downto 0);
+ rd_en : in std_logic;
+ rst : in std_logic;
+ wr_en : in std_logic;
+ data_count : out std_logic_vector(14 downto 0);
+ dout : out std_logic_vector(35 downto 0);
+ empty : out std_logic;
+ full : out std_logic;
+ prog_full : out std_logic
+ );
+end component;
+
+begin
+
+assert (FIFO_DEPTH >= 13 and FIFO_DEPTH <= 14 and FIFO_WIDTH = 36)
+ or (FIFO_DEPTH >= 9 and FIFO_DEPTH <= 9 and FIFO_WIDTH = 18)
+ or (FIFO_DEPTH >= 9 and FIFO_DEPTH <= 9 and FIFO_WIDTH = 36)
+ report "Selected data buffer size not implemented: depth - "&integer'image(FIFO_DEPTH)& ", width + 4 : " &integer'image(FIFO_WIDTH) severity error;
+
+
+
+ gen_36_16k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 14 generate
+ THE_FIFO : fifo_36x16k_oreg
+ port map(
+ din => Data,
+ clk => Clock,
+ wr_en => WrEn,
+ rd_en => RdEn,
+ rst => Reset,
+ prog_full_thresh => AmFullThresh,
+ dout => Q,
+ data_count => WCNT(13 downto 0),
+ empty => Empty,
+ full => Full,
+ prog_full => AlmostFull
+ );
+ end generate;
+
+
+ gen_36_32k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 15 generate
+ THE_FIFO : fifo_36x32k_oreg
+ port map(
+ din => Data,
+ clk => Clock,
+ wr_en => WrEn,
+ rd_en => RdEn,
+ rst => Reset,
+ prog_full_thresh => AmFullThresh,
+ dout => Q,
+ data_count => WCNT(14 downto 0),
+ empty => Empty,
+ full => Full,
+ prog_full => AlmostFull
+ );
+ end generate;
+
+ gen_36_512 : if FIFO_WIDTH = 36 and FIFO_DEPTH = 9 generate
+ THE_FIFO : fifo_36x512_oreg
+ port map(
+ din => Data,
+ clk => Clock,
+ wr_en => WrEn,
+ rd_en => RdEn,
+ rst => Reset,
+ prog_full_thresh => AmFullThresh,
+ dout => Q,
+ data_count => WCNT(8 downto 0),
+ empty => Empty,
+ full => Full,
+ prog_full => AlmostFull
+ );
+ end generate;
+
+ gen_18_512 : if FIFO_WIDTH = 18 and FIFO_DEPTH = 9 generate
+ THE_FIFO : fifo_18x512_oreg
+ port map(
+ din => Data,
+ clk => Clock,
+ wr_en => WrEn,
+ rd_en => RdEn,
+ rst => Reset,
+ prog_full_thresh => AmFullThresh,
+ dout => Q,
+ data_count => WCNT(8 downto 0),
+ empty => Empty,
+ full => Full,
+ prog_full => AlmostFull
+ );
+ end generate;
+
+
+
+end architecture;
--- /dev/null
+-- file: pll_in200_out200_clk_wiz.vhd
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1___200.000______0.000______50.0______112.745_____65.553
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________200.000___________500.000
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity jittercleaner_200M is
+port
+ (
+ clk_in : in std_logic;
+ clk_out : out std_logic;
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end jittercleaner_200M;
+
+architecture behavior of jittercleaner_200M is
+ -- Output clock buffering / unused connectors
+ signal clkfbout_pll_in200_out200 : std_logic;
+ signal clkfbout_buf_pll_in200_out200 : std_logic;
+ signal clkfboutb_unused : std_logic;
+ signal clk_out1_pll_in200_out200 : std_logic;
+ signal clkout0b_unused : std_logic;
+ signal clkout1_unused : std_logic;
+ signal clkout1b_unused : std_logic;
+ signal clkout2_unused : std_logic;
+ signal clkout2b_unused : std_logic;
+ signal clkout3_unused : std_logic;
+ signal clkout3b_unused : std_logic;
+ signal clkout4_unused : std_logic;
+ signal clkout5_unused : std_logic;
+ signal clkout6_unused : std_logic;
+ -- Dynamic programming unused signals
+ signal do_unused : std_logic_vector(15 downto 0);
+ signal drdy_unused : std_logic;
+ -- Dynamic phase shift unused signals
+ signal psdone_unused : std_logic;
+ signal locked_int : std_logic;
+ -- Unused status signals
+ signal clkfbstopped_unused : std_logic;
+ signal clkinstopped_unused : std_logic;
+ signal reset_high : std_logic;
+
+begin
+
+
+ -- Clocking PRIMITIVE
+ --------------------------------------
+ -- Instantiation of the MMCM PRIMITIVE
+ -- * Unused inputs are tied off
+ -- * Unused outputs are labeled unused
+ plle2 : PLLE2_ADV
+ generic map
+ (BANDWIDTH => "HIGH",
+ COMPENSATION => "ZHOLD",
+ DIVCLK_DIVIDE => 1,
+ CLKFBOUT_MULT => 9,
+ CLKFBOUT_PHASE => 0.000,
+ CLKOUT0_DIVIDE => 9,
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKIN1_PERIOD => 5.0)
+ port map
+ -- Output clocks
+ (
+ CLKFBOUT => clkfbout_pll_in200_out200,
+ CLKOUT0 => clk_out1_pll_in200_out200,
+ CLKOUT1 => clkout1_unused,
+ CLKOUT2 => clkout2_unused,
+ CLKOUT3 => clkout3_unused,
+ CLKOUT4 => clkout4_unused,
+ CLKOUT5 => clkout5_unused,
+ -- Input clock control
+ CLKFBIN => clkfbout_buf_pll_in200_out200,
+ CLKIN1 => clk_in,
+ CLKIN2 => '0',
+ -- Tied to always select the primary input clock
+ CLKINSEL => '1',
+ -- Ports for dynamic reconfiguration
+ DADDR => (others => '0'),
+ DCLK => '0',
+ DEN => '0',
+ DI => (others => '0'),
+ DO => do_unused,
+ DRDY => drdy_unused,
+ DWE => '0',
+ -- Other control and status signals
+ LOCKED => locked_int,
+ PWRDWN => '0',
+ RST => reset_high);
+
+ reset_high <= reset;
+ locked <= locked_int;
+
+ -- Output buffering
+ -------------------------------------
+
+ clkf_buf : BUFG
+ port map
+ (O => clkfbout_buf_pll_in200_out200,
+ I => clkfbout_pll_in200_out200);
+
+
+
+ clkout1_buf : BUFG
+ port map
+ (O => clk_out,
+ I => clk_out1_pll_in200_out200);
+
+
+
+end behavior;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+package lattice_ecp2m_fifo is
+
+ component fifo_var_oreg is
+ generic(
+ FIFO_WIDTH : integer range 1 to 64 := 36;
+ FIFO_DEPTH : integer range 1 to 16 := 8
+ );
+ port(
+ Data : in std_logic_vector(FIFO_WIDTH-1 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0);
+ Q : out std_logic_vector(FIFO_WIDTH-1 downto 0);
+ WCNT : out std_logic_vector(FIFO_DEPTH downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic
+ );
+ end component;
+
+end package;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 18-07-2013
+-- Module Name: serdesQuadMUXwrapper
+-- Description: Module with a quad serdes/GTX with synchronized transmit frequency and 16 bits bus
+-- Modifications:
+-- 29-08-2014 ADCCLOCKFREQUENCY added: SODA clock at 80MHz
+-- 27-01-2015 SCI interface removed
+-- 29-02-2015 txUsrClkDiv2 removed
+-- 04-05-2015 version for Kintex7
+-- 26-05-2015 version with only two fibers
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+----------------------------------------------------------------------------------
+-- serdesQuadMUXwrapper
+-- Quad serdes/GTX tranceiver for PANDA Front End Electronics and Multiplexer with synchronised transmitted data.
+--
+--
+--
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+--
+-- Inputs:
+-- refClk : Reference clock for the serdes, synchronous with transmitted data
+-- refClk_P : differential input pad for Reference clock for GTP/GTX, if internal clock cannot be used (Xilinx), now used for one of the reference clocks
+-- refClk_N : differential input pad for Reference clock for GTP/GTX, if internal clock cannot be used (Xilinx), now used for one of the reference clocks
+-- sysClk : Local bus system clock for serdes control interface and LEDs
+-- gtpReset : reset serdes
+-- refClkIn : reference clock from other part of QUAD, for common GTX module
+-- txUsrClk : clock for the synchronous data to be transmitted, SODA clock
+-- For channel0 in quad serdes :
+-- G0_txData : transmit data, clocked with refClk that is synchrouous with SODA
+-- G0_rxP,G0_rxN : differential input to the serdes
+-- G0_LOS : no fiber signal detected
+-- G0_txCharIsK0 : data is K-character
+-- For channel1 in quad serdes :
+-- G1_txData : transmit data, clocked with refClk that is synchrouous with SODA
+-- G1_rxP,G0_rxN : differential input to the serdes
+-- G1_LOS : no fiber signal detected
+-- G1_txCharIsK0 : data is K-character
+-- For channel2 in quad serdes :
+-- G2_txData : transmit data, clocked with refClk that is synchrouous with SODA
+-- G2_rxP,G0_rxN : differential input to the serdes
+-- G2_LOS : no fiber signal detected
+-- G2_txCharIsK0 : data is K-character
+-- For channel3 in quad serdes :
+-- G3_txData : transmit data, clocked with refClk that is synchrouous with SODA
+-- G3_rxP,G0_rxN : differential input to the serdes
+-- G3_LOS : no fiber signal detected
+-- G3_txCharIsK0 : data is K-character
+-- GT0_QPLLOUTCLK_IN : QPLL reference clock, needed for Xilinx
+-- GT0_QPLLOUTREFCLK_IN : QPLL reference clock, needed for Xilinx
+--
+-- Outputs:
+-- refClkOut : reference clock output
+-- refClk_OK : indicates if refClkOut is stable (PLL locked) (always 1 for Lattice serdes)
+-- txpll_clocks : clock used at GTX transmitter
+-- For channel0 in quad serdes :
+-- G0_rxData : Data received, clocked with G0_rxUsrClk
+-- G0_txP,G0_txN : differential transmit outputs of the serdes
+-- G0_rxUsrClk : clock for received data
+-- G0_rxLocked : Receiver is locked to incomming data
+-- G0_rxNotInTable : Error in received data
+-- G0_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+-- G0_rxCharIsK0 : received data is K-character
+-- For channel1 in quad serdes :
+-- G1_rxData : Data received, clocked with G1_rxUsrClk
+-- G1_txP,G0_txN : differential transmit outputs of the serdes
+-- G1_rxUsrClk : clock for received data
+-- G1_rxLocked : Receiver is locked to incomming data
+-- G1_rxNotInTable : Error in received data
+-- G1_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+-- G1_rxCharIsK0 : received data is K-character
+-- For channel2 in quad serdes :
+-- G2_rxData : Data received, clocked with G2_rxUsrClk
+-- G2_txP,G0_txN : differential transmit outputs of the serdes
+-- G2_rxUsrClk : clock for received data
+-- G2_rxLocked : Receiver is locked to incomming data
+-- G2_rxNotInTable : Error in received data
+-- G2_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+-- G2_rxCharIsK0 : received data is K-character
+-- For channel3 in quad serdes :
+-- G3_rxData : Data received, clocked with G3_rxUsrClk
+-- G3_txP,G0_txN : differential transmit outputs of the serdes
+-- G3_rxUsrClk : clock for received data
+-- G3_rxLocked : Receiver is locked to incomming data
+-- G3_rxNotInTable : Error in received data
+-- G3_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+-- G3_rxCharIsK0 : received data is K-character
+-- LEDs_link_ok : serdes status for LED on extension board : link ok
+-- LEDs_rx : serdes status for LED on extension board : receive
+-- LEDs_tx : serdes status for LED on extension board : transmit
+--
+--
+-- Components:
+-- GTX_quadSODA_support : wrapper module for GTX, produced by IP core generator
+-- DC_data8to16 : data from 8 bits to 16 bits on half clock speed
+-- DC_data16to8 : data from 16 bits to 8 bits on double clock speed
+-- clock100to200 : clock doubler : 100MHz to 200MHz
+-- sync_bit : Synchronization for 1 bit cross clock signal
+--
+----------------------------------------------------------------------------------
+
+entity serdesQuadMUXwrapper is
+ port (
+ refClk : in std_logic;
+ refClk_P : in std_logic := '0';
+ refClk_N : in std_logic := '1';
+ sysClk : in std_logic;
+ gtpReset : in std_logic;
+
+ refClk_OK : out std_logic;
+ txpll_clocks : out std_logic_vector(3 downto 0);
+
+ G0_txData : in std_logic_vector (7 downto 0);
+ G0_rxData : out std_logic_vector (7 downto 0);
+ G0_txP : out std_logic;
+ G0_txN : out std_logic;
+ G0_rxP : in std_logic;
+ G0_rxN : in std_logic;
+ G0_LOS : in std_logic;
+ G0_rxUsrClk : out std_logic; -- 200MHz
+ G0_rxLocked : out std_logic;
+ G0_rxNotInTable : out std_logic;
+ G0_txLocked : out std_logic;
+ G0_txCharIsK0 : in std_logic;
+ G0_rxCharIsK0 : out std_logic;
+
+ G1_txData : in std_logic_vector (7 downto 0);
+ G1_rxData : out std_logic_vector (7 downto 0);
+ G1_txP : out std_logic;
+ G1_txN : out std_logic;
+ G1_rxP : in std_logic;
+ G1_rxN : in std_logic;
+ G1_LOS : in std_logic;
+ G1_rxUsrClk : out std_logic; -- 200MHz
+ G1_rxLocked : out std_logic;
+ G1_rxNotInTable : out std_logic;
+ G1_txLocked : out std_logic;
+ G1_txCharIsK0 : in std_logic;
+ G1_rxCharIsK0 : out std_logic;
+
+ G2_txData : in std_logic_vector (7 downto 0);
+ G2_rxData : out std_logic_vector (7 downto 0);
+ G2_txP : out std_logic;
+ G2_txN : out std_logic;
+ G2_rxP : in std_logic;
+ G2_rxN : in std_logic;
+ G2_LOS : in std_logic;
+ G2_rxUsrClk : out std_logic; -- 200MHz
+ G2_rxLocked : out std_logic;
+ G2_rxNotInTable : out std_logic;
+ G2_txLocked : out std_logic;
+ G2_txCharIsK0 : in std_logic;
+ G2_rxCharIsK0 : out std_logic;
+
+ G3_txData : in std_logic_vector (7 downto 0);
+ G3_rxData : out std_logic_vector (7 downto 0);
+ G3_txP : out std_logic;
+ G3_txN : out std_logic;
+ G3_rxP : in std_logic;
+ G3_rxN : in std_logic;
+ G3_LOS : in std_logic;
+ G3_rxUsrClk : out std_logic; -- 200MHz
+ G3_rxLocked : out std_logic;
+ G3_rxNotInTable : out std_logic;
+ G3_txLocked : out std_logic;
+ G3_txCharIsK0 : in std_logic;
+ G3_rxCharIsK0 : out std_logic;
+
+ LEDs_link_ok : out std_logic_vector(0 to 3);
+ LEDs_rx : out std_logic_vector(0 to 3);
+ LEDs_tx : out std_logic_vector(0 to 3);
+
+ GT0_QPLLOUTCLK_IN : in std_logic := '0';
+ GT0_QPLLOUTREFCLK_IN : in std_logic := '0';
+ testword0 : out std_logic_vector (35 downto 0) := (others => '0');
+ testword0clock : out std_logic := '0'
+ );
+end serdesQuadMUXwrapper;
+
+architecture Behavioral of serdesQuadMUXwrapper is
+
+component GTX_dualSODA_support
+generic
+(
+ -- Simulation attributes
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to TRUE to speed up sim reset
+ STABLE_CLOCK_PERIOD : integer := 16
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --_________________________________________________________________________
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN : in std_logic;
+ GT0_QPLLOUTREFCLK_IN : in std_logic;
+ sysclk_in : in std_logic;
+ q2_clk1_gtrefclk : in std_logic; --//modification
+ q3_clk0_gtrefclk : in std_logic --//modification
+);
+end component;
+
+component DC_data8to16 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ kchar_in : in std_logic;
+ clock_out : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ kchar_out : out std_logic_vector(1 downto 0)
+ );
+end component;
+
+component DC_data16to8 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ kchar_in : in std_logic_vector(1 downto 0);
+ notintable_in : in std_logic_vector(1 downto 0);
+ clock_out : out std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ kchar_out : out std_logic;
+ notintable_out : out std_logic
+ );
+end component;
+
+component clock100to200 is
+ port
+ (
+ clk_in1 : in std_logic;
+ clk_out1 : out std_logic;
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+component sync_bit is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+end component;
+
+ constant DLY : time := 1 ns;
+signal gt0_txusrclkX2_i : std_logic;
+
+signal gt0_txusrclk2_i : std_logic;
+signal gt1_txusrclk2_i : std_logic;
+signal gt2_txusrclk2_i : std_logic;
+signal gt3_txusrclk2_i : std_logic;
+signal gt0_rxusrclk2_i : std_logic;
+signal gt1_rxusrclk2_i : std_logic;
+signal gt2_rxusrclk2_i : std_logic;
+signal gt3_rxusrclk2_i : std_logic;
+
+signal gt0_txdata_i : std_logic_vector(15 downto 0);
+signal gt1_txdata_i : std_logic_vector(15 downto 0);
+signal gt2_txdata_i : std_logic_vector(15 downto 0);
+signal gt3_txdata_i : std_logic_vector(15 downto 0);
+signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+signal gt1_txcharisk_i : std_logic_vector(1 downto 0);
+signal gt2_txcharisk_i : std_logic_vector(1 downto 0);
+signal gt3_txcharisk_i : std_logic_vector(1 downto 0);
+
+signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+signal gt1_rxdata_i : std_logic_vector(15 downto 0);
+signal gt2_rxdata_i : std_logic_vector(15 downto 0);
+signal gt3_rxdata_i : std_logic_vector(15 downto 0);
+signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+signal gt1_rxnotintable_i : std_logic_vector(1 downto 0);
+signal gt2_rxnotintable_i : std_logic_vector(1 downto 0);
+signal gt3_rxnotintable_i : std_logic_vector(1 downto 0);
+signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+signal gt1_rxcharisk_i : std_logic_vector(1 downto 0);
+signal gt2_rxcharisk_i : std_logic_vector(1 downto 0);
+signal gt3_rxcharisk_i : std_logic_vector(1 downto 0);
+
+signal gt0_gtrxreset_i : std_logic;
+signal gt1_gtrxreset_i : std_logic;
+signal gt2_gtrxreset_i : std_logic;
+signal gt3_gtrxreset_i : std_logic;
+signal gt0_gttxreset_i : std_logic;
+signal gt1_gttxreset_i : std_logic;
+signal gt2_gttxreset_i : std_logic;
+signal gt3_gttxreset_i : std_logic;
+signal gt0_txresetdone_i : std_logic;
+signal gt1_txresetdone_i : std_logic;
+signal gt2_txresetdone_i : std_logic;
+signal gt3_txresetdone_i : std_logic;
+
+signal gt0_rxresetdone_i : std_logic;
+signal gt1_rxresetdone_i : std_logic;
+signal gt2_rxresetdone_i : std_logic;
+signal gt3_rxresetdone_i : std_logic;
+
+
+--************************** Register Declarations ****************************
+attribute ASYNC_REG : string;
+signal gt_txfsmresetdone_i : std_logic;
+signal gt_txfsmresetdone_r : std_logic;
+signal gt_txfsmresetdone_r2 : std_logic;
+attribute ASYNC_REG of gt_txfsmresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt_txfsmresetdone_r2 : signal is "TRUE";
+signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_txfsmresetdone_r : std_logic;
+signal gt0_txfsmresetdone_r2 : std_logic;
+attribute ASYNC_REG of gt0_txfsmresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt0_txfsmresetdone_r2 : signal is "TRUE";
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+attribute ASYNC_REG of gt0_rxresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt0_rxresetdone_r2 : signal is "TRUE";
+attribute ASYNC_REG of gt0_rxresetdone_r3 : signal is "TRUE";
+signal gt1_txfsmresetdone_i : std_logic;
+signal gt1_txfsmresetdone_r : std_logic;
+signal gt1_txfsmresetdone_r2 : std_logic;
+attribute ASYNC_REG of gt1_txfsmresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt1_txfsmresetdone_r2 : signal is "TRUE";
+signal gt1_rxresetdone_r : std_logic;
+signal gt1_rxresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r3 : std_logic;
+attribute ASYNC_REG of gt1_rxresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt1_rxresetdone_r2 : signal is "TRUE";
+attribute ASYNC_REG of gt1_rxresetdone_r3 : signal is "TRUE";
+
+
+ begin
+G2_rxData <= (others => '0');
+G2_txP <= '0';
+G2_txN <= '0';
+G2_rxUsrClk <= '0';
+G2_rxLocked <= '0';
+G2_rxNotInTable <= '0';
+G2_txLocked <= '0';
+G2_rxCharIsK0 <= '0';
+
+
+G3_rxData <= (others => '0');
+G3_txP <= '0';
+G3_txN <= '0';
+G3_rxUsrClk <= '0';
+G3_rxLocked <= '0';
+G3_rxNotInTable <= '0';
+G3_txLocked <= '0';
+G3_rxCharIsK0 <= '0';
+
+
+txpll_clocks(0) <= gt0_txusrclkX2_i;
+txpll_clocks(1) <= gt0_txusrclkX2_i;
+txpll_clocks(2) <= gt0_txusrclkX2_i;
+txpll_clocks(3) <= gt0_txusrclkX2_i;
+
+clock100to200a: clock100to200 port map(
+ clk_in1 => gt0_txusrclk2_i,
+ clk_out1 => gt0_txusrclkX2_i,
+ reset => '0',
+ locked => open);
+
+
+DC_data8to16_0: DC_data8to16 port map(
+ clock_in => gt0_txusrclkX2_i,
+ data_in => G0_txData,
+ kchar_in => G0_txCharIsK0,
+ clock_out => gt0_txusrclk2_i,
+ data_out => gt0_txdata_i,
+ kchar_out => gt0_txcharisk_i);
+DC_data8to16_1: DC_data8to16 port map(
+ clock_in => gt0_txusrclkX2_i,
+ data_in => G1_txData,
+ kchar_in => G1_txCharIsK0,
+ clock_out => gt0_txusrclk2_i,
+ data_out => gt1_txdata_i,
+ kchar_out => gt1_txcharisk_i);
+
+
+DC_data16to8_0: DC_data16to8 port map(
+ clock_in => gt0_rxusrclk2_i,
+ data_in => gt0_rxdata_i,
+ kchar_in => gt0_rxcharisk_i,
+ notintable_in => gt0_rxnotintable_i,
+ clock_out => G0_rxUsrClk,
+ data_out => G0_rxData,
+ kchar_out => G0_rxCharIsK0,
+ notintable_out => G0_rxNotInTable);
+DC_data16to8_1: DC_data16to8 port map(
+ clock_in => gt1_rxusrclk2_i,
+ data_in => gt1_rxdata_i,
+ kchar_in => gt1_rxcharisk_i,
+ notintable_in => gt1_rxnotintable_i,
+ clock_out => G1_rxUsrClk,
+ data_out => G1_rxData,
+ kchar_out => G1_rxCharIsK0,
+ notintable_out => G1_rxNotInTable);
+
+GTX_dualSODA_support1: GTX_dualSODA_support port map(
+ SOFT_RESET_TX_IN => gtpReset,
+ SOFT_RESET_RX_IN => gtpReset,
+ DONT_RESET_ON_DATA_ERROR_IN => '0',
+ Q2_CLK1_GTREFCLK_PAD_N_IN => '0', -- not used, IBUFDS_GTE2 buffer is at top level
+ Q2_CLK1_GTREFCLK_PAD_P_IN => '0', -- not used, IBUFDS_GTE2 buffer is at top level
+
+ GT0_TX_FSM_RESET_DONE_OUT => gt0_txfsmresetdone_i,
+ GT0_RX_FSM_RESET_DONE_OUT => open,
+ GT0_DATA_VALID_IN => '1',
+ GT1_TX_FSM_RESET_DONE_OUT => gt1_txfsmresetdone_i,
+ GT1_RX_FSM_RESET_DONE_OUT => open,
+ GT1_DATA_VALID_IN => '1',
+
+ GT0_TXUSRCLK_OUT => open,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_RXUSRCLK_OUT => open,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+
+ GT1_TXUSRCLK_OUT => open,
+ GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
+ GT1_RXUSRCLK_OUT => open,
+ GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => open,
+ gt0_cplllock_out => refClk_OK,
+ gt0_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => (others => '0'),
+ gt0_drpdi_in => (others => '0'),
+ gt0_drpdo_out => open,
+ gt0_drpen_in => '0',
+ gt0_drprdy_out => open,
+ gt0_drpwe_in => '0',
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => '0',
+ gt0_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => open,
+ gt0_eyescantrigger_in => '0',
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => open,
+ gt0_rxnotintable_out => gt0_rxnotintable_i,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => G0_rxP,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => G0_rxN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => open,
+ gt0_rxphslipmonitor_out => open,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => '0',
+ gt0_rxmonitorout_out => open,
+ gt0_rxmonitorsel_in => "00",
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_i,
+ gt0_rxpmareset_in => '0',
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_i,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => gt0_gttxreset_i,
+ gt0_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => G0_txN,
+ gt0_gtxtxp_out => G0_txP,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out => testword0(35),
+ gt0_txoutclkpcs_out => testword0(34),
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_i,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out => open,
+ gt1_cplllock_out => open,
+ gt1_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in => (others => '0'),
+ gt1_drpdi_in => (others => '0'),
+ gt1_drpdo_out => open,
+ gt1_drpen_in => '0',
+ gt1_drprdy_out => open,
+ gt1_drpwe_in => '0',
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in => '0',
+ gt1_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out => open,
+ gt1_eyescantrigger_in => '0',
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out => gt1_rxdata_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out => open,
+ gt1_rxnotintable_out => gt1_rxnotintable_i,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in => G1_rxP,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in => G1_rxN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out => open,
+ gt1_rxphslipmonitor_out => open,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in => '0',
+ gt1_rxmonitorout_out => open,
+ gt1_rxmonitorsel_in => "00",
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in => gt1_gtrxreset_i,
+ gt1_rxpmareset_in => '0',
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out => gt1_rxcharisk_i,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out => gt1_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in => gt1_gttxreset_i,
+ gt1_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in => gt1_txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out => G1_txN,
+ gt1_gtxtxp_out => G1_txP,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclkfabric_out => open,
+ gt1_txoutclkpcs_out => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in => gt1_txcharisk_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out => gt1_txresetdone_i,
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
+ GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
+ sysclk_in => sysClk,
+ q2_clk1_gtrefclk => refClk_P, --//modification
+ q3_clk0_gtrefclk => refClk_N --//modification
+ );
+
+ -------------------------- User Module Resets -----------------------------
+ -- All the User Modules are held in reset till the RESETDONE goes high.
+ -- The RESETDONE is registered a couple of times on USRCLK2 and connected
+ -- to the reset of the modules
+
+process(gt0_rxusrclk2_i,gt0_rxresetdone_i,G0_LOS)
+ begin
+ if(gt0_rxresetdone_i = '0') or (G0_LOS='1') then
+ gt0_rxresetdone_r <= '0' after DLY;
+ gt0_rxresetdone_r2 <= '0' after DLY;
+ gt0_rxresetdone_r3 <= '0' after DLY;
+elsif (gt0_rxusrclk2_i'event and gt0_rxusrclk2_i = '1') then
+ gt0_rxresetdone_r <= gt0_rxresetdone_i after DLY;
+ gt0_rxresetdone_r2 <= gt0_rxresetdone_r after DLY;
+ gt0_rxresetdone_r3 <= gt0_rxresetdone_r2 after DLY;
+ end if;
+ end process;
+process(gt0_txusrclk2_i,gt0_txfsmresetdone_i,gt0_txresetdone_i)
+ begin
+ if(gt0_txfsmresetdone_i = '0') or (gt0_txresetdone_i='0') then
+ gt0_txfsmresetdone_r <= '0' after DLY;
+ gt0_txfsmresetdone_r2 <= '0' after DLY;
+elsif (gt0_txusrclk2_i'event and gt0_txusrclk2_i = '1') then
+ gt0_txfsmresetdone_r <= gt0_txfsmresetdone_i after DLY;
+ gt0_txfsmresetdone_r2 <= gt0_txfsmresetdone_r after DLY;
+ end if;
+ end process;
+
+process(gt1_rxusrclk2_i,gt1_rxresetdone_i,G1_LOS)
+ begin
+ if(gt1_rxresetdone_i = '0') or (G1_LOS='1') then
+ gt1_rxresetdone_r <= '0' after DLY;
+ gt1_rxresetdone_r2 <= '0' after DLY;
+ gt1_rxresetdone_r3 <= '0' after DLY;
+elsif (gt1_rxusrclk2_i'event and gt1_rxusrclk2_i = '1') then
+ gt1_rxresetdone_r <= gt1_rxresetdone_i after DLY;
+ gt1_rxresetdone_r2 <= gt1_rxresetdone_r after DLY;
+ gt1_rxresetdone_r3 <= gt1_rxresetdone_r2 after DLY;
+ end if;
+ end process;
+process(gt1_txusrclk2_i,gt1_txfsmresetdone_i,gt1_txresetdone_i)
+ begin
+ if(gt1_txfsmresetdone_i = '0') or (gt1_txresetdone_i='0') then
+ gt1_txfsmresetdone_r <= '0' after DLY;
+ gt1_txfsmresetdone_r2 <= '0' after DLY;
+elsif (gt1_txusrclk2_i'event and gt1_txusrclk2_i = '1') then
+ gt1_txfsmresetdone_r <= gt1_txfsmresetdone_i after DLY;
+ gt1_txfsmresetdone_r2 <= gt1_txfsmresetdone_r after DLY;
+ end if;
+ end process;
+
+
+G0_rxLocked <= gt0_rxresetdone_r3;
+G1_rxLocked <= gt1_rxresetdone_r3;
+
+G0_rxLocked <= gt0_rxresetdone_r3;
+G0_txLocked <= gt0_txfsmresetdone_r2;
+G1_txLocked <= gt1_txfsmresetdone_r2;
+
+
+gt0_gtrxreset_i <= '1' when (G0_LOS='1') or (gtpReset='1') else '0';
+gt1_gtrxreset_i <= '1' when (G1_LOS='1') or (gtpReset='1') else '0';
+
+gt0_gttxreset_i <= '1' when (G0_LOS='1') or (gtpReset='1') else '0';
+gt1_gttxreset_i <= '1' when (G1_LOS='1') or (gtpReset='1') else '0';
+
+
+LEDs_link_ok(0) <= '1' when (gt0_rxresetdone_r3='1') and (gt0_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(1) <= '1' when (gt0_rxresetdone_r3='1') and (gt1_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(2) <= '0';
+LEDs_link_ok(3) <= '0';
+
+LEDs_rx <= (others => '0');
+LEDs_tx <= (others => '0');
+
+
+end Behavioral;
+
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 18-07-2013
+-- Module Name: serdesQuadMUXwrapper
+-- Description: Module with a quad serdes/GTX with synchronized transmit frequency and 16 bits bus
+-- Modifications:
+-- 29-08-2014 ADCCLOCKFREQUENCY added: SODA clock at 80MHz
+-- 27-01-2015 SCI interface removed
+-- 29-02-2015 txUsrClkDiv2 removed
+-- 04-05-2015 version for Kintex7
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+----------------------------------------------------------------------------------
+-- serdesQuadMUXwrapper
+-- Quad serdes/GTX tranceiver for PANDA Front End Electronics and Multiplexer with synchronised transmitted data.
+--
+--
+--
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+--
+-- Inputs:
+-- gtpClk : Reference clock for the serdes, synchronous with transmitted data
+-- gtpClk_P : differential input pad for Reference clock for GTP/GTX, if internal clock cannot be used (Xilinx)
+-- gtpClk_N : differential input pad for Reference clock for GTP/GTX, if internal clock cannot be used (Xilinx)
+-- sysClk : Local bus system clock for serdes control interface and LEDs
+-- gtpReset : reset serdes
+-- txUsrClk : clock for the synchronous data to be transmitted, SODA clock
+-- For channel0 in quad serdes :
+-- G0_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+-- G0_rxP,G0_rxN : differential input to the serdes
+-- G0_LOS : no fiber signal detected
+-- G0_txCharIsK0 : data is K-character
+-- For channel1 in quad serdes :
+-- G1_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+-- G1_rxP,G0_rxN : differential input to the serdes
+-- G1_LOS : no fiber signal detected
+-- G1_txCharIsK0 : data is K-character
+-- For channel2 in quad serdes :
+-- G2_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+-- G2_rxP,G0_rxN : differential input to the serdes
+-- G2_LOS : no fiber signal detected
+-- G2_txCharIsK0 : data is K-character
+-- For channel3 in quad serdes :
+-- G3_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+-- G3_rxP,G0_rxN : differential input to the serdes
+-- G3_LOS : no fiber signal detected
+-- G3_txCharIsK0 : data is K-character
+--
+-- Outputs:
+-- refClkOut : reference clock output
+-- refClk_OK : indicates if refClkOut is stable (PLL locked) (always 1 for Lattice serdes)
+-- txpll_clocks : clock used at GTX transmitter
+-- For channel0 in quad serdes :
+-- G0_rxData : Data received, clocked with G0_rxUsrClk
+-- G0_txP,G0_txN : differential transmit outputs of the serdes
+-- G0_rxUsrClk : clock for received data
+-- G0_rxLocked : Receiver is locked to incomming data
+-- G0_rxNotInTable : Error in received data
+-- G0_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+-- G0_rxCharIsK0 : received data is K-character
+-- For channel1 in quad serdes :
+-- G1_rxData : Data received, clocked with G1_rxUsrClk
+-- G1_txP,G0_txN : differential transmit outputs of the serdes
+-- G1_rxUsrClk : clock for received data
+-- G1_rxLocked : Receiver is locked to incomming data
+-- G1_rxNotInTable : Error in received data
+-- G1_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+-- G1_rxCharIsK0 : received data is K-character
+-- For channel2 in quad serdes :
+-- G2_rxData : Data received, clocked with G2_rxUsrClk
+-- G2_txP,G0_txN : differential transmit outputs of the serdes
+-- G2_rxUsrClk : clock for received data
+-- G2_rxLocked : Receiver is locked to incomming data
+-- G2_rxNotInTable : Error in received data
+-- G2_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+-- G2_rxCharIsK0 : received data is K-character
+-- For channel3 in quad serdes :
+-- G3_rxData : Data received, clocked with G3_rxUsrClk
+-- G3_txP,G0_txN : differential transmit outputs of the serdes
+-- G3_rxUsrClk : clock for received data
+-- G3_rxLocked : Receiver is locked to incomming data
+-- G3_rxNotInTable : Error in received data
+-- G3_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+-- G3_rxCharIsK0 : received data is K-character
+-- LEDs_link_ok : serdes status for LED on extension board : link ok
+-- LEDs_rx : serdes status for LED on extension board : receive
+-- LEDs_tx : serdes status for LED on extension board : transmit
+--
+--
+-- Components:
+-- GTX_quadSODA_support : wrapper module for GTX, produced by IP core generator
+-- DC_data8to16 : data from 8 bits to 16 bits on half clock speed
+-- DC_data16to8 : data from 16 bits to 8 bits on double clock speed
+-- clock100to200 : clock doubler : 100MHz to 200MHz
+-- sync_bit : Synchronization for 1 bit cross clock signal
+--
+----------------------------------------------------------------------------------
+
+entity serdesQuadMUXwrapper is
+ port (
+ gtpClk : in std_logic;
+ gtpClk_P : in std_logic := '0';
+ gtpClk_N : in std_logic := '1';
+ sysClk : in std_logic;
+ gtpReset : in std_logic;
+
+ refClkOut : out std_logic;
+ refClk_OK : out std_logic;
+ txpll_clocks : out std_logic_vector(3 downto 0);
+
+ G0_txData : in std_logic_vector (7 downto 0);
+ G0_rxData : out std_logic_vector (7 downto 0);
+ G0_txP : out std_logic;
+ G0_txN : out std_logic;
+ G0_rxP : in std_logic;
+ G0_rxN : in std_logic;
+ G0_LOS : in std_logic;
+ G0_rxUsrClk : out std_logic; -- 200MHz
+ G0_rxLocked : out std_logic;
+ G0_rxNotInTable : out std_logic;
+ G0_txLocked : out std_logic;
+ G0_txCharIsK0 : in std_logic;
+ G0_rxCharIsK0 : out std_logic;
+
+ G1_txData : in std_logic_vector (7 downto 0);
+ G1_rxData : out std_logic_vector (7 downto 0);
+ G1_txP : out std_logic;
+ G1_txN : out std_logic;
+ G1_rxP : in std_logic;
+ G1_rxN : in std_logic;
+ G1_LOS : in std_logic;
+ G1_rxUsrClk : out std_logic; -- 200MHz
+ G1_rxLocked : out std_logic;
+ G1_rxNotInTable : out std_logic;
+ G1_txLocked : out std_logic;
+ G1_txCharIsK0 : in std_logic;
+ G1_rxCharIsK0 : out std_logic;
+
+ G2_txData : in std_logic_vector (7 downto 0);
+ G2_rxData : out std_logic_vector (7 downto 0);
+ G2_txP : out std_logic;
+ G2_txN : out std_logic;
+ G2_rxP : in std_logic;
+ G2_rxN : in std_logic;
+ G2_LOS : in std_logic;
+ G2_rxUsrClk : out std_logic; -- 200MHz
+ G2_rxLocked : out std_logic;
+ G2_rxNotInTable : out std_logic;
+ G2_txLocked : out std_logic;
+ G2_txCharIsK0 : in std_logic;
+ G2_rxCharIsK0 : out std_logic;
+
+ G3_txData : in std_logic_vector (7 downto 0);
+ G3_rxData : out std_logic_vector (7 downto 0);
+ G3_txP : out std_logic;
+ G3_txN : out std_logic;
+ G3_rxP : in std_logic;
+ G3_rxN : in std_logic;
+ G3_LOS : in std_logic;
+ G3_rxUsrClk : out std_logic; -- 200MHz
+ G3_rxLocked : out std_logic;
+ G3_rxNotInTable : out std_logic;
+ G3_txLocked : out std_logic;
+ G3_txCharIsK0 : in std_logic;
+ G3_rxCharIsK0 : out std_logic;
+
+ LEDs_link_ok : out std_logic_vector(0 to 3);
+ LEDs_rx : out std_logic_vector(0 to 3);
+ LEDs_tx : out std_logic_vector(0 to 3);
+
+ testword0 : out std_logic_vector (35 downto 0) := (others => '0');
+ testword0clock : out std_logic := '0'
+ );
+end serdesQuadMUXwrapper;
+
+architecture Behavioral of serdesQuadMUXwrapper is
+
+component GTX_quadSODA_support
+generic
+(
+ -- Simulation attributes
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to TRUE to speed up sim reset
+ STABLE_CLOCK_PERIOD : integer := 10
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT1_DATA_VALID_IN : in std_logic;
+ GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT2_DATA_VALID_IN : in std_logic;
+ GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT3_DATA_VALID_IN : in std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ GT1_TXUSRCLK_OUT : out std_logic;
+ GT1_TXUSRCLK2_OUT : out std_logic;
+ GT1_RXUSRCLK_OUT : out std_logic;
+ GT1_RXUSRCLK2_OUT : out std_logic;
+
+ GT2_TXUSRCLK_OUT : out std_logic;
+ GT2_TXUSRCLK2_OUT : out std_logic;
+ GT2_RXUSRCLK_OUT : out std_logic;
+ GT2_RXUSRCLK2_OUT : out std_logic;
+
+ GT3_TXUSRCLK_OUT : out std_logic;
+ GT3_TXUSRCLK2_OUT : out std_logic;
+ GT3_RXUSRCLK_OUT : out std_logic;
+ GT3_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y12)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+ --_________________________________________________________________________
+ --GT1 (X1Y13)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out : out std_logic;
+ gt1_cplllock_out : out std_logic;
+ gt1_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt1_drpdi_in : in std_logic_vector(15 downto 0);
+ gt1_drpdo_out : out std_logic_vector(15 downto 0);
+ gt1_drpen_in : in std_logic;
+ gt1_drprdy_out : out std_logic;
+ gt1_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in : in std_logic;
+ gt1_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out : out std_logic;
+ gt1_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in : in std_logic;
+ gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in : in std_logic;
+ gt1_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in : in std_logic;
+ gt1_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out : out std_logic;
+ gt1_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclkfabric_out : out std_logic;
+ gt1_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out : out std_logic;
+
+ --_________________________________________________________________________
+ --GT2 (X1Y14)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out : out std_logic;
+ gt2_cplllock_out : out std_logic;
+ gt2_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt2_drpdi_in : in std_logic_vector(15 downto 0);
+ gt2_drpdo_out : out std_logic_vector(15 downto 0);
+ gt2_drpen_in : in std_logic;
+ gt2_drprdy_out : out std_logic;
+ gt2_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in : in std_logic;
+ gt2_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out : out std_logic;
+ gt2_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt2_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt2_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in : in std_logic;
+ gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in : in std_logic;
+ gt2_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in : in std_logic;
+ gt2_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out : out std_logic;
+ gt2_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclkfabric_out : out std_logic;
+ gt2_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out : out std_logic;
+
+ --_________________________________________________________________________
+ --GT3 (X1Y15)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out : out std_logic;
+ gt3_cplllock_out : out std_logic;
+ gt3_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt3_drpdi_in : in std_logic_vector(15 downto 0);
+ gt3_drpdo_out : out std_logic_vector(15 downto 0);
+ gt3_drpen_in : in std_logic;
+ gt3_drprdy_out : out std_logic;
+ gt3_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in : in std_logic;
+ gt3_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out : out std_logic;
+ gt3_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt3_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt3_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in : in std_logic;
+ gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in : in std_logic;
+ gt3_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in : in std_logic;
+ gt3_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out : out std_logic;
+ gt3_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclkfabric_out : out std_logic;
+ gt3_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ sysclk_in : in std_logic
+);
+end component;
+
+component DC_data8to16 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ kchar_in : in std_logic;
+ clock_out : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ kchar_out : out std_logic_vector(1 downto 0)
+ );
+end component;
+
+component DC_data16to8 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ kchar_in : in std_logic_vector(1 downto 0);
+ notintable_in : in std_logic_vector(1 downto 0);
+ clock_out : out std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ kchar_out : out std_logic;
+ notintable_out : out std_logic
+ );
+end component;
+
+component clock100to200 is
+ port
+ (
+ clk_in1 : in std_logic;
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+component sync_bit is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+end component;
+
+ constant DLY : time := 1 ns;
+signal gt0_txusrclkX2_i : std_logic;
+
+signal gt0_txusrclk2_i : std_logic;
+signal gt1_txusrclk2_i : std_logic;
+signal gt2_txusrclk2_i : std_logic;
+signal gt3_txusrclk2_i : std_logic;
+signal gt0_rxusrclk2_i : std_logic;
+signal gt1_rxusrclk2_i : std_logic;
+signal gt2_rxusrclk2_i : std_logic;
+signal gt3_rxusrclk2_i : std_logic;
+
+signal gt0_txdata_i : std_logic_vector(15 downto 0);
+signal gt1_txdata_i : std_logic_vector(15 downto 0);
+signal gt2_txdata_i : std_logic_vector(15 downto 0);
+signal gt3_txdata_i : std_logic_vector(15 downto 0);
+signal gt0_txcharisk_i : std_logic_vector(1 downto 0);
+signal gt1_txcharisk_i : std_logic_vector(1 downto 0);
+signal gt2_txcharisk_i : std_logic_vector(1 downto 0);
+signal gt3_txcharisk_i : std_logic_vector(1 downto 0);
+
+signal gt0_rxdata_i : std_logic_vector(15 downto 0);
+signal gt1_rxdata_i : std_logic_vector(15 downto 0);
+signal gt2_rxdata_i : std_logic_vector(15 downto 0);
+signal gt3_rxdata_i : std_logic_vector(15 downto 0);
+signal gt0_rxnotintable_i : std_logic_vector(1 downto 0);
+signal gt1_rxnotintable_i : std_logic_vector(1 downto 0);
+signal gt2_rxnotintable_i : std_logic_vector(1 downto 0);
+signal gt3_rxnotintable_i : std_logic_vector(1 downto 0);
+signal gt0_rxcharisk_i : std_logic_vector(1 downto 0);
+signal gt1_rxcharisk_i : std_logic_vector(1 downto 0);
+signal gt2_rxcharisk_i : std_logic_vector(1 downto 0);
+signal gt3_rxcharisk_i : std_logic_vector(1 downto 0);
+
+signal gt0_gtrxreset_i : std_logic;
+signal gt1_gtrxreset_i : std_logic;
+signal gt2_gtrxreset_i : std_logic;
+signal gt3_gtrxreset_i : std_logic;
+signal gt0_txresetdone_i : std_logic;
+signal gt1_txresetdone_i : std_logic;
+signal gt2_txresetdone_i : std_logic;
+signal gt3_txresetdone_i : std_logic;
+
+signal gt0_rxresetdone_i : std_logic;
+signal gt1_rxresetdone_i : std_logic;
+signal gt2_rxresetdone_i : std_logic;
+signal gt3_rxresetdone_i : std_logic;
+
+
+--************************** Register Declarations ****************************
+attribute ASYNC_REG : string;
+signal gt_txfsmresetdone_i : std_logic;
+signal gt_txfsmresetdone_r : std_logic;
+signal gt_txfsmresetdone_r2 : std_logic;
+attribute ASYNC_REG of gt_txfsmresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt_txfsmresetdone_r2 : signal is "TRUE";
+signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_txfsmresetdone_r : std_logic;
+signal gt0_txfsmresetdone_r2 : std_logic;
+attribute ASYNC_REG of gt0_txfsmresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt0_txfsmresetdone_r2 : signal is "TRUE";
+signal gt0_rxresetdone_r : std_logic;
+signal gt0_rxresetdone_r2 : std_logic;
+signal gt0_rxresetdone_r3 : std_logic;
+attribute ASYNC_REG of gt0_rxresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt0_rxresetdone_r2 : signal is "TRUE";
+attribute ASYNC_REG of gt0_rxresetdone_r3 : signal is "TRUE";
+signal gt1_txfsmresetdone_i : std_logic;
+signal gt1_txfsmresetdone_r : std_logic;
+signal gt1_txfsmresetdone_r2 : std_logic;
+attribute ASYNC_REG of gt1_txfsmresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt1_txfsmresetdone_r2 : signal is "TRUE";
+signal gt1_rxresetdone_r : std_logic;
+signal gt1_rxresetdone_r2 : std_logic;
+signal gt1_rxresetdone_r3 : std_logic;
+attribute ASYNC_REG of gt1_rxresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt1_rxresetdone_r2 : signal is "TRUE";
+attribute ASYNC_REG of gt1_rxresetdone_r3 : signal is "TRUE";
+signal gt2_txfsmresetdone_i : std_logic;
+signal gt2_txfsmresetdone_r : std_logic;
+signal gt2_txfsmresetdone_r2 : std_logic;
+attribute ASYNC_REG of gt2_txfsmresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt2_txfsmresetdone_r2 : signal is "TRUE";
+signal gt2_rxresetdone_r : std_logic;
+signal gt2_rxresetdone_r2 : std_logic;
+signal gt2_rxresetdone_r3 : std_logic;
+attribute ASYNC_REG of gt2_rxresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt2_rxresetdone_r2 : signal is "TRUE";
+attribute ASYNC_REG of gt2_rxresetdone_r3 : signal is "TRUE";
+signal gt3_txfsmresetdone_i : std_logic;
+signal gt3_txfsmresetdone_r : std_logic;
+signal gt3_txfsmresetdone_r2 : std_logic;
+attribute ASYNC_REG of gt3_txfsmresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt3_txfsmresetdone_r2 : signal is "TRUE";
+signal gt3_rxresetdone_r : std_logic;
+signal gt3_rxresetdone_r2 : std_logic;
+signal gt3_rxresetdone_r3 : std_logic;
+attribute ASYNC_REG of gt3_rxresetdone_r : signal is "TRUE";
+attribute ASYNC_REG of gt3_rxresetdone_r2 : signal is "TRUE";
+attribute ASYNC_REG of gt3_rxresetdone_r3 : signal is "TRUE";
+
+
+ begin
+
+refClkOut <= gtpClk;
+refClk_OK <= '1';
+
+txpll_clocks(0) <= gt0_txusrclkX2_i;
+txpll_clocks(1) <= gt0_txusrclkX2_i;
+txpll_clocks(2) <= gt0_txusrclkX2_i;
+txpll_clocks(3) <= gt0_txusrclkX2_i;
+
+clock100to200a: clock100to200 port map(
+ clk_in1 => gt0_txusrclk2_i,
+ clk_out1 => open,
+ clk_out2 => gt0_txusrclkX2_i,
+ reset => '0',
+ locked => open);
+
+
+DC_data8to16_0: DC_data8to16 port map(
+ clock_in => gt0_txusrclkX2_i,
+ data_in => G0_txData,
+ kchar_in => G0_txCharIsK0,
+ clock_out => gt0_txusrclk2_i,
+ data_out => gt0_txdata_i,
+ kchar_out => gt0_txcharisk_i);
+DC_data8to16_1: DC_data8to16 port map(
+ clock_in => gt0_txusrclkX2_i,
+ data_in => G1_txData,
+ kchar_in => G1_txCharIsK0,
+ clock_out => gt0_txusrclk2_i,
+ data_out => gt1_txdata_i,
+ kchar_out => gt1_txcharisk_i);
+DC_data8to16_2: DC_data8to16 port map(
+ clock_in => gt0_txusrclkX2_i,
+ data_in => G2_txData,
+ kchar_in => G2_txCharIsK0,
+ clock_out => gt0_txusrclk2_i,
+ data_out => gt2_txdata_i,
+ kchar_out => gt2_txcharisk_i);
+DC_data8to16_3: DC_data8to16 port map(
+ clock_in => gt0_txusrclkX2_i,
+ data_in => G3_txData,
+ kchar_in => G3_txCharIsK0,
+ clock_out => gt0_txusrclk2_i,
+ data_out => gt3_txdata_i,
+ kchar_out => gt3_txcharisk_i);
+
+DC_data16to8_0: DC_data16to8 port map(
+ clock_in => gt0_rxusrclk2_i,
+ data_in => gt0_rxdata_i,
+ kchar_in => gt0_rxcharisk_i,
+ notintable_in => gt0_rxnotintable_i,
+ clock_out => G0_rxUsrClk,
+ data_out => G0_rxData,
+ kchar_out => G0_rxCharIsK0,
+ notintable_out => G0_rxNotInTable);
+DC_data16to8_1: DC_data16to8 port map(
+ clock_in => gt1_rxusrclk2_i,
+ data_in => gt1_rxdata_i,
+ kchar_in => gt1_rxcharisk_i,
+ notintable_in => gt1_rxnotintable_i,
+ clock_out => G1_rxUsrClk,
+ data_out => G1_rxData,
+ kchar_out => G1_rxCharIsK0,
+ notintable_out => G1_rxNotInTable);
+DC_data16to8_2: DC_data16to8 port map(
+ clock_in => gt2_rxusrclk2_i,
+ data_in => gt2_rxdata_i,
+ kchar_in => gt2_rxcharisk_i,
+ notintable_in => gt2_rxnotintable_i,
+ clock_out => G2_rxUsrClk,
+ data_out => G2_rxData,
+ kchar_out => G2_rxCharIsK0,
+ notintable_out => G2_rxNotInTable);
+DC_data16to8_3: DC_data16to8 port map(
+ clock_in => gt3_rxusrclk2_i,
+ data_in => gt3_rxdata_i,
+ kchar_in => gt3_rxcharisk_i,
+ notintable_in => gt3_rxnotintable_i,
+ clock_out => G3_rxUsrClk,
+ data_out => G3_rxData,
+ kchar_out => G3_rxCharIsK0,
+ notintable_out => G3_rxNotInTable);
+
+GTX_quadSODA_support1: GTX_quadSODA_support port map(
+ SOFT_RESET_TX_IN => gtpReset,
+ SOFT_RESET_RX_IN => gtpReset,
+ DONT_RESET_ON_DATA_ERROR_IN => '0',
+ Q2_CLK1_GTREFCLK_PAD_N_IN => gtpClk_N,
+ Q2_CLK1_GTREFCLK_PAD_P_IN => gtpClk_P,
+
+ GT0_TX_FSM_RESET_DONE_OUT => gt0_txfsmresetdone_i,
+ GT0_RX_FSM_RESET_DONE_OUT => open,
+ GT0_DATA_VALID_IN => '1',
+ GT1_TX_FSM_RESET_DONE_OUT => gt1_txfsmresetdone_i,
+ GT1_RX_FSM_RESET_DONE_OUT => open,
+ GT1_DATA_VALID_IN => '1',
+ GT2_TX_FSM_RESET_DONE_OUT => gt2_txfsmresetdone_i,
+ GT2_RX_FSM_RESET_DONE_OUT => open,
+ GT2_DATA_VALID_IN => '1',
+ GT3_TX_FSM_RESET_DONE_OUT => gt3_txfsmresetdone_i,
+ GT3_RX_FSM_RESET_DONE_OUT => open,
+ GT3_DATA_VALID_IN => '1',
+
+ GT0_TXUSRCLK_OUT => open,
+ GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+ GT0_RXUSRCLK_OUT => open,
+ GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+
+ GT1_TXUSRCLK_OUT => open,
+ GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
+ GT1_RXUSRCLK_OUT => open,
+ GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
+
+ GT2_TXUSRCLK_OUT => open,
+ GT2_TXUSRCLK2_OUT => gt2_txusrclk2_i,
+ GT2_RXUSRCLK_OUT => open,
+ GT2_RXUSRCLK2_OUT => gt2_rxusrclk2_i,
+
+ GT3_TXUSRCLK_OUT => open,
+ GT3_TXUSRCLK2_OUT => gt3_txusrclk2_i,
+ GT3_RXUSRCLK_OUT => open,
+ GT3_RXUSRCLK2_OUT => gt3_rxusrclk2_i,
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y12)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => open,
+ gt0_cplllock_out => open,
+ gt0_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => (others => '0'),
+ gt0_drpdi_in => (others => '0'),
+ gt0_drpdo_out => open,
+ gt0_drpen_in => '0',
+ gt0_drprdy_out => open,
+ gt0_drpwe_in => '0',
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => '0',
+ gt0_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => open,
+ gt0_eyescantrigger_in => '0',
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => gt0_rxdata_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => open,
+ gt0_rxnotintable_out => gt0_rxnotintable_i,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => G0_rxP,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => G0_rxN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => open,
+ gt0_rxphslipmonitor_out => open,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => '0',
+ gt0_rxmonitorout_out => open,
+ gt0_rxmonitorsel_in => "00",
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => gt0_gtrxreset_i,
+ gt0_rxpmareset_in => '0',
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => gt0_rxcharisk_i,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => gt0_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => '0',
+ gt0_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => gt0_txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => G0_txN,
+ gt0_gtxtxp_out => G0_txP,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out => testword0(35),
+ gt0_txoutclkpcs_out => testword0(34),
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => gt0_txcharisk_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_i,
+
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT1 (X1Y13)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt1_cpllfbclklost_out => open,
+ gt1_cplllock_out => open,
+ gt1_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt1_drpaddr_in => (others => '0'),
+ gt1_drpdi_in => (others => '0'),
+ gt1_drpdo_out => open,
+ gt1_drpen_in => '0',
+ gt1_drprdy_out => open,
+ gt1_drpwe_in => '0',
+ --------------------------- Digital Monitor Ports --------------------------
+ gt1_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt1_eyescanreset_in => '0',
+ gt1_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt1_eyescandataerror_out => open,
+ gt1_eyescantrigger_in => '0',
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt1_rxdata_out => gt1_rxdata_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt1_rxdisperr_out => open,
+ gt1_rxnotintable_out => gt1_rxnotintable_i,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt1_gtxrxp_in => G1_rxP,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt1_gtxrxn_in => G1_rxN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt1_rxphmonitor_out => open,
+ gt1_rxphslipmonitor_out => open,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt1_rxdfelpmreset_in => '0',
+ gt1_rxmonitorout_out => open,
+ gt1_rxmonitorsel_in => "00",
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt1_gtrxreset_in => gt1_gtrxreset_i,
+ gt1_rxpmareset_in => '0',
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt1_rxcharisk_out => gt1_rxcharisk_i,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt1_rxresetdone_out => gt1_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt1_gttxreset_in => '0',
+ gt1_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt1_txdata_in => gt1_txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt1_gtxtxn_out => G1_txN,
+ gt1_gtxtxp_out => G1_txP,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt1_txoutclkfabric_out => open,
+ gt1_txoutclkpcs_out => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt1_txcharisk_in => gt1_txcharisk_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt1_txresetdone_out => gt1_txresetdone_i,
+
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT2 (X1Y14)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt2_cpllfbclklost_out => open,
+ gt2_cplllock_out => open,
+ gt2_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt2_drpaddr_in => (others => '0'),
+ gt2_drpdi_in => (others => '0'),
+ gt2_drpdo_out => open,
+ gt2_drpen_in => '0',
+ gt2_drprdy_out => open,
+ gt2_drpwe_in => '0',
+ --------------------------- Digital Monitor Ports --------------------------
+ gt2_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt2_eyescanreset_in => '0',
+ gt2_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt2_eyescandataerror_out => open,
+ gt2_eyescantrigger_in => '0',
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt2_rxdata_out => gt2_rxdata_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt2_rxdisperr_out => open,
+ gt2_rxnotintable_out => gt2_rxnotintable_i,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt2_gtxrxp_in => G2_rxP,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt2_gtxrxn_in => G2_rxN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt2_rxphmonitor_out => open,
+ gt2_rxphslipmonitor_out => open,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt2_rxdfelpmreset_in => '0',
+ gt2_rxmonitorout_out => open,
+ gt2_rxmonitorsel_in => "00",
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt2_gtrxreset_in => gt2_gtrxreset_i,
+ gt2_rxpmareset_in => '0',
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt2_rxcharisk_out => gt2_rxcharisk_i,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt2_rxresetdone_out => gt2_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt2_gttxreset_in => '0',
+ gt2_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt2_txdata_in => gt2_txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt2_gtxtxn_out => G2_txN,
+ gt2_gtxtxp_out => G2_txP,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt2_txoutclkfabric_out => open,
+ gt2_txoutclkpcs_out => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt2_txcharisk_in => gt2_txcharisk_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt2_txresetdone_out => gt2_txresetdone_i,
+
+
+
+
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT3 (X1Y15)
+
+ --------------------------------- CPLL Ports -------------------------------
+ gt3_cpllfbclklost_out => open,
+ gt3_cplllock_out => open,
+ gt3_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt3_drpaddr_in => (others => '0'),
+ gt3_drpdi_in => (others => '0'),
+ gt3_drpdo_out => open,
+ gt3_drpen_in => '0',
+ gt3_drprdy_out => open,
+ gt3_drpwe_in => '0',
+ --------------------------- Digital Monitor Ports --------------------------
+ gt3_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt3_eyescanreset_in => '0',
+ gt3_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt3_eyescandataerror_out => open,
+ gt3_eyescantrigger_in => '0',
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt3_rxdata_out => gt3_rxdata_i,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt3_rxdisperr_out => open,
+ gt3_rxnotintable_out => gt3_rxnotintable_i,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt3_gtxrxp_in => G3_rxP,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt3_gtxrxn_in => G3_rxN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt3_rxphmonitor_out => open,
+ gt3_rxphslipmonitor_out => open,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt3_rxdfelpmreset_in => '0',
+ gt3_rxmonitorout_out => open,
+ gt3_rxmonitorsel_in => "00",
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt3_gtrxreset_in => gt3_gtrxreset_i,
+ gt3_rxpmareset_in => '0',
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt3_rxcharisk_out => gt3_rxcharisk_i,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt3_rxresetdone_out => gt3_rxresetdone_i,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt3_gttxreset_in => '0',
+ gt3_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt3_txdata_in => gt3_txdata_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt3_gtxtxn_out => G3_txN,
+ gt3_gtxtxp_out => G3_txP,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt3_txoutclkfabric_out => open,
+ gt3_txoutclkpcs_out => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt3_txcharisk_in => gt3_txcharisk_i,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt3_txresetdone_out => gt3_txresetdone_i,
+
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT => open,
+ GT0_QPLLOUTREFCLK_OUT => open,
+ sysclk_in => sysClk
+ );
+
+ -------------------------- User Module Resets -----------------------------
+ -- All the User Modules are held in reset till the RESETDONE goes high.
+ -- The RESETDONE is registered a couple of times on USRCLK2 and connected
+ -- to the reset of the modules
+
+process(gt0_rxusrclk2_i,gt0_rxresetdone_i,G0_LOS)
+ begin
+ if(gt0_rxresetdone_i = '0') or (G0_LOS='1') then
+ gt0_rxresetdone_r <= '0' after DLY;
+ gt0_rxresetdone_r2 <= '0' after DLY;
+ gt0_rxresetdone_r3 <= '0' after DLY;
+elsif (gt0_rxusrclk2_i'event and gt0_rxusrclk2_i = '1') then
+ gt0_rxresetdone_r <= gt0_rxresetdone_i after DLY;
+ gt0_rxresetdone_r2 <= gt0_rxresetdone_r after DLY;
+ gt0_rxresetdone_r3 <= gt0_rxresetdone_r2 after DLY;
+ end if;
+ end process;
+process(gt0_txusrclk2_i,gt0_txfsmresetdone_i,gt0_txresetdone_i)
+ begin
+ if(gt0_txfsmresetdone_i = '0') or (gt0_txresetdone_i='0') then
+ gt0_txfsmresetdone_r <= '0' after DLY;
+ gt0_txfsmresetdone_r2 <= '0' after DLY;
+elsif (gt0_txusrclk2_i'event and gt0_txusrclk2_i = '1') then
+ gt0_txfsmresetdone_r <= gt0_txfsmresetdone_i after DLY;
+ gt0_txfsmresetdone_r2 <= gt0_txfsmresetdone_r after DLY;
+ end if;
+ end process;
+
+process(gt1_rxusrclk2_i,gt1_rxresetdone_i,G1_LOS)
+ begin
+ if(gt1_rxresetdone_i = '0') or (G1_LOS='1') then
+ gt1_rxresetdone_r <= '0' after DLY;
+ gt1_rxresetdone_r2 <= '0' after DLY;
+ gt1_rxresetdone_r3 <= '0' after DLY;
+elsif (gt1_rxusrclk2_i'event and gt1_rxusrclk2_i = '1') then
+ gt1_rxresetdone_r <= gt1_rxresetdone_i after DLY;
+ gt1_rxresetdone_r2 <= gt1_rxresetdone_r after DLY;
+ gt1_rxresetdone_r3 <= gt1_rxresetdone_r2 after DLY;
+ end if;
+ end process;
+process(gt1_txusrclk2_i,gt1_txfsmresetdone_i,gt1_txresetdone_i)
+ begin
+ if(gt1_txfsmresetdone_i = '0') or (gt1_txresetdone_i='0') then
+ gt1_txfsmresetdone_r <= '0' after DLY;
+ gt1_txfsmresetdone_r2 <= '0' after DLY;
+elsif (gt1_txusrclk2_i'event and gt1_txusrclk2_i = '1') then
+ gt1_txfsmresetdone_r <= gt1_txfsmresetdone_i after DLY;
+ gt1_txfsmresetdone_r2 <= gt1_txfsmresetdone_r after DLY;
+ end if;
+ end process;
+
+process(gt2_rxusrclk2_i,gt2_rxresetdone_i,G2_LOS)
+ begin
+ if(gt2_rxresetdone_i = '0') or (G2_LOS='1') then
+ gt2_rxresetdone_r <= '0' after DLY;
+ gt2_rxresetdone_r2 <= '0' after DLY;
+ gt2_rxresetdone_r3 <= '0' after DLY;
+elsif (gt2_rxusrclk2_i'event and gt2_rxusrclk2_i = '1') then
+ gt2_rxresetdone_r <= gt2_rxresetdone_i after DLY;
+ gt2_rxresetdone_r2 <= gt2_rxresetdone_r after DLY;
+ gt2_rxresetdone_r3 <= gt2_rxresetdone_r2 after DLY;
+ end if;
+ end process;
+process(gt2_txusrclk2_i,gt2_txfsmresetdone_i,gt2_txresetdone_i)
+ begin
+ if(gt2_txfsmresetdone_i = '0') or (gt2_txresetdone_i='0') then
+ gt2_txfsmresetdone_r <= '0' after DLY;
+ gt2_txfsmresetdone_r2 <= '0' after DLY;
+elsif (gt2_txusrclk2_i'event and gt2_txusrclk2_i = '1') then
+ gt2_txfsmresetdone_r <= gt2_txfsmresetdone_i after DLY;
+ gt2_txfsmresetdone_r2 <= gt2_txfsmresetdone_r after DLY;
+ end if;
+ end process;
+
+process(gt3_rxusrclk2_i,gt3_rxresetdone_i,G3_LOS)
+ begin
+ if(gt3_rxresetdone_i = '0') or (G3_LOS='1') then
+ gt3_rxresetdone_r <= '0' after DLY;
+ gt3_rxresetdone_r2 <= '0' after DLY;
+ gt3_rxresetdone_r3 <= '0' after DLY;
+elsif (gt3_rxusrclk2_i'event and gt3_rxusrclk2_i = '1') then
+ gt3_rxresetdone_r <= gt3_rxresetdone_i after DLY;
+ gt3_rxresetdone_r2 <= gt3_rxresetdone_r after DLY;
+ gt3_rxresetdone_r3 <= gt3_rxresetdone_r2 after DLY;
+ end if;
+ end process;
+process(gt3_txusrclk2_i,gt3_txfsmresetdone_i,gt0_txresetdone_i)
+ begin
+ if (gt3_txfsmresetdone_i = '0') or (gt3_txresetdone_i='0') then
+ gt3_txfsmresetdone_r <= '0' after DLY;
+ gt3_txfsmresetdone_r2 <= '0' after DLY;
+elsif (gt3_txusrclk2_i'event and gt3_txusrclk2_i = '1') then
+ gt3_txfsmresetdone_r <= gt3_txfsmresetdone_i after DLY;
+ gt3_txfsmresetdone_r2 <= gt3_txfsmresetdone_r after DLY;
+ end if;
+ end process;
+
+
+
+G0_rxLocked <= gt0_rxresetdone_r3;
+G1_rxLocked <= gt1_rxresetdone_r3;
+G2_rxLocked <= gt2_rxresetdone_r3;
+G3_rxLocked <= gt3_rxresetdone_r3;
+G0_rxLocked <= gt0_rxresetdone_r3;
+G0_txLocked <= gt0_txfsmresetdone_r2;
+G1_txLocked <= gt1_txfsmresetdone_r2;
+G2_txLocked <= gt2_txfsmresetdone_r2;
+G3_txLocked <= gt3_txfsmresetdone_r2;
+
+gt0_gtrxreset_i <= G0_LOS;
+gt1_gtrxreset_i <= G1_LOS;
+gt2_gtrxreset_i <= G2_LOS;
+gt3_gtrxreset_i <= G3_LOS;
+
+LEDs_link_ok(0) <= '1' when (gt0_rxresetdone_r3='1') and (gt0_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(1) <= '1' when (gt0_rxresetdone_r3='1') and (gt1_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(2) <= '1' when (gt0_rxresetdone_r3='1') and (gt2_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(3) <= '1' when (gt0_rxresetdone_r3='1') and (gt3_txfsmresetdone_r2='1') else '0';
+
+LEDs_rx <= (others => '0');
+LEDs_tx <= (others => '0');
+
+
+end Behavioral;
+
+
+
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- dummy unit
+entity spi_dpram_32_to_8 is
+ port (
+ DataInA: in std_logic_vector(31 downto 0);
+ DataInB: in std_logic_vector(7 downto 0);
+ AddressA: in std_logic_vector(5 downto 0);
+ AddressB: in std_logic_vector(7 downto 0);
+ ClockA: in std_logic;
+ ClockB: in std_logic;
+ ClockEnA: in std_logic;
+ ClockEnB: in std_logic;
+ WrA: in std_logic;
+ WrB: in std_logic;
+ ResetA: in std_logic;
+ ResetB: in std_logic;
+ QA: out std_logic_vector(31 downto 0);
+ QB: out std_logic_vector(7 downto 0));
+end spi_dpram_32_to_8;
+
+architecture Structure of spi_dpram_32_to_8 is
+
+begin
+ QA <= (others => '0');
+ QB <= (others => '0');
+
+
+end Structure;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 21-05-2015
+-- Module Name: sync_bit
+-- Description: Synchronization for 1 bit cross clock signal
+-- Modifications:
+----------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+----------------------------------------------------------------------------------
+-- sync_bit
+-- Synchronize a signal to a different clock by passing through several registers.
+-- This is the Xilinx version with Xilinx specific registers and attributes
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock to synchronize to
+-- data_in : signal from different clock
+--
+-- Outputs:
+-- data_out : synchronized signal
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+
+entity sync_bit is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+end sync_bit;
+
+
+architecture structural of sync_bit is
+
+ signal dsync1 : std_logic;
+ signal dsync2 : std_logic;
+
+ -- These attributes will stop timing errors being reported in back annotated
+ -- SDF simulation.
+ attribute ASYNC_REG : string;
+ attribute ASYNC_REG of dsync_reg1 : label is "true";
+ attribute ASYNC_REG of dsync_reg2 : label is "true";
+ attribute ASYNC_REG of dsync_reg3 : label is "true";
+
+ -- These attributes will stop XST translating the desired flip-flops into an
+ -- SRL based shift register.
+ attribute shreg_extract : string;
+ attribute shreg_extract of dsync_reg1 : label is "no";
+ attribute shreg_extract of dsync_reg2 : label is "no";
+ attribute shreg_extract of dsync_reg3 : label is "no";
+
+
+begin
+
+ dsync_reg1 : FD
+ port map (
+ C => clock,
+ D => data_in,
+ Q => dsync1
+ );
+
+ dsync_reg2 : FD
+ port map (
+ C => clock,
+ D => dsync1,
+ Q => dsync2
+ );
+
+ dsync_reg3 : FD
+ port map (
+ C => clock,
+ D => dsync2,
+ Q => data_out
+ );
+
+
+
+end structural;
+
+
--- /dev/null
+library ieee;
+
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_signed.ALL;
+USE IEEE.numeric_std.ALL;
+use work.trb_net_std.all;
+
+entity trb_net16_fifo is
+ generic (
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ USE_DATA_COUNT : integer range 0 to 1 := c_NO;
+ DEPTH : integer := 6
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);
+ WRITE_ENABLE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
+ READ_ENABLE_IN : in std_logic;
+ DATA_COUNT_OUT : out std_logic_vector(10 downto 0);
+ FULL_OUT : out std_logic;
+ EMPTY_OUT : out std_logic
+ );
+end entity;
+
+architecture arch_trb_net16_fifo of trb_net16_fifo is
+-- attribute box_type: string;
+
+ component xilinx_fifo_18x1k
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+ end component;
+-- attribute box_type of xilinx_fifo_18x1k : component is "black_box";
+
+
+ component xilinx_fifo_18x16
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+ end component;
+-- attribute box_type of xilinx_fifo_18x16 : component is "black_box";
+
+ component xilinx_fifo_18x32
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic
+ );
+ end component;
+-- attribute box_type of xilinx_fifo_18x32 : component is "black_box";
+
+ component xilinx_fifo_18x64
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic
+ );
+ end component;
+-- attribute box_type of xilinx_fifo_18x64 : component is "black_box";
+
+ component xilinx_fifo_lut
+ generic (
+ WIDTH : integer := 18;
+ DEPTH : integer := 3
+ );
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic
+ );
+ end component;
+
+ component xilinx_fifo_18x1k_datacount is
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(9 downto 0);
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic
+ );
+ end component;
+-- attribute box_type of xilinx_fifo_18x1k_datacount : component is "black_box";
+
+ signal din, dout : std_logic_vector(c_DATA_WIDTH + 2-1 downto 0);
+ signal data_counter : std_logic_vector(9 downto 0);
+
+begin
+ din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN;
+ din(c_DATA_WIDTH + 2 -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN;
+ DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 2 - 1 downto c_DATA_WIDTH);
+ DATA_COUNT_OUT <= '0' & data_counter;
+
+ gen_FIFO6_Count : if DEPTH = 6 and USE_DATA_COUNT = 1 generate
+ fifo:xilinx_fifo_18x1k_datacount
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ rst => RESET,
+ data_count => data_counter,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+
+ end generate;
+
+ gen_FIFO6 : if DEPTH = 6 and USE_DATA_COUNT = 0 generate
+ fifo:xilinx_fifo_18x1k
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ rst => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+
+ gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate
+ gen_FIFO_LUT : if DEPTH < 6 generate
+ fifo:xilinx_fifo_lut
+ generic map (
+ WIDTH => c_DATA_WIDTH + 2,
+ DEPTH => ((DEPTH+3))
+ )
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+ end generate;
+
+ gen_XILINX_CORES : if USE_VENDOR_CORES = c_YES generate
+ gen_FIFO1 : if DEPTH = 1 generate
+ fifo:xilinx_fifo_18x16
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ rst => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+
+ gen_FIFO2 : if DEPTH = 2 generate
+ fifo:xilinx_fifo_18x32
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+
+
+ gen_FIFO3 : if DEPTH = 3 generate
+ fifo:xilinx_fifo_18x64
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+ end generate;
+
+
+end architecture;
+
+
--- /dev/null
+library ieee;
+
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_signed.ALL;
+USE IEEE.numeric_std.ALL;
+use work.trb_net_std.all;
+
+entity trb_net16_fifo is
+ generic (
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ USE_DATA_COUNT : integer range 0 to 1 := c_NO;
+ DEPTH : integer := 6
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);
+ WRITE_ENABLE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);
+ READ_ENABLE_IN : in std_logic;
+ DATA_COUNT_OUT : out std_logic_vector(10 downto 0);
+ FULL_OUT : out std_logic;
+ EMPTY_OUT : out std_logic
+ );
+end entity;
+
+architecture arch_trb_net16_fifo of trb_net16_fifo is
+-- attribute box_type: string;
+
+ component xilinx_fifo_18x1k
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+ end component;
+-- attribute box_type of xilinx_fifo_18x1k : component is "black_box";
+
+
+ component xilinx_fifo_18x16
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
+ end component;
+-- attribute box_type of xilinx_fifo_18x16 : component is "black_box";
+
+ component xilinx_fifo_18x32
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic
+ );
+ end component;
+-- attribute box_type of xilinx_fifo_18x32 : component is "black_box";
+
+ component xilinx_fifo_18x64
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic
+ );
+ end component;
+-- attribute box_type of xilinx_fifo_18x64 : component is "black_box";
+
+ component xilinx_fifo_lut
+ generic (
+ WIDTH : integer := 18;
+ DEPTH : integer := 3
+ );
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic
+ );
+ end component;
+
+ component xilinx_fifo_18x1k_datacount is
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(9 downto 0);
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic
+ );
+ end component;
+-- attribute box_type of xilinx_fifo_18x1k_datacount : component is "black_box";
+
+ signal din, dout : std_logic_vector(c_DATA_WIDTH + 2-1 downto 0);
+ signal data_counter : std_logic_vector(9 downto 0);
+
+begin
+ din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN;
+ din(c_DATA_WIDTH + 2 -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN;
+ DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0);
+ PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 2 - 1 downto c_DATA_WIDTH);
+ DATA_COUNT_OUT <= '0' & data_counter;
+
+ gen_FIFO6_Count : if DEPTH = 6 and USE_DATA_COUNT = 1 generate
+ fifo:xilinx_fifo_18x1k_datacount
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ rst => RESET,
+ data_count => data_counter,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+
+ end generate;
+
+ gen_FIFO6 : if DEPTH = 6 and USE_DATA_COUNT = 0 generate
+ fifo:xilinx_fifo_18x1k
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ rst => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+
+ gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate
+ gen_FIFO_LUT : if DEPTH < 6 generate
+ fifo:xilinx_fifo_lut
+ generic map (
+ WIDTH => c_DATA_WIDTH + 2,
+ DEPTH => ((DEPTH+3))
+ )
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+ end generate;
+
+ gen_XILINX_CORES : if USE_VENDOR_CORES = c_YES generate
+ gen_FIFO1 : if DEPTH = 1 generate
+ fifo:xilinx_fifo_18x16
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ rst => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+
+ gen_FIFO2 : if DEPTH = 2 generate
+ fifo:xilinx_fifo_18x32
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+
+
+ gen_FIFO3 : if DEPTH = 3 generate
+ fifo:xilinx_fifo_18x64
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ data_counter <= (others => '0');
+ end generate;
+ end generate;
+
+
+end architecture;
+
+
--- /dev/null
+--Media interface for Xilinx Kintex7 using SFP at 2GHz
+--One channel is used.
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+--use work.med_sync_define.all;
+
+entity trb_net16_med_gtx2_kintex7_sfp is
+ port(
+ CLK : in std_logic; -- SerDes clock
+ SYSCLK : in std_logic; -- fabric clock = 100MHz
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ REFCLK2CORE_OUT : out std_logic;
+ CLK_RX_HALF_OUT : out std_logic;
+ CLK_RX_FULL_OUT : out std_logic;
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic;
+ SD_REFCLK_N_IN : in std_logic;
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic; -- SFP disable
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+end entity;
+
+architecture trb_net16_med_gtx2_kintex7_sfp_arch of trb_net16_med_gtx2_kintex7_sfp is
+
+component GTX_trb3_2gb_wrapper
+generic
+(
+ -- Simulation attributes
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to TRUE to speed up sim reset
+ STABLE_CLOCK_PERIOD : integer := 10
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ SYSCLK_IN : in std_logic
+);
+end component;
+
+
+ signal refck2core : std_logic;
+ --serdes connections
+ signal tx_data : std_logic_vector(15 downto 0);
+ signal tx_k : std_logic_vector(1 downto 0);
+ signal rx_data : std_logic_vector(15 downto 0); -- delayed signals
+ signal rx_k : std_logic_vector(1 downto 0); -- delayed signals
+ signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP
+ signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP
+ signal link_ok : std_logic;
+ signal ff_txhalfclk : std_logic;
+ signal ff_rxhalfclk : std_logic;
+ signal ff_rxfullclk : std_logic;
+ --rx fifo signals
+ signal fifo_rx_rd_en : std_logic;
+ signal fifo_rx_wr_en : std_logic;
+ signal fifo_rx_reset : std_logic;
+ signal fifo_rx_din : std_logic_vector(17 downto 0);
+ signal fifo_rx_dout : std_logic_vector(17 downto 0);
+ signal fifo_rx_full : std_logic;
+ signal fifo_rx_empty : std_logic;
+ --tx fifo signals
+ signal fifo_tx_rd_en : std_logic;
+ signal fifo_tx_wr_en : std_logic;
+ signal fifo_tx_reset : std_logic;
+ signal fifo_tx_din : std_logic_vector(17 downto 0);
+ signal fifo_tx_dout : std_logic_vector(17 downto 0);
+ signal fifo_tx_full : std_logic;
+ signal fifo_tx_empty : std_logic;
+ signal fifo_tx_almost_full : std_logic;
+ --rx path
+ signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal buf_med_dataready_out : std_logic;
+ signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal last_rx : std_logic_vector(8 downto 0);
+ signal last_fifo_rx_empty : std_logic;
+ --tx path
+ signal last_fifo_tx_empty : std_logic;
+ --link status
+ signal rx_k_q : std_logic_vector(1 downto 0);
+
+ signal quad_rst : std_logic;
+ signal lane_rst : std_logic;
+ signal tx_allow : std_logic;
+ signal tx_allow0 : std_logic;
+ signal rx_allow : std_logic;
+ signal tx_allow_qtx : std_logic;
+
+ signal rx_allow_q : std_logic; -- clock domain changed signal
+ signal tx_allow_q : std_logic;
+ signal swap_bytes : std_logic;
+ signal buf_stat_debug : std_logic_vector(31 downto 0);
+
+ -- status inputs from SFP
+ signal sfp_prsnt_n : std_logic; -- synchronized input signals
+ signal sfp_los : std_logic; -- synchronized input signals
+
+ signal buf_STAT_OP : std_logic_vector(15 downto 0);
+
+ signal led_counter : unsigned(16 downto 0);
+ signal rx_led : std_logic;
+ signal tx_led : std_logic;
+
+
+ signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
+ signal first_idle : std_logic; -- tag the first IDLE2 after data
+
+ signal reset_word_cnt : unsigned(4 downto 0);
+ signal make_trbnet_reset : std_logic;
+ signal make_trbnet_reset_q : std_logic;
+ signal send_reset_words : std_logic;
+ signal send_reset_words_q : std_logic;
+ signal send_reset_in : std_logic;
+ signal send_reset_in_qtx : std_logic;
+ signal reset_i : std_logic;
+ signal reset_i_rx : std_logic;
+ signal pwr_up : std_logic;
+ signal clear_S : std_logic;
+
+ signal clk_tx : std_logic;
+ signal clk_rx : std_logic;
+
+ signal gt0_txfsmresetdone_i : std_logic;
+ signal gt0_rxfsmresetdone_i : std_logic;
+ signal gt0_txresetdone_i : std_logic;
+
+ signal gt0_rxnotintable_S : std_logic_vector(1 downto 0);
+ signal link_rx_error_S : std_logic;
+ signal link_tx_error_S : std_logic;
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of tx_data : signal is "true";
+-- attribute mark_debug of tx_k : signal is "true";
+-- attribute mark_debug of rx_data : signal is "true";
+-- attribute mark_debug of rx_k : signal is "true";
+-- attribute mark_debug of quad_rst : signal is "true";
+
+-- attribute mark_debug of link_ok : signal is "true";
+-- attribute mark_debug of rx_k_q : signal is "true";
+-- attribute mark_debug of sfp_prsnt_n : signal is "true";
+-- attribute mark_debug of tx_allow : signal is "true";
+-- attribute mark_debug of rx_allow : signal is "true";
+-- attribute mark_debug of swap_bytes : signal is "true";
+-- attribute mark_debug of gt0_rxnotintable_S : signal is "true";
+-- attribute mark_debug of link_rx_error_S : signal is "true";
+-- attribute mark_debug of link_tx_error_S : signal is "true";
+-- attribute mark_debug of ctrl_op : signal is "true";
+-- attribute mark_debug of buf_stat_debug : signal is "true";
+
+-- attribute mark_debug of make_trbnet_reset : signal is "true";
+-- attribute mark_debug of send_reset_in : signal is "true";
+-- attribute mark_debug of reset_i_rx : signal is "true";
+-- attribute mark_debug of gt0_txfsmresetdone_i : signal is "true";
+-- attribute mark_debug of gt0_rxfsmresetdone_i : signal is "true";
+-- attribute mark_debug of gt0_txresetdone_i : signal is "true";
+
+ begin
+
+--------------------------------------------------------------------------
+-- Select proper clock configuration
+--------------------------------------------------------------------------
+ clk_rx <= ff_rxhalfclk;
+
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+ clear_S <= clear;
+
+
+ PROC_RESET : process(SYSCLK)
+ begin
+ if rising_edge(SYSCLK) then
+ reset_i <= RESET;
+ send_reset_in <= ctrl_op(15);
+ pwr_up <= '1'; --not CTRL_OP(i*16+14);
+ end if;
+ end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+ generic map(
+ DEPTH => 3,
+ WIDTH => 2
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => sd_prsnt_n_in,
+ D_IN(1) => sd_los_in,
+ CLK0 => SYSCLK,
+ CLK1 => SYSCLK,
+ D_OUT(0) => sfp_prsnt_n,
+ D_OUT(1) => sfp_los
+ );
+
+
+THE_RX_K_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 4
+ )
+ port map(
+ RESET => reset_i,
+ D_IN(1 downto 0) => comb_rx_k,
+ D_IN(2) => send_reset_words,
+ D_IN(3) => make_trbnet_reset,
+ CLK0 => clk_rx, -- CHANGED
+ CLK1 => SYSCLK,
+ D_OUT(1 downto 0) => rx_k_q,
+ D_OUT(2) => send_reset_words_q,
+ D_OUT(3) => make_trbnet_reset_q
+ );
+
+THE_RX_DATA_DELAY: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 16
+ )
+ port map(
+ RESET => reset_i,
+ D_IN => comb_rx_data,
+ CLK0 => clk_rx,
+ CLK1 => clk_rx,
+ D_OUT => rx_data
+ );
+
+THE_RX_K_DELAY: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => reset_i,
+ D_IN => comb_rx_k,
+ CLK0 => clk_rx,
+ CLK1 => clk_rx,
+ D_OUT => rx_k
+ );
+
+THE_RX_RESET: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 1
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => reset_i,
+ CLK0 => clk_rx,
+ CLK1 => clk_rx,
+ D_OUT(0) => reset_i_rx
+ );
+
+-- Delay for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => reset_i,
+ D_IN(0) => rx_allow,
+ D_IN(1) => tx_allow,
+ CLK0 => SYSCLK,
+ CLK1 => SYSCLK,
+ D_OUT(0) => rx_allow_q,
+ D_OUT(1) => tx_allow_q
+ );
+
+THE_TX_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 2
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => send_reset_in,
+ D_IN(1) => tx_allow,
+ CLK0 => clk_tx,
+ CLK1 => clk_tx,
+ D_OUT(0) => send_reset_in_qtx,
+ D_OUT(1) => tx_allow_qtx
+ );
+
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+ generic map (
+ CHECK_FOR_CV => c_YES,
+ HIGHSPEED_STARTUP => c_YES
+ )
+ port map(
+ SYSCLK => SYSCLK,
+ RESET => reset_i,
+ CLEAR => clear_S,
+ SFP_MISSING_IN => sfp_prsnt_n,
+ SFP_LOS_IN => sfp_los,
+ SD_LINK_OK_IN => link_ok, -- apparently not used
+ SD_LOS_IN => '0', -- apparently not used
+ SD_TXCLK_BAD_IN => link_tx_error_S,
+ SD_RXCLK_BAD_IN => link_rx_error_S,
+ SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+ SD_ALIGNMENT_IN => rx_k_q,
+ SD_CV_IN => gt0_rxnotintable_S,
+ FULL_RESET_OUT => quad_rst,
+ LANE_RESET_OUT => open, -- apparently not used
+ TX_ALLOW_OUT => tx_allow,
+ RX_ALLOW_OUT => rx_allow,
+ SWAP_BYTES_OUT => swap_bytes,
+ STAT_OP => buf_stat_op,
+ CTRL_OP => ctrl_op,
+ STAT_DEBUG => buf_stat_debug
+ );
+sd_txdis_out <= quad_rst or reset_i;
+link_rx_error_S <= '1' when (gt0_rxfsmresetdone_i='0') else '0'; -- loss of lock
+link_tx_error_S <= '1' when (gt0_txresetdone_i='0') or (gt0_txfsmresetdone_i='0') else '0';
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+-- SerDes clock output to FPGA fabric
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
+THE_SERDES: GTX_trb3_2gb_wrapper port map
+ (
+ soft_reset_tx_in => quad_rst,
+ soft_reset_rx_in => quad_rst,
+ DONT_RESET_ON_DATA_ERROR_IN => '0',
+ Q2_CLK0_GTREFCLK_PAD_N_IN => SD_REFCLK_N_IN,
+ Q2_CLK0_GTREFCLK_PAD_P_IN => SD_REFCLK_P_IN,
+ GT0_TX_FSM_RESET_DONE_OUT => gt0_txfsmresetdone_i,
+ GT0_RX_FSM_RESET_DONE_OUT => gt0_rxfsmresetdone_i,
+ GT0_DATA_VALID_IN => '1', -- tx_allow,
+
+ GT0_TXUSRCLK_OUT => open,
+ GT0_TXUSRCLK2_OUT => clk_tx, -- clock for tx_data (100MHz)
+ GT0_RXUSRCLK_OUT => ff_rxfullclk,
+ GT0_RXUSRCLK2_OUT => ff_rxhalfclk, -- clock for rx_data (100MHz)
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y10)
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => open,
+ gt0_cplllock_out => open,
+ gt0_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => (others => '0'),
+ gt0_drpdi_in => (others => '0'),
+ gt0_drpdo_out => open,
+ gt0_drpen_in => '0',
+ gt0_drprdy_out => open,
+ gt0_drpwe_in => '0',
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => '0',
+ gt0_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => open,
+ gt0_eyescantrigger_in => '0',
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => comb_rx_data,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => open,
+ gt0_rxnotintable_out => gt0_rxnotintable_S,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => sd_rxd_p_in,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => sd_rxd_n_in,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => open,
+ gt0_rxphslipmonitor_out => open,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => '0',
+ gt0_rxmonitorout_out => open,
+ gt0_rxmonitorsel_in => "00",
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => '0',
+ gt0_rxpmareset_in => '0',
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => comb_rx_k,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => link_ok,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => '0',
+ gt0_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => tx_data,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => sd_txd_n_out,
+ gt0_gtxtxp_out => sd_txd_p_out,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out => open,
+ gt0_txoutclkpcs_out => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => tx_k,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_i,
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT => open,
+ GT0_QPLLOUTREFCLK_OUT => open,
+ SYSCLK_IN => SYSCLK
+ );
+
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+port map( read_clock_in => SYSCLK,
+ write_clock_in => clk_rx,
+ read_enable_in => fifo_rx_rd_en,
+ write_enable_in => fifo_rx_wr_en,
+ fifo_gsr_in => fifo_rx_reset,
+ write_data_in => fifo_rx_din,
+ read_data_out => fifo_rx_dout,
+ full_out => fifo_rx_full,
+ empty_out => fifo_rx_empty
+ );
+
+fifo_rx_reset <= reset_i or not rx_allow_q;
+fifo_rx_rd_en <= not fifo_rx_empty;
+
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+THE_BYTE_SWAP_PROC: process(clk_rx)
+ begin
+ if rising_edge(clk_rx) then
+ last_rx <= rx_k(1) & rx_data(15 downto 8);
+ if( swap_bytes = '0' ) then
+ fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
+ fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok;
+ else
+ fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
+ fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok;
+ end if;
+ end if;
+ end process THE_BYTE_SWAP_PROC;
+
+buf_med_data_out <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out <= rx_counter;
+med_read_out <= tx_allow_q and not fifo_tx_almost_full;
+
+
+THE_CNT_RESET_PROC : process(clk_rx)
+ begin
+ if rising_edge(clk_rx) then
+ if reset_i_rx = '1' then
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ reset_word_cnt <= (others => '0');
+ else
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ if fifo_rx_din = "11" & x"FEFE" then
+ if reset_word_cnt(4) = '0' then
+ reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
+ else
+ send_reset_words <= '1';
+ end if;
+ else
+ reset_word_cnt <= (others => '0');
+ make_trbnet_reset <= reset_word_cnt(4);
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+THE_SYNC_PROC: process(SYSCLK)
+ begin
+ if rising_edge(SYSCLK) then
+ med_dataready_out <= buf_med_dataready_out;
+ med_data_out <= buf_med_data_out;
+ med_packet_num_out <= buf_med_packet_num_out;
+ if reset_i = '1' then
+ med_dataready_out <= '0';
+ end if;
+ end if;
+ end process;
+
+
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process( SYSCLK )
+ begin
+ if( rising_edge(SYSCLK) ) then
+ last_fifo_rx_empty <= fifo_rx_empty;
+ if reset_i = '1' or rx_allow_q = '0' then
+ rx_counter <= c_H0;
+ else
+ if( buf_med_dataready_out = '1' ) then
+ if( rx_counter = c_max_word_number ) then
+ rx_counter <= (others => '0');
+ else
+ rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+ port map( read_clock_in => clk_tx,
+ write_clock_in => SYSCLK,
+ read_enable_in => fifo_tx_rd_en,
+ write_enable_in => fifo_tx_wr_en,
+ fifo_gsr_in => fifo_tx_reset,
+ write_data_in => fifo_tx_din,
+ read_data_out => fifo_tx_dout,
+ full_out => fifo_tx_full,
+ empty_out => fifo_tx_empty,
+ almost_full_out => fifo_tx_almost_full
+ );
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+fifo_tx_rd_en <= tx_allow_qtx;
+
+
+THE_SERDES_INPUT_PROC: process( clk_tx )
+ begin
+ if( rising_edge(clk_tx) ) then
+ last_fifo_tx_empty <= fifo_tx_empty;
+ first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
+ if send_reset_in = '1' then
+ tx_data <= x"FEFE";
+ tx_k <= "11";
+ elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
+ tx_data <= x"50bc";
+ tx_k <= "01";
+ tx_correct <= first_idle & '0'; -- ???????????
+ else
+ tx_data <= fifo_tx_dout(15 downto 0);
+ tx_k <= "00";
+ tx_correct <= "00"; -- ???????????
+ end if;
+ end if;
+ end process THE_SERDES_INPUT_PROC;
+
+
+
+--Generate LED signals
+----------------------
+process( SYSCLK )
+ begin
+ if rising_edge(SYSCLK) then
+ led_counter <= led_counter + to_unsigned(1,1);
+
+ if buf_med_dataready_out = '1' then
+ rx_led <= '1';
+ elsif led_counter = 0 then
+ rx_led <= '0';
+ end if;
+
+ if tx_k(0) = '0' then
+ tx_led <= '1';
+ elsif led_counter = 0 then
+ tx_led <= '0';
+ end if;
+
+ end if;
+ end process;
+
+stat_op(15) <= send_reset_words_q;
+stat_op(14) <= buf_stat_op(14);
+stat_op(13) <= make_trbnet_reset_q;
+stat_op(12) <= '0';
+stat_op(11) <= tx_led; --tx led
+stat_op(10) <= rx_led; --rx led
+stat_op(9 downto 0) <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(15 downto 0) <= rx_data;
+stat_debug(17 downto 16) <= rx_k;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24) <= fifo_rx_rd_en;
+stat_debug(25) <= fifo_rx_wr_en;
+stat_debug(26) <= fifo_rx_reset;
+stat_debug(27) <= fifo_rx_empty;
+stat_debug(28) <= fifo_rx_full;
+stat_debug(29) <= last_rx(8);
+stat_debug(30) <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42) <= SYSCLK;
+stat_debug(43) <= SYSCLK;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+end architecture;
\ No newline at end of file
--- /dev/null
+--Media interface for Xilinx Kintex7 using SFP at 2GHz
+--One channel is used.
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+--use work.med_sync_define.all;
+
+entity trb_net16_med_sync_gtx2_kintex7_sfp is
+ port(
+ CLK : in std_logic; -- SerDes clock
+ SYSCLK : in std_logic; -- fabric clock = 100MHz
+ SODA_clock : in std_logic; --//try
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ disable_GTX_reset : in std_logic;
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ REFCLK2CORE_OUT : out std_logic;
+ CLK_RX_HALF_OUT : out std_logic;
+ CLK_RX_FULL_OUT : out std_logic;
+ --SFP Connection
+ SODA_RXD_P_IN : in std_logic;
+ SODA_RXD_N_IN : in std_logic;
+ SODA_TXD_P_OUT : out std_logic;
+ SODA_TXD_N_OUT : out std_logic;
+ SODA_REFCLK_P_IN : in std_logic;
+ SODA_REFCLK_N_IN : in std_logic;
+ SODA_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SODA_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SODA_TXDIS_OUT : out std_logic; -- SFP disable
+ SODA_DLM_IN : in std_logic;
+ SODA_DLM_WORD_IN : in std_logic_vector(7 downto 0);
+ SODA_DLM_OUT : out std_logic;
+ SODA_DLM_WORD_OUT : out std_logic_vector(7 downto 0);
+ SODA_CLOCK_OUT : out std_logic; -- 200MHz
+ SODA_LOCKED_OUT : out std_logic;
+
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+end entity;
+
+architecture trb_net16_med_sync_gtx2_kintex7_sfp_arch of trb_net16_med_sync_gtx2_kintex7_sfp is
+
+component GTX_trb3_sync_2gb_support
+generic
+(
+ -- Simulation attributes
+ EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to TRUE to speed up sim reset
+ STABLE_CLOCK_PERIOD : integer := 10
+);
+port
+(
+ SOFT_RESET_TX_IN : in std_logic;
+ SOFT_RESET_RX_IN : in std_logic;
+ DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
+ Q2_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
+
+ GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
+ GT0_DATA_VALID_IN : in std_logic;
+ GT0_TX_MMCM_LOCK_OUT : out std_logic;
+
+ GT0_TXUSRCLK_OUT : out std_logic;
+ GT0_TXUSRCLK2_OUT : out std_logic;
+ GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified
+ GT0_RXUSRCLK_OUT : out std_logic;
+ GT0_RXUSRCLK2_OUT : out std_logic;
+
+ --_________________________________________________________________________
+ --GT0 (X1Y10)
+ --____________________________CHANNEL PORTS________________________________
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out : out std_logic;
+ gt0_cplllock_out : out std_logic;
+ gt0_cpllreset_in : in std_logic;
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in : in std_logic_vector(8 downto 0);
+ gt0_drpdi_in : in std_logic_vector(15 downto 0);
+ gt0_drpdo_out : out std_logic_vector(15 downto 0);
+ gt0_drpen_in : in std_logic;
+ gt0_drprdy_out : out std_logic;
+ gt0_drpwe_in : in std_logic;
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out : out std_logic_vector(7 downto 0);
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in : in std_logic;
+ gt0_rxuserrdy_in : in std_logic;
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out : out std_logic;
+ gt0_eyescantrigger_in : in std_logic;
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN : in std_logic; --// Modified
+ GT0_RXCDRLOCK_OUT : out std_logic; --// Modified
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out : out std_logic_vector(15 downto 0);
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
+ gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in : in std_logic;
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in : in std_logic;
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
+ gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in : in std_logic;
+ gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
+ gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in : in std_logic;
+ gt0_rxpmareset_in : in std_logic;
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out : out std_logic_vector(1 downto 0);
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out : out std_logic;
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in : in std_logic;
+ gt0_txuserrdy_in : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in : in std_logic_vector(15 downto 0);
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out : out std_logic;
+ gt0_gtxtxp_out : out std_logic;
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out : out std_logic;
+ gt0_txoutclkpcs_out : out std_logic;
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in : in std_logic_vector(1 downto 0);
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out : out std_logic;
+
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT : out std_logic;
+ GT0_QPLLOUTREFCLK_OUT : out std_logic;
+ sysclk_in : in std_logic
+);
+end component;
+
+component DC_data8to16 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ kchar_in : in std_logic;
+ clock_out : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ kchar_out : out std_logic_vector(1 downto 0)
+ );
+end component;
+
+component DC_data16to8 is
+ port (
+ clock_in : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ kchar_in : in std_logic_vector(1 downto 0);
+ notintable_in : in std_logic_vector(1 downto 0);
+ clock_out : out std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ kchar_out : out std_logic;
+ notintable_out : out std_logic
+ );
+end component;
+
+component DC_SODA_clockcrossing is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ DLM_in : in std_logic;
+ DLM_WORD_in : in std_logic_vector(7 downto 0);
+ DLM_out : out std_logic;
+ DLM_WORD_out : out std_logic_vector(7 downto 0);
+ error : out std_logic
+ );
+end component;
+
+component DC_rxBitLock is
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ resetDone : in std_logic;
+ lossOfSync : in std_logic;
+ rxPllLocked : in std_logic;
+ rxReset : out std_logic;
+ fsmStatus : out std_logic_vector (1 downto 0)
+ );
+end component;
+
+component HUB_8to16_SODA is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ char_is_k : in std_logic;
+ fifo_data : out std_logic_vector(17 downto 0);
+ fifo_full : in std_logic;
+ fifo_write : out std_logic;
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ error : out std_logic
+ );
+end component;
+
+component HUB_16to8_SODA is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ fifo_data : in std_logic_vector(15 downto 0);
+ fifo_empty : in std_logic;
+ fifo_read : out std_logic;
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ char_is_k : out std_logic;
+ error : out std_logic
+ );
+end component;
+
+component DC_posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+component sync_bit is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic
+ );
+end component;
+
+signal refck2core : std_logic;
+--serdes connections
+signal txData16_S : std_logic_vector(15 downto 0);
+signal txCharIsK16_S : std_logic_vector(1 downto 0);
+signal rxData16_S : std_logic_vector(15 downto 0);
+signal rxCharIsK16_S : std_logic_vector(1 downto 0);
+signal rxNotInTable16_S : std_logic_vector(1 downto 0);
+signal rxNotInTable16_q : std_logic_vector(1 downto 0);
+signal txData8_S : std_logic_vector(7 downto 0);
+signal txCharIsK8_S : std_logic;
+signal rxData8_S : std_logic_vector(7 downto 0);
+signal rxCharIsK8_S : std_logic;
+signal SODA_DLM_WORD_OUT_S : std_logic_vector(7 downto 0);
+signal SODA_DLM_OUT_S : std_logic;
+
+signal ff_txhalfclk : std_logic;
+signal ff_txfullclk : std_logic;
+signal ff_rxhalfclk : std_logic;
+signal ff_rxfullclk : std_logic;
+--rx fifo signals
+signal fifo_rx_rd_en : std_logic;
+signal fifo_rx_wr_en : std_logic;
+signal fifo_rx_reset : std_logic;
+signal fifo_rx_din : std_logic_vector(17 downto 0);
+signal fifo_rx_dout : std_logic_vector(17 downto 0);
+signal fifo_rx_full : std_logic;
+signal fifo_rx_empty : std_logic;
+--tx fifo signals
+signal fifo_tx_rd_en : std_logic;
+signal fifo_tx_wr_en : std_logic;
+signal fifo_tx_reset : std_logic;
+signal fifo_tx_din : std_logic_vector(17 downto 0);
+signal fifo_tx_dout : std_logic_vector(17 downto 0);
+signal fifo_tx_full : std_logic;
+signal fifo_tx_empty : std_logic;
+signal fifo_tx_almost_full : std_logic;
+--rx path
+signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal buf_med_dataready_out : std_logic;
+signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal last_fifo_rx_empty : std_logic;
+--link status
+signal quad_rst : std_logic;
+signal quad_rst_S : std_logic;
+
+signal tx_allow : std_logic;
+signal rx_allow : std_logic;
+
+signal rx_allow_q : std_logic;
+signal tx_allow_q : std_logic;
+signal buf_stat_debug : std_logic_vector(31 downto 0);
+
+signal sfp_prsnt_n : std_logic; -- synchronized input signals
+signal sfp_los : std_logic; -- synchronized input signals
+signal buf_STAT_OP : std_logic_vector(15 downto 0);
+
+signal pllLkDet_S : std_logic;
+signal rxResetBitLock_S : std_logic :='0';
+signal sync_rxResetBitLock_S : std_logic :='0';
+signal prev_rxResetBitLock_S : std_logic :='0';
+signal rxLossOfSync1_S : std_logic;
+signal fsmStatus_S : std_logic_vector(1 downto 0);
+signal rxPLLwrapper_reset_S : std_logic :='0';
+signal rxResetBitLock_pulse_S : std_logic :='0';
+
+signal rxReset_S : std_logic :='0';
+signal resetDone_S : std_logic :='0';
+signal rxCDRlock_S : std_logic :='0';
+signal CDR_reset_S : std_logic :='0';
+signal rxLocked0_S : std_logic;
+signal rxLocked1_S : std_logic;
+signal rxLocked2_S : std_logic;
+
+signal SODA_DLM_IN_S : std_logic;
+signal SODA_DLM_WORD_IN_S : std_logic_vector(7 downto 0);
+
+
+signal drpaddr_in_S : std_logic_vector(8 downto 0);
+signal drpdi_in_S : std_logic_vector(15 downto 0);
+signal drpdo_out_S : std_logic_vector(15 downto 0);
+signal drpen_in_S : std_logic;
+signal drprdy_out_S : std_logic;
+signal drpwe_in_S : std_logic;
+
+signal comma_align_latency_S : std_logic_vector(6 downto 0);
+signal comma_align_latency0_valid_S : std_logic;
+signal comma_align_latency_valid_S : std_logic;
+type drp_state_type is (initting, running, reading);
+signal drp_state_S : drp_state_type := initting;
+
+signal led_counter : unsigned(16 downto 0);
+signal rx_led : std_logic;
+signal tx_led : std_logic;
+
+signal reset_word_cnt : unsigned(4 downto 0);
+signal make_trbnet_reset : std_logic;
+signal make_trbnet_reset_q : std_logic;
+signal send_reset_words : std_logic;
+signal send_reset_words_q : std_logic;
+signal send_reset_in : std_logic;
+signal send_reset_in_qtx : std_logic;
+signal reset_i : std_logic;
+signal reset_i_rx : std_logic;
+signal pwr_up : std_logic;
+signal clear_S : std_logic;
+
+
+signal gt0_txfsmresetdone_i : std_logic;
+signal gt0_rxfsmresetdone_i : std_logic;
+signal gt0_txresetdone_i : std_logic;
+signal gt0_txfsmresetdone_q : std_logic;
+signal gt0_rxfsmresetdone_q : std_logic;
+signal gt0_txresetdone_q : std_logic;
+
+signal link_rx_error_S : std_logic;
+signal link_tx_error_S : std_logic;
+
+
+
+attribute mark_debug : string;
+-- attribute mark_debug of txData16_S : signal is "true";
+-- attribute mark_debug of txCharIsK16_S : signal is "true";
+-- attribute mark_debug of rxNotInTable16_S : signal is "true";
+-- attribute mark_debug of rxData16_S : signal is "true";
+-- attribute mark_debug of rxCharIsK16_S : signal is "true";
+
+-- attribute mark_debug of txData8_S : signal is "true";
+-- attribute mark_debug of txCharIsK8_S : signal is "true";
+-- attribute mark_debug of rxData8_S : signal is "true";
+-- attribute mark_debug of rxCharIsK8_S : signal is "true";
+
+-- attribute mark_debug of quad_rst : signal is "true";
+-- attribute mark_debug of quad_rst_S : signal is "true";
+-- attribute mark_debug of rxLocked2_S : signal is "true";
+-- attribute mark_debug of sfp_los : signal is "true";
+-- attribute mark_debug of tx_allow : signal is "true";
+-- attribute mark_debug of rx_allow : signal is "true";
+-- attribute mark_debug of link_rx_error_S : signal is "true";
+-- attribute mark_debug of link_tx_error_S : signal is "true";
+
+-- attribute mark_debug of fifo_rx_rd_en : signal is "true";
+-- attribute mark_debug of fifo_rx_wr_en : signal is "true";
+-- attribute mark_debug of fifo_rx_full : signal is "true";
+-- attribute mark_debug of fifo_rx_empty : signal is "true";
+-- attribute mark_debug of fifo_tx_rd_en : signal is "true";
+-- attribute mark_debug of fifo_tx_wr_en : signal is "true";
+-- attribute mark_debug of fifo_tx_full : signal is "true";
+-- attribute mark_debug of fifo_tx_empty : signal is "true";
+
+-- attribute mark_debug of make_trbnet_reset_q : signal is "true";
+-- attribute mark_debug of send_reset_in : signal is "true";
+-- attribute mark_debug of reset_i_rx : signal is "true";
+-- attribute mark_debug of gt0_rxfsmresetdone_q : signal is "true";
+-- attribute mark_debug of gt0_txfsmresetdone_q : signal is "true";
+-- attribute mark_debug of gt0_txresetdone_q : signal is "true";
+
+-- attribute mark_debug of pllLkDet_S : signal is "true";
+-- attribute mark_debug of CDR_reset_S : signal is "true";
+-- attribute mark_debug of rxCDRlock_S : signal is "true";
+-- attribute mark_debug of rxReset_S : signal is "true";
+-- attribute mark_debug of resetDone_S : signal is "true";
+-- attribute mark_debug of rxLossOfSync1_S : signal is "true";
+-- attribute mark_debug of rxResetBitLock_S : signal is "true";
+-- attribute mark_debug of fsmStatus_S : signal is "true";
+
+-- attribute mark_debug of rxResetBitLock_pulse_S : signal is "true";
+-- attribute mark_debug of gt0_txresetdone_i : signal is "true";
+
+
+
+ begin
+
+SODA_CLOCK_OUT <= ff_rxfullclk;
+--SODA_LOCKED_OUT <= rxLocked2_S;
+SODA_LOCKED_OUT <= '1' when (tx_allow='1') and (rx_allow='1') else '0';
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+ clear_S <= clear;
+
+
+ PROC_RESET : process(SYSCLK)
+ begin
+ if rising_edge(SYSCLK) then
+ reset_i <= RESET;
+ send_reset_in <= ctrl_op(15);
+ pwr_up <= '1'; --not CTRL_OP(i*16+14);
+ end if;
+ end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => SODA_PRSNT_N_IN,
+ D_IN(1) => SODA_LOS_IN,
+ CLK0 => SYSCLK,
+ CLK1 => SYSCLK,
+ D_OUT(0) => sfp_prsnt_n,
+ D_OUT(1) => sfp_los
+ );
+
+
+THE_SENDRESET_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 1
+ )
+ port map(
+ RESET => reset_i,
+ D_IN(0) => send_reset_words,
+ CLK0 => SYSCLK,
+ CLK1 => SYSCLK,
+ D_OUT(0) => send_reset_words_q
+ );
+
+THE_RESET_SYNC: DC_posedge_to_pulse
+ port map(
+ clock_in => ff_rxhalfclk,
+ clock_out => SYSCLK,
+ en_clk => '1',
+ signal_in => make_trbnet_reset,
+ pulse => make_trbnet_reset_q
+ );
+
+THE_RX_RESET: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 1
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => reset_i,
+ CLK0 => ff_rxhalfclk,
+ CLK1 => ff_rxhalfclk,
+ D_OUT(0) => reset_i_rx
+ );
+
+-- Delay for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => rx_allow,
+ D_IN(1) => tx_allow,
+ CLK0 => SYSCLK,
+ CLK1 => SYSCLK,
+ D_OUT(0) => rx_allow_q,
+ D_OUT(1) => tx_allow_q
+ );
+
+THE_TX_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 1
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => send_reset_in,
+ CLK0 => ff_txfullclk,
+ CLK1 => ff_txfullclk,
+ D_OUT(0) => send_reset_in_qtx
+ );
+
+THE_SFPSIGNALS_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 3
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => gt0_rxfsmresetdone_i,
+ D_IN(1) => gt0_txfsmresetdone_i,
+ D_IN(2) => gt0_txresetdone_i,
+ CLK0 => SYSCLK,
+ CLK1 => SYSCLK,
+ D_OUT(0) => gt0_rxfsmresetdone_q,
+ D_OUT(1) => gt0_txfsmresetdone_q,
+ D_OUT(2) => gt0_txresetdone_q
+ );
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+ generic map (
+ CHECK_FOR_CV => c_YES,
+ HIGHSPEED_STARTUP => c_YES
+ )
+ port map(
+ SYSCLK => SYSCLK,
+ RESET => reset_i,
+ CLEAR => clear_S,
+ SFP_MISSING_IN => sfp_prsnt_n,
+ SFP_LOS_IN => sfp_los,
+ SD_LINK_OK_IN => rxLocked2_S, -- apparently not used
+ SD_LOS_IN => '0', -- apparently not used
+ SD_TXCLK_BAD_IN => link_tx_error_S,
+ SD_RXCLK_BAD_IN => link_rx_error_S,
+ SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+ SD_ALIGNMENT_IN => "01",
+ SD_CV_IN => rxNotInTable16_q,
+ FULL_RESET_OUT => quad_rst,
+ LANE_RESET_OUT => open, -- apparently not used
+ TX_ALLOW_OUT => tx_allow,
+ RX_ALLOW_OUT => rx_allow,
+ SWAP_BYTES_OUT => open,
+ STAT_OP => buf_stat_op,
+ CTRL_OP => ctrl_op,
+ STAT_DEBUG => buf_stat_debug
+ );
+SODA_TXDIS_OUT <= quad_rst or reset_i;
+link_rx_error_S <= '1' when (gt0_rxfsmresetdone_q='0') or (rxLocked2_S='0') else '0'; -- loss of lock
+link_tx_error_S <= '1' when (gt0_txresetdone_q='0') or (gt0_txfsmresetdone_q='0') else '0';
+
+process(SYSClk,quad_rst)
+variable counter_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+ if quad_rst='1' then
+ quad_rst_S <= '1';
+ counter_V := (others => '0');
+ elsif rising_edge(sysClk) then
+ quad_rst_S <= '0';
+ if counter_V(counter_V'left)='1' then
+ if resetDone_S='0' then
+ counter_V := (others => '0');
+ quad_rst_S <= '1';
+ end if;
+ else
+ counter_V := counter_V+1;
+ end if;
+ end if;
+end process;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+-- SerDes clock output to FPGA fabric
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
+THE_SERDES: GTX_trb3_sync_2gb_support port map
+ (
+ soft_reset_tx_in => quad_rst_S, -- quad_rst,
+ soft_reset_rx_in => quad_rst_S, -- quad_rst,
+ DONT_RESET_ON_DATA_ERROR_IN => '1',
+ Q2_CLK0_GTREFCLK_PAD_N_IN => SODA_REFCLK_N_IN,
+ Q2_CLK0_GTREFCLK_PAD_P_IN => SODA_REFCLK_P_IN,
+ GT0_TX_FSM_RESET_DONE_OUT => gt0_txfsmresetdone_i,
+ GT0_RX_FSM_RESET_DONE_OUT => gt0_rxfsmresetdone_i,
+ GT0_DATA_VALID_IN => '1', -- tx_allow,
+ GT0_TX_MMCM_LOCK_OUT => open,
+
+ GT0_TXUSRCLK_OUT => open,
+ GT0_TXUSRCLK2_OUT => ff_txhalfclk, -- clock for tx_data (100MHz)
+ GT0_TXUSRCLKX2_OUT => open, --//tryff_txfullclk, -- clock for 8 bits data (200MHz)
+ GT0_RXUSRCLK_OUT => open,
+ GT0_RXUSRCLK2_OUT => ff_rxhalfclk, -- clock for rx_data (100MHz)
+ --_____________________________________________________________________
+ --_____________________________________________________________________
+ --GT0 (X1Y10)
+ --------------------------------- CPLL Ports -------------------------------
+ gt0_cpllfbclklost_out => open,
+ gt0_cplllock_out => pllLkDet_S,
+ gt0_cpllreset_in => '0',
+ ---------------------------- Channel - DRP Ports --------------------------
+ gt0_drpaddr_in => drpaddr_in_S,
+ gt0_drpdi_in => drpdi_in_S,
+ gt0_drpdo_out => drpdo_out_S,
+ gt0_drpen_in => drpen_in_S,
+ gt0_drprdy_out => drprdy_out_S,
+ gt0_drpwe_in => drpwe_in_S,
+ --------------------------- Digital Monitor Ports --------------------------
+ gt0_dmonitorout_out => open,
+ --------------------- RX Initialization and Reset Ports --------------------
+ gt0_eyescanreset_in => '0',
+ gt0_rxuserrdy_in => '0',
+ -------------------------- RX Margin Analysis Ports ------------------------
+ gt0_eyescandataerror_out => open,
+ gt0_eyescantrigger_in => '0',
+ ------------------------- Receive Ports - CDR Ports ------------------------
+ GT0_RXCDRRESET_IN => CDR_reset_S,
+ GT0_RXCDRLOCK_OUT => rxCDRlock_S,
+ ------------------ Receive Ports - FPGA RX interface Ports -----------------
+ gt0_rxdata_out => rxData16_S,
+ ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+ gt0_rxdisperr_out => open,
+ gt0_rxnotintable_out => rxNotInTable16_S,
+ --------------------------- Receive Ports - RX AFE -------------------------
+ gt0_gtxrxp_in => SODA_RXD_P_IN,
+ ------------------------ Receive Ports - RX AFE Ports ----------------------
+ gt0_gtxrxn_in => SODA_RXD_N_IN,
+ ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+ gt0_rxphmonitor_out => open,
+ gt0_rxphslipmonitor_out => open,
+ --------------------- Receive Ports - RX Equalizer Ports -------------------
+ gt0_rxdfelpmreset_in => '0',
+ gt0_rxmonitorout_out => open,
+ gt0_rxmonitorsel_in => "00",
+ ------------- Receive Ports - RX Initialization and Reset Ports ------------
+ gt0_gtrxreset_in => rxReset_S, --// => '0',
+ gt0_rxpmareset_in => rxReset_S, --// => '0',
+ ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+ gt0_rxcharisk_out => rxCharIsK16_S,
+ -------------- Receive Ports -RX Initialization and Reset Ports ------------
+ gt0_rxresetdone_out => resetDone_S,
+ --------------------- TX Initialization and Reset Ports --------------------
+ gt0_gttxreset_in => '0',
+ gt0_txuserrdy_in => '0',
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ gt0_txdata_in => txData16_S,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ gt0_gtxtxn_out => SODA_TXD_N_OUT,
+ gt0_gtxtxp_out => SODA_TXD_P_OUT,
+ ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+ gt0_txoutclkfabric_out => open,
+ gt0_txoutclkpcs_out => open,
+ --------------------- Transmit Ports - TX Gearbox Ports --------------------
+ gt0_txcharisk_in => txCharIsK16_S,
+ ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+ gt0_txresetdone_out => gt0_txresetdone_i,
+
+ --____________________________COMMON PORTS________________________________
+ GT0_QPLLOUTCLK_OUT => open,
+ GT0_QPLLOUTREFCLK_OUT => open,
+ SYSCLK_IN => SYSCLK
+ );
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+
+sync_notintable1: DC_posedge_to_pulse port map(
+ clock_in => ff_rxhalfclk,
+ clock_out => SYSCLK,
+ en_clk => '1',
+ signal_in => rxNotInTable16_S(0),
+ pulse => rxNotInTable16_q(0));
+sync_notintable2: DC_posedge_to_pulse port map(
+ clock_in => ff_rxhalfclk,
+ clock_out => SYSCLK,
+ en_clk => '1',
+ signal_in => rxNotInTable16_S(1),
+ pulse => rxNotInTable16_q(1));
+
+
+DC_data16to8_1: DC_data16to8
+ port map(
+ clock_in => ff_rxhalfclk,
+ data_in => rxData16_S,
+ kchar_in => rxCharIsK16_S,
+ notintable_in => rxNotInTable16_S,
+ clock_out => ff_rxfullclk,
+ data_out => rxData8_S,
+ kchar_out => rxCharIsK8_S,
+ notintable_out => open
+ );
+
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+ port map( read_clock_in => SYSCLK,
+ write_clock_in => ff_rxfullclk,
+ read_enable_in => fifo_rx_rd_en,
+ write_enable_in => fifo_rx_wr_en,
+ fifo_gsr_in => fifo_rx_reset,
+ write_data_in => fifo_rx_din,
+ read_data_out => fifo_rx_dout,
+ full_out => fifo_rx_full,
+ empty_out => fifo_rx_empty
+ );
+
+fifo_rx_reset <= reset_i or not rx_allow_q;
+fifo_rx_rd_en <= not fifo_rx_empty;
+HUB_8to16_SODA1: HUB_8to16_SODA
+ port map(
+ clock => ff_rxfullclk,
+ reset => fifo_rx_reset,
+ data_in => rxData8_S,
+ char_is_k => rxCharIsK8_S,
+ fifo_data => fifo_rx_din,
+ fifo_full => fifo_rx_full,
+ fifo_write => fifo_rx_wr_en,
+ RX_DLM => SODA_DLM_OUT_S,
+ RX_DLM_WORD => SODA_DLM_WORD_OUT_S,
+ error => open
+ );
+--//try SODA_DLM_OUT <= SODA_DLM_OUT_S;
+--//try SODA_DLM_WORD_OUT <= SODA_DLM_WORD_OUT_S;
+DC_SODA_clockcrossing2: DC_SODA_clockcrossing --//try
+ port map(
+ write_clock => ff_rxfullclk,
+ read_clock => SODA_clock,
+ DLM_in => SODA_DLM_OUT_S,
+ DLM_WORD_in => SODA_DLM_WORD_OUT_S,
+ DLM_out => SODA_DLM_OUT,
+ DLM_WORD_out => SODA_DLM_WORD_OUT,
+ error => open
+ );
+
+
+buf_med_data_out <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out <= rx_counter;
+med_read_out <= tx_allow_q and not fifo_tx_almost_full;
+
+THE_CNT_RESET_PROC : process(ff_rxhalfclk)
+begin
+ if rising_edge(ff_rxhalfclk) then
+ if reset_i_rx = '1' then
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ reset_word_cnt <= (others => '0');
+ else
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ if (rxCharIsK16_S="11") and (rxData16_S=x"FEFE") then
+ if reset_word_cnt(4) = '0' then
+ reset_word_cnt <= reset_word_cnt + 1;
+ else
+ send_reset_words <= '1';
+ end if;
+ else
+ reset_word_cnt <= (others => '0');
+ make_trbnet_reset <= reset_word_cnt(4);
+ end if;
+ end if;
+ end if;
+end process;
+
+THE_SYNC_PROC: process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ med_dataready_out <= buf_med_dataready_out;
+ med_data_out <= buf_med_data_out;
+ med_packet_num_out <= buf_med_packet_num_out;
+ if reset_i = '1' then
+ med_dataready_out <= '0';
+ end if;
+ end if;
+end process;
+
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process(SYSCLK)
+begin
+ if( rising_edge(SYSCLK) ) then
+ last_fifo_rx_empty <= fifo_rx_empty;
+ if reset_i = '1' or rx_allow_q = '0' then
+ rx_counter <= c_H0;
+ else
+ if( buf_med_dataready_out = '1' ) then
+ if( rx_counter = c_max_word_number ) then
+ rx_counter <= (others => '0');
+ else
+ rx_counter <= rx_counter + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+ port map(
+ read_clock_in => ff_txfullclk,
+ write_clock_in => SYSCLK,
+ read_enable_in => fifo_tx_rd_en,
+ write_enable_in => fifo_tx_wr_en,
+ fifo_gsr_in => fifo_tx_reset,
+ write_data_in => fifo_tx_din,
+ read_data_out => fifo_tx_dout,
+ full_out => open,
+ empty_out => fifo_tx_empty,
+ almost_full_out => fifo_tx_almost_full
+ );
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+
+clockdouble: DC_data16to8 port map( --//try
+ clock_in => ff_txhalfclk,
+ data_in => (others => '0'),
+ kchar_in => (others => '0'),
+ notintable_in => (others => '0'),
+ clock_out => ff_txfullclk,
+ data_out => open,
+ kchar_out => open,
+ notintable_out => open);
+
+HUB_16to8_SODA1: HUB_16to8_SODA
+ port map(
+ clock => ff_txfullclk,
+ reset => send_reset_in_qtx,
+ fifo_data => fifo_tx_dout(15 downto 0),
+ fifo_empty => fifo_tx_empty,
+ fifo_read => fifo_tx_rd_en,
+ TX_DLM => SODA_DLM_IN_S,
+ TX_DLM_WORD => SODA_DLM_WORD_IN_S,
+ data_out => txData8_S,
+ char_is_k => txCharIsK8_S,
+ error => open
+ );
+
+DC_SODA_clockcrossing1: DC_SODA_clockcrossing
+ port map(
+ write_clock => SODA_clock, -- ff_rxfullclk, --//try
+ read_clock => ff_txfullclk,
+ DLM_in => SODA_DLM_IN,
+ DLM_WORD_in => SODA_DLM_WORD_IN,
+ DLM_out => SODA_DLM_IN_S,
+ DLM_WORD_out => SODA_DLM_WORD_IN_S,
+ error => open
+ );
+
+DC_data8to16_1: DC_data8to16
+ port map(
+ clock_in => ff_txfullclk,
+ data_in => txData8_S,
+ kchar_in => txCharIsK8_S,
+ clock_out => ff_txhalfclk,
+ data_out => txData16_S,
+ kchar_out => txCharIsK16_S
+ );
+
+rxLossOfSync1_S <= '0' when (rxNotInTable16_S="00") or (disable_GTX_reset='1') else '1';
+DC_rxBitLock1 : DC_rxBitLock port map (
+ clk => ff_rxhalfclk,
+ reset => quad_rst,
+ resetDone => resetDone_S,
+ lossOfSync => rxLossOfSync1_S,
+ rxPllLocked => PllLkDet_S,
+ rxReset => rxResetBitLock_S,
+ fsmStatus => fsmStatus_S
+ );
+
+
+rxReset_S <= '1' when ((rxPLLwrapper_reset_S='1') or (quad_rst='1') or (rxResetBitLock_pulse_S='1')) and (disable_GTX_reset='0') else '0';
+
+rxLocked0_S <= '1' when (resetDone_S='1') and (fsmStatus_S = "10") else '0';
+sync_rx_locked: sync_bit port map(
+ clock => SYSCLK,
+ data_in => rxLocked0_S,
+ data_out => rxLocked1_S);
+
+process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ if (sync_rxResetBitLock_S='1') and (prev_rxResetBitLock_S='0') then
+ rxResetBitLock_pulse_S <= '1';
+ else
+ rxResetBitLock_pulse_S <= '0';
+ end if;
+ sync_rxResetBitLock_S <= rxResetBitLock_S;
+ prev_rxResetBitLock_S <= sync_rxResetBitLock_S;
+ end if;
+end process;
+process(SYSCLK)
+variable counter_V : std_logic_vector(5 downto 0) := (others => '0');
+variable timoutcounter_V : std_logic_vector(11 downto 0) := (others => '0');
+begin
+ if rising_edge(SYSCLK) then
+ rxPLLwrapper_reset_S <= '0';
+ CDR_reset_S <= '0';
+ comma_align_latency0_valid_S <= '0';
+ drpen_in_S <= '0';
+ drpwe_in_S <= '0';
+ drpdi_in_S <= (others => '0');
+ case drp_state_S is
+ when initting =>
+ rxLocked2_S <= '0';
+ counter_V := (others => '0');
+ if resetDone_S='1' then
+ drp_state_S <= running;
+ end if;
+ when running =>
+ if rxLocked1_S='0' then
+ drp_state_S <= initting;
+ else
+ if counter_V(counter_V'left) = '1' then
+ counter_V := (others => '0');
+ timoutcounter_V := (others => '0');
+ drpen_in_S <= '1';
+ drpaddr_in_S <= "101001110"; -- x"14E";
+ drp_state_S <= reading;
+ else
+ counter_V := counter_V+1;
+ end if;
+ end if;
+ when reading =>
+ if drprdy_out_S='1' then
+ comma_align_latency_S <= drpdo_out_S(6 downto 0); -- COMMA_ALIGN_LATENCY
+ comma_align_latency0_valid_S <= '1';
+ if drpdo_out_S(6 downto 0)/="0000000" then
+ CDR_reset_S <= '1'; --// rxPLLwrapper_reset_S <= '1';
+ rxLocked2_S <= '0';
+ else
+ rxLocked2_S <= '1';
+ end if;
+ drp_state_S <= running;
+ elsif timoutcounter_V(timoutcounter_V'left)='1' then
+ CDR_reset_S <= '1';
+ rxPLLwrapper_reset_S <= '1';
+ drp_state_S <= initting;
+ else
+ timoutcounter_V := timoutcounter_V+1;
+ end if;
+ when others =>
+ drp_state_S <= initting;
+ end case;
+ end if;
+end process;
+
+
+
+--Generate LED signals
+----------------------
+process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ led_counter <= led_counter + 1;
+ if buf_med_dataready_out = '1' then
+ rx_led <= '1';
+ elsif led_counter = 0 then
+ rx_led <= '0';
+ end if;
+ if fifo_tx_wr_en = '1' then
+ tx_led <= '1';
+ elsif led_counter = 0 then
+ tx_led <= '0';
+ end if;
+ end if;
+end process;
+
+stat_op(15) <= send_reset_words_q;
+stat_op(14) <= buf_stat_op(14);
+stat_op(13) <= make_trbnet_reset_q;
+stat_op(12) <= '0';
+stat_op(11) <= tx_led; --tx led
+stat_op(10) <= rx_led; --rx led
+stat_op(9 downto 0) <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(15 downto 0) <= rxData16_S;
+stat_debug(17 downto 16) <= rxCharIsK16_S;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24) <= fifo_rx_rd_en;
+stat_debug(25) <= fifo_rx_wr_en;
+stat_debug(26) <= fifo_rx_reset;
+stat_debug(27) <= fifo_rx_empty;
+stat_debug(28) <= fifo_rx_full;
+stat_debug(29) <= '0';
+stat_debug(30) <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42) <= SYSCLK;
+stat_debug(43) <= SYSCLK;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+end architecture;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+library unisim;
+use UNISIM.VComponents.all;
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_fifo_16bit_bram_dualport is
+ generic(
+ USE_STATUS_FLAGS : integer := c_YES
+ );
+ port (
+ read_clock_in: IN std_logic;
+ write_clock_in: IN std_logic;
+ read_enable_in: IN std_logic;
+ write_enable_in: IN std_logic;
+ fifo_gsr_in: IN std_logic;
+ write_data_in: IN std_logic_vector(17 downto 0);
+ read_data_out: OUT std_logic_vector(17 downto 0);
+ full_out: OUT std_logic;
+ empty_out: OUT std_logic;
+ fifostatus_out: OUT std_logic_vector(3 downto 0);
+ valid_read_out: OUT std_logic;
+ almost_empty_out:OUT std_logic;
+ almost_full_out :OUT std_logic
+ );
+end entity trb_net_fifo_16bit_bram_dualport;
+
+architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is
+
+ signal buf_empty_out, buf_full_out : std_logic;
+
+attribute box_type: string;
+ component xilinx_fifo_dualport_18x1k
+ port (
+ din: IN std_logic_VECTOR(17 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ valid: OUT std_logic);
+ end component;
+attribute box_type of xilinx_fifo_dualport_18x1k : component is "black_box";
+
+BEGIN
+ FIFO_DP_BRAM : xilinx_fifo_dualport_18x1k
+ port map (
+ din => write_data_in,
+ rd_clk => read_clock_in,
+ rd_en => read_enable_in,
+ rst => fifo_gsr_in,
+ wr_clk => write_clock_in,
+ wr_en => write_enable_in,
+ dout => read_data_out,
+ empty => buf_empty_out,
+ full => buf_full_out,
+ valid => valid_read_out
+ );
+
+empty_out <= buf_empty_out;
+full_out <= buf_full_out;
+almost_full_out <= buf_full_out;
+almost_empty_out <= buf_empty_out;
+fifostatus_out <= (others => '0');
+end architecture;
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+library unisim;
+use UNISIM.VComponents.all;
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_fifo_16bit_bram_dualport is
+ generic(
+ USE_STATUS_FLAGS : integer := c_YES
+ );
+ port (
+ read_clock_in: IN std_logic;
+ write_clock_in: IN std_logic;
+ read_enable_in: IN std_logic;
+ write_enable_in: IN std_logic;
+ fifo_gsr_in: IN std_logic;
+ write_data_in: IN std_logic_vector(17 downto 0);
+ read_data_out: OUT std_logic_vector(17 downto 0);
+ full_out: OUT std_logic;
+ empty_out: OUT std_logic;
+ fifostatus_out: OUT std_logic_vector(3 downto 0);
+ valid_read_out: OUT std_logic;
+ almost_empty_out:OUT std_logic;
+ almost_full_out :OUT std_logic
+ );
+end entity trb_net_fifo_16bit_bram_dualport;
+
+architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is
+
+ signal buf_empty_out, buf_full_out : std_logic;
+
+attribute box_type: string;
+ component xilinx_fifo_dualport_18x1k
+ port (
+ din: IN std_logic_VECTOR(17 downto 0);
+ rd_clk: IN std_logic;
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_clk: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ valid: OUT std_logic);
+ end component;
+attribute box_type of xilinx_fifo_dualport_18x1k : component is "black_box";
+
+BEGIN
+ FIFO_DP_BRAM : xilinx_fifo_dualport_18x1k
+ port map (
+ din => write_data_in,
+ rd_clk => read_clock_in,
+ rd_en => read_enable_in,
+ rst => fifo_gsr_in,
+ wr_clk => write_clock_in,
+ wr_en => write_enable_in,
+ dout => read_data_out,
+ empty => buf_empty_out,
+ full => buf_full_out,
+ valid => valid_read_out
+ );
+
+empty_out <= buf_empty_out;
+full_out <= buf_full_out;
+almost_full_out <= buf_full_out;
+almost_empty_out <= buf_empty_out;
+fifostatus_out <= (others => '0');
+end architecture;
+
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-\r
- entity test_module is
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- -- Slave bus
- BUS_READ_IN : in std_logic;
- BUS_WRITE_IN : in std_logic;
- BUS_BUSY_OUT : out std_logic;
- BUS_ACK_OUT : out std_logic;
- BUS_ADDR_IN : in std_logic_vector(1 downto 0);
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);
- LEDS_ACT_OUT : out std_logic;
- LEDS_OUT : out std_logic_vector(3 downto 0);
- SPARE_LINE : in std_logic_vector(5 downto 0);
- TEST_LINE : out std_logic_vector(15 downto 0);
- -- Status lines
- STAT : out std_logic_vector(31 downto 0) -- DEBUG
- );
-end entity;
-
-architecture Behavioral of test_module is
--- Signals
- type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
- signal CURRENT_STATE, NEXT_STATE: STATES;
-
- -- slave bus signals
- signal bus_ack_x : std_logic;
- signal bus_ack : std_logic;
- signal store_wr_x : std_logic;
- signal store_wr : std_logic;
- signal store_rd_x : std_logic;
- signal store_rd : std_logic;
- signal buf_bus_data_out : std_logic_vector(31 downto 0);
-\r
- signal LEDregister_i : std_logic_vector(31 downto 0);
- signal TEST_LINE_i : std_logic_vector(31 downto 0);
-
-begin
-
----------------------------------------------------------
--- Debugging --
----------------------------------------------------------
-stat(31 downto 0) <= (others => '0');
-
----------------------------------------------------------
--- Statemachine --
----------------------------------------------------------
- STATE_MEM: process( clk_in)
- begin
- if( rising_edge(clk_in) ) then
- if( RESET_IN = '1' ) then
- CURRENT_STATE <= SLEEP;
- bus_ack <= '0';
- store_wr <= '0';
- store_rd <= '0';
- else
- CURRENT_STATE <= NEXT_STATE;
- bus_ack <= bus_ack_x;
- store_wr <= store_wr_x;
- store_rd <= store_rd_x;
- end if;
- end if;
- end process STATE_MEM;
-
--- Transition matrix
- TRANSFORM: process(CURRENT_STATE, BUS_read_in, BUS_write_in )
- begin
- NEXT_STATE <= SLEEP;
- bus_ack_x <= '0';
- store_wr_x <= '0';
- store_rd_x <= '0';
- case CURRENT_STATE is
- when SLEEP =>
- if ( (BUS_read_in = '1') ) then
- NEXT_STATE <= RD_RDY;
- store_rd_x <= '1';
- elsif( (BUS_write_in = '1') ) then
- NEXT_STATE <= WR_RDY;
- store_wr_x <= '1';
- else
- NEXT_STATE <= SLEEP;
- end if;
-
- when RD_RDY =>
- NEXT_STATE <= RD_ACK;
-
- when WR_RDY =>
- NEXT_STATE <= WR_ACK;
-
- when RD_ACK =>
- if( BUS_read_in = '0' ) then
- NEXT_STATE <= DONE;
- bus_ack_x <= '1';
- else
- NEXT_STATE <= RD_ACK;
- bus_ack_x <= '1';
- end if;
-
- when WR_ACK =>
- if( BUS_write_in = '0' ) then
- NEXT_STATE <= DONE;
- bus_ack_x <= '1';
- else
- NEXT_STATE <= WR_ACK;
- bus_ack_x <= '1';
- end if;
-
- when DONE =>
- NEXT_STATE <= SLEEP;
-
- when others =>
- NEXT_STATE <= SLEEP;
- end case;
-end process TRANSFORM;
-
-
----------------------------------------------------------
--- data handling --
----------------------------------------------------------\r
-\r
--- register write
-THE_WRITE_REG_PROC: process( clk_in )
- begin
- if( rising_edge(clk_in) ) then
- if ( RESET_IN = '1' ) then
- LEDregister_i <= (others => '0');
- TEST_LINE_i <= (others => '0');
- elsif( (store_wr = '1') and (bus_addr_in = "00") ) then
- LEDregister_i <= bus_data_in;
- elsif( (store_wr = '1') and (bus_addr_in = "01") ) then
- TEST_LINE_i <= bus_data_in;
- else
- end if;
- end if;
- end process THE_WRITE_REG_PROC;\r
- \r
-LEDS_OUT <= LEDregister_i(3 downto 0);\r
-LEDS_ACT_OUT <= LEDregister_i(4);\r
-TEST_LINE <= TEST_LINE_i(15 downto 0); \r
-\r
--- register read
-THE_READ_REG_PROC: process( clk_in )
- begin
- if( rising_edge(clk_in) ) then
- if ( RESET_IN = '1' ) then
- buf_bus_data_out <= (others => '0');
- elsif( (store_rd = '1') and (bus_addr_in = "00") ) then
- buf_bus_data_out <= LEDregister_i;
- elsif( (store_rd = '1') and (bus_addr_in = "01") ) then\r
- buf_bus_data_out <= TEST_LINE_i;
- elsif( (store_rd = '1') and (bus_addr_in = "10") ) then\r
- buf_bus_data_out(5 downto 0) <= SPARE_LINE;
- buf_bus_data_out(31 downto 6) <= (others => '0');
- end if;
- end if;
- end process THE_READ_REG_PROC;\r
- \r
-
--- output signals
-BUS_DATA_OUT <= buf_bus_data_out;
-BUS_ACK_OUT <= bus_ack;\r
-BUS_BUSY_OUT <= '0';\r
-\r
-end Behavioral;
--- /dev/null
+define_clock {n:THE_MAIN_PLL.CLKOP} -name {clk_65_i} -freq 65
+define_clock {n:THE_MAIN_PLL.CLKOS} -name {clk_200_i} -freq 200
+define_clock {n:THE_CLKDIV.CDIV2} -name {clk_100_i} -freq 100
+define_clock {n:THE_MEDIA_UPLINK.THE_SERDES.rx_full_clk_ch2} -name {rx_full_clk_ch2} -freq 200
+define_clock {n:THE_MEDIA_UPLINK.THE_SERDES.tx_full_clk_ch2} -name {tx_full_clk_ch2} -freq 200
+define_clock {n:THE_MEDIA_UPLINK.THE_SERDES.rx_full_clk_ch3} -name {tx_full_clk_ch3} -freq 200
+define_clock {n:THE_MEDIA_UPLINK.THE_SERDES.tx_full_clk_ch3} -name {rx_full_clk_ch3} -freq 200
+define_clock {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.THE_SERDES.rx_full_clk_ch0} -name {rx_fee_clk0} -freq 200
+define_clock {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.THE_SERDES.rx_full_clk_ch1} -name {rx_fee_clk1} -freq 200
+define_clock {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.THE_SERDES.rx_full_clk_ch2} -name {rx_fee_clk2} -freq 200
+define_clock {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.THE_SERDES.rx_full_clk_ch3} -name {rx_fee_clk3} -freq 200
+define_clock {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.clk_tx_full[0]} -name {tx_fee_clk0} -freq 200
+define_clock {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.clk_tx_full[1]} -name {tx_fee_clk1} -freq 200
+define_clock {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.clk_tx_full[2]} -name {tx_fee_clk2} -freq 200
+define_clock {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.clk_tx_full[3]} -name {tx_fee_clk3} -freq 200
+define_clock {n:clk_SODA200_i} -name {clk_SODA200_i} -freq 200
+
+++ /dev/null
-rvl_alias "clk_80_i" "clk_80_i";
-RVL_ALIAS "clk_62M5_i" "clk_62M5_i"; \r
-RVL_ALIAS "clk_62M5_i" "clk_62M5_i"; \r
-RVL_ALIAS "clk_100_i" "clk_100_i"; \r
-BLOCK RESETPATHS ;\r
-BLOCK ASYNCPATHS ;\r
-BLOCK RD_DURING_WR_PATHS ;\r
-#################################################################\r
-# Basic Settings\r
-#################################################################\r
-SYSCONFIG MCCLK_FREQ=2.5 ;\r
-FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;\r
-FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;\r
-FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ;\r
-FREQUENCY PORT "CLK_GPLL_LEFT" 125.000000 MHz ;\r
-#################################################################\r
-# Clock I/O\r
-#################################################################\r
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;\r
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;\r
-LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18" ;\r
-LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10" ;\r
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;\r
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;\r
-DEFINE PORT GROUP "CLK_group" "CLK*" ;\r
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;\r
-#################################################################\r
-# Trigger I/O\r
-#################################################################\r
-#Trigger from fan-out\r
-LOCATE COMP "TRIGGER_LEFT" SITE "V3" ;\r
-LOCATE COMP "TRIGGER_RIGHT" SITE "N24" ;\r
-IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;\r
-IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;\r
-#################################################################\r
-# To central FPGA\r
-#################################################################\r
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;\r
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;\r
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;\r
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;\r
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;\r
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;\r
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;\r
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;\r
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;\r
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;\r
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;\r
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;\r
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;\r
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;\r
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;\r
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;\r
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;\r
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;\r
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;\r
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;\r
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;\r
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;\r
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;\r
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;\r
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;\r
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;\r
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;\r
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;\r
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;\r
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;\r
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;\r
-#################################################################\r
-# Connection to AddOn\r
-#################################################################\r
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1\r
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3\r
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5\r
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7\r
-LOCATE COMP "SFP_MOD1_1" SITE "R1" ;#DQLL0_4 #9\r
-LOCATE COMP "SFP_MOD2_1" SITE "R2" ;#DQLL0_5 #11\r
-LOCATE COMP "SFP_RATESEL_1" SITE "N3" ;#DQSLL0_T #13\r
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15\r
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17\r
-LOCATE COMP "SFP_TXFAULT_1" SITE "P6" ;#DQLL0_7 #19\r
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21\r
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23\r
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25\r
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27\r
-LOCATE COMP "SFP_MOD1_2" SITE "AB1" ;#DQLL2_2 #29\r
-LOCATE COMP "SFP_MOD2_2" SITE "AC1" ;#DQLL2_3 #31\r
-LOCATE COMP "SFP_RATESEL_2" SITE "AA1" ;#DQLL2_4 #33\r
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35\r
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2\r
-LOCATE COMP "SFP_TXFAULT_2" SITE "W6" ;#DQLL2_C #39 #should be DQSLL2\r
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2\r
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4\r
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6\r
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8\r
-LOCATE COMP "SFP_MOD1_3" SITE "AB3" ;#DQLL3_4 #10\r
-LOCATE COMP "SFP_MOD2_3" SITE "AB4" ;#DQLL3_5 #12\r
-LOCATE COMP "SFP_RATESEL_3" SITE "Y6" ;#DQLL3_T #14 #should be DQSLL3\r
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3\r
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18\r
-LOCATE COMP "SFP_TXFAULT_3" SITE "AA4" ;#DQLL3_7 #20\r
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22\r
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24\r
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26\r
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28\r
-LOCATE COMP "SFP_MOD1_4" SITE "T1" ;#DQLL1_2 #30\r
-LOCATE COMP "SFP_MOD2_4" SITE "U1" ;#DQLL1_3 #32\r
-LOCATE COMP "SFP_RATESEL_4" SITE "P4" ;#DQLL1_4 #34\r
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36\r
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38\r
-LOCATE COMP "SFP_TXFAULT_4" SITE "R4" ;#DQSLL1_C #40\r
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169\r
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171\r
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173\r
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175\r
-LOCATE COMP "SFP_MOD1_5" SITE "AA26" ;#DQLR1_4 #177\r
-LOCATE COMP "SFP_MOD2_5" SITE "AB26" ;#DQLR1_5 #179\r
-LOCATE COMP "SFP_RATESEL_5" SITE "W21" ;#DQSLR1_T #181\r
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183\r
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185\r
-LOCATE COMP "SFP_TXFAULT_5" SITE "AA23" ;#DQLR1_7 #187\r
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170\r
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172\r
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174\r
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176\r
-LOCATE COMP "SFP_MOD1_6" SITE "T26" ;#DQLR2_4 #178\r
-LOCATE COMP "SFP_MOD2_6" SITE "U26" ;#DQLR2_5 #180\r
-LOCATE COMP "SFP_RATESEL_6" SITE "V21" ;#DQSLR2_T #182\r
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184\r
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186\r
-LOCATE COMP "SFP_TXFAULT_6" SITE "V24" ;#DQLR2_7 #188\r
-DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-#################################################################\r
-# Additional Lines to AddOn\r
-#################################################################\r
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3\r
-#all lines are input only\r
-#line 4/5 go to PLL input\r
-LOCATE COMP "SPARE_LINE[0]" SITE "M25" ;#194\r
-LOCATE COMP "SPARE_LINE[1]" SITE "M26" ;#196\r
-LOCATE COMP "SPARE_LINE[2]" SITE "W4" ;#198\r
-LOCATE COMP "SPARE_LINE[3]" SITE "W5" ;#200\r
-LOCATE COMP "SPARE_LINE[4]" SITE "M3" ;#DQUL3_8_OUTOFLANE_FPGA__3 #69\r
-LOCATE COMP "SPARE_LINE[5]" SITE "M2" ;#DQUL3_9_OUTOFLANE_FPGA__3 #71 \r
-#################################################################\r
-# Flash ROM and Reboot\r
-#################################################################\r
-LOCATE COMP "FLASH_CLK" SITE "B12" ;\r
-LOCATE COMP "FLASH_CS" SITE "E11" ;\r
-LOCATE COMP "FLASH_DIN" SITE "E12" ;\r
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;\r
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;\r
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;\r
-LOCATE COMP "PROGRAMN" SITE "B11" ;\r
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
-#################################################################\r
-# Misc\r
-#################################################################\r
-LOCATE COMP "TEMPSENS" SITE "A13" ;\r
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
-#coding of FPGA number\r
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;\r
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;\r
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-#terminated differential pair to pads\r
-LOCATE COMP "SUPPL" SITE "C14" ;\r
-IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;\r
-#################################################################\r
-# LED\r
-#################################################################\r
-LOCATE COMP "LED_GREEN" SITE "F12" ;\r
-LOCATE COMP "LED_ORANGE" SITE "G13" ;\r
-LOCATE COMP "LED_RED" SITE "A15" ;\r
-LOCATE COMP "LED_YELLOW" SITE "A16" ;\r
-DEFINE PORT GROUP "LED_group" "LED*" ;\r
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;\r
-BLOCK RESETPATHS ;\r
-BLOCK ASYNCPATHS ;\r
-BLOCK RD_DURING_WR_PATHS ;\r
-MULTICYCLE TO GROUP "LED_group" 100.000000 ns ;
-#################################################################\r
-# Basic Settings\r
-#################################################################\r
-SYSCONFIG MCCLK_FREQ=20 ;\r
-FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;\r
-FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;\r
-FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ;\r
-FREQUENCY PORT "CLK_GPLL_LEFT" 125.000000 MHz ;\r
-#################################################################\r
-# Reset Nets\r
-################################################################# \r
-GSR_NET NET "GSR_N";\r
-#################################################################\r
-# Locate Serdes and media interfaces\r
-#################################################################\r
-#//? LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
-#//? LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_125_THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
-LOCATE COMP "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/THE_SERDES/PCSD_INST" SITE "PCSB" ;\r
-#####REGION "MEDIA_UPLINK" "R90C95D" 13 25;\r
-#####REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;\r
-REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;\r
-#####REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE;\r
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;\r
-LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;\r
-#####LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;\r
-#####LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;\r
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/SCI_DATA_OUT*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/sci*" 20.000000 ns ;\r
-MULTICYCLE FROM CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/sci*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/wa_pos*" 20.000000 ns ;\r
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;\r
-MAXSKEW NET "clk_125_i" 1.000000 nS ;\r
-MAXSKEW NET "clk_160_i" 1.000000 nS ;\r
-MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_62M5_i" 8.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_125_i" 8.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_62M5_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_100_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_62M5_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_200_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_125_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_100_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_125_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_200_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_160_i" TO CLKNET "clk_80_i" 6.250000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_160_i" 6.250000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_80_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_100_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_80_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_200_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_160_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_160_i" TO CLKNET "clk_100_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_160_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_160_i" TO CLKNET "clk_200_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_62M5_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_80_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_80_i" 200.000000 ns ;\r
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_125_i" 200.000000 ns ;\r
-
-\r
-BLOCK JTAGPATHS ;\r
-#MAXSKEW NET "the_dataconcentrator/dc_quad_fiber_module_all/serdesquadbuflayermux1/serdesquadmuxwrapper1/med_ecp3_quad_sfp_sync1/tx_sync_qd_c" 1.000000 nS ;\r
-#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 0.100000 ns ;\r
-#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 0.100000 ns ;\r
-#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 0.100000 ns ;\r
-#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" TO CLKNET "clk_125_i_c" 0.200000 ns ;\r
-#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" TO CLKNET "clk_125_i_c" 0.200000 ns ;\r
-#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" TO CLKNET "clk_125_i_c" 0.200000 ns ;\r
-#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" TO CLKNET "clk_125_i_c" 0.200000 ns ;\r
-#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1.000000 nS ;\r
-#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1.000000 nS ;\r
-#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1.000000 nS ;\r
-#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1.000000 nS ;\r
-#MAXDELAY FROM CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/tx_sync_qd_c" TO ASIC "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/THE_SERDES/PCSD_INST" PIN "FFC_SYNC_TOGGLE" 1.200000 ns ;\r
-#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 0.100000 ns ;\r
-#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1.000000 nS ;\r
-#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1.000000 nS ;\r
-#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1.000000 nS ;\r
-#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1.000000 nS ;\r
-#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1000.000000 MHz ;\r
-#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1000.000000 MHz ;\r
-#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1000.000000 MHz ;\r
-#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1000.000000 MHz ;\r
+++ /dev/null
--- the full endpoint for HADES: trg, data, unused, regio\r
-\r
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.std_logic_ARITH.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-\r
-\r
-entity trb_net16_endpoint_data_concentrator is\r
- generic (\r
- USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);\r
- IBUF_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);\r
- IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
- API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
- API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
- OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;\r
- INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
- REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);\r
- APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
- --standard values for output registers\r
- REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
- --set to 0 for unused ctrl registers to save resources\r
- REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');\r
- --set to 0 for each unused bit in a register\r
- REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
- REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
- REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
- REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
- CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
- );\r
-\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic := '1';\r
-\r
- -- Media direction port\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN : in std_logic;\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
-\r
- -- LVL1 trigger APL\r
- TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received or real timing trigger signal\r
-\r
- LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
- LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received\r
- LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received\r
- LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
-\r
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
-\r
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";\r
- LVL1_TRG_RELEASE_IN : in std_logic := '0';\r
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
-\r
- --Information about trigger handler errors\r
- TRG_MULTIPLE_TRG_OUT : out std_logic;\r
- TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
- TRG_SPURIOUS_TRG_OUT : out std_logic;\r
- TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
- TRG_SPIKE_DETECTED_OUT : out std_logic;\r
- TRG_LONG_TRG_OUT : out std_logic;\r
-\r
- --Data Port\r
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
- IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
- --start strobe\r
- IPU_START_READOUT_OUT : out std_logic;\r
- --detector data, equipped with DHDR\r
- IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
- IPU_DATAREADY_IN : in std_logic;\r
- --no more data, end transfer, send TRM\r
- IPU_READOUT_FINISHED_IN : in std_logic;\r
- --will be low every second cycle due to 32bit -> 16bit conversion\r
- IPU_READ_OUT : out std_logic;\r
- IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
- IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
-\r
-\r
- -- Slow Control Data Port\r
- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
- REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
- REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
- COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
- STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
- CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- --following ports only used when using internal data port\r
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
- REGIO_READ_ENABLE_OUT : out std_logic;\r
- REGIO_WRITE_ENABLE_OUT : out std_logic;\r
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
- REGIO_DATAREADY_IN : in std_logic := '0';\r
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
- REGIO_WRITE_ACK_IN : in std_logic := '0';\r
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
- REGIO_TIMEOUT_OUT : out std_logic;\r
- --IDRAM is used if no 1-wire interface, onewire used otherwise\r
- REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
- REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
- REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";\r
- REGIO_IDRAM_WR_IN : in std_logic := '0';\r
- REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
- REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0';\r
- REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
-\r
- GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
- LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
- TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
- --Debugging & Status information\r
- STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
- MED_STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
- IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
- STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
- STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
- STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);\r
- DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
- );\r
-end trb_net16_endpoint_data_concentrator;\r
-\r
-\r
-\r
-\r
-\r
-architecture trb_net16_endpoint_data_concentrator_arch of trb_net16_endpoint_data_concentrator is\r
-\r
-\r
- signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);\r
- signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);\r
- signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);\r
- signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0);\r
-\r
- signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0);\r
- signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);\r
- signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);\r
- signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0);\r
-\r
- signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0);\r
- signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);\r
- signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);\r
- signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0);\r
-\r
- signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0);\r
- signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);\r
- signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);\r
- signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0);\r
-\r
- -- for the connection to the multiplexer\r
- signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0);\r
- signal MED_IO_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);\r
- signal MED_IO_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);\r
- signal MED_IO_READ_OUT : std_logic_vector(3 downto 0);\r
-\r
- signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0);\r
- signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0);\r
- signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0);\r
- signal MED_IO_READ_IN : std_logic_vector(7 downto 0);\r
-\r
- signal buf_APL_DATA_IN : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- signal buf_APL_PACKET_NUM_IN : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- signal buf_APL_DATAREADY_IN : std_logic_vector(3 downto 0);\r
- signal buf_APL_READ_OUT : std_logic_vector(3 downto 0);\r
- signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0);\r
- signal buf_APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0);\r
- signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0);\r
- signal buf_APL_SEND_IN : std_logic_vector(3 downto 0);\r
- signal buf_APL_DATA_OUT : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- signal buf_APL_PACKET_NUM_OUT : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- signal buf_APL_DATAREADY_OUT : std_logic_vector(3 downto 0);\r
- signal buf_APL_READ_IN : std_logic_vector(3 downto 0);\r
- signal buf_APL_TYP_OUT : std_logic_vector(4*3-1 downto 0);\r
- signal buf_APL_RUN_OUT : std_logic_vector(3 downto 0);\r
- signal buf_APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0);\r
- signal buf_APL_LENGTH_IN : std_logic_vector(16*4-1 downto 0);\r
-\r
- signal MY_ADDRESS : std_logic_vector(15 downto 0);\r
-\r
- signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0);\r
- signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0);\r
- signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);\r
- signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0);\r
- signal buf_STAT_INIT_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0);\r
- signal buf_STAT_REPLY_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0);\r
-\r
- signal REGIO_REGIO_STAT : std_logic_vector(31 downto 0);\r
-\r
- signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);\r
- signal buf_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
-\r
- signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0);\r
- signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0);\r
- signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0);\r
- signal buf_IDRAM_WR_IN : std_logic;\r
- signal reset_no_link : std_logic;\r
- signal ONEWIRE_DATA : std_logic_vector(15 downto 0);\r
- signal ONEWIRE_ADDR : std_logic_vector(2 downto 0);\r
- signal ONEWIRE_WRITE : std_logic;\r
-\r
- signal buf_COMMON_STAT_REG_STROBE : std_logic_vector((std_COMSTATREG)-1 downto 0);\r
- signal buf_COMMON_CTRL_REG_STROBE : std_logic_vector((std_COMCTRLREG)-1 downto 0);\r
- signal buf_STAT_REG_STROBE : std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
- signal buf_CTRL_REG_STROBE : std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- signal int_trigger_num : std_logic_vector(15 downto 0);\r
-\r
- signal buf_LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0);\r
- signal buf_LVL1_TRG_RECEIVED_OUT : std_logic;\r
- signal buf_LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);\r
- signal buf_LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0);\r
- signal buf_LVL1_TRG_INFORMATION_OUT : std_logic_vector(23 downto 0);\r
- signal last_LVL1_TRG_RECEIVED_OUT : std_logic;\r
- signal LVL1_TRG_RECEIVED_OUT_rising : std_logic;\r
- signal LVL1_TRG_RECEIVED_OUT_falling: std_logic;\r
- signal buf_LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);\r
-\r
- signal temperature : std_logic_vector(11 downto 0);\r
- signal got_timing_trigger : std_logic;\r
- signal got_timingless_trigger : std_logic;\r
- signal trigger_number_match : std_logic;\r
- signal buf_TIMER_TICKS_OUT : std_logic_vector(1 downto 0);\r
--- signal timing_trigger_missing : std_logic;\r
-\r
- signal buf_LVL1_VALID_TIMING_TRG_OUT : std_logic;\r
- signal buf_LVL1_VALID_NOTIMING_TRG_OUT : std_logic;\r
- signal buf_LVL1_INVALID_TRG_OUT : std_logic;\r
- signal buf_LVL1_TRG_RELEASE_IN : std_logic;\r
- signal buf_LVL1_TRG_DATA_VALID_OUT : std_logic;\r
-\r
- signal int_lvl1_delay : std_logic_vector(15 downto 0);\r
- signal int_trg_reset : std_logic;\r
- signal reset_trg_logic : std_logic;\r
- signal stat_lvl1_handler : std_logic_vector(63 downto 0);\r
- signal stat_counters_lvl1_handler: std_logic_vector(79 downto 0);\r
- signal trg_invert_i : std_logic;\r
- signal int_multiple_trg : std_logic;\r
- signal int_lvl1_timeout_detected : std_logic;\r
- signal int_lvl1_spurious_trg : std_logic;\r
- signal int_lvl1_missing_tmg_trg : std_logic;\r
- signal int_spike_detected : std_logic;\r
- signal int_lvl1_long_trg : std_logic;\r
-\r
-\r
- signal last_TRG_TIMING_TRG_RECEIVED_IN : std_logic;\r
- signal last_timingtrg_counter_write : std_logic;\r
- signal last_timingtrg_counter_read : std_logic;\r
-\r
- signal reg_timing_trigger : std_logic;\r
- signal trigger_timing_rising : std_logic;\r
- signal last_reg_timing_trigger : std_logic;\r
--- signal timing_trigger_missing_stat : std_logic;\r
-\r
- signal link_error_i : std_logic;\r
- signal link_and_reset_status : std_logic_vector(31 downto 0);\r
-\r
- signal make_trbnet_reset : std_logic;\r
- signal last_make_trbnet_reset : std_logic;\r
- signal lvl1_tmg_trg_missing_flag : std_logic;\r
-\r
- component edge_to_pulse is\r
- port (\r
- clock : in std_logic;\r
- en_clk : in std_logic;\r
- signal_in : in std_logic;\r
- pulse : out std_logic);\r
- end component;\r
-\r
-begin\r
-\r
- process(CLK)\r
- begin\r
- if rising_edge(CLK) then\r
- reset_no_link <= MED_STAT_OP_IN(14) or RESET;\r
- reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1);\r
- end if;\r
- end process;\r
-\r
- MED_CTRL_OP_OUT(7 downto 0) <= (others => '0');\r
- MED_CTRL_OP_OUT(8) <= buf_REGIO_COMMON_CTRL_REG_OUT(64+27);\r
- MED_CTRL_OP_OUT(15 downto 9) <= (others => '0');\r
- MED_STAT_OP <= MED_STAT_OP_IN;\r
-\r
- --Connections for data channel\r
- genbuffers : for i in 0 to 3 generate\r
- geniobuf: if USE_CHANNEL(i) = c_YES generate\r
- IOBUF: trb_net16_iobuf\r
- generic map (\r
- IBUF_DEPTH => IBUF_DEPTH(i),\r
- IBUF_SECURE_MODE => IBUF_SECURE_MODE(i),\r
- SBUF_VERSION => 0,\r
- SBUF_VERSION_OBUF => 6,\r
- OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH,\r
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i),\r
- USE_CHECKSUM => USE_CHECKSUM(i),\r
- USE_VENDOR_CORES => c_YES,\r
- INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA(i),\r
- REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i),\r
- REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA(i)\r
- )\r
- port map (\r
- -- Misc\r
- CLK => CLK ,\r
- RESET => reset_no_link,\r
- CLK_EN => CLK_EN,\r
- -- Media direction port\r
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),\r
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),\r
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),\r
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),\r
-\r
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),\r
- MED_DATA_IN => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- MED_READ_OUT => MED_IO_READ_OUT(i),\r
- MED_ERROR_IN => MED_STAT_OP_IN(2 downto 0),\r
-\r
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),\r
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),\r
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),\r
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1),\r
-\r
- -- Internal direction port\r
-\r
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),\r
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_INIT_READ_IN => buf_to_apl_INIT_READ(i),\r
-\r
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i),\r
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i),\r
-\r
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),\r
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i),\r
-\r
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i),\r
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i),\r
-\r
- -- Status and control port\r
- STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32),\r
- STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32),\r
- CTRL_GEN => buf_CTRL_GEN(32*(i+1)-1 downto i*32),\r
- STAT_INIT_OBUF_DEBUG => buf_STAT_INIT_OBUF_DEBUG(32*(i+1)-1 downto i*32),\r
- STAT_REPLY_OBUF_DEBUG => buf_STAT_REPLY_OBUF_DEBUG(32*(i+1)-1 downto i*32),\r
- TIMER_TICKS_IN => buf_TIMER_TICKS_OUT,\r
- CTRL_STAT => x"0000"\r
- );\r
-\r
- gen_api : if i /= c_TRG_LVL1_CHANNEL generate\r
- constant j : integer := i;\r
- begin\r
- DAT_PASSIVE_API: trb_net16_api_base\r
- generic map (\r
- API_TYPE => c_API_PASSIVE,\r
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i),\r
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i),\r
- FORCE_REPLY => cfg_FORCE_REPLY(i),\r
- SBUF_VERSION => 0,\r
- USE_VENDOR_CORES => c_YES,\r
- SECURE_MODE_TO_APL => API_SECURE_MODE_TO_APL(i),\r
- SECURE_MODE_TO_INT => API_SECURE_MODE_TO_INT(i),\r
- APL_WRITE_ALL_WORDS=> APL_WRITE_ALL_WORDS(i),\r
- ADDRESS_MASK => ADDRESS_MASK,\r
- BROADCAST_BITMASK => BROADCAST_BITMASK,\r
- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR\r
- )\r
- port map (\r
- -- Misc\r
- CLK => CLK,\r
- RESET => RESET,\r
- CLK_EN => CLK_EN,\r
- -- APL Transmitter port\r
- APL_DATA_IN => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),\r
- APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),\r
- APL_DATAREADY_IN => buf_APL_DATAREADY_IN(j),\r
- APL_READ_OUT => buf_APL_READ_OUT(j),\r
- APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j),\r
- APL_DTYPE_IN => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4),\r
- APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32),\r
- APL_SEND_IN => buf_APL_SEND_IN(j),\r
- APL_TARGET_ADDRESS_IN => (others => '0'),\r
- -- Receiver port\r
- APL_DATA_OUT => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),\r
- APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),\r
- APL_TYP_OUT => buf_APL_TYP_OUT((j+1)*3-1 downto j*3),\r
- APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j),\r
- APL_READ_IN => buf_APL_READ_IN(j),\r
- -- APL Control port\r
- APL_RUN_OUT => buf_APL_RUN_OUT(j),\r
- APL_MY_ADDRESS_IN => MY_ADDRESS,\r
- APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8),\r
- APL_LENGTH_IN => buf_APL_LENGTH_IN((j+1)*16-1 downto j*16),\r
- -- Internal direction port\r
- INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),\r
- INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i),\r
- INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),\r
- INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i),\r
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),\r
- INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i),\r
- INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),\r
- INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i),\r
- -- Status and control port\r
- CTRL_SEQNR_RESET => buf_REGIO_COMMON_CTRL_REG_OUT(10),\r
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),\r
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)\r
- );\r
- end generate;\r
-\r
- gentrgapi : if i = c_TRG_LVL1_CHANNEL generate\r
- buf_APL_READ_OUT(i) <= '0';\r
- buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');\r
- buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');\r
- buf_APL_DATAREADY_OUT(i) <= '0';\r
- buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0');\r
- buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
- buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0');\r
- buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');\r
- buf_APL_RUN_OUT(i) <= '0';\r
- buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0');\r
- buf_APL_READ_IN(i) <= '0';\r
- buf_APL_SHORT_TRANSFER_IN(i) <= '0';\r
- buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0');\r
- buf_APL_DATAREADY_IN(i) <= '0';\r
- buf_APL_SEND_IN(i) <= '0';\r
- buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
-\r
- apl_to_buf_INIT_DATAREADY(i) <= '0';\r
- apl_to_buf_INIT_DATA((i+1)*16-1 downto i*16) <= (others => '0');\r
- apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
- apl_to_buf_INIT_READ(i) <= '0';\r
-\r
- buf_to_apl_REPLY_READ(i) <= '1';\r
- buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
- buf_to_apl_REPLY_DATAREADY(i) <= '0';\r
- buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');\r
-\r
- buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0');\r
- buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0');\r
-\r
-\r
- the_trigger_apl : trb_net16_trigger\r
- generic map(\r
- USE_TRG_PORT => c_YES,\r
- SECURE_MODE => std_TERM_SECURE_MODE\r
- )\r
- port map(\r
- -- Misc\r
- CLK => CLK,\r
- RESET => RESET,\r
- CLK_EN => CLK_EN,\r
- INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),\r
- INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_READ_IN => apl_to_buf_REPLY_READ(i),\r
- INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),\r
- INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- INT_READ_OUT => buf_to_apl_INIT_READ(i),\r
- TRG_RECEIVED_OUT => buf_LVL1_TRG_RECEIVED_OUT,\r
- TRG_TYPE_OUT => buf_LVL1_TRG_TYPE_OUT,\r
- TRG_NUMBER_OUT => buf_LVL1_TRG_NUMBER_OUT,\r
- TRG_CODE_OUT => buf_LVL1_TRG_CODE_OUT,\r
- TRG_INFORMATION_OUT => buf_LVL1_TRG_INFORMATION_OUT,\r
- TRG_RELEASE_IN => buf_LVL1_TRG_RELEASE_IN,\r
- TRG_ERROR_PATTERN_IN => buf_LVL1_ERROR_PATTERN_IN\r
- );\r
- end generate;\r
-\r
- gen_ipu_apl : if i = c_DATA_CHANNEL generate\r
- the_ipudata_apl : trb_net16_ipudata\r
- port map(\r
- CLK => CLK,\r
- RESET => RESET,\r
- CLK_EN => CLK_EN,\r
- API_DATA_OUT => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- API_DATAREADY_OUT => buf_APL_DATAREADY_IN(i),\r
- API_READ_IN => buf_APL_READ_OUT(i),\r
- API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i),\r
- API_DTYPE_OUT => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),\r
- API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),\r
- API_SEND_OUT => buf_APL_SEND_IN(i),\r
- API_DATA_IN => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- API_TYP_IN => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),\r
- API_DATAREADY_IN => buf_APL_DATAREADY_OUT(i),\r
- API_READ_OUT => buf_APL_READ_IN(i),\r
- API_RUN_IN => buf_APL_RUN_OUT(i),\r
- API_SEQNR_IN => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),\r
- API_LENGTH_OUT => buf_APL_LENGTH_IN((i+1)*16-1 downto i*16),\r
- MY_ADDRESS_IN => MY_ADDRESS,\r
- --Information received with request\r
- IPU_NUMBER_OUT => IPU_NUMBER_OUT,\r
- IPU_READOUT_TYPE_OUT => IPU_READOUT_TYPE_OUT,\r
- IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,\r
- --start strobe\r
- IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,\r
- --detector data, equipped with DHDR\r
- IPU_DATA_IN => IPU_DATA_IN,\r
- IPU_DATAREADY_IN => IPU_DATAREADY_IN,\r
- --no more data, end transfer, send TRM\r
- IPU_READOUT_FINISHED_IN=> IPU_READOUT_FINISHED_IN,\r
- --will be low every second cycle due to 32bit -> 16bit conversion\r
- IPU_READ_OUT => IPU_READ_OUT,\r
- IPU_LENGTH_IN => IPU_LENGTH_IN,\r
- IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,\r
- STAT_DEBUG => STAT_DEBUG_IPU\r
- );\r
- end generate;\r
-\r
- gen_regio : if i = c_SLOW_CTRL_CHANNEL generate\r
- buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');\r
-\r
- regIO : trb_net16_regIO\r
- generic map(\r
- NUM_STAT_REGS => REGIO_NUM_STAT_REGS,\r
- NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,\r
- --standard values for output registers\r
- INIT_CTRL_REGS => REGIO_INIT_CTRL_REGS,\r
- --set to 0 for unused ctrl registers to save resources\r
- USED_CTRL_REGS => REGIO_USED_CTRL_REGS,\r
- --set to 0 for each unused bit in a register\r
- USED_CTRL_BITMASK => REGIO_USED_CTRL_BITMASK,\r
- --no data / address out?\r
- USE_DAT_PORT => REGIO_USE_DAT_PORT,\r
- INIT_ADDRESS => REGIO_INIT_ADDRESS,\r
- INIT_UNIQUE_ID => REGIO_INIT_UNIQUE_ID,\r
- INIT_ENDPOINT_ID => REGIO_INIT_ENDPOINT_ID,\r
- COMPILE_TIME => REGIO_COMPILE_TIME,\r
- COMPILE_VERSION => REGIO_COMPILE_VERSION,\r
- HARDWARE_VERSION => REGIO_HARDWARE_VERSION,\r
- CLOCK_FREQ => CLOCK_FREQUENCY\r
- )\r
- port map(\r
- -- Misc\r
- CLK => CLK,\r
- RESET => RESET,\r
- CLK_EN => CLK_EN,\r
- -- Port to API\r
- API_DATA_OUT => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- API_DATAREADY_OUT => buf_APL_DATAREADY_IN(i),\r
- API_READ_IN => buf_APL_READ_OUT(i),\r
- API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i),\r
- API_DTYPE_OUT => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),\r
- API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),\r
- API_SEND_OUT => buf_APL_SEND_IN(3),\r
- API_DATA_IN => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- API_TYP_IN => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),\r
- API_DATAREADY_IN => buf_APL_DATAREADY_OUT(i),\r
- API_READ_OUT => buf_APL_READ_IN(i),\r
- API_RUN_IN => buf_APL_RUN_OUT(i),\r
- API_SEQNR_IN => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),\r
- --Port to write Unique ID\r
- IDRAM_DATA_IN => buf_IDRAM_DATA_IN,\r
- IDRAM_DATA_OUT => buf_IDRAM_DATA_OUT,\r
- IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN,\r
- IDRAM_WR_IN => buf_IDRAM_WR_IN,\r
- MY_ADDRESS_OUT => MY_ADDRESS,\r
- TRIGGER_MONITOR => buf_LVL1_VALID_TIMING_TRG_OUT,\r
- GLOBAL_TIME => GLOBAL_TIME_OUT,\r
- LOCAL_TIME => LOCAL_TIME_OUT,\r
- TIME_SINCE_LAST_TRG => TIME_SINCE_LAST_TRG_OUT,\r
- TIMER_US_TICK => buf_TIMER_TICKS_OUT(0),\r
- TIMER_MS_TICK => buf_TIMER_TICKS_OUT(1),\r
- --Common Register in / out\r
- COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN,\r
- COMMON_CTRL_REG_OUT => buf_REGIO_COMMON_CTRL_REG_OUT,\r
- --Custom Register in / out\r
- REGISTERS_IN => REGIO_REGISTERS_IN,\r
- REGISTERS_OUT => REGIO_REGISTERS_OUT,\r
- COMMON_STAT_REG_STROBE => buf_COMMON_STAT_REG_STROBE,\r
- COMMON_CTRL_REG_STROBE => buf_COMMON_CTRL_REG_STROBE,\r
- STAT_REG_STROBE => buf_STAT_REG_STROBE,\r
- CTRL_REG_STROBE => buf_CTRL_REG_STROBE,\r
- --following ports only used when no internal register is accessed\r
- DAT_ADDR_OUT => REGIO_ADDR_OUT,\r
- DAT_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,\r
- DAT_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,\r
- DAT_DATA_OUT => REGIO_DATA_OUT,\r
- DAT_DATA_IN => REGIO_DATA_IN,\r
- DAT_DATAREADY_IN => REGIO_DATAREADY_IN,\r
- DAT_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,\r
- DAT_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,\r
- DAT_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,\r
- DAT_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,\r
- STAT => REGIO_REGIO_STAT,\r
- STAT_ADDR_DEBUG => STAT_ADDR_DEBUG\r
- );\r
- gen_no1wire : if REGIO_USE_1WIRE_INTERFACE = c_NO generate\r
- ONEWIRE_DATA <= REGIO_IDRAM_DATA_IN;\r
- ONEWIRE_ADDR <= REGIO_IDRAM_ADDR_IN;\r
- ONEWIRE_WRITE <= REGIO_IDRAM_WR_IN;\r
- REGIO_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;\r
- REGIO_ONEWIRE_INOUT <= '0';\r
- REGIO_ONEWIRE_MONITOR_OUT <= '0';\r
-\r
- end generate;\r
- gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate\r
-\r
-\r
- REGIO_IDRAM_DATA_OUT <= (others => '0');\r
-\r
- onewire_interface : trb_net_onewire\r
- generic map(\r
- USE_TEMPERATURE_READOUT => c_YES,\r
- CLK_PERIOD => 10\r
- )\r
- port map(\r
- CLK => CLK,\r
- RESET => RESET,\r
- --connection to 1-wire interface\r
- ONEWIRE => REGIO_ONEWIRE_INOUT,\r
- MONITOR_OUT => REGIO_ONEWIRE_MONITOR_OUT,\r
- --connection to id ram, according to memory map in TrbNetRegIO\r
- DATA_OUT => ONEWIRE_DATA,\r
- ADDR_OUT => ONEWIRE_ADDR,\r
- WRITE_OUT=> ONEWIRE_WRITE,\r
- TEMP_OUT => temperature,\r
- STAT => STAT_ONEWIRE\r
- );\r
- end generate;\r
- gen_1wire_monitor : if REGIO_USE_1WIRE_INTERFACE = c_MONITOR generate\r
- REGIO_IDRAM_DATA_OUT <= (others => '0');\r
- REGIO_ONEWIRE_MONITOR_OUT <= '0';\r
-\r
- onewire_interface : trb_net_onewire_listener\r
- port map(\r
- CLK => CLK,\r
- CLK_EN => CLK_EN,\r
- RESET => RESET,\r
- --connection to 1-wire interface\r
- MONITOR_IN => REGIO_ONEWIRE_MONITOR_IN,\r
- --connection to id ram, according to memory map in TrbNetRegIO\r
- DATA_OUT => ONEWIRE_DATA,\r
- ADDR_OUT => ONEWIRE_ADDR,\r
- WRITE_OUT=> ONEWIRE_WRITE,\r
- TEMP_OUT => temperature,\r
- STAT => STAT_ONEWIRE\r
- );\r
- end generate;\r
- end generate;\r
- end generate;\r
- gentermbuf: if USE_CHANNEL(i) = c_NO generate\r
- buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');\r
- buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
- buf_APL_READ_OUT(i) <= '0';\r
- buf_APL_DATAREADY_OUT(i) <= '0';\r
- buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');\r
- buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0');\r
- buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
- buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0');\r
- buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');\r
- buf_APL_RUN_OUT(i) <= '0';\r
- buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0');\r
- buf_APL_READ_IN(i) <= '0';\r
- buf_APL_SHORT_TRANSFER_IN(i) <= '0';\r
- buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0');\r
- buf_APL_DATAREADY_IN(i) <= '0';\r
- buf_APL_SEND_IN(i) <= '0';\r
-\r
- apl_to_buf_INIT_READ(i) <= '0';\r
- apl_to_buf_INIT_DATAREADY(i) <= '0';\r
- apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');\r
- apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
- apl_to_buf_REPLY_DATAREADY(i) <= '0';\r
- apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');\r
- apl_to_buf_REPLY_READ(i) <= '0';\r
- apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
-\r
- buf_to_apl_INIT_READ(i) <= '0';\r
- buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
- buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');\r
- buf_to_apl_INIT_DATAREADY(i) <= '0';\r
- buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');\r
- buf_to_apl_REPLY_DATAREADY(i) <= '0';\r
- buf_to_apl_REPLY_READ(i) <= '0';\r
- buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');\r
-\r
- buf_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');\r
- buf_STAT_GEN((i+1)*32-1 downto i*32) <= (others => '0');\r
- buf_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');\r
- buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0');\r
- buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0');\r
- buf_STAT_INIT_BUFFER((i+1)*32-1 downto i*32) <= (others => '0');\r
-\r
- termbuf: trb_net16_term_buf\r
- port map(\r
- CLK => CLK,\r
- RESET => reset_no_link,\r
- CLK_EN => CLK_EN,\r
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),\r
- MED_DATA_IN => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),\r
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),\r
- MED_READ_OUT => MED_IO_READ_OUT(i),\r
-\r
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),\r
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),\r
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),\r
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),\r
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),\r
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),\r
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),\r
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1)\r
- );\r
- end generate;\r
- end generate;\r
-\r
-\r
- MPLEX: trb_net16_io_multiplexer\r
- generic map(\r
- USE_INPUT_SBUF => (1,1,1,1,0,0,1,1)\r
- )\r
- port map (\r
- CLK => CLK,\r
- RESET => reset_no_link,\r
- CLK_EN => CLK_EN,\r
- MED_DATAREADY_IN => MED_DATAREADY_IN,\r
- MED_DATA_IN => MED_DATA_IN,\r
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,\r
- MED_READ_OUT => MED_READ_OUT,\r
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,\r
- MED_DATA_OUT => MED_DATA_OUT,\r
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,\r
- MED_READ_IN => MED_READ_IN,\r
- INT_DATAREADY_OUT => MED_IO_DATAREADY_IN,\r
- INT_DATA_OUT => MED_IO_DATA_IN,\r
- INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN,\r
- INT_READ_IN => MED_IO_READ_OUT,\r
- INT_DATAREADY_IN => MED_IO_DATAREADY_OUT,\r
- INT_DATA_IN => MED_IO_DATA_OUT,\r
- INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT,\r
- INT_READ_OUT => MED_IO_READ_IN,\r
- STAT => open,\r
- CTRL => CTRL_MPLEX\r
- );\r
-\r
--------------------------------------------------\r
--- Include variable Endpoint ID\r
--------------------------------------------------\r
- gen_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_YES generate\r
- buf_IDRAM_DATA_IN <= REGIO_VAR_ENDPOINT_ID when RESET = '1' else ONEWIRE_DATA;\r
- buf_IDRAM_ADDR_IN <= "100" when RESET = '1' else ONEWIRE_ADDR;\r
- buf_IDRAM_WR_IN <= '1' when RESET = '1' else ONEWIRE_WRITE;\r
- end generate;\r
-\r
- gen_no_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_NO generate\r
- buf_IDRAM_DATA_IN <= ONEWIRE_DATA;\r
- buf_IDRAM_ADDR_IN <= ONEWIRE_ADDR;\r
- buf_IDRAM_WR_IN <= ONEWIRE_WRITE;\r
- end generate;\r
-\r
-\r
-\r
--------------------------------------------------\r
--- Common Status Register\r
--------------------------------------------------\r
- proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num,\r
- link_error_i, link_and_reset_status, stat_lvl1_handler)\r
- begin\r
- buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN;\r
- buf_COMMON_STAT_REG_IN(4) <= stat_lvl1_handler(12);\r
- buf_COMMON_STAT_REG_IN(8) <= lvl1_tmg_trg_missing_flag;\r
- buf_COMMON_STAT_REG_IN(13) <= stat_lvl1_handler(7);\r
- buf_COMMON_STAT_REG_IN(15) <= link_error_i;\r
- if REGIO_USE_1WIRE_INTERFACE = c_YES then\r
- buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature;\r
- end if;\r
- buf_COMMON_STAT_REG_IN(47 downto 32) <= int_trigger_num;\r
- buf_COMMON_STAT_REG_IN(127 downto 64) <= stat_lvl1_handler;\r
- buf_COMMON_STAT_REG_IN(159 downto 128) <= link_and_reset_status(31 downto 0);\r
- buf_COMMON_STAT_REG_IN(175 downto 160) <= buf_LVL1_TRG_INFORMATION_OUT(15 downto 0);\r
- buf_COMMON_STAT_REG_IN(179 downto 176) <= buf_LVL1_TRG_TYPE_OUT;\r
- buf_COMMON_STAT_REG_IN(183 downto 180) <= buf_LVL1_TRG_NUMBER_OUT(3 downto 0);\r
- buf_COMMON_STAT_REG_IN(191 downto 184) <= buf_LVL1_TRG_CODE_OUT;\r
- buf_COMMON_STAT_REG_IN(271 downto 192) <= stat_counters_lvl1_handler;\r
- buf_COMMON_STAT_REG_IN(287 downto 272) <= (others => '0');\r
- end process;\r
-\r
-\r
-\r
- REG_LINK_ERROR : process(CLK)\r
- begin\r
- if rising_edge(CLK) then\r
- if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then\r
- link_error_i <= '0';\r
- elsif MED_STAT_OP_IN(15) = '0' and MED_STAT_OP_IN(13) = '0' and MED_STAT_OP_IN(7 downto 4) = "0111" then\r
- link_error_i <= '1';\r
- end if;\r
-\r
- if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then\r
- lvl1_tmg_trg_missing_flag <= '0';\r
- elsif int_lvl1_missing_tmg_trg = '1' or int_lvl1_spurious_trg = '1' or int_spike_detected = '1' then\r
- lvl1_tmg_trg_missing_flag <= '1';\r
- end if;\r
-\r
--- if LVL1_TRG_RECEIVED_OUT_falling = '1' then\r
--- timing_trigger_missing_stat <= timing_trigger_missing;\r
--- end if;\r
-\r
- if make_trbnet_reset = '1' then\r
- link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + '1';\r
- end if;\r
-\r
- if MED_STAT_OP_IN(12) = '1' then\r
- link_and_reset_status(31 downto 24) <= link_and_reset_status(31 downto 24) + '1';\r
- end if;\r
-\r
- if MED_STAT_OP_IN(8) = '1' then\r
- link_and_reset_status(23 downto 16) <= link_and_reset_status(23 downto 16) + '1';\r
- end if;\r
-\r
- if buf_REGIO_COMMON_CTRL_REG_OUT(5) = '1' then\r
- link_and_reset_status <= (others => '0');\r
- end if;\r
-\r
- end if;\r
- end process;\r
-\r
- PROC_FIND_TRBNET_RESET : process(CLK)\r
- begin\r
- if rising_edge(CLK) then\r
- last_make_trbnet_reset <= MED_STAT_OP_IN(13);\r
- make_trbnet_reset <= MED_STAT_OP_IN(13) and not last_make_trbnet_reset;\r
- end if;\r
- end process;\r
-\r
--------------------------------------------------\r
--- Check LVL1 trigger number\r
--------------------------------------------------\r
-\r
- THE_LVL1_HANDLER : handler_lvl1\r
- generic map (\r
- TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW\r
- )\r
- port map(\r
- RESET => reset_trg_logic,\r
- RESET_FLAGS_IN => buf_REGIO_COMMON_CTRL_REG_OUT(4),\r
- RESET_STATS_IN => buf_REGIO_COMMON_CTRL_REG_OUT(5),\r
- CLOCK => CLK,\r
- --Timing Trigger\r
- LVL1_TIMING_TRG_IN => TRG_TIMING_TRG_RECEIVED_IN,\r
- LVL1_PSEUDO_TMG_TRG_IN => buf_REGIO_COMMON_CTRL_REG_OUT(16),\r
- --LVL1_handler connection\r
- LVL1_TRG_RECEIVED_IN => buf_LVL1_TRG_RECEIVED_OUT,\r
- LVL1_TRG_TYPE_IN => buf_LVL1_TRG_TYPE_OUT,\r
- LVL1_TRG_NUMBER_IN => buf_LVL1_TRG_NUMBER_OUT,\r
- LVL1_TRG_CODE_IN => buf_LVL1_TRG_CODE_OUT,\r
- LVL1_TRG_INFORMATION_IN => buf_LVL1_TRG_INFORMATION_OUT,\r
- LVL1_ERROR_PATTERN_OUT => buf_LVL1_ERROR_PATTERN_IN,\r
- LVL1_TRG_RELEASE_OUT => buf_LVL1_TRG_RELEASE_IN,\r
-\r
- LVL1_INT_TRG_NUMBER_OUT => int_trigger_num,\r
- LVL1_INT_TRG_LOAD_IN => buf_COMMON_CTRL_REG_STROBE(1),\r
- LVL1_INT_TRG_COUNTER_IN => buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32),\r
-\r
- --FEE logic / Data Handler\r
- LVL1_TRG_DATA_VALID_OUT => buf_LVL1_TRG_DATA_VALID_OUT,\r
- LVL1_VALID_TIMING_TRG_OUT => buf_LVL1_VALID_TIMING_TRG_OUT,\r
- LVL1_VALID_NOTIMING_TRG_OUT => buf_LVL1_VALID_NOTIMING_TRG_OUT,\r
- LVL1_INVALID_TRG_OUT => buf_LVL1_INVALID_TRG_OUT,\r
- LVL1_MULTIPLE_TRG_OUT => int_multiple_trg,\r
- LVL1_DELAY_OUT => int_lvl1_delay,\r
- LVL1_TIMEOUT_DETECTED_OUT => int_lvl1_timeout_detected,\r
- LVL1_SPURIOUS_TRG_OUT => int_lvl1_spurious_trg,\r
- LVL1_MISSING_TMG_TRG_OUT => int_lvl1_missing_tmg_trg,\r
- LVL1_LONG_TRG_OUT => int_lvl1_long_trg,\r
- SPIKE_DETECTED_OUT => int_spike_detected,\r
-\r
- LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,\r
- LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,\r
-\r
- --Stat/Control\r
- STATUS_OUT => stat_lvl1_handler,\r
- TRG_ENABLE_IN => buf_REGIO_COMMON_CTRL_REG_OUT(95),\r
- TRG_INVERT_IN => buf_REGIO_COMMON_CTRL_REG_OUT(93),\r
- COUNTERS_STATUS_OUT => stat_counters_lvl1_handler,\r
- --Debug\r
- DEBUG_OUT => DEBUG_LVL1_HANDLER_OUT\r
- );\r
-\r
- TRG_SPIKE_DETECTED_OUT <= int_spike_detected;\r
- TRG_SPURIOUS_TRG_OUT <= int_lvl1_spurious_trg;\r
- TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;\r
- TRG_MULTIPLE_TRG_OUT <= int_multiple_trg;\r
- TRG_MISSING_TMG_TRG_OUT <= int_lvl1_missing_tmg_trg;\r
- TRG_LONG_TRG_OUT <= int_lvl1_long_trg;\r
-\r
- \r
-\r
--- THE_TRG_SYNC : signal_sync\r
--- generic map(\r
--- DEPTH => 2,\r
--- WIDTH => 1\r
--- )\r
--- port map(\r
--- RESET => RESET,\r
--- D_IN(0) => TRG_TIMING_TRG_RECEIVED_IN,\r
--- CLK0 => CLK,\r
--- CLK1 => CLK,\r
--- D_OUT(0) => reg_timing_trigger\r
--- );\r
---\r
---\r
---\r
---\r
--- proc_internal_trigger_number : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if reset_no_link = '1' then\r
--- int_trigger_num <= (others => '0');\r
--- elsif LVL1_TRG_RECEIVED_OUT_falling = '1' then\r
--- int_trigger_num <= int_trigger_num + 1;\r
--- elsif buf_COMMON_CTRL_REG_STROBE(1) = '1' then\r
--- int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32);\r
--- end if;\r
--- end if;\r
--- end process;\r
---\r
--- proc_check_trigger_number : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then\r
--- trigger_number_match <= '1';\r
--- elsif LVL1_TRG_RECEIVED_OUT_rising = '1' then\r
--- if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT then\r
--- trigger_number_match <= '1';\r
--- else\r
--- trigger_number_match <= '0';\r
--- end if;\r
--- end if;\r
--- end if;\r
--- end process;\r
---\r
---\r
--- proc_detect_trigger_receive : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- last_reg_timing_trigger <= reg_timing_trigger;\r
--- trigger_timing_rising <= reg_timing_trigger and not last_reg_timing_trigger; -- and buf_REGIO_COMMON_CTRL_REG_OUT(95);\r
---\r
--- last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT;\r
--- LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT;\r
--- LVL1_TRG_RECEIVED_OUT_falling <= not buf_LVL1_TRG_RECEIVED_OUT and last_LVL1_TRG_RECEIVED_OUT;\r
---\r
--- if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then\r
--- got_timing_trigger <= '0';\r
--- got_timingless_trigger <= '0';\r
--- timing_trigger_missing <= '0';\r
--- elsif trigger_timing_rising = '1' then --TRG_TIMING_TRG_RECEIVED_IN\r
--- got_timing_trigger <= '1';\r
--- elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then\r
--- got_timingless_trigger <= '1';\r
--- elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and not (buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') and got_timing_trigger = '0') then\r
--- timing_trigger_missing <= '1';\r
--- end if;\r
--- end if;\r
--- end process;\r
---\r
---\r
--- proc_gen_lvl1_error_pattern : process(LVL1_ERROR_PATTERN_IN, trigger_number_match, got_timing_trigger,got_timingless_trigger )\r
--- begin\r
--- buf_LVL1_ERROR_PATTERN_IN <= LVL1_ERROR_PATTERN_IN;\r
--- buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match or LVL1_ERROR_PATTERN_IN(16);\r
--- buf_LVL1_ERROR_PATTERN_IN(17) <= (not got_timing_trigger and not got_timingless_trigger) or LVL1_ERROR_PATTERN_IN(17);\r
--- end process;\r
---\r
--- buf_LVL1_VALID_TIMING_TRG_OUT <= trigger_timing_rising; --TRG_TIMING_TRG_RECEIVED_IN;\r
--- buf_LVL1_VALID_NOTIMING_TRG_OUT <= LVL1_TRG_RECEIVED_OUT_rising and not got_timing_trigger\r
--- and buf_LVL1_TRG_TYPE_OUT(3) and buf_LVL1_TRG_INFORMATION_OUT(7);\r
--- buf_LVL1_INVALID_TRG_OUT <= '0';\r
-\r
--- proc_count_timing_trg : process(CLK)\r
--- begin\r
--- if rising_edge(CLK) then\r
--- last_TRG_TIMING_TRG_RECEIVED_IN <= TRG_TIMING_TRG_RECEIVED_IN;\r
--- last_timingtrg_counter_write <= timingtrg_counter_write;\r
--- last_timingtrg_counter_read <= timingtrg_counter_read;\r
--- if RESET = '1' or timingtrg_counter_write = '1' then\r
--- timingtrg_counter <= (others => '0');\r
--- elsif TRG_TIMING_TRG_RECEIVED_IN = '1' and last_TRG_TIMING_TRG_RECEIVED_IN = '0' then\r
--- timingtrg_counter <= (others => '0');\r
--- end if;\r
--- end if;\r
--- end process;\r
-\r
-\r
-\r
--------------------------------------------------\r
--- Connect Outputs\r
--------------------------------------------------\r
--- buf_LVL1_TRG_RELEASE_IN <= LVL1_TRG_RELEASE_IN; --changed back\r
--- LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_RECEIVED_OUT; --changed back\r
- LVL1_TRG_DATA_VALID_OUT <= buf_LVL1_TRG_DATA_VALID_OUT; --changed back\r
-\r
- LVL1_TRG_VALID_TIMING_OUT <= buf_LVL1_VALID_TIMING_TRG_OUT;\r
- LVL1_TRG_VALID_NOTIMING_OUT <= buf_LVL1_VALID_NOTIMING_TRG_OUT;\r
- LVL1_TRG_INVALID_OUT <= buf_LVL1_INVALID_TRG_OUT;\r
-\r
- LVL1_TRG_TYPE_OUT <= buf_LVL1_TRG_TYPE_OUT;\r
- LVL1_TRG_NUMBER_OUT <= buf_LVL1_TRG_NUMBER_OUT;\r
- LVL1_TRG_CODE_OUT <= buf_LVL1_TRG_CODE_OUT;\r
- LVL1_TRG_INFORMATION_OUT <= buf_LVL1_TRG_INFORMATION_OUT;\r
- LVL1_INT_TRG_NUMBER_OUT <= int_trigger_num;\r
-\r
- COMMON_STAT_REG_STROBE <= buf_COMMON_STAT_REG_STROBE;\r
- COMMON_CTRL_REG_STROBE <= buf_COMMON_CTRL_REG_STROBE;\r
- STAT_REG_STROBE <= buf_STAT_REG_STROBE;\r
- CTRL_REG_STROBE <= buf_CTRL_REG_STROBE;\r
-\r
- TIMER_TICKS_OUT <= buf_TIMER_TICKS_OUT;\r
-\r
- buf_CTRL_GEN <= IOBUF_CTRL_GEN;\r
- REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT;\r
-\r
- STAT_DEBUG_1 <= REGIO_REGIO_STAT;\r
- STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16);\r
- STAT_DEBUG_2(7 downto 4) <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16);\r
- STAT_DEBUG_2(8) <= apl_to_buf_REPLY_DATAREADY(3);\r
- STAT_DEBUG_2(11 downto 9) <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3);\r
- STAT_DEBUG_2(15 downto 12) <= (others => '0');\r
- STAT_DEBUG_2(31 downto 16) <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32);\r
-\r
- STAT_TRIGGER_OUT <= stat_counters_lvl1_handler;\r
-\r
-end architecture;\r
-\r
+++ /dev/null
--- the full endpoint for HADES: trg, data, unused, regio including data buffer & handling\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-\r
-\r
-entity trb_net16_endpoint_data_concentrator_handler is\r
- generic (\r
- IBUF_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);\r
- APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
- REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0');\r
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
- REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
- CLOCK_FREQUENCY : integer range 1 to 200 := 100;\r
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
- --Configure data handler\r
- DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
- DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;\r
- TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
- HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8\r
- );\r
-\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic := '1';\r
-\r
- -- Media direction port\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN : in std_logic;\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
-\r
- --Timing trigger in\r
- TRG_TIMING_TRG_RECEIVED_IN : in std_logic;\r
- --LVL1 trigger to FEE\r
- LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
- LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received\r
- LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received\r
- LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
-\r
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
-\r
- --Information about trigger handler errors\r
- TRG_MULTIPLE_TRG_OUT : out std_logic;\r
- TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
- TRG_SPURIOUS_TRG_OUT : out std_logic;\r
- TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
- TRG_SPIKE_DETECTED_OUT : out std_logic;\r
-\r
- --Response from FEE\r
- FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
-\r
- --Slow Control Port\r
- --common registers\r
- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
- REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
- REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
- --user defined registers\r
- REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');\r
- REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);\r
- REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
- REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- --internal data port\r
- BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
- BUS_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
- BUS_READ_ENABLE_OUT : out std_logic;\r
- BUS_WRITE_ENABLE_OUT : out std_logic;\r
- BUS_TIMEOUT_OUT : out std_logic;\r
- BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
- BUS_DATAREADY_IN : in std_logic := '0';\r
- BUS_WRITE_ACK_IN : in std_logic := '0';\r
- BUS_NO_MORE_DATA_IN : in std_logic := '0';\r
- BUS_UNKNOWN_ADDR_IN : in std_logic := '0';\r
- --Onewire\r
- ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
- ONEWIRE_MONITOR_IN : in std_logic := '0';\r
- ONEWIRE_MONITOR_OUT : out std_logic;\r
- --Config endpoint id, if not statically assigned\r
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');\r
-\r
- --Timing registers\r
- TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds\r
- TIME_LOCAL_OUT : out std_logic_vector ( 7 downto 0); --local time running with chip frequency\r
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger\r
- TIME_TICKS_OUT : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick\r
-\r
- --Debugging & Status information\r
- STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
- CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
- IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
- STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
- STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
- STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);\r
- DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
- );\r
-end entity;\r
-\r
-\r
-\r
-\r
-\r
-architecture trb_net16_endpoint_data_concentrator_handler_arch of trb_net16_endpoint_data_concentrator_handler is\r
-\r
-component trb_net16_endpoint_data_concentrator is\r
- generic (\r
- USE_CHANNEL : channel_config_t := (c_NO,c_NO,c_NO,c_YES);\r
- IBUF_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);\r
- IBUF_SECURE_MODE : channel_config_t := (c_NO,c_NO,c_NO,c_YES);\r
- API_SECURE_MODE_TO_APL : channel_config_t := (c_NO,c_NO,c_NO,c_YES);\r
- API_SECURE_MODE_TO_INT : channel_config_t := (c_NO,c_NO,c_NO,c_YES);\r
- OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;\r
- INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- REPLY_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_YES);\r
- REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- USE_CHECKSUM : channel_config_t := (c_NO,c_NO,c_NO,c_YES);\r
- APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
- --standard values for output registers\r
- REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
- --set to 0 for unused ctrl registers to save resources\r
- REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');\r
- --set to 0 for each unused bit in a register\r
- REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
- REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
- REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
- REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
- CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
- );\r
-\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic := '1';\r
-\r
- -- Media direction port\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN : in std_logic;\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
-\r
- -- LVL1 trigger APL\r
- TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received or real timing trigger signal\r
-\r
- LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
- LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received\r
- LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received\r
- LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
-\r
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
-\r
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";\r
- LVL1_TRG_RELEASE_IN : in std_logic := '0';\r
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
-\r
- --Information about trigger handler errors\r
- TRG_MULTIPLE_TRG_OUT : out std_logic;\r
- TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
- TRG_SPURIOUS_TRG_OUT : out std_logic;\r
- TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
- TRG_SPIKE_DETECTED_OUT : out std_logic;\r
- TRG_LONG_TRG_OUT : out std_logic;\r
-\r
- --Data Port\r
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
- IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
- --start strobe\r
- IPU_START_READOUT_OUT : out std_logic;\r
- --detector data, equipped with DHDR\r
- IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
- IPU_DATAREADY_IN : in std_logic;\r
- --no more data, end transfer, send TRM\r
- IPU_READOUT_FINISHED_IN : in std_logic;\r
- --will be low every second cycle due to 32bit -> 16bit conversion\r
- IPU_READ_OUT : out std_logic;\r
- IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
- IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
-\r
-\r
- -- Slow Control Data Port\r
- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
- REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
- REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
- COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
- STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
- CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- --following ports only used when using internal data port\r
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
- REGIO_READ_ENABLE_OUT : out std_logic;\r
- REGIO_WRITE_ENABLE_OUT : out std_logic;\r
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
- REGIO_DATAREADY_IN : in std_logic := '0';\r
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
- REGIO_WRITE_ACK_IN : in std_logic := '0';\r
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
- REGIO_TIMEOUT_OUT : out std_logic;\r
- --IDRAM is used if no 1-wire interface, onewire used otherwise\r
- REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
- REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
- REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";\r
- REGIO_IDRAM_WR_IN : in std_logic := '0';\r
- REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
- REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0';\r
- REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
-\r
- GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
- LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
- TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
- --Debugging & Status information\r
- STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
- MED_STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
- IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
- STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
- STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
- STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);\r
- DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
- signal lvl1_data_valid_i : std_logic;\r
- signal lvl1_valid_i : std_logic;\r
- signal lvl1_valid_timing_i : std_logic;\r
- signal lvl1_valid_notiming_i : std_logic;\r
- signal lvl1_invalid_i : std_logic;\r
- signal lvl1_type_i : std_logic_vector ( 3 downto 0);\r
- signal lvl1_number_i : std_logic_vector (15 downto 0);\r
- signal lvl1_code_i : std_logic_vector ( 7 downto 0);\r
- signal lvl1_information_i : std_logic_vector (23 downto 0);\r
- signal lvl1_error_pattern_i : std_logic_vector (31 downto 0);\r
- signal lvl1_release_i : std_logic;\r
- signal lvl1_int_trg_number_i : std_logic_vector (15 downto 0);\r
-\r
- signal ipu_number_i : std_logic_vector (15 downto 0);\r
- signal ipu_readout_type_i : std_logic_vector ( 3 downto 0);\r
- signal ipu_information_i : std_logic_vector ( 7 downto 0);\r
- signal ipu_start_readout_i : std_logic;\r
- signal ipu_data_i : std_logic_vector (31 downto 0);\r
- signal ipu_dataready_i : std_logic;\r
- signal ipu_readout_finished_i : std_logic;\r
- signal ipu_read_i : std_logic;\r
- signal ipu_length_i : std_logic_vector (15 downto 0);\r
- signal ipu_error_pattern_i : std_logic_vector (31 downto 0);\r
- signal reset_ipu_i : std_logic;\r
-\r
- signal common_stat_reg_i : std_logic_vector (std_COMSTATREG*32-1 downto 0);\r
- signal common_ctrl_reg_i : std_logic_vector (std_COMCTRLREG*32-1 downto 0);\r
- signal common_stat_strobe_i : std_logic_vector (std_COMSTATREG-1 downto 0);\r
- signal common_ctrl_strobe_i : std_logic_vector (std_COMCTRLREG-1 downto 0);\r
- signal stat_reg_i : std_logic_vector (2**(REGIO_NUM_STAT_REGS)*32-1 downto 0);\r
- signal ctrl_reg_i : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);\r
- signal stat_strobe_i : std_logic_vector (2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
- signal ctrl_strobe_i : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
-\r
- signal regio_addr_i : std_logic_vector (15 downto 0);\r
- signal regio_read_enable_i : std_logic;\r
- signal regio_write_enable_i : std_logic;\r
- signal regio_data_out_i : std_logic_vector (31 downto 0);\r
- signal regio_data_in_i : std_logic_vector (31 downto 0);\r
- signal regio_dataready_i : std_logic;\r
- signal regio_nomoredata_i : std_logic;\r
- signal regio_write_ack_i : std_logic;\r
- signal regio_unknown_addr_i : std_logic;\r
- signal regio_timeout_i : std_logic;\r
-\r
- signal time_global_i : std_logic_vector (31 downto 0);\r
- signal time_local_i : std_logic_vector ( 7 downto 0);\r
- signal time_since_last_trg_i : std_logic_vector (31 downto 0);\r
- signal time_ticks_i : std_logic_vector ( 1 downto 0);\r
-\r
- signal stat_handler_i : std_logic_vector (127 downto 0);\r
- signal stat_data_buffer_level : std_logic_vector (DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- signal stat_header_buffer_level: std_logic_vector (31 downto 0);\r
-\r
- signal dbuf_read_enable : std_logic;\r
- signal dbuf_addr : std_logic_vector (3 downto 0);\r
- signal dbuf_data_in : std_logic_vector (31 downto 0);\r
- signal dbuf_dataready : std_logic;\r
- signal dbuf_unknown_addr : std_logic;\r
-\r
- signal tbuf_dataready : std_logic;\r
- signal tbuf_read_enable : std_logic;\r
-\r
- signal dummy : std_logic_vector(300 downto 0);\r
- signal write_enable : std_logic_vector(6 downto 0);\r
- signal read_enable : std_logic_vector(6 downto 0);\r
- signal last_write_enable : std_logic_vector(6 downto 0);\r
- signal last_read_enable : std_logic_vector(6 downto 0);\r
-\r
- signal debug_data_handler_i : std_logic_vector(31 downto 0);\r
- signal debug_ipu_handler_i : std_logic_vector(31 downto 0);\r
-\r
- signal int_multiple_trg : std_logic;\r
- signal int_lvl1_timeout_detected : std_logic;\r
- signal int_lvl1_spurious_trg : std_logic;\r
- signal int_lvl1_missing_tmg_trg : std_logic;\r
- signal int_spike_detected : std_logic;\r
- signal int_lvl1_long_trg : std_logic;\r
- signal tmg_trg_error_i : std_logic;\r
-\r
- signal stat_buffer_i : std_logic_vector(31 downto 0);\r
- signal stat_buffer_read : std_logic;\r
- signal stat_buffer_ready : std_logic;\r
- signal stat_buffer_unknown : std_logic;\r
- signal stat_buffer_address : std_logic_vector(4 downto 0);\r
-\r
-\r
-begin\r
----------------------------------------------------------------------------\r
--- TrbNet Endpoint\r
----------------------------------------------------------------------------\r
-\r
- THE_ENDPOINT: trb_net16_endpoint_data_concentrator ---- trb_net16_endpoint_hades_full\r
- generic map(\r
- IBUF_DEPTH => IBUF_DEPTH,\r
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,\r
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,\r
- APL_WRITE_ALL_WORDS => APL_WRITE_ALL_WORDS,\r
- ADDRESS_MASK => ADDRESS_MASK,\r
- BROADCAST_BITMASK => BROADCAST_BITMASK,\r
- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,\r
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,\r
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,\r
- REGIO_INIT_CTRL_REGS => REGIO_INIT_CTRL_REGS,\r
- REGIO_INIT_ADDRESS => REGIO_INIT_ADDRESS,\r
- REGIO_INIT_BOARD_INFO => REGIO_INIT_BOARD_INFO,\r
- REGIO_INIT_ENDPOINT_ID => REGIO_INIT_ENDPOINT_ID,\r
- REGIO_COMPILE_TIME => REGIO_COMPILE_TIME,\r
- REGIO_COMPILE_VERSION => REGIO_COMPILE_VERSION,\r
- REGIO_HARDWARE_VERSION => REGIO_HARDWARE_VERSION,\r
- REGIO_USE_1WIRE_INTERFACE => REGIO_USE_1WIRE_INTERFACE,\r
- REGIO_USE_VAR_ENDPOINT_ID => REGIO_USE_VAR_ENDPOINT_ID,\r
- TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW,\r
- CLOCK_FREQUENCY => CLOCK_FREQUENCY\r
- )\r
- port map(\r
- CLK => CLK,\r
- RESET => RESET,\r
- CLK_EN => CLK_EN,\r
-\r
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,\r
- MED_DATA_OUT => MED_DATA_OUT,\r
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,\r
- MED_READ_IN => MED_READ_IN,\r
- MED_DATAREADY_IN => MED_DATAREADY_IN,\r
- MED_DATA_IN => MED_DATA_IN,\r
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,\r
- MED_READ_OUT => MED_READ_OUT,\r
- MED_STAT_OP_IN => MED_STAT_OP_IN,\r
- MED_CTRL_OP_OUT => MED_CTRL_OP_OUT,\r
-\r
- -- LVL1 trigger APL\r
- TRG_TIMING_TRG_RECEIVED_IN => TRG_TIMING_TRG_RECEIVED_IN,\r
- LVL1_TRG_DATA_VALID_OUT => lvl1_data_valid_i,\r
- LVL1_TRG_VALID_TIMING_OUT => lvl1_valid_timing_i,\r
- LVL1_TRG_VALID_NOTIMING_OUT=> lvl1_valid_notiming_i,\r
- LVL1_TRG_INVALID_OUT => lvl1_invalid_i,\r
- LVL1_TRG_TYPE_OUT => lvl1_type_i,\r
- LVL1_TRG_NUMBER_OUT => lvl1_number_i,\r
- LVL1_TRG_CODE_OUT => lvl1_code_i,\r
- LVL1_TRG_INFORMATION_OUT => lvl1_information_i,\r
- LVL1_ERROR_PATTERN_IN => lvl1_error_pattern_i,\r
- LVL1_TRG_RELEASE_IN => lvl1_release_i,\r
- LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number_i,\r
-\r
- --Information about trigger handler errors\r
- TRG_SPIKE_DETECTED_OUT => int_spike_detected,\r
- TRG_SPURIOUS_TRG_OUT => int_lvl1_spurious_trg,\r
- TRG_TIMEOUT_DETECTED_OUT => int_lvl1_timeout_detected,\r
- TRG_MULTIPLE_TRG_OUT => int_multiple_trg,\r
- TRG_MISSING_TMG_TRG_OUT => int_lvl1_missing_tmg_trg,\r
- TRG_LONG_TRG_OUT => int_lvl1_long_trg,\r
- --Data Port\r
- IPU_NUMBER_OUT => ipu_number_i,\r
- IPU_READOUT_TYPE_OUT => ipu_readout_type_i,\r
- IPU_INFORMATION_OUT => ipu_information_i,\r
- IPU_START_READOUT_OUT => ipu_start_readout_i,\r
- IPU_DATA_IN => ipu_data_i,\r
- IPU_DATAREADY_IN => ipu_dataready_i,\r
- IPU_READOUT_FINISHED_IN => ipu_readout_finished_i,\r
- IPU_READ_OUT => ipu_read_i,\r
- IPU_LENGTH_IN => ipu_length_i,\r
- IPU_ERROR_PATTERN_IN => ipu_error_pattern_i,\r
-\r
- -- Slow Control Data Port\r
- REGIO_COMMON_STAT_REG_IN => common_stat_reg_i,\r
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg_i,\r
- REGIO_REGISTERS_IN => stat_reg_i,\r
- REGIO_REGISTERS_OUT => ctrl_reg_i,\r
- COMMON_STAT_REG_STROBE => common_stat_strobe_i,\r
- COMMON_CTRL_REG_STROBE => common_ctrl_strobe_i,\r
- STAT_REG_STROBE => stat_strobe_i,\r
- CTRL_REG_STROBE => ctrl_strobe_i,\r
-\r
- REGIO_ADDR_OUT => regio_addr_i,\r
- REGIO_READ_ENABLE_OUT => regio_read_enable_i,\r
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_i,\r
- REGIO_DATA_OUT => regio_data_out_i,\r
- REGIO_DATA_IN => regio_data_in_i,\r
- REGIO_DATAREADY_IN => regio_dataready_i,\r
- REGIO_NO_MORE_DATA_IN => regio_nomoredata_i,\r
- REGIO_WRITE_ACK_IN => regio_write_ack_i,\r
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_i,\r
- REGIO_TIMEOUT_OUT => regio_timeout_i,\r
-\r
- REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,\r
- REGIO_ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,\r
- REGIO_ONEWIRE_MONITOR_OUT => ONEWIRE_MONITOR_OUT,\r
- REGIO_VAR_ENDPOINT_ID => REGIO_VAR_ENDPOINT_ID,\r
-\r
- GLOBAL_TIME_OUT => time_global_i,\r
- LOCAL_TIME_OUT => time_local_i,\r
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg_i,\r
- TIMER_TICKS_OUT => time_ticks_i,\r
-\r
- STAT_DEBUG_IPU => open,\r
- STAT_DEBUG_1 => open,\r
- STAT_DEBUG_2 => open,\r
- MED_STAT_OP => open,\r
- CTRL_MPLEX => (others => '0'),\r
- IOBUF_CTRL_GEN => (others => '0'),\r
- STAT_ONEWIRE => open,\r
- STAT_ADDR_DEBUG => open,\r
- STAT_TRIGGER_OUT => STAT_TRIGGER_OUT, \r
- DEBUG_LVL1_HANDLER_OUT => DEBUG_LVL1_HANDLER_OUT\r
- );\r
-\r
----------------------------------------------------------------------------\r
--- RegIO Bus Handler\r
----------------------------------------------------------------------------\r
-\r
- THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler\r
- generic map(\r
- PORT_NUMBER => 7,\r
- PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", 6 => x"7300", others => x"0000"),\r
- PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, 3 => 0, 4 => 0, 5 => 0, 6 => 5, others => 0)\r
- )\r
- port map(\r
- CLK => CLK,\r
- RESET => RESET,\r
-\r
- DAT_ADDR_IN => regio_addr_i,\r
- DAT_DATA_IN => regio_data_out_i,\r
- DAT_DATA_OUT => regio_data_in_i,\r
- DAT_READ_ENABLE_IN => regio_read_enable_i,\r
- DAT_WRITE_ENABLE_IN => regio_write_enable_i,\r
- DAT_TIMEOUT_IN => regio_timeout_i,\r
- DAT_DATAREADY_OUT => regio_dataready_i,\r
- DAT_WRITE_ACK_OUT => regio_write_ack_i,\r
- DAT_NO_MORE_DATA_OUT => regio_nomoredata_i,\r
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_i,\r
-\r
--- BUS_READ_ENABLE_OUT(0) => BUS_READ_ENABLE_OUT,\r
--- BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT,\r
--- BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT,\r
--- BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT,\r
--- BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT,\r
--- BUS_DATA_IN(31 downto 0) => BUS_DATA_IN,\r
--- BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN,\r
--- BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN,\r
--- BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN,\r
--- BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN,\r
---\r
--- BUS_READ_ENABLE_OUT(1) => dbuf_read_enable,\r
--- BUS_WRITE_ENABLE_OUT(1) => open,\r
--- BUS_DATA_OUT(63 downto 32) => open,\r
--- BUS_ADDR_OUT(19 downto 16) => dbuf_addr,\r
--- BUS_ADDR_OUT(31 downto 20) => open,\r
--- BUS_TIMEOUT_OUT(1) => open,\r
--- BUS_DATA_IN(63 downto 32) => dbuf_data_in,\r
--- BUS_DATAREADY_IN(1) => dbuf_dataready,\r
--- BUS_WRITE_ACK_IN(1) => '0',\r
--- BUS_NO_MORE_DATA_IN(1) => '0',\r
--- BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr,\r
---\r
--- BUS_READ_ENABLE_OUT(2) => tbuf_read_enable,\r
--- BUS_WRITE_ENABLE_OUT(2) => open,\r
--- BUS_DATA_OUT(95 downto 64) => open,\r
--- BUS_ADDR_OUT(47 downto 32) => open,\r
--- BUS_TIMEOUT_OUT(1) => open,\r
--- BUS_DATA_IN(95 downto 64) => stat_header_buffer_level,\r
--- BUS_DATAREADY_IN(2) => tbuf_dataready,\r
--- BUS_WRITE_ACK_IN(2) => '0',\r
--- BUS_NO_MORE_DATA_IN(2) => '0',\r
--- BUS_UNKNOWN_ADDR_IN(2) => '0'\r
-\r
---Fucking Modelsim wants it like this...\r
- BUS_READ_ENABLE_OUT(0) => BUS_READ_ENABLE_OUT,\r
- BUS_READ_ENABLE_OUT(1) => dbuf_read_enable,\r
- BUS_READ_ENABLE_OUT(2) => tbuf_read_enable,\r
- BUS_READ_ENABLE_OUT(3) => read_enable(3),\r
- BUS_READ_ENABLE_OUT(4) => read_enable(4),\r
- BUS_READ_ENABLE_OUT(5) => read_enable(5),\r
- BUS_READ_ENABLE_OUT(6) => stat_buffer_read,\r
- BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT,\r
- BUS_WRITE_ENABLE_OUT(1) => dummy(0),\r
- BUS_WRITE_ENABLE_OUT(2) => write_enable(2),\r
- BUS_WRITE_ENABLE_OUT(3) => write_enable(3),\r
- BUS_WRITE_ENABLE_OUT(4) => write_enable(4),\r
- BUS_WRITE_ENABLE_OUT(5) => write_enable(5),\r
- BUS_WRITE_ENABLE_OUT(6) => write_enable(6),\r
- BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT,\r
- BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2),\r
- BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34),\r
- BUS_DATA_OUT(191 downto 96) => dummy(191 downto 96),\r
- BUS_DATA_OUT(223 downto 192)=> dummy(291 downto 260),\r
- BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT,\r
- BUS_ADDR_OUT(19 downto 16) => dbuf_addr,\r
- BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66),\r
- BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78),\r
- BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195),\r
- BUS_ADDR_OUT(100 downto 96)=> stat_buffer_address,\r
- BUS_ADDR_OUT(111 downto 101)=> dummy(259 downto 249),\r
- BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT,\r
- BUS_TIMEOUT_OUT(1) => dummy(94),\r
- BUS_TIMEOUT_OUT(2) => dummy(95),\r
- BUS_TIMEOUT_OUT(3) => dummy(192),\r
- BUS_TIMEOUT_OUT(4) => dummy(193),\r
- BUS_TIMEOUT_OUT(5) => dummy(194),\r
- BUS_TIMEOUT_OUT(6) => dummy(243),\r
- BUS_DATA_IN(31 downto 0) => BUS_DATA_IN,\r
- BUS_DATA_IN(63 downto 32) => dbuf_data_in,\r
- BUS_DATA_IN(95 downto 64) => stat_header_buffer_level,\r
- BUS_DATA_IN(191 downto 96) => stat_handler_i(95 downto 0),\r
- BUS_DATA_IN(223 downto 192)=> stat_buffer_i,\r
- BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN,\r
- BUS_DATAREADY_IN(1) => dbuf_dataready,\r
- BUS_DATAREADY_IN(2) => tbuf_dataready,\r
- BUS_DATAREADY_IN(3) => last_read_enable(3),\r
- BUS_DATAREADY_IN(4) => last_read_enable(4),\r
- BUS_DATAREADY_IN(5) => last_read_enable(5),\r
- BUS_DATAREADY_IN(6) => stat_buffer_ready,\r
- BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN,\r
- BUS_WRITE_ACK_IN(1) => '0',\r
- BUS_WRITE_ACK_IN(2) => '0',\r
- BUS_WRITE_ACK_IN(3) => '0',\r
- BUS_WRITE_ACK_IN(4) => '0',\r
- BUS_WRITE_ACK_IN(5) => '0',\r
- BUS_WRITE_ACK_IN(6) => '0',\r
- BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN,\r
- BUS_NO_MORE_DATA_IN(1) => '0',\r
- BUS_NO_MORE_DATA_IN(2) => '0',\r
- BUS_NO_MORE_DATA_IN(3) => '0',\r
- BUS_NO_MORE_DATA_IN(4) => '0',\r
- BUS_NO_MORE_DATA_IN(5) => '0',\r
- BUS_NO_MORE_DATA_IN(6) => '0',\r
- BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN,\r
- BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr,\r
- BUS_UNKNOWN_ADDR_IN(2) => last_write_enable(2),\r
- BUS_UNKNOWN_ADDR_IN(3) => last_write_enable(3),\r
- BUS_UNKNOWN_ADDR_IN(4) => last_write_enable(4),\r
- BUS_UNKNOWN_ADDR_IN(5) => last_write_enable(5),\r
- BUS_UNKNOWN_ADDR_IN(6) => stat_buffer_unknown\r
- );\r
-\r
- proc_ack_strobes : process(CLK)\r
- begin\r
- if rising_edge(CLK) then\r
- last_write_enable <= write_enable;\r
- last_read_enable <= read_enable;\r
- end if;\r
- end process;\r
-\r
-\r
----------------------------------------------------------------------------\r
--- Data and IPU Handler\r
----------------------------------------------------------------------------\r
-\r
- THE_HANDLER_TRIGGER_DATA : handler_trigger_and_data\r
- generic map(\r
- DATA_INTERFACE_NUMBER => DATA_INTERFACE_NUMBER,\r
- DATA_BUFFER_DEPTH => DATA_BUFFER_DEPTH,\r
- DATA_BUFFER_WIDTH => DATA_BUFFER_WIDTH,\r
- DATA_BUFFER_FULL_THRESH => DATA_BUFFER_FULL_THRESH,\r
- TRG_RELEASE_AFTER_DATA => TRG_RELEASE_AFTER_DATA,\r
- HEADER_BUFFER_DEPTH => HEADER_BUFFER_DEPTH,\r
- HEADER_BUFFER_FULL_THRESH => HEADER_BUFFER_FULL_THRESH\r
- )\r
- port map(\r
- CLOCK => CLK,\r
- RESET => RESET,\r
- RESET_IPU => reset_ipu_i,\r
- --LVL1 channel\r
- LVL1_VALID_TRIGGER_IN => lvl1_valid_i,\r
- LVL1_INT_TRG_NUMBER_IN => lvl1_int_trg_number_i,\r
- LVL1_TRG_DATA_VALID_IN => lvl1_data_valid_i,\r
- LVL1_TRG_TYPE_IN => lvl1_type_i,\r
- LVL1_TRG_NUMBER_IN => lvl1_number_i,\r
- LVL1_TRG_CODE_IN => lvl1_code_i,\r
- LVL1_TRG_INFORMATION_IN => lvl1_information_i,\r
- LVL1_ERROR_PATTERN_OUT => lvl1_error_pattern_i,\r
- LVL1_TRG_RELEASE_OUT => lvl1_release_i,\r
-\r
- --IPU channel\r
- IPU_NUMBER_IN => ipu_number_i,\r
- IPU_INFORMATION_IN => ipu_information_i,\r
- IPU_READOUT_TYPE_IN => ipu_readout_type_i,\r
- IPU_START_READOUT_IN => ipu_start_readout_i,\r
- IPU_DATA_OUT => ipu_data_i,\r
- IPU_DATAREADY_OUT => ipu_dataready_i,\r
- IPU_READOUT_FINISHED_OUT => ipu_readout_finished_i,\r
- IPU_READ_IN => ipu_read_i,\r
- IPU_LENGTH_OUT => ipu_length_i,\r
- IPU_ERROR_PATTERN_OUT => ipu_error_pattern_i,\r
-\r
- --FEE Input\r
- FEE_TRG_RELEASE_IN => FEE_TRG_RELEASE_IN,\r
- FEE_TRG_STATUSBITS_IN => FEE_TRG_STATUSBITS_IN,\r
- FEE_DATA_IN => FEE_DATA_IN,\r
- FEE_DATA_WRITE_IN => FEE_DATA_WRITE_IN,\r
- FEE_DATA_FINISHED_IN => FEE_DATA_FINISHED_IN,\r
- FEE_DATA_ALMOST_FULL_OUT => FEE_DATA_ALMOST_FULL_OUT,\r
-\r
- TMG_TRG_ERROR_IN => tmg_trg_error_i,\r
- --Status Registers\r
- STAT_DATA_BUFFER_LEVEL => stat_data_buffer_level,\r
- STAT_HEADER_BUFFER_LEVEL => stat_header_buffer_level,\r
- STATUS_OUT => stat_handler_i,\r
- TIMER_TICKS_IN => time_ticks_i,\r
- STATISTICS_DATA_OUT => stat_buffer_i,\r
- STATISTICS_UNKNOWN_OUT => stat_buffer_unknown,\r
- STATISTICS_READY_OUT => stat_buffer_ready,\r
- STATISTICS_READ_IN => stat_buffer_read,\r
- STATISTICS_ADDR_IN => stat_buffer_address,\r
-\r
-\r
- --Debug\r
- DEBUG_DATA_HANDLER_OUT => debug_data_handler_i,\r
- DEBUG_IPU_HANDLER_OUT => debug_ipu_handler_i\r
-\r
- );\r
-\r
- reset_ipu_i <= RESET or common_ctrl_reg_i(2);\r
- lvl1_valid_i <= lvl1_valid_timing_i or lvl1_valid_notiming_i or lvl1_invalid_i;\r
- STAT_DEBUG_IPU_HANDLER_OUT <= debug_ipu_handler_i;\r
- STAT_DEBUG_DATA_HANDLER_OUT <= debug_data_handler_i;\r
- tmg_trg_error_i <= int_lvl1_missing_tmg_trg or int_lvl1_spurious_trg or int_lvl1_timeout_detected or int_multiple_trg\r
- or int_spike_detected or int_lvl1_long_trg;\r
-\r
----------------------------------------------------------------------------\r
--- Connect Status Registers\r
----------------------------------------------------------------------------\r
- proc_buf_status : process(CLK)\r
- variable tmp : integer range 0 to 15;\r
- begin\r
- if rising_edge(CLK) then\r
- dbuf_unknown_addr <= '0';\r
- dbuf_dataready <= '0';\r
- tbuf_dataready <= tbuf_read_enable;\r
- if dbuf_read_enable = '1' then\r
- tmp := to_integer(unsigned(dbuf_addr));\r
- if tmp < DATA_INTERFACE_NUMBER then\r
- dbuf_data_in <= stat_data_buffer_level(tmp*32+31 downto tmp*32);\r
- dbuf_dataready <= '1';\r
- else\r
- dbuf_data_in <= (others => '0');\r
- dbuf_unknown_addr <= '1';\r
- end if;\r
- end if;\r
- end if;\r
- end process;\r
-\r
-\r
-\r
----------------------------------------------------------------------------\r
--- Connect I/O Ports\r
----------------------------------------------------------------------------\r
-\r
- TRG_SPIKE_DETECTED_OUT <= int_spike_detected;\r
- TRG_SPURIOUS_TRG_OUT <= int_lvl1_spurious_trg;\r
- TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;\r
- TRG_MULTIPLE_TRG_OUT <= int_multiple_trg;\r
- TRG_MISSING_TMG_TRG_OUT <= int_lvl1_missing_tmg_trg;\r
-\r
- LVL1_TRG_DATA_VALID_OUT <= lvl1_data_valid_i;\r
- LVL1_VALID_TIMING_TRG_OUT <= lvl1_valid_timing_i;\r
- LVL1_VALID_NOTIMING_TRG_OUT <= lvl1_valid_notiming_i;\r
- LVL1_INVALID_TRG_OUT <= lvl1_invalid_i;\r
- LVL1_TRG_TYPE_OUT <= lvl1_type_i;\r
- LVL1_TRG_NUMBER_OUT <= lvl1_number_i;\r
- LVL1_TRG_CODE_OUT <= lvl1_code_i;\r
- LVL1_TRG_INFORMATION_OUT <= lvl1_information_i;\r
- LVL1_INT_TRG_NUMBER_OUT <= lvl1_int_trg_number_i;\r
-\r
- REGIO_COMMON_CTRL_REG_OUT <= common_ctrl_reg_i;\r
- REGIO_COMMON_STAT_STROBE_OUT <= common_stat_strobe_i;\r
- REGIO_COMMON_CTRL_STROBE_OUT <= common_ctrl_strobe_i;\r
- REGIO_CTRL_REG_OUT <= ctrl_reg_i;\r
- REGIO_STAT_STROBE_OUT <= stat_strobe_i;\r
- REGIO_CTRL_STROBE_OUT <= ctrl_strobe_i;\r
-\r
- stat_reg_i <= REGIO_STAT_REG_IN;\r
-\r
- TIME_GLOBAL_OUT <= time_global_i;\r
- TIME_LOCAL_OUT <= time_local_i;\r
- TIME_SINCE_LAST_TRG_OUT <= time_since_last_trg_i;\r
- TIME_TICKS_OUT <= time_ticks_i;\r
-\r
- process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,common_ctrl_reg_i, common_stat_reg_i)\r
- begin\r
- common_stat_reg_i(8 downto 0) <= REGIO_COMMON_STAT_REG_IN(8 downto 0);\r
- common_stat_reg_i(47 downto 12) <= REGIO_COMMON_STAT_REG_IN(47 downto 12);\r
- common_stat_reg_i(6) <= debug_ipu_handler_i(15) or REGIO_COMMON_STAT_REG_IN(6);\r
-\r
- if rising_edge(CLK) then\r
- if common_ctrl_reg_i(4) = '1' then \r
- common_stat_reg_i(11 downto 9) <= "000";\r
- else \r
- common_stat_reg_i(9) <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9) or common_stat_reg_i(9);\r
- common_stat_reg_i(10) <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10) or common_stat_reg_i(10);\r
- common_stat_reg_i(11) <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11) or common_stat_reg_i(11); \r
- end if;\r
- end if;\r
- common_stat_reg_i(159 downto 64) <= REGIO_COMMON_STAT_REG_IN(159 downto 64);\r
- end process;\r
-\r
- process(CLK)\r
- begin\r
- if rising_edge(CLK) then\r
- if ipu_start_readout_i = '1' then\r
- common_stat_reg_i(63 downto 48) <= ipu_number_i;\r
- end if;\r
- end if;\r
- end process;\r
-\r
-end architecture;
\ No newline at end of file
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 09-07-2015
+-- Module Name: HUB_16to8_SODA
+-- Description: 16 bits to 8 bits conversion and SODA
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- HUB_16to8_SODA
+-- Read from fifo with 16 bits, convert to 8 bits and add idles and SODA K-character
+-- If no data is available Idles (data 50 and k-char BC) are put on the output.
+-- SODA signals (DLM) are passed on directly (highest priority).
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock synchronous with SODA
+-- reset : reset : k-char FE are sent
+-- fifo_data : 16-bits input data from fifo
+-- fifo_empty : 16-bits input fifo empty signal
+-- TX_DLM : transmit SODA character
+-- TX_DLM_WORD : SODA character to be transmitted
+--
+-- Outputs:
+-- fifo_read : read signal for 16-bits input data fifo
+-- data_out : 16-bits output data
+-- char_is_k : corresponding byte in 16-bits output data is K-character
+-- error : error in DLM or read fifo
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+
+entity HUB_16to8_SODA is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ fifo_data : in std_logic_vector(15 downto 0);
+ fifo_empty : in std_logic;
+ fifo_read : out std_logic;
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ char_is_k : out std_logic;
+ error : out std_logic
+ );
+end HUB_16to8_SODA;
+
+architecture Behavioral of HUB_16to8_SODA is
+
+signal reset_S : std_logic;
+signal fifo_read_S : std_logic;
+signal fifo_databuf_S : std_logic_vector(15 downto 0);
+signal data_out_S : std_logic_vector(7 downto 0);
+signal char_is_k_S : std_logic;
+
+signal fifo_buffilled_S : std_logic := '0';
+signal fifo_read_after1clk_S : std_logic := '0';
+signal TX_DLM_S : std_logic;
+
+signal second_reset_S : std_logic;
+signal second_idle_S : std_logic;
+signal second_data_S : std_logic;
+signal error_S : std_logic;
+
+
+begin
+
+process (clock)
+begin
+ if rising_edge(clock) then
+ data_out <= data_out_S;
+ char_is_k <= char_is_k_S;
+ error <= error_S;
+ end if;
+end process;
+fifo_read <= fifo_read_S;
+
+fifo_read_S <= '1' when (fifo_empty='0')
+ and (TX_DLM='0')
+ and (fifo_read_after1clk_S='0')
+ and ((fifo_buffilled_S='0') or (second_data_S='1'))
+ and (not ((fifo_buffilled_S='1') and (TX_DLM_S='1')))
+ and (reset_S='0')
+ else '0';
+
+process (clock)
+begin
+ if rising_edge(clock) then
+ fifo_read_after1clk_S <= fifo_read_S;
+ if fifo_read_after1clk_S='1' then
+ fifo_databuf_S <= fifo_data;
+ end if;
+ TX_DLM_S <= TX_DLM;
+ reset_S <= reset;
+ end if;
+end process;
+
+process (clock)
+begin
+ if rising_edge(clock) then
+ error_S <= '0';
+ if (TX_DLM_S='1') then
+ data_out_S <= TX_DLM_WORD;
+ char_is_k_S <= '0';
+ if fifo_read_after1clk_S='1' then
+ fifo_buffilled_S <= '1';
+ end if;
+ if TX_DLM='1' then
+ error_S <= '1';
+ end if;
+ elsif (TX_DLM='1') then
+ data_out_S <= x"DC";
+ char_is_k_S <= '1';
+ if fifo_read_after1clk_S='1' then
+ fifo_buffilled_S <= '1';
+ end if;
+ elsif (second_reset_S='1') then
+ data_out_S <= x"FE";
+ char_is_k_S <= '1';
+ second_reset_S <= '0';
+ elsif (second_idle_S='1') then
+ data_out_S <= x"50";
+ char_is_k_S <= '0';
+ second_idle_S <= '0';
+ if fifo_read_after1clk_S='1' then
+ fifo_buffilled_S <= '1';
+ end if;
+ elsif (second_data_S='1') then
+ data_out_S <= fifo_databuf_S(15 downto 8);
+ char_is_k_S <= '0';
+ second_data_S <= '0';
+ if fifo_read_after1clk_S='1' then
+ fifo_buffilled_S <= '1';
+ else
+ fifo_buffilled_S <= '0';
+ end if;
+ elsif reset_S = '1' then
+ data_out_S <= x"FE";
+ char_is_k_S <= '1';
+ second_reset_S <= '1';
+ fifo_buffilled_S <= '0';
+ second_idle_S <= '0';
+ second_data_S <= '0';
+ elsif (fifo_buffilled_S='1') then
+ data_out_S <= fifo_databuf_S(7 downto 0);
+ char_is_k_S <= '0';
+ second_data_S <= '1';
+ if fifo_read_after1clk_S='1' then
+ error_S <= '1';
+ end if;
+ elsif (fifo_read_after1clk_S='1') then
+ data_out_S <= fifo_data(7 downto 0);
+ char_is_k_S <= '0';
+ second_data_S <= '1';
+ fifo_buffilled_S <= '1';
+ else
+ data_out_S <= x"BC";
+ char_is_k_S <= '1';
+ second_idle_S <= '1';
+ if fifo_read_after1clk_S='1' then
+ fifo_buffilled_S <= '1';
+ end if;
+ end if;
+ end if;
+end process;
+
+
+
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 09-07-2015
+-- Module Name: HUB_8to16_SODA
+-- Description: 16 bits to 8 bits conversion and SODA
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- HUB_8to16_SODA
+-- Convert 8-bits data from fiber and convert to 16 bits plus two K-character
+-- SODA signals (DLM) are passed on directly (highest priority).
+--
+-- Library
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock synchronous with SODA
+-- reset : reset : k-char FE are sent
+-- data_in : 8-bits input data from fiber
+-- char_is_k : data from fiber is k-character
+-- fifo_full : full signal from connected fifo: should not
+--
+-- Outputs:
+-- fifo_data : 16-bits output data plus 2 bits for k-character indication
+-- fifo_write : write signal for connected fifo
+-- RX_DLM : receive SODA character
+-- RX_DLM_WORD : received SODA character
+-- error : error in DLM or read fifo
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+
+entity HUB_8to16_SODA is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ char_is_k : in std_logic;
+ fifo_data : out std_logic_vector(17 downto 0);
+ fifo_full : in std_logic;
+ fifo_write : out std_logic;
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ error : out std_logic
+ );
+end HUB_8to16_SODA;
+
+architecture Behavioral of HUB_8to16_SODA is
+
+signal data_in_S : std_logic_vector(7 downto 0);
+signal char_is_k_S : std_logic;
+
+signal fifo_write_S : std_logic;
+signal fifo_data_S : std_logic_vector(17 downto 0);
+signal data_buf_S : std_logic_vector(7 downto 0);
+signal char_is_k_buf_S : std_logic;
+
+signal RX_DLM_WORD_S : std_logic_vector(7 downto 0);
+signal RX_DLM_S : std_logic;
+
+signal expect_dlm_word_S : std_logic := '0';
+signal expect_second_idle_S : std_logic;
+signal expect_second_data_S : std_logic;
+signal error_S : std_logic;
+
+
+begin
+
+RX_DLM_WORD <= RX_DLM_WORD_S;
+RX_DLM <= RX_DLM_S;
+
+process (clock)
+begin
+ if rising_edge(clock) then
+ data_in_S <= data_in;
+ char_is_k_S <= char_is_k;
+ fifo_data <= fifo_data_S;
+ fifo_write <= fifo_write_S;
+ error <= error_S;
+ end if;
+end process;
+
+process (clock)
+begin
+ if rising_edge(clock) then
+ error_S <= '0';
+ RX_DLM_S <= '0';
+ fifo_write_S <= '0';
+ if expect_dlm_word_S='1' then
+ expect_dlm_word_S <= '0';
+ if (char_is_k_S='0') then
+ RX_DLM_WORD_S <= data_in_S;
+ RX_DLM_S <= '1';
+ else
+ error_S <= '1';
+ end if;
+ elsif (char_is_k_S='1') and (data_in_S=x"DC") then
+ expect_dlm_word_S <= '1';
+ elsif expect_second_idle_S='1' then
+ expect_second_idle_S <= '0';
+ expect_second_data_S <= '0';
+ if (char_is_k_S='1') or (data_in_S/=x"50") then
+ error_S <= '1';
+ else
+--// fifo_data_S <= "01" & x"50BC";
+--// fifo_write_S <= '1';
+--// if fifo_full='1' then
+--// error_S <= '1';
+--// end if;
+ end if;
+ elsif (char_is_k_S='1') and (data_in_S=x"BC") then
+ expect_second_idle_S <= '1';
+ elsif expect_second_data_S='1' then
+ expect_second_data_S <= '0';
+ fifo_data_S <= char_is_k_S & char_is_k_buf_S & data_in_S & data_buf_S;
+ fifo_write_S <= '1';
+ if fifo_full='1' then
+ error_S <= '1';
+ end if;
+ else
+ expect_second_data_S <= '1';
+ data_buf_S <= data_in_S;
+ char_is_k_buf_S <= char_is_k_S;
+ end if;
+ end if;
+end process;
+
+
+
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 22-05-2015
+-- Module Name: HUB_SODA_clockcrossing
+-- Description: Transfer SODA signals to different clock domain
+-- Modifications:
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library work;
+
+----------------------------------------------------------------------------------
+-- HUB_SODA_clockcrossing
+-- Transfer SODA signals to different clock domain
+--
+-- Library
+-- work.gtpBufLayer : for GTP/GTX/serdes constants
+--
+-- Generics:
+--
+-- Inputs:
+-- write_clock : clock for DLM input
+-- read_clock : clock for DLM output
+-- DLM_in : SODA DLM active input
+-- DLM_WORD_in : 8-bits SODA DLM data (valid one clock cycle after DLM_in)
+--
+-- Outputs:
+-- DLM_out : SODA DLM active output
+-- RX_DLM_WORD : 8-bits SODA DLM data
+-- error : error : fifo full
+--
+-- Components:
+-- async_fifo_16x8 : 8-bits asynchronous fifo
+--
+----------------------------------------------------------------------------------
+
+
+entity HUB_SODA_clockcrossing is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ DLM_in : in std_logic;
+ DLM_WORD_in : in std_logic_vector(7 downto 0);
+ DLM_out : out std_logic;
+ DLM_WORD_out : out std_logic_vector(7 downto 0);
+ error : out std_logic
+ );
+end HUB_SODA_clockcrossing;
+
+architecture Behavioral of HUB_SODA_clockcrossing is
+
+component async_fifo_16x8
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(7 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(7 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+
+
+
+signal DLM_in_S : std_logic;
+signal DLM_WORD_out_S : std_logic_vector(7 downto 0);
+signal fifo_read_S : std_logic;
+signal fifo_empty_S : std_logic;
+signal fifo_read_aftr1clk_S : std_logic := '0';
+signal DLM_reading_busy0_S : std_logic := '0';
+signal DLM_reading_busy1_S : std_logic := '0';
+
+begin
+
+process(write_clock)
+begin
+ if rising_edge(write_clock) then
+ DLM_in_S <= DLM_in;
+ end if;
+end process;
+
+syncSODAfifo: async_fifo_16x8 port map(
+ rst => '0',
+ wr_clk => write_clock,
+ rd_clk => read_clock,
+ din => DLM_WORD_in,
+ wr_en => DLM_in_S,
+ rd_en => fifo_read_S,
+ dout => DLM_WORD_out_S,
+ full => error,
+ empty => fifo_empty_S);
+
+fifo_read_S <= '1' when (DLM_reading_busy0_S='1') and (DLM_reading_busy1_S='1') and (fifo_empty_S='0') and (fifo_read_aftr1clk_S='0') else '0';
+
+process(read_clock)
+begin
+ if rising_edge(read_clock) then
+ DLM_WORD_out <= DLM_WORD_out_S;
+ DLM_out <= fifo_read_aftr1clk_S;
+ end if;
+end process;
+
+process(read_clock)
+begin
+ if rising_edge(read_clock) then
+ if DLM_reading_busy0_S='0' then
+ if fifo_empty_S='0' then
+ DLM_reading_busy0_S <= '1';
+ end if;
+ else
+ if fifo_empty_S='1' then
+ DLM_reading_busy0_S <= '0';
+ end if;
+ end if;
+ fifo_read_aftr1clk_S <= fifo_read_S;
+ DLM_reading_busy1_S <= DLM_reading_busy0_S;
+ end if;
+end process;
+
+end Behavioral;
+
--- /dev/null
+-----------------------------------------------------------------------------------
+-- HUB_posedge_to_pulse
+-- Makes pulse with duration 1 clock-cycle from positive edge
+--
+-- inputs
+-- clock_in : clock input for input signal
+-- clock_out : clock input to synchronize to
+-- en_clk : clock enable
+-- signal_in : rising edge of this signal will result in pulse
+--
+-- output
+-- pulse : pulse output : one clock cycle '1'
+--
+-----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity HUB_posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end HUB_posedge_to_pulse;
+
+architecture behavioral of HUB_posedge_to_pulse is
+
+ signal resetff : std_logic := '0';
+ signal last_signal_in : std_logic := '0';
+ signal qff : std_logic := '0';
+ signal qff1 : std_logic := '0';
+ signal qff2 : std_logic := '0';
+ signal qff3 : std_logic := '0';
+begin
+
+process (clock_in)
+begin
+ if rising_edge(clock_in) then
+ if resetff='1' then
+ qff <= '0';
+ elsif (en_clk='1') and ((signal_in='1') and (qff='0') and (last_signal_in='0')) then
+ qff <= '1';
+ else
+ qff <= qff;
+ end if;
+ last_signal_in <= signal_in;
+ end if;
+end process;
+resetff <= qff2;
+
+process (clock_out)
+begin
+ if rising_edge(clock_out) then
+ if qff3='0' and qff2='1' then
+ pulse <= '1';
+ else
+ pulse <= '0';
+ end if;
+ qff3 <= qff2;
+ qff2 <= qff1;
+ qff1 <= qff;
+ end if;
+end process;
+
+
+end behavioral;
+
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_16x8 is
+port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(7 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(7 downto 0);
+ full : out std_logic;
+ empty : out std_logic
+ );
+end async_fifo_16x8;
+
+architecture Behavioral of async_fifo_16x8 is
+
+component async_fifo_16x8_ecp3 is
+ port (
+ Data: in std_logic_vector(7 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(7 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end component;
+
+begin
+
+async_fifo_16x8_ecp3_1: async_fifo_16x8_ecp3 port map(
+ Data => din,
+ WrClock => wr_clk,
+ RdClock => rd_clk,
+ WrEn => wr_en,
+ RdEn => rd_en,
+ Reset => rst,
+ RPReset => rst,
+ Q => dout,
+ Empty => empty,
+ Full => full);
+
+end Behavioral;
+
--- /dev/null
+(edif async_fifo_16x8_ecp3
+ (edifVersion 2 0 0)
+ (edifLevel 0)
+ (keywordMap (keywordLevel 0))
+ (status
+ (written
+ (timestamp 2015 7 14 16 15 57)
+ (program "SCUBA" (version "Diamond (64-bit) 3.2.0.134"))))
+ (comment "C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_16x8_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -pfu_fifo -depth 8 -width 8 -depth 8 -rdata_width 8 -no_enable -pe -1 -pf -1 ")
+ (library ORCLIB
+ (edifLevel 0)
+ (technology
+ (numberDefinition))
+ (cell AGEB2
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port A0
+ (direction INPUT))
+ (port A1
+ (direction INPUT))
+ (port B0
+ (direction INPUT))
+ (port B1
+ (direction INPUT))
+ (port CI
+ (direction INPUT))
+ (port GE
+ (direction OUTPUT)))))
+ (cell AND2
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port A
+ (direction INPUT))
+ (port B
+ (direction INPUT))
+ (port Z
+ (direction OUTPUT)))))
+ (cell CU2
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port CI
+ (direction INPUT))
+ (port PC0
+ (direction INPUT))
+ (port PC1
+ (direction INPUT))
+ (port CO
+ (direction OUTPUT))
+ (port NC0
+ (direction OUTPUT))
+ (port NC1
+ (direction OUTPUT)))))
+ (cell FADD2B
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port A0
+ (direction INPUT))
+ (port A1
+ (direction INPUT))
+ (port B0
+ (direction INPUT))
+ (port B1
+ (direction INPUT))
+ (port CI
+ (direction INPUT))
+ (port COUT
+ (direction OUTPUT))
+ (port S0
+ (direction OUTPUT))
+ (port S1
+ (direction OUTPUT)))))
+ (cell FD1P3BX
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port D
+ (direction INPUT))
+ (port SP
+ (direction INPUT))
+ (port CK
+ (direction INPUT))
+ (port PD
+ (direction INPUT))
+ (port Q
+ (direction OUTPUT)))))
+ (cell FD1P3DX
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port D
+ (direction INPUT))
+ (port SP
+ (direction INPUT))
+ (port CK
+ (direction INPUT))
+ (port CD
+ (direction INPUT))
+ (port Q
+ (direction OUTPUT)))))
+ (cell FD1S3BX
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port D
+ (direction INPUT))
+ (port CK
+ (direction INPUT))
+ (port PD
+ (direction INPUT))
+ (port Q
+ (direction OUTPUT)))))
+ (cell FD1S3DX
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port D
+ (direction INPUT))
+ (port CK
+ (direction INPUT))
+ (port CD
+ (direction INPUT))
+ (port Q
+ (direction OUTPUT)))))
+ (cell INV
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port A
+ (direction INPUT))
+ (port Z
+ (direction OUTPUT)))))
+ (cell OR2
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port A
+ (direction INPUT))
+ (port B
+ (direction INPUT))
+ (port Z
+ (direction OUTPUT)))))
+ (cell ROM16X1A
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port AD3
+ (direction INPUT))
+ (port AD2
+ (direction INPUT))
+ (port AD1
+ (direction INPUT))
+ (port AD0
+ (direction INPUT))
+ (port DO0
+ (direction OUTPUT)))))
+ (cell DPR16X4C
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port DI0
+ (direction INPUT))
+ (port DI1
+ (direction INPUT))
+ (port DI2
+ (direction INPUT))
+ (port DI3
+ (direction INPUT))
+ (port WCK
+ (direction INPUT))
+ (port WRE
+ (direction INPUT))
+ (port RAD0
+ (direction INPUT))
+ (port RAD1
+ (direction INPUT))
+ (port RAD2
+ (direction INPUT))
+ (port RAD3
+ (direction INPUT))
+ (port WAD0
+ (direction INPUT))
+ (port WAD1
+ (direction INPUT))
+ (port WAD2
+ (direction INPUT))
+ (port WAD3
+ (direction INPUT))
+ (port DO0
+ (direction OUTPUT))
+ (port DO1
+ (direction OUTPUT))
+ (port DO2
+ (direction OUTPUT))
+ (port DO3
+ (direction OUTPUT)))))
+ (cell VHI
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port Z
+ (direction OUTPUT)))))
+ (cell VLO
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port Z
+ (direction OUTPUT)))))
+ (cell XOR2
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port A
+ (direction INPUT))
+ (port B
+ (direction INPUT))
+ (port Z
+ (direction OUTPUT)))))
+ (cell async_fifo_16x8_ecp3
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port (array (rename Data "Data(7:0)") 8)
+ (direction INPUT))
+ (port WrClock
+ (direction INPUT))
+ (port RdClock
+ (direction INPUT))
+ (port WrEn
+ (direction INPUT))
+ (port RdEn
+ (direction INPUT))
+ (port Reset
+ (direction INPUT))
+ (port RPReset
+ (direction INPUT))
+ (port (array (rename Q "Q(7:0)") 8)
+ (direction OUTPUT))
+ (port Empty
+ (direction OUTPUT))
+ (port Full
+ (direction OUTPUT)))
+ (property NGD_DRC_MASK (integer 1))
+ (contents
+ (instance AND2_t8
+ (viewRef view1
+ (cellRef AND2)))
+ (instance INV_1
+ (viewRef view1
+ (cellRef INV)))
+ (instance AND2_t7
+ (viewRef view1
+ (cellRef AND2)))
+ (instance INV_0
+ (viewRef view1
+ (cellRef INV)))
+ (instance OR2_t6
+ (viewRef view1
+ (cellRef OR2)))
+ (instance XOR2_t5
+ (viewRef view1
+ (cellRef XOR2)))
+ (instance XOR2_t4
+ (viewRef view1
+ (cellRef XOR2)))
+ (instance XOR2_t3
+ (viewRef view1
+ (cellRef XOR2)))
+ (instance XOR2_t2
+ (viewRef view1
+ (cellRef XOR2)))
+ (instance XOR2_t1
+ (viewRef view1
+ (cellRef XOR2)))
+ (instance XOR2_t0
+ (viewRef view1
+ (cellRef XOR2)))
+ (instance LUT4_10
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x8000")))
+ (instance LUT4_9
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x6996")))
+ (instance LUT4_8
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x6996")))
+ (instance LUT4_7
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x6996")))
+ (instance LUT4_6
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x6996")))
+ (instance LUT4_5
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x6996")))
+ (instance LUT4_4
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x6996")))
+ (instance LUT4_3
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x0410")))
+ (instance LUT4_2
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x1004")))
+ (instance LUT4_1
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x0140")))
+ (instance LUT4_0
+ (viewRef view1
+ (cellRef ROM16X1A))
+ (property initval
+ (string "0x4001")))
+ (instance FF_49
+ (viewRef view1
+ (cellRef FD1P3BX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_48
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_47
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_46
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_45
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_44
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_43
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_42
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_41
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_40
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_39
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_38
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_37
+ (viewRef view1
+ (cellRef FD1P3BX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_36
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_35
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_34
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_33
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_32
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_31
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_30
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_29
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_28
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_27
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_26
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_25
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_24
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_23
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_22
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_21
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_20
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_19
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_18
+ (viewRef view1
+ (cellRef FD1P3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_17
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_16
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_15
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_14
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_13
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_12
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_11
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_10
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_9
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_8
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_7
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_6
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_5
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_4
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_3
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_2
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_1
+ (viewRef view1
+ (cellRef FD1S3BX))
+ (property GSR
+ (string "ENABLED")))
+ (instance FF_0
+ (viewRef view1
+ (cellRef FD1S3DX))
+ (property GSR
+ (string "ENABLED")))
+ (instance w_gctr_cia
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance w_gctr_0
+ (viewRef view1
+ (cellRef CU2)))
+ (instance w_gctr_1
+ (viewRef view1
+ (cellRef CU2)))
+ (instance scuba_vhi_inst
+ (viewRef view1
+ (cellRef VHI)))
+ (instance r_gctr_cia
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance r_gctr_0
+ (viewRef view1
+ (cellRef CU2)))
+ (instance r_gctr_1
+ (viewRef view1
+ (cellRef CU2)))
+ (instance empty_cmp_ci_a
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance empty_cmp_0
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance empty_cmp_1
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance a0
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance full_cmp_ci_a
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance full_cmp_0
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance full_cmp_1
+ (viewRef view1
+ (cellRef AGEB2)))
+ (instance a1
+ (viewRef view1
+ (cellRef FADD2B)))
+ (instance fifo_pfu_0_0
+ (viewRef view1
+ (cellRef DPR16X4C))
+ (property MEM_INIT_FILE
+ (string "(0-7)(0-3)"))
+ (property MEM_LPC_FILE
+ (string "async_fifo_16x8_ecp3.lpc"))
+ (property COMP
+ (string "fifo_pfu_0_0"))
+ (property initval
+ (string "0x0000000000000000")))
+ (instance scuba_vlo_inst
+ (viewRef view1
+ (cellRef VLO)))
+ (instance fifo_pfu_0_1
+ (viewRef view1
+ (cellRef DPR16X4C))
+ (property MEM_INIT_FILE
+ (string "(0-7)(4-7)"))
+ (property MEM_LPC_FILE
+ (string "async_fifo_16x8_ecp3.lpc"))
+ (property COMP
+ (string "fifo_pfu_0_1"))
+ (property initval
+ (string "0x0000000000000000")))
+ (net invout_1
+ (joined
+ (portRef Z (instanceRef INV_1))
+ (portRef B (instanceRef AND2_t8))))
+ (net invout_0
+ (joined
+ (portRef Z (instanceRef INV_0))
+ (portRef B (instanceRef AND2_t7))))
+ (net w_gdata_0
+ (joined
+ (portRef D (instanceRef FF_45))
+ (portRef Z (instanceRef XOR2_t5))))
+ (net w_gdata_1
+ (joined
+ (portRef D (instanceRef FF_44))
+ (portRef Z (instanceRef XOR2_t4))))
+ (net w_gdata_2
+ (joined
+ (portRef D (instanceRef FF_43))
+ (portRef Z (instanceRef XOR2_t3))))
+ (net wptr_3
+ (joined
+ (portRef Q (instanceRef FF_38))
+ (portRef AD3 (instanceRef LUT4_1))
+ (portRef AD3 (instanceRef LUT4_0))))
+ (net r_gdata_0
+ (joined
+ (portRef D (instanceRef FF_33))
+ (portRef Z (instanceRef XOR2_t2))))
+ (net r_gdata_1
+ (joined
+ (portRef D (instanceRef FF_32))
+ (portRef Z (instanceRef XOR2_t1))))
+ (net r_gdata_2
+ (joined
+ (portRef D (instanceRef FF_31))
+ (portRef Z (instanceRef XOR2_t0))))
+ (net rptr_3
+ (joined
+ (portRef Q (instanceRef FF_26))
+ (portRef AD3 (instanceRef LUT4_3))
+ (portRef AD3 (instanceRef LUT4_2))))
+ (net w_gcount_0
+ (joined
+ (portRef D (instanceRef FF_17))
+ (portRef Q (instanceRef FF_45))))
+ (net w_gcount_1
+ (joined
+ (portRef D (instanceRef FF_16))
+ (portRef Q (instanceRef FF_44))))
+ (net w_gcount_2
+ (joined
+ (portRef D (instanceRef FF_15))
+ (portRef Q (instanceRef FF_43))))
+ (net w_gcount_3
+ (joined
+ (portRef D (instanceRef FF_14))
+ (portRef Q (instanceRef FF_42))))
+ (net r_gcount_0
+ (joined
+ (portRef D (instanceRef FF_13))
+ (portRef Q (instanceRef FF_33))))
+ (net r_gcount_1
+ (joined
+ (portRef D (instanceRef FF_12))
+ (portRef Q (instanceRef FF_32))))
+ (net r_gcount_2
+ (joined
+ (portRef D (instanceRef FF_11))
+ (portRef Q (instanceRef FF_31))))
+ (net r_gcount_3
+ (joined
+ (portRef D (instanceRef FF_10))
+ (portRef Q (instanceRef FF_30))))
+ (net w_gcount_r20
+ (joined
+ (portRef Q (instanceRef FF_9))
+ (portRef AD3 (instanceRef LUT4_9))))
+ (net w_gcount_r0
+ (joined
+ (portRef D (instanceRef FF_9))
+ (portRef Q (instanceRef FF_17))))
+ (net w_gcount_r21
+ (joined
+ (portRef Q (instanceRef FF_8))
+ (portRef AD2 (instanceRef LUT4_9))
+ (portRef AD3 (instanceRef LUT4_7))))
+ (net w_gcount_r1
+ (joined
+ (portRef D (instanceRef FF_8))
+ (portRef Q (instanceRef FF_16))))
+ (net w_gcount_r22
+ (joined
+ (portRef Q (instanceRef FF_7))
+ (portRef AD1 (instanceRef LUT4_9))
+ (portRef AD3 (instanceRef LUT4_8))
+ (portRef AD2 (instanceRef LUT4_7))))
+ (net w_gcount_r2
+ (joined
+ (portRef D (instanceRef FF_7))
+ (portRef Q (instanceRef FF_15))))
+ (net w_gcount_r23
+ (joined
+ (portRef Q (instanceRef FF_6))
+ (portRef AD0 (instanceRef LUT4_9))
+ (portRef AD2 (instanceRef LUT4_8))
+ (portRef AD1 (instanceRef LUT4_7))
+ (portRef AD1 (instanceRef LUT4_3))
+ (portRef AD1 (instanceRef LUT4_2))))
+ (net w_gcount_r3
+ (joined
+ (portRef D (instanceRef FF_6))
+ (portRef Q (instanceRef FF_14))))
+ (net r_gcount_w20
+ (joined
+ (portRef Q (instanceRef FF_5))
+ (portRef AD3 (instanceRef LUT4_6))))
+ (net r_gcount_w0
+ (joined
+ (portRef D (instanceRef FF_5))
+ (portRef Q (instanceRef FF_13))))
+ (net r_gcount_w21
+ (joined
+ (portRef Q (instanceRef FF_4))
+ (portRef AD2 (instanceRef LUT4_6))
+ (portRef AD3 (instanceRef LUT4_4))))
+ (net r_gcount_w1
+ (joined
+ (portRef D (instanceRef FF_4))
+ (portRef Q (instanceRef FF_12))))
+ (net r_gcount_w22
+ (joined
+ (portRef Q (instanceRef FF_3))
+ (portRef AD1 (instanceRef LUT4_6))
+ (portRef AD3 (instanceRef LUT4_5))
+ (portRef AD2 (instanceRef LUT4_4))))
+ (net r_gcount_w2
+ (joined
+ (portRef D (instanceRef FF_3))
+ (portRef Q (instanceRef FF_11))))
+ (net r_gcount_w23
+ (joined
+ (portRef Q (instanceRef FF_2))
+ (portRef AD0 (instanceRef LUT4_6))
+ (portRef AD2 (instanceRef LUT4_5))
+ (portRef AD1 (instanceRef LUT4_4))
+ (portRef AD1 (instanceRef LUT4_1))
+ (portRef AD1 (instanceRef LUT4_0))))
+ (net r_gcount_w3
+ (joined
+ (portRef D (instanceRef FF_2))
+ (portRef Q (instanceRef FF_10))))
+ (net rRst
+ (joined
+ (portRef PD (instanceRef FF_1))
+ (portRef Z (instanceRef OR2_t6))
+ (portRef PD (instanceRef FF_37))
+ (portRef CD (instanceRef FF_36))
+ (portRef CD (instanceRef FF_35))
+ (portRef CD (instanceRef FF_34))
+ (portRef CD (instanceRef FF_33))
+ (portRef CD (instanceRef FF_32))
+ (portRef CD (instanceRef FF_31))
+ (portRef CD (instanceRef FF_30))
+ (portRef CD (instanceRef FF_29))
+ (portRef CD (instanceRef FF_28))
+ (portRef CD (instanceRef FF_27))
+ (portRef CD (instanceRef FF_26))
+ (portRef CD (instanceRef FF_25))
+ (portRef CD (instanceRef FF_24))
+ (portRef CD (instanceRef FF_23))
+ (portRef CD (instanceRef FF_22))
+ (portRef CD (instanceRef FF_21))
+ (portRef CD (instanceRef FF_20))
+ (portRef CD (instanceRef FF_19))
+ (portRef CD (instanceRef FF_18))
+ (portRef CD (instanceRef FF_13))
+ (portRef CD (instanceRef FF_12))
+ (portRef CD (instanceRef FF_11))
+ (portRef CD (instanceRef FF_10))
+ (portRef CD (instanceRef FF_5))
+ (portRef CD (instanceRef FF_4))
+ (portRef CD (instanceRef FF_3))
+ (portRef CD (instanceRef FF_2))))
+ (net iwcount_0
+ (joined
+ (portRef NC0 (instanceRef w_gctr_0))
+ (portRef D (instanceRef FF_49))))
+ (net iwcount_1
+ (joined
+ (portRef NC1 (instanceRef w_gctr_0))
+ (portRef D (instanceRef FF_48))))
+ (net w_gctr_ci
+ (joined
+ (portRef CI (instanceRef w_gctr_0))
+ (portRef COUT (instanceRef w_gctr_cia))))
+ (net iwcount_2
+ (joined
+ (portRef NC0 (instanceRef w_gctr_1))
+ (portRef D (instanceRef FF_47))))
+ (net iwcount_3
+ (joined
+ (portRef NC1 (instanceRef w_gctr_1))
+ (portRef D (instanceRef FF_46))))
+ (net co1
+ (joined
+ (portRef CO (instanceRef w_gctr_1))))
+ (net co0
+ (joined
+ (portRef CI (instanceRef w_gctr_1))
+ (portRef CO (instanceRef w_gctr_0))))
+ (net wcount_3
+ (joined
+ (portRef PC1 (instanceRef w_gctr_1))
+ (portRef B (instanceRef XOR2_t3))
+ (portRef AD2 (instanceRef LUT4_1))
+ (portRef AD2 (instanceRef LUT4_0))
+ (portRef Q (instanceRef FF_46))
+ (portRef D (instanceRef FF_42))
+ (portRef D (instanceRef FF_38))))
+ (net scuba_vhi
+ (joined
+ (portRef Z (instanceRef scuba_vhi_inst))
+ (portRef AD0 (instanceRef LUT4_10))
+ (portRef AD1 (instanceRef LUT4_10))
+ (portRef AD3 (instanceRef LUT4_10))
+ (portRef B1 (instanceRef w_gctr_cia))
+ (portRef A1 (instanceRef w_gctr_cia))
+ (portRef B1 (instanceRef r_gctr_cia))
+ (portRef A1 (instanceRef r_gctr_cia))))
+ (net ircount_0
+ (joined
+ (portRef NC0 (instanceRef r_gctr_0))
+ (portRef D (instanceRef FF_37))))
+ (net ircount_1
+ (joined
+ (portRef NC1 (instanceRef r_gctr_0))
+ (portRef D (instanceRef FF_36))))
+ (net r_gctr_ci
+ (joined
+ (portRef CI (instanceRef r_gctr_0))
+ (portRef COUT (instanceRef r_gctr_cia))))
+ (net ircount_2
+ (joined
+ (portRef NC0 (instanceRef r_gctr_1))
+ (portRef D (instanceRef FF_35))))
+ (net ircount_3
+ (joined
+ (portRef NC1 (instanceRef r_gctr_1))
+ (portRef D (instanceRef FF_34))))
+ (net co1_1
+ (joined
+ (portRef CO (instanceRef r_gctr_1))))
+ (net co0_1
+ (joined
+ (portRef CI (instanceRef r_gctr_1))
+ (portRef CO (instanceRef r_gctr_0))))
+ (net rcount_3
+ (joined
+ (portRef PC1 (instanceRef r_gctr_1))
+ (portRef B (instanceRef XOR2_t0))
+ (portRef AD2 (instanceRef LUT4_3))
+ (portRef AD2 (instanceRef LUT4_2))
+ (portRef Q (instanceRef FF_34))
+ (portRef D (instanceRef FF_30))
+ (portRef D (instanceRef FF_26))))
+ (net rden_i
+ (joined
+ (portRef A1 (instanceRef empty_cmp_ci_a))
+ (portRef Z (instanceRef AND2_t7))
+ (portRef SP (instanceRef FF_37))
+ (portRef SP (instanceRef FF_36))
+ (portRef SP (instanceRef FF_35))
+ (portRef SP (instanceRef FF_34))
+ (portRef SP (instanceRef FF_33))
+ (portRef SP (instanceRef FF_32))
+ (portRef SP (instanceRef FF_31))
+ (portRef SP (instanceRef FF_30))
+ (portRef SP (instanceRef FF_29))
+ (portRef SP (instanceRef FF_28))
+ (portRef SP (instanceRef FF_27))
+ (portRef SP (instanceRef FF_26))
+ (portRef SP (instanceRef FF_25))
+ (portRef SP (instanceRef FF_24))
+ (portRef SP (instanceRef FF_23))
+ (portRef SP (instanceRef FF_22))
+ (portRef SP (instanceRef FF_21))
+ (portRef SP (instanceRef FF_20))
+ (portRef SP (instanceRef FF_19))
+ (portRef SP (instanceRef FF_18))
+ (portRef B1 (instanceRef empty_cmp_ci_a))))
+ (net cmp_ci
+ (joined
+ (portRef CI (instanceRef empty_cmp_0))
+ (portRef COUT (instanceRef empty_cmp_ci_a))))
+ (net w_g2b_xor_cluster_0
+ (joined
+ (portRef B0 (instanceRef empty_cmp_0))
+ (portRef DO0 (instanceRef LUT4_9))))
+ (net wcount_r1
+ (joined
+ (portRef B1 (instanceRef empty_cmp_0))
+ (portRef DO0 (instanceRef LUT4_7))))
+ (net rcount_0
+ (joined
+ (portRef A0 (instanceRef empty_cmp_0))
+ (portRef A (instanceRef XOR2_t2))
+ (portRef Q (instanceRef FF_37))
+ (portRef D (instanceRef FF_29))
+ (portRef PC0 (instanceRef r_gctr_0))))
+ (net rcount_1
+ (joined
+ (portRef A1 (instanceRef empty_cmp_0))
+ (portRef B (instanceRef XOR2_t2))
+ (portRef A (instanceRef XOR2_t1))
+ (portRef Q (instanceRef FF_36))
+ (portRef D (instanceRef FF_28))
+ (portRef PC1 (instanceRef r_gctr_0))))
+ (net co0_2
+ (joined
+ (portRef CI (instanceRef empty_cmp_1))
+ (portRef GE (instanceRef empty_cmp_0))))
+ (net wcount_r2
+ (joined
+ (portRef B0 (instanceRef empty_cmp_1))
+ (portRef DO0 (instanceRef LUT4_8))))
+ (net empty_cmp_clr
+ (joined
+ (portRef B1 (instanceRef empty_cmp_1))
+ (portRef DO0 (instanceRef LUT4_2))))
+ (net rcount_2
+ (joined
+ (portRef A0 (instanceRef empty_cmp_1))
+ (portRef B (instanceRef XOR2_t1))
+ (portRef A (instanceRef XOR2_t0))
+ (portRef Q (instanceRef FF_35))
+ (portRef D (instanceRef FF_27))
+ (portRef PC0 (instanceRef r_gctr_1))))
+ (net empty_cmp_set
+ (joined
+ (portRef A1 (instanceRef empty_cmp_1))
+ (portRef DO0 (instanceRef LUT4_3))))
+ (net empty_d
+ (joined
+ (portRef S0 (instanceRef a0))
+ (portRef D (instanceRef FF_1))))
+ (net empty_d_c
+ (joined
+ (portRef CI (instanceRef a0))
+ (portRef GE (instanceRef empty_cmp_1))))
+ (net wren_i
+ (joined
+ (portRef A1 (instanceRef full_cmp_ci_a))
+ (portRef Z (instanceRef AND2_t8))
+ (portRef AD2 (instanceRef LUT4_10))
+ (portRef SP (instanceRef FF_49))
+ (portRef SP (instanceRef FF_48))
+ (portRef SP (instanceRef FF_47))
+ (portRef SP (instanceRef FF_46))
+ (portRef SP (instanceRef FF_45))
+ (portRef SP (instanceRef FF_44))
+ (portRef SP (instanceRef FF_43))
+ (portRef SP (instanceRef FF_42))
+ (portRef SP (instanceRef FF_41))
+ (portRef SP (instanceRef FF_40))
+ (portRef SP (instanceRef FF_39))
+ (portRef SP (instanceRef FF_38))
+ (portRef B1 (instanceRef full_cmp_ci_a))))
+ (net cmp_ci_1
+ (joined
+ (portRef CI (instanceRef full_cmp_0))
+ (portRef COUT (instanceRef full_cmp_ci_a))))
+ (net r_g2b_xor_cluster_0
+ (joined
+ (portRef B0 (instanceRef full_cmp_0))
+ (portRef DO0 (instanceRef LUT4_6))))
+ (net rcount_w1
+ (joined
+ (portRef B1 (instanceRef full_cmp_0))
+ (portRef DO0 (instanceRef LUT4_4))))
+ (net wcount_0
+ (joined
+ (portRef A0 (instanceRef full_cmp_0))
+ (portRef A (instanceRef XOR2_t5))
+ (portRef Q (instanceRef FF_49))
+ (portRef D (instanceRef FF_41))
+ (portRef PC0 (instanceRef w_gctr_0))))
+ (net wcount_1
+ (joined
+ (portRef A1 (instanceRef full_cmp_0))
+ (portRef B (instanceRef XOR2_t5))
+ (portRef A (instanceRef XOR2_t4))
+ (portRef Q (instanceRef FF_48))
+ (portRef D (instanceRef FF_40))
+ (portRef PC1 (instanceRef w_gctr_0))))
+ (net co0_3
+ (joined
+ (portRef CI (instanceRef full_cmp_1))
+ (portRef GE (instanceRef full_cmp_0))))
+ (net rcount_w2
+ (joined
+ (portRef B0 (instanceRef full_cmp_1))
+ (portRef DO0 (instanceRef LUT4_5))))
+ (net full_cmp_clr
+ (joined
+ (portRef B1 (instanceRef full_cmp_1))
+ (portRef DO0 (instanceRef LUT4_0))))
+ (net wcount_2
+ (joined
+ (portRef A0 (instanceRef full_cmp_1))
+ (portRef B (instanceRef XOR2_t4))
+ (portRef A (instanceRef XOR2_t3))
+ (portRef Q (instanceRef FF_47))
+ (portRef D (instanceRef FF_39))
+ (portRef PC0 (instanceRef w_gctr_1))))
+ (net full_cmp_set
+ (joined
+ (portRef A1 (instanceRef full_cmp_1))
+ (portRef DO0 (instanceRef LUT4_1))))
+ (net full_d
+ (joined
+ (portRef S0 (instanceRef a1))
+ (portRef D (instanceRef FF_0))))
+ (net full_d_c
+ (joined
+ (portRef CI (instanceRef a1))
+ (portRef GE (instanceRef full_cmp_1))))
+ (net rdataout7
+ (joined
+ (portRef DO3 (instanceRef fifo_pfu_0_0))
+ (portRef D (instanceRef FF_18))))
+ (net rdataout6
+ (joined
+ (portRef DO2 (instanceRef fifo_pfu_0_0))
+ (portRef D (instanceRef FF_19))))
+ (net rdataout5
+ (joined
+ (portRef DO1 (instanceRef fifo_pfu_0_0))
+ (portRef D (instanceRef FF_20))))
+ (net rdataout4
+ (joined
+ (portRef DO0 (instanceRef fifo_pfu_0_0))
+ (portRef D (instanceRef FF_21))))
+ (net rdataout3
+ (joined
+ (portRef DO3 (instanceRef fifo_pfu_0_1))
+ (portRef D (instanceRef FF_22))))
+ (net rdataout2
+ (joined
+ (portRef DO2 (instanceRef fifo_pfu_0_1))
+ (portRef D (instanceRef FF_23))))
+ (net rdataout1
+ (joined
+ (portRef DO1 (instanceRef fifo_pfu_0_1))
+ (portRef D (instanceRef FF_24))))
+ (net rdataout0
+ (joined
+ (portRef DO0 (instanceRef fifo_pfu_0_1))
+ (portRef D (instanceRef FF_25))))
+ (net rptr_2
+ (joined
+ (portRef RAD2 (instanceRef fifo_pfu_0_1))
+ (portRef Q (instanceRef FF_27))
+ (portRef RAD2 (instanceRef fifo_pfu_0_0))))
+ (net rptr_1
+ (joined
+ (portRef RAD1 (instanceRef fifo_pfu_0_1))
+ (portRef Q (instanceRef FF_28))
+ (portRef RAD1 (instanceRef fifo_pfu_0_0))))
+ (net rptr_0
+ (joined
+ (portRef RAD0 (instanceRef fifo_pfu_0_1))
+ (portRef Q (instanceRef FF_29))
+ (portRef RAD0 (instanceRef fifo_pfu_0_0))))
+ (net dec0_wre3
+ (joined
+ (portRef WRE (instanceRef fifo_pfu_0_1))
+ (portRef DO0 (instanceRef LUT4_10))
+ (portRef WRE (instanceRef fifo_pfu_0_0))))
+ (net scuba_vlo
+ (joined
+ (portRef Z (instanceRef scuba_vlo_inst))
+ (portRef AD0 (instanceRef LUT4_8))
+ (portRef AD1 (instanceRef LUT4_8))
+ (portRef AD0 (instanceRef LUT4_7))
+ (portRef AD0 (instanceRef LUT4_5))
+ (portRef AD1 (instanceRef LUT4_5))
+ (portRef AD0 (instanceRef LUT4_4))
+ (portRef AD0 (instanceRef LUT4_3))
+ (portRef AD0 (instanceRef LUT4_2))
+ (portRef AD0 (instanceRef LUT4_1))
+ (portRef AD0 (instanceRef LUT4_0))
+ (portRef CI (instanceRef w_gctr_cia))
+ (portRef B0 (instanceRef w_gctr_cia))
+ (portRef A0 (instanceRef w_gctr_cia))
+ (portRef CI (instanceRef r_gctr_cia))
+ (portRef B0 (instanceRef r_gctr_cia))
+ (portRef A0 (instanceRef r_gctr_cia))
+ (portRef CI (instanceRef empty_cmp_ci_a))
+ (portRef B0 (instanceRef empty_cmp_ci_a))
+ (portRef A0 (instanceRef empty_cmp_ci_a))
+ (portRef B0 (instanceRef a0))
+ (portRef B1 (instanceRef a0))
+ (portRef A0 (instanceRef a0))
+ (portRef A1 (instanceRef a0))
+ (portRef CI (instanceRef full_cmp_ci_a))
+ (portRef B0 (instanceRef full_cmp_ci_a))
+ (portRef A0 (instanceRef full_cmp_ci_a))
+ (portRef B0 (instanceRef a1))
+ (portRef B1 (instanceRef a1))
+ (portRef A0 (instanceRef a1))
+ (portRef A1 (instanceRef a1))
+ (portRef RAD3 (instanceRef fifo_pfu_0_0))
+ (portRef WAD3 (instanceRef fifo_pfu_0_0))
+ (portRef RAD3 (instanceRef fifo_pfu_0_1))
+ (portRef WAD3 (instanceRef fifo_pfu_0_1))))
+ (net wptr_2
+ (joined
+ (portRef WAD2 (instanceRef fifo_pfu_0_1))
+ (portRef Q (instanceRef FF_39))
+ (portRef WAD2 (instanceRef fifo_pfu_0_0))))
+ (net wptr_1
+ (joined
+ (portRef WAD1 (instanceRef fifo_pfu_0_1))
+ (portRef Q (instanceRef FF_40))
+ (portRef WAD1 (instanceRef fifo_pfu_0_0))))
+ (net wptr_0
+ (joined
+ (portRef WAD0 (instanceRef fifo_pfu_0_1))
+ (portRef Q (instanceRef FF_41))
+ (portRef WAD0 (instanceRef fifo_pfu_0_0))))
+ (net Full
+ (joined
+ (portRef Full)
+ (portRef Q (instanceRef FF_0))
+ (portRef A (instanceRef INV_1))))
+ (net Empty
+ (joined
+ (portRef Empty)
+ (portRef Q (instanceRef FF_1))
+ (portRef A (instanceRef INV_0))))
+ (net dataout7
+ (joined
+ (portRef (member Q 0))
+ (portRef Q (instanceRef FF_18))))
+ (net dataout6
+ (joined
+ (portRef (member Q 1))
+ (portRef Q (instanceRef FF_19))))
+ (net dataout5
+ (joined
+ (portRef (member Q 2))
+ (portRef Q (instanceRef FF_20))))
+ (net dataout4
+ (joined
+ (portRef (member Q 3))
+ (portRef Q (instanceRef FF_21))))
+ (net dataout3
+ (joined
+ (portRef (member Q 4))
+ (portRef Q (instanceRef FF_22))))
+ (net dataout2
+ (joined
+ (portRef (member Q 5))
+ (portRef Q (instanceRef FF_23))))
+ (net dataout1
+ (joined
+ (portRef (member Q 6))
+ (portRef Q (instanceRef FF_24))))
+ (net dataout0
+ (joined
+ (portRef (member Q 7))
+ (portRef Q (instanceRef FF_25))))
+ (net RPRst
+ (joined
+ (portRef RPReset)
+ (portRef B (instanceRef OR2_t6))))
+ (net reset
+ (joined
+ (portRef Reset)
+ (portRef A (instanceRef OR2_t6))
+ (portRef PD (instanceRef FF_49))
+ (portRef CD (instanceRef FF_48))
+ (portRef CD (instanceRef FF_47))
+ (portRef CD (instanceRef FF_46))
+ (portRef CD (instanceRef FF_45))
+ (portRef CD (instanceRef FF_44))
+ (portRef CD (instanceRef FF_43))
+ (portRef CD (instanceRef FF_42))
+ (portRef CD (instanceRef FF_41))
+ (portRef CD (instanceRef FF_40))
+ (portRef CD (instanceRef FF_39))
+ (portRef CD (instanceRef FF_38))
+ (portRef CD (instanceRef FF_17))
+ (portRef CD (instanceRef FF_16))
+ (portRef CD (instanceRef FF_15))
+ (portRef CD (instanceRef FF_14))
+ (portRef CD (instanceRef FF_9))
+ (portRef CD (instanceRef FF_8))
+ (portRef CD (instanceRef FF_7))
+ (portRef CD (instanceRef FF_6))
+ (portRef CD (instanceRef FF_0))))
+ (net rden
+ (joined
+ (portRef RdEn)
+ (portRef A (instanceRef AND2_t7))))
+ (net wren
+ (joined
+ (portRef WrEn)
+ (portRef A (instanceRef AND2_t8))))
+ (net rclk
+ (joined
+ (portRef RdClock)
+ (portRef CK (instanceRef FF_37))
+ (portRef CK (instanceRef FF_36))
+ (portRef CK (instanceRef FF_35))
+ (portRef CK (instanceRef FF_34))
+ (portRef CK (instanceRef FF_33))
+ (portRef CK (instanceRef FF_32))
+ (portRef CK (instanceRef FF_31))
+ (portRef CK (instanceRef FF_30))
+ (portRef CK (instanceRef FF_29))
+ (portRef CK (instanceRef FF_28))
+ (portRef CK (instanceRef FF_27))
+ (portRef CK (instanceRef FF_26))
+ (portRef CK (instanceRef FF_25))
+ (portRef CK (instanceRef FF_24))
+ (portRef CK (instanceRef FF_23))
+ (portRef CK (instanceRef FF_22))
+ (portRef CK (instanceRef FF_21))
+ (portRef CK (instanceRef FF_20))
+ (portRef CK (instanceRef FF_19))
+ (portRef CK (instanceRef FF_18))
+ (portRef CK (instanceRef FF_17))
+ (portRef CK (instanceRef FF_16))
+ (portRef CK (instanceRef FF_15))
+ (portRef CK (instanceRef FF_14))
+ (portRef CK (instanceRef FF_9))
+ (portRef CK (instanceRef FF_8))
+ (portRef CK (instanceRef FF_7))
+ (portRef CK (instanceRef FF_6))
+ (portRef CK (instanceRef FF_1))))
+ (net wclk
+ (joined
+ (portRef WrClock)
+ (portRef CK (instanceRef FF_49))
+ (portRef CK (instanceRef FF_48))
+ (portRef CK (instanceRef FF_47))
+ (portRef CK (instanceRef FF_46))
+ (portRef CK (instanceRef FF_45))
+ (portRef CK (instanceRef FF_44))
+ (portRef CK (instanceRef FF_43))
+ (portRef CK (instanceRef FF_42))
+ (portRef CK (instanceRef FF_41))
+ (portRef CK (instanceRef FF_40))
+ (portRef CK (instanceRef FF_39))
+ (portRef CK (instanceRef FF_38))
+ (portRef CK (instanceRef FF_13))
+ (portRef CK (instanceRef FF_12))
+ (portRef CK (instanceRef FF_11))
+ (portRef CK (instanceRef FF_10))
+ (portRef CK (instanceRef FF_5))
+ (portRef CK (instanceRef FF_4))
+ (portRef CK (instanceRef FF_3))
+ (portRef CK (instanceRef FF_2))
+ (portRef CK (instanceRef FF_0))
+ (portRef WCK (instanceRef fifo_pfu_0_0))
+ (portRef WCK (instanceRef fifo_pfu_0_1))))
+ (net datain7
+ (joined
+ (portRef (member Data 0))
+ (portRef DI3 (instanceRef fifo_pfu_0_0))))
+ (net datain6
+ (joined
+ (portRef (member Data 1))
+ (portRef DI2 (instanceRef fifo_pfu_0_0))))
+ (net datain5
+ (joined
+ (portRef (member Data 2))
+ (portRef DI1 (instanceRef fifo_pfu_0_0))))
+ (net datain4
+ (joined
+ (portRef (member Data 3))
+ (portRef DI0 (instanceRef fifo_pfu_0_0))))
+ (net datain3
+ (joined
+ (portRef (member Data 4))
+ (portRef DI3 (instanceRef fifo_pfu_0_1))))
+ (net datain2
+ (joined
+ (portRef (member Data 5))
+ (portRef DI2 (instanceRef fifo_pfu_0_1))))
+ (net datain1
+ (joined
+ (portRef (member Data 6))
+ (portRef DI1 (instanceRef fifo_pfu_0_1))))
+ (net datain0
+ (joined
+ (portRef (member Data 7))
+ (portRef DI0 (instanceRef fifo_pfu_0_1))))))))
+ (design async_fifo_16x8_ecp3
+ (cellRef async_fifo_16x8_ecp3
+ (libraryRef ORCLIB)))
+)
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_16x8_ecp3" module="async_fifo_16x8_ecp3" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 07 14 16:16:02.803" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="async_fifo_16x8_ecp3.lpc" type="lpc" modified="2015 07 14 16:15:57.082"/>
+ <File name="async_fifo_16x8_ecp3.vhd" type="top_level_vhdl" modified="2015 07 14 16:15:57.161"/>
+ <File name="async_fifo_16x8_ecp3_tmpl.vhd" type="template_vhdl" modified="2015 07 14 16:15:57.161"/>
+ <File name="tb_async_fifo_16x8_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2015 07 14 16:15:57.166"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.7
+ModuleName=async_fifo_16x8_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/14/2015
+Time=16:15:57
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=LUT Based
+Depth=8
+Width=8
+RDepth=8
+RWidth=8
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n async_fifo_16x8_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -pfu_fifo -addr_width 3 -data_width 8 -num_words 8 -rdata_width 8 -no_enable -pe -1 -pf -1
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module Version: 5.7
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_16x8_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -pfu_fifo -depth 8 -width 8 -depth 8 -rdata_width 8 -no_enable -pe -1 -pf -1
+
+-- Tue Jul 14 16:15:57 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_16x8_ecp3 is
+ port (
+ Data: in std_logic_vector(7 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(7 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end async_fifo_16x8_ecp3;
+
+architecture Structure of async_fifo_16x8_ecp3 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal wptr_3: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal rptr_3: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co1: std_logic;
+ signal co0: std_logic;
+ signal wcount_3: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co1_1: std_logic;
+ signal co0_1: std_logic;
+ signal rcount_3: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wcount_r2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_2: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal rcount_w2: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal wcount_2: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal rdataout7: std_logic;
+ signal rdataout6: std_logic;
+ signal rdataout5: std_logic;
+ signal rdataout4: std_logic;
+ signal rdataout3: std_logic;
+ signal rdataout2: std_logic;
+ signal rdataout1: std_logic;
+ signal rdataout0: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_0: std_logic;
+ signal dec0_wre3: std_logic;
+ signal scuba_vlo: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_0: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component DPR16X4C
+ generic (INITVAL : in String);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
+ RAD0: in std_logic; RAD1: in std_logic;
+ RAD2: in std_logic; RAD3: in std_logic;
+ WAD0: in std_logic; WAD1: in std_logic;
+ WAD2: in std_logic; WAD3: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute MEM_INIT_FILE : string;
+ attribute MEM_LPC_FILE : string;
+ attribute COMP : string;
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-7)(0-3)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "async_fifo_16x8_ecp3.lpc";
+ attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0";
+ attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-7)(4-7)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "async_fifo_16x8_ecp3.lpc";
+ attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t8: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t7: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t6: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t5: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t4: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t3: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ LUT4_10: ROM16X1A
+ generic map (initval=> X"8000")
+ port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_wre3);
+
+ LUT4_9: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>w_gcount_r23,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_8: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_7: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+ LUT4_6: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>r_gcount_w23,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_5: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_4: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"0410")
+ port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"1004")
+ port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"0140")
+ port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"4001")
+ port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ FF_49: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_48: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_47: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_46: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_45: FD1P3DX
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_44: FD1P3DX
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_43: FD1P3DX
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_42: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_41: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_40: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_39: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_38: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_37: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_36: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_35: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_34: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_33: FD1P3DX
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_32: FD1P3DX
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_31: FD1P3DX
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_30: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_29: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_28: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_27: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_26: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_25: FD1P3DX
+ port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(0));
+
+ FF_24: FD1P3DX
+ port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(1));
+
+ FF_23: FD1P3DX
+ port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(2));
+
+ FF_22: FD1P3DX
+ port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(3));
+
+ FF_21: FD1P3DX
+ port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(4));
+
+ FF_20: FD1P3DX
+ port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(5));
+
+ FF_19: FD1P3DX
+ port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(6));
+
+ FF_18: FD1P3DX
+ port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(7));
+
+ FF_17: FD1S3DX
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_16: FD1S3DX
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_15: FD1S3DX
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_14: FD1S3DX
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_13: FD1S3DX
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_12: FD1S3DX
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_11: FD1S3DX
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_10: FD1S3DX
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_9: FD1S3DX
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_8: FD1S3DX
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_7: FD1S3DX
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_6: FD1S3DX
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_5: FD1S3DX
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_4: FD1S3DX
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_3: FD1S3DX
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_2: FD1S3DX
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_1: FD1S3BX
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>empty_cmp_set, B0=>wcount_r2,
+ B1=>empty_cmp_clr, CI=>co0_2, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>r_g2b_xor_cluster_0,
+ B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>full_cmp_set, B0=>rcount_w2,
+ B1=>full_cmp_clr, CI=>co0_3, GE=>full_d_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ fifo_pfu_0_0: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
+ RAD2=>rptr_2, RAD3=>scuba_vlo, WAD0=>wptr_0, WAD1=>wptr_1,
+ WAD2=>wptr_2, WAD3=>scuba_vlo, DO0=>rdataout4,
+ DO1=>rdataout5, DO2=>rdataout6, DO3=>rdataout7);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ fifo_pfu_0_1: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
+ RAD2=>rptr_2, RAD3=>scuba_vlo, WAD0=>wptr_0, WAD1=>wptr_1,
+ WAD2=>wptr_2, WAD3=>scuba_vlo, DO0=>rdataout0,
+ DO1=>rdataout1, DO2=>rdataout2, DO3=>rdataout3);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_16x8_ecp3 is
+ for Structure
+ for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all:AND2 use entity ecp3.AND2(V); end for;
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:OR2 use entity ecp3.OR2(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:XOR2 use entity ecp3.XOR2(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_200_full" module="serdes_sync_200_full" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 11 27 15:50:28.339" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="serdes_sync_200_full.lpc" type="lpc" modified="2014 11 27 15:50:24.795"/>
+ <File name="serdes_sync_200_full.pp" type="pp" modified="2014 11 27 15:50:24.796"/>
+ <File name="serdes_sync_200_full.sym" type="sym" modified="2014 11 27 15:50:25.058"/>
+ <File name="serdes_sync_200_full.tft" type="tft" modified="2014 11 27 15:50:24.828"/>
+ <File name="serdes_sync_200_full.txt" type="pcs_module" modified="2014 11 27 15:50:24.831"/>
+ <File name="serdes_sync_200_full.vhd" type="top_level_vhdl" modified="2014 11 27 15:50:24.827"/>
+ </Package>
+</DiamondModule>
CoreStatus=Demo
CoreName=PCS
CoreRevision=8.2
-ModuleName=serdes_4_sync_downstream
+ModuleName=serdes_sync_200_full
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=02/19/2015
-Time=11:41:22
+Date=11/27/2014
+Time=15:50:24
[Parameters]
Verilog=0
_rx_ficlk_rate1=200
_rx_ficlk_rate2=200
_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
+_tdrv_ch0=1
+_tdrv_ch1=1
+_tdrv_ch2=1
+_tdrv_ch3=1
_tx_pre0=DISABLED
_tx_pre1=DISABLED
_tx_pre2=DISABLED
_los_threshold_hi2=7
_los_threshold_hi3=7
_pll_term=50
-_pll_dcc=DC
-_pll_lol_set=0
+_pll_dcc=AC
+_pll_lol_set=1
_tx_sb0=DISABLED
_tx_sb1=DISABLED
_tx_sb2=DISABLED
_rx_los_port3=Internal
_sci_ports=ENABLED
_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
+_refck2core=DISABLED
+Regen=auto
PAR1=0
PARTrace1=0
PAR3=0
PARTrace3=0
[FilesGenerated]
-serdes_4_sync_downstream.pp=pp
-serdes_4_sync_downstream.tft=tft
-serdes_4_sync_downstream.txt=pcs_module
-serdes_4_sync_downstream.sym=sym
+serdes_sync_200_full.pp=pp
+serdes_sync_200_full.tft=tft
+serdes_sync_200_full.txt=pcs_module
+serdes_sync_200_full.sym=sym
--- /dev/null
+#define _device_name "LFE3-150EA"
+#define _ch0_pll_rxsrc "REFCLK_CORE"
+#define _ch0_mode "RXTX"
+#define _ch0_protocol "G8B10B"
+#define _ch0_ldr "DISABLED"
+#define _ch0_tx_data_rate "FULL"
+#define _ch0_tx_data_width "8"
+#define _ch0_tx_fifo "DISABLED"
+#define _ch0_tx_ficlk_rate 200
+#define _ch0_rx_datarange "MEDHIGH"
+#define _ch0_rx_data_rate "FULL"
+#define _ch0_rxrefclk_rate "200"
+#define _ch0_rx_data_width "8"
+#define _ch0_rx_fifo "ENABLED"
+#define _ch0_rx_ficlk_rate 200
+#define _ch0_tdrv "1"
+#define _ch0_tx_pre "DISABLED"
+#define _ch0_rterm_tx "50"
+#define _ch0_rx_eq "DISABLED"
+#define _ch0_rterm_rx "50"
+#define _ch0_rx_dcc "DC"
+#define _los_threshold_lo0 "2"
+#define _ch0_tx_sb "DISABLED"
+#define _ch0_tx_8b10b "ENABLED"
+#define _ch0_rx_sb "DISABLED"
+#define _ch0_ird "DISABLED"
+#define _ch0_rx_8b10b "ENABLED"
+#define _ch0_rxwa "ENABLED"
+#define _ch0_ilsm "ENABLED"
+#define _ch0_scomma "K28P157"
+#define _ch0_comma_a "1100000101"
+#define _ch0_comma_b "0011111010"
+#define _ch0_comma_m "1111111100"
+#define _ch0_ctc "DISABLED"
+#define _ch0_cc_match_mode "1"
+#define _ch0_byten "0000011100"
+#define _ch0_byten1 "0000000000"
+#define _ch0_byten2 "0100011100"
+#define _ch0_byten3 "0100011100"
+#define _ch0_cc_min_ipg "3"
+#define _ch0_lbtype "DISABLED"
+#define _ch0_teidle "DISABLED"
+#define _ch0_rx_lol_port "INTERNAL"
+
+#define _ch1_pll_rxsrc "REFCLK_CORE"
+#define _ch1_mode "RXTX"
+#define _ch1_protocol "G8B10B"
+#define _ch1_ldr "DISABLED"
+#define _ch1_tx_data_rate "FULL"
+#define _ch1_tx_data_width "8"
+#define _ch1_tx_fifo "DISABLED"
+#define _ch1_tx_ficlk_rate 200
+#define _ch1_rx_datarange "MEDHIGH"
+#define _ch1_rx_data_rate "FULL"
+#define _ch1_rxrefclk_rate "200"
+#define _ch1_rx_data_width "8"
+#define _ch1_rx_fifo "ENABLED"
+#define _ch1_rx_ficlk_rate 200
+#define _ch1_tdrv "1"
+#define _ch1_tx_pre "DISABLED"
+#define _ch1_rterm_tx "50"
+#define _ch1_rx_eq "DISABLED"
+#define _ch1_rterm_rx "50"
+#define _ch1_rx_dcc "DC"
+#define _los_threshold_lo1 "2"
+#define _ch1_tx_sb "DISABLED"
+#define _ch1_tx_8b10b "ENABLED"
+#define _ch1_rx_sb "DISABLED"
+#define _ch1_ird "DISABLED"
+#define _ch1_rx_8b10b "ENABLED"
+#define _ch1_rxwa "ENABLED"
+#define _ch1_ilsm "ENABLED"
+#define _ch1_scomma "K28P157"
+#define _ch1_comma_a "1100000101"
+#define _ch1_comma_b "0011111010"
+#define _ch1_comma_m "1111111100"
+#define _ch1_ctc "DISABLED"
+#define _ch1_cc_match_mode "1"
+#define _ch1_byten "0000011100"
+#define _ch1_byten1 "0000000000"
+#define _ch1_byten2 "0100011100"
+#define _ch1_byten3 "0100011100"
+#define _ch1_cc_min_ipg "3"
+#define _ch1_lbtype "DISABLED"
+#define _ch1_teidle "DISABLED"
+#define _ch1_rx_lol_port "INTERNAL"
+
+#define _ch2_pll_rxsrc "REFCLK_CORE"
+#define _ch2_mode "RXTX"
+#define _ch2_protocol "G8B10B"
+#define _ch2_ldr "DISABLED"
+#define _ch2_tx_data_rate "FULL"
+#define _ch2_tx_data_width "8"
+#define _ch2_tx_fifo "DISABLED"
+#define _ch2_tx_ficlk_rate 200
+#define _ch2_rx_datarange "MEDHIGH"
+#define _ch2_rx_data_rate "FULL"
+#define _ch2_rxrefclk_rate "200"
+#define _ch2_rx_data_width "8"
+#define _ch2_rx_fifo "ENABLED"
+#define _ch2_rx_ficlk_rate 200
+#define _ch2_tdrv "1"
+#define _ch2_tx_pre "DISABLED"
+#define _ch2_rterm_tx "50"
+#define _ch2_rx_eq "DISABLED"
+#define _ch2_rterm_rx "50"
+#define _ch2_rx_dcc "DC"
+#define _los_threshold_lo2 "2"
+#define _ch2_tx_sb "DISABLED"
+#define _ch2_tx_8b10b "ENABLED"
+#define _ch2_rx_sb "DISABLED"
+#define _ch2_ird "DISABLED"
+#define _ch2_rx_8b10b "ENABLED"
+#define _ch2_rxwa "ENABLED"
+#define _ch2_ilsm "ENABLED"
+#define _ch2_scomma "K28P157"
+#define _ch2_comma_a "1100000101"
+#define _ch2_comma_b "0011111010"
+#define _ch2_comma_m "1111111100"
+#define _ch2_ctc "DISABLED"
+#define _ch2_cc_match_mode "1"
+#define _ch2_byten "0000011100"
+#define _ch2_byten1 "0000000000"
+#define _ch2_byten2 "0100011100"
+#define _ch2_byten3 "0100011100"
+#define _ch2_cc_min_ipg "3"
+#define _ch2_lbtype "DISABLED"
+#define _ch2_teidle "DISABLED"
+#define _ch2_rx_lol_port "INTERNAL"
+
+#define _ch3_pll_rxsrc "REFCLK_CORE"
+#define _ch3_mode "RXTX"
+#define _ch3_protocol "G8B10B"
+#define _ch3_ldr "DISABLED"
+#define _ch3_tx_data_rate "FULL"
+#define _ch3_tx_data_width "8"
+#define _ch3_tx_fifo "DISABLED"
+#define _ch3_tx_ficlk_rate 200
+#define _ch3_rx_datarange "MEDHIGH"
+#define _ch3_rx_data_rate "FULL"
+#define _ch3_rxrefclk_rate "200"
+#define _ch3_rx_data_width "8"
+#define _ch3_rx_fifo "ENABLED"
+#define _ch3_rx_ficlk_rate 200
+#define _ch3_tdrv "1"
+#define _ch3_tx_pre "DISABLED"
+#define _ch3_rterm_tx "50"
+#define _ch3_rx_eq "DISABLED"
+#define _ch3_rterm_rx "50"
+#define _ch3_rx_dcc "DC"
+#define _los_threshold_lo3 "2"
+#define _ch3_tx_sb "DISABLED"
+#define _ch3_tx_8b10b "ENABLED"
+#define _ch3_rx_sb "DISABLED"
+#define _ch3_ird "DISABLED"
+#define _ch3_rx_8b10b "ENABLED"
+#define _ch3_rxwa "ENABLED"
+#define _ch3_ilsm "ENABLED"
+#define _ch3_scomma "K28P157"
+#define _ch3_comma_a "1100000101"
+#define _ch3_comma_b "0011111010"
+#define _ch3_comma_m "1111111100"
+#define _ch3_ctc "DISABLED"
+#define _ch3_cc_match_mode "1"
+#define _ch3_byten "0000011100"
+#define _ch3_byten1 "0000000000"
+#define _ch3_byten2 "0100011100"
+#define _ch3_byten3 "0100011100"
+#define _ch3_cc_min_ipg "3"
+#define _ch3_lbtype "DISABLED"
+#define _ch3_teidle "DISABLED"
+#define _ch3_rx_lol_port "INTERNAL"
+
+#define _datarange "MEDHIGH"
+#define _pll_txsrc "REFCLK_CORE"
+#define _refclk_mult "10X"
+#define _refclk_rate 200
+#define _pll_term "50"
+#define _pll_dcc "AC"
+#define _pll_lol_set "1"
+#define _cchmark "9"
+#define _cclmark "7"
+#define _rst_gen "DISABLED"
+#define _sci_ports "ENABLED"
+#define _sci_int_port "DISABLED"
+#define _refck2core "DISABLED"
+#define _circuit_name serdes_sync_200_full
+#define _lang vhdl
+
+#include <pcs/PCSD.vhd>
+#include <pcs/pcsd_cfg.txt>
--- /dev/null
+@set suppresnewline=on@
+
+@comment --------------------------------------------------------------------- @
+@comment Template-drive TFI generator @
+@comment Template for TFI generation. @
+@comment --------------------------------------------------------------------- @
+
+@set suppresnewline=off@
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: %title%
+ MODULE: %module%
+ DESIGN: %module%
+ FILENAME: %filename%
+ PROJECT: %project%
+ VERSION: %ver%
+ This file is auto generated by the ispLEVER
+@set suppresnewline=on@
+
+@cr@
+@cr@
+
+@set sigdelim=@
+
+NOTE: This readme file has been provided to instantiate the interface@cr@
+netlist. Since this template contains synthesis attributes for precision that@cr@
+are crucial to the design flow, we recommend that you use this@cr@
+template in your FPGA design.@cr@
+entity chip is@cr@
+port (@cr@
+@cr@
+-- Add your FPGA design top level I/Os here@cr@
+@cr@
+@cr@
+-- ASIC side pins for PCSD. These pins must exist for the@cr@
+-- PCS core.@cr@
+ refclkp : in std_logic;@cr@
+ refclkn : in std_logic;@cr@
+ hdinp_ch0 : in std_logic;@cr@
+ hdinn_ch0 : in std_logic;@cr@
+ hdinp_ch1 : in std_logic;@cr@
+ hdinn_ch1 : in std_logic;@cr@
+ hdinp_ch2 : in std_logic;@cr@
+ hdinn_ch2 : in std_logic;@cr@
+ hdinp_ch3 : in std_logic;@cr@
+ hdinn_ch3 : in std_logic;@cr@
+@cr@
+ hdoutp_ch0 : out std_logic;@cr@
+ hdoutn_ch0 : out std_logic;@cr@
+ hdoutp_ch1 : out std_logic;@cr@
+ hdoutn_ch1 : out std_logic;@cr@
+ hdoutp_ch2 : out std_logic;@cr@
+ hdoutn_ch2 : out std_logic;@cr@
+ hdoutp_ch3 : out std_logic;@cr@
+ hdoutn_ch3 : out std_logic;@cr@
+@cr@
+@cr@
+);@cr@
+end chip;@cr@
+@cr@
+architecture chip_arch of chip is@cr@
+@cr@
+-- This defines all the high-speed ports. You may have to remove@cr@
+-- some of them depending on your design.@cr@
+attribute nopad : string;@cr@
+attribute nopad of@cr@
+ refclkp, refclkn,@cr@
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
+
+@cr@
+@tab@COMPONENT %module%
+@set sigdelim=@
+@cr@@tab@PORT(
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
+@ifhas oport=*@ @comment if the design has any output ports... @
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
+ @set sigdelim=;@
+ @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
+@endif@
+@ifnhas oport=*@ @comment we need an "else in this language! @
+ @set sigdelim=;@
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
+@endif@
+@cr@@tab@@tab@);@cr@
+@tab@END COMPONENT;@cr@@cr@
+@comment Now do a signal declaration for each port @
+
+@cr@@cr@
+@comment do the component instantiation @
+@set sigdelim=,@
+@tab@uut: %module% PORT MAP(
+@iterate@%port%
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
+@cr@@tab@);@cr@@cr@
+@set suppresnewline=off@
+
+
CH1_RX_FIFO "ENABLED"
CH2_RX_FIFO "ENABLED"
CH3_RX_FIFO "ENABLED"
-CH0_TDRV "0"
-CH1_TDRV "0"
-CH2_TDRV "0"
-CH3_TDRV "0"
+CH0_TDRV "1"
+CH1_TDRV "1"
+CH2_TDRV "1"
+CH3_TDRV "1"
#CH0_TX_FICLK_RATE 200
#CH1_TX_FICLK_RATE 200
#CH2_TX_FICLK_RATE 200
CH2_LOS_THRESHOLD_LO "2"
CH3_LOS_THRESHOLD_LO "2"
PLL_TERM "50"
-PLL_DCC "DC"
-PLL_LOL_SET "0"
+PLL_DCC "AC"
+PLL_LOL_SET "1"
CH0_TX_SB "DISABLED"
CH1_TX_SB "DISABLED"
CH2_TX_SB "DISABLED"
CH2_PCSLBPORTS "DISABLED"
CH3_PCSLBPORTS "DISABLED"
INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
+QD_REFCK2CORE "DISABLED"
CH2_CDR_SRC : String := "REFCLK_EXT";
CH3_CDR_SRC : String := "REFCLK_EXT";
PLL_SRC : String
--- CONFIG_FILE : String := "serdes_4_sync_downstream.txt";
+-- CONFIG_FILE : String := "serdes_sync_200_full.txt";
-- QUAD_MODE : String := "SINGLE";
-- CH0_CDR_SRC : String := "REFCLK_CORE";
-- CH1_CDR_SRC : String := "REFCLK_CORE";
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
-entity serdes_4_sync_downstream is
- GENERIC (USER_CONFIG_FILE : String := "serdes_4_sync_downstream.txt");
+entity serdes_sync_200_full is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_sync_200_full.txt");
port (
------------------
-- CH0 --
tx_pll_lol_qd_s : out std_logic;
tx_sync_qd_c : in std_logic;
rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
serdes_rst_qd_c : in std_logic);
-end serdes_4_sync_downstream;
+end serdes_sync_200_full;
-architecture serdes_4_sync_downstream_arch of serdes_4_sync_downstream is
+architecture serdes_sync_200_full_arch of serdes_sync_200_full is
component VLO
port (
attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
attribute black_box_pad_pin: string;
attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
vlo_inst : VLO port map(Z => fpsc_vlo);
vhi_inst : VHI port map(Z => fpsc_vhi);
- refclk2fpga <= refclk2fpga_sig;
rx_los_low_ch0_s <= rx_los_low_ch0_sig;
rx_los_low_ch1_s <= rx_los_low_ch1_sig;
rx_los_low_ch2_s <= rx_los_low_ch2_sig;
wait;
END PROCESS;
--synopsys translate_on
-end serdes_4_sync_downstream_arch ;
+end serdes_sync_200_full_arch ;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="sfp_3sync_200_int" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 07 13 09:03:34.099" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="sfp_3sync_200_int.lpc" type="lpc" modified="2015 07 13 09:03:29.063"/>
+ <File name="sfp_3sync_200_int.pp" type="pp" modified="2015 07 13 09:03:29.065"/>
+ <File name="sfp_3sync_200_int.sym" type="sym" modified="2015 07 13 09:03:29.325"/>
+ <File name="sfp_3sync_200_int.tft" type="tft" modified="2015 07 13 09:03:29.097"/>
+ <File name="sfp_3sync_200_int.txt" type="pcs_module" modified="2015 07 13 09:03:29.100"/>
+ <File name="sfp_3sync_200_int.vhd" type="top_level_vhdl" modified="2015 07 13 09:03:29.096"/>
+ </Package>
+</DiamondModule>
CoreStatus=Demo
CoreName=PCS
CoreRevision=8.2
-ModuleName=serdes_sync_upstream
+ModuleName=sfp_3sync_200_int
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=03/04/2015
-Time=13:04:49
+Date=07/13/2015
+Time=09:03:29
[Parameters]
Verilog=0
IO=0
_mode0=DISABLED
_mode1=DISABLED
-_mode2=DISABLED
-_mode3=RXTX
+_mode2=RXTX
+_mode3=DISABLED
_protocol0=G8B10B
_protocol1=G8B10B
_protocol2=G8B10B
_refclk_rate=200
_tx_protocol0=DISABLED
_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=G8B10B
+_tx_protocol2=G8B10B
+_tx_protocol3=DISABLED
_tx_data_rate0=FULL
_tx_data_rate1=FULL
_tx_data_rate2=FULL
_tx_data_width3=8
_tx_fifo0=ENABLED
_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
+_tx_fifo2=DISABLED
+_tx_fifo3=ENABLED
_tx_ficlk_rate0=200
_tx_ficlk_rate1=200
_tx_ficlk_rate2=200
_tx_ficlk_rate3=200
_pll_rxsrc0=EXTERNAL
_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
+_pll_rxsrc2=INTERNAL
+_pll_rxsrc3=EXTERNAL
Multiplier0=
Multiplier1=
Multiplier2=
Multiplier3=
_rx_datarange0=2.5
_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=2
+_rx_datarange2=2
+_rx_datarange3=2.5
_rx_protocol0=DISABLED
_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=G8B10B
+_rx_protocol2=G8B10B
+_rx_protocol3=DISABLED
_rx_data_rate0=FULL
_rx_data_rate1=FULL
_rx_data_rate2=FULL
_rx_data_rate3=FULL
_rxrefclk_rate0=250.0
_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=200
+_rxrefclk_rate2=200
+_rxrefclk_rate3=250.0
_rx_data_width0=8
_rx_data_width1=8
_rx_data_width2=8
_rx_fifo0=ENABLED
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
-_rx_fifo3=DISABLED
+_rx_fifo3=ENABLED
_rx_ficlk_rate0=250.0
_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=200
+_rx_ficlk_rate2=200
+_rx_ficlk_rate3=250.0
_tdrv_ch0=0
_tdrv_ch1=0
_tdrv_ch2=0
_rterm_rx3=50
_rx_dcc0=AC
_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=DC
+_rx_dcc2=DC
+_rx_dcc3=AC
_los_threshold_mode0=LOS_E
_los_threshold_mode1=LOS_E
_los_threshold_mode2=LOS_E
_rx_los_port3=Internal
_sci_ports=ENABLED
_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
+_refck2core=DISABLED
+Regen=auto
PAR1=0
PARTrace1=0
PAR3=0
PARTrace3=0
[FilesGenerated]
-serdes_sync_upstream.pp=pp
-serdes_sync_upstream.tft=tft
-serdes_sync_upstream.txt=pcs_module
-serdes_sync_upstream.sym=sym
+sfp_3sync_200_int.pp=pp
+sfp_3sync_200_int.tft=tft
+sfp_3sync_200_int.txt=pcs_module
+sfp_3sync_200_int.sym=sym
--- /dev/null
+#define _device_name "LFE3-150EA"
+#define _ch0_pll_rxsrc "REFCLK_EXT"
+#define _ch0_mode "DISABLED"
+#define _ch0_protocol "G8B10B"
+#define _ch0_ldr "DISABLED"
+#define _ch0_tx_data_rate "FULL"
+#define _ch0_tx_data_width "8"
+#define _ch0_tx_fifo "ENABLED"
+#define _ch0_tx_ficlk_rate 200
+#define _ch0_rx_datarange "MEDHIGH"
+#define _ch0_rx_data_rate "FULL"
+#define _ch0_rxrefclk_rate "250.0"
+#define _ch0_rx_data_width "8"
+#define _ch0_rx_fifo "ENABLED"
+#define _ch0_rx_ficlk_rate 250.0
+#define _ch0_tdrv "0"
+#define _ch0_tx_pre "DISABLED"
+#define _ch0_rterm_tx "50"
+#define _ch0_rx_eq "DISABLED"
+#define _ch0_rterm_rx "50"
+#define _ch0_rx_dcc "AC"
+#define _los_threshold_lo0 "2"
+#define _ch0_tx_sb "DISABLED"
+#define _ch0_tx_8b10b "ENABLED"
+#define _ch0_rx_sb "DISABLED"
+#define _ch0_ird "DISABLED"
+#define _ch0_rx_8b10b "ENABLED"
+#define _ch0_rxwa "ENABLED"
+#define _ch0_ilsm "ENABLED"
+#define _ch0_scomma "K28P157"
+#define _ch0_comma_a "1100000101"
+#define _ch0_comma_b "0011111010"
+#define _ch0_comma_m "1111111100"
+#define _ch0_ctc "DISABLED"
+#define _ch0_cc_match_mode "1"
+#define _ch0_byten "0000000000"
+#define _ch0_byten1 "0000000000"
+#define _ch0_byten2 "0100011100"
+#define _ch0_byten3 "0100011100"
+#define _ch0_cc_min_ipg "3"
+#define _ch0_lbtype "DISABLED"
+#define _ch0_teidle "DISABLED"
+#define _ch0_rx_lol_port "INTERNAL"
+
+#define _ch1_pll_rxsrc "REFCLK_EXT"
+#define _ch1_mode "DISABLED"
+#define _ch1_protocol "G8B10B"
+#define _ch1_ldr "DISABLED"
+#define _ch1_tx_data_rate "FULL"
+#define _ch1_tx_data_width "8"
+#define _ch1_tx_fifo "ENABLED"
+#define _ch1_tx_ficlk_rate 200
+#define _ch1_rx_datarange "MEDHIGH"
+#define _ch1_rx_data_rate "FULL"
+#define _ch1_rxrefclk_rate "250.0"
+#define _ch1_rx_data_width "8"
+#define _ch1_rx_fifo "ENABLED"
+#define _ch1_rx_ficlk_rate 250.0
+#define _ch1_tdrv "0"
+#define _ch1_tx_pre "DISABLED"
+#define _ch1_rterm_tx "50"
+#define _ch1_rx_eq "DISABLED"
+#define _ch1_rterm_rx "50"
+#define _ch1_rx_dcc "AC"
+#define _los_threshold_lo1 "2"
+#define _ch1_tx_sb "DISABLED"
+#define _ch1_tx_8b10b "ENABLED"
+#define _ch1_rx_sb "DISABLED"
+#define _ch1_ird "DISABLED"
+#define _ch1_rx_8b10b "ENABLED"
+#define _ch1_rxwa "ENABLED"
+#define _ch1_ilsm "ENABLED"
+#define _ch1_scomma "K28P157"
+#define _ch1_comma_a "1100000101"
+#define _ch1_comma_b "0011111010"
+#define _ch1_comma_m "1111111100"
+#define _ch1_ctc "DISABLED"
+#define _ch1_cc_match_mode "1"
+#define _ch1_byten "0000000000"
+#define _ch1_byten1 "0000000000"
+#define _ch1_byten2 "0100011100"
+#define _ch1_byten3 "0100011100"
+#define _ch1_cc_min_ipg "3"
+#define _ch1_lbtype "DISABLED"
+#define _ch1_teidle "DISABLED"
+#define _ch1_rx_lol_port "INTERNAL"
+
+#define _ch2_pll_rxsrc "REFCLK_CORE"
+#define _ch2_mode "RXTX"
+#define _ch2_protocol "G8B10B"
+#define _ch2_ldr "DISABLED"
+#define _ch2_tx_data_rate "FULL"
+#define _ch2_tx_data_width "8"
+#define _ch2_tx_fifo "DISABLED"
+#define _ch2_tx_ficlk_rate 200
+#define _ch2_rx_datarange "MEDHIGH"
+#define _ch2_rx_data_rate "FULL"
+#define _ch2_rxrefclk_rate "200"
+#define _ch2_rx_data_width "8"
+#define _ch2_rx_fifo "ENABLED"
+#define _ch2_rx_ficlk_rate 200
+#define _ch2_tdrv "0"
+#define _ch2_tx_pre "DISABLED"
+#define _ch2_rterm_tx "50"
+#define _ch2_rx_eq "DISABLED"
+#define _ch2_rterm_rx "50"
+#define _ch2_rx_dcc "DC"
+#define _los_threshold_lo2 "2"
+#define _ch2_tx_sb "DISABLED"
+#define _ch2_tx_8b10b "ENABLED"
+#define _ch2_rx_sb "DISABLED"
+#define _ch2_ird "DISABLED"
+#define _ch2_rx_8b10b "ENABLED"
+#define _ch2_rxwa "ENABLED"
+#define _ch2_ilsm "ENABLED"
+#define _ch2_scomma "K28P157"
+#define _ch2_comma_a "1100000101"
+#define _ch2_comma_b "0011111010"
+#define _ch2_comma_m "1111111100"
+#define _ch2_ctc "DISABLED"
+#define _ch2_cc_match_mode "1"
+#define _ch2_byten "0000000000"
+#define _ch2_byten1 "0000000000"
+#define _ch2_byten2 "0100011100"
+#define _ch2_byten3 "0100011100"
+#define _ch2_cc_min_ipg "3"
+#define _ch2_lbtype "DISABLED"
+#define _ch2_teidle "DISABLED"
+#define _ch2_rx_lol_port "INTERNAL"
+
+#define _ch3_pll_rxsrc "REFCLK_EXT"
+#define _ch3_mode "DISABLED"
+#define _ch3_protocol "G8B10B"
+#define _ch3_ldr "DISABLED"
+#define _ch3_tx_data_rate "FULL"
+#define _ch3_tx_data_width "8"
+#define _ch3_tx_fifo "ENABLED"
+#define _ch3_tx_ficlk_rate 200
+#define _ch3_rx_datarange "MEDHIGH"
+#define _ch3_rx_data_rate "FULL"
+#define _ch3_rxrefclk_rate "250.0"
+#define _ch3_rx_data_width "8"
+#define _ch3_rx_fifo "ENABLED"
+#define _ch3_rx_ficlk_rate 250.0
+#define _ch3_tdrv "0"
+#define _ch3_tx_pre "DISABLED"
+#define _ch3_rterm_tx "50"
+#define _ch3_rx_eq "DISABLED"
+#define _ch3_rterm_rx "50"
+#define _ch3_rx_dcc "AC"
+#define _los_threshold_lo3 "2"
+#define _ch3_tx_sb "DISABLED"
+#define _ch3_tx_8b10b "ENABLED"
+#define _ch3_rx_sb "DISABLED"
+#define _ch3_ird "DISABLED"
+#define _ch3_rx_8b10b "ENABLED"
+#define _ch3_rxwa "ENABLED"
+#define _ch3_ilsm "ENABLED"
+#define _ch3_scomma "K28P157"
+#define _ch3_comma_a "1100000101"
+#define _ch3_comma_b "0011111010"
+#define _ch3_comma_m "1111111100"
+#define _ch3_ctc "DISABLED"
+#define _ch3_cc_match_mode "1"
+#define _ch3_byten "0000000000"
+#define _ch3_byten1 "0000000000"
+#define _ch3_byten2 "0100011100"
+#define _ch3_byten3 "0100011100"
+#define _ch3_cc_min_ipg "3"
+#define _ch3_lbtype "DISABLED"
+#define _ch3_teidle "DISABLED"
+#define _ch3_rx_lol_port "INTERNAL"
+
+#define _datarange "MEDHIGH"
+#define _pll_txsrc "REFCLK_CORE"
+#define _refclk_mult "10X"
+#define _refclk_rate 200
+#define _pll_term "50"
+#define _pll_dcc "AC"
+#define _pll_lol_set "0"
+#define _cchmark "9"
+#define _cclmark "7"
+#define _rst_gen "DISABLED"
+#define _sci_ports "ENABLED"
+#define _sci_int_port "DISABLED"
+#define _refck2core "DISABLED"
+#define _circuit_name sfp_3sync_200_int
+#define _lang vhdl
+
+#include <pcs/PCSD.vhd>
+#include <pcs/pcsd_cfg.txt>
--- /dev/null
+@set suppresnewline=on@
+
+@comment --------------------------------------------------------------------- @
+@comment Template-drive TFI generator @
+@comment Template for TFI generation. @
+@comment --------------------------------------------------------------------- @
+
+@set suppresnewline=off@
+ TOOL: orcapp
+ DATE: 19-MAR-2008 13:11:52
+ TITLE: %title%
+ MODULE: %module%
+ DESIGN: %module%
+ FILENAME: %filename%
+ PROJECT: %project%
+ VERSION: %ver%
+ This file is auto generated by the ispLEVER
+@set suppresnewline=on@
+
+@cr@
+@cr@
+
+@set sigdelim=@
+
+NOTE: This readme file has been provided to instantiate the interface@cr@
+netlist. Since this template contains synthesis attributes for precision that@cr@
+are crucial to the design flow, we recommend that you use this@cr@
+template in your FPGA design.@cr@
+entity chip is@cr@
+port (@cr@
+@cr@
+-- Add your FPGA design top level I/Os here@cr@
+@cr@
+@cr@
+-- ASIC side pins for PCSD. These pins must exist for the@cr@
+-- PCS core.@cr@
+ refclkp : in std_logic;@cr@
+ refclkn : in std_logic;@cr@
+ hdinp_ch0 : in std_logic;@cr@
+ hdinn_ch0 : in std_logic;@cr@
+ hdinp_ch1 : in std_logic;@cr@
+ hdinn_ch1 : in std_logic;@cr@
+ hdinp_ch2 : in std_logic;@cr@
+ hdinn_ch2 : in std_logic;@cr@
+ hdinp_ch3 : in std_logic;@cr@
+ hdinn_ch3 : in std_logic;@cr@
+@cr@
+ hdoutp_ch0 : out std_logic;@cr@
+ hdoutn_ch0 : out std_logic;@cr@
+ hdoutp_ch1 : out std_logic;@cr@
+ hdoutn_ch1 : out std_logic;@cr@
+ hdoutp_ch2 : out std_logic;@cr@
+ hdoutn_ch2 : out std_logic;@cr@
+ hdoutp_ch3 : out std_logic;@cr@
+ hdoutn_ch3 : out std_logic;@cr@
+@cr@
+@cr@
+);@cr@
+end chip;@cr@
+@cr@
+architecture chip_arch of chip is@cr@
+@cr@
+-- This defines all the high-speed ports. You may have to remove@cr@
+-- some of them depending on your design.@cr@
+attribute nopad : string;@cr@
+attribute nopad of@cr@
+ refclkp, refclkn,@cr@
+ hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
+ hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
+ hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
+ hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
+
+@cr@
+@tab@COMPONENT %module%
+@set sigdelim=@
+@cr@@tab@PORT(
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
+@ifhas oport=*@ @comment if the design has any output ports... @
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
+ @set sigdelim=;@
+ @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
+@endif@
+@ifnhas oport=*@ @comment we need an "else in this language! @
+ @set sigdelim=;@
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
+@endif@
+@cr@@tab@@tab@);@cr@
+@tab@END COMPONENT;@cr@@cr@
+@comment Now do a signal declaration for each port @
+
+@cr@@cr@
+@comment do the component instantiation @
+@set sigdelim=,@
+@tab@uut: %module% PORT MAP(
+@iterate@%port%
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
+@cr@@tab@);@cr@@cr@
+@set suppresnewline=off@
+
+
--- /dev/null
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH2_PROTOCOL "G8B10B"
+CH0_MODE "DISABLED"
+CH1_MODE "DISABLED"
+CH2_MODE "RXTX"
+CH3_MODE "DISABLED"
+CH2_CDR_SRC "REFCLK_CORE"
+PLL_SRC "REFCLK_CORE"
+TX_DATARATE_RANGE "MEDHIGH"
+CH2_RX_DATARATE_RANGE "MEDHIGH"
+REFCK_MULT "10X"
+#REFCLK_RATE 200
+CH2_RX_DATA_RATE "FULL"
+CH2_TX_DATA_RATE "FULL"
+CH2_TX_DATA_WIDTH "8"
+CH2_RX_DATA_WIDTH "8"
+CH2_TX_FIFO "DISABLED"
+CH2_RX_FIFO "ENABLED"
+CH2_TDRV "0"
+#CH2_TX_FICLK_RATE 200
+#CH2_RXREFCLK_RATE "200"
+#CH2_RX_FICLK_RATE 200
+CH2_TX_PRE "DISABLED"
+CH2_RTERM_TX "50"
+CH2_RX_EQ "DISABLED"
+CH2_RTERM_RX "50"
+CH2_RX_DCC "DC"
+CH2_LOS_THRESHOLD_LO "2"
+PLL_TERM "50"
+PLL_DCC "AC"
+PLL_LOL_SET "0"
+CH2_TX_SB "DISABLED"
+CH2_RX_SB "DISABLED"
+CH2_TX_8B10B "ENABLED"
+CH2_RX_8B10B "ENABLED"
+CH2_COMMA_A "1100000101"
+CH2_COMMA_B "0011111010"
+CH2_COMMA_M "1111111100"
+CH2_RXWA "ENABLED"
+CH2_ILSM "ENABLED"
+CH2_CTC "DISABLED"
+CH2_CC_MATCH4 "0000000000"
+CH2_CC_MATCH_MODE "1"
+CH2_CC_MIN_IPG "3"
+CCHMARK "9"
+CCLMARK "7"
+CH2_SSLB "DISABLED"
+CH2_SPLBPORTS "DISABLED"
+CH2_PCSLBPORTS "DISABLED"
+INT_ALL "DISABLED"
+QD_REFCK2CORE "DISABLED"
+
+
CH2_CDR_SRC : String := "REFCLK_EXT";
CH3_CDR_SRC : String := "REFCLK_EXT";
PLL_SRC : String
--- CONFIG_FILE : String := "serdes_sync_upstream.txt";
+-- CONFIG_FILE : String := "sfp_3sync_200_int.txt";
-- QUAD_MODE : String := "SINGLE";
-- CH0_CDR_SRC : String := "REFCLK_EXT";
-- CH1_CDR_SRC : String := "REFCLK_EXT";
--- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_CORE";
+-- CH2_CDR_SRC : String := "REFCLK_CORE";
+-- CH3_CDR_SRC : String := "REFCLK_EXT";
-- PLL_SRC : String := "REFCLK_CORE"
);
port (
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
-entity serdes_sync_upstream is
- GENERIC (USER_CONFIG_FILE : String := "serdes_sync_upstream.txt");
+entity sfp_3sync_200_int is
+ GENERIC (USER_CONFIG_FILE : String := "sfp_3sync_200_int.txt");
port (
------------------
-- CH0 --
-- CH1 --
-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ sci_sel_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (7 downto 0);
+ tx_k_ch2 : in std_logic;
+ tx_force_disp_ch2 : in std_logic;
+ tx_disp_sel_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ rx_serdes_rst_ch2_c : in std_logic;
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pcs_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pcs_rst_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ tx_div2_mode_ch2_c : in std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
-- CH3 --
- hdinp_ch3, hdinn_ch3 : in std_logic;
- hdoutp_ch3, hdoutn_ch3 : out std_logic;
- sci_sel_ch3 : in std_logic;
- txiclk_ch3 : in std_logic;
- rx_full_clk_ch3 : out std_logic;
- rx_half_clk_ch3 : out std_logic;
- tx_full_clk_ch3 : out std_logic;
- tx_half_clk_ch3 : out std_logic;
- fpga_rxrefclk_ch3 : in std_logic;
- txdata_ch3 : in std_logic_vector (7 downto 0);
- tx_k_ch3 : in std_logic;
- tx_force_disp_ch3 : in std_logic;
- tx_disp_sel_ch3 : in std_logic;
- rxdata_ch3 : out std_logic_vector (7 downto 0);
- rx_k_ch3 : out std_logic;
- rx_disp_err_ch3 : out std_logic;
- rx_cv_err_ch3 : out std_logic;
- rx_serdes_rst_ch3_c : in std_logic;
- sb_felb_ch3_c : in std_logic;
- sb_felb_rst_ch3_c : in std_logic;
- tx_pcs_rst_ch3_c : in std_logic;
- tx_pwrup_ch3_c : in std_logic;
- rx_pcs_rst_ch3_c : in std_logic;
- rx_pwrup_ch3_c : in std_logic;
- rx_los_low_ch3_s : out std_logic;
- lsm_status_ch3_s : out std_logic;
- rx_cdr_lol_ch3_s : out std_logic;
- tx_div2_mode_ch3_c : in std_logic;
- rx_div2_mode_ch3_c : in std_logic;
---- Miscillaneous ports
sci_wrdata : in std_logic_vector (7 downto 0);
sci_addr : in std_logic_vector (5 downto 0);
tx_serdes_rst_c : in std_logic;
tx_pll_lol_qd_s : out std_logic;
rst_qd_c : in std_logic;
- refclk2fpga : out std_logic;
serdes_rst_qd_c : in std_logic);
-end serdes_sync_upstream;
+end sfp_3sync_200_int;
-architecture serdes_sync_upstream_arch of serdes_sync_upstream is
+architecture sfp_3sync_200_int_arch of sfp_3sync_200_int is
component VLO
port (
attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
attribute PLL_SRC: string;
attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
- attribute CH3_CDR_SRC: string;
- attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH2_CDR_SRC: string;
+ attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
- attribute FREQUENCY_PIN_REFCK2CORE: string;
- attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
attribute black_box_pad_pin: string;
attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
signal fpsc_vhi : std_logic := '1';
signal cin : std_logic_vector (11 downto 0) := "000000000000";
signal cout : std_logic_vector (19 downto 0);
-signal tx_full_clk_ch3_sig : std_logic;
+signal tx_full_clk_ch2_sig : std_logic;
signal refclk2fpga_sig : std_logic;
signal tx_pll_lol_qd_sig : std_logic;
vlo_inst : VLO port map(Z => fpsc_vlo);
vhi_inst : VHI port map(Z => fpsc_vhi);
- refclk2fpga <= refclk2fpga_sig;
- rx_los_low_ch3_s <= rx_los_low_ch3_sig;
- rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+ rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+ rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
- tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+ tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
-- pcs_quad instance
PCSD_INST : PCSD
--synopsys translate_off
generic map (CONFIG_FILE => USER_CONFIG_FILE,
QUAD_MODE => "SINGLE",
- CH3_CDR_SRC => "REFCLK_CORE",
+ CH2_CDR_SRC => "REFCLK_CORE",
PLL_SRC => "REFCLK_CORE"
)
--synopsys translate_on
FFC_RATE_MODE_RX_1 => fpsc_vlo,
----- CH2 -----
- HDOUTP2 => open,
- HDOUTN2 => open,
- HDINP2 => fpsc_vlo,
- HDINN2 => fpsc_vlo,
+ HDOUTP2 => hdoutp_ch2,
+ HDOUTN2 => hdoutn_ch2,
+ HDINP2 => hdinp_ch2,
+ HDINN2 => hdinn_ch2,
PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
PCIE_RXPOLARITY_2 => fpsc_vlo,
PCIE_POWERDOWN_2_1 => fpsc_vlo,
PCIE_RXVALID_2 => open,
PCIE_PHYSTATUS_2 => open,
- SCISELCH2 => fpsc_vlo,
- SCIENCH2 => fpsc_vlo,
- FF_RXI_CLK_2 => fpsc_vlo,
- FF_TXI_CLK_2 => fpsc_vlo,
+ SCISELCH2 => sci_sel_ch2,
+ SCIENCH2 => fpsc_vhi,
+ FF_RXI_CLK_2 => rxiclk_ch2,
+ FF_TXI_CLK_2 => txiclk_ch2,
FF_EBRD_CLK_2 => fpsc_vlo,
- FF_RX_F_CLK_2 => open,
- FF_RX_H_CLK_2 => open,
- FF_TX_F_CLK_2 => open,
- FF_TX_H_CLK_2 => open,
- FFC_CK_CORE_RX_2 => fpsc_vlo,
- FF_TX_D_2_0 => fpsc_vlo,
- FF_TX_D_2_1 => fpsc_vlo,
- FF_TX_D_2_2 => fpsc_vlo,
- FF_TX_D_2_3 => fpsc_vlo,
- FF_TX_D_2_4 => fpsc_vlo,
- FF_TX_D_2_5 => fpsc_vlo,
- FF_TX_D_2_6 => fpsc_vlo,
- FF_TX_D_2_7 => fpsc_vlo,
- FF_TX_D_2_8 => fpsc_vlo,
- FF_TX_D_2_9 => fpsc_vlo,
- FF_TX_D_2_10 => fpsc_vlo,
+ FF_RX_F_CLK_2 => rx_full_clk_ch2,
+ FF_RX_H_CLK_2 => rx_half_clk_ch2,
+ FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
+ FF_TX_H_CLK_2 => tx_half_clk_ch2,
+ FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+ FF_TX_D_2_0 => txdata_ch2(0),
+ FF_TX_D_2_1 => txdata_ch2(1),
+ FF_TX_D_2_2 => txdata_ch2(2),
+ FF_TX_D_2_3 => txdata_ch2(3),
+ FF_TX_D_2_4 => txdata_ch2(4),
+ FF_TX_D_2_5 => txdata_ch2(5),
+ FF_TX_D_2_6 => txdata_ch2(6),
+ FF_TX_D_2_7 => txdata_ch2(7),
+ FF_TX_D_2_8 => tx_k_ch2,
+ FF_TX_D_2_9 => tx_force_disp_ch2,
+ FF_TX_D_2_10 => tx_disp_sel_ch2,
FF_TX_D_2_11 => fpsc_vlo,
FF_TX_D_2_12 => fpsc_vlo,
FF_TX_D_2_13 => fpsc_vlo,
FF_TX_D_2_21 => fpsc_vlo,
FF_TX_D_2_22 => fpsc_vlo,
FF_TX_D_2_23 => fpsc_vlo,
- FF_RX_D_2_0 => open,
- FF_RX_D_2_1 => open,
- FF_RX_D_2_2 => open,
- FF_RX_D_2_3 => open,
- FF_RX_D_2_4 => open,
- FF_RX_D_2_5 => open,
- FF_RX_D_2_6 => open,
- FF_RX_D_2_7 => open,
- FF_RX_D_2_8 => open,
- FF_RX_D_2_9 => open,
- FF_RX_D_2_10 => open,
+ FF_RX_D_2_0 => rxdata_ch2(0),
+ FF_RX_D_2_1 => rxdata_ch2(1),
+ FF_RX_D_2_2 => rxdata_ch2(2),
+ FF_RX_D_2_3 => rxdata_ch2(3),
+ FF_RX_D_2_4 => rxdata_ch2(4),
+ FF_RX_D_2_5 => rxdata_ch2(5),
+ FF_RX_D_2_6 => rxdata_ch2(6),
+ FF_RX_D_2_7 => rxdata_ch2(7),
+ FF_RX_D_2_8 => rx_k_ch2,
+ FF_RX_D_2_9 => rx_disp_err_ch2,
+ FF_RX_D_2_10 => rx_cv_err_ch2,
FF_RX_D_2_11 => open,
FF_RX_D_2_12 => open,
FF_RX_D_2_13 => open,
FF_RX_D_2_22 => open,
FF_RX_D_2_23 => open,
- FFC_RRST_2 => fpsc_vlo,
+ FFC_RRST_2 => rx_serdes_rst_ch2_c,
FFC_SIGNAL_DETECT_2 => fpsc_vlo,
- FFC_SB_PFIFO_LP_2 => fpsc_vlo,
- FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
+ FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
FFC_SB_INV_RX_2 => fpsc_vlo,
FFC_PCIE_CT_2 => fpsc_vlo,
FFC_PCI_DET_EN_2 => fpsc_vlo,
FFC_FB_LOOPBACK_2 => fpsc_vlo,
FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
FFC_EI_EN_2 => fpsc_vlo,
- FFC_LANE_TX_RST_2 => fpsc_vlo,
- FFC_TXPWDNB_2 => fpsc_vlo,
- FFC_LANE_RX_RST_2 => fpsc_vlo,
- FFC_RXPWDNB_2 => fpsc_vlo,
- FFS_RLOS_LO_2 => open,
+ FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
+ FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
+ FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+ FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
+ FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
FFS_RLOS_HI_2 => open,
FFS_PCIE_CON_2 => open,
FFS_PCIE_DONE_2 => open,
- FFS_LS_SYNC_STATUS_2 => open,
+ FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
FFS_CC_OVERRUN_2 => open,
FFS_CC_UNDERRUN_2 => open,
FFS_SKP_ADDED_2 => open,
FFS_SKP_DELETED_2 => open,
- FFS_RLOL_2 => open,
+ FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
FFS_RXFBFIFO_ERROR_2 => open,
FFS_TXFBFIFO_ERROR_2 => open,
LDR_CORE2TX_2 => fpsc_vlo,
LDR_RX2CORE_2 => open,
FFS_CDR_TRAIN_DONE_2 => open,
FFC_DIV11_MODE_TX_2 => fpsc_vlo,
- FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
FFC_DIV11_MODE_RX_2 => fpsc_vlo,
- FFC_RATE_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
----- CH3 -----
- HDOUTP3 => hdoutp_ch3,
- HDOUTN3 => hdoutn_ch3,
- HDINP3 => hdinp_ch3,
- HDINN3 => hdinn_ch3,
+ HDOUTP3 => open,
+ HDOUTN3 => open,
+ HDINP3 => fpsc_vlo,
+ HDINN3 => fpsc_vlo,
PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
PCIE_RXPOLARITY_3 => fpsc_vlo,
PCIE_POWERDOWN_3_1 => fpsc_vlo,
PCIE_RXVALID_3 => open,
PCIE_PHYSTATUS_3 => open,
- SCISELCH3 => sci_sel_ch3,
- SCIENCH3 => fpsc_vhi,
+ SCISELCH3 => fpsc_vlo,
+ SCIENCH3 => fpsc_vlo,
FF_RXI_CLK_3 => fpsc_vlo,
- FF_TXI_CLK_3 => txiclk_ch3,
+ FF_TXI_CLK_3 => fpsc_vlo,
FF_EBRD_CLK_3 => fpsc_vlo,
- FF_RX_F_CLK_3 => rx_full_clk_ch3,
- FF_RX_H_CLK_3 => rx_half_clk_ch3,
- FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
- FF_TX_H_CLK_3 => tx_half_clk_ch3,
- FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
- FF_TX_D_3_0 => txdata_ch3(0),
- FF_TX_D_3_1 => txdata_ch3(1),
- FF_TX_D_3_2 => txdata_ch3(2),
- FF_TX_D_3_3 => txdata_ch3(3),
- FF_TX_D_3_4 => txdata_ch3(4),
- FF_TX_D_3_5 => txdata_ch3(5),
- FF_TX_D_3_6 => txdata_ch3(6),
- FF_TX_D_3_7 => txdata_ch3(7),
- FF_TX_D_3_8 => tx_k_ch3,
- FF_TX_D_3_9 => tx_force_disp_ch3,
- FF_TX_D_3_10 => tx_disp_sel_ch3,
+ FF_RX_F_CLK_3 => open,
+ FF_RX_H_CLK_3 => open,
+ FF_TX_F_CLK_3 => open,
+ FF_TX_H_CLK_3 => open,
+ FFC_CK_CORE_RX_3 => fpsc_vlo,
+ FF_TX_D_3_0 => fpsc_vlo,
+ FF_TX_D_3_1 => fpsc_vlo,
+ FF_TX_D_3_2 => fpsc_vlo,
+ FF_TX_D_3_3 => fpsc_vlo,
+ FF_TX_D_3_4 => fpsc_vlo,
+ FF_TX_D_3_5 => fpsc_vlo,
+ FF_TX_D_3_6 => fpsc_vlo,
+ FF_TX_D_3_7 => fpsc_vlo,
+ FF_TX_D_3_8 => fpsc_vlo,
+ FF_TX_D_3_9 => fpsc_vlo,
+ FF_TX_D_3_10 => fpsc_vlo,
FF_TX_D_3_11 => fpsc_vlo,
FF_TX_D_3_12 => fpsc_vlo,
FF_TX_D_3_13 => fpsc_vlo,
FF_TX_D_3_21 => fpsc_vlo,
FF_TX_D_3_22 => fpsc_vlo,
FF_TX_D_3_23 => fpsc_vlo,
- FF_RX_D_3_0 => rxdata_ch3(0),
- FF_RX_D_3_1 => rxdata_ch3(1),
- FF_RX_D_3_2 => rxdata_ch3(2),
- FF_RX_D_3_3 => rxdata_ch3(3),
- FF_RX_D_3_4 => rxdata_ch3(4),
- FF_RX_D_3_5 => rxdata_ch3(5),
- FF_RX_D_3_6 => rxdata_ch3(6),
- FF_RX_D_3_7 => rxdata_ch3(7),
- FF_RX_D_3_8 => rx_k_ch3,
- FF_RX_D_3_9 => rx_disp_err_ch3,
- FF_RX_D_3_10 => rx_cv_err_ch3,
+ FF_RX_D_3_0 => open,
+ FF_RX_D_3_1 => open,
+ FF_RX_D_3_2 => open,
+ FF_RX_D_3_3 => open,
+ FF_RX_D_3_4 => open,
+ FF_RX_D_3_5 => open,
+ FF_RX_D_3_6 => open,
+ FF_RX_D_3_7 => open,
+ FF_RX_D_3_8 => open,
+ FF_RX_D_3_9 => open,
+ FF_RX_D_3_10 => open,
FF_RX_D_3_11 => open,
FF_RX_D_3_12 => open,
FF_RX_D_3_13 => open,
FF_RX_D_3_22 => open,
FF_RX_D_3_23 => open,
- FFC_RRST_3 => rx_serdes_rst_ch3_c,
+ FFC_RRST_3 => fpsc_vlo,
FFC_SIGNAL_DETECT_3 => fpsc_vlo,
- FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
- FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+ FFC_PFIFO_CLR_3 => fpsc_vlo,
FFC_SB_INV_RX_3 => fpsc_vlo,
FFC_PCIE_CT_3 => fpsc_vlo,
FFC_PCI_DET_EN_3 => fpsc_vlo,
FFC_FB_LOOPBACK_3 => fpsc_vlo,
FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
FFC_EI_EN_3 => fpsc_vlo,
- FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
- FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
- FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
- FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
- FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+ FFC_LANE_TX_RST_3 => fpsc_vlo,
+ FFC_TXPWDNB_3 => fpsc_vlo,
+ FFC_LANE_RX_RST_3 => fpsc_vlo,
+ FFC_RXPWDNB_3 => fpsc_vlo,
+ FFS_RLOS_LO_3 => open,
FFS_RLOS_HI_3 => open,
FFS_PCIE_CON_3 => open,
FFS_PCIE_DONE_3 => open,
- FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+ FFS_LS_SYNC_STATUS_3 => open,
FFS_CC_OVERRUN_3 => open,
FFS_CC_UNDERRUN_3 => open,
FFS_SKP_ADDED_3 => open,
FFS_SKP_DELETED_3 => open,
- FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+ FFS_RLOL_3 => open,
FFS_RXFBFIFO_ERROR_3 => open,
FFS_TXFBFIFO_ERROR_3 => open,
LDR_CORE2TX_3 => fpsc_vlo,
LDR_RX2CORE_3 => open,
FFS_CDR_TRAIN_DONE_3 => open,
FFC_DIV11_MODE_TX_3 => fpsc_vlo,
- FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+ FFC_RATE_MODE_TX_3 => fpsc_vlo,
FFC_DIV11_MODE_RX_3 => fpsc_vlo,
- FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+ FFC_RATE_MODE_RX_3 => fpsc_vlo,
----- Auxilliary ----
SCIWDATA7 => sci_wrdata(7),
wait;
END PROCESS;
--synopsys translate_on
-end serdes_sync_upstream_arch ;
+end sfp_3sync_200_int_arch ;
--- /dev/null
+--Reset Sequence Generator
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity serdes_rx_reset_sm is
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic;
+ STATE_OUT : out std_logic_vector(3 downto 0)
+);
+end serdes_rx_reset_sm ;
+
+architecture serdes_rx_reset_sm_arch of serdes_rx_reset_sm is
+
+type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
+
+signal cs: statetype; -- current state of lsm
+signal ns: statetype; -- next state of lsm
+
+signal tx_pll_lol_qd_s_int: std_logic;
+signal rx_los_low_int: std_logic;
+signal plol_los_int: std_logic;
+signal rx_lol_los : std_logic;
+signal rx_lol_los_int: std_logic;
+signal rx_lol_los_del: std_logic;
+signal rx_pcs_rst_ch_c_int: std_logic;
+signal rx_serdes_rst_ch_c_int: std_logic;
+
+signal reset_timer1: std_logic;
+signal reset_timer2: std_logic;
+
+signal counter1: std_logic_vector(1 downto 0);
+signal TIMER1: std_logic;
+
+signal counter2: std_logic_vector(18 downto 0);
+signal TIMER2 : std_logic;
+
+begin
+
+rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
+
+process(refclkdiv2,rst_n)
+begin
+ if rising_edge(refclkdiv2) then
+ if rst_n = '0' then
+ cs <= WAIT_FOR_PLOL;
+ rx_lol_los_int <= '1';
+ rx_lol_los_del <= '1';
+ tx_pll_lol_qd_s_int <= '1';
+ rx_pcs_rst_ch_c <= '1';
+ rx_serdes_rst_ch_c <= '0';
+ rx_los_low_int <= '1';
+ else
+ cs <= ns;
+ rx_lol_los_del <= rx_lol_los;
+ rx_lol_los_int <= rx_lol_los_del;
+ tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+ rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
+ rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
+ rx_los_low_int <= rx_los_low_ch_s;
+ end if;
+ end if;
+end process;
+
+--TIMER1 = 3NS;
+--Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
+--A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
+
+process(refclkdiv2, reset_timer1)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer1 = '1' then
+ counter1 <= "00";
+ TIMER1 <= '0';
+ else
+ if counter1(1) = '1' then
+ TIMER1 <='1';
+ else
+ TIMER1 <='0';
+ counter1 <= counter1 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+--TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
+--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+process(refclkdiv2, reset_timer2)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer2 = '1' then
+ counter2 <= "0000000000000000000";
+ TIMER2 <= '0';
+ else
+ if counter2(18) = '1' then
+-- if counter2(4) = '1' then -- for simulation
+ TIMER2 <='1';
+ else
+ TIMER2 <='0';
+ counter2 <= counter2 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
+begin
+ reset_timer1 <= '0';
+ reset_timer2 <= '0';
+
+ case cs is
+ when WAIT_FOR_PLOL =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal
+ ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next
+ else
+ ns <= RX_SERDES_RESET;
+ end if;
+
+ when RX_SERDES_RESET =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ reset_timer1 <= '1';
+ ns <= WAIT_FOR_TIMER1;
+
+ when WAIT_FOR_TIMER1 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ if TIMER1 = '1' then
+ ns <= CHECK_LOL_LOS;
+ else
+ ns <= WAIT_FOR_TIMER1;
+ end if;
+
+ when CHECK_LOL_LOS =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ reset_timer2 <= '1';
+ ns <= WAIT_FOR_TIMER2;
+
+ when WAIT_FOR_TIMER2 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES
+ if TIMER2 = '1' then
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+ else
+ ns <= WAIT_FOR_TIMER2;
+ end if;
+ else
+ ns <= CHECK_LOL_LOS; --RESET TIMER2
+ end if;
+
+ when NORMAL =>
+ rx_pcs_rst_ch_c_int <= '0';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+
+ when others =>
+ ns <= WAIT_FOR_PLOL;
+
+ end case;
+
+end process;
+
+
+
+STATE_OUT <=
+ x"1" when cs=WAIT_FOR_PLOL else
+ x"2" when cs=RX_SERDES_RESET else
+ x"3" when cs=WAIT_FOR_timer1 else
+ x"4" when cs=CHECK_LOL_LOS else
+ x"5" when cs=WAIT_FOR_timer2 else
+ x"6" when cs=NORMAL else
+ x"f";
+
+end serdes_rx_reset_sm_arch;
--- /dev/null
+--TX Reset Sequence state machine--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity serdes_tx_reset_sm is
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rst_qd_c : out std_logic;
+ tx_pcs_rst_ch_c : out std_logic_vector(3 downto 0);
+ STATE_OUT : out std_logic_vector(3 downto 0)
+ );
+end serdes_tx_reset_sm;
+
+architecture serdes_tx_reset_sm_arch of serdes_tx_reset_sm is
+
+type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
+
+signal cs: statetype; -- current state of lsm
+signal ns: statetype; -- next state of lsm
+
+signal tx_pll_lol_qd_s_int : std_logic;
+signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0);
+signal rst_qd_c_int : std_logic;
+
+signal reset_timer1: std_logic;
+signal reset_timer2: std_logic;
+
+signal counter1: std_logic_vector(2 downto 0);
+signal TIMER1: std_logic;
+
+signal counter2: std_logic_vector(18 downto 0);
+signal TIMER2: std_logic;
+
+begin
+
+process (refclkdiv2, rst_n)
+begin
+ if rst_n = '0' then
+ cs <= QUAD_RESET;
+ tx_pll_lol_qd_s_int <= '1';
+ tx_pcs_rst_ch_c <= "1111";
+ rst_qd_c <= '1';
+ else if rising_edge(refclkdiv2) then
+ cs <= ns;
+ tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+ tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int;
+ rst_qd_c <= rst_qd_c_int;
+ end if;
+ end if;
+end process;
+
+
+--TIMER1 = 20ns;
+--Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
+-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
+
+
+process (refclkdiv2, reset_timer1)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer1 = '1' then
+ counter1 <= "000";
+ TIMER1 <= '0';
+ else
+ if counter1(2) = '1' then
+ TIMER1 <= '1';
+ else
+ TIMER1 <='0';
+ counter1 <= counter1 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+--TIMER2 = 1,400,000 UI;
+--WORST CASE CYCLES is with smallest multipier factor.
+-- This would be with X8 clock multiplier in DIV2 mode
+-- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
+-- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
+-- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+
+process(refclkdiv2, reset_timer2)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer2 = '1' then
+ counter2 <= "0000000000000000000";
+ TIMER2 <= '0';
+ else
+ if counter2(18) = '1' then
+-- if counter2(4) = '1' then -- for simulation
+ TIMER2 <='1';
+ else
+ TIMER2 <='0';
+ counter2 <= counter2 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
+begin
+
+ reset_timer1 <= '0';
+ reset_timer2 <= '0';
+
+ case cs is
+
+ when QUAD_RESET =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '1';
+ reset_timer1 <= '1';
+ ns <= WAIT_FOR_TIMER1;
+
+ when WAIT_FOR_TIMER1 =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '1';
+ if TIMER1 = '1' then
+ ns <= CHECK_PLOL;
+ else
+ ns <= WAIT_FOR_TIMER1;
+ end if;
+
+ when CHECK_PLOL =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '0';
+ reset_timer2 <= '1';
+ ns <= WAIT_FOR_TIMER2;
+
+ when WAIT_FOR_TIMER2 =>
+ tx_pcs_rst_ch_c_int <= "1111";
+ rst_qd_c_int <= '0';
+ if TIMER2 = '1' then
+ if tx_pll_lol_qd_s_int = '1' then
+ ns <= QUAD_RESET;
+ else
+ ns <= NORMAL;
+ end if;
+ else
+ ns <= WAIT_FOR_TIMER2;
+ end if;
+
+ when NORMAL =>
+ tx_pcs_rst_ch_c_int <= "0000";
+ rst_qd_c_int <= '0';
+ if tx_pll_lol_qd_s_int = '1' then
+ ns <= QUAD_RESET;
+ else
+ ns <= NORMAL;
+ end if;
+
+ when others =>
+ ns <= QUAD_RESET;
+
+ end case;
+
+end process;
+
+STATE_OUT <=
+ x"1" when cs=QUAD_RESET else
+ x"2" when cs=WAIT_FOR_TIMER1 else
+ x"3" when cs=CHECK_PLOL else
+ x"4" when cs=WAIT_FOR_TIMER2 else
+ x"5" when cs=NORMAL else
+ x"f";
+
+
+end serdes_tx_reset_sm_arch;
--- /dev/null
+--Media interface for Lattice ECP3 using PCS at 2GHz
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+--USE IEEE.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.med_sync_define.all;
+
+
+entity trb_net16_med_sync3_ecp3_sfp is
+ port(
+ CLK : in std_logic; -- SerDes clock
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ REFCLK2CORE_OUT : out std_logic;
+ CLK_RX_HALF_OUT : out std_logic;
+ CLK_RX_FULL_OUT : out std_logic;
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_DLM_IN : in std_logic;
+ SD_DLM_WORD_IN : in std_logic_vector(7 downto 0);
+ SD_DLM_OUT : out std_logic;
+ SD_DLM_WORD_OUT : out std_logic_vector(7 downto 0);
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+end entity;
+
+architecture trb_net16_med_sync3_ecp3_sfp_arch of trb_net16_med_sync3_ecp3_sfp is
+
+
+component sfp_3sync_200_int is
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ sci_sel_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (7 downto 0);
+ tx_k_ch2 : in std_logic;
+ tx_force_disp_ch2 : in std_logic;
+ tx_disp_sel_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ rx_serdes_rst_ch2_c : in std_logic;
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pcs_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pcs_rst_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ tx_div2_mode_ch2_c : in std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+-- CH3 --
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ rst_qd_c : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end component;
+
+
+component serdes_rx_reset_sm is
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic;
+ STATE_OUT : out std_logic_vector(3 downto 0));
+end component ;
+component serdes_tx_reset_sm is
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rst_qd_c : out std_logic;
+ tx_pcs_rst_ch_c : out std_logic_vector(3 downto 0);
+ STATE_OUT : out std_logic_vector(3 downto 0)
+ );
+end component;
+
+component HUB_8to16_SODA is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ char_is_k : in std_logic;
+ fifo_data : out std_logic_vector(17 downto 0);
+ fifo_full : in std_logic;
+ fifo_write : out std_logic;
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ error : out std_logic
+ );
+end component;
+
+component HUB_16to8_SODA is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ fifo_data : in std_logic_vector(15 downto 0);
+ fifo_empty : in std_logic;
+ fifo_read : out std_logic;
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ char_is_k : out std_logic;
+ error : out std_logic
+ );
+end component;
+
+component HUB_SODA_clockcrossing is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ DLM_in : in std_logic;
+ DLM_WORD_in : in std_logic_vector(7 downto 0);
+ DLM_out : out std_logic;
+ DLM_WORD_out : out std_logic_vector(7 downto 0);
+ error : out std_logic
+ );
+end component;
+
+component HUB_posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of trb_net16_med_sync3_ecp3_sfp_arch : architecture is "media_interface_group";
+ attribute syn_sharing : string;
+ attribute syn_sharing of trb_net16_med_sync3_ecp3_sfp_arch : architecture is "off";
+
+ signal ffc_quad_rst : std_logic;
+ --serdes connections
+ signal tx_data : std_logic_vector(7 downto 0);
+ signal tx_k : std_logic;
+ signal rx_data : std_logic_vector(7 downto 0);
+ signal rx_k : std_logic;
+ signal link_ok : std_logic;
+ signal ff_txhalfclk : std_logic;
+ signal ff_txfullclk : std_logic;
+ signal ff_rxhalfclk : std_logic;
+ signal ff_rxfullclk : std_logic;
+ --rx fifo signals
+ signal fifo_rx_rd_en : std_logic;
+ signal fifo_rx_wr_en : std_logic;
+ signal fifo_rx_reset : std_logic;
+ signal fifo_rx_din : std_logic_vector(17 downto 0);
+ signal fifo_rx_dout : std_logic_vector(17 downto 0);
+ signal fifo_rx_full : std_logic;
+ signal fifo_rx_empty : std_logic;
+ --tx fifo signals
+ signal fifo_tx_rd_en : std_logic;
+ signal fifo_tx_wr_en : std_logic;
+ signal fifo_tx_reset : std_logic;
+ signal fifo_tx_din : std_logic_vector(17 downto 0);
+ signal fifo_tx_dout : std_logic_vector(17 downto 0);
+ signal fifo_tx_empty : std_logic;
+ signal fifo_tx_almost_full : std_logic;
+ --rx path
+ signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal buf_med_dataready_out : std_logic;
+ signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal last_rx : std_logic_vector(8 downto 0);
+ signal last_fifo_rx_empty : std_logic;
+ --link status
+
+ signal quad_rst : std_logic;
+ signal lane_rst : std_logic;
+ signal tx_allow : std_logic;
+ signal rx_allow : std_logic;
+
+ signal rx_allow_q : std_logic; -- clock domain changed signal
+ signal tx_allow_q : std_logic;
+ signal buf_stat_debug : std_logic_vector(31 downto 0);
+
+ -- status inputs from SFP
+ signal sfp_prsnt_n : std_logic; -- synchronized input signals
+ signal sfp_los : std_logic; -- synchronized input signals
+
+ signal buf_STAT_OP : std_logic_vector(15 downto 0);
+
+ signal led_counter : unsigned(16 downto 0);
+ signal rx_led : std_logic;
+ signal tx_led : std_logic;
+
+ signal reset_word_cnt : unsigned(4 downto 0);
+ signal make_trbnet_reset : std_logic;
+ signal make_trbnet_reset_q : std_logic;
+ signal send_reset_words : std_logic;
+ signal send_reset_words_q : std_logic;
+ signal send_reset_in : std_logic;
+ signal send_reset_in_qtx : std_logic;
+ signal reset_i : std_logic;
+-- signal reset_i_rx : std_logic;
+ signal pwr_up : std_logic;
+ signal clear_n : std_logic;
+ signal trb_tx_pll_lol_qd_i : std_logic;
+
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+signal sci_state : sci_ctrl;
+ signal sci_ch_i : std_logic_vector(3 downto 0);
+ signal sci_qd_i : std_logic;
+ signal sci_reg_i : std_logic;
+ signal sci_addr_i : std_logic_vector(8 downto 0);
+ signal sci_data_in_i : std_logic_vector(7 downto 0);
+ signal sci_data_out_i : std_logic_vector(7 downto 0);
+ signal sci_read_i : std_logic;
+ signal sci_write_i : std_logic;
+ signal sci_timer : unsigned(12 downto 0) := (others => '0');
+ signal trb_reset_n : std_logic;
+ signal trb_rx_serdes_rst : std_logic;
+ signal trb_rx_cdr_lol : std_logic;
+ signal trb_rx_los_low : std_logic;
+ signal trb_rx_pcs_rst : std_logic;
+ signal trb_tx_pcs_rst : std_logic;
+ signal trb_tx_pcs_rst_all : std_logic_vector(3 downto 0);
+ signal rst_qd : std_logic;
+ signal trb_rx_fsm_state : std_logic_vector(3 downto 0);
+ signal trb_tx_fsm_state : std_logic_vector(3 downto 0);
+
+ signal trb_rx_los_low_q : std_logic;
+ signal trb_rx_cdr_lol_q : std_logic;
+ signal trb_tx_pll_lol_qd_q : std_logic;
+ signal trb_rx_cv_err_ch2 : std_logic;
+ signal trb_rx_cv_err_ch2_q : std_logic;
+
+ signal link_tx_ok : std_logic;
+ signal link_rx_ok : std_logic;
+ signal link_tx_ok_q : std_logic;
+ signal link_rx_ok_q : std_logic;
+
+ signal wa_position_sync1 : std_logic_vector(3 downto 0);
+ signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
+
+ signal SD_DLM_IN_S : std_logic;
+ signal SD_DLM_WORD_IN_S : std_logic_vector(7 downto 0);
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+ attribute syn_keep of led_counter : signal is true;
+ attribute syn_keep of send_reset_in : signal is true;
+ attribute syn_keep of reset_i : signal is true;
+ attribute syn_preserve of reset_i : signal is true;
+
+begin
+
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+ clear_n <= not clear;
+
+
+PROC_RESET : process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ reset_i <= RESET;
+ send_reset_in <= ctrl_op(15);
+ pwr_up <= '1'; --not CTRL_OP(i*16+14);
+ end if;
+end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+ generic map(
+ DEPTH => 3,
+ WIDTH => 2
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => sd_prsnt_n_in,
+ D_IN(1) => sd_los_in,
+ CLK0 => SYSCLK,
+ CLK1 => SYSCLK,
+ D_OUT(0) => sfp_prsnt_n,
+ D_OUT(1) => sfp_los
+ );
+
+
+THE_RX_K_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 1
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => send_reset_words,
+ CLK0 => ff_rxfullclk,
+ CLK1 => SYSCLK,
+ D_OUT(0) => send_reset_words_q
+ );
+
+THE_RESET_SYNC: HUB_posedge_to_pulse
+ port map(
+ clock_in => ff_rxfullclk,
+ clock_out => SYSCLK,
+ en_clk => '1',
+ signal_in => make_trbnet_reset,
+ pulse => make_trbnet_reset_q
+ );
+
+process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ if (tx_allow='1') and (link_tx_ok_q='1') then
+ tx_allow_q <= '1';
+ else
+ tx_allow_q <= '0';
+ end if;
+ if (rx_allow='1') and (link_rx_ok_q='1') then
+ rx_allow_q <= '1';
+ else
+ rx_allow_q <= '0';
+ end if;
+ link_tx_ok_q <= link_tx_ok;
+ link_rx_ok_q <= link_rx_ok;
+ end if;
+end process;
+-- synchronize link_OK
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if trb_tx_fsm_state=x"5" then
+ link_tx_ok <= '1';
+ else
+ link_tx_ok <= '0';
+ end if;
+ if (trb_rx_fsm_state=x"6") then
+ link_rx_ok <= '1';
+ else
+ link_rx_ok <= '0';
+ end if;
+ end if;
+end process;
+
+THE_TX_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 1
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => send_reset_in,
+ CLK0 => ff_txfullclk,
+ CLK1 => ff_txfullclk,
+ D_OUT(0) => send_reset_in_qtx
+ );
+
+THE_ERROR_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 4
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => trb_rx_los_low,
+ D_IN(1) => trb_rx_cdr_lol,
+ D_IN(2) => trb_tx_pll_lol_qd_i,
+ D_IN(3) => trb_rx_cv_err_ch2,
+ CLK0 => SYSCLK,
+ CLK1 => SYSCLK,
+ D_OUT(0) => trb_rx_los_low_q,
+ D_OUT(1) => trb_rx_cdr_lol_q,
+ D_OUT(2) => trb_tx_pll_lol_qd_q,
+ D_OUT(3) => trb_rx_cv_err_ch2_q
+ );
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+ generic map (
+ CHECK_FOR_CV => c_YES,
+ HIGHSPEED_STARTUP => c_YES
+ )
+ port map(
+ SYSCLK => SYSCLK,
+ RESET => reset_i,
+ CLEAR => clear,
+ SFP_MISSING_IN => sfp_prsnt_n,
+ SFP_LOS_IN => sfp_los,
+ SD_LINK_OK_IN => link_ok, -- apparently not used
+ SD_LOS_IN => trb_rx_los_low_q, -- apparently not used
+ SD_TXCLK_BAD_IN => trb_tx_pll_lol_qd_q,
+ SD_RXCLK_BAD_IN => trb_rx_cdr_lol_q,
+ SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+ SD_ALIGNMENT_IN => "01", -- should always be correct
+ SD_CV_IN(0) => trb_rx_cv_err_ch2_q,
+ SD_CV_IN(1) => trb_rx_cv_err_ch2_q,
+ FULL_RESET_OUT => quad_rst,
+ LANE_RESET_OUT => lane_rst, -- apparently not used
+ TX_ALLOW_OUT => tx_allow,
+ RX_ALLOW_OUT => rx_allow,
+ SWAP_BYTES_OUT => open,
+ STAT_OP => buf_stat_op,
+ CTRL_OP => ctrl_op,
+ STAT_DEBUG => buf_stat_debug
+ );
+sd_txdis_out <= quad_rst or reset_i;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+-- SerDes clock output to FPGA fabric
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
+
+THE_SERDES: sfp_3sync_200_int
+ port map(
+ hdinp_ch2 => sd_rxd_p_in,
+ hdinn_ch2 => sd_rxd_n_in,
+ hdoutp_ch2 => sd_txd_p_out,
+ hdoutn_ch2 => sd_txd_n_out,
+ sci_sel_ch2 => sci_ch_i(2),
+ rxiclk_ch2 => ff_rxfullclk,
+ txiclk_ch2 => ff_txfullclk,
+ rx_full_clk_ch2 => ff_rxfullclk,
+ rx_half_clk_ch2 => ff_rxhalfclk,
+ tx_full_clk_ch2 => ff_txfullclk,
+ tx_half_clk_ch2 => ff_txhalfclk,
+ fpga_rxrefclk_ch2 => CLK,
+ txdata_ch2 => tx_data,
+ tx_k_ch2 => tx_k,
+ tx_force_disp_ch2 => '0',
+ tx_disp_sel_ch2 => '0',
+ rxdata_ch2 => rx_data,
+ rx_k_ch2 => rx_k,
+ rx_disp_err_ch2 => open,
+ rx_cv_err_ch2 => trb_rx_cv_err_ch2,
+ rx_serdes_rst_ch2_c => trb_rx_serdes_rst,
+ sb_felb_ch2_c => '0',
+ sb_felb_rst_ch2_c => '0',
+ tx_pcs_rst_ch2_c => trb_tx_pcs_rst,
+ tx_pwrup_ch2_c => '1',
+ rx_pcs_rst_ch2_c => trb_rx_pcs_rst,
+ rx_pwrup_ch2_c => '1',
+ rx_los_low_ch2_s => trb_rx_los_low,
+ lsm_status_ch2_s => link_ok,
+ rx_cdr_lol_ch2_s => trb_rx_cdr_lol,
+ tx_div2_mode_ch2_c => '0',
+ rx_div2_mode_ch2_c => '0',
+ ---- Miscillaneous ports
+ sci_wrdata => sci_data_in_i,
+ sci_addr => sci_addr_i(5 downto 0),
+ sci_rddata => sci_data_out_i,
+ sci_sel_quad => sci_qd_i,
+ sci_rd => sci_read_i,
+ sci_wrn => sci_write_i,
+ fpga_txrefclk => CLK,
+ tx_serdes_rst_c => CLEAR,
+ tx_pll_lol_qd_s => trb_tx_pll_lol_qd_i,
+ rst_qd_c => '0',
+ serdes_rst_qd_c => ffc_quad_rst
+ );
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO)
+ port map(
+ read_clock_in => SYSCLK,
+ write_clock_in => ff_rxfullclk,
+ read_enable_in => fifo_rx_rd_en,
+ write_enable_in => fifo_rx_wr_en,
+ fifo_gsr_in => fifo_rx_reset,
+ write_data_in => fifo_rx_din,
+ read_data_out => fifo_rx_dout,
+ full_out => fifo_rx_full,
+ empty_out => fifo_rx_empty
+ );
+fifo_rx_reset <= '1' when (reset_i='1') or (rx_allow_q='0') else '0';
+fifo_rx_rd_en <= not fifo_rx_empty;
+HUB_8to16_SODA1: HUB_8to16_SODA
+ port map(
+ clock => ff_rxfullclk,
+ reset => fifo_rx_reset,
+ data_in => rx_data,
+ char_is_k => rx_k,
+ fifo_data => fifo_rx_din,
+ fifo_full => fifo_rx_full,
+ fifo_write => fifo_rx_wr_en,
+ RX_DLM => SD_DLM_OUT,
+ RX_DLM_WORD => SD_DLM_WORD_OUT,
+ error => open
+ );
+
+buf_med_data_out <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out <= rx_counter;
+med_read_out <= tx_allow_q and not fifo_tx_almost_full;
+
+THE_SYNC_PROC: process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ med_dataready_out <= buf_med_dataready_out;
+ med_data_out <= buf_med_data_out;
+ med_packet_num_out <= buf_med_packet_num_out;
+ if reset_i = '1' then
+ med_dataready_out <= '0';
+ end if;
+ end if;
+end process;
+
+THE_CNT_RESET_PROC : process(ff_rxfullclk,reset_i)
+ begin
+ if reset_i='1' then
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ reset_word_cnt <= (others => '0');
+ elsif rising_edge(ff_rxfullclk) then
+ send_reset_words <= '0';
+ make_trbnet_reset <= '0';
+ if (rx_k='1') and (rx_data=x"FE") then
+ if reset_word_cnt(4) = '0' then
+ reset_word_cnt <= reset_word_cnt + 1;
+ else
+ send_reset_words <= '1';
+ end if;
+ else
+ reset_word_cnt <= (others => '0');
+ make_trbnet_reset <= reset_word_cnt(4);
+ end if;
+ end if;
+ end process;
+
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process(SYSCLK)
+begin
+ if( rising_edge(SYSCLK) ) then
+ last_fifo_rx_empty <= fifo_rx_empty;
+ if reset_i = '1' or rx_allow_q = '0' then
+ rx_counter <= c_H0;
+ else
+ if( buf_med_dataready_out = '1' ) then
+ if( rx_counter = c_max_word_number ) then
+ rx_counter <= (others => '0');
+ else
+ rx_counter <= rx_counter + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+ port map(
+ read_clock_in => ff_txfullclk,
+ write_clock_in => SYSCLK,
+ read_enable_in => fifo_tx_rd_en,
+ write_enable_in => fifo_tx_wr_en,
+ fifo_gsr_in => fifo_tx_reset,
+ write_data_in => fifo_tx_din,
+ read_data_out => fifo_tx_dout,
+ full_out => open,
+ empty_out => fifo_tx_empty,
+ almost_full_out => fifo_tx_almost_full
+ );
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+
+HUB_16to8_SODA1: HUB_16to8_SODA
+ port map(
+ clock => ff_txfullclk,
+ reset => send_reset_in_qtx,
+ fifo_data => fifo_tx_dout(15 downto 0),
+ fifo_empty => fifo_tx_empty,
+ fifo_read => fifo_tx_rd_en,
+ TX_DLM => SD_DLM_IN_S,
+ TX_DLM_WORD => SD_DLM_WORD_IN_S,
+ data_out => tx_data,
+ char_is_k => tx_k,
+ error => open
+ );
+
+HUB_SODA_clockcrossing1: HUB_SODA_clockcrossing
+ port map(
+ write_clock => ff_rxfullclk,
+ read_clock => ff_txfullclk,
+ DLM_in => SD_DLM_IN,
+ DLM_WORD_in => SD_DLM_WORD_IN,
+ DLM_out => SD_DLM_IN_S,
+ DLM_WORD_out => SD_DLM_WORD_IN_S,
+ error => open
+ );
+
+
+
+trb_reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';
+ffc_quad_rst <= quad_rst;
+
+-------------------------------------------------
+-- Reset FSM & Link states
+-------------------------------------------------
+THE_RX_FSM1: rx_reset_fsm -- reset FSM for receiver channel 2 (SODA), synchronize to fiber bit with wa_position
+ port map(
+ RST_N => trb_reset_n,
+ RX_REFCLK => CLK, --//ff_rxfullclk, --??CLK,
+ TX_PLL_LOL_QD_S => trb_tx_pll_lol_qd_i,
+ RX_SERDES_RST_CH_C => trb_rx_serdes_rst,
+ RX_CDR_LOL_CH_S => trb_rx_cdr_lol,
+ RX_LOS_LOW_CH_S => trb_rx_los_low,
+ RX_PCS_RST_CH_C => trb_rx_pcs_rst,
+ WA_POSITION => wa_position_sync1,
+ STATE_OUT => trb_rx_fsm_state
+ );
+SYNC_WA_POSITION: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 4)
+ port map(
+ RESET => '0',
+ D_IN(3 downto 0) => wa_position(11 downto 8),
+ CLK0 => CLK, --// SYSCLK,
+ CLK1 => CLK, --//ff_rxfullclk,
+ D_OUT(3 downto 0) => wa_position_sync1
+ );
+
+
+THE_TX_FSM1: serdes_tx_reset_sm -- original from Lattice
+ port map(
+ RST_N => trb_reset_n,
+ refclkdiv2 => CLK, --//??SYSCLK,
+ TX_PLL_LOL_QD_S => trb_tx_pll_lol_qd_i,
+ RST_QD_C => rst_qd,
+ TX_PCS_RST_CH_C => trb_tx_pcs_rst_all,
+ STATE_OUT => trb_tx_fsm_state
+ );
+trb_tx_pcs_rst <= trb_tx_pcs_rst_all(1);
+
+
+-------------------------------------------------
+-- SCI
+-------------------------------------------------
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us
+PROC_SCI_CTRL: process(SYSCLK)
+variable cnt : integer range 0 to 4 := 0;
+begin
+ if( rising_edge(SYSCLK) ) then
+ SCI_ACK <= '0';
+ case sci_state is
+ when IDLE =>
+ sci_ch_i <= x"0";
+ sci_qd_i <= '0';
+ sci_reg_i <= '0';
+ sci_read_i <= '0';
+ sci_write_i <= '0';
+ sci_timer <= sci_timer + 1;
+ if SCI_READ = '1' or SCI_WRITE = '1' then
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
+ sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
+ sci_addr_i <= SCI_ADDR;
+ sci_data_in_i <= SCI_DATA_IN;
+ sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
+ sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
+ sci_state <= SCTRL;
+ elsif sci_timer(sci_timer'left) = '1' then
+ sci_timer <= (others => '0');
+ sci_state <= GET_WA;
+ end if;
+ when SCTRL =>
+ if sci_reg_i = '1' then
+ --// SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
+ SCI_DATA_OUT <= (others => '0');
+ SCI_ACK <= '1';
+ sci_write_i <= '0';
+ sci_read_i <= '0';
+ sci_state <= IDLE;
+ else
+ sci_state <= SCTRL_WAIT;
+ end if;
+ when SCTRL_WAIT =>
+ sci_state <= SCTRL_WAIT2;
+ when SCTRL_WAIT2 =>
+ sci_state <= SCTRL_FINISH;
+ when SCTRL_FINISH =>
+ SCI_DATA_OUT <= sci_data_out_i;
+ SCI_ACK <= '1';
+ sci_write_i <= '0';
+ sci_read_i <= '0';
+ sci_state <= IDLE;
+
+ when GET_WA =>
+ if cnt = 4 then
+ cnt := 0;
+ sci_state <= IDLE;
+ else
+ sci_state <= GET_WA_WAIT;
+ sci_addr_i <= '0' & x"22";
+ sci_ch_i <= x"0";
+ sci_ch_i(cnt) <= '1';
+ sci_read_i <= '1';
+ end if;
+ when GET_WA_WAIT =>
+ sci_state <= GET_WA_WAIT2;
+ when GET_WA_WAIT2 =>
+ sci_state <= GET_WA_FINISH;
+ when GET_WA_FINISH =>
+ wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
+ sci_state <= GET_WA;
+ cnt := cnt + 1;
+ end case;
+
+ if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
+ SCI_NACK <= '1';
+ else
+ SCI_NACK <= '0';
+ end if;
+ end if;
+end process;
+
+
+
+--Generate LED signals
+----------------------
+process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ led_counter <= led_counter + 1;
+ if buf_med_dataready_out = '1' then
+ rx_led <= '1';
+ elsif led_counter = 0 then
+ rx_led <= '0';
+ end if;
+ if tx_k = '0' then
+ tx_led <= '1';
+ elsif led_counter = 0 then
+ tx_led <= '0';
+ end if;
+ end if;
+end process;
+
+stat_op(15) <= send_reset_words_q;
+stat_op(14) <= buf_stat_op(14);
+stat_op(13) <= make_trbnet_reset_q;
+stat_op(12) <= '0';
+stat_op(11) <= tx_led; --tx led
+stat_op(10) <= rx_led; --rx led
+stat_op(9 downto 0) <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(7 downto 0) <= rx_data;
+stat_debug(16) <= rx_k;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24) <= fifo_rx_rd_en;
+stat_debug(25) <= fifo_rx_wr_en;
+stat_debug(26) <= fifo_rx_reset;
+stat_debug(27) <= fifo_rx_empty;
+stat_debug(28) <= fifo_rx_full;
+stat_debug(29) <= last_rx(8);
+stat_debug(30) <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42) <= SYSCLK;
+stat_debug(43) <= SYSCLK;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+
+end architecture;
+
--- /dev/null
+--Media interface for Lattice ECP3 using PCS at 2GHz, RX clock == TX clock
+--For fully synchronized FPGAs only!
+--Either 200 MHz input for 2GBit or 125 MHz for 2.5GBit.
+--system clock can be 100 MHz or 125 MHz
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+--use ieee.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.med_sync_define.all;
+
+
+entity trb_net16_med_syncfull_ecp3_sfp is
+ port(
+ CLK : in std_logic; -- SerDes clock
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
+ MED_READ_OUT : out std_logic_vector(3 downto 0);
+ MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);
+ MED_READ_IN : in std_logic_vector(3 downto 0);
+ REFCLK2CORE_OUT : out std_logic;
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic_vector(3 downto 0);
+ SD_RXD_N_IN : in std_logic_vector(3 downto 0);
+ SD_TXD_P_OUT : out std_logic_vector(3 downto 0);
+ SD_TXD_N_OUT : out std_logic_vector(3 downto 0);
+ SD_REFCLK_P_IN : in std_logic;
+ SD_REFCLK_N_IN : in std_logic;
+ SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable
+ --Synchronous signals
+ RX_DLM : out std_logic_vector(3 downto 0);
+ RX_DLM_WORD : out std_logic_vector(4*8-1 downto 0);
+ TX_DLM : in std_logic_vector(3 downto 0);
+ TX_DLM_WORD : in std_logic_vector(4*8-1 downto 0);
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out std_logic_vector (4*16-1 downto 0);
+ CTRL_OP : in std_logic_vector (4*16-1 downto 0);
+ STAT_DEBUG : out std_logic_vector (64*4-1 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+end entity;
+
+architecture arch_ecp3_sfp_4 of trb_net16_med_syncfull_ecp3_sfp is
+
+component serdes_sync_200_full is
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;
+ sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ txiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ tx_full_clk_ch0 : out std_logic;
+ tx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ txdata_ch0 : in std_logic_vector (7 downto 0);
+ tx_k_ch0 : in std_logic;
+ tx_force_disp_ch0 : in std_logic;
+ tx_disp_sel_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ rx_serdes_rst_ch0_c : in std_logic;
+ sb_felb_ch0_c : in std_logic;
+ sb_felb_rst_ch0_c : in std_logic;
+ tx_pcs_rst_ch0_c : in std_logic;
+ tx_pwrup_ch0_c : in std_logic;
+ rx_pcs_rst_ch0_c : in std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ tx_div2_mode_ch0_c : in std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;
+ sci_sel_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ txiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ tx_full_clk_ch1 : out std_logic;
+ tx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ txdata_ch1 : in std_logic_vector (7 downto 0);
+ tx_k_ch1 : in std_logic;
+ tx_force_disp_ch1 : in std_logic;
+ tx_disp_sel_ch1 : in std_logic;
+ rxdata_ch1 : out std_logic_vector (7 downto 0);
+ rx_k_ch1 : out std_logic;
+ rx_disp_err_ch1 : out std_logic;
+ rx_cv_err_ch1 : out std_logic;
+ rx_serdes_rst_ch1_c : in std_logic;
+ sb_felb_ch1_c : in std_logic;
+ sb_felb_rst_ch1_c : in std_logic;
+ tx_pcs_rst_ch1_c : in std_logic;
+ tx_pwrup_ch1_c : in std_logic;
+ rx_pcs_rst_ch1_c : in std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ tx_div2_mode_ch1_c : in std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ hdoutp_ch2, hdoutn_ch2 : out std_logic;
+ sci_sel_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ txiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ tx_full_clk_ch2 : out std_logic;
+ tx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ txdata_ch2 : in std_logic_vector (7 downto 0);
+ tx_k_ch2 : in std_logic;
+ tx_force_disp_ch2 : in std_logic;
+ tx_disp_sel_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ rx_serdes_rst_ch2_c : in std_logic;
+ sb_felb_ch2_c : in std_logic;
+ sb_felb_rst_ch2_c : in std_logic;
+ tx_pcs_rst_ch2_c : in std_logic;
+ tx_pwrup_ch2_c : in std_logic;
+ rx_pcs_rst_ch2_c : in std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ tx_div2_mode_ch2_c : in std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;
+ sci_sel_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ txiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ tx_full_clk_ch3 : out std_logic;
+ tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ txdata_ch3 : in std_logic_vector (7 downto 0);
+ tx_k_ch3 : in std_logic;
+ tx_force_disp_ch3 : in std_logic;
+ tx_disp_sel_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ rx_serdes_rst_ch3_c : in std_logic;
+ sb_felb_ch3_c : in std_logic;
+ sb_felb_rst_ch3_c : in std_logic;
+ tx_pcs_rst_ch3_c : in std_logic;
+ tx_pwrup_ch3_c : in std_logic;
+ rx_pcs_rst_ch3_c : in std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ tx_div2_mode_ch3_c : in std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ sci_wrdata : in std_logic_vector (7 downto 0);
+ sci_addr : in std_logic_vector (5 downto 0);
+ sci_rddata : out std_logic_vector (7 downto 0);
+ sci_sel_quad : in std_logic;
+ sci_rd : in std_logic;
+ sci_wrn : in std_logic;
+ fpga_txrefclk : in std_logic;
+ tx_serdes_rst_c : in std_logic;
+ tx_pll_lol_qd_s : out std_logic;
+ tx_sync_qd_c : in std_logic;
+ rst_qd_c : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+end component;
+
+component HUB_8to16_SODA is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ char_is_k : in std_logic;
+ fifo_data : out std_logic_vector(17 downto 0);
+ fifo_full : in std_logic;
+ fifo_write : out std_logic;
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ error : out std_logic
+ );
+end component;
+
+component HUB_16to8_SODA is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ fifo_data : in std_logic_vector(15 downto 0);
+ fifo_empty : in std_logic;
+ fifo_read : out std_logic;
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ char_is_k : out std_logic;
+ error : out std_logic
+ );
+end component;
+
+component HUB_SODA_clockcrossing is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ DLM_in : in std_logic;
+ DLM_WORD_in : in std_logic_vector(7 downto 0);
+ DLM_out : out std_logic;
+ DLM_WORD_out : out std_logic_vector(7 downto 0);
+ error : out std_logic
+ );
+end component;
+
+component HUB_posedge_to_pulse is
+ port (
+ clock_in : in std_logic;
+ clock_out : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic
+ );
+end component;
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of arch_ecp3_sfp_4 : architecture is "media_interface_group";
+ attribute syn_sharing : string;
+ attribute syn_sharing of arch_ecp3_sfp_4 : architecture is "off";
+ type array4x8_type is array(3 downto 0) of std_logic_vector(7 downto 0);
+ type array_4x4_type is array(3 downto 0) of std_logic_vector(3 downto 0);
+
+
+ signal refck2core : std_logic;
+ --reset signals
+ signal ffc_quad_rst : std_logic;
+ --serdes connections
+ signal tx_data : array4x8_type;
+ signal tx_k : std_logic_vector(4*1-1 downto 0);
+ signal rx_data : array4x8_type;
+ signal rx_k : std_logic_vector(4*1-1 downto 0);
+ signal link_ok : std_logic_vector(4*1-1 downto 0);
+ signal link_ok_q : std_logic_vector(4*1-1 downto 0);
+ --rx fifo signals
+ signal fifo_rx_rd_en : std_logic_vector(4*1-1 downto 0);
+ signal fifo_rx_wr_en : std_logic_vector(4*1-1 downto 0);
+ signal fifo_rx_reset : std_logic_vector(4*1-1 downto 0);
+ signal fifo_rx_din : std_logic_vector(4*18-1 downto 0);
+ signal fifo_rx_dout : std_logic_vector(4*18-1 downto 0);
+ signal fifo_rx_full : std_logic_vector(4*1-1 downto 0);
+ signal fifo_rx_empty : std_logic_vector(4*1-1 downto 0);
+ --tx fifo signals
+ signal fifo_tx_rd_en : std_logic_vector(4*1-1 downto 0);
+ signal fifo_tx_wr_en : std_logic_vector(4*1-1 downto 0);
+ signal fifo_tx_reset : std_logic_vector(4*1-1 downto 0);
+ signal fifo_tx_din : std_logic_vector(4*18-1 downto 0);
+ signal fifo_tx_dout : std_logic_vector(4*18-1 downto 0);
+ signal fifo_tx_full : std_logic_vector(4*1-1 downto 0);
+ signal fifo_tx_empty : std_logic_vector(4*1-1 downto 0);
+ signal fifo_tx_almost_full : std_logic_vector(4*1-1 downto 0);
+ --rx path
+ signal rx_counter : std_logic_vector(4*3-1 downto 0);
+ signal buf_med_dataready_out : std_logic_vector(4*1-1 downto 0);
+ signal buf_med_data_out : std_logic_vector(4*16-1 downto 0);
+ signal buf_med_packet_num_out : std_logic_vector(4*3-1 downto 0);
+ signal last_fifo_rx_empty : std_logic_vector(4*1-1 downto 0);
+ --tx path
+ signal last_fifo_tx_empty : std_logic_vector(4*1-1 downto 0);
+ --link status
+ signal fifo_rx_full_q : std_logic_vector(4*1-1 downto 0);
+
+ signal rx_rst_n : std_logic;
+ signal tx_rst_n : std_logic;
+
+ signal quad_rst : std_logic_vector(4*1-1 downto 0);
+ signal lane_rst : std_logic_vector(4*1-1 downto 0);
+ signal tx_allow : std_logic_vector(4*1-1 downto 0);
+ signal rx_allow : std_logic_vector(4*1-1 downto 0);
+ signal link_tx_ok : std_logic_vector(4*1-1 downto 0);
+ signal link_rx_ok : std_logic_vector(4*1-1 downto 0);
+ signal link_tx_ok_q : std_logic_vector(4*1-1 downto 0);
+ signal link_rx_ok_q : std_logic_vector(4*1-1 downto 0);
+ signal rx_fsm_state : array_4x4_type;
+ signal tx_fsm_state : array_4x4_type;
+
+ signal rx_allow_q : std_logic_vector(4*1-1 downto 0); -- clock domain changed signal
+ signal tx_allow_q : std_logic_vector(4*1-1 downto 0);
+ signal buf_stat_debug : std_logic_vector(4*32-1 downto 0);
+
+ -- status inputs from SFP
+ signal sfp_prsnt_n : std_logic_vector(4*1-1 downto 0);
+ signal sfp_los : std_logic_vector(4*1-1 downto 0);
+
+ signal buf_STAT_OP : std_logic_vector(4*16-1 downto 0);
+
+ signal led_counter : unsigned(16 downto 0);
+ signal rx_led : std_logic_vector(4*1-1 downto 0);
+ signal tx_led : std_logic_vector(4*1-1 downto 0);
+
+ type arr5_t is array (0 to 3) of unsigned(4 downto 0);
+ signal reset_word_cnt : arr5_t;
+ signal make_trbnet_reset : std_logic_vector(4*1-1 downto 0);
+ signal make_trbnet_reset_q : std_logic_vector(4*1-1 downto 0);
+ signal send_reset_words : std_logic_vector(4*1-1 downto 0);
+ signal send_reset_words_q : std_logic_vector(4*1-1 downto 0);
+ signal send_reset_in : std_logic_vector(4*1-1 downto 0);
+ signal reset_i : std_logic;
+ signal reset_i_rx : std_logic_vector(4*1-1 downto 0);
+ signal pwr_up : std_logic_vector(4*1-1 downto 0);
+ signal rx_serdes_rst : std_logic_vector(4*1-1 downto 0);
+ signal tx_pcs_rst : std_logic_vector(4*1-1 downto 0);
+ signal rx_pcs_rst : std_logic_vector(4*1-1 downto 0);
+ signal rst_qd : std_logic;
+ signal rst_qd_S : std_logic_vector(3 downto 0);
+ signal rx_los_low : std_logic_vector(3 downto 0);
+ signal rx_los_low_q : std_logic_vector(3 downto 0);
+ signal rx_cdr_lol : std_logic_vector(3 downto 0);
+ signal rx_cdr_lol_q : std_logic_vector(3 downto 0);
+ signal rx_cv_err : std_logic_vector(3 downto 0);
+ signal rx_cv_err_q : std_logic_vector(3 downto 0);
+ signal tx_pll_lol : std_logic;
+ signal tx_pll_lol_q : std_logic;
+
+ signal tx_sync_qd_c : std_logic;
+ signal tx_sync_qd_c_S : std_logic;
+
+ signal rx_fullclk_i : std_logic_vector(3 downto 0);
+ signal tx_fullclk_i : std_logic_vector(3 downto 0);
+
+ signal sci_ch_i : std_logic_vector(3 downto 0);
+ signal sci_addr_i : std_logic_vector(8 downto 0);
+ signal sci_data_in_i : std_logic_vector(7 downto 0);
+ signal sci_data_out_i : std_logic_vector(7 downto 0);
+ signal sci_read_i : std_logic;
+ signal sci_write_i : std_logic;
+ signal sci_write_shift_i : std_logic_vector(2 downto 0);
+ signal sci_read_shift_i : std_logic_vector(2 downto 0);
+
+ signal RX_DLM_S : std_logic_vector(3 downto 0);
+ signal RX_DLM_WORD_S : std_logic_vector(8*4-1 downto 0);
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+ attribute syn_keep of led_counter : signal is true;
+ attribute syn_keep of send_reset_in : signal is true;
+ attribute syn_keep of reset_i : signal is true;
+ attribute syn_preserve of reset_i : signal is true;
+ attribute syn_keep of SCI_DATA_OUT : signal is true;
+ attribute syn_preserve of SCI_DATA_OUT : signal is true;
+
+begin
+
+--------------------------------------------------------------------------
+-- Internal Resets
+--------------------------------------------------------------------------
+PROC_RESET : process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ reset_i <= RESET;
+ pwr_up <= x"F"; --not CTRL_OP(i*16+14);
+ end if;
+end process;
+
+THE_SENDRESET_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 4
+ )
+ port map(
+ RESET => '0',
+ D_IN(0) => ctrl_op(15),
+ D_IN(1) => ctrl_op(15+16),
+ D_IN(2) => ctrl_op(15+32),
+ D_IN(3) => ctrl_op(15+48),
+ CLK0 => SYSCLK,
+ CLK1 => CLK,
+ D_OUT(0) => send_reset_in(0),
+ D_OUT(1) => send_reset_in(1),
+ D_OUT(2) => send_reset_in(2),
+ D_OUT(3) => send_reset_in(3)
+ );
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFPSIGNALS_SYNC: signal_sync
+ generic map(
+ DEPTH => 1,
+ WIDTH => 29
+ )
+ port map(
+ RESET => '0',
+ D_IN(3 downto 0) => SD_PRSNT_N_IN,
+ D_IN(7 downto 4) => SD_LOS_IN,
+ D_IN(11 downto 8) => send_reset_words,
+ D_IN(15 downto 12) => link_ok,
+ D_IN(19 downto 16) => rx_los_low,
+ D_IN(23 downto 20) => rx_cdr_lol,
+ D_IN(27 downto 24) => rx_cv_err,
+ D_IN(28) => tx_pll_lol,
+ CLK0 => SYSCLK,
+ CLK1 => SYSCLK,
+ D_OUT(3 downto 0) => sfp_prsnt_n,
+ D_OUT(7 downto 4) => sfp_los,
+ D_OUT(11 downto 8)=> send_reset_words_q,
+ D_OUT(15 downto 12) => link_ok_q,
+ D_OUT(19 downto 16) => rx_los_low_q,
+ D_OUT(23 downto 20) => rx_cdr_lol_q,
+ D_OUT(27 downto 24) => rx_cv_err_q,
+ D_OUT(28) => tx_pll_lol_q
+ );
+
+
+process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ for i in 0 to 3 loop
+ if (tx_allow(i)='1') and (link_tx_ok_q(i)='1') then
+ tx_allow_q(i) <= '1';
+ else
+ tx_allow_q(i) <= '0';
+ end if;
+ if (rx_allow(i)='1') and (link_rx_ok_q(i)='1') then
+ rx_allow_q(i) <= '1';
+ else
+ rx_allow_q(i) <= '0';
+ end if;
+ end loop;
+ link_tx_ok_q <= link_tx_ok;
+ link_rx_ok_q <= link_rx_ok;
+ end if;
+end process;
+
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ for i in 0 to 3 loop
+ if tx_fsm_state(i)=x"5" then
+ link_tx_ok(i) <= '1';
+ else
+ link_tx_ok(i) <= '0';
+ end if;
+ if (rx_fsm_state(i)=x"6") then
+ link_rx_ok(i) <= '1';
+ else
+ link_rx_ok(i) <= '0';
+ end if;
+ end loop;
+ fifo_rx_full_q <= fifo_rx_full;
+ end if;
+end process;
+
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+gen_LSM : for i in 0 to 3 generate
+ THE_SFP_LSM: trb_net16_lsm_sfp
+ generic map (
+ HIGHSPEED_STARTUP => c_YES
+ )
+ port map(
+ SYSCLK => SYSCLK,
+ RESET => reset_i,
+ CLEAR => clear,
+ SFP_MISSING_IN => sfp_prsnt_n(i),
+ SFP_LOS_IN => sfp_los(i),
+ SD_LINK_OK_IN => link_ok_q(i),
+ SD_LOS_IN => rx_los_low_q(i),
+ SD_TXCLK_BAD_IN => tx_pll_lol_q,
+ SD_RXCLK_BAD_IN => rx_cdr_lol_q(i),
+ SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+ SD_ALIGNMENT_IN => "01", -- no swapping
+ SD_CV_IN(0) => rx_cv_err_q(i),
+ SD_CV_IN(1) => rx_cv_err_q(i),
+ FULL_RESET_OUT => quad_rst(i),
+ LANE_RESET_OUT => lane_rst(i),
+ TX_ALLOW_OUT => tx_allow(i),
+ RX_ALLOW_OUT => rx_allow(i),
+ SWAP_BYTES_OUT => open,
+ STAT_OP => buf_stat_op(i*16+15 downto i*16),
+ CTRL_OP => ctrl_op(i*16+15 downto i*16),
+ STAT_DEBUG => buf_stat_debug(i*32+31 downto i*32)
+ );
+
+ sd_txdis_out(i) <= quad_rst(i) or reset_i;
+ ffc_quad_rst <= quad_rst(0);
+
+end generate;
+
+
+PROC_SCI : process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ if SCI_READ = '1' or SCI_WRITE = '1' then
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
+ sci_addr_i <= SCI_ADDR;
+ sci_data_in_i <= SCI_DATA_IN;
+ end if;
+ sci_read_shift_i <= sci_read_shift_i(1 downto 0) & SCI_READ;
+ sci_write_shift_i <= sci_write_shift_i(1 downto 0) & SCI_WRITE;
+ SCI_DATA_OUT <= sci_data_out_i;
+ end if;
+end process;
+
+sci_write_i <= or_all(sci_write_shift_i);
+sci_read_i <= or_all(sci_read_shift_i);
+SCI_ACK <= sci_write_shift_i(2) or sci_read_shift_i(2);
+
+THE_SERDES: serdes_sync_200_full
+ port map(
+-- CH0 --
+ HDINP_CH0 => sd_rxd_p_in(0),
+ HDINN_CH0 => sd_rxd_n_in(0),
+ HDOUTP_CH0 => sd_txd_p_out(0),
+ HDOUTN_CH0 => sd_txd_n_out(0),
+ SCI_SEL_CH0 => sci_ch_i(0),
+ RXICLK_CH0 => rx_fullclk_i(0), -- CLK, -- ?
+ TXICLK_CH0 => CLK,
+ RX_FULL_CLK_CH0 => rx_fullclk_i(0),
+ RX_HALF_CLK_CH0 => open,
+ TX_FULL_CLK_CH0 => tx_fullclk_i(0),
+ TX_HALF_CLK_CH0 => open,
+ FPGA_RXREFCLK_CH0 => CLK,
+ TXDATA_CH0 => tx_data(0),
+ TX_K_CH0 => tx_k(0),
+ TX_FORCE_DISP_CH0 => '0',
+ TX_DISP_SEL_CH0 => '0',
+ RXDATA_CH0 => rx_data(0),
+ RX_K_CH0 => rx_k(0),
+ RX_DISP_ERR_CH0 => open,
+ RX_CV_ERR_CH0 => rx_cv_err(0),
+ rx_serdes_rst_ch0_c => rx_serdes_rst(0),
+ SB_FELB_CH0_C => '0', --loopback enable
+ SB_FELB_RST_CH0_C => '0', --loopback reset
+ tx_pcs_rst_ch0_c => tx_pcs_rst(0),
+ TX_PWRUP_CH0_C => '1', --tx power up
+ rx_pcs_rst_ch0_c => rx_pcs_rst(0),
+ RX_PWRUP_CH0_C => '1', --rx power up
+ RX_LOS_LOW_CH0_S => rx_los_low(0),
+ LSM_STATUS_CH0_S => link_ok(0),
+ RX_CDR_LOL_CH0_S => rx_cdr_lol(0),
+ TX_DIV2_MODE_CH0_C => '0', --full rate
+ RX_DIV2_MODE_CH0_C => '0', --full rate
+-- CH1 --
+ HDINP_CH1 => sd_rxd_p_in(1),
+ HDINN_CH1 => sd_rxd_n_in(1),
+ HDOUTP_CH1 => sd_txd_p_out(1),
+ HDOUTN_CH1 => sd_txd_n_out(1),
+ SCI_SEL_CH1 => sci_ch_i(1),
+ RXICLK_CH1 => rx_fullclk_i(1), -- CLK, -- ?
+ TXICLK_CH1 => CLK,
+ RX_FULL_CLK_CH1 => rx_fullclk_i(1),
+ RX_HALF_CLK_CH1 => open,
+ TX_FULL_CLK_CH1 => tx_fullclk_i(1),
+ TX_HALF_CLK_CH1 => open,
+ FPGA_RXREFCLK_CH1 => CLK,
+ TXDATA_CH1 => tx_data(1),
+ TX_K_CH1 => tx_k(1),
+ TX_FORCE_DISP_CH1 => '0',
+ TX_DISP_SEL_CH1 => '0',
+ RXDATA_CH1 => rx_data(1),
+ RX_K_CH1 => rx_k(1),
+ RX_DISP_ERR_CH1 => open,
+ RX_CV_ERR_CH1 => rx_cv_err(1),
+ rx_serdes_rst_ch1_c => rx_serdes_rst(1),
+ SB_FELB_CH1_C => '0', --loopback enable
+ SB_FELB_RST_CH1_C => '0', --loopback reset
+ tx_pcs_rst_ch1_c => tx_pcs_rst(1),
+ TX_PWRUP_CH1_C => '1', --tx power up
+ rx_pcs_rst_ch1_c => rx_pcs_rst(1),
+ RX_PWRUP_CH1_C => '1', --rx power up
+ RX_LOS_LOW_CH1_S => rx_los_low(1),
+ LSM_STATUS_CH1_S => link_ok(1),
+ RX_CDR_LOL_CH1_S => rx_cdr_lol(1),
+ TX_DIV2_MODE_CH1_C => '0', --full rate
+ RX_DIV2_MODE_CH1_C => '0', --full rate
+-- CH2 --
+ HDINP_CH2 => sd_rxd_p_in(2),
+ HDINN_CH2 => sd_rxd_n_in(2),
+ HDOUTP_CH2 => sd_txd_p_out(2),
+ HDOUTN_CH2 => sd_txd_n_out(2),
+ SCI_SEL_CH2 => sci_ch_i(2),
+ RXICLK_CH2 => rx_fullclk_i(2), -- CLK, -- ?
+ TXICLK_CH2 => CLK,
+ RX_FULL_CLK_CH2 => rx_fullclk_i(2),
+ RX_HALF_CLK_CH2 => open,
+ TX_FULL_CLK_CH2 => tx_fullclk_i(2),
+ TX_HALF_CLK_CH2 => open,
+ FPGA_RXREFCLK_CH2 => CLK,
+ TXDATA_CH2 => tx_data(2),
+ TX_K_CH2 => tx_k(2),
+ TX_FORCE_DISP_CH2 => '0',
+ TX_DISP_SEL_CH2 => '0',
+ RXDATA_CH2 => rx_data(2),
+ RX_K_CH2 => rx_k(2),
+ RX_DISP_ERR_CH2 => open,
+ RX_CV_ERR_CH2 => rx_cv_err(2),
+ rx_serdes_rst_ch2_c => rx_serdes_rst(2),
+ SB_FELB_CH2_C => '0', --loopback enable
+ SB_FELB_RST_CH2_C => '0', --loopback reset
+ tx_pcs_rst_ch2_c => tx_pcs_rst(2),
+ TX_PWRUP_CH2_C => '1', --tx power up
+ rx_pcs_rst_ch2_c => rx_pcs_rst(2),
+ RX_PWRUP_CH2_C => '1', --rx power up
+ RX_LOS_LOW_CH2_S => rx_los_low(2),
+ LSM_STATUS_CH2_S => link_ok(2),
+ RX_CDR_LOL_CH2_S => rx_cdr_lol(2),
+ TX_DIV2_MODE_CH2_C => '0', --full rate
+ RX_DIV2_MODE_CH2_C => '0', --full rate
+-- CH3 --
+ HDINP_CH3 => sd_rxd_p_in(3),
+ HDINN_CH3 => sd_rxd_n_in(3),
+ HDOUTP_CH3 => sd_txd_p_out(3),
+ HDOUTN_CH3 => sd_txd_n_out(3),
+ SCI_SEL_CH3 => sci_ch_i(3),
+ RXICLK_CH3 => rx_fullclk_i(3), -- CLK, -- ?
+ TXICLK_CH3 => CLK,
+ RX_FULL_CLK_CH3 => rx_fullclk_i(3),
+ RX_HALF_CLK_CH3 => open,
+ TX_FULL_CLK_CH3 => tx_fullclk_i(3),
+ TX_HALF_CLK_CH3 => open,
+ FPGA_RXREFCLK_CH3 => CLK,
+ TXDATA_CH3 => tx_data(3),
+ TX_K_CH3 => tx_k(3),
+ TX_FORCE_DISP_CH3 => '0',
+ TX_DISP_SEL_CH3 => '0',
+ RXDATA_CH3 => rx_data(3),
+ RX_K_CH3 => rx_k(3),
+ RX_DISP_ERR_CH3 => open,
+ RX_CV_ERR_CH3 => rx_cv_err(3),
+ rx_serdes_rst_ch3_c => rx_serdes_rst(3),
+ SB_FELB_CH3_C => '0', --loopback enable
+ SB_FELB_RST_CH3_C => '0', --loopback reset
+ tx_pcs_rst_ch3_c => tx_pcs_rst(3),
+ TX_PWRUP_CH3_C => '1', --tx power up
+ rx_pcs_rst_ch3_c => rx_pcs_rst(3),
+ RX_PWRUP_CH3_C => '1', --rx power up
+ RX_LOS_LOW_CH3_S => rx_los_low(3),
+ LSM_STATUS_CH3_S => link_ok(3),
+ RX_CDR_LOL_CH3_S => rx_cdr_lol(3),
+ TX_DIV2_MODE_CH3_C => '0', --full rate
+ RX_DIV2_MODE_CH3_C => '0', --full rate
+---- Miscillaneous ports
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_addr_i(8),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+ FPGA_TXREFCLK => CLK,
+ TX_SERDES_RST_C => CLEAR,
+ TX_PLL_LOL_QD_S => tx_pll_lol,
+ TX_SYNC_QD_C => tx_sync_qd_c,
+ rst_qd_c => rst_qd,
+ SERDES_RST_QD_C => ffc_quad_rst
+ );
+
+
+-------------------------------------------------
+-- Reset FSM & Link states
+-------------------------------------------------
+process(CLK)
+begin
+ if (rising_edge(CLK)) then
+ if rst_qd_S/="0000" then
+ rst_qd <= '1';
+ else
+ rst_qd <= '0';
+ end if;
+ tx_sync_qd_c <= tx_sync_qd_c_S;
+ end if;
+end process;
+
+process(CLK)
+variable prev_state_ok : std_logic_vector(0 to 3) := "0000";
+variable cntr : std_logic_vector(3 downto 0) := "0000";
+begin
+ if (rising_edge(CLK)) then
+ if ((tx_fsm_state(0)=x"5") and (prev_state_ok(0)='0')) or
+ ((tx_fsm_state(1)=x"5") and (prev_state_ok(1)='0')) or
+ ((tx_fsm_state(2)=x"5") and (prev_state_ok(2)='0')) or
+ ((tx_fsm_state(3)=x"5") and (prev_state_ok(3)='0')) then
+ tx_sync_qd_c_S <= not tx_sync_qd_c_S;
+ cntr := (others => '0');
+ else -- double toggle, necessary?
+ if cntr="1110" then
+ tx_sync_qd_c_S <= not tx_sync_qd_c_S;
+ end if;
+ if cntr/="1111" then
+ cntr := cntr+1;
+ end if;
+ end if;
+ for i in 0 to 3 loop
+ if (tx_fsm_state(i)=x"5") then
+ prev_state_ok(i) := '1';
+ else
+ prev_state_ok(i) := '0';
+ end if;
+ end loop;
+ end if;
+end process;
+
+GENERATE_RESET_FSM: for i in 0 to 3 generate
+
+THE_RX_FSM : rx_reset_fsm
+ port map(
+ RST_N => rx_rst_n,
+ RX_REFCLK => CLK,
+ TX_PLL_LOL_QD_S => tx_pll_lol,
+ RX_SERDES_RST_CH_C => rx_serdes_rst(i),
+ RX_CDR_LOL_CH_S => rx_cdr_lol(i),
+ RX_LOS_LOW_CH_S => rx_los_low(i),
+ RX_PCS_RST_CH_C => rx_pcs_rst(i),
+ WA_POSITION => "0000", -- for master
+ STATE_OUT => rx_fsm_state(i) -- ready when x"6"
+ );
+
+rx_rst_n <= '0' when (RESET='1') or (CLEAR='1') else '1';
+
+THE_TX_FSM : tx_reset_fsm
+ port map(
+ RST_N => tx_rst_n,
+ TX_REFCLK => CLK,
+ TX_PLL_LOL_QD_S => tx_pll_lol,
+ RST_QD_C => rst_qd_S(i),
+ TX_PCS_RST_CH_C => tx_pcs_rst(i),
+ STATE_OUT => tx_fsm_state(i) -- ready when x"5"
+ );
+
+process(CLK)
+begin
+ if (rising_edge(CLK)) then
+ tx_rst_n <= not CLEAR;
+ end if;
+end process;
+
+end generate;
+
+
+GENERATE_RXDATA_FSM: for i in 0 to 3 generate
+
+ HUB_8to16_SODA1: HUB_8to16_SODA
+ port map(
+ clock => rx_fullclk_i(i),
+ reset => RESET,
+ data_in => rx_data(i),
+ char_is_k => rx_k(i),
+ fifo_data => fifo_rx_din(i*18+17 downto i*18),
+ fifo_full => fifo_rx_full(i),
+ fifo_write => fifo_rx_wr_en(i),
+ RX_DLM => RX_DLM_S(i),
+ RX_DLM_WORD => RX_DLM_WORD_S(8*i+7 downto 8*i),
+ error => open
+ );
+
+ THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO)
+ port map(
+ read_clock_in => SYSCLK,
+ write_clock_in => rx_fullclk_i(i),
+ read_enable_in => fifo_rx_rd_en(i),
+ write_enable_in => fifo_rx_wr_en(i),
+ fifo_gsr_in => fifo_rx_reset(i),
+ write_data_in => fifo_rx_din(i*18+17 downto i*18),
+ read_data_out => fifo_rx_dout(i*18+17 downto i*18),
+ full_out => fifo_rx_full(i),
+ empty_out => fifo_rx_empty(i)
+ );
+ fifo_rx_reset(i) <= reset_i or not rx_allow_q(i);
+ fifo_rx_rd_en(i) <= not fifo_rx_empty(i);
+
+ buf_med_data_out(i*16+15 downto i*16) <= fifo_rx_dout(i*18+15 downto i*18);
+ buf_med_dataready_out(i) <= not fifo_rx_dout(i*18+17) and not fifo_rx_dout(i*18+16)
+ and not last_fifo_rx_empty(i) and rx_allow_q(i);
+ buf_med_packet_num_out(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3);
+
+ THE_SYNC_PROC: process(SYSCLK)
+ begin
+ if rising_edge(SYSCLK)then
+ med_dataready_out(i) <= buf_med_dataready_out(i);
+ med_data_out(i*16+15 downto i*16) <= buf_med_data_out(i*16+15 downto i*16);
+ med_packet_num_out(i*3+2 downto i*3) <= buf_med_packet_num_out(i*3+2 downto i*3);
+ if reset_i = '1' then
+ med_dataready_out(i) <= '0';
+ end if;
+ end if;
+ end process;
+
+ --rx packet counter
+ ---------------------
+ THE_RX_PACKETS_PROC: process(SYSCLK)
+ begin
+ if (rising_edge(SYSCLK)) then
+ last_fifo_rx_empty(i) <= fifo_rx_empty(i);
+ if reset_i = '1' or rx_allow_q(i) = '0' then
+ rx_counter(i*3+2 downto i*3) <= c_H0;
+ else
+ if( buf_med_dataready_out(i) = '1' ) then
+ if( rx_counter(i*3+2 downto i*3) = c_max_word_number ) then
+ rx_counter(i*3+2 downto i*3) <= (others => '0');
+ else
+ rx_counter(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3) + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ THE_CNT_RESET_PROC : process(rx_fullclk_i(i))
+ begin
+ if rising_edge(rx_fullclk_i(i)) then
+ reset_i_rx(i) <= reset_i;
+ if reset_i_rx(i) = '1' then
+ send_reset_words(i) <= '0';
+ make_trbnet_reset(i) <= '0';
+ reset_word_cnt(i) <= (others => '0');
+ else
+ send_reset_words(i) <= '0';
+ make_trbnet_reset(i) <= '0';
+ if (rx_k(i)='1') and (rx_data(i)=x"FE") then
+ if reset_word_cnt(i)(4) = '0' then
+ reset_word_cnt(i) <= reset_word_cnt(i) + 1;
+ else
+ send_reset_words(i) <= '1';
+ end if;
+ else
+ reset_word_cnt(i) <= (others => '0');
+ make_trbnet_reset(i) <= reset_word_cnt(i)(4);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ THE_RESET_SYNC: HUB_posedge_to_pulse
+ port map(
+ clock_in => rx_fullclk_i(i),
+ clock_out => SYSCLK,
+ en_clk => '1',
+ signal_in => make_trbnet_reset(i),
+ pulse => make_trbnet_reset_q(i)
+ );
+
+ HUB_SODA_clockcrossing1: HUB_SODA_clockcrossing
+ port map(
+ write_clock => rx_fullclk_i(i),
+ read_clock => CLK,
+ DLM_in => RX_DLM_S(i),
+ DLM_WORD_in => RX_DLM_WORD_S(8*i+7 downto 8*i),
+ DLM_out => RX_DLM(i),
+ DLM_WORD_out => RX_DLM_WORD(i*8+7 downto i*8),
+ error => open
+ );
+
+end generate; -- end GENERATE_RXDATA_FSM
+
+GENERATE_TXDATA_FSM: for i in 0 to 3 generate
+
+ HUB_16to8_SODA1: HUB_16to8_SODA
+ port map(
+ clock => CLK,
+ reset => send_reset_in(i),
+ fifo_data => fifo_tx_dout(i*18+15 downto i*18),
+ fifo_empty => fifo_tx_empty(i),
+ fifo_read => fifo_tx_rd_en(i),
+ TX_DLM => TX_DLM(i),
+ TX_DLM_WORD => TX_DLM_WORD(i*8+7 downto i*8),
+ data_out => tx_data(i),
+ char_is_k => tx_k(i),
+ error => open
+ );
+
+ --TX Fifo & Data output to Serdes
+ THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO)
+ port map(
+ read_clock_in => CLK,
+ write_clock_in => SYSCLK,
+ read_enable_in => fifo_tx_rd_en(i),
+ write_enable_in => fifo_tx_wr_en(i),
+ fifo_gsr_in => fifo_tx_reset(i),
+ write_data_in => fifo_tx_din(i*18+17 downto i*18),
+ read_data_out => fifo_tx_dout(i*18+17 downto i*18),
+ full_out => fifo_tx_full(i),
+ empty_out => fifo_tx_empty(i),
+ almost_full_out => fifo_tx_almost_full(i)
+ );
+
+ fifo_tx_reset(i) <= reset_i or not tx_allow_q(i);
+ fifo_tx_din(i*18+17 downto i*18) <= med_packet_num_in(i*3+2) & med_packet_num_in(i*3+0) & med_data_in(i*16+15 downto i*16);
+ fifo_tx_wr_en(i) <= med_dataready_in(i) and tx_allow_q(i);
+ med_read_out(i) <= tx_allow_q(i) and not fifo_tx_almost_full(i);
+
+end generate; -- end GENERATE_TXDATA_FSM
+
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+-- SerDes clock output to FPGA fabric
+refclk2core_out <= '0';
+
+--------------------------------------------------------------------------
+--Generate LED signals
+--------------------------------------------------------------------------
+PROC_LED : process(SYSCLK)
+begin
+ if rising_edge(SYSCLK) then
+ led_counter <= led_counter + 1;
+
+ if led_counter = 0 then
+ rx_led <= x"0";
+ else
+ rx_led <= rx_led or buf_med_dataready_out;
+ end if;
+ if led_counter = 0 then
+ tx_led <= x"0";
+ else
+ tx_led <= tx_led or not (tx_k(3) & tx_k(2) & tx_k(1) & tx_k(0));
+ end if;
+ end if;
+end process;
+
+gen_outputs : for i in 0 to 3 generate
+ stat_op(i*16+15) <= send_reset_words_q(i);
+ stat_op(i*16+14) <= buf_stat_op(i*16+14);
+ stat_op(i*16+13) <= make_trbnet_reset_q(i);
+ stat_op(i*16+12) <= '0';
+ stat_op(i*16+11) <= tx_led(i); --tx led
+ stat_op(i*16+10) <= rx_led(I); --rx led
+ stat_op(i*16+9 downto i*16+0) <= buf_stat_op(i*16+9 downto i*16+0);
+
+ -- Debug output
+ stat_debug(i*64+7 downto i*64+0) <= rx_data(i);
+ stat_debug(i*64+16) <= rx_k(i);
+ stat_debug(i*64+19 downto i*64+18) <= (others => '0');
+ stat_debug(i*64+23 downto i*64+20) <= buf_stat_debug(i*16+3 downto i*16+0);
+ stat_debug(i*64+24) <= fifo_rx_rd_en(i);
+ stat_debug(i*64+25) <= fifo_rx_wr_en(i);
+ stat_debug(i*64+26) <= fifo_rx_reset(i);
+ stat_debug(i*64+27) <= fifo_rx_empty(i);
+ stat_debug(i*64+28) <= fifo_rx_full_q(i);
+ stat_debug(i*64+29) <= '0';
+ stat_debug(i*64+30) <= rx_allow_q(i);
+ stat_debug(i*64+41 downto i*64+31) <= (others => '0');
+ stat_debug(i*64+42) <= sysclk;
+ stat_debug(i*64+43) <= sysclk;
+ stat_debug(i*64+59 downto i*64+44) <= (others => '0');
+ stat_debug(i*64+63 downto i*64+60) <= buf_stat_debug(i*16+3 downto i*16+0);
+end generate;
+
+end architecture;
\ No newline at end of file
<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="2.0" title="SODA_source" device="LFE3-150EA-8FN672C" synthesis="synplify" default_implementation="SODA_source">
+<BaliProject version="3.2" title="trb3_periph_hub_SODA" device="LFE3-150EA-8FN672C" default_implementation="trb3_periph_hub_SODA">
<Options/>
- <Implementation title="SODA_source" dir="SODA_source" description="SODA_source" default_strategy="Strategy1">
- <Options def_top="TDC" top="trb3_periph_sodasource"/>
- <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
+ <Implementation title="trb3_periph_hub_SODA" dir="trb3_periph_hub_SODA" description="trb3_periph_hub_SODA" synthesis="synplify" default_strategy="Strategy1">
+ <Options def_top="pll_in125_out125" top="trb3_periph_hub_SODA"/>
+ <Source name="trb3_periph_hub_SODA.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="trb3_periph_hub_SODA"/>
</Source>
<Source name="version.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/basics/priority_arbiter.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
<Source name="../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../../trbnet/basics/wide_adder_17x16.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net_sbuf4.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net_sbuf3.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net_sbuf2.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
<Source name="../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net16_hub_logic_2.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net16_hub_ipu_logic.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/special/slv_register.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/lattice/ecp3/fifo_dualclock_width_16_reg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trb3/base/cores/pll_in125_out125.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.lpc" type="LPC_Module" type_short="LPC">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Source name="sources/lattice/ecp3/sfp_3sync_200_int.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Source name="sources/HUB_8to16_SODA.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Source name="sources/HUB_16to8_SODA.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Source name="sources/HUB_SODA_clockcrossing.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../data_concentrator/sources/Panda_package.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../source/soda_hub.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../source/soda_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+ <Source name="sources/lattice/trb_net16_med_sync3_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+ <Source name="sources/lattice/trb_net16_med_syncfull_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../source/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+ <Source name="../source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="sources/lattice/ecp3/serdes_sync_200_full.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
-
- <Source name="trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb3_periph_sodasource"/>
+ <Source name="sources/lattice/ecp3/async_fifo_16x8_ecp3.ipx" type="IPX_Module" type_short="IPX">
+ <Options/>
+ </Source>
+ <Source name="sources/lattice/async_fifo_16x8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="sources/lattice/serdes_tx_reset_sm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="sources/HUB_posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="reveal_SODA1.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+ <Options/>
</Source>
- <Source name="../../trb3/tdc_releases/tdc_v1.1.1/bit_sync.vhd" type="VHDL" type_short="VHDL">
+ <Source name="reveal_SODA2.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
<Options/>
</Source>
- <Source name="../../source/soda_intercept.vhd" type="VHDL" type_short="VHDL">
+ <Source name="reveal_uplink1.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
<Options/>
</Source>
- <Source name="../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" type="VHDL" type_short="VHDL">
+ <Source name="trb3_periph_hub_SODA.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
- <Source name="../trb3_periph_sodasource.lpf" type="Logic Preference" type_short="LPF">
+ <Source name="trb3_periph_hub_SODA.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
</Implementation>
- <Strategy name="Strategy1" file="SODA_source1.sty"/>
+ <Strategy name="Strategy1" file="trb3_periph_hub_SODA1.sty"/>
</BaliProject>
--- /dev/null
+rvl_alias "rx_clock_200" "rx_clock_200";
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+ SYSCONFIG MCCLK_FREQ = 20;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Reset Nets
+#################################################################
+GSR_NET NET "GSR_N";
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18" ;
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+#################################################################
+# Trigger I/O
+#################################################################
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3" ;
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24" ;
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+#################################################################
+# To central FPGA
+#################################################################
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;
+LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;
+LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "TEST_LINE_0" SITE "A5" ;
+LOCATE COMP "TEST_LINE_1" SITE "A6" ;
+LOCATE COMP "TEST_LINE_2" SITE "G8" ;
+LOCATE COMP "TEST_LINE_3" SITE "F9" ;
+LOCATE COMP "TEST_LINE_4" SITE "D9" ;
+LOCATE COMP "TEST_LINE_5" SITE "D10" ;
+LOCATE COMP "TEST_LINE_6" SITE "F10" ;
+LOCATE COMP "TEST_LINE_7" SITE "E10" ;
+LOCATE COMP "TEST_LINE_8" SITE "A8" ;
+LOCATE COMP "TEST_LINE_9" SITE "B8" ;
+LOCATE COMP "TEST_LINE_10" SITE "G10" ;
+LOCATE COMP "TEST_LINE_11" SITE "G9" ;
+LOCATE COMP "TEST_LINE_12" SITE "C9" ;
+LOCATE COMP "TEST_LINE_13" SITE "C10" ;
+LOCATE COMP "TEST_LINE_14" SITE "H10" ;
+LOCATE COMP "TEST_LINE_15" SITE "H11" ;
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
+#################################################################
+# Connection to AddOn
+#################################################################
+LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1
+LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3
+LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5
+LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7
+LOCATE COMP "SFP_MOD1_1" SITE "R1" ;#DQLL0_4 #9
+LOCATE COMP "SFP_MOD2_1" SITE "R2" ;#DQLL0_5 #11
+LOCATE COMP "SFP_RATESEL_1" SITE "N3" ;#DQSLL0_T #13
+LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15
+LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17
+LOCATE COMP "SFP_TXFAULT_1" SITE "P6" ;#DQLL0_7 #19
+LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21
+LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23
+LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25
+LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27
+LOCATE COMP "SFP_MOD1_2" SITE "AB1" ;#DQLL2_2 #29
+LOCATE COMP "SFP_MOD2_2" SITE "AC1" ;#DQLL2_3 #31
+LOCATE COMP "SFP_RATESEL_2" SITE "AA1" ;#DQLL2_4 #33
+LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35
+LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
+LOCATE COMP "SFP_TXFAULT_2" SITE "W6" ;#DQLL2_C #39 #should be DQSLL2
+LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2
+LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4
+LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6
+LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8
+LOCATE COMP "SFP_MOD1_3" SITE "AB3" ;#DQLL3_4 #10
+LOCATE COMP "SFP_MOD2_3" SITE "AB4" ;#DQLL3_5 #12
+LOCATE COMP "SFP_RATESEL_3" SITE "Y6" ;#DQLL3_T #14 #should be DQSLL3
+LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
+LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18
+LOCATE COMP "SFP_TXFAULT_3" SITE "AA4" ;#DQLL3_7 #20
+LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22
+LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24
+LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26
+LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28
+LOCATE COMP "SFP_MOD1_4" SITE "T1" ;#DQLL1_2 #30
+LOCATE COMP "SFP_MOD2_4" SITE "U1" ;#DQLL1_3 #32
+LOCATE COMP "SFP_RATESEL_4" SITE "P4" ;#DQLL1_4 #34
+LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36
+LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38
+LOCATE COMP "SFP_TXFAULT_4" SITE "R4" ;#DQSLL1_C #40
+LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169
+LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171
+LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173
+LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175
+LOCATE COMP "SFP_MOD1_5" SITE "AA26" ;#DQLR1_4 #177
+LOCATE COMP "SFP_MOD2_5" SITE "AB26" ;#DQLR1_5 #179
+LOCATE COMP "SFP_RATESEL_5" SITE "W21" ;#DQSLR1_T #181
+LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183
+LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185
+LOCATE COMP "SFP_TXFAULT_5" SITE "AA23" ;#DQLR1_7 #187
+LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170
+LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172
+LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174
+LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176
+LOCATE COMP "SFP_MOD1_6" SITE "T26" ;#DQLR2_4 #178
+LOCATE COMP "SFP_MOD2_6" SITE "U26" ;#DQLR2_5 #180
+LOCATE COMP "SFP_RATESEL_6" SITE "V21" ;#DQSLR2_T #182
+LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184
+LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186
+LOCATE COMP "SFP_TXFAULT_6" SITE "V24" ;#DQLR2_7 #188
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+LOCATE COMP "SPARE_LINE_0" SITE "M25" ;#194
+LOCATE COMP "SPARE_LINE_1" SITE "M26" ;#196
+LOCATE COMP "SPARE_LINE_2" SITE "W4" ;#198
+LOCATE COMP "SPARE_LINE_3" SITE "W5" ;#200
+LOCATE COMP "SPARE_LINE_4" SITE "M3" ;#DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP "SPARE_LINE_5" SITE "M2" ;#DQUL3_9_OUTOFLANE_FPGA__3 #71
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP "FLASH_CLK" SITE "B12" ;
+LOCATE COMP "FLASH_CS" SITE "E11" ;
+LOCATE COMP "FLASH_DIN" SITE "E12" ;
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "B11" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20" ;
+LOCATE COMP "CODE_LINE_0" SITE "Y21" ;
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14" ;
+IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12" ;
+LOCATE COMP "LED_ORANGE" SITE "G13" ;
+LOCATE COMP "LED_RED" SITE "A15" ;
+LOCATE COMP "LED_YELLOW" SITE "A16" ;
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+MULTICYCLE TO GROUP "LED_group" 100.000000 ns ;
+
+
+
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP "THE_MEDIA_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+
+
+#REGION "MEDIA_UPLINK" "R90C95D" 13 25;
+#REGION "MEDIA_DOWNLINK" "R55C120D" 25 35;
+#REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;
+#REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE;
+
+LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
+LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
+
+LOCATE UGROUP "gen_sync_media_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "gen_full_media_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "THE_MEDIA_DOWNLINK/media_interface_group" REGION "MEDIA_DOWNLINK" ;
+
+#LOCATE UGROUP "THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_3_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_4_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_5_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_6_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+
+#LOCATE UGROUP "THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+
+MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+
+
+#not releated:
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "rx_clock_200" 200 ns ;
+MULTICYCLE FROM CLKNET "rx_clock_200" TO CLKNET "clk_100_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "rx_clock_200" 200 ns ;
+MULTICYCLE FROM CLKNET "rx_clock_200" TO CLKNET "clk_200_i" 200 ns ;
+
+MULTICYCLE FROM CLKNET "THE_MEDIA_UPLINK/sci_read_i" TO CLKNET "clk_100_i" 200 ns ;
+MULTICYCLE FROM CLKNET "THE_MEDIA_UPLINK/sci_read_i" TO CLKNET "clk_200_i" 200 ns ;
+MULTICYCLE FROM CLKNET "THE_MEDIA_UPLINK/sci_read_i" TO CLKNET "rx_clock_200" 200 ns ;
+
+
+BLOCK JTAGPATHS;
use work.trb_net_std.all;
use work.trb_net_components.all;
use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
+--use work.trb3_components.all;
use work.version.all;
+use work.soda_components.all;
+use work.panda_package.all;
-entity trb3_periph_hub is
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission. 4 SFP links only.
- );
+entity trb3_periph_hub_SODA is
port(
--Clocks
CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
TEST_LINE : out std_logic_vector(15 downto 0)
);
-
attribute syn_useioff : boolean;
--no IO-FF for LEDs relaxes timing constraints
attribute syn_useioff of LED_GREEN : signal is false;
end entity;
-architecture trb3_periph_hub_arch of trb3_periph_hub is
+architecture trb3_periph_hub_SODA_arch of trb3_periph_hub_SODA is
--Constants
constant REGIO_NUM_STAT_REGS : integer := 2;
constant REGIO_NUM_CTRL_REGS : integer := 2;
+component trb_net16_med_sync3_ecp3_sfp is
+ port(
+ CLK : in std_logic; -- SerDes clock
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ REFCLK2CORE_OUT : out std_logic;
+ CLK_RX_HALF_OUT : out std_logic;
+ CLK_RX_FULL_OUT : out std_logic;
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_DLM_IN : in std_logic;
+ SD_DLM_WORD_IN : in std_logic_vector(7 downto 0);
+ SD_DLM_OUT : out std_logic;
+ SD_DLM_WORD_OUT : out std_logic_vector(7 downto 0);
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+end component;
+
+component trb_net16_med_syncfull_ecp3_sfp is
+ port(
+ CLK : in std_logic; -- SerDes clock
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
+ MED_READ_OUT : out std_logic_vector(3 downto 0);
+ MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);
+ MED_READ_IN : in std_logic_vector(3 downto 0);
+ REFCLK2CORE_OUT : out std_logic;
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic_vector(3 downto 0);
+ SD_RXD_N_IN : in std_logic_vector(3 downto 0);
+ SD_TXD_P_OUT : out std_logic_vector(3 downto 0);
+ SD_TXD_N_OUT : out std_logic_vector(3 downto 0);
+ SD_REFCLK_P_IN : in std_logic;
+ SD_REFCLK_N_IN : in std_logic;
+ SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable
+ --Synchronous signals
+ RX_DLM : out std_logic_vector(3 downto 0);
+ RX_DLM_WORD : out std_logic_vector(4*8-1 downto 0);
+ TX_DLM : in std_logic_vector(3 downto 0);
+ TX_DLM_WORD : in std_logic_vector(4*8-1 downto 0);
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out std_logic_vector (4*16-1 downto 0);
+ CTRL_OP : in std_logic_vector (4*16-1 downto 0);
+ STAT_DEBUG : out std_logic_vector (64*4-1 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+end component;
+
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
signal GSR_N : std_logic;
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
- signal clk_100_internal : std_logic;
- signal clk_200_internal : std_logic;
signal rx_clock_100 : std_logic;
signal rx_clock_200 : std_logic;
+ attribute syn_keep of rx_clock_200 : signal is true;
+ attribute syn_preserve of rx_clock_200 : signal is true;
--Media Interface
signal med_stat_op : std_logic_vector (7*16-1 downto 0);
signal sci2_data_out : std_logic_vector(7 downto 0);
signal sci2_addr : std_logic_vector(8 downto 0);
- --FPGA Test
+ -- soda hub
+ signal soda_read_en : std_logic;
+ signal soda_write_en : std_logic;
+ signal soda_ack : std_logic;
+ signal soda_addr : std_logic_vector(3 downto 0);
+ signal soda_data_in : std_logic_vector(31 downto 0);
+ signal soda_data_out : std_logic_vector(31 downto 0);
+
+
+ signal DLM_to_uplink_S : std_logic;
+ signal DLM_WORD_to_uplink_S : std_logic_vector(7 downto 0);
+ signal DLM_from_uplink_S : std_logic;
+ signal DLM_WORD_from_uplink_S : std_logic_vector(7 downto 0);
+
+ signal DLM_from_downlink_S : std_logic_vector(3 downto 0);
+ signal DLM_WORD_from_downlink_S : std_logic_vector(8*4-1 downto 0);
+ signal DLM_to_downlink_S : std_logic_vector(3 downto 0);
+ signal DLM_WORD_to_downlink_S : std_logic_vector(8*4-1 downto 0);
+
+
+ --FPGA Test
signal time_counter : unsigned(31 downto 0);
port map(
CLEAR_IN => '0', -- reset input (high active, async)
CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_internal, -- raw master clock, NOT from PLL/DLL!
+ CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', -- general reset signal (SYSCLK)
THE_MAIN_PLL : pll_in200_out100
port map(
CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_internal,
- CLKOK => clk_200_internal,
+ RESET => '0',
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
LOCK => pll_lock
);
-
-gen_sync_clocks : if SYNC_MODE = c_YES generate
- clk_100_i <= rx_clock_100;
- clk_200_i <= rx_clock_200;
-end generate;
-
-gen_local_clocks : if SYNC_MODE = c_NO generate
- clk_100_i <= clk_100_internal;
- clk_200_i <= clk_200_internal;
-end generate;
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
---------------------------------------------------------------------------
-gen_full_media : if SYNC_MODE = c_NO generate
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp_4
- generic map(
- REVERSE_ORDER => c_NO, --order of ports
- FREQUENCY => 200 --run on 200 MHz clock
- )
- port map(
- CLK => clk_200_i,
- SYSCLK => clk_100_i,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN(0*16+15 downto 0*16) => (others => '0'),
- MED_DATA_IN(1*16+15 downto 1*16) => med_data_out(0*16+15 downto 0*16),
- MED_DATA_IN(2*16+15 downto 2*16) => med_data_out(5*16+15 downto 5*16),
- MED_DATA_IN(3*16+15 downto 3*16) => med_data_out(3*16+15 downto 3*16),
-
- MED_PACKET_NUM_IN(0*3+2 downto 0*3) => "000",
- MED_PACKET_NUM_IN(1*3+2 downto 1*3) => med_packet_num_out(0*3+2 downto 0*3),
- MED_PACKET_NUM_IN(2*3+2 downto 2*3) => med_packet_num_out(5*3+2 downto 5*3),
- MED_PACKET_NUM_IN(3*3+2 downto 3*3) => med_packet_num_out(3*3+2 downto 3*3),
-
- MED_DATAREADY_IN(0) => '0',
- MED_DATAREADY_IN(1) => med_dataready_out(0),
- MED_DATAREADY_IN(2) => med_dataready_out(5),
- MED_DATAREADY_IN(3) => med_dataready_out(3),
-
- MED_READ_OUT(0) => open,
- MED_READ_OUT(1) => med_read_in(0),
- MED_READ_OUT(2) => med_read_in(5),
- MED_READ_OUT(3) => med_read_in(3),
-
- MED_DATA_OUT(0*16+15 downto 0*16) => open,
- MED_DATA_OUT(1*16+15 downto 1*16) => med_data_in(0*16+15 downto 0*16),
- MED_DATA_OUT(2*16+15 downto 2*16) => med_data_in(5*16+15 downto 5*16),
- MED_DATA_OUT(3*16+15 downto 3*16) => med_data_in(3*16+15 downto 3*16),
-
- MED_PACKET_NUM_OUT(0*3+2 downto 0*3) => open,
- MED_PACKET_NUM_OUT(1*3+2 downto 1*3) => med_packet_num_in(0*3+2 downto 0*3),
- MED_PACKET_NUM_OUT(2*3+2 downto 2*3) => med_packet_num_in(5*3+2 downto 5*3),
- MED_PACKET_NUM_OUT(3*3+2 downto 3*3) => med_packet_num_in(3*3+2 downto 3*3),
- MED_DATAREADY_OUT(0) => open,
- MED_DATAREADY_OUT(1) => med_dataready_in(0),
- MED_DATAREADY_OUT(2) => med_dataready_in(5),
- MED_DATAREADY_OUT(3) => med_dataready_in(3),
- MED_READ_IN(0) => '1',
- MED_READ_IN(1) => med_read_out(0),
- MED_READ_IN(2) => med_read_out(5),
- MED_READ_IN(3) => med_read_out(3),
-
- REFCLK2CORE_OUT => open,
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(11 downto 8),
- SD_RXD_N_IN => SERDES_ADDON_RX(15 downto 12),
- SD_TXD_P_OUT => SERDES_ADDON_TX(11 downto 8),
- SD_TXD_N_OUT => SERDES_ADDON_TX(15 downto 12),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
- SD_PRSNT_N_IN(0) => '1',
- SD_PRSNT_N_IN(1) => FPGA5_COMM(0),
- SD_PRSNT_N_IN(2) => SFP_MOD0(5),
- SD_PRSNT_N_IN(3) => SFP_MOD0(3),
- SD_LOS_IN(0) => '1',
- SD_LOS_IN(1) => FPGA5_COMM(0),
- SD_LOS_IN(2) => SFP_LOS(5),
- SD_LOS_IN(3) => SFP_LOS(3),
- SD_TXDIS_OUT(0) => open,
- SD_TXDIS_OUT(1) => FPGA5_COMM(2),
- SD_TXDIS_OUT(2) => SFP_TXDIS(5),
- SD_TXDIS_OUT(3) => SFP_TXDIS(3),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- -- Status and control port
-
- STAT_OP(0*16+15 downto 0*16) => open,
- STAT_OP(1*16+15 downto 1*16) => med_stat_op(0*16+15 downto 0*16),
- STAT_OP(2*16+15 downto 2*16) => med_stat_op(5*16+15 downto 5*16),
- STAT_OP(3*16+15 downto 3*16) => med_stat_op(3*16+15 downto 3*16),
-
- CTRL_OP(0*16+15 downto 0*16) => x"0000",
- CTRL_OP(1*16+15 downto 1*16) => med_ctrl_op(0*16+15 downto 0*16),
- CTRL_OP(2*16+15 downto 2*16) => med_ctrl_op(5*16+15 downto 5*16),
- CTRL_OP(3*16+15 downto 3*16) => med_ctrl_op(3*16+15 downto 3*16),
-
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-end generate;
-
-gen_sync_media : if SYNC_MODE = c_YES generate
med_stat_op(3*16+15 downto 3*16) <= x"0007";
med_stat_op(5*16+15 downto 5*16) <= x"0007";
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => c_YES, --run on 200 MHz clock
- USE_CTC => c_NO,
- USE_SLAVE => c_YES
- )
+ THE_MEDIA_UPLINK : trb_net16_med_sync3_ecp3_sfp
port map(
- CLK => clk_200_internal,
- SYSCLK => clk_100_i,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
--Internal Connection
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
+ MED_DATA_IN => med_data_out(15 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(15 downto 0),
MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- REFCLK2CORE_OUT => open,
- CLK_RX_HALF_OUT => rx_clock_100,
- CLK_RX_FULL_OUT => rx_clock_200,
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
+ REFCLK2CORE_OUT => open,
+ CLK_RX_HALF_OUT => rx_clock_100,
+ CLK_RX_FULL_OUT => rx_clock_200,
--SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(8),
- SD_RXD_N_IN => SERDES_ADDON_RX(9),
- SD_TXD_P_OUT => SERDES_ADDON_TX(8),
- SD_TXD_N_OUT => SERDES_ADDON_TX(9),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
- SD_PRSNT_N_IN => FPGA5_COMM(0),
- SD_LOS_IN => FPGA5_COMM(0),
- SD_TXDIS_OUT => FPGA5_COMM(2),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
+ SD_RXD_P_IN => SERDES_ADDON_RX(8),
+ SD_RXD_N_IN => SERDES_ADDON_RX(9),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(8),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(9),
+ SD_DLM_IN => DLM_to_uplink_S,
+ SD_DLM_WORD_IN => DLM_WORD_to_uplink_S,
+ SD_DLM_OUT => DLM_from_uplink_S,
+ SD_DLM_WORD_OUT => DLM_WORD_from_uplink_S,
+ SD_PRSNT_N_IN => SFP_LOS(5), --//3?
+ SD_LOS_IN => SFP_LOS(5), --//3?
+ SD_TXDIS_OUT => SFP_TXDIS(5), --//3?
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
-- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => (others => '0')
+ STAT_OP => med_stat_op(15 downto 0),
+ CTRL_OP => med_ctrl_op(15 downto 0),
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => (others => '0')
);
-end generate;
-
-THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4
- generic map(
- REVERSE_ORDER => c_NO, --order of ports
- FREQUENCY => 200 --run on 200 MHz clock
- )
- port map(
- CLK => clk_200_i,
+
+THE_MEDIA_DOWNLINK : trb_net16_med_syncfull_ecp3_sfp port map(
+ CLK => rx_clock_200,
SYSCLK => clk_100_i,
RESET => reset_i,
CLEAR => clear_i,
MED_PACKET_NUM_IN(1*3+2 downto 1*3) => med_packet_num_out(6*3+2 downto 6*3),
MED_PACKET_NUM_IN(2*3+2 downto 2*3) => med_packet_num_out(2*3+2 downto 2*3),
MED_PACKET_NUM_IN(3*3+2 downto 3*3) => med_packet_num_out(4*3+2 downto 4*3),
-
+
MED_DATAREADY_IN(0) => med_dataready_out(1),
MED_DATAREADY_IN(1) => med_dataready_out(6),
MED_DATAREADY_IN(2) => med_dataready_out(2),
MED_READ_OUT(1) => med_read_in(6),
MED_READ_OUT(2) => med_read_in(2),
MED_READ_OUT(3) => med_read_in(4),
-
+
MED_DATA_OUT(0*16+15 downto 0*16) => med_data_in(1*16+15 downto 1*16),
MED_DATA_OUT(1*16+15 downto 1*16) => med_data_in(6*16+15 downto 6*16),
MED_DATA_OUT(2*16+15 downto 2*16) => med_data_in(2*16+15 downto 2*16),
MED_READ_IN(3) => med_read_out(4),
REFCLK2CORE_OUT => open,
- --SFP Connection
+
+ --SFP Connection
SD_RXD_P_IN => SERDES_ADDON_RX(3 downto 0),
SD_RXD_N_IN => SERDES_ADDON_RX(7 downto 4),
SD_TXD_P_OUT => SERDES_ADDON_TX(3 downto 0),
SD_TXD_N_OUT => SERDES_ADDON_TX(7 downto 4),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
+
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
SD_PRSNT_N_IN(0) => SFP_MOD0(1),
SD_PRSNT_N_IN(1) => SFP_MOD0(6),
SD_PRSNT_N_IN(2) => SFP_MOD0(2),
SD_PRSNT_N_IN(3) => SFP_MOD0(4),
+
SD_LOS_IN(0) => SFP_LOS(1),
SD_LOS_IN(1) => SFP_LOS(6),
SD_LOS_IN(2) => SFP_LOS(2),
SD_TXDIS_OUT(1) => SFP_TXDIS(6),
SD_TXDIS_OUT(2) => SFP_TXDIS(2),
SD_TXDIS_OUT(3) => SFP_TXDIS(4),
-
+
+ --Synchronous signals
+ RX_DLM => DLM_from_downlink_S,
+ RX_DLM_WORD => DLM_WORD_from_downlink_S,
+ TX_DLM => DLM_to_downlink_S,
+ TX_DLM_WORD => DLM_WORD_to_downlink_S,
+ --Control Interface
SCI_DATA_IN => sci2_data_in,
SCI_DATA_OUT => sci2_data_out,
SCI_ADDR => sci2_addr,
SCI_READ => sci2_read,
SCI_WRITE => sci2_write,
SCI_ACK => sci2_ack,
- -- Status and control port
-
+ -- Status and control port
STAT_OP(0*16+15 downto 0*16) => med_stat_op(1*16+15 downto 1*16),
STAT_OP(1*16+15 downto 1*16) => med_stat_op(6*16+15 downto 6*16),
STAT_OP(2*16+15 downto 2*16) => med_stat_op(2*16+15 downto 2*16),
CTRL_OP(3*16+15 downto 3*16) => med_ctrl_op(4*16+15 downto 4*16),
STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-
+ CTRL_DEBUG => (others => '0'));
---------------------------------------------------------------------------
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"b000", 3 => x"b200", others => x"0000"),
- PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 9, 3 => 9, others => 0)
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"b000", 3 => x"b200", 4 => x"e100", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 9, 3 => 9, 4 => 4, others => 0)
)
port map(
CLK => clk_100_i,
DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
--Bus Handler (SPI CTRL)
+ --Bus Handler (SPI Memory)
+ --SCI first Media Interface
+ --SCI second Media Interface
+ --SODA
BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_READ_ENABLE_OUT(2) => sci1_read,
+ BUS_READ_ENABLE_OUT(3) => sci2_read,
+ BUS_READ_ENABLE_OUT(4) => soda_read_en,
BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_WRITE_ENABLE_OUT(2) => sci1_write,
+ BUS_WRITE_ENABLE_OUT(3) => sci2_write,
+ BUS_WRITE_ENABLE_OUT(4) => soda_write_en,
BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_DATA_OUT(2*32+7 downto 2*32) => sci1_data_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
+ BUS_DATA_OUT(3*32+7 downto 3*32) => sci2_data_in,
+ BUS_DATA_OUT(3*32+31 downto 3*32+8) => open,
+ BUS_DATA_OUT(4*32+31 downto 4*32) => soda_data_in,
BUS_ADDR_OUT(0*16) => spictrl_addr,
BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
- BUS_DATAREADY_IN(0) => spictrl_ack,
- BUS_WRITE_ACK_IN(0) => spictrl_ack,
- BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
- BUS_UNKNOWN_ADDR_IN(0) => '0',
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
- BUS_DATAREADY_IN(1) => spimem_ack,
- BUS_WRITE_ACK_IN(1) => spimem_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- --SCI first Media Interface
- BUS_READ_ENABLE_OUT(2) => sci1_read,
- BUS_WRITE_ENABLE_OUT(2) => sci1_write,
- BUS_DATA_OUT(2*32+7 downto 2*32) => sci1_data_in,
- BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
BUS_ADDR_OUT(2*16+8 downto 2*16) => sci1_addr,
BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATA_IN(2*32+7 downto 2*32) => sci1_data_out,
- BUS_DATAREADY_IN(2) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => sci1_ack,
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => '0',
- --SCI second Media Interface
- BUS_READ_ENABLE_OUT(3) => sci2_read,
- BUS_WRITE_ENABLE_OUT(3) => sci2_write,
- BUS_DATA_OUT(3*32+7 downto 3*32) => sci2_data_in,
- BUS_DATA_OUT(3*32+31 downto 3*32+8) => open,
BUS_ADDR_OUT(3*16+8 downto 3*16) => sci2_addr,
BUS_ADDR_OUT(3*16+15 downto 3*16+9) => open,
+ BUS_ADDR_OUT(4*16+3 downto 4*16) => soda_addr,
+ BUS_ADDR_OUT(4*16+15 downto 4*16+4) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_TIMEOUT_OUT(2) => open,
BUS_TIMEOUT_OUT(3) => open,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATA_IN(2*32+7 downto 2*32) => sci1_data_out,
+ BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'),
BUS_DATA_IN(3*32+7 downto 3*32) => sci2_data_out,
+ BUS_DATA_IN(3*32+31 downto 3*32+8) => (others => '0'),
+ BUS_DATA_IN(4*32+31 downto 4*32) => soda_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_DATAREADY_IN(2) => sci1_ack,
BUS_DATAREADY_IN(3) => sci2_ack,
+ BUS_DATAREADY_IN(4) => soda_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(2) => sci1_ack,
BUS_WRITE_ACK_IN(3) => sci2_ack,
+ BUS_WRITE_ACK_IN(4) => soda_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(2) => '0',
BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_NO_MORE_DATA_IN(4) => '0',
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
BUS_UNKNOWN_ADDR_IN(3) => '0',
+ BUS_UNKNOWN_ADDR_IN(4) => '0',
STAT_DEBUG => open
);
STAT => open
);
+
+---------------------------------------------------------------------------
+-- SODA
+---------------------------------------------------------------------------
+THE_SODA_HUB: soda_hub
+ port map(
+ SYSCLK => clk_100_i,
+ SODACLK => rx_clock_200,
+ RESET => reset_i,
+ CLEAR => '0',
+ CLK_EN => '1',
+
+ -- SINGLE DUBPLEX UP-LINK TO THE TOP
+ RXUP_DLM_IN => DLM_from_uplink_S,
+ RXUP_DLM_WORD_IN => DLM_WORD_from_uplink_S,
+ TXUP_DLM_OUT => DLM_to_uplink_S,
+ TXUP_DLM_WORD_OUT => DLM_WORD_to_uplink_S,
+ TXUP_DLM_PREVIEW_OUT => open,
+ UPLINK_PHASE_IN => c_PHASE_H,
+
+ -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
+ RXDN_DLM_IN(0) => DLM_from_downlink_S(0),
+ RXDN_DLM_IN(1) => DLM_from_downlink_S(1),
+ RXDN_DLM_IN(2) => DLM_from_downlink_S(2),
+ RXDN_DLM_IN(3) => DLM_from_downlink_S(3),
+ RXDN_DLM_WORD_IN(0) => DLM_WORD_from_downlink_S(0*8+7 downto 0*8),
+ RXDN_DLM_WORD_IN(1) => DLM_WORD_from_downlink_S(1*8+7 downto 1*8),
+ RXDN_DLM_WORD_IN(2) => DLM_WORD_from_downlink_S(2*8+7 downto 2*8),
+ RXDN_DLM_WORD_IN(3) => DLM_WORD_from_downlink_S(3*8+7 downto 3*8),
+ TXDN_DLM_OUT(0) => DLM_to_downlink_S(0),
+ TXDN_DLM_OUT(1) => DLM_to_downlink_S(1),
+ TXDN_DLM_OUT(2) => DLM_to_downlink_S(2),
+ TXDN_DLM_OUT(3) => DLM_to_downlink_S(3),
+ TXDN_DLM_WORD_OUT(0) => DLM_WORD_to_downlink_S(0*8+7 downto 0*8),
+ TXDN_DLM_WORD_OUT(1) => DLM_WORD_to_downlink_S(1*8+7 downto 1*8),
+ TXDN_DLM_WORD_OUT(2) => DLM_WORD_to_downlink_S(2*8+7 downto 2*8),
+ TXDN_DLM_WORD_OUT(3) => DLM_WORD_to_downlink_S(3*8+7 downto 3*8),
+ TXDN_DLM_PREVIEW_OUT => open,
+ DNLINK_PHASE_IN => (others => c_PHASE_H),
+
+ SODA_DATA_IN => soda_data_in,
+ SODA_DATA_OUT => soda_data_out,
+ SODA_ADDR_IN => soda_addr,
+ SODA_READ_IN => soda_read_en,
+ SODA_WRITE_IN => soda_write_en,
+ SODA_ACK_OUT => soda_ack,
+ LEDS_OUT => open,
+ LINK_DEBUG_IN => (others => '0')
+ );
+
---------------------------------------------------------------------------
-- Reboot FPGA
---------------------------------------------------------------------------
PROGRAMN => PROGRAMN
);
-
-
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
LED_ORANGE <= not med_stat_op(10);
LED_RED <= not time_counter(26);
LED_YELLOW <= not med_stat_op(11);
-
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ blink : process (clk_100_i)
+ begin
+ if rising_edge(clk_100_i) then
+ if (time_counter = x"FFFFFFFF") then
+ time_counter <= x"00000000";
+ else
+ time_counter <= time_counter + 1;
+ end if;
+ end if;
+ end process;
+--
gen_LED : for i in 1 to 6 generate
LED_LINKOK(i) <= not med_stat_op(i*16+9);
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
-<ispXCF version="3.4.0">
+<ispXCF version="3.2.0">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <Operation>Fast Program</Operation>
+ <File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit</File>
+ <Operation>Bypass</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20150317.bit</File>
- <FileTime>03/17/15 15:09:57</FileTime>
+ <File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/SODA_source/trb3_periph_SODA_source/trb3_periph_SODA_source_trb3_periph_SODA_source.bit</File>
+ <FileTime>07/24/15 09:45:34</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
- <PreloadLength>1326</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
</Option>
</Device>
<Device>
- <SelectedProg value="FALSE"/>
+ <SelectedProg value="TRUE"/>
<Pos>3</Pos>
<Vendor>Lattice</Vendor>
<Family>LatticeECP3</Family>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
+ <File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit</File>
+ <FileTime>07/30/15 16:40:51</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
+ <PreloadLength>1326</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<OverideUES value="TRUE"/>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>ispVM</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
<AccessMode>JTAG</AccessMode>
</Option>
</Device>
<Device>
- <SelectedProg value="FALSE"/>
+ <SelectedProg value="TRUE"/>
<Pos>4</Pos>
<Vendor>Lattice</Vendor>
<Family>LatticeECP3</Family>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20150317.bit</File>
- <FileTime>03/17/15 13:31:23</FileTime>
+ <File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit</File>
+ <FileTime>07/30/15 16:40:51</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20150318.bit</File>
- <FileTime>03/18/15 13:53:16</FileTime>
- <JedecChecksum>N/A</JedecChecksum>
+ <File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit</File>
+ <FileTime>07/30/15 16:40:51</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed</File>
- <FileTime>04/10/13 09:35:41</FileTime>
+ <File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/trb3/base/clockmanager/CM1_125twice.jed</File>
+ <FileTime>03/26/15 13:13:40</FileTime>
<JedecChecksum>0x1C57</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<Option>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/trb3/base/clockmanager/CM2.jed</File>
- <FileTime>04/10/13 09:35:41</FileTime>
+ <File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/trb3/base/clockmanager/CM2.jed</File>
+ <FileTime>03/26/15 13:13:40</FileTime>
<JedecChecksum>0x18FB</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<Option>
<CableOptions>
<CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd>
+ <USBID>\\?\usb#vid_1134&amp;pid_8001#7&amp;2a838890&amp;0&amp;2#</USBID>
+ <JTAGPinSetting>
+ TRST ABSENT;
+ ISPEN ABSENT;
+ </JTAGPinSetting>
</CableOptions>
</ispXCF>
CH1_RX_FIFO "ENABLED"
CH2_RX_FIFO "ENABLED"
CH3_RX_FIFO "ENABLED"
-CH0_TDRV "0"
-CH1_TDRV "0"
-CH2_TDRV "0"
-CH3_TDRV "0"
+CH0_TDRV "1"
+CH1_TDRV "1"
+CH2_TDRV "1"
+CH3_TDRV "1"
#CH0_TX_FICLK_RATE 200
#CH1_TX_FICLK_RATE 200
#CH2_TX_FICLK_RATE 200
CH2_LOS_THRESHOLD_LO "2"
CH3_LOS_THRESHOLD_LO "2"
PLL_TERM "50"
-PLL_DCC "DC"
-PLL_LOL_SET "0"
+PLL_DCC "AC"
+PLL_LOL_SET "1"
CH0_TX_SB "DISABLED"
CH1_TX_SB "DISABLED"
CH2_TX_SB "DISABLED"
CH2_PCSLBPORTS "DISABLED"
CH3_PCSLBPORTS "DISABLED"
INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
+QD_REFCK2CORE "DISABLED"
--- /dev/null
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH2_PROTOCOL "G8B10B"
+CH0_MODE "DISABLED"
+CH1_MODE "DISABLED"
+CH2_MODE "RXTX"
+CH3_MODE "DISABLED"
+CH2_CDR_SRC "REFCLK_CORE"
+PLL_SRC "REFCLK_CORE"
+TX_DATARATE_RANGE "MEDHIGH"
+CH2_RX_DATARATE_RANGE "MEDHIGH"
+REFCK_MULT "10X"
+#REFCLK_RATE 200
+CH2_RX_DATA_RATE "FULL"
+CH2_TX_DATA_RATE "FULL"
+CH2_TX_DATA_WIDTH "8"
+CH2_RX_DATA_WIDTH "8"
+CH2_TX_FIFO "DISABLED"
+CH2_RX_FIFO "ENABLED"
+CH2_TDRV "0"
+#CH2_TX_FICLK_RATE 200
+#CH2_RXREFCLK_RATE "200"
+#CH2_RX_FICLK_RATE 200
+CH2_TX_PRE "DISABLED"
+CH2_RTERM_TX "50"
+CH2_RX_EQ "DISABLED"
+CH2_RTERM_RX "50"
+CH2_RX_DCC "DC"
+CH2_LOS_THRESHOLD_LO "2"
+PLL_TERM "50"
+PLL_DCC "AC"
+PLL_LOL_SET "0"
+CH2_TX_SB "DISABLED"
+CH2_RX_SB "DISABLED"
+CH2_TX_8B10B "ENABLED"
+CH2_RX_8B10B "ENABLED"
+CH2_COMMA_A "1100000101"
+CH2_COMMA_B "0011111010"
+CH2_COMMA_M "1111111100"
+CH2_RXWA "ENABLED"
+CH2_ILSM "ENABLED"
+CH2_CTC "DISABLED"
+CH2_CC_MATCH4 "0000000000"
+CH2_CC_MATCH_MODE "1"
+CH2_CC_MIN_IPG "3"
+CCHMARK "9"
+CCLMARK "7"
+CH2_SSLB "DISABLED"
+CH2_SPLBPORTS "DISABLED"
+CH2_PCSLBPORTS "DISABLED"
+INT_ALL "DISABLED"
+QD_REFCK2CORE "DISABLED"
+
+
+++ /dev/null
-../trb3/base/linkdesignfiles.sh
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="soda4srcEP" device="LFE3-150EA-8FN672C" default_implementation="soda4srcEP">
- <Options/>
- <Implementation title="soda4srcEP" dir="soda4srcEP" description="soda4srcEP" synthesis="synplify" default_strategy="Strategy1">
- <Options def_top="trb3_periph_ep_soda4source" top="trb3_periph_EP_soda4source"/>
- <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_4source.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_start_of_burst_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_1_125_int.lpc" type="LPC_Module" type_short="LPC">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_1_125_int.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_1_200_int.lpc" type="LPC_Module" type_short="LPC">
- <Options/>
- </Source>
- <Source name="code/ip/sfp_1_200_int.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_4_sync_downstream.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_4_sync_downstream.lpc" type="LPC_Module" type_short="LPC">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_4_sync_downstream.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
- <Source name="code/med_ecp3_sfp_4_SODA.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/cores/pll_in200_out100.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
- <Source name="../trb3/base/cores/pll_in200_out100.lpc" type="LPC_Module" type_short="LPC">
- <Options/>
- </Source>
- <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/trb3_periph_EP_soda4source.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb3_periph_EP_soda4source"/>
- </Source>
- <Source name="soda4srcEP.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- <Source name="soda4srcEP.rvl" type="Reveal" type_short="Reveal">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="soda4srcEP1.sty"/>
-</BaliProject>
+++ /dev/null
-rvl_alias "clk_200_osc" "clk_200_osc";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;
-\r
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-# TEST LINES
-#################################################################
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "MED_ECP3_SODA_QUAD_SOURCE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-#MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 25.000000 ns ;
-MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 25.000000 ns ;
-MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_0" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_1" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_2" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_3" 200.000000 MHz ;
-
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_0" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_1" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_2" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_3" 100.000000 MHz ;
-
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_0" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_1" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_2" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_3" 200.000000 MHz ;
-
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_0" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_1" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_2" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_3" 100.000000 MHz ;
-
-MULTICYCLE TO CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
+++ /dev/null
-rvl_alias "clk_200_osc" "clk_200_osc";
-RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-# SYSCONFIG MCCLK_FREQ = 2.5;
-# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
-# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";
-#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7
-#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9
-#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11
-#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17
-#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27
-#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29
-#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31
-#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
-#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8
-#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10
-#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12
-#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18
-#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28
-#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30
-#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32
-#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38
-#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175
-#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177
-#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179
-#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185
-#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176
-#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178
-#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180
-#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186
-#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-#GSR_NET NET "GSR_N";
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "MED_ECP3_SODA_QUAD_SOURCE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-\r
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 25.000000 ns ;
-MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/SCI_DATA_OUT*" 50.000000 ns ;
-MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-\r
-BLOCK JTAGPATHS ;
-\r
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-\r
+++ /dev/null
-SODA_SOURCE (0xF355)
-
-WRITE_REG:
-
-BE00 soda_cmd_word_S
-BE01 LEDregister_i
-
-READ_REG:
-
-BE00 soda_cmd_word_S
-BE01 super_burst_nr_S
-BE02 calib_register_S
-BE03 LEDregister_i
-
-
-SODA_CLIENT (0xF356)
-
-WRITE_REG:
-
-BE00 LEDregister_i
-
-READ_REG:
-
-BE00 soda_cmd_word_S
-BE01 super_burst_nr_S
-BE02 LEDregister_i
-BE03 Debug_status
-BE04 Debug_RX_count
-BE05 Debug_TX_count
-BE06 Debug_SOS_count
-BE07 Debug_CMD_count
-
-
-
-
-DEBUG_STATUS(31) <= send_link_reset_i when rising_edge(SYSCLK);
-DEBUG_STATUS(30) <= '0';
-DEBUG_STATUS(29) <= internal_make_link_reset_out when rising_edge(SYSCLK);
-DEBUG_STATUS(28) <= '0';
-DEBUG_STATUS(27) <= '0';
-DEBUG_STATUS(26) <= rx_allow;
-DEBUG_STATUS(25) <= tx_allow;
-DEBUG_STATUS(24:20) <= (others => '0');
-DEBUG_STATUS(19:16) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-DEBUG_STATUS(15:3) <= (others => '0');
-DEBUG_STATUS(2) <= CLK_EN;
-DEBUG_STATUS(1) <= CLEAR;
-DEBUG_STATUS(0) <= RESET;
-
------------------------------------------------------------------------------------
-constant K_IDLE : std_logic_vector(7 downto 0) := x"BC";
-constant D_IDLE0 : std_logic_vector(7 downto 0) := x"C5";
-constant D_IDLE1 : std_logic_vector(7 downto 0) := x"50";
-constant K_SOP : std_logic_vector(7 downto 0) := x"FB";
-constant K_EOP : std_logic_vector(7 downto 0) := x"FD";
-constant K_BGN : std_logic_vector(7 downto 0) := x"1C";
-constant K_REQ : std_logic_vector(7 downto 0) := x"7C";
-constant K_RST : std_logic_vector(7 downto 0) := x"FE";
-constant K_DLM : std_logic_vector(7 downto 0) := x"DC";
-
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="soda_client" device="LFE3-150EA-8FN672C" default_implementation="soda_client">
- <Options>
- <Option name="HDL type" value="VHDL"/>
- </Options>
- <Implementation title="soda_client" dir="soda_client" description="soda_client" synthesis="synplify" default_strategy="Strategy1">
- <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
- <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_client.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/med_ecp3_sfp_sync_up.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_sync_upstream.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_sync_upstream.lpc" type="LPC_Module" type_short="LPC">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
- <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb3_periph_sodaclient"/>
- </Source>
- <Source name="code/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
- <Options/>
- </Source>
- <Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- <Source name="soda_client_probe.rvl" type="Reveal" type_short="Reveal">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="soda_client1.sty"/>
-</BaliProject>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="2.0" title="soda_client" device="LFE3-150EA-8FN672C" synthesis="synplify" default_implementation="soda_client">
- <Options>
- <Option name="HDL type" value="VHDL"/>
- </Options>
- <Implementation title="soda_client" dir="soda_client" description="soda_client" default_strategy="Strategy1">
- <Options def_top="trb3_periph_sodasource" top="trb3_periph_sodaclient"/>
- <Source name="source/version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_client.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/tx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb3_periph_sodasource"/>
- </Source>
- <Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="soda_client1.sty"/>
-</BaliProject>
+++ /dev/null
-rvl_alias "rx_full_clk" "rx_full_clk";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ = 20;
-# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
-# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-#LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
-#LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
-#LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
-#LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
-#LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
-#LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
-#LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
-#LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
-#LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
-#LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
-#LOCATE COMP "FPGA5_COMM_10" SITE "V10";
-#LOCATE COMP "FPGA5_COMM_11" SITE "W10";
-#DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-#IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-FREQUENCY NET "rx_full_clk" 200.000000 MHz ;
-FREQUENCY NET "rx_half_clk" 100.000000 MHz ;
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH3_PROTOCOL "G8B10B"
-CH0_MODE "DISABLED"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "RXTX"
-CH3_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH3_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH3_RX_DATA_RATE "FULL"
-CH3_TX_DATA_RATE "FULL"
-CH3_TX_DATA_WIDTH "8"
-CH3_RX_DATA_WIDTH "8"
-CH3_TX_FIFO "DISABLED"
-CH3_RX_FIFO "DISABLED"
-CH3_TDRV "0"
-#CH3_TX_FICLK_RATE 200
-#CH3_RXREFCLK_RATE "200"
-#CH3_RX_FICLK_RATE 200
-CH3_TX_PRE "DISABLED"
-CH3_RTERM_TX "50"
-CH3_RX_EQ "DISABLED"
-CH3_RTERM_RX "50"
-CH3_RX_DCC "DC"
-CH3_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH3_TX_SB "DISABLED"
-CH3_RX_SB "DISABLED"
-CH3_TX_8B10B "ENABLED"
-CH3_RX_8B10B "ENABLED"
-CH3_COMMA_A "1100000101"
-CH3_COMMA_B "0011111010"
-CH3_COMMA_M "1111111100"
-CH3_RXWA "ENABLED"
-CH3_ILSM "ENABLED"
-CH3_CTC "DISABLED"
-CH3_CC_MATCH4 "0000000000"
-CH3_CC_MATCH_MODE "1"
-CH3_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH3_SSLB "DISABLED"
-CH3_SPLBPORTS "DISABLED"
-CH3_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2015-01-08">
- <IP Version="1_5_062609"/>
- <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_client"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2085654093" Name="trb3_periph_sodaclient_LA0" ID="0">
- <Setting>
- <Clock SampleClk="rx_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
- <Capture Mode="0" MinSamplesPerTrig="8"/>
- <Event CntEnable="0" MaxEventCnt="8"/>
- <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_client_LA0_net"/>
- </Setting>
- <Dataset Name="Base">
- <Trace>
- <Sig Type="SIG" Name="the_sync_link/got_link_ready_i"/>
- <Sig Type="SIG" Name="the_sync_link/link_phase_out"/>
- <Bus Name="the_sync_link/rx_data">
- <Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:3"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:4"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:5"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/rx_k"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
- <Bus Name="the_sync_link/rx_dlm_word">
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
- </Bus>
- <Bus Name="the_sync_link/tx_data">
- <Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:3"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:4"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:5"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:6"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/tx_k"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_preview_in"/>
- <Bus Name="the_sync_link/tx_dlm_word">
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/rx_allow_q"/>
- <Bus Name="sfp_los">
- <Sig Type="SIG" Name="sfp_los:1"/>
- <Sig Type="SIG" Name="sfp_los:2"/>
- <Sig Type="SIG" Name="sfp_los:3"/>
- <Sig Type="SIG" Name="sfp_los:4"/>
- <Sig Type="SIG" Name="sfp_los:5"/>
- <Sig Type="SIG" Name="sfp_los:6"/>
- </Bus>
- <Bus Name="the_sync_link/wa_position_rx">
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:0"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:1"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:2"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:3"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:4"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:5"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:6"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:7"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:8"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:9"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:10"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:11"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:12"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:13"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:14"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:15"/>
- </Bus>
- <Sig Type="SIG" Name="clk_100_osc"/>
- <Sig Type="SIG" Name="rx_half_clk"/>
- <Bus Name="the_sync_link/sci_state">
- <Sig Type="SIG" Name="the_sync_link/sci_state:0"/>
- <Sig Type="SIG" Name="the_sync_link/sci_state:1"/>
- <Sig Type="SIG" Name="the_sync_link/sci_state:2"/>
- <Sig Type="SIG" Name="the_sync_link/sci_state:3"/>
- </Bus>
- <Bus Name="the_sync_link/wa_position">
- <Sig Type="SIG" Name="the_sync_link/wa_position:0"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:1"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:2"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:3"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:4"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:5"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:6"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:7"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:8"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:9"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:10"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:11"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:12"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:13"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:14"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:15"/>
- </Bus>
- <Bus Name="the_sync_link/sci_addr_i">
- <Sig Type="SIG" Name="the_sync_link/sci_addr_i:0"/>
- <Sig Type="SIG" Name="the_sync_link/sci_addr_i:1"/>
- <Sig Type="SIG" Name="the_sync_link/sci_addr_i:2"/>
- <Sig Type="SIG" Name="the_sync_link/sci_addr_i:3"/>
- <Sig Type="SIG" Name="the_sync_link/sci_addr_i:4"/>
- <Sig Type="SIG" Name="the_sync_link/sci_addr_i:5"/>
- <Sig Type="SIG" Name="the_sync_link/sci_addr_i:6"/>
- <Sig Type="SIG" Name="the_sync_link/sci_addr_i:7"/>
- <Sig Type="SIG" Name="the_sync_link/sci_addr_i:8"/>
- </Bus>
- <Bus Name="the_sync_link/sci_data_in_i">
- <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:0"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:1"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:2"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:3"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:4"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:5"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:6"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:7"/>
- </Bus>
- <Bus Name="the_sync_link/sci_data_out_i">
- <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:0"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:1"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:2"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:3"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:4"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:5"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:6"/>
- <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/sci_read_i"/>
- <Sig Type="SIG" Name="the_sync_link/sci_write_i"/>
- <Bus Name="the_sync_link/sci_ch_i">
- <Sig Type="SIG" Name="the_sync_link/sci_ch_i:0"/>
- <Sig Type="SIG" Name="the_sync_link/sci_ch_i:1"/>
- <Sig Type="SIG" Name="the_sync_link/sci_ch_i:2"/>
- <Sig Type="SIG" Name="the_sync_link/sci_ch_i:3"/>
- </Bus>
- </Trace>
- <Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_client/start_of_superburst_s,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="a_soda_client/soda_cmd_valid_s,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/watchdog_trigger,"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="general_reset_i,"/>
- <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_sync_link/sci_state[3:0],"/>
- <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
- </Trigger>
- </Dataset>
- </Core>
-</Project>
+++ /dev/null
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- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/wide_adder_17x16.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_ipu_logic.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/trb3_periph_sodahub.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb3_periph_sodahub"/>
- </Source>
- <Source name="code/soda_hub_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
- <Options/>
- </Source>
- <Source name="soda_hub.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- <Source name="soda_hub_probe.rvl" type="Reveal" type_short="Reveal">
- <Options/>
- </Source>
- <Source name="trb3_soda_hub.xcf" type="Programming Project File" type_short="Programming">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="soda_hub1.sty"/>
- <Strategy name="soda_hub" file="soda_hub.sty"/>
-</BaliProject>
+++ /dev/null
-soda_hub_groningen.lpf
\ No newline at end of file
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH3_PROTOCOL "G8B10B"
-CH0_MODE "DISABLED"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "RXTX"
-CH3_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH3_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH3_RX_DATA_RATE "FULL"
-CH3_TX_DATA_RATE "FULL"
-CH3_TX_DATA_WIDTH "8"
-CH3_RX_DATA_WIDTH "8"
-CH3_TX_FIFO "DISABLED"
-CH3_RX_FIFO "DISABLED"
-CH3_TDRV "0"
-#CH3_TX_FICLK_RATE 200
-#CH3_RXREFCLK_RATE "200"
-#CH3_RX_FICLK_RATE 200
-CH3_TX_PRE "DISABLED"
-CH3_RTERM_TX "50"
-CH3_RX_EQ "DISABLED"
-CH3_RTERM_RX "50"
-CH3_RX_DCC "DC"
-CH3_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH3_TX_SB "DISABLED"
-CH3_RX_SB "DISABLED"
-CH3_TX_8B10B "ENABLED"
-CH3_RX_8B10B "ENABLED"
-CH3_COMMA_A "1100000101"
-CH3_COMMA_B "0011111010"
-CH3_COMMA_M "1111111100"
-CH3_RXWA "ENABLED"
-CH3_ILSM "ENABLED"
-CH3_CTC "DISABLED"
-CH3_CC_MATCH4 "0000000000"
-CH3_CC_MATCH_MODE "1"
-CH3_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH3_SSLB "DISABLED"
-CH3_SPLBPORTS "DISABLED"
-CH3_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-rvl_alias "rxup_full_clk" "rxup_full_clk";\r
-BLOCK RESETPATHS ;\r
-BLOCK ASYNCPATHS ;\r
-BLOCK RD_DURING_WR_PATHS ;\r
-BLOCK JTAGPATHS ;\r
-\r
-#################################################################\r
-# Basic Settings\r
-#################################################################\r
-SYSCONFIG MCCLK_FREQ = 20;\r
-# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;\r
-# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;\r
-# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;\r
-\r
-#################################################################\r
-# Clock I/O\r
-#################################################################\r
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;\r
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;\r
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???\r
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;\r
-#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";\r
-#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";\r
-#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";\r
-#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";\r
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!\r
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;\r
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;\r
-\r
-#################################################################\r
-# To central FPGA\r
-#################################################################\r
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;\r
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;\r
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;\r
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;\r
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;\r
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;\r
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;\r
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;\r
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;\r
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;\r
-LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;\r
-LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;\r
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;\r
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-\r
-LOCATE COMP "TEST_LINE_0" SITE "A5" ;\r
-LOCATE COMP "TEST_LINE_1" SITE "A6" ;\r
-LOCATE COMP "TEST_LINE_2" SITE "G8" ;\r
-LOCATE COMP "TEST_LINE_3" SITE "F9" ;\r
-LOCATE COMP "TEST_LINE_4" SITE "D9" ;\r
-LOCATE COMP "TEST_LINE_5" SITE "D10" ;\r
-LOCATE COMP "TEST_LINE_6" SITE "F10" ;\r
-LOCATE COMP "TEST_LINE_7" SITE "E10" ;\r
-LOCATE COMP "TEST_LINE_8" SITE "A8" ;\r
-LOCATE COMP "TEST_LINE_9" SITE "B8" ;\r
-LOCATE COMP "TEST_LINE_10" SITE "G10" ;\r
-LOCATE COMP "TEST_LINE_11" SITE "G9" ;\r
-LOCATE COMP "TEST_LINE_12" SITE "C9" ;\r
-LOCATE COMP "TEST_LINE_13" SITE "C10" ;\r
-LOCATE COMP "TEST_LINE_14" SITE "H10" ;\r
-LOCATE COMP "TEST_LINE_15" SITE "H11" ;\r
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;\r
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;\r
-\r
-#################################################################\r
-# Connection to AddOn\r
-#################################################################\r
-LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1\r
-LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3\r
-LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5\r
-LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7\r
-#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9\r
-#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11\r
-#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13\r
-LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15\r
-LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17\r
-#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19\r
-LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21\r
-LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23\r
-LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25\r
-LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27\r
-#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29\r
-#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31\r
-#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33\r
-LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35\r
-LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2\r
-#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2\r
-LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2\r
-LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4\r
-LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6\r
-LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8\r
-#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10\r
-#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12\r
-#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3\r
-LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3\r
-LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18\r
-#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20\r
-LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22\r
-LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24\r
-LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26\r
-LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28\r
-#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30\r
-#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32\r
-#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34\r
-LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36\r
-LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38\r
-#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40\r
-LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169\r
-LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171\r
-LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173\r
-LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175\r
-#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177\r
-#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179\r
-#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181\r
-LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183\r
-LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185\r
-#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187\r
-LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170\r
-LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172\r
-LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174\r
-LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176\r
-#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178\r
-#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180\r
-#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182\r
-LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184\r
-LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186\r
-#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188\r
-\r
-DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-#################################################################
-# Additional Lines to AddOn\r
-#################################################################\r
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3\r
-#all lines are input only\r
-#line 4/5 go to PLL input\r
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194\r
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196\r
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198\r
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200\r
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69\r
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
-#################################################################\r
-# Flash ROM and Reboot\r
-#################################################################\r
-LOCATE COMP "FLASH_CLK" SITE "B12" ;\r
-LOCATE COMP "FLASH_CS" SITE "E11" ;\r
-LOCATE COMP "FLASH_DIN" SITE "E12" ;\r
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;\r
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;\r
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;\r
-LOCATE COMP "PROGRAMN" SITE "B11" ;\r
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
-#################################################################\r
-# Misc\r
-#################################################################\r
-LOCATE COMP "TEMPSENS" SITE "A13" ;\r
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
-#coding of FPGA number\r
-LOCATE COMP "CODE_LINE_1" SITE "AA20" ;\r
-LOCATE COMP "CODE_LINE_0" SITE "Y21" ;\r
-IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-#terminated differential pair to pads\r
-LOCATE COMP "SUPPL" SITE "C14" ;\r
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################\r
-# LED\r
-#################################################################\r
-LOCATE COMP "LED_GREEN" SITE "F12" ;\r
-LOCATE COMP "LED_ORANGE" SITE "G13" ;\r
-LOCATE COMP "LED_RED" SITE "A15" ;\r
-LOCATE COMP "LED_YELLOW" SITE "A16" ;\r
-DEFINE PORT GROUP "LED_group" "LED*" ;\r
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;\r
-#################################################################\r
-#GSR_NET NET "GSR_N"; \r
-#################################################################\r
-# Locate Serdes and media interfaces\r
-#################################################################\r
-LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
-LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;\r
-\r
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
-#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
-#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only\r
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;\r
-\r
-BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;\r
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";\r
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";\r
-\r
-#UGROUP "SPIlogic" BBOX 20 20\r
-# BLKNAME THE_SPI_RELOAD;\r
-#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ;\r
-\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_0";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_1";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_2";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_3";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_0";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_1";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_2";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_3";\r
-\r
-## IOBUF ALLPORTS ;\r
-USE PRIMARY NET "clk_200_osc" ;\r
-USE PRIMARY NET "clk_100_osc" ;\r
-USE PRIMARY NET "rxup_full_clk" ;\r
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;\r
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;\r
-FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;\r
+++ /dev/null
-rvl_alias "rxup_full_clk" "rxup_full_clk";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???\r
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;\r
-#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";\r
-#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";\r
-#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";\r
-#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";\r
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!\r
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;\r
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;\r
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;\r
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;\r
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;\r
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;\r
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;\r
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;\r
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;\r
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;\r
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;\r
-LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;\r
-LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;\r
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-\r
-LOCATE COMP "TEST_LINE_0" SITE "A5" ;\r
-LOCATE COMP "TEST_LINE_1" SITE "A6" ;\r
-LOCATE COMP "TEST_LINE_2" SITE "G8" ;\r
-LOCATE COMP "TEST_LINE_3" SITE "F9" ;\r
-LOCATE COMP "TEST_LINE_4" SITE "D9" ;\r
-LOCATE COMP "TEST_LINE_5" SITE "D10" ;\r
-LOCATE COMP "TEST_LINE_6" SITE "F10" ;\r
-LOCATE COMP "TEST_LINE_7" SITE "E10" ;\r
-LOCATE COMP "TEST_LINE_8" SITE "A8" ;\r
-LOCATE COMP "TEST_LINE_9" SITE "B8" ;\r
-LOCATE COMP "TEST_LINE_10" SITE "G10" ;\r
-LOCATE COMP "TEST_LINE_11" SITE "G9" ;\r
-LOCATE COMP "TEST_LINE_12" SITE "C9" ;\r
-LOCATE COMP "TEST_LINE_13" SITE "C10" ;\r
-LOCATE COMP "TEST_LINE_14" SITE "H10" ;\r
-LOCATE COMP "TEST_LINE_15" SITE "H11" ;\r
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-\r
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1\r
-LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3\r
-LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5\r
-LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7\r
-#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9\r
-#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11\r
-#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13\r
-LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15\r
-LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17\r
-#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19\r
-LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21\r
-LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23\r
-LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25\r
-LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27\r
-#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29\r
-#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31\r
-#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33\r
-LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35\r
-LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2\r
-#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2\r
-LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2\r
-LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4\r
-LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6\r
-LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8\r
-#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10\r
-#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12\r
-#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3\r
-LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3\r
-LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18
-#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20\r
-LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22\r
-LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24\r
-LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26\r
-LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28\r
-#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30\r
-#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32\r
-#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34\r
-LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36\r
-LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38\r
-#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40\r
-LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169\r
-LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171\r
-LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173\r
-LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175\r
-#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177\r
-#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179\r
-#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181\r
-LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183\r
-LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185\r
-#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187\r
-LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170\r
-LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172\r
-LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174\r
-LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176\r
-#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178\r
-#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180\r
-#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182\r
-LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184\r
-LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186\r
-#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188\r
-\r
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE_1" SITE "AA20" ;\r
-LOCATE COMP "CODE_LINE_0" SITE "Y21" ;\r
-IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-#GSR_NET NET "GSR_N";
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
-#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
-#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only\r
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;
-
-BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";
-
-#UGROUP "SPIlogic" BBOX 20 20\r
-# BLKNAME THE_SPI_RELOAD;\r
-#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ;\r
-\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_0";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_1";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_2";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_3";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_0";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_1";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_2";\r
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_3";\r
-
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;
+++ /dev/null
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2015-03-17">
- <IP Version="1_5_062609"/>
- <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2095246907" Name="trb3_periph_sodahub_LA0" ID="0">
- <Setting>
- <Clock SampleClk="rxup_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="64"/>
- <Capture Mode="0" MinSamplesPerTrig="8"/>
- <Event CntEnable="0" MaxEventCnt="8"/>
- <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_hub_LA0_net"/>
- <DistRAM Disable="0"/>
- </Setting>
- <Dataset Name="Base">
- <Trace>
- <Sig Type="SIG" Name="the_hub_sync_uplink/got_link_ready_i"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
- <Bus Name="the_hub_sync_uplink/rx_data">
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:3"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:4"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:5"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:6"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm"/>
- <Bus Name="the_hub_sync_uplink/rx_dlm_word">
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:7"/>
- </Bus>
- <Bus Name="the_hub_sync_uplink/rx_fsm_state">
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_k"/>
- <Bus Name="the_hub_sync_uplink/tx_data">
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:3"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:4"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:5"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:6"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_preview_in"/>
- <Bus Name="the_hub_sync_uplink/tx_dlm_word">
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:7"/>
- </Bus>
- <Bus Name="the_hub_sync_uplink/tx_fsm_state">
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/sd_los_in"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/sd_txdis_out"/>
- <Bus Name="the_hub_sync_uplink/wa_position_rx">
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:3"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:4"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:5"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:6"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:7"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:8"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:9"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:10"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:11"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:12"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:13"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:14"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:15"/>
- </Bus>
- <Bus Name="the_hub_sync_uplink/wa_position">
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:0"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:1"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:2"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:3"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:4"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:5"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:6"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:7"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:8"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:9"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:10"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:11"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:12"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:13"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:14"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:15"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pll_lol"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pcs_rst"/>
- <Bus Name="sfp_los">
- <Sig Type="SIG" Name="sfp_los:1"/>
- <Sig Type="SIG" Name="sfp_los:2"/>
- <Sig Type="SIG" Name="sfp_los:3"/>
- <Sig Type="SIG" Name="sfp_los:4"/>
- <Sig Type="SIG" Name="sfp_los:5"/>
- <Sig Type="SIG" Name="sfp_los:6"/>
- </Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/watchdog_trigger"/>
- <Bus Name="the_hub_sync_downlink/got_link_ready_i">
- <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/rx_k">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/rx_data[3:0]">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:7"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/rx_dlm">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/rx_dlm_word[3:0]">
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:7"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_k">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_data[3:0]">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:7"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_dlm">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:3"/>
- </Bus>
- <Bus Name="the_hub_sync_downlink/tx_dlm_word[3:0]">
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:7"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:0"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:1"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:2"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:3"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:4"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:5"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:6"/>
- <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:7"/>
- </Bus>
- </Trace>
- <Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_hub/start_of_superburst_s,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="a_soda_hub/soda_cmd_valid_s,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="the_hub_sync_uplink/watchdog_trigger,"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="the_hub_sync_uplink/the_rx_fsm/reset_timer2,"/>
- <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_hub_sync_uplink/the_rx_fsm/state_out[3:0],"/>
- <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
- </Trigger>
- </Dataset>
- </Core>
-</Project>
+++ /dev/null
-The place for diamond projects
+++ /dev/null
-The place for the simulator projects.
+++ /dev/null
--w
--i 15
--l 5
--n 1
--y
--s 12
--t 23
--c 1
--e 2
-#-g guidefile.ncd
--m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
+++ /dev/null
-
-# implementation: "workdir"
-impl -add workdir -type fpga
-
-# device options
-set_option -technology LATTICE-ECP3
-set_option -part LFE3_150EA
-set_option -package FN672C
-set_option -speed_grade -8
-set_option -part_companion ""
-
-# compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
-set_option -top_module "trb3_periph_sodaslave"
-set_option -resource_sharing true
-
-# map options
-set_option -frequency 200
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-#set_option -force_gsr
-set_option -force_gsr false
-set_option -fixgatedclocks false #3
-set_option -fixgeneratedclocks false #3
-set_option -compiler_compatible true
-
-
-# simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 1
-
-# automatic place and route (vendor) options
-set_option -write_apr_constraint 0
-
-# set result format/file last
-project -result_format "edif"
-project -result_file "workdir/trb3_periph_sodaslave.edf"
-
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-impl -active "workdir"
-
-####################
-
-
-
-#add_file options
-
-add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib "work" "../../trb3/base/trb3_components.vhd"
-
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic.vhd"
-
-
-add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
-
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
-add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
-
-
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
-
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
-
-add_file -vhdl -lib "work" "../../trb3/base/cores/pll_in200_out100.vhd"
-
-
-
-
-add_file -vhdl -lib "work" "trb3_periph_sodaslave.vhd"
-
+++ /dev/null
---No serdes connection to central FPGA, only one synchronous input link on one SFP of the SFP-AddOn
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodaslave is
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_INTERFACES : integer := 1
- );
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
- --Trigger
- --TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
- --TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
- --Serdes Clocks - do not use
- --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
- --CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
-
- --serdes I/O - connect as you like, no real use
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
-
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- --SFP_MOD1 : inout std_logic_vector(6 downto 1);
- --SFP_MOD2 : inout std_logic_vector(6 downto 1);
- --SFP_RATESEL : out std_logic_vector(6 downto 1);
- --SFP_TXFAULT : in std_logic_vector(6 downto 1);
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
-
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
-
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of LED_LINKOK : signal is false;
- attribute syn_useioff of LED_TX : signal is false;
- attribute syn_useioff of LED_RX : signal is false;
- attribute syn_useioff of SFP_MOD0 : signal is false;
- attribute syn_useioff of SFP_TXDIS : signal is false;
- attribute syn_useioff of SFP_LOS : signal is false;
- attribute syn_useioff of TEST_LINE : signal is false;
-
- --important signals _with_ IO-FF
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_sodaslave_arch of trb3_periph_sodaslave is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-
- --Clock / Reset
- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
--- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- signal clk_sys_internal : std_logic;
- signal clk_raw_internal : std_logic;
- signal rx_clock_half : std_logic;
- signal rx_clock_full : std_logic;
- signal clk_tdc : std_logic;
- signal time_counter, time_counter2 : unsigned(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- --media interface
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sci1_nack : std_logic;
-
-
- signal soda_rx_clock_half : std_logic;
- signal soda_rx_clock_full : std_logic;
- signal tx_dlm_i : std_logic;
- signal rx_dlm_i : std_logic;
- signal tx_dlm_word : std_logic_vector(7 downto 0);
- signal rx_dlm_word : std_logic_vector(7 downto 0);
- signal send_net_reset : std_logic;
- signal make_reset : std_logic;
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
- send_net_reset <= med_stat_op(15);
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_sys_i, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => make_reset, -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
-make_reset <= med_stat_op(13); -- or med_stat_op(1) or med_stat_op(0);
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_sys_internal,
- CLKOK => clk_raw_internal,
- LOCK => pll_lock
- );
-end generate;
-
-gen_125 : if USE_125_MHZ = c_YES generate
- clk_sys_internal <= CLK_GPLL_LEFT;
- clk_raw_internal <= CLK_GPLL_LEFT;
-end generate;
-
-gen_sync_clocks : if SYNC_MODE = c_YES generate
- clk_sys_i <= rx_clock_half;
--- clk_200_i <= rx_clock_full;
-end generate;
-
-gen_local_clocks : if SYNC_MODE = c_NO generate
- clk_sys_i <= clk_sys_internal;
--- clk_200_i <= clk_raw_internal;
-end generate;
-
-
--- ---------------------------------------------------------------------------
--- -- The TrbNet media interface (to other FPGA)
--- ---------------------------------------------------------------------------
--- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
--- generic map(
--- SERDES_NUM => 1, --number of serdes in quad
--- EXT_CLOCK => c_NO, --use internal clock
--- USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
--- USE_125_MHZ => USE_125_MHZ,
--- USE_CTC => c_NO,
--- USE_SLAVE => SYNC_MODE
--- )
--- port map(
--- CLK => clk_raw_internal,
--- SYSCLK => clk_sys_i,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- CLK_EN => '1',
--- --Internal Connection
--- MED_DATA_IN => med_data_out(15 downto 0),
--- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
--- MED_DATAREADY_IN => med_dataready_out(0),
--- MED_READ_OUT => med_read_in(0),
--- MED_DATA_OUT => med_data_in(15 downto 0),
--- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
--- MED_DATAREADY_OUT => med_dataready_in(0),
--- MED_READ_IN => med_read_out(0),
--- REFCLK2CORE_OUT => open,
--- CLK_RX_HALF_OUT => rx_clock_half,
--- CLK_RX_FULL_OUT => rx_clock_full,
---
--- --SFP Connection
--- SD_RXD_P_IN => SERDES_ADDON_RX(2),
--- SD_RXD_N_IN => SERDES_ADDON_RX(3),
--- SD_TXD_P_OUT => SERDES_ADDON_TX(2),
--- SD_TXD_N_OUT => SERDES_ADDON_TX(3),
--- SD_REFCLK_P_IN => '0',
--- SD_REFCLK_N_IN => '0',
--- SD_PRSNT_N_IN => FPGA5_COMM(0),
--- SD_LOS_IN => FPGA5_COMM(0),
--- SD_TXDIS_OUT => FPGA5_COMM(2),
---
--- SCI_DATA_IN => sci1_data_in,
--- SCI_DATA_OUT => sci1_data_out,
--- SCI_ADDR => sci1_addr,
--- SCI_READ => sci1_read,
--- SCI_WRITE => sci1_write,
--- SCI_ACK => sci1_ack,
--- -- Status and control port
--- STAT_OP => med_stat_op(15 downto 0),
--- CTRL_OP => med_ctrl_op(15 downto 0),
--- STAT_DEBUG => med_stat_debug(63 downto 0),
--- CTRL_DEBUG => (others => '0')
--- );
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"45",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"9100b000",
- REGIO_INIT_ADDRESS => x"f351",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 9, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 256,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 256
- )
- port map(
- CLK => clk_sys_i,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out(0),
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in(0),
- MED_DATAREADY_IN => med_dataready_in(0),
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out(0),
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => '0',
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => open,
- LVL1_VALID_TIMING_TRG_OUT => open,
- LVL1_VALID_NOTIMING_TRG_OUT => open,
- LVL1_INVALID_TRG_OUT => open,
-
- LVL1_TRG_TYPE_OUT => open,
- LVL1_TRG_NUMBER_OUT => open,
- LVL1_TRG_CODE_OUT => open,
- LVL1_TRG_INFORMATION_OUT => open,
- LVL1_INT_TRG_NUMBER_OUT => open,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => open,
- TRG_TIMEOUT_DETECTED_OUT => open,
- TRG_SPURIOUS_TRG_OUT => open,
- TRG_MISSING_TMG_TRG_OUT => open,
- TRG_SPIKE_DETECTED_OUT => open,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => '1',
- FEE_TRG_STATUSBITS_IN => (others => '0'),
- FEE_DATA_IN => (others => '0'),
- FEE_DATA_WRITE_IN(0) => '0',
- FEE_DATA_FINISHED_IN(0) => '1',
- FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 2,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, others => 0)
- )
- port map(
- CLK => clk_sys_i,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
-
-
- --SCI soda uplink Media Interface
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => sci1_nack,
-
- STAT_DEBUG => open
- );
-
-
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
- port map(
- CLK_IN => clk_sys_i,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
-
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------
-
-THE_SODA_INPUT : med_ecp3_sfp_sync
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_YES
- )
- port map(
- CLK => clk_raw_internal,
- SYSCLK => clk_sys_i,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection for TrbNet data
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- CLK_RX_HALF_OUT => soda_rx_clock_half,
- CLK_RX_FULL_OUT => soda_rx_clock_full,
-
- RX_DLM => rx_dlm_i,
- RX_DLM_WORD => rx_dlm_word,
- TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(0),
- SD_RXD_N_IN => SERDES_ADDON_RX(1),
- SD_TXD_P_OUT => SERDES_ADDON_TX(0),
- SD_TXD_N_OUT => SERDES_ADDON_TX(1),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => SFP_TXDIS(1),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- SCI_NACK => sci1_nack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => (others => '0')
- );
-
-
----------------------------------------------------------------------------
--- The Soda Slave
----------------------------------------------------------------------------
- tx_dlm_i <= '0';
- tx_dlm_word <= x"00";
-
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
- LED_YELLOW <= '1';
- LED_GREEN <= not med_stat_op(9);
- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
-
- LED_LINKOK(1) <= not med_stat_op(9); --link established
- LED_TX(1) <= not (med_stat_op(10) or med_stat_op(11)); --data RX or TX
- LED_RX(1) <= not med_stat_op(12); --DLM RX
-
- LED_LINKOK(6 downto 2) <= "11111";
- LED_TX(6 downto 2) <= "11111";
- LED_RX(6 downto 2) <= "11111";
-
- --no link to central FPGA
- FPGA5_COMM(3) <= '0';
- FPGA5_COMM(2) <= '0';
-
-
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------
- TEST_LINE(15 downto 0) <= med_stat_debug(15 downto 0);
-
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- process
- begin
- wait until rising_edge(clk_sys_internal);
- time_counter <= time_counter + 1;
- end process;
-
-
-
-
-end architecture;
+++ /dev/null
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-
-#################################################################
-# Basic Settings
-#################################################################
-
- SYSCONFIG MCCLK_FREQ = 20;
-
- FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
- FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
- FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
- FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-
-#################################################################
-# Reset Nets
-#################################################################
-GSR_NET NET "GSR_N";
-
-
-
-
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-
-LOCATE COMP "THE_SODA_INPUT/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-
-REGION "MEDIA_UPLINK" "R90C95D" 13 25;
-REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
-REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;
-REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE;
-
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
-LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-LOCATE UGROUP "THE_SODA_INPUT/media_interface_group" REGION "MEDIA_DOWNLINK" ;
-
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_INPUT/SCI_DATA_OUT*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_INPUT/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_SODA_INPUT/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_INPUT/wa_pos*" 20 ns;
-
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-
+++ /dev/null
-*
-
-!*txt
-!pmi*ngo
-!tsmac*ngo
-!sgm*ngo
-!.gitignore
-
-run_options.txt
-
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn208256208256.ngo
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn96649664.ngo
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_125_0.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ngo
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35.ngo
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="soda_source" device="LFE3-150EA-8FN672C" default_implementation="soda_source">
- <Options>
- <Option name="HDL type" value="VHDL"/>
- </Options>
- <Implementation title="soda_source" dir="soda_source" description="soda_source" synthesis="synplify" default_strategy="Strategy1">
- <Options def_top="trb3_periph_sodasource" top="trb3_periph_sodasource"/>
- <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_source.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_start_of_burst_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_clockscaler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
- <Options/>
- </Source>
- <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/med_ecp3_sfp_sync_down.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_cmd_window_generator.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_sync_source_downstream.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_sync_source_downstream.lpc" type="LPC_Module" type_short="LPC">
- <Options/>
- </Source>
- <Source name="code/ip/serdes_sync_source_downstream.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
- <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb3_periph_sodasource"/>
- </Source>
- <Source name="code/soda_source_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
- <Options/>
- </Source>
- <Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
- <Options/>
- </Source>
- <Source name="soda_source_probe.rvl" type="Reveal" type_short="Reveal">
- <Options/>
- </Source>
- <Source name="trb3_soda_source.xcf" type="Programming Project File" type_short="Programming">
- <Options/>
- </Source>
- </Implementation>
- <Strategy name="Strategy1" file="soda_source1.sty"/>
-</BaliProject>
+++ /dev/null
-soda_source_groningen.lpf
\ No newline at end of file
+++ /dev/null
-#!/bin/sh -x
-cd /usr/local/diamond/2.1_x64/bin/lin64
-export bindir=`pwd`
-
-#export bindirs=/usr/local/diamond/2.1_x64/bin/lin64
-. /usr/local/diamond/2.1_x64/bin/lin64/diamond_env
-
-cd /local/lemmens/lattice/soda/soda_source
-exec ./compile_periph_kvi.pl
+++ /dev/null
-#!/usr/bin/perl -W
-use Data::Dumper;
-use warnings;
-use strict;
-
-
-
-
-###################################################################################
-#Settings for this project
-my $TOPNAME = "trb3_periph_sodasource"; #Name of top-level entity
-my $PRJNAME = "soda_source"; #Name of the project
-my $lattice_path = '/usr/local/diamond/2.1_x64';
-my $synplify_path = '/usr/local/diamond/2.1_x64';
-my $lm_license_file_for_synplify = "27031\@kvivs17.kvi.nl";
-#my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
-my $lm_license_file_for_par = "27031\@kvivs17.kvi.nl";
-###################################################################################
-
-
-use FileHandle;
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-
-my $FAMILYNAME="LatticeECP3";
-my $DEVICENAME="LFE3-150EA";
-my $PACKAGE="FPBGA672";
-my $SPEEDGRADE="8";
-
-
-#create full lpf file
-system("cp ../../trb3/base/trb3_periph_hub.lpf workdir/$TOPNAME.lpf");
-system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
-
-
-#set -e
-#set -o errexit
-
-#generate timestamp
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := $t;
-
-end package version;
-EOF
-$fh->close;
-
-system("env| grep LM_");
-my $r = "";
-
-## timestamp to remember compiletime
-my $c="$synplify_path/bin/lin64/synpwrap -prj $PRJNAME"."_syn.prj"; ##$TOPNAME.prj";
-$r=execute($c, "do_not_exit" );
-
-
-chdir "workdir";
-##$fh = new FileHandle("<$TOPNAME".".srr");
-$fh = new FileHandle("../$PRJNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-
-
-foreach (@a)
-{
- if(/\@E:/)
- {
- print "\n";
- $c="cat $PRJNAME.srr | grep \"\@E\"";
- system($c);
- print "\n\n";
- exit 129;
- }
-}
-
-
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-
-$c=qq| $lattice_path/ispfpga/bin/lin64/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "../$PRJNAME.edn" "$PRJNAME.ngo" |;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate -t "$PRJNAME.tcy" -w "$PRJNAME.ngo" -m "$PRJNAME.ngo" "$PRJNAME.ngx"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$PRJNAME.ngo" "$PRJNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-system("mv $TOPNAME.ncd guidefile.ncd");
-# $c=qq|$lattice_path/ispfpga/bin/lin/map -g guidefile.ncd -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-$c=qq|$lattice_path/ispfpga/bin/lin64/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-
-#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|$lattice_path/ispfpga/bin/lin64/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# IOR IO Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin64/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-#execute($c);
-
-# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin64/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/ltxt2ptxt $TOPNAME.ncd|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-chdir "..";
-
-exit;
-
-sub execute {
- my ($c, $op) = @_;
- #print "option: $op \n";
- $op = "" if(!$op);
- print "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
- }
-
- return $r;
-
-}
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL "G8B10B"
-CH0_MODE "RXTX"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH0_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH0_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH0_RX_DATA_RATE "FULL"
-CH0_TX_DATA_RATE "FULL"
-CH0_TX_DATA_WIDTH "8"
-CH0_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "DISABLED"
-CH0_RX_FIFO "ENABLED"
-CH0_TDRV "0"
-#CH0_TX_FICLK_RATE 200
-#CH0_RXREFCLK_RATE "200"
-#CH0_RX_FICLK_RATE 200
-CH0_TX_PRE "DISABLED"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLED"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "DC"
-CH0_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "DISABLED"
-CH0_RX_SB "DISABLED"
-CH0_TX_8B10B "ENABLED"
-CH0_RX_8B10B "ENABLED"
-CH0_COMMA_A "1100000101"
-CH0_COMMA_B "0011111010"
-CH0_COMMA_M "1111111100"
-CH0_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH0_CTC "DISABLED"
-CH0_CC_MATCH4 "0100011100"
-CH0_CC_MATCH_MODE "1"
-CH0_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH0_SSLB "DISABLED"
-CH0_SPLBPORTS "DISABLED"
-CH0_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-The place for the simulator projects.
+++ /dev/null
--w
--i 15
--l 5
--n 1
--y
--s 12
--t 24
--c 1
--e 2
-#-g guidefile.ncd
--m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodasource is
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_INTERFACES : integer := 2
- );
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
- --Trigger
- --TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
- --TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
- --Serdes Clocks - do not use
- --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
- --CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
-
- --serdes I/O - connect as you like, no real use
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
-
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- --SFP_MOD1 : inout std_logic_vector(6 downto 1);
- --SFP_MOD2 : inout std_logic_vector(6 downto 1);
- --SFP_RATESEL : out std_logic_vector(6 downto 1);
- --SFP_TXFAULT : in std_logic_vector(6 downto 1);
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
-
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
-
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of LED_LINKOK : signal is false;
- attribute syn_useioff of LED_TX : signal is false;
- attribute syn_useioff of LED_RX : signal is false;
- attribute syn_useioff of SFP_MOD0 : signal is false;
- attribute syn_useioff of SFP_TXDIS : signal is false;
- attribute syn_useioff of SFP_LOS : signal is false;
- attribute syn_useioff of TEST_LINE : signal is false;
-
- --important signals _with_ IO-FF
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-
- --Clock / Reset
- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
--- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- signal clk_sys_internal : std_logic;
- signal clk_raw_internal : std_logic;
- signal rx_clock_half : std_logic;
- signal rx_clock_full : std_logic;
- signal clk_tdc : std_logic;
- signal time_counter, time_counter2 : unsigned(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sci2_ack : std_logic;
- signal sci2_nack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
-
- --TDC
- signal hit_in_i : std_logic_vector(63 downto 0);
-
- signal soda_rx_clock_half : std_logic;
- signal soda_rx_clock_full : std_logic;
- signal tx_dlm_i : std_logic;
- signal rx_dlm_i : std_logic;
- signal tx_dlm_word : std_logic_vector(7 downto 0);
- signal rx_dlm_word : std_logic_vector(7 downto 0);
-\r
- --SODA
- signal rst_S : std_logic;
- signal clk_S : std_logic;
- signal enable_S : std_logic := '0';
- signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0');
- signal soda_cmd_strobe_S : std_logic := '0';
- signal SOS_S : std_logic := '0';
- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
- signal SOB_S : std_logic := '0';
- signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
- signal dlm_valid_S : std_logic;
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_sys_i, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_sys_internal,
- CLKOK => clk_raw_internal,
- LOCK => pll_lock
- );
-end generate;
-
-gen_125 : if USE_125_MHZ = c_YES generate
- clk_sys_internal <= CLK_GPLL_LEFT;
- clk_raw_internal <= CLK_GPLL_LEFT;
-end generate;
-
-gen_sync_clocks : if SYNC_MODE = c_YES generate
- clk_sys_i <= rx_clock_half;
--- clk_200_i <= rx_clock_full;
-end generate;
-
-gen_local_clocks : if SYNC_MODE = c_NO generate
- clk_sys_i <= clk_sys_internal;
--- clk_200_i <= clk_raw_internal;
-end generate;
-
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
- USE_125_MHZ => USE_125_MHZ,
- USE_CTC => c_NO,
- USE_SLAVE => SYNC_MODE
- )
- port map(
- CLK => clk_raw_internal,
- SYSCLK => clk_sys_i,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- REFCLK2CORE_OUT => open,
- CLK_RX_HALF_OUT => rx_clock_half,
- CLK_RX_FULL_OUT => rx_clock_full,
-
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(2),
- SD_RXD_N_IN => SERDES_ADDON_RX(3),
- SD_TXD_P_OUT => SERDES_ADDON_TX(2),
- SD_TXD_N_OUT => SERDES_ADDON_TX(3),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => FPGA5_COMM(0),
- SD_LOS_IN => FPGA5_COMM(0),
- SD_TXDIS_OUT => FPGA5_COMM(2),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => (others => '0')
- );
-
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
--- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
--- generic map(
--- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
--- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
--- ADDRESS_MASK => x"FFFF",
--- BROADCAST_BITMASK => x"FF",
--- BROADCAST_SPECIAL_ADDR => x"45",
--- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
--- REGIO_HARDWARE_VERSION => x"91000000",
--- REGIO_INIT_ADDRESS => x"f306",
--- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
--- CLOCK_FREQUENCY => 100,
--- TIMING_TRIGGER_RAW => c_YES,
--- --Configure data handler
--- DATA_INTERFACE_NUMBER => 1,
--- DATA_BUFFER_DEPTH => 9, --13
--- DATA_BUFFER_WIDTH => 32,
--- DATA_BUFFER_FULL_THRESH => 256,
--- TRG_RELEASE_AFTER_DATA => c_YES,
--- HEADER_BUFFER_DEPTH => 9,
--- HEADER_BUFFER_FULL_THRESH => 256
--- )
--- port map(
--- CLK => clk_sys_i,
--- RESET => reset_i,
--- CLK_EN => '1',
--- MED_DATAREADY_OUT => med_dataready_out,
--- MED_DATA_OUT => med_data_out,
--- MED_PACKET_NUM_OUT => med_packet_num_out,
--- MED_READ_IN => med_read_in,
--- MED_DATAREADY_IN => med_dataready_in,
--- MED_DATA_IN => med_data_in,
--- MED_PACKET_NUM_IN => med_packet_num_in,
--- MED_READ_OUT => med_read_out,
--- MED_STAT_OP_IN => med_stat_op,
--- MED_CTRL_OP_OUT => med_ctrl_op,
---
--- --Timing trigger in
--- TRG_TIMING_TRG_RECEIVED_IN => '0',
--- --LVL1 trigger to FEE
--- LVL1_TRG_DATA_VALID_OUT => open,
--- LVL1_VALID_TIMING_TRG_OUT => open,
--- LVL1_VALID_NOTIMING_TRG_OUT => open,
--- LVL1_INVALID_TRG_OUT => open,
---
--- LVL1_TRG_TYPE_OUT => open,
--- LVL1_TRG_NUMBER_OUT => open,
--- LVL1_TRG_CODE_OUT => open,
--- LVL1_TRG_INFORMATION_OUT => open,
--- LVL1_INT_TRG_NUMBER_OUT => open,
---
--- --Information about trigger handler errors
--- TRG_MULTIPLE_TRG_OUT => open,
--- TRG_TIMEOUT_DETECTED_OUT => open,
--- TRG_SPURIOUS_TRG_OUT => open,
--- TRG_MISSING_TMG_TRG_OUT => open,
--- TRG_SPIKE_DETECTED_OUT => open,
---
--- --Response from FEE
--- FEE_TRG_RELEASE_IN(0) => '1',
--- FEE_TRG_STATUSBITS_IN => (others => '0'),
--- FEE_DATA_IN => (others => '0'),
--- FEE_DATA_WRITE_IN(0) => '0',
--- FEE_DATA_FINISHED_IN(0) => '1',
--- FEE_DATA_ALMOST_FULL_OUT(0) => open,
---
--- -- Slow Control Data Port
--- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
--- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
--- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
--- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
--- REGIO_STAT_REG_IN => stat_reg, --start 0x80
--- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
--- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
--- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
--- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
--- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
---
--- BUS_ADDR_OUT => regio_addr_out,
--- BUS_READ_ENABLE_OUT => regio_read_enable_out,
--- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
--- BUS_DATA_OUT => regio_data_out,
--- BUS_DATA_IN => regio_data_in,
--- BUS_DATAREADY_IN => regio_dataready_in,
--- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
--- BUS_WRITE_ACK_IN => regio_write_ack_in,
--- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
--- BUS_TIMEOUT_OUT => regio_timeout_out,
--- ONEWIRE_INOUT => TEMPSENS,
--- ONEWIRE_MONITOR_OUT => open,
---
--- TIME_GLOBAL_OUT => global_time,
--- TIME_LOCAL_OUT => local_time,
--- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
--- TIME_TICKS_OUT => timer_ticks,
---
--- STAT_DEBUG_IPU => open,
--- STAT_DEBUG_1 => open,
--- STAT_DEBUG_2 => open,
--- STAT_DEBUG_DATA_HANDLER_OUT => open,
--- STAT_DEBUG_IPU_HANDLER_OUT => open,
--- STAT_TRIGGER_OUT => open,
--- CTRL_MPLEX => (others => '0'),
--- IOBUF_CTRL_GEN => (others => '0'),
--- STAT_ONEWIRE => open,
--- STAT_ADDR_DEBUG => open,
--- DEBUG_LVL1_HANDLER_OUT => open
--- );
-
-
----------------------------------------------------------------------------
--- Hub
----------------------------------------------------------------------------
-
-THE_HUB : trb_net16_hub_base
- generic map (
- HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),
- IBUF_SECURE_MODE => c_YES,
- MII_NUMBER => NUM_INTERFACES,
- MII_IS_UPLINK => (0 => 1, others => 0),
- MII_IS_DOWNLINK => (0 => 0, others => 1),
- MII_IS_UPLINK_ONLY=> (0 => 1, others => 0),
- INT_NUMBER => 0,
- USE_ONEWIRE => c_YES,
- COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
--- COMPILE_TIME => VERSION_NUMBER_TIME,
- HARDWARE_VERSION => x"91003200",
- INIT_ENDPOINT_ID => x"0000",
- INIT_ADDRESS => x"F355",
- USE_VAR_ENDPOINT_ID => c_YES,
- BROADCAST_SPECIAL_ADDR => x"45",
- CLOCK_FREQUENCY => CLOCK_FREQUENCY
- )
- port map (
- CLK => clk_sys_i,
- RESET => reset_i,
- CLK_EN => '1',
-
- --Media interfacces
- MED_DATAREADY_OUT(NUM_INTERFACES*1-1 downto 0) => med_dataready_out,
- MED_DATA_OUT(NUM_INTERFACES*16-1 downto 0) => med_data_out,
- MED_PACKET_NUM_OUT(NUM_INTERFACES*3-1 downto 0) => med_packet_num_out,
- MED_READ_IN(NUM_INTERFACES*1-1 downto 0) => med_read_in,
- MED_DATAREADY_IN(NUM_INTERFACES*1-1 downto 0) => med_dataready_in,
- MED_DATA_IN(NUM_INTERFACES*16-1 downto 0) => med_data_in,
- MED_PACKET_NUM_IN(NUM_INTERFACES*3-1 downto 0) => med_packet_num_in,
- MED_READ_OUT(NUM_INTERFACES*1-1 downto 0) => med_read_out,
- MED_STAT_OP(NUM_INTERFACES*16-1 downto 0) => med_stat_op,
- MED_CTRL_OP(NUM_INTERFACES*16-1 downto 0) => med_ctrl_op,
-
- COMMON_STAT_REGS => common_stat_reg,
- COMMON_CTRL_REGS => common_ctrl_reg,
- MY_ADDRESS_OUT => open,
- --REGIO INTERFACE
- REGIO_ADDR_OUT => regio_addr_out,
- REGIO_READ_ENABLE_OUT => regio_read_enable_out,
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
- REGIO_DATA_OUT => regio_data_out,
- REGIO_DATA_IN => regio_data_in,
- REGIO_DATAREADY_IN => regio_dataready_in,
- REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
- REGIO_WRITE_ACK_IN => regio_write_ack_in,
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- REGIO_TIMEOUT_OUT => regio_timeout_out,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
- ONEWIRE => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
- --Status ports (for debugging)
- MPLEX_CTRL => (others => '0'),
- CTRL_DEBUG => (others => '0'),
- STAT_DEBUG => open
- );
-
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, others => 0)
- )
- port map(
- CLK => clk_sys_i,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
-
-
- --SCI first Media Interface
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- --SCI soda test Media Interface
- BUS_READ_ENABLE_OUT(2) => sci2_read,
- BUS_WRITE_ENABLE_OUT(2) => sci2_write,
- BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
- BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
- BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
- BUS_DATAREADY_IN(2) => sci2_ack,
- BUS_WRITE_ACK_IN(2) => sci2_ack,
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => sci2_nack,
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
- port map(
- CLK_IN => clk_sys_i,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
-
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------
-
-THE_SODA_SOURCE : entity work.med_ecp3_sfp_sync
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_NO
- )
- port map(
- CLK => clk_raw_internal, --clk_200_i,
- SYSCLK => clk_sys_i,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => med_data_out(31 downto 16),
- MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),
- MED_DATAREADY_IN => med_dataready_out(1),
- MED_READ_OUT => med_read_in(1),
- MED_DATA_OUT => med_data_in(31 downto 16),
- MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
- MED_DATAREADY_OUT => med_dataready_in(1),
- MED_READ_IN => med_read_out(1),
- CLK_RX_HALF_OUT => soda_rx_clock_half,
- CLK_RX_FULL_OUT => soda_rx_clock_full,
-
- RX_DLM => rx_dlm_i,
- RX_DLM_WORD => rx_dlm_word,
- TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(0),
- SD_RXD_N_IN => SERDES_ADDON_RX(1),
- SD_TXD_P_OUT => SERDES_ADDON_TX(0),
- SD_TXD_N_OUT => SERDES_ADDON_TX(1),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => SFP_TXDIS(1),
-
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
- SCI_NACK => sci2_nack,
- -- Status and control port
- STAT_OP => med_stat_op(31 downto 16),
- CTRL_OP => med_ctrl_op(31 downto 16),
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-
-
----------------------------------------------------------------------------
--- The Soda Source
----------------------------------------------------------------------------
- tx_dlm_i <= '0';
- tx_dlm_word <= x"00";\r
-
- \r
- superburst_gen : super_burst_generator
- generic map(BURST_COUNT => 16)
- port map(
- SYSCLK => clk_sys_i, --clk_S,
- RESET => reset_i, --rst_S,
- CLEAR => '0',
- CLK_EN => '0',
- --Internal Connection
- SODA_BURST_PULSE_IN => SOB_S,
- START_OF_SUPERBURST => SOS_S,
- SUPER_BURST_NR_OUT => super_burst_nr_S
- );
-
- packet_builder : soda_packet_builder
- port map(
- SYSCLK => clk_sys_i, --clk_S,
- RESET => reset_i, --rst_S,
- CLEAR => '0',
- CLK_EN => '0',
- --Internal Connection
- SODA_CMD_STROBE_IN => soda_cmd_strobe_S,
- START_OF_SUPERBURST => SOS_S,
- SUPER_BURST_NR_IN => super_burst_nr_S,
- SODA_CMD_WORD_IN => soda_cmd_word_S,
- TX_DLM_OUT => dlm_valid_S,
- TX_DLM_WORD_OUT => dlm_word_S
-
- );
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
- LED_YELLOW <= '1';
- LED_GREEN <= not med_stat_op(9);
- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------
--- TEST_LINE(15 downto 0) <= (others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- process
- begin
- wait until rising_edge(clk_sys_internal);
- time_counter <= time_counter + 1;
- end process;
-
-
-
-
-end architecture;
+++ /dev/null
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-
-#################################################################
-# Basic Settings
-#################################################################
-
- SYSCONFIG MCCLK_FREQ = 20;
-
- FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
- FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
- FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
- FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-
-#################################################################
-# Reset Nets
-#################################################################
-GSR_NET NET "GSR_N";
-
-
-
-
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-
-LOCATE COMP "THE_SODA_SOURCE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-
-REGION "MEDIA_UPLINK" "R90C95D" 13 25;
-REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
-REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;
-REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE;
-
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
-LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;
-
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/SCI_DATA_OUT*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_SODA_SOURCE/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns;
-
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-
+++ /dev/null
-*
-
-!*txt
-!pmi*ngo
-!tsmac*ngo
-!sgm*ngo
-!.gitignore
-
-run_options.txt
-
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn208256208256.ngo
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn96649664.ngo
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_125_0.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ngo
\ No newline at end of file
+++ /dev/null
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35.ngo
\ No newline at end of file
+++ /dev/null
-rvl_alias "clk_100_osc" "clk_100_osc";
-RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";
-#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE_0" SITE "A5" ;
-LOCATE COMP "TEST_LINE_1" SITE "A6" ;
-LOCATE COMP "TEST_LINE_2" SITE "G8" ;
-LOCATE COMP "TEST_LINE_3" SITE "F9" ;
-LOCATE COMP "TEST_LINE_4" SITE "D9" ;
-LOCATE COMP "TEST_LINE_5" SITE "D10" ;
-LOCATE COMP "TEST_LINE_6" SITE "F10" ;
-LOCATE COMP "TEST_LINE_7" SITE "E10" ;
-LOCATE COMP "TEST_LINE_8" SITE "A8" ;
-LOCATE COMP "TEST_LINE_9" SITE "B8" ;
-LOCATE COMP "TEST_LINE_10" SITE "G10" ;
-LOCATE COMP "TEST_LINE_11" SITE "G9" ;
-LOCATE COMP "TEST_LINE_12" SITE "C9" ;
-LOCATE COMP "TEST_LINE_13" SITE "C10" ;
-LOCATE COMP "TEST_LINE_14" SITE "H10" ;
-LOCATE COMP "TEST_LINE_15" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1
-LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3
-LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5
-LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7
-#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9
-#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11
-#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13
-LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15
-LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17
-#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19
-LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21
-LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23
-LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25
-LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27
-#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29
-#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31
-#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33
-LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35
-LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
-#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2
-LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2
-LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4
-LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6
-LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8
-#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10
-#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12
-#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
-LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
-LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18
-#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20
-LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22
-LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24
-LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26
-LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28
-#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30
-#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32
-#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34
-LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36
-LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38
-#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40
-LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169
-LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171
-LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173
-LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175
-#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177
-#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179
-#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181
-LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183
-LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185
-#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187
-LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170
-LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172
-LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174
-LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176
-#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178
-#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180
-#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182
-LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184
-LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186
-#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE_1" SITE "AA20" ;
-LOCATE COMP "CODE_LINE_0" SITE "Y21" ;
-IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ=20 ;
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-#REGION "MEDIA_UPLINK_REGION" "R90C95D" 20 25 DEVSIZE;
-#REGION "MEDIA_DOWNLINK_REGION" "R90C45D" 25 35 DEVSIZE;
-#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE;
-
-REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE;
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ;
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ;
-#LOCATE UGROUP "THE_SYNC_LINK/media_downlink_group" REGION "MEDIA_DOWNLINK_REGION" ;
-#USE SECONDARY NET "THE_MEDIA_UPLINK/rx_clock_half_c" "MEDIA_DOWNLINK_REGION" ;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;\r
-BLOCK PATH FROM CLKNET "clk_100_osc" TO CLKNET "THE_MEDIA_UPLINK/tmp_1";
-BLOCK PATH FROM CLKNET "clk_100_osc" TO CLKNET "THE_SYNC_LINK/sci_write_i_0";
-
-## IOBUF ALLPORTS ;
-#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-#USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
+++ /dev/null
-rvl_alias "clk_200_osc" "clk_200_osc";
-RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";
-#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7
-#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9
-#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11
-#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17
-#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27
-#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29
-#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31
-#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
-#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8
-#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10
-#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12
-#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18
-#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28
-#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30
-#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32
-#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38
-#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175
-#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177
-#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179
-#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185
-#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176
-#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178
-#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180
-#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186
-#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ=20 ;
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-#REGION "MEDIA_UPLINK_REGION" "R90C95D" 20 25 DEVSIZE;
-#REGION "MEDIA_DOWNLINK_REGION" "R90C45D" 25 35 DEVSIZE;
-#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE;
-
-REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE;
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ;
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ;
-#LOCATE UGROUP "THE_SYNC_LINK/media_downlink_group" REGION "MEDIA_DOWNLINK_REGION" ;
-#USE SECONDARY NET "THE_MEDIA_UPLINK/rx_clock_half_c" "MEDIA_DOWNLINK_REGION" ;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-BLOCK JTAGPATHS ;
-## IOBUF ALLPORTS ;
-#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-#USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
+++ /dev/null
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2015-03-18">
- <IP Version="1_5_062609"/>
- <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_source"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2095382979" Name="trb3_periph_sodasource_LA0" ID="0">
- <Setting>
- <Clock SampleClk="clk_200_osc" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
- <Capture Mode="0" MinSamplesPerTrig="8"/>
- <Event CntEnable="0" MaxEventCnt="8"/>
- <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_source_LA0_net"/>
- <DistRAM Disable="0"/>
- </Setting>
- <Dataset Name="Base">
- <Trace>
- <Sig Type="SIG" Name="the_soda_source/soda_reset_s"/>
- <Sig Type="SIG" Name="the_soda_source/soda_enable_s"/>
- <Sig Type="SIG" Name="the_soda_source/dead_channel_s"/>
- <Sig Type="SIG" Name="the_soda_source/report_error_s"/>
- <Sig Type="SIG" Name="the_soda_source/downstream_error_s"/>
- <Sig Type="SIG" Name="the_soda_source/channel_timeout_status_s"/>
- <Bus Name="the_soda_source/ctrl_status_register_s">
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:7"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:8"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:9"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:10"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:11"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:12"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:13"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:14"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:15"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:16"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:17"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:18"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:19"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:20"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:21"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:22"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:23"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:24"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:25"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:26"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:27"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:28"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:29"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:30"/>
- <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:31"/>
- </Bus>
- <Sig Type="SIG" Name="the_soda_source/soda_burst_pulse_in"/>
- <Bus Name="the_soda_source/super_burst_nr_s">
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:7"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:8"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:9"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:10"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:11"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:12"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:13"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:14"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:15"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:16"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:17"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:18"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:19"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:20"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:21"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:22"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:23"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:24"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:25"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:26"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:27"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:28"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:29"/>
- <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:30"/>
- </Bus>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_strobe_s"/>
- <Bus Name="the_soda_source/soda_cmd_word_s">
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:7"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:8"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:9"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:10"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:11"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:12"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:13"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:14"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:15"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:16"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:17"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:18"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:19"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:20"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:21"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:22"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:23"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:24"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:25"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:26"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:27"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:28"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:29"/>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:30"/>
- </Bus>
- <Sig Type="SIG" Name="the_soda_source/soda_cmd_window_s"/>
- <Sig Type="SIG" Name="the_sync_link/got_link_ready_i"/>
- <Sig Type="SIG" Name="the_sync_link/rx_k"/>
- <Bus Name="the_sync_link/rx_data">
- <Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:3"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:4"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:5"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
- <Bus Name="the_sync_link/rx_dlm_word">
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
- </Bus>
- <Bus Name="the_sync_link/rx_fsm_state">
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:3"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/tx_k"/>
- <Bus Name="the_sync_link/tx_data">
- <Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:3"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:4"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:5"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:6"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_preview_in"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm"/>
- <Bus Name="the_sync_link/tx_dlm_word">
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
- </Bus>
- <Bus Name="the_sync_link/tx_fsm_state">
- <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:3"/>
- </Bus>
- <Bus Name="the_sync_link/wa_position">
- <Sig Type="SIG" Name="the_sync_link/wa_position:0"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:1"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:2"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:3"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:4"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:5"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:6"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:7"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:8"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:9"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:10"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:11"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:12"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:13"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:14"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position:15"/>
- </Bus>
- <Bus Name="the_sync_link/wa_position_rx">
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:0"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:1"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:2"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:3"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:4"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:5"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:6"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:7"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:8"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:9"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:10"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:11"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:12"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:13"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:14"/>
- <Sig Type="SIG" Name="the_sync_link/wa_position_rx:15"/>
- </Bus>
- <Bus Name="the_soda_source/packet_builder/build_packet_state_s">
- <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:4"/>
- </Bus>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_data_valid_s"/>
- <Bus Name="the_soda_source/packet_builder/crc_datain_s">
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:7"/>
- </Bus>
- <Bus Name="the_soda_source/packet_builder/crc_out_s">
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_valid_s"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_pending_s"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_strobe_in"/>
- <Bus Name="the_soda_source/packet_builder/soda_cmd_word_in">
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:0"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:1"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:2"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:3"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:4"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:5"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:6"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:7"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:8"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:9"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:10"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:11"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:12"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:13"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:14"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:15"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:16"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:17"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:18"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:19"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:20"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:21"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:22"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:23"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:24"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:25"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:26"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:27"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:28"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:29"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:30"/>
- </Bus>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cycle_in"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/start_of_superburst"/>
- <Bus Name="the_soda_source/packet_builder/super_burst_nr_in">
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:0"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:1"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:2"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:3"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:4"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:5"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:6"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:7"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:8"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:9"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:10"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:11"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:12"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:13"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:14"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:15"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:16"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:17"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:18"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:19"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:20"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:21"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:22"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:23"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:24"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:25"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:26"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:27"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:28"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:29"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:30"/>
- </Bus>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_out"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_preview_out"/>
- <Bus Name="the_soda_source/packet_builder/tx_dlm_word_out">
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:0"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:1"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:2"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:3"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:4"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:5"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:6"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/wait4cycle_s"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_strobe_s"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_window_in"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_dlm_preview_s"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_valid_s"/>
- <Bus Name="the_soda_source/packet_builder/soda_pkt_word_s">
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:7"/>
- </Bus>
- <Bus Name="the_soda_source/packet_builder/cmd_window_state_s">
- <Sig Type="SIG" Name="the_soda_source/packet_builder/cmd_window_state_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/packet_builder/cmd_window_state_s:1"/>
- </Bus>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/soda_burst_pulse_in"/>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/soda_cmd_window_out"/>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/start_of_superburst_out"/>
- <Bus Name="the_soda_source/superburst_gen/burst_counter_s">
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:0"/>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:1"/>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:2"/>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:3"/>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:4"/>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:5"/>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:6"/>
- <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:7"/>
- </Bus>
- </Trace>
- <Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="the_soda_source/start_of_superburst_s,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="the_soda_source/packet_builder/soda_cmd_pending_s,"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
- </Trigger>
- </Dataset>
- </Core>
-</Project>
+++ /dev/null
-The place for all Soda related scripts.
signal calibration_timer_S : std_logic_vector(15 downto 0) := (others => '0'); -- from super-burst-nr-generator
begin
-\r
+
CALIBRATION_RUNNING <= calibration_running_S;
calibration_fsm_proc : process(SODACLK)
SODA_READ_IN : in std_logic := '0';
SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
- LEDS_OUT : out std_logic_vector(3 downto 0);\r
+ LEDS_OUT : out std_logic_vector(3 downto 0);
LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
);
end soda_client;
signal buf_bus_data_out : std_logic_vector(31 downto 0);
signal ledregister_i : std_logic_vector(31 downto 0);
signal tx_dlm_out_S : std_logic;
-\r
--- debug\r
+
+-- debug
signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0');
signal debug_rx_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
signal debug_tx_cnt_S : std_logic_vector(31 downto 0) := (others => '0');
SUPER_BURST_NR_OUT => super_burst_nr_S,
SODA_CMD_VALID_OUT => soda_cmd_valid_S,
SODA_CMD_WORD_OUT => soda_cmd_word_S,
--- CRC_VALID_OUT => crc_valid_S,\r
+-- CRC_VALID_OUT => crc_valid_S,
-- CRC_DATA_OUT => crc_data_S,
RX_DLM_IN => RX_DLM_IN,
RX_DLM_WORD_IN => RX_DLM_WORD_IN
);
- reply_packet_builder : soda_reply_pkt_builder \r
+ reply_packet_builder : soda_reply_pkt_builder
port map(
SODACLK => SODACLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => CLK_EN,
--Internal Connection
- LINK_PHASE_IN => LINK_PHASE_IN,\r
+ LINK_PHASE_IN => LINK_PHASE_IN,
START_OF_SUPERBURST => start_of_superburst_S,
SUPER_BURST_NR_IN => super_burst_nr_S,
SODA_CMD_STROBE_IN => soda_cmd_valid_S,
end if;
end if;
end process THE_READ_REG_PROC;
-\r
--- debug signals\r
- DEBUG_CLIENT : process(SODACLK)\r
- begin\r
- if( rising_edge(SODACLK) ) then\r
+
+-- debug signals
+ DEBUG_CLIENT : process(SODACLK)
+ begin
+ if( rising_edge(SODACLK) ) then
debug_status_S(0) <= RESET;
debug_status_S(1) <= CLEAR;
debug_status_S(2) <= CLK_EN;
- if ( RESET = '1' ) then\r
+ if ( RESET = '1' ) then
debug_rx_cnt_S <= (others => '0');
debug_tx_cnt_S <= (others => '0');
else
debug_cmd_cnt_S <= debug_cmd_cnt_S + 1;
end if;
end if;
- end if; \r
- end process;\r
-\r
- debug_status_S(31 downto 3) <= LINK_DEBUG_IN(31 downto 3);\r
+ end if;
+ end process;
+
+ debug_status_S(31 downto 3) <= LINK_DEBUG_IN(31 downto 3);
TX_DLM_OUT <= tx_dlm_out_S;
-- output signals
LEDS_OUT <= LEDregister_i(3 downto 0);
end component;
component soda_packet_handler
+ generic(
+ CLOCKSper25ns : integer := 5 -- PS
+ );
port(
SODACLK : in std_logic; -- fabric clock
RESET : in std_logic; -- synchronous reset
START_OF_CALIBRATION_OUT : out std_logic := '0';
SODA_CMD_VALID_OUT : out std_logic := '0';
SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CYCLE_OUT : out std_logic := '0'; -- PS
RX_DLM_IN : in std_logic;
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0')
);
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
-use ieee.std_logic_unsigned.all ;\r
-\r
+use ieee.std_logic_unsigned.all ;
+
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; \r
+use work.trb_net16_hub_func.all;
use work.soda_components.all;
entity soda_d8crc8 is
);
end soda_d8crc8;
-architecture behavioral of soda_d8crc8 is\r
- \r
- constant crc_const: std_logic_vector(7 downto 0) := (others => '0');\r
+architecture behavioral of soda_d8crc8 is
+
+ constant crc_const: std_logic_vector(7 downto 0) := (others => '0');
signal crc_r : std_logic_vector(7 downto 0);
signal crc_c : std_logic_vector(7 downto 0);
--SODA
signal soda_reset_S : std_logic;
- signal soda_enable_S : std_logic;\r
+ signal soda_enable_S : std_logic;
signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
signal soda_cmd_valid_S : std_logic := '0';
signal common_timeout_status_S : std_logic;
signal common_downstream_error_S : std_logic;
signal common_report_error_S : std_logic;
-\r
+
signal dead_channel_S : t_HUB_BIT_ARRAY := (others => '0');
signal COMMON_CTRL_STATUS_register_S: std_logic_vector(31 downto 0);
signal ledregister_i : std_logic_vector(31 downto 0) := (others => '0');
-- signal txup_dlm_out_S : std_logic;
+ signal SODA_CYCLE_S : std_logic; -- PS
begin
hub_packet_handler : soda_packet_handler
+ generic map(
+ CLOCKSper25ns => 5 -- PS
+ )
port map(
SODACLK => SODACLK,
RESET => RESET,
SUPER_BURST_NR_OUT => super_burst_nr_S,
SODA_CMD_VALID_OUT => soda_cmd_valid_S,
SODA_CMD_WORD_OUT => soda_cmd_word_S,
+ SODA_CYCLE_OUT => SODA_CYCLE_S, -- PS
RX_DLM_IN => RXUP_DLM_IN,
RX_DLM_WORD_IN => RXUP_DLM_WORD_IN
);
channel :for i in c_HUB_CHILDREN-1 downto 0 generate
- start_calibration_S(i) <= send_start_calibration_S(i);
+start_calibration_S(i) <= send_start_calibration_S(i);
packet_builder : soda_packet_builder
port map(
RESET => RESET,
--Internal Connection
LINK_PHASE_IN => UPLINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ?
- SODA_CYCLE_IN => '1', -- 40MHz cycle is only required to sync superbursts at the source PL! 24022015
+ SODA_CYCLE_IN => SODA_CYCLE_S, -- PS : 40MHz cycle also required for commands !!!
SODA_CMD_WINDOW_IN => '1', -- soda-source determines the sending of a command; hub always copies
- SODA_CMD_STROBE_IN => trb_cmd_strobe_S, --soda_cmd_valid_S, --TXsoda_cmd_valid_S(i),
+ SODA_CMD_STROBE_IN => soda_cmd_valid_S, -- PS: commands from source must be passed on !, my opinion:no need for hubs to send commands -- trb_cmd_strobe_S, -- PS: should be trb_cmd_strobe_sodaclk_S --soda_cmd_valid_S, --TXsoda_cmd_valid_S(i),
START_OF_SUPERBURST => start_of_superburst_S, --TXstart_of_superburst_S(i),
SUPER_BURST_NR_IN => super_burst_nr_S, --TXsuper_burst_nr_S(i)(30 downto 0),
- SODA_CMD_WORD_IN => trb_cmd_word_S, --soda_cmd_word_S, --TXsoda_cmd_word_S(i)(30 downto 0),
+ SODA_CMD_WORD_IN => soda_cmd_word_S, -- PS: commands from source must be passed on !, my opinion:no need for hubs to send commands -- trb_cmd_word_S, --soda_cmd_word_S, --TXsoda_cmd_word_S(i)(30 downto 0),
EXPECTED_REPLY_OUT => expected_reply_S(i),
SEND_TIME_CAL_OUT => send_start_calibration_S(i),
TX_DLM_PREVIEW_OUT => TXDN_DLM_PREVIEW_OUT(i),
--CTRL_STATUS_register_S(i)(0) <= channel_timeout_status_S(i);
end generate;
-\r
+
soda_reset_S <= (RESET or COMMON_CTRL_STATUS_register_S(31));
soda_enable_S <= COMMON_CTRL_STATUS_register_S(30);
common_downstream_error_S <= '1' when ((downstream_error_S(0)='1') or (downstream_error_S(1)='1') or (downstream_error_S(2)='1') or (downstream_error_S(3)='1'))
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-\r
+
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; \r
+use work.trb_net16_hub_func.all;
use work.soda_components.all;
-\r
-entity soda_packet_builder is\r
- port(\r
- SODACLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- --Internal Connection\r
+
+entity soda_packet_builder is
+ port(
+ SODACLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ --Internal Connection
LINK_PHASE_IN : in std_logic := '0'; -- even/odd fase needed to match 16-bit link stuff in trb
SODA_CYCLE_IN : in std_logic := '0'; -- 40MHz cycle for soda transmissions
SODA_CMD_WINDOW_IN : in std_logic := '0';
SODA_CMD_STROBE_IN : in std_logic := '0';
- START_OF_SUPERBURST : in std_logic := '0';\r
- SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');\r
- SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit\r
+ START_OF_SUPERBURST : in std_logic := '0';
+ SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit
EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
SEND_TIME_CAL_OUT : out std_logic := '0';
TX_DLM_PREVIEW_OUT : out std_logic := '0'; --
TX_DLM_OUT : out std_logic := '0'; --
- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')\r
- );\r
-end soda_packet_builder;\r
-\r
-architecture Behavioral of soda_packet_builder is\r
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')
+ );
+end soda_packet_builder;
+
+architecture Behavioral of soda_packet_builder is
signal soda_cmd_pending_S : std_logic := '0';
signal soda_cmd_strobe_S : std_logic := '0';
signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); -- from slowcontrol
- signal soda_pkt_word_S : std_logic_vector(7 downto 0) := (others => '0');\r
+ signal soda_pkt_word_S : std_logic_vector(7 downto 0) := (others => '0');
signal soda_pkt_valid_S : std_logic;
signal reg1_soda_pkt_valid_S : std_logic;
-- signal reg2_soda_pkt_valid_S : std_logic;
signal wait4cycle_S : std_logic;
- signal soc_S : std_logic;\r
- signal eoc_S : std_logic;\r
- signal crc_data_valid_S : std_logic;\r
- signal crc_datain_S : std_logic_vector(7 downto 0) := (others => '0');\r
- signal crc_out_S : std_logic_vector(7 downto 0) := (others => '0');\r
- signal crc_valid_S : std_logic;\r
- \r
+ signal soc_S : std_logic;
+ signal eoc_S : std_logic;
+ signal crc_data_valid_S : std_logic;
+ signal crc_datain_S : std_logic_vector(7 downto 0) := (others => '0');
+ signal crc_out_S : std_logic_vector(7 downto 0) := (others => '0');
+ signal crc_valid_S : std_logic;
+
type build_packet_state_type is ( c_IDLE, c_ERROR,
c_WAIT4CYCLE_B, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8,
c_WAIT4CYCLE_C, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8
- ); -- c_WAIT4BST1, c_WAIT4CMD1, \r
- signal build_packet_state_S : build_packet_state_type := c_IDLE;\r
+ ); -- c_WAIT4BST1, c_WAIT4CMD1,
+ signal build_packet_state_S : build_packet_state_type := c_IDLE;
signal build_packet_bits_S : std_logic_vector(7 downto 0) := (others => '0');
- \r
+
type cmd_window_state_type is ( c_WINDOW_IDLE, c_WAIT4WINDOW, c_START_CMD);
- signal cmd_window_state_S : cmd_window_state_type := c_WINDOW_IDLE;\r
+ signal cmd_window_state_S : cmd_window_state_type := c_WINDOW_IDLE;
-\r
+
signal soda_dlm_preview_S : std_logic;
-\r
-begin\r
-\r
+
+ signal PS_crc_out_S : std_logic_vector(7 downto 0); -- PS
+
+begin
+
tx_crc8: soda_d8crc8
port map(
CLOCK => SODACLK,
CRC_VALID_OUT => crc_valid_S
);
- soda_cmd_word_S <= SODA_CMD_WORD_IN;\r
- \r
+ soda_cmd_word_S <= SODA_CMD_WORD_IN;
+
-- TX_DLM_PREVIEW_OUT <= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (soda_cmd_strobe_S='1'))) or
-- ((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1')))
-- else '0';
TX_DLM_PREVIEW_OUT <= '1' when ((soda_dlm_preview_S='1') or ((wait4cycle_S='1') and (SODA_CYCLE_IN='1')))
else '0';
- TX_DLM_OUT <= reg1_soda_pkt_valid_S;\r
+ TX_DLM_OUT <= reg1_soda_pkt_valid_S;
TX_DLM_WORD_OUT <= soda_pkt_word_S;
-\r
-\r
--- strobe_delay_proc : process(SODACLK)\r
--- begin\r
+
+
+-- strobe_delay_proc : process(SODACLK)
+-- begin
-- if rising_edge(SODACLK) then
-- if (RESET='1') then
-- soda_cmd_pending_S <= '0';
--- elsif (SODA_CMD_STROBE_IN='1') then\r
--- soda_cmd_pending_S <= '1';\r
--- elsif (soda_cmd_strobe_S='1') then\r
+-- elsif (SODA_CMD_STROBE_IN='1') then
+-- soda_cmd_pending_S <= '1';
+-- elsif (soda_cmd_strobe_S='1') then
-- soda_cmd_pending_S <= '0';
--- end if;\r
--- end if;\r
--- end process;\r
-\r
-\r
+-- end if;
+-- end if;
+-- end process;
+
+
-- strobe_delivery_proc : process(SODACLK)
-- begin
-- if rising_edge(SODACLK) then
-- end if;
-- end if;
-- end process;
-\r
+
SODA_CMD_FLOWCTRL : process(SODACLK)
begin
if( rising_edge(SODACLK) ) then
if( RESET = '1' ) then
cmd_window_state_S <= c_WINDOW_IDLE;
soda_cmd_pending_S <= '0';
- soda_cmd_strobe_S <= '0';\r
+ soda_cmd_strobe_S <= '0';
else
- case cmd_window_state_S is\r
+ case cmd_window_state_S is
when c_WINDOW_IDLE =>
if (SODA_CMD_STROBE_IN='1') then
cmd_window_state_S <= c_WAIT4WINDOW;
- soda_cmd_pending_S <= '1';\r
+ soda_cmd_pending_S <= '1';
end if;
- when c_WAIT4WINDOW =>\r
+ when c_WAIT4WINDOW =>
if ((SODA_CMD_WINDOW_IN ='1') and (soda_cmd_pending_S ='1')) then
cmd_window_state_S <= c_START_CMD;
soda_cmd_strobe_S <= '1';
- soda_cmd_pending_S <= '0';\r
+ soda_cmd_pending_S <= '0';
end if;
- when c_START_CMD =>\r
+ when c_START_CMD =>
cmd_window_state_S <= c_WINDOW_IDLE;
soda_cmd_strobe_S <= '0';
soda_cmd_pending_S <= '0';
- when others =>\r
- cmd_window_state_S <= c_WINDOW_IDLE;\r
+ when others =>
+ cmd_window_state_S <= c_WINDOW_IDLE;
soda_cmd_strobe_S <= '0';
soda_cmd_pending_S <= '0';
- end case;\r
+ end case;
end if;
end if;
- end process SODA_CMD_FLOWCTRL; \r
-\r
- packet_fsm_proc : process(SODACLK)\r
- begin\r
- if rising_edge(SODACLK) then\r
- if (RESET='1') then\r
- build_packet_bits_S <= x"00";\r
- build_packet_state_S <= c_IDLE;\r
+ end process SODA_CMD_FLOWCTRL;
+
+ packet_fsm_proc : process(SODACLK)
+ begin
+ if rising_edge(SODACLK) then
+ if (RESET='1') then
+ build_packet_bits_S <= x"00";
+ build_packet_state_S <= c_IDLE;
soda_dlm_preview_S <= '0';
soda_pkt_valid_S <= '0';
reg1_soda_pkt_valid_S <= '0';
--- reg2_soda_pkt_valid_S <= '0';\r
+-- reg2_soda_pkt_valid_S <= '0';
wait4cycle_S <= '0';
soda_pkt_word_S <= (others => '0');
- else\r
+ else
soda_pkt_valid_S <= reg1_soda_pkt_valid_S;
-- reg2_soda_pkt_valid_S <= reg1_soda_pkt_valid_S;
- case build_packet_state_S is\r
+ case build_packet_state_S is
-- when c_IDLE =>
-- if (START_OF_SUPERBURST='1') then
-- soda_dlm_preview_S <= '1';
reg1_soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
end if;
- when c_WAIT4CYCLE_B =>\r
+ when c_WAIT4CYCLE_B =>
wait4cycle_S <= '1';
if ((SODA_CYCLE_IN='1') and (LINK_PHASE_IN = c_PHASE_H)) then
build_packet_bits_S <= x"11";
-- soda_dlm_preview_S <= '1';
-- reg1_soda_pkt_valid_S <= '1';
-- soda_pkt_word_S <= '1' & SUPER_BURST_NR_IN(30 downto 24);
- when c_BST1 =>\r
+ when c_BST1 =>
build_packet_bits_S <= x"12";
- build_packet_state_S <= c_BST2;\r
+ build_packet_state_S <= c_BST2;
reg1_soda_pkt_valid_S <= '0';
- when c_BST2 =>\r
+ when c_BST2 =>
build_packet_bits_S <= x"13";
- build_packet_state_S <= c_BST3;\r
+ build_packet_state_S <= c_BST3;
reg1_soda_pkt_valid_S <= '1';
soda_pkt_word_S <= SUPER_BURST_NR_IN(23 downto 16);
- when c_BST3 =>\r
+ when c_BST3 =>
build_packet_bits_S <= x"14";
- build_packet_state_S <= c_BST4;\r
+ build_packet_state_S <= c_BST4;
reg1_soda_pkt_valid_S <= '0';
- when c_BST4 =>\r
+ when c_BST4 =>
build_packet_bits_S <= x"15";
- build_packet_state_S <= c_BST5;\r
+ build_packet_state_S <= c_BST5;
reg1_soda_pkt_valid_S <= '1';
soda_pkt_word_S <= SUPER_BURST_NR_IN(15 downto 8);
- when c_BST5 =>\r
+ when c_BST5 =>
build_packet_bits_S <= x"16";
- build_packet_state_S <= c_BST6;\r
+ build_packet_state_S <= c_BST6;
reg1_soda_pkt_valid_S <= '0';
- when c_BST6 =>\r
+ when c_BST6 =>
build_packet_bits_S <= x"17";
- build_packet_state_S <= c_BST7;\r
+ build_packet_state_S <= c_BST7;
reg1_soda_pkt_valid_S <= '1';
- soda_pkt_word_S <= SUPER_BURST_NR_IN(7 downto 0);\r
+ soda_pkt_word_S <= SUPER_BURST_NR_IN(7 downto 0);
EXPECTED_REPLY_OUT <= SUPER_BURST_NR_IN(7 downto 0);
- when c_BST7 =>\r
+ when c_BST7 =>
build_packet_bits_S <= x"18";
- build_packet_state_S <= c_BST8;\r
+ build_packet_state_S <= c_BST8;
soda_dlm_preview_S <= '0';
reg1_soda_pkt_valid_S <= '0';
- when c_BST8 =>\r
- if (soda_cmd_strobe_S='0') then\r
+ when c_BST8 =>
+ if (soda_cmd_strobe_S='0') then
soda_dlm_preview_S <= '0';
build_packet_bits_S <= x"00";
- build_packet_state_S <= c_IDLE;\r
- else\r
+ build_packet_state_S <= c_IDLE;
+ else
soda_dlm_preview_S <= '1';
build_packet_bits_S <= x"21";
- build_packet_state_S <= c_CMD1;\r
- end if;\r
+ build_packet_state_S <= c_CMD1;
+ end if;
reg1_soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
when c_WAIT4CYCLE_C =>
soda_dlm_preview_S <= '0';
reg1_soda_pkt_valid_S <= '0';
soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);
- end if;\r
+ end if;
-- when c_WAIT4CMD1 =>
-- build_packet_state_S <= c_CMD1;
-- soda_dlm_preview_S <= '1';
-- soda_pkt_valid_S <= '1';
-- soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);
- when c_CMD1 =>\r
+ when c_CMD1 =>
build_packet_bits_S <= x"22";
- build_packet_state_S <= c_CMD2;\r
+ build_packet_state_S <= c_CMD2;
soda_dlm_preview_S <= '1';
reg1_soda_pkt_valid_S <= '0';
SEND_TIME_CAL_OUT <= soda_cmd_word_S(30);
- when c_CMD2 =>\r
+ when c_CMD2 =>
build_packet_bits_S <= x"23";
- build_packet_state_S <= c_CMD3;\r
+ build_packet_state_S <= c_CMD3;
reg1_soda_pkt_valid_S <= '1';
soda_pkt_word_S <= soda_cmd_word_S(23 downto 16);
SEND_TIME_CAL_OUT <= '0';
- when c_CMD3 =>\r
+ when c_CMD3 =>
build_packet_bits_S <= x"24";
- build_packet_state_S <= c_CMD4;\r
+ build_packet_state_S <= c_CMD4;
reg1_soda_pkt_valid_S <= '0';
- when c_CMD4 =>\r
+ when c_CMD4 =>
build_packet_bits_S <= x"25";
- build_packet_state_S <= c_CMD5;\r
+ build_packet_state_S <= c_CMD5;
reg1_soda_pkt_valid_S <= '1';
soda_pkt_word_S <= soda_cmd_word_S(15 downto 8);
- when c_CMD5 =>\r
+ when c_CMD5 =>
build_packet_bits_S <= x"26";
- build_packet_state_S <= c_CMD6;\r
+ build_packet_state_S <= c_CMD6;
reg1_soda_pkt_valid_S <= '0';
- when c_CMD6 =>\r
+ if (crc_valid_S = '0') then --PS
+ build_packet_state_S <= c_ERROR; --PS
+ else
+ PS_crc_out_S <= crc_out_S; --PS
+ end if;
+ when c_CMD6 =>
build_packet_bits_S <= x"27";
- build_packet_state_S <= c_CMD7;\r
+ build_packet_state_S <= c_CMD7;
reg1_soda_pkt_valid_S <= '1';
- soda_pkt_word_S <= soda_cmd_word_S(7 downto 0);\r
- EXPECTED_REPLY_OUT <= soda_cmd_word_S(7 downto 0);
- when c_CMD7 =>\r
- if (crc_valid_S = '0') then
+ soda_pkt_word_S <= PS_crc_out_S; --PS: crc needed soda_cmd_word_S(7 downto 0);
+ EXPECTED_REPLY_OUT <= PS_crc_out_S; --PS: crc needed soda_cmd_word_S(7 downto 0);
+ when c_CMD7 =>
+ if (crc_valid_S = '1') then --PS
build_packet_bits_S <= x"0E";
- build_packet_state_S <= c_ERROR;\r
+ build_packet_state_S <= c_ERROR;
else
build_packet_bits_S <= x"28";
- build_packet_state_S <= c_CMD8;\r
- end if;\r
+ build_packet_state_S <= c_CMD8;
+ end if;
soda_dlm_preview_S <= '0';
reg1_soda_pkt_valid_S <= '0';
when c_CMD8 =>
build_packet_bits_S <= x"00";
- build_packet_state_S <= c_IDLE;\r
+ build_packet_state_S <= c_IDLE;
soda_dlm_preview_S <= '0';
reg1_soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
when c_ERROR =>
build_packet_bits_S <= x"00";
- build_packet_state_S <= c_IDLE;\r
+ build_packet_state_S <= c_IDLE;
soda_dlm_preview_S <= '0';
reg1_soda_pkt_valid_S <= '0';
- when others =>\r
+ when others =>
build_packet_bits_S <= x"00";
- build_packet_state_S <= c_IDLE;\r
+ build_packet_state_S <= c_IDLE;
soda_dlm_preview_S <= '0';
reg1_soda_pkt_valid_S <= '0';
- end case;\r
- end if;\r
- end if;\r
- end process;\r
-\r
--- soda_cmd_reg_proc : process(SODACLK)\r
--- begin\r
--- if rising_edge(SODACLK) then\r
--- if (RESET='1') then\r
--- soda_cmd_reg_full_S <= '0';\r
--- soda_cmd_reg_S <= (others => '0');\r
--- elsif (soda_pkt_valid_S = '1') then\r
+ end case;
+ end if;
+ end if;
+ end process;
+
+-- soda_cmd_reg_proc : process(SODACLK)
+-- begin
+-- if rising_edge(SODACLK) then
+-- if (RESET='1') then
+-- soda_cmd_reg_full_S <= '0';
+-- soda_cmd_reg_S <= (others => '0');
+-- elsif (soda_pkt_valid_S = '1') then
-- soda_cmd_reg_full_S <= '1';
-- soda_cmd_reg_S <= '0' & soda_cmd_word_S;
--
--- end if;\r
+-- end if;
-- end if;
--- end process;\r
-\r
-\r
- crc_gen_proc : process(SODACLK, build_packet_state_S)\r
- begin\r
- if rising_edge(SODACLK) then\r
- case build_packet_state_S is\r
- when c_IDLE =>\r
- crc_data_valid_S <= '0';\r
- crc_datain_S <= (others=>'0');
- soc_S <= '1';\r
- eoc_S <= '0';\r
- when c_CMD1 =>\r
- crc_data_valid_S <= '1';\r
- crc_datain_S <= '0' & soda_cmd_word_S(30 downto 24);
- soc_S <= '0';\r
- eoc_S <= '0';\r
- when c_CMD2 =>\r
- crc_data_valid_S <= '0';\r
- crc_datain_S <= (others=>'0');\r
- soc_S <= '0';\r
- eoc_S <= '0';\r
- when c_CMD3 =>\r
- crc_data_valid_S <= '1';\r
- crc_datain_S <= soda_cmd_word_S(23 downto 16);\r
- soc_S <= '0';\r
- eoc_S <= '0';\r
- when c_CMD4 =>\r
- crc_data_valid_S <= '0';\r
- crc_datain_S <= (others=>'0');\r
- soc_S <= '0';\r
- eoc_S <= '0';\r
- when c_CMD5 =>\r
- crc_data_valid_S <= '1';\r
- crc_datain_S <= soda_cmd_word_S(15 downto 8);\r
- soc_S <= '0';\r
- eoc_S <= '1';\r
- when c_CMD6 =>\r
- crc_data_valid_S <= '0';\r
- crc_datain_S <= (others=>'0');\r
- soc_S <= '0';\r
- eoc_S <= '0';\r
- when c_CMD7 =>\r
- crc_data_valid_S <= '0';\r
- crc_datain_S <= (others=>'0');\r
- soc_S <= '0';\r
- eoc_S <= '0';\r
- when c_CMD8 =>\r
- crc_data_valid_S <= '0';\r
- crc_datain_S <= (others=>'0');\r
- soc_S <= '0';\r
- eoc_S <= '0';\r
- when others =>\r
- crc_data_valid_S <= '0';\r
- crc_datain_S <= (others=>'0');\r
- soc_S <= '0';\r
- eoc_S <= '0';\r
- end case; \r
- end if;\r
- end process;
-\r
+-- end process;
+
+
+-- -- PS : crc one clock earlier
+crc_data_valid_S <=
+ '1' when (((build_packet_state_S=c_WAIT4CYCLE_C) and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)))
+ or ((build_packet_state_S=c_BST8) and (soda_cmd_strobe_S='1'))
+ or ((build_packet_state_S=c_IDLE) and (START_OF_SUPERBURST='0') and (soda_cmd_strobe_S='1') and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H))))
+ else '1' when (build_packet_state_S=c_CMD2)
+ else '1' when (build_packet_state_S=c_CMD4)
+ else '0';
+
+crc_datain_S <=
+ '0' & soda_cmd_word_S(30 downto 24)
+ when (((build_packet_state_S=c_WAIT4CYCLE_C) and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)))
+ or ((build_packet_state_S=c_BST8) and (soda_cmd_strobe_S='1'))
+ or ((build_packet_state_S=c_IDLE) and (START_OF_SUPERBURST='0') and (soda_cmd_strobe_S='1') and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H))))
+ else soda_cmd_word_S(23 downto 16) when (build_packet_state_S=c_CMD2)
+ else soda_cmd_word_S(15 downto 8) when (build_packet_state_S=c_CMD4)
+ else (others => '0');
+
+soc_S <=
+ '1'
+ when (((build_packet_state_S=c_WAIT4CYCLE_C) and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)))
+ or ((build_packet_state_S=c_BST8) and (soda_cmd_strobe_S='1'))
+ or ((build_packet_state_S=c_IDLE) and (START_OF_SUPERBURST='0') and (soda_cmd_strobe_S='1') and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H))))
+ else '0';
+
+eoc_S <= '1' when (build_packet_state_S=c_CMD4) else '0';
+
+
+
+ -- crc_gen_proc : process(SODACLK, build_packet_state_S)
+ -- begin
+ -- if rising_edge(SODACLK) then
+ -- case build_packet_state_S is
+ -- when c_IDLE =>
+ -- crc_data_valid_S <= '0';
+ -- crc_datain_S <= (others=>'0');
+ -- soc_S <= '1';
+ -- eoc_S <= '0';
+ -- when c_CMD1 =>
+ -- crc_data_valid_S <= '1';
+ -- crc_datain_S <= '0' & soda_cmd_word_S(30 downto 24);
+ -- soc_S <= '0';
+ -- eoc_S <= '0';
+ -- when c_CMD2 =>
+ -- crc_data_valid_S <= '0';
+ -- crc_datain_S <= (others=>'0');
+ -- soc_S <= '0';
+ -- eoc_S <= '0';
+ -- when c_CMD3 =>
+ -- crc_data_valid_S <= '1';
+ -- crc_datain_S <= soda_cmd_word_S(23 downto 16);
+ -- soc_S <= '0';
+ -- eoc_S <= '0';
+ -- when c_CMD4 =>
+ -- crc_data_valid_S <= '0';
+ -- crc_datain_S <= (others=>'0');
+ -- soc_S <= '0';
+ -- eoc_S <= '0';
+ -- when c_CMD5 =>
+ -- crc_data_valid_S <= '1';
+ -- crc_datain_S <= soda_cmd_word_S(15 downto 8);
+ -- soc_S <= '0';
+ -- eoc_S <= '1';
+ -- when c_CMD6 =>
+ -- crc_data_valid_S <= '0';
+ -- crc_datain_S <= (others=>'0');
+ -- soc_S <= '0';
+ -- eoc_S <= '0';
+ -- when c_CMD7 =>
+ -- crc_data_valid_S <= '0';
+ -- crc_datain_S <= (others=>'0');
+ -- soc_S <= '0';
+ -- eoc_S <= '0';
+ -- when c_CMD8 =>
+ -- crc_data_valid_S <= '0';
+ -- crc_datain_S <= (others=>'0');
+ -- soc_S <= '0';
+ -- eoc_S <= '0';
+ -- when others =>
+ -- crc_data_valid_S <= '0';
+ -- crc_datain_S <= (others=>'0');
+ -- soc_S <= '0';
+ -- eoc_S <= '0';
+ -- end case;
+ -- end if;
+ -- end process;
+
end architecture;
\ No newline at end of file
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; \r
+use work.trb_net16_hub_func.all;
use work.soda_components.all;
entity soda_packet_handler is
+ generic(
+ CLOCKSper25ns : integer := 5 -- PS
+ );
port(
SODACLK : in std_logic; -- fabric clock
RESET : in std_logic; -- synchronous reset
START_OF_CALIBRATION_OUT : out std_logic := '0';
SODA_CMD_VALID_OUT : out std_logic := '0';
SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CYCLE_OUT : out std_logic := '0'; -- PS
RX_DLM_IN : in std_logic;
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0')
);
c_SODA_PKT5, c_SODA_PKT6, c_SODA_PKT7, c_SODA_PKT8
);
signal packet_state_S : packet_state_type := c_IDLE;
+ signal SODA40MHz_counter_S : integer range 0 to CLOCKSper25ns-1 := 0; -- PS
begin
START_OF_SUPERBURST_OUT <= '0';
START_OF_CALIBRATION_OUT <= '0';
SODA_CMD_VALID_OUT <= '0';
- soda_pkt_word_S(31 downto 24) <= RX_DLM_WORD_IN;\r
+ soda_pkt_word_S(31 downto 24) <= RX_DLM_WORD_IN;
when c_SODA_PKT2 =>
-- do nothing -- disregard K28.7
when c_SODA_PKT3 =>
SUPER_BURST_NR_OUT <= soda_pkt_word_S(30 downto 0);
else
SODA_CMD_VALID_OUT <= '1';
- SODA_CMD_WORD_OUT <= soda_pkt_word_S(30 downto 0);\r
- if soda_pkt_word_S(30)='1' then\r
- START_OF_CALIBRATION_OUT <= '1';\r
+ SODA_CMD_WORD_OUT <= soda_pkt_word_S(30 downto 0);
+ if soda_pkt_word_S(30)='1' then
+ START_OF_CALIBRATION_OUT <= '1';
end if;
end if;
when others =>
end if;
end process;
+-- PS : 40MHz clock cycle, synchronized to SODA
+make_synchronous_40MHz_proc : process(SODACLK, packet_state_S)
+ begin
+ if rising_edge(SODACLK) then
+ if ((packet_state_S=c_RST) or (packet_state_S=c_IDLE)) and (RX_DLM_IN='1') then
+ SODA40MHz_counter_S <= 0;
+ else
+ if SODA40MHz_counter_S<CLOCKSper25ns-1 then
+ SODA40MHz_counter_S <= SODA40MHz_counter_S+1;
+ else
+ SODA40MHz_counter_S <= 0;
+ end if;
+ end if;
+ if SODA40MHz_counter_S=1 then
+ SODA_CYCLE_OUT <= '1';
+ else
+ SODA_CYCLE_OUT <= '0';
+ end if;
+ end if;
+ end process;
end architecture;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+use work.soda_components.all;
+
+entity soda_reply_handler is
+ port(
+ SODACLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
+ EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ RX_DLM_IN : in std_logic := '0';
+ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ REPLY_VALID_OUT : out std_logic := '0';
+ REPLY_OK_OUT : out std_logic := '0'
+ );
+end soda_reply_handler;
+
+architecture Behavioral of soda_reply_handler is
+
+ -- type packet_state_type is ( c_RST, c_IDLE, c_ERROR, c_REPLY, c_DONE);
+ -- signal reply_recv_state_S : packet_state_type := c_IDLE;
+
+begin
+
+ reply_fsm_proc : process(SODACLK)
+ begin
+ if rising_edge(SODACLK) then
+ REPLY_VALID_OUT <= '0';
+ REPLY_OK_OUT <= '0';
+ if (RX_DLM_IN='1') then
+ REPLY_VALID_OUT <= '1';
+ if (EXPECTED_REPLY_IN = RX_DLM_WORD_IN) then
+ REPLY_OK_OUT <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- reply_fsm_proc : process(SODACLK)
+ -- begin
+ -- if rising_edge(SODACLK) then
+ -- if (RESET='1') then
+ -- REPLY_VALID_OUT <= '0';
+ -- REPLY_OK_OUT <= '0';
+ -- reply_recv_state_S <= c_IDLE;
+ -- else
+ -- REPLY_VALID_OUT <= '0';
+ -- case reply_recv_state_S is
+ -- when c_IDLE =>
+ -- if (RX_DLM_IN='1') then
+ -- reply_recv_state_S <= c_REPLY;
+ -- REPLY_VALID_OUT <= '1';
+ -- if (EXPECTED_REPLY_IN = RX_DLM_WORD_IN) then
+ -- REPLY_OK_OUT <= '1';
+ -- else
+ -- REPLY_OK_OUT <= '0';
+ -- end if;
+ -- end if;
+ -- when c_REPLY =>
+ -- REPLY_VALID_OUT <= '0';
+ -- REPLY_OK_OUT <= '0';
+ -- if (RX_DLM_IN='0') then
+ -- reply_recv_state_S <= c_IDLE;
+ -- else
+ -- reply_recv_state_S <= c_ERROR;
+ -- end if;
+ -- when c_ERROR =>
+ -- reply_recv_state_S <= c_IDLE;
+ -- REPLY_OK_OUT <= '0';
+ -- REPLY_OK_OUT <= '0';
+ -- when others =>
+ -- reply_recv_state_S <= c_IDLE;
+ -- REPLY_OK_OUT <= '0';
+ -- end case;
+ -- end if;
+ -- end if;
+ -- end process;
+
+end architecture;
\ No newline at end of file
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-\r
+
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; \r
+use work.trb_net16_hub_func.all;
use work.soda_components.all;
-\r
-entity soda_reply_pkt_builder is\r
- port(\r
- SODACLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic; \r
- --Internal Connection\r
+
+entity soda_reply_pkt_builder is
+ port(
+ SODACLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
LINK_PHASE_IN : in std_logic := '0'; --_vector(1 downto 0) := (others => '0');
- START_OF_SUPERBURST : in std_logic := '0';\r
- SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');\r
- SODA_CMD_STROBE_IN : in std_logic := '0'; -- \r
- SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit\r
+ START_OF_SUPERBURST : in std_logic := '0';
+ SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CMD_STROBE_IN : in std_logic := '0'; --
+ SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit
TX_DLM_PREVIEW_OUT : out std_logic := '0'; --
TX_DLM_OUT : out std_logic := '0'; --
- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')\r
- );\r
-end soda_reply_pkt_builder;\r
-\r
-architecture soda_reply_pkt_builder_arch of soda_reply_pkt_builder is\r
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')
+ );
+end soda_reply_pkt_builder;
+
+architecture soda_reply_pkt_builder_arch of soda_reply_pkt_builder is
type reply_packet_state_type is ( c_IDLE, c_ERROR,
c_WAIT4BST1, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8,
);
signal reply_packet_state_S : reply_packet_state_type := c_IDLE;
signal reply_packet_bits_S : std_logic_vector(7 downto 0) := (others => '0');
-\r
+
signal soda_dlm_preview_S : std_logic;
signal sequence_error_S : std_logic;
signal next_superburst_nr_S : std_logic_vector(30 downto 0);
-\r
-\r
-begin\r
+
+
+begin
-- TX_DLM_PREVIEW_OUT <= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1'))) or
-- ((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1')))
-- else '0';
TX_DLM_PREVIEW_OUT <= soda_dlm_preview_S;
-\r
+
sequence_check_proc : process(SODACLK)
begin
if rising_edge(SODACLK) then
- if (RESET='1') then\r
- sequence_error_S <= '0';\r
- next_superburst_nr_S <= (others => '0');\r
- else\r
+ if (RESET='1') then
+ sequence_error_S <= '0';
+ next_superburst_nr_S <= (others => '0');
+ else
case reply_packet_state_S is
when c_IDLE =>
if (START_OF_SUPERBURST='1') then
- if (SUPER_BURST_NR_IN=next_superburst_nr_S) then\r
+ if (SUPER_BURST_NR_IN=next_superburst_nr_S) then
sequence_error_S <= '0';
- else\r
+ else
sequence_error_S <= '1';
- end if;\r
- end if;\r
+ end if;
+ end if;
-- when c_BST1 =>
-- sequence_error_S <= '0';
-- next_superburst_nr_S <= SUPER_BURST_NR_IN + 1;
next_superburst_nr_S <= SUPER_BURST_NR_IN + 1;
when others =>
end case;
- end if;\r
- end if;\r
- end process;\r
-\r
+ end if;
+ end if;
+ end process;
+
reply_fsm_proc : process(SODACLK)
begin
if rising_edge(SODACLK) then
- if (RESET='1') then\r
+ if (RESET='1') then
reply_packet_bits_S <= x"00";
reply_packet_state_S <= c_IDLE;
soda_dlm_preview_S <= '0';
else
case reply_packet_state_S is
when c_IDLE =>
- if (START_OF_SUPERBURST='1') then\r
+ if (START_OF_SUPERBURST='1') then
soda_dlm_preview_S <= '1';
if (LINK_PHASE_IN = c_PHASE_H) then
reply_packet_bits_S <= x"11";
else
reply_packet_bits_S <= x"20";
reply_packet_state_S <= c_WAIT4CMD1;
- TX_DLM_OUT <= '0';\r
+ TX_DLM_OUT <= '0';
end if;
end if;
when c_WAIT4BST1 =>
reply_packet_bits_S <= x"12";
reply_packet_state_S <= c_BST2;
TX_DLM_OUT <= '0';
- soda_dlm_preview_S <= '0';\r
+ soda_dlm_preview_S <= '0';
when c_BST2 =>
reply_packet_bits_S <= x"00";
reply_packet_state_S <= c_IDLE;
when c_CMD2 =>
reply_packet_bits_S <= x"00";
reply_packet_state_S <= c_IDLE;
- when others =>\r
+ when others =>
reply_packet_bits_S <= x"00";
reply_packet_state_S <= c_IDLE;
TX_DLM_OUT <= '0';
end case;
end if;
end if;
- end process;\r
-\r
+ end process;
+
end soda_reply_pkt_builder_arch;
\ No newline at end of file
SYSCLK : in std_logic; -- fabric clock
SODACLK : in std_logic; -- clock for data to serdes
RESET : in std_logic; -- synchronous reset
-\r
+
SODA_BURST_PULSE_IN : in std_logic := '0'; --
SODA_CYCLE_IN : in std_logic := '0'; --
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
RX_DLM_IN : in std_logic;
TX_DLM_OUT : out std_logic;
- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
TX_DLM_PREVIEW_OUT : out std_logic := '0'; --PL!
LINK_PHASE_IN : in std_logic := '0'; --PL!
signal calib_data_valid_S : std_logic;
signal calibration_time_s : std_logic_vector(15 downto 0) := (others => '0');
signal calib_register_s : std_logic_vector(31 downto 0) := (others => '0');
--- signal calib_register_rst_s : std_logic := '0'; -- read of calibration register resets contents to 0\r
+-- signal calib_register_rst_s : std_logic := '0'; -- read of calibration register resets contents to 0
signal reply_timeout_error_S : std_logic;
signal channel_timeout_status_S : std_logic;
signal downstream_error_S : std_logic;
signal report_error_S : std_logic;
-\r
+
signal dead_channel_S : std_logic;
signal soda_reset_S : std_logic;
signal soda_enable_S : std_logic;
+-- PS synchronize calib_data_valid_S
+ signal calib_data_valid_SYSCLK_S : std_logic;
+
+begin
-begin\r
-\r
superburst_gen : soda_superburst_generator
generic map(BURST_COUNT => 16)
port map(
ENABLE => soda_enable_S,
SODA_BURST_PULSE_IN => SODA_BURST_PULSE_IN,
START_OF_SUPERBURST_OUT => start_of_superburst_S,
- SUPER_BURST_NR_OUT => super_burst_nr_S,\r
+ SUPER_BURST_NR_OUT => super_burst_nr_S,
SODA_CMD_WINDOW_OUT => soda_cmd_window_S
);
--Internal Connection
LINK_PHASE_IN => LINK_PHASE_IN, --link_phase_S, PL!
SODA_CYCLE_IN => SODA_CYCLE_IN,
- SODA_CMD_WINDOW_IN => soda_cmd_window_S,\r
+ SODA_CMD_WINDOW_IN => soda_cmd_window_S,
SODA_CMD_STROBE_IN => soda_cmd_strobe_sodaclk_S, --soda_send_cmd_S, goes with removal of SODA_CMD_FLOWCTRL
START_OF_SUPERBURST => start_of_superburst_S,
SUPER_BURST_NR_IN => super_burst_nr_S,
SODA_CMD_WORD_IN => soda_cmd_word_S,
EXPECTED_REPLY_OUT => expected_reply_S,
- SEND_TIME_CAL_OUT => start_calibration_S,\r
+ SEND_TIME_CAL_OUT => start_calibration_S,
TX_DLM_PREVIEW_OUT => TX_DLM_PREVIEW_OUT,
TX_DLM_OUT => TX_DLM_OUT,
TX_DLM_WORD_OUT => TX_DLM_WORD_OUT
START_CALIBRATION => start_calibration_S,
END_CALIBRATION => reply_data_valid_S,
VALID_OUT => calib_data_valid_S,
- CALIB_TIME_OUT => calibration_time_S,\r
+ CALIB_TIME_OUT => calibration_time_S,
TIMEOUT_ERROR => reply_timeout_error_S -- timeout because no reply was received
);
+
+ --PS: synchronize calib_data_valid_S (not very important: calibration time is internal in FPGA)
+ calib_data_valid_posedge_to_pulse: posedge_to_pulse
+ port map(
+ IN_CLK => SODACLK,
+ OUT_CLK => SYSCLK,
+ CLK_EN => '1',
+ SIGNAL_IN => calib_data_valid_S,
+ PULSE_OUT => calib_data_valid_SYSCLK_S
+ );
+
sodasource_calib_timeout_proc : process(SYSCLK) -- converting to sysclk domain
begin
if rising_edge(SYSCLK) then
if( RESET = '1' ) then
- calib_register_S <= (others => '0');\r
+ calib_register_S <= (others => '0');
channel_timeout_status_S <= '0';
downstream_error_S <= '0';
channel_timeout_status_S <= '0';
report_error_S <= '0';
- elsif (calib_data_valid_S = '1') then -- calibration finished in time
- calib_register_S(15 downto 0) <= calibration_time_S;\r
+ elsif (calib_data_valid_SYSCLK_S = '1') then -- calibration finished in time
+ calib_register_S(15 downto 0) <= calibration_time_S;
channel_timeout_status_S <= '0';
elsif (reply_data_valid_S = '1') then -- the reply was correct
- channel_timeout_status_S <= '0';\r
- if (reply_OK_S = '1') then\r
- downstream_error_S <= '0';\r
- elsif (dead_channel_S = '0') then\r
- downstream_error_S <= '1';\r
+ channel_timeout_status_S <= '0';
+ if (reply_OK_S = '1') then
+ downstream_error_S <= '0';
+ elsif (dead_channel_S = '0') then
+ downstream_error_S <= '1';
report_error_S <= '1'; -- set REPORT_ERROR status-bit
end if;
elsif ((reply_timeout_error_S = '1') and (reply_OK_S = '1')) then
channel_timeout_status_S <= '1';
downstream_error_S <= '1'; -- set CALIBRATION_TIMEOUT_ERROR status-bit
- report_error_S <= '1'; -- set REPORT_ERROR status-bit\r
- elsif (report_error_S = '1') then -- check if slowcontrol wants to reset errors\r
+ report_error_S <= '1'; -- set REPORT_ERROR status-bit
+ elsif (report_error_S = '1') then -- check if slowcontrol wants to reset errors
channel_timeout_status_S <= '0';
downstream_error_S <= '0'; -- set CALIBRATION_TIMEOUT_ERROR status-bit
report_error_S <= '0'; -- set REPORT_ERROR status-bit
end if;
end if;
end process;
-\r
+
---------------------------------------------------------
-- RegIO Statemachine
---------------------------------------------------------
SIGNAL_IN => soda_cmd_strobe_S,
PULSE_OUT => soda_cmd_strobe_sodaclk_S
);
-\r
-\r
+
+
---------------------------------------------------------
-- Control bits --
---------------------------------------------------------
CTRL_STATUS_register_S(14 downto 2) <= (others => '0');
CTRL_STATUS_register_S(1) <= downstream_error_S;
CTRL_STATUS_register_S(0) <= channel_timeout_status_S;
-\r
+
---------------------------------------------------------
-- data handling --
---------------------------------------------------------
end if;
end if;
end process THE_WRITE_REG_PROC;
-\r
+
-- register read
THE_READ_REG_PROC: process( SYSCLK )
SODA_DATA_OUT <= buf_bus_data_out;
SODA_ACK_OUT <= bus_ack;
+
end architecture;
burst_counter_S <= cCYCLES_PER_BURST;
SODA_40MHZ_CYCLE_OUT <= '0';
SODA_BURST_PULSE_OUT <= '0';
- elsif (cycle_counter_S=0) then\r
+ elsif (cycle_counter_S=0) then
cycle_counter_S <= cCLOCKS_PER_CYCLE;
SODA_40MHZ_CYCLE_OUT <= '1';
if (burst_counter_S=0) then
else
burst_counter_S <= burst_counter_S - 1;
SODA_BURST_PULSE_OUT <= '0';
- end if;\r
- else\r
+ end if;
+ else
cycle_counter_S <= cycle_counter_S - 1;
SODA_40MHZ_CYCLE_OUT <= '0';
end if;
+++ /dev/null
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- <Vendor>Lattice</Vendor>
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- <SVFVendor>JTAG STANDARD</SVFVendor>
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- <Operation>Fast Program</Operation>
- <Option>
- <SVFVendor>JTAG STANDARD</SVFVendor>
- <IOState>HighZ</IOState>
- <PreloadLength>1326</PreloadLength>
- <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
- <OverideUES value="TRUE"/>
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- <SVFProcessor>ispVM</SVFProcessor>
- <Usercode>0x00000000</Usercode>
- </Option>
- </Device>
- <Device>
- <SelectedProg value="TRUE"/>
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- <Vendor>Lattice</Vendor>
- <Family>ispCLOCK</Family>
- <Name>ispPAC-CLK5410D</Name>
- <IDCode>0x00190043</IDCode>
- <Package>64-pin QFNS</Package>
- <PON>ispPAC-CLK5410D-XXSN64C</PON>
- <Bypass>
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- <InstrVal>11111111</InstrVal>
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- <Operation>Erase,Program,Verify</Operation>
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- <SVFVendor>JTAG STANDARD</SVFVendor>
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- <IOVectorData>0x00000000</IOVectorData>
- <OverideUES value="TRUE"/>
- <TCKFrequency>1.000000 MHz</TCKFrequency>
- <SVFProcessor>ispVM</SVFProcessor>
- <Usercode>0xFFFFFFFF</Usercode>
- </Option>
- </Device>
- <Device>
- <SelectedProg value="FALSE"/>
- <Pos>7</Pos>
- <Vendor>Lattice</Vendor>
- <Family>ispCLOCK</Family>
- <Name>ispPAC-CLK5410D</Name>
- <IDCode>0x00190043</IDCode>
- <Package>64-pin QFNS</Package>
- <PON>ispPAC-CLK5410D-XXSN64C</PON>
- <Bypass>
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- <InstrVal>11111111</InstrVal>
- <BScanLen>1</BScanLen>
- <BScanVal>0</BScanVal>
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- <File>/local/lemmens/lattice/trb3/base/clockmanager/CM2.jed</File>
- <FileTime>04/10/13 09:35:41</FileTime>
- <JedecChecksum>0x18FB</JedecChecksum>
- <Operation>Erase,Program,Verify</Operation>
- <Option>
- <SVFVendor>JTAG STANDARD</SVFVendor>
- <IOState>HighZ</IOState>
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- <IOVectorData>0x00000000</IOVectorData>
- <OverideUES value="TRUE"/>
- <TCKFrequency>1.000000 MHz</TCKFrequency>
- <SVFProcessor>ispVM</SVFProcessor>
- <Usercode>0xFFFFFFFF</Usercode>
- </Option>
- </Device>
- </Chain>
- <ProjectOptions>
- <Program>SEQUENTIAL</Program>
- <Process>ENTIRED CHAIN</Process>
- <OperationOverride>No Override</OperationOverride>
- <StartTAP>TLR</StartTAP>
- <EndTAP>TLR</EndTAP>
- <VerifyUsercode value="FALSE"/>
- </ProjectOptions>
- <CableOptions>
- <CableName>USB</CableName>
- <PortAdd>EzUSB-0</PortAdd>
- <JTAGPinSetting>
- TRST ABSENT;
- ISPEN ABSENT;
- </JTAGPinSetting>
- </CableOptions>
-</ispXCF>
+++ /dev/null
-<?xml version='1.0' encoding='utf-8' ?>
-<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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- <Comment></Comment>
- <Chain>
- <Comm>JTAG</Comm>
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- <Family>LatticeECP3</Family>
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- <PON>LFE3-150EA</PON>
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- <TCKFrequency>1.000000 MHz</TCKFrequency>
- <SVFProcessor>SVF Processor</SVFProcessor>
- <AccessMode>JTAG</AccessMode>
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- <Vendor>Lattice</Vendor>
- <Family>LatticeECP3</Family>
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- <Vendor>Lattice</Vendor>
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- <AccessMode>JTAG</AccessMode>
- </Option>
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- <Pos>7</Pos>
- <Vendor>Lattice</Vendor>
- <Family>ispCLOCK</Family>
- <Name>ispPAC-CLK5410D</Name>
- <IDCode>0x00190043</IDCode>
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- <SVFVendor>JTAG STANDARD</SVFVendor>
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- <IOVectorData>0x00000000</IOVectorData>
- <OverideUES value="TRUE"/>
- <TCKFrequency>1.000000 MHz</TCKFrequency>
- <SVFProcessor>ispVM</SVFProcessor>
- <AccessMode>JTAG</AccessMode>
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- </Device>
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- <VerifyUsercode value="FALSE"/>
- </ProjectOptions>
- <CableOptions>
- <CableName>USB</CableName>
- <PortAdd>EzUSB-0</PortAdd>
- </CableOptions>
-</ispXCF>
jspc29 / soda.git / commitdiff