end component lattice_scm_bram_fifo;
signal fifo_write_enable, fifo_read_enable : std_logic;
- signal fifo_data_out : std_logic_vector(17 downto 0);
- signal fifo_empty, fifo_full : std_logic;
-
+ signal fifo_data_out : std_logic_vector(17 downto 0);
+ signal fifo_empty, fifo_full : std_logic;
+ signal buf_EMPTY_OUT, next_EMPTY_OUT : std_logic;
+ type state_t is (EMPTY, BUFFER_FULL, BRAM_NOT_EMPTY);
+ signal state, next_state : state_t;
+ signal next_DATA_OUT, buf_DATA_OUT : std_logic_vector(WIDTH-1 downto 0);
+ signal last_fifo_empty : std_logic;
begin
gen_BRAM : if (DEPTH = 8 and WIDTH = 18) and FORCE_LUT = 0 generate
-
- fifo_write_enable <= WRITE_ENABLE_IN;
FULL_OUT <= fifo_full;
+ EMPTY_OUT <= buf_EMPTY_OUT;
+ DATA_OUT <= buf_DATA_OUT;
+
+ process(CLK)
+ begin
+ next_DATA_OUT <= buf_DATA_OUT;
+ next_EMPTY_OUT <= buf_EMPTY_OUT;
+ next_state <= state;
+ fifo_write_enable <= '0';
+ fifo_read_enable <= '0';
+ case state is
+ when EMPTY =>
+ next_DATA_OUT <= DATA_IN;
+ if WRITE_ENABLE_IN = '1' then
+ next_state <= BUFFER_FULL;
+ next_EMPTY_OUT <= '0';
+ end if;
+ when BUFFER_FULL =>
+ if READ_ENABLE_IN = '1' and WRITE_ENABLE_IN = '0' then
+ next_state <= EMPTY;
+ next_EMPTY_OUT <= '1';
+ elsif READ_ENABLE_IN = '1' and WRITE_ENABLE_IN = '1' then
+ next_DATA_OUT <= DATA_IN;
+ elsif READ_ENABLE_IN = '0' and WRITE_ENABLE_IN = '1' then
+ fifo_write_enable <= '1';
+ next_state <= BRAM_NOT_EMPTY;
+ end if;
+ when BRAM_NOT_EMPTY =>
+ if WRITE_ENABLE_IN <= '1' then
+ fifo_write_enable <= '1';
+ end if;
+ fifo_read_enable <= READ_ENABLE_IN;
+ fifo_write_enable <= WRITE_ENABLE_IN;
+ next_DATA_OUT <= fifo_data_out;
+ if last_fifo_empty <= '0' and fifo_empty <= '1' then
+ next_state <= BUFFER_FULL;
+ end if;
+ end case;
+ end process;
+
+
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
buf_DATA_OUT <= (others => '0');
- elsif last_fifo_read_enable = '1' then
- buf_DATA_OUT <= fifo_data_out;
+ state <= EMPTY;
+ buf_EMPTY_OUT <= '1';
+ else
+ buf_DATA_OUT <= next_DATA_OUT;
+ state <= next_state;
+ buf_EMPTY_OUT <= next_EMPTY_OUT;
end if;
end if;
end process;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ last_fifo_empty <= '0';
+ else
+ last_fifo_empty <= fifo_empty;
+ end if;
+ end if;
+ end process;
+
+
+
end architecture;
\ No newline at end of file
constant c_DATA_WIDTH : integer := 16;
constant c_NUM_WIDTH : integer := 2;
constant c_MUX_WIDTH : integer := 3;
- constant c_USE_ACKNOWLEDGE : channel_config_t := (1,1,1,1);
- constant c_FORCE_REPLY : channel_config_t := (1,1,1,1);
- constant c_USE_REPLY_CHANNEL : channel_config_t := (1,1,1,1);
+
--assigning channel names
constant c_TRG_LVL1_CHANNEL : integer := 0;
constant c_DATA_CHANNEL : integer := 2;
constant c_SLOW_CTRL_CHANNEL : integer := 3;
---standard values
- constant std_SBUF_VERSION : integer := 0;
- constant std_IBUF_SECURE_MODE : integer := 1;
- constant std_USE_ACKNOWLEDGE : integer := 1;
- constant std_USE_REPLY_CHANNEL: integer := 1;
- constant std_FIFO_DEPTH : integer := 1;
- constant std_DATA_COUNT_WIDTH : integer := 5; --max 7
- constant std_TERM_SECURE_MODE : integer := 0;
- constant std_MUX_SECURE_MODE : integer := 0;
- constant std_FORCE_REPLY : integer := 1;
--api_type generic
constant c_API_ACTIVE : integer := 1;
constant c_NO : integer := 0;
+--standard values
+ constant std_SBUF_VERSION : integer := c_SBUF_FULL;
+ constant std_IBUF_SECURE_MODE : integer := c_SECURE_MODE;
+ constant std_USE_ACKNOWLEDGE : integer := c_YES;
+ constant std_USE_REPLY_CHANNEL: integer := c_YES;
+ constant std_FIFO_DEPTH : integer := c_SMALL;
+ constant std_DATA_COUNT_WIDTH : integer := 5; --max 7
+ constant std_TERM_SECURE_MODE : integer := c_NO;
+ constant std_MUX_SECURE_MODE : integer := c_NO;
+ constant std_FORCE_REPLY : integer := c_YES;
+ constant cfg_USE_ACKNOWLEDGE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ constant cfg_FORCE_REPLY : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ constant cfg_USE_REPLY_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+
+
--packet types
constant TYPE_DAT : std_logic_vector(2 downto 0) := "000";
constant TYPE_HDR : std_logic_vector(2 downto 0) := "001";