--- /dev/null
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--- /dev/null
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+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/tx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="trb3_periph_sodasource"/>
+ </Source>
+ <Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="soda_client1.sty"/>
+</BaliProject>
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+# SYSCONFIG MCCLK_FREQ = 2.5;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25;
+
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3";
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+
+
+
+
+#################################################################
+# To central FPGA
+#################################################################
+
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
+LOCATE COMP "FPGA5_COMM_10" SITE "V10";
+LOCATE COMP "FPGA5_COMM_11" SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+LOCATE COMP "TEST_LINE_0" SITE "A5";
+LOCATE COMP "TEST_LINE_1" SITE "A6";
+LOCATE COMP "TEST_LINE_2" SITE "G8";
+LOCATE COMP "TEST_LINE_3" SITE "F9";
+LOCATE COMP "TEST_LINE_4" SITE "D9";
+LOCATE COMP "TEST_LINE_5" SITE "D10";
+LOCATE COMP "TEST_LINE_6" SITE "F10";
+LOCATE COMP "TEST_LINE_7" SITE "E10";
+LOCATE COMP "TEST_LINE_8" SITE "A8";
+LOCATE COMP "TEST_LINE_9" SITE "B8";
+LOCATE COMP "TEST_LINE_10" SITE "G10";
+LOCATE COMP "TEST_LINE_11" SITE "G9";
+LOCATE COMP "TEST_LINE_12" SITE "C9";
+LOCATE COMP "TEST_LINE_13" SITE "C10";
+LOCATE COMP "TEST_LINE_14" SITE "H10";
+LOCATE COMP "TEST_LINE_15" SITE "H11";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+
+#################################################################
+# Connection to AddOn
+#################################################################
+
+LOCATE COMP "LED_LINKOK_1" SITE "P1"; #DQLL0_0 #1
+LOCATE COMP "LED_RX_1" SITE "P2"; #DQLL0_1 #3
+LOCATE COMP "LED_TX_1" SITE "T2"; #DQLL0_2 #5
+LOCATE COMP "SFP_MOD0_1" SITE "U3"; #DQLL0_3 #7
+LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9
+LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11
+LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13
+LOCATE COMP "SFP_TXDIS_1" SITE "P3"; #DQSLL0_C #15
+LOCATE COMP "SFP_LOS_1" SITE "P5"; #DQLL0_6 #17
+LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19
+
+LOCATE COMP "LED_LINKOK_2" SITE "N5"; #DQLL0_8 #21
+LOCATE COMP "LED_RX_2" SITE "N6"; #DQLL0_9 #23
+LOCATE COMP "LED_TX_2" SITE "AC2"; #DQLL2_0 #25
+LOCATE COMP "SFP_MOD0_2" SITE "AC3"; #DQLL2_1 #27
+LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29
+LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31
+LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33
+LOCATE COMP "SFP_TXDIS_2" SITE "AA2"; #DQLL2_5 #35
+LOCATE COMP "SFP_LOS_2" SITE "W7"; #DQLL2_T #37 #should be DQSLL2
+LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2
+
+LOCATE COMP "LED_LINKOK_3" SITE "AD1"; #DQLL3_0 #2
+LOCATE COMP "LED_RX_3" SITE "AD2"; #DQLL3_1 #4
+LOCATE COMP "LED_TX_3" SITE "AB5"; #DQLL3_2 #6
+LOCATE COMP "SFP_MOD0_3" SITE "AB6"; #DQLL3_3 #8
+LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10
+LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12
+LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
+LOCATE COMP "SFP_TXDIS_3" SITE "Y7"; #DQLL3_C #16 #should be DQSLL3
+LOCATE COMP "SFP_LOS_3" SITE "AA3"; #DQLL3_6 #18
+LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20
+
+LOCATE COMP "LED_LINKOK_4" SITE "W8"; #DQLL3_8 #22
+LOCATE COMP "LED_RX_4" SITE "W9"; #DQLL3_9 #24
+LOCATE COMP "LED_TX_4" SITE "V1"; #DQLL1_0 #26
+LOCATE COMP "SFP_MOD0_4" SITE "U2"; #DQLL1_1 #28
+LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30
+LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32
+LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34
+LOCATE COMP "SFP_TXDIS_4" SITE "R3"; #DQLL1_5 #36
+LOCATE COMP "SFP_LOS_4" SITE "T3"; #DQSLL1_T #38
+LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40
+
+
+
+LOCATE COMP "LED_LINKOK_5" SITE "W23"; #DQLR1_0 #169
+LOCATE COMP "LED_RX_5" SITE "W22"; #DQLR1_1 #171
+LOCATE COMP "LED_TX_5" SITE "AA25"; #DQLR1_2 #173
+LOCATE COMP "SFP_MOD0_5" SITE "Y24"; #DQLR1_3 #175
+LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177
+LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179
+LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181
+LOCATE COMP "SFP_TXDIS_5" SITE "W20"; #DQSLR1_C #183
+LOCATE COMP "SFP_LOS_5" SITE "AA24"; #DQLR1_6 #185
+LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187
+
+LOCATE COMP "LED_LINKOK_6" SITE "R25"; #DQLR2_0 #170
+LOCATE COMP "LED_RX_6" SITE "R26"; #DQLR2_1 #172
+LOCATE COMP "LED_TX_6" SITE "T25"; #DQLR2_2 #174
+LOCATE COMP "SFP_MOD0_6" SITE "T24"; #DQLR2_3 #176
+LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178
+LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180
+LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182
+LOCATE COMP "SFP_TXDIS_6" SITE "V22"; #DQSLR2_C #184
+LOCATE COMP "SFP_LOS_6" SITE "U24"; #DQLR2_6 #186
+LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188
+
+
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
+LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
+LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
+LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+
+LOCATE COMP "FLASH_CLK" SITE "B12";
+LOCATE COMP "FLASH_CS" SITE "E11";
+LOCATE COMP "FLASH_DIN" SITE "E12";
+LOCATE COMP "FLASH_DOUT" SITE "A12";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP "PROGRAMN" SITE "B11";
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20";
+LOCATE COMP "CODE_LINE_0" SITE "Y21";
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14";
+IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12";
+LOCATE COMP "LED_ORANGE" SITE "G13";
+LOCATE COMP "LED_RED" SITE "A15";
+LOCATE COMP "LED_YELLOW" SITE "A16";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;\r
+\r
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+ SYSCONFIG MCCLK_FREQ = 20;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Reset Nets
+#################################################################
+GSR_NET NET "GSR_N";
+
+
+
+
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
+
+LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+
+
+REGION "MEDIA_UPLINK" "R90C95D" 13 25;
+REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
+REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;
+REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE;
+
+LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
+LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
+
+LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;
+
+
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns;
+MULTICYCLE TO CELL "THE_SODA_SOURCE/SCI_DATA_OUT*" 20 ns;
+MULTICYCLE TO CELL "THE_SODA_SOURCE/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_SODA_SOURCE/sci*" 20 ns;
+MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns;
+
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
);
end component;
+ component soda_start_of_burst_faker
+ generic(
+ cCLOCK_PERIOD : natural range 1 to 20 := 5; -- clock-period in ns
+ cBURST_PERIOD : natural range 1 to 2400 := 2400 -- burst-period in ns
+ );
+ port(
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ SODA_BURST_PULSE_OUT : out std_logic := '0'
+ );
+ end component;
+\r
end package;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+use work.soda_components.all;
+
+entity soda_source is
+ port(
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
+ SODA_BURST_PULSE_IN : in std_logic := '0'; --
+
+ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ RX_DLM_IN : in std_logic;
+ TX_DLM_OUT : out std_logic;
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+
+ SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
+ SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
+ SODA_READ_IN : in std_logic := '0';
+ SODA_WRITE_IN : in std_logic := '0';
+ SODA_ACK_OUT : out std_logic := '0';
+ LEDS_OUT : out std_logic_vector(3 downto 0);
+ TEST_LINE : out std_logic_vector(15 downto 0);
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG
+ );
+end soda_source;
+
+architecture Behavioral of soda_source is
+
+ --SODA
+ signal link_phase_S : natural range 0 to 1 := 0;
+ signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
+ signal soda_cmd_strobe_S : std_logic := '0';
+ signal start_of_superburst_S : std_logic := '0';
+ signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
+
+-- Signals
+ type t_STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
+ signal CURRENT_STATE, NEXT_STATE: t_STATES;
+
+ signal last_packet_sent_S : t_PACKET_TYPE_SENT := c_NO_PACKET;
+
+ -- slave bus signals
+ signal bus_ack_x : std_logic;
+ signal bus_ack : std_logic;
+ signal store_wr_x : std_logic;
+ signal store_wr : std_logic;
+ signal store_rd_x : std_logic;
+ signal store_rd : std_logic;
+ signal buf_bus_data_out : std_logic_vector(31 downto 0);
+
+ signal ledregister_i : std_logic_vector(31 downto 0);
+ signal test_line_i : std_logic_vector(31 downto 0);
+
+ signal reply_valid_S : std_logic;
+ signal expected_reply_S : std_logic_vector(7 downto 0);
+ signal reply_OK_S : std_logic;
+ signal start_calibration_S : std_logic;
+
+ signal calibration_valid_s : std_logic;
+ signal calibration_time_s : std_logic_vector(7 downto 0) := (others => '0');
+ signal calib_register_s : std_logic_vector(31 downto 0) := (others => '0');
+
+begin
+
+ superburst_gen : soda_superburst_generator
+ generic map(BURST_COUNT => 16)
+ port map(
+ SYSCLK => SYSCLK,
+ RESET => RESET,
+ CLEAR => '0',
+ CLK_EN => CLK_EN,
+ --Internal Connection
+ SODA_BURST_PULSE_IN => SODA_BURST_PULSE_IN,
+ START_OF_SUPERBURST => start_of_superburst_S,
+ SUPER_BURST_NR_OUT => super_burst_nr_S
+ );
+
+ packet_builder : soda_packet_builder
+ port map(
+ SYSCLK => SYSCLK,
+ RESET => RESET,
+ CLEAR => '0',
+ CLK_EN => CLK_EN,
+ --Internal Connection
+ LINK_PHASE => link_phase_S,
+ SODA_CMD_STROBE_IN => soda_cmd_strobe_S,
+ START_OF_SUPERBURST => start_of_superburst_S,
+ SUPER_BURST_NR_IN => super_burst_nr_S,
+ SODA_CMD_WORD_IN => soda_cmd_word_S,
+ EXPECTED_REPLY_OUT => expected_reply_S,
+ TIME_CAL_OUT => start_calibration_S,
+ TX_DLM_OUT => TX_DLM_OUT,
+ TX_DLM_WORD_OUT => TX_DLM_WORD_OUT
+ );
+
+ src_reply_handler : soda_reply_handler
+ port map(
+ SYSCLK => SYSCLK,
+ RESET => RESET,
+ CLEAR => '0',
+ CLK_EN => '1',
+ --Internal Connection
+ LAST_PACKET => last_packet_sent_S,
+ EXPECTED_REPLY_IN => expected_reply_S,
+ RX_DLM_IN => RX_DLM_IN,
+ RX_DLM_WORD_IN => RX_DLM_WORD_IN,
+ REPLY_VALID_OUT => reply_valid_S,\r
+ REPLY_OK_OUT => reply_OK_S
+ );
+\r
+ src_calibration_timer : soda_calibration_timer\r
+ port map(
+ SYSCLK => SYSCLK,
+ RESET => RESET,
+ CLEAR => '0',
+ CLK_EN => '1',
+ --Internal Connection
+ START_CALIBRATION => start_calibration_S,\r
+ END_CALIBRATION => reply_valid_S,\r
+ CALIB_VALID_OUT => calibration_valid_S,
+ CALIB_TIME_OUT => calibration_time_S\r
+ );
+
+ src_store_calib_proc : process(SYSCLK)
+ begin
+ if rising_edge(SYSCLK) then
+ if( RESET = '1' ) then
+ calib_register_S <= (others => '0');
+ else
+ calib_register_S(7 downto 0) <= calibration_time_S;
+ end if;
+ end if;
+ end process;
+-----------------------------------------------------------
+-- Phase fsm for 16-bit transmissions --
+-----------------------------------------------------------
+ phase_fsm_proc : process(SYSCLK)
+ begin
+ if rising_edge(SYSCLK) then
+ if( RESET = '1' ) then
+ link_phase_S <= 0;
+ elsif (link_phase_S < 1) then
+ link_phase_S <= link_phase_S + 1;
+ else
+ link_phase_S <= 0;
+ end if;
+ end if;
+ end process;
+
+-----------------------------------------------------------
+-- Transmission history for reply-checking --
+-----------------------------------------------------------
+ packet_history_proc : process(SYSCLK)
+ begin
+ if rising_edge(SYSCLK) then
+ if( RESET = '1' ) then
+ last_packet_sent_S <= c_NO_PACKET;
+ elsif (start_of_superburst_S='1') then
+ last_packet_sent_S <= c_BST_PACKET;
+ elsif (soda_cmd_strobe_S='1') then
+ last_packet_sent_S <= c_CMD_PACKET;
+ end if;
+ end if;
+ end process;
+
+---------------------------------------------------------
+-- RegIO Statemachine
+---------------------------------------------------------
+ STATE_MEM: process( SYSCLK)
+ begin
+ if( rising_edge(SYSCLK) ) then
+ if( RESET = '1' ) then
+ CURRENT_STATE <= SLEEP;
+ bus_ack <= '0';
+ store_wr <= '0';
+ store_rd <= '0';
+ else
+ CURRENT_STATE <= NEXT_STATE;
+ bus_ack <= bus_ack_x;
+ store_wr <= store_wr_x;
+ store_rd <= store_rd_x;
+ end if;
+ end if;
+ end process STATE_MEM;
+
+-- Transition matrix
+ TRANSFORM: process(CURRENT_STATE, SODA_READ_IN, SODA_WRITE_IN )
+ begin
+ NEXT_STATE <= SLEEP;
+ bus_ack_x <= '0';
+ store_wr_x <= '0';
+ store_rd_x <= '0';
+ case CURRENT_STATE is
+ when SLEEP =>
+ if (SODA_READ_IN = '1') then
+ NEXT_STATE <= RD_RDY;
+ store_rd_x <= '1';
+ elsif(SODA_WRITE_IN = '1') then
+ NEXT_STATE <= WR_RDY;
+ store_wr_x <= '1';
+ else
+ NEXT_STATE <= SLEEP;
+ end if;
+ when RD_RDY =>
+ NEXT_STATE <= RD_ACK;
+ when WR_RDY =>
+ NEXT_STATE <= WR_ACK;
+ when RD_ACK =>
+ if( SODA_READ_IN = '0' ) then
+ NEXT_STATE <= DONE;
+ bus_ack_x <= '1';
+ else
+ NEXT_STATE <= RD_ACK;
+ bus_ack_x <= '1';
+ end if;
+ when WR_ACK =>
+ if( SODA_WRITE_IN = '0' ) then
+ NEXT_STATE <= DONE;
+ bus_ack_x <= '1';
+ else
+ NEXT_STATE <= WR_ACK;
+ bus_ack_x <= '1';
+ end if;
+ when DONE =>
+ NEXT_STATE <= SLEEP;
+ when others =>
+ NEXT_STATE <= SLEEP;
+ end case;
+end process TRANSFORM;
+
+---------------------------------------------------------
+-- data handling --
+---------------------------------------------------------
+-- For sim purposes the SOURCE gets addresses 00XX
+-- register write
+ THE_WRITE_REG_PROC: process( SYSCLK )
+ begin
+ if( rising_edge(SYSCLK) ) then
+ if ( RESET = '1' ) then
+ soda_cmd_strobe_S <= '0';
+ soda_cmd_word_S <= (others => '0');
+ LEDregister_i <= (others => '0');
+ TEST_LINE_i <= (others => '0');
+ elsif( (store_wr = '1') and (SODA_ADDR_IN = "0000") ) then\r
+ soda_cmd_strobe_S <= '1';
+ soda_cmd_word_S <= SODA_DATA_IN(30 downto 0);
+ elsif( (store_wr = '1') and (SODA_ADDR_IN = "0001") ) then
+ LEDregister_i <= SODA_DATA_IN;
+ elsif( (store_wr = '1') and (SODA_ADDR_IN = "0010") ) then
+ TEST_LINE_i <= SODA_DATA_IN;
+ else\r
+ soda_cmd_strobe_S <= '0';
+ end if;
+ end if;
+ end process THE_WRITE_REG_PROC;
+
+ LEDS_OUT <= LEDregister_i(3 downto 0);
+ TEST_LINE <= TEST_LINE_i(15 downto 0);
+
+-- register read
+ THE_READ_REG_PROC: process( SYSCLK )
+ begin
+ if( rising_edge(SYSCLK) ) then
+ if ( RESET = '1' ) then
+ buf_bus_data_out <= (others => '0');
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "0000") ) then
+ buf_bus_data_out <= '0' & soda_cmd_word_S;
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "0001") ) then
+ buf_bus_data_out <= calib_register_S;
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "0001") ) then
+ buf_bus_data_out <= LEDregister_i;
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "0010") ) then
+ buf_bus_data_out <= TEST_LINE_i;
+ end if;
+ end if;
+ end process THE_READ_REG_PROC;
+
+-- output signals
+ SODA_DATA_OUT <= buf_bus_data_out;
+ SODA_ACK_OUT <= bus_ack;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+use work.trb3_components.all;
+use work.soda_components.all;
+use work.med_sync_define.all;
+use work.version.all;
+
+entity trb3_periph_sodaclient is
+ generic(
+ SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
+ USE_125_MHZ : integer := c_NO;
+ CLOCK_FREQUENCY : integer := 100;
+ NUM_INTERFACES : integer := 2
+ );
+ port(
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+
+ --Trigger
+ --TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ --TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+ --Serdes Clocks - do not use
+ --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ --CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+
+ --serdes I/O - connect as you like, no real use
+ SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
+ SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
+
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+ --others yet undefined
+ --Connection to AddOn
+ LED_LINKOK : out std_logic_vector(6 downto 1);
+ LED_RX : out std_logic_vector(6 downto 1);
+ LED_TX : out std_logic_vector(6 downto 1);
+ SFP_MOD0 : in std_logic_vector(6 downto 1);
+ SFP_TXDIS : out std_logic_vector(6 downto 1);
+ SFP_LOS : in std_logic_vector(6 downto 1);
+ --SFP_MOD1 : inout std_logic_vector(6 downto 1);
+ --SFP_MOD2 : inout std_logic_vector(6 downto 1);
+ --SFP_RATESEL : out std_logic_vector(6 downto 1);
+ --SFP_TXFAULT : in std_logic_vector(6 downto 1);
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of LED_LINKOK : signal is false;
+ attribute syn_useioff of LED_TX : signal is false;
+ attribute syn_useioff of LED_RX : signal is false;
+ attribute syn_useioff of SFP_MOD0 : signal is false;
+ attribute syn_useioff of SFP_TXDIS : signal is false;
+ attribute syn_useioff of SFP_LOS : signal is false;
+ attribute syn_useioff of TEST_LINE : signal is false;
+
+ --important signals _with_ IO-FF
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+
+
+end entity;
+
+architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is
+ --Constants
+ constant REGIO_NUM_STAT_REGS : integer := 0;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
+
+ --Clock / Reset
+ signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+-- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ signal clk_sys_internal : std_logic;
+ signal clk_raw_internal : std_logic;
+ signal rx_clock_half : std_logic;
+ signal rx_clock_full : std_logic;
+ signal clk_tdc : std_logic;
+ signal time_counter, time_counter2 : unsigned(31 downto 0);
+ --Media Interface
+ signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+ signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+ signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+ signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(8 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_dataready_out : std_logic;
+ signal spimem_no_more_data_out : std_logic;
+ signal spimem_unknown_addr_out : std_logic;
+ signal spimem_write_ack_out : std_logic;
+
+ signal sci1_ack : std_logic;
+ signal sci1_write : std_logic;
+ signal sci1_read : std_logic;
+ signal sci1_data_in : std_logic_vector(7 downto 0);
+ signal sci1_data_out : std_logic_vector(7 downto 0);
+ signal sci1_addr : std_logic_vector(8 downto 0);
+ signal sci2_ack : std_logic;
+ signal sci2_nack : std_logic;
+ signal sci2_write : std_logic;
+ signal sci2_read : std_logic;
+ signal sci2_data_in : std_logic_vector(7 downto 0);
+ signal sci2_data_out : std_logic_vector(7 downto 0);
+ signal sci2_addr : std_logic_vector(8 downto 0);
+
+ --SODA
+ signal soda_ack : std_logic;
+-- signal soda_nack : std_logic;
+ signal soda_write : std_logic;
+ signal soda_read : std_logic;
+ signal soda_data_in : std_logic_vector(31 downto 0);
+ signal soda_data_out : std_logic_vector(31 downto 0);
+ signal soda_addr : std_logic_vector(3 downto 0);
+ signal soda_leds : std_logic_vector(3 downto 0);
+
+ --TDC
+ signal hit_in_i : std_logic_vector(63 downto 0);
+
+ signal soda_rx_clock_half : std_logic;
+ signal soda_rx_clock_full : std_logic;
+ signal tx_dlm_i : std_logic;
+ signal rx_dlm_i : std_logic;
+ signal tx_dlm_word : std_logic_vector(7 downto 0);
+ signal rx_dlm_word : std_logic_vector(7 downto 0);
+
+ --SODA
+ signal rst_S : std_logic;
+ signal clk_S : std_logic;
+ signal enable_S : std_logic := '0';
+ signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0');
+ signal soda_cmd_strobe_S : std_logic := '0';
+ signal SOS_S : std_logic := '0';
+ signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
+ signal SOB_S : std_logic := '0';
+ signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');
+ signal dlm_valid_S : std_logic;
+
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_sys_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+gen_200_PLL : if USE_125_MHZ = c_NO generate
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_RIGHT,
+ CLKOP => clk_sys_internal,
+ CLKOK => clk_raw_internal,
+ LOCK => pll_lock
+ );
+end generate;
+
+gen_125 : if USE_125_MHZ = c_YES generate
+ clk_sys_internal <= CLK_GPLL_LEFT;
+ clk_raw_internal <= CLK_GPLL_LEFT;
+end generate;
+
+gen_sync_clocks : if SYNC_MODE = c_YES generate
+ clk_sys_i <= rx_clock_half;
+-- clk_200_i <= rx_clock_full;
+end generate;
+
+gen_local_clocks : if SYNC_MODE = c_NO generate
+ clk_sys_i <= clk_sys_internal;
+-- clk_200_i <= clk_raw_internal;
+end generate;
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
+ USE_125_MHZ => USE_125_MHZ,
+ USE_CTC => c_NO,
+ USE_SLAVE => SYNC_MODE
+ )
+ port map(
+ CLK => clk_raw_internal,
+ SYSCLK => clk_sys_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out(15 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(15 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
+ REFCLK2CORE_OUT => open,
+ CLK_RX_HALF_OUT => rx_clock_half,
+ CLK_RX_FULL_OUT => rx_clock_full,
+
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_ADDON_RX(2),
+ SD_RXD_N_IN => SERDES_ADDON_RX(3),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(2),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(3),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
+ -- Status and control port
+ STAT_OP => med_stat_op(15 downto 0),
+ CTRL_OP => med_ctrl_op(15 downto 0),
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => (others => '0')
+ );
+
+
+---------------------------------------------------------------------------
+-- Hub
+---------------------------------------------------------------------------
+
+THE_HUB : trb_net16_hub_base
+ generic map (
+ HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),
+ IBUF_SECURE_MODE => c_YES,
+ MII_NUMBER => NUM_INTERFACES,
+ MII_IS_UPLINK => (0 => 1, others => 0),
+ MII_IS_DOWNLINK => (0 => 0, others => 1),
+ MII_IS_UPLINK_ONLY=> (0 => 1, others => 0),
+ INT_NUMBER => 0,
+ USE_ONEWIRE => c_YES,
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+-- COMPILE_TIME => VERSION_NUMBER_TIME,
+ HARDWARE_VERSION => x"91003200",
+ INIT_ENDPOINT_ID => x"0000",
+ INIT_ADDRESS => x"F355",
+ USE_VAR_ENDPOINT_ID => c_YES,
+ BROADCAST_SPECIAL_ADDR => x"45",
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY
+ )
+ port map (
+ CLK => clk_sys_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ --Media interfacces
+ MED_DATAREADY_OUT(NUM_INTERFACES*1-1 downto 0) => med_dataready_out,
+ MED_DATA_OUT(NUM_INTERFACES*16-1 downto 0) => med_data_out,
+ MED_PACKET_NUM_OUT(NUM_INTERFACES*3-1 downto 0) => med_packet_num_out,
+ MED_READ_IN(NUM_INTERFACES*1-1 downto 0) => med_read_in,
+ MED_DATAREADY_IN(NUM_INTERFACES*1-1 downto 0) => med_dataready_in,
+ MED_DATA_IN(NUM_INTERFACES*16-1 downto 0) => med_data_in,
+ MED_PACKET_NUM_IN(NUM_INTERFACES*3-1 downto 0) => med_packet_num_in,
+ MED_READ_OUT(NUM_INTERFACES*1-1 downto 0) => med_read_out,
+ MED_STAT_OP(NUM_INTERFACES*16-1 downto 0) => med_stat_op,
+ MED_CTRL_OP(NUM_INTERFACES*16-1 downto 0) => med_ctrl_op,
+
+ COMMON_STAT_REGS => common_stat_reg,
+ COMMON_CTRL_REGS => common_ctrl_reg,
+ MY_ADDRESS_OUT => open,
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT => regio_addr_out,
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
+ REGIO_DATA_OUT => regio_data_out,
+ REGIO_DATA_IN => regio_data_in,
+ REGIO_DATAREADY_IN => regio_dataready_in,
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ REGIO_TIMEOUT_OUT => regio_timeout_out,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+ ONEWIRE => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+ --Status ports (for debugging)
+ MPLEX_CTRL => (others => '0'),
+ CTRL_DEBUG => (others => '0'),
+ STAT_DEBUG => open
+ );
+
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
+ )
+ port map(
+ CLK => clk_sys_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ BUS_READ_ENABLE_OUT(0) => spimem_read_en,
+ BUS_READ_ENABLE_OUT(1) => sci1_read,
+ BUS_READ_ENABLE_OUT(2) => sci2_read,
+ BUS_READ_ENABLE_OUT(3) => soda_read,
+
+ BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
+ BUS_WRITE_ENABLE_OUT(1) => sci1_write,
+ BUS_WRITE_ENABLE_OUT(2) => sci2_write,
+ BUS_WRITE_ENABLE_OUT(3) => soda_write,
+
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
+ BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
+ BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
+ BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
+
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+ BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
+ BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
+ BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
+ BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
+
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_TIMEOUT_OUT(3) => open,
+
+ BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
+ BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
+ BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
+ BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
+
+ BUS_DATAREADY_IN(0) => spimem_dataready_out,
+ BUS_DATAREADY_IN(1) => sci1_ack,
+ BUS_DATAREADY_IN(2) => sci2_ack,
+ BUS_DATAREADY_IN(3) => soda_ack,
+
+ BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
+ BUS_WRITE_ACK_IN(1) => sci1_ack,
+ BUS_WRITE_ACK_IN(2) => sci2_ack,
+ BUS_WRITE_ACK_IN(3) => soda_ack,
+
+ BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_NO_MORE_DATA_IN(3) => '0',
+
+ BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => sci2_nack,
+ BUS_UNKNOWN_ADDR_IN(3) => '0',
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
+ port map(
+ CLK_IN => clk_sys_i,
+ RESET_IN => reset_i,
+
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_DATAREADY_OUT => spimem_dataready_out,
+ BUS_WRITE_ACK_OUT => spimem_write_ack_out,
+ BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
+ BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+
+ DO_REBOOT_IN => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN,
+
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SCK_OUT => FLASH_CLK,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SDI_IN => FLASH_DOUT
+ );
+
+
+---------------------------------------------------------------------------
+-- The synchronous interface for Soda tests
+---------------------------------------------------------------------------
+
+THE_SYNC_LINK : med_ecp3_sfp_sync
+ generic map(
+ SERDES_NUM => 0, --number of serdes in quad
+ IS_SYNC_SLAVE => c_NO
+ )
+ port map(
+ CLK => clk_raw_internal, --clk_200_i,
+ SYSCLK => clk_sys_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection for TrbNet data -> not used a.t.m.
+ MED_DATA_IN => med_data_out(31 downto 16),
+ MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),
+ MED_DATAREADY_IN => med_dataready_out(1),
+ MED_READ_OUT => med_read_in(1),
+ MED_DATA_OUT => med_data_in(31 downto 16),
+ MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
+ MED_DATAREADY_OUT => med_dataready_in(1),
+ MED_READ_IN => med_read_out(1),
+ CLK_RX_HALF_OUT => soda_rx_clock_half,
+ CLK_RX_FULL_OUT => soda_rx_clock_full,
+
+ RX_DLM => rx_dlm_i,
+ RX_DLM_WORD => rx_dlm_word,
+ TX_DLM => tx_dlm_i,
+ TX_DLM_WORD => tx_dlm_word,
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_ADDON_RX(0),
+ SD_RXD_N_IN => SERDES_ADDON_RX(1),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(0),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(1),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => SFP_MOD0(1),
+ SD_LOS_IN => SFP_LOS(1),
+ SD_TXDIS_OUT => SFP_TXDIS(1),
+
+ SCI_DATA_IN => sci2_data_in,
+ SCI_DATA_OUT => sci2_data_out,
+ SCI_ADDR => sci2_addr,
+ SCI_READ => sci2_read,
+ SCI_WRITE => sci2_write,
+ SCI_ACK => sci2_ack,
+ SCI_NACK => sci2_nack,
+ -- Status and control port
+ STAT_OP => med_stat_op(31 downto 16),
+ CTRL_OP => med_ctrl_op(31 downto 16),
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );
+
+
+---------------------------------------------------------------------------
+-- The Soda Central
+---------------------------------------------------------------------------
+\r
+ A_SODA_CLIENT : soda_client
+ port map(
+ SYSCLK => clk_S,
+ RESET => rst_S,
+ CLEAR => '0',
+ CLK_EN => '1',
+ --Internal Connection
+ RX_DLM_WORD_IN => rx_dlm_word,
+ RX_DLM_IN => rx_dlm_i,
+ TX_DLM_OUT => tx_dlm_i,
+ TX_DLM_WORD_OUT => tx_dlm_word,
+\r
+ SODA_DATA_IN => soda_data_in,
+ SODA_DATA_OUT => soda_data_out,
+ SODA_ADDR_IN => soda_addr,
+ SODA_READ_IN => soda_read,
+ SODA_WRITE_IN => soda_write,
+ SODA_ACK_OUT => soda_ack,
+ STAT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+-- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
+-- LED_YELLOW <= '1';
+-- LED_GREEN <= not med_stat_op(9);
+-- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
+ LED_ORANGE <= soda_leds(0);
+ LED_YELLOW <= soda_leds(1);
+ LED_GREEN <= soda_leds(2);
+ LED_RED <= soda_leds(3);
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------
+-- TEST_LINE(15 downto 0) <= (others => '0');
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ process
+ begin
+ wait until rising_edge(clk_sys_internal);
+ time_counter <= time_counter + 1;
+ end process;
+
+
+
+
+end trb3_periph_sodaclient_arch;
-- The Soda Central
---------------------------------------------------------------------------
-- tx_dlm_i <= '0';
--- tx_dlm_word <= x"00";
+-- tx_dlm_word <= x"00";\r
+THE_SOB_SOURCE : soda_start_of_burst_faker
+ port map(
+ SYSCLK => clk_sys_i,
+ RESET => reset_i,
+ SODA_BURST_PULSE_OUT => SOB_S
+ );
+
+
THE_SODA_SOURCE : soda_source
port map(
jspc29 / soda.git / commitdiff