changed uart ctrlbus interface to records

diff --git a/special/uart.vhd b/special/uart.vhd
index db69331fd6dca3e3bed86a6f50947cb5d3f08c2b..5c33cbfcb4682da2069e8503b0ca426c88073a21 100644 (file)
--- a/special/uart.vhd
+++ b/special/uart.vhd
@@ -20,15 +20,8 @@ entity uart is
     UART_RX : in  std_logic_vector(0 to OUTPUTS-1);
     UART_TX : out std_logic_vector(0 to OUTPUTS-1);
     
-    DATA_OUT  : out std_logic_vector(31 downto 0);
-    DATA_IN   : in  std_logic_vector(31 downto 0);
-    ADDR_IN   : in  std_logic_vector(15 downto 0);
-    WRITE_IN  : in  std_logic;
-    READ_IN   : in  std_logic;
-    ACK_OUT   : out std_logic;
-    EMPTY_OUT : out std_logic;
-    UNKWN_OUT : out std_logic;
-    DEBUG     : out std_logic_vector(15 downto 0)
+    BUS_RX  : in CTRLBUS_RX;
+    BUS_TX  : out CTRLBUS_TX
     );
 end entity;
 
@@ -99,7 +92,7 @@ THE_RX_FIFO : entity work.fifo_9x2k_oreg
 THE_TX_FIFO : entity work.fifo_9x2k_oreg
   port map(
     Clock => CLK,
-    Data  => DATA_IN(8 downto 0),
+    Data  => BUS_RX.data(8 downto 0),
     WrEn  => tx_fifo_write,
     RdEn  => tx_fifo_read,
     Reset => RESET,
@@ -110,10 +103,10 @@ THE_TX_FIFO : entity work.fifo_9x2k_oreg
 
 PROC_REGS : process begin
   wait until rising_edge(CLK);
-  UNKWN_OUT <= '0';
-  ACK_OUT   <= '0';
-  EMPTY_OUT <= '0';
-  DATA_OUT  <= (others => '0');
+  BUS_TX.unknown <= '0';
+  BUS_TX.ack     <= '0';
+  BUS_TX.nack    <= '0';
+  BUS_TX.data    <= (others => '0');
   
   tx_fifo_write <= '0';
   rx_fifo_read  <= '0';
@@ -121,35 +114,35 @@ PROC_REGS : process begin
   last2_rx_read <= last_rx_read;
   
   if last2_rx_read = '1' then
-    DATA_OUT(8 downto 0) <= rx_fifo_out;
-    ACK_OUT              <= '1';
-  elsif WRITE_IN = '1' then
-    if ADDR_IN(3 downto 0) = x"0" then
+    BUS_TX.data(8 downto 0) <= rx_fifo_out;
+    BUS_TX.ack              <= '1';
+  elsif BUS_RX.write = '1' then
+    if BUS_RX.addr(3 downto 0) = x"0" then
       tx_fifo_write <= not tx_fifo_full;
-      ACK_OUT       <= not tx_fifo_full;
-      EMPTY_OUT     <=     tx_fifo_full;
-    elsif ADDR_IN(3 downto 0) = x"1" then
-      clk_div  <= to_integer(unsigned(DATA_IN));
-      ACK_OUT  <= '1';
-    elsif ADDR_IN(3 downto 0) = x"2" then
-      out_sel  <= to_integer(unsigned(DATA_IN(3 downto 0)));
-      ACK_OUT  <= '1';
+      BUS_TX.ack    <= not tx_fifo_full;
+      BUS_TX.nack   <=     tx_fifo_full;
+    elsif BUS_RX.addr(3 downto 0) = x"1" then
+      clk_div  <= to_integer(unsigned(BUS_RX.data));
+      BUS_TX.ack  <= '1';
+    elsif BUS_RX.addr(3 downto 0) = x"2" then
+      out_sel  <= to_integer(unsigned(BUS_RX.data(3 downto 0)));
+      BUS_TX.ack  <= '1';
     else
-      UNKWN_OUT     <= '1';
+      BUS_TX.unknown <= '1';
     end if;
   
-  elsif READ_IN = '1' then
-    if ADDR_IN(3 downto 0) = x"0" then
+  elsif BUS_RX.read = '1' then
+    if BUS_RX.addr(3 downto 0) = x"0" then
       rx_fifo_read <= not rx_fifo_empty;
-      EMPTY_OUT    <=     rx_fifo_empty;
-    elsif ADDR_IN(3 downto 0) = x"1" then
-      DATA_OUT <= std_logic_vector(to_unsigned(clk_div,32));
-      ACK_OUT  <= '1';
-    elsif ADDR_IN(3 downto 0) = x"2" then
-      DATA_OUT(3 downto 0) <= std_logic_vector(to_unsigned(out_sel,4));
-      ACK_OUT  <= '1';
+      BUS_TX.nack  <=     rx_fifo_empty;
+    elsif BUS_RX.addr(3 downto 0) = x"1" then
+      BUS_TX.data <= std_logic_vector(to_unsigned(clk_div,32));
+      BUS_TX.ack  <= '1';
+    elsif BUS_RX.addr(3 downto 0) = x"2" then
+      BUS_TX.data(3 downto 0) <= std_logic_vector(to_unsigned(out_sel,4));
+      BUS_TX.ack  <= '1';
     else
-      UNKWN_OUT <= '1';
+      BUS_TX.unknown <= '1';
     end if;
   end if;