--- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20)
+-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
-- Module Version: 4.8
---/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n fifo_19x16_obuf -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 16 -width 19 -pfu_fifo -regout -no_enable -pe -1 -pf 0 -fill -e
+--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_19x16_obuf -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 16 -width 19 -no_enable -pe -1 -pf 0 -fill -e
--- Tue Nov 30 19:27:36 2010
+-- Wed Dec 8 14:00:12 2010
library IEEE;
use IEEE.std_logic_1164.all;
signal empty_d: std_logic;
signal full_i: std_logic;
signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
signal wptr_4: std_logic;
signal rptr_4: std_logic;
- signal edataout0: std_logic;
- signal edataout1: std_logic;
- signal edataout2: std_logic;
- signal edataout3: std_logic;
- signal edataout4: std_logic;
- signal edataout5: std_logic;
- signal edataout6: std_logic;
- signal edataout7: std_logic;
- signal edataout8: std_logic;
- signal edataout9: std_logic;
- signal edataout10: std_logic;
- signal edataout11: std_logic;
- signal edataout12: std_logic;
- signal edataout13: std_logic;
- signal edataout14: std_logic;
- signal edataout15: std_logic;
- signal edataout16: std_logic;
- signal edataout17: std_logic;
- signal edataout18: std_logic;
signal ifcount_0: std_logic;
signal ifcount_1: std_logic;
signal ifcount_2: std_logic;
signal ircount_1: std_logic;
signal rcount_0: std_logic;
signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
signal ircount_2: std_logic;
signal ircount_3: std_logic;
signal rcount_2: std_logic;
signal wcnt_sub_0: std_logic;
signal wcnt_sub_1: std_logic;
signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
signal wcount_0: std_logic;
signal wcount_1: std_logic;
signal wcnt_sub_2: std_logic;
signal wcnt_sub_3: std_logic;
signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
signal wcount_2: std_logic;
signal wcount_3: std_logic;
signal wcnt_sub_4: std_logic;
signal co1_5: std_logic;
signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
signal wcnt_reg_0: std_logic;
signal wcnt_reg_1: std_logic;
signal co0_6: std_logic;
signal wcnt_reg_4: std_logic;
signal af_set: std_logic;
signal af_set_c: std_logic;
- signal rdataout18: std_logic;
signal scuba_vlo: std_logic;
- signal rdataout17: std_logic;
- signal rdataout16: std_logic;
- signal rdataout15: std_logic;
- signal rdataout14: std_logic;
- signal rdataout13: std_logic;
- signal rdataout12: std_logic;
- signal rdataout11: std_logic;
- signal rdataout10: std_logic;
- signal rdataout9: std_logic;
- signal rdataout8: std_logic;
- signal rdataout7: std_logic;
- signal rdataout6: std_logic;
- signal rdataout5: std_logic;
- signal rdataout4: std_logic;
- signal rdataout3: std_logic;
- signal rdataout2: std_logic;
- signal rdataout1: std_logic;
- signal rdataout0: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal wren_i: std_logic;
- signal scuba_vhi: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
-- local component declarations
- component DPR16X2
- -- synopsys translate_off
- generic (INITVAL : in String; GSR : in String);
- -- synopsys translate_on
- port (DI0: in std_logic; DI1: in std_logic;
- WAD3: in std_logic; WAD2: in std_logic;
- WAD1: in std_logic; WAD0: in std_logic; WRE: in std_logic;
- WPE: in std_logic; WCK: in std_logic; RAD3: in std_logic;
- RAD2: in std_logic; RAD1: in std_logic;
- RAD0: in std_logic; WDO0: out std_logic;
- WDO1: out std_logic; RDO0: out std_logic;
- RDO1: out std_logic);
- end component;
component ROM16X1
-- synopsys translate_off
generic (initval : in String);
port (D: in std_logic; CK: in std_logic; CD: in std_logic;
Q: out std_logic);
end component;
- attribute GSR : string;
- attribute MEM_INIT_FILE : string;
- attribute MEM_LPC_FILE : string;
- attribute COMP : string;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
attribute initval of LUT4_1 : label is "0x3232";
attribute initval of LUT4_0 : label is "0x3232";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_19x16_obuf.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
attribute GSR of FF_32 : label is "ENABLED";
attribute GSR of FF_31 : label is "ENABLED";
attribute GSR of FF_30 : label is "ENABLED";
attribute GSR of FF_2 : label is "ENABLED";
attribute GSR of FF_1 : label is "ENABLED";
attribute GSR of FF_0 : label is "ENABLED";
- attribute GSR of fifo_pfu_0_0 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-1)";
- attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0";
- attribute initval of fifo_pfu_0_0 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_1 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(2-3)";
- attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1";
- attribute initval of fifo_pfu_0_1 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_2 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(4-5)";
- attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2";
- attribute initval of fifo_pfu_0_2 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_3 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_3 : label is "(0-15)(6-7)";
- attribute MEM_LPC_FILE of fifo_pfu_0_3 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_3 : label is "fifo_pfu_0_3";
- attribute initval of fifo_pfu_0_3 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_4 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_4 : label is "(0-15)(8-9)";
- attribute MEM_LPC_FILE of fifo_pfu_0_4 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_4 : label is "fifo_pfu_0_4";
- attribute initval of fifo_pfu_0_4 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_5 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_5 : label is "(0-15)(10-11)";
- attribute MEM_LPC_FILE of fifo_pfu_0_5 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_5 : label is "fifo_pfu_0_5";
- attribute initval of fifo_pfu_0_5 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_6 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_6 : label is "(0-15)(12-13)";
- attribute MEM_LPC_FILE of fifo_pfu_0_6 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_6 : label is "fifo_pfu_0_6";
- attribute initval of fifo_pfu_0_6 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_7 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_7 : label is "(0-15)(14-15)";
- attribute MEM_LPC_FILE of fifo_pfu_0_7 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_7 : label is "fifo_pfu_0_7";
- attribute initval of fifo_pfu_0_7 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_8 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_8 : label is "(0-15)(16-17)";
- attribute MEM_LPC_FILE of fifo_pfu_0_8 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_8 : label is "fifo_pfu_0_8";
- attribute initval of fifo_pfu_0_8 : label is "0x0000000000000000";
- attribute GSR of fifo_pfu_0_9 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_9 : label is "(0-15)(18-19)";
- attribute MEM_LPC_FILE of fifo_pfu_0_9 : label is "fifo_19x16_obuf.lpc";
- attribute COMP of fifo_pfu_0_9 : label is "fifo_pfu_0_9";
- attribute initval of fifo_pfu_0_9 : label is "0x0000000000000000";
attribute syn_keep : boolean;
begin
XOR2_t0: XOR2
port map (A=>wcount_4, B=>rptr_4, Z=>wcnt_sub_msb);
- FF_70: FD1P3DX
+ pdp_ram_0_0_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vhi,
+ ADW3=>scuba_vhi, ADW4=>scuba_vlo, ADW5=>wptr_0, ADW6=>wptr_1,
+ ADW7=>wptr_2, ADW8=>wptr_3, ADW9=>scuba_vlo,
+ ADW10=>scuba_vlo, ADW11=>scuba_vlo, ADW12=>scuba_vlo,
+ ADW13=>scuba_vlo, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
+ ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>scuba_vlo,
+ ADR10=>scuba_vlo, ADR11=>scuba_vlo, ADR12=>scuba_vlo,
+ ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
+ DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open,
+ DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
+ DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
+ DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>Q(16), DO35=>Q(17));
+
+ FF_32: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_69: FD1P3DX
+ FF_31: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_68: FD1P3DX
+ FF_30: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_67: FD1P3DX
+ FF_29: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_66: FD1P3DX
+ FF_28: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_65: FD1S3BX
+ FF_27: FD1S3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_64: FD1S3DX
+ FF_26: FD1S3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_63: FD1P3BX
+ FF_25: FD1P3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
Q=>wcount_0);
- FF_62: FD1P3DX
+ FF_24: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_61: FD1P3DX
+ FF_23: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_60: FD1P3DX
+ FF_22: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_59: FD1P3DX
+ FF_21: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_58: FD1P3BX
+ FF_20: FD1P3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
Q=>rcount_0);
- FF_57: FD1P3DX
+ FF_19: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_56: FD1P3DX
+ FF_18: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_55: FD1P3DX
+ FF_17: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_54: FD1P3DX
+ FF_16: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_53: FD1P3DX
+ FF_15: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_0);
- FF_52: FD1P3DX
+ FF_14: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_1);
- FF_51: FD1P3DX
+ FF_13: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_2);
- FF_50: FD1P3DX
+ FF_12: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_3);
- FF_49: FD1P3DX
+ FF_11: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_4);
- FF_48: FD1P3DX
+ FF_10: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_0);
- FF_47: FD1P3DX
+ FF_9: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_1);
- FF_46: FD1P3DX
+ FF_8: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_2);
- FF_45: FD1P3DX
+ FF_7: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_3);
- FF_44: FD1P3DX
+ FF_6: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_4);
- FF_43: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout0, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(0));
-
- FF_42: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout0);
-
- FF_41: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout1, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(1));
-
- FF_40: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout1);
-
- FF_39: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout2, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(2));
-
- FF_38: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout2);
-
- FF_37: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout3, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(3));
-
- FF_36: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout3);
-
- FF_35: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout4, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(4));
-
- FF_34: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout4);
-
- FF_33: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout5, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(5));
-
- FF_32: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout5);
-
- FF_31: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout6, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(6));
-
- FF_30: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout6);
-
- FF_29: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout7, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(7));
-
- FF_28: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout7);
-
- FF_27: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout8, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(8));
-
- FF_26: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout8);
-
- FF_25: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout9, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(9));
-
- FF_24: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout9);
-
- FF_23: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout10, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(10));
-
- FF_22: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout10, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout10);
-
- FF_21: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout11, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(11));
-
- FF_20: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout11, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout11);
-
- FF_19: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout12, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(12));
-
- FF_18: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout12, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout12);
-
- FF_17: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout13, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(13));
-
- FF_16: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout13, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout13);
-
- FF_15: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout14, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(14));
-
- FF_14: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout14, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout14);
-
- FF_13: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout15, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(15));
-
- FF_12: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout15, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout15);
-
- FF_11: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout16, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(16));
-
- FF_10: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout16, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout16);
-
- FF_9: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout17, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(17));
-
- FF_8: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout17, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout17);
-
- FF_7: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>edataout18, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
- Q=>Q(18));
-
- FF_6: FD1P3DX
- -- synopsys translate_off
- generic map (GSR=> "ENABLED")
- -- synopsys translate_on
- port map (D=>rdataout18, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>edataout18);
-
FF_5: FD1S3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
port map (CI=>co1_3, PC1=>scuba_vlo, PC0=>wcount_4, CO=>co2_1,
NC1=>open, NC0=>iwcount_4);
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
r_ctr_0: CU2
port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
NC1=>ircount_1, NC0=>ircount_0);
port map (A1=>scuba_vlo, A0=>wcnt_reg_4, B1=>scuba_vlo,
B0=>scuba_vlo, CI=>co1_6, GE=>af_set_c);
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
a0: FADD2
port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
S1=>open, S0=>af_set);
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- fifo_pfu_0_0: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(18), DI1=>scuba_vlo, WAD3=>wptr_3,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout18, RDO1=>open);
-
- fifo_pfu_0_1: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(16), DI1=>Data(17), WAD3=>wptr_3,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout16, RDO1=>rdataout17);
-
- fifo_pfu_0_2: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(14), DI1=>Data(15), WAD3=>wptr_3,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout14, RDO1=>rdataout15);
-
- fifo_pfu_0_3: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(12), DI1=>Data(13), WAD3=>wptr_3,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout12, RDO1=>rdataout13);
-
- fifo_pfu_0_4: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(10), DI1=>Data(11), WAD3=>wptr_3,
- WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
- WPE=>wren_i, WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2,
- RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
- RDO0=>rdataout10, RDO1=>rdataout11);
-
- fifo_pfu_0_5: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(8), DI1=>Data(9), WAD3=>wptr_3, WAD2=>wptr_2,
- WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
- WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
- RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout8,
- RDO1=>rdataout9);
-
- fifo_pfu_0_6: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(6), DI1=>Data(7), WAD3=>wptr_3, WAD2=>wptr_2,
- WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
- WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
- RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout6,
- RDO1=>rdataout7);
-
- fifo_pfu_0_7: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(4), DI1=>Data(5), WAD3=>wptr_3, WAD2=>wptr_2,
- WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
- WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
- RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout4,
- RDO1=>rdataout5);
-
- fifo_pfu_0_8: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(2), DI1=>Data(3), WAD3=>wptr_3, WAD2=>wptr_2,
- WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
- WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
- RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout2,
- RDO1=>rdataout3);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- fifo_pfu_0_9: DPR16X2
- -- synopsys translate_off
- generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
- -- synopsys translate_on
- port map (DI0=>Data(0), DI1=>Data(1), WAD3=>wptr_3, WAD2=>wptr_2,
- WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
- WCK=>Clock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
- RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout0,
- RDO1=>rdataout1);
-
WCNT(0) <= fcount_0;
WCNT(1) <= fcount_1;
WCNT(2) <= fcount_2;
library SCM;
configuration Structure_CON of fifo_19x16_obuf is
for Structure
- for all:DPR16X2 use entity SCM.DPR16X2(V); end for;
for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
for all:AND2 use entity SCM.AND2(V); end for;
for all:XOR2 use entity SCM.XOR2(V); end for;
for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
end for;
end Structure_CON;
jspc29 / trbnet.git / commitdiff