#################################################################
# I/O
#################################################################
-
-
LOCATE COMP "CON_1" SITE "A4";
LOCATE COMP "CON_2" SITE "A5";
LOCATE COMP "CON_3" SITE "A3";
LOCATE COMP "CON_4" SITE "D6";
LOCATE COMP "CON_5" SITE "B7";
-LOCATE COMP "CON_6" SITE "F7";
-LOCATE COMP "CON_7" SITE "C8";
-LOCATE COMP "CON_8" SITE "D8";
-LOCATE COMP "CON_9" SITE "F8";
+LOCATE COMP "CON_6" SITE "F7";
+LOCATE COMP "CON_7" SITE "C8";
+LOCATE COMP "CON_8" SITE "D8";
+LOCATE COMP "CON_9" SITE "F8";
LOCATE COMP "CON_10" SITE "B9";
LOCATE COMP "CON_11" SITE "F9";
LOCATE COMP "CON_12" SITE "D10";
DEFINE PORT GROUP "CON_group" "CON*" ;
IOBUF GROUP "CON_group" IO_TYPE=LVDS25;
+
+# LOCATE COMP "CON_1" SITE "A4";
+# LOCATE COMP "CON_2" SITE "A5";
+# LOCATE COMP "CON_3" SITE "A3";
+# LOCATE COMP "CON_4" SITE "D6";
+# LOCATE COMP "CON_5" SITE "B7";
+# LOCATE COMP "CON_6" SITE "F7";
+# LOCATE COMP "CON_7" SITE "C8";
+# LOCATE COMP "CON_8" SITE "D8";
+# LOCATE COMP "CON_9" SITE "F8";
+# LOCATE COMP "CON_10" SITE "B9";
+# LOCATE COMP "CON_11" SITE "F9";
+# LOCATE COMP "CON_12" SITE "D10";
+# LOCATE COMP "CON_13" SITE "A11";
+# LOCATE COMP "CON_14" SITE "B11";
+# LOCATE COMP "CON_15" SITE "B13";
+# LOCATE COMP "CON_16" SITE "C12";
+# DEFINE PORT GROUP "CON_group" "CON*" ;
+# IOBUF GROUP "CON_group" IO_TYPE=LVDS25;
+
LOCATE COMP "INP_1" SITE "T2";
LOCATE COMP "INP_2" SITE "T3";
DEFINE PORT GROUP "TRIGGER_EXT_group" "TRIGGER_EXT*" ;
IOBUF GROUP "TRIGGER_EXT_group" IO_TYPE=LVDS25;
-
+LOCATE COMP "CLK_TEST_OUT_2" SITE "Y34";
+IOBUF PORT "CLK_TEST_OUT_2" IO_TYPE=LVDS25 ;
+LOCATE COMP "CLK_TEST_OUT_1" SITE "W4";
+IOBUF PORT "CLK_TEST_OUT_1" IO_TYPE=LVDS25 ;
+LOCATE COMP "CLK_TEST_OUT_0" SITE "U9";
+IOBUF PORT "CLK_TEST_OUT_0" IO_TYPE=LVDS25 ;
#################################################################
--Trigger
TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
- TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45
+ TRIGGER_EXT : in std_logic_vector(2 downto 2); --additional trigger from RJ45
TRIGGER_OUT : out std_logic; --trigger to second input of fan-out
TRIGGER_OUT2 : out std_logic;
+ RXCLK_OUT : out std_logic;
--Serdes
CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 2/0, 200 MHz, only in case of problems
--FPGA Test
signal time_counter, time_counter2 : unsigned(31 downto 0);
-
+ signal rx_clock : std_logic;
--Media Interface
signal med_stat_op : std_logic_vector (5*16-1 downto 0);
signal med_ctrl_op : std_logic_vector (5*16-1 downto 0);
signal cts_rdo_invalid_trg : std_logic;
signal cts_rdo_trg_status_bits,
- cts_rdo_trg_status_bits_cts,
- cts_rdo_trg_status_bits_additional: std_logic_vector(31 downto 0) := (others => '0');
+ cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0');
signal cts_rdo_data : std_logic_vector(31 downto 0);
signal cts_rdo_write : std_logic;
signal cts_rdo_finished : std_logic;
signal cts_ext_control : std_logic_vector(31 downto 0);
signal cts_ext_debug : std_logic_vector(31 downto 0);
- signal cts_rdo_additional_data : std_logic_vector(31 downto 0);
- signal cts_rdo_additional_write : std_logic := '0';
- signal cts_rdo_additional_finished : std_logic := '0';
-
+ signal cts_rdo_additional_data : std_logic_vector(63 downto 0);
+ signal cts_rdo_additional_write : std_logic_vector(1 downto 0) := "00";
+ signal cts_rdo_additional_finished : std_logic_vector(1 downto 0) := "00";
+ signal cts_rdo_trg_status_bits_additional : std_logic_vector(63 downto 0) := (others => '0');
+ signal cts_rdo_trg_type : std_logic_vector(3 downto 0);
+ signal cts_rdo_trg_code : std_logic_vector(7 downto 0);
+ signal cts_rdo_trg_information : std_logic_vector(23 downto 0);
+ signal cts_rdo_trg_number : std_logic_vector(15 downto 0);
+
+
+
signal cts_trg_send : std_logic;
signal cts_trg_type : std_logic_vector(3 downto 0);
signal cts_trg_number : std_logic_vector(15 downto 0);
TRG_SYNC_OUT => cts_ext_trigger,
TRIGGER_IN => cts_rdo_trg_data_valid,
- DATA_OUT => cts_rdo_additional_data,
- WRITE_OUT => cts_rdo_additional_write,
- STATUSBIT_OUT => cts_rdo_trg_status_bits_additional,
- FINISHED_OUT => cts_rdo_additional_finished,
+ DATA_OUT => cts_rdo_additional_data(31 downto 0),
+ WRITE_OUT => cts_rdo_additional_write(0),
+ STATUSBIT_OUT => cts_rdo_trg_status_bits_additional(31 downto 0),
+ FINISHED_OUT => cts_rdo_additional_finished(0),
CONTROL_REG_IN => cts_ext_control,
STATUS_REG_OUT => cts_ext_status,
);
trigger_in_buf_i(1 downto 0) <= CLK_EXT;
- trigger_in_buf_i(3 downto 2) <= TRIGGER_EXT(3 downto 2);
+ trigger_in_buf_i(2 downto 2) <= TRIGGER_EXT(2 downto 2);
+ trigger_in_buf_i(3) <= '0';
THE_CTS: CTS
generic map (
MED_PACKET_NUM_OUT => med_packet_num_in(14 downto 12),
MED_DATAREADY_OUT => med_dataready_in(4),
MED_READ_IN => med_read_out(4),
- REFCLK2CORE_OUT => open,
+ REFCLK2CORE_OUT => rx_clock,
--SFP Connection
SD_RXD_P_IN => SFP_RX_P(1),
SD_RXD_N_IN => SFP_RX_N(1),
CLOCK_FREQUENCY => 100,
USE_ONEWIRE => c_YES,
BROADCAST_SPECIAL_ADDR => x"35",
- RDO_ADDITIONAL_PORT => c_YES,
+ RDO_ADDITIONAL_PORT => 2,
RDO_DATA_BUFFER_DEPTH => 9,
RDO_DATA_BUFFER_FULL_THRESH => 2**9-128,
RDO_HEADER_BUFFER_DEPTH => 9,
- RDO_HEADER_BUFFER_FULL_THRESH => 2**9-128
+ RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16
)
port map(
CLK => clk_100_i,
RESET => reset_i,
CLK_EN => '1',
- --Media interfacces
+-- Media interfacces ---------------------------------------------------------------
MED_DATAREADY_OUT(5*1-1 downto 0) => med_dataready_out,
MED_DATA_OUT(5*16-1 downto 0) => med_data_out,
MED_PACKET_NUM_OUT(5*3-1 downto 0) => med_packet_num_out,
CTS_IPU_BUSY_OUT => cts_ipu_busy,
-- CTS Data Readout ----------------------------------------------------------------
- --Trigger In
+ --Trigger to CTS out
RDO_TRIGGER_IN => cts_rdo_trigger,
RDO_TRG_DATA_VALID_OUT => cts_rdo_trg_data_valid,
RDO_VALID_TIMING_TRG_OUT => cts_rdo_valid_timing_trg,
RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_valid_notiming_trg,
RDO_INVALID_TRG_OUT => cts_rdo_invalid_trg,
- --Data out
+ RDO_TRG_TYPE_OUT => cts_rdo_trg_type,
+ RDO_TRG_CODE_OUT => cts_rdo_trg_code,
+ RDO_TRG_INFORMATION_OUT => cts_rdo_trg_information,
+ RDO_TRG_NUMBER_OUT => cts_rdo_trg_number,
+
+ --Data from CTS in
RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts,
RDO_DATA_IN => cts_rdo_data,
RDO_DATA_WRITE_IN => cts_rdo_write,
RDO_DATA_FINISHED_IN => cts_rdo_finished,
-
+ --Data from additional modules
RDO_ADDITIONAL_STATUSBITS_IN => cts_rdo_trg_status_bits_additional,
RDO_ADDITIONAL_DATA => cts_rdo_additional_data,
RDO_ADDITIONAL_WRITE => cts_rdo_additional_write,
RDO_ADDITIONAL_FINISHED => cts_rdo_additional_finished,
+-- Slow Control --------------------------------------------------------------------
COMMON_STAT_REGS => common_stat_regs, --open,
COMMON_CTRL_REGS => common_ctrl_regs, --open,
ONEWIRE => TEMPSENS,
);
-PROC_TDC_CTRL_REG : process begin
+PROC_TDC_CTRL_REG : process
+ variable pos : integer;
+begin
wait until rising_edge(clk_100_i);
- tdc_ctrl_data_out <= tdc_ctrl_reg(to_integer(unsigned(tdc_ctrl_addr))*32+31 downto to_integer(unsigned(tdc_ctrl_addr))*32);
+ pos := to_integer(unsigned(tdc_ctrl_addr))*32;
+ tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos);
last_tdc_ctrl_read <= tdc_ctrl_read;
- if tdc_ctrl_read = '1' then
- tdc_ctrl_reg(to_integer(unsigned(tdc_ctrl_addr))*32+31 downto to_integer(unsigned(tdc_ctrl_addr))*32) <= tdc_ctrl_data_in;
+ if tdc_ctrl_write = '1' then
+ tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in;
end if;
end process;
TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
--
+
-- Trigger signals from handler
--- TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet
--- VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet
--- VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet
--- INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet
--- TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet
--- SPIKE_DETECTED_IN => trg_spike_detected_i,
--- MULTI_TMG_TRG_IN => trg_multiple_trg_i,
--- SPURIOUS_TRG_IN => trg_spurious_trg_i,
--- --
--- TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package
--- TRG_CODE_IN => trg_code_i, --
--- TRG_INFORMATION_IN => trg_information_i, --
--- TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package
--- --
+ TRG_DATA_VALID_IN => cts_rdo_trg_data_valid, -- trig data valid signal from trbnet
+ VALID_TIMING_TRG_IN => cts_rdo_valid_timing_trg, -- valid timing trigger signal from trbnet
+ VALID_NOTIMING_TRG_IN => cts_rdo_valid_notiming_trg, -- valid notiming signal from trbnet
+ INVALID_TRG_IN => cts_rdo_invalid_trg, -- invalid trigger signal from trbnet
+ TMGTRG_TIMEOUT_IN => '0', -- timing trigger timeout signal from trbnet
+ SPIKE_DETECTED_IN => '0',
+ MULTI_TMG_TRG_IN => '0',
+ SPURIOUS_TRG_IN => '0',
+ --
+ TRG_NUMBER_IN => cts_rdo_trg_number, -- LVL1 trigger information package
+ TRG_CODE_IN => cts_rdo_trg_code, --
+ TRG_INFORMATION_IN => cts_rdo_trg_information, --
+ TRG_TYPE_IN => cts_rdo_trg_type, -- LVL1 trigger information package
--Response to handler
-- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
--- TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc
--- DATA_OUT => fee_data_i, -- tdc data
--- DATA_WRITE_OUT => fee_data_write_i, -- data valid signal
--- DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal
+ TRG_STATUSBIT_OUT => cts_rdo_trg_status_bits_additional(63 downto 32), -- status information of the tdc
+ DATA_OUT => cts_rdo_additional_data(63 downto 32), -- tdc data
+ DATA_WRITE_OUT => cts_rdo_additional_write(1), -- data valid signal
+ DATA_FINISHED_OUT => cts_rdo_additional_finished(1), -- readout finished signal
--
--Hit Counter Bus
HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe
TRIGGER_OUT <= cts_trigger_out;
TRIGGER_OUT2 <= cts_trigger_out;
-
+ cts_rdo_trigger <= cts_trigger_out;
---------------------------------------------------------------------------
-- FPGA communication
---------------------------------------------------------------------------
LED_RED <= debug(2);
LED_YELLOW <= link_ok; --debug(3);
-
+RXCLK_OUT <= rx_clock;
---------------------------------------------------------------------------
-- Test Connector
---------------------------------------------------------------------------
REGION "MEDIA_ONBOARD" "R90C122" 20 40;\r
LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_ONBOARD" ;\r
\r
+MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;\r
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
\r
#SPI Interface\r
REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;\r
###################################################################################
#Settings for this project
my $TOPNAME = "trb3_periph_hub"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
+my $lattice_path = '/d/jspc29/lattice/diamond/2.01';
my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
###################################################################################
-
+$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
entity trb3_periph_hub is
+ generic(
+ SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission. 4 SFP links only.
+ );
port(
--Clocks
CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
signal GSR_N : std_logic;
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
+ signal clk_100_internal : std_logic;
+ signal clk_200_internal : std_logic;
+ signal rx_clock_100 : std_logic;
+ signal rx_clock_200 : std_logic;
--Media Interface
signal med_stat_op : std_logic_vector (7*16-1 downto 0);
port map(
CLEAR_IN => '0', -- reset input (high active, async)
CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
+ CLK_IN => clk_200_internal, -- raw master clock, NOT from PLL/DLL!
SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', -- general reset signal (SYSCLK)
THE_MAIN_PLL : pll_in200_out100
port map(
CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_i,
- CLKOK => clk_200_i,
+ CLKOP => clk_100_internal,
+ CLKOK => clk_200_internal,
LOCK => pll_lock
);
+
+gen_sync_clocks : if SYNC_MODE = c_YES generate
+ clk_100_i <= rx_clock_100;
+ clk_200_i <= rx_clock_200;
+end generate;
+
+gen_local_clocks : if SYNC_MODE = c_NO generate
+ clk_100_i <= clk_100_internal;
+ clk_200_i <= clk_200_internal;
+end generate;
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
---------------------------------------------------------------------------
+gen_full_media : if SYNC_MODE = c_NO generate
THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp_4
generic map(
REVERSE_ORDER => c_NO, --order of ports
STAT_DEBUG => open,
CTRL_DEBUG => (others => '0')
);
+end generate;
+
+gen_sync_media : if SYNC_MODE = c_YES generate
+ med_stat_op(3*16+15 downto 3*16) <= x"0007";
+ med_stat_op(5*16+15 downto 5*16) <= x"0007";
-
-
--- trb_net16_med_ecp3_sfp
--- generic map(
--- SERDES_NUM => 1, --number of serdes in quad
--- EXT_CLOCK => c_NO, --use internal clock
--- USE_200_MHZ => c_YES --run on 200 MHz clock
--- )
--- port map(
--- CLK => clk_200_i,
--- SYSCLK => clk_100_i,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- CLK_EN => '1',
--- --Internal Connection
--- MED_DATA_IN => med_data_out(15 downto 0),
--- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
--- MED_DATAREADY_IN => med_dataready_out(0),
--- MED_READ_OUT => med_read_in(0),
--- MED_DATA_OUT => med_data_in(15 downto 0),
--- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
--- MED_DATAREADY_OUT => med_dataready_in(0),
--- MED_READ_IN => med_read_out(0),
--- REFCLK2CORE_OUT => open,
--- --SFP Connection
--- SD_RXD_P_IN => SERDES_INT_RX(2),
--- SD_RXD_N_IN => SERDES_INT_RX(3),
--- SD_TXD_P_OUT => SERDES_INT_TX(2),
--- SD_TXD_N_OUT => SERDES_INT_TX(3),
--- SD_REFCLK_P_IN => open,
--- SD_REFCLK_N_IN => open,
--- SD_PRSNT_N_IN => FPGA5_COMM(0),
--- SD_LOS_IN => FPGA5_COMM(0),
--- SD_TXDIS_OUT => FPGA5_COMM(2),
--- -- Status and control port
--- STAT_OP => med_stat_op(15 downto 0),
--- CTRL_OP => med_ctrl_op(15 downto 0),
--- STAT_DEBUG => med_stat_debug(63 downto 0),
--- CTRL_DEBUG => (others => '0')
--- );
-
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES, --run on 200 MHz clock
+ USE_CTC => c_NO,
+ USE_SLAVE => c_YES
+ )
+ port map(
+ CLK => clk_200_internal,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out(15 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(15 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
+ REFCLK2CORE_OUT => open,
+ CLK_RX_HALF_OUT => rx_clock_100,
+ CLK_RX_FULL_OUT => rx_clock_200,
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_ADDON_RX(8),
+ SD_RXD_N_IN => SERDES_ADDON_RX(9),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(8),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(9),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
+ -- Status and control port
+ STAT_OP => med_stat_op(15 downto 0),
+ CTRL_OP => med_ctrl_op(15 downto 0),
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => (others => '0')
+ );
+end generate;
THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4
generic map(
CTRL_DEBUG => (others => '0')
);
--- med_stat_op(3*16+15 downto 3*16) <= x"0007";
--- med_stat_op(5*16+15 downto 5*16) <= x"0007";
+
---------------------------------------------------------------------------
-- Hub
#################################################################
# Locate Serdes and media interfaces
#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "gen_sync_media_THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "gen_sync_media_THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "gen_full_media_THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
+
LOCATE COMP "THE_MEDIA_DOWNLINK/gen_serdes_200/PCSD_INST" SITE "PCSB" ;
LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "gen_sync_media_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "gen_full_media_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
LOCATE UGROUP "THE_MEDIA_DOWNLINK/media_interface_group" REGION "MEDIA_DOWNLINK" ;
#LOCATE UGROUP "THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "gen_full_media_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "gen_sync_media_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
signal proc_finished_3 : std_logic;
signal proc_finished_4 : std_logic;
signal conv_finished_i : std_logic;
+ signal thermocode_i : std_logic_vector(303 downto -1);
attribute syn_keep : boolean;
attribute syn_keep of mux_control : signal is true;
-------------------------------------------------------------------------------
begin
+
+ thermocode_i(303 downto 0) <= THERMOCODE_IN;
+ thermocode_i(-1) <= '1';
+
+
--purpose : Register signals
Register_Signals : process (CLK, RESET)
begin
end process Interval_Number_to_Binary;
Interval_Selection : process (CLK, RESET)
+ variable tmp : std_logic_vector(8 downto 0);
begin -- The interval with the 0-1 transition is selected.
if rising_edge(CLK) then
if RESET = '1' then
interval_reg <= (others => '0');
else
+-- tmp := (others => '0');
+-- make_mux : for i in 0 to 37 loop
+-- make_mux_2 : for j in 0 to 8 loop
+-- tmp(j) := tmp(j) or (thermocode_i(i*8-1+j) and P_one(j));
+-- end loop;
+-- end loop;
+-- interval_reg <= tmp;
case mux_control is
when "000001" => interval_reg <= THERMOCODE_IN(7 downto 0) & '1';
when "000010" => interval_reg <= THERMOCODE_IN(15 downto 7);
###################################################################################
#Settings for this project
my $TOPNAME = "trb3_central"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
+my $lattice_path = '/d/jspc29/lattice/diamond/2.01';
# my $synplify_path = '/d/jspc29/lattice/synplify/fpga_e201103/';
my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd"
add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
add_file -vhdl -lib work "./trb3_central.vhd"
entity trb3_central is
generic (
- USE_ETHERNET : integer range c_NO to c_YES := c_NO
+ USE_ETHERNET : integer range c_NO to c_YES := c_NO;
+ SYNC_MODE : integer range c_NO to c_YES := c_NO
);
port(
--Clocks
- CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45
+-- CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45
CLK_GPLL_LEFT : in std_logic; --Clock Manager 2/9, 200 MHz <-- MAIN CLOCK
CLK_GPLL_RIGHT : in std_logic; --Clock Manager 1/9, 125 MHz <-- for GbE
CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz
CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz
+ CLK_TEST_OUT : out std_logic_vector(2 downto 0);
--Trigger
TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
- TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45
+-- TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45
TRIGGER_OUT : out std_logic; --trigger to second input of fan-out
-
--Serdes
CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 2/0, 200 MHz, only in case of problems
CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible
--FPGA Test
signal time_counter, time_counter2 : unsigned(31 downto 0);
+ signal rx_clock : std_logic;
+ signal rx_clock_100 : std_logic;
+ signal rx_clock_200 : std_logic;
+ signal clk_100_internal : std_logic;
+ signal clk_200_internal : std_logic;
--Media Interface
signal med_stat_op : std_logic_vector (5*16-1 downto 0);
signal spimem_addr : std_logic_vector(5 downto 0);
signal spimem_data_out : std_logic_vector(31 downto 0);
signal spimem_ack : std_logic;
-
+ signal sci1_ack : std_logic;
+ signal sci1_write : std_logic;
+ signal sci1_read : std_logic;
+ signal sci1_data_in : std_logic_vector(7 downto 0);
+ signal sci1_data_out : std_logic_vector(7 downto 0);
+ signal sci1_addr : std_logic_vector(8 downto 0);
+
+ signal sci2_ack : std_logic;
+ signal sci2_write : std_logic;
+ signal sci2_read : std_logic;
+ signal sci2_data_in : std_logic_vector(7 downto 0);
+ signal sci2_data_out : std_logic_vector(7 downto 0);
+ signal sci2_addr : std_logic_vector(8 downto 0);
+
signal spi_bram_addr : std_logic_vector(7 downto 0);
signal spi_bram_wr_d : std_logic_vector(7 downto 0);
signal spi_bram_rd_d : std_logic_vector(7 downto 0);
port map(
CLEAR_IN => '0', -- reset input (high active, async)
CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
+ CLK_IN => clk_200_internal,-- raw master clock, NOT from PLL/DLL!
SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', -- general reset signal (SYSCLK)
THE_MAIN_PLL : pll_in200_out100
port map(
CLK => CLK_GPLL_LEFT,
- CLKOP => clk_100_i,
- CLKOK => clk_200_i,
+ CLKOP => clk_100_internal,--clk_100_i
+ CLKOK => clk_200_internal, --clk_200_i
LOCK => pll_lock
);
+gen_sync_clocks : if SYNC_MODE = c_YES generate
+ clk_100_i <= rx_clock_100;
+ clk_200_i <= rx_clock_200;
+end generate;
+
+gen_local_clocks : if SYNC_MODE = c_NO generate
+ clk_100_i <= clk_100_internal;
+ clk_200_i <= clk_200_internal;
+end generate;
---------------------------------------------------------------------------
-- The TrbNet media interface (Uplink)
SERDES_NUM => 0, --number of serdes in quad
EXT_CLOCK => c_NO, --use internal clock
USE_200_MHZ => c_YES, --run on 200 MHz clock
- USE_CTC => c_YES
+ USE_CTC => c_NO,
+ USE_SLAVE => SYNC_MODE
)
port map(
- CLK => clk_200_i,
+ CLK => clk_200_internal, --clk_200_i,
SYSCLK => clk_100_i,
RESET => reset_i,
CLEAR => clear_i,
MED_DATAREADY_OUT => med_dataready_in(4),
MED_READ_IN => med_read_out(4),
REFCLK2CORE_OUT => open,
+ CLK_RX_HALF_OUT => rx_clock_100,
+ CLK_RX_FULL_OUT => rx_clock_200,
--SFP Connection
SD_RXD_P_IN => SFP_RX_P(1),
SD_RXD_N_IN => SFP_RX_N(1),
SD_PRSNT_N_IN => SFP_MOD0(1),
SD_LOS_IN => SFP_LOS(1),
SD_TXDIS_OUT => SFP_TXDIS(1),
+
+ SCI_DATA_IN => sci1_data_in,
+ SCI_DATA_OUT => sci1_data_out,
+ SCI_ADDR => sci1_addr,
+ SCI_READ => sci1_read,
+ SCI_WRITE => sci1_write,
+ SCI_ACK => sci1_ack,
-- Status and control port
STAT_OP => med_stat_op(79 downto 64),
CTRL_OP => med_ctrl_op(79 downto 64),
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
---------------------------------------------------------------------------
-THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard
+THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4
port map(
CLK => clk_200_i,
SYSCLK => clk_100_i,
SD_TXDIS_OUT(1) => FPGA2_COMM(0),
SD_TXDIS_OUT(2) => FPGA3_COMM(0),
SD_TXDIS_OUT(3) => FPGA4_COMM(0),
+
+ SCI_DATA_IN => sci2_data_in,
+ SCI_DATA_OUT => sci2_data_out,
+ SCI_ADDR => sci2_addr,
+ SCI_READ => sci2_read,
+ SCI_WRITE => sci2_write,
+ SCI_ACK => sci2_ack,
-- Status and control port
STAT_OP => med_stat_op(63 downto 0),
CTRL_OP => med_ctrl_op(63 downto 0),
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", others => x"0000"),
- PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, others => 0)
+ PORT_NUMBER => 6,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"b000", 5 => x"b200", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 9, 5 => 9, others => 0)
)
port map(
CLK => clk_100_i,
BUS_NO_MORE_DATA_IN(1) => '0',
BUS_UNKNOWN_ADDR_IN(1) => '0',
- -- third one - IP config memory
- BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr,
- BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr,
- BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read,
- BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd,
- BUS_DATAREADY_IN(2) => mb_ip_mem_ack,
- BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack,
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => '0',
-
- -- gk 22.04.10
- -- gbe setup
- BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr,
- BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr,
- BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read,
- BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write,
- BUS_TIMEOUT_OUT(3) => open,
- BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd,
- BUS_DATAREADY_IN(3) => gbe_stp_reg_ack,
- BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack,
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => '0',
-
+ -- third one - IP config memory
+ BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr,
+ BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr,
+ BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read,
+ BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd,
+ BUS_DATAREADY_IN(2) => mb_ip_mem_ack,
+ BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack,
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
+
+ -- gk 22.04.10
+ -- gbe setup
+ BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr,
+ BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr,
+ BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read,
+ BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd,
+ BUS_DATAREADY_IN(3) => gbe_stp_reg_ack,
+ BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack,
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => '0',
+
+ --SCI first Media Interface
+ BUS_READ_ENABLE_OUT(4) => sci1_read,
+ BUS_WRITE_ENABLE_OUT(4) => sci1_write,
+ BUS_DATA_OUT(4*32+7 downto 4*32) => sci1_data_in,
+ BUS_DATA_OUT(4*32+31 downto 4*32+8) => open,
+ BUS_ADDR_OUT(4*16+8 downto 4*16) => sci1_addr,
+ BUS_ADDR_OUT(4*16+15 downto 4*16+9) => open,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATA_IN(4*32+7 downto 4*32) => sci1_data_out,
+ BUS_DATAREADY_IN(4) => sci1_ack,
+ BUS_WRITE_ACK_IN(4) => sci1_ack,
+ BUS_NO_MORE_DATA_IN(4) => '0',
+ BUS_UNKNOWN_ADDR_IN(4) => '0',
+ --SCI second Media Interface
+ BUS_READ_ENABLE_OUT(5) => sci2_read,
+ BUS_WRITE_ENABLE_OUT(5) => sci2_write,
+ BUS_DATA_OUT(5*32+7 downto 5*32) => sci2_data_in,
+ BUS_DATA_OUT(5*32+31 downto 5*32+8) => open,
+ BUS_ADDR_OUT(5*16+8 downto 5*16) => sci2_addr,
+ BUS_ADDR_OUT(5*16+15 downto 5*16+9) => open,
+ BUS_TIMEOUT_OUT(5) => open,
+ BUS_DATA_IN(5*32+7 downto 5*32) => sci2_data_out,
+ BUS_DATAREADY_IN(5) => sci2_ack,
+ BUS_WRITE_ACK_IN(5) => sci2_ack,
+ BUS_NO_MORE_DATA_IN(5) => '0',
+ BUS_UNKNOWN_ADDR_IN(5) => '0',
+
STAT_DEBUG => open
);
TEST_LINE(31 downto 10) <= (others => '0');
+ CLK_TEST_OUT <= clk_200_i & rx_clock & clk_100_i;
+
-- FPGA1_CONNECTOR(0) <= '0';
FPGA2_CONNECTOR(0) <= '0';
---------------------------------------------------------------------------
process
begin
- wait until rising_edge(clk_100_i);
+ wait until rising_edge(clk_100_internal);
time_counter <= time_counter + 1;
end process;
#################################################################\r
LOCATE COMP "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSD_INST" SITE "PCSB";\r
LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSC" ;\r
LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ;\r
\r
REGION "MEDIA_ONBOARD" "R90C122" 20 40;\r
LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_ONBOARD" ;\r
\r
+MULTICYCLE TO CELL "THE_MEDIA_ONBOARD/SCI_DATA_OUT*" 50 ns;\r
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
\r
#SPI Interface\r
REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;\r
--- /dev/null
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 11
+-c 1
+-e 2
+-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
\r
entity panda_dirc_wasa is\r
generic(\r
- SAME_ORDER : integer := 0\r
+ NORMAL_ORDER : integer := 1\r
);\r
port(\r
CON : out std_logic_vector(16 downto 1);\r
signal ram : ram_t;\r
\r
signal pwm_i : std_logic_vector(31 downto 0);\r
-signal tmp_con : std_logic_vector(15 downto 0);\r
+signal INP_i : std_logic_vector(15 downto 0);\r
signal spi_reg00_i : std_logic_vector(15 downto 0);\r
signal spi_reg10_i : std_logic_vector(15 downto 0);\r
signal spi_reg20_i : std_logic_vector(15 downto 0);\r
SEDSTDBY => open\r
);\r
\r
+---------------------------------------------------------------------------\r
+-- Input re-ordering\r
+---------------------------------------------------------------------------\r
+gen_outputs_1 : if NORMAL_ORDER = 1 generate\r
+ INP_i <= INP;\r
+ PWM <= pwm_i(15 downto 0);\r
+end generate;\r
\r
+gen_outputs_2 : if NORMAL_ORDER = 0 generate\r
+ INP_i <= INP(15) & INP(7) & INP(14) & INP(6) & INP(13) & INP(5) & INP(12) & INP(4) & \r
+ INP(11) & INP(3) & INP(10) & INP(2) & INP(9) & INP(1) & INP(8) & INP(0);\r
+ PWM <= pwm_i(15) & pwm_i(7) & pwm_i(14) & pwm_i(6) & pwm_i(13) & pwm_i(5) & pwm_i(12) & pwm_i(4) & \r
+ pwm_i(11) & pwm_i(3) & pwm_i(10) & pwm_i(2) & pwm_i(9) & pwm_i(1) & pwm_i(8) & pwm_i(0);\r
+end generate;\r
+\r
+ \r
+ \r
+ \r
---------------------------------------------------------------------------\r
-- SPI Interface\r
--------------------------------------------------------------------------- \r
);\r
\r
SPI_OUT <= buf_SPI_OUT; \r
----------------------------------------------------------------------------\r
--- RAM Interface\r
---------------------------------------------------------------------------- \r
-\r
\r
+spi_reg00_i <= pwm_data_o;\r
+spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0))));\r
spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o;\r
\r
+---------------------------------------------------------------------------\r
+-- RAM Interface\r
+--------------------------------------------------------------------------- \r
\r
\r
PROC_CTRL_FLASH : process begin\r
PWM => pwm_i\r
);\r
\r
- PWM <= pwm_i(15 downto 0);\r
\r
-spi_reg00_i <= pwm_data_o;\r
\r
PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i,\r
pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write,\r
else\r
idram(4) <= "0000" & temperature_i;\r
end if;\r
- spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0))));\r
\r
if spi_write_i(1) = '1' then\r
onewire_reset <= spi_data_i(0);\r
end if;\r
end process;\r
\r
-inp_status <= INP when rising_edge(clk_i);\r
+inp_status <= INP_i when rising_edge(clk_i);\r
last_inp <= inp_status(3 downto 0) when rising_edge(clk_i);\r
\r
\r
-- Rest of the I/O\r
---------------------------------------------------------------------------\r
\r
-inp_gated <= (INP xor inp_invert) and not input_enable;\r
-tmp_con <= inp_gated or (inp_stretched and inp_stretch);\r
-\r
-gen_outputs_1 : if SAME_ORDER = 1 generate\r
- CON <= tmp_con;\r
-end generate;\r
-gen_outputs_2 : if SAME_ORDER = 0 generate\r
- CON <= tmp_con;\r
-end generate;\r
+inp_gated <= (INP_i xor inp_invert) and not input_enable;\r
+CON <= inp_gated or (inp_stretched and inp_stretch);\r
\r
\r
\r
\r
\r
\r
-SPARE_OUTPUT : process(INP, inp_select, inp_or, inp_long_or, inp_long_reg, last_inp_long_reg)\r
+SPARE_OUTPUT : process(INP_i, inp_select, inp_or, inp_long_or, inp_long_reg, last_inp_long_reg)\r
begin\r
if inp_select < 16 then\r
- SPARE_LVDS <= INP(inp_select+1);\r
+ SPARE_LVDS <= INP_i(inp_select);\r
elsif inp_select < 24 then\r
SPARE_LVDS <= inp_or;\r
else\r
end if;\r
end process;\r
\r
-inp_or <= or_all((INP xor inp_invert) and not input_enable);\r
-\r
+inp_or <= or_all((INP_i xor inp_invert) and not input_enable);\r
inp_long_or <= (inp_or or inp_long_or) and not inp_long_reg;\r
-\r
inp_long_reg <= inp_long_or when rising_edge(clk_i);\r
last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);\r
+\r
-- ll_inp_long_reg <= last_inp_long_reg when rising_edge(clk_i);\r
\r
\r
-- TEST_LINE(15) <= '1' when fsm_copydat = PWM_WRITE_GET_2 or fsm_copydat = PWM_WRITE else '0';\r
\r
\r
-TEST_LINE <= spi_debug_i;\r
+TEST_LINE <= (others => '0');\r
\r
\r
LED_GREEN <= not leds(0) when led_status(4) = '0' else not led_status(0);\r
jspc29 / trb3.git / commitdiff