entity trb_net16_api_base is
generic (
- API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
+ API_TYPE : integer := 1; -- type of api: 0 passive, 1 active
--FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium
FIFO_TO_APL_DEPTH : integer := 1; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering master path
- -- if set to 0, no buffer is used
SBUF_VERSION : integer range 0 to 1 := 0
);
component trb_net16_term is
generic (
- FIFO_TERM_BUFFER_DEPTH : integer := FIFO_TERM_BUFFER_DEPTH;
- -- fifo for auto-answering of the master path, if set to 0 no buffer is used at all
SECURE_MODE : integer range 0 to 1 := 0
--if secure_mode is not used, apl must provide error pattern and dtype until
--next trigger comes in. In secure mode these must be available when hold_trm goes low
);
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
INT_DATAREADY_OUT: out std_logic;
INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
);
end component;
+
-- signals for the APL to INT fifo:
signal fifo_to_int_data_in : std_logic_vector(15 downto 0);
signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0);
signal fifo_to_apl_empty : std_logic;
signal saved_fifo_to_apl_packet_type, current_fifo_to_apl_packet_type : std_logic_vector(2 downto 0);
-
- -- signals for the test buffer
- signal fifo_term_buffer_data_in : std_logic_vector(15 downto 0);
- signal fifo_term_buffer_packet_num_in : std_logic_vector(1 downto 0);
- signal fifo_term_buffer_write : std_logic;
- signal fifo_term_buffer_data_out : std_logic_vector(15 downto 0);
- signal fifo_term_buffer_packet_num_out : std_logic_vector(1 downto 0);
- signal fifo_term_buffer_read : std_logic;
- signal fifo_term_buffer_full : std_logic;
- signal fifo_term_buffer_empty : std_logic;
-
- signal state_bits : std_logic_vector(2 downto 0);
- type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR);
- type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR);
- signal current_state, next_state : API_STATE;
- signal tb_current_state, tb_next_state : TERM_BUFFER_STATE;
- signal slave_running, next_slave_running : std_logic;
+ signal state_bits, state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0);
+ signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic;
signal next_INT_MASTER_DATA_OUT: std_logic_vector(15 downto 0);
signal next_INT_MASTER_PACKET_NUM_OUT: std_logic_vector(1 downto 0);
signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0);
signal combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0);
signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0);
- signal next_registered_trailer_F1, next_registered_trailer_F2, next_registered_trailer_F3 : std_logic_vector(15 downto 0);
signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0);
signal current_combined_header, current_registered_trailer, current_combined_trailer, current_data : std_logic_vector(15 downto 0);
signal update_registered_trailer: std_logic;
signal master_counter : std_logic_vector(1 downto 0);
signal out_enable : std_logic_vector(1 downto 0);
+ signal send_trm_wrong_addr, next_send_trm_wrong_addr : std_logic;
+ signal wait_for_answer, next_wait_for_answer : std_logic;
+
+ type PAS_API_TO_APL_STATE_T is (IDLE, WRONG_ADDR, MY_ADDR);
+ signal state_to_apl, next_state_to_apl : PAS_API_TO_APL_STATE_T;
+
+ type state_to_int_t is (IDLE, WAITING, SEND_SHORT, SEND_HEADER, RUNNING, SEND_TRAILER, SHUTDOWN);
+ signal state_to_int, next_state_to_int : state_to_int_t;
+
+ type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR);
+ signal current_state, next_state : API_STATE;
+
+
begin
---------------------------------------
-- termination for active api
---------------------------------------
-- a sbuf on the active channel
---------------------------------------
-
ACTIVE_SBUF: trb_net16_sbuf
generic map (
DATA_WIDTH => 16,
end process;
+ gen_pas_api_fsm : if API_TYPE = 0 generate
---------------------------------------
---the state machine
+--state machine for passive api
---------------------------------------
+ to_apl : process(fifo_to_apl_full, reg_INT_SLAVE_READ_OUT, INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty,
+ fifo_to_apl_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT,
+ APL_READ_IN, INT_SLAVE_DATA_IN, INT_SLAVE_PACKET_NUM_IN, APL_MY_ADDRESS_IN,
+ reg_APL_DATAREADY_OUT, slave_running )
+ begin
+ next_INT_SLAVE_READ_OUT <= not fifo_to_apl_full;
+ fifo_to_apl_write <= reg_INT_SLAVE_READ_OUT and INT_SLAVE_DATAREADY_IN;
+ fifo_to_apl_read <= '0';
+ next_APL_DATAREADY_OUT <= '0';
+ next_state_to_apl <= state_to_apl;
+ next_send_trm_wrong_addr <= '0';
+ next_wait_for_answer <= '0';
+ get_slave_running <= '0';
+
+ if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and APL_READ_IN = '1' then
+ next_state_to_apl <= IDLE;
+ end if;
- STATE_COMB: process(current_state, APL_SEND_IN, slave_running, sequence_counter,
- APL_SHORT_TRANSFER_IN, APL_WRITE_IN, fifo_to_int_empty,
- sbuf_free, master_counter, fifo_to_apl_full,
- reg_APL_DATAREADY_OUT, reg_INT_SLAVE_READ_OUT,
- INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, APL_READ_IN,
- fifo_to_apl_packet_num_out, reg_APL_TYP_OUT,
- reg_APL_PACKET_NUM_OUT, last_out_select)
- begin
- next_state <= MY_ERROR;
- next_INT_MASTER_DATAREADY_OUT <= '0';
- out_select <= DAT;
- update_registered_trailer <= '0';
- fifo_to_int_read <= '0';
- next_INT_SLAVE_READ_OUT <= '0';
- fifo_to_apl_write <= '0';
- next_APL_DATAREADY_OUT <= '0';
- fifo_to_apl_read <= '0';
- next_slave_running <= slave_running;
- next_sequence_counter <= sequence_counter;
- -------------------------------------------------------------------------------
- -- IDLE
- -------------------------------------------------------------------------------
- if current_state = IDLE then
- if APL_SEND_IN = '1' then
- if APL_SHORT_TRANSFER_IN = '1' then -- and APL_WRITE_IN = '0' and fifo_to_int_empty = '1'
- next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN
- update_registered_trailer <= '1'; -- moved from SEND_SHORT
- else -- normal transfer, prepare the header
- next_state <= SEND_HEADER;
+ case state_to_apl is
+ when IDLE =>
+ if INT_SLAVE_DATAREADY_IN = '1' then
+ if (INT_SLAVE_DATA_IN(2 downto 0) = TYPE_TRM and INT_SLAVE_PACKET_NUM_IN = "00") then
+ get_slave_running <= '1';
+ next_wait_for_answer <= '1';
+ next_state_to_apl <= MY_ADDR;
+ end if;
+ if INT_SLAVE_PACKET_NUM_IN = "10" then
+ if INT_SLAVE_DATA_IN = APL_MY_ADDRESS_IN or and_all(INT_SLAVE_DATA_IN) = '1' then
+ get_slave_running <= '1';
+ next_wait_for_answer <= '1';
+ next_state_to_apl <= MY_ADDR;
+ else
+ next_state_to_apl <= WRONG_ADDR;
+ next_send_trm_wrong_addr <= '1';
+ end if;
+ end if;
+ end if;
+ when WRONG_ADDR =>
+ fifo_to_apl_read <= not fifo_to_apl_empty;
+ when MY_ADDR =>
+ next_APL_DATAREADY_OUT <= not fifo_to_apl_empty and or_all(fifo_to_apl_packet_num_out);
+ fifo_to_apl_read <= not fifo_to_apl_empty and( (not fifo_to_apl_empty and or_all(fifo_to_apl_packet_num_out) and APL_READ_IN)
+ or not or_all(fifo_to_apl_packet_num_out));
+ end case;
+ end process;
+
+ to_int : process(state_to_int, send_trm_wrong_addr, wait_for_answer, APL_SHORT_TRANSFER_IN, APL_SEND_IN,
+ master_counter, sbuf_free, fifo_to_int_empty, sequence_counter)
+ begin
+ next_state_to_int <= state_to_int;
+ update_registered_trailer <= '0';
+ out_select <= DAT;
+ next_INT_MASTER_DATAREADY_OUT <= '0';
+ next_sequence_counter <= sequence_counter;
+ fifo_to_int_read <= '0';
+ release_slave_running <= '0';
+
+ case state_to_int is
+ when IDLE =>
+ if wait_for_answer = '1' then
+ next_state_to_int <= WAITING;
+ end if;
+ if send_trm_wrong_addr = '1' then
+ next_state_to_int <= SEND_SHORT;
+ end if;
+ when WAITING =>
+ if APL_SEND_IN = '1' then
+ if APL_SHORT_TRANSFER_IN = '1' then
+ next_state_to_int <= SEND_SHORT;
+ update_registered_trailer <= '1';
+ else
+ next_state_to_int <= SEND_HEADER;
+ out_select <= HDR;
+ next_INT_MASTER_DATAREADY_OUT <= '1';
+ end if;
+ end if;
+ when SEND_SHORT =>
+ out_select <= TRM;
+ if APL_SEND_IN = '0' then
+ next_state_to_int <= SEND_TRAILER;
+ next_INT_MASTER_DATAREADY_OUT <= '1';
+ end if;
+ when SEND_HEADER =>
out_select <= HDR;
- next_INT_MASTER_DATAREADY_OUT <= '1';
- end if; -- next word will be a header
- else
- next_state <= IDLE;
- end if; -- APL_SEND_IN
- -------------------------------------------------------------------------------
- -- SEND_SHORT
- -------------------------------------------------------------------------------
- elsif current_state = SEND_SHORT then
- next_state <= SEND_SHORT;
- out_select <= TRM;
- if APL_SEND_IN = '0' then -- terminate the transfer
- next_state <= SEND_TRAILER;
- next_INT_MASTER_DATAREADY_OUT <= '1';
- end if;
- -------------------------------------------------------------------------------
- -- SEND_HEADER
- -------------------------------------------------------------------------------
- elsif current_state = SEND_HEADER then
- out_select <= HDR;
- if sbuf_free = '1' then
- next_INT_MASTER_DATAREADY_OUT <= '1';
+ next_INT_MASTER_DATAREADY_OUT <= sbuf_free;
+ if master_counter = "00" then
+ next_state_to_int <= RUNNING;
+ next_INT_MASTER_DATAREADY_OUT <= '0';
+ end if;
+ when RUNNING =>
+ fifo_to_int_read <= sbuf_free;
+ next_INT_MASTER_DATAREADY_OUT <= sbuf_free and ((not fifo_to_int_empty and APL_SEND_IN) or not APL_SEND_IN);
+ if APL_SEND_IN = '0' then -- terminate the transfer
+ update_registered_trailer <= '1';
+ next_INT_MASTER_DATAREADY_OUT <= sbuf_free;
+ if fifo_to_int_empty = '1' then -- immediate stop
+ if master_counter = "11" then
+ next_state_to_int <= SEND_TRAILER;
+ out_select <= TRM_COMB;
+ end if;
+ else
+ next_state_to_int <= SHUTDOWN;
+ end if;
+ end if;
+ when SHUTDOWN =>
+ next_INT_MASTER_DATAREADY_OUT <= sbuf_free;
+ fifo_to_int_read <= not fifo_to_int_empty and sbuf_free;
+ if master_counter = "00" and fifo_to_int_empty = '1' and sbuf_free = '1' then
+ --implicit: fill with padding words
+ next_state_to_int <= SEND_TRAILER;
+ out_select <= TRM;
+ end if;
+ when SEND_TRAILER =>
+ out_select <= TRM;
+ next_INT_MASTER_DATAREADY_OUT <= sbuf_free;
+ if master_counter = "00" then
+ next_state_to_int <= IDLE;
+ next_INT_MASTER_DATAREADY_OUT <= '0';
+ next_sequence_counter <= sequence_counter +1;
+ release_slave_running <= '1';
+ end if;
+ end case;
+ if master_counter = "00" or fifo_to_int_empty = '1' then
+ fifo_to_int_read <= '0';
end if;
- if master_counter = "00" then
- next_state <= RUNNING;
- next_INT_MASTER_DATAREADY_OUT <= '0';
- else
- next_state <= SEND_HEADER;
+ end process;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or release_slave_running = '1' then
+ slave_running <= '0';
+ elsif get_slave_running = '1' then
+ slave_running <= '1';
+ end if;
end if;
- -------------------------------------------------------------------------------
- -- RUNNING
- -------------------------------------------------------------------------------
- elsif current_state = RUNNING then
- if sbuf_free = '1' then
- fifo_to_int_read <= '1';
+ end process;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ state_to_apl <= IDLE;
+ state_to_int <= IDLE;
+ reg_INT_SLAVE_READ_OUT <= '0';
+ send_trm_wrong_addr <= '0';
+ wait_for_answer <= '0';
+ sequence_counter <= (others => '0');
+ else
+ state_to_apl <= next_state_to_apl;
+ state_to_int <= next_state_to_int;
+ reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT;
+ send_trm_wrong_addr <= next_send_trm_wrong_addr;
+ wait_for_answer <= next_wait_for_answer;
+ sequence_counter <= next_sequence_counter;
+ end if;
end if;
- if APL_SEND_IN = '0' then -- terminate the transfer
- update_registered_trailer <= '1';
- if fifo_to_int_empty = '1' then -- immediate stop
+ end process;
+ end generate;
+
+---------------------------------------
+--the state machine for active api
+---------------------------------------
+ gen_act_api_fsm : if API_TYPE = 1 generate
+ STATE_COMB: process(current_state, APL_SEND_IN, slave_running, sequence_counter,
+ APL_SHORT_TRANSFER_IN, APL_WRITE_IN, fifo_to_int_empty,
+ sbuf_free, master_counter, fifo_to_apl_full,
+ reg_APL_DATAREADY_OUT, reg_INT_SLAVE_READ_OUT,
+ INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, APL_READ_IN,
+ fifo_to_apl_packet_num_out, reg_APL_TYP_OUT,
+ reg_APL_PACKET_NUM_OUT, last_out_select)
+ begin
+ next_state <= MY_ERROR;
+ next_INT_MASTER_DATAREADY_OUT <= '0';
+ out_select <= DAT;
+ update_registered_trailer <= '0';
+ fifo_to_int_read <= '0';
+ next_INT_SLAVE_READ_OUT <= '0';
+ fifo_to_apl_write <= '0';
+ next_APL_DATAREADY_OUT <= '0';
+ fifo_to_apl_read <= '0';
+ next_slave_running <= slave_running;
+ next_sequence_counter <= sequence_counter;
+ -------------------------------------------------------------------------------
+ -- IDLE
+ -------------------------------------------------------------------------------
+ if current_state = IDLE then
+ if APL_SEND_IN = '1' then
+ if APL_SHORT_TRANSFER_IN = '1' then -- and APL_WRITE_IN = '0' and fifo_to_int_empty = '1'
+ next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN
+ update_registered_trailer <= '1'; -- moved from SEND_SHORT
+ else -- normal transfer, prepare the header
+ next_state <= SEND_HEADER;
+ out_select <= HDR;
+ next_INT_MASTER_DATAREADY_OUT <= '1';
+ end if; -- next word will be a header
+ else
+ next_state <= IDLE;
+ end if; -- APL_SEND_IN
+ -------------------------------------------------------------------------------
+ -- SEND_SHORT
+ -------------------------------------------------------------------------------
+ elsif current_state = SEND_SHORT then
+ next_state <= SEND_SHORT;
+ out_select <= TRM;
+ if APL_SEND_IN = '0' then -- terminate the transfer
+ next_state <= SEND_TRAILER;
next_INT_MASTER_DATAREADY_OUT <= '1';
- if master_counter = "11" then
- next_state <= SEND_TRAILER;
- out_select <= TRM_COMB;
- end if;
+ end if;
+ -------------------------------------------------------------------------------
+ -- SEND_HEADER
+ -------------------------------------------------------------------------------
+ elsif current_state = SEND_HEADER then
+ out_select <= HDR;
+ if sbuf_free = '1' then
+ next_INT_MASTER_DATAREADY_OUT <= '1';
+ end if;
+ if master_counter = "00" then
+ next_state <= RUNNING;
+ next_INT_MASTER_DATAREADY_OUT <= '0';
else
- next_state <= SHUTDOWN;
- if sbuf_free = '1' then
- next_INT_MASTER_DATAREADY_OUT <= '1';
+ next_state <= SEND_HEADER;
+ end if;
+ -------------------------------------------------------------------------------
+ -- RUNNING
+ -------------------------------------------------------------------------------
+ elsif current_state = RUNNING then
+ if sbuf_free = '1' then
+ fifo_to_int_read <= '1';
+ end if;
+ if APL_SEND_IN = '0' then -- terminate the transfer
+ update_registered_trailer <= '1';
+ if fifo_to_int_empty = '1' then -- immediate stop
+ next_INT_MASTER_DATAREADY_OUT <= sbuf_free;
+ if master_counter = "11" then
+ next_state <= SEND_TRAILER;
+ out_select <= TRM_COMB;
+ end if;
+ else
+ next_state <= SHUTDOWN;
+ if sbuf_free = '1' then
+ next_INT_MASTER_DATAREADY_OUT <= '1';
+ end if;
end if;
+ else -- APL_SEND_IN: still running
+ next_state <= RUNNING;
+ if fifo_to_int_empty = '0' and sbuf_free = '1' then
+ -- data words have to be prepared
+ next_INT_MASTER_DATAREADY_OUT <= '1';
+ end if; -- fifo_to_int_empty = '0'
end if;
- else -- APL_SEND_IN: still running
- next_state <= RUNNING;
- if fifo_to_int_empty = '0' and sbuf_free = '1' then
- -- data words have to be prepared
+ -------------------------------------------------------------------------------
+ -- SHUTDOWN: Empty the pipe
+ -------------------------------------------------------------------------------
+ elsif current_state = SHUTDOWN then
+ next_state <= SHUTDOWN;
+ if sbuf_free = '1' then
next_INT_MASTER_DATAREADY_OUT <= '1';
- end if; -- fifo_to_int_empty = '0'
- end if;
- -------------------------------------------------------------------------------
- -- SHUTDOWN: Empty the pipe
- -------------------------------------------------------------------------------
- elsif current_state = SHUTDOWN then
- next_state <= SHUTDOWN;
- if sbuf_free = '1' then
--- next_INT_MASTER_DATAREADY_OUT <= '1';
--- -- we are done
--- --implicit: fill with padding words
--- if master_counter = "00" and fifo_to_int_empty = '1' then
--- next_state <= SEND_TRAILER;
--- out_select <= TRM;
- if fifo_to_int_empty = '0' then
- -- data words have to be prepared
- fifo_to_int_read <= '1';
- next_INT_MASTER_DATAREADY_OUT <= '1';
- else
- -- we are done
- --implicit: fill with padding words
- if master_counter = "00" then
+ if fifo_to_int_empty = '0' then
+ -- data words have to be prepared
+ fifo_to_int_read <= '1';
+ elsif master_counter = "00" then
+ -- we are done
+ --implicit: fill with padding words
next_state <= SEND_TRAILER;
out_select <= TRM;
end if;
+ end if;
+ -------------------------------------------------------------------------------
+ -- SEND_TRAILER
+ -------------------------------------------------------------------------------
+ elsif current_state = SEND_TRAILER then
+ out_select <= TRM;
+ if sbuf_free = '1' then
next_INT_MASTER_DATAREADY_OUT <= '1';
end if;
- end if;
- -------------------------------------------------------------------------------
- -- SEND_TRAILER
- -------------------------------------------------------------------------------
- elsif current_state = SEND_TRAILER then
- out_select <= TRM;
- if sbuf_free = '1' then
- next_INT_MASTER_DATAREADY_OUT <= '1';
- end if;
- if master_counter = "00" then
+ if master_counter = "00" then
+ next_state <= WAITING;
+ next_INT_MASTER_DATAREADY_OUT <= '0';
+ if API_TYPE = 0 then --here is the end of the passive transfer
+ next_sequence_counter <= sequence_counter +1;
+ next_slave_running <= '0';
+ end if;
+ else
+ next_state <= SEND_TRAILER;
+ end if;
+ -------------------------------------------------------------------------------
+ -- WAITING => for the answer or a request
+ -------------------------------------------------------------------------------
+ elsif current_state = WAITING then
next_state <= WAITING;
- next_INT_MASTER_DATAREADY_OUT <= '0';
- if API_TYPE = 0 then --here is the end of the passive transfer
- next_sequence_counter <= sequence_counter +1;
- next_slave_running <= '0';
+ -- here we have to supply the receiver port
+ -- part 1: connection to network
+ if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then
+ next_INT_SLAVE_READ_OUT <= '1';
end if;
- else
- next_state <= SEND_TRAILER;
- end if;
- -------------------------------------------------------------------------------
- -- WAITING => for the answer or a request
- -------------------------------------------------------------------------------
- elsif current_state = WAITING then
- next_state <= WAITING;
- -- here we have to supply the receiver port
- -- part 1: connection to network
- if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then
- next_INT_SLAVE_READ_OUT <= '1';
- end if;
- if reg_INT_SLAVE_READ_OUT = '1' and INT_SLAVE_DATAREADY_IN = '1' then
- fifo_to_apl_write <= '1'; -- use fifo as the pipe
- end if;
-
- -- part 2: connection to apl
--- if fifo_to_apl_empty = '0' then
- if fifo_to_apl_empty = '0' --and not (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1')
- and fifo_to_apl_packet_num_out /= "00" then --is this really correct????
- next_APL_DATAREADY_OUT <= '1';
- end if; -- read/no read
-
- if (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') or fifo_to_apl_packet_num_out = "00" then
- -- valid read
- fifo_to_apl_read <= not fifo_to_apl_empty;
- if API_TYPE = 0 then
- if (reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR) then
- next_slave_running <= '1';
- end if;
+ if reg_INT_SLAVE_READ_OUT = '1' and INT_SLAVE_DATAREADY_IN = '1' then
+ fifo_to_apl_write <= '1'; -- use fifo as the pipe
end if;
- if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT= "11" and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1')
- then --fifo_to_apl_read = '1'
- next_state <= IDLE;
- if API_TYPE = 1 then
+
+ -- part 2: connection to apl
+ -- if fifo_to_apl_empty = '0' then
+ if fifo_to_apl_empty = '0' --and not (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1')
+ and fifo_to_apl_packet_num_out /= "00" then --is this really correct????
+ next_APL_DATAREADY_OUT <= '1';
+ end if; -- read/no read
+
+ if (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') or fifo_to_apl_packet_num_out = "00" then
+ -- valid read
+ fifo_to_apl_read <= not fifo_to_apl_empty;
+ if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT= "11" and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1')
+ then --fifo_to_apl_read = '1'
+ next_state <= IDLE;
next_sequence_counter <= sequence_counter +1;
end if;
end if;
+ -- MISSING: SEQNR check
+ -- OPEN QUESTION: Address matching? makes sense for a reply transfer?
+ end if;
+ if master_counter = "00" or fifo_to_int_empty = '1' then
+ fifo_to_int_read <= '0';
end if;
- -- MISSING: SEQNR check
- -- OPEN QUESTION: Address matching? makes sense for a reply transfer?
- end if;
- if master_counter = "00" or fifo_to_int_empty = '1' then
- fifo_to_int_read <= '0';
- end if;
- end process;
-
- CLK_REG: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- sequence_counter <= (others => '0');
- reg_INT_SLAVE_READ_OUT <= '0';
- last_out_select <= DAT;
- if API_TYPE = 1 then
- current_state <= IDLE;
- else
- current_state <= WAITING;
+ end process;
+
+ CLK_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ sequence_counter <= (others => '0');
+ reg_INT_SLAVE_READ_OUT <= '0';
+ last_out_select <= DAT;
+ if API_TYPE = 1 then
+ current_state <= IDLE;
+ else
+ current_state <= WAITING;
+ end if;
+ slave_running <= '0';
+ elsif CLK_EN = '1' then
+ sequence_counter <= next_sequence_counter;
+ last_out_select <= out_select;
+ reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT;
+ current_state <= next_state;
+ slave_running <= next_slave_running;
end if;
- slave_running <= '0';
- elsif CLK_EN = '1' then
- sequence_counter <= next_sequence_counter;
- last_out_select <= out_select;
- reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT;
- current_state <= next_state;
- slave_running <= next_slave_running;
end if;
- end if;
- end process;
-
+ end process;
+ end generate;
+
+
---------------------------------------
--
---------------------------------------
-- connect Transmitter port
fifo_to_int_data_in <= APL_DATA_IN;
fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN;
- fifo_to_int_write <= (APL_WRITE_IN and not fifo_to_int_full)
- when (current_state = IDLE or current_state = SEND_HEADER or current_state = RUNNING)
- else '0';
+ fifo_to_int_write <= (APL_WRITE_IN and not fifo_to_int_full);
+-- when (current_state = IDLE or current_state = SEND_HEADER or current_state = RUNNING)
+-- else '0';
APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing
begin
if rising_edge(CLK) then
if RESET = '1' then
- reg_APL_DATAREADY_OUT <= '0';
reg_APL_DATA_OUT <= (others => '0');
reg_APL_PACKET_NUM_OUT <= (others => '0');
reg_APL_TYP_OUT <= (others => '0');
- elsif CLK_EN = '1' then
- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
+ elsif APL_READ_IN = '1' then --CLK_EN
reg_APL_DATA_OUT <= next_APL_DATA_OUT;
reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT;
reg_APL_TYP_OUT <= next_APL_TYP_OUT;
end if;
end process;
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_APL_DATAREADY_OUT <= '0';
+ elsif CLK_EN = '1' then
+ reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
+ end if;
+ end if;
+ end process;
-- connect receiver
fifo_to_apl_data_in <= INT_SLAVE_DATA_IN;
end if;
end process;
- process(current_state)
+--for simulation only
+ gen_1: if API_TYPE = 1 generate
+ process(current_state)
begin
case current_state is
when IDLE => state_bits <= "000";
when others => state_bits <= "111";
end case;
end process;
+ state_bits_to_apl <= "000";
+ state_bits_to_int <= "000";
+ end generate;
+
+ gen_2: if API_TYPE = 0 generate
+ state_bits <= "000";
+ process(state_to_apl)
+ begin
+ case state_to_apl is
+ when IDLE => state_bits_to_apl <= "000";
+ when MY_ADDR => state_bits_to_apl <= "001";
+ when WRONG_ADDR => state_bits_to_apl <= "100";
+ when others => state_bits_to_apl <= "111";
+ end case;
+ end process;
+ process(state_to_int)
+ begin
+ case state_to_int is
+ when IDLE => state_bits_to_int <= "000";
+ when SEND_HEADER => state_bits_to_int <= "001";
+ when RUNNING => state_bits_to_int <= "010";
+ when SHUTDOWN => state_bits_to_int <= "011";
+ when SEND_SHORT => state_bits_to_int <= "100";
+ when SEND_TRAILER => state_bits_to_int <= "101";
+ when WAITING => state_bits_to_int <= "110";
+ when others => state_bits_to_int <= "111";
+ end case;
+ end process;
+ end generate;
-end architecture;
\ No newline at end of file
+end architecture;
jspc29 / trbnet.git / commitdiff