reset changes, better behaviour

diff --git a/gbe_trb/base/gbe_lsm.vhd b/gbe_trb/base/gbe_lsm.vhd
index 1c9dead640579c04f154ad3fd2f5072e06002836..81ab5d50c7084b4d9503f82b4a4afb03cadc13e2 100644 (file)
--- a/gbe_trb/base/gbe_lsm.vhd
+++ b/gbe_trb/base/gbe_lsm.vhd
@@ -42,10 +42,10 @@ begin
   \r
   THE_DLY_CTR: process( CLK )\r
   begin\r
-    if( rising_edge(CLK) ) then\r
-      if   ( RESET = '1' ) then\r
-        dly_ctr <= (others => '0');\r
-      elsif( rst_dly_ctr = '1' ) then\r
+    if   ( RESET = '1' ) then\r
+      dly_ctr <= (others => '0');\r
+    elsif( rising_edge(CLK) ) then\r
+      if( rst_dly_ctr = '1' ) then\r
         dly_ctr <= (others => '0');\r
       elsif( ce_dly_ctr = '1' ) then\r
         dly_ctr <= dly_ctr + 1;\r
@@ -58,14 +58,12 @@ begin
   -----------------------------------------------------------\r
   -- statemachine: clocked process\r
   -----------------------------------------------------------\r
-  THE_FSM: process( CLK )\r
+  THE_FSM: process( CLK, RESET )\r
   begin\r
-    if( rising_edge(CLK) ) then\r
-      if( RESET = '1' ) then\r
-        STATE <= INACTIVE;\r
-      else\r
-        STATE <= NEXT_STATE;\r
-      end if;\r
+    if   ( RESET = '1' ) then\r
+      STATE <= INACTIVE;\r
+    elsif( rising_edge(CLK) ) then\r
+      STATE <= NEXT_STATE;\r
     end if;\r
   end process THE_FSM;\r
 \r

diff --git a/gbe_trb/base/inserter.vhd b/gbe_trb/base/inserter.vhd
index 727afea1d810a140aaaa518f13983e1b45934508..c93874d233fe31cc11ca7bbf7dbf97ed2d817fdb 100644 (file)
--- a/gbe_trb/base/inserter.vhd
+++ b/gbe_trb/base/inserter.vhd
@@ -7,7 +7,7 @@ library work;
 entity inserter is\r
   port(\r
     CLK           : in  std_logic;\r
-    CLEAR         : in  std_logic;\r
+    CLEAR         : in  std_logic; -- not used\r
     ACTIVE_IN     : in  std_logic;\r
     -- PHY output\r
     PHY_D_IN      : in  std_logic_vector(7 downto 0);\r

diff --git a/gbe_trb/base/parser.vhd b/gbe_trb/base/parser.vhd
index 5f993c5df121e81fa60ef01502b6d2af99041168..9767d375cbb730d4ac0d7c39334c17dbe085a006 100644 (file)
--- a/gbe_trb/base/parser.vhd
+++ b/gbe_trb/base/parser.vhd
@@ -49,14 +49,12 @@ begin
   -----------------------------------------------------------\r
   -- statemachine: clocked process\r
   -----------------------------------------------------------\r
-  THE_FSM: process( CLK )\r
+  THE_FSM: process( CLK, RESET )\r
   begin\r
-    if( rising_edge(CLK) ) then\r
-      if( RESET = '1' ) then\r
-        STATE <= ST0;\r
-      else\r
+    if( RESET = '1' ) then\r
+      STATE <= ST0;\r
+    elsif( rising_edge(CLK) ) then\r
         STATE <= NEXT_STATE;\r
-      end if;\r
     end if;\r
   end process THE_FSM;\r
 \r

diff --git a/gbe_trb/base/remover.vhd b/gbe_trb/base/remover.vhd
index 4c12082510f340b9e22a571af470b5a8a25c87f1..3fc16785a3be467ae504ef1e7cb823827dfdca1f 100644 (file)
--- a/gbe_trb/base/remover.vhd
+++ b/gbe_trb/base/remover.vhd
@@ -7,7 +7,7 @@ library work;
 entity remover is\r
   port(\r
     CLK           : in  std_logic;\r
-    CLEAR         : in  std_logic;\r
+    CLEAR         : in  std_logic; -- not used\r
     ACTIVE_IN     : in  std_logic;\r
     -- SerDes output\r
     RX_D_IN       : in  std_logic_vector(7 downto 0);\r

diff --git a/gbe_trb/base/trb_net16_gbe_mac_control.vhd b/gbe_trb/base/trb_net16_gbe_mac_control.vhd
index 130c15165baf7adb63e11bebec3f9bd1d3ff19fa..978387f5855afbf7969a1b99c0ae6e2b47a8f1f4 100644 (file)
--- a/gbe_trb/base/trb_net16_gbe_mac_control.vhd
+++ b/gbe_trb/base/trb_net16_gbe_mac_control.vhd
@@ -82,14 +82,12 @@ reg_tx_rx_ctrl1(1)           <= '1'; -- receive discard FCS and padding
 reg_tx_rx_ctrl1(0)           <= MC_PROMISC_IN; -- promiscuous mode
 
 
-MAC_CONF_MACHINE_PROC : process(CLK)
+MAC_CONF_MACHINE_PROC : process( CLK, RESET )
 begin
-  if( rising_edge(CLK) ) then
-    if( RESET = '1' ) then
-      mac_conf_current_state <= IDLE;
-    else
-      mac_conf_current_state <= mac_conf_next_state;
-    end if;
+  if   ( RESET = '1' ) then
+    mac_conf_current_state <= IDLE;
+  elsif( rising_edge(CLK) ) then
+    mac_conf_current_state <= mac_conf_next_state;
   end if;
 end process MAC_CONF_MACHINE_PROC;
 

diff --git a/gbe_trb_ecp3/media/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd
index 943104ddb77b371c6340887295f5fa716799caea..2b78765576158989bbe56bdbbdea2f032c22b17d 100644 (file)
--- a/gbe_trb_ecp3/media/gbe_med_fifo.vhd
+++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd
@@ -694,7 +694,7 @@ begin
       SGMII_GBE_PCS : sgmii_gbe_pcs42
       port map(
         rst_n                   => RESET_N, --CLEAR_N,
-        signal_detect           => link_rx_ready(i), --serdes_active(i),
+        signal_detect           => serdes_active(i), --link_rx_ready(i),
         gbe_mode                => '1',
         sgmii_mode              => '0',
         operational_rate        => b"10",
@@ -738,7 +738,7 @@ begin
         mr_page_rx              => mr_page_rx_i(i), --open,
         mr_lp_adv_ability       => open,
         mr_main_reset           => RESET, --CLEAR,
-        mr_an_enable            => link_rx_ready(i), --'1',
+        mr_an_enable            => serdes_active(i), --link_rx_ready(i), --'1',
         mr_restart_an           => '0',
         mr_adv_ability          => x"0020"
       );

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index de4ad43bd9c00c7a1557d8b66e428bf039fd27da..efce1083795af1f4c9accb53409718246f88c338 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -12,7 +12,7 @@ entity sci_reader_RS is
 
   port(
     CLK              : in std_logic;
-    RESET            : in std_logic;
+    RESET            : in std_logic; -- not used
     --SCI
     SCI_WRDATA       : out std_logic_vector(7 downto 0);
     SCI_RDDATA       : in  std_logic_vector(7 downto 0);