compiling version with ADC PLLs rearranged

diff --git a/base/cores/dqsinput.ipx b/base/cores/dqsinput.ipx
index ddcdf1430a634e60ecfefab17fa8ed59242f6cfc..f9a6e2c9bfb59d5b66100b904572546c0adf4904 100644 (file)
--- a/base/cores/dqsinput.ipx
+++ b/base/cores/dqsinput.ipx
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="dqsinput" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 03 27 19:58:13.784" version="5.3" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="dqsinput" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 23:39:55.772" version="5.4" type="Module" synthesis="" source_format="VHDL">
   <Package>
-               <File name="dqsinput.lpc" type="lpc" modified="2013 03 27 19:58:10.000"/>
-               <File name="dqsinput.vhd" type="top_level_vhdl" modified="2013 03 27 19:58:10.000"/>
-               <File name="dqsinput_tmpl.vhd" type="template_vhdl" modified="2013 03 27 19:58:10.000"/>
+               <File name="dqsinput.lpc" type="lpc" modified="2013 10 02 23:39:53.000"/>
+               <File name="dqsinput.vhd" type="top_level_vhdl" modified="2013 10 02 23:39:53.000"/>
+               <File name="dqsinput_tmpl.vhd" type="template_vhdl" modified="2013 10 02 23:39:53.000"/>
   </Package>
 </DiamondModule>

diff --git a/base/cores/dqsinput.lpc b/base/cores/dqsinput.lpc
index 326ccd1f8add1f9289f66106a3f883ed0976bf51..16e4e23768f2d3a46a6b0220162446b04aa078c4 100644 (file)
--- a/base/cores/dqsinput.lpc
+++ b/base/cores/dqsinput.lpc
@@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation
 CoreType=LPM
 CoreStatus=Demo
 CoreName=DDR_GENERIC
-CoreRevision=5.3
+CoreRevision=5.4
 ModuleName=dqsinput
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=03/27/2013
-Time=19:58:10
+Date=10/02/2013
+Time=23:39:53
 
 [Parameters]
 Verilog=0

diff --git a/base/cores/dqsinput.vhd b/base/cores/dqsinput.vhd
index 9be81a03fc158ca710283cdb4585d6e3e2b798a1..e207a19f4e950ee30e1d40e0ddb52de808de82e0 100644 (file)
--- a/base/cores/dqsinput.vhd
+++ b/base/cores/dqsinput.vhd
@@ -1,8 +1,8 @@
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module  Version: 5.3
---/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n dqsinput -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 192 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e 
+-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
+-- Module  Version: 5.4
+--/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n dqsinput -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 192 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e 
 
--- Wed Mar 27 19:58:10 2013
+-- Wed Oct  2 23:39:53 2013
 
 library IEEE;
 use IEEE.std_logic_1164.all;

diff --git a/nxyter/compile_frankfurt.pl b/nxyter/compile_frankfurt.pl
index 05a3bd88a153c80523fad35e9f18ae83f96fcecd..63e4b756b089a810fa15cce25c0c6f0111ab89d1 100755 (executable)
--- a/nxyter/compile_frankfurt.pl
+++ b/nxyter/compile_frankfurt.pl
@@ -9,7 +9,7 @@ use strict;
 ###################################################################################
 #Settings for this project
 my $TOPNAME                      = "trb3_periph";  #Name of top-level entity
-my $lattice_path                 = '/d/jspc29/lattice/diamond/2.01';
+my $lattice_path                 = '/d/jspc29/lattice/diamond/2.1_x64';
 my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
 my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
@@ -112,7 +112,8 @@ execute($c);
 system("rm $TOPNAME.ncd");
 
 
-$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
 execute($c);
 
 # IOR IO Timing Report

diff --git a/nxyter/trb3_periph.p3t b/nxyter/trb3_periph.p3t
new file mode 100644 (file)
index 0000000..2534469
--- /dev/null
+++ b/nxyter/trb3_periph.p3t
@@ -0,0 +1,5 @@
+-rem
+-distrce
+-log "trb3_gbe_trb3_gbe.log"
+-o "trb3_gbe_trb3_gbe.csv"
+-pr "trb3_gbe_trb3_gbe.prf"

diff --git a/nxyter/trb3_periph.pt b/nxyter/trb3_periph.pt
new file mode 100644 (file)
index 0000000..b5319a3
--- /dev/null
+++ b/nxyter/trb3_periph.pt
@@ -0,0 +1,10 @@
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 8
+-sphld m

diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd
index 0c789268ddb4f6dfd3a31df86ec668ee12179cd6..ba13427da702cdec352aba987095003acebf3f0c 100644 (file)
--- a/nxyter/trb3_periph.vhd
+++ b/nxyter/trb3_periph.vhd
@@ -279,7 +279,8 @@ architecture trb3_periph_arch of trb3_periph is
   -- nXyter-FEB-Board Clocks
   signal nx_main_clk                   : std_logic;
   signal pll_nx_clk_lock             : std_logic;
-  signal clk_adc_dat                 : std_logic;
+  signal clk_adc_dat_2               : std_logic;
+  signal clk_adc_dat_1               : std_logic;
   signal pll_adc_clk_lock            : std_logic;
   
   -- nXyter 1 Regio Bus
@@ -344,7 +345,7 @@ begin
 ---------------------------------------------------------------------------
   THE_MAIN_PLL : pll_in200_out100
     port map(
-      CLK   => CLK_GPLL_RIGHT,
+      CLK   => CLK_PCLK_RIGHT,
       CLKOP => clk_100_i,
       CLKOK => clk_200_i,
       LOCK  => pll_lock
@@ -692,7 +693,7 @@ begin
       CLK_IN                     => clk_100_i,
       RESET_IN                   => reset_i,
       CLK_NX_IN                  => nx_main_clk,
-      CLK_ADC_IN                 => clk_adc_dat,
+      CLK_ADC_IN                 => clk_adc_dat_1,
       TRIGGER_OUT                => fee1_trigger,                       
 
       I2C_SDA_INOUT              => NX1_I2C_SDA_INOUT,
@@ -770,7 +771,7 @@ begin
       CLK_IN                     => clk_100_i,
       RESET_IN                   => reset_i,
       CLK_NX_IN                  => nx_main_clk,
-      CLK_ADC_IN                 => clk_adc_dat,
+      CLK_ADC_IN                 => clk_adc_dat_2,
       TRIGGER_OUT                => fee2_trigger,
       
       I2C_SDA_INOUT              => NX2_I2C_SDA_INOUT,
@@ -856,8 +857,14 @@ begin
   -- ClockSource as nXyter Main Clock)
   pll_adc_clk_1: pll_adc_clk
     port map (
-      CLK   => clk_200_i,
-      CLKOP => clk_adc_dat,
+      CLK   => CLK_PCLK_RIGHT,
+      CLKOP => clk_adc_dat_1,
+      LOCK  => pll_adc_clk_lock
+      );
+  pll_adc_clk_2: pll_adc_clk
+    port map (
+      CLK   => CLK_PCLK_RIGHT,
+      CLKOP => clk_adc_dat_2,
       LOCK  => pll_adc_clk_lock
       );
 

diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf
index 6758f2d8f74052be6b017326bd833989fc66a7a2..5af8655cc9ee9fa8a84e53c6972518d69aa5d288 100644 (file)
--- a/nxyter/trb3_periph_constraints.lpf
+++ b/nxyter/trb3_periph_constraints.lpf
@@ -31,28 +31,25 @@
 
   # Not used in current design
   #FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-  #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
   #FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  #USE PRIMARY NET CLK_GPLL_RIGHT; 
-  #USE PRIMARY NET CLK_GPLL_RIGHT_c;
-
-  #FREQUENCY PORT nx_main_clk 250 MHz;
-  USE PRIMARY NET "nx_main_clk"; 
-  #USE PRIMARY NET CLK_GPLL_RIGHT_c;
-
-  LOCATE COMP  THE_MAIN_PLL/PLLInst_0 SITE PLL_R79C5;
-
-
-# Put the names of your nxyter inputs here:  
   FREQUENCY PORT NX1_CLK128_IN 125 MHz;
   FREQUENCY PORT NX2_CLK128_IN 125 MHz;
-  #FREQUENCY PORT NX1_ADC_DCLK_IN 93.75 MHz;   
-  #FREQUENCY PORT NX2_ADC_DCLK_IN 93.75 MHz;  
-
   FREQUENCY PORT NX1_ADC_SAMPLE_CLK_OUT 31.25 MHz;  
   FREQUENCY PORT NX2_ADC_SAMPLE_CLK_OUT 31.25 MHz;  
+  
+  USE PRIMARY NET "nx_main_clk"; 
+  USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT";
+  USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT";
+  USE PRIMARY NET "clk_200_i";
+  USE PRIMARY NET "clk_100_i_c";
+  USE PRIMARY NET "CLK_PCLK_RIGHT_c";
+  
+  #LOCATE COMP  THE_MAIN_PLL/PLLInst_0 SITE PLL_R79C178;
+
+
+# Put the names of your nxyter inputs here:  
 
 # ------ ADC Stuff ---------------------------
 
@@ -62,9 +59,6 @@
   #FREQUENCY PORT clk_adc_dat 93.75 MHz;
   #USE PRIMARY NET "clk_adc_dat";
 
-  USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT";
-  USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT";
-
   #PROHIBIT PRIMARY NET "NX1_ADC_FCLK_IN";
   #PROHIBIT PRIMARY NET "NX1B_ADC_FCLK_IN";
   #PROHIBIT SECONDARY NET "NX1_ADC_FCLK_IN";