+# Word count by `grep -v '^#' abstract.txt | wc -w`
+# Currently 91 (maximum allowed: 100)
+
+The TRB3 features four FPGA-based TDCs with <20ps RMS time precision
+between two channels and 256+4 channels in total. One central FPGA
+provides flexible trigger functionality and GbE connectivity including
+powerful slow control. We present the recent users' applications of
+this platform following the COME&KISS principle: Successful test
+beamtimes at CERN (CBM), in Jülich and Mainz with an FPGA-based
+discriminator board (PaDiWa), a charge-to-width FEE board with high
+dynamic range, read-out of the n-XYTER ASIC and software for data
+unpacking and TDC calibration. We conclude with an outlook on future
+developments.
--- /dev/null
+# Please check your name spelling and affiliation
+# and tell neiser@kph.uni-mainz.de if something is wrong
+# Authors List (first one is presenter, rest alphabetically sorted)
+
+Andreas Neiser [1]
+Joern Adamczewski-Musch [2]
+Matthias Hoek [5] ???
+Wolfgang Koenig [2]
+Grzegorz Korcyl [4]
+Sergey Linev [2]
+Ludwig Maier [6]
+Jan Michel [3]
+Marek Palka [4]
+Manuel Penschuk [3]
+Michael Traxler [2]
+Cahit Ugur [2]
+
+[1] Institute of Nuclear Physics, Mainz - Germany
+[2] GSI Helmholtz Centre for Heavy Ion Research GmbH, Darmstadt - Germany
+[3] Goethe-University, Frankfurt - Germany
+[4] Jagiellonian University, Krakow – Poland
+[5] Helmholtz Institute, Mainz - Germany
+[6] Technische Universität, Munich - Germany
+# Word count by `grep -v '^#' summary.txt | wc -w`
+# Currently 500 (maximum allowed: 500)
+
+The 4+1 FPGA board "TRB3" can serve various applications in
+experimental particle physics and beyond due to its general-purpose
+design. It uses FPGAs as complex commercial electronic components
+while realizing the remaining auxiliary parts with simple standard
+components. Consequently, the board provides flexible connectivity by
+eight SFP ports and mezzanine extensions for every FPGA including a
+high pin-out for the peripheral FPGAs. We call this concept COME&KISS:
+COMplex COMmercial Elements & Keep It Small and Simple. This ensures a
+wide range of applications in data acquisition scenarios as well as a
+long-term maintainability of the platform.
+
+Usually, in each of the four peripheral FPGAs a tapped delay line TDC
+is implemented with <20ps RMS time precision between two channels
+providing 64 channels plus one reference channel. The TDCs are used
+for leading edge measurements, for example from time of flight
+experiments, or by using the TDC channels in pairs, one can
+additionally extract the width of the digital pulse. The central FPGA
+serves as a flexible central trigger system and manages slow control
+and read-out of the peripheral FPGAs over a single gigabit Ethernet
+connection. The project provides a comfortable, robust and modular
+software environment, ranging from low-level register access to the
+FPGA firmwares on the command line to high-level control web2.0
+technologies. This is complemented by comprehensive specifications and
+documentation.
+
+To convert the analog signals from the detector to digital pulses
+suitable for the TDC, the front-end electronics board PaDiWa was
+designed using the differential input buffers of an FPGA as
+discriminators with a PWM generated voltage as a variable threshold.
+However, for calorimeters the charge information of the pulse
+extracted from time over threshold is usually not sufficient. Thus,
+the leading edge measurement can complemented by a modified Wilkinson
+ADC circuit, which encodes the charge in the width of the digital
+pulse delivered to the TDC. A proof-of-concept board was successfully
+tested and a version with an improved dynamic range is currently
+designed. Both approaches follow again the COME&KISS principle,
+already enabling other groups to use the existing FEE boards without
+major modifications. The overall reliability, flexibility and
+performance of this platform was proven in three test beamtimes with
+different detectors and FEEs at CERN (CBM), in Jülich and Mainz with
+up to 2400 channels, of which results are shown.
+
+Furthermore, the TRB3 can be used as an infrastructure to read-out
+specialized integrated solutions using the peripheral FPGAs, for
+example to provide a timing reference, transport the acquired data to
+the eventbuilder and slow control configuration of the chip. This was
+realized for the n-XYTER ASIC. Additionally, the platform enables
+every user group to profit from common software developments, such as
+an unpacker for the TDC datastream including the necessary calibration
+of the delay lines.
+
+Finally, we present planned extensions of the platform: The detection
+of leading and trailing edge in a single TDC channel, which doubles
+the number of channels per board for timestamp and width measurements,
+and the integration in data acquisition frameworks such as DABC.
jspc29 / conferences.git / commitdiff