relaxed timing for muxing data

diff --git a/gbe_trb/base/rx_rb.vhd b/gbe_trb/base/rx_rb.vhd
index 0c57f4661f804b413e270654f42abb1a5b826bcd..31f3f5e0c771dba0ceb15618809bf8c01145aef0 100644 (file)
--- a/gbe_trb/base/rx_rb.vhd
+++ b/gbe_trb/base/rx_rb.vhd
@@ -50,25 +50,26 @@ architecture rx_rb_arch of rx_rb is
   signal STATE, NEXT_STATE    : state_t;\r
 \r
 -- Signals\r
-  signal rd_ptr          : unsigned(11 downto 0);\r
-  signal wr_ptr          : unsigned(11 downto 0);\r
-  signal last_wr_ptr     : std_logic_vector(11 downto 0);\r
-  signal rb_used         : unsigned(11 downto 0);\r
-  signal rb_full         : std_logic;\r
-  signal rb_empty        : std_logic;\r
-  signal ce_wr_ptr       : std_logic;\r
-  signal ld_wr_ptr       : std_logic;\r
-  signal ce_rd_ptr       : std_logic;\r
-  signal wr_ram          : std_logic;\r
-  signal rd_ram          : std_logic;\r
-  signal ram_q           : std_logic_vector(8 downto 0);\r
-  signal frame_active    : std_logic;\r
-  signal frame_requested : std_logic;\r
-  signal fifo_wr_int     : std_logic;\r
-  signal empty_read_ack  : std_logic;\r
-  signal normal_read_ack : std_logic;\r
-  signal sof_int         : std_logic;\r
-  signal frames_avail    : unsigned(7 downto 0);\r
+  signal rd_ptr             : unsigned(11 downto 0);\r
+  signal wr_ptr             : unsigned(11 downto 0);\r
+  signal last_wr_ptr        : std_logic_vector(11 downto 0);\r
+  signal rb_used            : unsigned(11 downto 0);\r
+  signal rb_full            : std_logic;\r
+  signal rb_empty           : std_logic;\r
+  signal ce_wr_ptr          : std_logic;\r
+  signal ld_wr_ptr          : std_logic;\r
+  signal ce_rd_ptr          : std_logic;\r
+  signal wr_ram             : std_logic;\r
+  signal rd_ram             : std_logic;\r
+  signal ram_q              : std_logic_vector(8 downto 0);\r
+  signal frame_active       : std_logic;\r
+  signal frame_requested    : std_logic;\r
+  signal frame_acknowledged : std_logic;\r
+  signal fifo_wr_int        : std_logic;\r
+  signal empty_read_ack     : std_logic;\r
+  signal normal_read_ack    : std_logic;\r
+  signal sof_int            : std_logic;\r
+  signal frames_avail       : unsigned(7 downto 0);\r
 \r
 \r
 begin\r
@@ -180,6 +181,7 @@ begin
   empty_read_ack <= FRAME_REQ_IN and rb_empty when rising_edge(CLK);\r
   \r
   -- NormalReadAck signal\r
+--  normal_read_ack <= ram_q(8) and fifo_wr_int when rising_edge(CLK); -- ADDED 2nd step\r
   normal_read_ack <= ram_q(8) and fifo_wr_int;\r
   \r
   -- read signal\r
@@ -188,15 +190,15 @@ begin
   \r
   sof_int <= FRAME_REQ_IN and not frame_requested when rising_edge(CLK);\r
   \r
-  FRAME_ACK_OUT <= normal_read_ack or empty_read_ack;\r
+  FRAME_ACK_OUT <= normal_read_ack or empty_read_ack when rising_edge(CLK); -- ADDED\r
   \r
-  FRAME_START_OUT <= sof_int;\r
+  FRAME_START_OUT <= sof_int when rising_edge(CLK); -- ADDED\r
   \r
-  FIFO_Q_OUT <= ram_q;\r
+  FIFO_Q_OUT <= ram_q when rising_edge(CLK); -- ADDED\r
   \r
   fifo_wr_int <= rd_ram when rising_edge(CLK);\r
    \r
-  FIFO_WR_OUT <= fifo_wr_int;\r
+  FIFO_WR_OUT <= fifo_wr_int when rising_edge(CLK); -- ADDED\r
   \r
   -- FramesAvailable counter\r
   THE_FRAMES_AVAIL_PROC: process( CLK )\r