constant USE_200MHZOSCILLATOR : integer := c_YES;
constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)?
-
+
+ constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
+
--Use sync mode, RX clock for all parts of the FPGA
constant USE_RXCLOCK : integer := c_NO;
add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
#Hub
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_accel.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_accel.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"