changed ECP5 Serdes settings

diff --git a/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd b/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd
index c8b0baaf60fccdb82e711c9a87c6aa049892fceb..420b0ed39df9fe61f3cff4f9f7f731d272a2d3f3 100644 (file)
--- a/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd
+++ b/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd
@@ -114,7 +114,7 @@ architecture v1 of serdes_sync_0 is
     end component serdes_sync_0rsl_core; -- syn_black_box=1    -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88)
     component serdes_sync_0sll_core is
         generic (PPROTOCOL: string := "G8B10B";
-            PLOL_SETTING: integer := 1;
+            PLOL_SETTING: integer := 0;
             PDYN_RATE_CTRL: string := "DISABLED";
             PPCIE_MAX_RATE: string := "2.5";
             PDIFF_VAL_LOCK: integer := 20;
@@ -159,7 +159,7 @@ begin
     pll_lol <= pll_lol_c;
     DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
         D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
-        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
         CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",

diff --git a/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd b/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd
index 688815c3f4d47edb984916c9295f85934407bd94..f75db06b13bc3834cc822a45e40a407a3722b781 100644 (file)
--- a/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd
+++ b/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd
@@ -159,7 +159,7 @@ begin
     pll_lol <= pll_lol_c;
     DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
         D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
-        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0",
         CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0",

diff --git a/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd b/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd
index d769bb88eb4fe558a8f60af2074a1c363812314f..0651ba5a7ad2c21c5f644293c7a7f24de55663fa 100644 (file)
--- a/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd
+++ b/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd
@@ -159,7 +159,7 @@ begin
     pll_lol <= pll_lol_c;
     DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
         D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
-        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
         CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",

diff --git a/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd b/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd
index 39c1ff973fff102a3805c5cf4cd2b8d98a6b9f3c..f3193c366e8aba374a05a74251012a2c6ce7eea9 100644 (file)
--- a/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd
+++ b/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd
@@ -127,7 +127,7 @@ begin
     rx_cdr_lol_s <= rx_cdr_lol_s_c;
     DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
         D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
-        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0",
         CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0",

diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd
index f58d70227b17ec401bdc897bbf0f7f0391eba8da..d62e2ee93e8b34de2db6d65a5020a23ccf38a288 100644 (file)
--- a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd
+++ b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd
@@ -159,7 +159,7 @@ begin
     pll_lol <= pll_lol_c;
     DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
         D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
-        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
         CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",

diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd
index f8a36f262b7c0b7474be5634fdfe875197a7410e..30e182aaeba7bd87f32c734871770cdd777c2584 100644 (file)
--- a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd
+++ b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd
@@ -127,7 +127,7 @@ begin
     rx_cdr_lol_s <= rx_cdr_lol_s_c;
     DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
         D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
-        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0",
         CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0",

diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd
index 56647c2292b95ce0419574dc895ef793672a4791..62e277572a0f9220d83d8931d20ffe94780b9c92 100644 (file)
--- a/media_interfaces/med_ecp5_sfp_sync.vhd
+++ b/media_interfaces/med_ecp5_sfp_sync.vhd
@@ -110,15 +110,16 @@ attribute nopad : string;
 attribute nopad of  hdinp, hdinn, hdoutp, hdoutn : signal is "true";
 
 signal stat_med           : std_logic_vector(31 downto 0);
-signal timer              : unsigned(31 downto 0);
+signal timer              : unsigned(32 downto 0);
 
 begin
 
 reset_n <= not RESET;
-clk_200_ref <= CLK_REF_FULL;
+clk_200_ref <= CLK_INTERNAL_FULL;
 
-SD_TXDIS_OUT <= not rx_ready when IS_SYNC_SLAVE = 1 else '0';   --slave only switches on when RX is ready
+SD_TXDIS_OUT <= not MEDIA_MED2INT.stat_op(4) when IS_SYNC_SLAVE = 1 else '0';   --slave only switches on when RX is ready, on rx_allow
 
+--'0'; --not rx_ready when IS_SYNC_SLAVE = 1 else '0';   --slave only switches on when RX is ready
 -- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
 --   clk_200_i        <= clk_rx_full;
 -- end generate;
@@ -179,7 +180,7 @@ gen_pcs0 : if SERDES_NUM = 0 or SERDES_NUM = 1 generate -- same entity in any ca
       serdes_sync_0_serdes_pdb           => '1', 
       serdes_sync_0_tx_serdes_rst_c      => tx_serdes_rst,
 
-      serdes_sync_0_pll_refclki          => CLK_REF_FULL,
+      serdes_sync_0_pll_refclki          => CLK_INTERNAL_FULL,
       serdes_sync_0_pll_lol              => tx_pll_lol,
       serdes_sync_0_rsl_disable          => '1',
       serdes_sync_0_rsl_rst              => '0',
@@ -238,7 +239,7 @@ gen_pcs2 : if SERDES_NUM = 2 generate
       serdes_sync_0_serdes_pdb           => '1', 
       serdes_sync_0_tx_serdes_rst_c      => tx_serdes_rst,
 
-      serdes_sync_0_pll_refclki          => CLK_REF_FULL,
+      serdes_sync_0_pll_refclki          => CLK_INTERNAL_FULL,
       serdes_sync_0_pll_lol              => tx_pll_lol,
       serdes_sync_0_rsl_disable          => '1',
       serdes_sync_0_rsl_rst              => '0',
@@ -295,8 +296,8 @@ THE_MED_CONTROL : entity work.med_sync_control
     RX_DLM_WORD   => RX_DLM_WORD,
     RX_DLM        => RX_DLM,
     
-    SERDES_RX_READY_IN => rx_ready,
-    SERDES_TX_READY_IN => tx_ready,
+    -- SERDES_RX_READY_IN => rx_ready,
+    -- SERDES_TX_READY_IN => tx_ready,
     
     STAT_TX_CONTROL  => stat_tx_control_i,
     STAT_RX_CONTROL  => stat_rx_control_i,
@@ -336,10 +337,15 @@ THE_SCI_READER : entity work.sci_reader
     DEBUG_OUT   => open
     );
 
-STAT_DEBUG(11 downto 0)  <= debug_med_sync_control_i(11 downto 0);
-STAT_DEBUG(15 downto 12) <= (others => '0');
-STAT_DEBUG(31 downto 16) <= wa_position;
-STAT_DEBUG(63 downto 32) <= (others => '0');
+STAT_DEBUG(12 downto 0)  <= debug_med_sync_control_i(12 downto 0);
+STAT_DEBUG(13)           <= lsm_status;
+STAT_DEBUG(14)           <= rx_cdr_lol;
+STAT_DEBUG(15)           <= rx_error;
+STAT_DEBUG(19 downto 16) <= debug_med_sync_control_i(16 downto 13);
+STAT_DEBUG(20)           <= rx_ready;
+STAT_DEBUG(21)           <= tx_ready;
+STAT_DEBUG(22)           <= clk_rx_full;
+STAT_DEBUG(63 downto 23) <= (others => '0');
 
 stat_med(0) <= rst_qd; 
 stat_med(1) <= rx_pcs_rst;
@@ -352,7 +358,7 @@ stat_med(7) <= rx_ready;
 stat_med(8) <= tx_ready;
 stat_med(9) <= lsm_status;
 stat_med(15 downto 10) <= (others => '0');
-stat_med(31 downto 16) <= timer(30 downto 15);
+stat_med(31 downto 16) <= timer(32 downto 17);
   
   
   PROC_TIMER : process begin

diff --git a/media_interfaces/med_ecp5_sfp_sync_2.vhd b/media_interfaces/med_ecp5_sfp_sync_2.vhd
index 7f75ad5f67fec32e59a006a3687c0bbe2445c9e6..aee845356c9831c9ae73125324020a10f7239d5c 100644 (file)
--- a/media_interfaces/med_ecp5_sfp_sync_2.vhd
+++ b/media_interfaces/med_ecp5_sfp_sync_2.vhd
@@ -39,10 +39,10 @@ entity med_ecp5_sfp_sync_2 is
     SD_TXDIS_OUT       : out  std_logic_vector(1 downto 0) := "00"; -- SFP disable
     --Control Interface
     BUS_RX             : in  CTRLBUS_RX;
-    BUS_TX             : out CTRLBUS_TX
+    BUS_TX             : out CTRLBUS_TX;
 
     -- Status and control port
---     STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0)
 --     CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
    );
 end entity;
@@ -110,17 +110,18 @@ attribute nopad of  hdinp, hdinn, hdoutp, hdoutn : signal is "true";
 
 signal stat_med : std_logic_vector(63 downto 0);
 
-type timer_t is array(0 to 1) of unsigned(31 downto 0);
+type timer_t is array(0 to 1) of unsigned(32 downto 0);
 signal timer : timer_t;
 
 begin
 
 reset_n <= not RESET;
-clk_200_ref <= CLK_REF_FULL;
+clk_200_ref <= CLK_INTERNAL_FULL;
 
+signal_detect_i <= '1' when USE_NEW_ECP5_RESET = 1 else '0';
 
 gen_txdis : for i in 0 to 1 generate
-  SD_TXDIS_OUT(i) <= not rx_ready(i)  when IS_SYNC_SLAVE(i) = 1 else '0';   --slave only switches on when RX is ready
+  SD_TXDIS_OUT(i) <= not MEDIA_MED2INT(i).stat_op(4)  when IS_SYNC_SLAVE(i) = 1 else '0';   --slave only switches on when RX is ready
 end generate;  
 -- SD_TXDIS_OUT <= RESET;
 
@@ -132,7 +133,6 @@ end generate;
 --   clk_200_i        <= clk_200_internal;
 -- end generate;
 
-    signal_detect_i <= '1' when USE_NEW_ECP5_RESET = 1 else '0';
 
 -------------------------------------------------      
 -- Serdes
@@ -221,7 +221,7 @@ THE_SERDES : entity work.dual_serdes
         serdes0_pll_lol          => tx_pll_lol,
         
         serdes1_cyawstn          => '0',
-        serdes1_pll_refclki      => CLK_REF_FULL,
+        serdes1_pll_refclki      => CLK_INTERNAL_FULL,
         serdes1_serdes_pdb       => '1'
     );
 end generate;
@@ -310,7 +310,7 @@ THE_SERDES : entity work.dual_serdes_1
         serdes0_pll_lol          => tx_pll_lol,
         
         serdes1_cyawstn          => '0',
-        serdes1_pll_refclki      => CLK_REF_FULL,
+        serdes1_pll_refclki      => CLK_INTERNAL_FULL,
         serdes1_serdes_pdb       => '1'
     );
 end generate;
@@ -379,7 +379,7 @@ THE_MED_CONTROL : entity work.med_sync_control
 --  STAT_DEBUG(9)  <= CLK_REF_FULL;
 --  STAT_DEBUG(10) <= clk_rx_full;
 --  STAT_DEBUG(11) <= clk_tx_full;
-
+  STAT_DEBUG(22) <= clk_rx_full(0);
 
   stat_med(i*32+0) <= rst_qd(i); 
   stat_med(i*32+1) <= rx_pcs_rst(i);
@@ -392,7 +392,7 @@ THE_MED_CONTROL : entity work.med_sync_control
   stat_med(i*32+8) <= tx_ready(i);
   stat_med(i*32+9) <= lsm_status(i);
   stat_med(i*32+15 downto i*32+10) <= (others => '0');
-  stat_med(i*32+31 downto i*32+16) <= timer(i)(30 downto 15);
+  stat_med(i*32+31 downto i*32+16) <= timer(i)(32 downto 17);
   
   
   PROC_TIMER : process begin

diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd
index a391ec482246180d5ea6c3741fde9e4de78cdea8..dfbc73a050eb7ff397ea34cebbdaad5fad5a31a1 100644 (file)
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@ -67,7 +67,7 @@ architecture med_sync_control_arch of med_sync_control is
 signal rx_fsm_state : std_logic_vector(3 downto 0);
 signal tx_fsm_state : std_logic_vector(3 downto 0);
 signal wa_position_rx : std_logic_vector(3 downto 0);
-signal start_timer       : unsigned(21 downto 0) := (others => '0');
+signal start_timer       : unsigned(23 downto 0) := (others => '0');
 
 signal request_retr_i     : std_logic;
 signal start_retr_i       : std_logic;
@@ -117,7 +117,8 @@ begin
 rst_n_tx  <=       not (CLEAR or sd_los_i or make_link_reset_real_i or RESET) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1)
               else not (CLEAR or make_link_reset_real_i or RESET);
 
-rst_n     <= not (CLEAR or sd_los_i or make_link_reset_real_i or RESET);
+rst_n     <=   (CLEAR or sd_los_i or make_link_reset_real_i or RESET) when USE_NEW_ECP5_RESET = 0
+          else (CLEAR or sd_los_i);
 reset_i   <=     (RESET or sd_los_i or make_link_reset_real_i);
 
 media_med2int_i.clk_half <= CLK_RXHALF;
@@ -143,7 +144,7 @@ gen_rx_fsm : if USE_NEW_ECP5_RESET = 0 generate
 else generate
   THE_MAIN_RX_RST: main_rx_reset_RS 
     port map(
-      CLEAR             => CLEAR, --CLEAR, -- should work
+      CLEAR             => rst_n, --CLEAR, -- should work
       CLK_REF           => CLK_REF, -- ok
       CDR_LOL_IN        => RX_CDR_LOL, -- ok
       CV_IN             => RX_CV, -- ok
@@ -226,13 +227,15 @@ wa_position_rx <= x"0";
 PROC_ALLOW : process begin
   wait until rising_edge(CLK_SYS);
   if( (finished_reset_rx_q = '1')   
-            and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') ) then
+            and ((IS_SYNC_SLAVE = 1 and not start_timer(start_timer'left downto start_timer'left-2) = "000") 
+                 or start_timer(start_timer'left) = '1') ) then
     rx_allow <= '1';
   else
     rx_allow <= '0';
   end if;
   if( (finished_reset_tx_q = '1' and finished_reset_rx_q = '1') 
-            and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') ) then
+            and ((IS_SYNC_SLAVE = 1 and not start_timer(start_timer'left downto start_timer'left-2) = "000") 
+                 or start_timer(start_timer'left) = '1') ) then
     tx_allow <= '1';
   else
     tx_allow <= '0';