--- /dev/null
+######################################################################\r
+# ADCMv3 pinouts\r
+######################################################################\r
+\r
+COMMERCIAL;\r
+BLOCK RESETPATHS;\r
+BLOCK ASYNCPATHS;\r
+\r
+######################################################################\r
+# I/O bank 8 - 3.30V\r
+# JTAG and SPI boot interface\r
+######################################################################\r
+#\r
+# These signals are not user definable! Hands off!\r
+\r
+######################################################################\r
+# I/O bank 7 - 2.50V\r
+# APV1 control signals, ADC1 inputs\r
+######################################################################\r
+LOCATE COMP "APV1A_CLK" SITE "J8" ;\r
+IOBUF PORT "APV1A_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1B_CLK" SITE "G5" ;\r
+IOBUF PORT "APV1B_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1A_TRG" SITE "L5" ;\r
+IOBUF PORT "APV1A_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1B_TRG" SITE "G6" ;\r
+IOBUF PORT "APV1B_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1_SDA" SITE "K7" ;\r
+IOBUF PORT "APV1_SDA" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV1_SCL" SITE "K6" ;\r
+IOBUF PORT "APV1_SCL" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV1_RST" SITE "K5" ;\r
+IOBUF PORT "APV1_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "ADC1_LCLK" SITE "L3" ;\r
+IOBUF PORT "ADC1_LCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_ADCLK" SITE "D2" ;\r
+IOBUF PORT "ADC1_ADCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_7" SITE "E2" ;\r
+IOBUF PORT "ADC1_OUT_7" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_6" SITE "G2" ;\r
+IOBUF PORT "ADC1_OUT_6" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_5" SITE "J5" ;\r
+IOBUF PORT "ADC1_OUT_5" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_4" SITE "J3" ;\r
+IOBUF PORT "ADC1_OUT_4" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_3" SITE "K2" ;\r
+IOBUF PORT "ADC1_OUT_3" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_2" SITE "N5" ;\r
+IOBUF PORT "ADC1_OUT_2" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_1" SITE "M4" ;\r
+IOBUF PORT "ADC1_OUT_1" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_0" SITE "P3" ;\r
+IOBUF PORT "ADC1_OUT_0" IO_TYPE=LVDS25 ;\r
+\r
+LOCATE COMP "ADC1_CLK" SITE "H2" ;\r
+IOBUF PORT "ADC1_CLK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "ADC1_RST" SITE "G3" ;\r
+IOBUF PORT "ADC1_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC1_CS" SITE "E1" ;\r
+IOBUF PORT "ADC1_CS" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC1_PD" SITE "H1" ;\r
+IOBUF PORT "ADC1_PD" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC1_SDI" SITE "F2" ;\r
+IOBUF PORT "ADC1_SDI" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "ADC1_SCK" SITE "F1" ;\r
+IOBUF PORT "ADC1_SCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "FPGA_LED_ADC_1" SITE "H3" ;\r
+IOBUF PORT "FPGA_LED_ADC_1" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# LOCATE COMP "ADC1_DEBUG" SITE "H4" ;\r
+# IOBUF PORT "ADC1_DEBUG" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_7_IN" SITE "E3" ;\r
+# LOCATE COMP "PIN_CHECK_7_OUT" SITE "E4" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 6 - 2.50V\r
+# APV0 control signals, ADC0 inputs, 12 test outputs to pads\r
+######################################################################\r
+LOCATE COMP "APV0A_CLK" SITE "AC7" ;\r
+IOBUF PORT "APV0A_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0B_CLK" SITE "W3" ;\r
+IOBUF PORT "APV0B_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0A_TRG" SITE "Y9" ;\r
+IOBUF PORT "APV0A_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0B_TRG" SITE "AB4" ;\r
+IOBUF PORT "APV0B_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0_SDA" SITE "Y6" ;\r
+IOBUF PORT "APV0_SDA" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV0_SCL" SITE "AA6" ;\r
+IOBUF PORT "APV0_SCL" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV0_RST" SITE "AA5" ;\r
+IOBUF PORT "APV0_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "ADC0_LCLK" SITE "T3" ;\r
+IOBUF PORT "ADC0_LCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_ADCLK" SITE "R3" ;\r
+IOBUF PORT "ADC0_ADCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_7" SITE "T5" ;\r
+IOBUF PORT "ADC0_OUT_7" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_6" SITE "U3" ;\r
+IOBUF PORT "ADC0_OUT_6" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_5" SITE "U5" ;\r
+IOBUF PORT "ADC0_OUT_5" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_4" SITE "Y1" ;\r
+IOBUF PORT "ADC0_OUT_4" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_3" SITE "AA1" ;\r
+IOBUF PORT "ADC0_OUT_3" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_2" SITE "AB2" ;\r
+IOBUF PORT "ADC0_OUT_2" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_1" SITE "AC1" ;\r
+IOBUF PORT "ADC0_OUT_1" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_0" SITE "AD2" ;\r
+IOBUF PORT "ADC0_OUT_0" IO_TYPE=LVDS25 ;\r
+\r
+LOCATE COMP "ADC0_CLK" SITE "W1" ;\r
+IOBUF PORT "ADC0_CLK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4;\r
+LOCATE COMP "ADC0_RST" SITE "AD3" ;\r
+IOBUF PORT "ADC0_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC0_CS" SITE "AC3" ;\r
+IOBUF PORT "ADC0_CS" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC0_PD" SITE "V1" ;\r
+IOBUF PORT "ADC0_PD" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC0_SDI" SITE "AB1" ;\r
+IOBUF PORT "ADC0_SDI" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "ADC0_SCK" SITE "W2" ;\r
+IOBUF PORT "ADC0_SCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "FPGA_LED_ADC_0" SITE "V2" ;\r
+IOBUF PORT "FPGA_LED_ADC_0" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# LOCATE COMP "ADC0_DEBUG" SITE "AC5" ;\r
+# IOBUF PORT "ADC0_DEBUG" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 5 - 3.30V\r
+# LVDS driver control, backplane sense pins\r
+######################################################################\r
+LOCATE COMP "ENA_LVDS_7" SITE "AG2" ;\r
+LOCATE COMP "ENA_LVDS_6" SITE "AG3" ;\r
+LOCATE COMP "ENA_LVDS_5" SITE "AG4" ;\r
+LOCATE COMP "ENA_LVDS_4" SITE "AG5" ;\r
+LOCATE COMP "ENA_LVDS_3" SITE "AG11" ;\r
+LOCATE COMP "ENA_LVDS_2" SITE "AG12" ;\r
+LOCATE COMP "ENA_LVDS_1" SITE "AG13" ;\r
+LOCATE COMP "ENA_LVDS_0" SITE "AG15" ;\r
+# LOCATE COMP "FPGA_SECTOR_5" SITE "AF16" ;\r
+# IOBUF PORT "FPGA_SECTOR_5" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SECTOR_4" SITE "AE16" ;\r
+# IOBUF PORT "FPGA_SECTOR_4" IO_TYPE=LVTTL33 ;\r
+# Backplane sense wires: sector number\r
+# small assembly bug: switch is 180degree rotated, so number are mirrored\r
+LOCATE COMP "BP_SECTOR_3" SITE "AF11" ; # was "AF15"\r
+IOBUF PORT "BP_SECTOR_3" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_SECTOR_2" SITE "AF12" ; # was "AF13"\r
+IOBUF PORT "BP_SECTOR_2" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_SECTOR_1" SITE "AF13" ; # was "AF12"\r
+IOBUF PORT "BP_SECTOR_1" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_SECTOR_0" SITE "AF15" ; # was "AF11"\r
+IOBUF PORT "BP_MODULE_0 IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+\r
+LOCATE COMP "BP_LED" SITE "AE8" ;\r
+IOBUF PORT "BP_LED" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ;\r
+\r
+# LOCATE COMP "FPGA_SPARE_4" SITE "AF10" ;\r
+# IOBUF PORT "FPGA_SPARE_4" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_3" SITE "AG8" ;\r
+# IOBUF PORT "FPGA_SPARE_3" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_2" SITE "AF8" ;\r
+# IOBUF PORT "FPGA_SPARE_2" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_1" SITE "AG10" ;\r
+# IOBUF PORT "FPGA_SPARE_1" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_0" SITE "AG9" ;\r
+# IOBUF PORT "FPGA_SPARE_0" IO_TYPE=LVTTL33 ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_5_IN" SITE "AF4" ;\r
+# LOCATE COMP "PIN_CHECK_5_OUT" SITE "AF3" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 4 - 3.30V\r
+# 100MHZ clock in, SPI user pins, APV0 OneWire\r
+######################################################################\r
+LOCATE COMP "CLK100M" SITE "AJ14" ;\r
+IOBUF PORT "CLK100M" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0_1W_7" SITE "AJ16" ;\r
+IOBUF PORT "APV0_1W_7" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_6" SITE "AK16" ;\r
+IOBUF PORT "APV0_1W_6" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_5" SITE "AJ17" ;\r
+IOBUF PORT "APV0_1W_5" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_4" SITE "AK17" ;\r
+IOBUF PORT "APV0_1W_4" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_3" SITE "AG18" ;\r
+IOBUF PORT "APV0_1W_3" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_2" SITE "AG19" ;\r
+IOBUF PORT "APV0_1W_2" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_1" SITE "AG20" ;\r
+IOBUF PORT "APV0_1W_1" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_0" SITE "AG21" ;\r
+IOBUF PORT "APV0_1W_0" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+# LOCATE COMP "EXP_2" SITE "AF21" ;\r
+# IOBUF PORT "EXP_2" IO_TYPE=LVTTL33;\r
+# LOCATE COMP "EXP_1" SITE "AE20" ;\r
+# IOBUF PORT "EXP_1" IO_TYPE=LVTTL33;\r
+# LOCATE COMP "EXP_0" SITE "AE21" ;\r
+# IOBUF PORT "EXP_0" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "U_SPI_SDO" SITE "AE24" ;\r
+IOBUF PORT "U_SPI_SDO" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "U_SPI_SDI" SITE "AE25" ;\r
+IOBUF PORT "U_SPI_SDI" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "U_SPI_CS" SITE "AD24" ;\r
+IOBUF PORT "U_SPI_CS" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "U_SPI_SCK" SITE "AF26" ;\r
+IOBUF PORT "U_SPI_SCK" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+\r
+LOCATE COMP "FPGA_LED_PLL" SITE "AG22" ;\r
+IOBUF PORT "FPGA_LED_PLL" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_4_IN" SITE "AD23" ;\r
+# LOCATE COMP "PIN_CHECK_4_OUT" SITE "AC23" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 3 - 3.30V\r
+# uC connection, external inputs, debug pins (SMC50)\r
+######################################################################\r
+LOCATE COMP "EXT_IN_3" SITE "AA30" ;\r
+IOBUF PORT "EXT_IN_3" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "EXT_IN_2" SITE "AB30" ;\r
+IOBUF PORT "EXT_IN_2" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "EXT_IN_1" SITE "AB29" ;\r
+IOBUF PORT "EXT_IN_1" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "EXT_IN_0" SITE "AB28" ;\r
+# alternative, if needed\r
+# LOCATE COMP "EXT_IN_0" SITE "P28" ;\r
+IOBUF PORT "EXT_IN_0" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "DBG_EXP_41" SITE "T27" ;\r
+# LOCATE COMP "DBG_EXP_39" SITE "T26" ;\r
+# LOCATE COMP "DBG_EXP_37" SITE "U26" ;\r
+# LOCATE COMP "DBG_EXP_35" SITE "V25" ;\r
+# LOCATE COMP "DBG_EXP_33" SITE "W25" ;\r
+# LOCATE COMP "DBG_EXP_31" SITE "W26" ;\r
+# LOCATE COMP "DBG_EXP_29" SITE "Y26" ;\r
+# LOCATE COMP "DBG_EXP_27" SITE "Y27" ;\r
+# LOCATE COMP "DBG_EXP_25" SITE "AB26" ;\r
+# LOCATE COMP "DBG_EXP_23" SITE "AC27" ;\r
+# LOCATE COMP "DBG_EXP_21" SITE "U25" ;\r
+# LOCATE COMP "DBG_EXP_19" SITE "U28" ;\r
+# LOCATE COMP "DBG_EXP_17" SITE "U27" ;\r
+# LOCATE COMP "DBG_EXP_5" SITE "R28" ;\r
+# LOCATE COMP "DBG_EXP_3" SITE "R27" ;\r
+# LOCATE COMP "DBG_EXP_1" SITE "T28" ;\r
+LOCATE COMP "UC_REBOOT" SITE "Y28" ; # was UC_FPGA3\r
+IOBUF PORT "UC_REBOOT" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_FPGA_2" SITE "W27" ;\r
+# IOBUF PORT "UC_FPGA_2" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_FPGA_1" SITE "W28" ;\r
+# IOBUF PORT "UC_FPGA_1" IO_TYPE=LVTTL33 ;\r
+# UC_FPGA_0 pin is GSR\r
+LOCATE COMP "UC_RESET" SITE "V26" ;\r
+IOBUF PORT "UC_RESET" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_WR" SITE "P29" ;\r
+# IOBUF PORT "UC_WR" IO_TYPE=LVTTL33;\r
+# LOCATE COMP "UC_RD" SITE "P30" ;\r
+# IOBUF PORT "UC_RD" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_ALE" SITE "W29" ;\r
+# IOBUF PORT "UC_ALE" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_SCL" SITE "N30" ;\r
+# IOBUF PORT "UC_SCL" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_SDA" SITE "N29" ;\r
+# IOBUF PORT "UC_SDA" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_7" SITE "W30" ;\r
+# IOBUF PORT "UC_AD_7" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_6" SITE "Y29" ;\r
+# IOBUF PORT "UC_AD_6" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_5" SITE "Y30" ;\r
+# IOBUF PORT "UC_AD_5" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_4" SITE "AA29" ;\r
+# IOBUF PORT "UC_AD_4" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_3" SITE "AB27" ;\r
+# IOBUF PORT "UC_AD_3" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_2" SITE "AC29" ;\r
+# IOBUF PORT "UC_AD_2" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_1" SITE "AC30" ;\r
+# IOBUF PORT "UC_AD_1" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_0" SITE "AC28" ;\r
+# IOBUF PORT "UC_AD_0" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_15" SITE "V30" ;\r
+# IOBUF PORT "UC_A_15" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_14" SITE "V29" ;\r
+# IOBUF PORT "UC_A_14" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_13" SITE "U30" ;\r
+# IOBUF PORT "UC_A_13" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_12" SITE "U29" ;\r
+# IOBUF PORT "UC_A_12" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_11" SITE "T30" ;\r
+# IOBUF PORT "UC_A_11" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_10" SITE "T29" ;\r
+# IOBUF PORT "UC_A_10" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_9" SITE "R30" ;\r
+# IOBUF PORT "UC_A_9" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_8" SITE "R29" ;\r
+# IOBUF PORT "UC_A_8" IO_TYPE=LVTTL33 ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 2 - 3.30V\r
+# SFP control, LEDs, 1Wire ID, debug pins (SMC50)\r
+######################################################################\r
+# LOCATE COMP "DBG_EXP_43" SITE "R26" ;\r
+# LOCATE COMP "DBG_EXP_42" SITE "P25" ;\r
+# LOCATE COMP "DBG_EXP_40" SITE "P26" ;\r
+# LOCATE COMP "DBG_EXP_38" SITE "N25" ;\r
+# LOCATE COMP "DBG_EXP_36" SITE "M25" ;\r
+# LOCATE COMP "DBG_EXP_34" SITE "M26" ;\r
+# LOCATE COMP "DBG_EXP_32" SITE "L25" ;\r
+# LOCATE COMP "DBG_EXP_30" SITE "L26" ;\r
+# LOCATE COMP "DBG_EXP_28" SITE "K25" ;\r
+# LOCATE COMP "DBG_EXP_26" SITE "J26" ;\r
+# LOCATE COMP "DBG_EXP_24" SITE "H25" ;\r
+# LOCATE COMP "DBG_EXP_22" SITE "H26" ;\r
+# LOCATE COMP "DBG_EXP_20" SITE "H24" ;\r
+# LOCATE COMP "DBG_EXP_18" SITE "G26" ;\r
+# LOCATE COMP "DBG_EXP_16" SITE "G25" ;\r
+# LOCATE COMP "DBG_EXP_15" SITE "L27" ;\r
+# LOCATE COMP "DBG_EXP_14" SITE "L28" ;\r
+# LOCATE COMP "DBG_EXP_13" SITE "M28" ;\r
+# LOCATE COMP "DBG_EXP_12" SITE "K24" ;\r
+# LOCATE COMP "DBG_EXP_11" SITE "M27" ;\r
+# LOCATE COMP "DBG_EXP_10" SITE "M30" ;\r
+# LOCATE COMP "DBG_EXP_9" SITE "N26" ;\r
+# LOCATE COMP "DBG_EXP_8" SITE "M29" ;\r
+# LOCATE COMP "DBG_EXP_7" SITE "P27" ;\r
+# LOCATE COMP "DBG_EXP_6" SITE "L30" ;\r
+# LOCATE COMP "DBG_EXP_4" SITE "L29" ;\r
+# LOCATE COMP "DBG_EXP_2" SITE "K30" ;\r
+# LOCATE COMP "DBG_EXP_0" SITE "K29" ;\r
+LOCATE COMP "FPGA_LED_6" SITE "G28" ;\r
+IOBUF PORT "FPGA_LED_6" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_5" SITE "G27" ;\r
+IOBUF PORT "FPGA_LED_5" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_4" SITE "H28" ;\r
+IOBUF PORT "FPGA_LED_4" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_3" SITE "H27" ;\r
+IOBUF PORT "FPGA_LED_3" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_RXD" SITE "J28" ;\r
+IOBUF PORT "FPGA_LED_RXD" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_TXD" SITE "J27" ;\r
+IOBUF PORT "FPGA_LED_TXD" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_LINK" SITE "K26" ;\r
+IOBUF PORT "FPGA_LED_LINK" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "SD_LOS" SITE "F30" ;\r
+IOBUF PORT "SD_LOS" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "SD_PRESENT" SITE "G30" ; # alias MD[0]\r
+IOBUF PORT "SD_PRESENT" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "SD_TXDIS" SITE "J29" ;\r
+IOBUF PORT "SD_TXDIS" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+# LOCATE COMP "SD_TXFAULT" SITE "J30" ;\r
+# IOBUF PORT "SD_TXFAULT" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "SD_SDA" SITE "H30" ; # alias MD[2]\r
+# IOBUF PORT "SD_SDA" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "SD_SCL" SITE "H29" ; # alias MD[1]\r
+# IOBUF PORT "SD_SCL" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "SD_RATE" SITE "G29" ;\r
+# IOBUF PORT "SD_RATE" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "ADCM_ONEWIRE" SITE "F29" ;\r
+IOBUF PORT "ADCM_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_2_IN" SITE "D29" ;\r
+# LOCATE COMP "PIN_CHECK_2_OUT" SITE "D30" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 1 - 3.30V\r
+# APV1 OneWire\r
+######################################################################\r
+LOCATE COMP "APV1_1W_7" SITE "B15" ;\r
+IOBUF PORT "APV1_1W_7" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_6" SITE "A16" ;\r
+IOBUF PORT "APV1_1W_6" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_5" SITE "B16" ;\r
+IOBUF PORT "APV1_1W_5" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_4" SITE "A17" ;\r
+IOBUF PORT "APV1_1W_4" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_3" SITE "B17" ;\r
+IOBUF PORT "APV1_1W_3" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_2" SITE "C16" ;\r
+IOBUF PORT "APV1_1W_2" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_1" SITE "C17" ;\r
+IOBUF PORT "APV1_1W_1" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_0" SITE "D16" ;\r
+IOBUF PORT "APV1_1W_0" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+\r
+#### HERE WE ARE ######################\r
+\r
+\r
+######################################################################\r
+# I/O bank 0 - 3.30V\r
+# ADC1 control, LVDS driver control, backplane sense pins\r
+######################################################################\r
+LOCATE COMP "ENB_LVDS_7" SITE "F6" ;\r
+LOCATE COMP "ENB_LVDS_6" SITE "D5" ;\r
+LOCATE COMP "ENB_LVDS_5" SITE "D4" ;\r
+LOCATE COMP "ENB_LVDS_4" SITE "E5" ;\r
+LOCATE COMP "ENB_LVDS_3" SITE "D15" ;\r
+LOCATE COMP "ENB_LVDS_2" SITE "E13" ;\r
+LOCATE COMP "ENB_LVDS_1" SITE "D13" ;\r
+LOCATE COMP "ENB_LVDS_0" SITE "D12" ;\r
+# LOCATE COMP "FPGA_BP_13" SITE "C15" ;\r
+# IOBUF PORT "FPGA_BP_13" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_BP_12" SITE "C14" ;\r
+# IOBUF PORT "FPGA_BP_12" IO_TYPE=LVTTL33 ;\r
+# Backplane sense wires: backplane number\r
+LOCATE COMP "BP_MODULE_3" SITE "A14" ;\r
+IOBUF PORT "BP_MODULE_3" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_MODULE_2" SITE "F13" ;\r
+IOBUF PORT "BP_MODULE_2" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_MODULE_1" SITE "E12" ;\r
+IOBUF PORT "BP_MODULE_1" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_MODULE_0" SITE "G11" ;\r
+IOBUF PORT "BP_MODULE_0" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+\r
+# LOCATE COMP "FPGA_SPARE_12" SITE "D8" ;\r
+# IOBUF PORT "FPGA_SPARE_12" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_11" SITE "E8" ;\r
+# IOBUF PORT "FPGA_SPARE_11" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_10" SITE "D9" ;\r
+# IOBUF PORT "FPGA_SPARE_10" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_9" SITE "D11" ;\r
+# IOBUF PORT "FPGA_SPARE_9" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_8" SITE "F11" ;\r
+# IOBUF PORT "FPGA_SPARE_8" IO_TYPE=LVTTL33 ;\r
+\r
+LOCATE COMP "BP_ONEWIRE" SITE "F7" ;\r
+IOBUF PORT "BP_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ;\r
+\r
+\r
+######################################################################\r
+# simplify IO definitions\r
+######################################################################\r
+# Debug header (50pin SMC connector)\r
+# DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ;\r
+# IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=4 SLEWRATE=FAST ;\r
+\r
+# LED drivers\r
+# DEFINE PORT GROUP "led_output_group" "FPGA_LED*" ;\r
+# IOBUF GROUP "led_output_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# LVDS driver control\r
+DEFINE PORT GROUP "enable_lvds_group" "EN?_LVDS_{0:7}" ;\r
+IOBUF GROUP "enable_lvds_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW ;\r
+\r
+######################################################################\r
+# FPGA boot et. al.\r
+######################################################################\r
+SYSCONFIG PERSISTENT=OFF ;\r
+SYSCONFIG CONFIG_MODE=SPI ;\r
+SYSCONFIG DONE_OD=OFF ;\r
+SYSCONFIG DONE_EX=OFF ;\r
+SYSCONFIG MCCLK_FREQ=34 ;\r
+SYSCONFIG CONFIG_SECURE=OFF ;\r
+SYSCONFIG WAKE_UP=21 ;\r
+#SYSCONFIG WAKE_ON_LOCK=OFF ;\r
+SYSCONFIG COMPRESS_CONFIG=OFF ;\r
+SYSCONFIG INBUF=OFF ;\r
+SYSCONFIG ENABLE_NDR=OFF ;\r
+USERCODE HEX "DEADAFFE" ;\r
jspc29 / trbnet.git / commitdiff