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-\title{Noise performance of CMOS Monolithic Active Pixel Sensors manufactured in a 0.18$\upmu$m CMOS process\thanks{This work has been supported by BMBF (05P12RFFC7), HIC for FAIR and GSI.}}
+\title{Noise performance and radiation tolerance of CMOS Monolithic Active Pixel Sensors manufactured in a 0.18$\upmu$m CMOS process\thanks{This work has been supported by BMBF (05P12RFFC7), HIC for FAIR and GSI.}}
\author[1]{D. Doering}
%\author[2]{J. Baudot}
\author[1]{B. Linnik}
%\author[2]{S. Senyukov}
\author[1]{S. Strohauer}
-\author[1]{J. Stroth}
+\author[1,2]{J. Stroth}
%\author[2]{M. Winter}
%\affil{Institut f\"ur Kernphysik, Goethe University Frankfurt, Germany and IPHC Strasbourg, France}
%\affil{IPHC Strasbourg, 23 Rue du Loess, 67037 Strasbourg, France}
\affil[1]{Institut f\"ur Kernphysik, Goethe University Frankfurt, Germany}
%\affil[2]{IPHC Strasbourg, France}
-
+\affil[2]{GSI Darmstadt, Germany}
%\affil[mun]{Forschungsneutronenquelle Heinz-Maier-Leibnitz (FRM II), Technical University Munich, Lichtenbergstr. 1,
%85747 Garching, Germany}
\maketitle
So far, MAPS match the requirements of CBM in terms of spatial resolution, light material budget and tolerance to non-ionizing radiation. Migrating them from the previously used $0.35 \mum$ CMOS process to a novel $0.18\mum$ process was done to exploit the known higher tolerance of deep sub-micron processes to ionizing radiation. Moreover, the novel process allows for a first time to use also PMOS transistors in the pixel. This creates the potential to discriminate the signal inside the pixels instead of transporting it to the end of the columns, which would turn into a substantial acceleration of the read-out.
%During several years, their radiation tolerance has been adapted to the needs of this experiment. Since recently, a dedicated imaging process with $0.18~\rm \upmu m$ feature size became available for particle detectors. The radiation tolerance of this CMOS process was explored and it could be demonstrated that this process provides the radiation tolerance required for CBM at SIS-100. However, the exploratory study found that this new sensors have a quite substantial high noise. In 2013, the origin of this noise was studied to understand the effect and to provide strategies to suppress the noise and improve the performance.\newline
-Three prototypes named MIMOSA-32, MIMOSA-32ter and MIMOSA-34 were designed and tested in order to discover the novel technology. Various parameters of the pixels were varied in a systematic way in order to find an optimum. During our tests, we found that the average noise of the novel pixels exceed the noise of elder pixels manufactured in the $0.35 \mum$-process by about a factor of two. Moreover, we observed a correlation between the noise and the surface of the gate of the transistor serving as input stage of the on-pixel pre-amplifier. This is shown in Table \ref{tab:Mi32-1-f-noise-table}, which displays the noise as a function of the width of the gate of this transistor. The length of the gate of the pixels manufactured in $0.18\mum$-CMOS (pixel A-D) was $0.2\mum$. In the reference pixel (pixel R), which was manufactured in $0.35\mum$-CMOS, an enclosed transistor layout turning into an effective width of several$\mum$ was used and the gate length was $0.35\mum$.
-
-Initially, we expected the noise to shrink with a decreasing surface of this gate as the capacity of the input node is reduced and therefore the gain of the signal is increased. In contrast to this expectation, we observed the noise to increase with shrinking gate. Moreover, we observed a strong increase in the number of hot pixels. This is shown in the most right column (Noise 99\%) of Table \ref{tab:Mi32-1-f-noise-table}. Here, we assumed that 1\% of all pixels can be masked and that the common threshold of the pixels of the chip should be set to discriminate the noise of the most noisy active pixel. The noise of this pixel is shown.
+Three prototypes named MIMOSA-32, -32ter and -34 were designed to discover the novel technology.
+%Various parameters of the pixels were varied in a systematic way in order to find an optimum.
+While testing them,
+%we found that the average noise of the novel pixels exceed the noise of elder pixels manufactured in the $0.35 \mum$-process by about a factor of two. Moreover,
+we observed a correlation between the noise and the surface of the gate of the so-called SF-transistor, which serves as input stage of the on-pixel pre-amplifier. This is shown in Table \ref{tab:Mi32-1-f-noise-table}, which displays the noise as a function of the width of the gate of this transistor. The length of the gate of the pixels manufactured in $0.18\mum$-CMOS (pixel A-C) was $0.2\mum$. A reference pixel (pixel R), which was manufactured in $0.35\mum$-CMOS, an enclosed transistor layout turning into an effective width of several$\mum$ was used and the gate length was $0.35\mum$.
+Initially, we expected the noise to shrink with a decreasing surface of this gate as the capacity of the input node is reduced and therefore the gain of the signal is increased. In contrast to this expectation, we observed the noise to increase with shrinking gate. Moreover, we observed a strong increase in the number of hot pixels. This is shown in the most right column (Noise 99\%) of Table \ref{tab:Mi32-1-f-noise-table}. Here, we assumed that 1\% of all pixels can be masked and that the common threshold of the pixels of the chip should be set to discriminate the noise of the most noisy non-masked pixel. The noise of this pixel is shown.
+We find that decreasing the width of the SF-transistor from $1.5\mum$ to $0.5\mum$ (pixel A-C) improves the gain of the pixel by $10\%$ but increases the noise slightly by $8\%$ (median noise) and by 54\% (``99\%-noise''). Moreover, the novel pixels exhibit twice the median noise and up to three times the ``99\%-noise'' of the reference pixel R.
-tested in laboratory. Each flavor is composed of arrays of 32 different pixels with various parameters, which were put to study selected pixel parameters in a systematic way.\newline
-The aim of the presented study is to optimize the transistor dimensions to improve the noise performance. Therefore the matrices MIMOSA-32ter-P2, MIMOSA-32ter-P6, MIMOSA-32ter-P5 and MIMOSA-34-P17 were chosen. In the following, the matrices are named Pixel A-D accordingly (table \ref{tab:Mi32-1-f-noise-table}). As a reference, the matrix MIMOSA-18AHR-A2, produced in an \mbox{0.35 $\upmu \rm m$} CMOS process is supplemented (Pixel R).\newline
-The pixels A-D in the $0.18 \mum$-process have a higher noise in comparison to the reference pixel R in the $0.35 \mum$-process. In particular the 99\%-noise, which represents the noise value that $>99\%$ of the pixel have a lower noise, is doubled. \newline
+%tested in laboratory. Each flavor is composed of arrays of 32 different pixels with various parameters, which were put to study selected pixel parameters in a systematic way.\newline
+%The aim of the presented study is to optimize the transistor dimensions to improve the noise performance. Therefore the matrices MIMOSA-32ter-P2, MIMOSA-32ter-P6, MIMOSA-32ter-P5 and MIMOSA-34-P17 were chosen. In the following, the matrices are named Pixel A-D accordingly (table \ref{tab:Mi32-1-f-noise-table}). As a reference, the matrix MIMOSA-18AHR-A2, produced in an \mbox{0.35 $\upmu \rm m$} CMOS process is supplemented (Pixel R).\newline
+%The pixels A-D in the $0.18 \mum$-process have a higher noise in comparison to the reference pixel R in the $0.35 \mum$-process. In particular the 99\%-noise, which represents the noise value that $>99\%$ of the pixel have a lower noise, is doubled. \newline
\begin{table}[t]
A & 1.5 & 11.1 & 19.8 & 41\\
B & 0.9 & 10.5 & 20.5 & 55\\
C & 0.5 & 10.1 & 21.3 & 63\\
-\hline
- D & 1.5 & 5.8 & 16.2 & 38\\
+%\hline
+% D & 1.5 & 5.8 & 16.2 & 38\\
\hline
R & - & 6.0 & 10.7 & 18\\
\hline
\end{tabular}
-\caption{Noise and gain in dependence of the source follower gate width.}
+\caption{Noise and gain in dependence of the source follower gate width. See text.}
\label{tab:Mi32-1-f-noise-table}
\end{table}
-According to table \ref{tab:Mi32-1-f-noise-table} A-C, decreasing the width of the source follower transistor from $1.5\mum$ to $0.5\mum$, the gain improves by $10\%$ and the noise increases slightly by $8\%$. The noise increase is in particular large for the 99\% noise, which is increased by 54\%. Therefore a smaller transistor surface is not beneficial for the noise performance. The origin of this effect was identified as an 1/f-noise or Random Telegraph Signal (RTS) as it was already described in \cite{RTS0.18,RTS0.182}. This holds also for the gate of the reset transistor, which could be enlarged in \mbox{Pixel D}. After this modification, the median noise was reduced from \mbox{$19.8~\rm e$} \mbox{(Pixel A)} to \mbox{$16.2~\rm e$} \mbox{(Pixel D)}. Note that, while enlarging the transistor size reduces the RTS, cooling seems not to show a positive impact. This is in contrast to our observations on RTS-noise originating from the pixel \mbox{diodes \cite{PaperRTS}}.\newline
-We conclude that the lower feature size of the $0.18 \mum$-process under study cannot be fully exploited to reduce the capacitive noise of the pixels. This is as the smaller transistors show an RTS-1/f noise, which dominates the capacitive noise. Knowing this effect, it should be possible to reduce the noise of the above presented sensors by means of optimizing the layout of the few relevant transistors.\newline
-This work is part of a proceeding paper to the IWORID conference 2013 in Paris, which was sent to editorial office in December 2013.\newline
+% , which is increased by 54\%. Therefore a smaller transistor surface is not beneficial for the noise performance. The origin of this effect was identified as an 1/f-noise or Random Telegraph Signal (RTS) as it was already described in \cite{RTS0.18,RTS0.182}. This holds also for the gate of the reset transistor, which could be enlarged in \mbox{Pixel D}. After this modification, the median noise was reduced from \mbox{$19.8~\rm e$} \mbox{(Pixel A)} to \mbox{$16.2~\rm e$} \mbox{(Pixel D)}. Note that, while enlarging the transistor size reduces the RTS, cooling seems not to show a positive impact. This is in contrast to our observations on RTS-noise originating from the pixel \mbox{diodes \cite{PaperRTS}}.\newline
+
+Analyzing the effect, we found the signatures of Random Telegraph Noise and 1/f-noise, which affects the SF-transistor and which is amplified within the amplification chain. This effect was observed earlier on MAPS for optical imaging \cite{RTS0.18,RTS0.182}, but it was so far unknown in the community doing MAPS for charged particle detection. As suggested by our observations and literature, we increased the gate size in a follow-up prototype and first measurements suggest that this mostly eliminated the additional noise\cite{MarcVertex}.
+
+We studied the tolerance of the above mentioned sensors to ionizing radiation by irradiating them with soft X-rays and testing them hereafter with X-rays from a $^{55}$Fe-source and a $\upbeta$-rays from a $^{90}$Sr-source. The preliminary results of this study suggest that the novel sensors tolerate ionizing doses of up to $3 \Mrad$ without significant losses in performance. On a sensor irradiated with $10 \Mrad$, the gain of the detector was reduced for so-far unknown reasons. However, the S/N of the device remained sufficient for a reliable charged particle detection.
+
+From this, we conclude the MAPS based on a $0.18 \mum$ CMOS process have the potential to match the requirements of CBM in terms of tolerance to ionizing radiation.
+
+%We conclude that the lower feature size of the $0.18 \mum$-process under study cannot be fully exploited to reduce the capacitive noise of the pixels. This is as the smaller transistors show an RTS-1/f noise, which dominates the capacitive noise. Knowing this effect, it should be possible to reduce the noise of the above presented sensors by means of optimizing the layout of the few relevant transistors.\newline
+%This work is part of a proceeding paper to the IWORID conference 2013 in Paris, which was sent to editorial office in December 2013.\newline
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