signal_in : in std_logic;
pulse : out std_logic);
end component;
+ component DCS
+-- synthesis translate_off
+ generic (
+ DCSMODE : string := "LOW_LOW");
+-- synthesis translate_on
+ port (
+ CLK0 : in std_logic;
+ CLK1 : in std_logic;
+ SEL : in std_logic;
+ DCSOUT : out std_logic);
+ end component;
-----------------------------------------------------------------------------
-- FLEXI_PCS
-----------------------------------------------------------------------------
signal word_counter_for_api_00 : std_logic_vector(1 downto 0);
signal word_counter_for_api_01 : std_logic_vector(1 downto 0);
signal global_reset_i : std_logic;
- signal global_reset_cnt : std_logic_vector(3 downto 0);
+ signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0";
signal registered_signals : std_logic_vector(7 downto 0);
signal hub_register_0a_i_synch : std_logic_vector(7 downto 0);
signal hub_register_0e_and_0d_synch : std_logic_vector(15 downto 0);
signal test_signal : std_logic_vector(1 downto 0);
signal pulse_test : std_logic;
+ signal saved_ready : std_logic_vector(HOW_MANY_CHANNELS-2 downto 0);
+ signal all_ready : std_logic;
+ signal flexi_pcs_ref_clk : std_logic;
+ signal lok_i : std_logic_vector(16 downto 1);
+ signal not_used_lok : std_logic_vector(15 downto 0);
+ signal used_channels_locked : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ signal channels_locked : std_logic_vector(16 downto 1);
+ signal switch_rx_clk : std_logic;
+ signal lock_pattern : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
begin
GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt)
begin
pulse => pulse_test);
test_signal(1) <= pulse_test;
test_signal(0) <= pulse_test;
+ REF_CLK_SELECT: DCS
+ -- synthesis translate_off
+ generic map (
+ DCSMODE => DCSMODE)
+ -- synthesis translate_on
+ port map (
+ CLK0 => LVDS_CLK_200P,
+ CLK1 => '0',
+ SEL => switch_rx_clk,--hub_register_0a_i(0),--'0',--switch_rx_clk,
+ DCSOUT => flexi_pcs_ref_clk);
+ SWITCH_CLOCK: process (LVDS_CLK_200P, global_reset_i)
+ begin -- process SWITCH_CLOCK
+ if rising_edge(LVDS_CLK_200P) then
+ if global_reset_i = '1' or lock_pattern /= used_channels_locked then -- asynchronous reset (active low)
+ switch_rx_clk <= '0';
+ lock_pattern <= (others => '1');
+ elsif lock_pattern = used_channels_locked then
+ switch_rx_clk <= '1';
+ lock_pattern <= (others => '1');
+ end if;
+ end if;
+ end process SWITCH_CLOCK;
+ LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
+ begin
+ used_channels_locked(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
+ end generate LOK_STATUS_DIOD_EN;
+
+ --lock_pattern(15 downto HOW_MANY_CHANNELS) <= lok_i(16 downto HOW_MANY_CHANNELS +1);
QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate
begin
QUAD : serdes_fpga_ref_clk
port map (
-- refclkp => SERDES_200P,
-- refclkn => SERDES_200N,
- rxrefclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P,
+ rxrefclk => flexi_pcs_ref_clk,--LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P,
refclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P,
hdinp_0 => SFP_INP_P(bit_index*4+0),
hdinn_0 => SFP_INP_N(bit_index*4+0),
MED_STAT_OP => med_stat_op_i,
MED_CTRL_OP => med_ctrl_op_i
);
+ ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0);
+ ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0);
-- med_data_in_i(15 downto 0) <= hub_register_0e_and_0d;
-- med_read_in_i <= (others => '1'); --test
end if;
end process;
process (rx_clk_i(0), global_reset_i, rx_k_i(0))
+
begin
if rising_edge(rx_clk_i(0)) then
if global_reset_i = '1' then -- asynchronous reset (active low)
end if;
end process;
registered_signals(4 downto 3) <= rx_k_i(1) & rx_k_i(0);
- TRB_HUB_INT : trb_hub_interface
- port map (
- CLK => ref_pclk(0),
- RESET => global_reset_i,
- STROBE => ADO_TTL(9),
- internal_data_in => ADO_TTL(18 downto 11),
- internal_data_out => ADO_TTL(42 downto 35),
- internal_address => ADO_TTL(34 downto 19),
- internal_mode => ADO_TTL(10),
- VALID_DATA_SENT => ADO_TTL(8),
- HUB_REGISTER_00 => hub_register_00_i,
- HUB_REGISTER_01 => hub_register_01_i,
- HUB_REGISTER_02 => hub_register_02_i,
- HUB_REGISTER_03 => hub_register_03_i,
- HUB_REGISTER_04 => hub_register_04_i,
- HUB_REGISTER_05 => hub_register_05_i,
- HUB_REGISTER_06 => hub_register_06_i,
- HUB_REGISTER_07 => hub_register_07_i,
- HUB_REGISTER_08 => hub_register_08_i,
- HUB_REGISTER_09 => hub_register_09_i,
- HUB_REGISTER_0a => hub_register_0a_i,
- HUB_REGISTER_0b => hub_register_0b_i,
- HUB_REGISTER_0c => hub_register_0c_i,
- HUB_REGISTER_0d => hub_register_0d_i,
- HUB_REGISTER_0e => hub_register_0e_i,
- HUB_REGISTER_0f => hub_register_0f_i,
- HUB_REGISTER_10 => hub_register_10_i,
- HUB_REGISTER_11 => hub_register_11_i,
- HUB_REGISTER_12 => hub_register_12_i,
- HUB_REGISTER_13 => hub_register_13_i,
- HUB_REGISTER_14 => hub_register_14_i,
- HUB_REGISTER_15 => hub_register_15_i,
- HUB_REGISTER_16 => hub_register_16_i
- );
+-- TRB_HUB_INT : trb_hub_interface
+-- port map (
+-- CLK => ref_pclk(0),
+-- RESET => global_reset_i,
+-- STROBE => ADO_TTL(9),
+-- internal_data_in => ADO_TTL(18 downto 11),
+-- internal_data_out => ADO_TTL(42 downto 35),
+-- internal_address => ADO_TTL(34 downto 19),
+-- internal_mode => ADO_TTL(10),
+-- VALID_DATA_SENT => ADO_TTL(8),
+-- HUB_REGISTER_00 => hub_register_00_i,
+-- HUB_REGISTER_01 => hub_register_01_i,
+-- HUB_REGISTER_02 => hub_register_02_i,
+-- HUB_REGISTER_03 => hub_register_03_i,
+-- HUB_REGISTER_04 => hub_register_04_i,
+-- HUB_REGISTER_05 => hub_register_05_i,
+-- HUB_REGISTER_06 => hub_register_06_i,
+-- HUB_REGISTER_07 => hub_register_07_i,
+-- HUB_REGISTER_08 => hub_register_08_i,
+-- HUB_REGISTER_09 => hub_register_09_i,
+-- HUB_REGISTER_0a => hub_register_0a_i,
+-- HUB_REGISTER_0b => hub_register_0b_i,
+-- HUB_REGISTER_0c => hub_register_0c_i,
+-- HUB_REGISTER_0d => hub_register_0d_i,
+-- HUB_REGISTER_0e => hub_register_0e_i,
+-- HUB_REGISTER_0f => hub_register_0f_i,
+-- HUB_REGISTER_10 => hub_register_10_i,
+-- HUB_REGISTER_11 => hub_register_11_i,
+-- HUB_REGISTER_12 => hub_register_12_i,
+-- HUB_REGISTER_13 => hub_register_13_i,
+-- HUB_REGISTER_14 => hub_register_14_i,
+-- HUB_REGISTER_15 => hub_register_15_i,
+-- HUB_REGISTER_16 => hub_register_16_i
+-- );
+-- ADO_TTL(34 downto 9) <= (others => 'Z');
+
SYNCH_DATA: process (ref_pclk(0), global_reset_i)
begin -- process SYNCH_DATA
if falling_edge(ref_pclk(0)) then
end if;
end if;
end process SYNCH_DATA;
- ADO_TTL(34 downto 9) <= (others => 'Z');
+
hub_register_00_i <= flexi_pcs_synch_status_i(7 downto 0);
hub_register_01_i <= hub_stat_gen_i(15 downto 8);
hub_register_02_i <= rxd_i(7 downto 0); --; --rxd_1_a(15 downto 8);
---------------------------------------------------------------------------
LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
begin
- LOK(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16);
+ lok_i(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16);
end generate LOK_STATUS_DIOD_EN;
LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
begin
WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
- LOK(16-not_connected) <= '1';
+ lok_i(16-not_connected) <= '1';
end generate WHEN_NOT_ALL_EN;
end generate LOK_STATUS_DIOD_DIS;
-
+ LOK <= lok_i;
IPLL <= '0';
OPLL <= '0';
DBAD <= ADO_TTL(11);
end if;
end process CV_COUNTERaab;
RT(16 downto 8) <= cv_counter(31 downto 23);
- RT(2) <= cv_counter(0);
+ RT(2) <= flexi_pcs_ref_clk;--cv_counter(0);
- RT(1) <= ref_pclk(0);
+ RT(1) <= not switch_rx_clk;--ref_pclk(0);
RT(3) <= LVDS_CLK_200P;
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