add missing files from last commit

diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj
index a8a7b83abdd3828e0e25a6bac166f0088417dd71..7b434cd196c17f1e14eff239f8fc1d8164f4f1b6 100644 (file)
--- a/combiner_cts/combiner.prj
+++ b/combiner_cts/combiner.prj
@@ -225,9 +225,11 @@ add_file -vhdl -lib work "../../cri/src/trb_net16_cri_interface.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
 add_file -vhdl -lib work "../../cri/src/cri_data_sender.vhd"
-add_file -vhdl -lib work "../../cri/src/mbs_generator_cbmrich.vhd"
 add_file -vhdl -lib work "../../cri/src/cri_cbm_rich_calib.vhd"
 
+add_file -vhdl -lib work "../../cri/src/DLM_CTS_generator.vhd"
+
+add_file -vhdl -lib work "../../cri/src/mbs_generator_cbmrich.vhd"
 add_file -vhdl -lib work "../../trb3/cts/source/mbs_master.vhd"
 add_file -vhdl -lib work "../../trb3sc/hub_cts/code/mbs_vulom_recv.vhd"
 

diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd
index e83fb5860014ea76b2acefba052a24122cfb5807..28d96fc517d42aa9257bf499d5edc64cfe6af7d7 100644 (file)
--- a/combiner_cts/combiner.vhd
+++ b/combiner_cts/combiner.vhd
@@ -883,74 +883,113 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
 -- MBS
 ---------------------------------------------------------------------------  
    
-   THE_MBS_GENERATOR : entity work.mbs_generator_cbmrich
-   port map (
-      CLK_SYS               => clk_sys,                       
-      CLK_RX                => med2int(INTERFACE_NUM).clk_full,
-      RESET_IN              => reset_i,
-
-      DLM_RX_IN             => dlm_rx_i,
-      DLM_RX_DATA           => dlm_rx_word,
-      
-      MBS_LOC_TRIG          => mbs_local_trigger_in,
-      MBS_LOC_TRIG_NUM      => mbs_local_trigger_num_in,
-      
-      BUS_RX                => bus_mbs_gen_rx,
-      BUS_TX                => bus_mbs_gen_tx
-     );
-  
-  
-   THE_MBS_MASTER : entity work.mbs_master
-      port map (
-        CLK                 => med2int(INTERFACE_NUM).clk_half,
-        RESET_IN            => reset_i,
- 
-        MBS_CLOCK_OUT       => open,
-        MBS_DATA_OUT        => mbs_trigger,
- 
-        --data output for read-out
-        TRIGGER_IN          => mbs_local_trigger_in,
-        TRIGGER_NUMBER_IN   => mbs_local_trigger_num_in,
-        DATA_OUT            => open,
-        WRITE_OUT           => open,
-        FINISHED_OUT        => open,
-        STATUSBIT_OUT       => open
-        );  
-  
-  
-   THE_MBS_REC : entity work.mbs_recv
-      generic map(
-        USE_40MHz => c_NO
-      )
-      port map (
-        CLK      => clk_sys,
-        RESET_IN => reset_i,
-
-        MBS_IN  => mbs_trigger,
-        CLK_200 => clk_full_osc,
-
-        TRG_ASYNC_OUT => async_ext_trig,--tdc_inputs(1),
-        TRG_SYNC_OUT  => cts_ext_trigger,
-
-        TRIGGER_IN    => cts_rdo_rx.data_valid,
-        TRG_NUMBER_IN => cts_trg_number,
-        TRG_CODE_IN   => cts_trg_code,
-        TIMING_TRG_IN => cts_trigger_out,
-        
-        DATA_OUT      => cts_rdo_additional(0).data,
-        WRITE_OUT     => cts_rdo_additional(0).data_write,
-        FINISHED_OUT  => cts_rdo_additional(0).data_finished,
-        STATUSBIT_OUT => cts_rdo_additional(0).statusbits,
-
-        REGIO_IN      => bus_mbs_rx,
-        REGIO_OUT     => bus_mbs_tx,
-        
-        CONTROL_REG_IN => cts_ext_control,
-        STATUS_REG_OUT => cts_ext_status,
-        HEADER_REG_OUT => cts_ext_header,
-
-        DEBUG => cts_ext_debug
-        );
+--    THE_MBS_GENERATOR : entity work.mbs_generator_cbmrich
+--    port map (
+--       CLK_SYS               => clk_sys,                       
+--       CLK_RX                => med2int(INTERFACE_NUM).clk_full,
+--       RESET_IN              => reset_i,
+-- 
+--       DLM_RX_IN             => dlm_rx_i,
+--       DLM_RX_DATA           => dlm_rx_word,
+--       
+--       MBS_LOC_TRIG          => mbs_local_trigger_in,
+--       MBS_LOC_TRIG_NUM      => mbs_local_trigger_num_in,
+--       
+--       BUS_RX                => bus_mbs_gen_rx,
+--       BUS_TX                => bus_mbs_gen_tx
+--      );
+--   
+--   
+--    THE_MBS_MASTER : entity work.mbs_master
+--       port map (
+--         CLK                 => med2int(INTERFACE_NUM).clk_half,
+--         RESET_IN            => reset_i,
+--  
+--         MBS_CLOCK_OUT       => open,
+--         MBS_DATA_OUT        => mbs_trigger,
+--  
+--         --data output for read-out
+--         TRIGGER_IN          => mbs_local_trigger_in,
+--         TRIGGER_NUMBER_IN   => mbs_local_trigger_num_in,
+--         DATA_OUT            => open,
+--         WRITE_OUT           => open,
+--         FINISHED_OUT        => open,
+--         STATUSBIT_OUT       => open
+--         );  
+--   
+--   
+--    THE_MBS_REC : entity work.mbs_recv
+--       generic map(
+--         USE_40MHz => c_NO
+--       )
+--       port map (
+--         CLK      => clk_sys,
+--         RESET_IN => reset_i,
+-- 
+--         MBS_IN  => mbs_trigger,
+--         CLK_200 => clk_full_osc,
+-- 
+--         TRG_ASYNC_OUT => async_ext_trig,--tdc_inputs(1),
+--         TRG_SYNC_OUT  => cts_ext_trigger,
+-- 
+--         TRIGGER_IN    => cts_rdo_rx.data_valid,
+--         TRG_NUMBER_IN => cts_trg_number,
+--         TRG_CODE_IN   => cts_trg_code,
+--         TIMING_TRG_IN => cts_trigger_out,
+--         
+--         DATA_OUT      => cts_rdo_additional(0).data,
+--         WRITE_OUT     => cts_rdo_additional(0).data_write,
+--         FINISHED_OUT  => cts_rdo_additional(0).data_finished,
+--         STATUSBIT_OUT => cts_rdo_additional(0).statusbits,
+-- 
+--         REGIO_IN      => bus_mbs_rx,
+--         REGIO_OUT     => bus_mbs_tx,
+--         
+--         CONTROL_REG_IN => cts_ext_control,
+--         STATUS_REG_OUT => cts_ext_status,
+--         HEADER_REG_OUT => cts_ext_header,
+-- 
+--         DEBUG => cts_ext_debug
+--         );
+
+      THE_DLM_CTS_GNRTR : entity work.DLM_CTS_generator
+        generic map(
+          INCL_REGIO      => c_YES
+        )
+        port map (
+           CLK            => clk_sys,
+           RESET_IN       => reset_i,
+           
+           -- recovered clock, synchronous to DLM @240MHz
+           CLK_RCV        => med2int(INTERFACE_NUM).clk_full,
+           
+           --DLM inputs
+           DLM_IN         => dlm_rx_i,
+           DLM_MSG_IN     => dlm_rx_word,
+           
+           --trigger outputs
+           TRG_ASYNC_OUT  => async_ext_trig,
+           TRG_SYNC_OUT   => cts_ext_trigger,
+           
+           --data output for read-out
+           TRIGGER_IN     => cts_rdo_rx.data_valid,
+           
+           -- Data connection to Streamer
+           DATA_OUT       => cts_rdo_additional(0).data,
+           WRITE_OUT      => cts_rdo_additional(0).data_write,
+           STATUSBIT_OUT  => cts_rdo_additional(0).statusbits,
+           FINISHED_OUT   => cts_rdo_additional(0).data_finished,
+           
+           --Registers / Debug    
+           REGIO_IN       => bus_mbs_rx,
+           REGIO_OUT      => bus_mbs_tx,
+
+           -- Ctrl and Status registers are only in use, if INCL_REGIO = c_NO ("ETM" mode)
+           CONTROL_REG_IN => cts_ext_control,
+           STATUS_REG_OUT => cts_ext_status,
+           HEADER_REG_OUT => cts_ext_header,
+           DEBUG          => cts_ext_debug   
+           );
         
         
 ---------------------------------------------------------------------------
@@ -958,11 +997,11 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
 ---------------------------------------------------------------------------
   THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
     generic map(
-      PORT_NUMBER      => 14,
+      PORT_NUMBER      => 13,--14,
       PORT_ADDRESSES   => ( 0 => x"d000", 1 => x"d300", 2 => x"b000",  3 => x"b200",  4 => x"b400",  5 => x"b600", 6 => x"c000",
-                            7 => x"e000", 8 => x"ef00", 9 => x"a000", 10 => x"8300", 11 => x"e500", 12 => x"e400", 13 => x"e410", others => x"0000"),
+                            7 => x"e000", 8 => x"ef00", 9 => x"a000", 10 => x"8300", 11 => x"e500", 12 => x"e410", 13 => x"e400", others => x"0000"),
       PORT_ADDR_MASK   => ( 0 => 12,      1 => 1,       2 => 9,        3 => 9,        4 => 9,        5 => 9,       6  => 12,
-                            7 =>  9,      8 => 8,       9 => 11,      10 => 8,       11 => 8,       12 => 4,       13 =>  2, others => 0),
+                            7 =>  9,      8 => 8,       9 => 11,      10 => 8,       11 => 8,       12 => 2,       13 =>  4, others => 0),
       PORT_MASK_ENABLE => 1
       )
     port map(
@@ -984,8 +1023,8 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
       BUS_RX(9) => buscts_rx,
       BUS_RX(10)=> buscrireg_rx,
       BUS_RX(11)=> busCriDatadbgReg_rx,
-      BUS_RX(12)=> bus_mbs_gen_rx,
-      BUS_RX(13)=> bus_mbs_rx,
+      BUS_RX(12)=> bus_mbs_rx,
+      --BUS_RX(13)=> bus_mbs_gen_rx,
       BUS_TX(0) => bustools_tx,
       BUS_TX(1) => bustc_tx,
       BUS_TX(2) => bussci_tx(0),
@@ -998,8 +1037,8 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
       BUS_TX(9) => buscts_tx,
       BUS_TX(10)=> buscrireg_tx,
       BUS_TX(11)=> busCriDatadbgReg_tx,
-      BUS_TX(12)=> bus_mbs_gen_tx,
-      BUS_TX(13)=> bus_mbs_tx,
+      BUS_TX(12)=> bus_mbs_tx,
+      --BUS_TX(13)=> bus_mbs_gen_tx,
       STAT_DEBUG => open
       );