MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0),
MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0),
- MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i(31 downto 0),
- MEDIA_STATUS_REG_IN(127 downto 96) => (others => '0'),
+ MEDIA_STATUS_REG_IN(191 downto 64) => stat_fsm_reset_i(127 downto 0),
+ MEDIA_STATUS_REG_IN(255 downto 192) => (others => '0'),
DEBUG_OUT => open
);
BUS_RX : in CTRLBUS_RX;
BUS_TX : out CTRLBUS_TX;
- MEDIA_STATUS_REG_IN : in std_logic_vector(127 downto 0);
+ MEDIA_STATUS_REG_IN : in std_logic_vector(255 downto 0) := (others => '0');
DEBUG_OUT : out std_logic_vector(31 downto 0)
);
end entity;
end process;
-end architecture;
\ No newline at end of file
+end architecture;
STAT_DEBUG => buf_stat_debug(i*32+31 downto i*32)
);
- sd_txdis_out(i) <= quad_rst(i) or reset_i;
+ sd_txdis_out(i) <= '0'; --quad_rst(i) or reset_i;
ffc_quad_rst <= quad_rst(0);
ffc_lane_tx_rst(i) <= lane_rst(i);
stat_debug(i*64+63 downto i*64+60) <= buf_stat_debug(i*16+3 downto i*16+0);
end generate;
-end architecture;
\ No newline at end of file
+end architecture;