med_sync_control: Fix signal_sync source clocks

The signal_sync instances for the finished_reset_* signals from
tx_reset_fsm and rx_reset_fsm had the source clock set to CLK_SYS, but
both source signals are synchronous to CLK_REF.

diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd
index a692953c6cf471c6599a31eacfd4aa7437e66da2..aded4e7d554bac1edc4dd39de2ba3350ffad430e 100644 (file)
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@ -230,10 +230,10 @@ PROC_ALLOW : process begin
   end if;
 end process;
 
-LINK_RESET_FIN_TX  : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS,
+LINK_RESET_FIN_TX  : signal_sync port map(RESET => '0',CLK0 => CLK_REF, CLK1 => CLK_SYS,
                                           D_IN(0)  => finished_reset_tx, 
                                           D_OUT(0) => finished_reset_tx_q);
-LINK_RESET_FIN_RX  : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS,
+LINK_RESET_FIN_RX  : signal_sync port map(RESET => '0',CLK0 => CLK_REF, CLK1 => CLK_SYS,
                                           D_IN(0)  => finished_reset_rx, 
                                           D_OUT(0) => finished_reset_rx_q);