*** empty log message ***

diff --git a/lattice/scm/trb_net16_fifo_arch.vhd b/lattice/scm/trb_net16_fifo_arch.vhd
index 24b1555e60e93c8ee0d3d3e4a2cea9c335f79952..319e3fa16452b13ab2926fee22feb521fb694c90 100644 (file)
--- a/lattice/scm/trb_net16_fifo_arch.vhd
+++ b/lattice/scm/trb_net16_fifo_arch.vhd
@@ -97,7 +97,7 @@ begin
   DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8));
 
   gen_FIFO6 : if DEPTH = 6  generate
-    fifo:xilinx_fifo_18x1k
+    fifo:lattice_scm_fifo_18x1k
       port map (
         Data     => din,
         WrClock  => CLK,
@@ -115,7 +115,7 @@ begin
   end generate;
 
     gen_FIFO1 : if DEPTH = 1  generate
-      fifo:xilinx_fifo_18x16
+      fifo:lattice_scm_fifo_18x16
         port map (
           Data     => din,
           WrClock  => CLK,

diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd
index 026ff6c9bdbeb03cd9426b7a07bbff8c0ffa9f3b..04c5cd2075157c84aff9c93a886f2fa58d859f78 100644 (file)
--- a/trb_net16_med_tlk.vhd
+++ b/trb_net16_med_tlk.vhd
@@ -177,8 +177,12 @@ begin
   STAT(36 downto 34) <= state_bits;
   STAT(40 downto 37) <= fifo_status_a;
   STAT(44 downto 41) <= fifo_status_m;
-  STAT(63 downto 45) <= counter(22 downto 4);
-
+  STAT(48 downto 45) <= fifo_dout_m(3 downto 0);
+  STAT(50 downto 49) <= fifo_dout_m(17 downto 16);
+  STAT(54 downto 51) <= fifo_dout_a(3 downto 0);
+  STAT(56 downto 55) <= fifo_dout_a(17 downto 16);
+  STAT(63 downto 57) <= (others => '0');
+  
   process(CLK)
     begin
       if rising_edge(CLK) then