added few more control registers for ADC

diff --git a/ADC/sim/adcprocessor.mpf b/ADC/sim/adcprocessor.mpf
index f527f1d0a4a9f57e189ce26267ca3474da99154d..c403e03c431534877a049919ee4d9f3c8fdf790e 100644 (file)
--- a/ADC/sim/adcprocessor.mpf
+++ b/ADC/sim/adcprocessor.mpf
@@ -1744,7 +1744,7 @@ Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v
 Project_File_1 = /d/jspc22/trb/git/trb3/ADC/sim/dummyADC.vhd
 Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1412951167 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_File_2 = /d/jspc22/trb/git/trb3/ADC/sim/tb_adcprocessor.vhd
-Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417457796 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417457796 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_3 = /d/jspc22/trb/git/trbnet/trb_net_std.vhd
 Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409927354 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_File_4 = /d/jspc22/trb/git/trb3/ADC/sim/txt_util.vhd
@@ -1758,7 +1758,7 @@ Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v
 Project_File_8 = /d/jspc22/trb/git/trb3/ADC/source/adc_processor.vhd
 Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417182250 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_9 = /d/jspc22/trb/git/trb3/base/trb3_components.vhd
-Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1413807482 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1413807482 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0

diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd
index da55f71372a1f980b02dde5372fd42bc5ff12301..de87cc1fb890365f8e9d6ae570e18c248037211e 100644 (file)
--- a/ADC/source/adc_handler.vhd
+++ b/ADC/source/adc_handler.vhd
@@ -245,6 +245,9 @@ PROC_BUS : process begin
         when x"18" =>  BUS_TX.data(15 downto 0) <=  config.trigger_enable(47 downto 32);
         when x"19" =>  BUS_TX.data(RESOLUTION-1 downto 0)     <= config.check_word1;
                        BUS_TX.data(RESOLUTION-1+16 downto 16) <= config.check_word2;
+                       BUS_TX.data(31)                        <= config.check_word_enable;
+        when x"1a" =>  BUS_TX.data(31 downto 0) <=  config.channel_disable(31 downto  0);
+        when x"1b" =>  BUS_TX.data(15 downto 0) <=  config.channel_disable(47 downto 32);
         when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
       end case;
     elsif BUS_RX.addr >= x"0020" and BUS_RX.addr <= x"002f" then      
@@ -292,6 +295,9 @@ PROC_BUS : process begin
         when x"18" =>   config.trigger_enable(47 downto 32) <= BUS_RX.data(15 downto 0);
         when x"19" =>   config.check_word1        <= BUS_RX.data(RESOLUTION-1 downto 0);
                         config.check_word2        <= BUS_RX.data(RESOLUTION-1+16 downto 16);
+                        config.check_word_enable  <= BUS_RX.data(31);
+        when x"1a" =>  config.channel_disable(31 downto  0) <=  BUS_RX.data(31 downto 0);
+        when x"1b" =>  config.channel_disable(47 downto 32) <=  BUS_RX.data(15 downto 0);
         when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';        
       end case;
     elsif BUS_RX.addr >= x"0020" and BUS_RX.addr <= x"002f" then      

diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd
index bede861c693c7dce2914b5c4bf6c0506dc461f95..a48a74af1bc7c17f332b026b566bdc0b736c4e5d 100644 (file)
--- a/ADC/source/adc_package.vhd
+++ b/ADC/source/adc_package.vhd
@@ -33,6 +33,7 @@ type cfg_t is record
   presum            : unsigned( 7 downto 0);
   averaging         : unsigned( 3 downto 0);
   trigger_enable    : std_logic_vector(47 downto 0);
+  channel_disable   : std_logic_vector(47 downto 0);
   baseline_always_on: std_logic;
   baseline_reset_value : unsigned(31 downto 0);
   block_avg         : unsigned_array_8(0 to 3);
@@ -40,6 +41,7 @@ type cfg_t is record
   block_scale       : unsigned_array_8(0 to 3);
   check_word1       : std_logic_vector(RESOLUTION-1 downto 0);
   check_word2       : std_logic_vector(RESOLUTION-1 downto 0);
+  check_word_enable : std_logic;
 end record;
 
 end package;

diff --git a/ADC/source/adc_processor.vhd b/ADC/source/adc_processor.vhd
index 89dca9568664f7688d0698f33e963e595d20d429..f5eea7de588ca99de49fac0c9df74e9bc6cfbf7d 100644 (file)
--- a/ADC/source/adc_processor.vhd
+++ b/ADC/source/adc_processor.vhd
@@ -191,7 +191,8 @@ gen_word_checker : for i in 0 to CHANNELS-1 generate
     wait until rising_edge(CLK);
     if ADC_VALID = '1' then
       if ADC_DATA(RESOLUTION*(i+1)-1 downto RESOLUTION*i) /= CONF.check_word1 and
-         ADC_DATA(RESOLUTION*(i+1)-1 downto RESOLUTION*i) /= CONF.check_word2 then
+         ADC_DATA(RESOLUTION*(i+1)-1 downto RESOLUTION*i) /= CONF.check_word2 and 
+         CONF.check_word_enable = '1' then
         invalid_word_count(i) <= invalid_word_count(i) + 1; 
       end if;
     end if;
@@ -539,7 +540,7 @@ begin
     
     when READ_CHANNEL =>
       ram_read(channelselect) <= '1';
-      if readcount = 1 then
+      if readcount = 1 or ram_count(channelselect) = 1 then
         if blockcurrent < to_integer(CONF.block_count)-1 then
           readout_state <= NEXT_BLOCK;
         elsif channelselect < 3 then
@@ -610,7 +611,7 @@ begin
     end if;
     if cnt = to_integer(myavg-1) then
       cnt := 0;
-      RDO_write_proc <= '1';
+      RDO_write_proc <= not CONF.channel_disable(DEVICE*CHANNELS+channelselect_valid);
     elsif myavg /= 0 then
       cnt := cnt + 1;
     end if;
@@ -700,3 +701,4 @@ end architecture;
 -- 1SSSSSSS  -- Status word, MSN=0x1
 -- 4-AC--LL  -- ADC Header, L: number of data words that follow, MSN=0x4
 -- 2RRVVVVV  -- Configuration data
+-- 3-ACVVVV  -- Processed values