if( rising_edge(ff_txhalfclk) ) then
last_fifo_tx_empty <= fifo_tx_empty;
if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then
- tx_data <= x"c5bc";
+ tx_data <= x"50bc";
tx_k <= "01";
-- elsif send_resync = '1' then
-- tx_data <= x"7F7F";
if( rising_edge(SYSCLK) ) then
last_fifo_tx_empty(i) <= fifo_tx_empty(i);
first_idle(i) <= not last_fifo_tx_empty(i) and fifo_tx_empty(i);
- if( (last_fifo_tx_empty(i) = '1') or tx_allow(i) = '0') then
+ if CTRL_OP(i*16+15) = '1' then
+ tx_data(i*16+15 downto i*16) <= x"FEFE";
+ tx_k(i*2+1 downto i*2) <= "11";
+ elsif( (last_fifo_tx_empty(i) = '1') or tx_allow(i) = '0') then
tx_data(i*16+15 downto i*16) <= x"50bc";
tx_k(i*2+1 downto i*2) <= "01";
tx_correct(i*2+1 downto i*2) <= first_idle(i) & '0';
- elsif CTRL_OP(i*16+15) = '1' then
- tx_data(i*16+15 downto i*16) <= x"FEFE";
- tx_k(i*2+1 downto i*2) <= "11";
else
tx_data(i*16+15 downto i*16) <= fifo_tx_dout(i*18+15 downto i*18+0);
tx_k(i*2+1 downto i*2) <= "00";
if( rising_edge(sysclk) ) then
last_fifo_tx_empty <= fifo_tx_empty;
first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
- if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then
+ if CTRL_OP(15) = '1' then
+ tx_data <= x"FEFE";
+ tx_k <= "11";
+ elsif( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then
tx_data <= x"50bc";
tx_k <= "01";
tx_correct <= first_idle & '0';
- elsif CTRL_OP(15) = '1' then
- tx_data <= x"FEFE";
- tx_k <= "11";
else
tx_data <= fifo_tx_dout(15 downto 0);
tx_k <= "00";
-COMMERCIAL ;\r
-BLOCK RESETPATHS ;\r
-BLOCK ASYNCPATHS ;\r
-\r
-#################################################################\r
-#Clock Constraints\r
-#################################################################\r
-FREQUENCY PORT "CLOCK_INTER_FPGA" 100.000000 MHz ;\r
-FREQUENCY PORT "FCLK_2" 100.000000 MHz ;\r
-FREQUENCY PORT "CLOCK_FEEDBACK" 100.000000 MHz ;\r
-\r
-\r
-#################################################################\r
-# Placement\r
-#################################################################\r
-LOCATE COMP "THE_MED_INTERFACE/THE_SERDES/PCSC_INST" SITE "URPCS" ;\r
-# LOCATE COMP "THE_MED_INTERFACE/THE_SERDES_1" SITE "LRPCS" ;\r
-# LOCATE COMP "THE_MED_INTERFACE/THE_SERDES_2" SITE "URPCS" ;\r
-# LOCATE COMP "THE_MED_INTERFACE/THE_SERDES_3" SITE "ULPCS" ;\r
-\r
-\r
\r
\r
#################################################################\r
# IOBUF PORT "S_OSC_6" IO_TYPE=LVDS25 ;\r
# IOBUF PORT "S_OSC_7" IO_TYPE=LVDS25 ;\r
# IOBUF PORT "S_OSC_8" IO_TYPE=LVDS25 ;\r
-\r
-COMMERCIAL ;\r
-BLOCK RESETPATHS ;\r
-BLOCK ASYNCPATHS ;\r
\r
-#####################################################################\r
-# Constraints\r
-#####################################################################\r
-FREQUENCY PORT "FCLK3" 100.000000 MHz;\r
-FREQUENCY NET "serdes/ff_txhalfclk" 100.000000 MHz ;\r
-FREQUENCY NET "serdes/ff_rxhalfclk_0" 100.000000 MHz ;\r
-FREQUENCY NET "serdes/ff_rxhalfclk_1" 100.000000 MHz ;\r
-FREQUENCY NET "serdes/ff_rxhalfclk_2" 100.000000 MHz ;\r
-FREQUENCY NET "serdes/ff_rxhalfclk_3" 100.000000 MHz ;\r
-FREQUENCY NET "serdes_ff_txhalfclk" 100.000000 MHz ;\r
-FREQUENCY NET "serdes_ff_rxhalfclk_0" 100.000000 MHz ;\r
-FREQUENCY NET "serdes_ff_rxhalfclk_1" 100.000000 MHz ;\r
-FREQUENCY NET "serdes_ff_rxhalfclk_2" 100.000000 MHz ;\r
-FREQUENCY NET "serdes_ff_rxhalfclk_3" 100.000000 MHz ;\r
\r
#####################################################################\r
#Clock\r
LOCATE COMP "ONEWIRE_F3" SITE "T12";\r
IOBUF PORT "ONEWIRE_F3" IO_TYPE=LVTTL33 PULLMODE=NONE ;\r
\r
-# DEFINE CELL GROUP "f3_to_f1_cells" "F3_TO_F2*" ;\r
-#USE DOUT TRUE CELL GROUP "f3_to_f1_cells" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_0" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_1" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_2" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_3" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_4" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_5" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_6" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_7" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_8" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_9" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_10" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_11" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_12" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_13" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_14" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_15" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_16" ;\r
-# USE DOUT TRUE CELL "F3_TO_F1_17" ;\r
-\r
-#\r
-# USE DOUT TRUE CELL "F3_TO_F2_0" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_1" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_2" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_3" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_4" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_5" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_6" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_7" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_8" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_9" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_10" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_11" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_12" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_13" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_14" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_15" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_16" ;\r
-# USE DOUT TRUE CELL "F3_TO_F2_17" ;\r
-\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_0" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_1" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_2" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_3" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_4" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_5" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_6" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_7" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_8" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_9" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_10" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_11" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_12" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_13" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_14" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_15" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_16" ;\r
-# USE DIN TRUE CELL "reg_F1_TO_F3_17" ;\r
-#\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_0" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_1" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_2" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_3" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_4" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_5" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_6" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_7" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_8" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_9" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_10" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_11" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_12" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_13" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_14" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_15" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_16" ;\r
-# USE DIN TRUE CELL "reg_F2_TO_F3_17" ;\r
\r
#####################################################################\r
#JTAG\r
entity adc_ltc2308_readout is
generic(
CLOCK_FREQUENCY : integer := 100; --MHz
- PRESET_RANGES_CH0 : std_logic_vector(23 downto 0) := x"A28_960" ; --5V/2 - 2.4-2.6
- PRESET_RANGES_CH1 : std_logic_vector(23 downto 0) := x"A28_960" ; --5V/2 - 2.4-2.6
- PRESET_RANGES_CH2 : std_logic_vector(23 downto 0) := x"ED8_D48" ; --3.5 - 3.4-3.8
+ PRESET_RANGES_CH0 : std_logic_vector(23 downto 0) := x"C10_A28" ; --5V/2 - 2.4-2.6
+ PRESET_RANGES_CH1 : std_logic_vector(23 downto 0) := x"A00_940" ; --5V/2 - 2.4-2.6
+ PRESET_RANGES_CH2 : std_logic_vector(23 downto 0) := x"F00_D50" ; --3.5 - 3.4-3.8
PRESET_RANGES_CH3 : std_logic_vector(23 downto 0) := x"D48_C80" ; --3.3 - 3.2-3.4
PRESET_RANGES_CH4 : std_logic_vector(23 downto 0) := x"6A0_510" ; --1.4 - 1.3-1.7
PRESET_RANGES_CH5 : std_logic_vector(23 downto 0) := x"4E0_480" ; --1.2 - 1.15-1.25
PRESET_RANGES_CH6 : std_logic_vector(23 downto 0) := x"C10_B50" ; --3.0 - 2.9-3.1
- PRESET_RANGES_CH7 : std_logic_vector(23 downto 0) := x"FFF_000" ---3.0 - ???-???
+ PRESET_RANGES_CH7 : std_logic_vector(23 downto 0) := x"C10_B50" ---3.0 - ???-???
);
port(
CLK : in std_logic;
component trb_net_bridge_etrax_endpoint is
generic(
USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_NO,c_NO,c_NO,c_NO)
+ AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_YES,c_YES,c_YES,c_YES)
);
port(
RESET : in std_logic;
process(CLK)
begin
if rising_edge(CLK) then
- if RESET_VIRT = '0' then
+ if RESET_VIRT = '0' or send_reset_counter(10 downto 0) = "01111111111" then
RESET <= '1';
RESET_CNT <= "00";
else
---------------------------------------------------------------------
STAT_REGS(63 downto 0) <= APL_STAT & STAT_ENDP;
- buf_ADO_TTL(14 downto 0) <= TLK_STAT(15 downto 14) & "0" & TLK_STAT(27 downto 16);
+ buf_ADO_TTL(14 downto 0) <= STAT_API1(14 downto 0); --TLK_STAT(15 downto 14) & "0" & TLK_STAT(27 downto 16);
-- buf_ADO_TTL(0) <= etrax_read;
-- buf_ADO_TTL(6 downto 1) <= EI_STAT(5 downto 0);
-- buf_ADO_TTL(14 downto 7) <= (others => 'Z');
STAT_ENDP(31 downto 24) <= APL_DATA_OUT(55 downto 48);
-STAT_API1(7 downto 0) <= buf_to_apl_REPLY_DATA(23 downto 16);
-STAT_API1(8) <= buf_to_apl_REPLY_READ(1);
-STAT_API1(9) <= buf_to_apl_REPLY_DATAREADY(1);
-STAT_API1(12 downto 10) <= buf_to_apl_REPLY_PACKET_NUM(5 downto 3);
-STAT_API1(31 downto 13) <= (others => '0');
+STAT_API1(3 downto 0) <= apl_to_buf_REPLY_DATA(23 downto 16);
+STAT_API1(7 downto 4) <= apl_to_buf_REPLY_DATA(23 downto 16);
+
+STAT_API1(11) <= apl_to_buf_REPLY_READ(3);
+STAT_API1(12) <= buf_to_apl_REPLY_DATAREADY(3);
+STAT_API1(13) <= apl_to_buf_INIT_DATAREADY(3);
+STAT_API1(14) <= buf_to_apl_INIT_READ(3);
+STAT_API1(31 downto 15) <= (others => '0');
--STAT_API1 <= buf_api_stat_fifo_to_int((2)*32-1 downto (1)*32);
---------------------------------------
-- termination for active api
---------------------------------------
- genterm: if API_TYPE = 1 generate
+ genterm: if API_TYPE = c_API_ACTIVE generate
TrbNetTerm: trb_net16_term
generic map(
USE_APL_PORT => 0,
APL_ERROR_PATTERN_IN => (others => '0')
);
end generate;
- gennotterm: if API_TYPE = 0 generate
+ gennotterm: if API_TYPE = c_API_PASSIVE generate
INT_MASTER_READ_OUT <= '1';
INT_SLAVE_DATAREADY_OUT <= '0';
INT_SLAVE_DATA_OUT <= (others => '0');
CTS_REPLY_READ_IN : in std_logic;
--Event information coming from CTS
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
- IPU_CODE_OUT : out std_logic_vector (7 downto 0);
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- IPU_START_READOUT_OUT : out std_logic;
-
- --Answer sent to CTS
- APL_CTS_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_CTS_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_CTS_DATAREADY_IN : in std_logic;
- APL_CTS_READ_OUT : out std_logic;
- APL_CTS_SHORT_TRANSFER_IN : in std_logic;
- APL_CTS_DTYPE_IN : in std_logic_vector (3 downto 0);
- APL_CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
- APL_CTS_SEND_IN : in std_logic;
- APL_CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
-
- -- Receiver port
- APL_FEE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_FEE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_FEE_TYP_OUT : out std_logic_vector (2 downto 0);
- APL_FEE_DATAREADY_OUT : out std_logic;
- APL_FEE_READ_IN : in std_logic;
-
- -- APL Control port
- APL_CTS_RUN_OUT : out std_logic;
- APL_FEE_RUN_OUT : out std_logic;
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0);
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
+ CTS_START_READOUT_OUT : out std_logic;
+
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);
+ CTS_DATAREADY_IN : in std_logic;
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
+ CTS_READ_OUT : out std_logic;
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
+ CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+
+ -- Data from Frontends
+ FEE_DATA_OUT : out std_logic_vector (31 downto 0);
+ FEE_DATAREADY_OUT : out std_logic;
+ FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
+ FEE_BUSY_OUT : out std_logic;
MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
CTRL_SEQNR_RESET : in std_logic;
architecture trb_net16_api_ipu_streaming_arch of trb_net16_api_ipu_streaming is
- signal APL_CTS_TARGET_ADDRESS : std_logic_vector(15 downto 0);
+ signal APL_CTS_TARGET_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
signal APL_CTS_DATA_OUT : std_logic_vector(15 downto 0);
signal APL_CTS_PACKET_NUM_OUT : std_logic_vector(2 downto 0);
signal APL_CTS_DATAREADY_OUT : std_logic;
signal APL_FEE_DTYPE_IN : std_logic_vector(3 downto 0);
signal APL_FEE_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
signal APL_FEE_SEND_IN : std_logic;
+ signal APL_CTS_TYP_OUT : std_logic_vector(2 downto 0);
-
+ signal buf_CTS_CODE_OUT : std_logic_vector(7 downto 0);
+ signal buf_CTS_INFORMATION_OUT : std_logic_vector(7 downto 0);
+ signal buf_CTS_READOUT_TYPE_OUT : std_logic_vector(3 downto 0);
+ signal buf_CTS_NUMBER_OUT : std_logic_vector(15 downto 0);
+ signal buf_CTS_START_READOUT_OUT : std_logic;
+ signal last_buf_CTS_START_READOUT_OUT : std_logic;
+ signal cts_start_readout_rising : std_logic;
begin
-- Receiver port
APL_DATA_OUT => APL_CTS_DATA_OUT,
APL_PACKET_NUM_OUT=> APL_CTS_PACKET_NUM_OUT,
- APL_TYP_OUT => open,
+ APL_TYP_OUT => APL_CTS_TYP_OUT,
APL_DATAREADY_OUT => APL_CTS_DATAREADY_OUT,
APL_READ_IN => APL_CTS_READ_IN,
-- APL Control port
--Reading CTS data, forwarding to FEE
-------------------------------------------------------------------------------
+ THE_IPUDATA : trb_net16_ipudata
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+ -- Port to API
+ API_DATA_OUT => APL_CTS_DATA_IN,
+ API_PACKET_NUM_OUT => APL_CTS_PACKET_NUM_IN,
+ API_DATAREADY_OUT => APL_CTS_DATAREADY_IN,
+ API_READ_IN => APL_CTS_READ_OUT,
+ API_SHORT_TRANSFER_OUT => APL_CTS_SHORT_TRANSFER_IN,
+ API_DTYPE_OUT => APL_CTS_DTYPE_IN,
+ API_ERROR_PATTERN_OUT => APL_CTS_ERROR_PATTERN_IN,
+ API_SEND_OUT => APL_CTS_SEND_IN,
+ -- Receiver port
+ API_DATA_IN => APL_CTS_DATA_OUT,
+ API_PACKET_NUM_IN => APL_CTS_PACKET_NUM_OUT,
+ API_TYP_IN => APL_CTS_TYP_OUT,
+ API_DATAREADY_IN => APL_CTS_DATAREADY_OUT,
+ API_READ_OUT => APL_CTS_READ_IN,
+ -- APL Control port
+ API_RUN_IN => APL_CTS_RUN_OUT,
+ API_SEQNR_IN => APL_CTS_SEQNR_OUT,
+ API_LENGTH_OUT => APL_CTS_LENGTH_IN,
+ MY_ADDRESS_IN => MY_ADDRESS_IN,
+
+ --Information received with request
+ IPU_NUMBER_OUT => buf_CTS_NUMBER_OUT,
+ IPU_INFORMATION_OUT => buf_CTS_INFORMATION_OUT,
+ IPU_READOUT_TYPE_OUT => buf_CTS_READOUT_TYPE_OUT,
+ IPU_CODE_OUT => buf_CTS_CODE_OUT,
+ --start strobe
+ IPU_START_READOUT_OUT => buf_CTS_START_READOUT_OUT,
+ --detector data, equipped with DHDR
+ IPU_DATA_IN => CTS_DATA_IN,
+ IPU_DATAREADY_IN => CTS_DATAREADY_IN,
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_IN => CTS_READOUT_FINISHED_IN,
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_READ_OUT => CTS_READ_OUT,
+ IPU_LENGTH_IN => CTS_LENGTH_IN,
+ IPU_ERROR_PATTERN_IN => CTS_ERROR_PATTERN_IN,
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------
+--Forward CTS request to FEE & Put Information to Output
+---------------------------------------------------------------------
+
- PROC_FSM_FORWARD_CTS_REQUEST : process(CLK)
+ PROC_START_READOUT_RISING : process(CLK)
begin
- APL_CTS_READ_IN <= '1';
- APL_FEE_SEND_IN <= '0';
- if APL_CTS_DATAREADY_OUT = '1' then
- case APL_CTS_PACKET_NUM_OUT is
- when c_F1 =>
- APL_FEE_ERROR_PATTERN_IN(31 downto 16) <= APL_CTS_DATA_OUT;
- when c_F2 =>
- APL_FEE_ERROR_PATTERN_IN(15 downto 0) <= APL_CTS_DATA_OUT;
- when c_F3 =>
- APL_FEE_SEQNR_IN <= APL_CTS_DATA_OUT(11 downto 4);
- APL_FEE_DTYPE_IN <= APL_CTS_DATA_OUT(3 downto 0);
- APL_FEE_SEND_IN <= '1';
- IPU_START_READOUT_OUT <= '1';
- when others =>
- null;
- end case;
- end if;
- if APL_CTS_RUN_OUT = '0' then
- IPU_START_READOUT_OUT <= '0';
+ if rising_edge(CLK) then
+ last_buf_CTS_START_READOUT_OUT <= buf_CTS_START_READOUT_OUT;
+ cts_start_readout_rising <= buf_CTS_START_READOUT_OUT and not last_buf_CTS_START_READOUT_OUT;
end if;
end process;
+ APL_FEE_SEND_IN <= cts_start_readout_rising;
+
- IPU_NUMBER_OUT <= APL_FEE_ERROR_PATTERN_IN(15 downto 0);
- IPU_CODE_OUT <= APL_FEE_ERROR_PATTERN_IN(23 downto 16);
- IPU_INFORMATION_OUT <= APL_FEE_ERROR_PATTERN_IN(31 downto 24);
+ APL_FEE_ERROR_PATTERN_IN(15 downto 0) <= buf_CTS_NUMBER_OUT;
+ APL_FEE_ERROR_PATTERN_IN(23 downto 16) <= buf_CTS_CODE_OUT;
+ APL_FEE_ERROR_PATTERN_IN(31 downto 24) <= buf_CTS_INFORMATION_OUT;
+ APL_FEE_DTYPE_IN <= buf_CTS_READOUT_TYPE_OUT;
+ CTS_NUMBER_OUT <= buf_CTS_NUMBER_OUT;
+ CTS_INFORMATION_OUT <= buf_CTS_INFORMATION_OUT;
+ CTS_READOUT_TYPE_OUT <= buf_CTS_READOUT_TYPE_OUT;
+ CTS_CODE_OUT <= buf_CTS_CODE_OUT;
+ CTS_START_READOUT_OUT <= buf_CTS_START_READOUT_OUT;
+---------------------------------------------------------------------
+-- Handle incoming data from FEE
+---------------------------------------------------------------------
+
+ PROC_IPU_STATUS_BITS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if APL_FEE_PACKET_NUM_OUT = c_F1 and APL_FEE_TYP_OUT = TYPE_TRM then
+ FEE_STATUS_BITS_OUT(31 downto 16) <= APL_FEE_DATA_OUT;
+ elsif APL_FEE_PACKET_NUM_OUT = c_F2 and APL_FEE_TYP_OUT = TYPE_TRM then
+ FEE_STATUS_BITS_OUT(15 downto 0) <= APL_FEE_DATA_OUT;
+ end if;
+ end if;
+ end process;
+
+ PROC_IPU_DATA : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if FEE_READ_IN = '1' then
+ FEE_DATAREADY_OUT <= '0';
+ end if;
+ if APL_FEE_READ_IN = '1' and APL_FEE_DATAREADY_OUT = '1' and APL_FEE_TYP_OUT = TYPE_DAT then
+ if APL_FEE_PACKET_NUM_OUT = c_F0 or APL_FEE_PACKET_NUM_OUT = c_F2 then
+ FEE_DATA_OUT(31 downto 16) <= APL_FEE_DATA_OUT;
+ elsif APL_FEE_PACKET_NUM_OUT = c_F1 or APL_FEE_PACKET_NUM_OUT = c_F3 then
+ FEE_DATA_OUT(15 downto 0) <= APL_FEE_DATA_OUT;
+ FEE_DATAREADY_OUT <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
end architecture;
\ No newline at end of file
begin
reset_no_link <= MED_STAT_OP_IN(14) or RESET;
- MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15);
- MED_CTRL_OP_OUT(14 downto 0) <= (others => '0');
+ --MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15);
+ MED_CTRL_OP_OUT(15 downto 0) <= (others => '0');
MED_STAT_OP <= MED_STAT_OP_IN;
--Connections for data channel
INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
CLOCK_FREQUENCY : integer range 1 to 200 := 100;
USE_ONEWIRE : integer range 0 to 2 := c_YES;
signal saved_reply_packet_type : std_logic_vector(POINT_NUMBER*3-1 downto 0);
signal last_reply_packet_type : std_logic_vector(POINT_NUMBER*3-1 downto 0);
signal last_reply_packet_number : std_logic_vector(POINT_NUMBER*3-1 downto 0);
- signal last_REPLY_PACKET_NUM_IN : std_logic_vector(POINT_NUMBER*3-1 downto 0);
signal reply_reading_H0 : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_reading_F0 : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_reading_F1 : std_logic_vector(POINT_NUMBER-1 downto 0);
end if;
end process;
- process(CLK)
- begin
- if rising_edge(CLK) then
- if REPLY_DATAREADY_IN(i) = '1' and buf_REPLY_READ_OUT(i) = '1' then
- last_REPLY_PACKET_NUM_IN(i*3+2 downto i*3) <= REPLY_PACKET_NUM_IN(i*3+2 downto i*3);
- end if;
- end if;
- end process;
-
current_reply_packet_type((i+1)*3-1 downto i*3) <= REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH)
when (REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2 downto i*c_NUM_WIDTH) = c_H0)
else saved_reply_packet_type((i+1)*3-1 downto i*3);
--Problematic stuff here... needing reply_packet_num_in to determine read_out ...
- PROC_auto_read_DHDR : process(current_reply_reading_DHDR, current_reply_reading_HDR, last_REPLY_PACKET_NUM_IN)
+ PROC_auto_read_DHDR : process(current_reply_reading_DHDR, current_reply_reading_HDR, REPLY_PACKET_NUM_IN)
begin
- if (reg_current_reply_reading_DHDR(i) = '1' and
- (last_REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = "100" or last_REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = "000"))
- or reg_current_reply_reading_HDR(i) = '1' then
+ if (reg_current_reply_reading_DHDR(i) = '1' and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) = '0') --reg_
+ or reg_current_reply_reading_HDR(i) = '1' then --reg_
reg_current_reply_auto_reading_DHDR(i) <= '1';
else
reg_current_reply_auto_reading_DHDR(i) <= '0';
signal init_arbiter_CLK_EN : std_logic;
signal init_arbiter_ENABLE : std_logic;
signal init_arbiter_read_out : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal init_arbiter_input : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_arbiter_input : std_logic_vector(POINT_NUMBER-1 downto 0);
signal INIT_muxed_DATAREADY : std_logic;
CLK => CLK,
RESET => reset_i,
CLK_EN => init_arbiter_CLK_EN,
- INPUT_IN => INIT_DATAREADY_IN,
+ INPUT_IN => init_arbiter_input,
RESULT_OUT => init_arbiter_read_out,
ENABLE => init_arbiter_ENABLE,
CTRL => (others => '0')
);
init_arbiter_CLK_EN <= not locked;
init_arbiter_ENABLE <= not init_locked;
+ init_arbiter_input <= INIT_DATAREADY_IN and real_activepoints;
----------------------------------
--Merging Data from Init-Channel
CTRL => (others => '0')
);
- reply_arbiter_input <= reply_dataready_in_i and not REPLY_reading_trm;
+ reply_arbiter_input <= reply_dataready_in_i and not REPLY_reading_trm and real_activepoints;
-- we have to care to read multiples of four packets from every point
-- release is currently done after first packet of TRM
next_waiting_for_init_finish <= waiting_for_init_finish;
if current_state = SENDING_DATA then
+ next_waiting_for_init_finish <= '0';
comb_REPLY_POOL_DATAREADY <= comb_REPLY_muxed_DATAREADY;
comb_REPLY_POOL_DATA <= comb_REPLY_muxed_DATA;
comb_REPLY_POOL_PACKET_NUM <= comb_REPLY_muxed_PACKET_NUM;
MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
- --Data Output
--Event information coming from CTS
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
- IPU_CODE_OUT : out std_logic_vector (7 downto 0);
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- IPU_START_READOUT_OUT : out std_logic;
- --Answer sent to CTS
- APL_CTS_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_CTS_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_CTS_DATAREADY_IN : in std_logic;
- APL_CTS_READ_OUT : out std_logic;
- APL_CTS_SHORT_TRANSFER_IN : in std_logic;
- APL_CTS_DTYPE_IN : in std_logic_vector (3 downto 0);
- APL_CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
- APL_CTS_SEND_IN : in std_logic;
- APL_CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
- -- Receiver port
- APL_FEE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_FEE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_FEE_TYP_OUT : out std_logic_vector (2 downto 0);
- APL_FEE_DATAREADY_OUT : out std_logic;
- APL_FEE_READ_IN : in std_logic;
- -- APL Control port
- APL_CTS_RUN_OUT : out std_logic;
- APL_FEE_RUN_OUT : out std_logic;
- IPU_MY_ADDRESS_IN : in std_logic_vector(15 downto 0);
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0);
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
+ CTS_START_READOUT_OUT : out std_logic;
+
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);
+ CTS_DATAREADY_IN : in std_logic;
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
+ CTS_READ_OUT : out std_logic;
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
+ CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+
+ -- Data from Frontends
+ FEE_DATA_OUT : out std_logic_vector (31 downto 0);
+ FEE_DATAREADY_OUT : out std_logic;
+ FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
+ FEE_BUSY_OUT : out std_logic;
+
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ CTRL_SEQNR_RESET : in std_logic;
COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
ONEWIRE_MONITOR_IN : in std_logic;
MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- --Fixed status and control ports
+ --status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
-
- --Debugging registers
+ --Debugging registers
STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
);
CTS_REPLY_READ_IN => cts_reply_read_out,
--Event information coming from CTS
- IPU_NUMBER_OUT => IPU_NUMBER_OUT,
- IPU_CODE_OUT => IPU_CODE_OUT,
- IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
- IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
-
- --Answer sent to CTS
- APL_CTS_DATA_IN => APL_CTS_DATA_IN,
- APL_CTS_PACKET_NUM_IN => APL_CTS_PACKET_NUM_IN,
- APL_CTS_DATAREADY_IN => APL_CTS_DATAREADY_IN,
- APL_CTS_READ_OUT => APL_CTS_READ_OUT,
- APL_CTS_SHORT_TRANSFER_IN => APL_CTS_SHORT_TRANSFER_IN,
- APL_CTS_DTYPE_IN => APL_CTS_DTYPE_IN,
- APL_CTS_ERROR_PATTERN_IN => APL_CTS_ERROR_PATTERN_IN,
- APL_CTS_SEND_IN => APL_CTS_SEND_IN,
- APL_CTS_LENGTH_IN => APL_CTS_LENGTH_IN,
-
- -- Receiver port
- APL_FEE_DATA_OUT => APL_FEE_DATA_OUT,
- APL_FEE_PACKET_NUM_OUT => APL_FEE_PACKET_NUM_OUT,
- APL_FEE_TYP_OUT => APL_FEE_TYP_OUT,
- APL_FEE_DATAREADY_OUT => APL_FEE_DATAREADY_OUT,
- APL_FEE_READ_IN => APL_FEE_READ_IN,
-
- -- APL Control port
- APL_CTS_RUN_OUT => APL_CTS_RUN_OUT,
- APL_FEE_RUN_OUT => APL_FEE_RUN_OUT,
+ CTS_NUMBER_OUT => CTS_NUMBER_OUT,
+ CTS_CODE_OUT => CTS_CODE_OUT,
+ CTS_INFORMATION_OUT => CTS_INFORMATION_OUT,
+ CTS_READOUT_TYPE_OUT => CTS_READOUT_TYPE_OUT,
+ CTS_START_READOUT_OUT => CTS_START_READOUT_OUT,
+
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN => CTS_DATA_IN,
+ CTS_DATAREADY_IN => CTS_DATAREADY_IN,
+ CTS_READOUT_FINISHED_IN => CTS_READOUT_FINISHED_IN,
+ CTS_READ_OUT => CTS_READ_OUT,
+ CTS_LENGTH_IN => CTS_LENGTH_IN,
+ CTS_ERROR_PATTERN_IN => CTS_ERROR_PATTERN_IN,
+
+ -- Data from Frontends
+ FEE_DATA_OUT => FEE_DATA_OUT,
+ FEE_DATAREADY_OUT => FEE_DATAREADY_OUT,
+ FEE_READ_IN => FEE_READ_IN,
+ FEE_STATUS_BITS_OUT => FEE_STATUS_BITS_OUT,
+ FEE_BUSY_OUT => FEE_BUSY_OUT,
MY_ADDRESS_IN => IPU_MY_ADDRESS_IN,
CTRL_SEQNR_RESET => common_ctrl(10)
IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
+ IPU_CODE_OUT : out std_logic_vector (7 downto 0);
--start strobe
IPU_START_READOUT_OUT: out std_logic;
--detector data, equipped with DHDR
IPU_READ_OUT <= buf_IPU_READ;
IPU_INFORMATION_OUT <= buf_INFORMATION;
IPU_READOUT_TYPE_OUT <= buf_TYPE;
+ IPU_CODE_OUT <= buf_RND_CODE;
---------------------------------------------------------------------
--Debugging
when RESETTING =>
next_MED_ERROR_OUT <= ERROR_NC;
next_internal_reset <= '1';
+ next_rx_allow <= '0';
+ next_tx_allow <= '0';
counter_reset <= '0';
if counter(16) = '1' then
counter_reset <= '1';
stat_op(10) <= rx_led; --rx led
stat_op(11) <= tx_led; --tx led
stat_op(12) <= '0'; -- unused
- stat_op(13) <= '0';
+ stat_op(13) <= make_reset_q;
stat_op(14) <= reg_SFP_LOS or make_reset_q; -- reset out
stat_op(15) <= send_reset_q; -- protocol error
CTS_REPLY_READ_IN : in std_logic;
--Event information coming from CTS
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
- IPU_CODE_OUT : out std_logic_vector (7 downto 0);
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- IPU_START_READOUT_OUT : out std_logic;
-
- --Answer sent to CTS
- APL_CTS_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_CTS_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_CTS_DATAREADY_IN : in std_logic;
- APL_CTS_READ_OUT : out std_logic;
- APL_CTS_SHORT_TRANSFER_IN : in std_logic;
- APL_CTS_DTYPE_IN : in std_logic_vector (3 downto 0);
- APL_CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
- APL_CTS_SEND_IN : in std_logic;
- APL_CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
-
- -- Receiver port
- APL_FEE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- APL_FEE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_FEE_TYP_OUT : out std_logic_vector (2 downto 0);
- APL_FEE_DATAREADY_OUT : out std_logic;
- APL_FEE_READ_IN : in std_logic;
-
- -- APL Control port
- APL_CTS_RUN_OUT : out std_logic;
- APL_FEE_RUN_OUT : out std_logic;
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0);
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
+ CTS_START_READOUT_OUT : out std_logic;
+
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);
+ CTS_DATAREADY_IN : in std_logic;
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
+ CTS_READ_OUT : out std_logic;
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
+ CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+
+ -- Data from Frontends
+ FEE_DATA_OUT : out std_logic_vector (31 downto 0);
+ FEE_DATAREADY_OUT : out std_logic;
+ FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
+ FEE_BUSY_OUT : out std_logic;
MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
- CTRL_SEQNR_RESET : in std_logic
+ CTRL_SEQNR_RESET : in std_logic;
);
end component;
IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ IPU_CODE_OUT : out std_logic_vector (7 downto 0);
--start strobe
IPU_START_READOUT_OUT: out std_logic;
--detector data, equipped with DHDR
jspc29 / trbnet.git / commitdiff