architecture arch of MimosisInput is
constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00";
- constant WORD_LIMIT : integer := 3990;
+ constant WORD_LIMIT : integer := 8500;
signal input_active_i : std_logic;
signal data_i : std_logic_vector(15 downto 0);
if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then
frame_state <= HDR1;
frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16);
- buffer_write <= not buffer_full;
- buffer_blocked <= buffer_full;
+ buffer_write <= '1' when buffer_full = '0' and state = IDLE else '0';
+ buffer_blocked <= '0' when buffer_full = '0' and state = IDLE else '1';
count_header <= count_header + 1;
end if;
when HDR1 =>
add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd"
add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
+
add_file -vhdl -lib work "./cores/mimosis_inp.vhd"
add_file -vhdl -lib work "./cores/testout.vhd"
add_file -vhdl -lib work "./code/MimosisInput.vhd"
H6 : inout std_logic_vector(4 downto 0);\r
H7 : inout std_logic_vector(4 downto 0);\r
\r
- PIN : inout std_logic_vector(8 downto 1);\r
+ PIN : out std_logic_vector(8 downto 1);\r
\r
MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic;\r
\r
\r
--Other Connectors\r
TEST : inout std_logic_vector(14 downto 1); --on v1 only\r
- HDR_IO : inout std_logic_vector(23 downto 0) --23..16 on v2 only\r
+ --COMMON_SDA, COMMON_SCL : inout std_logic\r
+ HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only\r
);\r
\r
\r
signal mimosis_scl_drv, mimosis_sda_drv : std_logic;\r
signal i2c_go_100, i2c_go : std_logic;\r
signal i2c_reg_5_40 : std_logic_vector(31 downto 0);\r
-\r
+ signal counter : unsigned(23 downto 0);\r
--signal fwd_dst_mac : std_logic_vector(47 downto 0);\r
--signal fwd_dst_ip : std_logic_vector(31 downto 0);\r
--signal fwd_dst_port : std_logic_vector(15 downto 0);\r
SPI_MISO_IN => spi_miso,\r
SPI_CLK_OUT => spi_clk,\r
--Header\r
- HEADER_IO => open, --HDR_IO(9 downto 0),\r
+ --HEADER_IO => open,\r
+ HEADER_IO(7) => HDR_IO(6),\r
+ HEADER_IO(8) => HDR_IO(7),\r
ADDITIONAL_REG => add_reg,\r
--ADC\r
ADC_CS => ADC_NCS,\r
DEBUG_OUT => debug_tools\r
);\r
\r
+--counter <= counter + '1' when rising_edge(clk_sys);\r
+--HDR_IO <= std_logic_vector(counter(15 downto 0));\r
+--LED <= std_logic_vector(counter(23 downto 16));\r
\r
-\r
+ --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
+ --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
+ \r
FLASH_HOLD <= '1';\r
FLASH_WP <= '1';\r
\r
---------------------------------------------------------------------------\r
-- I2C\r
---------------------------------------------------------------------------\r
-THE_I2C : entity work.i2c_slim \r
+THE_I2C : entity work.i2c_slim2 \r
port map(\r
CLOCK => clk_40,\r
RESET => reset_i,\r
I2C_GO_IN => i2c_go,\r
ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read\r
WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word\r
+ DIRECT_IN => i2c_reg_1(4), -- don't send command\r
I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined)\r
I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored)\r
I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte)\r
SCL_IN => PIN(3),\r
SCL_OUT => mimosis_scl_drv,\r
-- Debug\r
- BSM_OUT => i2c_reg_4(28 downto 24)\r
+ BSM_OUT => i2c_reg_4(27 downto 24)\r
);\r
\r
-- I2C signal open collector driver\r
-PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
-PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+\r
+PIN(4) <= MIMOSIS_SDA;\r
+PIN(3) <= MIMOSIS_SCL;\r
+MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+\r
H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC\r
PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START\r
PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET\r
LOCATE COMP "H7[3]" SITE "W30" ; #was "FE_DIFF[7]"
#LOCATE COMP "H5[4]" SITE "T32" ; #was "FE_DIFF[8]"
-LOCATE COMP "MIMOSIS_SCL" SITE "T32" ; #was "FE_DIFF[8]"
-LOCATE COMP "MIMOSIS_SDA" SITE "U32" ; #was "FE_DIFF[8]"
+LOCATE COMP "MIMOSIS_SCL" SITE "U32" ; #was "FE_DIFF[8]"
+LOCATE COMP "MIMOSIS_SDA" SITE "T32" ; #was "FE_DIFF[8]"
IOBUF PORT "MIMOSIS_SCL" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MIMOSIS_SDA" IO_TYPE=LVCMOS25 ;
LOCATE COMP "HDR_IO_23" SITE "F20"; #on HDR_14
DEFINE PORT GROUP "HDR_group" "HDR*" ;
-IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ;
+IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "COMMON_SDA" SITE "B22"; #on HDR_2
+LOCATE COMP "COMMON_SCL" SITE "D24"; #on HDR_9
+DEFINE PORT GROUP "COMMON_group" "COMMON*" ;
+IOBUF GROUP "COMMON_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
#################################################################
# Test & Other IO - from version 1 boards (TEST pins have not been reassigned)
#################################################################