<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_44_data_delay" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 20 20:31:36.041" version="4.8" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="fifo_44_data_delay" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 01 16:22:47.436" version="4.8" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="fifo_44_data_delay.lpc" type="lpc" modified="2013 10 20 20:31:33.000"/>
- <File name="fifo_44_data_delay.vhd" type="top_level_vhdl" modified="2013 10 20 20:31:33.000"/>
- <File name="fifo_44_data_delay_tmpl.vhd" type="template_vhdl" modified="2013 10 20 20:31:33.000"/>
- <File name="tb_fifo_44_data_delay_tmpl.vhd" type="testbench_vhdl" modified="2013 10 20 20:31:33.000"/>
+ <File name="fifo_44_data_delay.lpc" type="lpc" modified="2013 12 01 16:22:45.000"/>
+ <File name="fifo_44_data_delay.vhd" type="top_level_vhdl" modified="2013 12 01 16:22:45.000"/>
+ <File name="fifo_44_data_delay_tmpl.vhd" type="template_vhdl" modified="2013 12 01 16:22:45.000"/>
+ <File name="tb_fifo_44_data_delay_tmpl.vhd" type="testbench_vhdl" modified="2013 12 01 16:22:45.000"/>
</Package>
</DiamondModule>
ModuleName=fifo_44_data_delay
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=10/20/2013
-Time=20:31:33
+Date=12/01/2013
+Time=16:22:45
[Parameters]
Verilog=0
Depth=256
Width=44
regout=1
-CtrlByRdEn=1
+CtrlByRdEn=0
EmpFlg=1
PeMode=Dynamic - Single Threshold
-PeAssert=10
+PeAssert=2
PeDeassert=12
FullFlg=0
-PfMode=Static - Dual Threshold
+PfMode=Dynamic - Single Threshold
PfAssert=508
PfDeassert=506
RDataCount=0
-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
-- Module Version: 4.8
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 44 -depth 256 -regout -pe 0 -pf -1 -e
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 44 -depth 256 -regout -no_enable -pe 0 -pf -1 -e
--- Sun Oct 20 20:31:33 2013
+-- Sun Dec 1 16:22:45 2013
library IEEE;
use IEEE.std_logic_1164.all;
signal rptr_6: std_logic;
signal rptr_7: std_logic;
signal rptr_8: std_logic;
- signal ffidata_0: std_logic;
- signal ffidata_1: std_logic;
- signal ffidata_2: std_logic;
- signal ffidata_3: std_logic;
- signal ffidata_4: std_logic;
- signal ffidata_5: std_logic;
- signal ffidata_6: std_logic;
- signal ffidata_7: std_logic;
- signal ffidata_8: std_logic;
- signal ffidata_9: std_logic;
- signal ffidata_10: std_logic;
- signal ffidata_11: std_logic;
- signal ffidata_12: std_logic;
- signal ffidata_13: std_logic;
- signal ffidata_14: std_logic;
- signal ffidata_15: std_logic;
- signal ffidata_16: std_logic;
- signal ffidata_17: std_logic;
- signal ffidata_18: std_logic;
- signal ffidata_19: std_logic;
- signal ffidata_20: std_logic;
- signal ffidata_21: std_logic;
- signal ffidata_22: std_logic;
- signal ffidata_23: std_logic;
- signal ffidata_24: std_logic;
- signal ffidata_25: std_logic;
- signal ffidata_26: std_logic;
- signal ffidata_27: std_logic;
- signal ffidata_28: std_logic;
- signal ffidata_29: std_logic;
- signal ffidata_30: std_logic;
- signal ffidata_31: std_logic;
- signal ffidata_32: std_logic;
- signal ffidata_33: std_logic;
- signal ffidata_34: std_logic;
- signal ffidata_35: std_logic;
- signal ffidata_36: std_logic;
- signal ffidata_37: std_logic;
- signal ffidata_38: std_logic;
- signal ffidata_39: std_logic;
- signal ffidata_40: std_logic;
- signal ffidata_41: std_logic;
- signal ffidata_42: std_logic;
- signal ffidata_43: std_logic;
signal rcnt_reg_8: std_logic;
signal ifcount_0: std_logic;
signal ifcount_1: std_logic;
attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_44_data_delay.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
attribute GSR of FF_56 : label is "ENABLED";
attribute GSR of FF_55 : label is "ENABLED";
attribute GSR of FF_54 : label is "ENABLED";
port map (A=>rcnt_reg_8, B=>rcnt_reg_7, Z=>ae_set_setsig);
pdp_ram_0_0_1: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>ffidata_18, DO1=>ffidata_19,
- DO2=>ffidata_20, DO3=>ffidata_21, DO4=>ffidata_22,
- DO5=>ffidata_23, DO6=>ffidata_24, DO7=>ffidata_25,
- DO8=>ffidata_26, DO9=>ffidata_27, DO10=>ffidata_28,
- DO11=>ffidata_29, DO12=>ffidata_30, DO13=>ffidata_31,
- DO14=>ffidata_32, DO15=>ffidata_33, DO16=>ffidata_34,
- DO17=>ffidata_35, DO18=>ffidata_0, DO19=>ffidata_1,
- DO20=>ffidata_2, DO21=>ffidata_3, DO22=>ffidata_4,
- DO23=>ffidata_5, DO24=>ffidata_6, DO25=>ffidata_7,
- DO26=>ffidata_8, DO27=>ffidata_9, DO28=>ffidata_10,
- DO29=>ffidata_11, DO30=>ffidata_12, DO31=>ffidata_13,
- DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16,
- DO35=>ffidata_17);
+ ADR12=>rptr_7, ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset,
+ DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22),
+ DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27),
+ DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), DO13=>Q(31),
+ DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), DO17=>Q(35),
+ DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4),
+ DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9),
+ DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13),
+ DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
pdp_ram_0_1_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
DI7=>Data(43), DI8=>scuba_vlo, DI9=>scuba_vlo,
ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3,
ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7,
- ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo,
+ ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>open,
DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open,
DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open,
DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
- DO16=>open, DO17=>open, DO18=>ffidata_36, DO19=>ffidata_37,
- DO20=>ffidata_38, DO21=>ffidata_39, DO22=>ffidata_40,
- DO23=>ffidata_41, DO24=>ffidata_42, DO25=>ffidata_43,
- DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
- DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+ DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37),
+ DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41),
+ DO24=>Q(42), DO25=>Q(43), DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
- FF_100: FD1P3DX
+ FF_56: FD1P3DX
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_99: FD1P3DX
+ FF_55: FD1P3DX
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_98: FD1P3DX
+ FF_54: FD1P3DX
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_97: FD1P3DX
+ FF_53: FD1P3DX
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_96: FD1P3DX
+ FF_52: FD1P3DX
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_95: FD1P3DX
+ FF_51: FD1P3DX
port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
- FF_94: FD1P3DX
+ FF_50: FD1P3DX
port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
- FF_93: FD1P3DX
+ FF_49: FD1P3DX
port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_7);
- FF_92: FD1P3DX
+ FF_48: FD1P3DX
port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_8);
- FF_91: FD1S3BX
+ FF_47: FD1S3BX
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_90: FD1S3DX
+ FF_46: FD1S3DX
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_89: FD1P3BX
+ FF_45: FD1P3BX
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
Q=>wcount_0);
- FF_88: FD1P3DX
+ FF_44: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_87: FD1P3DX
+ FF_43: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_86: FD1P3DX
+ FF_42: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_85: FD1P3DX
+ FF_41: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_84: FD1P3DX
+ FF_40: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
- FF_83: FD1P3DX
+ FF_39: FD1P3DX
port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
- FF_82: FD1P3DX
+ FF_38: FD1P3DX
port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_7);
- FF_81: FD1P3DX
+ FF_37: FD1P3DX
port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_8);
- FF_80: FD1P3BX
+ FF_36: FD1P3BX
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
Q=>rcount_0);
- FF_79: FD1P3DX
+ FF_35: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_78: FD1P3DX
+ FF_34: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_77: FD1P3DX
+ FF_33: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_76: FD1P3DX
+ FF_32: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_75: FD1P3DX
+ FF_31: FD1P3DX
port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
- FF_74: FD1P3DX
+ FF_30: FD1P3DX
port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
- FF_73: FD1P3DX
+ FF_29: FD1P3DX
port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_7);
- FF_72: FD1P3DX
+ FF_28: FD1P3DX
port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_8);
- FF_71: FD1P3DX
+ FF_27: FD1P3DX
port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_0);
- FF_70: FD1P3DX
+ FF_26: FD1P3DX
port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_1);
- FF_69: FD1P3DX
+ FF_25: FD1P3DX
port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_2);
- FF_68: FD1P3DX
+ FF_24: FD1P3DX
port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_3);
- FF_67: FD1P3DX
+ FF_23: FD1P3DX
port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_4);
- FF_66: FD1P3DX
+ FF_22: FD1P3DX
port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_5);
- FF_65: FD1P3DX
+ FF_21: FD1P3DX
port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_6);
- FF_64: FD1P3DX
+ FF_20: FD1P3DX
port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_7);
- FF_63: FD1P3DX
+ FF_19: FD1P3DX
port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_8);
- FF_62: FD1P3DX
+ FF_18: FD1P3DX
port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_0);
- FF_61: FD1P3DX
+ FF_17: FD1P3DX
port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_1);
- FF_60: FD1P3DX
+ FF_16: FD1P3DX
port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_2);
- FF_59: FD1P3DX
+ FF_15: FD1P3DX
port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_3);
- FF_58: FD1P3DX
+ FF_14: FD1P3DX
port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_4);
- FF_57: FD1P3DX
+ FF_13: FD1P3DX
port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_5);
- FF_56: FD1P3DX
+ FF_12: FD1P3DX
port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_6);
- FF_55: FD1P3DX
+ FF_11: FD1P3DX
port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_7);
- FF_54: FD1P3DX
+ FF_10: FD1P3DX
port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_8);
- FF_53: FD1P3DX
- port map (D=>ffidata_0, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(0));
-
- FF_52: FD1P3DX
- port map (D=>ffidata_1, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(1));
-
- FF_51: FD1P3DX
- port map (D=>ffidata_2, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(2));
-
- FF_50: FD1P3DX
- port map (D=>ffidata_3, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(3));
-
- FF_49: FD1P3DX
- port map (D=>ffidata_4, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(4));
-
- FF_48: FD1P3DX
- port map (D=>ffidata_5, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(5));
-
- FF_47: FD1P3DX
- port map (D=>ffidata_6, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(6));
-
- FF_46: FD1P3DX
- port map (D=>ffidata_7, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(7));
-
- FF_45: FD1P3DX
- port map (D=>ffidata_8, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(8));
-
- FF_44: FD1P3DX
- port map (D=>ffidata_9, SP=>RdEn, CK=>Clock, CD=>Reset, Q=>Q(9));
-
- FF_43: FD1P3DX
- port map (D=>ffidata_10, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(10));
-
- FF_42: FD1P3DX
- port map (D=>ffidata_11, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(11));
-
- FF_41: FD1P3DX
- port map (D=>ffidata_12, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(12));
-
- FF_40: FD1P3DX
- port map (D=>ffidata_13, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(13));
-
- FF_39: FD1P3DX
- port map (D=>ffidata_14, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(14));
-
- FF_38: FD1P3DX
- port map (D=>ffidata_15, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(15));
-
- FF_37: FD1P3DX
- port map (D=>ffidata_16, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(16));
-
- FF_36: FD1P3DX
- port map (D=>ffidata_17, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(17));
-
- FF_35: FD1P3DX
- port map (D=>ffidata_18, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(18));
-
- FF_34: FD1P3DX
- port map (D=>ffidata_19, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(19));
-
- FF_33: FD1P3DX
- port map (D=>ffidata_20, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(20));
-
- FF_32: FD1P3DX
- port map (D=>ffidata_21, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(21));
-
- FF_31: FD1P3DX
- port map (D=>ffidata_22, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(22));
-
- FF_30: FD1P3DX
- port map (D=>ffidata_23, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(23));
-
- FF_29: FD1P3DX
- port map (D=>ffidata_24, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(24));
-
- FF_28: FD1P3DX
- port map (D=>ffidata_25, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(25));
-
- FF_27: FD1P3DX
- port map (D=>ffidata_26, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(26));
-
- FF_26: FD1P3DX
- port map (D=>ffidata_27, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(27));
-
- FF_25: FD1P3DX
- port map (D=>ffidata_28, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(28));
-
- FF_24: FD1P3DX
- port map (D=>ffidata_29, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(29));
-
- FF_23: FD1P3DX
- port map (D=>ffidata_30, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(30));
-
- FF_22: FD1P3DX
- port map (D=>ffidata_31, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(31));
-
- FF_21: FD1P3DX
- port map (D=>ffidata_32, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(32));
-
- FF_20: FD1P3DX
- port map (D=>ffidata_33, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(33));
-
- FF_19: FD1P3DX
- port map (D=>ffidata_34, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(34));
-
- FF_18: FD1P3DX
- port map (D=>ffidata_35, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(35));
-
- FF_17: FD1P3DX
- port map (D=>ffidata_36, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(36));
-
- FF_16: FD1P3DX
- port map (D=>ffidata_37, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(37));
-
- FF_15: FD1P3DX
- port map (D=>ffidata_38, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(38));
-
- FF_14: FD1P3DX
- port map (D=>ffidata_39, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(39));
-
- FF_13: FD1P3DX
- port map (D=>ffidata_40, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(40));
-
- FF_12: FD1P3DX
- port map (D=>ffidata_41, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(41));
-
- FF_11: FD1P3DX
- port map (D=>ffidata_42, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(42));
-
- FF_10: FD1P3DX
- port map (D=>ffidata_43, SP=>RdEn, CK=>Clock, CD=>Reset,
- Q=>Q(43));
-
FF_9: FD1S3DX
port map (D=>rcnt_sub_0, CK=>Clock, CD=>Reset, Q=>rcnt_reg_0);
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="fifo_ts_32to32_dc" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 08 16 20:07:51.705" version="5.4" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="fifo_ts_32to32_dc" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 01 06:07:44.664" version="5.4" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="fifo_ts_32to32_dc.lpc" type="lpc" modified="2013 08 16 20:07:49.000"/>
- <File name="fifo_ts_32to32_dc.vhd" type="top_level_vhdl" modified="2013 08 16 20:07:50.000"/>
- <File name="fifo_ts_32to32_dc_tmpl.vhd" type="template_vhdl" modified="2013 08 16 20:07:50.000"/>
- <File name="tb_fifo_ts_32to32_dc_tmpl.vhd" type="testbench_vhdl" modified="2013 08 16 20:07:50.000"/>
+ <File name="fifo_ts_32to32_dc.lpc" type="lpc" modified="2013 12 01 06:07:38.000"/>
+ <File name="fifo_ts_32to32_dc.vhd" type="top_level_vhdl" modified="2013 12 01 06:07:38.000"/>
+ <File name="fifo_ts_32to32_dc_tmpl.vhd" type="template_vhdl" modified="2013 12 01 06:07:38.000"/>
+ <File name="tb_fifo_ts_32to32_dc_tmpl.vhd" type="testbench_vhdl" modified="2013 12 01 06:07:38.000"/>
</Package>
</DiamondModule>
ModuleName=fifo_ts_32to32_dc
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=08/16/2013
-Time=20:07:49
+Date=12/01/2013
+Time=06:07:38
[Parameters]
Verilog=0
RDepth=4
RWidth=32
regout=1
-CtrlByRdEn=1
+CtrlByRdEn=0
EmpFlg=0
PeMode=Static - Single Threshold
PeAssert=2
-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
-- Module Version: 5.4
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 32 -depth 4 -rdata_width 32 -regout -pe -1 -pf -1 -e
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 32 -depth 4 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -e
--- Fri Aug 16 20:07:50 2013
+-- Sun Dec 1 06:07:38 2013
library IEEE;
use IEEE.std_logic_1164.all;
signal rptr_0: std_logic;
signal rptr_1: std_logic;
signal rptr_2: std_logic;
- signal ffidata_0: std_logic;
- signal ffidata_1: std_logic;
- signal ffidata_2: std_logic;
- signal ffidata_3: std_logic;
- signal ffidata_4: std_logic;
- signal ffidata_5: std_logic;
- signal ffidata_6: std_logic;
- signal ffidata_7: std_logic;
- signal ffidata_8: std_logic;
- signal ffidata_9: std_logic;
- signal ffidata_10: std_logic;
- signal ffidata_11: std_logic;
- signal ffidata_12: std_logic;
- signal ffidata_13: std_logic;
- signal ffidata_14: std_logic;
- signal ffidata_15: std_logic;
- signal ffidata_16: std_logic;
- signal ffidata_17: std_logic;
- signal ffidata_18: std_logic;
- signal ffidata_19: std_logic;
- signal ffidata_20: std_logic;
- signal ffidata_21: std_logic;
- signal ffidata_22: std_logic;
- signal ffidata_23: std_logic;
- signal ffidata_24: std_logic;
- signal ffidata_25: std_logic;
- signal ffidata_26: std_logic;
- signal ffidata_27: std_logic;
- signal ffidata_28: std_logic;
- signal ffidata_29: std_logic;
- signal ffidata_30: std_logic;
- signal ffidata_31: std_logic;
signal w_gcount_0: std_logic;
signal w_gcount_1: std_logic;
signal w_gcount_2: std_logic;
attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_ts_32to32_dc.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
attribute GSR of FF_31 : label is "ENABLED";
attribute GSR of FF_30 : label is "ENABLED";
attribute GSR of FF_29 : label is "ENABLED";
AD0=>scuba_vlo, DO0=>full_cmp_clr);
pdp_ram_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo,
ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo,
- ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i,
- CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_18,
- DO1=>ffidata_19, DO2=>ffidata_20, DO3=>ffidata_21,
- DO4=>ffidata_22, DO5=>ffidata_23, DO6=>ffidata_24,
- DO7=>ffidata_25, DO8=>ffidata_26, DO9=>ffidata_27,
- DO10=>ffidata_28, DO11=>ffidata_29, DO12=>ffidata_30,
- DO13=>ffidata_31, DO14=>open, DO15=>open, DO16=>open,
- DO17=>open, DO18=>ffidata_0, DO19=>ffidata_1,
- DO20=>ffidata_2, DO21=>ffidata_3, DO22=>ffidata_4,
- DO23=>ffidata_5, DO24=>ffidata_6, DO25=>ffidata_7,
- DO26=>ffidata_8, DO27=>ffidata_9, DO28=>ffidata_10,
- DO29=>ffidata_11, DO30=>ffidata_12, DO31=>ffidata_13,
- DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16,
- DO35=>ffidata_17);
-
- FF_63: FD1P3BX
+ ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi,
+ CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
+ DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
+ DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
+ DO12=>Q(30), DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
+ DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
+ DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
+ DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
+ DO35=>Q(17));
+
+ FF_31: FD1P3BX
port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
Q=>wcount_0);
- FF_62: FD1P3DX
+ FF_30: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_1);
- FF_61: FD1P3DX
+ FF_29: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_2);
- FF_60: FD1P3DX
+ FF_28: FD1P3DX
port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_0);
- FF_59: FD1P3DX
+ FF_27: FD1P3DX
port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_1);
- FF_58: FD1P3DX
+ FF_26: FD1P3DX
port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_2);
- FF_57: FD1P3DX
+ FF_25: FD1P3DX
port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_0);
- FF_56: FD1P3DX
+ FF_24: FD1P3DX
port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_1);
- FF_55: FD1P3DX
+ FF_23: FD1P3DX
port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_2);
- FF_54: FD1P3BX
+ FF_22: FD1P3BX
port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
Q=>rcount_0);
- FF_53: FD1P3DX
+ FF_21: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_1);
- FF_52: FD1P3DX
+ FF_20: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_2);
- FF_51: FD1P3DX
+ FF_19: FD1P3DX
port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_0);
- FF_50: FD1P3DX
+ FF_18: FD1P3DX
port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_1);
- FF_49: FD1P3DX
+ FF_17: FD1P3DX
port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_2);
- FF_48: FD1P3DX
+ FF_16: FD1P3DX
port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_0);
- FF_47: FD1P3DX
+ FF_15: FD1P3DX
port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_1);
- FF_46: FD1P3DX
+ FF_14: FD1P3DX
port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_2);
- FF_45: FD1P3DX
- port map (D=>ffidata_0, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(0));
-
- FF_44: FD1P3DX
- port map (D=>ffidata_1, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(1));
-
- FF_43: FD1P3DX
- port map (D=>ffidata_2, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(2));
-
- FF_42: FD1P3DX
- port map (D=>ffidata_3, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(3));
-
- FF_41: FD1P3DX
- port map (D=>ffidata_4, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(4));
-
- FF_40: FD1P3DX
- port map (D=>ffidata_5, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(5));
-
- FF_39: FD1P3DX
- port map (D=>ffidata_6, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(6));
-
- FF_38: FD1P3DX
- port map (D=>ffidata_7, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(7));
-
- FF_37: FD1P3DX
- port map (D=>ffidata_8, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(8));
-
- FF_36: FD1P3DX
- port map (D=>ffidata_9, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(9));
-
- FF_35: FD1P3DX
- port map (D=>ffidata_10, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(10));
-
- FF_34: FD1P3DX
- port map (D=>ffidata_11, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(11));
-
- FF_33: FD1P3DX
- port map (D=>ffidata_12, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(12));
-
- FF_32: FD1P3DX
- port map (D=>ffidata_13, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(13));
-
- FF_31: FD1P3DX
- port map (D=>ffidata_14, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(14));
-
- FF_30: FD1P3DX
- port map (D=>ffidata_15, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(15));
-
- FF_29: FD1P3DX
- port map (D=>ffidata_16, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(16));
-
- FF_28: FD1P3DX
- port map (D=>ffidata_17, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(17));
-
- FF_27: FD1P3DX
- port map (D=>ffidata_18, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(18));
-
- FF_26: FD1P3DX
- port map (D=>ffidata_19, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(19));
-
- FF_25: FD1P3DX
- port map (D=>ffidata_20, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(20));
-
- FF_24: FD1P3DX
- port map (D=>ffidata_21, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(21));
-
- FF_23: FD1P3DX
- port map (D=>ffidata_22, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(22));
-
- FF_22: FD1P3DX
- port map (D=>ffidata_23, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(23));
-
- FF_21: FD1P3DX
- port map (D=>ffidata_24, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(24));
-
- FF_20: FD1P3DX
- port map (D=>ffidata_25, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(25));
-
- FF_19: FD1P3DX
- port map (D=>ffidata_26, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(26));
-
- FF_18: FD1P3DX
- port map (D=>ffidata_27, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(27));
-
- FF_17: FD1P3DX
- port map (D=>ffidata_28, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(28));
-
- FF_16: FD1P3DX
- port map (D=>ffidata_29, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(29));
-
- FF_15: FD1P3DX
- port map (D=>ffidata_30, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(30));
-
- FF_14: FD1P3DX
- port map (D=>ffidata_31, SP=>RdEn, CK=>RdClock, CD=>rRst,
- Q=>Q(31));
-
FF_13: FD1S3DX
port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="ram_dp_128x32" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 11 30 22:39:04.386" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="" type="mem" modified="2013 11 30 22:39:04.000"/>
+ <File name="ram_dp_128x32.lpc" type="lpc" modified="2013 11 30 22:39:02.000"/>
+ <File name="ram_dp_128x32.vhd" type="top_level_vhdl" modified="2013 11 30 22:39:02.000"/>
+ <File name="ram_dp_128x32_tmpl.vhd" type="template_vhdl" modified="2013 11 30 22:39:02.000"/>
+ <File name="tb_ram_dp_128x32_tmpl.vhd" type="testbench_vhdl" modified="2013 11 30 22:39:02.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP
+CoreRevision=6.1
+ModuleName=ram_dp_128x32
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=11/30/2013
+Time=22:39:02
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=128
+RData=32
+WAddress=128
+WData=32
+enByte=0
+ByteSize=9
+adPipeline=0
+inPipeline=0
+outPipeline=1
+MOR=0
+InData=Registered
+AdControl=Registered
+MemFile=
+MemFormat=bin
+Reset=Sync
+GSR=Enabled
+Pad=0
+EnECC=0
+Optimization=Speed
+EnSleep=ENABLED
+Pipeline=0
+
+[FilesGenerated]
+=mem
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module Version: 6.1
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 128 -outdata REGISTERED -cascade -1 -e
+
+-- Sat Nov 30 22:39:02 2013
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ram_dp_128x32 is
+ port (
+ WrAddress: in std_logic_vector(6 downto 0);
+ RdAddress: in std_logic_vector(6 downto 0);
+ Data: in std_logic_vector(31 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(31 downto 0));
+end ram_dp_128x32;
+
+architecture Structure of ram_dp_128x32 is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component PDPW16KC
+ generic (GSR : in String; CSDECODE_R : in String;
+ CSDECODE_W : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute MEM_LPC_FILE of ram_dp_128x32_0_0_0 : label is "ram_dp_128x32.lpc";
+ attribute MEM_INIT_FILE of ram_dp_128x32_0_0_0 : label is "";
+ attribute RESETMODE of ram_dp_128x32_0_0_0 : label is "SYNC";
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ ram_dp_128x32_0_0_0: PDPW16KC
+ generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2),
+ ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5),
+ ADW6=>WrAddress(6), ADW7=>scuba_vlo, ADW8=>scuba_vlo,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1),
+ ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4),
+ ADR10=>RdAddress(5), ADR11=>RdAddress(6), ADR12=>scuba_vlo,
+ ADR13=>scuba_vlo, CER=>RdClockEn, CLKR=>RdClock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
+ DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
+ DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), DO12=>Q(30),
+ DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, DO17=>open,
+ DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4),
+ DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9),
+ DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), DO31=>Q(13),
+ DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ram_dp_128x32 is
+ for Structure
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
q_1 => q_1
);
+-- ddr_generic_single_1: ddr_generic_single
+-- port map (
+-- clk_0 => ADC0_DCLK_IN,
+-- clkdiv_reset => clkdiv_reset,
+-- eclk => CLK_ADCDAT_IN,
+-- reset_0 => reset_0,
+-- sclk => DDR_DATA_CLK,
+--
+-- datain_0(0) => ADC0_DATA_A_IN,
+-- datain_0(1) => ADC0_DATA_B_IN,
+-- datain_0(2) => ADC0_DATA_C_IN,
+-- datain_0(3) => ADC0_DATA_D_IN,
+-- datain_0(4) => ADC0_FCLK_IN
+-- );
+
reset_0 <= RESET_IN or RESTART_IN;
reset_1 <= RESET_IN or RESTART_IN;
clkdiv_reset <= RESET_IN;
SPI_SPEED : unsigned(7 downto 0) := x"32"
);
port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- -- SPI connections
- SCLK_OUT : out std_logic;
- SDIO_INOUT : inout std_logic;
- CSB_OUT : out std_logic;
-
- -- Internal Interface
- INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0);
- COMMAND_ACK_OUT : out std_logic;
- SPI_DATA : out std_logic_vector(31 downto 0);
- SPI_LOCK_IN : in std_logic;
-
- -- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
-
- -- Debug Line
- DEBUG_OUT : out std_logic_vector(15 downto 0)
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- SPI connections
+ SCLK_OUT : out std_logic;
+ SDIO_INOUT : inout std_logic;
+ CSB_OUT : out std_logic;
+
+ -- Internal Interface
+ INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0);
+ COMMAND_ACK_OUT : out std_logic;
+ SPI_DATA : out std_logic_vector(31 downto 0);
+ SPI_LOCK_IN : in std_logic;
+
+ -- Slave bus
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+
+ -- Debug Line
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end entity;
signal fifo_full : std_logic;
signal fifo_write_enable : std_logic;
signal fifo_reset : std_logic;
-
- -- FIFO READ ENABLE
+
+ -- My FIFO
+ signal fifo_full_0 : std_logic;
+ signal fifo_empty_0 : std_logic;
+ signal fifo_almost_empty_0 : std_logic;
+ signal fifo_data_out_0 : std_logic_vector(43 downto 0);
+ signal fifo_read_enable_0 : std_logic;
+
+ -- Lattice FIFO
+ signal fifo_full_1 : std_logic;
+ signal fifo_empty_1 : std_logic;
+ signal fifo_almost_empty_1 : std_logic;
+ signal fifo_data_out_1 : std_logic_vector(43 downto 0);
+ signal fifo_read_enable_1 : std_logic;
+ signal fifo_read_enable_r_1 : std_logic;
+
+ -- FIFO READ
signal fifo_data_out : std_logic_vector(43 downto 0);
signal fifo_read_enable : std_logic;
signal fifo_empty : std_logic;
signal fifo_almost_empty : std_logic;
- signal fifo_data_valid_t : std_logic;
- signal fifo_data_valid : std_logic;
-
- -- FIFO READ
+ signal fifo_read_enable_t : std_logic;
+ signal fifo_read_enable_tt : std_logic;
signal nx_frame_o : std_logic_vector(31 downto 0);
signal adc_data_o : std_logic_vector(11 downto 0);
signal new_data_o : std_logic;
+
+ -- Fifo Delay
+ signal fifo_delay : std_logic_vector(7 downto 0);
+ signal fifo_delay_reset : std_logic;
-- Slave Bus
signal slv_data_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
- signal fifo_delay : std_logic_vector(7 downto 0);
- signal fifo_delay_reset : std_logic;
-
-begin
+ signal fifo_reset_r : std_logic;
+ signal debug_r : std_logic;
- -- Debug Signals
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= fifo_reset;
- DEBUG_OUT(2) <= fifo_full;
- DEBUG_OUT(3) <= fifo_write_enable;
- DEBUG_OUT(4) <= fifo_empty;
- DEBUG_OUT(5) <= fifo_almost_empty;
- DEBUG_OUT(6) <= fifo_read_enable;
- DEBUG_OUT(7) <= fifo_data_valid;
- DEBUG_OUT(8) <= new_data_o;
- DEBUG_OUT(15 downto 9) <= fifo_delay(6 downto 0);
+ -- Misc
+ signal fifo_select : std_logic;
+ signal debug_fifo : std_logic_vector(15 downto 0);
+
+begin
+ -- Debug
+ PROC_DEBUG_MULTIPLEXER: process(debug_r)
+ begin
+ if (debug_r = '0') then
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= fifo_reset;
+ DEBUG_OUT(2) <= fifo_full;
+ DEBUG_OUT(3) <= fifo_write_enable;
+ DEBUG_OUT(4) <= fifo_empty;
+ DEBUG_OUT(5) <= fifo_almost_empty;
+ DEBUG_OUT(6) <= fifo_read_enable;
+ DEBUG_OUT(7) <= fifo_read_enable_t;
+ DEBUG_OUT(8) <= fifo_read_enable_tt;
+ DEBUG_OUT(9) <= new_data_o;
+ DEBUG_OUT(12 downto 10) <= NX_FRAME_IN(11 downto 9);
+ DEBUG_OUT(15 downto 13) <= nx_frame_o(11 downto 9);
+ --DEBUG_OUT(15 downto 13) <= fifo_data_out(11 downto 9);
+ else
+ DEBUG_OUT <= debug_fifo;
+ end if;
+ end process PROC_DEBUG_MULTIPLEXER;
+
-----------------------------------------------------------------------------
-- FIFO Delay Handler
-----------------------------------------------------------------------------
-
+
fifo_44_data_delay_1: fifo_44_data_delay
port map (
Data => fifo_data_in,
Clock => CLK_IN,
WrEn => fifo_write_enable,
- RdEn => fifo_read_enable,
+ RdEn => fifo_read_enable_1,
Reset => fifo_reset,
AmEmptyThresh => fifo_delay,
- Q => fifo_data_out,
- Empty => fifo_empty,
- Full => fifo_full,
- AlmostEmpty => fifo_almost_empty
+ Q => fifo_data_out_1,
+ Empty => fifo_empty_1,
+ Full => fifo_full_1,
+ AlmostEmpty => fifo_almost_empty_1
);
- -----------------------------------------------------------------------------
- -- FIFO Handler
- -----------------------------------------------------------------------------
+ fifo_read_enable_r_1 <= fifo_read_enable_1 when rising_edge(CLK_IN);
- -- Write to FIFO
- PROC_WRITE_TO_FIFO: process(NEW_DATA_IN,
- NX_FRAME_IN,
- ADC_DATA_IN)
+ fifo_44_data_delay_my_1: fifo_44_data_delay_my
+ port map (
+ Data => fifo_data_in,
+ Clock => CLK_IN,
+ WrEn => fifo_write_enable,
+ RdEn => fifo_read_enable_0,
+ Reset => fifo_reset,
+ AmEmptyThresh => fifo_delay,
+ Q => fifo_data_out_0,
+ Empty => fifo_empty_0,
+ Full => fifo_full_0,
+ AlmostEmpty => fifo_almost_empty_0,
+ DEBUG_OUT => debug_fifo
+ );
+
+ PROC_FIFO_SELECT: process(fifo_select)
begin
- if ( NEW_DATA_IN = '1' and fifo_full = '0') then
- fifo_data_in(31 downto 0) <= NX_FRAME_IN;
- fifo_data_in(43 downto 32) <= ADC_DATA_IN;
- fifo_write_enable <= '1';
+ if (fifo_select = '0') then
+ fifo_read_enable_0 <= not fifo_almost_empty_0;
+ fifo_read_enable <= fifo_read_enable_0;
+ fifo_full <= fifo_full_0;
+ fifo_empty <= fifo_empty_0;
+ fifo_almost_empty <= fifo_almost_empty_0;
+ fifo_data_out <= fifo_data_out_0;
else
- fifo_data_in <= x"fff_ffff_ffff";
- fifo_write_enable <= '0';
+ fifo_read_enable_1 <= not fifo_almost_empty_1
+ and not fifo_read_enable_r_1;
+ fifo_read_enable <= fifo_read_enable_1;
+ fifo_full <= fifo_full_1;
+ fifo_empty <= fifo_empty_1;
+ fifo_almost_empty <= fifo_almost_empty_1;
+ fifo_data_out <= fifo_data_out_1;
+
end if;
+ end process PROC_FIFO_SELECT;
- end process PROC_WRITE_TO_FIFO;
-
- fifo_reset <= RESET_IN or fifo_delay_reset;
-
+ fifo_reset <= RESET_IN or fifo_reset_r or fifo_delay_reset;
+ fifo_data_in(31 downto 0) <= NX_FRAME_IN;
+ fifo_data_in(43 downto 32) <= ADC_DATA_IN;
+ fifo_write_enable <= NEW_DATA_IN and not fifo_full;
+
-- FIFO Read Handler
- fifo_read_enable <= not fifo_almost_empty;
-
- PROC_FIFO_READ_ENABLE: process(CLK_IN)
+ PROC_FIFO_READ: process(CLK_IN)
begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' or fifo_reset = '1') then
- fifo_data_valid_t <= '0';
- fifo_data_valid <= '0';
- else
- -- Delay read signal by one CLK
- fifo_data_valid_t <= fifo_read_enable;
- fifo_data_valid <= fifo_data_valid_t;
- end if;
- end if;
- end process PROC_FIFO_READ_ENABLE;
+ if (rising_edge(CLK_IN)) then
+ if (RESET_IN = '1' or fifo_delay_reset = '1') then
+ fifo_read_enable_t <= '0';
+ fifo_read_enable_tt <= '0';
- PROC_NX_FIFO_READ: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1' or fifo_reset = '1') then
- nx_frame_o <= (others => '0');
- adc_data_o <= (others => '0');
- new_data_o <= '0';
+ nx_frame_o <= (others => '0');
+ adc_data_o <= (others => '0');
+ new_data_o <= '0';
else
- if (fifo_data_valid = '1') then
- nx_frame_o <= fifo_data_out(31 downto 0);
- adc_data_o <= fifo_data_out(43 downto 32);
- new_data_o <= '1';
+ -- Read enable
+ fifo_read_enable_t <= fifo_read_enable;
+ fifo_read_enable_tt <= fifo_read_enable_t;
+
+ if (fifo_read_enable_tt = '1') then
+ nx_frame_o <= fifo_data_out(31 downto 0);
+ adc_data_o <= fifo_data_out(43 downto 32);
+ new_data_o <= '1';
else
- nx_frame_o <= x"ffff_ffff";
- adc_data_o <= x"fff";
- new_data_o <= '0';
+ nx_frame_o <= x"ffff_ffff";
+ adc_data_o <= x"fff";
+ new_data_o <= '0';
end if;
end if;
end if;
- end process PROC_NX_FIFO_READ;
+ end process PROC_FIFO_READ;
PROC_FIFO_DELAY: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
- fifo_delay <= x"01";
+ fifo_delay <= x"02";
fifo_delay_reset <= '0';
else
fifo_delay_reset <= '0';
if ((FIFO_DELAY_IN /= fifo_delay) and
- (unsigned(FIFO_DELAY_IN) >= 1) and
+ (unsigned(FIFO_DELAY_IN) >= 2) and
(unsigned(FIFO_DELAY_IN) <= 250)
) then
fifo_delay <= FIFO_DELAY_IN;
slv_ack_o <= '0';
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
+ fifo_reset_r <= '0';
+ debug_r <= '0';
+ fifo_select <= '0';
else
slv_data_o <= (others => '0');
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
-
+ fifo_reset_r <= '0';
+
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
slv_data_o( 7 downto 0) <= fifo_delay;
slv_data_o(31 downto 8) <= (others => '0');
slv_ack_o <= '1';
+
+ when x"0001" =>
+ slv_data_o(0) <= debug_r;
+ slv_data_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0002" =>
+ slv_data_o(0) <= fifo_select;
+ slv_data_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
when others =>
slv_unknown_addr_o <= '1';
end case;
elsif (SLV_WRITE_IN = '1') then
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
+ case SLV_ADDR_IN is
+ when x"0000" =>
+ fifo_reset_r <= '1';
+ slv_ack_o <= '1';
+
+ when x"0001" =>
+ debug_r <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
+ when x"0002" =>
+ fifo_select <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+
+ end case;
else
slv_ack_o <= '0';
end if;
-- Output Signals
- NX_TIMESTAMP_OUT <= nx_timestamp_o;
- ADC_DATA_OUT <= adc_data_o;
+ NX_TIMESTAMP_OUT <= nx_timestamp_o
+ when new_data_o = '1' else x"0000_0000";
+ ADC_DATA_OUT <= adc_data_o when new_data_o = '1' else x"000";
NEW_DATA_OUT <= new_data_o;
ADC_SCLK_LOCK_OUT <= pll_adc_sampling_clk_lock;
ERROR_OUT <= error_o;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.nxyter_components.all;
+
+entity nx_histogram is
+ generic (
+ BUS_WIDTH : integer := 7;
+ DATA_WIDTH : integer := 32
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
+ CHANNEL_DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0);
+ CHANNEL_ADD_IN : in std_logic;
+ CHANNEL_WRITE_IN : in std_logic;
+ CHANNEL_WRITE_BUSY_OUT : out std_logic;
+
+ CHANNEL_ID_READ_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
+ CHANNEL_READ_IN : in std_logic;
+ CHANNEL_DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0);
+ CHANNEL_DATA_VALID_OUT : out std_logic;
+ CHANNEL_READ_BUSY_OUT : out std_logic;
+
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+
+end entity;
+
+architecture Behavioral of nx_histogram is
+
+ -- Read Handler
+ type R_STATES is (R_IDLE,
+ R_WAIT,
+ R_READ
+ );
+ signal R_STATE, R_NEXT_STATE : R_STATES;
+
+ signal read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
+ signal read_address : std_logic_vector(BUS_WIDTH - 1 downto 0);
+ signal read_address_f : std_logic_vector(BUS_WIDTH - 1 downto 0);
+ signal read_enable : std_logic;
+ signal channel_data_o : std_logic_vector(DATA_WIDTH - 1 downto 0);
+ signal channel_data_valid_o : std_logic;
+ signal channel_read_busy_o : std_logic;
+
+ -- Write Handler
+ type W_STATES is (W_IDLE,
+ W_WRITE,
+ W_ADD
+ );
+ signal W_STATE, W_NEXT_STATE : W_STATES;
+
+ signal write_address : std_logic_vector(BUS_WIDTH - 1 downto 0);
+ signal write_address_f : std_logic_vector(BUS_WIDTH - 1 downto 0);
+ signal write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
+ signal write_data_f : std_logic_vector(DATA_WIDTH - 1 downto 0);
+ signal write_enable : std_logic;
+ signal channel_write_busy_o : std_logic;
+
+begin
+
+ -----------------------------------------------------------------------------
+
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= channel_write_busy_o;
+ DEBUG_OUT(2) <= CHANNEL_WRITE_IN;
+ DEBUG_OUT(3) <= write_enable;
+ DEBUG_OUT(4) <= channel_read_busy_o;
+ DEBUG_OUT(5) <= CHANNEL_READ_IN;
+ DEBUG_OUT(6) <= read_enable;
+ DEBUG_OUT(7) <= channel_data_valid_o;
+ DEBUG_OUT(15 downto 8) <= read_data(7 downto 0);
+
+ -----------------------------------------------------------------------------
+
+ ram_dp_128x32_1: ram_dp_128x32
+ port map (
+ WrAddress => write_address,
+ RdAddress => read_address,
+ Data => write_data,
+ WE => not RESET_IN,
+ RdClock => CLK_IN,
+ RdClockEn => read_enable,
+ Reset => RESET_IN,
+ WrClock => CLK_IN,
+ WrClockEn => write_enable,
+ Q => read_data
+ );
+
+ -----------------------------------------------------------------------------
+ -- Memory Handler
+ -----------------------------------------------------------------------------
+ PROC_MEM_HANDLER_TRANSFER: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ read_address_f <= (others => '0');
+ R_STATE <= R_IDLE;
+
+ write_address_f <= (others => '0');
+ write_data_f <= (others => '0');
+ W_STATE <= W_IDLE;
+ else
+ read_address_f <= read_address;
+ R_STATE <= R_NEXT_STATE;
+
+ write_address_f <= write_address;
+ write_data_f <= write_data;
+ W_STATE <= W_NEXT_STATE;
+ end if;
+ end if;
+ end process PROC_MEM_HANDLER_TRANSFER;
+
+ PROC_MEM_HANDLER: process(R_STATE,
+ CHANNEL_ID_READ_IN,
+ CHANNEL_READ_IN
+ )
+ begin
+ case R_STATE is
+ when R_IDLE =>
+ channel_data_o <= (others => '0');
+ channel_data_valid_o <= '0';
+
+ if (CHANNEL_READ_IN = '1') then
+ read_address <= CHANNEL_ID_READ_IN;
+ if (CHANNEL_ADD_IN = '1') then
+ read_enable <= '0';
+ channel_read_busy_o <= '0';
+ R_NEXT_STATE <= R_WAIT;
+ else
+ read_enable <= '1';
+ channel_read_busy_o <= '1';
+ R_NEXT_STATE <= R_READ;
+ end if;
+ else
+ read_address <= (others => '0');
+ read_enable <= '0';
+ channel_read_busy_o <= '0';
+ R_NEXT_STATE <= R_IDLE;
+ end if;
+
+ when R_WAIT =>
+ read_address <= read_address_f;
+ if (channel_read_busy_o = '0') then
+ channel_read_busy_o <= '1';
+ read_enable <= '1';
+ R_NEXT_STATE <= R_READ;
+ else
+ read_enable <= '0';
+ R_NEXT_STATE <= R_WAIT;
+ end if;
+
+ when R_READ =>
+ read_address <= (others => '0');
+ read_enable <= '0';
+ channel_read_busy_o <= '1';
+ channel_data_o <= read_data;
+ channel_data_valid_o <= '1';
+ R_NEXT_STATE <= R_IDLE;
+
+ end case;
+
+ case W_STATE is
+ when W_IDLE =>
+ if (CHANNEL_WRITE_IN = '1') then
+ write_address <= CHANNEL_ID_IN;
+ write_data <= CHANNEL_DATA_IN;
+ write_enable <= '1';
+ channel_write_busy_o <= '1';
+ W_NEXT_STATE <= W_WRITE;
+ elsif (CHANNEL_ADD_IN = '1') then
+ read_address <= CHANNEL_ID_IN;
+ read_enable <= '1';
+ write_address <= CHANNEL_ID_IN;
+ write_data <= CHANNEL_DATA_IN;
+ channel_read_busy_o <= '1';
+ channel_write_busy_o <= '1';
+ W_NEXT_STATE <= W_ADD;
+ else
+ write_address <= (others => '0');
+ write_data <= (others => '0');
+ write_enable <= '0';
+ channel_write_busy_o <= '0';
+ W_NEXT_STATE <= W_IDLE;
+ end if;
+
+ when W_ADD =>
+ write_address <= write_address_f;
+ write_data <=
+ std_logic_vector(unsigned(read_data) + unsigned(write_data_f));
+ write_enable <= '1';
+ channel_write_busy_o <= '1';
+ W_NEXT_STATE <= W_WRITE;
+
+ when W_WRITE =>
+ write_address <= (others => '0');
+ write_data <= (others => '0');
+ write_enable <= '0';
+ channel_write_busy_o <= '1';
+ W_NEXT_STATE <= W_IDLE;
+
+ end case;
+ end process PROC_MEM_HANDLER;
+
+ -----------------------------------------------------------------------------
+ -- Output Signals
+ -----------------------------------------------------------------------------
+
+ CHANNEL_WRITE_BUSY_OUT <= channel_write_busy_o;
+ CHANNEL_DATA_OUT <= channel_data_o;
+ CHANNEL_DATA_VALID_OUT <= channel_data_valid_o;
+ CHANNEL_READ_BUSY_OUT <= channel_read_busy_o;
+
+end Behavioral;
use work.nxyter_components.all;
entity nx_histograms is
- generic (
- BUS_WIDTH : integer := 7;
- ENABLE : boolean := true
- );
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
RESET_HISTS_IN : in std_logic;
CHANNEL_STAT_FILL_IN : in std_logic;
- CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
+ CHANNEL_ID_IN : in std_logic_vector(6 downto 0);
CHANNEL_ADC_IN : in std_logic_vector(11 downto 0);
-- Slave bus
architecture nx_histograms of nx_histograms is
- type histogram_t is array(0 to 2**BUS_WIDTH - 1) of unsigned(31 downto 0);
-
- -- PROC_CHANNEL_HIST
- signal hist_channel_stat : histogram_t;
- signal hist_channel_freq : histogram_t;
+-- Histograms
+ signal hist_write_busy : std_logic;
+ signal hist_read_busy : std_logic;
+
+ signal hist_write_id : std_logic_vector(6 downto 0);
+ signal hist_write_data : std_logic_vector(31 downto 0);
+ signal hist_write : std_logic;
+ signal hist_add : std_logic;
- signal wait_timer_init : unsigned(27 downto 0);
- signal wait_timer_done : std_logic;
+ signal hist_read_id : std_logic_vector(6 downto 0);
+ signal hist_read : std_logic;
+ signal hist_read_data : std_logic_vector(31 downto 0);
+ signal hist_read_data_valid : std_logic;
- -- PROC_CHANNEL_HIST
- signal hist_channel_adc : histogram_t;
+ signal write_ctr : unsigned(11 downto 0);
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal reset_hists_r : std_logic;
begin
-
- hist_enable_1: if ENABLE = true generate
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= RESET_IN;
- DEBUG_OUT(2) <= RESET_HISTS_IN;
- DEBUG_OUT(3) <= reset_hists_r;
- DEBUG_OUT(4) <= CHANNEL_STAT_FILL_IN;
- DEBUG_OUT(5) <= slv_ack_o;
- DEBUG_OUT(6) <= SLV_READ_IN;
- DEBUG_OUT(7) <= SLV_WRITE_IN;
- DEBUG_OUT(8) <= wait_timer_done;
- DEBUG_OUT(15 downto 9) <= CHANNEL_ID_IN;
-
- ---------------------------------------------------------------------------
-
- PROC_CHANNEL_HIST : process (CLK_IN)
- variable value : unsigned(31 downto 0);
- begin
- if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1' or reset_hists_r = '1' or RESET_HISTS_IN = '1') then
- for I in 0 to (2**BUS_WIDTH - 1) loop
- hist_channel_stat(I) <= (others => '0');
- hist_channel_freq(I) <= (others => '0');
- hist_channel_adc(I) <= (others => '0');
- end loop;
- wait_timer_init <= x"000_0001";
- else
- wait_timer_init <= (others => '0');
- if (wait_timer_done = '1') then
- for I in 0 to (2**BUS_WIDTH - 1) loop
- hist_channel_stat(I) <= (others => '0');
- hist_channel_freq(I) <=
- (hist_channel_freq(I) + hist_channel_stat(I)) / 2;
- end loop;
- wait_timer_init <= x"5f5_e100";
- else
- if (CHANNEL_STAT_FILL_IN = '1') then
- hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) <=
- hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) + 1;
-
- value := (hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN)))
- + unsigned(CHANNEL_ADC_IN)) / 2;
- hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN))) <= value;
- end if;
- end if;
+
+ ---------------------------------------------------------------------------
+
+ nx_histogram_1: nx_histogram
+ generic map (
+ BUS_WIDTH => 7,
+ DATA_WIDTH => 32
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ CHANNEL_ID_IN => hist_write_id,
+ CHANNEL_DATA_IN => hist_write_data,
+ CHANNEL_ADD_IN => hist_add,
+ CHANNEL_WRITE_IN => hist_write,
+ CHANNEL_WRITE_BUSY_OUT => hist_write_busy,
+
+ CHANNEL_ID_READ_IN => hist_read_id,
+ CHANNEL_READ_IN => hist_read,
+ CHANNEL_DATA_OUT => hist_read_data,
+ CHANNEL_DATA_VALID_OUT => hist_read_data_valid,
+ CHANNEL_READ_BUSY_OUT => hist_read_busy,
+
+ DEBUG_OUT => DEBUG_OUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- Fill Histograms
+ -----------------------------------------------------------------------------
+
+ PROC_FILL_HISTOGRAMS: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN)) then
+ if (RESET_IN = '1') then
+ hist_write_id <= CHANNEL_ID_IN;
+ hist_write_data <= (others => '0');
+ hist_write <= '0';
+ hist_add <= '0';
+ write_ctr <= (others => '0');
+ else
+ hist_write_id <= (others => '0');
+ hist_write_data <= (others => '0');
+ hist_write <= '0';
+ hist_add <= '0';
+
+ if (CHANNEL_STAT_FILL_IN = '1' and hist_write_busy = '0') then
+ hist_write_id <= CHANNEL_ID_IN;
+ hist_write_data(11 downto 0) <= x"001"; --CHANNEL_ADC_IN;
+ hist_write_data(31 downto 12) <= (others => '0');
+ hist_add <= '1';
+
+ write_ctr <= write_ctr + 1;
end if;
end if;
- end process PROC_CHANNEL_HIST;
-
- -- Timer
- nx_timer_1: nx_timer
- generic map (
- CTR_WIDTH => 28
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TIMER_START_IN => wait_timer_init,
- TIMER_DONE_OUT => wait_timer_done
- );
-
- ---------------------------------------------------------------------------
- -- TRBNet Slave Bus
- ---------------------------------------------------------------------------
-
- -- Give status info to the TRB Slow Control Channel
- PROC_HISTOGRAMS_READ: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- slv_data_out_o <= (others => '0');
- slv_no_more_data_o <= '0';
- slv_unknown_addr_o <= '0';
- slv_ack_o <= '0';
- reset_hists_r <= '0';
- else
- slv_data_out_o <= (others => '0');
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
-
- reset_hists_r <= '0';
+ end if;
+ end process PROC_FILL_HISTOGRAMS;
+
+ ---------------------------------------------------------------------------
+ -- TRBNet Slave Bus
+ ---------------------------------------------------------------------------
+
+ -- Give status info to the TRB Slow Control Channel
+ PROC_HISTOGRAMS_READ: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ slv_data_out_o <= (others => '0');
+ slv_no_more_data_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_ack_o <= '0';
+
+ hist_read_id <= (others => '0');
+ hist_read <= '0';
+ else
+ slv_data_out_o <= (others => '0');
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+
+ hist_read_id <= (others => '0');
+ hist_read <= '0';
+
+ if (hist_read_busy = '1') then
+ if (hist_read_data_valid = '1') then
+ slv_data_out_o(11 downto 0) <= hist_read_data(11 downto 0);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+ else
+ slv_ack_o <= '0';
+ end if;
- if (SLV_READ_IN = '1') then
- if (unsigned(SLV_ADDR_IN) >= x"0000" and
- unsigned(SLV_ADDR_IN) <= x"007f") then
- slv_data_out_o(31 downto 0) <= std_logic_vector(
- hist_channel_stat(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
- );
- slv_ack_o <= '1';
- elsif (unsigned(SLV_ADDR_IN) >= x"0080" and
- unsigned(SLV_ADDR_IN) <= x"00ff") then
- slv_data_out_o(31 downto 0) <= std_logic_vector(
- hist_channel_freq(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
- );
- slv_ack_o <= '1';
- elsif (unsigned(SLV_ADDR_IN) >= x"0100" and
- unsigned(SLV_ADDR_IN) <= x"017f") then
- slv_data_out_o(31 downto 0) <= std_logic_vector(
- hist_channel_adc(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
- );
- slv_ack_o <= '1';
- else
- slv_ack_o <= '0';
- end if;
-
- elsif (SLV_WRITE_IN = '1') then
-
- case SLV_ADDR_IN is
-
- when x"0000" =>
- reset_hists_r <= '1';
- slv_ack_o <= '1';
-
- when others =>
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
- end case;
+ elsif (SLV_READ_IN = '1') then
+ if (unsigned(SLV_ADDR_IN) >= x"0000" and
+ unsigned(SLV_ADDR_IN) <= x"007f") then
+ hist_read_id <= SLV_ADDR_IN(6 downto 0);
+ hist_read <= '1';
+ slv_ack_o <= '0';
else
- slv_ack_o <= '0';
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
end if;
+
+ elsif (SLV_WRITE_IN = '1') then
+
+ case SLV_ADDR_IN is
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+
+ end case;
+ else
+ slv_ack_o <= '0';
end if;
- end if;
- end process PROC_HISTOGRAMS_READ;
+ end if;
+ end if;
+ end process PROC_HISTOGRAMS_READ;
+
+ ---------------------------------------------------------------------------
+ -- Output Signals
+ ---------------------------------------------------------------------------
+ -- Slave
+ SLV_DATA_OUT <= slv_data_out_o;
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
+ SLV_ACK_OUT <= slv_ack_o;
-
- ---------------------------------------------------------------------------
- -- Output Signals
- ---------------------------------------------------------------------------
-
- -- Slave
- SLV_DATA_OUT <= slv_data_out_o;
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
- SLV_ACK_OUT <= slv_ack_o;
-
- end generate hist_enable_1;
-
- hist_disable_1: if ENABLE = false generate
- SLV_DATA_OUT <= (others => '0');
- SLV_NO_MORE_DATA_OUT <= '0';
- SLV_UNKNOWN_ADDR_OUT <= '0';
- SLV_ACK_OUT <= '0';
- end generate hist_disable_1;
-
end nx_histograms;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic;
signal sendbyte_byte : std_logic_vector(7 downto 0);
signal read_seq_ctr : std_logic;
signal i2c_data : std_logic_vector(31 downto 0);
+ signal i2c_bytes : std_logic_vector(31 downto 0);
signal i2c_busy_x : std_logic;
signal startstop_select_x : std_logic;
signal readbyte_seq_start_x : std_logic;
signal read_seq_ctr_x : std_logic;
signal i2c_data_x : std_logic_vector(31 downto 0);
+ signal i2c_bytes_x : std_logic_vector(31 downto 0);
signal sda_startstop : std_logic;
signal scl_startstop : std_logic;
signal sda_readbyte : std_logic;
signal scl_readbyte : std_logic;
- signal readbyte_byte : std_logic_vector(7 downto 0);
+ signal readbyte_byte : std_logic_vector(31 downto 0);
signal readbyte_done : std_logic;
type STATES is (S_RESET,
signal i2c_chipid : std_logic_vector(6 downto 0);
signal i2c_rw_bit : std_logic;
+ signal i2c_num_bytes : unsigned(2 downto 0);
signal i2c_registerid : std_logic_vector(7 downto 0);
signal i2c_register_data : std_logic_vector(7 downto 0);
signal i2c_register_value_read : std_logic_vector(7 downto 0);
-- Debug
DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(8 downto 1) <= i2c_data(7 downto 0);
- DEBUG_OUT(10 downto 9) <= i2c_data(31 downto 30);
+ DEBUG_OUT(3 downto 1) <= i2c_num_bytes; --i2c_data(7 downto 0);
+ DEBUG_OUT(4) <= startstop_seq_start;
+ DEBUG_OUT(5) <= readbyte_seq_start;
+ DEBUG_OUT(6) <= startstop_done;
+ DEBUG_OUT(7) <= sendbyte_done;
+ DEBUG_OUT(8) <= readbyte_done;
+
+ --DEBUG_OUT(10 downto 9) <= i2c_data(31 downto 30);
+ DEBUG_OUT(9) <= i2c_busy;
+ DEBUG_OUT(10) <= i2c_busy;
DEBUG_OUT(11) <= i2c_busy;
DEBUG_OUT(12) <= sda_o;
DEBUG_OUT(13) <= scl_o;
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
START_IN => readbyte_seq_start,
+ NUM_BYTES_IN => i2c_num_bytes,
BYTE_OUT => readbyte_byte,
SEQUENCE_DONE_OUT => readbyte_done,
SDA_OUT => sda_readbyte,
readbyte_seq_start <= '0';
sendbyte_byte <= (others => '0');
i2c_data <= (others => '0');
+ i2c_bytes <= (others => '0');
read_seq_ctr <= '0';
STATE <= S_RESET;
else
readbyte_seq_start <= readbyte_seq_start_x;
sendbyte_byte <= sendbyte_byte_x;
i2c_data <= i2c_data_x;
+ i2c_bytes <= i2c_bytes_x;
read_seq_ctr <= read_seq_ctr_x;
STATE <= NEXT_STATE;
end if;
sendbyte_byte_x <= (others => '0');
readbyte_seq_start_x <= '0';
i2c_data_x <= i2c_data;
+ i2c_bytes_x <= i2c_bytes;
read_seq_ctr_x <= read_seq_ctr;
case STATE is
when S_RESET =>
i2c_data_x <= (others => '0');
+ i2c_bytes_x <= (others => '0');
NEXT_STATE <= S_IDLE;
when S_IDLE =>
else
i2c_busy_x <= '0';
i2c_data_x <= i2c_data and x"7fff_ffff"; -- clear running
- -- bit;
+ -- bit;
read_seq_ctr_x <= '0';
NEXT_STATE <= S_IDLE;
end if;
NEXT_STATE <= S_GET_DATA_WAIT;
else
scl_master <= '0';
- i2c_data_x(7 downto 0)<= readbyte_byte;
+ i2c_data_x(7 downto 0)<= readbyte_byte(7 downto 0);
+ i2c_bytes_x <= readbyte_byte;
NEXT_STATE <= S_STOP;
end if;
-- D[31] I2C_GO 0 => don't do anything on I2C,
-- 1 => start I2C access
-- D[30] I2C_ACTION 0 => write byte, 1 => read byte
- -- D[29:24] I2C_SPEED set all to '1'
+ -- D[29:27] RESERVED set all to '0'
+ -- D[26:24] I2C_NUM_BYTES number of bytes to be read 1..4
-- D[23:16] I2C_ADDRESS address of I2C chip
-- D[15:8] I2C_CMD command byte for access
-- D[7:0] I2C_DATA data to be written
internal_command_d <= '0';
i2c_chipid <= (others => '0');
- i2c_rw_bit <= '0';
+ i2c_rw_bit <= '0';
+ i2c_num_bytes <= "001";
i2c_registerid <= (others => '0');
i2c_register_data <= (others => '0');
i2c_register_value_read <= (others => '0');
else
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
- slv_data_out_o <= (others => '0');
- i2c_start <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+ slv_data_out_o <= (others => '0');
+ i2c_start <= '0';
- internal_command_d <= internal_command;
+ internal_command_d <= internal_command;
if (i2c_busy = '0' and internal_command_d = '1') then
internal_command <= '0';
elsif (i2c_busy = '0' and INTERNAL_COMMAND_IN(31) = '1') then
-- Internal Interface Command
i2c_rw_bit <= INTERNAL_COMMAND_IN(30);
+ i2c_num_bytes <= unsigned(INTERNAL_COMMAND_IN(26 downto 24));
i2c_chipid <= INTERNAL_COMMAND_IN(22 downto 16);
i2c_registerid <= INTERNAL_COMMAND_IN(15 downto 8);
i2c_register_data <= INTERNAL_COMMAND_IN(7 downto 0);
slv_ack_o <= '0';
elsif (SLV_WRITE_IN = '1') then
- if (internal_command = '0' and
- I2C_LOCK_IN = '0' and
- i2c_busy = '0' and
- SLV_DATA_IN(31) = '1') then
- i2c_rw_bit <= SLV_DATA_IN(30);
- i2c_chipid <= SLV_DATA_IN(22 downto 16);
- i2c_registerid <= SLV_DATA_IN(15 downto 8);
- i2c_register_data <= SLV_DATA_IN(7 downto 0);
- i2c_start <= '1';
- slv_ack_o <= '1';
- else
- slv_no_more_data_o <= '1';
- slv_ack_o <= '0';
- end if;
-
+ case SLV_ADDR_IN is
+ when x"0000" =>
+ if (internal_command = '0' and
+ I2C_LOCK_IN = '0' and
+ i2c_busy = '0' and
+ SLV_DATA_IN(31) = '1') then
+ i2c_rw_bit <= SLV_DATA_IN(30);
+ if (SLV_DATA_IN(29 downto 24) = "111111") then
+ i2c_num_bytes <= "001";
+ else
+ i2c_num_bytes <= unsigned(SLV_DATA_IN(26 downto 24));
+ end if;
+ i2c_chipid <= SLV_DATA_IN(22 downto 16);
+ i2c_registerid <= SLV_DATA_IN(15 downto 8);
+ i2c_register_data <= SLV_DATA_IN(7 downto 0);
+ i2c_start <= '1';
+ slv_ack_o <= '1';
+ else
+ slv_no_more_data_o <= '1';
+ slv_ack_o <= '0';
+ end if;
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+ end case;
+
elsif (SLV_READ_IN = '1') then
- if (internal_command = '0' and
- I2C_LOCK_IN = '0' and
- i2c_busy = '0') then
- slv_data_out_o <= i2c_data_slave;
- slv_ack_o <= '1';
- else
- slv_data_out_o <= (others => '0');
- slv_no_more_data_o <= '1';
- slv_ack_o <= '0';
- end if;
-
+ case SLV_ADDR_IN is
+ when x"0000" =>
+ if (internal_command = '0' and
+ I2C_LOCK_IN = '0' and
+ i2c_busy = '0') then
+ slv_data_out_o <= i2c_data_slave;
+ slv_ack_o <= '1';
+ else
+ slv_data_out_o <= (others => '0');
+ slv_no_more_data_o <= '1';
+ slv_ack_o <= '0';
+ end if;
+
+ when x"0001" =>
+ slv_data_out_o <= i2c_bytes;
+ slv_ack_o <= '1';
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+ end case;
+
else
slv_ack_o <= '0';
end if;
RESET_IN : in std_logic;
START_IN : in std_logic;
- BYTE_OUT : out std_logic_vector(7 downto 0);
+ NUM_BYTES_IN : in unsigned(2 downto 0);
+ BYTE_OUT : out std_logic_vector(31 downto 0);
SEQUENCE_DONE_OUT : out std_logic;
-
+
-- I2C connections
SDA_OUT : out std_logic;
SCL_OUT : out std_logic;
signal i2c_start : std_logic;
signal sequence_done_o : std_logic;
- signal i2c_byte : unsigned(7 downto 0);
+ signal i2c_byte : unsigned(31 downto 0);
signal bit_ctr : unsigned(3 downto 0);
signal i2c_ack_o : std_logic;
+ signal byte_ctr : unsigned(2 downto 0);
signal wait_timer_init : unsigned(11 downto 0);
signal sequence_done_o_x : std_logic;
- signal i2c_byte_x : unsigned(7 downto 0);
+ signal i2c_byte_x : unsigned(31 downto 0);
signal bit_ctr_x : unsigned(3 downto 0);
signal i2c_ack_o_x : std_logic;
+ signal byte_ctr_x : unsigned(2 downto 0);
signal wait_timer_init_x : unsigned(11 downto 0);
type STATES is (S_IDLE,
S_UNSET_SCL2,
S_NEXT_BIT,
+ S_ACK_SET,
+ S_ACK_SET_SCL,
+ S_ACK_UNSET_SCL,
+
S_NACK_SET,
S_NACK_SET_SCL,
S_NACK_UNSET_SCL
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
sequence_done_o <= '0';
+ i2c_byte <= (others => '0');
bit_ctr <= (others => '0');
i2c_ack_o <= '0';
+ byte_ctr <= (others => '0');
wait_timer_init <= (others => '0');
STATE <= S_IDLE;
else
i2c_byte <= i2c_byte_x;
bit_ctr <= bit_ctr_x;
i2c_ack_o <= i2c_ack_o_x;
+ byte_ctr <= byte_ctr_x;
wait_timer_init <= wait_timer_init_x;
STATE <= NEXT_STATE;
end if;
i2c_byte_x <= i2c_byte;
bit_ctr_x <= bit_ctr;
i2c_ack_o_x <= i2c_ack_o;
+ byte_ctr_x <= byte_ctr;
wait_timer_init_x <= (others => '0');
case STATE is
when S_IDLE =>
if (START_IN = '1') then
- sda_o <= '0';
- scl_o <= '0';
- i2c_byte_x <= (others => '0');
- NEXT_STATE <= S_INIT;
+ sda_o <= '0';
+ scl_o <= '0';
+ i2c_byte_x <= (others => '0');
+ byte_ctr_x <= (others => '0');
+ NEXT_STATE <= S_INIT;
else
- NEXT_STATE <= S_IDLE;
+ NEXT_STATE <= S_IDLE;
end if;
-- INIT
when S_INIT =>
- sda_o <= '0';
- scl_o <= '0';
- wait_timer_init_x <= I2C_SPEED srl 1;
- NEXT_STATE <= S_INIT_WAIT;
+ sda_o <= '0';
+ scl_o <= '0';
+ wait_timer_init_x <= I2C_SPEED srl 1;
+ NEXT_STATE <= S_INIT_WAIT;
when S_INIT_WAIT =>
- sda_o <= '0';
- scl_o <= '0';
+ sda_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_INIT_WAIT;
+ NEXT_STATE <= S_INIT_WAIT;
else
- NEXT_STATE <= S_READ_BYTE;
+ NEXT_STATE <= S_READ_BYTE;
end if;
-- I2C Read byte
when S_READ_BYTE =>
- scl_o <= '0';
- bit_ctr_x <= x"7";
- wait_timer_init_x <= I2C_SPEED srl 2;
- NEXT_STATE <= S_UNSET_SCL1;
+ scl_o <= '0';
+ bit_ctr_x <= x"7";
+ byte_ctr_x <= byte_ctr + 1;
+ wait_timer_init_x <= I2C_SPEED srl 2;
+ NEXT_STATE <= S_UNSET_SCL1;
when S_UNSET_SCL1 =>
scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_UNSET_SCL1;
+ NEXT_STATE <= S_UNSET_SCL1;
else
wait_timer_init_x <= I2C_SPEED srl 2;
- NEXT_STATE <= S_SET_SCL1;
+ NEXT_STATE <= S_SET_SCL1;
end if;
when S_SET_SCL1 =>
if (wait_timer_done = '0') then
- NEXT_STATE <= S_SET_SCL1;
+ NEXT_STATE <= S_SET_SCL1;
else
- wait_timer_init_x <= I2C_SPEED srl 2;
- NEXT_STATE <= S_GET_BIT;
+ wait_timer_init_x <= I2C_SPEED srl 2;
+ NEXT_STATE <= S_GET_BIT;
end if;
when S_GET_BIT =>
- i2c_byte_x(0) <= SDA_IN;
- NEXT_STATE <= S_SET_SCL2;
+ i2c_byte_x(0) <= SDA_IN;
+ NEXT_STATE <= S_SET_SCL2;
when S_SET_SCL2 =>
if (wait_timer_done = '0') then
NEXT_STATE <= S_SET_SCL2;
else
- wait_timer_init_x <= I2C_SPEED srl 2;
- NEXT_STATE <= S_UNSET_SCL2;
+ wait_timer_init_x <= I2C_SPEED srl 2;
+ NEXT_STATE <= S_UNSET_SCL2;
end if;
when S_UNSET_SCL2 =>
- scl_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_UNSET_SCL2;
+ NEXT_STATE <= S_UNSET_SCL2;
else
- NEXT_STATE <= S_NEXT_BIT;
+ NEXT_STATE <= S_NEXT_BIT;
end if;
when S_NEXT_BIT =>
- scl_o <= '0';
+ scl_o <= '0';
if (bit_ctr > 0) then
bit_ctr_x <= bit_ctr - 1;
i2c_byte_x <= i2c_byte sll 1;
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_UNSET_SCL1;
else
- wait_timer_init_x <= I2C_SPEED srl 2;
- NEXT_STATE <= S_NACK_SET;
+ if (byte_ctr < NUM_BYTES_IN) then
+ wait_timer_init_x <= I2C_SPEED srl 2;
+ NEXT_STATE <= S_ACK_SET;
+ else
+ wait_timer_init_x <= I2C_SPEED srl 2;
+ NEXT_STATE <= S_NACK_SET;
+ end if;
+ end if;
+
+ -- I2C Send ACK (ACK) Sequence to tell client to read next byte
+ when S_ACK_SET =>
+ sda_o <= '0';
+ scl_o <= '0';
+ if (wait_timer_done = '0') then
+ NEXT_STATE <= S_ACK_SET;
+ else
+ wait_timer_init_x <= I2C_SPEED srl 1;
+ NEXT_STATE <= S_ACK_SET_SCL;
end if;
+ when S_ACK_SET_SCL =>
+ sda_o <= '0';
+ if (wait_timer_done = '0') then
+ NEXT_STATE <= S_ACK_SET_SCL;
+ else
+ wait_timer_init_x <= I2C_SPEED srl 2;
+ NEXT_STATE <= S_ACK_UNSET_SCL;
+ end if;
+
+ when S_ACK_UNSET_SCL =>
+ sda_o <= '0';
+ scl_o <= '0';
+ if (wait_timer_done = '0') then
+ NEXT_STATE <= S_ACK_UNSET_SCL;
+ else
+ NEXT_STATE <= S_READ_BYTE;
+ end if;
+
-- I2C Send NOT_ACK (NACK) Sequence to tell client to release the bus
when S_NACK_SET =>
- scl_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_NACK_SET;
+ NEXT_STATE <= S_NACK_SET;
else
wait_timer_init_x <= I2C_SPEED srl 1;
NEXT_STATE <= S_NACK_SET_SCL;
when S_NACK_SET_SCL =>
if (wait_timer_done = '0') then
- NEXT_STATE <= S_NACK_SET_SCL;
+ NEXT_STATE <= S_NACK_SET_SCL;
else
wait_timer_init_x <= I2C_SPEED srl 2;
NEXT_STATE <= S_NACK_UNSET_SCL;
end if;
when S_NACK_UNSET_SCL =>
- scl_o <= '0';
+ scl_o <= '0';
if (wait_timer_done = '0') then
- NEXT_STATE <= S_NACK_UNSET_SCL;
+ NEXT_STATE <= S_NACK_UNSET_SCL;
else
sequence_done_o_x <= '1';
NEXT_STATE <= S_IDLE;
-- Write I2C Register
when T_WRITE_I2C_REGISTER =>
- nx_i2c_command(31 downto 16) <= x"bf08";
+ nx_i2c_command(31 downto 16) <= x"8008";
nx_i2c_command(15 downto 14) <= (others => '0');
nx_i2c_command(13 downto 8) <= token_ctr;
nx_i2c_command( 7 downto 0) <= i2c_ram(index);
-- Read I2C Register
when T_READ_I2C_REGISTER =>
- nx_i2c_command(31 downto 16) <= x"ff08";
+ nx_i2c_command(31 downto 16) <= x"c108";
nx_i2c_command(15 downto 14) <= (others => '0');
nx_i2c_command(13 downto 8) <= token_ctr;
nx_i2c_command( 7 downto 0) <= (others => '0');
r_fifo_ctr <= (others => '0');
when DR_REGISTER =>
- dac_read_i2c_command(31 downto 16) <= x"ff08";
+ dac_read_i2c_command(31 downto 16) <= x"c108";
dac_read_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42
dac_read_i2c_command(7 downto 0) <= (others => '0');
if (i2c_lock_1 = '0') then
dac_ram_write_1 <= '1';
-- Write Data Back to FIFO
- dac_read_i2c_command(31 downto 16) <= x"bf08";
+ dac_read_i2c_command(31 downto 16) <= x"8008";
dac_read_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42
dac_read_i2c_command(5 downto 0) <= i2c_data(5 downto 0);
dac_read_i2c_command(7 downto 6) <= (others => '0');
w_fifo_ctr <= (others => '0');
when DW_REGISTER =>
- dac_write_i2c_command(31 downto 16) <= x"ff08";
+ dac_write_i2c_command(31 downto 16) <= x"c108";
dac_write_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42
dac_write_i2c_command(7 downto 0) <= (others => '0');
dac_write_token_clear(index) <= '1';
when DW_WRITE_BACK =>
-- Write Data Back to FIFO
- dac_write_i2c_command(31 downto 16) <= x"bf08";
+ dac_write_i2c_command(31 downto 16) <= x"8008";
dac_write_i2c_command(15 downto 8) <= x"2a"; -- DAC Reg 42
dac_write_i2c_command(7 downto 6) <= (others => '0');
dac_write_i2c_command(5 downto 0) <= dac_ram(index);
case R_STATE is
when R_TIMER_RESTART =>
- wait_timer_init <= x"1dcd_6500"; -- 5s
+ wait_timer_init <= x"5968_2f00"; -- 15s
R_STATE <= R_IDLE;
when R_IDLE =>
end if;
when R_READ_DUMMY =>
- i2c_online_command(31 downto 16) <= x"ff08";
+ i2c_online_command(31 downto 16) <= x"c108";
i2c_online_command(15 downto 8) <= x"1f"; -- Dummy register
i2c_online_command(7 downto 0) <= (others => '0');
if (i2c_lock_3 = '0') then
deltaTStore( 1 downto 0) := unsigned(TIMESTAMP_IN(1 downto 0));
-----------------------------------------------------------------------
- -- Validate incomming Data
+ -- Validate incoming Data
-----------------------------------------------------------------------
if (DATA_CLK_IN = '1') then
if (out_of_window_error_ctr_clear = '1') then
out_of_window_error_ctr <= (others => '0');
end if;
-
- -- Fill Histogram
- histogram_fill_o <= '1';
- histogram_bin_o <= CHANNEL_IN;
- histogram_adc_o <= ADC_DATA_IN;
end if;
-
+
+ -- Fill Histogram
+ histogram_fill_o <= '1';
+ histogram_bin_o <= CHANNEL_IN;
+ histogram_adc_o <= ADC_DATA_IN;
end if;
end if;
end if;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
START_IN : in std_logic;
- BYTE_OUT : out std_logic_vector(7 downto 0);
+ NUM_BYTES_IN : in unsigned(2 downto 0);
+ BYTE_OUT : out std_logic_vector(31 downto 0);
SEQUENCE_DONE_OUT : out std_logic;
SDA_OUT : out std_logic;
SCL_OUT : out std_logic;
);
end component;
+component ddr_generic_single
+ port (
+ clk_0 : in std_logic;
+ clkdiv_reset : in std_logic;
+ eclk : in std_logic;
+ reset_0 : in std_logic;
+ sclk : out std_logic;
+ datain_0 : in std_logic_vector(4 downto 0);
+ q_0 : out std_logic_vector(19 downto 0)
+ );
+end component;
+
component fifo_adc_48to48_dc
port (
Data : in std_logic_vector(47 downto 0);
);
end component;
+component ram_fifo_delay_256x44
+ port (
+ WrAddress : in std_logic_vector(7 downto 0);
+ RdAddress : in std_logic_vector(7 downto 0);
+ Data : in std_logic_vector(43 downto 0);
+ WE : in std_logic;
+ RdClock : in std_logic;
+ RdClockEn : in std_logic;
+ Reset : in std_logic;
+ WrClock : in std_logic;
+ WrClockEn : in std_logic;
+ Q : out std_logic_vector(43 downto 0)
+ );
+end component;
+
+component fifo_44_data_delay_my
+ port (
+ Data : in std_logic_vector(43 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmEmptyThresh : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(43 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
component fifo_44_data_delay
port (
Data : in std_logic_vector(43 downto 0);
-------------------------------------------------------------------------------
-component nx_histograms
+component nx_histogram
generic (
- BUS_WIDTH : integer;
- ENABLE : boolean
+ BUS_WIDTH : integer;
+ DATA_WIDTH : integer
);
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
+ CHANNEL_DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0);
+ CHANNEL_ADD_IN : in std_logic;
+ CHANNEL_WRITE_IN : in std_logic;
+ CHANNEL_WRITE_BUSY_OUT : out std_logic;
+ CHANNEL_ID_READ_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
+ CHANNEL_READ_IN : in std_logic;
+ CHANNEL_DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0);
+ CHANNEL_DATA_VALID_OUT : out std_logic;
+ CHANNEL_READ_BUSY_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0));
+end component;
+
+component nx_histograms
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
RESET_HISTS_IN : in std_logic;
CHANNEL_STAT_FILL_IN : in std_logic;
- CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
+ CHANNEL_ID_IN : in std_logic_vector(6 downto 0);
CHANNEL_ADC_IN : in std_logic_vector(11 downto 0);
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0));
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
end component;
component ram_dp_128x32
),
PORT_ADDR_MASK => ( 0 => 4, -- NX Control Handler
- 1 => 0, -- I2C master
+ 1 => 1, -- I2C master
2 => 5, -- Data Receiver
3 => 3, -- Data Buffer
4 => 0, -- SPI Master
9 => 9, -- NX Setup
10 => 9, -- NX Histograms
11 => 0, -- Debug Handler
- 12 => 1, -- Data Delay
+ 12 => 2, -- Data Delay
others => 0
),
SLV_WRITE_IN => slv_write(1),
SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
+ SLV_ADDR_IN => slv_addr(1*16+15 downto 1*16),
SLV_ACK_OUT => slv_ack(1),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
adc_spi_master_1: adc_spi_master
generic map (
- SPI_SPEED => x"32"
+ SPI_SPEED => x"c8"
)
port map (
CLK_IN => CLK_IN,
);
nx_histograms_1: nx_histograms
- generic map (
- BUS_WIDTH => 7,
- ENABLE => false
- )
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
-
+
RESET_HISTS_IN => '0',
CHANNEL_STAT_FILL_IN => trigger_validate_fill,
CHANNEL_ID_IN => trigger_validate_bin,
CHANNEL_ADC_IN => trigger_validate_adc,
-
+
SLV_READ_IN => slv_read(10),
SLV_WRITE_IN => slv_write(10),
SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32),
0x8125 : r Frame Rate (in Hz)
-- NX Data Delay
-0x8130 : r FIFO Delay, i.e. Trigger Delay (8 Bit, in 32ns).
- Calculation is based on CTS Trigger Delay
- (see NX Trigger Validate)
+0x8130 : r FIFO Delay, i.e. Trigger Delay (8 Bit, in 32ns).
+ Calculation is based on CTS Trigger Delay
+ (see NX Trigger Validate)
+0x8131 : r/w Debug Multiplexer (0=Dta Delay, 1=FIFO)
-- NX Trigger Validate
0x8400 : r/w Readout Mode: 4 Bits
--- DEBUG ------------------------------------------------------------
-- I2C Master
-0x8040 : Access to I2C Interface
+0x8040 : r/w Access to I2C Interface
Chip Ids: 0x08 : nXyter
0x29 : AD7991-1
0x50 : EEPROM
+0x8041 : r Full I2C Word
+
-- SPI Master
0x8060 : Access to SPI Interface
add_file -vhdl -lib "work" "cores/fifo_44_data_delay.vhd"
add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd"
+add_file -vhdl -lib "work" "cores/ram_fifo_delay_256x44.vhd"
add_file -vhdl -lib "work" "cores/adc_ddr_generic.vhd"
add_file -vhdl -lib "work" "cores/fifo_adc_48to48_dc.vhd"
+
add_file -vhdl -lib "work" "trb3_periph.vhd"
add_file -vhdl -lib "work" "source/nxyter_components.vhd"
add_file -vhdl -lib "work" "source/gray_encoder.vhd"
add_file -vhdl -lib "work" "source/nx_timer.vhd"
add_file -vhdl -lib "work" "source/debug_multiplexer.vhd"
+add_file -vhdl -lib "work" "source/fifo_44_data_delay_my.vhd"
add_file -vhdl -lib "work" "source/nxyter_fee_board.vhd"
add_file -vhdl -lib "work" "source/nx_data_receiver.vhd"
add_file -vhdl -lib "work" "source/nx_control.vhd"
add_file -vhdl -lib "work" "source/nx_setup.vhd"
+add_file -vhdl -lib "work" "source/nx_histogram.vhd"
add_file -vhdl -lib "work" "source/nx_histograms.vhd"
add_file -vhdl -lib "work" "source/nx_i2c_master.vhd"
add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd"
add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd"
add_file -vhdl -lib "work" "source/adc_ad9228.vhd"
+add_file -vhdl -lib "work" "source/ddr_generic_single.vhd"
add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd"
add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd"
add_file -vhdl -lib "work" "source/nx_trigger_handler.vhd"
add_file -vhdl -lib "work" "source/nx_timestamp_sim.vhd"
-# Needed by ADC9222 Entity
-#add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd"
-#add_file -vhdl -lib "work" "../base/cores/dqsinput1x4.vhd"
-#add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200.vhd"
-#add_file -vhdl -lib "work" "../base/cores/pll_adc12bit.vhd"
-#add_file -vhdl -lib "work" "../base/cores/fifo_32x512.vhd"
-#add_file -vhdl -lib "work" "../base/code/adc_ad9222.vhd"
REGIO_HARDWARE_VERSION => x"9100_6000",
REGIO_INIT_ADDRESS => x"3800",
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => 125,
+ CLOCK_FREQUENCY => 100,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 2,
jspc29 / trb3.git / commitdiff