_ilsm1=ENABLED
_ilsm2=ENABLED
_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
+_scomma0=User Defined
+_scomma1=User Defined
+_scomma2=User Defined
+_scomma3=User Defined
_comma_a0=1100000101
_comma_a1=1100000101
_comma_a2=1100000101
_comma_b1=0011111010
_comma_b2=0011111010
_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
+_comma_m0=1111111111
+_comma_m1=1111111111
+_comma_m2=1111111111
+_comma_m3=1111111111
_ctc0=DISABLED
_ctc1=DISABLED
_ctc2=DISABLED
CH1_COMMA_B "0011111010"
CH2_COMMA_B "0011111010"
CH3_COMMA_B "0011111010"
-CH0_COMMA_M "1111111100"
-CH1_COMMA_M "1111111100"
-CH2_COMMA_M "1111111100"
-CH3_COMMA_M "1111111100"
+CH0_COMMA_M "1111111111"
+CH1_COMMA_M "1111111111"
+CH2_COMMA_M "1111111111"
+CH3_COMMA_M "1111111111"
CH0_RXWA "ENABLED"
CH1_RXWA "ENABLED"
CH2_RXWA "ENABLED"
_ilsm1=ENABLED
_ilsm2=ENABLED
_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
+_scomma0=User Defined
+_scomma1=User Defined
+_scomma2=User Defined
+_scomma3=User Defined
_comma_a0=1100000101
_comma_a1=1100000101
_comma_a2=1100000101
_comma_b1=0011111010
_comma_b2=0011111010
_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
+_comma_m0=1111111111
+_comma_m1=1111111111
+_comma_m2=1111111111
+_comma_m3=1111111111
_ctc0=DISABLED
_ctc1=DISABLED
_ctc2=DISABLED
CH1_COMMA_B "0011111010"
CH2_COMMA_B "0011111010"
CH3_COMMA_B "0011111010"
-CH0_COMMA_M "1111111100"
-CH1_COMMA_M "1111111100"
-CH2_COMMA_M "1111111100"
-CH3_COMMA_M "1111111100"
+CH0_COMMA_M "1111111111"
+CH1_COMMA_M "1111111111"
+CH2_COMMA_M "1111111111"
+CH3_COMMA_M "1111111111"
CH0_RXWA "ENABLED"
CH1_RXWA "ENABLED"
CH2_RXWA "ENABLED"
RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); -- RST data byte, registered
TX_RST_IN : in std_logic;
TX_RST_WORD_IN : in std_logic_vector(7 downto 0);
+ -- phase measurement
+ PING_OUT : out std_logic_vector(3 downto 0);
+ PONG_OUT : out std_logic_vector(3 downto 0);
+ PONG_CLK_OUT : out std_logic_vector(3 downto 0);
-- sync operation
WORD_SYNC_IN : in std_logic; -- byte alignment for DLM/RST forwarding (to master port)
WORD_SYNC_OUT : out std_logic; -- byte alignment for DLM/RST forwarding (from slave port)
TX_PCS_RST_IN : in std_logic; -- TX PCS reset signal
SYNC_TX_PLL_IN : in std_logic; -- bit0 alignment for TX serializer
LINK_TX_READY_IN : in std_logic; -- from TX reset generator
- DESTROY_LINK_IN : in std_logic_vector(3 downto 0); -- hard reset for links
+ DISABLE_LINK_IN : in std_logic_vector(3 downto 0); -- disable links by status
WAP_REQUESTED_IN : in std_logic_vector(3 downto 0); -- TESTTESTTEST
--SFP Connection
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
signal lb_start_i : std_logic;
signal lb_start_qsys : std_logic;
signal lb_onoff_i : std_logic;
+
+ signal ws_tx_i : std_logic_vector(3 downto 0);
+ signal ws_rx_i : std_logic_vector(3 downto 0);
signal quad_mode : integer range 0 to 100;
link_rx_null_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
'0';
- link_tx_null_i(3) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(3)) when (IS_MODE(3) = c_IS_MASTER) else '0';
- link_tx_null_i(2) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(2)) when (IS_MODE(2) = c_IS_MASTER) else '0';
- link_tx_null_i(1) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(1)) when (IS_MODE(1) = c_IS_MASTER) else '0';
- link_tx_null_i(0) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(0)) when (IS_MODE(0) = c_IS_MASTER) else '0';
+ link_tx_null_i(3) <= LINK_TX_NULL_IN when (IS_MODE(3) = c_IS_MASTER) else '0';
+ link_tx_null_i(2) <= LINK_TX_NULL_IN when (IS_MODE(2) = c_IS_MASTER) else '0';
+ link_tx_null_i(1) <= LINK_TX_NULL_IN when (IS_MODE(1) = c_IS_MASTER) else '0';
+ link_tx_null_i(0) <= LINK_TX_NULL_IN when (IS_MODE(0) = c_IS_MASTER) else '0';
-------------------------------------------------
-- stable RX recovered clock available
lb_onoff_i <= TX_RST_WORD_IN(0);
+-------------------------------------------------
+-------------------------------------------------
+ PING_OUT(0) <= ws_tx_i(0) when (IS_MODE(0) = c_IS_MASTER) else '0';
+ PING_OUT(1) <= ws_tx_i(1) when (IS_MODE(1) = c_IS_MASTER) else '0';
+ PING_OUT(2) <= ws_tx_i(2) when (IS_MODE(2) = c_IS_MASTER) else '0';
+ PING_OUT(3) <= ws_tx_i(3) when (IS_MODE(3) = c_IS_MASTER) else '0';
+
+ PONG_OUT(0) <= ws_rx_i(0) when (IS_MODE(0) = c_IS_MASTER) else '0';
+ PONG_OUT(1) <= ws_rx_i(1) when (IS_MODE(1) = c_IS_MASTER) else '0';
+ PONG_OUT(2) <= ws_rx_i(2) when (IS_MODE(2) = c_IS_MASTER) else '0';
+ PONG_OUT(3) <= ws_rx_i(3) when (IS_MODE(3) = c_IS_MASTER) else '0';
+
+ PONG_CLK_OUT(0) <= clk_rx_full(0) when (IS_MODE(0) = c_IS_MASTER) else '0';
+ PONG_CLK_OUT(1) <= clk_rx_full(1) when (IS_MODE(1) = c_IS_MASTER) else '0';
+ PONG_CLK_OUT(2) <= clk_rx_full(2) when (IS_MODE(2) = c_IS_MASTER) else '0';
+ PONG_CLK_OUT(3) <= clk_rx_full(3) when (IS_MODE(3) = c_IS_MASTER) else '0';
+
-------------------------------------------------
-- Serdes
-------------------------------------------------
LINK_RX_READY_OUT => link_rx_ready_i(i),
LINK_RX_NULL_OUT => link_rx_null_i(i),
LINK_TX_NULL_IN => link_tx_null_i(i),
+ DISABLE_LINK_IN => DISABLE_LINK_IN(i),
-- komma operation
TX_DLM_IN => TX_DLM_IN,
TX_DLM_WORD_IN => TX_DLM_WORD_IN,
RX_DLM_WORD_OUT => RX_DLM_WORD_OUT(i*8+7 downto i*8),
RX_RST_OUT => rx_rst_i(i),
RX_RST_WORD_OUT => rx_rst_word_i(i*8+7 downto i*8),
+ --
+ WS_RX_OUT => ws_rx_i(i),
+ WS_TX_OUT => ws_tx_i(i),
-- Status and debug signals
STAT_TX_CONTROL => stat_tx_control_i(i*32+31 downto i*32),
STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32),
RX_DLM_WORD_OUT(i*8+7 downto i*8) <= (others => '0');
rx_rst_i(i) <= '0';
rx_rst_word_i(i*8+7 downto i*8) <= (others => '0');
+ ws_tx_i(i) <= '0';
+ ws_rx_i(i) <= '0';
debug_i(i*32+31 downto i*32) <= (others => '0');
end generate;
-- ports for synchronous operation
WORD_SYNC_IN : in std_logic; -- sync signal for Byte/Word Alignment
WORD_SYNC_OUT : out std_logic;
- LINK_TX_READY_IN : in std_logic; --
- LINK_RX_READY_OUT : out std_logic; --
+ LINK_TX_READY_IN : in std_logic;
+ LINK_RX_READY_OUT : out std_logic;
LINK_RX_NULL_OUT : out std_logic;
LINK_TX_NULL_IN : in std_logic;
+ DISABLE_LINK_IN : in std_logic;
-- komma handling
TX_DLM_IN : in std_logic; -- transmit one DLM komma
TX_DLM_WORD_IN : in std_logic_vector(7 downto 0);
RX_DLM_WORD_OUT : out std_logic_vector(7 downto 0);
RX_RST_OUT : out std_logic; -- one RST komma received
RX_RST_WORD_OUT : out std_logic_vector(7 downto 0);
+ --
+ WS_RX_OUT : out std_logic;
+ WS_TX_OUT : out std_logic;
-- Status and debug signals
STAT_TX_CONTROL : out std_logic_vector(31 downto 0);
STAT_RX_CONTROL : out std_logic_vector(31 downto 0);
);
DEBUG_RX_CONTROL <= debug_rx_control_i;
-
+
+ WS_RX_OUT <= word_sync_rx_i;
+
-- clocks for media interface
media_med2int_i.clk_half <= CLK_RXHALF; -- goes to clock and reset handler
media_med2int_i.clk_full <= CLK_RXI; -- goes to clock and reset handler
DEBUG_TX_CONTROL <= debug_tx_control_i;
+ WS_TX_OUT <= word_sync_tx_i;
+
-- WordSync is taken from RX in case of SP to sync the MPs in a hub.
-- In case of a root MP it is taken from MP to sync DLM sending.
-- NB: a root MP needs WORD_SYNC_IN set to '1' for operation.
media_med2int_i.stat_op(4) <= link_active_qsys; -- rx_allow
media_med2int_i.stat_op(3 downto 0) <= link_status_qsys;
- link_status <= x"0" when (link_active_i = '1') else x"7";
+ link_status <= x"0" when ((link_active_i = '1') and (DISABLE_LINK_IN = '0')) else x"7";
SYNC_MEDIA_SIGS : entity work.signal_sync
generic map(
DEBUG_OUT(2) <= link_active_qsys;
DEBUG_OUT(1) <= link_rx_ready_qsys;
DEBUG_OUT(0) <= link_tx_ready_qsys;
-
+
end architecture;
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity ddmtd is\r
+port(\r
+ AUXCLK : in std_logic; -- auxiliary clock for sampling\r
+ RESET : in std_logic;\r
+ PING_IN : in std_logic; -- TX_K signal\r
+ PONG_IN : in std_logic; -- RX_K signal\r
+ PING_OUT : out std_logic; -- stretched TX_K signal\r
+ PONG_OUT : out std_logic; -- stretched RX_K signal\r
+ START_PING_OUT : out std_logic; -- rising edge of stretched TX_K signal\r
+ START_PONG_OUT : out std_logic; -- rising edge of stretched RX_K signal \r
+ TOGGLE_OUT : out std_logic;\r
+ BEAT_OUT : out std_logic\r
+);\r
+end entity ddmtd;\r
+\r
+architecture ddmtd_arch of ddmtd is\r
+\r
+ signal ping_q : std_logic_vector(2 downto 0);\r
+ signal pong_q : std_logic_vector(2 downto 0);\r
+ signal beat_xor_x : std_logic;\r
+ signal beat_xor_q : std_logic;\r
+ signal toggle_q : std_logic;\r
+ signal start_ping_i : std_logic;\r
+ signal start_pong_i : std_logic;\r
+ \r
+\r
+ attribute HGROUP : string;\r
+-- attribute BBOX : string;\r
+ attribute HGROUP of ddmtd_arch : architecture is "ddmtd_group";\r
+-- attribute BBOX of ddmtd_arch : architecture is "2,2";\r
+ attribute syn_sharing : string;\r
+ attribute syn_sharing of ddmtd_arch : architecture is "off";\r
+ attribute syn_hier : string;\r
+ attribute syn_hier of ddmtd_arch : architecture is "hard";\r
+\r
+begin\r
+\r
+THE_SAMPLER_PROC: process( AUXCLK )\r
+begin\r
+ if( rising_edge(AUXCLK) ) then\r
+ -- shift register for metastability\r
+ ping_q <= ping_q(1 downto 0) & PING_IN;\r
+ pong_q <= pong_q(1 downto 0) & PONG_IN;\r
+ -- register stages\r
+ beat_xor_q <= beat_xor_x;\r
+ end if;\r
+end process THE_SAMPLER_PROC;\r
+\r
+-- PING deglitcher\r
+THE_PING_DEGLITCH: entity deglitch\r
+port map(\r
+ AUXCLK => AUXCLK,\r
+ RESET => RESET,\r
+ SIGNAL_IN => ping_q(1),\r
+ START_OUT => start_ping_i\r
+);\r
+\r
+-- PONG deglitcher\r
+THE_PONG_DEGLITCH: entity deglitch\r
+port map(\r
+ AUXCLK => AUXCLK,\r
+ RESET => RESET,\r
+ SIGNAL_IN => pong_q(1),\r
+ START_OUT => start_pong_i\r
+);\r
+\r
+-- XOR of both stretched signals\r
+beat_xor_x <= ping_q(1) xor pong_q(1);\r
+\r
+-- toggle bit for clock check\r
+THE_TOGGLE_PROC: process( AUXCLK, RESET )\r
+begin\r
+ if ( RESET = '1' ) then\r
+ toggle_q <= '0';\r
+ elsif( rising_edge(AUXCLK) ) then\r
+ toggle_q <= not toggle_q;\r
+ end if;\r
+end process THE_TOGGLE_PROC;\r
+\r
+PING_OUT <= ping_q(1);\r
+PONG_OUT <= pong_q(1);\r
+START_PING_OUT <= start_ping_i;\r
+START_PONG_OUT <= start_pong_i;\r
+\r
+TOGGLE_OUT <= toggle_q;\r
+BEAT_OUT <= beat_xor_q;\r
+\r
+end architecture;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity deglitch is\r
+port(\r
+ AUXCLK : in std_logic;\r
+ RESET : in std_logic;\r
+ SIGNAL_IN : in std_logic;\r
+ START_OUT : out std_logic\r
+);\r
+end entity deglitch;\r
+\r
+architecture deglitch_arch of deglitch is\r
+\r
+ signal deglitch_q : std_logic_vector(7 downto 0);\r
+ signal counter : unsigned(3 downto 0);\r
+ signal start_x : std_logic;\r
+ signal start_q : std_logic;\r
+ signal ctr_up_x : std_logic;\r
+ signal ctr_down_x : std_logic;\r
+\r
+ attribute HGROUP : string;\r
+-- attribute BBOX : string;\r
+ attribute HGROUP of deglitch_arch : architecture is "deglitch_group";\r
+-- attribute BBOX of deglitch_arch : architecture is "4,4";\r
+ attribute syn_sharing : string;\r
+ attribute syn_sharing of deglitch_arch : architecture is "off";\r
+ attribute syn_hier : string;\r
+ attribute syn_hier of deglitch_arch : architecture is "hard";\r
+\r
+ begin\r
+\r
+THE_SYNC_PROC: process( AUXCLK )\r
+begin\r
+ if( rising_edge(AUXCLK) ) then\r
+ deglitch_q <= deglitch_q(6 downto 0) & SIGNAL_IN;\r
+ start_q <= start_x;\r
+ end if;\r
+end process THE_SYNC_PROC;\r
+\r
+THE_UP_DOWN_COUNTER_PROC: process( AUXCLK, RESET )\r
+begin\r
+ if ( RESET = '1' ) then\r
+ counter <= (others => '0');\r
+ elsif( rising_edge(AUXCLK) ) then\r
+ if ( ctr_up_x = '1' ) then\r
+ counter <= counter + 1;\r
+ elsif( ctr_down_x = '1' ) then\r
+ counter <= counter - 1;\r
+ end if;\r
+ end if;\r
+end process THE_UP_DOWN_COUNTER_PROC;\r
+\r
+ctr_up_x <= '1' when ( (SIGNAL_IN = '1') and (deglitch_q(7) = '0') ) else '0';\r
+ctr_down_x <= '1' when ( (SIGNAL_IN = '0') and (deglitch_q(7) = '1') ) else '0';\r
+\r
+--start_x <= '1' when ( counter = x"4" ) else '0';\r
+start_x <= '1' when ( (counter = x"3") and (ctr_up_x = '1') ) else '0';\r
+\r
+START_OUT <= start_q;\r
+\r
+end architecture;\r
RESET : in std_logic;\r
START_IN : in std_logic; -- TX DLM\r
STOP_IN : in std_logic; -- RX DLM\r
- PING_IN : in std_logic; -- TX K\r
CLK_PING : in std_logic; -- TX CLK\r
+ PING_IN : in std_logic; -- TX K\r
PONG_IN : in std_logic; -- RX K\r
- CLK_PONG : in std_logic; -- RX CLK\r
+ SELECT_IN : in std_logic_vector(1 downto 0);\r
RESULT_OUT : out std_logic_vector(31 downto 0);\r
UPDATE_OUT : out std_logic\r
);\r
port map(\r
SAMPLE_CLK => SAMPLE_CLK,\r
PING_IN => PING_IN,\r
- CLK_PING => CLK_PING,\r
PONG_IN => PONG_IN,\r
- CLK_PONG => CLK_PONG,\r
+ SELECT_IN => SELECT_IN,\r
PHASE_OUT => phase\r
);\r
\r
port(\r
SAMPLE_CLK : in std_logic;\r
PING_IN : in std_logic; -- TX K\r
- CLK_PING : in std_logic; -- TX CLK\r
PONG_IN : in std_logic; -- RX K\r
- CLK_PONG : in std_logic; -- RX CLK\r
+ SELECT_IN : in std_logic_vector(1 downto 0);\r
PHASE_OUT : out std_logic\r
);\r
end entity phaser_core;\r
-- state machine signals\r
\r
-- Signals\r
- signal ping_i : std_logic;\r
- signal pong_i : std_logic;\r
- signal ping_i_q : std_logic;\r
- signal pong_i_q : std_logic;\r
+ signal ch_up_x : std_logic;\r
+ signal ch_up_q : std_logic;\r
+ signal ch_dn_x : std_logic;\r
+ signal ch_dn_q : std_logic;\r
signal phase_x : std_logic;\r
-\r
+ signal phase : std_logic;\r
+ \r
attribute HGROUP : string;\r
attribute BBOX : string;\r
attribute HGROUP of phaser_core_arch : architecture is "phaser_core_group";\r
- attribute BBOX of phaser_core_arch : architecture is "1,2";\r
+ attribute BBOX of phaser_core_arch : architecture is "1,1";\r
attribute syn_sharing : string;\r
attribute syn_sharing of phaser_core_arch : architecture is "off";\r
attribute syn_hier : string;\r
-- we want all logic in here in one PFU (defined timing)!\r
---------------------------------------------------------------------------\r
\r
--- PINGFF : FD1S3AX port map ( CK => CLK_PING, D => PING_IN, Q => ping_i );\r
--- PONGFF : FD1S3AX port map ( CK => CLK_PONG, D => PONG_IN, Q => pong_i );\r
---\r
--- PINQFF : FD1S3AX port map ( CK => SAMPLE_CLK, D => ping_i, Q => ping_i_q );\r
--- PONQFF : FD1S3AX port map ( CK => SAMPLE_CLK, D => pong_i, Q => pong_i_q );\r
---\r
--- PHXLUT: LUT4 generic map ( INIT => b"0000_0000_0000_0110")\r
--- port map ( A => ping_i_q, B => pong_i_q, C => '0', D => '0', Z => phase_x );\r
- \r
- -- slice 0\r
- ping_i <= PING_IN when rising_edge(CLK_PING); -- FF\r
- -- slice 1\r
- pong_i <= PONG_IN when rising_edge(CLK_PONG); -- FF\r
- -- slice 2\r
- ping_i_q <= ping_i when rising_edge(SAMPLE_CLK); -- FF\r
- pong_i_q <= pong_i when rising_edge(SAMPLE_CLK); -- FF\r
- -- slice 3\r
- phase_x <= ping_i_q xor pong_i_q; -- LUT4\r
+ -- LUT4\r
+ ch_up_x <= PING_IN when SELECT_IN = b"00" else\r
+ PONG_IN when SELECT_IN = b"01" else\r
+ PING_IN when SELECT_IN = b"10" else\r
+ PONG_IN;\r
\r
- PHASE_OUT <= phase_x;\r
+ -- LUT4\r
+ ch_dn_x <= PING_IN when SELECT_IN = b"00" else\r
+ PONG_IN when SELECT_IN = b"01" else\r
+ PONG_IN when SELECT_IN = b"10" else\r
+ PING_IN;\r
+\r
+ -- FF\r
+ ch_up_q <= ch_up_x when rising_edge(SAMPLE_CLK);\r
+ \r
+ -- FF\r
+ ch_dn_q <= ch_dn_x when rising_edge(SAMPLE_CLK);\r
+ \r
+ -- LUT4\r
+ phase_x <= ch_up_q xor ch_dn_q;\r
+ \r
+ -- FF\r
+ phase <= phase_x when rising_edge(SAMPLE_CLK);\r
+ \r
+ PHASE_OUT <= phase;\r
\r
end architecture;\r
jspc29 / trbnet.git / commitdiff