]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
̈́
authorhadeshyp <hadeshyp>
Tue, 12 Feb 2013 14:29:12 +0000 (14:29 +0000)
committerhadeshyp <hadeshyp>
Tue, 12 Feb 2013 14:29:12 +0000 (14:29 +0000)
cts/project2/cts.ldf [new file with mode: 0755]

diff --git a/cts/project2/cts.ldf b/cts/project2/cts.ldf
new file mode 100755 (executable)
index 0000000..7c447c2
--- /dev/null
@@ -0,0 +1,506 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="2.0" title="cts" device="LFE3-150EA-8FN1156C" default_implementation="cts">
+    <Options/>
+    <Implementation title="cts" dir="cts" description="cts" default_strategy="Strategy1">
+        <Options top="trb3_central"/>
+        <Source name="../version.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
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+        <Source name="../../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/code/mbs_vulom_recv.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
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+        </Source>
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+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_type_validator.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd" type="VHDL" type_short="VHDL">
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+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd" type="VHDL" type_short="VHDL">
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+        </Source>
+        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd" type="VHDL" type_short="VHDL">
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