--- /dev/null
+//**************************************************************************\r
+// *************************************************************************\r
+// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
+// * PROPRIETARY NOTE *\r
+// * *\r
+// * This software contains information confidential and proprietary *\r
+// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
+// * in whole or in part, or transferred to other documents, or disclosed *\r
+// * to third parties, or used for any purpose other than that for which *\r
+// * it was obtained, without the prior written consent of Lattice *\r
+// * Semiconductor Corporation. All rights reserved. *\r
+// * *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`timescale 1ns/100ps\r
+\r
+module rate_resolution (\r
+ gbe_mode,\r
+ sgmii_mode,\r
+ an_enable,\r
+ advertised_rate,\r
+ link_partner_rate,\r
+ non_an_rate,\r
+\r
+ operational_rate\r
+);\r
+\r
+input gbe_mode;\r
+input sgmii_mode;\r
+input an_enable;\r
+input [1:0] advertised_rate; // 00=10Mbps 01=100Mbps 10=1Gbps\r
+input [1:0] link_partner_rate;\r
+input [1:0] non_an_rate;\r
+\r
+output [1:0] operational_rate;\r
+reg [1:0] operational_rate;\r
+\r
+\r
+\r
+always @(gbe_mode or sgmii_mode or an_enable or advertised_rate or link_partner_rate or non_an_rate) begin\r
+ if (gbe_mode) begin\r
+ operational_rate <= 2'b10; // 1Gbps\r
+ end\r
+ else begin\r
+ if (an_enable) begin\r
+ if (sgmii_mode) begin\r
+ // PHY Mode\r
+ operational_rate <= advertised_rate;\r
+ end\r
+ else begin\r
+ // MAC Mode\r
+ operational_rate <= link_partner_rate;\r
+ end\r
+ end\r
+ else begin\r
+ // If auto-negotiation disabled, then this becomes active rate\r
+ operational_rate <= non_an_rate;\r
+ end\r
+ end\r
+end\r
+\r
+\r
+\r
+endmodule\r
+\r
--- /dev/null
+//**************************************************************************\r
+// *************************************************************************\r
+// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
+// * PROPRIETARY NOTE *\r
+// * *\r
+// * This software contains information confidential and proprietary *\r
+// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
+// * in whole or in part, or transferred to other documents, or disclosed *\r
+// * to third parties, or used for any purpose other than that for which *\r
+// * it was obtained, without the prior written consent of Lattice *\r
+// * Semiconductor Corporation. All rights reserved. *\r
+// * *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`timescale 1ns/100ps\r
+\r
+module register_interface_hb (\r
+\r
+ // Control Signals\r
+ rst_n,\r
+ hclk,\r
+ gbe_mode,\r
+ sgmii_mode,\r
+\r
+ // Host Bus\r
+ hcs_n,\r
+ hwrite_n,\r
+ haddr,\r
+ hdatain,\r
+\r
+ hdataout,\r
+ hready_n,\r
+\r
+ // Register Inputs\r
+ mr_an_enable,\r
+ mr_restart_an,\r
+ mr_adv_ability,\r
+\r
+ // Register Outputs\r
+ mr_main_reset,\r
+ mr_an_complete,\r
+ mr_page_rx,\r
+ mr_lp_adv_ability\r
+ );\r
+\r
+\r
+input rst_n ;\r
+input hclk ;\r
+input gbe_mode ;\r
+input sgmii_mode ;\r
+\r
+input hcs_n;\r
+input hwrite_n;\r
+input [3:0] haddr;\r
+input [7:0] hdatain;\r
+\r
+output [7:0] hdataout;\r
+output hready_n;\r
+\r
+input mr_an_complete;\r
+input mr_page_rx;\r
+input [15:0] mr_lp_adv_ability;\r
+\r
+output mr_an_enable;\r
+output mr_restart_an;\r
+output [15:0] mr_adv_ability;\r
+output mr_main_reset;\r
+\r
+regs_hb regs (\r
+ .rst_n (rst_n),\r
+ .hclk (hclk),\r
+\r
+ .gbe_mode (gbe_mode),\r
+ .sgmii_mode (sgmii_mode),\r
+\r
+ .hcs_n (hcs_n),\r
+ .hwrite_n (hwrite_n),\r
+ .haddr (haddr),\r
+ .hdatain (hdatain),\r
+\r
+ .hdataout (hdataout),\r
+ .hready_n (hready_n),\r
+\r
+ .mr_an_complete (mr_an_complete),\r
+ .mr_page_rx (mr_page_rx),\r
+ .mr_lp_adv_ability (mr_lp_adv_ability),\r
+\r
+ .mr_main_reset (mr_main_reset),\r
+ .mr_an_enable (mr_an_enable),\r
+ .mr_restart_an (mr_restart_an),\r
+ .mr_adv_ability (mr_adv_ability)\r
+);\r
+endmodule\r
+\r
+\r
+\r
+\r
+\r
+\r
+module register_0_hb (\r
+ rst_n,\r
+ clk, \r
+ cs_0,\r
+ cs_1,\r
+ write,\r
+ ready,\r
+ data_in,\r
+\r
+ data_out,\r
+ mr_main_reset,\r
+ mr_an_enable,\r
+ mr_restart_an\r
+);\r
+\r
+input rst_n;\r
+input clk;\r
+input cs_0;\r
+input cs_1;\r
+input write;\r
+input ready;\r
+input [15:0] data_in;\r
+\r
+output [15:0] data_out;\r
+output mr_main_reset; // bit D15 // R/W // Self Clearing\r
+output mr_an_enable; // bit D12 // R/W\r
+output mr_restart_an; // bit D09 // R/W // Self Clearing\r
+\r
+reg [15:0] data_out;\r
+reg mr_main_reset;\r
+reg mr_an_enable;\r
+reg mr_restart_an;\r
+reg m_m_r;\r
+reg m_r_a;\r
+\r
+\r
+// Write Operations\r
+\r
+ // Low Portion of Register[D7:D0] has no\r
+ // implemented bits. Therefore, no write\r
+ // operations here.\r
+\r
+ // High Portion of Register[D15:D8]\r
+ always @(posedge clk or negedge rst_n) begin\r
+ if (rst_n == 1'b0) begin\r
+ mr_main_reset <= 0; // default value\r
+ mr_an_enable <= 1; // default value\r
+ mr_restart_an <= 0; // default value\r
+ m_m_r <= 0;\r
+ m_r_a <= 0;\r
+ end\r
+ else begin\r
+\r
+ // Do the Writes\r
+ if (cs_1 && ready && write) begin\r
+ mr_main_reset <= data_in[15];\r
+ mr_an_enable <= data_in[12];\r
+ mr_restart_an <= data_in[9];\r
+ end\r
+\r
+ // Delay the Self Clearing Register Bits\r
+ m_m_r <= mr_main_reset;\r
+ m_r_a <= mr_restart_an;\r
+\r
+ // Do the Self Clearing\r
+ if (m_m_r)\r
+ mr_main_reset <= 0;\r
+\r
+ if (m_r_a)\r
+ mr_restart_an <= 0;\r
+ end\r
+ end\r
+\r
+\r
+\r
+\r
+\r
+// Read Operations\r
+ always @(*) begin\r
+ data_out[7:0] = 8'b00000000;\r
+ data_out[15] = mr_main_reset;\r
+ data_out[14] = 0;\r
+ data_out[13] = 0;\r
+ data_out[12] = mr_an_enable;\r
+ data_out[11] = 0;\r
+ data_out[10] = 0;\r
+ data_out[9] = mr_restart_an;\r
+ data_out[8] = 0;\r
+ end\r
+endmodule\r
+\r
+module register_1_hb (\r
+ rst_n,\r
+ cs_0,\r
+ cs_1,\r
+ mr_an_complete,\r
+\r
+ data_out\r
+);\r
+\r
+input rst_n;\r
+input cs_0;\r
+input cs_1;\r
+input mr_an_complete; // bit D5 // Read-Only\r
+\r
+output [15:0] data_out;\r
+\r
+reg [15:0] data_out;\r
+\r
+\r
+// Read Operations\r
+\r
+ always @(*) begin\r
+ data_out[7] <= 0;\r
+ data_out[6] <= 0;\r
+ data_out[5] <= mr_an_complete;\r
+ data_out[4] <= 0;\r
+ data_out[3] <= 0;\r
+ data_out[2] <= 0;\r
+ data_out[1] <= 0;\r
+ data_out[0] <= 0;\r
+ data_out[15:8] <= 8'b00000000;\r
+ end\r
+endmodule\r
+\r
+module register_4_hb (\r
+ rst_n,\r
+ clk, \r
+ gbe_mode,\r
+ sgmii_mode,\r
+ cs_0,\r
+ cs_1,\r
+ write,\r
+ ready,\r
+ data_in,\r
+\r
+ data_out,\r
+ mr_adv_ability\r
+);\r
+\r
+parameter [15:0] initval_gbe = 16'h0020;\r
+parameter [15:0] initval_phy = 16'hd801;\r
+parameter [15:0] initval_mac = 16'h4001;\r
+\r
+input rst_n;\r
+input clk;\r
+input gbe_mode;\r
+input sgmii_mode;\r
+input cs_0;\r
+input cs_1;\r
+input write;\r
+input ready;\r
+input [15:0] data_in;\r
+\r
+output [15:0] data_out;\r
+output [15:0] mr_adv_ability; // When sgmii_mode == 1 == PHY\r
+ // all bits D15-D0 are R/W,\r
+ ///////////////////////////////////\r
+ // D15 = Link Status (1=up, 0=down)\r
+ // D14 = Can be written but has no effect\r
+ // on autonegotiation. Instead\r
+ // the autonegotiation state machine\r
+ // controls the utilization of this bit.\r
+ // D12 = Duplex Mode (1=full, 0=half)\r
+ // D11:10 = Speed (11=reserved)\r
+ // (10=1000Mbps)\r
+ // (01=100 Mbps)\r
+ // (00=10 Mbps)\r
+ // D0 = 1\r
+ // all other bits = 0\r
+ ///////////////////////////////////\r
+ //When sgmii_mode == 0 = MAC\r
+ // all bits D15-D0 are R/W,\r
+ // D14 = Can be written but has no effect\r
+ // on autonegotiation. Instead\r
+ // the autonegotiation state machine\r
+ // controls the utilization of this bit.\r
+ // D0 = 1\r
+ // all other bits = 0\r
+ ///////////////////////////////////\r
+\r
+\r
+reg [15:0] data_out;\r
+reg [15:0] mr_adv_ability;\r
+reg rst_d1;\r
+reg rst_d2;\r
+reg rst_d3;\r
+reg rst_d4;\r
+reg rst_d5;\r
+reg rst_d6;\r
+reg rst_d7;\r
+reg rst_d8;\r
+reg sync_reset;\r
+reg sgmii_mode_d1;\r
+reg sgmii_mode_d2;\r
+reg sgmii_mode_d3;\r
+reg sgmii_mode_d4;\r
+reg sgmii_mode_change;\r
+reg gbe_mode_d1;\r
+reg gbe_mode_d2;\r
+reg gbe_mode_d3;\r
+reg gbe_mode_d4;\r
+reg gbe_mode_change;\r
+\r
+// generate a synchronous reset signal\r
+// note: this method is used so that\r
+// an initval can be applied during\r
+// device run-time, instead of at compile time\r
+always @(posedge clk or negedge rst_n) begin\r
+ if (rst_n == 1'b0) begin\r
+ rst_d1 <= 0;\r
+ rst_d2 <= 0;\r
+ rst_d3 <= 0;\r
+ rst_d4 <= 0;\r
+ rst_d5 <= 0;\r
+ rst_d6 <= 0;\r
+ rst_d7 <= 0;\r
+ rst_d8 <= 0;\r
+ sync_reset <= 0;\r
+ end\r
+ else begin\r
+ rst_d1 <= 1;\r
+ rst_d2 <= rst_d1;\r
+ rst_d3 <= rst_d2;\r
+ rst_d4 <= rst_d3;\r
+ rst_d5 <= rst_d4;\r
+ rst_d6 <= rst_d5;\r
+ rst_d7 <= rst_d6;\r
+ rst_d8 <= rst_d7;\r
+\r
+ // asserts on rising edge of rst_d8\r
+ sync_reset <= !rst_d8 & rst_d7; \r
+ end\r
+end\r
+\r
+\r
+// Detect change in sgmii_mode\r
+always @(posedge clk or negedge rst_n) begin\r
+ if (rst_n == 1'b0) begin\r
+ sgmii_mode_d1 <= 0;\r
+ sgmii_mode_d2 <= 0;\r
+ sgmii_mode_d3 <= 0;\r
+ sgmii_mode_d4 <= 0;\r
+ sgmii_mode_change <= 0;\r
+ end\r
+ else begin\r
+\r
+ // deboggle\r
+ sgmii_mode_d1 <= sgmii_mode;\r
+ sgmii_mode_d2 <= sgmii_mode_d1;\r
+\r
+ // delay \r
+ sgmii_mode_d3 <= sgmii_mode_d2;\r
+ sgmii_mode_d4 <= sgmii_mode_d3;\r
+\r
+ // detect change\r
+ if (sgmii_mode_d3 != sgmii_mode_d4)\r
+ sgmii_mode_change <= 1;\r
+ else\r
+ sgmii_mode_change <= 0;\r
+ end\r
+end\r
+\r
+\r
+// Detect change in gbe_mode\r
+always @(posedge clk or negedge rst_n) begin\r
+ if (rst_n == 1'b0) begin\r
+ gbe_mode_d1 <= 0;\r
+ gbe_mode_d2 <= 0;\r
+ gbe_mode_d3 <= 0;\r
+ gbe_mode_d4 <= 0;\r
+ gbe_mode_change <= 0;\r
+ end\r
+ else begin\r
+\r
+ // deboggle\r
+ gbe_mode_d1 <= gbe_mode;\r
+ gbe_mode_d2 <= gbe_mode_d1;\r
+\r
+ // delay \r
+ gbe_mode_d3 <= gbe_mode_d2;\r
+ gbe_mode_d4 <= gbe_mode_d3;\r
+\r
+ // detect change\r
+ if (gbe_mode_d3 != gbe_mode_d4)\r
+ gbe_mode_change <= 1;\r
+ else\r
+ gbe_mode_change <= 0;\r
+ end\r
+end\r
+\r
+\r
+// Write Operations\r
+ // Low Portion of Register[D7:D0]\r
+ always @(posedge clk or negedge rst_n) begin\r
+ if (rst_n == 1'b0) begin\r
+ mr_adv_ability[7:0] <= 8'h01;\r
+ end\r
+ else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin\r
+ if (gbe_mode_d4)\r
+ mr_adv_ability[7:0] <= initval_gbe[7:0];\r
+ else if (sgmii_mode)\r
+ mr_adv_ability[7:0] <= initval_phy[7:0];\r
+ else\r
+ mr_adv_ability[7:0] <= initval_mac[7:0];\r
+ end\r
+ else begin\r
+ if (cs_0 && ready && write && (sgmii_mode || gbe_mode)) begin\r
+ mr_adv_ability[7:0] <= data_in[7:0];\r
+ end\r
+ end\r
+ end\r
+\r
+\r
+ // High Portion of Register[D15:D8]\r
+ always @(posedge clk or negedge rst_n) begin\r
+ if (rst_n == 1'b0) begin\r
+ mr_adv_ability[15:8] <= 8'h40; // default\r
+ end\r
+ else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin\r
+ if (gbe_mode_d4)\r
+ mr_adv_ability[15:8] <= initval_gbe[15:8];\r
+ else if (sgmii_mode)\r
+ mr_adv_ability[15:8] <= initval_phy[15:8];\r
+ else\r
+ mr_adv_ability[15:8] <= initval_mac[15:8];\r
+ end\r
+ else begin\r
+ if (cs_1 && ready && write && (sgmii_mode || gbe_mode)) begin\r
+ mr_adv_ability[15:8] <= data_in[15:8];\r
+ end\r
+ end\r
+ end\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+// Read Operations\r
+\r
+ always @(*) begin\r
+ data_out[7:0] <= mr_adv_ability[7:0];\r
+ data_out[15:8] <= mr_adv_ability[15:8];\r
+ end\r
+\r
+endmodule\r
+\r
+\r
+\r
+\r
+\r
+\r
+module register_5_hb (\r
+ rst_n,\r
+ mr_lp_adv_ability,\r
+ cs_0,\r
+ cs_1,\r
+ ready,\r
+\r
+ data_out\r
+);\r
+\r
+input rst_n;\r
+input cs_0;\r
+input cs_1;\r
+input ready;\r
+input [15:0] mr_lp_adv_ability;\r
+ // This entire register is read-only\r
+ ///////////////////////////////////\r
+ // When sgmii_mode == 0 == MAC\r
+ ///////////////////////////////////\r
+ // D15 = PHY Link Status (1=up, 0=down)\r
+ // D14 = PHY Autonegotiation Handshake\r
+ // D12 = PHY Duplex Mode (1=full, 0=half)\r
+ // D11:10 = PHY Speed (11=reserved)\r
+ // (10=1000Mbps)\r
+ // (01=100 Mbps)\r
+ // (00=10 Mbps)\r
+ // D0 = 1\r
+ // all other bits = 0\r
+ ///////////////////////////////////\r
+ //When sgmii_mode == 1 = PHY\r
+ // D14 = MAC Autonegotiation Handshake\r
+ // D0 = 1\r
+ // all other bits = 0\r
+ ///////////////////////////////////\r
+output [15:0] data_out;\r
+\r
+reg [15:0] data_out;\r
+\r
+// Read Operations\r
+\r
+ always @(*) begin\r
+ data_out[7:0] <= mr_lp_adv_ability[7:0];\r
+ data_out[15:8] <= mr_lp_adv_ability[15:8];\r
+ end\r
+endmodule\r
+\r
+module register_6_hb (\r
+ rst_n,\r
+ clk,\r
+ mr_page_rx,\r
+ cs_0,\r
+ cs_1,\r
+ write,\r
+ ready,\r
+\r
+ data_out\r
+);\r
+\r
+input rst_n;\r
+input clk;\r
+input cs_0;\r
+input cs_1;\r
+input write;\r
+input ready;\r
+input mr_page_rx;\r
+output [15:0] data_out;\r
+\r
+reg [15:0] data_out;\r
+reg mr_page_rx_latched;\r
+reg clear_on_read;\r
+reg read_detect;\r
+reg rd_d1;\r
+reg rd_d2;\r
+\r
+// generate clear-on-read signal\r
+ always @(posedge clk or negedge rst_n) begin\r
+ if (rst_n == 1'b0) begin\r
+ clear_on_read <= 0;\r
+ read_detect <= 0;\r
+ rd_d1 <= 0;\r
+ rd_d2 <= 0;\r
+ end\r
+ else begin\r
+ if (!write && ready && cs_0)\r
+ read_detect <= 1;\r
+ else \r
+ read_detect <= 0;\r
+\r
+ rd_d1 <= read_detect;\r
+ rd_d2 <= rd_d1;\r
+\r
+ // assert on falling edge of rd_d2\r
+ clear_on_read <= !rd_d1 & rd_d2;\r
+ end\r
+ end\r
+\r
+\r
+// Latch and Clear\r
+ always @(posedge clk or negedge rst_n) begin\r
+ if (rst_n == 1'b0) begin\r
+ mr_page_rx_latched <= 0;\r
+ end\r
+ else begin\r
+ if (clear_on_read)\r
+ mr_page_rx_latched <= 0;\r
+ else if (mr_page_rx)\r
+ mr_page_rx_latched <= 1;\r
+ end\r
+ end\r
+\r
+\r
+// Read Operations\r
+\r
+ always @(*) begin\r
+ data_out[15:2] <= 14'd0;\r
+ data_out[1] <= mr_page_rx_latched;\r
+ data_out[0] <= 0;\r
+ end\r
+endmodule\r
+\r
+\r
+module regs_hb (\r
+ rst_n,\r
+ hclk,\r
+ gbe_mode,\r
+ sgmii_mode,\r
+ hcs_n,\r
+ hwrite_n,\r
+ haddr,\r
+ hdatain,\r
+\r
+ hdataout,\r
+ hready_n,\r
+\r
+ mr_an_complete,\r
+ mr_page_rx,\r
+ mr_lp_adv_ability,\r
+\r
+ mr_main_reset,\r
+ mr_an_enable,\r
+ mr_restart_an,\r
+ mr_adv_ability\r
+);\r
+\r
+input rst_n;\r
+input hclk;\r
+input gbe_mode;\r
+input sgmii_mode;\r
+input hcs_n;\r
+input hwrite_n;\r
+input [3:0] haddr;\r
+input [7:0] hdatain;\r
+\r
+output [7:0] hdataout;\r
+output hready_n;\r
+\r
+input mr_an_complete;\r
+input mr_page_rx;\r
+input [15:0] mr_lp_adv_ability;\r
+\r
+output mr_main_reset;\r
+output mr_an_enable;\r
+output mr_restart_an;\r
+output [15:0] mr_adv_ability;\r
+\r
+///////////////////////////////////\r
+\r
+\r
+\r
+reg [7:0] hdataout;\r
+reg hr;\r
+reg hready_n;\r
+\r
+reg hcs_n_delayed;\r
+\r
+wire reg0_cs_0;\r
+wire reg0_cs_1;\r
+\r
+wire reg1_cs_0;\r
+wire reg1_cs_1;\r
+\r
+wire reg4_cs_0;\r
+wire reg4_cs_1;\r
+\r
+wire reg5_cs_0;\r
+wire reg5_cs_1;\r
+\r
+wire reg6_cs_0;\r
+wire reg6_cs_1;\r
+\r
+wire [15:0] data_out_reg_0;\r
+wire [15:0] data_out_reg_1;\r
+wire [15:0] data_out_reg_4;\r
+wire [15:0] data_out_reg_5;\r
+wire [15:0] data_out_reg_6;\r
+\r
+\r
+\r
+register_addr_decoder ad_dec (\r
+ .rst_n(rst_n),\r
+ .addr(haddr),\r
+ .cs_in(~hcs_n),\r
+\r
+ .reg0_cs_0 (reg0_cs_0),\r
+ .reg0_cs_1 (reg0_cs_1),\r
+ .reg1_cs_0 (reg1_cs_0),\r
+ .reg1_cs_1 (reg1_cs_1),\r
+ .reg4_cs_0 (reg4_cs_0),\r
+ .reg4_cs_1 (reg4_cs_1),\r
+ .reg5_cs_0 (reg5_cs_0),\r
+ .reg5_cs_1 (reg5_cs_1),\r
+ .reg6_cs_0 (reg6_cs_0),\r
+ .reg6_cs_1 (reg6_cs_1)\r
+);\r
+\r
+\r
+register_0_hb register_0 (\r
+ .rst_n (rst_n),\r
+ .clk (hclk), \r
+ .cs_0 (reg0_cs_0),\r
+ .cs_1 (reg0_cs_1),\r
+ .write (~hwrite_n),\r
+ .ready (1'b1),\r
+ .data_in ({hdatain, hdatain}),\r
+\r
+ .data_out (data_out_reg_0),\r
+ .mr_main_reset (mr_main_reset),\r
+ .mr_an_enable (mr_an_enable),\r
+ .mr_restart_an (mr_restart_an)\r
+);\r
+\r
+\r
+register_1_hb register_1 (\r
+ .rst_n (rst_n),\r
+ .cs_0 (reg1_cs_0),\r
+ .cs_1 (reg1_cs_1),\r
+ .mr_an_complete (mr_an_complete),\r
+\r
+ .data_out (data_out_reg_1)\r
+);\r
+\r
+\r
+register_4_hb register_4 (\r
+ .rst_n (rst_n),\r
+ .clk (hclk), \r
+ .gbe_mode (gbe_mode),\r
+ .sgmii_mode (sgmii_mode),\r
+ .cs_0 (reg4_cs_0),\r
+ .cs_1 (reg4_cs_1),\r
+ .write (~hwrite_n),\r
+ .ready (1'b1),\r
+ .data_in ({hdatain, hdatain}),\r
+\r
+ .data_out (data_out_reg_4),\r
+ .mr_adv_ability (mr_adv_ability)\r
+);\r
+\r
+\r
+register_5_hb register_5 (\r
+ .rst_n (rst_n),\r
+ .mr_lp_adv_ability (mr_lp_adv_ability),\r
+ .cs_0 (reg5_cs_0),\r
+ .cs_1 (reg5_cs_1),\r
+ .ready (1'b1),\r
+\r
+ .data_out (data_out_reg_5)\r
+);\r
+\r
+\r
+register_6_hb register_6 (\r
+ .rst_n (rst_n),\r
+ .clk (hclk), \r
+ .mr_page_rx (mr_page_rx),\r
+ .cs_0 (reg6_cs_0),\r
+ .cs_1 (reg6_cs_1),\r
+ .write (~hwrite_n),\r
+ .ready (1'b1),\r
+\r
+ .data_out (data_out_reg_6)\r
+);\r
+\r
+\r
+\r
+// generate an ack\r
+always @(posedge hclk or negedge rst_n) begin\r
+ if (rst_n == 1'b0) begin\r
+ hcs_n_delayed <= 1'b1;\r
+ hr <= 1'b1;\r
+ hready_n <= 1'b1;\r
+ end\r
+ else begin\r
+ hcs_n_delayed <= hcs_n;\r
+\r
+ //assert on falling edge of delayed chip select\r
+ hr <= ~hcs_n & hcs_n_delayed;\r
+ hready_n <= ~hr;\r
+ end\r
+end\r
+\r
+\r
+\r
+// Mux Register Read-Data Outputs\r
+always @(posedge hclk or negedge rst_n)\r
+begin\r
+ if (rst_n == 1'b0) begin\r
+ hdataout <= 8'd0;\r
+ end\r
+ else begin\r
+ case (haddr[3:0])\r
+\r
+ 4'd0:\r
+ begin\r
+ hdataout <= data_out_reg_0[7:0];\r
+ end\r
+\r
+\r
+ 4'd1:\r
+ begin\r
+ hdataout <= data_out_reg_0[15:8];\r
+ end\r
+\r
+ /////////////////////////////////////////////\r
+\r
+ 4'd2:\r
+ begin\r
+ hdataout <= data_out_reg_1[7:0];\r
+ end\r
+\r
+\r
+ 4'd3:\r
+ begin\r
+ hdataout <= data_out_reg_1[15:8];\r
+ end\r
+\r
+ /////////////////////////////////////////////\r
+\r
+ 4'd8:\r
+ begin\r
+ hdataout <= data_out_reg_4[7:0];\r
+ end\r
+\r
+\r
+ 4'd9:\r
+ begin\r
+ hdataout <= data_out_reg_4[15:8];\r
+ end\r
+\r
+ /////////////////////////////////////////////\r
+\r
+ 4'd10:\r
+ begin\r
+ hdataout <= data_out_reg_5[7:0];\r
+ end\r
+\r
+\r
+ 4'd11:\r
+ begin\r
+ hdataout <= data_out_reg_5[15:8];\r
+ end\r
+\r
+ /////////////////////////////////////////////\r
+\r
+ 4'd12:\r
+ begin\r
+ hdataout <= data_out_reg_6[7:0];\r
+ end\r
+\r
+\r
+ 4'd13:\r
+ begin\r
+ hdataout <= data_out_reg_6[15:8];\r
+ end\r
+\r
+ /////////////////////////////////////////////\r
+\r
+ default:\r
+ begin\r
+ hdataout <= 8'd0;\r
+ end\r
+ endcase\r
+ end\r
+end\r
+\r
+endmodule\r
+\r
+module register_addr_decoder (\r
+ rst_n,\r
+ addr,\r
+ cs_in,\r
+\r
+ reg0_cs_0,\r
+ reg0_cs_1,\r
+\r
+ reg1_cs_0,\r
+ reg1_cs_1,\r
+\r
+ reg4_cs_0,\r
+ reg4_cs_1,\r
+\r
+ reg5_cs_0,\r
+ reg5_cs_1,\r
+\r
+ reg6_cs_0,\r
+ reg6_cs_1\r
+);\r
+\r
+input rst_n;\r
+input cs_in;\r
+input [3:0] addr;\r
+\r
+output reg0_cs_0;\r
+output reg0_cs_1;\r
+\r
+output reg1_cs_0;\r
+output reg1_cs_1;\r
+\r
+output reg4_cs_0;\r
+output reg4_cs_1;\r
+\r
+output reg5_cs_0;\r
+output reg5_cs_1;\r
+\r
+output reg6_cs_0;\r
+output reg6_cs_1;\r
+\r
+//////////////////////////\r
+\r
+wire reg0_cs_0;\r
+wire reg0_cs_1;\r
+\r
+wire reg1_cs_0;\r
+wire reg1_cs_1;\r
+\r
+wire reg4_cs_0;\r
+wire reg4_cs_1;\r
+\r
+wire reg5_cs_0;\r
+wire reg5_cs_1;\r
+\r
+wire reg6_cs_0;\r
+wire reg6_cs_1;\r
+\r
+//////////////////////////\r
+\r
+assign reg0_cs_0 = (addr == 4'h0) ? cs_in : 1'b0;\r
+assign reg0_cs_1 = (addr == 4'h1) ? cs_in : 1'b0;\r
+\r
+assign reg1_cs_0 = (addr == 4'h2) ? cs_in : 1'b0;\r
+assign reg1_cs_1 = (addr == 4'h3) ? cs_in : 1'b0;\r
+\r
+assign reg4_cs_0 = (addr == 4'h8) ? cs_in : 1'b0;\r
+assign reg4_cs_1 = (addr == 4'h9) ? cs_in : 1'b0;\r
+\r
+assign reg5_cs_0 = (addr == 4'ha) ? cs_in : 1'b0;\r
+assign reg5_cs_1 = (addr == 4'hb) ? cs_in : 1'b0;\r
+\r
+assign reg6_cs_0 = (addr == 4'hc) ? cs_in : 1'b0;\r
+assign reg6_cs_1 = (addr == 4'hd) ? cs_in : 1'b0;\r
+\r
+\r
+endmodule\r
+\r
--- /dev/null
+//**************************************************************************\r
+// *************************************************************************\r
+// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
+// * PROPRIETARY NOTE *\r
+// * *\r
+// * This software contains information confidential and proprietary *\r
+// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
+// * in whole or in part, or transferred to other documents, or disclosed *\r
+// * to third parties, or used for any purpose other than that for which *\r
+// * it was obtained, without the prior written consent of Lattice *\r
+// * Semiconductor Corporation. All rights reserved. *\r
+// * *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+////////////////////////////////////////////////////////////////////////\r
+// This module forces a RESET to the SERDES CDR\r
+// when the CDR either loses lock or loses signal\r
+////////////////////////////////////////////////////////////////////////\r
+\r
+`timescale 1ns/100ps\r
+\r
+module reset_controller_cdr (\r
+\r
+ rst_n,\r
+ clk,\r
+\r
+ cdr_lol,\r
+\r
+ cdr_rst_out\r
+ );\r
+\r
+input rst_n;\r
+input clk; // 125Mhz clock\r
+\r
+input cdr_lol;\r
+\r
+output cdr_rst_out;\r
+\r
+\r
+///////////////////////////////////////\r
+\r
+reg cdr_rst_out;\r
+\r
+reg cdr_lol_mstb_1;\r
+reg cdr_lol_mstb_2;\r
+\r
+\r
+reg sht_mx;\r
+reg [5:0] sht_count;\r
+\r
+reg lng_mx;\r
+reg [22:0] lng_count;\r
+\r
+reg cnt_rst;\r
+parameter\r
+ ASSRT_RST = 3'd0,\r
+ WAIT_SHORT = 3'd1,\r
+ DSSRT_RST = 3'd2,\r
+ WAIT_LONG = 3'd3,\r
+ SEEK_CDR_ERR = 3'd4,\r
+ SEEK_SIGNAL_RESTORE = 3'd5;\r
+reg[2:0] fsm;\r
+\r
+//////////////////////////////////////\r
+// Mestastability Filter\r
+//////////////////////////////////////\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+ if (rst_n == 1'b0) begin\r
+ cdr_lol_mstb_1 <= 1'b1;\r
+ cdr_lol_mstb_2 <= 1'b1;\r
+\r
+\r
+ end\r
+ else begin\r
+ cdr_lol_mstb_1 <= cdr_lol;\r
+ cdr_lol_mstb_2 <= cdr_lol_mstb_1;\r
+\r
+ end\r
+end \r
+\r
+\r
+\r
+///////////////////////////////////////\r
+// Operate Short Timer (256 nsec)\r
+///////////////////////////////////////\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+ if (rst_n == 1'b0) begin\r
+ sht_mx <= 1'b0;\r
+ sht_count <= 6'd0;\r
+ end\r
+ else begin\r
+\r
+ // define max count\r
+ if (sht_count[5] && (!cnt_rst)) begin\r
+ sht_mx <= 1'b1;\r
+ end\r
+ else begin\r
+ sht_mx <= 1'b0;\r
+ end\r
+\r
+ // operate counter\r
+ if (cnt_rst) begin\r
+ sht_count <= 6'd0; //clear\r
+ end\r
+ else if (sht_mx) begin\r
+ sht_count <= sht_count; //hold\r
+ end\r
+ else begin\r
+ sht_count <= sht_count + 1; //count\r
+ end\r
+ end\r
+end \r
+\r
+\r
+/////////////////////////////////////\r
+// Operate Long Timer (33 msec)\r
+/////////////////////////////////////\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+ if (rst_n == 1'b0) begin\r
+ lng_mx <= 1'b0;\r
+ lng_count <= 23'd0;\r
+ end\r
+ else begin\r
+\r
+ // define max count\r
+ if (lng_count[22] && (!cnt_rst)) begin\r
+ lng_mx <= 1'b1;\r
+ end\r
+ else begin\r
+ lng_mx <= 1'b0;\r
+ end\r
+\r
+ // operate counter\r
+ if (cnt_rst) begin\r
+ lng_count <= 6'd0; //clear\r
+ end\r
+ else if (lng_mx) begin\r
+ lng_count <= lng_count; //hold\r
+ end\r
+ else begin\r
+ lng_count <= lng_count + 1; //count\r
+ end\r
+ end\r
+end \r
+\r
+\r
+/////////////////////////////////////\r
+// State Machine\r
+/////////////////////////////////////\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+ if (rst_n == 1'b0) begin\r
+ cdr_rst_out <= 1'b1;\r
+ cnt_rst <= 1'b1;\r
+ fsm <= ASSRT_RST;\r
+ end\r
+ else begin\r
+\r
+ // defaults\r
+ cnt_rst <= 1'b0;\r
+\r
+ case (fsm)\r
+ ASSRT_RST: begin\r
+ cdr_rst_out <= 1'b1; // assert\r
+ cnt_rst <= 1'b1;\r
+ fsm <= WAIT_SHORT;\r
+ end\r
+\r
+ WAIT_SHORT: begin\r
+ // wait for 256 nsec\r
+ if (sht_mx && (!cnt_rst)) begin\r
+ fsm <= DSSRT_RST;\r
+ end\r
+ end\r
+\r
+ DSSRT_RST: begin\r
+ cdr_rst_out <= 1'b0; // de-assert\r
+ fsm <= WAIT_LONG;\r
+ end\r
+\r
+ WAIT_LONG: begin\r
+ // wait for 33 msec\r
+ if (lng_mx && (!cnt_rst)) begin\r
+ fsm <= SEEK_CDR_ERR;\r
+ end\r
+ end\r
+\r
+ SEEK_CDR_ERR: begin\r
+\r
+ cnt_rst <= 1'b1;\r
+\r
+\r
+ // Wait for CDR to fail\r
+ if (cdr_lol_mstb_2) begin\r
+ fsm <= ASSRT_RST;\r
+ end\r
+ else begin\r
+ fsm <= SEEK_CDR_ERR;\r
+ end\r
+ end\r
+\r
+\r
+\r
+ default: begin\r
+ fsm <= ASSRT_RST;\r
+ end\r
+ endcase\r
+\r
+ end\r
+end \r
+\r
+\r
+\r
+endmodule\r
+\r
--- /dev/null
+//**************************************************************************\r
+// *************************************************************************\r
+// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
+// * PROPRIETARY NOTE *\r
+// * *\r
+// * This software contains information confidential and proprietary *\r
+// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
+// * in whole or in part, or transferred to other documents, or disclosed *\r
+// * to third parties, or used for any purpose other than that for which *\r
+// * it was obtained, without the prior written consent of Lattice *\r
+// * Semiconductor Corporation. All rights reserved. *\r
+// * *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+////////////////////////////////////////////////////////////////////////\r
+// This module implements the SERDES/PCS reset sequence as specified\r
+// in Figure 47 of Lattice Technical Note TN1176\r
+////////////////////////////////////////////////////////////////////////\r
+\r
+`timescale 1ns/100ps\r
+\r
+module reset_controller_pcs (\r
+\r
+ rst_n,\r
+ clk,\r
+\r
+ tx_plol,\r
+ rx_cdr_lol,\r
+\r
+ quad_rst_out,\r
+ tx_pcs_rst_out,\r
+ rx_pcs_rst_out\r
+ );\r
+\r
+input rst_n;\r
+input clk; // 125Mhz clock\r
+\r
+input tx_plol;\r
+input rx_cdr_lol;\r
+\r
+output quad_rst_out;\r
+output tx_pcs_rst_out;\r
+output rx_pcs_rst_out;\r
+\r
+\r
+///////////////////////////////////////\r
+\r
+reg quad_rst_out;\r
+reg tx_pcs_rst_out;\r
+reg rx_pcs_rst_out;\r
+\r
+reg q_mx;\r
+reg [3:0] q_count;\r
+\r
+reg rx_cdr_lol_mstb_1;\r
+reg rx_cdr_lol_mstb_2;\r
+\r
+reg wd_mx;\r
+reg wd_mx_d1;\r
+reg wd_mx_re;\r
+reg [22:0] wd_count;\r
+reg watchdog_flag;\r
+\r
+////////////////////////////////////////////////////////\r
+// Assert Quad RST For 8 Clocks After Device Hard Reset\r
+////////////////////////////////////////////////////////\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+ if (rst_n == 1'b0) begin\r
+ q_mx <= 1'b0;\r
+ q_count <= 4'd0;\r
+ quad_rst_out <= 1'b1; // assert\r
+ end\r
+ else begin\r
+\r
+ // define max count\r
+ if (q_count[3]) begin\r
+ q_mx <= 1'b1;\r
+ end\r
+ else begin\r
+ q_mx <= 1'b0;\r
+ end\r
+\r
+ // operate counter\r
+ if (q_mx) begin\r
+ q_count <= q_count; //hold\r
+ end\r
+ else begin\r
+ q_count <= q_count + 1; //count\r
+ end\r
+\r
+ // operate quad reset\r
+ if (q_mx) begin\r
+ quad_rst_out <= 1'b0; //de-assert on max-count\r
+ end\r
+ else begin\r
+ quad_rst_out <= 1'b1; //assert otherwise\r
+ end\r
+ end\r
+end \r
+\r
+\r
+////////////////////////////////////////////////////////////////////\r
+// Watchdog Timer -- In Case PLLs Don't Acquire Lock Within 33msec\r
+////////////////////////////////////////////////////////////////////\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+ if (rst_n == 1'b0) begin\r
+ wd_mx <= 1'b0;\r
+ wd_mx_d1 <= 1'b0;\r
+ wd_mx_re <= 1'b0;\r
+ wd_count <= 23'd0;\r
+ watchdog_flag <= 1'b0;\r
+ end\r
+ else begin\r
+\r
+ // define max count\r
+ if (wd_count[22]) begin\r
+ wd_mx <= 1'b1;\r
+ end\r
+ else begin\r
+ wd_mx <= 1'b0;\r
+ end\r
+\r
+ // operate counter\r
+ if (quad_rst_out) begin\r
+ wd_count <= 23'd0; //clear\r
+ end\r
+ else if (wd_mx) begin\r
+ wd_count <= wd_count; //hold\r
+ end\r
+ else begin\r
+ wd_count <= wd_count + 1; //count\r
+ end\r
+\r
+ // detect rising edge of max_count flag\r
+ wd_mx_d1 <= wd_mx;\r
+\r
+ wd_mx_re <= wd_mx & (!wd_mx_d1);\r
+\r
+ // generate watchdog flag\r
+ watchdog_flag <= wd_mx_re;\r
+ end\r
+end \r
+\r
+\r
+\r
+\r
+////////////////////////////////////////////////\r
+// De-Assert TX PCS After TX PLL Acquires Lock\r
+////////////////////////////////////////////////\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+ if (rst_n == 1'b0) begin\r
+ tx_pcs_rst_out <= 1'b1; // assert\r
+ end\r
+ else begin\r
+\r
+ case (tx_pcs_rst_out)\r
+ 1'b1: begin\r
+ // if asserted, wait for PLL to acquire lock\r
+ if ((!quad_rst_out && (!tx_plol)) || watchdog_flag) begin\r
+ tx_pcs_rst_out <= 1'b0; // deassert\r
+ end\r
+ end\r
+\r
+ 1'b0: begin\r
+ // if de-asserted, stay that way\r
+ tx_pcs_rst_out <= 1'b0; // deassert\r
+ end\r
+\r
+ default: begin\r
+ tx_pcs_rst_out <= 1'b1; // assert\r
+ end\r
+ endcase\r
+\r
+ end\r
+end \r
+\r
+\r
+\r
+\r
+\r
+///////////////////////////////////////////////////////\r
+// De-Assert RX PCS-Chan-0 After RX CDR Acquires Lock\r
+///////////////////////////////////////////////////////\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+ if (rst_n == 1'b0) begin\r
+ rx_pcs_rst_out <= 1'b1; // assert\r
+ rx_cdr_lol_mstb_1 <= 1'b1;\r
+ rx_cdr_lol_mstb_2 <= 1'b1;\r
+ end\r
+ else begin\r
+\r
+ // metastability - filter\r
+ rx_cdr_lol_mstb_1 <= rx_cdr_lol;\r
+ rx_cdr_lol_mstb_2 <= rx_cdr_lol_mstb_1;\r
+\r
+ case (rx_pcs_rst_out)\r
+ 1'b1: begin\r
+ // if asserted, wait for CDR to acquire lock\r
+ if ((!quad_rst_out && (!rx_cdr_lol_mstb_2)) || watchdog_flag) begin\r
+ rx_pcs_rst_out <= 1'b0; // deassert\r
+ end\r
+ end\r
+\r
+ 1'b0: begin\r
+ // if de-asserted, stay that way\r
+ rx_pcs_rst_out <= 1'b0; // deassert\r
+ end\r
+\r
+ default: begin\r
+ rx_pcs_rst_out <= 1'b1; // assert\r
+ end\r
+ endcase\r
+\r
+ end\r
+end \r
+\r
+\r
+\r
+\r
+endmodule\r
+\r
--- /dev/null
+//**************************************************************************\r
+// *************************************************************************\r
+// * LATTICE SEMICONDUCTOR CONFIDENTIAL *\r
+// * PROPRIETARY NOTE *\r
+// * *\r
+// * This software contains information confidential and proprietary *\r
+// * to Lattice Semiconductor Corporation. It shall not be reproduced *\r
+// * in whole or in part, or transferred to other documents, or disclosed *\r
+// * to third parties, or used for any purpose other than that for which *\r
+// * it was obtained, without the prior written consent of Lattice *\r
+// * Semiconductor Corporation. All rights reserved. *\r
+// * *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`timescale 1ns/100ps\r
+\r
+module sgmii_channel_smi (\r
+\r
+ // Control Interface\r
+ rst_n,\r
+ gbe_mode,\r
+ sgmii_mode,\r
+ signal_detect,\r
+ debug_link_timer_short,\r
+ rx_compensation_err,\r
+ non_an_rate,\r
+\r
+ // G/MII Interface\r
+ in_clk_gmii,\r
+ in_clk_mii,\r
+ data_in_mii,\r
+ en_in_mii,\r
+ err_in_mii,\r
+\r
+ out_clk_gmii,\r
+ out_clk_mii,\r
+ data_out_mii,\r
+ dv_out_mii,\r
+ err_out_mii,\r
+ col_out_mii,\r
+ crs_out_mii,\r
+\r
+ // 8-bit Interface\r
+ data_out_8bi,\r
+ kcntl_out_8bi,\r
+ disparity_cntl_out_8bi,\r
+\r
+ serdes_recovered_clk,\r
+ data_in_8bi,\r
+ kcntl_in_8bi,\r
+ even_in_8bi,\r
+ disp_err_in_8bi,\r
+ cv_err_in_8bi,\r
+ err_decode_mode_8bi,\r
+\r
+ // MDIO Port\r
+ mdc,\r
+ mdio,\r
+ port_id\r
+ );\r
+\r
+\r
+\r
+// I/O Declarations\r
+input rst_n ; // System Reset, Active Low\r
+input signal_detect ;\r
+input gbe_mode ; // GBE Mode (0=SGMII 1=GBE)\r
+input sgmii_mode ; // SGMII PCS Mode (0=MAC 1=PHY)\r
+input debug_link_timer_short ; // (0=NORMAL 1=SHORT)\r
+output rx_compensation_err; // Active high pulse indicating RX_CTC_FIFO either underflowed or overflowed\r
+input [1:0] non_an_rate ; // MII Rate Used When Autonegotiation is Disabled (00=10Mbps; 01=100Mbps; 10=1Gbps)\r
+\r
+input in_clk_mii ; // G/MII Transmit clock 2.5Mhz/25Mhz/125Mhz \r
+input [7:0] data_in_mii ; // G/MII Tx data\r
+input en_in_mii ; // G/MII data valid\r
+input err_in_mii ; // G/MII Tx error\r
+\r
+input out_clk_mii ; // G/MII Receice clock 2.5Mhz/25Mhz/125MHz \r
+output [7:0] data_out_mii ; // G/MII Rx data\r
+output dv_out_mii ; // G/MII Rx data valid\r
+output err_out_mii ; // G/MII Rx error\r
+output col_out_mii ; // G/MII collision detect \r
+output crs_out_mii ; // G/MII carrier sense detect \r
+\r
+output [7:0] data_out_8bi ; // 8BI Tx Data\r
+output kcntl_out_8bi ; // 8BI Tx Kcntl\r
+output disparity_cntl_out_8bi ; // 8BI Tx Kcntl\r
+\r
+input serdes_recovered_clk ;\r
+input [7:0] data_in_8bi ; // 8BI Rx Data\r
+input kcntl_in_8bi ; // 8BI Rx Kcntl\r
+input even_in_8bi ; // 8BI Rx Even\r
+input disp_err_in_8bi ; // 8BI Rx Disparity Error\r
+input cv_err_in_8bi ; // 8BI Rx Coding Violation Error\r
+input err_decode_mode_8bi ; // 8BI Error Decode Mode (0=NORMAL, 1=DECODE_MODE)\r
+\r
+input in_clk_gmii ; // GMII Transmit clock 125Mhz\r
+input out_clk_gmii ; // GMII Receive clock 125Mhz\r
+\r
+input mdc;\r
+inout mdio;\r
+input [4:0] port_id;\r
+\r
+\r
+wire mdin;\r
+wire mdout;\r
+wire mdout_en;\r
+\r
+// Internal Signals \r
+\r
+wire mr_an_complete;\r
+wire mr_page_rx;\r
+wire [15:0] mr_lp_adv_ability;\r
+\r
+wire mr_main_reset;\r
+wire mr_an_enable;\r
+wire mr_restart_an;\r
+wire [15:0] mr_adv_ability;\r
+\r
+wire [1:0] operational_rate;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+// SGMII PCS\r
+sgmii33 sgmii33_U (\r
+ // Clock and Reset\r
+ .rst_n (rst_n ),\r
+ .signal_detect (signal_detect),\r
+ .gbe_mode (gbe_mode),\r
+ .sgmii_mode (sgmii_mode),\r
+ .debug_link_timer_short (debug_link_timer_short), \r
+ .operational_rate (operational_rate),\r
+ .rx_compensation_err (rx_compensation_err),\r
+ .tx_clk_125 (in_clk_gmii),\r
+ .serdes_recovered_clk (serdes_recovered_clk),\r
+ .rx_clk_125 (out_clk_gmii),\r
+\r
+ // Control\r
+\r
+\r
+ // (G)MII TX Port\r
+ .tx_clk_mii (in_clk_mii),\r
+ .tx_d (data_in_mii),\r
+ .tx_en (err_in_mii),\r
+ .tx_er (en_in_mii),\r
+\r
+ // (G)MII RX Port\r
+ .rx_clk_mii (out_clk_mii),\r
+ .rx_d (data_out_mii),\r
+ .rx_dv (dv_out_mii),\r
+ .rx_er (err_out_mii),\r
+ .col (col_out_mii),\r
+ .crs (crs_out_mii),\r
+ \r
+ // 8BI TX Port\r
+ .tx_data (data_out_8bi),\r
+ .tx_kcntl (kcntl_out_8bi),\r
+ .tx_disparity_cntl (disparity_cntl_out_8bi),\r
+\r
+ // 8BI RX Port\r
+ .rx_data (data_in_8bi),\r
+ .rx_kcntl (kcntl_in_8bi),\r
+ .rx_even (even_in_8bi),\r
+ .rx_disp_err (disp_err_in_8bi),\r
+ .rx_cv_err (cv_err_in_8bi),\r
+ .rx_err_decode_mode (err_decode_mode_8bi),\r
+\r
+ // Management Interface I/O\r
+ .mr_adv_ability (mr_adv_ability),\r
+ .mr_an_enable (mr_an_enable), \r
+ .mr_main_reset (mr_main_reset), \r
+ .mr_restart_an (mr_restart_an), \r
+\r
+ .mr_an_complete (mr_an_complete), \r
+ .mr_lp_adv_ability (mr_lp_adv_ability), \r
+ .mr_page_rx (mr_page_rx)\r
+ );\r
+\r
+\r
+\r
+// SMI Register Interface for SGMII IP Core\r
+register_interface_smi ri (\r
+\r
+ // Control Signals\r
+ .rst_n (rst_n),\r
+ .gbe_mode (gbe_mode),\r
+ .sgmii_mode (sgmii_mode),\r
+\r
+ // MDIO Port\r
+ .mdc (mdc),\r
+ .mdin (mdin),\r
+ .mdout (mdout),\r
+ .mdout_en (mdout_en),\r
+ .port_id (port_id),\r
+\r
+ // Register Outputs\r
+ .mr_an_enable (mr_an_enable),\r
+ .mr_restart_an (mr_restart_an),\r
+ .mr_main_reset (mr_main_reset),\r
+ .mr_adv_ability (mr_adv_ability),\r
+\r
+ // Register Inputs\r
+ .mr_an_complete (mr_an_complete),\r
+ .mr_page_rx (mr_page_rx),\r
+ .mr_lp_adv_ability (mr_lp_adv_ability)\r
+ );\r
+\r
+\r
+\r
+// (G)MII Rate Resolution for SGMII IP Core\r
+rate_resolution rate_resolution (\r
+ .gbe_mode (gbe_mode),\r
+ .sgmii_mode (sgmii_mode),\r
+ .an_enable (mr_an_enable),\r
+ .advertised_rate (mr_adv_ability[11:10]),\r
+ .link_partner_rate (mr_lp_adv_ability[11:10]),\r
+ .non_an_rate (non_an_rate),\r
+\r
+ .operational_rate (operational_rate)\r
+);\r
+\r
+\r
+\r
+\r
+\r
+// Bidirectional Assignments\r
+assign mdio = mdout_en ? mdout : 1'bz; // MDIO Output\r
+assign mdin = mdio; // MDIO Input\r
+\r
+endmodule\r
+\r
jspc29 / trbnet.git / commitdiff