added new padiwa register

diff --git a/fw_spiconfig.tex b/fw_spiconfig.tex
index c5a4b593ed585a1e3b8168d6796ea21c15a63380..72b59b31f3f5b9a10a34b194a86b30b871b4bce3 100644 (file)
--- a/fw_spiconfig.tex
+++ b/fw_spiconfig.tex
@@ -34,6 +34,8 @@ when temperature is changing. See below. \\
 0x20 & 10 & Test & Reads a word from the test Fifo. \\
 0x21 & 0--2 & Design & Design Information. Register 0/1: lower/upper part of 
 Unix timestamp of time of compilation. Register 2: Padiwa version number.\\
+0x22 & any & Cnt & Lower 16 Bits of input signal counters for all 16 channels.\\
+0x23 & any & Cnt & Upper 8 Bit of input signal counters.\\
 0x40 & any & Memory & Read/Write to/from RAM. 16 registers with 8 Bit each.\\
 0x50 & 0 & Flash & Execute Flash command.\\
 0x51 & 0--1 & Flash & Load RAM content to PWM settings. Channel Bit 0 selects upper or lower half of PWM channels. No data payload\\