typos fixed

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index f372974b07f412dc2b0aa5656fb0edf342be1101..bdc408f38c5f21f3b672f65e2e338f1745c1a353 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -18,7 +18,6 @@ entity med_ecp3_sfp_sync_all_RS is
     -- Clocks and reset
     CLK_REF_FULL       : in  std_logic; -- TRBnet reference clock
     SYSCLK             : in  std_logic; -- FPGA fabric clock
-    SAMPLE_CLK         : in  std_logic; -- DLM measurement clock
     RESET              : in  std_logic; -- synchronous reset
     -- Media Interface TX/RX
     MEDIA_MED2INT      : out med2int_array_t(0 to 3);

diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd
index aec67017e6beb42fcc2053f4b850ae8dc99da3b7..47d523bea9fe0bf8ef1191a63afb11c0eb9afb21 100644 (file)
--- a/media_interfaces/sync/main_rx_reset_RS.vhd
+++ b/media_interfaces/sync/main_rx_reset_RS.vhd
@@ -150,7 +150,7 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
-          if( cnt(Tshort_bit) ) then\r
+          if( cnt(Tshort_bit) = '1' ) then\r
             cnt <= (others => '0');\r
             rx_sm <= WAIT_RXPCS_LOCK;\r
           else\r