-[c2]
+[ash]
system = linux
corenum = 4
env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
-[c3]
+[dallas]
system = linux
corenum = 4
env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
-[c4]
+[vasquez]
system = linux
corenum = 4
env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
-[c5]
+[bishop]
system = linux
corenum = 4
env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
-[c6]
-system = linux
-corenum = 4
-env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
-workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/
-[c7]
+[lambert]
system = linux
corenum = 4
env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
-----------------------------------------------------------------------------
- adc_ddr_generic_1: adc_ddr_generic
+ adc_ddr_generic_1: entity work.adc_ddr_generic
port map (
clk_0 => ADC0_DCLK_IN,
clk_1 => ADC1_DCLK_IN,
-- Tansfer to CLK_IN
-----------------------------------------------------------------------------
- fifo_adc_48to48_dc_1: fifo_adc_48to48_dc
+ fifo_adc_48to48_dc_1: entity work.fifo_adc_48to48_dc
port map (
Data(11 downto 0) => adc0_data_m(0),
Data(23 downto 12) => adc0_data_m(1),
-----------------------------------------------------------------------------
- fifo_adc_48to48_dc_2: fifo_adc_48to48_dc
+ fifo_adc_48to48_dc_2: entity work.fifo_adc_48to48_dc
port map (
Data(11 downto 0) => adc1_data_m(0),
Data(23 downto 12) => adc1_data_m(1),
-----------------------------------------------------------------------------
- ram_fifo_delay_256x44_1: ram_fifo_delay_256x44
+ ram_fifo_delay_256x44_1: entity work.ram_fifo_delay_256x44
port map (
WrAddress => write_address,
RdAddress => read_address,
-- Fifo Delay
signal fifo_delay : std_logic_vector(7 downto 0);
signal fifo_delay_reset : std_logic;
+
+ -- Frame Rate Counter
+ signal rate_timer : unsigned(27 downto 0);
+ signal frame_rate_in_ctr_t : unsigned(27 downto 0);
+ signal frame_rate_out_ctr_t : unsigned(27 downto 0);
+ signal frame_rate_input : unsigned(27 downto 0);
+ signal frame_rate_output : unsigned(27 downto 0);
+
+ -- Error Status
+ signal data_clk_shift : std_logic_vector(3 downto 0);
+ signal frame_dt_error : std_logic;
+ signal frame_dt_error_ctr : unsigned(15 downto 0);
+ signal frame_rate_error : std_logic;
+
+ signal data_clk_out_shift : std_logic_vector(3 downto 0);
+ signal frame_dt_out_error : std_logic;
+ signal frame_dt_out_error_ctr : unsigned(15 downto 0);
+ signal frame_rate_out_error : std_logic;
+
+ signal error_o : std_logic;
-- Slave Bus
signal slv_data_o : std_logic_vector(31 downto 0);
end if;
end if;
end process PROC_FIFO_DELAY;
+
+ PROC_CAL_RATES: process (CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if (RESET_IN = '1') then
+ rate_timer <= (others => '0');
+ frame_rate_input <= (others => '0');
+ frame_rate_output <= (others => '0');
+ frame_rate_in_ctr_t <= (others => '0');
+ frame_rate_out_ctr_t <= (others => '0');
+ else
+ if (rate_timer < x"5f5e100") then
+ if (DATA_CLK_IN = '1') then
+ frame_rate_in_ctr_t <= frame_rate_in_ctr_t + 1;
+ end if;
+ if (data_clk_o = '1') then
+ frame_rate_out_ctr_t <= frame_rate_out_ctr_t + 1;
+ end if;
+ rate_timer <= rate_timer + 1;
+ else
+ frame_rate_input <= frame_rate_in_ctr_t;
+ frame_rate_in_ctr_t(27 downto 1) <= (others => '0');
+ frame_rate_in_ctr_t(0) <= DATA_CLK_IN;
+
+ frame_rate_output <= frame_rate_out_ctr_t;
+ frame_rate_out_ctr_t(27 downto 1) <= (others => '0');
+ frame_rate_out_ctr_t(0) <= data_clk_o;
+
+ rate_timer <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end process PROC_CAL_RATES;
+
+ PROC_DATA_STREAM_DELTA_T: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN)) then
+ if (RESET_IN = '1') then
+ data_clk_shift <= (others => '0');
+ frame_dt_error_ctr <= (others => '0');
+ frame_dt_error <= '0';
+ data_clk_out_shift <= (others => '0');
+ frame_dt_out_error_ctr <= (others => '0');
+ frame_dt_out_error <= '0';
+ else
+ -- Frame
+ data_clk_shift(0) <= DATA_CLK_IN;
+ data_clk_shift(3 downto 1) <= data_clk_shift(2 downto 0);
+
+ data_clk_out_shift(0) <= data_clk_o;
+ data_clk_out_shift(3 downto 1) <= data_clk_out_shift(2 downto 0);
+
+ case data_clk_shift is
+ when "1100" | "1110" | "1111" | "0000" =>
+ frame_dt_error_ctr <= frame_dt_error_ctr + 1;
+ frame_dt_error <= '1';
+
+ when others =>
+ frame_dt_error <= '0';
+
+ end case;
+
+ case data_clk_out_shift is
+ when "1100" | "1110" | "1111" | "0000" =>
+ frame_dt_out_error_ctr <= frame_dt_out_error_ctr + 1;
+ frame_dt_out_error <= '1';
+
+ when others =>
+ frame_dt_out_error <= '0';
+
+ end case;
+
+ end if;
+ end if;
+ end process PROC_DATA_STREAM_DELTA_T;
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
slv_ack_o <= '1';
when x"0001" =>
+ slv_data_o(27 downto 0) <= frame_rate_input;
+ slv_data_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0002" =>
+ slv_data_o(27 downto 0) <= frame_rate_output;
+ slv_data_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0003" =>
+ slv_data_o(15 downto 0) <= frame_dt_error_ctr;
+ slv_data_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0004" =>
+ slv_data_o(15 downto 0) <= frame_dt_out_error_ctr;
+ slv_data_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0005" =>
slv_data_o(0) <= debug_r;
slv_data_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
fifo_reset_r <= '1';
slv_ack_o <= '1';
- when x"0001" =>
+ when x"0005" =>
debug_r <= SLV_DATA_IN(0);
slv_ack_o <= '1';
signal nx_frame_synced_r : std_logic;
signal disable_adc_r : std_logic;
signal adc_debug_type_r : std_logic_vector(3 downto 0);
-
+
+ signal adc_sloppy_frame : std_logic; -- not used
+ signal reset_inhibit_r : std_logic; -- not used
+
-----------------------------------------------------------------------------
-- Reset Handler
-----------------------------------------------------------------------------
signal rs_timeout_timer_reset : std_logic;
signal nx_timestamp_reset_o : std_logic;
signal fifo_reset_handler : std_logic;
-
+
+ signal reset_handler_trigger : std_logic_vector(15 downto 0);
+
type R_STATES is (R_IDLE,
R_START,
R_WAIT_0,
end if;
end process PROC_PLL_PHASE_SETUP;
- pll_adc_sampling_clk_2: pll_adc_sampling_clk
+ pll_adc_sampling_clk_2: entity work.pll_adc_sampling_clk
port map (
CLK => adc_sampling_clk,
nx_frame_word_f <= nx_frame_word_ff when rising_edge(NX_DATA_CLK_IN);
-- Second delay NX_TIMESTAMP_IN relatively to ADC Clock
- dynamic_shift_register8x64_1: dynamic_shift_register8x64
+ dynamic_shift_register8x64_1: entity work.dynamic_shift_register8x64
port map (
Din => nx_frame_word_f,
Addr => nx_shift_register_delay,
DEBUG_OUT => ADC_DEBUG
);
+ -- Deprecated --> REMOVE
PROC_ADC_DATA_BIT_SHIFT: process(NX_DATA_CLK_IN)
variable adcval : unsigned(11 downto 0) := (others => '0');
begin
if (rising_edge(NX_DATA_CLK_IN)) then
- if (adc_bit_shift(3) = '1') then
- adcval := unsigned(adc_data) rol
- to_integer(adc_bit_shift(2 downto 0));
- else
- adcval := unsigned(adc_data) ror
- to_integer(adc_bit_shift(2 downto 0));
- end if;
-
if (adc_data_clk = '1') then
- adc_data_s <= std_logic_vector(adcval);
+ adc_data_s <= adc_data;
adc_data_s_clk <= '1';
else
adc_data_s <= x"aff";
reset_timeout_flag <= '0';
startup_reset <= '1';
nx_timestamp_reset_o <= '0';
+ reset_handler_trigger <= (others => '0');
R_STATE <= R_IDLE;
else
frame_rates_reset <= '0';
if (reset_handler_start_r = '1') then
-- Reset by register always wins, start it
rs_timeout_timer_reset <= '1';
+ reset_timeout_flag <= '0';
+ reset_handler_trigger(0) <= '1';
+ reset_handler_trigger(15 downto 1) <= (others => '0');
R_STATE <= R_START;
elsif (rs_timeout_timer_done = '1') then
-- Reset Timeout, retry RESET
rs_timeout_timer_reset <= '1';
reset_timeout_flag <= '1';
+ reset_handler_trigger(0) <= '0';
+ reset_handler_trigger(1) <= '1';
+ reset_handler_trigger(15 downto 2) <= (others => '0');
R_STATE <= R_START;
else
adc_reset_sync = '1' or
adc_frame_rate_error = '1' or
adc_error = '1' or
- pll_adc_not_lock = '1' or
adc_dt_error = '1' or
adc_sclk_ok_c100 = '0' or
adc_locked_c100 = '0'
parity_rate_error = '1' or
nx_frame_rate_error = '1'
) then
+
+ reset_handler_trigger(1 downto 0) <= (others => '0');
+ reset_handler_trigger( 2) <= nx_frame_rate_error;
+ reset_handler_trigger( 3) <= startup_reset;
+ reset_handler_trigger( 4) <= timestamp_dt_error;
+ reset_handler_trigger( 5) <= parity_rate_error;
+ reset_handler_trigger( 6) <= nx_frame_rate_error;
+ reset_handler_trigger( 7) <= pll_adc_not_lock;
+ reset_handler_trigger( 8) <= adc_reset_sync;
+ reset_handler_trigger( 9) <= adc_frame_rate_error;
+ reset_handler_trigger(10) <= adc_error;
+ reset_handler_trigger(11) <= adc_dt_error ;
+ reset_handler_trigger(12) <= not adc_sclk_ok_c100;
+ reset_handler_trigger(13) <= not adc_locked_c100;
+ reset_handler_trigger(15 downto 4) <= (others => '0');
+
R_STATE <= R_RESET_TIMESTAMP;
else
reset_timeout_flag <= '0';
begin
if (rising_edge(CLK_IN)) then
if (RESET_IN = '1') then
- nx_timestamp_delay_a <= (others => '0');
+ nx_timestamp_delay_a <= "010";
nx_timestamp_delay_actr <= (others => '0');
else
-- Automatic nx_timestamp_delay adjust
- if (nx_timestamp_delay_adjust = '1' and ADC_TR_ERROR_IN = '1') then
+ if (disable_adc_f = '0' and
+ nx_timestamp_delay_adjust = '1' and
+ ADC_TR_ERROR_IN = '1') then
if (nx_timestamp_delay_a <= "100") then
nx_timestamp_delay_a <= nx_timestamp_delay_a + 1;
else
adc_debug_type_r <= (others => '0');
debug_mode <= (others => '0');
disable_adc_r <= '0';
+
+ adc_sloppy_frame <= '0';
+ reset_inhibit_r <= '0';
else
slv_data_out_o <= (others => '0');
slv_ack_o <= '0';
when x"0001" =>
slv_data_out_o(0) <= reset_handler_busy;
slv_data_out_o(1) <= reset_timeout_flag;
- slv_data_out_o(31 downto 2) <= (others => '0');
+ slv_data_out_o(15 downto 2) <= (others => '0');
+ slv_data_out_o(31 downto 16) <= reset_handler_trigger;
slv_ack_o <= '1';
when x"0002" =>
when x"0004" =>
slv_data_out_o(27 downto 0) <= std_logic_vector(adc_frame_rate);
slv_data_out_o(30 downto 28) <= (others => '0');
+ slv_data_out_o(30) <= adc_sloppy_frame;
slv_data_out_o(31) <= disable_adc_r;
slv_ack_o <= '1';
when x"0005" =>
- slv_data_out_o(27 downto 0) <= parity_err_rate;
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(parity_err_rate);
slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0006" =>
- slv_data_out_o(15 downto 0) <= reset_handler_counter;
- slv_data_out_o(31 downto 6) <= (others => '0');
+ slv_data_out_o(2 downto 0) <=
+ std_logic_vector(nx_timestamp_delay_s);
+ slv_data_out_o(14 downto 3) <= (others => '0');
+ slv_data_out_o(15) <= nx_timestamp_delay_adjust;
+ slv_data_out_o(31 downto 16) <= nx_timestamp_delay_actr;
slv_ack_o <= '1';
when x"0007" =>
- slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr);
- slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_data_out_o(3 downto 0) <=
+ std_logic_vector(pll_adc_sample_clk_dphase_r);
+ slv_data_out_o(15 downto 4) <= (others => '0');
+ slv_data_out_o(19 downto 16) <=
+ std_logic_vector(pll_adc_sample_clk_finedelb_r);
+ slv_data_out_o(31 downto 20) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0008" =>
- slv_data_out_o(7 downto 0) <=
- std_logic_vector(adc_notlock_ctr_r);
- slv_data_out_o(31 downto 8) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(15 downto 0) <=
+ std_logic_vector(reset_handler_counter);
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
when x"0009" =>
- slv_data_out_o(11 downto 0) <= merge_error_ctr_r;
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(adc_reset_ctr);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"000a" =>
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(adc_notlock_counter);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000b" =>
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(merge_error_ctr_r);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000c" =>
slv_data_out_o(11 downto 0) <=
std_logic_vector(resync_counter);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
- when x"000b" =>
+ when x"000d" =>
slv_data_out_o(11 downto 0) <=
std_logic_vector(parity_error_counter);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
- when x"000c" =>
+ when x"000e" =>
slv_data_out_o(11 downto 0) <=
std_logic_vector(pll_adc_not_lock_ctr);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
- when x"000d" =>
- slv_data_out_o(3 downto 0) <=
- std_logic_vector(pll_adc_sample_clk_dphase_r);
- slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"000e" =>
- slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb_r;
- slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
-
+
when x"000f" =>
- slv_data_out_o(1 downto 0) <= johnson_counter_sync_r;
- slv_data_out_o(31 downto 2) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0010" =>
- slv_data_out_o(2 downto 0) <=
- std_logic_vector(nx_timestamp_delay_s);
- slv_data_out_o(3) <= '0';
- slv_data_out_o(5 downto 4) <=
- std_logic_vector(nx_frame_word_delay_r);
- slv_data_out_o(14 downto 6) <= (others => '0');
- slv_data_out_o(15) <= nx_timestamp_delay_adjust;
- slv_data_out_o(31 downto 16) <= nx_timestamp_delay_actr;
- slv_ack_o <= '1';
-
- when x"0011" =>
- slv_data_out_o(0) <= fifo_full_r;
- slv_data_out_o(1) <= fifo_empty_r;
- slv_data_out_o(2) <= '0';
- slv_data_out_o(3) <= '0';
- slv_data_out_o(4) <= '0';
- slv_data_out_o(5) <= '0';
- slv_data_out_o(29 downto 6) <= (others => '0');
- slv_data_out_o(30) <= '0';
- slv_data_out_o(31) <= nx_frame_synced_r;
- slv_ack_o <= '1';
-
- when x"0012" =>
- slv_data_out_o(3 downto 0) <= std_logic_vector(adc_bit_shift);
- slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0013" =>
- slv_data_out_o <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0014" =>
- slv_data_out_o(11 downto 0) <= new_adc_dt_error_ctr_r;
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(new_adc_dt_error_ctr_r);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
- when x"0015" =>
- slv_data_out_o(11 downto 0) <= new_timestamp_dt_error_ctr_r;
+ when x"0010" =>
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(new_timestamp_dt_error_ctr_r);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
- when x"0016" =>
- slv_data_out_o(27 downto 0) <=
- std_logic_vector(adc_notlock_counter);
- slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0017" =>
+ when x"0011" =>
slv_data_out_o(27 downto 0) <=
std_logic_vector(adc_error_counter);
- slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_data_out_o(31 downto 15) <= (others => '0');
slv_ack_o <= '1';
-
- when x"0018" =>
- slv_data_out_o(27 downto 0) <=
- std_logic_vector(adc_error_undef_counter);
- slv_data_out_o(31 downto 28) <= (others => '0');
+
+ when x"001d" =>
+ slv_data_out_o(1 downto 0) <= johnson_counter_sync_r;
+ slv_data_out_o(31 downto 2) <= (others => '0');
slv_ack_o <= '1';
when x"001e" =>
slv_unknown_addr_o <= '1';
end case;
+ -- case SLV_ADDR_IN is
+ -- when x"0000" =>
+ -- slv_data_out_o(15 downto 0) <= error_status_bits;
+ -- slv_data_out_o(31 downto 16) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0001" =>
+ -- slv_data_out_o(0) <= reset_handler_busy;
+ -- slv_data_out_o(1) <= reset_timeout_flag;
+ -- slv_data_out_o(31 downto 2) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0002" =>
+ -- slv_data_out_o(27 downto 0) <= std_logic_vector(frame_rate);
+ -- slv_data_out_o(31 downto 28) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0003" =>
+ -- slv_data_out_o(27 downto 0) <= std_logic_vector(nx_frame_rate);
+ -- slv_data_out_o(31 downto 28) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0004" =>
+ -- slv_data_out_o(27 downto 0) <= std_logic_vector(adc_frame_rate);
+ -- slv_data_out_o(30 downto 28) <= (others => '0');
+ -- slv_data_out_o(31) <= disable_adc_r;
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0005" =>
+ -- slv_data_out_o(27 downto 0) <= parity_err_rate;
+ -- slv_data_out_o(31 downto 28) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0006" =>
+ -- slv_data_out_o(15 downto 0) <= reset_handler_counter;
+ -- slv_data_out_o(31 downto 6) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0007" =>
+ -- slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr);
+ -- slv_data_out_o(31 downto 12) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0008" =>
+ -- slv_data_out_o(7 downto 0) <=
+ -- std_logic_vector(adc_notlock_ctr_r);
+ -- slv_data_out_o(31 downto 8) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0009" =>
+ -- slv_data_out_o(11 downto 0) <= merge_error_ctr_r;
+ -- slv_data_out_o(31 downto 12) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000a" =>
+ -- slv_data_out_o(11 downto 0) <=
+ -- std_logic_vector(resync_counter);
+ -- slv_data_out_o(31 downto 12) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000b" =>
+ -- slv_data_out_o(11 downto 0) <=
+ -- std_logic_vector(parity_error_counter);
+ -- slv_data_out_o(31 downto 12) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000c" =>
+ -- slv_data_out_o(11 downto 0) <=
+ -- std_logic_vector(pll_adc_not_lock_ctr);
+ -- slv_data_out_o(31 downto 12) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000d" =>
+ -- slv_data_out_o(3 downto 0) <=
+ -- std_logic_vector(pll_adc_sample_clk_dphase_r);
+ -- slv_data_out_o(31 downto 4) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000e" =>
+ -- slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb_r;
+ -- slv_data_out_o(31 downto 4) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000f" =>
+ -- slv_data_out_o(1 downto 0) <= johnson_counter_sync_r;
+ -- slv_data_out_o(31 downto 2) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0010" =>
+ -- slv_data_out_o(2 downto 0) <=
+ -- std_logic_vector(nx_timestamp_delay_s);
+ -- slv_data_out_o(3) <= '0';
+ -- slv_data_out_o(5 downto 4) <=
+ -- std_logic_vector(nx_frame_word_delay_r);
+ -- slv_data_out_o(14 downto 6) <= (others => '0');
+ -- slv_data_out_o(15) <= nx_timestamp_delay_adjust;
+ -- slv_data_out_o(31 downto 16) <= nx_timestamp_delay_actr;
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0011" =>
+ -- slv_data_out_o(0) <= fifo_full_r;
+ -- slv_data_out_o(1) <= fifo_empty_r;
+ -- slv_data_out_o(2) <= '0';
+ -- slv_data_out_o(3) <= '0';
+ -- slv_data_out_o(4) <= '0';
+ -- slv_data_out_o(5) <= '0';
+ -- slv_data_out_o(29 downto 6) <= (others => '0');
+ -- slv_data_out_o(30) <= '0';
+ -- slv_data_out_o(31) <= nx_frame_synced_r;
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0012" =>
+ -- slv_data_out_o(3 downto 0) <= std_logic_vector(adc_bit_shift);
+ -- slv_data_out_o(31 downto 4) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0013" =>
+ -- slv_data_out_o <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0014" =>
+ -- slv_data_out_o(11 downto 0) <= new_adc_dt_error_ctr_r;
+ -- slv_data_out_o(31 downto 12) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0015" =>
+ -- slv_data_out_o(11 downto 0) <= new_timestamp_dt_error_ctr_r;
+ -- slv_data_out_o(31 downto 12) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0016" =>
+ -- slv_data_out_o(27 downto 0) <=
+ -- std_logic_vector(adc_notlock_counter);
+ -- slv_data_out_o(31 downto 28) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0017" =>
+ -- slv_data_out_o(27 downto 0) <=
+ -- std_logic_vector(adc_error_counter);
+ -- slv_data_out_o(31 downto 28) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0018" =>
+ -- slv_data_out_o(27 downto 0) <=
+ -- std_logic_vector(adc_error_undef_counter);
+ -- slv_data_out_o(31 downto 28) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"001e" =>
+ -- slv_data_out_o(2 downto 0) <= debug_mode;
+ -- slv_data_out_o(31 downto 3) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when x"001f" =>
+ -- slv_data_out_o(3 downto 0) <= adc_debug_type_r;
+ -- slv_data_out_o(31 downto 4) <= (others => '0');
+ -- slv_ack_o <= '1';
+ --
+ -- when others =>
+ -- slv_unknown_addr_o <= '1';
+ -- end case;
+
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
when x"0001" =>
when x"0004" =>
disable_adc_r <= SLV_DATA_IN(31);
+ adc_sloppy_frame <= SLV_DATA_IN(30);
+ reset_inhibit_r <= '1';
slv_ack_o <= '1';
-
- when x"000a" =>
- reset_resync_ctr <= '1';
- slv_ack_o <= '1';
-
- when x"000b" =>
- reset_parity_error_ctr <= '1';
- slv_ack_o <= '1';
- when x"000c" =>
- pll_adc_not_lock_ctr_clear <= '1';
+ when x"0006" =>
+ nx_timestamp_delay_r <=
+ unsigned(SLV_DATA_IN(2 downto 0));
+ nx_timestamp_delay_adjust <= SLV_DATA_IN(15);
+ reset_inhibit_r <= '1';
slv_ack_o <= '1';
- when x"000d" =>
+ when x"0007" =>
pll_adc_sample_clk_dphase_r <=
unsigned(SLV_DATA_IN(3 downto 0));
+ pll_adc_sample_clk_finedelb_r <=
+ unsigned(SLV_DATA_IN(19 downto 16));
reset_handler_start_r <= '1';
slv_ack_o <= '1';
-
+
+ when x"000c" =>
+ reset_resync_ctr <= '1';
+ slv_ack_o <= '1';
+
+ when x"000d" =>
+ reset_parity_error_ctr <= '1';
+ slv_ack_o <= '1';
+
when x"000e" =>
- pll_adc_sample_clk_finedelb_r <= SLV_DATA_IN(3 downto 0);
- reset_handler_start_r <= '1';
- slv_ack_o <= '1';
+ pll_adc_not_lock_ctr_clear <= '1';
+ slv_ack_o <= '1';
- when x"000f" =>
+ when x"001d" =>
johnson_counter_sync_r
<= unsigned(SLV_DATA_IN(1 downto 0)) + 1;
reset_handler_start_r <= '1';
slv_ack_o <= '1';
-
- when x"0010" =>
- nx_timestamp_delay_r <=
- unsigned(SLV_DATA_IN(2 downto 0));
- nx_timestamp_delay_adjust <= SLV_DATA_IN(15);
- slv_ack_o <= '1';
-
- when x"0012" =>
- adc_bit_shift <=
- unsigned(SLV_DATA_IN(3 downto 0));
- slv_ack_o <= '1';
when x"001e" =>
debug_mode <= SLV_DATA_IN(2 downto 0);
when others =>
slv_unknown_addr_o <= '1';
-
- end case;
+ end case;
+
+
+ -- case SLV_ADDR_IN is
+ -- when x"0001" =>
+ -- reset_handler_start_r <= '1';
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0004" =>
+ -- disable_adc_r <= SLV_DATA_IN(31);
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000a" =>
+ -- reset_resync_ctr <= '1';
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000b" =>
+ -- reset_parity_error_ctr <= '1';
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000c" =>
+ -- pll_adc_not_lock_ctr_clear <= '1';
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000d" =>
+ -- pll_adc_sample_clk_dphase_r <=
+ -- unsigned(SLV_DATA_IN(3 downto 0));
+ -- reset_handler_start_r <= '1';
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000e" =>
+ -- pll_adc_sample_clk_finedelb_r <= SLV_DATA_IN(3 downto 0);
+ -- reset_handler_start_r <= '1';
+ -- slv_ack_o <= '1';
+ --
+ -- when x"000f" =>
+ -- johnson_counter_sync_r
+ -- <= unsigned(SLV_DATA_IN(1 downto 0)) + 1;
+ -- reset_handler_start_r <= '1';
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0010" =>
+ -- nx_timestamp_delay_r <=
+ -- unsigned(SLV_DATA_IN(2 downto 0));
+ -- nx_timestamp_delay_adjust <= SLV_DATA_IN(15);
+ -- slv_ack_o <= '1';
+ --
+ -- when x"0012" =>
+ -- adc_bit_shift <=
+ -- unsigned(SLV_DATA_IN(3 downto 0));
+ -- slv_ack_o <= '1';
+ --
+ -- when x"001e" =>
+ -- debug_mode <= SLV_DATA_IN(2 downto 0);
+ -- slv_ack_o <= '1';
+ --
+ -- when x"001f" =>
+ -- adc_debug_type_r <=
+ -- unsigned(SLV_DATA_IN(3 downto 0));
+ -- slv_ack_o <= '1';
+ --
+ -- when others =>
+ -- slv_unknown_addr_o <= '1';
+ --
+ -- end case;
+
end if;
end if;
end if;
signal pileup_ctr : unsigned(15 downto 0);
signal trigger_rate_inc : std_logic;
- signal frame_rate_inc : std_logic;
signal pileup_rate_inc : std_logic;
signal overflow_rate_inc : std_logic;
-- Rate Calculation
signal nx_trigger_ctr_t : unsigned(27 downto 0);
signal nx_trigger_ctr_t_nr : unsigned(31 downto 0);
- signal nx_frame_ctr_t : unsigned(27 downto 0);
+ signal frame_ctr_t : unsigned(27 downto 0);
signal nx_pileup_ctr_t : unsigned(27 downto 0);
signal nx_overflow_ctr_t : unsigned(27 downto 0);
signal adc_tr_error_ctr_t : unsigned(27 downto 0);
-
+ signal adc_tr_update_ctr_t : unsigned(27 downto 0);
+ signal adc_tr_data_ctr_t : unsigned(27 downto 0);
+
signal nx_rate_timer : unsigned(27 downto 0);
-- ADC Averages
signal adc_data_last : std_logic_vector(11 downto 0);
-- Token Return Average
- signal nx_token_return_pipec : std_logic_vector(4 downto 0);
- signal nx_token_return_pipev : std_logic_vector(8 downto 0);
+ signal nx_token_return_pipec : std_logic_vector(9 downto 0);
+ signal nx_token_return_pipev : std_logic_vector(11 downto 0);
signal adc_tr_value_tmp : std_logic_vector(11 downto 0);
signal adc_tr_value : std_logic_vector(11 downto 0);
signal adc_tr_data_p : unsigned(11 downto 0);
signal readout_type : std_logic_vector(1 downto 0);
-- Error Status
+ signal new_timestamp_shift : std_logic_vector(3 downto 0);
+ signal frame_dt_error : std_logic;
+ signal frame_dt_error_ctr : unsigned(15 downto 0);
+ signal frame_rate_error : std_logic;
signal error_o : std_logic;
-- Slave Bus
signal slv_ack_o : std_logic;
signal clear_counters : std_logic;
signal nx_hit_rate : unsigned(27 downto 0);
- signal nx_frame_rate : unsigned(27 downto 0);
+ signal frame_rate : unsigned(27 downto 0);
signal nx_pileup_rate : unsigned(27 downto 0);
signal nx_overflow_rate : unsigned(27 downto 0);
signal adc_tr_error_rate : unsigned(27 downto 0);
+ signal adc_tr_update_rate : unsigned(27 downto 0);
+ signal adc_tr_data_rate : unsigned(27 downto 0);
signal invalid_adc : std_logic;
signal adc_tr_value_r : std_logic_vector(11 downto 0);
nx_token_return_o <= '0';
nx_nomore_data_o <= '0';
trigger_rate_inc <= '0';
- frame_rate_inc <= '0';
pileup_rate_inc <= '0';
overflow_rate_inc <= '0';
parity_error_ctr <= (others => '0');
adc_data_o <= (others => '0');
data_clk_o <= '0';
trigger_rate_inc <= '0';
- frame_rate_inc <= '0';
pileup_rate_inc <= '0';
overflow_rate_inc <= '0';
invalid_adc <= '0';
if (new_timestamp = '1') then
adc_data_last <= adc_data;
-
+
if (parity_error = '1') then
parity_error_ctr <= parity_error_ctr + 1;
end if;
trigger_rate_inc <= '1';
if (nx_token_return_o = '1' and
- nx_token_return_pipec = "11111") then
+ nx_token_return_pipec = "1111111111") then
-- First Data Word after 5 empty Frames
adc_tr_data_p <= unsigned(adc_data_last);
adc_tr_data_c <= unsigned(adc_data);
end case;
- frame_rate_inc <= '1';
-
-- Token Return Check Handler
case TR_STATE is
when S_IDLE =>
- if (nx_token_return_pipev(4 downto 0) = "11111") then
+ if (nx_token_return_pipev(6 downto 0) = "1111111") then
adc_tr_value_tmp <= adc_data_last;
TR_STATE <= S_START;
else
state_debug <= "01";
when S_START =>
- if (nx_token_return_pipev = "111111111") then
+ if (nx_token_return_pipev = "111111111111") then
TR_STATE <= S_END;
- elsif (nx_token_return_pipev(5 downto 0) = "111111" or
- nx_token_return_pipev(6 downto 0) = "1111111" or
- nx_token_return_pipev(7 downto 0) = "11111111") then
+ elsif (nx_token_return_pipev( 6 downto 0) = "1111111" or
+ nx_token_return_pipev( 7 downto 0) = "11111111" or
+ nx_token_return_pipev( 8 downto 0) = "111111111" or
+ nx_token_return_pipev( 9 downto 0) = "1111111111" or
+ nx_token_return_pipev(10 downto 0) = "11111111111") then
TR_STATE <= S_START;
else
TR_STATE <= S_IDLE;
-- Token Return Pipeline
nx_token_return_pipec(0) <= nx_token_return_o;
- for I in 1 to 4 loop
+ for I in 1 to 9 loop
nx_token_return_pipec(I) <= nx_token_return_pipec(I - 1);
end loop;
if (TR_STATE /= S_END) then
nx_token_return_pipev(0) <= nx_token_return_o;
- for I in 1 to 8 loop
+ for I in 1 to 11 loop
nx_token_return_pipev(I) <= nx_token_return_pipev(I - 1);
end loop;
else
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
- nx_trigger_ctr_t <= (others => '0');
- nx_trigger_ctr_t_nr <= (others => '0');
- nx_frame_ctr_t <= (others => '0');
nx_rate_timer <= (others => '0');
- nx_hit_rate <= (others => '0');
- nx_frame_rate <= (others => '0');
+
+ nx_trigger_ctr_t <= (others => '0');
+ frame_ctr_t <= (others => '0');
adc_tr_error_ctr_t <= (others => '0');
- adc_tr_error_ctr <= (others => '0');
+ adc_tr_update_ctr_t <= (others => '0');
+ adc_tr_data_ctr_t <= (others => '0');
+
+ nx_hit_rate <= (others => '0');
+ frame_rate <= (others => '0');
adc_tr_error_rate <= (others => '0');
+ adc_tr_update_rate <= (others => '0');
+ adc_tr_data_rate <= (others => '0');
+
+ nx_trigger_ctr_t_nr <= (others => '0');
+ adc_tr_error_ctr <= (others => '0');
else
if (nx_rate_timer < x"5f5e100") then
if (trigger_rate_inc = '1') then
nx_trigger_ctr_t <= nx_trigger_ctr_t + 1;
nx_trigger_ctr_t_nr <= nx_trigger_ctr_t_nr + 1;
end if;
- if (frame_rate_inc = '1') then
- nx_frame_ctr_t <= nx_frame_ctr_t + 1;
+ if (new_timestamp = '1') then
+ frame_ctr_t <= frame_ctr_t + 1;
end if;
if (pileup_rate_inc = '1') then
nx_pileup_ctr_t <= nx_pileup_ctr_t + 1;
adc_tr_error_ctr_t <= adc_tr_error_ctr_t + 1;
adc_tr_error_ctr <= adc_tr_error_ctr + 1;
end if;
+ if (adc_tr_value_update = '1') then
+ adc_tr_update_ctr_t <= adc_tr_update_ctr_t + 1;
+ end if;
+ if (adc_tr_data_clk = '1') then
+ adc_tr_data_ctr_t <= adc_tr_data_ctr_t + 1;
+ end if;
+
nx_rate_timer <= nx_rate_timer + 1;
else
nx_hit_rate <= nx_trigger_ctr_t;
- nx_frame_rate <= nx_frame_ctr_t;
+ frame_rate <= frame_ctr_t;
nx_pileup_rate <= nx_pileup_ctr_t;
nx_overflow_rate <= nx_overflow_ctr_t;
adc_tr_error_rate <= adc_tr_error_ctr_t;
-
+ adc_tr_update_rate <= adc_tr_update_ctr_t;
+ adc_tr_data_rate <= adc_tr_data_ctr_t;
+
nx_trigger_ctr_t(27 downto 1) <= (others => '0');
nx_trigger_ctr_t(0) <= trigger_rate_inc;
- nx_frame_ctr_t(27 downto 1) <= (others => '0');
- nx_frame_ctr_t(0) <= frame_rate_inc;
+ frame_ctr_t(27 downto 1) <= (others => '0');
+ frame_ctr_t(0) <= new_timestamp;
nx_pileup_ctr_t(27 downto 1) <= (others => '0');
nx_pileup_ctr_t(0) <= pileup_rate_inc;
adc_tr_error_ctr_t(27 downto 0) <= (others => '0');
adc_tr_error_ctr_t(0) <= adc_tr_error;
+
+ adc_tr_update_ctr_t(27 downto 0) <= (others => '0');
+ adc_tr_update_ctr_t(0) <= adc_tr_value_update;
+
+ adc_tr_data_ctr_t(27 downto 0) <= (others => '0');
+ adc_tr_data_ctr_t(0) <= adc_tr_data_clk;
nx_rate_timer <= (others => '0');
end if;
lower_limit := unsigned(adc_tr_value) - adc_tr_limit;
adc_tr_error <= '0';
- if (adc_tr_data_clk = '1') then
+ if (adc_tr_data_clk = '1' and DISABLE_ADC_IN = '0') then
if (adc_tr_data_p > lower_limit) then
adc_tr_debug_p <= '1';
end if;
end process PROC_ADC_TOKEN_RETURN;
- PROC_ADC_TOKEN_RETURN_ERROR: process(CLK_IN)
+ PROC_ERROR_HANDLER: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
- error_o <= '0';
+ frame_rate_error <= '0';
+ error_o <= '0';
else
if (adc_tr_error_rate > x"0000020" and DISABLE_ADC_IN = '0') then
- error_o <= '1';
+ error_o <= '1';
else
- error_o <= '0';
+ error_o <= '0';
+ end if;
+
+ if ((frame_rate < x"1dc_d64e" or
+ frame_rate > x"1dc_d652")) then
+ frame_rate_error <= '1';
+ else
+ frame_rate_error <= '0';
end if;
end if;
end if;
- end process PROC_ADC_TOKEN_RETURN_ERROR;
-
+ end process PROC_ERROR_HANDLER;
+
+ PROC_DATA_STREAM_DELTA_T: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN)) then
+ if (RESET_IN = '1') then
+ new_timestamp_shift <= (others => '0');
+ frame_dt_error_ctr <= (others => '0');
+ frame_dt_error <= '0';
+ else
+ -- Frame
+ new_timestamp_shift(0) <= new_timestamp;
+ new_timestamp_shift(3 downto 1) <= new_timestamp_shift(2 downto 0);
+
+ case new_timestamp_shift is
+ when "1100" | "1110" | "1111" | "0000" =>
+ frame_dt_error_ctr <= frame_dt_error_ctr + 1;
+ frame_dt_error <= '1';
+
+ when others =>
+ frame_dt_error <= '0';
+
+ end case;
+
+ end if;
+ end if;
+ end process PROC_DATA_STREAM_DELTA_T;
+
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
when x"0001" =>
slv_data_out_o(27 downto 0) <=
- std_logic_vector(nx_frame_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
+ std_logic_vector(frame_rate);
+ slv_data_out_o(30 downto 28) <= (others => '0');
+ slv_data_out_o(31) <= frame_rate_error;
slv_ack_o <= '1';
-
+
when x"0002" =>
+ slv_data_out_o(15 downto 0)
+ <= std_logic_vector(parity_error_ctr);
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0003" =>
+ slv_data_out_o(15 downto 0) <=
+ std_logic_vector(invalid_frame_ctr);
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0004" =>
slv_data_out_o(27 downto 0) <=
std_logic_vector(nx_pileup_rate);
slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
- when x"0003" =>
+ when x"0005" =>
slv_data_out_o(27 downto 0) <=
std_logic_vector(nx_overflow_rate);
slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0004" =>
- slv_data_out_o(3 downto 0) <=
- std_logic_vector(adc_average_divisor);
- slv_data_out_o(31 downto 4) <= (others => '0');
slv_ack_o <= '1';
-
- when x"0005" =>
- slv_data_out_o(11 downto 0) <= std_logic_vector(adc_average);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
-
+
when x"0006" =>
slv_data_out_o(1 downto 0) <= adc_tr_error_status;
slv_data_out_o(31 downto 2) <= (others => '0');
slv_ack_o <= '1';
when x"0009" =>
- slv_data_out_o(15 downto 0)
- <= std_logic_vector(parity_error_ctr);
- slv_data_out_o(31 downto 16) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(27 downto 0)
+ <= std_logic_vector(adc_tr_update_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
when x"000a" =>
+ slv_data_out_o(27 downto 0)
+ <= std_logic_vector(adc_tr_data_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000b" =>
slv_data_out_o(11 downto 0)
<= std_logic_vector(adc_tr_limit);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
- when x"000b" =>
- slv_data_out_o(11 downto 0)
- <= std_logic_vector(adc_tr_error_ctr);
+ when x"000c" =>
+ slv_data_out_o(11 downto 0) <= std_logic_vector(adc_average);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
- when x"000c" =>
+
+ when x"000d" =>
+ slv_data_out_o(3 downto 0) <=
+ std_logic_vector(adc_average_divisor);
+ slv_data_out_o(31 downto 4) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000e" =>
slv_data_out_o(15 downto 0) <=
std_logic_vector(pileup_ctr);
slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
- when x"000d" =>
+ when x"000f" =>
slv_data_out_o(15 downto 0) <=
std_logic_vector(overflow_ctr);
slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
- when x"000e" =>
- slv_data_out_o(15 downto 0) <=
- std_logic_vector(invalid_frame_ctr);
- slv_data_out_o(31 downto 16) <= (others => '0');
+ when x"0010" =>
+ slv_data_out_o(11 downto 0)
+ <= std_logic_vector(adc_tr_error_ctr);
+ slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
- when x"000f" =>
+
+ when x"0011" =>
slv_data_out_o(0) <= adc_tr_debug_mode;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
- when x"0010" =>
+ when x"0012" =>
slv_data_out_o <= nx_trigger_ctr_t_nr;
slv_ack_o <= '1';
+ when x"0013" =>
+ slv_data_out_o(15 downto 0) <= frame_dt_error_ctr;
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
when others =>
slv_unknown_addr_o <= '1';
slv_ack_o <= '0';
when x"0000" =>
clear_counters <= '1';
slv_ack_o <= '1';
-
- when x"0004" =>
- adc_average_divisor <= SLV_DATA_IN(3 downto 0);
- slv_ack_o <= '1';
-
- when x"000a" =>
+
+ when x"000b" =>
adc_tr_limit
<= unsigned(SLV_DATA_IN(11 downto 0));
slv_ack_o <= '1';
- when x"000f" =>
+ when x"000d" =>
+ adc_average_divisor <= SLV_DATA_IN(3 downto 0);
+ slv_ack_o <= '1';
+
+ when x"0011" =>
adc_tr_debug_mode <= SLV_DATA_IN(0);
slv_ack_o <= '1';
-----------------------------------------------------------------------------
-- Send data to FIFO
- fifo_32_data_1: fifo_32_data
+ fifo_32_data_1: entity work.fifo_32_data
port map (
Data => fifo_next_word,
Clock => CLK_IN,
SMALL: if (BUS_WIDTH = 7) generate
- ram_dp_COUNTER_HIST: ram_dp_128x40
+ ram_dp_COUNTER_HIST: entity work.ram_dp_128x40
port map (
WrAddress => write_address_hist,
RdAddress => read_address_hist,
Q(39 downto 32) => read_data_ctr_hist
);
- ram_dp_RESULT_HIST: ram_dp_128x32
+ ram_dp_RESULT_HIST: entity work.ram_dp_128x32
port map (
WrAddress => write_address,
RdAddress => read_address,
LARGE: if (BUS_WIDTH = 9) generate
- ram_dp_COUNTER_HIST: ram_dp_512x40
+ ram_dp_COUNTER_HIST: entity work.ram_dp_512x40
port map (
WrAddress => write_address_hist,
RdAddress => read_address_hist,
Q(39 downto 32) => read_data_ctr_hist
);
- ram_dp_RESULT_HIST: ram_dp_512x32
+ ram_dp_RESULT_HIST: entity work.ram_dp_512x32
port map (
WrAddress => write_address,
RdAddress => read_address,
slv_ack_o <= '1';
when x"000a" =>
- status_trigger_type <= SLV_DATA_IN(3 downto 0);
+ calibration_trigger_type <= SLV_DATA_IN(3 downto 0);
slv_ack_o <= '1';
when others =>
signal reset_hists_o : std_logic;
-- Timestamp Trigger Window Settings
- signal nxyter_cv_time : unsigned(11 downto 0);
- signal cts_trigger_delay : unsigned(11 downto 0);
- signal ts_window_offset : signed(11 downto 0);
- signal ts_window_width : unsigned(9 downto 0);
- signal readout_time_max : unsigned(11 downto 0);
- signal fpga_timestamp_offset : unsigned(11 downto 0);
-
- signal state_d : std_logic_vector(1 downto 0);
+ signal nxyter_cv_time : unsigned(11 downto 0);
+ signal cts_trigger_delay : unsigned(11 downto 0);
+ signal trigger_calibration_delay : unsigned(11 downto 0);
+ signal ts_window_offset : signed(11 downto 0);
+ signal ts_window_width : unsigned(9 downto 0);
+ signal readout_time_max : unsigned(11 downto 0);
+ signal fpga_timestamp_offset : unsigned(11 downto 0);
+
+ signal state_d : std_logic_vector(1 downto 0);
+ -----------------------------------------------------------------------------
+
attribute syn_keep : boolean;
attribute syn_keep of timestamp_fpga_ff : signal is true;
attribute syn_keep of timestamp_fpga_f : signal is true;
-- Calculate Thresholds and values for FIFO Delay
-----------------------------------------------------------------------
- if (trigger_calibration = '0') then
- cts_trigger_delay_tmp := cts_trigger_delay;
- else
- cts_trigger_delay_tmp := (others => '0');
- end if;
-
+ cts_trigger_delay_tmp := cts_trigger_delay;
+
if (ts_window_offset(11) = '1') then
-- Offset is negative
ts_window_offset_unsigned :=
-- Final lower Threshold value relative to TS Reference TS
window_lower_thr := timestamp_fpga - window_lower_thr;
-
window_upper_thr :=
window_lower_thr + resize(ts_window_width, 12);
+
ts_window_check_value :=
unsigned(TIMESTAMP_IN(13 downto 2)) - window_lower_thr;
-
+
-- Timestamp to be stored
deltaTStore(13 downto 2) := ts_window_check_value;
deltaTStore( 1 downto 0) := unsigned(TIMESTAMP_IN(1 downto 0));
min_validation_time + wait_for_data_time;
wait_for_data_time := x"00001";
end if;
+
+ if (trigger_calibration = '1') then
+ min_validation_time :=
+ min_validation_time + resize(trigger_calibration_delay, 20);
+ end if;
+
min_validation_time_r <= min_validation_time;
wait_for_data_time_r <= wait_for_data_time;
timestamp_fpga <=
timestamp_fpga_f + fpga_timestamp_offset;
end if;
+
+ if (trigger_calibration = '1') then
+ timestamp_fpga <=
+ timestamp_fpga_f + trigger_calibration_delay;
+ end if;
STATE <= S_WRITE_HEADER;
end if;
histogram_limits <= '0';
histogram_trig_filter <= '0';
histogram_ts_range <= "100";
+ trigger_calibration_delay <= x"190"; -- 400ns
else
slv_data_out_o <= (others => '0');
slv_unknown_addr_o <= '0';
when x"0003" =>
slv_data_out_o(9 downto 0) <=
std_logic_vector(cts_trigger_delay(9 downto 0));
- slv_data_out_o(31 downto 10) <= (others => '0');
+ slv_data_out_o(15 downto 10) <= (others => '0');
+ slv_data_out_o(27 downto 16) <=
+ std_logic_vector(trigger_calibration_delay);
+ slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
when x"0004" =>
when x"001a" =>
slv_data_out_o(11 downto 0) <=
std_logic_vector(nxyter_cv_time);
- slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"001b" =>
slv_data_out_o(19 downto 0) <=
std_logic_vector(min_validation_time_r);
when x"0003" =>
cts_trigger_delay(9 downto 0) <=
unsigned(SLV_DATA_IN(9 downto 0));
+ trigger_calibration_delay <=
+ unsigned(SLV_DATA_IN(27 downto 16));
slv_ack_o <= '1';
when x"0004" =>
when x"0020" =>
histogram_lower_limit <= SLV_DATA_IN(13 downto 0);
histogram_upper_limit <= SLV_DATA_IN(28 downto 15);
- reset_hists <= SLV_DATA_IN(29);
histogram_limits <= SLV_DATA_IN(30);
histogram_trig_filter <= SLV_DATA_IN(31);
+ reset_hists <= '1';
slv_ack_o <= '1';
when x"0021" =>
+ reset_hists <= '1';
histogram_ts_range <= SLV_DATA_IN(2 downto 0);
slv_ack_o <= '1';
SPI_SCLK_OUT : out std_logic;
SPI_SDIO_INOUT : inout std_logic;
SPI_CSB_OUT : out std_logic;
- NX_DATA_CLK_IN : in std_logic;
+ NX_TIMESTAMP_CLK_IN : in std_logic;
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
NX_RESET_OUT : out std_logic;
NX_TESTPULSE_OUT : out std_logic;
);
end component;
-component adc_ddr_generic
- port (
- clk_0 : in std_logic;
- clk_1 : in std_logic;
- clkdiv_reset : in std_logic;
- eclk : in std_logic;
- reset_0 : in std_logic;
- reset_1 : in std_logic;
- sclk : out std_logic;
- datain_0 : in std_logic_vector(4 downto 0);
- datain_1 : in std_logic_vector(4 downto 0);
- q_0 : out std_logic_vector(19 downto 0);
- q_1 : out std_logic_vector(19 downto 0)
- );
-end component;
-
-component ddr_generic_single
- port (
- clk_0 : in std_logic;
- clkdiv_reset : in std_logic;
- eclk : in std_logic;
- reset_0 : in std_logic;
- sclk : out std_logic;
- datain_0 : in std_logic_vector(4 downto 0);
- q_0 : out std_logic_vector(19 downto 0)
- );
-end component;
-
-component fifo_adc_48to48_dc
- port (
- Data : in std_logic_vector(47 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(47 downto 0);
- Empty : out std_logic;
- Full : out std_logic
- );
-end component;
-
-------------------------------------------------------------------------------
-- TRBNet Registers
-------------------------------------------------------------------------------
);
end component;
-component clock10MHz
- port (
- CLK : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
component fifo_data_stream_44to44_dc
port (
Data : in std_logic_vector(43 downto 0);
);
end component;
-component dynamic_shift_register8x64
- port (
- Din : in std_logic_vector(7 downto 0);
- Addr : in std_logic_vector(5 downto 0);
- Clock : in std_logic;
- ClockEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(7 downto 0)
- );
-end component;
-
-component ram_fifo_delay_256x44
- port (
- WrAddress : in std_logic_vector(7 downto 0);
- RdAddress : in std_logic_vector(7 downto 0);
- Data : in std_logic_vector(43 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(43 downto 0)
- );
-end component;
-
component fifo_44_data_delay_my
port (
Data : in std_logic_vector(43 downto 0);
);
end component;
-component fifo_32_data
- port (
- Data : in std_logic_vector(31 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- AmFullThresh : in std_logic_vector(10 downto 0);
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
- );
-end component;
-
component nx_data_receiver
generic (
DEBUG_ENABLE : boolean
);
end component;
-component ram_dp_128x40
- port (
- WrAddress : in std_logic_vector(6 downto 0);
- RdAddress : in std_logic_vector(6 downto 0);
- Data : in std_logic_vector(39 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(39 downto 0)
- );
-end component;
-
-component ram_dp_128x32
- port (
- WrAddress : in std_logic_vector(6 downto 0);
- RdAddress : in std_logic_vector(6 downto 0);
- Data : in std_logic_vector(31 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(31 downto 0)
- );
-end component;
-
-component ram_dp_512x40
- port (
- WrAddress : in std_logic_vector(8 downto 0);
- RdAddress : in std_logic_vector(8 downto 0);
- Data : in std_logic_vector(39 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(39 downto 0)
- );
-end component;
-
-component ram_dp_512x32
- port (
- WrAddress : in std_logic_vector(8 downto 0);
- RdAddress : in std_logic_vector(8 downto 0);
- Data : in std_logic_vector(31 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(31 downto 0)
- );
-end component;
-
-------------------------------------------------------------------------------
component level_to_pulse
);
end component;
--------------------------------------------------------------------------------
--- PLLs
--------------------------------------------------------------------------------
-
-component pll_nx_clk250
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
-component pll_adc_clk
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
-component pll_adc_sampling_clk
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- FINEDELB0 : in std_logic;
- FINEDELB1 : in std_logic;
- FINEDELB2 : in std_logic;
- FINEDELB3 : in std_logic;
- DPHASE0 : in std_logic;
- DPHASE1 : in std_logic;
- DPHASE2 : in std_logic;
- DPHASE3 : in std_logic;
- CLKOP : out std_logic;
- CLKOS : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
component nx_fpga_timestamp
port (
CLK_IN : in std_logic;
SPI_CSB_OUT : out std_logic;
-- nXyter Timestamp Ports
- NX_DATA_CLK_IN : in std_logic;
+ NX_TIMESTAMP_CLK_IN : in std_logic;
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
NX_RESET_OUT : out std_logic;
NX_TESTPULSE_OUT : out std_logic;
error_all(0) <= error_data_receiver;
error_all(1) <= error_data_validate;
error_all(2) <= error_event_buffer;
- error_all(7 downto 3) <= (others => '0');
+ error_all(3) <= not nxyter_online;
+ error_all(7 downto 4) <= (others => '0');
-------------------------------------------------------------------------------
-- Port Maps
9 => 9, -- NX Register Setup
10 => 11, -- NX Histograms
11 => 0, -- Debug Handler
- 12 => 1, -- Data Delay
+ 12 => 3, -- Data Delay
others => 0
),
NX_ONLINE_IN => nxyter_online,
NX_CLOCK_ON_IN => nxyter_clock_on,
- NX_DATA_CLK_IN => NX_DATA_CLK_IN,
+ NX_DATA_CLK_IN => NX_TIMESTAMP_CLK_IN,
NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset,
# Basic Settings
#################################################################
- # nXyter FEB Clock Setup:
- #
- # CLK_PCLK_RIGHT : real Oszillator 200MHz
- # CLK_PCLK_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities
- #
- # CLK_PCLK_RIGHT --> nx_main_clk 1+2
- # (250 MHz) -----> nXyter Main Clock 1+2
- # |
- # |----> FPGA Timestamp Entity 1+2
- #
- # nx_main_clk 1+2 --> nXyter Data Clk
- # (1/2 = 125MHz) -----> FPGA Data Receiver
- # |
- # |----> Johnson 1/4 --> ADC SCLK
- #
- # CLK_PCLK_RIGHT (PLL#2) --> clk_adc_dat_1
- # (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 1
- #
- # CLK_PCLK_RIGHT (PLL#3) --> clk_adc_dat_2
- # (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 2
-
- # Speed for the configuration Flash access
- SYSCONFIG MCCLK_FREQ = 20;
-
- FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
- FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz;
-
- USE PRIMARY NET "nx_main_clk_c";
- USE PRIMARY NET "clk_100_i_c";
- USE PRIMARY NET "CLK_PCLK_RIGHT_c";
+# nXyter FEB Clock Setup:
+#
+# CLK_PCLK_RIGHT : real Oszillator 200MHz
+# CLK_PCLK_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities
+#
+# CLK_PCLK_RIGHT --> nx_main_clk 1+2
+# (250 MHz) -----> nXyter Main Clock 1+2
+# |
+# |----> FPGA Timestamp Entity 1+2
+#
+# nx_main_clk 1+2 --> nXyter Data Clk
+# (1/2 = 125MHz) -----> FPGA Data Receiver
+# |
+# |----> Johnson 1/4 --> ADC SCLK
+#
+# CLK_PCLK_RIGHT (PLL#2) --> clk_adc_dat_1
+# (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 1
+#
+# CLK_PCLK_RIGHT (PLL#3) --> clk_adc_dat_2
+# (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 2
+
+# Speed for the configuration Flash access
+SYSCONFIG MCCLK_FREQ = 20;
+
+FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz;
+
+#USE PRIMARY NET "nx_main_clk_c";
+#USE PRIMARY NET "clk_100_i_c";
+#USE PRIMARY NET "CLK_PCLK_RIGHT_c";
+
+FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz;
+
+USE PRIMARY NET "nx_main_clk_c";
+USE PRIMARY NET "clk_100_i_c";
+USE PRIMARY NET "CLK_PCLK_RIGHT_c";
+USE EDGE2EDGE NET "NX_CLK_ADC_DAT";
+USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c";
+
+#PRIORITIZE NET "NX1_DATA_CLK_IN_c" 40;
+#PRIORITIZE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c" 50;
#################################################################
# Reset Nets
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 100 ns;
+
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 500 ns;
+
+MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ;
+MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ;
+MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ;
+MAXDELAY TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ;
#SPI Interface
REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE;
PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c";
DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX1_IN" 0.5 ns HOLD 0.5 ns CLKPORT="NX1_DATA_CLK_IN";
+INPUT_SETUP GROUP "NX1_IN" 1.5 ns HOLD 1.5 ns CLKPORT="NX1_DATA_CLK_IN";
-UGROUP NXYTER1 BBOX 100 70
- BLKNAME nXyter_FEE_board_0;
-LOCATE UGROUP NXYTER1 SITE "R2C2D";
+#UGROUP NXYTER1 BBOX 100 70
+ #BLKNAME nXyter_FEE_board_0;
+#LOCATE UGROUP NXYTER1 SITE "R2C2D";
-w
-i 2
-l 5
--n 20
--t 5
+-n 20
+-t 1
-s 1
-c 1
-e 2
SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT,
SPI_CSB_OUT => NX1_SPI_CSB_OUT,
- NX_DATA_CLK_IN => NX1_DATA_CLK_IN,
+ NX_TIMESTAMP_CLK_IN => NX1_DATA_CLK_IN,
NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN,
NX_RESET_OUT => NX1_RESET_OUT,
-- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be
-- based on same ClockSource as nXyter Main Clock)
- pll_adc_clk_1: pll_adc_clk
+ pll_adc_clk_1: entity work.pll_adc_clk
port map (
CLK => CLK_PCLK_RIGHT,
RESET => nx_pll_reset,
jspc29 / trb3.git / commitdiff