fifo_18x16_dualport_oreg_xcku: Add missing ports

diff --git a/xilinx/xcku/lattice_ecp3_fifo_18x16_dualport_oreg.vhd b/xilinx/xcku/lattice_ecp3_fifo_18x16_dualport_oreg.vhd
index b49437d89cb4afaab8256b648211e26c562c9354..44c66e40f00979e7b078e2c674acc47214230b02 100644 (file)
--- a/xilinx/xcku/lattice_ecp3_fifo_18x16_dualport_oreg.vhd
+++ b/xilinx/xcku/lattice_ecp3_fifo_18x16_dualport_oreg.vhd
@@ -20,30 +20,34 @@ end entity lattice_ecp3_fifo_18x16_dualport_oreg;
 architecture structural of lattice_ecp3_fifo_18x16_dualport_oreg is
     component fifo_18x16_dualport_oreg_xcku
         port (
-            rst       :  in std_logic;
-            wr_clk    :  in std_logic;
-            rd_clk    :  in std_logic;
-            din       :  in std_logic_vector(17 downto 0);
-            wr_en     :  in std_logic;
-            rd_en     :  in std_logic;
-            dout      : out std_logic_vector(17 downto 0);
-            full      : out std_logic;
-            empty     : out std_logic;
-            prog_full : out std_logic
+            rst         :  in std_logic;
+            wr_clk      :  in std_logic;
+            rd_clk      :  in std_logic;
+            din         :  in std_logic_vector(17 downto 0);
+            wr_en       :  in std_logic;
+            rd_en       :  in std_logic;
+            dout        : out std_logic_vector(17 downto 0);
+            full        : out std_logic;
+            empty       : out std_logic;
+            prog_full   : out std_logic;
+            wr_rst_busy : out std_logic;
+            rd_rst_busy : out std_logic
         );
     end component;
 begin
     fifo : fifo_18x16_dualport_oreg_xcku
     port map (
-        rst       => Reset,
-        wr_clk    => WrClock,
-        rd_clk    => RdClock,
-        din       => Data,
-        wr_en     => WrEn,
-        rd_en     => RdEn,
-        dout      => Q,
-        full      => Full,
-        empty     => Empty,
-        prog_full => AlmostFull
+        rst         => Reset,
+        wr_clk      => WrClock,
+        rd_clk      => RdClock,
+        din         => Data,
+        wr_en       => WrEn,
+        rd_en       => RdEn,
+        dout        => Q,
+        full        => Full,
+        empty       => Empty,
+        prog_full   => AlmostFull,
+        wr_rst_busy => open,
+        rd_rst_busy => open
     );
 end architecture structural;