use work.trb3_components.all;
use work.config.all;
+-- REMARK: USE_RXCLOCK doesnt't make sense here, can be removed
+-- REMARK: USE_EXTERNAL_CLOCK seems to be mandatory, can be simplified
+-- REMARK: RESET_ROM_NET should be RESET_FROM_NET_IN
+
entity clock_reset_handler is
- port (
- INT_CLK_IN : in std_logic; -- oscillator
- EXT_CLK_IN : in std_logic; -- external clock input
- NET_CLK_FULL_IN : in std_logic; -- recovered clock
- NET_CLK_HALF_IN : in std_logic;
- RESET_FROM_NET : in std_logic := '0';
- SEND_RESET_IN : in std_logic := '0';
+ port(
+ INT_CLK_IN : in std_logic; -- oscillator
+ EXT_CLK_IN : in std_logic; -- external clock input
+ NET_CLK_FULL_IN : in std_logic; -- TO BE REMOVED
+ NET_CLK_HALF_IN : in std_logic; -- TO BE REMOVED
+ GLOBAL_RESET_IN : in std_logic; -- from Link Layer
+ RESET_FROM_NET_IN : in std_logic := '0'; -- stat_op(13)
+ SEND_RESET_IN : in std_logic := '0'; -- stat_op(15)
- BUS_RX : in CTRLBUS_RX;
- BUS_TX : out CTRLBUS_TX;
+ BUS_RX : in CTRLBUS_RX; -- NOT USED
+ BUS_TX : out CTRLBUS_TX; -- NOT USED
- RESET_OUT : out std_logic;
- CLEAR_OUT : out std_logic;
- GSR_OUT : out std_logic;
+ RESET_OUT : out std_logic;
+ CLEAR_OUT : out std_logic;
+ GSR_OUT : out std_logic;
- FULL_CLK_OUT : out std_logic; -- 200/240 MHz for FPGA fabric
- SYS_CLK_OUT : out std_logic; -- 100/120 MHz for FPGA fabric
- REF_CLK_OUT : out std_logic; -- 200/240 internal reference clock
+ FULL_CLK_OUT : out std_logic; -- 200/240 MHz for FPGA fabric
+ SYS_CLK_OUT : out std_logic; -- 100/120 MHz for FPGA fabric
+ REF_CLK_OUT : out std_logic; -- 200/240 internal reference clock
- ENPIRION_CLOCK : out std_logic;
- LED_RED_OUT : out std_logic_vector( 1 downto 0);
- LED_GREEN_OUT : out std_logic_vector( 1 downto 0);
- DEBUG_OUT : out std_logic_vector(31 downto 0)
- );
+ ENPIRION_CLOCK : out std_logic;
+ LED_RED_OUT : out std_logic_vector( 1 downto 0);
+ LED_GREEN_OUT : out std_logic_vector( 1 downto 0);
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
end entity;
architecture clock_reset_handler_arch of clock_reset_handler is
begin
+assert not (USE_RXCLOCK = c_YES) report "USE_RXCLOCK is not supported anymore" severity error;
+assert not (USE_EXTERNAL_CLOCK = c_NO) report "USE_EXTERNAL_CLOCK is mandatory" severity error;
assert not (USE_RXCLOCK = c_YES and USE_200MHZOSCILLATOR = c_YES) report "RX Clock and 200 MHz oscillator not implemented" severity error;
assert not (USE_120_MHZ = c_YES and USE_200MHZOSCILLATOR = c_YES) report "120 MHz with 200 MHz oscillator not implemented" severity error;
LED_RED_OUT(0) <= '0' when USE_RXCLOCK = c_YES else '1';
LED_GREEN_OUT(0) <= '0' when USE_RXCLOCK = c_NO else '1';
-LED_GREEN_OUT(1) <= '0';
LED_RED_OUT(1) <= clock_select;
+LED_GREEN_OUT(1) <= '0';
-GSR_OUT <= not pll_int_lock or clear_n_i;
+GSR_OUT <= not pll_int_lock or clear_n_i; -- keeps everything in reset until a valid FPGA fabric clock is available
---------------------------------------------------------------------------
-- if RX clock is used, just forward what is provided, adjust internal as reference
CLKOP => clk_int_full,
CLKOK => clk_int_half,
LOCK => pll_int_lock
- );
+ );
clk_selected_ref <= clk_int_full;
end generate;
end generate;
end generate;
-
---------------------------------------------------------------------------
-- No recovered clock
---------------------------------------------------------------------------
gen_norecov_clock : if USE_RXCLOCK = c_NO generate
- clk_selected_ref <= clk_selected_full; --clk_int_full; --
+ clk_selected_ref <= clk_selected_full;
---------------------------------------------------------------------------
-- Make internal clock 200 MHz if required
CLKOS => clk_int_full, --same as OP, but for DCS
CLKOK => clk_int_half, --100
LOCK => pll_int_lock
- );
+ );
end generate;
gen_osc200 : if USE_200MHZOSCILLATOR = c_YES generate
THE_INT_PLL : entity work.pll_in200_out200
CLKOS => clk_int_full, --same as OP, but for DCS
CLKOK => clk_int_half, --100
LOCK => pll_int_lock
- );
+ );
end generate;
gen_ext_pll : if USE_EXTERNAL_CLOCK = c_YES generate
CLKOS => clk_ext_half, --same as OP, but for DCS
CLKOK => clk_ext_full, --200, bypassed
LOCK => pll_ext_lock
- );
+ );
end generate;
end generate;
CLKOP => clk_int_half,
CLKOK => clk_int_full,
LOCK => pll_int_lock
- );
+ );
gen_ext_pll : if USE_EXTERNAL_CLOCK = c_YES generate
THE_EXT_PLL : entity work.pll_in240_out240
CLKOP => clk_ext_half,
CLKOK => clk_ext_full,
LOCK => pll_ext_lock
- );
+ );
end generate;
end generate;
-
---------------------------------------------------------------------------
-- Select clocks
---------------------------------------------------------------------------
CLK0 => clk_int_full,
CLK1 => clk_ext_full,
DCSOUT => clk_selected_full
- );
+ );
THE_CLOCK_SWITCH_HALF: DCS
port map(
SEL => clock_select,
CLK0 => clk_int_half,
CLK1 => clk_ext_half,
DCSOUT => clk_selected_half
- );
+ );
end generate;
gen_direct_clock : if USE_EXTERNAL_CLOCK = c_NO generate
clk_selected_half <= clk_int_half;
clk_selected_full <= clk_int_full;
end generate;
-
-
+
---------------------------------------------------------------------------
-- Clock switch logic
---------------------------------------------------------------------------
-
process begin
wait until rising_edge(INT_CLK_IN);
if timer(26-CLOCK_FAST_SELECT*11) = '0' and timer(27-CLOCK_FAST_SELECT*11) = '0' then
timer <= timer + 1;
end if;
end process;
-
-
+
end generate;
clear_n_i <= timer(27-CLOCK_FAST_SELECT*11) when rising_edge(INT_CLK_IN);
RESET_DELAY => x"FEEE"
)
port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => clear_n_i, -- reset input (low active, async)
- CLK_IN => INT_CLK_IN, -- raw master clock, NOT from PLL/DLL!
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => clear_n_i, -- reset input (low active, async)
+ CLK_IN => INT_CLK_IN, -- raw master clock, NOT from PLL/DLL!
SYSCLK_IN => clk_selected_half, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_int_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => trb_reset_i, -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => trb_reset_i, -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
DEBUG_OUT => debug_reset_handler
);
-RESET_OUT <= reset_i;
+RESET_OUT <= reset_i;
send_reset_detect <= SEND_RESET_IN when rising_edge(INT_CLK_IN);
-trb_reset_i <= RESET_FROM_NET or (send_reset_detect and not SEND_RESET_IN);
+trb_reset_i <= RESET_FROM_NET_IN or (send_reset_detect and not SEND_RESET_IN);
---------------------------------------------------------------------------
-- Slow clock for DCDC converters
RESET => reset_i,
CLKOP => ENPIRION_CLOCK,
LOCK => open
- );
-
+ );
DEBUG_OUT(0) <= pll_int_lock;
DEBUG_OUT(1) <= clear_n_i;
DEBUG_OUT(15) <= clock_select;
DEBUG_OUT(31 downto 16) <= (others => '0');
-BUS_TX.data <= (others => '0');
+BUS_TX.data <= (others => '0');
BUS_TX.unknown <= '1';
-BUS_TX.ack <= '0';
-BUS_TX.nack <= '0';
-
-
+BUS_TX.ack <= '0';
+BUS_TX.nack <= '0';
end architecture;
signal clk_cal : std_logic;
signal GSR_N : std_logic;
signal reset_i : std_logic;
- signal clear_i : std_logic;
signal do_reboot_i : std_logic;
signal reboot_from_gbe : std_logic;
---------------------------------------------------------------------------
THE_CLOCK_RESET : entity work.clock_reset_handler
port map(
- INT_CLK_IN => CLK_CORE_PCLK,
- EXT_CLK_IN => CLK_EXT_PLL_LEFT,
- NET_CLK_FULL_IN => '0',
- NET_CLK_HALF_IN => '0',
- RESET_FROM_NET => make_reset,
- BUS_RX => bustc_rx,
- BUS_TX => bustc_tx,
- RESET_OUT => reset_i,
- CLEAR_OUT => clear_i,
- GSR_OUT => GSR_N,
- FULL_CLK_OUT => clk_full,
- SYS_CLK_OUT => clk_sys,
- REF_CLK_OUT => clk_full_osc,
- ENPIRION_CLOCK => ENPIRION_CLOCK,
- LED_RED_OUT => LED_RJ_RED,
- LED_GREEN_OUT => LED_RJ_GREEN,
- DEBUG_OUT => debug_clock_reset
+ INT_CLK_IN => CLK_CORE_PCLK,
+ EXT_CLK_IN => CLK_EXT_PLL_LEFT,
+ NET_CLK_FULL_IN => '0',
+ NET_CLK_HALF_IN => '0',
+ GLOBAL_RESET_IN => '0', -- BUG
+ RESET_FROM_NET_IN => make_reset,
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+ RESET_OUT => reset_i,
+ CLEAR_OUT => open,
+ GSR_OUT => GSR_N,
+ FULL_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ REF_CLK_OUT => clk_full_osc,
+ ENPIRION_CLOCK => ENPIRION_CLOCK,
+ LED_RED_OUT => LED_RJ_RED,
+ LED_GREEN_OUT => LED_RJ_GREEN,
+ DEBUG_OUT => debug_clock_reset
);
-- Reset by GbE: a minimum delay of 1us is kept before the reset
CLK_REF_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i, -- check
- CLEAR => reset_i, -- check
-
-- Media Interface TX/RX
MEDIA_MED2INT(0) => open,
MEDIA_MED2INT(1) => open,
-w
-l 5
-s 12
--t 32 # seed setting here! # 32
+-t 31 # seed setting here! # 32
-c 1
-e 2
-i 15
signal clk_sys, clk_full, clk_full_osc : std_logic;
signal GSR_N : std_logic;
signal reset_i : std_logic;
- signal clear_i : std_logic;
signal do_reboot_i, reboot_from_gbe : std_logic;
signal external_reset_i : std_logic;
---------------------------------------------------------------------------
THE_CLOCK_RESET : entity work.clock_reset_handler
port map(
- INT_CLK_IN => CLK_CORE_PCLK,
- EXT_CLK_IN => CLK_EXT_PLL_LEFT,
- NET_CLK_FULL_IN => med2int(INTERFACE_NUM-1).clk_full,
- NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half,
- RESET_FROM_NET => med2int(INTERFACE_NUM-1).stat_op(13),
- SEND_RESET_IN => med2int(INTERFACE_NUM-1).stat_op(15),
- --
- BUS_RX => bustc_rx,
- BUS_TX => bustc_tx,
- --
- RESET_OUT => reset_i,
- CLEAR_OUT => clear_i,
- GSR_OUT => GSR_N,
- --
- FULL_CLK_OUT => clk_full,
- SYS_CLK_OUT => clk_sys,
- REF_CLK_OUT => clk_full_osc,
- --
- ENPIRION_CLOCK => ENPIRION_CLOCK,
- LED_RED_OUT => LED_RJ_RED,
- LED_GREEN_OUT => LED_RJ_GREEN,
- DEBUG_OUT => debug_clock_reset
+ INT_CLK_IN => CLK_CORE_PCLK,
+ EXT_CLK_IN => CLK_EXT_PLL_LEFT,
+ NET_CLK_FULL_IN => med2int(INTERFACE_NUM-1).clk_full,
+ NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half,
+ GLOBAL_RESET_IN => master_reset_i, -- BUG
+ RESET_FROM_NET_IN => med2int(INTERFACE_NUM-1).stat_op(13),
+ SEND_RESET_IN => med2int(INTERFACE_NUM-1).stat_op(15),
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+ RESET_OUT => reset_i,
+ CLEAR_OUT => open,
+ GSR_OUT => GSR_N,
+ FULL_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ REF_CLK_OUT => clk_full_osc,
+ ENPIRION_CLOCK => ENPIRION_CLOCK,
+ LED_RED_OUT => LED_RJ_RED,
+ LED_GREEN_OUT => LED_RJ_GREEN,
+ DEBUG_OUT => debug_clock_reset
);
CLK_REF_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
- CLEAR => clear_i,
-- Media Interface TX/RX
MEDIA_MED2INT(0) => med2int(4),
MEDIA_MED2INT(1) => med2int(5),
CLK_REF_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
- CLEAR => clear_i,
-- Media Interface TX/RX
MEDIA_MED2INT(0) => med2int(2),
MEDIA_MED2INT(1) => med2int(3),
CLK_REF_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
- CLEAR => clear_i,
-- Media Interface TX/RX
MEDIA_MED2INT(0) => med2int(8),
MEDIA_MED2INT(1) => med2int(7),
signal clk_cal : std_logic;
signal GSR_N : std_logic;
signal reset_i : std_logic;
- signal clear_i : std_logic;
signal time_counter : unsigned(31 downto 0) := (others => '0');
signal led : std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
THE_CLOCK_RESET : entity work.clock_reset_handler
port map(
- INT_CLK_IN => CLK_CORE_PCLK,
- EXT_CLK_IN => CLK_EXT_PLL_LEFT,
- NET_CLK_FULL_IN => med2int(0).clk_full,
- NET_CLK_HALF_IN => med2int(0).clk_half,
- RESET_FROM_NET => med2int(0).stat_op(13),
- SEND_RESET_IN => med2int(0).stat_op(15),
-
- BUS_RX => bustc_rx,
- BUS_TX => bustc_tx,
-
- RESET_OUT => reset_i,
- CLEAR_OUT => clear_i,
- GSR_OUT => GSR_N,
-
- FULL_CLK_OUT => clk_full,
- SYS_CLK_OUT => clk_sys,
- REF_CLK_OUT => clk_full_osc,
-
- ENPIRION_CLOCK => ENPIRION_CLOCK,
- LED_RED_OUT => LED_RJ_RED,
- LED_GREEN_OUT => LED_RJ_GREEN,
- DEBUG_OUT => debug_clock_reset
+ INT_CLK_IN => CLK_CORE_PCLK,
+ EXT_CLK_IN => CLK_EXT_PLL_LEFT,
+ NET_CLK_FULL_IN => med2int(0).clk_full,
+ NET_CLK_HALF_IN => med2int(0).clk_half,
+ GLOBAL_RESET_IN => master_reset_i, -- BUG
+ RESET_FROM_NET_IN => med2int(0).stat_op(13),
+ SEND_RESET_IN => med2int(0).stat_op(15),
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+ RESET_OUT => reset_i,
+ CLEAR_OUT => open,
+ GSR_OUT => GSR_N,
+ FULL_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ REF_CLK_OUT => clk_full_osc,
+ ENPIRION_CLOCK => ENPIRION_CLOCK,
+ LED_RED_OUT => LED_RJ_RED,
+ LED_GREEN_OUT => LED_RJ_GREEN,
+ DEBUG_OUT => debug_clock_reset
);
gen_cal125 : if (USE_CALIBRATION_200MHZ = c_NO) generate
CLK_REF_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
- CLEAR => reset_i,
-- Media Interface TX/RX
MEDIA_MED2INT(0) => open,
MEDIA_MED2INT(1) => open,
jspc29 / trb3sc.git / commitdiff