generic flash ctrl with generic bus width, IF

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index ee5670c5cc921682c321047d07ad4c5970c91480..7cfeeea9ae4a752b897314a0ff17fe4a1e1f069a 100644 (file)
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -30,22 +30,24 @@ library work;
 use work.trb_net_std.all;\r
 \r
 entity generic_flash_ctrl is\r
-  generic (MASTER_STARTPAGE : std_logic_vector(12 downto 0) := "1" & x"C00");\r
+  generic (MASTER_STARTPAGE : std_logic_vector(12 downto 0) := "1" & x"C00";\r
+           DATA_BUS_WIDTH   : integer := 16\r
+           );\r
   port(\r
     CLK   : in  std_logic;\r
     RESET : in  std_logic;\r
 \r
     -- SPI in host direction\r
-    SPI_DATA_IN   : in  std_logic_vector(15 downto 0);\r
-    SPI_DATA_OUT  : out std_logic_vector(15 downto 0);\r
+    SPI_DATA_IN   : in  std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
+    SPI_DATA_OUT  : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
     SPI_ADDR_IN   : in  std_logic_vector(7 downto 0);\r
     SPI_WRITE_IN  : in  std_logic;\r
     SPI_READ_IN   : in  std_logic;\r
     SPI_READY_OUT : out std_logic;\r
         \r
     -- SPI in local direction\r
-    LOC_DATA_OUT  : out std_logic_vector(15 downto 0);\r
-    LOC_DATA_IN   : in  std_logic_vector(15 downto 0);\r
+    LOC_DATA_OUT  : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
+    LOC_DATA_IN   : in  std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
     LOC_ADDR_OUT  : out std_logic_vector(7 downto 0);\r
     LOC_WRITE_OUT : out std_logic;\r
     LOC_READ_OUT  : out std_logic;\r
@@ -73,9 +75,9 @@ architecture arch of generic_flash_ctrl is
       );\r
   end component;\r
 \r
-  signal reg_SPI_DATA_OUT  : std_logic_vector(15 downto 0);\r
+  signal reg_SPI_DATA_OUT  : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
   signal reg_SPI_READY_OUT : std_logic;\r
-  signal reg_LOC_DATA_OUT  : std_logic_vector(15 downto 0);\r
+  signal reg_LOC_DATA_OUT  : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
   signal reg_LOC_ADDR_OUT  : std_logic_vector(7 downto 0);\r
   signal reg_LOC_WRITE_OUT : std_logic;\r
   signal reg_LOC_READ_OUT  : std_logic;\r
@@ -103,7 +105,7 @@ architecture arch of generic_flash_ctrl is
   signal spi_ram_addr_i  : std_logic_vector(3 downto 0);\r
   \r
   signal enable_cfg_flash : std_logic;\r
-  signal testreg : std_logic_vector(15 downto 0);\r
+  signal testreg : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
 \r
   signal out_delay : std_logic_vector(1 downto 0);\r
   \r
@@ -117,7 +119,7 @@ architecture arch of generic_flash_ctrl is
   signal master_flash_go      : std_logic;\r
   signal master_start_reg     : std_logic := '0';\r
   signal clean_master_start_reg : std_logic := '0';\r
-  signal master_DATA_OUT  : std_logic_vector(15 downto 0);\r
+  signal master_DATA_OUT  : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);\r
   signal master_ADDR_OUT  : std_logic_vector(7 downto 0);\r
   signal master_WRITE_OUT : std_logic;\r
   \r
@@ -179,7 +181,7 @@ PROC_SELECTOR : process begin
   reg_LOC_READ_OUT  <= SPI_READ_IN;\r
   reg_SPI_DATA_OUT  <= LOC_DATA_IN;\r
   reg_SPI_READY_OUT <= LOC_READY_IN;\r
-\r
+  \r
   ram_write_i <= '0';\r
   ram_data_i <= x"00";\r
   spi_ram_addr_i <= x"0";\r
@@ -221,7 +223,10 @@ PROC_SELECTOR : process begin
     reg_LOC_ADDR_OUT  <= master_ADDR_OUT;\r
   end if;\r
   \r
-  \r
+  if (DATA_BUS_WIDTH-1 > 15) then\r
+    reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 16) <= (others => '0');\r
+  end if;\r
+\r
   if (out_delay = "01") then\r
     reg_LOC_READ_OUT  <= '0';\r
     reg_SPI_READY_OUT <= '0';\r
@@ -229,13 +234,13 @@ PROC_SELECTOR : process begin
   elsif (out_delay = "10") then\r
     reg_LOC_READ_OUT  <= '0';\r
     reg_SPI_READY_OUT <= '1';\r
-    reg_SPI_DATA_OUT  <= flash_busy & flash_err & "000000" & ram_data_o;\r
+    reg_SPI_DATA_OUT(15 downto 0) <= flash_busy & flash_err & "000000" & ram_data_o;\r
     out_delay <= "00";\r
   else\r
     out_delay <= "00";\r
   end if;\r
   \r
-  if (SPI_READ_IN = '1') then\r
+  if (SPI_READ_IN = '1') then    \r
     if (SPI_ADDR_IN(7 downto 4) = x"4") then\r
       out_delay <= "01";\r
       reg_LOC_READ_OUT  <= '0';\r
@@ -246,11 +251,11 @@ PROC_SELECTOR : process begin
     elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
-      reg_SPI_DATA_OUT  <= x"01" & "00000" & master_running & master_start_reg & enable_cfg_flash;\r
+      reg_SPI_DATA_OUT(15 downto 0) <= x"01" & "00000" & master_running & master_start_reg & enable_cfg_flash;\r
     elsif (SPI_ADDR_IN(7 downto 0) = x"5d") then\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
-      reg_SPI_DATA_OUT  <= auto_dbg & "00" & master_flash_page;\r
+      reg_SPI_DATA_OUT(15 downto 0) <= auto_dbg & "00" & master_flash_page;\r
     elsif (SPI_ADDR_IN(7 downto 0) = x"5e") then\r
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
@@ -259,7 +264,7 @@ PROC_SELECTOR : process begin
       reg_LOC_READ_OUT  <= '0';\r
       reg_SPI_READY_OUT <= '1';\r
       -- reg_SPI_DATA_OUT  <= testreg;\r
-      reg_SPI_DATA_OUT  <= x"000" & master_word_counter;\r
+      reg_SPI_DATA_OUT(15 downto 0)  <= x"000" & master_word_counter;\r
     end if;\r
   end if;\r
   \r
@@ -278,12 +283,16 @@ begin
     master_WRITE_OUT <= '0';\r
     clean_master_start_reg <= '0';\r
 \r
+    if (DATA_BUS_WIDTH-1 > 15) then\r
+      master_DATA_OUT(DATA_BUS_WIDTH-1 downto 16) <= (others => '0');\r
+    end if;\r
+            \r
     case state is\r
       when IDLE =>\r
         if (master_start_reg = '1' or auto_reset = '1') then\r
           state <= Start;\r
           clean_master_start_reg <= '1';\r
-          master_DATA_OUT <= x"0000";\r
+          master_DATA_OUT <= (others => '0');\r
           master_ADDR_OUT <= x"00";\r
           if (auto_reset = '1') then\r
             auto_cnt <= std_logic_vector(unsigned(auto_cnt) + 1);\r
@@ -331,7 +340,7 @@ begin
           state <= WaitRAM2;\r
           master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
         else\r
-          master_DATA_OUT <= x"ff" & ram_data_o;\r
+          master_DATA_OUT(15 downto 0) <= x"ff" & ram_data_o;\r
           state <= IDLE;\r
         end if;\r
       when WaitRAM2 =>\r
@@ -339,16 +348,16 @@ begin
         state <= WaitRAM3;\r
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
       when WaitRAM3 =>\r
-        master_DATA_OUT <= ram_data_o & x"00";\r
+        master_DATA_OUT(15 downto 0) <= ram_data_o & x"00";\r
         state <= WaitRAM4;\r
       when WaitRAM4 =>\r
-        master_DATA_OUT <= master_DATA_OUT(15 downto 8) & ram_data_o;\r
+        master_DATA_OUT(15 downto 0) <= master_DATA_OUT(15 downto 8) & ram_data_o;\r
         state <= WriteSPI;\r
         master_WRITE_OUT <= '1';\r
       when WriteSPI =>\r
         -- prepare for next cycle\r
         if (master_word_counter = x"F") then\r
-          master_DATA_OUT <= x"eeee";\r
+          --master_DATA_OUT(15 downto 0) <= x"eeee";\r
           state <= ReadPage;\r
           master_word_counter <= "0000";\r
           master_flash_page <= std_logic_vector(unsigned(master_flash_page) + 1);\r