API_RUN_IN : in std_logic;
API_SEQNR_IN : in std_logic_vector (7 downto 0);
API_LENGTH_OUT : out std_logic_vector (15 downto 0);
-
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
--Information received with request
IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
CLK_EN <= '1';
- THE_HUB_LOGIC : trb_net16_hub_ipu_logic
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- --Internal interfaces to IOBufs
- INIT_DATAREADY_IN => INIT_DATAREADY_IN,
- INIT_DATA_IN => INIT_DATA_IN,
- INIT_PACKET_NUM_IN => INIT_PACKET_NUM_IN,
- INIT_READ_OUT => INIT_READ_OUT,
-
- INIT_DATAREADY_OUT => INIT_DATAREADY_OUT,
- INIT_DATA_OUT => INIT_DATA_OUT,
- INIT_PACKET_NUM_OUT => INIT_PACKET_NUM_OUT,
- INIT_READ_IN => INIT_READ_IN,
-
- REPLY_DATAREADY_IN => REPLY_DATAREADY_IN,
- REPLY_DATA_IN => REPLY_DATA_IN,
- REPLY_PACKET_NUM_IN => REPLY_PACKET_NUM_IN,
- REPLY_READ_OUT => REPLY_READ_OUT,
-
- REPLY_DATAREADY_OUT => REPLY_DATAREADY_OUT,
- REPLY_DATA_OUT => REPLY_DATA_OUT,
- REPLY_PACKET_NUM_OUT => REPLY_PACKET_NUM_OUT,
- REPLY_READ_IN => REPLY_READ_IN,
-
- MY_ADDRESS_IN => x"F00E",
- --Status ports
- CTRL => (others => '0'),
- CTRL_activepoints => (others => '1')
- );
+-- THE_HUB_LOGIC : trb_net16_hub_ipu_logic
+-- port map(
+-- CLK => CLK,
+-- RESET => RESET,
+-- CLK_EN => CLK_EN,
+--
+-- --Internal interfaces to IOBufs
+-- INIT_DATAREADY_IN => INIT_DATAREADY_IN,
+-- INIT_DATA_IN => INIT_DATA_IN,
+-- INIT_PACKET_NUM_IN => INIT_PACKET_NUM_IN,
+-- INIT_READ_OUT => INIT_READ_OUT,
+--
+-- INIT_DATAREADY_OUT => INIT_DATAREADY_OUT,
+-- INIT_DATA_OUT => INIT_DATA_OUT,
+-- INIT_PACKET_NUM_OUT => INIT_PACKET_NUM_OUT,
+-- INIT_READ_IN => INIT_READ_IN,
+--
+-- REPLY_DATAREADY_IN => REPLY_DATAREADY_IN,
+-- REPLY_DATA_IN => REPLY_DATA_IN,
+-- REPLY_PACKET_NUM_IN => REPLY_PACKET_NUM_IN,
+-- REPLY_READ_OUT => REPLY_READ_OUT,
+--
+-- REPLY_DATAREADY_OUT => REPLY_DATAREADY_OUT,
+-- REPLY_DATA_OUT => REPLY_DATA_OUT,
+-- REPLY_PACKET_NUM_OUT => REPLY_PACKET_NUM_OUT,
+-- REPLY_READ_IN => REPLY_READ_IN,
+--
+-- MY_ADDRESS_IN => x"F00E",
+-- --Status ports
+-- CTRL => (others => '0'),
+-- CTRL_activepoints => (others => '1')
+-- );
THE_ACTIVE_API : trb_net16_api_base
generic map(
APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN(15 downto 0),
APL_SEQNR_OUT => APL_SEQNR_OUT(7 downto 0),
APL_LENGTH_IN => APL_LENGTH_IN(15 downto 0),
- INT_MASTER_DATAREADY_OUT => INIT_DATAREADY_IN(0),
- INT_MASTER_DATA_OUT => INIT_DATA_IN(c_DATA_WIDTH-1 downto 0),
- INT_MASTER_PACKET_NUM_OUT => INIT_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0),
- INT_MASTER_READ_IN => INIT_READ_OUT(0),
- INT_MASTER_DATAREADY_IN => INIT_DATAREADY_OUT(0),
- INT_MASTER_DATA_IN => INIT_DATA_OUT(15 downto 0),
- INT_MASTER_PACKET_NUM_IN => INIT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0),
- INT_MASTER_READ_OUT => INIT_READ_IN(0),
- INT_SLAVE_DATAREADY_OUT => REPLY_DATAREADY_IN(0),
- INT_SLAVE_DATA_OUT => REPLY_DATA_IN(c_DATA_WIDTH-1 downto 0),
- INT_SLAVE_PACKET_NUM_OUT => REPLY_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0),
- INT_SLAVE_READ_IN => REPLY_READ_OUT(0),
- INT_SLAVE_DATAREADY_IN => REPLY_DATAREADY_OUT(0),
- INT_SLAVE_DATA_IN => REPLY_DATA_OUT(15 downto 0),
- INT_SLAVE_PACKET_NUM_IN => REPLY_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0),
- INT_SLAVE_READ_OUT => REPLY_READ_IN(0)
+-- INT_MASTER_DATAREADY_OUT => INIT_DATAREADY_IN(0),
+-- INT_MASTER_DATA_OUT => INIT_DATA_IN(c_DATA_WIDTH-1 downto 0),
+-- INT_MASTER_PACKET_NUM_OUT => INIT_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0),
+-- INT_MASTER_READ_IN => INIT_READ_OUT(0),
+-- INT_MASTER_DATAREADY_IN => INIT_DATAREADY_OUT(0),
+-- INT_MASTER_DATA_IN => INIT_DATA_OUT(15 downto 0),
+-- INT_MASTER_PACKET_NUM_IN => INIT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0),
+-- INT_MASTER_READ_OUT => INIT_READ_IN(0),
+-- INT_SLAVE_DATAREADY_OUT => REPLY_DATAREADY_IN(0),
+-- INT_SLAVE_DATA_OUT => REPLY_DATA_IN(c_DATA_WIDTH-1 downto 0),
+-- INT_SLAVE_PACKET_NUM_OUT => REPLY_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0),
+-- INT_SLAVE_READ_IN => REPLY_READ_OUT(0),
+-- INT_SLAVE_DATAREADY_IN => REPLY_DATAREADY_OUT(0),
+-- INT_SLAVE_DATA_IN => REPLY_DATA_OUT(15 downto 0),
+-- INT_SLAVE_PACKET_NUM_IN => REPLY_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0),
+-- INT_SLAVE_READ_OUT => REPLY_READ_IN(0)
+ INT_MASTER_DATAREADY_OUT => INIT_DATAREADY_OUT(1),
+ INT_MASTER_DATA_OUT => INIT_DATA_OUT(31 downto 16),
+ INT_MASTER_PACKET_NUM_OUT => INIT_PACKET_NUM_OUT(5 downto 3),
+ INT_MASTER_READ_IN => INIT_READ_IN(1),
+ INT_MASTER_DATAREADY_IN => INIT_DATAREADY_IN(1),
+ INT_MASTER_DATA_IN => INIT_DATA_IN(31 downto 16),
+ INT_MASTER_PACKET_NUM_IN => INIT_PACKET_NUM_IN(5 downto 3),
+ INT_MASTER_READ_OUT => INIT_READ_OUT(1),
+ INT_SLAVE_DATAREADY_OUT => REPLY_DATAREADY_OUT(1),
+ INT_SLAVE_DATA_OUT => REPLY_DATA_OUT(31 downto 16),
+ INT_SLAVE_PACKET_NUM_OUT => REPLY_PACKET_NUM_OUT(5 downto 3),
+ INT_SLAVE_READ_IN => REPLY_READ_IN(1),
+ INT_SLAVE_DATAREADY_IN => REPLY_DATAREADY_IN(1),
+ INT_SLAVE_DATA_IN => REPLY_DATA_IN(31 downto 16),
+ INT_SLAVE_PACKET_NUM_IN => REPLY_PACKET_NUM_IN(5 downto 3),
+ INT_SLAVE_READ_OUT => REPLY_READ_OUT(1)
);
REPLY_DATAREADY_IN(0) <= '0';
- gen_passive_apis : for i in 1 to 3 generate
+ gen_passive_apis : for i in 1 to 1 generate
A_PASSIVE_API : trb_net16_api_base
generic map(
API_TYPE => c_API_PASSIVE
APL_SEND_IN(0) <= not APL_RUN_OUT(0);
- gen_ipudatas : for i in 1 to 3 generate
+ gen_ipudatas : for i in 1 to 1 generate
A_IPUDATA : trb_net16_ipudata
port map(
CLK => CLK,
API_RUN_IN => APL_RUN_OUT(i),
API_SEQNR_IN => APL_SEQNR_OUT((i+1)*8-1 downto i*8),
API_LENGTH_OUT => APL_LENGTH_IN((i+1)*16-1 downto i*16),
+ MY_ADDRESS_IN => x"F00E",
--Information received with request
IPU_NUMBER_OUT => IPU_NUMBER_OUT((i+1)*16-1 downto i*16),
IPU_INFORMATION_OUT => IPU_INFORMATION_OUT((i+1)*8-1 downto i*8),
counter(i) <= 1;
end if;
IPU_DATAREADY_IN(i) <= '1';
- IPU_LENGTH_IN((i*16+15) downto i*16) <= std_logic_vector(to_unsigned(i+2,16));
+ IPU_LENGTH_IN((i*16+15) downto i*16) <= std_logic_vector(to_unsigned(i,16));
IPU_DATA_IN((i*32+31) downto i*32) <= "0001100101010101" & x"EFE0";
end if;
when 2 =>
--Media interface for Lattice ECP2M using PCS at 2GHz
---Still missing: link reset features, fifo full error handling, signals on stat_op
+--Still missing: fifo full error handling
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use work.trb_net_std.all;
entity trb_net16_med_ecp_sfp is
+ generic(
+ SERDES_NUM : integer range 0 to 3 := 0
+ );
port(
CLK : in std_logic;
RESET : in std_logic; -- synchronous reset
MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
MED_DATAREADY_OUT : out std_logic;
MED_READ_IN : in std_logic;
- REFCLK2CORE_OUT : out std_logic;
--SFP Connection
SD_RXD_P_IN : in std_logic;
SD_RXD_N_IN : in std_logic;
architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
- component serdes
+ component serdes_0
+ port(
+ core_txrefclk : in std_logic;
+ core_rxrefclk : in std_logic;
+-- refclkp : IN std_logic;
+-- refclkn : IN std_logic;
+ hdinp0 : in std_logic;
+ hdinn0 : in std_logic;
+ ff_rxiclk_ch0 : in std_logic;
+ ff_txiclk_ch0 : in std_logic;
+ ff_ebrd_clk_0 : in std_logic;
+ ff_txdata_ch0 : in std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch0 : in std_logic_vector(1 downto 0);
+ ff_force_disp_ch0 : in std_logic_vector(1 downto 0);
+ ff_disp_sel_ch0 : in std_logic_vector(1 downto 0);
+ ff_correct_disp_ch0 : in std_logic_vector(1 downto 0);
+ ffc_rrst_ch0 : in std_logic;
+ ffc_lane_tx_rst_ch0 : in std_logic;
+ ffc_lane_rx_rst_ch0 : in std_logic;
+ ffc_txpwdnb_ch0 : in std_logic;
+ ffc_rxpwdnb_ch0 : in std_logic;
+ ffc_macro_rst : in std_logic;
+ ffc_quad_rst : in std_logic;
+ ffc_trst : in std_logic;
+ hdoutp0 : out std_logic;
+ hdoutn0 : out std_logic;
+ ff_rxdata_ch0 : out std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch0 : out std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch0 : out std_logic;
+ ff_rxhalfclk_ch0 : out std_logic;
+ ff_disp_err_ch0 : out std_logic_vector(1 downto 0);
+ ff_cv_ch0 : out std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch0 : out std_logic;
+ ffs_ls_sync_status_ch0 : out std_logic;
+ ffs_cc_underrun_ch0 : out std_logic;
+ ffs_cc_overrun_ch0 : out std_logic;
+ ffs_txfbfifo_error_ch0 : out std_logic;
+ ffs_rxfbfifo_error_ch0 : out std_logic;
+ ffs_rlol_ch0 : out std_logic;
+ oob_out_ch0 : out std_logic;
+ ff_txfullclk : out std_logic;
+ ff_txhalfclk : out std_logic;
+ ffs_plol : out std_logic
+ );
+ end component;
+
+ component serdes_1
+ port(
+ core_txrefclk : in std_logic;
+ core_rxrefclk : in std_logic;
+ hdinp1 : in std_logic;
+ hdinn1 : in std_logic;
+ ff_rxiclk_ch1 : in std_logic;
+ ff_txiclk_ch1 : in std_logic;
+ ff_ebrd_clk_1 : in std_logic;
+ ff_txdata_ch1 : in std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch1 : in std_logic_vector(1 downto 0);
+ ff_force_disp_ch1 : in std_logic_vector(1 downto 0);
+ ff_disp_sel_ch1 : in std_logic_vector(1 downto 0);
+ ff_correct_disp_ch1 : in std_logic_vector(1 downto 0);
+ ffc_rrst_ch1 : in std_logic;
+ ffc_lane_tx_rst_ch1 : in std_logic;
+ ffc_lane_rx_rst_ch1 : in std_logic;
+ ffc_txpwdnb_ch1 : in std_logic;
+ ffc_rxpwdnb_ch1 : in std_logic;
+ ffc_macro_rst : in std_logic;
+ ffc_quad_rst : in std_logic;
+ ffc_trst : in std_logic;
+ hdoutp1 : out std_logic;
+ hdoutn1 : out std_logic;
+ ff_rxdata_ch1 : out std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch1 : out std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch1 : out std_logic;
+ ff_rxhalfclk_ch1 : out std_logic;
+ ff_disp_err_ch1 : out std_logic_vector(1 downto 0);
+ ff_cv_ch1 : out std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch1 : out std_logic;
+ ffs_ls_sync_status_ch1 : out std_logic;
+ ffs_cc_underrun_ch1 : out std_logic;
+ ffs_cc_overrun_ch1 : out std_logic;
+ ffs_txfbfifo_error_ch1 : out std_logic;
+ ffs_rxfbfifo_error_ch1 : out std_logic;
+ ffs_rlol_ch1 : out std_logic;
+ oob_out_ch1 : out std_logic;
+ ff_txfullclk : out std_logic;
+ ff_txhalfclk : out std_logic;
+ ffs_plol : out std_logic
+ );
+ end component;
+
+
+ component serdes_2
+ port(
+ core_txrefclk : in std_logic;
+ core_rxrefclk : in std_logic;
+ hdinp2 : in std_logic;
+ hdinn2 : in std_logic;
+ ff_rxiclk_ch2 : in std_logic;
+ ff_txiclk_ch2 : in std_logic;
+ ff_ebrd_clk_2 : in std_logic;
+ ff_txdata_ch2 : in std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch2 : in std_logic_vector(1 downto 0);
+ ff_force_disp_ch2 : in std_logic_vector(1 downto 0);
+ ff_disp_sel_ch2 : in std_logic_vector(1 downto 0);
+ ff_correct_disp_ch2 : in std_logic_vector(1 downto 0);
+ ffc_rrst_ch2 : in std_logic;
+ ffc_lane_tx_rst_ch2 : in std_logic;
+ ffc_lane_rx_rst_ch2 : in std_logic;
+ ffc_txpwdnb_ch2 : in std_logic;
+ ffc_rxpwdnb_ch2 : in std_logic;
+ ffc_macro_rst : in std_logic;
+ ffc_quad_rst : in std_logic;
+ ffc_trst : in std_logic;
+ hdoutp2 : out std_logic;
+ hdoutn2 : out std_logic;
+ ff_rxdata_ch2 : out std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch2 : out std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch2 : out std_logic;
+ ff_rxhalfclk_ch2 : out std_logic;
+ ff_disp_err_ch2 : out std_logic_vector(1 downto 0);
+ ff_cv_ch2 : out std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch2 : out std_logic;
+ ffs_ls_sync_status_ch2 : out std_logic;
+ ffs_cc_underrun_ch2 : out std_logic;
+ ffs_cc_overrun_ch2 : out std_logic;
+ ffs_txfbfifo_error_ch2 : out std_logic;
+ ffs_rxfbfifo_error_ch2 : out std_logic;
+ ffs_rlol_ch2 : out std_logic;
+ oob_out_ch2 : out std_logic;
+ ff_txfullclk : out std_logic;
+ ff_txhalfclk : out std_logic;
+ ffs_plol : out std_logic
+ );
+ end component;
+
+ component serdes_3
port(
- core_txrefclk : IN std_logic; --CLK
- core_rxrefclk : IN std_logic; --CLK
- hdinp2 : IN std_logic; --RX Data input
- hdinn2 : IN std_logic; --RX Data input
- ff_rxiclk_ch2 : IN std_logic; --CLK ff_txhalfclk
- ff_txiclk_ch2 : IN std_logic; --CLK ff_txhalfclk
- ff_ebrd_clk_2 : IN std_logic; --CLK ff_txfullclk
- ff_txdata_ch2 : IN std_logic_vector(15 downto 0); --internal tx data
- ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0); --control character flag 00
- ff_force_disp_ch2 : IN std_logic_vector(1 downto 0); --activate disparity value 00
- ff_disp_sel_ch2 : IN std_logic_vector(1 downto 0); --disparity value in 00
- ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0); --disparity check 00
- ffc_rrst_ch2 : IN std_logic; --RESET
- ffc_signal_detect_ch2 : IN std_logic; --enable signal detect
- ffc_enable_cgalign_ch2 : IN std_logic; --enable comma aligner 0
- ffc_lane_tx_rst_ch2 : IN std_logic; --RESET
- ffc_lane_rx_rst_ch2 : IN std_logic; -- reset PCS (word alignment)
- ffc_txpwdnb_ch2 : IN std_logic; --power down active low
- ffc_rxpwdnb_ch2 : IN std_logic; --power down active low
- ffc_macro_rst : IN std_logic; --RESET
- ffc_quad_rst : IN std_logic; --RESET
- ffc_trst : IN std_logic; --RESET
- hdoutp2 : OUT std_logic; --TX Data output
- hdoutn2 : OUT std_logic; --TX Data output
- ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0); --internal rx data
- ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0); --control character flag
- ff_rxfullclk_ch2 : OUT std_logic; --RX recovered CLK
- ff_rxhalfclk_ch2 : OUT std_logic; --+ --RX half recovered CLK
- ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0); --disparity error flag
- ff_cv_ch2 : OUT std_logic_vector(1 downto 0); --code violation flag
- ffs_rlos_lo_ch2 : OUT std_logic; --NOT signal loss
- ffs_ls_sync_status_ch2 : OUT std_logic; --+ --link state machine status
- ffs_cc_underrun_ch2 : OUT std_logic; --Clock compensator FIFO error
- ffs_cc_overrun_ch2 : OUT std_logic; --Clock compensator FIFO error
- ffs_txfbfifo_error_ch2 : OUT std_logic; --TX FIFO error
- ffs_rxfbfifo_error_ch2 : OUT std_logic; --RX FIFO error
- ffs_rlol_ch2 : OUT std_logic; --Clock Recovery error
- oob_out_ch2 : OUT std_logic; --internal output same as real serdes output
- ff_txfullclk : OUT std_logic; --TX CLK
- ff_txhalfclk : OUT std_logic; --TX CLK/2 <- interface CLK from MED to Serdes
- refck2core : OUT std_logic; --+ --Reference CLK
- ffs_plol : OUT std_logic --TX PLL error (not locked)
+ core_txrefclk : in std_logic;
+ core_rxrefclk : in std_logic;
+ hdinp3 : in std_logic;
+ hdinn3 : in std_logic;
+ ff_rxiclk_ch3 : in std_logic;
+ ff_txiclk_ch3 : in std_logic;
+ ff_ebrd_clk_3 : in std_logic;
+ ff_txdata_ch3 : in std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch3 : in std_logic_vector(1 downto 0);
+ ff_force_disp_ch3 : in std_logic_vector(1 downto 0);
+ ff_disp_sel_ch3 : in std_logic_vector(1 downto 0);
+ ff_correct_disp_ch3 : in std_logic_vector(1 downto 0);
+ ffc_rrst_ch3 : in std_logic;
+ ffc_lane_tx_rst_ch3 : in std_logic;
+ ffc_lane_rx_rst_ch3 : in std_logic;
+ ffc_txpwdnb_ch3 : in std_logic;
+ ffc_rxpwdnb_ch3 : in std_logic;
+ ffc_macro_rst : in std_logic;
+ ffc_quad_rst : in std_logic;
+ ffc_trst : in std_logic;
+ hdoutp3 : out std_logic;
+ hdoutn3 : out std_logic;
+ ff_rxdata_ch3 : out std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch3 : out std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch3 : out std_logic;
+ ff_rxhalfclk_ch3 : out std_logic;
+ ff_disp_err_ch3 : out std_logic_vector(1 downto 0);
+ ff_cv_ch3 : out std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch3 : out std_logic;
+ ffs_ls_sync_status_ch3 : out std_logic;
+ ffs_cc_underrun_ch3 : out std_logic;
+ ffs_cc_overrun_ch3 : out std_logic;
+ ffs_txfbfifo_error_ch3 : out std_logic;
+ ffs_rxfbfifo_error_ch3 : out std_logic;
+ ffs_rlol_ch3 : out std_logic;
+ oob_out_ch3 : out std_logic;
+ ff_txfullclk : out std_logic;
+ ff_txhalfclk : out std_logic;
+ ffs_plol : out std_logic
);
end component;
component trb_net_fifo_16bit_bram_dualport is
generic(
USE_STATUS_FLAGS : integer := c_YES
- );
- port( read_clock_in : in std_logic;
- write_clock_in : in std_logic;
- read_enable_in : in std_logic;
- write_enable_in : in std_logic;
- fifo_gsr_in : in std_logic;
- write_data_in : in std_logic_vector(17 downto 0);
- read_data_out : out std_logic_vector(17 downto 0);
- full_out : out std_logic;
- empty_out : out std_logic;
- fifostatus_out : out std_logic_vector(3 downto 0);
- valid_read_out : out std_logic;
- almost_empty_out : out std_logic;
- almost_full_out : out std_logic
+ );
+ port(
+ read_clock_in : in std_logic;
+ write_clock_in : in std_logic;
+ read_enable_in : in std_logic;
+ write_enable_in : in std_logic;
+ fifo_gsr_in : in std_logic;
+ write_data_in : in std_logic_vector(17 downto 0);
+ read_data_out : out std_logic_vector(17 downto 0);
+ full_out : out std_logic;
+ empty_out : out std_logic;
+ fifostatus_out : out std_logic_vector(3 downto 0);
+ valid_read_out : out std_logic;
+ almost_empty_out : out std_logic;
+ almost_full_out : out std_logic
);
end component;
DEPTH : integer := 3
);
port(
- RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
- CLK0 : in std_logic; --clock for first FF
- CLK1 : in std_logic; --Clock for other FF
- D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input
- D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output
+ RESET : in std_logic;
+ CLK0 : in std_logic;
+ CLK1 : in std_logic;
+ D_IN : in std_logic_vector(WIDTH-1 downto 0);
+ D_OUT : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
- signal refck2core : std_logic;
--reset signals
signal ffc_quad_rst : std_logic;
- signal ffc_lane_tx_rst_ch2 : std_logic;
- signal ffc_lane_rx_rst_ch2 : std_logic;
+ signal ffc_lane_tx_rst : std_logic;
+ signal ffc_lane_rx_rst : std_logic;
--serdes connections
signal tx_data : std_logic_vector(15 downto 0);
signal tx_k : std_logic_vector(1 downto 0);
signal rx_data : std_logic_vector(15 downto 0);
signal rx_k : std_logic_vector(1 downto 0);
signal link_ok : std_logic_vector(0 downto 0);
- signal link_error : std_logic_vector(9 downto 0);
+ signal link_error : std_logic_vector(8 downto 0);
signal ff_rxhalfclk : std_logic;
signal ff_txhalfclk : std_logic;
--rx fifo signals
signal buf_STAT_OP : std_logic_vector(15 downto 15);
signal buf_RESET_TRBNET_OUT : std_logic;
signal resync_counter : std_logic_vector(2 downto 0);
- signal internal_reset : std_logic;
signal send_resync_counter : std_logic_vector(11 downto 0);
signal next_send_resync : std_logic;
signal send_resync : std_logic;
end case;
end process;
-THE_DECODE_PROC: process( CURRENT_STATE, timing_ctr )
+THE_DECODE_PROC: process( CURRENT_STATE )
begin
case CURRENT_STATE is
when SLEEP => state_bits <= "0000";
- info_led <= '0';
- when QRST => state_bits <= "0001";
- info_led <= timing_ctr(21); -- too high
- when WPAR => state_bits <= "0010";
- info_led <= timing_ctr(21) and timing_ctr(24); -- nice frequency for human eye
- when WLOS => state_bits <= "0011";
- info_led <= timing_ctr(22);
+ when QRST => state_bits <= "0001";
+ when WPAR => state_bits <= "0010";
+ when WLOS => state_bits <= "0011";
when ALIGN => state_bits <= "0100";
- info_led <= timing_ctr(23);
- when WRXA => state_bits <= "0101";
- info_led <= timing_ctr(24);
- when WTXA => state_bits <= "0110";
- info_led <= timing_ctr(25);
- when LINK => state_bits <= "0111";
- info_led <= '1';
- when others => state_bits <= "1111";
- info_led <= '0';
+ when WRXA => state_bits <= "0101";
+ when WTXA => state_bits <= "0110";
+ when LINK => state_bits <= "0111";
+ when others => state_bits <= "1111";
end case;
end process THE_DECODE_PROC;
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-ffc_quad_rst <= quad_rst;
-ffc_lane_tx_rst_ch2 <= lane_rst;
-ffc_lane_rx_rst_ch2 <= lane_rst;
-
-
+ffc_quad_rst <= quad_rst;
+ffc_lane_tx_rst <= lane_rst;
+ffc_lane_rx_rst <= lane_rst;
--- SerDes clock output to FPGA fabric
-refclk2core_out <= refck2core;
-- Instantiation of serdes module
-THE_SERDES: serdes
- port map(
- core_txrefclk => clk,
- core_rxrefclk => clk,
- hdinp2 => sd_rxd_p_in,
- hdinn2 => sd_rxd_n_in,
- ff_rxiclk_ch2 => ff_rxhalfclk,
- ff_txiclk_ch2 => ff_txhalfclk,
- ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness
- ff_txdata_ch2 => tx_data,
- ff_tx_k_cntrl_ch2 => tx_k,
- ff_force_disp_ch2 => "00",
- ff_disp_sel_ch2 => "00",
- ff_correct_disp_ch2 => "00",
- ffc_rrst_ch2 => '0',
- ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2,
- ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2,
- ffc_txpwdnb_ch2 => '1',
- ffc_rxpwdnb_ch2 => '1',
- ffc_macro_rst => '0',
- ffc_quad_rst => ffc_quad_rst,
- ffc_trst => '0',
- hdoutp2 => sd_txd_p_out,
- hdoutn2 => sd_txd_n_out,
- ff_rxdata_ch2 => rx_data, --comb_rx_data,
- ff_rx_k_cntrl_ch2 => rx_k, --comb_rx_k,
- ff_rxfullclk_ch2 => open,
- ff_rxhalfclk_ch2 => ff_rxhalfclk,
- ff_disp_err_ch2 => open,
- ff_cv_ch2 => link_error(7 downto 6),
- ffs_rlos_lo_ch2 => link_error(8),
- ffs_ls_sync_status_ch2 => link_ok(0),
- ffs_cc_underrun_ch2 => link_error(0),
- ffs_cc_overrun_ch2 => link_error(1),
- ffs_txfbfifo_error_ch2 => link_error(2),
- ffs_rxfbfifo_error_ch2 => link_error(3),
- ffs_rlol_ch2 => link_error(4),
- oob_out_ch2 => open,
- ff_txfullclk => open,
- ff_txhalfclk => ff_txhalfclk,
- refck2core => refck2core,
- ffs_plol => link_error(5)
- );
-
-link_error(9) <= '0'; -- unused
+ gen_serdes_0 : if SERDES_NUM = 0 generate
+ THE_SERDES: serdes_0
+ port map(
+ core_txrefclk => clk,
+ core_rxrefclk => clk,
+-- refclkp => SD_REFCLK_P_IN,
+-- refclkn => SD_REFCLK_N_IN,
+ hdinp0 => sd_rxd_p_in,
+ hdinn0 => sd_rxd_n_in,
+ ff_rxiclk_ch0 => ff_rxhalfclk,
+ ff_txiclk_ch0 => ff_txhalfclk,
+ ff_ebrd_clk_0 => ff_rxhalfclk, -- not used, just for completeness
+ ff_txdata_ch0 => tx_data,
+ ff_tx_k_cntrl_ch0 => tx_k,
+ ff_force_disp_ch0 => "00",
+ ff_disp_sel_ch0 => "00",
+ ff_correct_disp_ch0 => "00",
+ ffc_rrst_ch0 => '0',
+ ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch0 => ffc_lane_rx_rst,
+ ffc_txpwdnb_ch0 => '1',
+ ffc_rxpwdnb_ch0 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp0 => sd_txd_p_out,
+ hdoutn0 => sd_txd_n_out,
+ ff_rxdata_ch0 => rx_data, --comb_rx_data,
+ ff_rx_k_cntrl_ch0 => rx_k, --comb_rx_k,
+ ff_rxfullclk_ch0 => open,
+ ff_rxhalfclk_ch0 => ff_rxhalfclk,
+ ff_disp_err_ch0 => open,
+ ff_cv_ch0 => link_error(7 downto 6),
+ ffs_rlos_lo_ch0 => link_error(8),
+ ffs_ls_sync_status_ch0 => link_ok(0),
+ ffs_cc_underrun_ch0 => link_error(0),
+ ffs_cc_overrun_ch0 => link_error(1),
+ ffs_txfbfifo_error_ch0 => link_error(2),
+ ffs_rxfbfifo_error_ch0 => link_error(3),
+ ffs_rlol_ch0 => link_error(4),
+ oob_out_ch0 => open,
+ ff_txfullclk => open,
+ ff_txhalfclk => ff_txhalfclk,
+ ffs_plol => link_error(5)
+ );
+ end generate;
+ gen_serdes_1 : if SERDES_NUM = 1 generate
+ THE_SERDES: serdes_1
+ port map(
+ core_txrefclk => clk,
+ core_rxrefclk => clk,
+ hdinp1 => sd_rxd_p_in,
+ hdinn1 => sd_rxd_n_in,
+ ff_rxiclk_ch1 => ff_rxhalfclk,
+ ff_txiclk_ch1 => ff_txhalfclk,
+ ff_ebrd_clk_1 => ff_rxhalfclk, -- not used, just for completeness
+ ff_txdata_ch1 => tx_data,
+ ff_tx_k_cntrl_ch1 => tx_k,
+ ff_force_disp_ch1 => "00",
+ ff_disp_sel_ch1 => "00",
+ ff_correct_disp_ch1 => "00",
+ ffc_rrst_ch1 => '0',
+ ffc_lane_tx_rst_ch1 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch1 => ffc_lane_rx_rst,
+ ffc_txpwdnb_ch1 => '1',
+ ffc_rxpwdnb_ch1 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp1 => sd_txd_p_out,
+ hdoutn1 => sd_txd_n_out,
+ ff_rxdata_ch1 => rx_data, --comb_rx_data,
+ ff_rx_k_cntrl_ch1 => rx_k, --comb_rx_k,
+ ff_rxfullclk_ch1 => open,
+ ff_rxhalfclk_ch1 => ff_rxhalfclk,
+ ff_disp_err_ch1 => open,
+ ff_cv_ch1 => link_error(7 downto 6),
+ ffs_rlos_lo_ch1 => link_error(8),
+ ffs_ls_sync_status_ch1 => link_ok(0),
+ ffs_cc_underrun_ch1 => link_error(0),
+ ffs_cc_overrun_ch1 => link_error(1),
+ ffs_txfbfifo_error_ch1 => link_error(2),
+ ffs_rxfbfifo_error_ch1 => link_error(3),
+ ffs_rlol_ch1 => link_error(4),
+ oob_out_ch1 => open,
+ ff_txfullclk => open,
+ ff_txhalfclk => ff_txhalfclk,
+ ffs_plol => link_error(5)
+ );
+ end generate;
+ gen_serdes_2 : if SERDES_NUM = 2 generate
+ THE_SERDES: serdes_2
+ port map(
+ core_txrefclk => clk,
+ core_rxrefclk => clk,
+ hdinp2 => sd_rxd_p_in,
+ hdinn2 => sd_rxd_n_in,
+ ff_rxiclk_ch2 => ff_rxhalfclk,
+ ff_txiclk_ch2 => ff_txhalfclk,
+ ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness
+ ff_txdata_ch2 => tx_data,
+ ff_tx_k_cntrl_ch2 => tx_k,
+ ff_force_disp_ch2 => "00",
+ ff_disp_sel_ch2 => "00",
+ ff_correct_disp_ch2 => "00",
+ ffc_rrst_ch2 => '0',
+ ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst,
+ ffc_txpwdnb_ch2 => '1',
+ ffc_rxpwdnb_ch2 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp2 => sd_txd_p_out,
+ hdoutn2 => sd_txd_n_out,
+ ff_rxdata_ch2 => rx_data, --comb_rx_data,
+ ff_rx_k_cntrl_ch2 => rx_k, --comb_rx_k,
+ ff_rxfullclk_ch2 => open,
+ ff_rxhalfclk_ch2 => ff_rxhalfclk,
+ ff_disp_err_ch2 => open,
+ ff_cv_ch2 => link_error(7 downto 6),
+ ffs_rlos_lo_ch2 => link_error(8),
+ ffs_ls_sync_status_ch2 => link_ok(0),
+ ffs_cc_underrun_ch2 => link_error(0),
+ ffs_cc_overrun_ch2 => link_error(1),
+ ffs_txfbfifo_error_ch2 => link_error(2),
+ ffs_rxfbfifo_error_ch2 => link_error(3),
+ ffs_rlol_ch2 => link_error(4),
+ oob_out_ch2 => open,
+ ff_txfullclk => open,
+ ff_txhalfclk => ff_txhalfclk,
+ ffs_plol => link_error(5)
+ );
+ end generate;
+ gen_serdes_3 : if SERDES_NUM = 3 generate
+ THE_SERDES: serdes_3
+ port map(
+ core_txrefclk => clk,
+ core_rxrefclk => clk,
+ hdinp3 => sd_rxd_p_in,
+ hdinn3 => sd_rxd_n_in,
+ ff_rxiclk_ch3 => ff_rxhalfclk,
+ ff_txiclk_ch3 => ff_txhalfclk,
+ ff_ebrd_clk_3 => ff_rxhalfclk, -- not used, just for completeness
+ ff_txdata_ch3 => tx_data,
+ ff_tx_k_cntrl_ch3 => tx_k,
+ ff_force_disp_ch3 => "00",
+ ff_disp_sel_ch3 => "00",
+ ff_correct_disp_ch3 => "00",
+ ffc_rrst_ch3 => '0',
+ ffc_lane_tx_rst_ch3 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch3 => ffc_lane_rx_rst,
+ ffc_txpwdnb_ch3 => '1',
+ ffc_rxpwdnb_ch3 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp3 => sd_txd_p_out,
+ hdoutn3 => sd_txd_n_out,
+ ff_rxdata_ch3 => rx_data, --comb_rx_data,
+ ff_rx_k_cntrl_ch3 => rx_k, --comb_rx_k,
+ ff_rxfullclk_ch3 => open,
+ ff_rxhalfclk_ch3 => ff_rxhalfclk,
+ ff_disp_err_ch3 => open,
+ ff_cv_ch3 => link_error(7 downto 6),
+ ffs_rlos_lo_ch3 => link_error(8),
+ ffs_ls_sync_status_ch3 => link_ok(0),
+ ffs_cc_underrun_ch3 => link_error(0),
+ ffs_cc_overrun_ch3 => link_error(1),
+ ffs_txfbfifo_error_ch3 => link_error(2),
+ ffs_rxfbfifo_error_ch3 => link_error(3),
+ ffs_rlol_ch3 => link_error(4),
+ oob_out_ch3 => open,
+ ff_txfullclk => open,
+ ff_txhalfclk => ff_txhalfclk,
+ ffs_plol => link_error(5)
+ );
+ end generate;
+
-------------------------------------------------------------------------
-- RX Fifo & Data output
--TX Fifo & Data output to Serdes
---------------------
THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
-generic map(
- USE_STATUS_FLAGS => c_NO
- )
-port map( read_clock_in => ff_txhalfclk,
- write_clock_in => clock,
- read_enable_in => fifo_tx_rd_en,
- write_enable_in => fifo_tx_wr_en,
- fifo_gsr_in => fifo_tx_reset,
- write_data_in => fifo_tx_din,
- read_data_out => fifo_tx_dout,
- full_out => fifo_tx_full,
- empty_out => fifo_tx_empty
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+ port map(
+ read_clock_in => ff_txhalfclk,
+ write_clock_in => clock,
+ read_enable_in => fifo_tx_rd_en,
+ write_enable_in => fifo_tx_wr_en,
+ fifo_gsr_in => fifo_tx_reset,
+ write_data_in => fifo_tx_din,
+ read_data_out => fifo_tx_dout,
+ full_out => fifo_tx_full,
+ empty_out => fifo_tx_empty
);
fifo_tx_reset <= RESET;
end if;
end process THE_SERDES_INPUT_PROC;
---
--Generate LED signals
stat_debug(7) <= rx_k(1);
stat_debug(8) <= rx_k_q(0);
stat_debug(9) <= rx_k_q(1);
---stat_debug(9 downto 7) <= (others => '0');
-stat_debug(19 downto 10) <= link_error;
+stat_debug(18 downto 10) <= link_error;
+stat_debug(19) <= '0';
stat_debug(20) <= link_ok(0);
stat_debug(38 downto 21) <= fifo_rx_din;
stat_debug(39) <= swap_bytes;
stat_debug(40) <= fifo_rx_wr_en;
stat_debug(41) <= info_led;
stat_debug(42) <= resync;
-stat_debug(59 downto 43) <= (others => '0');
+stat_debug(43) <= ff_rxhalfclk;
+stat_debug(44) <= ff_txhalfclk;
+stat_debug(59 downto 45) <= (others => '0');
stat_debug(63 downto 60) <= link_error(3 downto 0);
end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff